xen: events: propagate irq allocation failure instead of panicking
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
6cb6537d
IC
59static LIST_HEAD(xen_irq_list_head);
60
e46cdb66 61/* IRQ <-> VIRQ mapping. */
204fba4a 62static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 63
f87e4cac 64/* IRQ <-> IPI mapping */
204fba4a 65static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 66
ced40d0f
JF
67/* Interrupt types. */
68enum xen_irq_type {
d77bbd4d 69 IRQT_UNBOUND = 0,
f87e4cac
JF
70 IRQT_PIRQ,
71 IRQT_VIRQ,
72 IRQT_IPI,
73 IRQT_EVTCHN
74};
e46cdb66 75
ced40d0f
JF
76/*
77 * Packed IRQ information:
78 * type - enum xen_irq_type
79 * event channel - irq->event channel mapping
80 * cpu - cpu this event channel is bound to
81 * index - type-specific information:
42a1de56
SS
82 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
83 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
84 * VIRQ - virq number
85 * IPI - IPI vector
86 * EVTCHN -
87 */
88struct irq_info
89{
6cb6537d 90 struct list_head list;
ced40d0f 91 enum xen_irq_type type; /* type */
6cb6537d 92 unsigned irq;
ced40d0f
JF
93 unsigned short evtchn; /* event channel */
94 unsigned short cpu; /* cpu bound */
95
96 union {
97 unsigned short virq;
98 enum ipi_vector ipi;
99 struct {
7a043f11 100 unsigned short pirq;
ced40d0f 101 unsigned short gsi;
d46a78b0
JF
102 unsigned char vector;
103 unsigned char flags;
ced40d0f
JF
104 } pirq;
105 } u;
106};
d46a78b0 107#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 108#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 109
b21ddbf5 110static int *evtchn_to_irq;
3b32f574 111
cb60d114
IC
112static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
113 cpu_evtchn_mask);
e46cdb66 114
e46cdb66
JF
115/* Xen will never allocate port zero for any purpose. */
116#define VALID_EVTCHN(chn) ((chn) != 0)
117
e46cdb66 118static struct irq_chip xen_dynamic_chip;
aaca4964 119static struct irq_chip xen_percpu_chip;
d46a78b0 120static struct irq_chip xen_pirq_chip;
e46cdb66 121
9158c358
IC
122/* Get info for IRQ */
123static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 124{
ca62ce8c 125 return get_irq_data(irq);
ced40d0f
JF
126}
127
9158c358
IC
128/* Constructors for packed IRQ information. */
129static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 130 unsigned irq,
9158c358
IC
131 enum xen_irq_type type,
132 unsigned short evtchn,
133 unsigned short cpu)
ced40d0f 134{
9158c358
IC
135
136 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
137
138 info->type = type;
6cb6537d 139 info->irq = irq;
9158c358
IC
140 info->evtchn = evtchn;
141 info->cpu = cpu;
3d4cfa37
IC
142
143 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
144}
145
9158c358
IC
146static void xen_irq_info_evtchn_init(unsigned irq,
147 unsigned short evtchn)
e46cdb66 148{
9158c358
IC
149 struct irq_info *info = info_for_irq(irq);
150
3d4cfa37 151 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
152}
153
3d4cfa37
IC
154static void xen_irq_info_ipi_init(unsigned cpu,
155 unsigned irq,
9158c358
IC
156 unsigned short evtchn,
157 enum ipi_vector ipi)
ced40d0f 158{
9158c358
IC
159 struct irq_info *info = info_for_irq(irq);
160
3d4cfa37 161 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
162
163 info->u.ipi = ipi;
3d4cfa37
IC
164
165 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
166}
167
3d4cfa37
IC
168static void xen_irq_info_virq_init(unsigned cpu,
169 unsigned irq,
9158c358
IC
170 unsigned short evtchn,
171 unsigned short virq)
ced40d0f 172{
9158c358
IC
173 struct irq_info *info = info_for_irq(irq);
174
3d4cfa37 175 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
176
177 info->u.virq = virq;
3d4cfa37
IC
178
179 per_cpu(virq_to_irq, cpu)[virq] = irq;
e46cdb66
JF
180}
181
9158c358
IC
182static void xen_irq_info_pirq_init(unsigned irq,
183 unsigned short evtchn,
184 unsigned short pirq,
185 unsigned short gsi,
186 unsigned short vector,
187 unsigned char flags)
e46cdb66 188{
9158c358
IC
189 struct irq_info *info = info_for_irq(irq);
190
3d4cfa37 191 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
192
193 info->u.pirq.pirq = pirq;
194 info->u.pirq.gsi = gsi;
195 info->u.pirq.vector = vector;
196 info->u.pirq.flags = flags;
e46cdb66
JF
197}
198
9158c358
IC
199/*
200 * Accessors for packed IRQ information.
201 */
ced40d0f 202static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 203{
110e7c7e
JJ
204 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
205 return 0;
206
ced40d0f 207 return info_for_irq(irq)->evtchn;
e46cdb66
JF
208}
209
d4c04536
IC
210unsigned irq_from_evtchn(unsigned int evtchn)
211{
212 return evtchn_to_irq[evtchn];
213}
214EXPORT_SYMBOL_GPL(irq_from_evtchn);
215
ced40d0f 216static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 217{
ced40d0f
JF
218 struct irq_info *info = info_for_irq(irq);
219
220 BUG_ON(info == NULL);
221 BUG_ON(info->type != IRQT_IPI);
222
223 return info->u.ipi;
224}
225
226static unsigned virq_from_irq(unsigned irq)
227{
228 struct irq_info *info = info_for_irq(irq);
229
230 BUG_ON(info == NULL);
231 BUG_ON(info->type != IRQT_VIRQ);
232
233 return info->u.virq;
234}
235
7a043f11
SS
236static unsigned pirq_from_irq(unsigned irq)
237{
238 struct irq_info *info = info_for_irq(irq);
239
240 BUG_ON(info == NULL);
241 BUG_ON(info->type != IRQT_PIRQ);
242
243 return info->u.pirq.pirq;
244}
245
ced40d0f
JF
246static enum xen_irq_type type_from_irq(unsigned irq)
247{
248 return info_for_irq(irq)->type;
249}
250
251static unsigned cpu_from_irq(unsigned irq)
252{
253 return info_for_irq(irq)->cpu;
254}
255
256static unsigned int cpu_from_evtchn(unsigned int evtchn)
257{
258 int irq = evtchn_to_irq[evtchn];
259 unsigned ret = 0;
260
261 if (irq != -1)
262 ret = cpu_from_irq(irq);
263
264 return ret;
e46cdb66
JF
265}
266
d46a78b0
JF
267static bool pirq_needs_eoi(unsigned irq)
268{
269 struct irq_info *info = info_for_irq(irq);
270
271 BUG_ON(info->type != IRQT_PIRQ);
272
273 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
274}
275
e46cdb66
JF
276static inline unsigned long active_evtchns(unsigned int cpu,
277 struct shared_info *sh,
278 unsigned int idx)
279{
280 return (sh->evtchn_pending[idx] &
cb60d114 281 per_cpu(cpu_evtchn_mask, cpu)[idx] &
e46cdb66
JF
282 ~sh->evtchn_mask[idx]);
283}
284
285static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
286{
287 int irq = evtchn_to_irq[chn];
288
289 BUG_ON(irq == -1);
290#ifdef CONFIG_SMP
c9e265e0 291 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
292#endif
293
cb60d114
IC
294 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
295 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 296
ca62ce8c 297 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
298}
299
300static void init_evtchn_cpu_bindings(void)
301{
1c6969ec 302 int i;
e46cdb66 303#ifdef CONFIG_SMP
6cb6537d 304 struct irq_info *info;
10e58084 305
e46cdb66 306 /* By default all event channels notify CPU#0. */
6cb6537d
IC
307 list_for_each_entry(info, &xen_irq_list_head, list) {
308 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 309 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 310 }
e46cdb66
JF
311#endif
312
1c6969ec 313 for_each_possible_cpu(i)
cb60d114
IC
314 memset(per_cpu(cpu_evtchn_mask, i),
315 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
316}
317
e46cdb66
JF
318static inline void clear_evtchn(int port)
319{
320 struct shared_info *s = HYPERVISOR_shared_info;
321 sync_clear_bit(port, &s->evtchn_pending[0]);
322}
323
324static inline void set_evtchn(int port)
325{
326 struct shared_info *s = HYPERVISOR_shared_info;
327 sync_set_bit(port, &s->evtchn_pending[0]);
328}
329
168d2f46
JF
330static inline int test_evtchn(int port)
331{
332 struct shared_info *s = HYPERVISOR_shared_info;
333 return sync_test_bit(port, &s->evtchn_pending[0]);
334}
335
e46cdb66
JF
336
337/**
338 * notify_remote_via_irq - send event to remote end of event channel via irq
339 * @irq: irq of event channel to send event to
340 *
341 * Unlike notify_remote_via_evtchn(), this is safe to use across
342 * save/restore. Notifications on a broken connection are silently
343 * dropped.
344 */
345void notify_remote_via_irq(int irq)
346{
347 int evtchn = evtchn_from_irq(irq);
348
349 if (VALID_EVTCHN(evtchn))
350 notify_remote_via_evtchn(evtchn);
351}
352EXPORT_SYMBOL_GPL(notify_remote_via_irq);
353
354static void mask_evtchn(int port)
355{
356 struct shared_info *s = HYPERVISOR_shared_info;
357 sync_set_bit(port, &s->evtchn_mask[0]);
358}
359
360static void unmask_evtchn(int port)
361{
362 struct shared_info *s = HYPERVISOR_shared_info;
363 unsigned int cpu = get_cpu();
364
365 BUG_ON(!irqs_disabled());
366
367 /* Slow path (hypercall) if this is a non-local port. */
368 if (unlikely(cpu != cpu_from_evtchn(port))) {
369 struct evtchn_unmask unmask = { .port = port };
370 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
371 } else {
780f36d8 372 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
373
374 sync_clear_bit(port, &s->evtchn_mask[0]);
375
376 /*
377 * The following is basically the equivalent of
378 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
379 * the interrupt edge' if the channel is masked.
380 */
381 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
382 !sync_test_and_set_bit(port / BITS_PER_LONG,
383 &vcpu_info->evtchn_pending_sel))
384 vcpu_info->evtchn_upcall_pending = 1;
385 }
386
387 put_cpu();
388}
389
6cb6537d
IC
390static void xen_irq_init(unsigned irq)
391{
392 struct irq_info *info;
393 struct irq_desc *desc = irq_to_desc(irq);
394
395 /* By default all event channels notify CPU#0. */
396 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
397
ca62ce8c
IC
398 info = kzalloc(sizeof(*info), GFP_KERNEL);
399 if (info == NULL)
400 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
401
402 info->type = IRQT_UNBOUND;
403
ca62ce8c
IC
404 set_irq_data(irq, info);
405
6cb6537d
IC
406 list_add_tail(&info->list, &xen_irq_list_head);
407}
408
7bee9768 409static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 410{
89911501
IC
411 int first = 0;
412 int irq;
0794bfc7
KRW
413
414#ifdef CONFIG_X86_IO_APIC
89911501
IC
415 /*
416 * For an HVM guest or domain 0 which see "real" (emulated or
417 * actual repectively) GSIs we allocate dynamic IRQs
418 * e.g. those corresponding to event channels or MSIs
419 * etc. from the range above those "real" GSIs to avoid
420 * collisions.
421 */
422 if (xen_initial_domain() || xen_hvm_domain())
423 first = get_nr_irqs_gsi();
0794bfc7
KRW
424#endif
425
89911501 426 irq = irq_alloc_desc_from(first, -1);
3a69e916 427
6cb6537d
IC
428 xen_irq_init(irq);
429
e46cdb66 430 return irq;
d46a78b0
JF
431}
432
7bee9768 433static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
434{
435 int irq;
436
89911501
IC
437 /*
438 * A PV guest has no concept of a GSI (since it has no ACPI
439 * nor access to/knowledge of the physical APICs). Therefore
440 * all IRQs are dynamically allocated from the entire IRQ
441 * space.
442 */
443 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
444 return xen_allocate_irq_dynamic();
445
446 /* Legacy IRQ descriptors are already allocated by the arch. */
447 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
448 irq = gsi;
449 else
450 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 451
6cb6537d
IC
452 xen_irq_init(irq);
453
c9df1ce5
IC
454 return irq;
455}
456
457static void xen_free_irq(unsigned irq)
458{
ca62ce8c 459 struct irq_info *info = get_irq_data(irq);
6cb6537d
IC
460
461 list_del(&info->list);
9158c358 462
ca62ce8c
IC
463 set_irq_data(irq, NULL);
464
465 kfree(info);
466
72146104
IC
467 /* Legacy IRQ descriptors are managed by the arch. */
468 if (irq < NR_IRQS_LEGACY)
469 return;
470
c9df1ce5
IC
471 irq_free_desc(irq);
472}
473
d46a78b0
JF
474static void pirq_unmask_notify(int irq)
475{
7a043f11 476 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
477
478 if (unlikely(pirq_needs_eoi(irq))) {
479 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
480 WARN_ON(rc);
481 }
482}
483
484static void pirq_query_unmask(int irq)
485{
486 struct physdev_irq_status_query irq_status;
487 struct irq_info *info = info_for_irq(irq);
488
489 BUG_ON(info->type != IRQT_PIRQ);
490
7a043f11 491 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
492 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
493 irq_status.flags = 0;
494
495 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
496 if (irq_status.flags & XENIRQSTAT_needs_eoi)
497 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
498}
499
500static bool probing_irq(int irq)
501{
502 struct irq_desc *desc = irq_to_desc(irq);
503
504 return desc && desc->action == NULL;
505}
506
c9e265e0 507static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
508{
509 struct evtchn_bind_pirq bind_pirq;
510 struct irq_info *info = info_for_irq(irq);
511 int evtchn = evtchn_from_irq(irq);
15ebbb82 512 int rc;
d46a78b0
JF
513
514 BUG_ON(info->type != IRQT_PIRQ);
515
516 if (VALID_EVTCHN(evtchn))
517 goto out;
518
7a043f11 519 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 520 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
521 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
522 BIND_PIRQ__WILL_SHARE : 0;
523 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
524 if (rc != 0) {
d46a78b0
JF
525 if (!probing_irq(irq))
526 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
527 irq);
528 return 0;
529 }
530 evtchn = bind_pirq.port;
531
532 pirq_query_unmask(irq);
533
534 evtchn_to_irq[evtchn] = irq;
535 bind_evtchn_to_cpu(evtchn, 0);
536 info->evtchn = evtchn;
537
538out:
539 unmask_evtchn(evtchn);
540 pirq_unmask_notify(irq);
541
542 return 0;
543}
544
c9e265e0
TG
545static unsigned int startup_pirq(struct irq_data *data)
546{
547 return __startup_pirq(data->irq);
548}
549
550static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
551{
552 struct evtchn_close close;
c9e265e0 553 unsigned int irq = data->irq;
d46a78b0
JF
554 struct irq_info *info = info_for_irq(irq);
555 int evtchn = evtchn_from_irq(irq);
556
557 BUG_ON(info->type != IRQT_PIRQ);
558
559 if (!VALID_EVTCHN(evtchn))
560 return;
561
562 mask_evtchn(evtchn);
563
564 close.port = evtchn;
565 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
566 BUG();
567
568 bind_evtchn_to_cpu(evtchn, 0);
569 evtchn_to_irq[evtchn] = -1;
570 info->evtchn = 0;
571}
572
c9e265e0 573static void enable_pirq(struct irq_data *data)
d46a78b0 574{
c9e265e0 575 startup_pirq(data);
d46a78b0
JF
576}
577
c9e265e0 578static void disable_pirq(struct irq_data *data)
d46a78b0
JF
579{
580}
581
c9e265e0 582static void ack_pirq(struct irq_data *data)
d46a78b0 583{
c9e265e0 584 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 585
aa673c1c 586 move_native_irq(data->irq);
d46a78b0
JF
587
588 if (VALID_EVTCHN(evtchn)) {
589 mask_evtchn(evtchn);
590 clear_evtchn(evtchn);
591 }
592}
593
d46a78b0
JF
594static int find_irq_by_gsi(unsigned gsi)
595{
6cb6537d 596 struct irq_info *info;
d46a78b0 597
6cb6537d
IC
598 list_for_each_entry(info, &xen_irq_list_head, list) {
599 if (info->type != IRQT_PIRQ)
d46a78b0
JF
600 continue;
601
6cb6537d
IC
602 if (info->u.pirq.gsi == gsi)
603 return info->irq;
d46a78b0
JF
604 }
605
606 return -1;
607}
608
f4d0635b 609int xen_allocate_pirq_gsi(unsigned gsi)
7a043f11 610{
f4d0635b 611 return gsi;
7a043f11
SS
612}
613
653378ac
IC
614/*
615 * Do not make any assumptions regarding the relationship between the
616 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
617 *
618 * Note: We don't assign an event channel until the irq actually started
619 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 620 */
f4d0635b
IC
621int xen_bind_pirq_gsi_to_irq(unsigned gsi,
622 unsigned pirq, int shareable, char *name)
d46a78b0 623{
a0e18116 624 int irq = -1;
d46a78b0
JF
625 struct physdev_irq irq_op;
626
627 spin_lock(&irq_mapping_update_lock);
628
629 irq = find_irq_by_gsi(gsi);
630 if (irq != -1) {
7a043f11 631 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
632 irq, gsi);
633 goto out; /* XXX need refcount? */
634 }
635
c9df1ce5 636 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
637 if (irq < 0)
638 goto out;
d46a78b0
JF
639
640 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 641 handle_level_irq, name);
d46a78b0
JF
642
643 irq_op.irq = irq;
b5401a96
AN
644 irq_op.vector = 0;
645
646 /* Only the privileged domain can do this. For non-priv, the pcifront
647 * driver provides a PCI bus that does the call to do exactly
648 * this in the priv domain. */
649 if (xen_initial_domain() &&
650 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 651 xen_free_irq(irq);
d46a78b0
JF
652 irq = -ENOSPC;
653 goto out;
654 }
655
9158c358
IC
656 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector,
657 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0
JF
658
659out:
660 spin_unlock(&irq_mapping_update_lock);
661
662 return irq;
663}
664
f731e3ef 665#ifdef CONFIG_PCI_MSI
bf480d95 666int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 667{
5cad61a6 668 int rc;
cbf6aa89 669 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 670
bf480d95 671 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 672 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 673
5cad61a6
IC
674 WARN_ONCE(rc == -ENOSYS,
675 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
676
677 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
678}
679
bf480d95 680int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
ca1d8fe9 681 int pirq, int vector, const char *name)
809f9267 682{
bf480d95 683 int irq, ret;
4b41df7f 684
809f9267
SS
685 spin_lock(&irq_mapping_update_lock);
686
4b41df7f
IC
687 irq = xen_allocate_irq_dynamic();
688 if (irq == -1)
bb5d079a 689 goto out;
809f9267 690
4b41df7f 691 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
809f9267
SS
692 handle_level_irq, name);
693
9158c358 694 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0);
bf480d95
IC
695 ret = set_irq_msi(irq, msidesc);
696 if (ret < 0)
697 goto error_irq;
809f9267
SS
698out:
699 spin_unlock(&irq_mapping_update_lock);
4b41df7f 700 return irq;
bf480d95
IC
701error_irq:
702 spin_unlock(&irq_mapping_update_lock);
703 xen_free_irq(irq);
704 return -1;
809f9267 705}
f731e3ef
QH
706#endif
707
b5401a96
AN
708int xen_destroy_irq(int irq)
709{
710 struct irq_desc *desc;
38aa66fc
JF
711 struct physdev_unmap_pirq unmap_irq;
712 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
713 int rc = -ENOENT;
714
715 spin_lock(&irq_mapping_update_lock);
716
717 desc = irq_to_desc(irq);
718 if (!desc)
719 goto out;
720
38aa66fc 721 if (xen_initial_domain()) {
12334715 722 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
723 unmap_irq.domid = DOMID_SELF;
724 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
725 if (rc) {
726 printk(KERN_WARNING "unmap irq failed %d\n", rc);
727 goto out;
728 }
729 }
1aa0b51a 730
c9df1ce5 731 xen_free_irq(irq);
b5401a96
AN
732
733out:
734 spin_unlock(&irq_mapping_update_lock);
735 return rc;
736}
737
af42b8d1
SS
738int xen_irq_from_pirq(unsigned pirq)
739{
69c358ce
IC
740 int irq;
741
742 struct irq_info *info;
743
744 spin_lock(&irq_mapping_update_lock);
745
746 list_for_each_entry(info, &xen_irq_list_head, list) {
747 if (info == NULL || info->type != IRQT_PIRQ)
748 continue;
749 irq = info->irq;
750 if (info->u.pirq.pirq == pirq)
751 goto out;
752 }
753 irq = -1;
754out:
755 spin_lock(&irq_mapping_update_lock);
756
757 return irq;
af42b8d1
SS
758}
759
b536b4b9 760int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
761{
762 int irq;
763
764 spin_lock(&irq_mapping_update_lock);
765
766 irq = evtchn_to_irq[evtchn];
767
768 if (irq == -1) {
c9df1ce5 769 irq = xen_allocate_irq_dynamic();
7bee9768
IC
770 if (irq == -1)
771 goto out;
e46cdb66 772
e46cdb66 773 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 774 handle_fasteoi_irq, "event");
e46cdb66 775
9158c358 776 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
777 }
778
7bee9768 779out:
e46cdb66
JF
780 spin_unlock(&irq_mapping_update_lock);
781
782 return irq;
783}
b536b4b9 784EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 785
f87e4cac
JF
786static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
787{
788 struct evtchn_bind_ipi bind_ipi;
789 int evtchn, irq;
790
791 spin_lock(&irq_mapping_update_lock);
792
793 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 794
f87e4cac 795 if (irq == -1) {
c9df1ce5 796 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
797 if (irq < 0)
798 goto out;
799
aaca4964
JF
800 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
801 handle_percpu_irq, "ipi");
f87e4cac
JF
802
803 bind_ipi.vcpu = cpu;
804 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
805 &bind_ipi) != 0)
806 BUG();
807 evtchn = bind_ipi.port;
808
3d4cfa37 809 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
810
811 bind_evtchn_to_cpu(evtchn, cpu);
812 }
813
f87e4cac
JF
814 out:
815 spin_unlock(&irq_mapping_update_lock);
816 return irq;
817}
818
819
4fe7d5a7 820int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
821{
822 struct evtchn_bind_virq bind_virq;
823 int evtchn, irq;
824
825 spin_lock(&irq_mapping_update_lock);
826
827 irq = per_cpu(virq_to_irq, cpu)[virq];
828
829 if (irq == -1) {
c9df1ce5 830 irq = xen_allocate_irq_dynamic();
7bee9768
IC
831 if (irq == -1)
832 goto out;
a52521f1
JF
833
834 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
835 handle_percpu_irq, "virq");
836
e46cdb66
JF
837 bind_virq.virq = virq;
838 bind_virq.vcpu = cpu;
839 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
840 &bind_virq) != 0)
841 BUG();
842 evtchn = bind_virq.port;
843
3d4cfa37 844 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
845
846 bind_evtchn_to_cpu(evtchn, cpu);
847 }
848
7bee9768 849out:
e46cdb66
JF
850 spin_unlock(&irq_mapping_update_lock);
851
852 return irq;
853}
854
855static void unbind_from_irq(unsigned int irq)
856{
857 struct evtchn_close close;
858 int evtchn = evtchn_from_irq(irq);
859
860 spin_lock(&irq_mapping_update_lock);
861
d77bbd4d 862 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
863 close.port = evtchn;
864 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
865 BUG();
866
867 switch (type_from_irq(irq)) {
868 case IRQT_VIRQ:
869 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 870 [virq_from_irq(irq)] = -1;
e46cdb66 871 break;
d68d82af
AN
872 case IRQT_IPI:
873 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 874 [ipi_from_irq(irq)] = -1;
d68d82af 875 break;
e46cdb66
JF
876 default:
877 break;
878 }
879
880 /* Closed ports are implicitly re-bound to VCPU0. */
881 bind_evtchn_to_cpu(evtchn, 0);
882
883 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
884 }
885
ca62ce8c 886 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 887
9158c358 888 xen_free_irq(irq);
e46cdb66
JF
889
890 spin_unlock(&irq_mapping_update_lock);
891}
892
893int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 894 irq_handler_t handler,
e46cdb66
JF
895 unsigned long irqflags,
896 const char *devname, void *dev_id)
897{
898 unsigned int irq;
899 int retval;
900
901 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
902 if (irq < 0)
903 return irq;
e46cdb66
JF
904 retval = request_irq(irq, handler, irqflags, devname, dev_id);
905 if (retval != 0) {
906 unbind_from_irq(irq);
907 return retval;
908 }
909
910 return irq;
911}
912EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
913
914int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 915 irq_handler_t handler,
e46cdb66
JF
916 unsigned long irqflags, const char *devname, void *dev_id)
917{
918 unsigned int irq;
919 int retval;
920
921 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
922 if (irq < 0)
923 return irq;
e46cdb66
JF
924 retval = request_irq(irq, handler, irqflags, devname, dev_id);
925 if (retval != 0) {
926 unbind_from_irq(irq);
927 return retval;
928 }
929
930 return irq;
931}
932EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
933
f87e4cac
JF
934int bind_ipi_to_irqhandler(enum ipi_vector ipi,
935 unsigned int cpu,
936 irq_handler_t handler,
937 unsigned long irqflags,
938 const char *devname,
939 void *dev_id)
940{
941 int irq, retval;
942
943 irq = bind_ipi_to_irq(ipi, cpu);
944 if (irq < 0)
945 return irq;
946
676dc3cf 947 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
948 retval = request_irq(irq, handler, irqflags, devname, dev_id);
949 if (retval != 0) {
950 unbind_from_irq(irq);
951 return retval;
952 }
953
954 return irq;
955}
956
e46cdb66
JF
957void unbind_from_irqhandler(unsigned int irq, void *dev_id)
958{
959 free_irq(irq, dev_id);
960 unbind_from_irq(irq);
961}
962EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
963
f87e4cac
JF
964void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
965{
966 int irq = per_cpu(ipi_to_irq, cpu)[vector];
967 BUG_ON(irq < 0);
968 notify_remote_via_irq(irq);
969}
970
ee523ca1
JF
971irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
972{
973 struct shared_info *sh = HYPERVISOR_shared_info;
974 int cpu = smp_processor_id();
cb60d114 975 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
976 int i;
977 unsigned long flags;
978 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 979 struct vcpu_info *v;
ee523ca1
JF
980
981 spin_lock_irqsave(&debug_lock, flags);
982
cb52e6d9 983 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
984
985 for_each_online_cpu(i) {
cb52e6d9
IC
986 int pending;
987 v = per_cpu(xen_vcpu, i);
988 pending = (get_irq_regs() && i == cpu)
989 ? xen_irqs_disabled(get_irq_regs())
990 : v->evtchn_upcall_mask;
991 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
992 pending, v->evtchn_upcall_pending,
993 (int)(sizeof(v->evtchn_pending_sel)*2),
994 v->evtchn_pending_sel);
995 }
996 v = per_cpu(xen_vcpu, cpu);
997
998 printk("\npending:\n ");
999 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1000 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1001 sh->evtchn_pending[i],
1002 i % 8 == 0 ? "\n " : " ");
1003 printk("\nglobal mask:\n ");
1004 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1005 printk("%0*lx%s",
1006 (int)(sizeof(sh->evtchn_mask[0])*2),
1007 sh->evtchn_mask[i],
1008 i % 8 == 0 ? "\n " : " ");
1009
1010 printk("\nglobally unmasked:\n ");
1011 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1012 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1013 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1014 i % 8 == 0 ? "\n " : " ");
1015
1016 printk("\nlocal cpu%d mask:\n ", cpu);
1017 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1018 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1019 cpu_evtchn[i],
1020 i % 8 == 0 ? "\n " : " ");
1021
1022 printk("\nlocally unmasked:\n ");
1023 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1024 unsigned long pending = sh->evtchn_pending[i]
1025 & ~sh->evtchn_mask[i]
1026 & cpu_evtchn[i];
1027 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1028 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1029 }
ee523ca1
JF
1030
1031 printk("\npending list:\n");
cb52e6d9 1032 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1033 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1034 int word_idx = i / BITS_PER_LONG;
1035 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1036 cpu_from_evtchn(i), i,
cb52e6d9
IC
1037 evtchn_to_irq[i],
1038 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1039 ? "" : " l2-clear",
1040 !sync_test_bit(i, sh->evtchn_mask)
1041 ? "" : " globally-masked",
1042 sync_test_bit(i, cpu_evtchn)
1043 ? "" : " locally-masked");
ee523ca1
JF
1044 }
1045 }
1046
1047 spin_unlock_irqrestore(&debug_lock, flags);
1048
1049 return IRQ_HANDLED;
1050}
1051
245b2e70
TH
1052static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1053
e46cdb66
JF
1054/*
1055 * Search the CPUs pending events bitmasks. For each one found, map
1056 * the event number to an irq, and feed it into do_IRQ() for
1057 * handling.
1058 *
1059 * Xen uses a two-level bitmap to speed searching. The first level is
1060 * a bitset of words which contain pending event bits. The second
1061 * level is a bitset of pending events themselves.
1062 */
38e20b07 1063static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1064{
1065 int cpu = get_cpu();
1066 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1067 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1068 unsigned count;
e46cdb66 1069
229664be
JF
1070 do {
1071 unsigned long pending_words;
e46cdb66 1072
229664be 1073 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1074
b2e4ae69 1075 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1076 goto out;
e46cdb66 1077
e849c3e9
IY
1078#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1079 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1080 wmb();
e849c3e9 1081#endif
229664be
JF
1082 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1083 while (pending_words != 0) {
1084 unsigned long pending_bits;
1085 int word_idx = __ffs(pending_words);
1086 pending_words &= ~(1UL << word_idx);
1087
1088 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1089 int bit_idx = __ffs(pending_bits);
1090 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1091 int irq = evtchn_to_irq[port];
ca4dbc66 1092 struct irq_desc *desc;
229664be 1093
3588fe2e
JF
1094 mask_evtchn(port);
1095 clear_evtchn(port);
1096
ca4dbc66
EB
1097 if (irq != -1) {
1098 desc = irq_to_desc(irq);
1099 if (desc)
1100 generic_handle_irq_desc(irq, desc);
1101 }
e46cdb66
JF
1102 }
1103 }
e46cdb66 1104
229664be
JF
1105 BUG_ON(!irqs_disabled());
1106
780f36d8
CL
1107 count = __this_cpu_read(xed_nesting_count);
1108 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1109 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1110
1111out:
38e20b07
SY
1112
1113 put_cpu();
1114}
1115
1116void xen_evtchn_do_upcall(struct pt_regs *regs)
1117{
1118 struct pt_regs *old_regs = set_irq_regs(regs);
1119
1120 exit_idle();
1121 irq_enter();
1122
1123 __xen_evtchn_do_upcall();
1124
3445a8fd
JF
1125 irq_exit();
1126 set_irq_regs(old_regs);
38e20b07 1127}
3445a8fd 1128
38e20b07
SY
1129void xen_hvm_evtchn_do_upcall(void)
1130{
1131 __xen_evtchn_do_upcall();
e46cdb66 1132}
183d03cc 1133EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1134
eb1e305f
JF
1135/* Rebind a new event channel to an existing irq. */
1136void rebind_evtchn_irq(int evtchn, int irq)
1137{
d77bbd4d
JF
1138 struct irq_info *info = info_for_irq(irq);
1139
eb1e305f
JF
1140 /* Make sure the irq is masked, since the new event channel
1141 will also be masked. */
1142 disable_irq(irq);
1143
1144 spin_lock(&irq_mapping_update_lock);
1145
1146 /* After resume the irq<->evtchn mappings are all cleared out */
1147 BUG_ON(evtchn_to_irq[evtchn] != -1);
1148 /* Expect irq to have been bound before,
d77bbd4d
JF
1149 so there should be a proper type */
1150 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1151
9158c358 1152 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f
JF
1153
1154 spin_unlock(&irq_mapping_update_lock);
1155
1156 /* new event channels are always bound to cpu 0 */
0de26520 1157 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1158
1159 /* Unmask the event channel. */
1160 enable_irq(irq);
1161}
1162
e46cdb66 1163/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1164static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1165{
1166 struct evtchn_bind_vcpu bind_vcpu;
1167 int evtchn = evtchn_from_irq(irq);
1168
be49472f
IC
1169 if (!VALID_EVTCHN(evtchn))
1170 return -1;
1171
1172 /*
1173 * Events delivered via platform PCI interrupts are always
1174 * routed to vcpu 0 and hence cannot be rebound.
1175 */
1176 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1177 return -1;
e46cdb66
JF
1178
1179 /* Send future instances of this interrupt to other vcpu. */
1180 bind_vcpu.port = evtchn;
1181 bind_vcpu.vcpu = tcpu;
1182
1183 /*
1184 * If this fails, it usually just indicates that we're dealing with a
1185 * virq or IPI channel, which don't actually need to be rebound. Ignore
1186 * it, but don't do the xenlinux-level rebind in that case.
1187 */
1188 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1189 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1190
d5dedd45
YL
1191 return 0;
1192}
e46cdb66 1193
c9e265e0
TG
1194static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1195 bool force)
e46cdb66 1196{
0de26520 1197 unsigned tcpu = cpumask_first(dest);
d5dedd45 1198
c9e265e0 1199 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1200}
1201
642e0c88
IY
1202int resend_irq_on_evtchn(unsigned int irq)
1203{
1204 int masked, evtchn = evtchn_from_irq(irq);
1205 struct shared_info *s = HYPERVISOR_shared_info;
1206
1207 if (!VALID_EVTCHN(evtchn))
1208 return 1;
1209
1210 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1211 sync_set_bit(evtchn, s->evtchn_pending);
1212 if (!masked)
1213 unmask_evtchn(evtchn);
1214
1215 return 1;
1216}
1217
c9e265e0 1218static void enable_dynirq(struct irq_data *data)
e46cdb66 1219{
c9e265e0 1220 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1221
1222 if (VALID_EVTCHN(evtchn))
1223 unmask_evtchn(evtchn);
1224}
1225
c9e265e0 1226static void disable_dynirq(struct irq_data *data)
e46cdb66 1227{
c9e265e0 1228 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1229
1230 if (VALID_EVTCHN(evtchn))
1231 mask_evtchn(evtchn);
1232}
1233
c9e265e0 1234static void ack_dynirq(struct irq_data *data)
e46cdb66 1235{
c9e265e0 1236 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1237
c9e265e0 1238 move_masked_irq(data->irq);
e46cdb66
JF
1239
1240 if (VALID_EVTCHN(evtchn))
3588fe2e 1241 unmask_evtchn(evtchn);
e46cdb66
JF
1242}
1243
c9e265e0 1244static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1245{
c9e265e0 1246 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1247 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1248 int ret = 0;
1249
1250 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1251 int masked;
1252
1253 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1254 sync_set_bit(evtchn, sh->evtchn_pending);
1255 if (!masked)
1256 unmask_evtchn(evtchn);
e46cdb66
JF
1257 ret = 1;
1258 }
1259
1260 return ret;
1261}
1262
0a85226f 1263static void restore_pirqs(void)
9a069c33
SS
1264{
1265 int pirq, rc, irq, gsi;
1266 struct physdev_map_pirq map_irq;
69c358ce 1267 struct irq_info *info;
9a069c33 1268
69c358ce
IC
1269 list_for_each_entry(info, &xen_irq_list_head, list) {
1270 if (info->type != IRQT_PIRQ)
9a069c33
SS
1271 continue;
1272
69c358ce
IC
1273 pirq = info->u.pirq.pirq;
1274 gsi = info->u.pirq.gsi;
1275 irq = info->irq;
1276
9a069c33
SS
1277 /* save/restore of PT devices doesn't work, so at this point the
1278 * only devices present are GSI based emulated devices */
9a069c33
SS
1279 if (!gsi)
1280 continue;
1281
1282 map_irq.domid = DOMID_SELF;
1283 map_irq.type = MAP_PIRQ_TYPE_GSI;
1284 map_irq.index = gsi;
1285 map_irq.pirq = pirq;
1286
1287 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1288 if (rc) {
1289 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1290 gsi, irq, pirq, rc);
9158c358 1291 xen_free_irq(irq);
9a069c33
SS
1292 continue;
1293 }
1294
1295 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1296
c9e265e0 1297 __startup_pirq(irq);
9a069c33
SS
1298 }
1299}
1300
0e91398f
JF
1301static void restore_cpu_virqs(unsigned int cpu)
1302{
1303 struct evtchn_bind_virq bind_virq;
1304 int virq, irq, evtchn;
1305
1306 for (virq = 0; virq < NR_VIRQS; virq++) {
1307 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1308 continue;
1309
ced40d0f 1310 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1311
1312 /* Get a new binding from Xen. */
1313 bind_virq.virq = virq;
1314 bind_virq.vcpu = cpu;
1315 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1316 &bind_virq) != 0)
1317 BUG();
1318 evtchn = bind_virq.port;
1319
1320 /* Record the new mapping. */
3d4cfa37 1321 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1322 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1323 }
1324}
1325
1326static void restore_cpu_ipis(unsigned int cpu)
1327{
1328 struct evtchn_bind_ipi bind_ipi;
1329 int ipi, irq, evtchn;
1330
1331 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1332 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1333 continue;
1334
ced40d0f 1335 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1336
1337 /* Get a new binding from Xen. */
1338 bind_ipi.vcpu = cpu;
1339 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1340 &bind_ipi) != 0)
1341 BUG();
1342 evtchn = bind_ipi.port;
1343
1344 /* Record the new mapping. */
3d4cfa37 1345 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1346 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1347 }
1348}
1349
2d9e1e2f
JF
1350/* Clear an irq's pending state, in preparation for polling on it */
1351void xen_clear_irq_pending(int irq)
1352{
1353 int evtchn = evtchn_from_irq(irq);
1354
1355 if (VALID_EVTCHN(evtchn))
1356 clear_evtchn(evtchn);
1357}
d9a8814f 1358EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1359void xen_set_irq_pending(int irq)
1360{
1361 int evtchn = evtchn_from_irq(irq);
1362
1363 if (VALID_EVTCHN(evtchn))
1364 set_evtchn(evtchn);
1365}
1366
1367bool xen_test_irq_pending(int irq)
1368{
1369 int evtchn = evtchn_from_irq(irq);
1370 bool ret = false;
1371
1372 if (VALID_EVTCHN(evtchn))
1373 ret = test_evtchn(evtchn);
1374
1375 return ret;
1376}
1377
d9a8814f
KRW
1378/* Poll waiting for an irq to become pending with timeout. In the usual case,
1379 * the irq will be disabled so it won't deliver an interrupt. */
1380void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1381{
1382 evtchn_port_t evtchn = evtchn_from_irq(irq);
1383
1384 if (VALID_EVTCHN(evtchn)) {
1385 struct sched_poll poll;
1386
1387 poll.nr_ports = 1;
d9a8814f 1388 poll.timeout = timeout;
ff3c5362 1389 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1390
1391 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1392 BUG();
1393 }
1394}
d9a8814f
KRW
1395EXPORT_SYMBOL(xen_poll_irq_timeout);
1396/* Poll waiting for an irq to become pending. In the usual case, the
1397 * irq will be disabled so it won't deliver an interrupt. */
1398void xen_poll_irq(int irq)
1399{
1400 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1401}
2d9e1e2f 1402
0e91398f
JF
1403void xen_irq_resume(void)
1404{
6cb6537d
IC
1405 unsigned int cpu, evtchn;
1406 struct irq_info *info;
0e91398f
JF
1407
1408 init_evtchn_cpu_bindings();
1409
1410 /* New event-channel space is not 'live' yet. */
1411 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1412 mask_evtchn(evtchn);
1413
1414 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1415 list_for_each_entry(info, &xen_irq_list_head, list)
1416 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1417
1418 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1419 evtchn_to_irq[evtchn] = -1;
1420
1421 for_each_possible_cpu(cpu) {
1422 restore_cpu_virqs(cpu);
1423 restore_cpu_ipis(cpu);
1424 }
6903591f 1425
0a85226f 1426 restore_pirqs();
0e91398f
JF
1427}
1428
e46cdb66 1429static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1430 .name = "xen-dyn",
54a353a0 1431
c9e265e0
TG
1432 .irq_disable = disable_dynirq,
1433 .irq_mask = disable_dynirq,
1434 .irq_unmask = enable_dynirq,
54a353a0 1435
c9e265e0
TG
1436 .irq_eoi = ack_dynirq,
1437 .irq_set_affinity = set_affinity_irq,
1438 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1439};
1440
d46a78b0 1441static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1442 .name = "xen-pirq",
d46a78b0 1443
c9e265e0
TG
1444 .irq_startup = startup_pirq,
1445 .irq_shutdown = shutdown_pirq,
d46a78b0 1446
c9e265e0
TG
1447 .irq_enable = enable_pirq,
1448 .irq_unmask = enable_pirq,
d46a78b0 1449
c9e265e0
TG
1450 .irq_disable = disable_pirq,
1451 .irq_mask = disable_pirq,
d46a78b0 1452
c9e265e0 1453 .irq_ack = ack_pirq,
d46a78b0 1454
c9e265e0 1455 .irq_set_affinity = set_affinity_irq,
d46a78b0 1456
c9e265e0 1457 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1458};
1459
aaca4964 1460static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1461 .name = "xen-percpu",
aaca4964 1462
c9e265e0
TG
1463 .irq_disable = disable_dynirq,
1464 .irq_mask = disable_dynirq,
1465 .irq_unmask = enable_dynirq,
aaca4964 1466
c9e265e0 1467 .irq_ack = ack_dynirq,
aaca4964
JF
1468};
1469
38e20b07
SY
1470int xen_set_callback_via(uint64_t via)
1471{
1472 struct xen_hvm_param a;
1473 a.domid = DOMID_SELF;
1474 a.index = HVM_PARAM_CALLBACK_IRQ;
1475 a.value = via;
1476 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1477}
1478EXPORT_SYMBOL_GPL(xen_set_callback_via);
1479
ca65f9fc 1480#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1481/* Vector callbacks are better than PCI interrupts to receive event
1482 * channel notifications because we can receive vector callbacks on any
1483 * vcpu and we don't need PCI support or APIC interactions. */
1484void xen_callback_vector(void)
1485{
1486 int rc;
1487 uint64_t callback_via;
1488 if (xen_have_vector_callback) {
1489 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1490 rc = xen_set_callback_via(callback_via);
1491 if (rc) {
1492 printk(KERN_ERR "Request for Xen HVM callback vector"
1493 " failed.\n");
1494 xen_have_vector_callback = 0;
1495 return;
1496 }
1497 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1498 "enabled\n");
1499 /* in the restore case the vector has already been allocated */
1500 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1501 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1502 }
1503}
ca65f9fc
SS
1504#else
1505void xen_callback_vector(void) {}
1506#endif
38e20b07 1507
e46cdb66
JF
1508void __init xen_init_IRQ(void)
1509{
e5fc7345 1510 int i;
c7a3589e 1511
b21ddbf5
JF
1512 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1513 GFP_KERNEL);
1514 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1515 evtchn_to_irq[i] = -1;
e46cdb66
JF
1516
1517 init_evtchn_cpu_bindings();
1518
1519 /* No event channels are 'live' right now. */
1520 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1521 mask_evtchn(i);
1522
38e20b07
SY
1523 if (xen_hvm_domain()) {
1524 xen_callback_vector();
1525 native_init_IRQ();
3942b740
SS
1526 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1527 * __acpi_register_gsi can point at the right function */
1528 pci_xen_hvm_init();
38e20b07
SY
1529 } else {
1530 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1531 if (xen_initial_domain())
1532 xen_setup_pirqs();
38e20b07 1533 }
e46cdb66 1534}
This page took 0.642466 seconds and 5 git commands to generate.