xen/events: fix unmask_evtchn for PV on HVM guests
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
e46cdb66 42#include <asm/xen/hypercall.h>
8d1b8753 43#include <asm/xen/hypervisor.h>
e46cdb66 44
38e20b07
SY
45#include <xen/xen.h>
46#include <xen/hvm.h>
e04d0d07 47#include <xen/xen-ops.h>
e46cdb66
JF
48#include <xen/events.h>
49#include <xen/interface/xen.h>
50#include <xen/interface/event_channel.h>
38e20b07
SY
51#include <xen/interface/hvm/hvm_op.h>
52#include <xen/interface/hvm/params.h>
e46cdb66 53
e46cdb66
JF
54/*
55 * This lock protects updates to the following mapping and reference-count
56 * arrays. The lock does not need to be acquired to read the mapping tables.
57 */
77365948 58static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 59
6cb6537d
IC
60static LIST_HEAD(xen_irq_list_head);
61
e46cdb66 62/* IRQ <-> VIRQ mapping. */
204fba4a 63static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 64
f87e4cac 65/* IRQ <-> IPI mapping */
204fba4a 66static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 67
ced40d0f
JF
68/* Interrupt types. */
69enum xen_irq_type {
d77bbd4d 70 IRQT_UNBOUND = 0,
f87e4cac
JF
71 IRQT_PIRQ,
72 IRQT_VIRQ,
73 IRQT_IPI,
74 IRQT_EVTCHN
75};
e46cdb66 76
ced40d0f
JF
77/*
78 * Packed IRQ information:
79 * type - enum xen_irq_type
80 * event channel - irq->event channel mapping
81 * cpu - cpu this event channel is bound to
82 * index - type-specific information:
42a1de56
SS
83 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
84 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
85 * VIRQ - virq number
86 * IPI - IPI vector
87 * EVTCHN -
88 */
088c05a8 89struct irq_info {
6cb6537d 90 struct list_head list;
420eb554 91 int refcnt;
ced40d0f 92 enum xen_irq_type type; /* type */
6cb6537d 93 unsigned irq;
ced40d0f
JF
94 unsigned short evtchn; /* event channel */
95 unsigned short cpu; /* cpu bound */
96
97 union {
98 unsigned short virq;
99 enum ipi_vector ipi;
100 struct {
7a043f11 101 unsigned short pirq;
ced40d0f 102 unsigned short gsi;
d46a78b0
JF
103 unsigned char vector;
104 unsigned char flags;
beafbdc1 105 uint16_t domid;
ced40d0f
JF
106 } pirq;
107 } u;
108};
d46a78b0 109#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 110#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 111
b21ddbf5 112static int *evtchn_to_irq;
9846ff10
SS
113static unsigned long *pirq_eoi_map;
114static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 115
cb60d114
IC
116static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
117 cpu_evtchn_mask);
e46cdb66 118
e46cdb66
JF
119/* Xen will never allocate port zero for any purpose. */
120#define VALID_EVTCHN(chn) ((chn) != 0)
121
e46cdb66 122static struct irq_chip xen_dynamic_chip;
aaca4964 123static struct irq_chip xen_percpu_chip;
d46a78b0 124static struct irq_chip xen_pirq_chip;
7e186bdd
SS
125static void enable_dynirq(struct irq_data *data);
126static void disable_dynirq(struct irq_data *data);
e46cdb66 127
9158c358
IC
128/* Get info for IRQ */
129static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 130{
c442b806 131 return irq_get_handler_data(irq);
ced40d0f
JF
132}
133
9158c358
IC
134/* Constructors for packed IRQ information. */
135static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 136 unsigned irq,
9158c358
IC
137 enum xen_irq_type type,
138 unsigned short evtchn,
139 unsigned short cpu)
ced40d0f 140{
9158c358
IC
141
142 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
143
144 info->type = type;
6cb6537d 145 info->irq = irq;
9158c358
IC
146 info->evtchn = evtchn;
147 info->cpu = cpu;
3d4cfa37
IC
148
149 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
150}
151
9158c358
IC
152static void xen_irq_info_evtchn_init(unsigned irq,
153 unsigned short evtchn)
ced40d0f 154{
9158c358
IC
155 struct irq_info *info = info_for_irq(irq);
156
3d4cfa37 157 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
158}
159
3d4cfa37
IC
160static void xen_irq_info_ipi_init(unsigned cpu,
161 unsigned irq,
9158c358
IC
162 unsigned short evtchn,
163 enum ipi_vector ipi)
e46cdb66 164{
9158c358
IC
165 struct irq_info *info = info_for_irq(irq);
166
3d4cfa37 167 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
168
169 info->u.ipi = ipi;
3d4cfa37
IC
170
171 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
172}
173
3d4cfa37
IC
174static void xen_irq_info_virq_init(unsigned cpu,
175 unsigned irq,
9158c358
IC
176 unsigned short evtchn,
177 unsigned short virq)
ced40d0f 178{
9158c358
IC
179 struct irq_info *info = info_for_irq(irq);
180
3d4cfa37 181 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
182
183 info->u.virq = virq;
3d4cfa37
IC
184
185 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
186}
187
9158c358
IC
188static void xen_irq_info_pirq_init(unsigned irq,
189 unsigned short evtchn,
190 unsigned short pirq,
191 unsigned short gsi,
192 unsigned short vector,
beafbdc1 193 uint16_t domid,
9158c358 194 unsigned char flags)
ced40d0f 195{
9158c358
IC
196 struct irq_info *info = info_for_irq(irq);
197
3d4cfa37 198 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
199
200 info->u.pirq.pirq = pirq;
201 info->u.pirq.gsi = gsi;
202 info->u.pirq.vector = vector;
beafbdc1 203 info->u.pirq.domid = domid;
9158c358 204 info->u.pirq.flags = flags;
e46cdb66
JF
205}
206
207/*
208 * Accessors for packed IRQ information.
209 */
ced40d0f 210static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 211{
110e7c7e
JJ
212 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
213 return 0;
214
ced40d0f 215 return info_for_irq(irq)->evtchn;
e46cdb66
JF
216}
217
d4c04536
IC
218unsigned irq_from_evtchn(unsigned int evtchn)
219{
220 return evtchn_to_irq[evtchn];
221}
222EXPORT_SYMBOL_GPL(irq_from_evtchn);
223
ced40d0f 224static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 225{
ced40d0f
JF
226 struct irq_info *info = info_for_irq(irq);
227
228 BUG_ON(info == NULL);
229 BUG_ON(info->type != IRQT_IPI);
230
231 return info->u.ipi;
232}
233
234static unsigned virq_from_irq(unsigned irq)
235{
236 struct irq_info *info = info_for_irq(irq);
237
238 BUG_ON(info == NULL);
239 BUG_ON(info->type != IRQT_VIRQ);
240
241 return info->u.virq;
242}
243
7a043f11
SS
244static unsigned pirq_from_irq(unsigned irq)
245{
246 struct irq_info *info = info_for_irq(irq);
247
248 BUG_ON(info == NULL);
249 BUG_ON(info->type != IRQT_PIRQ);
250
251 return info->u.pirq.pirq;
252}
253
ced40d0f
JF
254static enum xen_irq_type type_from_irq(unsigned irq)
255{
256 return info_for_irq(irq)->type;
257}
258
259static unsigned cpu_from_irq(unsigned irq)
260{
261 return info_for_irq(irq)->cpu;
262}
263
264static unsigned int cpu_from_evtchn(unsigned int evtchn)
265{
266 int irq = evtchn_to_irq[evtchn];
267 unsigned ret = 0;
268
269 if (irq != -1)
270 ret = cpu_from_irq(irq);
271
272 return ret;
e46cdb66
JF
273}
274
9846ff10 275static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 276{
521394e4 277 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 278}
d46a78b0 279
9846ff10
SS
280static bool pirq_needs_eoi_flag(unsigned irq)
281{
282 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
283 BUG_ON(info->type != IRQT_PIRQ);
284
285 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
286}
287
e46cdb66
JF
288static inline unsigned long active_evtchns(unsigned int cpu,
289 struct shared_info *sh,
290 unsigned int idx)
291{
088c05a8 292 return sh->evtchn_pending[idx] &
cb60d114 293 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 294 ~sh->evtchn_mask[idx];
e46cdb66
JF
295}
296
297static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
298{
299 int irq = evtchn_to_irq[chn];
300
301 BUG_ON(irq == -1);
302#ifdef CONFIG_SMP
c9e265e0 303 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
304#endif
305
cb60d114
IC
306 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
307 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 308
ca62ce8c 309 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
310}
311
312static void init_evtchn_cpu_bindings(void)
313{
1c6969ec 314 int i;
e46cdb66 315#ifdef CONFIG_SMP
6cb6537d 316 struct irq_info *info;
10e58084 317
e46cdb66 318 /* By default all event channels notify CPU#0. */
6cb6537d
IC
319 list_for_each_entry(info, &xen_irq_list_head, list) {
320 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 321 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 322 }
e46cdb66
JF
323#endif
324
1c6969ec 325 for_each_possible_cpu(i)
cb60d114
IC
326 memset(per_cpu(cpu_evtchn_mask, i),
327 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
328}
329
e46cdb66
JF
330static inline void clear_evtchn(int port)
331{
332 struct shared_info *s = HYPERVISOR_shared_info;
333 sync_clear_bit(port, &s->evtchn_pending[0]);
334}
335
336static inline void set_evtchn(int port)
337{
338 struct shared_info *s = HYPERVISOR_shared_info;
339 sync_set_bit(port, &s->evtchn_pending[0]);
340}
341
168d2f46
JF
342static inline int test_evtchn(int port)
343{
344 struct shared_info *s = HYPERVISOR_shared_info;
345 return sync_test_bit(port, &s->evtchn_pending[0]);
346}
347
e46cdb66
JF
348
349/**
350 * notify_remote_via_irq - send event to remote end of event channel via irq
351 * @irq: irq of event channel to send event to
352 *
353 * Unlike notify_remote_via_evtchn(), this is safe to use across
354 * save/restore. Notifications on a broken connection are silently
355 * dropped.
356 */
357void notify_remote_via_irq(int irq)
358{
359 int evtchn = evtchn_from_irq(irq);
360
361 if (VALID_EVTCHN(evtchn))
362 notify_remote_via_evtchn(evtchn);
363}
364EXPORT_SYMBOL_GPL(notify_remote_via_irq);
365
366static void mask_evtchn(int port)
367{
368 struct shared_info *s = HYPERVISOR_shared_info;
369 sync_set_bit(port, &s->evtchn_mask[0]);
370}
371
372static void unmask_evtchn(int port)
373{
374 struct shared_info *s = HYPERVISOR_shared_info;
375 unsigned int cpu = get_cpu();
b5e57923 376 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
377
378 BUG_ON(!irqs_disabled());
379
b5e57923
SS
380 if (unlikely((cpu != cpu_from_evtchn(port))))
381 do_hypercall = 1;
382 else
383 evtchn_pending = sync_test_bit(port, &s->evtchn_pending[0]);
384
385 if (unlikely(evtchn_pending && xen_hvm_domain()))
386 do_hypercall = 1;
387
388 /* Slow path (hypercall) if this is a non-local port or if this is
389 * an hvm domain and an event is pending (hvm domains don't have
390 * their own implementation of irq_enable). */
391 if (do_hypercall) {
e46cdb66
JF
392 struct evtchn_unmask unmask = { .port = port };
393 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
394 } else {
780f36d8 395 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
396
397 sync_clear_bit(port, &s->evtchn_mask[0]);
398
399 /*
400 * The following is basically the equivalent of
401 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
402 * the interrupt edge' if the channel is masked.
403 */
b5e57923 404 if (evtchn_pending &&
e46cdb66
JF
405 !sync_test_and_set_bit(port / BITS_PER_LONG,
406 &vcpu_info->evtchn_pending_sel))
407 vcpu_info->evtchn_upcall_pending = 1;
408 }
409
410 put_cpu();
411}
412
6cb6537d
IC
413static void xen_irq_init(unsigned irq)
414{
415 struct irq_info *info;
b5328cd1 416#ifdef CONFIG_SMP
6cb6537d
IC
417 struct irq_desc *desc = irq_to_desc(irq);
418
419 /* By default all event channels notify CPU#0. */
420 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 421#endif
6cb6537d 422
ca62ce8c
IC
423 info = kzalloc(sizeof(*info), GFP_KERNEL);
424 if (info == NULL)
425 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
426
427 info->type = IRQT_UNBOUND;
420eb554 428 info->refcnt = -1;
6cb6537d 429
c442b806 430 irq_set_handler_data(irq, info);
ca62ce8c 431
6cb6537d
IC
432 list_add_tail(&info->list, &xen_irq_list_head);
433}
434
7bee9768 435static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 436{
89911501
IC
437 int first = 0;
438 int irq;
0794bfc7
KRW
439
440#ifdef CONFIG_X86_IO_APIC
89911501
IC
441 /*
442 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 443 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
444 * e.g. those corresponding to event channels or MSIs
445 * etc. from the range above those "real" GSIs to avoid
446 * collisions.
447 */
448 if (xen_initial_domain() || xen_hvm_domain())
449 first = get_nr_irqs_gsi();
0794bfc7
KRW
450#endif
451
89911501 452 irq = irq_alloc_desc_from(first, -1);
3a69e916 453
e6599225
KRW
454 if (irq >= 0)
455 xen_irq_init(irq);
ced40d0f 456
e46cdb66 457 return irq;
d46a78b0
JF
458}
459
7bee9768 460static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
461{
462 int irq;
463
89911501
IC
464 /*
465 * A PV guest has no concept of a GSI (since it has no ACPI
466 * nor access to/knowledge of the physical APICs). Therefore
467 * all IRQs are dynamically allocated from the entire IRQ
468 * space.
469 */
470 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
471 return xen_allocate_irq_dynamic();
472
473 /* Legacy IRQ descriptors are already allocated by the arch. */
474 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
475 irq = gsi;
476 else
477 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 478
6cb6537d 479 xen_irq_init(irq);
c9df1ce5
IC
480
481 return irq;
482}
483
484static void xen_free_irq(unsigned irq)
485{
c442b806 486 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
487
488 list_del(&info->list);
9158c358 489
c442b806 490 irq_set_handler_data(irq, NULL);
ca62ce8c 491
420eb554
DDG
492 WARN_ON(info->refcnt > 0);
493
ca62ce8c
IC
494 kfree(info);
495
72146104
IC
496 /* Legacy IRQ descriptors are managed by the arch. */
497 if (irq < NR_IRQS_LEGACY)
498 return;
499
c9df1ce5
IC
500 irq_free_desc(irq);
501}
502
d46a78b0
JF
503static void pirq_query_unmask(int irq)
504{
505 struct physdev_irq_status_query irq_status;
506 struct irq_info *info = info_for_irq(irq);
507
508 BUG_ON(info->type != IRQT_PIRQ);
509
7a043f11 510 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
511 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
512 irq_status.flags = 0;
513
514 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
515 if (irq_status.flags & XENIRQSTAT_needs_eoi)
516 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
517}
518
519static bool probing_irq(int irq)
520{
521 struct irq_desc *desc = irq_to_desc(irq);
522
523 return desc && desc->action == NULL;
524}
525
7e186bdd
SS
526static void eoi_pirq(struct irq_data *data)
527{
528 int evtchn = evtchn_from_irq(data->irq);
529 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
530 int rc = 0;
531
532 irq_move_irq(data);
533
534 if (VALID_EVTCHN(evtchn))
535 clear_evtchn(evtchn);
536
537 if (pirq_needs_eoi(data->irq)) {
538 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
539 WARN_ON(rc);
540 }
541}
542
543static void mask_ack_pirq(struct irq_data *data)
544{
545 disable_dynirq(data);
546 eoi_pirq(data);
547}
548
c9e265e0 549static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
550{
551 struct evtchn_bind_pirq bind_pirq;
552 struct irq_info *info = info_for_irq(irq);
553 int evtchn = evtchn_from_irq(irq);
15ebbb82 554 int rc;
d46a78b0
JF
555
556 BUG_ON(info->type != IRQT_PIRQ);
557
558 if (VALID_EVTCHN(evtchn))
559 goto out;
560
7a043f11 561 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 562 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
563 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
564 BIND_PIRQ__WILL_SHARE : 0;
565 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
566 if (rc != 0) {
d46a78b0
JF
567 if (!probing_irq(irq))
568 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
569 irq);
570 return 0;
571 }
572 evtchn = bind_pirq.port;
573
574 pirq_query_unmask(irq);
575
576 evtchn_to_irq[evtchn] = irq;
577 bind_evtchn_to_cpu(evtchn, 0);
578 info->evtchn = evtchn;
579
580out:
581 unmask_evtchn(evtchn);
7e186bdd 582 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
583
584 return 0;
585}
586
c9e265e0
TG
587static unsigned int startup_pirq(struct irq_data *data)
588{
589 return __startup_pirq(data->irq);
590}
591
592static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
593{
594 struct evtchn_close close;
c9e265e0 595 unsigned int irq = data->irq;
d46a78b0
JF
596 struct irq_info *info = info_for_irq(irq);
597 int evtchn = evtchn_from_irq(irq);
598
599 BUG_ON(info->type != IRQT_PIRQ);
600
601 if (!VALID_EVTCHN(evtchn))
602 return;
603
604 mask_evtchn(evtchn);
605
606 close.port = evtchn;
607 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
608 BUG();
609
610 bind_evtchn_to_cpu(evtchn, 0);
611 evtchn_to_irq[evtchn] = -1;
612 info->evtchn = 0;
613}
614
c9e265e0 615static void enable_pirq(struct irq_data *data)
d46a78b0 616{
c9e265e0 617 startup_pirq(data);
d46a78b0
JF
618}
619
c9e265e0 620static void disable_pirq(struct irq_data *data)
d46a78b0 621{
7e186bdd 622 disable_dynirq(data);
d46a78b0
JF
623}
624
68c2c39a 625int xen_irq_from_gsi(unsigned gsi)
d46a78b0 626{
6cb6537d 627 struct irq_info *info;
d46a78b0 628
6cb6537d
IC
629 list_for_each_entry(info, &xen_irq_list_head, list) {
630 if (info->type != IRQT_PIRQ)
d46a78b0
JF
631 continue;
632
6cb6537d
IC
633 if (info->u.pirq.gsi == gsi)
634 return info->irq;
d46a78b0
JF
635 }
636
637 return -1;
638}
68c2c39a 639EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 640
653378ac
IC
641/*
642 * Do not make any assumptions regarding the relationship between the
643 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
644 *
645 * Note: We don't assign an event channel until the irq actually started
646 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
647 *
648 * Shareable implies level triggered, not shareable implies edge
649 * triggered here.
d46a78b0 650 */
f4d0635b
IC
651int xen_bind_pirq_gsi_to_irq(unsigned gsi,
652 unsigned pirq, int shareable, char *name)
d46a78b0 653{
a0e18116 654 int irq = -1;
d46a78b0
JF
655 struct physdev_irq irq_op;
656
77365948 657 mutex_lock(&irq_mapping_update_lock);
d46a78b0 658
68c2c39a 659 irq = xen_irq_from_gsi(gsi);
d46a78b0 660 if (irq != -1) {
7a043f11 661 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 662 irq, gsi);
420eb554 663 goto out;
d46a78b0
JF
664 }
665
c9df1ce5 666 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
667 if (irq < 0)
668 goto out;
d46a78b0 669
d46a78b0 670 irq_op.irq = irq;
b5401a96
AN
671 irq_op.vector = 0;
672
673 /* Only the privileged domain can do this. For non-priv, the pcifront
674 * driver provides a PCI bus that does the call to do exactly
675 * this in the priv domain. */
676 if (xen_initial_domain() &&
677 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 678 xen_free_irq(irq);
d46a78b0
JF
679 irq = -ENOSPC;
680 goto out;
681 }
682
beafbdc1 683 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 684 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 685
7e186bdd
SS
686 pirq_query_unmask(irq);
687 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
688 * type of interrupt: if the interrupt is an edge triggered
689 * interrupt we use handle_edge_irq.
7e186bdd 690 *
e5ac0bda
SS
691 * On the other hand if the interrupt is level triggered we use
692 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 693 * interrupts.
e5ac0bda 694 *
7e186bdd
SS
695 * Depending on the Xen version, pirq_needs_eoi might return true
696 * not only for level triggered interrupts but for edge triggered
697 * interrupts too. In any case Xen always honors the eoi mechanism,
698 * not injecting any more pirqs of the same kind if the first one
699 * hasn't received an eoi yet. Therefore using the fasteoi handler
700 * is the right choice either way.
701 */
e5ac0bda 702 if (shareable)
7e186bdd
SS
703 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
704 handle_fasteoi_irq, name);
705 else
706 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
707 handle_edge_irq, name);
708
d46a78b0 709out:
77365948 710 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
711
712 return irq;
713}
714
f731e3ef 715#ifdef CONFIG_PCI_MSI
bf480d95 716int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 717{
5cad61a6 718 int rc;
cbf6aa89 719 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 720
bf480d95 721 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 722 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 723
5cad61a6
IC
724 WARN_ONCE(rc == -ENOSYS,
725 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
726
727 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
728}
729
bf480d95 730int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
731 int pirq, int vector, const char *name,
732 domid_t domid)
809f9267 733{
bf480d95 734 int irq, ret;
4b41df7f 735
77365948 736 mutex_lock(&irq_mapping_update_lock);
809f9267 737
4b41df7f 738 irq = xen_allocate_irq_dynamic();
e6599225 739 if (irq < 0)
bb5d079a 740 goto out;
809f9267 741
7e186bdd
SS
742 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
743 name);
809f9267 744
beafbdc1 745 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 746 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
747 if (ret < 0)
748 goto error_irq;
809f9267 749out:
77365948 750 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 751 return irq;
bf480d95 752error_irq:
77365948 753 mutex_unlock(&irq_mapping_update_lock);
bf480d95 754 xen_free_irq(irq);
e6599225 755 return ret;
809f9267 756}
f731e3ef
QH
757#endif
758
b5401a96
AN
759int xen_destroy_irq(int irq)
760{
761 struct irq_desc *desc;
38aa66fc
JF
762 struct physdev_unmap_pirq unmap_irq;
763 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
764 int rc = -ENOENT;
765
77365948 766 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
767
768 desc = irq_to_desc(irq);
769 if (!desc)
770 goto out;
771
38aa66fc 772 if (xen_initial_domain()) {
12334715 773 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 774 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 775 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
776 /* If another domain quits without making the pci_disable_msix
777 * call, the Xen hypervisor takes care of freeing the PIRQs
778 * (free_domain_pirqs).
779 */
780 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
781 printk(KERN_INFO "domain %d does not have %d anymore\n",
782 info->u.pirq.domid, info->u.pirq.pirq);
783 else if (rc) {
38aa66fc
JF
784 printk(KERN_WARNING "unmap irq failed %d\n", rc);
785 goto out;
786 }
787 }
b5401a96 788
c9df1ce5 789 xen_free_irq(irq);
b5401a96
AN
790
791out:
77365948 792 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
793 return rc;
794}
795
af42b8d1 796int xen_irq_from_pirq(unsigned pirq)
d46a78b0 797{
69c358ce 798 int irq;
d46a78b0 799
69c358ce 800 struct irq_info *info;
e46cdb66 801
77365948 802 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
803
804 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 805 if (info->type != IRQT_PIRQ)
69c358ce
IC
806 continue;
807 irq = info->irq;
808 if (info->u.pirq.pirq == pirq)
809 goto out;
810 }
811 irq = -1;
812out:
77365948 813 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
814
815 return irq;
af42b8d1
SS
816}
817
e6197acc
KRW
818
819int xen_pirq_from_irq(unsigned irq)
820{
821 return pirq_from_irq(irq);
822}
823EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 824int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
825{
826 int irq;
827
77365948 828 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
829
830 irq = evtchn_to_irq[evtchn];
831
832 if (irq == -1) {
c9df1ce5 833 irq = xen_allocate_irq_dynamic();
7bee9768
IC
834 if (irq == -1)
835 goto out;
e46cdb66 836
c442b806 837 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 838 handle_edge_irq, "event");
e46cdb66 839
9158c358 840 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
841 } else {
842 struct irq_info *info = info_for_irq(irq);
843 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
844 }
845
7bee9768 846out:
77365948 847 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
848
849 return irq;
850}
b536b4b9 851EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 852
f87e4cac
JF
853static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
854{
855 struct evtchn_bind_ipi bind_ipi;
856 int evtchn, irq;
857
77365948 858 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
859
860 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 861
f87e4cac 862 if (irq == -1) {
c9df1ce5 863 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
864 if (irq < 0)
865 goto out;
866
c442b806 867 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 868 handle_percpu_irq, "ipi");
f87e4cac
JF
869
870 bind_ipi.vcpu = cpu;
871 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
872 &bind_ipi) != 0)
873 BUG();
874 evtchn = bind_ipi.port;
875
3d4cfa37 876 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
877
878 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
879 } else {
880 struct irq_info *info = info_for_irq(irq);
881 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
882 }
883
f87e4cac 884 out:
77365948 885 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
886 return irq;
887}
888
2e820f58
IC
889static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
890 unsigned int remote_port)
891{
892 struct evtchn_bind_interdomain bind_interdomain;
893 int err;
894
895 bind_interdomain.remote_dom = remote_domain;
896 bind_interdomain.remote_port = remote_port;
897
898 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
899 &bind_interdomain);
900
901 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
902}
903
62cc5fc7
OH
904static int find_virq(unsigned int virq, unsigned int cpu)
905{
906 struct evtchn_status status;
907 int port, rc = -ENOENT;
908
909 memset(&status, 0, sizeof(status));
910 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
911 status.dom = DOMID_SELF;
912 status.port = port;
913 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
914 if (rc < 0)
915 continue;
916 if (status.status != EVTCHNSTAT_virq)
917 continue;
918 if (status.u.virq == virq && status.vcpu == cpu) {
919 rc = port;
920 break;
921 }
922 }
923 return rc;
924}
f87e4cac 925
4fe7d5a7 926int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
927{
928 struct evtchn_bind_virq bind_virq;
62cc5fc7 929 int evtchn, irq, ret;
e46cdb66 930
77365948 931 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
932
933 irq = per_cpu(virq_to_irq, cpu)[virq];
934
935 if (irq == -1) {
c9df1ce5 936 irq = xen_allocate_irq_dynamic();
7bee9768
IC
937 if (irq == -1)
938 goto out;
a52521f1 939
c442b806 940 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
941 handle_percpu_irq, "virq");
942
e46cdb66
JF
943 bind_virq.virq = virq;
944 bind_virq.vcpu = cpu;
62cc5fc7
OH
945 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
946 &bind_virq);
947 if (ret == 0)
948 evtchn = bind_virq.port;
949 else {
950 if (ret == -EEXIST)
951 ret = find_virq(virq, cpu);
952 BUG_ON(ret < 0);
953 evtchn = ret;
954 }
e46cdb66 955
3d4cfa37 956 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
957
958 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
959 } else {
960 struct irq_info *info = info_for_irq(irq);
961 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
962 }
963
7bee9768 964out:
77365948 965 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
966
967 return irq;
968}
969
970static void unbind_from_irq(unsigned int irq)
971{
972 struct evtchn_close close;
973 int evtchn = evtchn_from_irq(irq);
420eb554 974 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 975
77365948 976 mutex_lock(&irq_mapping_update_lock);
e46cdb66 977
420eb554
DDG
978 if (info->refcnt > 0) {
979 info->refcnt--;
980 if (info->refcnt != 0)
981 goto done;
982 }
983
d77bbd4d 984 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
985 close.port = evtchn;
986 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
987 BUG();
988
989 switch (type_from_irq(irq)) {
990 case IRQT_VIRQ:
991 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 992 [virq_from_irq(irq)] = -1;
e46cdb66 993 break;
d68d82af
AN
994 case IRQT_IPI:
995 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 996 [ipi_from_irq(irq)] = -1;
d68d82af 997 break;
e46cdb66
JF
998 default:
999 break;
1000 }
1001
1002 /* Closed ports are implicitly re-bound to VCPU0. */
1003 bind_evtchn_to_cpu(evtchn, 0);
1004
1005 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1006 }
1007
ca62ce8c 1008 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1009
9158c358 1010 xen_free_irq(irq);
e46cdb66 1011
420eb554 1012 done:
77365948 1013 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1014}
1015
1016int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1017 irq_handler_t handler,
e46cdb66
JF
1018 unsigned long irqflags,
1019 const char *devname, void *dev_id)
1020{
361ae8cb 1021 int irq, retval;
e46cdb66
JF
1022
1023 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1024 if (irq < 0)
1025 return irq;
e46cdb66
JF
1026 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1027 if (retval != 0) {
1028 unbind_from_irq(irq);
1029 return retval;
1030 }
1031
1032 return irq;
1033}
1034EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1035
2e820f58
IC
1036int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1037 unsigned int remote_port,
1038 irq_handler_t handler,
1039 unsigned long irqflags,
1040 const char *devname,
1041 void *dev_id)
1042{
1043 int irq, retval;
1044
1045 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1046 if (irq < 0)
1047 return irq;
1048
1049 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1050 if (retval != 0) {
1051 unbind_from_irq(irq);
1052 return retval;
1053 }
1054
1055 return irq;
1056}
1057EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1058
e46cdb66 1059int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1060 irq_handler_t handler,
e46cdb66
JF
1061 unsigned long irqflags, const char *devname, void *dev_id)
1062{
361ae8cb 1063 int irq, retval;
e46cdb66
JF
1064
1065 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1066 if (irq < 0)
1067 return irq;
e46cdb66
JF
1068 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1069 if (retval != 0) {
1070 unbind_from_irq(irq);
1071 return retval;
1072 }
1073
1074 return irq;
1075}
1076EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1077
f87e4cac
JF
1078int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1079 unsigned int cpu,
1080 irq_handler_t handler,
1081 unsigned long irqflags,
1082 const char *devname,
1083 void *dev_id)
1084{
1085 int irq, retval;
1086
1087 irq = bind_ipi_to_irq(ipi, cpu);
1088 if (irq < 0)
1089 return irq;
1090
9bab0b7f 1091 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1092 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1093 if (retval != 0) {
1094 unbind_from_irq(irq);
1095 return retval;
1096 }
1097
1098 return irq;
1099}
1100
e46cdb66
JF
1101void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1102{
1103 free_irq(irq, dev_id);
1104 unbind_from_irq(irq);
1105}
1106EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1107
420eb554
DDG
1108int evtchn_make_refcounted(unsigned int evtchn)
1109{
1110 int irq = evtchn_to_irq[evtchn];
1111 struct irq_info *info;
1112
1113 if (irq == -1)
1114 return -ENOENT;
1115
1116 info = irq_get_handler_data(irq);
1117
1118 if (!info)
1119 return -ENOENT;
1120
1121 WARN_ON(info->refcnt != -1);
1122
1123 info->refcnt = 1;
1124
1125 return 0;
1126}
1127EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1128
1129int evtchn_get(unsigned int evtchn)
1130{
1131 int irq;
1132 struct irq_info *info;
1133 int err = -ENOENT;
1134
c3b3f16d
DDG
1135 if (evtchn >= NR_EVENT_CHANNELS)
1136 return -EINVAL;
1137
420eb554
DDG
1138 mutex_lock(&irq_mapping_update_lock);
1139
1140 irq = evtchn_to_irq[evtchn];
1141 if (irq == -1)
1142 goto done;
1143
1144 info = irq_get_handler_data(irq);
1145
1146 if (!info)
1147 goto done;
1148
1149 err = -EINVAL;
1150 if (info->refcnt <= 0)
1151 goto done;
1152
1153 info->refcnt++;
1154 err = 0;
1155 done:
1156 mutex_unlock(&irq_mapping_update_lock);
1157
1158 return err;
1159}
1160EXPORT_SYMBOL_GPL(evtchn_get);
1161
1162void evtchn_put(unsigned int evtchn)
1163{
1164 int irq = evtchn_to_irq[evtchn];
1165 if (WARN_ON(irq == -1))
1166 return;
1167 unbind_from_irq(irq);
1168}
1169EXPORT_SYMBOL_GPL(evtchn_put);
1170
f87e4cac
JF
1171void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1172{
1173 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1174 BUG_ON(irq < 0);
1175 notify_remote_via_irq(irq);
1176}
1177
ee523ca1
JF
1178irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1179{
1180 struct shared_info *sh = HYPERVISOR_shared_info;
1181 int cpu = smp_processor_id();
cb60d114 1182 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1183 int i;
1184 unsigned long flags;
1185 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1186 struct vcpu_info *v;
ee523ca1
JF
1187
1188 spin_lock_irqsave(&debug_lock, flags);
1189
cb52e6d9 1190 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1191
1192 for_each_online_cpu(i) {
cb52e6d9
IC
1193 int pending;
1194 v = per_cpu(xen_vcpu, i);
1195 pending = (get_irq_regs() && i == cpu)
1196 ? xen_irqs_disabled(get_irq_regs())
1197 : v->evtchn_upcall_mask;
1198 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1199 pending, v->evtchn_upcall_pending,
1200 (int)(sizeof(v->evtchn_pending_sel)*2),
1201 v->evtchn_pending_sel);
1202 }
1203 v = per_cpu(xen_vcpu, cpu);
1204
1205 printk("\npending:\n ");
1206 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1207 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1208 sh->evtchn_pending[i],
1209 i % 8 == 0 ? "\n " : " ");
1210 printk("\nglobal mask:\n ");
1211 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1212 printk("%0*lx%s",
1213 (int)(sizeof(sh->evtchn_mask[0])*2),
1214 sh->evtchn_mask[i],
1215 i % 8 == 0 ? "\n " : " ");
1216
1217 printk("\nglobally unmasked:\n ");
1218 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1219 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1220 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1221 i % 8 == 0 ? "\n " : " ");
1222
1223 printk("\nlocal cpu%d mask:\n ", cpu);
1224 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1225 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1226 cpu_evtchn[i],
1227 i % 8 == 0 ? "\n " : " ");
1228
1229 printk("\nlocally unmasked:\n ");
1230 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1231 unsigned long pending = sh->evtchn_pending[i]
1232 & ~sh->evtchn_mask[i]
1233 & cpu_evtchn[i];
1234 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1235 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1236 }
ee523ca1
JF
1237
1238 printk("\npending list:\n");
cb52e6d9 1239 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1240 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1241 int word_idx = i / BITS_PER_LONG;
1242 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1243 cpu_from_evtchn(i), i,
cb52e6d9
IC
1244 evtchn_to_irq[i],
1245 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1246 ? "" : " l2-clear",
1247 !sync_test_bit(i, sh->evtchn_mask)
1248 ? "" : " globally-masked",
1249 sync_test_bit(i, cpu_evtchn)
1250 ? "" : " locally-masked");
ee523ca1
JF
1251 }
1252 }
1253
1254 spin_unlock_irqrestore(&debug_lock, flags);
1255
1256 return IRQ_HANDLED;
1257}
1258
245b2e70 1259static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1260static DEFINE_PER_CPU(unsigned int, current_word_idx);
1261static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1262
ab7f863e
SR
1263/*
1264 * Mask out the i least significant bits of w
1265 */
1266#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1267
e46cdb66
JF
1268/*
1269 * Search the CPUs pending events bitmasks. For each one found, map
1270 * the event number to an irq, and feed it into do_IRQ() for
1271 * handling.
1272 *
1273 * Xen uses a two-level bitmap to speed searching. The first level is
1274 * a bitset of words which contain pending event bits. The second
1275 * level is a bitset of pending events themselves.
1276 */
38e20b07 1277static void __xen_evtchn_do_upcall(void)
e46cdb66 1278{
24b51c2f 1279 int start_word_idx, start_bit_idx;
ab7f863e 1280 int word_idx, bit_idx;
24b51c2f 1281 int i;
e46cdb66
JF
1282 int cpu = get_cpu();
1283 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1284 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1285 unsigned count;
e46cdb66 1286
229664be
JF
1287 do {
1288 unsigned long pending_words;
e46cdb66 1289
229664be 1290 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1291
b2e4ae69 1292 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1293 goto out;
e46cdb66 1294
e849c3e9
IY
1295#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1296 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1297 wmb();
e849c3e9 1298#endif
229664be 1299 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1300
24b51c2f
KF
1301 start_word_idx = __this_cpu_read(current_word_idx);
1302 start_bit_idx = __this_cpu_read(current_bit_idx);
1303
1304 word_idx = start_word_idx;
ab7f863e 1305
24b51c2f 1306 for (i = 0; pending_words != 0; i++) {
229664be 1307 unsigned long pending_bits;
ab7f863e 1308 unsigned long words;
229664be 1309
ab7f863e
SR
1310 words = MASK_LSBS(pending_words, word_idx);
1311
1312 /*
ada6814c 1313 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1314 */
1315 if (words == 0) {
ada6814c
KF
1316 word_idx = 0;
1317 bit_idx = 0;
ab7f863e
SR
1318 continue;
1319 }
1320 word_idx = __ffs(words);
229664be 1321
24b51c2f
KF
1322 pending_bits = active_evtchns(cpu, s, word_idx);
1323 bit_idx = 0; /* usually scan entire word from start */
1324 if (word_idx == start_word_idx) {
1325 /* We scan the starting word in two parts */
1326 if (i == 0)
1327 /* 1st time: start in the middle */
1328 bit_idx = start_bit_idx;
1329 else
1330 /* 2nd time: mask bits done already */
1331 bit_idx &= (1UL << start_bit_idx) - 1;
1332 }
1333
ab7f863e
SR
1334 do {
1335 unsigned long bits;
1336 int port, irq;
ca4dbc66 1337 struct irq_desc *desc;
229664be 1338
ab7f863e
SR
1339 bits = MASK_LSBS(pending_bits, bit_idx);
1340
1341 /* If we masked out all events, move on. */
ada6814c 1342 if (bits == 0)
ab7f863e 1343 break;
ab7f863e
SR
1344
1345 bit_idx = __ffs(bits);
1346
1347 /* Process port. */
1348 port = (word_idx * BITS_PER_LONG) + bit_idx;
1349 irq = evtchn_to_irq[port];
1350
ca4dbc66
EB
1351 if (irq != -1) {
1352 desc = irq_to_desc(irq);
1353 if (desc)
1354 generic_handle_irq_desc(irq, desc);
1355 }
ab7f863e 1356
ada6814c
KF
1357 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1358
1359 /* Next caller starts at last processed + 1 */
1360 __this_cpu_write(current_word_idx,
1361 bit_idx ? word_idx :
1362 (word_idx+1) % BITS_PER_LONG);
1363 __this_cpu_write(current_bit_idx, bit_idx);
1364 } while (bit_idx != 0);
ab7f863e 1365
24b51c2f
KF
1366 /* Scan start_l1i twice; all others once. */
1367 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1368 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1369
1370 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1371 }
e46cdb66 1372
229664be
JF
1373 BUG_ON(!irqs_disabled());
1374
780f36d8
CL
1375 count = __this_cpu_read(xed_nesting_count);
1376 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1377 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1378
1379out:
38e20b07
SY
1380
1381 put_cpu();
1382}
1383
1384void xen_evtchn_do_upcall(struct pt_regs *regs)
1385{
1386 struct pt_regs *old_regs = set_irq_regs(regs);
1387
1388 exit_idle();
1389 irq_enter();
1390
1391 __xen_evtchn_do_upcall();
1392
3445a8fd
JF
1393 irq_exit();
1394 set_irq_regs(old_regs);
38e20b07 1395}
3445a8fd 1396
38e20b07
SY
1397void xen_hvm_evtchn_do_upcall(void)
1398{
1399 __xen_evtchn_do_upcall();
e46cdb66 1400}
183d03cc 1401EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1402
eb1e305f
JF
1403/* Rebind a new event channel to an existing irq. */
1404void rebind_evtchn_irq(int evtchn, int irq)
1405{
d77bbd4d
JF
1406 struct irq_info *info = info_for_irq(irq);
1407
eb1e305f
JF
1408 /* Make sure the irq is masked, since the new event channel
1409 will also be masked. */
1410 disable_irq(irq);
1411
77365948 1412 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1413
1414 /* After resume the irq<->evtchn mappings are all cleared out */
1415 BUG_ON(evtchn_to_irq[evtchn] != -1);
1416 /* Expect irq to have been bound before,
d77bbd4d
JF
1417 so there should be a proper type */
1418 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1419
9158c358 1420 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1421
77365948 1422 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1423
1424 /* new event channels are always bound to cpu 0 */
0de26520 1425 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1426
1427 /* Unmask the event channel. */
1428 enable_irq(irq);
1429}
1430
e46cdb66 1431/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1432static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1433{
1434 struct evtchn_bind_vcpu bind_vcpu;
1435 int evtchn = evtchn_from_irq(irq);
1436
be49472f
IC
1437 if (!VALID_EVTCHN(evtchn))
1438 return -1;
1439
1440 /*
1441 * Events delivered via platform PCI interrupts are always
1442 * routed to vcpu 0 and hence cannot be rebound.
1443 */
1444 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1445 return -1;
e46cdb66
JF
1446
1447 /* Send future instances of this interrupt to other vcpu. */
1448 bind_vcpu.port = evtchn;
1449 bind_vcpu.vcpu = tcpu;
1450
1451 /*
1452 * If this fails, it usually just indicates that we're dealing with a
1453 * virq or IPI channel, which don't actually need to be rebound. Ignore
1454 * it, but don't do the xenlinux-level rebind in that case.
1455 */
1456 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1457 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1458
d5dedd45
YL
1459 return 0;
1460}
e46cdb66 1461
c9e265e0
TG
1462static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1463 bool force)
e46cdb66 1464{
0de26520 1465 unsigned tcpu = cpumask_first(dest);
d5dedd45 1466
c9e265e0 1467 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1468}
1469
642e0c88
IY
1470int resend_irq_on_evtchn(unsigned int irq)
1471{
1472 int masked, evtchn = evtchn_from_irq(irq);
1473 struct shared_info *s = HYPERVISOR_shared_info;
1474
1475 if (!VALID_EVTCHN(evtchn))
1476 return 1;
1477
1478 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1479 sync_set_bit(evtchn, s->evtchn_pending);
1480 if (!masked)
1481 unmask_evtchn(evtchn);
1482
1483 return 1;
1484}
1485
c9e265e0 1486static void enable_dynirq(struct irq_data *data)
e46cdb66 1487{
c9e265e0 1488 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1489
1490 if (VALID_EVTCHN(evtchn))
1491 unmask_evtchn(evtchn);
1492}
1493
c9e265e0 1494static void disable_dynirq(struct irq_data *data)
e46cdb66 1495{
c9e265e0 1496 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1497
1498 if (VALID_EVTCHN(evtchn))
1499 mask_evtchn(evtchn);
1500}
1501
c9e265e0 1502static void ack_dynirq(struct irq_data *data)
e46cdb66 1503{
c9e265e0 1504 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1505
7e186bdd 1506 irq_move_irq(data);
e46cdb66
JF
1507
1508 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1509 clear_evtchn(evtchn);
1510}
1511
1512static void mask_ack_dynirq(struct irq_data *data)
1513{
1514 disable_dynirq(data);
1515 ack_dynirq(data);
e46cdb66
JF
1516}
1517
c9e265e0 1518static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1519{
c9e265e0 1520 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1521 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1522 int ret = 0;
1523
1524 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1525 int masked;
1526
1527 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1528 sync_set_bit(evtchn, sh->evtchn_pending);
1529 if (!masked)
1530 unmask_evtchn(evtchn);
e46cdb66
JF
1531 ret = 1;
1532 }
1533
1534 return ret;
1535}
1536
0a85226f 1537static void restore_pirqs(void)
9a069c33
SS
1538{
1539 int pirq, rc, irq, gsi;
1540 struct physdev_map_pirq map_irq;
69c358ce 1541 struct irq_info *info;
9a069c33 1542
69c358ce
IC
1543 list_for_each_entry(info, &xen_irq_list_head, list) {
1544 if (info->type != IRQT_PIRQ)
9a069c33
SS
1545 continue;
1546
69c358ce
IC
1547 pirq = info->u.pirq.pirq;
1548 gsi = info->u.pirq.gsi;
1549 irq = info->irq;
1550
9a069c33
SS
1551 /* save/restore of PT devices doesn't work, so at this point the
1552 * only devices present are GSI based emulated devices */
9a069c33
SS
1553 if (!gsi)
1554 continue;
1555
1556 map_irq.domid = DOMID_SELF;
1557 map_irq.type = MAP_PIRQ_TYPE_GSI;
1558 map_irq.index = gsi;
1559 map_irq.pirq = pirq;
1560
1561 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1562 if (rc) {
1563 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1564 gsi, irq, pirq, rc);
9158c358 1565 xen_free_irq(irq);
9a069c33
SS
1566 continue;
1567 }
1568
1569 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1570
c9e265e0 1571 __startup_pirq(irq);
9a069c33
SS
1572 }
1573}
1574
0e91398f
JF
1575static void restore_cpu_virqs(unsigned int cpu)
1576{
1577 struct evtchn_bind_virq bind_virq;
1578 int virq, irq, evtchn;
1579
1580 for (virq = 0; virq < NR_VIRQS; virq++) {
1581 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1582 continue;
1583
ced40d0f 1584 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1585
1586 /* Get a new binding from Xen. */
1587 bind_virq.virq = virq;
1588 bind_virq.vcpu = cpu;
1589 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1590 &bind_virq) != 0)
1591 BUG();
1592 evtchn = bind_virq.port;
1593
1594 /* Record the new mapping. */
3d4cfa37 1595 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1596 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1597 }
1598}
1599
1600static void restore_cpu_ipis(unsigned int cpu)
1601{
1602 struct evtchn_bind_ipi bind_ipi;
1603 int ipi, irq, evtchn;
1604
1605 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1606 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1607 continue;
1608
ced40d0f 1609 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1610
1611 /* Get a new binding from Xen. */
1612 bind_ipi.vcpu = cpu;
1613 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1614 &bind_ipi) != 0)
1615 BUG();
1616 evtchn = bind_ipi.port;
1617
1618 /* Record the new mapping. */
3d4cfa37 1619 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1620 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1621 }
1622}
1623
2d9e1e2f
JF
1624/* Clear an irq's pending state, in preparation for polling on it */
1625void xen_clear_irq_pending(int irq)
1626{
1627 int evtchn = evtchn_from_irq(irq);
1628
1629 if (VALID_EVTCHN(evtchn))
1630 clear_evtchn(evtchn);
1631}
d9a8814f 1632EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1633void xen_set_irq_pending(int irq)
1634{
1635 int evtchn = evtchn_from_irq(irq);
1636
1637 if (VALID_EVTCHN(evtchn))
1638 set_evtchn(evtchn);
1639}
1640
1641bool xen_test_irq_pending(int irq)
1642{
1643 int evtchn = evtchn_from_irq(irq);
1644 bool ret = false;
1645
1646 if (VALID_EVTCHN(evtchn))
1647 ret = test_evtchn(evtchn);
1648
1649 return ret;
1650}
1651
d9a8814f
KRW
1652/* Poll waiting for an irq to become pending with timeout. In the usual case,
1653 * the irq will be disabled so it won't deliver an interrupt. */
1654void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1655{
1656 evtchn_port_t evtchn = evtchn_from_irq(irq);
1657
1658 if (VALID_EVTCHN(evtchn)) {
1659 struct sched_poll poll;
1660
1661 poll.nr_ports = 1;
d9a8814f 1662 poll.timeout = timeout;
ff3c5362 1663 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1664
1665 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1666 BUG();
1667 }
1668}
d9a8814f
KRW
1669EXPORT_SYMBOL(xen_poll_irq_timeout);
1670/* Poll waiting for an irq to become pending. In the usual case, the
1671 * irq will be disabled so it won't deliver an interrupt. */
1672void xen_poll_irq(int irq)
1673{
1674 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1675}
2d9e1e2f 1676
c7c2c3a2
KRW
1677/* Check whether the IRQ line is shared with other guests. */
1678int xen_test_irq_shared(int irq)
1679{
1680 struct irq_info *info = info_for_irq(irq);
1681 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1682
1683 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1684 return 0;
1685 return !(irq_status.flags & XENIRQSTAT_shared);
1686}
1687EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1688
0e91398f
JF
1689void xen_irq_resume(void)
1690{
6cb6537d
IC
1691 unsigned int cpu, evtchn;
1692 struct irq_info *info;
0e91398f
JF
1693
1694 init_evtchn_cpu_bindings();
1695
1696 /* New event-channel space is not 'live' yet. */
1697 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1698 mask_evtchn(evtchn);
1699
1700 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1701 list_for_each_entry(info, &xen_irq_list_head, list)
1702 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1703
1704 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1705 evtchn_to_irq[evtchn] = -1;
1706
1707 for_each_possible_cpu(cpu) {
1708 restore_cpu_virqs(cpu);
1709 restore_cpu_ipis(cpu);
1710 }
6903591f 1711
0a85226f 1712 restore_pirqs();
0e91398f
JF
1713}
1714
e46cdb66 1715static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1716 .name = "xen-dyn",
54a353a0 1717
c9e265e0
TG
1718 .irq_disable = disable_dynirq,
1719 .irq_mask = disable_dynirq,
1720 .irq_unmask = enable_dynirq,
54a353a0 1721
7e186bdd
SS
1722 .irq_ack = ack_dynirq,
1723 .irq_mask_ack = mask_ack_dynirq,
1724
c9e265e0
TG
1725 .irq_set_affinity = set_affinity_irq,
1726 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1727};
1728
d46a78b0 1729static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1730 .name = "xen-pirq",
d46a78b0 1731
c9e265e0
TG
1732 .irq_startup = startup_pirq,
1733 .irq_shutdown = shutdown_pirq,
c9e265e0 1734 .irq_enable = enable_pirq,
c9e265e0 1735 .irq_disable = disable_pirq,
d46a78b0 1736
7e186bdd
SS
1737 .irq_mask = disable_dynirq,
1738 .irq_unmask = enable_dynirq,
1739
1740 .irq_ack = eoi_pirq,
1741 .irq_eoi = eoi_pirq,
1742 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1743
c9e265e0 1744 .irq_set_affinity = set_affinity_irq,
d46a78b0 1745
c9e265e0 1746 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1747};
1748
aaca4964 1749static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1750 .name = "xen-percpu",
aaca4964 1751
c9e265e0
TG
1752 .irq_disable = disable_dynirq,
1753 .irq_mask = disable_dynirq,
1754 .irq_unmask = enable_dynirq,
aaca4964 1755
c9e265e0 1756 .irq_ack = ack_dynirq,
aaca4964
JF
1757};
1758
38e20b07
SY
1759int xen_set_callback_via(uint64_t via)
1760{
1761 struct xen_hvm_param a;
1762 a.domid = DOMID_SELF;
1763 a.index = HVM_PARAM_CALLBACK_IRQ;
1764 a.value = via;
1765 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1766}
1767EXPORT_SYMBOL_GPL(xen_set_callback_via);
1768
ca65f9fc 1769#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1770/* Vector callbacks are better than PCI interrupts to receive event
1771 * channel notifications because we can receive vector callbacks on any
1772 * vcpu and we don't need PCI support or APIC interactions. */
1773void xen_callback_vector(void)
1774{
1775 int rc;
1776 uint64_t callback_via;
1777 if (xen_have_vector_callback) {
1778 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1779 rc = xen_set_callback_via(callback_via);
1780 if (rc) {
1781 printk(KERN_ERR "Request for Xen HVM callback vector"
1782 " failed.\n");
1783 xen_have_vector_callback = 0;
1784 return;
1785 }
1786 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1787 "enabled\n");
1788 /* in the restore case the vector has already been allocated */
1789 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1790 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1791 }
1792}
ca65f9fc
SS
1793#else
1794void xen_callback_vector(void) {}
1795#endif
38e20b07 1796
e46cdb66
JF
1797void __init xen_init_IRQ(void)
1798{
9846ff10 1799 int i, rc;
c7a3589e 1800
b21ddbf5
JF
1801 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1802 GFP_KERNEL);
9d093e29 1803 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1804 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1805 evtchn_to_irq[i] = -1;
e46cdb66
JF
1806
1807 init_evtchn_cpu_bindings();
1808
1809 /* No event channels are 'live' right now. */
1810 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1811 mask_evtchn(i);
1812
9846ff10
SS
1813 pirq_needs_eoi = pirq_needs_eoi_flag;
1814
38e20b07
SY
1815 if (xen_hvm_domain()) {
1816 xen_callback_vector();
1817 native_init_IRQ();
3942b740
SS
1818 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1819 * __acpi_register_gsi can point at the right function */
1820 pci_xen_hvm_init();
38e20b07 1821 } else {
9846ff10
SS
1822 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1823
38e20b07 1824 irq_ctx_init(smp_processor_id());
38aa66fc 1825 if (xen_initial_domain())
a0ee0567 1826 pci_xen_initial_domain();
9846ff10
SS
1827
1828 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1829 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1830 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1831 if (rc != 0) {
1832 free_page((unsigned long) pirq_eoi_map);
1833 pirq_eoi_map = NULL;
1834 } else
1835 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1836 }
e46cdb66 1837}
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