Merge branch 'clk/mxs-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6...
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
e46cdb66 42#include <asm/xen/hypercall.h>
8d1b8753 43#include <asm/xen/hypervisor.h>
e46cdb66 44
38e20b07
SY
45#include <xen/xen.h>
46#include <xen/hvm.h>
e04d0d07 47#include <xen/xen-ops.h>
e46cdb66
JF
48#include <xen/events.h>
49#include <xen/interface/xen.h>
50#include <xen/interface/event_channel.h>
38e20b07
SY
51#include <xen/interface/hvm/hvm_op.h>
52#include <xen/interface/hvm/params.h>
e46cdb66 53
e46cdb66
JF
54/*
55 * This lock protects updates to the following mapping and reference-count
56 * arrays. The lock does not need to be acquired to read the mapping tables.
57 */
77365948 58static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 59
6cb6537d
IC
60static LIST_HEAD(xen_irq_list_head);
61
e46cdb66 62/* IRQ <-> VIRQ mapping. */
204fba4a 63static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 64
f87e4cac 65/* IRQ <-> IPI mapping */
204fba4a 66static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 67
ced40d0f
JF
68/* Interrupt types. */
69enum xen_irq_type {
d77bbd4d 70 IRQT_UNBOUND = 0,
f87e4cac
JF
71 IRQT_PIRQ,
72 IRQT_VIRQ,
73 IRQT_IPI,
74 IRQT_EVTCHN
75};
e46cdb66 76
ced40d0f
JF
77/*
78 * Packed IRQ information:
79 * type - enum xen_irq_type
80 * event channel - irq->event channel mapping
81 * cpu - cpu this event channel is bound to
82 * index - type-specific information:
42a1de56
SS
83 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
84 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
85 * VIRQ - virq number
86 * IPI - IPI vector
87 * EVTCHN -
88 */
088c05a8 89struct irq_info {
6cb6537d 90 struct list_head list;
420eb554 91 int refcnt;
ced40d0f 92 enum xen_irq_type type; /* type */
6cb6537d 93 unsigned irq;
ced40d0f
JF
94 unsigned short evtchn; /* event channel */
95 unsigned short cpu; /* cpu bound */
96
97 union {
98 unsigned short virq;
99 enum ipi_vector ipi;
100 struct {
7a043f11 101 unsigned short pirq;
ced40d0f 102 unsigned short gsi;
d46a78b0
JF
103 unsigned char vector;
104 unsigned char flags;
beafbdc1 105 uint16_t domid;
ced40d0f
JF
106 } pirq;
107 } u;
108};
d46a78b0 109#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 110#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 111
b21ddbf5 112static int *evtchn_to_irq;
9846ff10
SS
113static unsigned long *pirq_eoi_map;
114static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 115
cb60d114
IC
116static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
117 cpu_evtchn_mask);
e46cdb66 118
e46cdb66
JF
119/* Xen will never allocate port zero for any purpose. */
120#define VALID_EVTCHN(chn) ((chn) != 0)
121
e46cdb66 122static struct irq_chip xen_dynamic_chip;
aaca4964 123static struct irq_chip xen_percpu_chip;
d46a78b0 124static struct irq_chip xen_pirq_chip;
7e186bdd
SS
125static void enable_dynirq(struct irq_data *data);
126static void disable_dynirq(struct irq_data *data);
e46cdb66 127
9158c358
IC
128/* Get info for IRQ */
129static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 130{
c442b806 131 return irq_get_handler_data(irq);
ced40d0f
JF
132}
133
9158c358
IC
134/* Constructors for packed IRQ information. */
135static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 136 unsigned irq,
9158c358
IC
137 enum xen_irq_type type,
138 unsigned short evtchn,
139 unsigned short cpu)
ced40d0f 140{
9158c358
IC
141
142 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
143
144 info->type = type;
6cb6537d 145 info->irq = irq;
9158c358
IC
146 info->evtchn = evtchn;
147 info->cpu = cpu;
3d4cfa37
IC
148
149 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
150}
151
9158c358
IC
152static void xen_irq_info_evtchn_init(unsigned irq,
153 unsigned short evtchn)
ced40d0f 154{
9158c358
IC
155 struct irq_info *info = info_for_irq(irq);
156
3d4cfa37 157 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
158}
159
3d4cfa37
IC
160static void xen_irq_info_ipi_init(unsigned cpu,
161 unsigned irq,
9158c358
IC
162 unsigned short evtchn,
163 enum ipi_vector ipi)
e46cdb66 164{
9158c358
IC
165 struct irq_info *info = info_for_irq(irq);
166
3d4cfa37 167 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
168
169 info->u.ipi = ipi;
3d4cfa37
IC
170
171 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
172}
173
3d4cfa37
IC
174static void xen_irq_info_virq_init(unsigned cpu,
175 unsigned irq,
9158c358
IC
176 unsigned short evtchn,
177 unsigned short virq)
ced40d0f 178{
9158c358
IC
179 struct irq_info *info = info_for_irq(irq);
180
3d4cfa37 181 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
182
183 info->u.virq = virq;
3d4cfa37
IC
184
185 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
186}
187
9158c358
IC
188static void xen_irq_info_pirq_init(unsigned irq,
189 unsigned short evtchn,
190 unsigned short pirq,
191 unsigned short gsi,
192 unsigned short vector,
beafbdc1 193 uint16_t domid,
9158c358 194 unsigned char flags)
ced40d0f 195{
9158c358
IC
196 struct irq_info *info = info_for_irq(irq);
197
3d4cfa37 198 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
199
200 info->u.pirq.pirq = pirq;
201 info->u.pirq.gsi = gsi;
202 info->u.pirq.vector = vector;
beafbdc1 203 info->u.pirq.domid = domid;
9158c358 204 info->u.pirq.flags = flags;
e46cdb66
JF
205}
206
207/*
208 * Accessors for packed IRQ information.
209 */
ced40d0f 210static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 211{
110e7c7e
JJ
212 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
213 return 0;
214
ced40d0f 215 return info_for_irq(irq)->evtchn;
e46cdb66
JF
216}
217
d4c04536
IC
218unsigned irq_from_evtchn(unsigned int evtchn)
219{
220 return evtchn_to_irq[evtchn];
221}
222EXPORT_SYMBOL_GPL(irq_from_evtchn);
223
ced40d0f 224static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 225{
ced40d0f
JF
226 struct irq_info *info = info_for_irq(irq);
227
228 BUG_ON(info == NULL);
229 BUG_ON(info->type != IRQT_IPI);
230
231 return info->u.ipi;
232}
233
234static unsigned virq_from_irq(unsigned irq)
235{
236 struct irq_info *info = info_for_irq(irq);
237
238 BUG_ON(info == NULL);
239 BUG_ON(info->type != IRQT_VIRQ);
240
241 return info->u.virq;
242}
243
7a043f11
SS
244static unsigned pirq_from_irq(unsigned irq)
245{
246 struct irq_info *info = info_for_irq(irq);
247
248 BUG_ON(info == NULL);
249 BUG_ON(info->type != IRQT_PIRQ);
250
251 return info->u.pirq.pirq;
252}
253
ced40d0f
JF
254static enum xen_irq_type type_from_irq(unsigned irq)
255{
256 return info_for_irq(irq)->type;
257}
258
259static unsigned cpu_from_irq(unsigned irq)
260{
261 return info_for_irq(irq)->cpu;
262}
263
264static unsigned int cpu_from_evtchn(unsigned int evtchn)
265{
266 int irq = evtchn_to_irq[evtchn];
267 unsigned ret = 0;
268
269 if (irq != -1)
270 ret = cpu_from_irq(irq);
271
272 return ret;
e46cdb66
JF
273}
274
9846ff10 275static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 276{
521394e4 277 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 278}
d46a78b0 279
9846ff10
SS
280static bool pirq_needs_eoi_flag(unsigned irq)
281{
282 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
283 BUG_ON(info->type != IRQT_PIRQ);
284
285 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
286}
287
e46cdb66
JF
288static inline unsigned long active_evtchns(unsigned int cpu,
289 struct shared_info *sh,
290 unsigned int idx)
291{
088c05a8 292 return sh->evtchn_pending[idx] &
cb60d114 293 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 294 ~sh->evtchn_mask[idx];
e46cdb66
JF
295}
296
297static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
298{
299 int irq = evtchn_to_irq[chn];
300
301 BUG_ON(irq == -1);
302#ifdef CONFIG_SMP
c9e265e0 303 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
304#endif
305
cb60d114
IC
306 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
307 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 308
ca62ce8c 309 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
310}
311
312static void init_evtchn_cpu_bindings(void)
313{
1c6969ec 314 int i;
e46cdb66 315#ifdef CONFIG_SMP
6cb6537d 316 struct irq_info *info;
10e58084 317
e46cdb66 318 /* By default all event channels notify CPU#0. */
6cb6537d
IC
319 list_for_each_entry(info, &xen_irq_list_head, list) {
320 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 321 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 322 }
e46cdb66
JF
323#endif
324
1c6969ec 325 for_each_possible_cpu(i)
cb60d114
IC
326 memset(per_cpu(cpu_evtchn_mask, i),
327 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
328}
329
e46cdb66
JF
330static inline void clear_evtchn(int port)
331{
332 struct shared_info *s = HYPERVISOR_shared_info;
333 sync_clear_bit(port, &s->evtchn_pending[0]);
334}
335
336static inline void set_evtchn(int port)
337{
338 struct shared_info *s = HYPERVISOR_shared_info;
339 sync_set_bit(port, &s->evtchn_pending[0]);
340}
341
168d2f46
JF
342static inline int test_evtchn(int port)
343{
344 struct shared_info *s = HYPERVISOR_shared_info;
345 return sync_test_bit(port, &s->evtchn_pending[0]);
346}
347
e46cdb66
JF
348
349/**
350 * notify_remote_via_irq - send event to remote end of event channel via irq
351 * @irq: irq of event channel to send event to
352 *
353 * Unlike notify_remote_via_evtchn(), this is safe to use across
354 * save/restore. Notifications on a broken connection are silently
355 * dropped.
356 */
357void notify_remote_via_irq(int irq)
358{
359 int evtchn = evtchn_from_irq(irq);
360
361 if (VALID_EVTCHN(evtchn))
362 notify_remote_via_evtchn(evtchn);
363}
364EXPORT_SYMBOL_GPL(notify_remote_via_irq);
365
366static void mask_evtchn(int port)
367{
368 struct shared_info *s = HYPERVISOR_shared_info;
369 sync_set_bit(port, &s->evtchn_mask[0]);
370}
371
372static void unmask_evtchn(int port)
373{
374 struct shared_info *s = HYPERVISOR_shared_info;
375 unsigned int cpu = get_cpu();
376
377 BUG_ON(!irqs_disabled());
378
379 /* Slow path (hypercall) if this is a non-local port. */
380 if (unlikely(cpu != cpu_from_evtchn(port))) {
381 struct evtchn_unmask unmask = { .port = port };
382 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
383 } else {
780f36d8 384 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
385
386 sync_clear_bit(port, &s->evtchn_mask[0]);
387
388 /*
389 * The following is basically the equivalent of
390 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
391 * the interrupt edge' if the channel is masked.
392 */
393 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
394 !sync_test_and_set_bit(port / BITS_PER_LONG,
395 &vcpu_info->evtchn_pending_sel))
396 vcpu_info->evtchn_upcall_pending = 1;
397 }
398
399 put_cpu();
400}
401
6cb6537d
IC
402static void xen_irq_init(unsigned irq)
403{
404 struct irq_info *info;
b5328cd1 405#ifdef CONFIG_SMP
6cb6537d
IC
406 struct irq_desc *desc = irq_to_desc(irq);
407
408 /* By default all event channels notify CPU#0. */
409 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 410#endif
6cb6537d 411
ca62ce8c
IC
412 info = kzalloc(sizeof(*info), GFP_KERNEL);
413 if (info == NULL)
414 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
415
416 info->type = IRQT_UNBOUND;
420eb554 417 info->refcnt = -1;
6cb6537d 418
c442b806 419 irq_set_handler_data(irq, info);
ca62ce8c 420
6cb6537d
IC
421 list_add_tail(&info->list, &xen_irq_list_head);
422}
423
7bee9768 424static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 425{
89911501
IC
426 int first = 0;
427 int irq;
0794bfc7
KRW
428
429#ifdef CONFIG_X86_IO_APIC
89911501
IC
430 /*
431 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 432 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
433 * e.g. those corresponding to event channels or MSIs
434 * etc. from the range above those "real" GSIs to avoid
435 * collisions.
436 */
437 if (xen_initial_domain() || xen_hvm_domain())
438 first = get_nr_irqs_gsi();
0794bfc7
KRW
439#endif
440
89911501 441 irq = irq_alloc_desc_from(first, -1);
3a69e916 442
e6599225
KRW
443 if (irq >= 0)
444 xen_irq_init(irq);
ced40d0f 445
e46cdb66 446 return irq;
d46a78b0
JF
447}
448
7bee9768 449static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
450{
451 int irq;
452
89911501
IC
453 /*
454 * A PV guest has no concept of a GSI (since it has no ACPI
455 * nor access to/knowledge of the physical APICs). Therefore
456 * all IRQs are dynamically allocated from the entire IRQ
457 * space.
458 */
459 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
460 return xen_allocate_irq_dynamic();
461
462 /* Legacy IRQ descriptors are already allocated by the arch. */
463 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
464 irq = gsi;
465 else
466 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 467
6cb6537d 468 xen_irq_init(irq);
c9df1ce5
IC
469
470 return irq;
471}
472
473static void xen_free_irq(unsigned irq)
474{
c442b806 475 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
476
477 list_del(&info->list);
9158c358 478
c442b806 479 irq_set_handler_data(irq, NULL);
ca62ce8c 480
420eb554
DDG
481 WARN_ON(info->refcnt > 0);
482
ca62ce8c
IC
483 kfree(info);
484
72146104
IC
485 /* Legacy IRQ descriptors are managed by the arch. */
486 if (irq < NR_IRQS_LEGACY)
487 return;
488
c9df1ce5
IC
489 irq_free_desc(irq);
490}
491
d46a78b0
JF
492static void pirq_query_unmask(int irq)
493{
494 struct physdev_irq_status_query irq_status;
495 struct irq_info *info = info_for_irq(irq);
496
497 BUG_ON(info->type != IRQT_PIRQ);
498
7a043f11 499 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
500 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
501 irq_status.flags = 0;
502
503 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
504 if (irq_status.flags & XENIRQSTAT_needs_eoi)
505 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
506}
507
508static bool probing_irq(int irq)
509{
510 struct irq_desc *desc = irq_to_desc(irq);
511
512 return desc && desc->action == NULL;
513}
514
7e186bdd
SS
515static void eoi_pirq(struct irq_data *data)
516{
517 int evtchn = evtchn_from_irq(data->irq);
518 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
519 int rc = 0;
520
521 irq_move_irq(data);
522
523 if (VALID_EVTCHN(evtchn))
524 clear_evtchn(evtchn);
525
526 if (pirq_needs_eoi(data->irq)) {
527 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
528 WARN_ON(rc);
529 }
530}
531
532static void mask_ack_pirq(struct irq_data *data)
533{
534 disable_dynirq(data);
535 eoi_pirq(data);
536}
537
c9e265e0 538static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
539{
540 struct evtchn_bind_pirq bind_pirq;
541 struct irq_info *info = info_for_irq(irq);
542 int evtchn = evtchn_from_irq(irq);
15ebbb82 543 int rc;
d46a78b0
JF
544
545 BUG_ON(info->type != IRQT_PIRQ);
546
547 if (VALID_EVTCHN(evtchn))
548 goto out;
549
7a043f11 550 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 551 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
552 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
553 BIND_PIRQ__WILL_SHARE : 0;
554 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
555 if (rc != 0) {
d46a78b0
JF
556 if (!probing_irq(irq))
557 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
558 irq);
559 return 0;
560 }
561 evtchn = bind_pirq.port;
562
563 pirq_query_unmask(irq);
564
565 evtchn_to_irq[evtchn] = irq;
566 bind_evtchn_to_cpu(evtchn, 0);
567 info->evtchn = evtchn;
568
569out:
570 unmask_evtchn(evtchn);
7e186bdd 571 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
572
573 return 0;
574}
575
c9e265e0
TG
576static unsigned int startup_pirq(struct irq_data *data)
577{
578 return __startup_pirq(data->irq);
579}
580
581static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
582{
583 struct evtchn_close close;
c9e265e0 584 unsigned int irq = data->irq;
d46a78b0
JF
585 struct irq_info *info = info_for_irq(irq);
586 int evtchn = evtchn_from_irq(irq);
587
588 BUG_ON(info->type != IRQT_PIRQ);
589
590 if (!VALID_EVTCHN(evtchn))
591 return;
592
593 mask_evtchn(evtchn);
594
595 close.port = evtchn;
596 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
597 BUG();
598
599 bind_evtchn_to_cpu(evtchn, 0);
600 evtchn_to_irq[evtchn] = -1;
601 info->evtchn = 0;
602}
603
c9e265e0 604static void enable_pirq(struct irq_data *data)
d46a78b0 605{
c9e265e0 606 startup_pirq(data);
d46a78b0
JF
607}
608
c9e265e0 609static void disable_pirq(struct irq_data *data)
d46a78b0 610{
7e186bdd 611 disable_dynirq(data);
d46a78b0
JF
612}
613
68c2c39a 614int xen_irq_from_gsi(unsigned gsi)
d46a78b0 615{
6cb6537d 616 struct irq_info *info;
d46a78b0 617
6cb6537d
IC
618 list_for_each_entry(info, &xen_irq_list_head, list) {
619 if (info->type != IRQT_PIRQ)
d46a78b0
JF
620 continue;
621
6cb6537d
IC
622 if (info->u.pirq.gsi == gsi)
623 return info->irq;
d46a78b0
JF
624 }
625
626 return -1;
627}
68c2c39a 628EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 629
653378ac
IC
630/*
631 * Do not make any assumptions regarding the relationship between the
632 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
633 *
634 * Note: We don't assign an event channel until the irq actually started
635 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
636 *
637 * Shareable implies level triggered, not shareable implies edge
638 * triggered here.
d46a78b0 639 */
f4d0635b
IC
640int xen_bind_pirq_gsi_to_irq(unsigned gsi,
641 unsigned pirq, int shareable, char *name)
d46a78b0 642{
a0e18116 643 int irq = -1;
d46a78b0
JF
644 struct physdev_irq irq_op;
645
77365948 646 mutex_lock(&irq_mapping_update_lock);
d46a78b0 647
68c2c39a 648 irq = xen_irq_from_gsi(gsi);
d46a78b0 649 if (irq != -1) {
7a043f11 650 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 651 irq, gsi);
420eb554 652 goto out;
d46a78b0
JF
653 }
654
c9df1ce5 655 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
656 if (irq < 0)
657 goto out;
d46a78b0 658
d46a78b0 659 irq_op.irq = irq;
b5401a96
AN
660 irq_op.vector = 0;
661
662 /* Only the privileged domain can do this. For non-priv, the pcifront
663 * driver provides a PCI bus that does the call to do exactly
664 * this in the priv domain. */
665 if (xen_initial_domain() &&
666 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 667 xen_free_irq(irq);
d46a78b0
JF
668 irq = -ENOSPC;
669 goto out;
670 }
671
beafbdc1 672 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 673 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 674
7e186bdd
SS
675 pirq_query_unmask(irq);
676 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
677 * type of interrupt: if the interrupt is an edge triggered
678 * interrupt we use handle_edge_irq.
7e186bdd 679 *
e5ac0bda
SS
680 * On the other hand if the interrupt is level triggered we use
681 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 682 * interrupts.
e5ac0bda 683 *
7e186bdd
SS
684 * Depending on the Xen version, pirq_needs_eoi might return true
685 * not only for level triggered interrupts but for edge triggered
686 * interrupts too. In any case Xen always honors the eoi mechanism,
687 * not injecting any more pirqs of the same kind if the first one
688 * hasn't received an eoi yet. Therefore using the fasteoi handler
689 * is the right choice either way.
690 */
e5ac0bda 691 if (shareable)
7e186bdd
SS
692 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
693 handle_fasteoi_irq, name);
694 else
695 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
696 handle_edge_irq, name);
697
d46a78b0 698out:
77365948 699 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
700
701 return irq;
702}
703
f731e3ef 704#ifdef CONFIG_PCI_MSI
bf480d95 705int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 706{
5cad61a6 707 int rc;
cbf6aa89 708 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 709
bf480d95 710 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 711 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 712
5cad61a6
IC
713 WARN_ONCE(rc == -ENOSYS,
714 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
715
716 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
717}
718
bf480d95 719int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
720 int pirq, int vector, const char *name,
721 domid_t domid)
809f9267 722{
bf480d95 723 int irq, ret;
4b41df7f 724
77365948 725 mutex_lock(&irq_mapping_update_lock);
809f9267 726
4b41df7f 727 irq = xen_allocate_irq_dynamic();
e6599225 728 if (irq < 0)
bb5d079a 729 goto out;
809f9267 730
7e186bdd
SS
731 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
732 name);
809f9267 733
beafbdc1 734 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 735 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
736 if (ret < 0)
737 goto error_irq;
809f9267 738out:
77365948 739 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 740 return irq;
bf480d95 741error_irq:
77365948 742 mutex_unlock(&irq_mapping_update_lock);
bf480d95 743 xen_free_irq(irq);
e6599225 744 return ret;
809f9267 745}
f731e3ef
QH
746#endif
747
b5401a96
AN
748int xen_destroy_irq(int irq)
749{
750 struct irq_desc *desc;
38aa66fc
JF
751 struct physdev_unmap_pirq unmap_irq;
752 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
753 int rc = -ENOENT;
754
77365948 755 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
756
757 desc = irq_to_desc(irq);
758 if (!desc)
759 goto out;
760
38aa66fc 761 if (xen_initial_domain()) {
12334715 762 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 763 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 764 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
765 /* If another domain quits without making the pci_disable_msix
766 * call, the Xen hypervisor takes care of freeing the PIRQs
767 * (free_domain_pirqs).
768 */
769 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
770 printk(KERN_INFO "domain %d does not have %d anymore\n",
771 info->u.pirq.domid, info->u.pirq.pirq);
772 else if (rc) {
38aa66fc
JF
773 printk(KERN_WARNING "unmap irq failed %d\n", rc);
774 goto out;
775 }
776 }
b5401a96 777
c9df1ce5 778 xen_free_irq(irq);
b5401a96
AN
779
780out:
77365948 781 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
782 return rc;
783}
784
af42b8d1 785int xen_irq_from_pirq(unsigned pirq)
d46a78b0 786{
69c358ce 787 int irq;
d46a78b0 788
69c358ce 789 struct irq_info *info;
e46cdb66 790
77365948 791 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
792
793 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 794 if (info->type != IRQT_PIRQ)
69c358ce
IC
795 continue;
796 irq = info->irq;
797 if (info->u.pirq.pirq == pirq)
798 goto out;
799 }
800 irq = -1;
801out:
77365948 802 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
803
804 return irq;
af42b8d1
SS
805}
806
e6197acc
KRW
807
808int xen_pirq_from_irq(unsigned irq)
809{
810 return pirq_from_irq(irq);
811}
812EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 813int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
814{
815 int irq;
816
77365948 817 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
818
819 irq = evtchn_to_irq[evtchn];
820
821 if (irq == -1) {
c9df1ce5 822 irq = xen_allocate_irq_dynamic();
7bee9768
IC
823 if (irq == -1)
824 goto out;
e46cdb66 825
c442b806 826 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 827 handle_edge_irq, "event");
e46cdb66 828
9158c358 829 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
830 } else {
831 struct irq_info *info = info_for_irq(irq);
832 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
833 }
834
7bee9768 835out:
77365948 836 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
837
838 return irq;
839}
b536b4b9 840EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 841
f87e4cac
JF
842static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
843{
844 struct evtchn_bind_ipi bind_ipi;
845 int evtchn, irq;
846
77365948 847 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
848
849 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 850
f87e4cac 851 if (irq == -1) {
c9df1ce5 852 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
853 if (irq < 0)
854 goto out;
855
c442b806 856 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 857 handle_percpu_irq, "ipi");
f87e4cac
JF
858
859 bind_ipi.vcpu = cpu;
860 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
861 &bind_ipi) != 0)
862 BUG();
863 evtchn = bind_ipi.port;
864
3d4cfa37 865 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
866
867 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
868 } else {
869 struct irq_info *info = info_for_irq(irq);
870 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
871 }
872
f87e4cac 873 out:
77365948 874 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
875 return irq;
876}
877
2e820f58
IC
878static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
879 unsigned int remote_port)
880{
881 struct evtchn_bind_interdomain bind_interdomain;
882 int err;
883
884 bind_interdomain.remote_dom = remote_domain;
885 bind_interdomain.remote_port = remote_port;
886
887 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
888 &bind_interdomain);
889
890 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
891}
892
62cc5fc7
OH
893static int find_virq(unsigned int virq, unsigned int cpu)
894{
895 struct evtchn_status status;
896 int port, rc = -ENOENT;
897
898 memset(&status, 0, sizeof(status));
899 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
900 status.dom = DOMID_SELF;
901 status.port = port;
902 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
903 if (rc < 0)
904 continue;
905 if (status.status != EVTCHNSTAT_virq)
906 continue;
907 if (status.u.virq == virq && status.vcpu == cpu) {
908 rc = port;
909 break;
910 }
911 }
912 return rc;
913}
f87e4cac 914
4fe7d5a7 915int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
916{
917 struct evtchn_bind_virq bind_virq;
62cc5fc7 918 int evtchn, irq, ret;
e46cdb66 919
77365948 920 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
921
922 irq = per_cpu(virq_to_irq, cpu)[virq];
923
924 if (irq == -1) {
c9df1ce5 925 irq = xen_allocate_irq_dynamic();
7bee9768
IC
926 if (irq == -1)
927 goto out;
a52521f1 928
c442b806 929 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
930 handle_percpu_irq, "virq");
931
e46cdb66
JF
932 bind_virq.virq = virq;
933 bind_virq.vcpu = cpu;
62cc5fc7
OH
934 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
935 &bind_virq);
936 if (ret == 0)
937 evtchn = bind_virq.port;
938 else {
939 if (ret == -EEXIST)
940 ret = find_virq(virq, cpu);
941 BUG_ON(ret < 0);
942 evtchn = ret;
943 }
e46cdb66 944
3d4cfa37 945 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
946
947 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
948 } else {
949 struct irq_info *info = info_for_irq(irq);
950 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
951 }
952
7bee9768 953out:
77365948 954 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
955
956 return irq;
957}
958
959static void unbind_from_irq(unsigned int irq)
960{
961 struct evtchn_close close;
962 int evtchn = evtchn_from_irq(irq);
420eb554 963 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 964
77365948 965 mutex_lock(&irq_mapping_update_lock);
e46cdb66 966
420eb554
DDG
967 if (info->refcnt > 0) {
968 info->refcnt--;
969 if (info->refcnt != 0)
970 goto done;
971 }
972
d77bbd4d 973 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
974 close.port = evtchn;
975 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
976 BUG();
977
978 switch (type_from_irq(irq)) {
979 case IRQT_VIRQ:
980 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 981 [virq_from_irq(irq)] = -1;
e46cdb66 982 break;
d68d82af
AN
983 case IRQT_IPI:
984 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 985 [ipi_from_irq(irq)] = -1;
d68d82af 986 break;
e46cdb66
JF
987 default:
988 break;
989 }
990
991 /* Closed ports are implicitly re-bound to VCPU0. */
992 bind_evtchn_to_cpu(evtchn, 0);
993
994 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
995 }
996
ca62ce8c 997 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 998
9158c358 999 xen_free_irq(irq);
e46cdb66 1000
420eb554 1001 done:
77365948 1002 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1003}
1004
1005int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1006 irq_handler_t handler,
e46cdb66
JF
1007 unsigned long irqflags,
1008 const char *devname, void *dev_id)
1009{
361ae8cb 1010 int irq, retval;
e46cdb66
JF
1011
1012 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1013 if (irq < 0)
1014 return irq;
e46cdb66
JF
1015 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1016 if (retval != 0) {
1017 unbind_from_irq(irq);
1018 return retval;
1019 }
1020
1021 return irq;
1022}
1023EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1024
2e820f58
IC
1025int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1026 unsigned int remote_port,
1027 irq_handler_t handler,
1028 unsigned long irqflags,
1029 const char *devname,
1030 void *dev_id)
1031{
1032 int irq, retval;
1033
1034 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1035 if (irq < 0)
1036 return irq;
1037
1038 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1039 if (retval != 0) {
1040 unbind_from_irq(irq);
1041 return retval;
1042 }
1043
1044 return irq;
1045}
1046EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1047
e46cdb66 1048int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1049 irq_handler_t handler,
e46cdb66
JF
1050 unsigned long irqflags, const char *devname, void *dev_id)
1051{
361ae8cb 1052 int irq, retval;
e46cdb66
JF
1053
1054 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1055 if (irq < 0)
1056 return irq;
e46cdb66
JF
1057 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1058 if (retval != 0) {
1059 unbind_from_irq(irq);
1060 return retval;
1061 }
1062
1063 return irq;
1064}
1065EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1066
f87e4cac
JF
1067int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1068 unsigned int cpu,
1069 irq_handler_t handler,
1070 unsigned long irqflags,
1071 const char *devname,
1072 void *dev_id)
1073{
1074 int irq, retval;
1075
1076 irq = bind_ipi_to_irq(ipi, cpu);
1077 if (irq < 0)
1078 return irq;
1079
9bab0b7f 1080 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1081 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1082 if (retval != 0) {
1083 unbind_from_irq(irq);
1084 return retval;
1085 }
1086
1087 return irq;
1088}
1089
e46cdb66
JF
1090void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1091{
1092 free_irq(irq, dev_id);
1093 unbind_from_irq(irq);
1094}
1095EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1096
420eb554
DDG
1097int evtchn_make_refcounted(unsigned int evtchn)
1098{
1099 int irq = evtchn_to_irq[evtchn];
1100 struct irq_info *info;
1101
1102 if (irq == -1)
1103 return -ENOENT;
1104
1105 info = irq_get_handler_data(irq);
1106
1107 if (!info)
1108 return -ENOENT;
1109
1110 WARN_ON(info->refcnt != -1);
1111
1112 info->refcnt = 1;
1113
1114 return 0;
1115}
1116EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1117
1118int evtchn_get(unsigned int evtchn)
1119{
1120 int irq;
1121 struct irq_info *info;
1122 int err = -ENOENT;
1123
c3b3f16d
DDG
1124 if (evtchn >= NR_EVENT_CHANNELS)
1125 return -EINVAL;
1126
420eb554
DDG
1127 mutex_lock(&irq_mapping_update_lock);
1128
1129 irq = evtchn_to_irq[evtchn];
1130 if (irq == -1)
1131 goto done;
1132
1133 info = irq_get_handler_data(irq);
1134
1135 if (!info)
1136 goto done;
1137
1138 err = -EINVAL;
1139 if (info->refcnt <= 0)
1140 goto done;
1141
1142 info->refcnt++;
1143 err = 0;
1144 done:
1145 mutex_unlock(&irq_mapping_update_lock);
1146
1147 return err;
1148}
1149EXPORT_SYMBOL_GPL(evtchn_get);
1150
1151void evtchn_put(unsigned int evtchn)
1152{
1153 int irq = evtchn_to_irq[evtchn];
1154 if (WARN_ON(irq == -1))
1155 return;
1156 unbind_from_irq(irq);
1157}
1158EXPORT_SYMBOL_GPL(evtchn_put);
1159
f87e4cac
JF
1160void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1161{
1162 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1163 BUG_ON(irq < 0);
1164 notify_remote_via_irq(irq);
1165}
1166
ee523ca1
JF
1167irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1168{
1169 struct shared_info *sh = HYPERVISOR_shared_info;
1170 int cpu = smp_processor_id();
cb60d114 1171 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1172 int i;
1173 unsigned long flags;
1174 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1175 struct vcpu_info *v;
ee523ca1
JF
1176
1177 spin_lock_irqsave(&debug_lock, flags);
1178
cb52e6d9 1179 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1180
1181 for_each_online_cpu(i) {
cb52e6d9
IC
1182 int pending;
1183 v = per_cpu(xen_vcpu, i);
1184 pending = (get_irq_regs() && i == cpu)
1185 ? xen_irqs_disabled(get_irq_regs())
1186 : v->evtchn_upcall_mask;
1187 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1188 pending, v->evtchn_upcall_pending,
1189 (int)(sizeof(v->evtchn_pending_sel)*2),
1190 v->evtchn_pending_sel);
1191 }
1192 v = per_cpu(xen_vcpu, cpu);
1193
1194 printk("\npending:\n ");
1195 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1196 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1197 sh->evtchn_pending[i],
1198 i % 8 == 0 ? "\n " : " ");
1199 printk("\nglobal mask:\n ");
1200 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1201 printk("%0*lx%s",
1202 (int)(sizeof(sh->evtchn_mask[0])*2),
1203 sh->evtchn_mask[i],
1204 i % 8 == 0 ? "\n " : " ");
1205
1206 printk("\nglobally unmasked:\n ");
1207 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1208 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1209 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1210 i % 8 == 0 ? "\n " : " ");
1211
1212 printk("\nlocal cpu%d mask:\n ", cpu);
1213 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1214 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1215 cpu_evtchn[i],
1216 i % 8 == 0 ? "\n " : " ");
1217
1218 printk("\nlocally unmasked:\n ");
1219 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1220 unsigned long pending = sh->evtchn_pending[i]
1221 & ~sh->evtchn_mask[i]
1222 & cpu_evtchn[i];
1223 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1224 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1225 }
ee523ca1
JF
1226
1227 printk("\npending list:\n");
cb52e6d9 1228 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1229 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1230 int word_idx = i / BITS_PER_LONG;
1231 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1232 cpu_from_evtchn(i), i,
cb52e6d9
IC
1233 evtchn_to_irq[i],
1234 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1235 ? "" : " l2-clear",
1236 !sync_test_bit(i, sh->evtchn_mask)
1237 ? "" : " globally-masked",
1238 sync_test_bit(i, cpu_evtchn)
1239 ? "" : " locally-masked");
ee523ca1
JF
1240 }
1241 }
1242
1243 spin_unlock_irqrestore(&debug_lock, flags);
1244
1245 return IRQ_HANDLED;
1246}
1247
245b2e70 1248static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1249static DEFINE_PER_CPU(unsigned int, current_word_idx);
1250static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1251
ab7f863e
SR
1252/*
1253 * Mask out the i least significant bits of w
1254 */
1255#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1256
e46cdb66
JF
1257/*
1258 * Search the CPUs pending events bitmasks. For each one found, map
1259 * the event number to an irq, and feed it into do_IRQ() for
1260 * handling.
1261 *
1262 * Xen uses a two-level bitmap to speed searching. The first level is
1263 * a bitset of words which contain pending event bits. The second
1264 * level is a bitset of pending events themselves.
1265 */
38e20b07 1266static void __xen_evtchn_do_upcall(void)
e46cdb66 1267{
24b51c2f 1268 int start_word_idx, start_bit_idx;
ab7f863e 1269 int word_idx, bit_idx;
24b51c2f 1270 int i;
e46cdb66
JF
1271 int cpu = get_cpu();
1272 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1273 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1274 unsigned count;
e46cdb66 1275
229664be
JF
1276 do {
1277 unsigned long pending_words;
e46cdb66 1278
229664be 1279 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1280
b2e4ae69 1281 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1282 goto out;
e46cdb66 1283
e849c3e9
IY
1284#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1285 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1286 wmb();
e849c3e9 1287#endif
229664be 1288 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1289
24b51c2f
KF
1290 start_word_idx = __this_cpu_read(current_word_idx);
1291 start_bit_idx = __this_cpu_read(current_bit_idx);
1292
1293 word_idx = start_word_idx;
ab7f863e 1294
24b51c2f 1295 for (i = 0; pending_words != 0; i++) {
229664be 1296 unsigned long pending_bits;
ab7f863e 1297 unsigned long words;
229664be 1298
ab7f863e
SR
1299 words = MASK_LSBS(pending_words, word_idx);
1300
1301 /*
ada6814c 1302 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1303 */
1304 if (words == 0) {
ada6814c
KF
1305 word_idx = 0;
1306 bit_idx = 0;
ab7f863e
SR
1307 continue;
1308 }
1309 word_idx = __ffs(words);
229664be 1310
24b51c2f
KF
1311 pending_bits = active_evtchns(cpu, s, word_idx);
1312 bit_idx = 0; /* usually scan entire word from start */
1313 if (word_idx == start_word_idx) {
1314 /* We scan the starting word in two parts */
1315 if (i == 0)
1316 /* 1st time: start in the middle */
1317 bit_idx = start_bit_idx;
1318 else
1319 /* 2nd time: mask bits done already */
1320 bit_idx &= (1UL << start_bit_idx) - 1;
1321 }
1322
ab7f863e
SR
1323 do {
1324 unsigned long bits;
1325 int port, irq;
ca4dbc66 1326 struct irq_desc *desc;
229664be 1327
ab7f863e
SR
1328 bits = MASK_LSBS(pending_bits, bit_idx);
1329
1330 /* If we masked out all events, move on. */
ada6814c 1331 if (bits == 0)
ab7f863e 1332 break;
ab7f863e
SR
1333
1334 bit_idx = __ffs(bits);
1335
1336 /* Process port. */
1337 port = (word_idx * BITS_PER_LONG) + bit_idx;
1338 irq = evtchn_to_irq[port];
1339
ca4dbc66
EB
1340 if (irq != -1) {
1341 desc = irq_to_desc(irq);
1342 if (desc)
1343 generic_handle_irq_desc(irq, desc);
1344 }
ab7f863e 1345
ada6814c
KF
1346 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1347
1348 /* Next caller starts at last processed + 1 */
1349 __this_cpu_write(current_word_idx,
1350 bit_idx ? word_idx :
1351 (word_idx+1) % BITS_PER_LONG);
1352 __this_cpu_write(current_bit_idx, bit_idx);
1353 } while (bit_idx != 0);
ab7f863e 1354
24b51c2f
KF
1355 /* Scan start_l1i twice; all others once. */
1356 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1357 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1358
1359 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1360 }
e46cdb66 1361
229664be
JF
1362 BUG_ON(!irqs_disabled());
1363
780f36d8
CL
1364 count = __this_cpu_read(xed_nesting_count);
1365 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1366 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1367
1368out:
38e20b07
SY
1369
1370 put_cpu();
1371}
1372
1373void xen_evtchn_do_upcall(struct pt_regs *regs)
1374{
1375 struct pt_regs *old_regs = set_irq_regs(regs);
1376
1377 exit_idle();
1378 irq_enter();
1379
1380 __xen_evtchn_do_upcall();
1381
3445a8fd
JF
1382 irq_exit();
1383 set_irq_regs(old_regs);
38e20b07 1384}
3445a8fd 1385
38e20b07
SY
1386void xen_hvm_evtchn_do_upcall(void)
1387{
1388 __xen_evtchn_do_upcall();
e46cdb66 1389}
183d03cc 1390EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1391
eb1e305f
JF
1392/* Rebind a new event channel to an existing irq. */
1393void rebind_evtchn_irq(int evtchn, int irq)
1394{
d77bbd4d
JF
1395 struct irq_info *info = info_for_irq(irq);
1396
eb1e305f
JF
1397 /* Make sure the irq is masked, since the new event channel
1398 will also be masked. */
1399 disable_irq(irq);
1400
77365948 1401 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1402
1403 /* After resume the irq<->evtchn mappings are all cleared out */
1404 BUG_ON(evtchn_to_irq[evtchn] != -1);
1405 /* Expect irq to have been bound before,
d77bbd4d
JF
1406 so there should be a proper type */
1407 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1408
9158c358 1409 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1410
77365948 1411 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1412
1413 /* new event channels are always bound to cpu 0 */
0de26520 1414 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1415
1416 /* Unmask the event channel. */
1417 enable_irq(irq);
1418}
1419
e46cdb66 1420/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1421static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1422{
1423 struct evtchn_bind_vcpu bind_vcpu;
1424 int evtchn = evtchn_from_irq(irq);
1425
be49472f
IC
1426 if (!VALID_EVTCHN(evtchn))
1427 return -1;
1428
1429 /*
1430 * Events delivered via platform PCI interrupts are always
1431 * routed to vcpu 0 and hence cannot be rebound.
1432 */
1433 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1434 return -1;
e46cdb66
JF
1435
1436 /* Send future instances of this interrupt to other vcpu. */
1437 bind_vcpu.port = evtchn;
1438 bind_vcpu.vcpu = tcpu;
1439
1440 /*
1441 * If this fails, it usually just indicates that we're dealing with a
1442 * virq or IPI channel, which don't actually need to be rebound. Ignore
1443 * it, but don't do the xenlinux-level rebind in that case.
1444 */
1445 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1446 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1447
d5dedd45
YL
1448 return 0;
1449}
e46cdb66 1450
c9e265e0
TG
1451static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1452 bool force)
e46cdb66 1453{
0de26520 1454 unsigned tcpu = cpumask_first(dest);
d5dedd45 1455
c9e265e0 1456 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1457}
1458
642e0c88
IY
1459int resend_irq_on_evtchn(unsigned int irq)
1460{
1461 int masked, evtchn = evtchn_from_irq(irq);
1462 struct shared_info *s = HYPERVISOR_shared_info;
1463
1464 if (!VALID_EVTCHN(evtchn))
1465 return 1;
1466
1467 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1468 sync_set_bit(evtchn, s->evtchn_pending);
1469 if (!masked)
1470 unmask_evtchn(evtchn);
1471
1472 return 1;
1473}
1474
c9e265e0 1475static void enable_dynirq(struct irq_data *data)
e46cdb66 1476{
c9e265e0 1477 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1478
1479 if (VALID_EVTCHN(evtchn))
1480 unmask_evtchn(evtchn);
1481}
1482
c9e265e0 1483static void disable_dynirq(struct irq_data *data)
e46cdb66 1484{
c9e265e0 1485 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1486
1487 if (VALID_EVTCHN(evtchn))
1488 mask_evtchn(evtchn);
1489}
1490
c9e265e0 1491static void ack_dynirq(struct irq_data *data)
e46cdb66 1492{
c9e265e0 1493 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1494
7e186bdd 1495 irq_move_irq(data);
e46cdb66
JF
1496
1497 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1498 clear_evtchn(evtchn);
1499}
1500
1501static void mask_ack_dynirq(struct irq_data *data)
1502{
1503 disable_dynirq(data);
1504 ack_dynirq(data);
e46cdb66
JF
1505}
1506
c9e265e0 1507static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1508{
c9e265e0 1509 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1510 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1511 int ret = 0;
1512
1513 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1514 int masked;
1515
1516 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1517 sync_set_bit(evtchn, sh->evtchn_pending);
1518 if (!masked)
1519 unmask_evtchn(evtchn);
e46cdb66
JF
1520 ret = 1;
1521 }
1522
1523 return ret;
1524}
1525
0a85226f 1526static void restore_pirqs(void)
9a069c33
SS
1527{
1528 int pirq, rc, irq, gsi;
1529 struct physdev_map_pirq map_irq;
69c358ce 1530 struct irq_info *info;
9a069c33 1531
69c358ce
IC
1532 list_for_each_entry(info, &xen_irq_list_head, list) {
1533 if (info->type != IRQT_PIRQ)
9a069c33
SS
1534 continue;
1535
69c358ce
IC
1536 pirq = info->u.pirq.pirq;
1537 gsi = info->u.pirq.gsi;
1538 irq = info->irq;
1539
9a069c33
SS
1540 /* save/restore of PT devices doesn't work, so at this point the
1541 * only devices present are GSI based emulated devices */
9a069c33
SS
1542 if (!gsi)
1543 continue;
1544
1545 map_irq.domid = DOMID_SELF;
1546 map_irq.type = MAP_PIRQ_TYPE_GSI;
1547 map_irq.index = gsi;
1548 map_irq.pirq = pirq;
1549
1550 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1551 if (rc) {
1552 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1553 gsi, irq, pirq, rc);
9158c358 1554 xen_free_irq(irq);
9a069c33
SS
1555 continue;
1556 }
1557
1558 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1559
c9e265e0 1560 __startup_pirq(irq);
9a069c33
SS
1561 }
1562}
1563
0e91398f
JF
1564static void restore_cpu_virqs(unsigned int cpu)
1565{
1566 struct evtchn_bind_virq bind_virq;
1567 int virq, irq, evtchn;
1568
1569 for (virq = 0; virq < NR_VIRQS; virq++) {
1570 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1571 continue;
1572
ced40d0f 1573 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1574
1575 /* Get a new binding from Xen. */
1576 bind_virq.virq = virq;
1577 bind_virq.vcpu = cpu;
1578 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1579 &bind_virq) != 0)
1580 BUG();
1581 evtchn = bind_virq.port;
1582
1583 /* Record the new mapping. */
3d4cfa37 1584 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1585 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1586 }
1587}
1588
1589static void restore_cpu_ipis(unsigned int cpu)
1590{
1591 struct evtchn_bind_ipi bind_ipi;
1592 int ipi, irq, evtchn;
1593
1594 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1595 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1596 continue;
1597
ced40d0f 1598 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1599
1600 /* Get a new binding from Xen. */
1601 bind_ipi.vcpu = cpu;
1602 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1603 &bind_ipi) != 0)
1604 BUG();
1605 evtchn = bind_ipi.port;
1606
1607 /* Record the new mapping. */
3d4cfa37 1608 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1609 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1610 }
1611}
1612
2d9e1e2f
JF
1613/* Clear an irq's pending state, in preparation for polling on it */
1614void xen_clear_irq_pending(int irq)
1615{
1616 int evtchn = evtchn_from_irq(irq);
1617
1618 if (VALID_EVTCHN(evtchn))
1619 clear_evtchn(evtchn);
1620}
d9a8814f 1621EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1622void xen_set_irq_pending(int irq)
1623{
1624 int evtchn = evtchn_from_irq(irq);
1625
1626 if (VALID_EVTCHN(evtchn))
1627 set_evtchn(evtchn);
1628}
1629
1630bool xen_test_irq_pending(int irq)
1631{
1632 int evtchn = evtchn_from_irq(irq);
1633 bool ret = false;
1634
1635 if (VALID_EVTCHN(evtchn))
1636 ret = test_evtchn(evtchn);
1637
1638 return ret;
1639}
1640
d9a8814f
KRW
1641/* Poll waiting for an irq to become pending with timeout. In the usual case,
1642 * the irq will be disabled so it won't deliver an interrupt. */
1643void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1644{
1645 evtchn_port_t evtchn = evtchn_from_irq(irq);
1646
1647 if (VALID_EVTCHN(evtchn)) {
1648 struct sched_poll poll;
1649
1650 poll.nr_ports = 1;
d9a8814f 1651 poll.timeout = timeout;
ff3c5362 1652 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1653
1654 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1655 BUG();
1656 }
1657}
d9a8814f
KRW
1658EXPORT_SYMBOL(xen_poll_irq_timeout);
1659/* Poll waiting for an irq to become pending. In the usual case, the
1660 * irq will be disabled so it won't deliver an interrupt. */
1661void xen_poll_irq(int irq)
1662{
1663 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1664}
2d9e1e2f 1665
c7c2c3a2
KRW
1666/* Check whether the IRQ line is shared with other guests. */
1667int xen_test_irq_shared(int irq)
1668{
1669 struct irq_info *info = info_for_irq(irq);
1670 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1671
1672 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1673 return 0;
1674 return !(irq_status.flags & XENIRQSTAT_shared);
1675}
1676EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1677
0e91398f
JF
1678void xen_irq_resume(void)
1679{
6cb6537d
IC
1680 unsigned int cpu, evtchn;
1681 struct irq_info *info;
0e91398f
JF
1682
1683 init_evtchn_cpu_bindings();
1684
1685 /* New event-channel space is not 'live' yet. */
1686 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1687 mask_evtchn(evtchn);
1688
1689 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1690 list_for_each_entry(info, &xen_irq_list_head, list)
1691 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1692
1693 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1694 evtchn_to_irq[evtchn] = -1;
1695
1696 for_each_possible_cpu(cpu) {
1697 restore_cpu_virqs(cpu);
1698 restore_cpu_ipis(cpu);
1699 }
6903591f 1700
0a85226f 1701 restore_pirqs();
0e91398f
JF
1702}
1703
e46cdb66 1704static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1705 .name = "xen-dyn",
54a353a0 1706
c9e265e0
TG
1707 .irq_disable = disable_dynirq,
1708 .irq_mask = disable_dynirq,
1709 .irq_unmask = enable_dynirq,
54a353a0 1710
7e186bdd
SS
1711 .irq_ack = ack_dynirq,
1712 .irq_mask_ack = mask_ack_dynirq,
1713
c9e265e0
TG
1714 .irq_set_affinity = set_affinity_irq,
1715 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1716};
1717
d46a78b0 1718static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1719 .name = "xen-pirq",
d46a78b0 1720
c9e265e0
TG
1721 .irq_startup = startup_pirq,
1722 .irq_shutdown = shutdown_pirq,
c9e265e0 1723 .irq_enable = enable_pirq,
c9e265e0 1724 .irq_disable = disable_pirq,
d46a78b0 1725
7e186bdd
SS
1726 .irq_mask = disable_dynirq,
1727 .irq_unmask = enable_dynirq,
1728
1729 .irq_ack = eoi_pirq,
1730 .irq_eoi = eoi_pirq,
1731 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1732
c9e265e0 1733 .irq_set_affinity = set_affinity_irq,
d46a78b0 1734
c9e265e0 1735 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1736};
1737
aaca4964 1738static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1739 .name = "xen-percpu",
aaca4964 1740
c9e265e0
TG
1741 .irq_disable = disable_dynirq,
1742 .irq_mask = disable_dynirq,
1743 .irq_unmask = enable_dynirq,
aaca4964 1744
c9e265e0 1745 .irq_ack = ack_dynirq,
aaca4964
JF
1746};
1747
38e20b07
SY
1748int xen_set_callback_via(uint64_t via)
1749{
1750 struct xen_hvm_param a;
1751 a.domid = DOMID_SELF;
1752 a.index = HVM_PARAM_CALLBACK_IRQ;
1753 a.value = via;
1754 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1755}
1756EXPORT_SYMBOL_GPL(xen_set_callback_via);
1757
ca65f9fc 1758#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1759/* Vector callbacks are better than PCI interrupts to receive event
1760 * channel notifications because we can receive vector callbacks on any
1761 * vcpu and we don't need PCI support or APIC interactions. */
1762void xen_callback_vector(void)
1763{
1764 int rc;
1765 uint64_t callback_via;
1766 if (xen_have_vector_callback) {
1767 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1768 rc = xen_set_callback_via(callback_via);
1769 if (rc) {
1770 printk(KERN_ERR "Request for Xen HVM callback vector"
1771 " failed.\n");
1772 xen_have_vector_callback = 0;
1773 return;
1774 }
1775 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1776 "enabled\n");
1777 /* in the restore case the vector has already been allocated */
1778 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1779 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1780 }
1781}
ca65f9fc
SS
1782#else
1783void xen_callback_vector(void) {}
1784#endif
38e20b07 1785
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JF
1786void __init xen_init_IRQ(void)
1787{
9846ff10 1788 int i, rc;
c7a3589e 1789
b21ddbf5
JF
1790 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1791 GFP_KERNEL);
9d093e29 1792 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1793 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1794 evtchn_to_irq[i] = -1;
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JF
1795
1796 init_evtchn_cpu_bindings();
1797
1798 /* No event channels are 'live' right now. */
1799 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1800 mask_evtchn(i);
1801
9846ff10
SS
1802 pirq_needs_eoi = pirq_needs_eoi_flag;
1803
38e20b07
SY
1804 if (xen_hvm_domain()) {
1805 xen_callback_vector();
1806 native_init_IRQ();
3942b740
SS
1807 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1808 * __acpi_register_gsi can point at the right function */
1809 pci_xen_hvm_init();
38e20b07 1810 } else {
9846ff10
SS
1811 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1812
38e20b07 1813 irq_ctx_init(smp_processor_id());
38aa66fc 1814 if (xen_initial_domain())
a0ee0567 1815 pci_xen_initial_domain();
9846ff10
SS
1816
1817 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1818 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1819 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1820 if (rc != 0) {
1821 free_page((unsigned long) pirq_eoi_map);
1822 pirq_eoi_map = NULL;
1823 } else
1824 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1825 }
e46cdb66 1826}
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