xen/enlighten: Disable MWAIT_LEAF so that acpi-pad won't be loaded.
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
e46cdb66 42#include <asm/xen/hypercall.h>
8d1b8753 43#include <asm/xen/hypervisor.h>
e46cdb66 44
38e20b07
SY
45#include <xen/xen.h>
46#include <xen/hvm.h>
e04d0d07 47#include <xen/xen-ops.h>
e46cdb66
JF
48#include <xen/events.h>
49#include <xen/interface/xen.h>
50#include <xen/interface/event_channel.h>
38e20b07
SY
51#include <xen/interface/hvm/hvm_op.h>
52#include <xen/interface/hvm/params.h>
e46cdb66 53
e46cdb66
JF
54/*
55 * This lock protects updates to the following mapping and reference-count
56 * arrays. The lock does not need to be acquired to read the mapping tables.
57 */
77365948 58static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 59
6cb6537d
IC
60static LIST_HEAD(xen_irq_list_head);
61
e46cdb66 62/* IRQ <-> VIRQ mapping. */
204fba4a 63static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 64
f87e4cac 65/* IRQ <-> IPI mapping */
204fba4a 66static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 67
ced40d0f
JF
68/* Interrupt types. */
69enum xen_irq_type {
d77bbd4d 70 IRQT_UNBOUND = 0,
f87e4cac
JF
71 IRQT_PIRQ,
72 IRQT_VIRQ,
73 IRQT_IPI,
74 IRQT_EVTCHN
75};
e46cdb66 76
ced40d0f
JF
77/*
78 * Packed IRQ information:
79 * type - enum xen_irq_type
80 * event channel - irq->event channel mapping
81 * cpu - cpu this event channel is bound to
82 * index - type-specific information:
42a1de56
SS
83 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
84 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
85 * VIRQ - virq number
86 * IPI - IPI vector
87 * EVTCHN -
88 */
088c05a8 89struct irq_info {
6cb6537d 90 struct list_head list;
420eb554 91 int refcnt;
ced40d0f 92 enum xen_irq_type type; /* type */
6cb6537d 93 unsigned irq;
ced40d0f
JF
94 unsigned short evtchn; /* event channel */
95 unsigned short cpu; /* cpu bound */
96
97 union {
98 unsigned short virq;
99 enum ipi_vector ipi;
100 struct {
7a043f11 101 unsigned short pirq;
ced40d0f 102 unsigned short gsi;
d46a78b0
JF
103 unsigned char vector;
104 unsigned char flags;
beafbdc1 105 uint16_t domid;
ced40d0f
JF
106 } pirq;
107 } u;
108};
d46a78b0 109#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 110#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 111
b21ddbf5 112static int *evtchn_to_irq;
9846ff10
SS
113static unsigned long *pirq_eoi_map;
114static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 115
cb60d114
IC
116static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
117 cpu_evtchn_mask);
e46cdb66 118
e46cdb66
JF
119/* Xen will never allocate port zero for any purpose. */
120#define VALID_EVTCHN(chn) ((chn) != 0)
121
e46cdb66 122static struct irq_chip xen_dynamic_chip;
aaca4964 123static struct irq_chip xen_percpu_chip;
d46a78b0 124static struct irq_chip xen_pirq_chip;
7e186bdd
SS
125static void enable_dynirq(struct irq_data *data);
126static void disable_dynirq(struct irq_data *data);
e46cdb66 127
9158c358
IC
128/* Get info for IRQ */
129static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 130{
c442b806 131 return irq_get_handler_data(irq);
ced40d0f
JF
132}
133
9158c358
IC
134/* Constructors for packed IRQ information. */
135static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 136 unsigned irq,
9158c358
IC
137 enum xen_irq_type type,
138 unsigned short evtchn,
139 unsigned short cpu)
ced40d0f 140{
9158c358
IC
141
142 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
143
144 info->type = type;
6cb6537d 145 info->irq = irq;
9158c358
IC
146 info->evtchn = evtchn;
147 info->cpu = cpu;
3d4cfa37
IC
148
149 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
150}
151
9158c358
IC
152static void xen_irq_info_evtchn_init(unsigned irq,
153 unsigned short evtchn)
ced40d0f 154{
9158c358
IC
155 struct irq_info *info = info_for_irq(irq);
156
3d4cfa37 157 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
158}
159
3d4cfa37
IC
160static void xen_irq_info_ipi_init(unsigned cpu,
161 unsigned irq,
9158c358
IC
162 unsigned short evtchn,
163 enum ipi_vector ipi)
e46cdb66 164{
9158c358
IC
165 struct irq_info *info = info_for_irq(irq);
166
3d4cfa37 167 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
168
169 info->u.ipi = ipi;
3d4cfa37
IC
170
171 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
172}
173
3d4cfa37
IC
174static void xen_irq_info_virq_init(unsigned cpu,
175 unsigned irq,
9158c358
IC
176 unsigned short evtchn,
177 unsigned short virq)
ced40d0f 178{
9158c358
IC
179 struct irq_info *info = info_for_irq(irq);
180
3d4cfa37 181 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
182
183 info->u.virq = virq;
3d4cfa37
IC
184
185 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
186}
187
9158c358
IC
188static void xen_irq_info_pirq_init(unsigned irq,
189 unsigned short evtchn,
190 unsigned short pirq,
191 unsigned short gsi,
192 unsigned short vector,
beafbdc1 193 uint16_t domid,
9158c358 194 unsigned char flags)
ced40d0f 195{
9158c358
IC
196 struct irq_info *info = info_for_irq(irq);
197
3d4cfa37 198 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
199
200 info->u.pirq.pirq = pirq;
201 info->u.pirq.gsi = gsi;
202 info->u.pirq.vector = vector;
beafbdc1 203 info->u.pirq.domid = domid;
9158c358 204 info->u.pirq.flags = flags;
e46cdb66
JF
205}
206
207/*
208 * Accessors for packed IRQ information.
209 */
ced40d0f 210static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 211{
110e7c7e
JJ
212 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
213 return 0;
214
ced40d0f 215 return info_for_irq(irq)->evtchn;
e46cdb66
JF
216}
217
d4c04536
IC
218unsigned irq_from_evtchn(unsigned int evtchn)
219{
220 return evtchn_to_irq[evtchn];
221}
222EXPORT_SYMBOL_GPL(irq_from_evtchn);
223
ced40d0f 224static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 225{
ced40d0f
JF
226 struct irq_info *info = info_for_irq(irq);
227
228 BUG_ON(info == NULL);
229 BUG_ON(info->type != IRQT_IPI);
230
231 return info->u.ipi;
232}
233
234static unsigned virq_from_irq(unsigned irq)
235{
236 struct irq_info *info = info_for_irq(irq);
237
238 BUG_ON(info == NULL);
239 BUG_ON(info->type != IRQT_VIRQ);
240
241 return info->u.virq;
242}
243
7a043f11
SS
244static unsigned pirq_from_irq(unsigned irq)
245{
246 struct irq_info *info = info_for_irq(irq);
247
248 BUG_ON(info == NULL);
249 BUG_ON(info->type != IRQT_PIRQ);
250
251 return info->u.pirq.pirq;
252}
253
ced40d0f
JF
254static enum xen_irq_type type_from_irq(unsigned irq)
255{
256 return info_for_irq(irq)->type;
257}
258
259static unsigned cpu_from_irq(unsigned irq)
260{
261 return info_for_irq(irq)->cpu;
262}
263
264static unsigned int cpu_from_evtchn(unsigned int evtchn)
265{
266 int irq = evtchn_to_irq[evtchn];
267 unsigned ret = 0;
268
269 if (irq != -1)
270 ret = cpu_from_irq(irq);
271
272 return ret;
e46cdb66
JF
273}
274
9846ff10 275static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 276{
9846ff10
SS
277 return test_bit(irq, pirq_eoi_map);
278}
d46a78b0 279
9846ff10
SS
280static bool pirq_needs_eoi_flag(unsigned irq)
281{
282 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
283 BUG_ON(info->type != IRQT_PIRQ);
284
285 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
286}
287
e46cdb66
JF
288static inline unsigned long active_evtchns(unsigned int cpu,
289 struct shared_info *sh,
290 unsigned int idx)
291{
088c05a8 292 return sh->evtchn_pending[idx] &
cb60d114 293 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 294 ~sh->evtchn_mask[idx];
e46cdb66
JF
295}
296
297static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
298{
299 int irq = evtchn_to_irq[chn];
300
301 BUG_ON(irq == -1);
302#ifdef CONFIG_SMP
c9e265e0 303 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
304#endif
305
cb60d114
IC
306 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
307 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 308
ca62ce8c 309 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
310}
311
312static void init_evtchn_cpu_bindings(void)
313{
1c6969ec 314 int i;
e46cdb66 315#ifdef CONFIG_SMP
6cb6537d 316 struct irq_info *info;
10e58084 317
e46cdb66 318 /* By default all event channels notify CPU#0. */
6cb6537d
IC
319 list_for_each_entry(info, &xen_irq_list_head, list) {
320 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 321 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 322 }
e46cdb66
JF
323#endif
324
1c6969ec 325 for_each_possible_cpu(i)
cb60d114
IC
326 memset(per_cpu(cpu_evtchn_mask, i),
327 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
328}
329
e46cdb66
JF
330static inline void clear_evtchn(int port)
331{
332 struct shared_info *s = HYPERVISOR_shared_info;
333 sync_clear_bit(port, &s->evtchn_pending[0]);
334}
335
336static inline void set_evtchn(int port)
337{
338 struct shared_info *s = HYPERVISOR_shared_info;
339 sync_set_bit(port, &s->evtchn_pending[0]);
340}
341
168d2f46
JF
342static inline int test_evtchn(int port)
343{
344 struct shared_info *s = HYPERVISOR_shared_info;
345 return sync_test_bit(port, &s->evtchn_pending[0]);
346}
347
e46cdb66
JF
348
349/**
350 * notify_remote_via_irq - send event to remote end of event channel via irq
351 * @irq: irq of event channel to send event to
352 *
353 * Unlike notify_remote_via_evtchn(), this is safe to use across
354 * save/restore. Notifications on a broken connection are silently
355 * dropped.
356 */
357void notify_remote_via_irq(int irq)
358{
359 int evtchn = evtchn_from_irq(irq);
360
361 if (VALID_EVTCHN(evtchn))
362 notify_remote_via_evtchn(evtchn);
363}
364EXPORT_SYMBOL_GPL(notify_remote_via_irq);
365
366static void mask_evtchn(int port)
367{
368 struct shared_info *s = HYPERVISOR_shared_info;
369 sync_set_bit(port, &s->evtchn_mask[0]);
370}
371
372static void unmask_evtchn(int port)
373{
374 struct shared_info *s = HYPERVISOR_shared_info;
375 unsigned int cpu = get_cpu();
376
377 BUG_ON(!irqs_disabled());
378
379 /* Slow path (hypercall) if this is a non-local port. */
380 if (unlikely(cpu != cpu_from_evtchn(port))) {
381 struct evtchn_unmask unmask = { .port = port };
382 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
383 } else {
780f36d8 384 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
385
386 sync_clear_bit(port, &s->evtchn_mask[0]);
387
388 /*
389 * The following is basically the equivalent of
390 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
391 * the interrupt edge' if the channel is masked.
392 */
393 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
394 !sync_test_and_set_bit(port / BITS_PER_LONG,
395 &vcpu_info->evtchn_pending_sel))
396 vcpu_info->evtchn_upcall_pending = 1;
397 }
398
399 put_cpu();
400}
401
6cb6537d
IC
402static void xen_irq_init(unsigned irq)
403{
404 struct irq_info *info;
b5328cd1 405#ifdef CONFIG_SMP
6cb6537d
IC
406 struct irq_desc *desc = irq_to_desc(irq);
407
408 /* By default all event channels notify CPU#0. */
409 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 410#endif
6cb6537d 411
ca62ce8c
IC
412 info = kzalloc(sizeof(*info), GFP_KERNEL);
413 if (info == NULL)
414 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
415
416 info->type = IRQT_UNBOUND;
420eb554 417 info->refcnt = -1;
6cb6537d 418
c442b806 419 irq_set_handler_data(irq, info);
ca62ce8c 420
6cb6537d
IC
421 list_add_tail(&info->list, &xen_irq_list_head);
422}
423
7bee9768 424static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 425{
89911501
IC
426 int first = 0;
427 int irq;
0794bfc7
KRW
428
429#ifdef CONFIG_X86_IO_APIC
89911501
IC
430 /*
431 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 432 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
433 * e.g. those corresponding to event channels or MSIs
434 * etc. from the range above those "real" GSIs to avoid
435 * collisions.
436 */
437 if (xen_initial_domain() || xen_hvm_domain())
438 first = get_nr_irqs_gsi();
0794bfc7
KRW
439#endif
440
89911501 441 irq = irq_alloc_desc_from(first, -1);
3a69e916 442
e6599225
KRW
443 if (irq >= 0)
444 xen_irq_init(irq);
ced40d0f 445
e46cdb66 446 return irq;
d46a78b0
JF
447}
448
7bee9768 449static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
450{
451 int irq;
452
89911501
IC
453 /*
454 * A PV guest has no concept of a GSI (since it has no ACPI
455 * nor access to/knowledge of the physical APICs). Therefore
456 * all IRQs are dynamically allocated from the entire IRQ
457 * space.
458 */
459 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
460 return xen_allocate_irq_dynamic();
461
462 /* Legacy IRQ descriptors are already allocated by the arch. */
463 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
464 irq = gsi;
465 else
466 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 467
6cb6537d 468 xen_irq_init(irq);
c9df1ce5
IC
469
470 return irq;
471}
472
473static void xen_free_irq(unsigned irq)
474{
c442b806 475 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
476
477 list_del(&info->list);
9158c358 478
c442b806 479 irq_set_handler_data(irq, NULL);
ca62ce8c 480
420eb554
DDG
481 WARN_ON(info->refcnt > 0);
482
ca62ce8c
IC
483 kfree(info);
484
72146104
IC
485 /* Legacy IRQ descriptors are managed by the arch. */
486 if (irq < NR_IRQS_LEGACY)
487 return;
488
c9df1ce5
IC
489 irq_free_desc(irq);
490}
491
d46a78b0
JF
492static void pirq_query_unmask(int irq)
493{
494 struct physdev_irq_status_query irq_status;
495 struct irq_info *info = info_for_irq(irq);
496
497 BUG_ON(info->type != IRQT_PIRQ);
498
7a043f11 499 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
500 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
501 irq_status.flags = 0;
502
503 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
504 if (irq_status.flags & XENIRQSTAT_needs_eoi)
505 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
506}
507
508static bool probing_irq(int irq)
509{
510 struct irq_desc *desc = irq_to_desc(irq);
511
512 return desc && desc->action == NULL;
513}
514
7e186bdd
SS
515static void eoi_pirq(struct irq_data *data)
516{
517 int evtchn = evtchn_from_irq(data->irq);
518 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
519 int rc = 0;
520
521 irq_move_irq(data);
522
523 if (VALID_EVTCHN(evtchn))
524 clear_evtchn(evtchn);
525
526 if (pirq_needs_eoi(data->irq)) {
527 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
528 WARN_ON(rc);
529 }
530}
531
532static void mask_ack_pirq(struct irq_data *data)
533{
534 disable_dynirq(data);
535 eoi_pirq(data);
536}
537
c9e265e0 538static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
539{
540 struct evtchn_bind_pirq bind_pirq;
541 struct irq_info *info = info_for_irq(irq);
542 int evtchn = evtchn_from_irq(irq);
15ebbb82 543 int rc;
d46a78b0
JF
544
545 BUG_ON(info->type != IRQT_PIRQ);
546
547 if (VALID_EVTCHN(evtchn))
548 goto out;
549
7a043f11 550 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 551 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
552 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
553 BIND_PIRQ__WILL_SHARE : 0;
554 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
555 if (rc != 0) {
d46a78b0
JF
556 if (!probing_irq(irq))
557 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
558 irq);
559 return 0;
560 }
561 evtchn = bind_pirq.port;
562
563 pirq_query_unmask(irq);
564
565 evtchn_to_irq[evtchn] = irq;
566 bind_evtchn_to_cpu(evtchn, 0);
567 info->evtchn = evtchn;
568
569out:
570 unmask_evtchn(evtchn);
7e186bdd 571 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
572
573 return 0;
574}
575
c9e265e0
TG
576static unsigned int startup_pirq(struct irq_data *data)
577{
578 return __startup_pirq(data->irq);
579}
580
581static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
582{
583 struct evtchn_close close;
c9e265e0 584 unsigned int irq = data->irq;
d46a78b0
JF
585 struct irq_info *info = info_for_irq(irq);
586 int evtchn = evtchn_from_irq(irq);
587
588 BUG_ON(info->type != IRQT_PIRQ);
589
590 if (!VALID_EVTCHN(evtchn))
591 return;
592
593 mask_evtchn(evtchn);
594
595 close.port = evtchn;
596 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
597 BUG();
598
599 bind_evtchn_to_cpu(evtchn, 0);
600 evtchn_to_irq[evtchn] = -1;
601 info->evtchn = 0;
602}
603
c9e265e0 604static void enable_pirq(struct irq_data *data)
d46a78b0 605{
c9e265e0 606 startup_pirq(data);
d46a78b0
JF
607}
608
c9e265e0 609static void disable_pirq(struct irq_data *data)
d46a78b0 610{
7e186bdd 611 disable_dynirq(data);
d46a78b0
JF
612}
613
d46a78b0
JF
614static int find_irq_by_gsi(unsigned gsi)
615{
6cb6537d 616 struct irq_info *info;
d46a78b0 617
6cb6537d
IC
618 list_for_each_entry(info, &xen_irq_list_head, list) {
619 if (info->type != IRQT_PIRQ)
d46a78b0
JF
620 continue;
621
6cb6537d
IC
622 if (info->u.pirq.gsi == gsi)
623 return info->irq;
d46a78b0
JF
624 }
625
626 return -1;
627}
628
653378ac
IC
629/*
630 * Do not make any assumptions regarding the relationship between the
631 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
632 *
633 * Note: We don't assign an event channel until the irq actually started
634 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
635 *
636 * Shareable implies level triggered, not shareable implies edge
637 * triggered here.
d46a78b0 638 */
f4d0635b
IC
639int xen_bind_pirq_gsi_to_irq(unsigned gsi,
640 unsigned pirq, int shareable, char *name)
d46a78b0 641{
a0e18116 642 int irq = -1;
d46a78b0
JF
643 struct physdev_irq irq_op;
644
77365948 645 mutex_lock(&irq_mapping_update_lock);
d46a78b0
JF
646
647 irq = find_irq_by_gsi(gsi);
648 if (irq != -1) {
7a043f11 649 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 650 irq, gsi);
420eb554 651 goto out;
d46a78b0
JF
652 }
653
c9df1ce5 654 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
655 if (irq < 0)
656 goto out;
d46a78b0 657
d46a78b0 658 irq_op.irq = irq;
b5401a96
AN
659 irq_op.vector = 0;
660
661 /* Only the privileged domain can do this. For non-priv, the pcifront
662 * driver provides a PCI bus that does the call to do exactly
663 * this in the priv domain. */
664 if (xen_initial_domain() &&
665 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 666 xen_free_irq(irq);
d46a78b0
JF
667 irq = -ENOSPC;
668 goto out;
669 }
670
beafbdc1 671 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 672 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 673
7e186bdd
SS
674 pirq_query_unmask(irq);
675 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
676 * type of interrupt: if the interrupt is an edge triggered
677 * interrupt we use handle_edge_irq.
7e186bdd 678 *
e5ac0bda
SS
679 * On the other hand if the interrupt is level triggered we use
680 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 681 * interrupts.
e5ac0bda 682 *
7e186bdd
SS
683 * Depending on the Xen version, pirq_needs_eoi might return true
684 * not only for level triggered interrupts but for edge triggered
685 * interrupts too. In any case Xen always honors the eoi mechanism,
686 * not injecting any more pirqs of the same kind if the first one
687 * hasn't received an eoi yet. Therefore using the fasteoi handler
688 * is the right choice either way.
689 */
e5ac0bda 690 if (shareable)
7e186bdd
SS
691 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
692 handle_fasteoi_irq, name);
693 else
694 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
695 handle_edge_irq, name);
696
d46a78b0 697out:
77365948 698 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
699
700 return irq;
701}
702
f731e3ef 703#ifdef CONFIG_PCI_MSI
bf480d95 704int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 705{
5cad61a6 706 int rc;
cbf6aa89 707 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 708
bf480d95 709 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 710 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 711
5cad61a6
IC
712 WARN_ONCE(rc == -ENOSYS,
713 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
714
715 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
716}
717
bf480d95 718int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
719 int pirq, int vector, const char *name,
720 domid_t domid)
809f9267 721{
bf480d95 722 int irq, ret;
4b41df7f 723
77365948 724 mutex_lock(&irq_mapping_update_lock);
809f9267 725
4b41df7f 726 irq = xen_allocate_irq_dynamic();
e6599225 727 if (irq < 0)
bb5d079a 728 goto out;
809f9267 729
7e186bdd
SS
730 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
731 name);
809f9267 732
beafbdc1 733 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 734 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
735 if (ret < 0)
736 goto error_irq;
809f9267 737out:
77365948 738 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 739 return irq;
bf480d95 740error_irq:
77365948 741 mutex_unlock(&irq_mapping_update_lock);
bf480d95 742 xen_free_irq(irq);
e6599225 743 return ret;
809f9267 744}
f731e3ef
QH
745#endif
746
b5401a96
AN
747int xen_destroy_irq(int irq)
748{
749 struct irq_desc *desc;
38aa66fc
JF
750 struct physdev_unmap_pirq unmap_irq;
751 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
752 int rc = -ENOENT;
753
77365948 754 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
755
756 desc = irq_to_desc(irq);
757 if (!desc)
758 goto out;
759
38aa66fc 760 if (xen_initial_domain()) {
12334715 761 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 762 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 763 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
764 /* If another domain quits without making the pci_disable_msix
765 * call, the Xen hypervisor takes care of freeing the PIRQs
766 * (free_domain_pirqs).
767 */
768 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
769 printk(KERN_INFO "domain %d does not have %d anymore\n",
770 info->u.pirq.domid, info->u.pirq.pirq);
771 else if (rc) {
38aa66fc
JF
772 printk(KERN_WARNING "unmap irq failed %d\n", rc);
773 goto out;
774 }
775 }
b5401a96 776
c9df1ce5 777 xen_free_irq(irq);
b5401a96
AN
778
779out:
77365948 780 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
781 return rc;
782}
783
af42b8d1 784int xen_irq_from_pirq(unsigned pirq)
d46a78b0 785{
69c358ce 786 int irq;
d46a78b0 787
69c358ce 788 struct irq_info *info;
e46cdb66 789
77365948 790 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
791
792 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 793 if (info->type != IRQT_PIRQ)
69c358ce
IC
794 continue;
795 irq = info->irq;
796 if (info->u.pirq.pirq == pirq)
797 goto out;
798 }
799 irq = -1;
800out:
77365948 801 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
802
803 return irq;
af42b8d1
SS
804}
805
e6197acc
KRW
806
807int xen_pirq_from_irq(unsigned irq)
808{
809 return pirq_from_irq(irq);
810}
811EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 812int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
813{
814 int irq;
815
77365948 816 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
817
818 irq = evtchn_to_irq[evtchn];
819
820 if (irq == -1) {
c9df1ce5 821 irq = xen_allocate_irq_dynamic();
7bee9768
IC
822 if (irq == -1)
823 goto out;
e46cdb66 824
c442b806 825 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 826 handle_edge_irq, "event");
e46cdb66 827
9158c358 828 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
829 }
830
7bee9768 831out:
77365948 832 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
833
834 return irq;
835}
b536b4b9 836EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 837
f87e4cac
JF
838static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
839{
840 struct evtchn_bind_ipi bind_ipi;
841 int evtchn, irq;
842
77365948 843 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
844
845 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 846
f87e4cac 847 if (irq == -1) {
c9df1ce5 848 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
849 if (irq < 0)
850 goto out;
851
c442b806 852 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 853 handle_percpu_irq, "ipi");
f87e4cac
JF
854
855 bind_ipi.vcpu = cpu;
856 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
857 &bind_ipi) != 0)
858 BUG();
859 evtchn = bind_ipi.port;
860
3d4cfa37 861 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
862
863 bind_evtchn_to_cpu(evtchn, cpu);
864 }
865
f87e4cac 866 out:
77365948 867 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
868 return irq;
869}
870
2e820f58
IC
871static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
872 unsigned int remote_port)
873{
874 struct evtchn_bind_interdomain bind_interdomain;
875 int err;
876
877 bind_interdomain.remote_dom = remote_domain;
878 bind_interdomain.remote_port = remote_port;
879
880 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
881 &bind_interdomain);
882
883 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
884}
885
62cc5fc7
OH
886static int find_virq(unsigned int virq, unsigned int cpu)
887{
888 struct evtchn_status status;
889 int port, rc = -ENOENT;
890
891 memset(&status, 0, sizeof(status));
892 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
893 status.dom = DOMID_SELF;
894 status.port = port;
895 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
896 if (rc < 0)
897 continue;
898 if (status.status != EVTCHNSTAT_virq)
899 continue;
900 if (status.u.virq == virq && status.vcpu == cpu) {
901 rc = port;
902 break;
903 }
904 }
905 return rc;
906}
f87e4cac 907
4fe7d5a7 908int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
909{
910 struct evtchn_bind_virq bind_virq;
62cc5fc7 911 int evtchn, irq, ret;
e46cdb66 912
77365948 913 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
914
915 irq = per_cpu(virq_to_irq, cpu)[virq];
916
917 if (irq == -1) {
c9df1ce5 918 irq = xen_allocate_irq_dynamic();
7bee9768
IC
919 if (irq == -1)
920 goto out;
a52521f1 921
c442b806 922 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
923 handle_percpu_irq, "virq");
924
e46cdb66
JF
925 bind_virq.virq = virq;
926 bind_virq.vcpu = cpu;
62cc5fc7
OH
927 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
928 &bind_virq);
929 if (ret == 0)
930 evtchn = bind_virq.port;
931 else {
932 if (ret == -EEXIST)
933 ret = find_virq(virq, cpu);
934 BUG_ON(ret < 0);
935 evtchn = ret;
936 }
e46cdb66 937
3d4cfa37 938 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
939
940 bind_evtchn_to_cpu(evtchn, cpu);
941 }
942
7bee9768 943out:
77365948 944 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
945
946 return irq;
947}
948
949static void unbind_from_irq(unsigned int irq)
950{
951 struct evtchn_close close;
952 int evtchn = evtchn_from_irq(irq);
420eb554 953 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 954
77365948 955 mutex_lock(&irq_mapping_update_lock);
e46cdb66 956
420eb554
DDG
957 if (info->refcnt > 0) {
958 info->refcnt--;
959 if (info->refcnt != 0)
960 goto done;
961 }
962
d77bbd4d 963 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
964 close.port = evtchn;
965 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
966 BUG();
967
968 switch (type_from_irq(irq)) {
969 case IRQT_VIRQ:
970 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 971 [virq_from_irq(irq)] = -1;
e46cdb66 972 break;
d68d82af
AN
973 case IRQT_IPI:
974 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 975 [ipi_from_irq(irq)] = -1;
d68d82af 976 break;
e46cdb66
JF
977 default:
978 break;
979 }
980
981 /* Closed ports are implicitly re-bound to VCPU0. */
982 bind_evtchn_to_cpu(evtchn, 0);
983
984 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
985 }
986
ca62ce8c 987 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 988
9158c358 989 xen_free_irq(irq);
e46cdb66 990
420eb554 991 done:
77365948 992 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
993}
994
995int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 996 irq_handler_t handler,
e46cdb66
JF
997 unsigned long irqflags,
998 const char *devname, void *dev_id)
999{
361ae8cb 1000 int irq, retval;
e46cdb66
JF
1001
1002 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1003 if (irq < 0)
1004 return irq;
e46cdb66
JF
1005 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1006 if (retval != 0) {
1007 unbind_from_irq(irq);
1008 return retval;
1009 }
1010
1011 return irq;
1012}
1013EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1014
2e820f58
IC
1015int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1016 unsigned int remote_port,
1017 irq_handler_t handler,
1018 unsigned long irqflags,
1019 const char *devname,
1020 void *dev_id)
1021{
1022 int irq, retval;
1023
1024 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1025 if (irq < 0)
1026 return irq;
1027
1028 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1029 if (retval != 0) {
1030 unbind_from_irq(irq);
1031 return retval;
1032 }
1033
1034 return irq;
1035}
1036EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1037
e46cdb66 1038int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1039 irq_handler_t handler,
e46cdb66
JF
1040 unsigned long irqflags, const char *devname, void *dev_id)
1041{
361ae8cb 1042 int irq, retval;
e46cdb66
JF
1043
1044 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1045 if (irq < 0)
1046 return irq;
e46cdb66
JF
1047 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1048 if (retval != 0) {
1049 unbind_from_irq(irq);
1050 return retval;
1051 }
1052
1053 return irq;
1054}
1055EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1056
f87e4cac
JF
1057int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1058 unsigned int cpu,
1059 irq_handler_t handler,
1060 unsigned long irqflags,
1061 const char *devname,
1062 void *dev_id)
1063{
1064 int irq, retval;
1065
1066 irq = bind_ipi_to_irq(ipi, cpu);
1067 if (irq < 0)
1068 return irq;
1069
9bab0b7f 1070 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1071 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1072 if (retval != 0) {
1073 unbind_from_irq(irq);
1074 return retval;
1075 }
1076
1077 return irq;
1078}
1079
e46cdb66
JF
1080void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1081{
1082 free_irq(irq, dev_id);
1083 unbind_from_irq(irq);
1084}
1085EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1086
420eb554
DDG
1087int evtchn_make_refcounted(unsigned int evtchn)
1088{
1089 int irq = evtchn_to_irq[evtchn];
1090 struct irq_info *info;
1091
1092 if (irq == -1)
1093 return -ENOENT;
1094
1095 info = irq_get_handler_data(irq);
1096
1097 if (!info)
1098 return -ENOENT;
1099
1100 WARN_ON(info->refcnt != -1);
1101
1102 info->refcnt = 1;
1103
1104 return 0;
1105}
1106EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1107
1108int evtchn_get(unsigned int evtchn)
1109{
1110 int irq;
1111 struct irq_info *info;
1112 int err = -ENOENT;
1113
c3b3f16d
DDG
1114 if (evtchn >= NR_EVENT_CHANNELS)
1115 return -EINVAL;
1116
420eb554
DDG
1117 mutex_lock(&irq_mapping_update_lock);
1118
1119 irq = evtchn_to_irq[evtchn];
1120 if (irq == -1)
1121 goto done;
1122
1123 info = irq_get_handler_data(irq);
1124
1125 if (!info)
1126 goto done;
1127
1128 err = -EINVAL;
1129 if (info->refcnt <= 0)
1130 goto done;
1131
1132 info->refcnt++;
1133 err = 0;
1134 done:
1135 mutex_unlock(&irq_mapping_update_lock);
1136
1137 return err;
1138}
1139EXPORT_SYMBOL_GPL(evtchn_get);
1140
1141void evtchn_put(unsigned int evtchn)
1142{
1143 int irq = evtchn_to_irq[evtchn];
1144 if (WARN_ON(irq == -1))
1145 return;
1146 unbind_from_irq(irq);
1147}
1148EXPORT_SYMBOL_GPL(evtchn_put);
1149
f87e4cac
JF
1150void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1151{
1152 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1153 BUG_ON(irq < 0);
1154 notify_remote_via_irq(irq);
1155}
1156
ee523ca1
JF
1157irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1158{
1159 struct shared_info *sh = HYPERVISOR_shared_info;
1160 int cpu = smp_processor_id();
cb60d114 1161 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1162 int i;
1163 unsigned long flags;
1164 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1165 struct vcpu_info *v;
ee523ca1
JF
1166
1167 spin_lock_irqsave(&debug_lock, flags);
1168
cb52e6d9 1169 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1170
1171 for_each_online_cpu(i) {
cb52e6d9
IC
1172 int pending;
1173 v = per_cpu(xen_vcpu, i);
1174 pending = (get_irq_regs() && i == cpu)
1175 ? xen_irqs_disabled(get_irq_regs())
1176 : v->evtchn_upcall_mask;
1177 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1178 pending, v->evtchn_upcall_pending,
1179 (int)(sizeof(v->evtchn_pending_sel)*2),
1180 v->evtchn_pending_sel);
1181 }
1182 v = per_cpu(xen_vcpu, cpu);
1183
1184 printk("\npending:\n ");
1185 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1186 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1187 sh->evtchn_pending[i],
1188 i % 8 == 0 ? "\n " : " ");
1189 printk("\nglobal mask:\n ");
1190 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1191 printk("%0*lx%s",
1192 (int)(sizeof(sh->evtchn_mask[0])*2),
1193 sh->evtchn_mask[i],
1194 i % 8 == 0 ? "\n " : " ");
1195
1196 printk("\nglobally unmasked:\n ");
1197 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1198 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1199 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1200 i % 8 == 0 ? "\n " : " ");
1201
1202 printk("\nlocal cpu%d mask:\n ", cpu);
1203 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1204 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1205 cpu_evtchn[i],
1206 i % 8 == 0 ? "\n " : " ");
1207
1208 printk("\nlocally unmasked:\n ");
1209 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1210 unsigned long pending = sh->evtchn_pending[i]
1211 & ~sh->evtchn_mask[i]
1212 & cpu_evtchn[i];
1213 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1214 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1215 }
ee523ca1
JF
1216
1217 printk("\npending list:\n");
cb52e6d9 1218 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1219 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1220 int word_idx = i / BITS_PER_LONG;
1221 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1222 cpu_from_evtchn(i), i,
cb52e6d9
IC
1223 evtchn_to_irq[i],
1224 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1225 ? "" : " l2-clear",
1226 !sync_test_bit(i, sh->evtchn_mask)
1227 ? "" : " globally-masked",
1228 sync_test_bit(i, cpu_evtchn)
1229 ? "" : " locally-masked");
ee523ca1
JF
1230 }
1231 }
1232
1233 spin_unlock_irqrestore(&debug_lock, flags);
1234
1235 return IRQ_HANDLED;
1236}
1237
245b2e70 1238static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1239static DEFINE_PER_CPU(unsigned int, current_word_idx);
1240static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1241
ab7f863e
SR
1242/*
1243 * Mask out the i least significant bits of w
1244 */
1245#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1246
e46cdb66
JF
1247/*
1248 * Search the CPUs pending events bitmasks. For each one found, map
1249 * the event number to an irq, and feed it into do_IRQ() for
1250 * handling.
1251 *
1252 * Xen uses a two-level bitmap to speed searching. The first level is
1253 * a bitset of words which contain pending event bits. The second
1254 * level is a bitset of pending events themselves.
1255 */
38e20b07 1256static void __xen_evtchn_do_upcall(void)
e46cdb66 1257{
24b51c2f 1258 int start_word_idx, start_bit_idx;
ab7f863e 1259 int word_idx, bit_idx;
24b51c2f 1260 int i;
e46cdb66
JF
1261 int cpu = get_cpu();
1262 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1263 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1264 unsigned count;
e46cdb66 1265
229664be
JF
1266 do {
1267 unsigned long pending_words;
e46cdb66 1268
229664be 1269 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1270
b2e4ae69 1271 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1272 goto out;
e46cdb66 1273
e849c3e9
IY
1274#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1275 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1276 wmb();
e849c3e9 1277#endif
229664be 1278 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1279
24b51c2f
KF
1280 start_word_idx = __this_cpu_read(current_word_idx);
1281 start_bit_idx = __this_cpu_read(current_bit_idx);
1282
1283 word_idx = start_word_idx;
ab7f863e 1284
24b51c2f 1285 for (i = 0; pending_words != 0; i++) {
229664be 1286 unsigned long pending_bits;
ab7f863e 1287 unsigned long words;
229664be 1288
ab7f863e
SR
1289 words = MASK_LSBS(pending_words, word_idx);
1290
1291 /*
ada6814c 1292 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1293 */
1294 if (words == 0) {
ada6814c
KF
1295 word_idx = 0;
1296 bit_idx = 0;
ab7f863e
SR
1297 continue;
1298 }
1299 word_idx = __ffs(words);
229664be 1300
24b51c2f
KF
1301 pending_bits = active_evtchns(cpu, s, word_idx);
1302 bit_idx = 0; /* usually scan entire word from start */
1303 if (word_idx == start_word_idx) {
1304 /* We scan the starting word in two parts */
1305 if (i == 0)
1306 /* 1st time: start in the middle */
1307 bit_idx = start_bit_idx;
1308 else
1309 /* 2nd time: mask bits done already */
1310 bit_idx &= (1UL << start_bit_idx) - 1;
1311 }
1312
ab7f863e
SR
1313 do {
1314 unsigned long bits;
1315 int port, irq;
ca4dbc66 1316 struct irq_desc *desc;
229664be 1317
ab7f863e
SR
1318 bits = MASK_LSBS(pending_bits, bit_idx);
1319
1320 /* If we masked out all events, move on. */
ada6814c 1321 if (bits == 0)
ab7f863e 1322 break;
ab7f863e
SR
1323
1324 bit_idx = __ffs(bits);
1325
1326 /* Process port. */
1327 port = (word_idx * BITS_PER_LONG) + bit_idx;
1328 irq = evtchn_to_irq[port];
1329
ca4dbc66
EB
1330 if (irq != -1) {
1331 desc = irq_to_desc(irq);
1332 if (desc)
1333 generic_handle_irq_desc(irq, desc);
1334 }
ab7f863e 1335
ada6814c
KF
1336 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1337
1338 /* Next caller starts at last processed + 1 */
1339 __this_cpu_write(current_word_idx,
1340 bit_idx ? word_idx :
1341 (word_idx+1) % BITS_PER_LONG);
1342 __this_cpu_write(current_bit_idx, bit_idx);
1343 } while (bit_idx != 0);
ab7f863e 1344
24b51c2f
KF
1345 /* Scan start_l1i twice; all others once. */
1346 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1347 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1348
1349 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1350 }
e46cdb66 1351
229664be
JF
1352 BUG_ON(!irqs_disabled());
1353
780f36d8
CL
1354 count = __this_cpu_read(xed_nesting_count);
1355 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1356 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1357
1358out:
38e20b07
SY
1359
1360 put_cpu();
1361}
1362
1363void xen_evtchn_do_upcall(struct pt_regs *regs)
1364{
1365 struct pt_regs *old_regs = set_irq_regs(regs);
1366
1367 exit_idle();
1368 irq_enter();
1369
1370 __xen_evtchn_do_upcall();
1371
3445a8fd
JF
1372 irq_exit();
1373 set_irq_regs(old_regs);
38e20b07 1374}
3445a8fd 1375
38e20b07
SY
1376void xen_hvm_evtchn_do_upcall(void)
1377{
1378 __xen_evtchn_do_upcall();
e46cdb66 1379}
183d03cc 1380EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1381
eb1e305f
JF
1382/* Rebind a new event channel to an existing irq. */
1383void rebind_evtchn_irq(int evtchn, int irq)
1384{
d77bbd4d
JF
1385 struct irq_info *info = info_for_irq(irq);
1386
eb1e305f
JF
1387 /* Make sure the irq is masked, since the new event channel
1388 will also be masked. */
1389 disable_irq(irq);
1390
77365948 1391 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1392
1393 /* After resume the irq<->evtchn mappings are all cleared out */
1394 BUG_ON(evtchn_to_irq[evtchn] != -1);
1395 /* Expect irq to have been bound before,
d77bbd4d
JF
1396 so there should be a proper type */
1397 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1398
9158c358 1399 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1400
77365948 1401 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1402
1403 /* new event channels are always bound to cpu 0 */
0de26520 1404 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1405
1406 /* Unmask the event channel. */
1407 enable_irq(irq);
1408}
1409
e46cdb66 1410/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1411static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1412{
1413 struct evtchn_bind_vcpu bind_vcpu;
1414 int evtchn = evtchn_from_irq(irq);
1415
be49472f
IC
1416 if (!VALID_EVTCHN(evtchn))
1417 return -1;
1418
1419 /*
1420 * Events delivered via platform PCI interrupts are always
1421 * routed to vcpu 0 and hence cannot be rebound.
1422 */
1423 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1424 return -1;
e46cdb66
JF
1425
1426 /* Send future instances of this interrupt to other vcpu. */
1427 bind_vcpu.port = evtchn;
1428 bind_vcpu.vcpu = tcpu;
1429
1430 /*
1431 * If this fails, it usually just indicates that we're dealing with a
1432 * virq or IPI channel, which don't actually need to be rebound. Ignore
1433 * it, but don't do the xenlinux-level rebind in that case.
1434 */
1435 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1436 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1437
d5dedd45
YL
1438 return 0;
1439}
e46cdb66 1440
c9e265e0
TG
1441static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1442 bool force)
e46cdb66 1443{
0de26520 1444 unsigned tcpu = cpumask_first(dest);
d5dedd45 1445
c9e265e0 1446 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1447}
1448
642e0c88
IY
1449int resend_irq_on_evtchn(unsigned int irq)
1450{
1451 int masked, evtchn = evtchn_from_irq(irq);
1452 struct shared_info *s = HYPERVISOR_shared_info;
1453
1454 if (!VALID_EVTCHN(evtchn))
1455 return 1;
1456
1457 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1458 sync_set_bit(evtchn, s->evtchn_pending);
1459 if (!masked)
1460 unmask_evtchn(evtchn);
1461
1462 return 1;
1463}
1464
c9e265e0 1465static void enable_dynirq(struct irq_data *data)
e46cdb66 1466{
c9e265e0 1467 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1468
1469 if (VALID_EVTCHN(evtchn))
1470 unmask_evtchn(evtchn);
1471}
1472
c9e265e0 1473static void disable_dynirq(struct irq_data *data)
e46cdb66 1474{
c9e265e0 1475 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1476
1477 if (VALID_EVTCHN(evtchn))
1478 mask_evtchn(evtchn);
1479}
1480
c9e265e0 1481static void ack_dynirq(struct irq_data *data)
e46cdb66 1482{
c9e265e0 1483 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1484
7e186bdd 1485 irq_move_irq(data);
e46cdb66
JF
1486
1487 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1488 clear_evtchn(evtchn);
1489}
1490
1491static void mask_ack_dynirq(struct irq_data *data)
1492{
1493 disable_dynirq(data);
1494 ack_dynirq(data);
e46cdb66
JF
1495}
1496
c9e265e0 1497static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1498{
c9e265e0 1499 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1500 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1501 int ret = 0;
1502
1503 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1504 int masked;
1505
1506 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1507 sync_set_bit(evtchn, sh->evtchn_pending);
1508 if (!masked)
1509 unmask_evtchn(evtchn);
e46cdb66
JF
1510 ret = 1;
1511 }
1512
1513 return ret;
1514}
1515
0a85226f 1516static void restore_pirqs(void)
9a069c33
SS
1517{
1518 int pirq, rc, irq, gsi;
1519 struct physdev_map_pirq map_irq;
69c358ce 1520 struct irq_info *info;
9a069c33 1521
69c358ce
IC
1522 list_for_each_entry(info, &xen_irq_list_head, list) {
1523 if (info->type != IRQT_PIRQ)
9a069c33
SS
1524 continue;
1525
69c358ce
IC
1526 pirq = info->u.pirq.pirq;
1527 gsi = info->u.pirq.gsi;
1528 irq = info->irq;
1529
9a069c33
SS
1530 /* save/restore of PT devices doesn't work, so at this point the
1531 * only devices present are GSI based emulated devices */
9a069c33
SS
1532 if (!gsi)
1533 continue;
1534
1535 map_irq.domid = DOMID_SELF;
1536 map_irq.type = MAP_PIRQ_TYPE_GSI;
1537 map_irq.index = gsi;
1538 map_irq.pirq = pirq;
1539
1540 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1541 if (rc) {
1542 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1543 gsi, irq, pirq, rc);
9158c358 1544 xen_free_irq(irq);
9a069c33
SS
1545 continue;
1546 }
1547
1548 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1549
c9e265e0 1550 __startup_pirq(irq);
9a069c33
SS
1551 }
1552}
1553
0e91398f
JF
1554static void restore_cpu_virqs(unsigned int cpu)
1555{
1556 struct evtchn_bind_virq bind_virq;
1557 int virq, irq, evtchn;
1558
1559 for (virq = 0; virq < NR_VIRQS; virq++) {
1560 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1561 continue;
1562
ced40d0f 1563 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1564
1565 /* Get a new binding from Xen. */
1566 bind_virq.virq = virq;
1567 bind_virq.vcpu = cpu;
1568 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1569 &bind_virq) != 0)
1570 BUG();
1571 evtchn = bind_virq.port;
1572
1573 /* Record the new mapping. */
3d4cfa37 1574 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1575 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1576 }
1577}
1578
1579static void restore_cpu_ipis(unsigned int cpu)
1580{
1581 struct evtchn_bind_ipi bind_ipi;
1582 int ipi, irq, evtchn;
1583
1584 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1585 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1586 continue;
1587
ced40d0f 1588 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1589
1590 /* Get a new binding from Xen. */
1591 bind_ipi.vcpu = cpu;
1592 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1593 &bind_ipi) != 0)
1594 BUG();
1595 evtchn = bind_ipi.port;
1596
1597 /* Record the new mapping. */
3d4cfa37 1598 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1599 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1600 }
1601}
1602
2d9e1e2f
JF
1603/* Clear an irq's pending state, in preparation for polling on it */
1604void xen_clear_irq_pending(int irq)
1605{
1606 int evtchn = evtchn_from_irq(irq);
1607
1608 if (VALID_EVTCHN(evtchn))
1609 clear_evtchn(evtchn);
1610}
d9a8814f 1611EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1612void xen_set_irq_pending(int irq)
1613{
1614 int evtchn = evtchn_from_irq(irq);
1615
1616 if (VALID_EVTCHN(evtchn))
1617 set_evtchn(evtchn);
1618}
1619
1620bool xen_test_irq_pending(int irq)
1621{
1622 int evtchn = evtchn_from_irq(irq);
1623 bool ret = false;
1624
1625 if (VALID_EVTCHN(evtchn))
1626 ret = test_evtchn(evtchn);
1627
1628 return ret;
1629}
1630
d9a8814f
KRW
1631/* Poll waiting for an irq to become pending with timeout. In the usual case,
1632 * the irq will be disabled so it won't deliver an interrupt. */
1633void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1634{
1635 evtchn_port_t evtchn = evtchn_from_irq(irq);
1636
1637 if (VALID_EVTCHN(evtchn)) {
1638 struct sched_poll poll;
1639
1640 poll.nr_ports = 1;
d9a8814f 1641 poll.timeout = timeout;
ff3c5362 1642 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1643
1644 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1645 BUG();
1646 }
1647}
d9a8814f
KRW
1648EXPORT_SYMBOL(xen_poll_irq_timeout);
1649/* Poll waiting for an irq to become pending. In the usual case, the
1650 * irq will be disabled so it won't deliver an interrupt. */
1651void xen_poll_irq(int irq)
1652{
1653 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1654}
2d9e1e2f 1655
c7c2c3a2
KRW
1656/* Check whether the IRQ line is shared with other guests. */
1657int xen_test_irq_shared(int irq)
1658{
1659 struct irq_info *info = info_for_irq(irq);
1660 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1661
1662 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1663 return 0;
1664 return !(irq_status.flags & XENIRQSTAT_shared);
1665}
1666EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1667
0e91398f
JF
1668void xen_irq_resume(void)
1669{
6cb6537d
IC
1670 unsigned int cpu, evtchn;
1671 struct irq_info *info;
0e91398f
JF
1672
1673 init_evtchn_cpu_bindings();
1674
1675 /* New event-channel space is not 'live' yet. */
1676 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1677 mask_evtchn(evtchn);
1678
1679 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1680 list_for_each_entry(info, &xen_irq_list_head, list)
1681 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1682
1683 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1684 evtchn_to_irq[evtchn] = -1;
1685
1686 for_each_possible_cpu(cpu) {
1687 restore_cpu_virqs(cpu);
1688 restore_cpu_ipis(cpu);
1689 }
6903591f 1690
0a85226f 1691 restore_pirqs();
0e91398f
JF
1692}
1693
e46cdb66 1694static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1695 .name = "xen-dyn",
54a353a0 1696
c9e265e0
TG
1697 .irq_disable = disable_dynirq,
1698 .irq_mask = disable_dynirq,
1699 .irq_unmask = enable_dynirq,
54a353a0 1700
7e186bdd
SS
1701 .irq_ack = ack_dynirq,
1702 .irq_mask_ack = mask_ack_dynirq,
1703
c9e265e0
TG
1704 .irq_set_affinity = set_affinity_irq,
1705 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1706};
1707
d46a78b0 1708static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1709 .name = "xen-pirq",
d46a78b0 1710
c9e265e0
TG
1711 .irq_startup = startup_pirq,
1712 .irq_shutdown = shutdown_pirq,
c9e265e0 1713 .irq_enable = enable_pirq,
c9e265e0 1714 .irq_disable = disable_pirq,
d46a78b0 1715
7e186bdd
SS
1716 .irq_mask = disable_dynirq,
1717 .irq_unmask = enable_dynirq,
1718
1719 .irq_ack = eoi_pirq,
1720 .irq_eoi = eoi_pirq,
1721 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1722
c9e265e0 1723 .irq_set_affinity = set_affinity_irq,
d46a78b0 1724
c9e265e0 1725 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1726};
1727
aaca4964 1728static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1729 .name = "xen-percpu",
aaca4964 1730
c9e265e0
TG
1731 .irq_disable = disable_dynirq,
1732 .irq_mask = disable_dynirq,
1733 .irq_unmask = enable_dynirq,
aaca4964 1734
c9e265e0 1735 .irq_ack = ack_dynirq,
aaca4964
JF
1736};
1737
38e20b07
SY
1738int xen_set_callback_via(uint64_t via)
1739{
1740 struct xen_hvm_param a;
1741 a.domid = DOMID_SELF;
1742 a.index = HVM_PARAM_CALLBACK_IRQ;
1743 a.value = via;
1744 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1745}
1746EXPORT_SYMBOL_GPL(xen_set_callback_via);
1747
ca65f9fc 1748#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1749/* Vector callbacks are better than PCI interrupts to receive event
1750 * channel notifications because we can receive vector callbacks on any
1751 * vcpu and we don't need PCI support or APIC interactions. */
1752void xen_callback_vector(void)
1753{
1754 int rc;
1755 uint64_t callback_via;
1756 if (xen_have_vector_callback) {
1757 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1758 rc = xen_set_callback_via(callback_via);
1759 if (rc) {
1760 printk(KERN_ERR "Request for Xen HVM callback vector"
1761 " failed.\n");
1762 xen_have_vector_callback = 0;
1763 return;
1764 }
1765 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1766 "enabled\n");
1767 /* in the restore case the vector has already been allocated */
1768 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1769 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1770 }
1771}
ca65f9fc
SS
1772#else
1773void xen_callback_vector(void) {}
1774#endif
38e20b07 1775
e46cdb66
JF
1776void __init xen_init_IRQ(void)
1777{
9846ff10 1778 int i, rc;
c7a3589e 1779
b21ddbf5
JF
1780 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1781 GFP_KERNEL);
9d093e29 1782 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1783 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1784 evtchn_to_irq[i] = -1;
e46cdb66
JF
1785
1786 init_evtchn_cpu_bindings();
1787
1788 /* No event channels are 'live' right now. */
1789 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1790 mask_evtchn(i);
1791
9846ff10
SS
1792 pirq_needs_eoi = pirq_needs_eoi_flag;
1793
38e20b07
SY
1794 if (xen_hvm_domain()) {
1795 xen_callback_vector();
1796 native_init_IRQ();
3942b740
SS
1797 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1798 * __acpi_register_gsi can point at the right function */
1799 pci_xen_hvm_init();
38e20b07 1800 } else {
9846ff10
SS
1801 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1802
38e20b07 1803 irq_ctx_init(smp_processor_id());
38aa66fc 1804 if (xen_initial_domain())
a0ee0567 1805 pci_xen_initial_domain();
9846ff10
SS
1806
1807 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1808 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1809 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1810 if (rc != 0) {
1811 free_page((unsigned long) pirq_eoi_map);
1812 pirq_eoi_map = NULL;
1813 } else
1814 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1815 }
e46cdb66 1816}
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