Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
38e20b07 | 34 | #include <asm/desc.h> |
e46cdb66 JF |
35 | #include <asm/ptrace.h> |
36 | #include <asm/irq.h> | |
792dc4f6 | 37 | #include <asm/idle.h> |
0794bfc7 | 38 | #include <asm/io_apic.h> |
e46cdb66 | 39 | #include <asm/sync_bitops.h> |
42a1de56 | 40 | #include <asm/xen/pci.h> |
e46cdb66 | 41 | #include <asm/xen/hypercall.h> |
8d1b8753 | 42 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 43 | |
38e20b07 SY |
44 | #include <xen/xen.h> |
45 | #include <xen/hvm.h> | |
e04d0d07 | 46 | #include <xen/xen-ops.h> |
e46cdb66 JF |
47 | #include <xen/events.h> |
48 | #include <xen/interface/xen.h> | |
49 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
50 | #include <xen/interface/hvm/hvm_op.h> |
51 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 52 | |
e46cdb66 JF |
53 | /* |
54 | * This lock protects updates to the following mapping and reference-count | |
55 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
56 | */ | |
57 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
58 | ||
59 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 60 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 61 | |
f87e4cac | 62 | /* IRQ <-> IPI mapping */ |
204fba4a | 63 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 64 | |
ced40d0f JF |
65 | /* Interrupt types. */ |
66 | enum xen_irq_type { | |
d77bbd4d | 67 | IRQT_UNBOUND = 0, |
f87e4cac JF |
68 | IRQT_PIRQ, |
69 | IRQT_VIRQ, | |
70 | IRQT_IPI, | |
71 | IRQT_EVTCHN | |
72 | }; | |
e46cdb66 | 73 | |
ced40d0f JF |
74 | /* |
75 | * Packed IRQ information: | |
76 | * type - enum xen_irq_type | |
77 | * event channel - irq->event channel mapping | |
78 | * cpu - cpu this event channel is bound to | |
79 | * index - type-specific information: | |
42a1de56 SS |
80 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
81 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
82 | * VIRQ - virq number |
83 | * IPI - IPI vector | |
84 | * EVTCHN - | |
85 | */ | |
86 | struct irq_info | |
87 | { | |
88 | enum xen_irq_type type; /* type */ | |
89 | unsigned short evtchn; /* event channel */ | |
90 | unsigned short cpu; /* cpu bound */ | |
91 | ||
92 | union { | |
93 | unsigned short virq; | |
94 | enum ipi_vector ipi; | |
95 | struct { | |
7a043f11 | 96 | unsigned short pirq; |
ced40d0f | 97 | unsigned short gsi; |
d46a78b0 JF |
98 | unsigned char vector; |
99 | unsigned char flags; | |
ced40d0f JF |
100 | } pirq; |
101 | } u; | |
102 | }; | |
d46a78b0 | 103 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 104 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 105 | |
b21ddbf5 | 106 | static struct irq_info *irq_info; |
7a043f11 | 107 | static int *pirq_to_irq; |
e46cdb66 | 108 | |
b21ddbf5 | 109 | static int *evtchn_to_irq; |
c7a3589e MT |
110 | struct cpu_evtchn_s { |
111 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
112 | }; | |
3b32f574 JF |
113 | |
114 | static __initdata struct cpu_evtchn_s init_evtchn_mask = { | |
115 | .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul, | |
116 | }; | |
117 | static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask; | |
118 | ||
c7a3589e MT |
119 | static inline unsigned long *cpu_evtchn_mask(int cpu) |
120 | { | |
121 | return cpu_evtchn_mask_p[cpu].bits; | |
122 | } | |
e46cdb66 | 123 | |
e46cdb66 JF |
124 | /* Xen will never allocate port zero for any purpose. */ |
125 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
126 | ||
e46cdb66 | 127 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 128 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 129 | static struct irq_chip xen_pirq_chip; |
e46cdb66 JF |
130 | |
131 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
132 | static struct irq_info mk_unbound_info(void) |
133 | { | |
134 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
135 | } | |
136 | ||
137 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
138 | { | |
90af9514 IC |
139 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
140 | .cpu = 0 }; | |
ced40d0f JF |
141 | } |
142 | ||
143 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 144 | { |
ced40d0f | 145 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 146 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
147 | } |
148 | ||
149 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
150 | { | |
151 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 152 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
153 | } |
154 | ||
7a043f11 | 155 | static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq, |
ced40d0f JF |
156 | unsigned short gsi, unsigned short vector) |
157 | { | |
158 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
7a043f11 SS |
159 | .cpu = 0, |
160 | .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } }; | |
e46cdb66 JF |
161 | } |
162 | ||
163 | /* | |
164 | * Accessors for packed IRQ information. | |
165 | */ | |
ced40d0f | 166 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 167 | { |
ced40d0f | 168 | return &irq_info[irq]; |
e46cdb66 JF |
169 | } |
170 | ||
ced40d0f | 171 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 172 | { |
ced40d0f | 173 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
174 | } |
175 | ||
d4c04536 IC |
176 | unsigned irq_from_evtchn(unsigned int evtchn) |
177 | { | |
178 | return evtchn_to_irq[evtchn]; | |
179 | } | |
180 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
181 | ||
ced40d0f | 182 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 183 | { |
ced40d0f JF |
184 | struct irq_info *info = info_for_irq(irq); |
185 | ||
186 | BUG_ON(info == NULL); | |
187 | BUG_ON(info->type != IRQT_IPI); | |
188 | ||
189 | return info->u.ipi; | |
190 | } | |
191 | ||
192 | static unsigned virq_from_irq(unsigned irq) | |
193 | { | |
194 | struct irq_info *info = info_for_irq(irq); | |
195 | ||
196 | BUG_ON(info == NULL); | |
197 | BUG_ON(info->type != IRQT_VIRQ); | |
198 | ||
199 | return info->u.virq; | |
200 | } | |
201 | ||
7a043f11 SS |
202 | static unsigned pirq_from_irq(unsigned irq) |
203 | { | |
204 | struct irq_info *info = info_for_irq(irq); | |
205 | ||
206 | BUG_ON(info == NULL); | |
207 | BUG_ON(info->type != IRQT_PIRQ); | |
208 | ||
209 | return info->u.pirq.pirq; | |
210 | } | |
211 | ||
ced40d0f JF |
212 | static unsigned gsi_from_irq(unsigned irq) |
213 | { | |
214 | struct irq_info *info = info_for_irq(irq); | |
215 | ||
216 | BUG_ON(info == NULL); | |
217 | BUG_ON(info->type != IRQT_PIRQ); | |
218 | ||
219 | return info->u.pirq.gsi; | |
220 | } | |
221 | ||
222 | static unsigned vector_from_irq(unsigned irq) | |
223 | { | |
224 | struct irq_info *info = info_for_irq(irq); | |
225 | ||
226 | BUG_ON(info == NULL); | |
227 | BUG_ON(info->type != IRQT_PIRQ); | |
228 | ||
229 | return info->u.pirq.vector; | |
230 | } | |
231 | ||
232 | static enum xen_irq_type type_from_irq(unsigned irq) | |
233 | { | |
234 | return info_for_irq(irq)->type; | |
235 | } | |
236 | ||
237 | static unsigned cpu_from_irq(unsigned irq) | |
238 | { | |
239 | return info_for_irq(irq)->cpu; | |
240 | } | |
241 | ||
242 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
243 | { | |
244 | int irq = evtchn_to_irq[evtchn]; | |
245 | unsigned ret = 0; | |
246 | ||
247 | if (irq != -1) | |
248 | ret = cpu_from_irq(irq); | |
249 | ||
250 | return ret; | |
e46cdb66 JF |
251 | } |
252 | ||
d46a78b0 JF |
253 | static bool pirq_needs_eoi(unsigned irq) |
254 | { | |
255 | struct irq_info *info = info_for_irq(irq); | |
256 | ||
257 | BUG_ON(info->type != IRQT_PIRQ); | |
258 | ||
259 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
260 | } | |
261 | ||
e46cdb66 JF |
262 | static inline unsigned long active_evtchns(unsigned int cpu, |
263 | struct shared_info *sh, | |
264 | unsigned int idx) | |
265 | { | |
266 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 267 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
268 | ~sh->evtchn_mask[idx]); |
269 | } | |
270 | ||
271 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
272 | { | |
273 | int irq = evtchn_to_irq[chn]; | |
274 | ||
275 | BUG_ON(irq == -1); | |
276 | #ifdef CONFIG_SMP | |
7f7ace0c | 277 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
278 | #endif |
279 | ||
e0419564 JF |
280 | clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
281 | set_bit(chn, cpu_evtchn_mask(cpu)); | |
e46cdb66 | 282 | |
ced40d0f | 283 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
284 | } |
285 | ||
286 | static void init_evtchn_cpu_bindings(void) | |
287 | { | |
1c6969ec | 288 | int i; |
e46cdb66 | 289 | #ifdef CONFIG_SMP |
10e58084 | 290 | struct irq_desc *desc; |
10e58084 | 291 | |
e46cdb66 | 292 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 293 | for_each_irq_desc(i, desc) { |
7f7ace0c | 294 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 295 | } |
e46cdb66 JF |
296 | #endif |
297 | ||
1c6969ec JB |
298 | for_each_possible_cpu(i) |
299 | memset(cpu_evtchn_mask(i), | |
300 | (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s)); | |
301 | ||
e46cdb66 JF |
302 | } |
303 | ||
e46cdb66 JF |
304 | static inline void clear_evtchn(int port) |
305 | { | |
306 | struct shared_info *s = HYPERVISOR_shared_info; | |
307 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
308 | } | |
309 | ||
310 | static inline void set_evtchn(int port) | |
311 | { | |
312 | struct shared_info *s = HYPERVISOR_shared_info; | |
313 | sync_set_bit(port, &s->evtchn_pending[0]); | |
314 | } | |
315 | ||
168d2f46 JF |
316 | static inline int test_evtchn(int port) |
317 | { | |
318 | struct shared_info *s = HYPERVISOR_shared_info; | |
319 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
320 | } | |
321 | ||
e46cdb66 JF |
322 | |
323 | /** | |
324 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
325 | * @irq: irq of event channel to send event to | |
326 | * | |
327 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
328 | * save/restore. Notifications on a broken connection are silently | |
329 | * dropped. | |
330 | */ | |
331 | void notify_remote_via_irq(int irq) | |
332 | { | |
333 | int evtchn = evtchn_from_irq(irq); | |
334 | ||
335 | if (VALID_EVTCHN(evtchn)) | |
336 | notify_remote_via_evtchn(evtchn); | |
337 | } | |
338 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
339 | ||
340 | static void mask_evtchn(int port) | |
341 | { | |
342 | struct shared_info *s = HYPERVISOR_shared_info; | |
343 | sync_set_bit(port, &s->evtchn_mask[0]); | |
344 | } | |
345 | ||
346 | static void unmask_evtchn(int port) | |
347 | { | |
348 | struct shared_info *s = HYPERVISOR_shared_info; | |
349 | unsigned int cpu = get_cpu(); | |
350 | ||
351 | BUG_ON(!irqs_disabled()); | |
352 | ||
353 | /* Slow path (hypercall) if this is a non-local port. */ | |
354 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
355 | struct evtchn_unmask unmask = { .port = port }; | |
356 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
357 | } else { | |
358 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
359 | ||
360 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
361 | ||
362 | /* | |
363 | * The following is basically the equivalent of | |
364 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
365 | * the interrupt edge' if the channel is masked. | |
366 | */ | |
367 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
368 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
369 | &vcpu_info->evtchn_pending_sel)) | |
370 | vcpu_info->evtchn_upcall_pending = 1; | |
371 | } | |
372 | ||
373 | put_cpu(); | |
374 | } | |
375 | ||
0794bfc7 KRW |
376 | static int get_nr_hw_irqs(void) |
377 | { | |
378 | int ret = 1; | |
379 | ||
380 | #ifdef CONFIG_X86_IO_APIC | |
381 | ret = get_nr_irqs_gsi(); | |
382 | #endif | |
383 | ||
384 | return ret; | |
385 | } | |
386 | ||
e5fc7345 | 387 | static int find_unbound_pirq(int type) |
7a043f11 | 388 | { |
e5fc7345 SS |
389 | int rc, i; |
390 | struct physdev_get_free_pirq op_get_free_pirq; | |
391 | op_get_free_pirq.type = type; | |
392 | ||
393 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); | |
394 | if (!rc) | |
395 | return op_get_free_pirq.pirq; | |
396 | ||
397 | for (i = 0; i < nr_irqs; i++) { | |
7a043f11 SS |
398 | if (pirq_to_irq[i] < 0) |
399 | return i; | |
400 | } | |
401 | return -1; | |
402 | } | |
403 | ||
e46cdb66 JF |
404 | static int find_unbound_irq(void) |
405 | { | |
77dff1c7 TG |
406 | struct irq_data *data; |
407 | int irq, res; | |
d1b758eb KRW |
408 | int bottom = get_nr_hw_irqs(); |
409 | int top = nr_irqs-1; | |
e46cdb66 | 410 | |
d1b758eb | 411 | if (bottom == nr_irqs) |
3a69e916 KRW |
412 | goto no_irqs; |
413 | ||
d1b758eb KRW |
414 | /* This loop starts from the top of IRQ space and goes down. |
415 | * We need this b/c if we have a PCI device in a Xen PV guest | |
416 | * we do not have an IO-APIC (though the backend might have them) | |
417 | * mapped in. To not have a collision of physical IRQs with the Xen | |
418 | * event channels start at the top of the IRQ space for virtual IRQs. | |
419 | */ | |
420 | for (irq = top; irq > bottom; irq--) { | |
77dff1c7 | 421 | data = irq_get_irq_data(irq); |
d1b758eb | 422 | /* only 15->0 have init'd desc; handle irq > 16 */ |
77dff1c7 | 423 | if (!data) |
99ad198c | 424 | break; |
77dff1c7 | 425 | if (data->chip == &no_irq_chip) |
99ad198c | 426 | break; |
77dff1c7 | 427 | if (data->chip != &xen_dynamic_chip) |
99ad198c | 428 | continue; |
d77bbd4d | 429 | if (irq_info[irq].type == IRQT_UNBOUND) |
77dff1c7 | 430 | return irq; |
99ad198c | 431 | } |
e46cdb66 | 432 | |
d1b758eb | 433 | if (irq == bottom) |
3a69e916 | 434 | goto no_irqs; |
e46cdb66 | 435 | |
29dcbc5c | 436 | res = irq_alloc_desc_at(irq, -1); |
6f8a0ed4 | 437 | |
77dff1c7 TG |
438 | if (WARN_ON(res != irq)) |
439 | return -1; | |
ced40d0f | 440 | |
e46cdb66 | 441 | return irq; |
3a69e916 KRW |
442 | |
443 | no_irqs: | |
444 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 JF |
445 | } |
446 | ||
d46a78b0 JF |
447 | static bool identity_mapped_irq(unsigned irq) |
448 | { | |
0794bfc7 KRW |
449 | /* identity map all the hardware irqs */ |
450 | return irq < get_nr_hw_irqs(); | |
d46a78b0 JF |
451 | } |
452 | ||
453 | static void pirq_unmask_notify(int irq) | |
454 | { | |
7a043f11 | 455 | struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) }; |
d46a78b0 JF |
456 | |
457 | if (unlikely(pirq_needs_eoi(irq))) { | |
458 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
459 | WARN_ON(rc); | |
460 | } | |
461 | } | |
462 | ||
463 | static void pirq_query_unmask(int irq) | |
464 | { | |
465 | struct physdev_irq_status_query irq_status; | |
466 | struct irq_info *info = info_for_irq(irq); | |
467 | ||
468 | BUG_ON(info->type != IRQT_PIRQ); | |
469 | ||
7a043f11 | 470 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
471 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
472 | irq_status.flags = 0; | |
473 | ||
474 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
475 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
476 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
477 | } | |
478 | ||
479 | static bool probing_irq(int irq) | |
480 | { | |
481 | struct irq_desc *desc = irq_to_desc(irq); | |
482 | ||
483 | return desc && desc->action == NULL; | |
484 | } | |
485 | ||
486 | static unsigned int startup_pirq(unsigned int irq) | |
487 | { | |
488 | struct evtchn_bind_pirq bind_pirq; | |
489 | struct irq_info *info = info_for_irq(irq); | |
490 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 491 | int rc; |
d46a78b0 JF |
492 | |
493 | BUG_ON(info->type != IRQT_PIRQ); | |
494 | ||
495 | if (VALID_EVTCHN(evtchn)) | |
496 | goto out; | |
497 | ||
7a043f11 | 498 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 499 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
500 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
501 | BIND_PIRQ__WILL_SHARE : 0; | |
502 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
503 | if (rc != 0) { | |
d46a78b0 JF |
504 | if (!probing_irq(irq)) |
505 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
506 | irq); | |
507 | return 0; | |
508 | } | |
509 | evtchn = bind_pirq.port; | |
510 | ||
511 | pirq_query_unmask(irq); | |
512 | ||
513 | evtchn_to_irq[evtchn] = irq; | |
514 | bind_evtchn_to_cpu(evtchn, 0); | |
515 | info->evtchn = evtchn; | |
516 | ||
517 | out: | |
518 | unmask_evtchn(evtchn); | |
519 | pirq_unmask_notify(irq); | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static void shutdown_pirq(unsigned int irq) | |
525 | { | |
526 | struct evtchn_close close; | |
527 | struct irq_info *info = info_for_irq(irq); | |
528 | int evtchn = evtchn_from_irq(irq); | |
529 | ||
530 | BUG_ON(info->type != IRQT_PIRQ); | |
531 | ||
532 | if (!VALID_EVTCHN(evtchn)) | |
533 | return; | |
534 | ||
535 | mask_evtchn(evtchn); | |
536 | ||
537 | close.port = evtchn; | |
538 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
539 | BUG(); | |
540 | ||
541 | bind_evtchn_to_cpu(evtchn, 0); | |
542 | evtchn_to_irq[evtchn] = -1; | |
543 | info->evtchn = 0; | |
544 | } | |
545 | ||
546 | static void enable_pirq(unsigned int irq) | |
547 | { | |
548 | startup_pirq(irq); | |
549 | } | |
550 | ||
551 | static void disable_pirq(unsigned int irq) | |
552 | { | |
553 | } | |
554 | ||
555 | static void ack_pirq(unsigned int irq) | |
556 | { | |
557 | int evtchn = evtchn_from_irq(irq); | |
558 | ||
559 | move_native_irq(irq); | |
560 | ||
561 | if (VALID_EVTCHN(evtchn)) { | |
562 | mask_evtchn(evtchn); | |
563 | clear_evtchn(evtchn); | |
564 | } | |
565 | } | |
566 | ||
567 | static void end_pirq(unsigned int irq) | |
568 | { | |
569 | int evtchn = evtchn_from_irq(irq); | |
570 | struct irq_desc *desc = irq_to_desc(irq); | |
571 | ||
572 | if (WARN_ON(!desc)) | |
573 | return; | |
574 | ||
575 | if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) == | |
576 | (IRQ_DISABLED|IRQ_PENDING)) { | |
577 | shutdown_pirq(irq); | |
578 | } else if (VALID_EVTCHN(evtchn)) { | |
579 | unmask_evtchn(evtchn); | |
580 | pirq_unmask_notify(irq); | |
581 | } | |
582 | } | |
583 | ||
584 | static int find_irq_by_gsi(unsigned gsi) | |
585 | { | |
586 | int irq; | |
587 | ||
b21ddbf5 | 588 | for (irq = 0; irq < nr_irqs; irq++) { |
d46a78b0 JF |
589 | struct irq_info *info = info_for_irq(irq); |
590 | ||
591 | if (info == NULL || info->type != IRQT_PIRQ) | |
592 | continue; | |
593 | ||
594 | if (gsi_from_irq(irq) == gsi) | |
595 | return irq; | |
596 | } | |
597 | ||
598 | return -1; | |
599 | } | |
600 | ||
7a043f11 SS |
601 | int xen_allocate_pirq(unsigned gsi, int shareable, char *name) |
602 | { | |
603 | return xen_map_pirq_gsi(gsi, gsi, shareable, name); | |
604 | } | |
605 | ||
606 | /* xen_map_pirq_gsi might allocate irqs from the top down, as a | |
3a69e916 KRW |
607 | * consequence don't assume that the irq number returned has a low value |
608 | * or can be used as a pirq number unless you know otherwise. | |
609 | * | |
7a043f11 | 610 | * One notable exception is when xen_map_pirq_gsi is called passing an |
3a69e916 | 611 | * hardware gsi as argument, in that case the irq number returned |
7a043f11 SS |
612 | * matches the gsi number passed as second argument. |
613 | * | |
614 | * Note: We don't assign an event channel until the irq actually started | |
615 | * up. Return an existing irq if we've already got one for the gsi. | |
d46a78b0 | 616 | */ |
7a043f11 | 617 | int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name) |
d46a78b0 | 618 | { |
7a043f11 | 619 | int irq = 0; |
d46a78b0 JF |
620 | struct physdev_irq irq_op; |
621 | ||
622 | spin_lock(&irq_mapping_update_lock); | |
623 | ||
e5fc7345 | 624 | if ((pirq > nr_irqs) || (gsi > nr_irqs)) { |
01557baf | 625 | printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n", |
e5fc7345 SS |
626 | pirq > nr_irqs ? "pirq" :"", |
627 | gsi > nr_irqs ? "gsi" : ""); | |
01557baf SS |
628 | goto out; |
629 | } | |
630 | ||
d46a78b0 JF |
631 | irq = find_irq_by_gsi(gsi); |
632 | if (irq != -1) { | |
7a043f11 | 633 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
634 | irq, gsi); |
635 | goto out; /* XXX need refcount? */ | |
636 | } | |
637 | ||
b5401a96 AN |
638 | /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore |
639 | * we are using the !xen_initial_domain() to drop in the function.*/ | |
3942b740 SS |
640 | if (identity_mapped_irq(gsi) || (!xen_initial_domain() && |
641 | xen_pv_domain())) { | |
d46a78b0 | 642 | irq = gsi; |
29dcbc5c | 643 | irq_alloc_desc_at(irq, -1); |
d46a78b0 JF |
644 | } else |
645 | irq = find_unbound_irq(); | |
646 | ||
647 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
1a60d05f | 648 | handle_level_irq, name); |
d46a78b0 JF |
649 | |
650 | irq_op.irq = irq; | |
b5401a96 AN |
651 | irq_op.vector = 0; |
652 | ||
653 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
654 | * driver provides a PCI bus that does the call to do exactly | |
655 | * this in the priv domain. */ | |
656 | if (xen_initial_domain() && | |
657 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
2c52f8d3 | 658 | irq_free_desc(irq); |
d46a78b0 JF |
659 | irq = -ENOSPC; |
660 | goto out; | |
661 | } | |
662 | ||
7a043f11 | 663 | irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector); |
15ebbb82 | 664 | irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0; |
7a043f11 | 665 | pirq_to_irq[pirq] = irq; |
d46a78b0 JF |
666 | |
667 | out: | |
668 | spin_unlock(&irq_mapping_update_lock); | |
669 | ||
670 | return irq; | |
671 | } | |
672 | ||
f731e3ef QH |
673 | #ifdef CONFIG_PCI_MSI |
674 | #include <linux/msi.h> | |
675 | #include "../pci/msi.h" | |
676 | ||
af42b8d1 | 677 | void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc) |
809f9267 SS |
678 | { |
679 | spin_lock(&irq_mapping_update_lock); | |
680 | ||
af42b8d1 SS |
681 | if (alloc & XEN_ALLOC_IRQ) { |
682 | *irq = find_unbound_irq(); | |
683 | if (*irq == -1) | |
684 | goto out; | |
685 | } | |
809f9267 | 686 | |
af42b8d1 SS |
687 | if (alloc & XEN_ALLOC_PIRQ) { |
688 | *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI); | |
689 | if (*pirq == -1) | |
690 | goto out; | |
691 | } | |
809f9267 SS |
692 | |
693 | set_irq_chip_and_handler_name(*irq, &xen_pirq_chip, | |
694 | handle_level_irq, name); | |
695 | ||
696 | irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0); | |
697 | pirq_to_irq[*pirq] = *irq; | |
698 | ||
699 | out: | |
700 | spin_unlock(&irq_mapping_update_lock); | |
701 | } | |
702 | ||
f731e3ef QH |
703 | int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type) |
704 | { | |
705 | int irq = -1; | |
706 | struct physdev_map_pirq map_irq; | |
707 | int rc; | |
708 | int pos; | |
709 | u32 table_offset, bir; | |
710 | ||
711 | memset(&map_irq, 0, sizeof(map_irq)); | |
712 | map_irq.domid = DOMID_SELF; | |
713 | map_irq.type = MAP_PIRQ_TYPE_MSI; | |
714 | map_irq.index = -1; | |
715 | map_irq.pirq = -1; | |
716 | map_irq.bus = dev->bus->number; | |
717 | map_irq.devfn = dev->devfn; | |
718 | ||
719 | if (type == PCI_CAP_ID_MSIX) { | |
720 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
721 | ||
722 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
723 | &table_offset); | |
724 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
725 | ||
726 | map_irq.table_base = pci_resource_start(dev, bir); | |
727 | map_irq.entry_nr = msidesc->msi_attrib.entry_nr; | |
728 | } | |
729 | ||
730 | spin_lock(&irq_mapping_update_lock); | |
731 | ||
732 | irq = find_unbound_irq(); | |
733 | ||
734 | if (irq == -1) | |
735 | goto out; | |
736 | ||
737 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
738 | if (rc) { | |
739 | printk(KERN_WARNING "xen map irq failed %d\n", rc); | |
740 | ||
741 | irq_free_desc(irq); | |
742 | ||
743 | irq = -1; | |
744 | goto out; | |
745 | } | |
746 | irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index); | |
747 | ||
748 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
749 | handle_level_irq, | |
750 | (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi"); | |
751 | ||
752 | out: | |
753 | spin_unlock(&irq_mapping_update_lock); | |
754 | return irq; | |
755 | } | |
756 | #endif | |
757 | ||
b5401a96 AN |
758 | int xen_destroy_irq(int irq) |
759 | { | |
760 | struct irq_desc *desc; | |
38aa66fc JF |
761 | struct physdev_unmap_pirq unmap_irq; |
762 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
763 | int rc = -ENOENT; |
764 | ||
765 | spin_lock(&irq_mapping_update_lock); | |
766 | ||
767 | desc = irq_to_desc(irq); | |
768 | if (!desc) | |
769 | goto out; | |
770 | ||
38aa66fc | 771 | if (xen_initial_domain()) { |
12334715 | 772 | unmap_irq.pirq = info->u.pirq.pirq; |
38aa66fc JF |
773 | unmap_irq.domid = DOMID_SELF; |
774 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); | |
775 | if (rc) { | |
776 | printk(KERN_WARNING "unmap irq failed %d\n", rc); | |
777 | goto out; | |
778 | } | |
af42b8d1 | 779 | pirq_to_irq[info->u.pirq.pirq] = -1; |
38aa66fc | 780 | } |
b5401a96 AN |
781 | irq_info[irq] = mk_unbound_info(); |
782 | ||
2c52f8d3 | 783 | irq_free_desc(irq); |
b5401a96 AN |
784 | |
785 | out: | |
786 | spin_unlock(&irq_mapping_update_lock); | |
787 | return rc; | |
788 | } | |
789 | ||
d46a78b0 JF |
790 | int xen_vector_from_irq(unsigned irq) |
791 | { | |
792 | return vector_from_irq(irq); | |
793 | } | |
794 | ||
795 | int xen_gsi_from_irq(unsigned irq) | |
796 | { | |
797 | return gsi_from_irq(irq); | |
e46cdb66 JF |
798 | } |
799 | ||
af42b8d1 SS |
800 | int xen_irq_from_pirq(unsigned pirq) |
801 | { | |
802 | return pirq_to_irq[pirq]; | |
803 | } | |
804 | ||
b536b4b9 | 805 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
806 | { |
807 | int irq; | |
808 | ||
809 | spin_lock(&irq_mapping_update_lock); | |
810 | ||
811 | irq = evtchn_to_irq[evtchn]; | |
812 | ||
813 | if (irq == -1) { | |
814 | irq = find_unbound_irq(); | |
815 | ||
e46cdb66 | 816 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
3588fe2e | 817 | handle_fasteoi_irq, "event"); |
e46cdb66 JF |
818 | |
819 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 820 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
821 | } |
822 | ||
e46cdb66 JF |
823 | spin_unlock(&irq_mapping_update_lock); |
824 | ||
825 | return irq; | |
826 | } | |
b536b4b9 | 827 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 828 | |
f87e4cac JF |
829 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
830 | { | |
831 | struct evtchn_bind_ipi bind_ipi; | |
832 | int evtchn, irq; | |
833 | ||
834 | spin_lock(&irq_mapping_update_lock); | |
835 | ||
836 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 837 | |
f87e4cac JF |
838 | if (irq == -1) { |
839 | irq = find_unbound_irq(); | |
840 | if (irq < 0) | |
841 | goto out; | |
842 | ||
aaca4964 JF |
843 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
844 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
845 | |
846 | bind_ipi.vcpu = cpu; | |
847 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
848 | &bind_ipi) != 0) | |
849 | BUG(); | |
850 | evtchn = bind_ipi.port; | |
851 | ||
852 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 853 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
854 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
855 | ||
856 | bind_evtchn_to_cpu(evtchn, cpu); | |
857 | } | |
858 | ||
f87e4cac JF |
859 | out: |
860 | spin_unlock(&irq_mapping_update_lock); | |
861 | return irq; | |
862 | } | |
863 | ||
864 | ||
4fe7d5a7 | 865 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
866 | { |
867 | struct evtchn_bind_virq bind_virq; | |
868 | int evtchn, irq; | |
869 | ||
870 | spin_lock(&irq_mapping_update_lock); | |
871 | ||
872 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
873 | ||
874 | if (irq == -1) { | |
a52521f1 JF |
875 | irq = find_unbound_irq(); |
876 | ||
877 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, | |
878 | handle_percpu_irq, "virq"); | |
879 | ||
e46cdb66 JF |
880 | bind_virq.virq = virq; |
881 | bind_virq.vcpu = cpu; | |
882 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
883 | &bind_virq) != 0) | |
884 | BUG(); | |
885 | evtchn = bind_virq.port; | |
886 | ||
e46cdb66 | 887 | evtchn_to_irq[evtchn] = irq; |
ced40d0f | 888 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
889 | |
890 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
891 | ||
892 | bind_evtchn_to_cpu(evtchn, cpu); | |
893 | } | |
894 | ||
e46cdb66 JF |
895 | spin_unlock(&irq_mapping_update_lock); |
896 | ||
897 | return irq; | |
898 | } | |
899 | ||
900 | static void unbind_from_irq(unsigned int irq) | |
901 | { | |
902 | struct evtchn_close close; | |
903 | int evtchn = evtchn_from_irq(irq); | |
904 | ||
905 | spin_lock(&irq_mapping_update_lock); | |
906 | ||
d77bbd4d | 907 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
908 | close.port = evtchn; |
909 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
910 | BUG(); | |
911 | ||
912 | switch (type_from_irq(irq)) { | |
913 | case IRQT_VIRQ: | |
914 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 915 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 916 | break; |
d68d82af AN |
917 | case IRQT_IPI: |
918 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 919 | [ipi_from_irq(irq)] = -1; |
d68d82af | 920 | break; |
e46cdb66 JF |
921 | default: |
922 | break; | |
923 | } | |
924 | ||
925 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
926 | bind_evtchn_to_cpu(evtchn, 0); | |
927 | ||
928 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
929 | } |
930 | ||
931 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 932 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 933 | |
77dff1c7 | 934 | irq_free_desc(irq); |
e46cdb66 JF |
935 | } |
936 | ||
937 | spin_unlock(&irq_mapping_update_lock); | |
938 | } | |
939 | ||
940 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 941 | irq_handler_t handler, |
e46cdb66 JF |
942 | unsigned long irqflags, |
943 | const char *devname, void *dev_id) | |
944 | { | |
945 | unsigned int irq; | |
946 | int retval; | |
947 | ||
948 | irq = bind_evtchn_to_irq(evtchn); | |
949 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
950 | if (retval != 0) { | |
951 | unbind_from_irq(irq); | |
952 | return retval; | |
953 | } | |
954 | ||
955 | return irq; | |
956 | } | |
957 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
958 | ||
959 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 960 | irq_handler_t handler, |
e46cdb66 JF |
961 | unsigned long irqflags, const char *devname, void *dev_id) |
962 | { | |
963 | unsigned int irq; | |
964 | int retval; | |
965 | ||
966 | irq = bind_virq_to_irq(virq, cpu); | |
967 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
968 | if (retval != 0) { | |
969 | unbind_from_irq(irq); | |
970 | return retval; | |
971 | } | |
972 | ||
973 | return irq; | |
974 | } | |
975 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
976 | ||
f87e4cac JF |
977 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
978 | unsigned int cpu, | |
979 | irq_handler_t handler, | |
980 | unsigned long irqflags, | |
981 | const char *devname, | |
982 | void *dev_id) | |
983 | { | |
984 | int irq, retval; | |
985 | ||
986 | irq = bind_ipi_to_irq(ipi, cpu); | |
987 | if (irq < 0) | |
988 | return irq; | |
989 | ||
4877c737 | 990 | irqflags |= IRQF_NO_SUSPEND; |
f87e4cac JF |
991 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
992 | if (retval != 0) { | |
993 | unbind_from_irq(irq); | |
994 | return retval; | |
995 | } | |
996 | ||
997 | return irq; | |
998 | } | |
999 | ||
e46cdb66 JF |
1000 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1001 | { | |
1002 | free_irq(irq, dev_id); | |
1003 | unbind_from_irq(irq); | |
1004 | } | |
1005 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1006 | ||
f87e4cac JF |
1007 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1008 | { | |
1009 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
1010 | BUG_ON(irq < 0); | |
1011 | notify_remote_via_irq(irq); | |
1012 | } | |
1013 | ||
ee523ca1 JF |
1014 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
1015 | { | |
1016 | struct shared_info *sh = HYPERVISOR_shared_info; | |
1017 | int cpu = smp_processor_id(); | |
cb52e6d9 | 1018 | unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu); |
ee523ca1 JF |
1019 | int i; |
1020 | unsigned long flags; | |
1021 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 1022 | struct vcpu_info *v; |
ee523ca1 JF |
1023 | |
1024 | spin_lock_irqsave(&debug_lock, flags); | |
1025 | ||
cb52e6d9 | 1026 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
1027 | |
1028 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
1029 | int pending; |
1030 | v = per_cpu(xen_vcpu, i); | |
1031 | pending = (get_irq_regs() && i == cpu) | |
1032 | ? xen_irqs_disabled(get_irq_regs()) | |
1033 | : v->evtchn_upcall_mask; | |
1034 | printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i, | |
1035 | pending, v->evtchn_upcall_pending, | |
1036 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
1037 | v->evtchn_pending_sel); | |
1038 | } | |
1039 | v = per_cpu(xen_vcpu, cpu); | |
1040 | ||
1041 | printk("\npending:\n "); | |
1042 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
1043 | printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2, | |
1044 | sh->evtchn_pending[i], | |
1045 | i % 8 == 0 ? "\n " : " "); | |
1046 | printk("\nglobal mask:\n "); | |
1047 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1048 | printk("%0*lx%s", | |
1049 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
1050 | sh->evtchn_mask[i], | |
1051 | i % 8 == 0 ? "\n " : " "); | |
1052 | ||
1053 | printk("\nglobally unmasked:\n "); | |
1054 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1055 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1056 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
1057 | i % 8 == 0 ? "\n " : " "); | |
1058 | ||
1059 | printk("\nlocal cpu%d mask:\n ", cpu); | |
1060 | for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--) | |
1061 | printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2), | |
1062 | cpu_evtchn[i], | |
1063 | i % 8 == 0 ? "\n " : " "); | |
1064 | ||
1065 | printk("\nlocally unmasked:\n "); | |
1066 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
1067 | unsigned long pending = sh->evtchn_pending[i] | |
1068 | & ~sh->evtchn_mask[i] | |
1069 | & cpu_evtchn[i]; | |
1070 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1071 | pending, i % 8 == 0 ? "\n " : " "); | |
ee523ca1 | 1072 | } |
ee523ca1 JF |
1073 | |
1074 | printk("\npending list:\n"); | |
cb52e6d9 | 1075 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
ee523ca1 | 1076 | if (sync_test_bit(i, sh->evtchn_pending)) { |
cb52e6d9 IC |
1077 | int word_idx = i / BITS_PER_LONG; |
1078 | printk(" %d: event %d -> irq %d%s%s%s\n", | |
ced40d0f | 1079 | cpu_from_evtchn(i), i, |
cb52e6d9 IC |
1080 | evtchn_to_irq[i], |
1081 | sync_test_bit(word_idx, &v->evtchn_pending_sel) | |
1082 | ? "" : " l2-clear", | |
1083 | !sync_test_bit(i, sh->evtchn_mask) | |
1084 | ? "" : " globally-masked", | |
1085 | sync_test_bit(i, cpu_evtchn) | |
1086 | ? "" : " locally-masked"); | |
ee523ca1 JF |
1087 | } |
1088 | } | |
1089 | ||
1090 | spin_unlock_irqrestore(&debug_lock, flags); | |
1091 | ||
1092 | return IRQ_HANDLED; | |
1093 | } | |
1094 | ||
245b2e70 TH |
1095 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1096 | ||
e46cdb66 JF |
1097 | /* |
1098 | * Search the CPUs pending events bitmasks. For each one found, map | |
1099 | * the event number to an irq, and feed it into do_IRQ() for | |
1100 | * handling. | |
1101 | * | |
1102 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1103 | * a bitset of words which contain pending event bits. The second | |
1104 | * level is a bitset of pending events themselves. | |
1105 | */ | |
38e20b07 | 1106 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
1107 | { |
1108 | int cpu = get_cpu(); | |
1109 | struct shared_info *s = HYPERVISOR_shared_info; | |
1110 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be | 1111 | unsigned count; |
e46cdb66 | 1112 | |
229664be JF |
1113 | do { |
1114 | unsigned long pending_words; | |
e46cdb66 | 1115 | |
229664be | 1116 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1117 | |
245b2e70 | 1118 | if (__get_cpu_var(xed_nesting_count)++) |
229664be | 1119 | goto out; |
e46cdb66 | 1120 | |
e849c3e9 IY |
1121 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
1122 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 1123 | wmb(); |
e849c3e9 | 1124 | #endif |
229664be JF |
1125 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
1126 | while (pending_words != 0) { | |
1127 | unsigned long pending_bits; | |
1128 | int word_idx = __ffs(pending_words); | |
1129 | pending_words &= ~(1UL << word_idx); | |
1130 | ||
1131 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
1132 | int bit_idx = __ffs(pending_bits); | |
1133 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1134 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 1135 | struct irq_desc *desc; |
229664be | 1136 | |
3588fe2e JF |
1137 | mask_evtchn(port); |
1138 | clear_evtchn(port); | |
1139 | ||
ca4dbc66 EB |
1140 | if (irq != -1) { |
1141 | desc = irq_to_desc(irq); | |
1142 | if (desc) | |
1143 | generic_handle_irq_desc(irq, desc); | |
1144 | } | |
e46cdb66 JF |
1145 | } |
1146 | } | |
e46cdb66 | 1147 | |
229664be JF |
1148 | BUG_ON(!irqs_disabled()); |
1149 | ||
245b2e70 TH |
1150 | count = __get_cpu_var(xed_nesting_count); |
1151 | __get_cpu_var(xed_nesting_count) = 0; | |
183d03cc | 1152 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1153 | |
1154 | out: | |
38e20b07 SY |
1155 | |
1156 | put_cpu(); | |
1157 | } | |
1158 | ||
1159 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1160 | { | |
1161 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1162 | ||
1163 | exit_idle(); | |
1164 | irq_enter(); | |
1165 | ||
1166 | __xen_evtchn_do_upcall(); | |
1167 | ||
3445a8fd JF |
1168 | irq_exit(); |
1169 | set_irq_regs(old_regs); | |
38e20b07 | 1170 | } |
3445a8fd | 1171 | |
38e20b07 SY |
1172 | void xen_hvm_evtchn_do_upcall(void) |
1173 | { | |
1174 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1175 | } |
183d03cc | 1176 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1177 | |
eb1e305f JF |
1178 | /* Rebind a new event channel to an existing irq. */ |
1179 | void rebind_evtchn_irq(int evtchn, int irq) | |
1180 | { | |
d77bbd4d JF |
1181 | struct irq_info *info = info_for_irq(irq); |
1182 | ||
eb1e305f JF |
1183 | /* Make sure the irq is masked, since the new event channel |
1184 | will also be masked. */ | |
1185 | disable_irq(irq); | |
1186 | ||
1187 | spin_lock(&irq_mapping_update_lock); | |
1188 | ||
1189 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1190 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1191 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1192 | so there should be a proper type */ |
1193 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
1194 | |
1195 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1196 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
1197 | |
1198 | spin_unlock(&irq_mapping_update_lock); | |
1199 | ||
1200 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1201 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1202 | |
1203 | /* Unmask the event channel. */ | |
1204 | enable_irq(irq); | |
1205 | } | |
1206 | ||
e46cdb66 | 1207 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1208 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1209 | { |
1210 | struct evtchn_bind_vcpu bind_vcpu; | |
1211 | int evtchn = evtchn_from_irq(irq); | |
1212 | ||
183d03cc SS |
1213 | /* events delivered via platform PCI interrupts are always |
1214 | * routed to vcpu 0 */ | |
1215 | if (!VALID_EVTCHN(evtchn) || | |
1216 | (xen_hvm_domain() && !xen_have_vector_callback)) | |
d5dedd45 | 1217 | return -1; |
e46cdb66 JF |
1218 | |
1219 | /* Send future instances of this interrupt to other vcpu. */ | |
1220 | bind_vcpu.port = evtchn; | |
1221 | bind_vcpu.vcpu = tcpu; | |
1222 | ||
1223 | /* | |
1224 | * If this fails, it usually just indicates that we're dealing with a | |
1225 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1226 | * it, but don't do the xenlinux-level rebind in that case. | |
1227 | */ | |
1228 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1229 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1230 | |
d5dedd45 YL |
1231 | return 0; |
1232 | } | |
e46cdb66 | 1233 | |
d5dedd45 | 1234 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 1235 | { |
0de26520 | 1236 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
1237 | |
1238 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
1239 | } |
1240 | ||
642e0c88 IY |
1241 | int resend_irq_on_evtchn(unsigned int irq) |
1242 | { | |
1243 | int masked, evtchn = evtchn_from_irq(irq); | |
1244 | struct shared_info *s = HYPERVISOR_shared_info; | |
1245 | ||
1246 | if (!VALID_EVTCHN(evtchn)) | |
1247 | return 1; | |
1248 | ||
1249 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1250 | sync_set_bit(evtchn, s->evtchn_pending); | |
1251 | if (!masked) | |
1252 | unmask_evtchn(evtchn); | |
1253 | ||
1254 | return 1; | |
1255 | } | |
1256 | ||
e46cdb66 JF |
1257 | static void enable_dynirq(unsigned int irq) |
1258 | { | |
1259 | int evtchn = evtchn_from_irq(irq); | |
1260 | ||
1261 | if (VALID_EVTCHN(evtchn)) | |
1262 | unmask_evtchn(evtchn); | |
1263 | } | |
1264 | ||
1265 | static void disable_dynirq(unsigned int irq) | |
1266 | { | |
1267 | int evtchn = evtchn_from_irq(irq); | |
1268 | ||
1269 | if (VALID_EVTCHN(evtchn)) | |
1270 | mask_evtchn(evtchn); | |
1271 | } | |
1272 | ||
1273 | static void ack_dynirq(unsigned int irq) | |
1274 | { | |
1275 | int evtchn = evtchn_from_irq(irq); | |
1276 | ||
3588fe2e | 1277 | move_masked_irq(irq); |
e46cdb66 JF |
1278 | |
1279 | if (VALID_EVTCHN(evtchn)) | |
3588fe2e | 1280 | unmask_evtchn(evtchn); |
e46cdb66 JF |
1281 | } |
1282 | ||
1283 | static int retrigger_dynirq(unsigned int irq) | |
1284 | { | |
1285 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 1286 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1287 | int ret = 0; |
1288 | ||
1289 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1290 | int masked; |
1291 | ||
1292 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1293 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1294 | if (!masked) | |
1295 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1296 | ret = 1; |
1297 | } | |
1298 | ||
1299 | return ret; | |
1300 | } | |
1301 | ||
9a069c33 SS |
1302 | static void restore_cpu_pirqs(void) |
1303 | { | |
1304 | int pirq, rc, irq, gsi; | |
1305 | struct physdev_map_pirq map_irq; | |
1306 | ||
1307 | for (pirq = 0; pirq < nr_irqs; pirq++) { | |
1308 | irq = pirq_to_irq[pirq]; | |
1309 | if (irq == -1) | |
1310 | continue; | |
1311 | ||
1312 | /* save/restore of PT devices doesn't work, so at this point the | |
1313 | * only devices present are GSI based emulated devices */ | |
1314 | gsi = gsi_from_irq(irq); | |
1315 | if (!gsi) | |
1316 | continue; | |
1317 | ||
1318 | map_irq.domid = DOMID_SELF; | |
1319 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1320 | map_irq.index = gsi; | |
1321 | map_irq.pirq = pirq; | |
1322 | ||
1323 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1324 | if (rc) { | |
1325 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1326 | gsi, irq, pirq, rc); | |
1327 | irq_info[irq] = mk_unbound_info(); | |
1328 | pirq_to_irq[pirq] = -1; | |
1329 | continue; | |
1330 | } | |
1331 | ||
1332 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1333 | ||
1334 | startup_pirq(irq); | |
1335 | } | |
1336 | } | |
1337 | ||
0e91398f JF |
1338 | static void restore_cpu_virqs(unsigned int cpu) |
1339 | { | |
1340 | struct evtchn_bind_virq bind_virq; | |
1341 | int virq, irq, evtchn; | |
1342 | ||
1343 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1344 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1345 | continue; | |
1346 | ||
ced40d0f | 1347 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1348 | |
1349 | /* Get a new binding from Xen. */ | |
1350 | bind_virq.virq = virq; | |
1351 | bind_virq.vcpu = cpu; | |
1352 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1353 | &bind_virq) != 0) | |
1354 | BUG(); | |
1355 | evtchn = bind_virq.port; | |
1356 | ||
1357 | /* Record the new mapping. */ | |
1358 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1359 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f | 1360 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1361 | } |
1362 | } | |
1363 | ||
1364 | static void restore_cpu_ipis(unsigned int cpu) | |
1365 | { | |
1366 | struct evtchn_bind_ipi bind_ipi; | |
1367 | int ipi, irq, evtchn; | |
1368 | ||
1369 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1370 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1371 | continue; | |
1372 | ||
ced40d0f | 1373 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1374 | |
1375 | /* Get a new binding from Xen. */ | |
1376 | bind_ipi.vcpu = cpu; | |
1377 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1378 | &bind_ipi) != 0) | |
1379 | BUG(); | |
1380 | evtchn = bind_ipi.port; | |
1381 | ||
1382 | /* Record the new mapping. */ | |
1383 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1384 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f | 1385 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1386 | } |
1387 | } | |
1388 | ||
2d9e1e2f JF |
1389 | /* Clear an irq's pending state, in preparation for polling on it */ |
1390 | void xen_clear_irq_pending(int irq) | |
1391 | { | |
1392 | int evtchn = evtchn_from_irq(irq); | |
1393 | ||
1394 | if (VALID_EVTCHN(evtchn)) | |
1395 | clear_evtchn(evtchn); | |
1396 | } | |
d9a8814f | 1397 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1398 | void xen_set_irq_pending(int irq) |
1399 | { | |
1400 | int evtchn = evtchn_from_irq(irq); | |
1401 | ||
1402 | if (VALID_EVTCHN(evtchn)) | |
1403 | set_evtchn(evtchn); | |
1404 | } | |
1405 | ||
1406 | bool xen_test_irq_pending(int irq) | |
1407 | { | |
1408 | int evtchn = evtchn_from_irq(irq); | |
1409 | bool ret = false; | |
1410 | ||
1411 | if (VALID_EVTCHN(evtchn)) | |
1412 | ret = test_evtchn(evtchn); | |
1413 | ||
1414 | return ret; | |
1415 | } | |
1416 | ||
d9a8814f KRW |
1417 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1418 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1419 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1420 | { |
1421 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1422 | ||
1423 | if (VALID_EVTCHN(evtchn)) { | |
1424 | struct sched_poll poll; | |
1425 | ||
1426 | poll.nr_ports = 1; | |
d9a8814f | 1427 | poll.timeout = timeout; |
ff3c5362 | 1428 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1429 | |
1430 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1431 | BUG(); | |
1432 | } | |
1433 | } | |
d9a8814f KRW |
1434 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1435 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1436 | * irq will be disabled so it won't deliver an interrupt. */ | |
1437 | void xen_poll_irq(int irq) | |
1438 | { | |
1439 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1440 | } | |
2d9e1e2f | 1441 | |
0e91398f JF |
1442 | void xen_irq_resume(void) |
1443 | { | |
1444 | unsigned int cpu, irq, evtchn; | |
6903591f | 1445 | struct irq_desc *desc; |
0e91398f JF |
1446 | |
1447 | init_evtchn_cpu_bindings(); | |
1448 | ||
1449 | /* New event-channel space is not 'live' yet. */ | |
1450 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1451 | mask_evtchn(evtchn); | |
1452 | ||
1453 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 1454 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
1455 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
1456 | ||
1457 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1458 | evtchn_to_irq[evtchn] = -1; | |
1459 | ||
1460 | for_each_possible_cpu(cpu) { | |
1461 | restore_cpu_virqs(cpu); | |
1462 | restore_cpu_ipis(cpu); | |
1463 | } | |
6903591f IC |
1464 | |
1465 | /* | |
1466 | * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These | |
1467 | * are not handled by the IRQ core. | |
1468 | */ | |
1469 | for_each_irq_desc(irq, desc) { | |
1470 | if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND)) | |
1471 | continue; | |
1472 | if (desc->status & IRQ_DISABLED) | |
1473 | continue; | |
1474 | ||
1475 | evtchn = evtchn_from_irq(irq); | |
1476 | if (evtchn == -1) | |
1477 | continue; | |
1478 | ||
1479 | unmask_evtchn(evtchn); | |
1480 | } | |
9a069c33 SS |
1481 | |
1482 | restore_cpu_pirqs(); | |
0e91398f JF |
1483 | } |
1484 | ||
e46cdb66 JF |
1485 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
1486 | .name = "xen-dyn", | |
54a353a0 JF |
1487 | |
1488 | .disable = disable_dynirq, | |
e46cdb66 JF |
1489 | .mask = disable_dynirq, |
1490 | .unmask = enable_dynirq, | |
54a353a0 | 1491 | |
3588fe2e | 1492 | .eoi = ack_dynirq, |
e46cdb66 JF |
1493 | .set_affinity = set_affinity_irq, |
1494 | .retrigger = retrigger_dynirq, | |
1495 | }; | |
1496 | ||
d46a78b0 JF |
1497 | static struct irq_chip xen_pirq_chip __read_mostly = { |
1498 | .name = "xen-pirq", | |
1499 | ||
1500 | .startup = startup_pirq, | |
1501 | .shutdown = shutdown_pirq, | |
1502 | ||
1503 | .enable = enable_pirq, | |
1504 | .unmask = enable_pirq, | |
1505 | ||
1506 | .disable = disable_pirq, | |
1507 | .mask = disable_pirq, | |
1508 | ||
1509 | .ack = ack_pirq, | |
1510 | .end = end_pirq, | |
1511 | ||
1512 | .set_affinity = set_affinity_irq, | |
1513 | ||
1514 | .retrigger = retrigger_dynirq, | |
1515 | }; | |
1516 | ||
aaca4964 JF |
1517 | static struct irq_chip xen_percpu_chip __read_mostly = { |
1518 | .name = "xen-percpu", | |
1519 | ||
1520 | .disable = disable_dynirq, | |
1521 | .mask = disable_dynirq, | |
1522 | .unmask = enable_dynirq, | |
1523 | ||
1524 | .ack = ack_dynirq, | |
1525 | }; | |
1526 | ||
38e20b07 SY |
1527 | int xen_set_callback_via(uint64_t via) |
1528 | { | |
1529 | struct xen_hvm_param a; | |
1530 | a.domid = DOMID_SELF; | |
1531 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1532 | a.value = via; | |
1533 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1534 | } | |
1535 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1536 | ||
ca65f9fc | 1537 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1538 | /* Vector callbacks are better than PCI interrupts to receive event |
1539 | * channel notifications because we can receive vector callbacks on any | |
1540 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1541 | void xen_callback_vector(void) | |
1542 | { | |
1543 | int rc; | |
1544 | uint64_t callback_via; | |
1545 | if (xen_have_vector_callback) { | |
1546 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1547 | rc = xen_set_callback_via(callback_via); | |
1548 | if (rc) { | |
1549 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1550 | " failed.\n"); | |
1551 | xen_have_vector_callback = 0; | |
1552 | return; | |
1553 | } | |
1554 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1555 | "enabled\n"); | |
1556 | /* in the restore case the vector has already been allocated */ | |
1557 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1558 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1559 | } | |
1560 | } | |
ca65f9fc SS |
1561 | #else |
1562 | void xen_callback_vector(void) {} | |
1563 | #endif | |
38e20b07 | 1564 | |
e46cdb66 JF |
1565 | void __init xen_init_IRQ(void) |
1566 | { | |
e5fc7345 | 1567 | int i; |
c7a3589e | 1568 | |
a70c352a PE |
1569 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
1570 | GFP_KERNEL); | |
b21ddbf5 JF |
1571 | irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL); |
1572 | ||
e5fc7345 SS |
1573 | /* We are using nr_irqs as the maximum number of pirq available but |
1574 | * that number is actually chosen by Xen and we don't know exactly | |
1575 | * what it is. Be careful choosing high pirq numbers. */ | |
1576 | pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL); | |
1577 | for (i = 0; i < nr_irqs; i++) | |
7a043f11 SS |
1578 | pirq_to_irq[i] = -1; |
1579 | ||
b21ddbf5 JF |
1580 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1581 | GFP_KERNEL); | |
1582 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1583 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1584 | |
1585 | init_evtchn_cpu_bindings(); | |
1586 | ||
1587 | /* No event channels are 'live' right now. */ | |
1588 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1589 | mask_evtchn(i); | |
1590 | ||
38e20b07 SY |
1591 | if (xen_hvm_domain()) { |
1592 | xen_callback_vector(); | |
1593 | native_init_IRQ(); | |
3942b740 SS |
1594 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1595 | * __acpi_register_gsi can point at the right function */ | |
1596 | pci_xen_hvm_init(); | |
38e20b07 SY |
1597 | } else { |
1598 | irq_ctx_init(smp_processor_id()); | |
38aa66fc JF |
1599 | if (xen_initial_domain()) |
1600 | xen_setup_pirqs(); | |
38e20b07 | 1601 | } |
e46cdb66 | 1602 | } |