projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
*** empty log message ***
[deliverable/binutils-gdb.git] / gas / ChangeLog
CommitLineData
784906c5
NC		 12006-07-21 Nick Clifton <nickc@redhat.com>
2
3 * config/tc-sh.c (md_longopts): Add -EL and -EB for use by the
4 linker testsuite.
5
d5f010e9
TS		 62006-07-20 Thiemo Seufer <ths@mips.com>
7 Nigel Stephens <nigel@mips.com>
8
9 * config/tc-mips.c (md_parse_option): Don't infer optimisation
10 options from debug options.
11
35d3d567
TS		 122006-07-20 Thiemo Seufer <ths@mips.com>
13
14 * config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP.
15 (tc_gen_reloc): Handle mips16 jumps to section symbol offsets.
16
401a54cf
PB		 172006-07-19 Paul Brook <paul@codesourcery.com>
18
19 * config/tc-arm.c (insns): Fix rbit Arm opcode.
20
16805f35
PB		 212006-07-18 Paul Brook <paul@codesourcery.com>
22
23 * tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
24 (md_convert_frag): Use correct reloc for add_pc. Use
25 BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
26 (md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
27 (arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
28
d9e05e4e
AM		 292006-07-17 Mat Hostetter <mat@lcs.mit.edu>
30
31 * symbols.c (report_op_error): Fix pasto. Don't use as_bad_where
32 when file and line unknown.
33
f43abd2b
TS		 342006-07-17 Thiemo Seufer <ths@mips.com>
35
36 * read.c (s_struct): Use IS_ELF.
37 * config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
38 md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
39 tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
40 s_mips_mask): Likewise.
41
a2902af6
TS		 422006-07-16 Thiemo Seufer <ths@mips.com>
43 David Ung <davidu@mips.com>
44
45 * read.c (s_struct): Handle ELF section changing.
46 * config/tc-mips.c (s_align): Leave enabling auto-align to the
47 generic code.
48 (s_change_sec): Try section changing only if we output ELF.
49
d32cad65
L		 502006-07-15 H.J. Lu <hongjiu.lu@intel.com>
51
52 * config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
53 CpuAmdFam10.
54 (smallest_imm_type): Remove Cpu086.
55 (i386_target_format): Likewise.
56
57 * config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
58 Update CpuXXX.
59
050dfa73
MM		 602006-07-13 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
61 Michael Meissner <michael.meissner@amd.com>
62
63 * config/tc-i386.h (PROCESSOR_AMDFAM10): New processor_type.
64 (CpuSSE4a, CpuABM, CpuAmdFam10): New Cpu directives.
65 * config/tc-i386.c (cpu_arch): Add support for AmdFam10
66 architecture.
67 (i386_align_code): Ditto.
68 (md_assemble_code): Add support for insertq/extrq instructions,
69 swapping as needed for intel syntax.
70 (swap_imm_operands): New function to swap immediate operands.
71 (swap_operands): Deal with 4 operand instructions.
72 (build_modrm_byte): Add support for insertq instruction.
73
6b2de085
L		 742006-07-13 H.J. Lu <hongjiu.lu@intel.com>
75
76 * config/tc-i386.h (Size64): Fix a typo in comment.
77
01eaea5a
NC		 782006-07-12 Nick Clifton <nickc@redhat.com>
79
80 * config/tc-sh.c (md_apply_fix): Do not allow the generic code in
7cfe9437 81 fixup_segment() to repeat a range check on a value that has
01eaea5a
NC		 82 already been checked here.
83
1e85aad8
JW		 842006-07-07 James E Wilson <wilson@specifix.com>
85
86 * config/tc-mips.c (mips_cpu_info_table): Add sb1a.
87
1370e33d
NC		 882006-07-06 Mohammed Adnène Trojette <adn@diwi.org>
89 Nick Clifton <nickc@redhat.com>
90
91 PR binutils/2877
92 * doc/as.texi: Fix spelling typo: branchs => branches.
93 * doc/c-m68hc11.texi: Likewise.
94 * config/tc-m68hc11.c: Likewise.
95 Support old spelling of command line switch for backwards
96 compatibility.
97
5f0fe04b
TS		 982006-07-04 Thiemo Seufer <ths@mips.com>
99 David Ung <davidu@mips.com>
100
101 * config/tc-mips.c (s_is_linkonce): New function.
102 (mips16_mark_labels): Don't adjust mips16 symbol addresses for
103 weak, external, and linkonce symbols.
104 (pic_need_relax): Use s_is_linkonce.
105
85234291
L		 1062006-06-24 H.J. Lu <hongjiu.lu@intel.com>
107
108 * doc/as.texinfo (Org): Remove space.
109 (P2align): Add "@var{abs-expr},".
110
ccc9c027
L		 1112006-06-23 H.J. Lu <hongjiu.lu@intel.com>
112
113 * config/tc-i386.c (cpu_arch_tune_set): New.
114 (cpu_arch_isa): Likewise.
115 (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
116 nops with short or long nop sequences based on -march=/.arch
117 and -mtune=.
118 (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
119 set cpu_arch_tune and cpu_arch_tune_flags.
120 (md_parse_option): For -march=, set cpu_arch_isa and set
121 cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
122 0. Set cpu_arch_tune_set to 1 for -mtune=.
123 (i386_target_format): Don't set cpu_arch_tune.
124
d4dc2f22
TS		 1252006-06-23 Nigel Stephens <nigel@mips.com>
126
127 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
128 generated .sbss.* and .gnu.linkonce.sb.*.
129
a8dbcb85
TS		 1302006-06-23 Thiemo Seufer <ths@mips.com>
131 David Ung <davidu@mips.com>
132
133 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
134 label_list.
135 * config/tc-mips.c (label_list): Define per-segment label_list.
136 (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
137 append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
138 mips_from_file_after_relocs, mips_define_label): Use per-segment
139 label_list.
140
3994f87e
TS		 1412006-06-22 Thiemo Seufer <ths@mips.com>
142
143 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
144 (append_insn): Use it.
145 (md_apply_fix): Whitespace formatting.
146 (md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
147 mips16_extended_frag): Remove register specifier.
148 (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
149 constants.
150
fa073d69
MS		 1512006-06-21 Mark Shinwell <shinwell@codesourcery.com>
152
153 * config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
154 a directive saving VFP registers for ARMv6 or later.
155 (s_arm_unwind_save): Add parameter arch_v6 and call
156 s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
157 appropriate.
158 (md_pseudo_table): Add entry for new "vsave" directive.
159 * doc/c-arm.texi: Correct error in example for "save"
160 directive (fstmdf -> fstmdx). Also document "vsave" directive.
161
8e77b565 1622006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
026dcbd7
DC		 163 Anatoly Sokolov <aesok@post.ru>
164
165 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
166 and atmega644p devices. Rename atmega164/atmega324 devices to
167 atmega164p/atmega324p.
168 * doc/c-avr.texi: Document new mcu and arch options.
169
8b1ad454
NC		 1702006-06-17 Nick Clifton <nickc@redhat.com>
171
172 * config/tc-arm.c (enum parse_operand_result): Move outside of
173 #ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
174
9103f4f4
L		 1752006-06-16 H.J. Lu <hongjiu.lu@intel.com>
176
177 * config/tc-i386.h (processor_type): New.
178 (arch_entry): Add type.
179
180 * config/tc-i386.c (cpu_arch_tune): New.
181 (cpu_arch_tune_flags): Likewise.
182 (cpu_arch_isa_flags): Likewise.
183 (cpu_arch): Updated.
184 (set_cpu_arch): Also update cpu_arch_isa_flags.
185 (md_assemble): Update cpu_arch_isa_flags.
186 (OPTION_MARCH): New.
187 (OPTION_MTUNE): Likewise.
188 (md_longopts): Add -march= and -mtune=.
189 (md_parse_option): Support -march= and -mtune=.
190 (md_show_usage): Add -march=CPU/-mtune=CPU.
191 (i386_target_format): Also update cpu_arch_isa_flags,
192 cpu_arch_tune and cpu_arch_tune_flags.
193
194 * doc/as.texinfo: Add -march=CPU/-mtune=CPU.
195
196 * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
197
4962c51a
MS		 1982006-06-15 Mark Shinwell <shinwell@codesourcery.com>
199
200 * config/tc-arm.c (enum parse_operand_result): New.
201 (struct group_reloc_table_entry): New.
202 (enum group_reloc_type): New.
203 (group_reloc_table): New array.
204 (find_group_reloc_table_entry): New function.
205 (parse_shifter_operand_group_reloc): New function.
206 (parse_address_main): New function, incorporating code
207 from the old parse_address function. To be used via...
208 (parse_address): wrapper for parse_address_main; and
209 (parse_address_group_reloc): new function, likewise.
210 (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
211 OP_ADDRGLDRS, OP_ADDRGLDC.
212 (parse_operands): Support for these new operand codes.
213 New macro po_misc_or_fail_no_backtrack.
214 (encode_arm_cp_address): Preserve group relocations.
215 (insns): Modify to use the above operand codes where group
216 relocations are permitted.
217 (md_apply_fix): Handle the group relocations
218 ALU_PC_G0_NC through LDC_SB_G2.
219 (tc_gen_reloc): Likewise.
220 (arm_force_relocation): Leave group relocations for the linker.
221 (arm_fix_adjustable): Likewise.
222
cd2f129f
JB		 2232006-06-15 Julian Brown <julian@codesourcery.com>
224
225 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
226 (do_neon_ldr_str): Always defer to VFP encoding routines, which handle
227 relocs properly.
228
46e883c5
L		 2292006-06-12 H.J. Lu <hongjiu.lu@intel.com>
230
231 * config/tc-i386.c (process_suffix): Don't add rex64 for
232 "xchg %rax,%rax".
233
1787fe5b
TS		 2342006-06-09 Thiemo Seufer <ths@mips.com>
235
236 * config/tc-mips.c (mips_ip): Maintain argument count.
237
96f989c2
AM		 2382006-06-09 Alan Modra <amodra@bigpond.net.au>
239
240 * config/tc-iq2000.c: Include sb.h.
241
7c752c2a
TS		 2422006-06-08 Nigel Stephens <nigel@mips.com>
243
244 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
245 aliases for better compatibility with SGI tools.
246
03bf704f
AM		 2472006-06-08 Alan Modra <amodra@bigpond.net.au>
248
249 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
250 * Makefile.am (GASLIBS): Expand @BFDLIB@.
251 (BFDVER_H): Delete.
252 (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
253 (obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
254 (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
255 Run "make dep-am".
256 * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
257 * Makefile.in: Regenerate.
258 * doc/Makefile.in: Regenerate.
259 * configure: Regenerate.
260
6648b7cf
JM		 2612006-06-07 Joseph S. Myers <joseph@codesourcery.com>
262
263 * po/Make-in (pdf, ps): New dummy targets.
264
037e8744
JB		 2652006-06-07 Julian Brown <julian@codesourcery.com>
266
267 * config/tc-arm.c (stdarg.h): include.
268 (arm_it): Add uncond_value field. Add isvec and issingle to operand
269 array.
270 (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
271 REG_TYPE_NSDQ (single, double or quad vector reg).
272 (reg_expected_msgs): Update.
273 (BAD_FPU): Add macro for unsupported FPU instruction error.
274 (parse_neon_type): Support 'd' as an alias for .f64.
275 (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
276 sets of registers.
277 (parse_vfp_reg_list): Don't update first arg on error.
278 (parse_neon_mov): Support extra syntax for VFP moves.
279 (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
280 OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
281 (parse_operands): Support isvec, issingle operands fields, new parse
282 codes above.
283 (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
284 msr variants.
285 (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
286 (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
287 (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
288 (NEON_SHAPE_DEF): New macro. Define table of possible instruction
289 shapes.
290 (neon_shape): Redefine in terms of above.
291 (neon_shape_class): New enumeration, table of shape classes.
292 (neon_shape_el): New enumeration. One element of a shape.
293 (neon_shape_el_size): Register widths of above, where appropriate.
294 (neon_shape_info): New struct. Info for shape table.
295 (neon_shape_tab): New array.
296 (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
297 (neon_check_shape): Rewrite as...
298 (neon_select_shape): New function to classify instruction shapes,
299 driven by new table neon_shape_tab array.
300 (neon_quad): New function. Return 1 if shape should set Q flag in
301 instructions (or equivalent), 0 otherwise.
302 (type_chk_of_el_type): Support F64.
303 (el_type_of_type_chk): Likewise.
304 (neon_check_type): Add support for VFP type checking (VFP data
305 elements fill their containing registers).
306 (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
307 in thumb mode for VFP instructions.
308 (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
309 and encode the current instruction as if it were that opcode.
310 (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
311 arguments, call function in PFN.
312 (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
313 (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
314 (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
315 (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
316 (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
317 Redirect Neon-syntax VFP instructions to VFP instruction handlers.
318 (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
319 (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
320 (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
321 (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
322 (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
323 (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
324 (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
325 (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
326 (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
327 neon_quad.
328 (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
329 between VFP and Neon turns out to belong to Neon. Perform
330 architecture check and fill in condition field if appropriate.
331 (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
332 (do_neon_cvt): Add support for VFP variants of instructions.
333 (neon_cvt_flavour): Extend to cover VFP conversions.
334 (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
335 vmov variants.
336 (do_neon_ldr_str): Handle single-precision VFP load/store.
337 (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
338 NS_NULL not NS_IGNORE.
339 (opcode_tag): Add OT_csuffixF for operands which either take a
340 conditional suffix, or have 0xF in the condition field.
341 (md_assemble): Add support for OT_csuffixF.
342 (NCE): Replace macro with...
343 (NCE_tag, NCE, NCEF): New macros.
344 (nCE): Replace macro with...
345 (nCE_tag, nCE, nCEF): New macros.
346 (insns): Add support for VFP insns or VFP versions of insns msr,
347 mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
348 vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
349 vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
350 VFP/Neon insns together.
351
ebd1c875
AM		 3522006-06-07 Alan Modra <amodra@bigpond.net.au>
353 Ladislav Michl <ladis@linux-mips.org>
354
355 * app.c: Don't include headers already included by as.h.
356 * as.c: Likewise.
357 * atof-generic.c: Likewise.
358 * cgen.c: Likewise.
359 * dwarf2dbg.c: Likewise.
360 * expr.c: Likewise.
361 * input-file.c: Likewise.
362 * input-scrub.c: Likewise.
363 * macro.c: Likewise.
364 * output-file.c: Likewise.
365 * read.c: Likewise.
366 * sb.c: Likewise.
367 * config/bfin-lex.l: Likewise.
368 * config/obj-coff.h: Likewise.
369 * config/obj-elf.h: Likewise.
370 * config/obj-som.h: Likewise.
371 * config/tc-arc.c: Likewise.
372 * config/tc-arm.c: Likewise.
373 * config/tc-avr.c: Likewise.
374 * config/tc-bfin.c: Likewise.
375 * config/tc-cris.c: Likewise.
376 * config/tc-d10v.c: Likewise.
377 * config/tc-d30v.c: Likewise.
378 * config/tc-dlx.h: Likewise.
379 * config/tc-fr30.c: Likewise.
380 * config/tc-frv.c: Likewise.
381 * config/tc-h8300.c: Likewise.
382 * config/tc-hppa.c: Likewise.
383 * config/tc-i370.c: Likewise.
384 * config/tc-i860.c: Likewise.
385 * config/tc-i960.c: Likewise.
386 * config/tc-ip2k.c: Likewise.
387 * config/tc-iq2000.c: Likewise.
388 * config/tc-m32c.c: Likewise.
389 * config/tc-m32r.c: Likewise.
390 * config/tc-maxq.c: Likewise.
391 * config/tc-mcore.c: Likewise.
392 * config/tc-mips.c: Likewise.
393 * config/tc-mmix.c: Likewise.
394 * config/tc-mn10200.c: Likewise.
395 * config/tc-mn10300.c: Likewise.
396 * config/tc-msp430.c: Likewise.
397 * config/tc-mt.c: Likewise.
398 * config/tc-ns32k.c: Likewise.
399 * config/tc-openrisc.c: Likewise.
400 * config/tc-ppc.c: Likewise.
401 * config/tc-s390.c: Likewise.
402 * config/tc-sh.c: Likewise.
403 * config/tc-sh64.c: Likewise.
404 * config/tc-sparc.c: Likewise.
405 * config/tc-tic30.c: Likewise.
406 * config/tc-tic4x.c: Likewise.
407 * config/tc-tic54x.c: Likewise.
408 * config/tc-v850.c: Likewise.
409 * config/tc-vax.c: Likewise.
410 * config/tc-xc16x.c: Likewise.
411 * config/tc-xstormy16.c: Likewise.
412 * config/tc-xtensa.c: Likewise.
413 * config/tc-z80.c: Likewise.
414 * config/tc-z8k.c: Likewise.
415 * macro.h: Don't include sb.h or ansidecl.h.
416 * sb.h: Don't include stdio.h or ansidecl.h.
417 * cond.c: Include sb.h.
418 * itbl-lex.l: Include as.h instead of other system headers.
419 * itbl-parse.y: Likewise.
420 * itbl-ops.c: Similarly.
421 * itbl-ops.h: Don't include as.h or ansidecl.h.
422 * config/bfin-defs.h: Don't include bfd.h or as.h.
423 * config/bfin-parse.y: Include as.h instead of other system headers.
424
9622b051
AM		 4252006-06-06 Ben Elliston <bje@au.ibm.com>
426 Anton Blanchard <anton@samba.org>
427
428 * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
429 (md_show_usage): Document it.
430 (ppc_setup_opcodes): Test power6 opcode flag bits.
431 * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
432
65263ce3
TS		 4332006-06-06 Thiemo Seufer <ths@mips.com>
434 Chao-ying Fu <fu@mips.com>
435
436 * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
437 (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
438 (macro_build): Update comment.
439 (mips_ip): Allow DSP64 instructions for MIPS64R2.
440 (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
441 CPU_HAS_MDMX.
442 (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
443 MIPS_CPU_ASE_MDMX flags for sb1.
444
a9e24354
TS		 4452006-06-05 Thiemo Seufer <ths@mips.com>
446
447 * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
448 appropriate.
449 (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
450 (mips_ip): Make overflowed/underflowed constant arguments in DSP
451 and MT instructions a fatal error. Use INSERT_OPERAND where
452 appropriate. Improve warnings for break and wait code overflows.
453 Use symbolic constant of OP_MASK_COPZ.
454 (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
455
4cfe2c59
DJ		 4562006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
457
458 * po/Make-in (top_builddir): Define.
459
e10fad12
JM		 4602006-06-02 Joseph S. Myers <joseph@codesourcery.com>
461
462 * doc/Makefile.am (TEXI2DVI): Define.
463 * doc/Makefile.in: Regenerate.
464 * doc/c-arc.texi: Fix typo.
465
12e64c2c
AM		 4662006-06-01 Alan Modra <amodra@bigpond.net.au>
467
468 * config/obj-ieee.c: Delete.
469 * config/obj-ieee.h: Delete.
470 * Makefile.am (OBJ_FORMATS): Remove ieee.
471 (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
472 (obj-ieee.o): Remove rule.
473 * Makefile.in: Regenerate.
474 * configure.in (atof): Remove tahoe.
475 (OBJ_MAYBE_IEEE): Don't define.
476 * configure: Regenerate.
477 * config.in: Regenerate.
478 * doc/Makefile.in: Regenerate.
479 * po/POTFILES.in: Regenerate.
480
20e95c23
DJ		 4812006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
482
483 * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
484 and LIBINTL_DEP everywhere.
485 (INTLLIBS): Remove.
486 (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
487 * acinclude.m4: Include new gettext macros.
488 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
489 Remove local code for po/Makefile.
490 * Makefile.in, configure, doc/Makefile.in: Regenerated.
491
eebf07fb
NC		 4922006-05-30 Nick Clifton <nickc@redhat.com>
493
494 * po/es.po: Updated Spanish translation.
495
b6aee19e
DC		 4962006-05-06 Denis Chertykov <denisc@overta.ru>
497
498 * doc/c-avr.texi: New file.
499 * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
500 * doc/all.texi: Set AVR
501 * doc/as.texinfo: Include c-avr.texi
502
f8fdc850
JZ		 5032006-05-28 Jie Zhang <jie.zhang@analog.com>
504
505 * config/bfin-parse.y (check_macfunc): Loose the condition of
506 calling check_multiply_halfregs ().
507
a3205465
JZ		 5082006-05-25 Jie Zhang <jie.zhang@analog.com>
509
510 * config/bfin-parse.y (asm_1): Better check and deal with
511 vector and scalar Multiply 16-Bit Operands instructions.
512
9b52905e
NC		 5132006-05-24 Nick Clifton <nickc@redhat.com>
514
515 * config/tc-hppa.c: Convert to ISO C90 format.
516 * config/tc-hppa.h: Likewise.
517
5182006-05-24 Carlos O'Donell <carlos@systemhalted.org>
519 Randolph Chung <randolph@tausq.org>
520
521 * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
522 is_tls_ieoff, is_tls_leoff): Define.
523 (fix_new_hppa): Handle TLS.
524 (cons_fix_new_hppa): Likewise.
525 (pa_ip): Likewise.
526 (md_apply_fix): Handle TLS relocs.
527 * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
528
28c9d252
NC		 5292006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
530
531 * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
532
ad3fea08
TS		 5332006-05-23 Thiemo Seufer <ths@mips.com>
534 David Ung <davidu@mips.com>
535 Nigel Stephens <nigel@mips.com>
536
537 [ gas/ChangeLog ]
538 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
539 (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
540 ISA_HAS_MXHC1): New macros.
541 (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
542 ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
543 (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
544 (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
545 MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
546 (mips_after_parse_args): Change default handling of float register
547 size to account for 32bit code with 64bit FP. Better sanity checking
548 of ISA/ASE/ABI option combinations.
549 (s_mipsset): Support switching of GPR and FPR sizes via
550 .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
551 options.
552 (mips_elf_final_processing): We should record the use of 64bit FP
553 registers in 32bit code but we don't, because ELF header flags are
554 a scarce ressource.
555 (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
556 extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
557 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
558 (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
559 * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
560 missing -march options. Document .set arch=CPU. Move .set smartmips
561 to ASE page. Use @code for .set FOO examples.
562
8b64503a
JZ		 5632006-05-23 Jie Zhang <jie.zhang@analog.com>
564
565 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
566 if needed.
567
403022e0
JZ		 5682006-05-23 Jie Zhang <jie.zhang@analog.com>
569
570 * config/bfin-defs.h (bfin_equals): Remove declaration.
571 * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
572 * config/tc-bfin.c (bfin_name_is_register): Remove.
573 (bfin_equals): Remove.
574 * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
575 (bfin_name_is_register): Remove declaration.
576
7455baf8
TS		 5772006-05-19 Thiemo Seufer <ths@mips.com>
578 Nigel Stephens <nigel@mips.com>
579
580 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
581 (mips_oddfpreg_ok): New function.
582 (mips_ip): Use it.
583
707bfff6
TS		 5842006-05-19 Thiemo Seufer <ths@mips.com>
585 David Ung <davidu@mips.com>
586
587 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
588 * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
589 ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
590 (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
591 RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
592 RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
593 FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
594 N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
595 SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
596 MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
597 reg_names_o32, reg_names_n32n64): Define register classes.
598 (reg_lookup): New function, use register classes.
599 (md_begin): Reserve register names in the symbol table. Simplify
600 OBJ_ELF defines.
601 (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
602 Use reg_lookup.
603 (mips16_ip): Use reg_lookup.
604 (tc_get_register): Likewise.
605 (tc_mips_regname_to_dw2regnum): New function.
606
1df69f4f
TS		 6072006-05-19 Thiemo Seufer <ths@mips.com>
608
609 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
610 Un-constify string argument.
611 * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
612 Likewise.
613 * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
614 Likewise.
615 * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
616 Likewise.
617 * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
618 Likewise.
619 * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
620 Likewise.
621 * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
622 Likewise.
623
377260ba
NS		 6242006-05-19 Nathan Sidwell <nathan@codesourcery.com>
625
626 * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
627 cfloat/m68881 to correct architecture before using it.
628
cce7653b
NC		 6292006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
630
631 * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
632 constant values.
633
b0796911
PB		 6342006-05-15 Paul Brook <paul@codesourcery.com>
635
636 * config/tc-arm.c (arm_adjust_symtab): Use
637 bfd_is_arm_special_symbol_name.
638
64b607e6
BW		 6392006-05-15 Bob Wilson <bob.wilson@acm.org>
640
641 * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
642 xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
643 xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
644 Handle errors from calls to xtensa_opcode_is_* functions.
645
9b3f89ee
TS		 6462006-05-14 Thiemo Seufer <ths@mips.com>
647
648 * config/tc-mips.c (macro_build): Test for currently active
649 mips16 option.
650 (mips16_ip): Reject invalid opcodes.
651
370b66a1
CD		 6522006-05-11 Carlos O'Donell <carlos@codesourcery.com>
653
654 * doc/as.texinfo: Rename "Index" to "AS Index",
655 and "ABORT" to "ABORT (COFF)".
656
b6895b4f
PB		 6572006-05-11 Paul Brook <paul@codesourcery.com>
658
659 * config/tc-arm.c (parse_half): New function.
660 (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
661 (parse_operands): Ditto.
662 (do_mov16): Reject invalid relocations.
663 (do_t_mov16): Ditto. Use Thumb reloc numbers.
664 (insns): Replace Iffff with HALF.
665 (md_apply_fix): Add MOVW and MOVT relocs.
666 (tc_gen_reloc): Ditto.
667 * doc/c-arm.texi: Document relocation operators
668
e28387c3
PB		 6692006-05-11 Paul Brook <paul@codesourcery.com>
670
671 * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
672
89ee2ebe
TS		 6732006-05-11 Thiemo Seufer <ths@mips.com>
674
675 * config/tc-mips.c (append_insn): Don't check the range of j or
676 jal addresses.
677
53baae48
NC		 6782006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
679
680 * config/tc-arm.c (md_pcrel_from_section): Force a bias for
681 relocs against external symbols for WinCE targets.
682 (md_apply_fix): Likewise.
683
4e2a74a8
TS		 6842006-05-09 David Ung <davidu@mips.com>
685
686 * config/tc-mips.c (append_insn): Only warn about an out-of-range
687 j or jal address.
688
337ff0a5
NC		 6892006-05-09 Nick Clifton <nickc@redhat.com>
690
691 * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
692 against symbols which are not going to be placed into the symbol
693 table.
694
8c9f705e
BE		 6952006-05-09 Ben Elliston <bje@au.ibm.com>
696
697 * expr.c (operand): Remove `if (0 && ..)' statement and
698 subsequently unused target_op label. Collapse `if (1 || ..)'
699 statement.
700 * app.c (do_scrub_chars): Remove unused case 0, as it is handled
701 separately above the switch.
702
2fd0d2ac
NC		 7032006-05-08 Nick Clifton <nickc@redhat.com>
704
705 PR gas/2623
706 * config/tc-msp430.c (line_separator_character): Define as |.
707
e16bfa71
TS		 7082006-05-08 Thiemo Seufer <ths@mips.com>
709 Nigel Stephens <nigel@mips.com>
710 David Ung <davidu@mips.com>
711
712 * config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
713 (mips_opts): Likewise.
714 (file_ase_smartmips): New variable.
715 (ISA_HAS_ROR): SmartMIPS implements rotate instructions.
716 (macro_build): Handle SmartMIPS instructions.
717 (mips_ip): Likewise.
718 (md_longopts): Add argument handling for smartmips.
719 (md_parse_options, mips_after_parse_args): Likewise.
720 (s_mipsset): Add .set smartmips support.
721 (md_show_usage): Document -msmartmips/-mno-smartmips.
722 * doc/as.texinfo: Document -msmartmips/-mno-smartmips and
723 .set smartmips.
724 * doc/c-mips.texi: Likewise.
725
32638454
AM		 7262006-05-08 Alan Modra <amodra@bigpond.net.au>
727
728 * write.c (relax_segment): Add pass count arg. Don't error on
729 negative org/space on first two passes.
730 (relax_seg_info): New struct.
731 (relax_seg, write_object_file): Adjust.
732 * write.h (relax_segment): Update prototype.
733
b7fc2769
JB		 7342006-05-05 Julian Brown <julian@codesourcery.com>
735
736 * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
737 checking.
738 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
739 architecture version checks.
740 (insns): Allow overlapping instructions to be used in VFP mode.
741
7f841127
L		 7422006-05-05 H.J. Lu <hongjiu.lu@intel.com>
743
744 PR gas/2598
745 * config/obj-elf.c (obj_elf_change_section): Allow user
746 specified SHF_ALPHA_GPREL.
747
73160847
NC		 7482006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
749
750 * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
751 for PMEM related expressions.
752
56487c55
NC		 7532006-05-05 Nick Clifton <nickc@redhat.com>
754
755 PR gas/2582
756 * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
757 insertion of a directory separator character into a string at a
758 given offset. Uses heuristics to decide when to use a backslash
759 character rather than a forward-slash character.
760 (dwarf2_directive_loc): Use the macro.
761 (out_debug_info): Likewise.
762
d43b4baf
TS		 7632006-05-05 Thiemo Seufer <ths@mips.com>
764 David Ung <davidu@mips.com>
765
766 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
767 instruction.
768 (macro): Add new case M_CACHE_AB.
769
088fa78e
KH		 7702006-05-04 Kazu Hirata <kazu@codesourcery.com>
771
772 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
773 (opcode_lookup): Issue a warning for opcode with
774 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
775 identical to OT_cinfix3.
776 (TxC3w, TC3w, tC3w): New.
777 (insns): Use tC3w and TC3w for comparison instructions with
778 's' suffix.
779
c9049d30
AM		 7802006-05-04 Alan Modra <amodra@bigpond.net.au>
781
782 * subsegs.h (struct frchain): Delete frch_seg.
783 (frchain_root): Delete.
784 (seg_info): Define as macro.
785 * subsegs.c (frchain_root): Delete.
786 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
787 (subsegs_begin, subseg_change): Adjust for above.
788 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
789 rather than to one big list.
790 (subseg_get): Don't special case abs, und sections.
791 (subseg_new, subseg_force_new): Don't set frchainP here.
792 (seg_info): Delete.
793 (subsegs_print_statistics): Adjust frag chain control list traversal.
794 * debug.c (dmp_frags): Likewise.
795 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
796 at frchain_root. Make use of known frchain ordering.
797 (last_frag_for_seg): Likewise.
798 (get_frag_fix): Likewise. Add seg param.
799 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
800 * write.c (chain_frchains_together_1): Adjust for struct frchain.
801 (SUB_SEGMENT_ALIGN): Likewise.
802 (subsegs_finish): Adjust frchain list traversal.
803 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
804 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
805 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
806 (xtensa_fix_b_j_loop_end_frags): Likewise.
807 (xtensa_fix_close_loop_end_frags): Likewise.
808 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
809 (retrieve_segment_info): Delete frch_seg initialisation.
810
f592407e
AM		 8112006-05-03 Alan Modra <amodra@bigpond.net.au>
812
813 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
814 * config/obj-elf.h (obj_sec_set_private_data): Delete.
815 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
816 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
817
df7849c5
JM		 8182006-05-02 Joseph Myers <joseph@codesourcery.com>
819
820 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
821 here.
822 (md_apply_fix3): Multiply offset by 4 here for
823 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
824
2d545b82
L		 8252006-05-02 H.J. Lu <hongjiu.lu@intel.com>
826 Jan Beulich <jbeulich@novell.com>
827
828 * config/tc-i386.c (output_invalid_buf): Change size for
829 unsigned char.
830 * config/tc-tic30.c (output_invalid_buf): Likewise.
831
832 * config/tc-i386.c (output_invalid): Cast none-ascii char to
833 unsigned char.
834 * config/tc-tic30.c (output_invalid): Likewise.
835
38fc1cb1
DJ		 8362006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
837
838 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
839 (TEXI2POD): Use AM_MAKEINFOFLAGS.
840 (asconfig.texi): Don't set top_srcdir.
841 * doc/as.texinfo: Don't use top_srcdir.
842 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
843
2d545b82
L		 8442006-05-02 H.J. Lu <hongjiu.lu@intel.com>
845
846 * config/tc-i386.c (output_invalid_buf): Change size to 16.
847 * config/tc-tic30.c (output_invalid_buf): Likewise.
848
849 * config/tc-i386.c (output_invalid): Use snprintf instead of
850 sprintf.
851 * config/tc-ia64.c (declare_register_set): Likewise.
852 (emit_one_bundle): Likewise.
853 (check_dependencies): Likewise.
854 * config/tc-tic30.c (output_invalid): Likewise.
855
a8bc6c78
PB		 8562006-05-02 Paul Brook <paul@codesourcery.com>
857
858 * config/tc-arm.c (arm_optimize_expr): New function.
859 * config/tc-arm.h (md_optimize_expr): Define
860 (arm_optimize_expr): Add prototype.
861 (TC_FORCE_RELOCATION_SUB_SAME): Define.
862
58633d9a
BE		 8632006-05-02 Ben Elliston <bje@au.ibm.com>
864
22772e33
BE		 865 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
866 field unsigned.
867
58633d9a
BE		 868 * sb.h (sb_list_vector): Move to sb.c.
869 * sb.c (free_list): Use type of sb_list_vector directly.
870 (sb_build): Fix off-by-one error in assertion about `size'.
871
89cdfe57
BE		 8722006-05-01 Ben Elliston <bje@au.ibm.com>
873
874 * listing.c (listing_listing): Remove useless loop.
875 * macro.c (macro_expand): Remove is_positional local variable.
876 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
877 and simplify surrounding expressions, where possible.
878 (assign_symbol): Likewise.
879 (s_weakref): Likewise.
880 * symbols.c (colon): Likewise.
881
c35da140
AM		 8822006-05-01 James Lemke <jwlemke@wasabisystems.com>
883
884 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
885
9bcd4f99
TS		 8862006-04-30 Thiemo Seufer <ths@mips.com>
887 David Ung <davidu@mips.com>
888
889 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
890 (mips_immed): New table that records various handling of udi
891 instruction patterns.
892 (mips_ip): Adds udi handling.
893
001ae1a4
AM		 8942006-04-28 Alan Modra <amodra@bigpond.net.au>
895
896 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
897 of list rather than beginning.
898
136da414
JB		 8992006-04-26 Julian Brown <julian@codesourcery.com>
900
901 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
902 (is_quarter_float): Rename from above. Simplify slightly.
903 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
904 number.
905 (parse_neon_mov): Parse floating-point constants.
906 (neon_qfloat_bits): Fix encoding.
907 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
908 preference to integer encoding when using the F32 type.
909
dcbf9037
JB		 9102006-04-26 Julian Brown <julian@codesourcery.com>
911
912 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
913 zero-initialising structures containing it will lead to invalid types).
914 (arm_it): Add vectype to each operand.
915 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
916 defined field.
917 (neon_typed_alias): New structure. Extra information for typed
918 register aliases.
919 (reg_entry): Add neon type info field.
920 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
921 Break out alternative syntax for coprocessor registers, etc. into...
922 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
923 out from arm_reg_parse.
924 (parse_neon_type): Move. Return SUCCESS/FAIL.
925 (first_error): New function. Call to ensure first error which occurs is
926 reported.
927 (parse_neon_operand_type): Parse exactly one type.
928 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
929 (parse_typed_reg_or_scalar): New function. Handle core of both
930 arm_typed_reg_parse and parse_scalar.
931 (arm_typed_reg_parse): Parse a register with an optional type.
932 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
933 result.
934 (parse_scalar): Parse a Neon scalar with optional type.
935 (parse_reg_list): Use first_error.
936 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
937 (neon_alias_types_same): New function. Return true if two (alias) types
938 are the same.
939 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
940 of elements.
941 (insert_reg_alias): Return new reg_entry not void.
942 (insert_neon_reg_alias): New function. Insert type/index information as
943 well as register for alias.
944 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
945 make typed register aliases accordingly.
946 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
947 of line.
948 (s_unreq): Delete type information if present.
949 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
950 (s_arm_unwind_save_mmxwcg): Likewise.
951 (s_arm_unwind_movsp): Likewise.
952 (s_arm_unwind_setfp): Likewise.
953 (parse_shift): Likewise.
954 (parse_shifter_operand): Likewise.
955 (parse_address): Likewise.
956 (parse_tb): Likewise.
957 (tc_arm_regname_to_dw2regnum): Likewise.
958 (md_pseudo_table): Add dn, qn.
959 (parse_neon_mov): Handle typed operands.
960 (parse_operands): Likewise.
961 (neon_type_mask): Add N_SIZ.
962 (N_ALLMODS): New macro.
963 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
964 (el_type_of_type_chk): Add some safeguards.
965 (modify_types_allowed): Fix logic bug.
966 (neon_check_type): Handle operands with types.
967 (neon_three_same): Remove redundant optional arg handling.
968 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
969 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
970 (do_neon_step): Adjust accordingly.
971 (neon_cmode_for_logic_imm): Use first_error.
972 (do_neon_bitfield): Call neon_check_type.
973 (neon_dyadic): Rename to...
974 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
975 to allow modification of type of the destination.
976 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
977 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
978 (do_neon_compare): Make destination be an untyped bitfield.
979 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
980 (neon_mul_mac): Return early in case of errors.
981 (neon_move_immediate): Use first_error.
982 (neon_mac_reg_scalar_long): Fix type to include scalar.
983 (do_neon_dup): Likewise.
984 (do_neon_mov): Likewise (in several places).
985 (do_neon_tbl_tbx): Fix type.
986 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
987 (do_neon_ld_dup): Exit early in case of errors and/or use
988 first_error.
989 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
990 Handle .dn/.qn directives.
991 (REGDEF): Add zero for reg_entry neon field.
992
5287ad62
JB		 9932006-04-26 Julian Brown <julian@codesourcery.com>
994
995 * config/tc-arm.c (limits.h): Include.
996 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
997 (fpu_vfp_v3_or_neon_ext): Declare constants.
998 (neon_el_type): New enumeration of types for Neon vector elements.
999 (neon_type_el): New struct. Define type and size of a vector element.
1000 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
1001 instruction.
1002 (neon_type): Define struct. The type of an instruction.
1003 (arm_it): Add 'vectype' for the current instruction.
1004 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
1005 (vfp_sp_reg_pos): Rename to...
1006 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
1007 tags.
1008 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
1009 (Neon D or Q register).
1010 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
1011 register.
1012 (GE_OPT_PREFIX_BIG): Define constant, for use in...
1013 (my_get_expression): Allow above constant as argument to accept
1014 64-bit constants with optional prefix.
1015 (arm_reg_parse): Add extra argument to return the specific type of
1016 register in when either a D or Q register (REG_TYPE_NDQ) is
1017 requested. Can be NULL.
1018 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
1019 (parse_reg_list): Update for new arm_reg_parse args.
1020 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
1021 (parse_neon_el_struct_list): New function. Parse element/structure
1022 register lists for VLD<n>/VST<n> instructions.
1023 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
1024 (s_arm_unwind_save_mmxwr): Likewise.
1025 (s_arm_unwind_save_mmxwcg): Likewise.
1026 (s_arm_unwind_movsp): Likewise.
1027 (s_arm_unwind_setfp): Likewise.
1028 (parse_big_immediate): New function. Parse an immediate, which may be
1029 64 bits wide. Put results in inst.operands[i].
1030 (parse_shift): Update for new arm_reg_parse args.
1031 (parse_address): Likewise. Add parsing of alignment specifiers.
1032 (parse_neon_mov): Parse the operands of a VMOV instruction.
1033 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
1034 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
1035 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
1036 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
1037 (parse_operands): Handle new codes above.
1038 (encode_arm_vfp_sp_reg): Rename to...
1039 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
1040 selected VFP version only supports D0-D15.
1041 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
1042 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
1043 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
1044 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
1045 encode_arm_vfp_reg name, and allow 32 D regs.
1046 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
1047 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
1048 regs.
1049 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
1050 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
1051 constant-load and conversion insns introduced with VFPv3.
1052 (neon_tab_entry): New struct.
1053 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
1054 those which are the targets of pseudo-instructions.
1055 (neon_opc): Enumerate opcodes, use as indices into...
1056 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
1057 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
1058 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
1059 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
1060 neon_enc_tab.
1061 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
1062 Neon instructions.
1063 (neon_type_mask): New. Compact type representation for type checking.
1064 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
1065 permitted type combinations.
1066 (N_IGNORE_TYPE): New macro.
1067 (neon_check_shape): New function. Check an instruction shape for
1068 multiple alternatives. Return the specific shape for the current
1069 instruction.
1070 (neon_modify_type_size): New function. Modify a vector type and size,
1071 depending on the bit mask in argument 1.
1072 (neon_type_promote): New function. Convert a given "key" type (of an
1073 operand) into the correct type for a different operand, based on a bit
1074 mask.
1075 (type_chk_of_el_type): New function. Convert a type and size into the
1076 compact representation used for type checking.
1077 (el_type_of_type_ckh): New function. Reverse of above (only when a
1078 single bit is set in the bit mask).
1079 (modify_types_allowed): New function. Alter a mask of allowed types
1080 based on a bit mask of modifications.
1081 (neon_check_type): New function. Check the type of the current
1082 instruction against the variable argument list. The "key" type of the
1083 instruction is returned.
1084 (neon_dp_fixup): New function. Fill in and modify instruction bits for
1085 a Neon data-processing instruction depending on whether we're in ARM
1086 mode or Thumb-2 mode.
1087 (neon_logbits): New function.
1088 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
1089 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
1090 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
1091 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
1092 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
1093 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
1094 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
1095 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
1096 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
1097 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
1098 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
1099 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
1100 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
1101 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
1102 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
1103 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
1104 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
1105 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
1106 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
1107 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
1108 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
1109 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
1110 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
1111 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
1112 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
1113 helpers.
1114 (parse_neon_type): New function. Parse Neon type specifier.
1115 (opcode_lookup): Allow parsing of Neon type specifiers.
1116 (REGNUM2, REGSETH, REGSET2): New macros.
1117 (reg_names): Add new VFPv3 and Neon registers.
1118 (NUF, nUF, NCE, nCE): New macros for opcode table.
1119 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
1120 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
1121 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
1122 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
1123 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
1124 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
1125 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
1126 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
1127 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
1128 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
1129 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
1130 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
1131 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
1132 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
1133 fto[us][lh][sd].
1134 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
1135 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
1136 (arm_option_cpu_value): Add vfp3 and neon.
1137 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
1138 VFPv1 attribute.
1139
1946c96e
BW		 11402006-04-25 Bob Wilson <bob.wilson@acm.org>
1141
1142 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
1143 syntax instead of hardcoded opcodes with ".w18" suffixes.
1144 (wide_branch_opcode): New.
1145 (build_transition): Use it to check for wide branch opcodes with
1146 either ".w18" or ".w15" suffixes.
1147
5033a645
BW		 11482006-04-25 Bob Wilson <bob.wilson@acm.org>
1149
1150 * config/tc-xtensa.c (xtensa_create_literal_symbol,
1151 xg_assemble_literal, xg_assemble_literal_space): Do not set the
1152 frag's is_literal flag.
1153
395fa56f
BW		 11542006-04-25 Bob Wilson <bob.wilson@acm.org>
1155
1156 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
1157
708587a4
KH		 11582006-04-23 Kazu Hirata <kazu@codesourcery.com>
1159
1160 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
1161 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
1162 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
1163 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
1164 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
1165
8463be01
PB		 11662005-04-20 Paul Brook <paul@codesourcery.com>
1167
1168 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
1169 all targets.
1170 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
1171
f26a5955
AM		 11722006-04-19 Alan Modra <amodra@bigpond.net.au>
1173
1174 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
1175 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
1176 Make some cpus unsupported on ELF. Run "make dep-am".
1177 * Makefile.in: Regenerate.
1178
241a6c40
AM		 11792006-04-19 Alan Modra <amodra@bigpond.net.au>
1180
1181 * configure.in (--enable-targets): Indent help message.
1182 * configure: Regenerate.
1183
bb8f5920
L		 11842006-04-18 H.J. Lu <hongjiu.lu@intel.com>
1185
1186 PR gas/2533
1187 * config/tc-i386.c (i386_immediate): Check illegal immediate
1188 register operand.
1189
23d9d9de
AM		 11902006-04-18 Alan Modra <amodra@bigpond.net.au>
1191
64e74474
AM		 1192 * config/tc-i386.c: Formatting.
1193 (output_disp, output_imm): ISO C90 params.
1194
6cbe03fb
AM		 1195 * frags.c (frag_offset_fixed_p): Constify args.
1196 * frags.h (frag_offset_fixed_p): Ditto.
1197
23d9d9de
AM		 1198 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
1199 (COFF_MAGIC): Delete.
a37d486e
AM		 1200
1201 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
1202
e7403566
DJ		 12032006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
1204
1205 * po/POTFILES.in: Regenerated.
1206
58ab4f3d
MM		 12072006-04-16 Mark Mitchell <mark@codesourcery.com>
1208
1209 * doc/as.texinfo: Mention that some .type syntaxes are not
1210 supported on all architectures.
1211
482fd9f9
BW		 12122006-04-14 Sterling Augustine <sterling@tensilica.com>
1213
1214 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
1215 instructions when such transformations have been disabled.
1216
05d58145
BW		 12172006-04-10 Sterling Augustine <sterling@tensilica.com>
1218
1219 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
1220 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
1221 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
1222 decoding the loop instructions. Remove current_offset variable.
1223 (xtensa_fix_short_loop_frags): Likewise.
1224 (min_bytes_to_other_loop_end): Remove current_offset argument.
1225
9e75b3fa
AM		 12262006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
1227
a37d486e 1228 * config/tc-z80.c (z80_optimize_expr): Removed.
9e75b3fa
AM		 1229 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
1230
d727e8c2
NC		 12312006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1232
1233 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
1234 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
1235 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
1236 atmega644, atmega329, atmega3290, atmega649, atmega6490,
1237 atmega406, atmega640, atmega1280, atmega1281, at90can32,
1238 at90can64, at90usb646, at90usb647, at90usb1286 and
1239 at90usb1287.
1240 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
1241
d252fdde
PB		 12422006-04-07 Paul Brook <paul@codesourcery.com>
1243
1244 * config/tc-arm.c (parse_operands): Set default error message.
1245
ab1eb5fe
PB		 12462006-04-07 Paul Brook <paul@codesourcery.com>
1247
1248 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
1249
7ae2971b
PB		 12502006-04-07 Paul Brook <paul@codesourcery.com>
1251
1252 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
1253
53365c0d
PB		 12542006-04-07 Paul Brook <paul@codesourcery.com>
1255
1256 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
1257 (move_or_literal_pool): Handle Thumb-2 instructions.
1258 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
1259
45aa61fe
AM		 12602006-04-07 Alan Modra <amodra@bigpond.net.au>
1261
1262 PR 2512.
1263 * config/tc-i386.c (match_template): Move 64-bit operand tests
1264 inside loop.
1265
108a6f8e
CD		 12662006-04-06 Carlos O'Donell <carlos@codesourcery.com>
1267
1268 * po/Make-in: Add install-html target.
1269 * Makefile.am: Add install-html and install-html-recursive targets.
1270 * Makefile.in: Regenerate.
1271 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
1272 * configure: Regenerate.
1273 * doc/Makefile.am: Add install-html and install-html-am targets.
1274 * doc/Makefile.in: Regenerate.
1275
ec651a3b
AM		 12762006-04-06 Alan Modra <amodra@bigpond.net.au>
1277
1278 * frags.c (frag_offset_fixed_p): Reinitialise offset before
1279 second scan.
1280
910600e9
RS		 12812006-04-05 Richard Sandiford <richard@codesourcery.com>
1282 Daniel Jacobowitz <dan@codesourcery.com>
1283
1284 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
1285 (GOTT_BASE, GOTT_INDEX): New.
1286 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
1287 GOTT_INDEX when generating VxWorks PIC.
1288 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
1289 use the generic *-*-vxworks* stanza instead.
1290
99630778
AM		 12912006-04-04 Alan Modra <amodra@bigpond.net.au>
1292
1293 PR 997
1294 * frags.c (frag_offset_fixed_p): New function.
1295 * frags.h (frag_offset_fixed_p): Declare.
1296 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
1297 (resolve_expression): Likewise.
1298
a02728c8
BW		 12992006-04-03 Sterling Augustine <sterling@tensilica.com>
1300
1301 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
1302 of the same length but different numbers of slots.
1303
9dfde49d
AS		 13042006-03-30 Andreas Schwab <schwab@suse.de>
1305
1306 * configure.in: Fix help string for --enable-targets option.
1307 * configure: Regenerate.
1308
2da12c60
NS		 13092006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1310
6d89cc8f
NS		 1311 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
1312 (m68k_ip): ... here. Use for all chips. Protect against buffer
1313 overrun and avoid excessive copying.
1314
2da12c60
NS		 1315 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
1316 m68020_control_regs, m68040_control_regs, m68060_control_regs,
1317 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
1318 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
1319 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
1320 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
1321 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
1322 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
1323 mcf5282_ctrl, mcfv4e_ctrl): ... these.
1324 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
1325 (struct m68k_cpu): Change chip field to control_regs.
1326 (current_chip): Remove.
1327 (control_regs): New.
1328 (m68k_archs, m68k_extensions): Adjust.
1329 (m68k_cpus): Reorder to be in cpu number order. Adjust.
1330 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
1331 (find_cf_chip): Reimplement for new organization of cpu table.
1332 (select_control_regs): Remove.
1333 (mri_chip): Adjust.
1334 (struct save_opts): Save control regs, not chip.
1335 (s_save, s_restore): Adjust.
1336 (m68k_lookup_cpu): Give deprecated warning when necessary.
1337 (m68k_init_arch): Adjust.
1338 (md_show_usage): Adjust for new cpu table organization.
1339
1ac4baed
BS		 13402006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
1341
1342 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
1343 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
1344 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
1345 "elf/bfin.h".
1346 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
1347 (any_gotrel): New rule.
1348 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
1349 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
1350 "elf/bfin.h".
1351 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
1352 (bfin_pic_ptr): New function.
1353 (md_pseudo_table): Add it for ".picptr".
1354 (OPTION_FDPIC): New macro.
1355 (md_longopts): Add -mfdpic.
1356 (md_parse_option): Handle it.
1357 (md_begin): Set BFD flags.
1358 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
1359 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
1360 us for GOT relocs.
1361 * Makefile.am (bfin-parse.o): Update dependencies.
1362 (DEPTC_bfin_elf): Likewise.
1363 * Makefile.in: Regenerate.
1364
a9d34880
RS		 13652006-03-25 Richard Sandiford <richard@codesourcery.com>
1366
1367 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
1368 mcfemac instead of mcfmac.
1369
9ca26584
AJ		 13702006-03-23 Michael Matz <matz@suse.de>
1371
1372 * config/tc-i386.c (type_names): Correct placement of 'static'.
1373 (reloc): Map some more relocs to their 64 bit counterpart when
1374 size is 8.
1375 (output_insn): Work around breakage if DEBUG386 is defined.
1376 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
1377 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
1378 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
1379 different from i386.
1380 (output_imm): Ditto.
1381 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
1382 Imm64.
1383 (md_convert_frag): Jumps can now be larger than 2GB away, error
1384 out in that case.
1385 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
1386 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
1387
0a44bf69
RS		 13882006-03-22 Richard Sandiford <richard@codesourcery.com>
1389 Daniel Jacobowitz <dan@codesourcery.com>
1390 Phil Edwards <phil@codesourcery.com>
1391 Zack Weinberg <zack@codesourcery.com>
1392 Mark Mitchell <mark@codesourcery.com>
1393 Nathan Sidwell <nathan@codesourcery.com>
1394
1395 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
1396 (md_begin): Complain about -G being used for PIC. Don't change
1397 the text, data and bss alignments on VxWorks.
1398 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
1399 generating VxWorks PIC.
1400 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
1401 (macro): Likewise, but do not treat la $25 specially for
1402 VxWorks PIC, and do not handle jal.
1403 (OPTION_MVXWORKS_PIC): New macro.
1404 (md_longopts): Add -mvxworks-pic.
1405 (md_parse_option): Don't complain about using PIC and -G together here.
1406 Handle OPTION_MVXWORKS_PIC.
1407 (md_estimate_size_before_relax): Always use the first relaxation
1408 sequence on VxWorks.
1409 * config/tc-mips.h (VXWORKS_PIC): New.
1410
080eb7fe
PB		 14112006-03-21 Paul Brook <paul@codesourcery.com>
1412
1413 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
1414
03aaa593
BW		 14152006-03-21 Sterling Augustine <sterling@tensilica.com>
1416
1417 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
1418 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
1419 (get_loop_align_size): New.
1420 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
1421 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
1422 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
1423 (get_noop_aligned_address): Use get_loop_align_size.
1424 (get_aligned_diff): Likewise.
1425
3e94bf1a
PB		 14262006-03-21 Paul Brook <paul@codesourcery.com>
1427
1428 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
1429
dfa9f0d5
PB		 14302006-03-20 Paul Brook <paul@codesourcery.com>
1431
1432 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
1433 (do_t_branch): Encode branches inside IT blocks as unconditional.
1434 (do_t_cps): New function.
1435 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
1436 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
1437 (opcode_lookup): Allow conditional suffixes on all instructions in
1438 Thumb mode.
1439 (md_assemble): Advance condexec state before checking for errors.
1440 (insns): Use do_t_cps.
1441
6e1cb1a6
PB		 14422006-03-20 Paul Brook <paul@codesourcery.com>
1443
1444 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
1445 outputting the insn.
1446
0a966e2d
JBG		 14472006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1448
1449 * config/tc-vax.c: Update copyright year.
1450 * config/tc-vax.h: Likewise.
1451
a49fcc17
JBG		 14522006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1453
1454 * config/tc-vax.c (md_chars_to_number): Used only locally, so
1455 make it static.
1456 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
1457
f5208ef2
PB		 14582006-03-17 Paul Brook <paul@codesourcery.com>
1459
1460 * config/tc-arm.c (insns): Add ldm and stm.
1461
cb4c78d6
BE		 14622006-03-17 Ben Elliston <bje@au.ibm.com>
1463
1464 PR gas/2446
1465 * doc/as.texinfo (Ident): Document this directive more thoroughly.
1466
c16d2bf0
PB		 14672006-03-16 Paul Brook <paul@codesourcery.com>
1468
1469 * config/tc-arm.c (insns): Add "svc".
1470
80ca4e2c
BW		 14712006-03-13 Bob Wilson <bob.wilson@acm.org>
1472
1473 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
1474 flag and avoid double underscore prefixes.
1475
3a4a14e9
PB		 14762006-03-10 Paul Brook <paul@codesourcery.com>
1477
1478 * config/tc-arm.c (md_begin): Handle EABIv5.
1479 (arm_eabis): Add EF_ARM_EABI_VER5.
1480 * doc/c-arm.texi: Document -meabi=5.
1481
518051dc
BE		 14822006-03-10 Ben Elliston <bje@au.ibm.com>
1483
1484 * app.c (do_scrub_chars): Simplify string handling.
1485
00a97672
RS		 14862006-03-07 Richard Sandiford <richard@codesourcery.com>
1487 Daniel Jacobowitz <dan@codesourcery.com>
1488 Zack Weinberg <zack@codesourcery.com>
1489 Nathan Sidwell <nathan@codesourcery.com>
1490 Paul Brook <paul@codesourcery.com>
1491 Ricardo Anguiano <anguiano@codesourcery.com>
1492 Phil Edwards <phil@codesourcery.com>
1493
1494 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
1495 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
1496 R_ARM_ABS12 reloc.
1497 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
1498 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
1499 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
1500
b29757dc
BW		 15012006-03-06 Bob Wilson <bob.wilson@acm.org>
1502
1503 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
1504 even when using the text-section-literals option.
1505
0b2e31dc
NS		 15062006-03-06 Nathan Sidwell <nathan@codesourcery.com>
1507
1508 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
1509 and cf.
1510 (m68k_ip): <case 'J'> Check we have some control regs.
1511 (md_parse_option): Allow raw arch switch.
1512 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
1513 whether 68881 or cfloat was meant by -mfloat.
1514 (md_show_usage): Adjust extension display.
1515 (m68k_elf_final_processing): Adjust.
1516
df406460
NC		 15172006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
1518
1519 * config/tc-avr.c (avr_mod_hash_value): New function.
1520 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
1521 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
1522 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
1523 instead of int avr_ldi_expression: use avr_mod_hash_value instead
1524 of (int).
1525 (tc_gen_reloc): Handle substractions of symbols, if possible do
1526 fixups, abort otherwise.
1527 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
1528 tc_fix_adjustable): Define.
1529
53022e4a
JW		 15302006-03-02 James E Wilson <wilson@specifix.com>
1531
1532 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
1533 change the template, then clear md.slot[curr].end_of_insn_group.
1534
9f6f925e
JB		 15352006-02-28 Jan Beulich <jbeulich@novell.com>
1536
1537 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
1538
0e31b3e1
JB		 15392006-02-28 Jan Beulich <jbeulich@novell.com>
1540
1541 PR/1070
1542 * macro.c (getstring): Don't treat parentheses special anymore.
1543 (get_any_string): Don't consider '(' and ')' as quoting anymore.
1544 Special-case '(', ')', '[', and ']' when dealing with non-quoting
1545 characters.
1546
10cd14b4
AM		 15472006-02-28 Mat <mat@csail.mit.edu>
1548
1549 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
1550
63752a75
JJ		 15512006-02-27 Jakub Jelinek <jakub@redhat.com>
1552
1553 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
1554 field.
1555 (CFI_signal_frame): Define.
1556 (cfi_pseudo_table): Add .cfi_signal_frame.
1557 (dot_cfi): Handle CFI_signal_frame.
1558 (output_cie): Handle cie->signal_frame.
1559 (select_cie_for_fde): Don't share CIE if signal_frame flag is
1560 different. Copy signal_frame from FDE to newly created CIE.
1561 * doc/as.texinfo: Document .cfi_signal_frame.
1562
f7d9e5c3
CD		 15632006-02-27 Carlos O'Donell <carlos@codesourcery.com>
1564
1565 * doc/Makefile.am: Add html target.
1566 * doc/Makefile.in: Regenerate.
1567 * po/Make-in: Add html target.
1568
331d2d0d
L		 15692006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1570
8502d882 1571 * config/tc-i386.c (output_insn): Support Intel Merom New
331d2d0d
L		 1572 Instructions.
1573
8502d882 1574 * config/tc-i386.h (CpuMNI): New.
331d2d0d
L		 1575 (CpuUnknownFlags): Add CpuMNI.
1576
10156f83
DM		 15772006-02-24 David S. Miller <davem@sunset.davemloft.net>
1578
1579 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
1580 (hpriv_reg_table): New table for hyperprivileged registers.
1581 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
1582 register encoding.
1583
6772dd07
DD		 15842006-02-24 DJ Delorie <dj@redhat.com>
1585
1586 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
1587 (tc_gen_reloc): Don't define.
1588 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
1589 (OPTION_LINKRELAX): New.
1590 (md_longopts): Add it.
1591 (m32c_relax): New.
1592 (md_parse_options): Set it.
1593 (md_assemble): Emit relaxation relocs as needed.
1594 (md_convert_frag): Emit relaxation relocs as needed.
1595 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
1596 (m32c_apply_fix): New.
1597 (tc_gen_reloc): New.
1598 (m32c_force_relocation): Force out jump relocs when relaxing.
1599 (m32c_fix_adjustable): Return false if relaxing.
1600
62b3e311
PB		 16012006-02-24 Paul Brook <paul@codesourcery.com>
1602
1603 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
1604 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
1605 (struct asm_barrier_opt): Define.
1606 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
1607 (parse_psr): Accept V7M psr names.
1608 (parse_barrier): New function.
1609 (enum operand_parse_code): Add OP_oBARRIER.
1610 (parse_operands): Implement OP_oBARRIER.
1611 (do_barrier): New function.
1612 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
1613 (do_t_cpsi): Add V7M restrictions.
1614 (do_t_mrs, do_t_msr): Validate V7M variants.
1615 (md_assemble): Check for NULL variants.
1616 (v7m_psrs, barrier_opt_names): New tables.
1617 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
1618 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
1619 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
1620 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
1621 (struct cpu_arch_ver_table): Define.
1622 (cpu_arch_ver): New.
1623 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
1624 Tag_CPU_arch_profile.
1625 * doc/c-arm.texi: Document new cpu and arch options.
1626
59cf82fe
L		 16272006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1628
1629 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
1630
19a7219f
L		 16312006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1632
1633 * config/tc-ia64.c: Update copyright years.
1634
7f3dfb9c
L		 16352006-02-22 H.J. Lu <hongjiu.lu@intel.com>
1636
1637 * config/tc-ia64.c (specify_resource): Add the rule 17 from
1638 SDM 2.2.
1639
f40d1643
PB		 16402005-02-22 Paul Brook <paul@codesourcery.com>
1641
1642 * config/tc-arm.c (do_pld): Remove incorrect write to
1643 inst.instruction.
1644 (encode_thumb32_addr_mode): Use correct operand.
1645
216d22bc
PB		 16462006-02-21 Paul Brook <paul@codesourcery.com>
1647
1648 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
1649
d70c5fc7
NC		 16502006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
1651 Anil Paranjape <anilp1@kpitcummins.com>
1652 Shilin Shakti <shilins@kpitcummins.com>
1653
1654 * Makefile.am: Add xc16x related entry.
1655 * Makefile.in: Regenerate.
1656 * configure.in: Added xc16x related entry.
1657 * configure: Regenerate.
1658 * config/tc-xc16x.h: New file
1659 * config/tc-xc16x.c: New file
1660 * doc/c-xc16x.texi: New file for xc16x
1661 * doc/all.texi: Entry for xc16x
1662 * doc/Makefile.texi: Added c-xc16x.texi
1663 * NEWS: Announce the support for the new target.
1664
aaa2ab3d
NH		 16652006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
1666
1667 * configure.tgt: set emulation for mips-*-netbsd*
1668
82de001f
JJ		 16692006-02-14 Jakub Jelinek <jakub@redhat.com>
1670
1671 * config.in: Rebuilt.
1672
431ad2d0
BW		 16732006-02-13 Bob Wilson <bob.wilson@acm.org>
1674
1675 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
1676 from 1, not 0, in error messages.
1677 (md_assemble): Simplify special-case check for ENTRY instructions.
1678 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
1679 operand in error message.
1680
94089a50
JM		 16812006-02-13 Joseph S. Myers <joseph@codesourcery.com>
1682
1683 * configure.tgt (arm-*-linux-gnueabi*): Change to
1684 arm-*-linux-*eabi*.
1685
52de4c06
NC		 16862006-02-10 Nick Clifton <nickc@redhat.com>
1687
70e45ad9
NC		 1688 * config/tc-crx.c (check_range): Ensure that the sign bit of a
1689 32-bit value is propagated into the upper bits of a 64-bit long.
1690
52de4c06
NC		 1691 * config/tc-arc.c (init_opcode_tables): Fix cast.
1692 (arc_extoper, md_operand): Likewise.
1693
21af2bbd
BW		 16942006-02-09 David Heine <dlheine@tensilica.com>
1695
1696 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
1697 each relaxation step.
1698
75a706fc
L		 16992006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
1700
1701 * configure.in (CHECK_DECLS): Add vsnprintf.
1702 * configure: Regenerate.
1703 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
1704 include/declare here, but...
1705 * as.h: Move code detecting VARARGS idiom to the top.
1706 (errno.h, stdarg.h, varargs.h, va_list): ...here.
1707 (vsnprintf): Declare if not already declared.
1708
0d474464
L		 17092006-02-08 H.J. Lu <hongjiu.lu@intel.com>
1710
1711 * as.c (close_output_file): New.
1712 (main): Register close_output_file with xatexit before
1713 dump_statistics. Don't call output_file_close.
1714
266abb8f
NS		 17152006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1716
1717 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
1718 mcf5329_control_regs): New.
1719 (not_current_architecture, selected_arch, selected_cpu): New.
1720 (m68k_archs, m68k_extensions): New.
1721 (archs): Renamed to ...
1722 (m68k_cpus): ... here. Adjust.
1723 (n_arches): Remove.
1724 (md_pseudo_table): Add arch and cpu directives.
1725 (find_cf_chip, m68k_ip): Adjust table scanning.
1726 (no_68851, no_68881): Remove.
1727 (md_assemble): Lazily initialize.
1728 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
1729 (md_init_after_args): Move functionality to m68k_init_arch.
1730 (mri_chip): Adjust table scanning.
1731 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
1732 options with saner parsing.
1733 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
1734 m68k_init_arch): New.
1735 (s_m68k_cpu, s_m68k_arch): New.
1736 (md_show_usage): Adjust.
1737 (m68k_elf_final_processing): Set CF EF flags.
1738 * config/tc-m68k.h (m68k_init_after_args): Remove.
1739 (tc_init_after_args): Remove.
1740 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
1741 (M68k-Directives): Document .arch and .cpu directives.
1742
134dcee5
AM		 17432006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
1744
1745 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
1746 synonyms for equ and defl.
1747 (z80_cons_fix_new): New function.
1748 (emit_byte): Disallow relative jumps to absolute locations.
1749 (emit_data): Only handle defb, prototype changed, because defb is
1750 now handled as pseudo-op rather than an instruction.
1751 (instab): Entries for defb,defw,db,dw moved from here...
1752 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
1753 Add entries for def24,def32,d24,d32.
1754 (md_assemble): Improved error handling.
1755 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
1756 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
1757 (z80_cons_fix_new): Declare.
1758 * doc/c-z80.texi (defb, db): Mention warning on overflow.
1759 (def24,d24,def32,d32): New pseudo-ops.
1760
a9931606
PB		 17612006-02-02 Paul Brook <paul@codesourcery.com>
1762
1763 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1764
ef8d22e6
PB		 17652005-02-02 Paul Brook <paul@codesourcery.com>
1766
1767 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1768 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1769 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1770 T2_OPCODE_RSB): Define.
1771 (thumb32_negate_data_op): New function.
1772 (md_apply_fix): Use it.
1773
e7da6241
BW		 17742006-01-31 Bob Wilson <bob.wilson@acm.org>
1775
1776 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1777 fields.
1778 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1779 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1780 subtracted symbols.
1781 (relaxation_requirements): Add pfinish_frag argument and use it to
1782 replace setting tinsn->record_fix fields.
1783 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1784 and vinsn_to_insnbuf. Remove references to record_fix and
1785 slot_sub_symbols fields.
1786 (xtensa_mark_narrow_branches): Delete unused code.
1787 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1788 a symbol.
1789 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1790 record_fix fields.
1791 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1792 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1793 of the record_fix field. Simplify error messages for unexpected
1794 symbolic operands.
1795 (set_expr_symbol_offset_diff): Delete.
1796
79134647
PB		 17972006-01-31 Paul Brook <paul@codesourcery.com>
1798
1799 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1800
e74cfd16
PB		 18012006-01-31 Paul Brook <paul@codesourcery.com>
1802 Richard Earnshaw <rearnsha@arm.com>
1803
1804 * config/tc-arm.c: Use arm_feature_set.
1805 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1806 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1807 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1808 New variables.
1809 (insns): Use them.
1810 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1811 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1812 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1813 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1814 feature flags.
1815 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1816 (arm_opts): Move old cpu/arch options from here...
1817 (arm_legacy_opts): ... to here.
1818 (md_parse_option): Search arm_legacy_opts.
1819 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1820 (arm_float_abis, arm_eabis): Make const.
1821
d47d412e
BW		 18222006-01-25 Bob Wilson <bob.wilson@acm.org>
1823
1824 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1825
b14273fe
JZ		 18262006-01-21 Jie Zhang <jie.zhang@analog.com>
1827
1828 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1829 in load immediate intruction.
1830
39cd1c76
JZ		 18312006-01-21 Jie Zhang <jie.zhang@analog.com>
1832
1833 * config/bfin-parse.y (value_match): Use correct conversion
1834 specifications in template string for __FILE__ and __LINE__.
1835 (binary): Ditto.
1836 (unary): Ditto.
1837
67a4f2b7
AO		 18382006-01-18 Alexandre Oliva <aoliva@redhat.com>
1839
1840 Introduce TLS descriptors for i386 and x86_64.
1841 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1842 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1843 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1844 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1845 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1846 displacement bits.
1847 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1848 (lex_got): Handle @tlsdesc and @tlscall.
1849 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1850
8ad7c533
NC		 18512006-01-11 Nick Clifton <nickc@redhat.com>
1852
1853 Fixes for building on 64-bit hosts:
1854 * config/tc-avr.c (mod_index): New union to allow conversion
1855 between pointers and integers.
1856 (md_begin, avr_ldi_expression): Use it.
1857 * config/tc-i370.c (md_assemble): Add cast for argument to print
1858 statement.
1859 * config/tc-tic54x.c (subsym_substitute): Likewise.
1860 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1861 opindex field of fr_cgen structure into a pointer so that it can
1862 be stored in a frag.
1863 * config/tc-mn10300.c (md_assemble): Likewise.
1864 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1865 types.
1866 * config/tc-v850.c: Replace uses of (int) casts with correct
1867 types.
1868
4dcb3903
L		 18692006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1870
1871 PR gas/2117
1872 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1873
e0f6ea40
HPN		 18742006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1875
1876 PR gas/2101
1877 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1878 a local-label reference.
1879
e88d958a 1880For older changes see ChangeLog-2005
08d56133
NC		 1881\f
1882Local Variables:
1883mode: change-log
1884left-margin: 8
1885fill-column: 74
1886version-control: never
1887End:
GDB Binutils - Deliverables
This page took 0.353204 seconds and 4 git commands to generate.