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[deliverable/binutils-gdb.git] / gas / ChangeLog
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601e61cd
NC		 12006-07-24 Andreas Schwab <schwab@suse.de>
2
3 PR/2756
4 * read.c (read_a_source_file): Ignore unknown text after line
5 comment character. Fix misleading comment.
6
b45619c0
NC		 72006-07-24 Ralk Wildenhues <Ralf.Wildenhues@gmx.de>
8
9 * doc/all.texi, doc/as.texinfo, doc/c-arc.texi, doc/c-arm.texi,
10 doc/c-avr.texi, doc/c-bfin.texi, doc/c-i386.texi,
11 doc/c-i960.texi, doc/c-m32r.texi, doc/c-m68k.texi,
12 doc/c-mmix.texi, doc/c-pdp11.texi, doc/c-ppc.texi,
13 doc/c-tic54x.texi, doc/c-v850.texi, doc/c-xtensa.texi,
14 doc/c-z80.texi, doc/internals.texi: Fix some typos.
15
784906c5
NC		 162006-07-21 Nick Clifton <nickc@redhat.com>
17
18 * config/tc-sh.c (md_longopts): Add -EL and -EB for use by the
19 linker testsuite.
20
d5f010e9
TS		 212006-07-20 Thiemo Seufer <ths@mips.com>
22 Nigel Stephens <nigel@mips.com>
23
24 * config/tc-mips.c (md_parse_option): Don't infer optimisation
25 options from debug options.
26
35d3d567
TS		 272006-07-20 Thiemo Seufer <ths@mips.com>
28
29 * config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP.
30 (tc_gen_reloc): Handle mips16 jumps to section symbol offsets.
31
401a54cf
PB		 322006-07-19 Paul Brook <paul@codesourcery.com>
33
34 * config/tc-arm.c (insns): Fix rbit Arm opcode.
35
16805f35
PB		 362006-07-18 Paul Brook <paul@codesourcery.com>
37
38 * tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
39 (md_convert_frag): Use correct reloc for add_pc. Use
40 BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
41 (md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
42 (arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
43
d9e05e4e
AM		 442006-07-17 Mat Hostetter <mat@lcs.mit.edu>
45
46 * symbols.c (report_op_error): Fix pasto. Don't use as_bad_where
47 when file and line unknown.
48
f43abd2b
TS		 492006-07-17 Thiemo Seufer <ths@mips.com>
50
51 * read.c (s_struct): Use IS_ELF.
52 * config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
53 md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
54 tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
55 s_mips_mask): Likewise.
56
a2902af6
TS		 572006-07-16 Thiemo Seufer <ths@mips.com>
58 David Ung <davidu@mips.com>
59
60 * read.c (s_struct): Handle ELF section changing.
61 * config/tc-mips.c (s_align): Leave enabling auto-align to the
62 generic code.
63 (s_change_sec): Try section changing only if we output ELF.
64
d32cad65
L		 652006-07-15 H.J. Lu <hongjiu.lu@intel.com>
66
67 * config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
68 CpuAmdFam10.
69 (smallest_imm_type): Remove Cpu086.
70 (i386_target_format): Likewise.
71
72 * config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
73 Update CpuXXX.
74
050dfa73
MM		 752006-07-13 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
76 Michael Meissner <michael.meissner@amd.com>
77
78 * config/tc-i386.h (PROCESSOR_AMDFAM10): New processor_type.
79 (CpuSSE4a, CpuABM, CpuAmdFam10): New Cpu directives.
80 * config/tc-i386.c (cpu_arch): Add support for AmdFam10
81 architecture.
82 (i386_align_code): Ditto.
83 (md_assemble_code): Add support for insertq/extrq instructions,
84 swapping as needed for intel syntax.
85 (swap_imm_operands): New function to swap immediate operands.
86 (swap_operands): Deal with 4 operand instructions.
87 (build_modrm_byte): Add support for insertq instruction.
88
6b2de085
L		 892006-07-13 H.J. Lu <hongjiu.lu@intel.com>
90
91 * config/tc-i386.h (Size64): Fix a typo in comment.
92
01eaea5a
NC		 932006-07-12 Nick Clifton <nickc@redhat.com>
94
95 * config/tc-sh.c (md_apply_fix): Do not allow the generic code in
7cfe9437 96 fixup_segment() to repeat a range check on a value that has
01eaea5a
NC		 97 already been checked here.
98
1e85aad8
JW		 992006-07-07 James E Wilson <wilson@specifix.com>
100
101 * config/tc-mips.c (mips_cpu_info_table): Add sb1a.
102
1370e33d
NC		 1032006-07-06 Mohammed Adnène Trojette <adn@diwi.org>
104 Nick Clifton <nickc@redhat.com>
105
106 PR binutils/2877
107 * doc/as.texi: Fix spelling typo: branchs => branches.
108 * doc/c-m68hc11.texi: Likewise.
109 * config/tc-m68hc11.c: Likewise.
110 Support old spelling of command line switch for backwards
111 compatibility.
112
5f0fe04b
TS		 1132006-07-04 Thiemo Seufer <ths@mips.com>
114 David Ung <davidu@mips.com>
115
116 * config/tc-mips.c (s_is_linkonce): New function.
117 (mips16_mark_labels): Don't adjust mips16 symbol addresses for
118 weak, external, and linkonce symbols.
119 (pic_need_relax): Use s_is_linkonce.
120
85234291
L		 1212006-06-24 H.J. Lu <hongjiu.lu@intel.com>
122
123 * doc/as.texinfo (Org): Remove space.
124 (P2align): Add "@var{abs-expr},".
125
ccc9c027
L		 1262006-06-23 H.J. Lu <hongjiu.lu@intel.com>
127
128 * config/tc-i386.c (cpu_arch_tune_set): New.
129 (cpu_arch_isa): Likewise.
130 (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
131 nops with short or long nop sequences based on -march=/.arch
132 and -mtune=.
133 (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
134 set cpu_arch_tune and cpu_arch_tune_flags.
135 (md_parse_option): For -march=, set cpu_arch_isa and set
136 cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
137 0. Set cpu_arch_tune_set to 1 for -mtune=.
138 (i386_target_format): Don't set cpu_arch_tune.
139
d4dc2f22
TS		 1402006-06-23 Nigel Stephens <nigel@mips.com>
141
142 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
143 generated .sbss.* and .gnu.linkonce.sb.*.
144
a8dbcb85
TS		 1452006-06-23 Thiemo Seufer <ths@mips.com>
146 David Ung <davidu@mips.com>
147
148 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
149 label_list.
150 * config/tc-mips.c (label_list): Define per-segment label_list.
151 (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
152 append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
153 mips_from_file_after_relocs, mips_define_label): Use per-segment
154 label_list.
155
3994f87e
TS		 1562006-06-22 Thiemo Seufer <ths@mips.com>
157
158 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
159 (append_insn): Use it.
160 (md_apply_fix): Whitespace formatting.
161 (md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
162 mips16_extended_frag): Remove register specifier.
163 (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
164 constants.
165
fa073d69
MS		 1662006-06-21 Mark Shinwell <shinwell@codesourcery.com>
167
168 * config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
169 a directive saving VFP registers for ARMv6 or later.
170 (s_arm_unwind_save): Add parameter arch_v6 and call
171 s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
172 appropriate.
173 (md_pseudo_table): Add entry for new "vsave" directive.
174 * doc/c-arm.texi: Correct error in example for "save"
175 directive (fstmdf -> fstmdx). Also document "vsave" directive.
176
8e77b565 1772006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
026dcbd7
DC		 178 Anatoly Sokolov <aesok@post.ru>
179
180 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
181 and atmega644p devices. Rename atmega164/atmega324 devices to
182 atmega164p/atmega324p.
183 * doc/c-avr.texi: Document new mcu and arch options.
184
8b1ad454
NC		 1852006-06-17 Nick Clifton <nickc@redhat.com>
186
187 * config/tc-arm.c (enum parse_operand_result): Move outside of
188 #ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
189
9103f4f4
L		 1902006-06-16 H.J. Lu <hongjiu.lu@intel.com>
191
192 * config/tc-i386.h (processor_type): New.
193 (arch_entry): Add type.
194
195 * config/tc-i386.c (cpu_arch_tune): New.
196 (cpu_arch_tune_flags): Likewise.
197 (cpu_arch_isa_flags): Likewise.
198 (cpu_arch): Updated.
199 (set_cpu_arch): Also update cpu_arch_isa_flags.
200 (md_assemble): Update cpu_arch_isa_flags.
201 (OPTION_MARCH): New.
202 (OPTION_MTUNE): Likewise.
203 (md_longopts): Add -march= and -mtune=.
204 (md_parse_option): Support -march= and -mtune=.
205 (md_show_usage): Add -march=CPU/-mtune=CPU.
206 (i386_target_format): Also update cpu_arch_isa_flags,
207 cpu_arch_tune and cpu_arch_tune_flags.
208
209 * doc/as.texinfo: Add -march=CPU/-mtune=CPU.
210
211 * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
212
4962c51a
MS		 2132006-06-15 Mark Shinwell <shinwell@codesourcery.com>
214
215 * config/tc-arm.c (enum parse_operand_result): New.
216 (struct group_reloc_table_entry): New.
217 (enum group_reloc_type): New.
218 (group_reloc_table): New array.
219 (find_group_reloc_table_entry): New function.
220 (parse_shifter_operand_group_reloc): New function.
221 (parse_address_main): New function, incorporating code
222 from the old parse_address function. To be used via...
223 (parse_address): wrapper for parse_address_main; and
224 (parse_address_group_reloc): new function, likewise.
225 (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
226 OP_ADDRGLDRS, OP_ADDRGLDC.
227 (parse_operands): Support for these new operand codes.
228 New macro po_misc_or_fail_no_backtrack.
229 (encode_arm_cp_address): Preserve group relocations.
230 (insns): Modify to use the above operand codes where group
231 relocations are permitted.
232 (md_apply_fix): Handle the group relocations
233 ALU_PC_G0_NC through LDC_SB_G2.
234 (tc_gen_reloc): Likewise.
235 (arm_force_relocation): Leave group relocations for the linker.
236 (arm_fix_adjustable): Likewise.
237
cd2f129f
JB		 2382006-06-15 Julian Brown <julian@codesourcery.com>
239
240 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
241 (do_neon_ldr_str): Always defer to VFP encoding routines, which handle
242 relocs properly.
243
46e883c5
L		 2442006-06-12 H.J. Lu <hongjiu.lu@intel.com>
245
246 * config/tc-i386.c (process_suffix): Don't add rex64 for
247 "xchg %rax,%rax".
248
1787fe5b
TS		 2492006-06-09 Thiemo Seufer <ths@mips.com>
250
251 * config/tc-mips.c (mips_ip): Maintain argument count.
252
96f989c2
AM		 2532006-06-09 Alan Modra <amodra@bigpond.net.au>
254
255 * config/tc-iq2000.c: Include sb.h.
256
7c752c2a
TS		 2572006-06-08 Nigel Stephens <nigel@mips.com>
258
259 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
260 aliases for better compatibility with SGI tools.
261
03bf704f
AM		 2622006-06-08 Alan Modra <amodra@bigpond.net.au>
263
264 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
265 * Makefile.am (GASLIBS): Expand @BFDLIB@.
266 (BFDVER_H): Delete.
267 (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
268 (obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
269 (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
270 Run "make dep-am".
271 * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
272 * Makefile.in: Regenerate.
273 * doc/Makefile.in: Regenerate.
274 * configure: Regenerate.
275
6648b7cf
JM		 2762006-06-07 Joseph S. Myers <joseph@codesourcery.com>
277
278 * po/Make-in (pdf, ps): New dummy targets.
279
037e8744
JB		 2802006-06-07 Julian Brown <julian@codesourcery.com>
281
282 * config/tc-arm.c (stdarg.h): include.
283 (arm_it): Add uncond_value field. Add isvec and issingle to operand
284 array.
285 (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
286 REG_TYPE_NSDQ (single, double or quad vector reg).
287 (reg_expected_msgs): Update.
288 (BAD_FPU): Add macro for unsupported FPU instruction error.
289 (parse_neon_type): Support 'd' as an alias for .f64.
290 (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
291 sets of registers.
292 (parse_vfp_reg_list): Don't update first arg on error.
293 (parse_neon_mov): Support extra syntax for VFP moves.
294 (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
295 OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
296 (parse_operands): Support isvec, issingle operands fields, new parse
297 codes above.
298 (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
299 msr variants.
300 (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
301 (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
302 (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
303 (NEON_SHAPE_DEF): New macro. Define table of possible instruction
304 shapes.
305 (neon_shape): Redefine in terms of above.
306 (neon_shape_class): New enumeration, table of shape classes.
307 (neon_shape_el): New enumeration. One element of a shape.
308 (neon_shape_el_size): Register widths of above, where appropriate.
309 (neon_shape_info): New struct. Info for shape table.
310 (neon_shape_tab): New array.
311 (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
312 (neon_check_shape): Rewrite as...
313 (neon_select_shape): New function to classify instruction shapes,
314 driven by new table neon_shape_tab array.
315 (neon_quad): New function. Return 1 if shape should set Q flag in
316 instructions (or equivalent), 0 otherwise.
317 (type_chk_of_el_type): Support F64.
318 (el_type_of_type_chk): Likewise.
319 (neon_check_type): Add support for VFP type checking (VFP data
320 elements fill their containing registers).
321 (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
322 in thumb mode for VFP instructions.
323 (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
324 and encode the current instruction as if it were that opcode.
325 (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
326 arguments, call function in PFN.
327 (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
328 (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
329 (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
330 (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
331 (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
332 Redirect Neon-syntax VFP instructions to VFP instruction handlers.
333 (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
334 (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
335 (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
336 (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
337 (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
338 (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
339 (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
340 (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
341 (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
342 neon_quad.
343 (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
344 between VFP and Neon turns out to belong to Neon. Perform
345 architecture check and fill in condition field if appropriate.
346 (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
347 (do_neon_cvt): Add support for VFP variants of instructions.
348 (neon_cvt_flavour): Extend to cover VFP conversions.
349 (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
350 vmov variants.
351 (do_neon_ldr_str): Handle single-precision VFP load/store.
352 (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
353 NS_NULL not NS_IGNORE.
354 (opcode_tag): Add OT_csuffixF for operands which either take a
355 conditional suffix, or have 0xF in the condition field.
356 (md_assemble): Add support for OT_csuffixF.
357 (NCE): Replace macro with...
358 (NCE_tag, NCE, NCEF): New macros.
359 (nCE): Replace macro with...
360 (nCE_tag, nCE, nCEF): New macros.
361 (insns): Add support for VFP insns or VFP versions of insns msr,
362 mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
363 vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
364 vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
365 VFP/Neon insns together.
366
ebd1c875
AM		 3672006-06-07 Alan Modra <amodra@bigpond.net.au>
368 Ladislav Michl <ladis@linux-mips.org>
369
370 * app.c: Don't include headers already included by as.h.
371 * as.c: Likewise.
372 * atof-generic.c: Likewise.
373 * cgen.c: Likewise.
374 * dwarf2dbg.c: Likewise.
375 * expr.c: Likewise.
376 * input-file.c: Likewise.
377 * input-scrub.c: Likewise.
378 * macro.c: Likewise.
379 * output-file.c: Likewise.
380 * read.c: Likewise.
381 * sb.c: Likewise.
382 * config/bfin-lex.l: Likewise.
383 * config/obj-coff.h: Likewise.
384 * config/obj-elf.h: Likewise.
385 * config/obj-som.h: Likewise.
386 * config/tc-arc.c: Likewise.
387 * config/tc-arm.c: Likewise.
388 * config/tc-avr.c: Likewise.
389 * config/tc-bfin.c: Likewise.
390 * config/tc-cris.c: Likewise.
391 * config/tc-d10v.c: Likewise.
392 * config/tc-d30v.c: Likewise.
393 * config/tc-dlx.h: Likewise.
394 * config/tc-fr30.c: Likewise.
395 * config/tc-frv.c: Likewise.
396 * config/tc-h8300.c: Likewise.
397 * config/tc-hppa.c: Likewise.
398 * config/tc-i370.c: Likewise.
399 * config/tc-i860.c: Likewise.
400 * config/tc-i960.c: Likewise.
401 * config/tc-ip2k.c: Likewise.
402 * config/tc-iq2000.c: Likewise.
403 * config/tc-m32c.c: Likewise.
404 * config/tc-m32r.c: Likewise.
405 * config/tc-maxq.c: Likewise.
406 * config/tc-mcore.c: Likewise.
407 * config/tc-mips.c: Likewise.
408 * config/tc-mmix.c: Likewise.
409 * config/tc-mn10200.c: Likewise.
410 * config/tc-mn10300.c: Likewise.
411 * config/tc-msp430.c: Likewise.
412 * config/tc-mt.c: Likewise.
413 * config/tc-ns32k.c: Likewise.
414 * config/tc-openrisc.c: Likewise.
415 * config/tc-ppc.c: Likewise.
416 * config/tc-s390.c: Likewise.
417 * config/tc-sh.c: Likewise.
418 * config/tc-sh64.c: Likewise.
419 * config/tc-sparc.c: Likewise.
420 * config/tc-tic30.c: Likewise.
421 * config/tc-tic4x.c: Likewise.
422 * config/tc-tic54x.c: Likewise.
423 * config/tc-v850.c: Likewise.
424 * config/tc-vax.c: Likewise.
425 * config/tc-xc16x.c: Likewise.
426 * config/tc-xstormy16.c: Likewise.
427 * config/tc-xtensa.c: Likewise.
428 * config/tc-z80.c: Likewise.
429 * config/tc-z8k.c: Likewise.
430 * macro.h: Don't include sb.h or ansidecl.h.
431 * sb.h: Don't include stdio.h or ansidecl.h.
432 * cond.c: Include sb.h.
433 * itbl-lex.l: Include as.h instead of other system headers.
434 * itbl-parse.y: Likewise.
435 * itbl-ops.c: Similarly.
436 * itbl-ops.h: Don't include as.h or ansidecl.h.
437 * config/bfin-defs.h: Don't include bfd.h or as.h.
438 * config/bfin-parse.y: Include as.h instead of other system headers.
439
9622b051
AM		 4402006-06-06 Ben Elliston <bje@au.ibm.com>
441 Anton Blanchard <anton@samba.org>
442
443 * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
444 (md_show_usage): Document it.
445 (ppc_setup_opcodes): Test power6 opcode flag bits.
446 * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
447
65263ce3
TS		 4482006-06-06 Thiemo Seufer <ths@mips.com>
449 Chao-ying Fu <fu@mips.com>
450
451 * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
452 (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
453 (macro_build): Update comment.
454 (mips_ip): Allow DSP64 instructions for MIPS64R2.
455 (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
456 CPU_HAS_MDMX.
457 (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
458 MIPS_CPU_ASE_MDMX flags for sb1.
459
a9e24354
TS		 4602006-06-05 Thiemo Seufer <ths@mips.com>
461
462 * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
463 appropriate.
464 (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
465 (mips_ip): Make overflowed/underflowed constant arguments in DSP
466 and MT instructions a fatal error. Use INSERT_OPERAND where
467 appropriate. Improve warnings for break and wait code overflows.
468 Use symbolic constant of OP_MASK_COPZ.
469 (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
470
4cfe2c59
DJ		 4712006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
472
473 * po/Make-in (top_builddir): Define.
474
e10fad12
JM		 4752006-06-02 Joseph S. Myers <joseph@codesourcery.com>
476
477 * doc/Makefile.am (TEXI2DVI): Define.
478 * doc/Makefile.in: Regenerate.
479 * doc/c-arc.texi: Fix typo.
480
12e64c2c
AM		 4812006-06-01 Alan Modra <amodra@bigpond.net.au>
482
483 * config/obj-ieee.c: Delete.
484 * config/obj-ieee.h: Delete.
485 * Makefile.am (OBJ_FORMATS): Remove ieee.
486 (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
487 (obj-ieee.o): Remove rule.
488 * Makefile.in: Regenerate.
489 * configure.in (atof): Remove tahoe.
490 (OBJ_MAYBE_IEEE): Don't define.
491 * configure: Regenerate.
492 * config.in: Regenerate.
493 * doc/Makefile.in: Regenerate.
494 * po/POTFILES.in: Regenerate.
495
20e95c23
DJ		 4962006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
497
498 * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
499 and LIBINTL_DEP everywhere.
500 (INTLLIBS): Remove.
501 (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
502 * acinclude.m4: Include new gettext macros.
503 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
504 Remove local code for po/Makefile.
505 * Makefile.in, configure, doc/Makefile.in: Regenerated.
506
eebf07fb
NC		 5072006-05-30 Nick Clifton <nickc@redhat.com>
508
509 * po/es.po: Updated Spanish translation.
510
b6aee19e
DC		 5112006-05-06 Denis Chertykov <denisc@overta.ru>
512
513 * doc/c-avr.texi: New file.
514 * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
515 * doc/all.texi: Set AVR
516 * doc/as.texinfo: Include c-avr.texi
517
f8fdc850
JZ		 5182006-05-28 Jie Zhang <jie.zhang@analog.com>
519
520 * config/bfin-parse.y (check_macfunc): Loose the condition of
521 calling check_multiply_halfregs ().
522
a3205465
JZ		 5232006-05-25 Jie Zhang <jie.zhang@analog.com>
524
525 * config/bfin-parse.y (asm_1): Better check and deal with
526 vector and scalar Multiply 16-Bit Operands instructions.
527
9b52905e
NC		 5282006-05-24 Nick Clifton <nickc@redhat.com>
529
530 * config/tc-hppa.c: Convert to ISO C90 format.
531 * config/tc-hppa.h: Likewise.
532
5332006-05-24 Carlos O'Donell <carlos@systemhalted.org>
534 Randolph Chung <randolph@tausq.org>
535
536 * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
537 is_tls_ieoff, is_tls_leoff): Define.
538 (fix_new_hppa): Handle TLS.
539 (cons_fix_new_hppa): Likewise.
540 (pa_ip): Likewise.
541 (md_apply_fix): Handle TLS relocs.
542 * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
543
28c9d252
NC		 5442006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
545
546 * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
547
ad3fea08
TS		 5482006-05-23 Thiemo Seufer <ths@mips.com>
549 David Ung <davidu@mips.com>
550 Nigel Stephens <nigel@mips.com>
551
552 [ gas/ChangeLog ]
553 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
554 (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
555 ISA_HAS_MXHC1): New macros.
556 (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
557 ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
558 (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
559 (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
560 MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
561 (mips_after_parse_args): Change default handling of float register
562 size to account for 32bit code with 64bit FP. Better sanity checking
563 of ISA/ASE/ABI option combinations.
564 (s_mipsset): Support switching of GPR and FPR sizes via
565 .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
566 options.
567 (mips_elf_final_processing): We should record the use of 64bit FP
568 registers in 32bit code but we don't, because ELF header flags are
569 a scarce ressource.
570 (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
571 extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
572 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
573 (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
574 * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
575 missing -march options. Document .set arch=CPU. Move .set smartmips
576 to ASE page. Use @code for .set FOO examples.
577
8b64503a
JZ		 5782006-05-23 Jie Zhang <jie.zhang@analog.com>
579
580 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
581 if needed.
582
403022e0
JZ		 5832006-05-23 Jie Zhang <jie.zhang@analog.com>
584
585 * config/bfin-defs.h (bfin_equals): Remove declaration.
586 * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
587 * config/tc-bfin.c (bfin_name_is_register): Remove.
588 (bfin_equals): Remove.
589 * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
590 (bfin_name_is_register): Remove declaration.
591
7455baf8
TS		 5922006-05-19 Thiemo Seufer <ths@mips.com>
593 Nigel Stephens <nigel@mips.com>
594
595 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
596 (mips_oddfpreg_ok): New function.
597 (mips_ip): Use it.
598
707bfff6
TS		 5992006-05-19 Thiemo Seufer <ths@mips.com>
600 David Ung <davidu@mips.com>
601
602 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
603 * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
604 ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
605 (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
606 RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
607 RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
608 FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
609 N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
610 SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
611 MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
612 reg_names_o32, reg_names_n32n64): Define register classes.
613 (reg_lookup): New function, use register classes.
614 (md_begin): Reserve register names in the symbol table. Simplify
615 OBJ_ELF defines.
616 (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
617 Use reg_lookup.
618 (mips16_ip): Use reg_lookup.
619 (tc_get_register): Likewise.
620 (tc_mips_regname_to_dw2regnum): New function.
621
1df69f4f
TS		 6222006-05-19 Thiemo Seufer <ths@mips.com>
623
624 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
625 Un-constify string argument.
626 * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
627 Likewise.
628 * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
629 Likewise.
630 * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
631 Likewise.
632 * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
633 Likewise.
634 * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
635 Likewise.
636 * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
637 Likewise.
638
377260ba
NS		 6392006-05-19 Nathan Sidwell <nathan@codesourcery.com>
640
641 * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
642 cfloat/m68881 to correct architecture before using it.
643
cce7653b
NC		 6442006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
645
646 * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
647 constant values.
648
b0796911
PB		 6492006-05-15 Paul Brook <paul@codesourcery.com>
650
651 * config/tc-arm.c (arm_adjust_symtab): Use
652 bfd_is_arm_special_symbol_name.
653
64b607e6
BW		 6542006-05-15 Bob Wilson <bob.wilson@acm.org>
655
656 * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
657 xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
658 xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
659 Handle errors from calls to xtensa_opcode_is_* functions.
660
9b3f89ee
TS		 6612006-05-14 Thiemo Seufer <ths@mips.com>
662
663 * config/tc-mips.c (macro_build): Test for currently active
664 mips16 option.
665 (mips16_ip): Reject invalid opcodes.
666
370b66a1
CD		 6672006-05-11 Carlos O'Donell <carlos@codesourcery.com>
668
669 * doc/as.texinfo: Rename "Index" to "AS Index",
670 and "ABORT" to "ABORT (COFF)".
671
b6895b4f
PB		 6722006-05-11 Paul Brook <paul@codesourcery.com>
673
674 * config/tc-arm.c (parse_half): New function.
675 (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
676 (parse_operands): Ditto.
677 (do_mov16): Reject invalid relocations.
678 (do_t_mov16): Ditto. Use Thumb reloc numbers.
679 (insns): Replace Iffff with HALF.
680 (md_apply_fix): Add MOVW and MOVT relocs.
681 (tc_gen_reloc): Ditto.
682 * doc/c-arm.texi: Document relocation operators
683
e28387c3
PB		 6842006-05-11 Paul Brook <paul@codesourcery.com>
685
686 * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
687
89ee2ebe
TS		 6882006-05-11 Thiemo Seufer <ths@mips.com>
689
690 * config/tc-mips.c (append_insn): Don't check the range of j or
691 jal addresses.
692
53baae48
NC		 6932006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
694
695 * config/tc-arm.c (md_pcrel_from_section): Force a bias for
696 relocs against external symbols for WinCE targets.
697 (md_apply_fix): Likewise.
698
4e2a74a8
TS		 6992006-05-09 David Ung <davidu@mips.com>
700
701 * config/tc-mips.c (append_insn): Only warn about an out-of-range
702 j or jal address.
703
337ff0a5
NC		 7042006-05-09 Nick Clifton <nickc@redhat.com>
705
706 * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
707 against symbols which are not going to be placed into the symbol
708 table.
709
8c9f705e
BE		 7102006-05-09 Ben Elliston <bje@au.ibm.com>
711
712 * expr.c (operand): Remove `if (0 && ..)' statement and
713 subsequently unused target_op label. Collapse `if (1 || ..)'
714 statement.
715 * app.c (do_scrub_chars): Remove unused case 0, as it is handled
716 separately above the switch.
717
2fd0d2ac
NC		 7182006-05-08 Nick Clifton <nickc@redhat.com>
719
720 PR gas/2623
721 * config/tc-msp430.c (line_separator_character): Define as |.
722
e16bfa71
TS		 7232006-05-08 Thiemo Seufer <ths@mips.com>
724 Nigel Stephens <nigel@mips.com>
725 David Ung <davidu@mips.com>
726
727 * config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
728 (mips_opts): Likewise.
729 (file_ase_smartmips): New variable.
730 (ISA_HAS_ROR): SmartMIPS implements rotate instructions.
731 (macro_build): Handle SmartMIPS instructions.
732 (mips_ip): Likewise.
733 (md_longopts): Add argument handling for smartmips.
734 (md_parse_options, mips_after_parse_args): Likewise.
735 (s_mipsset): Add .set smartmips support.
736 (md_show_usage): Document -msmartmips/-mno-smartmips.
737 * doc/as.texinfo: Document -msmartmips/-mno-smartmips and
738 .set smartmips.
739 * doc/c-mips.texi: Likewise.
740
32638454
AM		 7412006-05-08 Alan Modra <amodra@bigpond.net.au>
742
743 * write.c (relax_segment): Add pass count arg. Don't error on
744 negative org/space on first two passes.
745 (relax_seg_info): New struct.
746 (relax_seg, write_object_file): Adjust.
747 * write.h (relax_segment): Update prototype.
748
b7fc2769
JB		 7492006-05-05 Julian Brown <julian@codesourcery.com>
750
751 * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
752 checking.
753 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
754 architecture version checks.
755 (insns): Allow overlapping instructions to be used in VFP mode.
756
7f841127
L		 7572006-05-05 H.J. Lu <hongjiu.lu@intel.com>
758
759 PR gas/2598
760 * config/obj-elf.c (obj_elf_change_section): Allow user
761 specified SHF_ALPHA_GPREL.
762
73160847
NC		 7632006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
764
765 * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
766 for PMEM related expressions.
767
56487c55
NC		 7682006-05-05 Nick Clifton <nickc@redhat.com>
769
770 PR gas/2582
771 * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
772 insertion of a directory separator character into a string at a
773 given offset. Uses heuristics to decide when to use a backslash
774 character rather than a forward-slash character.
775 (dwarf2_directive_loc): Use the macro.
776 (out_debug_info): Likewise.
777
d43b4baf
TS		 7782006-05-05 Thiemo Seufer <ths@mips.com>
779 David Ung <davidu@mips.com>
780
781 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
782 instruction.
783 (macro): Add new case M_CACHE_AB.
784
088fa78e
KH		 7852006-05-04 Kazu Hirata <kazu@codesourcery.com>
786
787 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
788 (opcode_lookup): Issue a warning for opcode with
789 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
790 identical to OT_cinfix3.
791 (TxC3w, TC3w, tC3w): New.
792 (insns): Use tC3w and TC3w for comparison instructions with
793 's' suffix.
794
c9049d30
AM		 7952006-05-04 Alan Modra <amodra@bigpond.net.au>
796
797 * subsegs.h (struct frchain): Delete frch_seg.
798 (frchain_root): Delete.
799 (seg_info): Define as macro.
800 * subsegs.c (frchain_root): Delete.
801 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
802 (subsegs_begin, subseg_change): Adjust for above.
803 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
804 rather than to one big list.
805 (subseg_get): Don't special case abs, und sections.
806 (subseg_new, subseg_force_new): Don't set frchainP here.
807 (seg_info): Delete.
808 (subsegs_print_statistics): Adjust frag chain control list traversal.
809 * debug.c (dmp_frags): Likewise.
810 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
811 at frchain_root. Make use of known frchain ordering.
812 (last_frag_for_seg): Likewise.
813 (get_frag_fix): Likewise. Add seg param.
814 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
815 * write.c (chain_frchains_together_1): Adjust for struct frchain.
816 (SUB_SEGMENT_ALIGN): Likewise.
817 (subsegs_finish): Adjust frchain list traversal.
818 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
819 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
820 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
821 (xtensa_fix_b_j_loop_end_frags): Likewise.
822 (xtensa_fix_close_loop_end_frags): Likewise.
823 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
824 (retrieve_segment_info): Delete frch_seg initialisation.
825
f592407e
AM		 8262006-05-03 Alan Modra <amodra@bigpond.net.au>
827
828 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
829 * config/obj-elf.h (obj_sec_set_private_data): Delete.
830 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
831 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
832
df7849c5
JM		 8332006-05-02 Joseph Myers <joseph@codesourcery.com>
834
835 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
836 here.
837 (md_apply_fix3): Multiply offset by 4 here for
838 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
839
2d545b82
L		 8402006-05-02 H.J. Lu <hongjiu.lu@intel.com>
841 Jan Beulich <jbeulich@novell.com>
842
843 * config/tc-i386.c (output_invalid_buf): Change size for
844 unsigned char.
845 * config/tc-tic30.c (output_invalid_buf): Likewise.
846
847 * config/tc-i386.c (output_invalid): Cast none-ascii char to
848 unsigned char.
849 * config/tc-tic30.c (output_invalid): Likewise.
850
38fc1cb1
DJ		 8512006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
852
853 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
854 (TEXI2POD): Use AM_MAKEINFOFLAGS.
855 (asconfig.texi): Don't set top_srcdir.
856 * doc/as.texinfo: Don't use top_srcdir.
857 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
858
2d545b82
L		 8592006-05-02 H.J. Lu <hongjiu.lu@intel.com>
860
861 * config/tc-i386.c (output_invalid_buf): Change size to 16.
862 * config/tc-tic30.c (output_invalid_buf): Likewise.
863
864 * config/tc-i386.c (output_invalid): Use snprintf instead of
865 sprintf.
866 * config/tc-ia64.c (declare_register_set): Likewise.
867 (emit_one_bundle): Likewise.
868 (check_dependencies): Likewise.
869 * config/tc-tic30.c (output_invalid): Likewise.
870
a8bc6c78
PB		 8712006-05-02 Paul Brook <paul@codesourcery.com>
872
873 * config/tc-arm.c (arm_optimize_expr): New function.
874 * config/tc-arm.h (md_optimize_expr): Define
875 (arm_optimize_expr): Add prototype.
876 (TC_FORCE_RELOCATION_SUB_SAME): Define.
877
58633d9a
BE		 8782006-05-02 Ben Elliston <bje@au.ibm.com>
879
22772e33
BE		 880 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
881 field unsigned.
882
58633d9a
BE		 883 * sb.h (sb_list_vector): Move to sb.c.
884 * sb.c (free_list): Use type of sb_list_vector directly.
885 (sb_build): Fix off-by-one error in assertion about `size'.
886
89cdfe57
BE		 8872006-05-01 Ben Elliston <bje@au.ibm.com>
888
889 * listing.c (listing_listing): Remove useless loop.
890 * macro.c (macro_expand): Remove is_positional local variable.
891 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
892 and simplify surrounding expressions, where possible.
893 (assign_symbol): Likewise.
894 (s_weakref): Likewise.
895 * symbols.c (colon): Likewise.
896
c35da140
AM		 8972006-05-01 James Lemke <jwlemke@wasabisystems.com>
898
899 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
900
9bcd4f99
TS		 9012006-04-30 Thiemo Seufer <ths@mips.com>
902 David Ung <davidu@mips.com>
903
904 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
905 (mips_immed): New table that records various handling of udi
906 instruction patterns.
907 (mips_ip): Adds udi handling.
908
001ae1a4
AM		 9092006-04-28 Alan Modra <amodra@bigpond.net.au>
910
911 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
912 of list rather than beginning.
913
136da414
JB		 9142006-04-26 Julian Brown <julian@codesourcery.com>
915
916 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
917 (is_quarter_float): Rename from above. Simplify slightly.
918 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
919 number.
920 (parse_neon_mov): Parse floating-point constants.
921 (neon_qfloat_bits): Fix encoding.
922 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
923 preference to integer encoding when using the F32 type.
924
dcbf9037
JB		 9252006-04-26 Julian Brown <julian@codesourcery.com>
926
927 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
928 zero-initialising structures containing it will lead to invalid types).
929 (arm_it): Add vectype to each operand.
930 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
931 defined field.
932 (neon_typed_alias): New structure. Extra information for typed
933 register aliases.
934 (reg_entry): Add neon type info field.
935 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
936 Break out alternative syntax for coprocessor registers, etc. into...
937 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
938 out from arm_reg_parse.
939 (parse_neon_type): Move. Return SUCCESS/FAIL.
940 (first_error): New function. Call to ensure first error which occurs is
941 reported.
942 (parse_neon_operand_type): Parse exactly one type.
943 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
944 (parse_typed_reg_or_scalar): New function. Handle core of both
945 arm_typed_reg_parse and parse_scalar.
946 (arm_typed_reg_parse): Parse a register with an optional type.
947 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
948 result.
949 (parse_scalar): Parse a Neon scalar with optional type.
950 (parse_reg_list): Use first_error.
951 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
952 (neon_alias_types_same): New function. Return true if two (alias) types
953 are the same.
954 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
955 of elements.
956 (insert_reg_alias): Return new reg_entry not void.
957 (insert_neon_reg_alias): New function. Insert type/index information as
958 well as register for alias.
959 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
960 make typed register aliases accordingly.
961 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
962 of line.
963 (s_unreq): Delete type information if present.
964 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
965 (s_arm_unwind_save_mmxwcg): Likewise.
966 (s_arm_unwind_movsp): Likewise.
967 (s_arm_unwind_setfp): Likewise.
968 (parse_shift): Likewise.
969 (parse_shifter_operand): Likewise.
970 (parse_address): Likewise.
971 (parse_tb): Likewise.
972 (tc_arm_regname_to_dw2regnum): Likewise.
973 (md_pseudo_table): Add dn, qn.
974 (parse_neon_mov): Handle typed operands.
975 (parse_operands): Likewise.
976 (neon_type_mask): Add N_SIZ.
977 (N_ALLMODS): New macro.
978 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
979 (el_type_of_type_chk): Add some safeguards.
980 (modify_types_allowed): Fix logic bug.
981 (neon_check_type): Handle operands with types.
982 (neon_three_same): Remove redundant optional arg handling.
983 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
984 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
985 (do_neon_step): Adjust accordingly.
986 (neon_cmode_for_logic_imm): Use first_error.
987 (do_neon_bitfield): Call neon_check_type.
988 (neon_dyadic): Rename to...
989 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
990 to allow modification of type of the destination.
991 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
992 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
993 (do_neon_compare): Make destination be an untyped bitfield.
994 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
995 (neon_mul_mac): Return early in case of errors.
996 (neon_move_immediate): Use first_error.
997 (neon_mac_reg_scalar_long): Fix type to include scalar.
998 (do_neon_dup): Likewise.
999 (do_neon_mov): Likewise (in several places).
1000 (do_neon_tbl_tbx): Fix type.
1001 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
1002 (do_neon_ld_dup): Exit early in case of errors and/or use
1003 first_error.
1004 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
1005 Handle .dn/.qn directives.
1006 (REGDEF): Add zero for reg_entry neon field.
1007
5287ad62
JB		 10082006-04-26 Julian Brown <julian@codesourcery.com>
1009
1010 * config/tc-arm.c (limits.h): Include.
1011 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
1012 (fpu_vfp_v3_or_neon_ext): Declare constants.
1013 (neon_el_type): New enumeration of types for Neon vector elements.
1014 (neon_type_el): New struct. Define type and size of a vector element.
1015 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
1016 instruction.
1017 (neon_type): Define struct. The type of an instruction.
1018 (arm_it): Add 'vectype' for the current instruction.
1019 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
1020 (vfp_sp_reg_pos): Rename to...
1021 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
1022 tags.
1023 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
1024 (Neon D or Q register).
1025 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
1026 register.
1027 (GE_OPT_PREFIX_BIG): Define constant, for use in...
1028 (my_get_expression): Allow above constant as argument to accept
1029 64-bit constants with optional prefix.
1030 (arm_reg_parse): Add extra argument to return the specific type of
1031 register in when either a D or Q register (REG_TYPE_NDQ) is
1032 requested. Can be NULL.
1033 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
1034 (parse_reg_list): Update for new arm_reg_parse args.
1035 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
1036 (parse_neon_el_struct_list): New function. Parse element/structure
1037 register lists for VLD<n>/VST<n> instructions.
1038 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
1039 (s_arm_unwind_save_mmxwr): Likewise.
1040 (s_arm_unwind_save_mmxwcg): Likewise.
1041 (s_arm_unwind_movsp): Likewise.
1042 (s_arm_unwind_setfp): Likewise.
1043 (parse_big_immediate): New function. Parse an immediate, which may be
1044 64 bits wide. Put results in inst.operands[i].
1045 (parse_shift): Update for new arm_reg_parse args.
1046 (parse_address): Likewise. Add parsing of alignment specifiers.
1047 (parse_neon_mov): Parse the operands of a VMOV instruction.
1048 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
1049 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
1050 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
1051 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
1052 (parse_operands): Handle new codes above.
1053 (encode_arm_vfp_sp_reg): Rename to...
1054 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
1055 selected VFP version only supports D0-D15.
1056 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
1057 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
1058 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
1059 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
1060 encode_arm_vfp_reg name, and allow 32 D regs.
1061 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
1062 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
1063 regs.
1064 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
1065 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
1066 constant-load and conversion insns introduced with VFPv3.
1067 (neon_tab_entry): New struct.
1068 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
1069 those which are the targets of pseudo-instructions.
1070 (neon_opc): Enumerate opcodes, use as indices into...
1071 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
1072 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
1073 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
1074 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
1075 neon_enc_tab.
1076 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
1077 Neon instructions.
1078 (neon_type_mask): New. Compact type representation for type checking.
1079 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
1080 permitted type combinations.
1081 (N_IGNORE_TYPE): New macro.
1082 (neon_check_shape): New function. Check an instruction shape for
1083 multiple alternatives. Return the specific shape for the current
1084 instruction.
1085 (neon_modify_type_size): New function. Modify a vector type and size,
1086 depending on the bit mask in argument 1.
1087 (neon_type_promote): New function. Convert a given "key" type (of an
1088 operand) into the correct type for a different operand, based on a bit
1089 mask.
1090 (type_chk_of_el_type): New function. Convert a type and size into the
1091 compact representation used for type checking.
1092 (el_type_of_type_ckh): New function. Reverse of above (only when a
1093 single bit is set in the bit mask).
1094 (modify_types_allowed): New function. Alter a mask of allowed types
1095 based on a bit mask of modifications.
1096 (neon_check_type): New function. Check the type of the current
1097 instruction against the variable argument list. The "key" type of the
1098 instruction is returned.
1099 (neon_dp_fixup): New function. Fill in and modify instruction bits for
1100 a Neon data-processing instruction depending on whether we're in ARM
1101 mode or Thumb-2 mode.
1102 (neon_logbits): New function.
1103 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
1104 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
1105 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
1106 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
1107 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
1108 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
1109 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
1110 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
1111 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
1112 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
1113 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
1114 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
1115 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
1116 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
1117 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
1118 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
1119 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
1120 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
1121 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
1122 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
1123 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
1124 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
1125 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
1126 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
1127 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
1128 helpers.
1129 (parse_neon_type): New function. Parse Neon type specifier.
1130 (opcode_lookup): Allow parsing of Neon type specifiers.
1131 (REGNUM2, REGSETH, REGSET2): New macros.
1132 (reg_names): Add new VFPv3 and Neon registers.
1133 (NUF, nUF, NCE, nCE): New macros for opcode table.
1134 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
1135 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
1136 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
1137 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
1138 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
1139 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
1140 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
1141 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
1142 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
1143 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
1144 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
1145 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
1146 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
1147 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
1148 fto[us][lh][sd].
1149 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
1150 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
1151 (arm_option_cpu_value): Add vfp3 and neon.
1152 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
1153 VFPv1 attribute.
1154
1946c96e
BW		 11552006-04-25 Bob Wilson <bob.wilson@acm.org>
1156
1157 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
1158 syntax instead of hardcoded opcodes with ".w18" suffixes.
1159 (wide_branch_opcode): New.
1160 (build_transition): Use it to check for wide branch opcodes with
1161 either ".w18" or ".w15" suffixes.
1162
5033a645
BW		 11632006-04-25 Bob Wilson <bob.wilson@acm.org>
1164
1165 * config/tc-xtensa.c (xtensa_create_literal_symbol,
1166 xg_assemble_literal, xg_assemble_literal_space): Do not set the
1167 frag's is_literal flag.
1168
395fa56f
BW		 11692006-04-25 Bob Wilson <bob.wilson@acm.org>
1170
1171 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
1172
708587a4
KH		 11732006-04-23 Kazu Hirata <kazu@codesourcery.com>
1174
1175 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
1176 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
1177 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
1178 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
1179 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
1180
8463be01
PB		 11812005-04-20 Paul Brook <paul@codesourcery.com>
1182
1183 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
1184 all targets.
1185 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
1186
f26a5955
AM		 11872006-04-19 Alan Modra <amodra@bigpond.net.au>
1188
1189 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
1190 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
1191 Make some cpus unsupported on ELF. Run "make dep-am".
1192 * Makefile.in: Regenerate.
1193
241a6c40
AM		 11942006-04-19 Alan Modra <amodra@bigpond.net.au>
1195
1196 * configure.in (--enable-targets): Indent help message.
1197 * configure: Regenerate.
1198
bb8f5920
L		 11992006-04-18 H.J. Lu <hongjiu.lu@intel.com>
1200
1201 PR gas/2533
1202 * config/tc-i386.c (i386_immediate): Check illegal immediate
1203 register operand.
1204
23d9d9de
AM		 12052006-04-18 Alan Modra <amodra@bigpond.net.au>
1206
64e74474
AM		 1207 * config/tc-i386.c: Formatting.
1208 (output_disp, output_imm): ISO C90 params.
1209
6cbe03fb
AM		 1210 * frags.c (frag_offset_fixed_p): Constify args.
1211 * frags.h (frag_offset_fixed_p): Ditto.
1212
23d9d9de
AM		 1213 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
1214 (COFF_MAGIC): Delete.
a37d486e
AM		 1215
1216 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
1217
e7403566
DJ		 12182006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
1219
1220 * po/POTFILES.in: Regenerated.
1221
58ab4f3d
MM		 12222006-04-16 Mark Mitchell <mark@codesourcery.com>
1223
1224 * doc/as.texinfo: Mention that some .type syntaxes are not
1225 supported on all architectures.
1226
482fd9f9
BW		 12272006-04-14 Sterling Augustine <sterling@tensilica.com>
1228
1229 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
1230 instructions when such transformations have been disabled.
1231
05d58145
BW		 12322006-04-10 Sterling Augustine <sterling@tensilica.com>
1233
1234 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
1235 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
1236 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
1237 decoding the loop instructions. Remove current_offset variable.
1238 (xtensa_fix_short_loop_frags): Likewise.
1239 (min_bytes_to_other_loop_end): Remove current_offset argument.
1240
9e75b3fa
AM		 12412006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
1242
a37d486e 1243 * config/tc-z80.c (z80_optimize_expr): Removed.
9e75b3fa
AM		 1244 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
1245
d727e8c2
NC		 12462006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1247
1248 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
1249 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
1250 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
1251 atmega644, atmega329, atmega3290, atmega649, atmega6490,
1252 atmega406, atmega640, atmega1280, atmega1281, at90can32,
1253 at90can64, at90usb646, at90usb647, at90usb1286 and
1254 at90usb1287.
1255 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
1256
d252fdde
PB		 12572006-04-07 Paul Brook <paul@codesourcery.com>
1258
1259 * config/tc-arm.c (parse_operands): Set default error message.
1260
ab1eb5fe
PB		 12612006-04-07 Paul Brook <paul@codesourcery.com>
1262
1263 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
1264
7ae2971b
PB		 12652006-04-07 Paul Brook <paul@codesourcery.com>
1266
1267 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
1268
53365c0d
PB		 12692006-04-07 Paul Brook <paul@codesourcery.com>
1270
1271 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
1272 (move_or_literal_pool): Handle Thumb-2 instructions.
1273 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
1274
45aa61fe
AM		 12752006-04-07 Alan Modra <amodra@bigpond.net.au>
1276
1277 PR 2512.
1278 * config/tc-i386.c (match_template): Move 64-bit operand tests
1279 inside loop.
1280
108a6f8e
CD		 12812006-04-06 Carlos O'Donell <carlos@codesourcery.com>
1282
1283 * po/Make-in: Add install-html target.
1284 * Makefile.am: Add install-html and install-html-recursive targets.
1285 * Makefile.in: Regenerate.
1286 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
1287 * configure: Regenerate.
1288 * doc/Makefile.am: Add install-html and install-html-am targets.
1289 * doc/Makefile.in: Regenerate.
1290
ec651a3b
AM		 12912006-04-06 Alan Modra <amodra@bigpond.net.au>
1292
1293 * frags.c (frag_offset_fixed_p): Reinitialise offset before
1294 second scan.
1295
910600e9
RS		 12962006-04-05 Richard Sandiford <richard@codesourcery.com>
1297 Daniel Jacobowitz <dan@codesourcery.com>
1298
1299 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
1300 (GOTT_BASE, GOTT_INDEX): New.
1301 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
1302 GOTT_INDEX when generating VxWorks PIC.
1303 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
1304 use the generic *-*-vxworks* stanza instead.
1305
99630778
AM		 13062006-04-04 Alan Modra <amodra@bigpond.net.au>
1307
1308 PR 997
1309 * frags.c (frag_offset_fixed_p): New function.
1310 * frags.h (frag_offset_fixed_p): Declare.
1311 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
1312 (resolve_expression): Likewise.
1313
a02728c8
BW		 13142006-04-03 Sterling Augustine <sterling@tensilica.com>
1315
1316 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
1317 of the same length but different numbers of slots.
1318
9dfde49d
AS		 13192006-03-30 Andreas Schwab <schwab@suse.de>
1320
1321 * configure.in: Fix help string for --enable-targets option.
1322 * configure: Regenerate.
1323
2da12c60
NS		 13242006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1325
6d89cc8f
NS		 1326 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
1327 (m68k_ip): ... here. Use for all chips. Protect against buffer
1328 overrun and avoid excessive copying.
1329
2da12c60
NS		 1330 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
1331 m68020_control_regs, m68040_control_regs, m68060_control_regs,
1332 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
1333 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
1334 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
1335 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
1336 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
1337 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
1338 mcf5282_ctrl, mcfv4e_ctrl): ... these.
1339 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
1340 (struct m68k_cpu): Change chip field to control_regs.
1341 (current_chip): Remove.
1342 (control_regs): New.
1343 (m68k_archs, m68k_extensions): Adjust.
1344 (m68k_cpus): Reorder to be in cpu number order. Adjust.
1345 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
1346 (find_cf_chip): Reimplement for new organization of cpu table.
1347 (select_control_regs): Remove.
1348 (mri_chip): Adjust.
1349 (struct save_opts): Save control regs, not chip.
1350 (s_save, s_restore): Adjust.
1351 (m68k_lookup_cpu): Give deprecated warning when necessary.
1352 (m68k_init_arch): Adjust.
1353 (md_show_usage): Adjust for new cpu table organization.
1354
1ac4baed
BS		 13552006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
1356
1357 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
1358 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
1359 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
1360 "elf/bfin.h".
1361 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
1362 (any_gotrel): New rule.
1363 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
1364 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
1365 "elf/bfin.h".
1366 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
1367 (bfin_pic_ptr): New function.
1368 (md_pseudo_table): Add it for ".picptr".
1369 (OPTION_FDPIC): New macro.
1370 (md_longopts): Add -mfdpic.
1371 (md_parse_option): Handle it.
1372 (md_begin): Set BFD flags.
1373 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
1374 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
1375 us for GOT relocs.
1376 * Makefile.am (bfin-parse.o): Update dependencies.
1377 (DEPTC_bfin_elf): Likewise.
1378 * Makefile.in: Regenerate.
1379
a9d34880
RS		 13802006-03-25 Richard Sandiford <richard@codesourcery.com>
1381
1382 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
1383 mcfemac instead of mcfmac.
1384
9ca26584
AJ		 13852006-03-23 Michael Matz <matz@suse.de>
1386
1387 * config/tc-i386.c (type_names): Correct placement of 'static'.
1388 (reloc): Map some more relocs to their 64 bit counterpart when
1389 size is 8.
1390 (output_insn): Work around breakage if DEBUG386 is defined.
1391 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
1392 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
1393 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
1394 different from i386.
1395 (output_imm): Ditto.
1396 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
1397 Imm64.
1398 (md_convert_frag): Jumps can now be larger than 2GB away, error
1399 out in that case.
1400 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
1401 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
1402
0a44bf69
RS		 14032006-03-22 Richard Sandiford <richard@codesourcery.com>
1404 Daniel Jacobowitz <dan@codesourcery.com>
1405 Phil Edwards <phil@codesourcery.com>
1406 Zack Weinberg <zack@codesourcery.com>
1407 Mark Mitchell <mark@codesourcery.com>
1408 Nathan Sidwell <nathan@codesourcery.com>
1409
1410 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
1411 (md_begin): Complain about -G being used for PIC. Don't change
1412 the text, data and bss alignments on VxWorks.
1413 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
1414 generating VxWorks PIC.
1415 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
1416 (macro): Likewise, but do not treat la $25 specially for
1417 VxWorks PIC, and do not handle jal.
1418 (OPTION_MVXWORKS_PIC): New macro.
1419 (md_longopts): Add -mvxworks-pic.
1420 (md_parse_option): Don't complain about using PIC and -G together here.
1421 Handle OPTION_MVXWORKS_PIC.
1422 (md_estimate_size_before_relax): Always use the first relaxation
1423 sequence on VxWorks.
1424 * config/tc-mips.h (VXWORKS_PIC): New.
1425
080eb7fe
PB		 14262006-03-21 Paul Brook <paul@codesourcery.com>
1427
1428 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
1429
03aaa593
BW		 14302006-03-21 Sterling Augustine <sterling@tensilica.com>
1431
1432 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
1433 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
1434 (get_loop_align_size): New.
1435 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
1436 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
1437 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
1438 (get_noop_aligned_address): Use get_loop_align_size.
1439 (get_aligned_diff): Likewise.
1440
3e94bf1a
PB		 14412006-03-21 Paul Brook <paul@codesourcery.com>
1442
1443 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
1444
dfa9f0d5
PB		 14452006-03-20 Paul Brook <paul@codesourcery.com>
1446
1447 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
1448 (do_t_branch): Encode branches inside IT blocks as unconditional.
1449 (do_t_cps): New function.
1450 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
1451 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
1452 (opcode_lookup): Allow conditional suffixes on all instructions in
1453 Thumb mode.
1454 (md_assemble): Advance condexec state before checking for errors.
1455 (insns): Use do_t_cps.
1456
6e1cb1a6
PB		 14572006-03-20 Paul Brook <paul@codesourcery.com>
1458
1459 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
1460 outputting the insn.
1461
0a966e2d
JBG		 14622006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1463
1464 * config/tc-vax.c: Update copyright year.
1465 * config/tc-vax.h: Likewise.
1466
a49fcc17
JBG		 14672006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1468
1469 * config/tc-vax.c (md_chars_to_number): Used only locally, so
1470 make it static.
1471 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
1472
f5208ef2
PB		 14732006-03-17 Paul Brook <paul@codesourcery.com>
1474
1475 * config/tc-arm.c (insns): Add ldm and stm.
1476
cb4c78d6
BE		 14772006-03-17 Ben Elliston <bje@au.ibm.com>
1478
1479 PR gas/2446
1480 * doc/as.texinfo (Ident): Document this directive more thoroughly.
1481
c16d2bf0
PB		 14822006-03-16 Paul Brook <paul@codesourcery.com>
1483
1484 * config/tc-arm.c (insns): Add "svc".
1485
80ca4e2c
BW		 14862006-03-13 Bob Wilson <bob.wilson@acm.org>
1487
1488 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
1489 flag and avoid double underscore prefixes.
1490
3a4a14e9
PB		 14912006-03-10 Paul Brook <paul@codesourcery.com>
1492
1493 * config/tc-arm.c (md_begin): Handle EABIv5.
1494 (arm_eabis): Add EF_ARM_EABI_VER5.
1495 * doc/c-arm.texi: Document -meabi=5.
1496
518051dc
BE		 14972006-03-10 Ben Elliston <bje@au.ibm.com>
1498
1499 * app.c (do_scrub_chars): Simplify string handling.
1500
00a97672
RS		 15012006-03-07 Richard Sandiford <richard@codesourcery.com>
1502 Daniel Jacobowitz <dan@codesourcery.com>
1503 Zack Weinberg <zack@codesourcery.com>
1504 Nathan Sidwell <nathan@codesourcery.com>
1505 Paul Brook <paul@codesourcery.com>
1506 Ricardo Anguiano <anguiano@codesourcery.com>
1507 Phil Edwards <phil@codesourcery.com>
1508
1509 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
1510 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
1511 R_ARM_ABS12 reloc.
1512 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
1513 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
1514 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
1515
b29757dc
BW		 15162006-03-06 Bob Wilson <bob.wilson@acm.org>
1517
1518 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
1519 even when using the text-section-literals option.
1520
0b2e31dc
NS		 15212006-03-06 Nathan Sidwell <nathan@codesourcery.com>
1522
1523 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
1524 and cf.
1525 (m68k_ip): <case 'J'> Check we have some control regs.
1526 (md_parse_option): Allow raw arch switch.
1527 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
1528 whether 68881 or cfloat was meant by -mfloat.
1529 (md_show_usage): Adjust extension display.
1530 (m68k_elf_final_processing): Adjust.
1531
df406460
NC		 15322006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
1533
1534 * config/tc-avr.c (avr_mod_hash_value): New function.
1535 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
1536 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
1537 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
1538 instead of int avr_ldi_expression: use avr_mod_hash_value instead
1539 of (int).
1540 (tc_gen_reloc): Handle substractions of symbols, if possible do
1541 fixups, abort otherwise.
1542 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
1543 tc_fix_adjustable): Define.
1544
53022e4a
JW		 15452006-03-02 James E Wilson <wilson@specifix.com>
1546
1547 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
1548 change the template, then clear md.slot[curr].end_of_insn_group.
1549
9f6f925e
JB		 15502006-02-28 Jan Beulich <jbeulich@novell.com>
1551
1552 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
1553
0e31b3e1
JB		 15542006-02-28 Jan Beulich <jbeulich@novell.com>
1555
1556 PR/1070
1557 * macro.c (getstring): Don't treat parentheses special anymore.
1558 (get_any_string): Don't consider '(' and ')' as quoting anymore.
1559 Special-case '(', ')', '[', and ']' when dealing with non-quoting
1560 characters.
1561
10cd14b4
AM		 15622006-02-28 Mat <mat@csail.mit.edu>
1563
1564 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
1565
63752a75
JJ		 15662006-02-27 Jakub Jelinek <jakub@redhat.com>
1567
1568 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
1569 field.
1570 (CFI_signal_frame): Define.
1571 (cfi_pseudo_table): Add .cfi_signal_frame.
1572 (dot_cfi): Handle CFI_signal_frame.
1573 (output_cie): Handle cie->signal_frame.
1574 (select_cie_for_fde): Don't share CIE if signal_frame flag is
1575 different. Copy signal_frame from FDE to newly created CIE.
1576 * doc/as.texinfo: Document .cfi_signal_frame.
1577
f7d9e5c3
CD		 15782006-02-27 Carlos O'Donell <carlos@codesourcery.com>
1579
1580 * doc/Makefile.am: Add html target.
1581 * doc/Makefile.in: Regenerate.
1582 * po/Make-in: Add html target.
1583
331d2d0d
L		 15842006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1585
8502d882 1586 * config/tc-i386.c (output_insn): Support Intel Merom New
331d2d0d
L		 1587 Instructions.
1588
8502d882 1589 * config/tc-i386.h (CpuMNI): New.
331d2d0d
L		 1590 (CpuUnknownFlags): Add CpuMNI.
1591
10156f83
DM		 15922006-02-24 David S. Miller <davem@sunset.davemloft.net>
1593
1594 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
1595 (hpriv_reg_table): New table for hyperprivileged registers.
1596 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
1597 register encoding.
1598
6772dd07
DD		 15992006-02-24 DJ Delorie <dj@redhat.com>
1600
1601 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
1602 (tc_gen_reloc): Don't define.
1603 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
1604 (OPTION_LINKRELAX): New.
1605 (md_longopts): Add it.
1606 (m32c_relax): New.
1607 (md_parse_options): Set it.
1608 (md_assemble): Emit relaxation relocs as needed.
1609 (md_convert_frag): Emit relaxation relocs as needed.
1610 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
1611 (m32c_apply_fix): New.
1612 (tc_gen_reloc): New.
1613 (m32c_force_relocation): Force out jump relocs when relaxing.
1614 (m32c_fix_adjustable): Return false if relaxing.
1615
62b3e311
PB		 16162006-02-24 Paul Brook <paul@codesourcery.com>
1617
1618 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
1619 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
1620 (struct asm_barrier_opt): Define.
1621 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
1622 (parse_psr): Accept V7M psr names.
1623 (parse_barrier): New function.
1624 (enum operand_parse_code): Add OP_oBARRIER.
1625 (parse_operands): Implement OP_oBARRIER.
1626 (do_barrier): New function.
1627 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
1628 (do_t_cpsi): Add V7M restrictions.
1629 (do_t_mrs, do_t_msr): Validate V7M variants.
1630 (md_assemble): Check for NULL variants.
1631 (v7m_psrs, barrier_opt_names): New tables.
1632 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
1633 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
1634 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
1635 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
1636 (struct cpu_arch_ver_table): Define.
1637 (cpu_arch_ver): New.
1638 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
1639 Tag_CPU_arch_profile.
1640 * doc/c-arm.texi: Document new cpu and arch options.
1641
59cf82fe
L		 16422006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1643
1644 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
1645
19a7219f
L		 16462006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1647
1648 * config/tc-ia64.c: Update copyright years.
1649
7f3dfb9c
L		 16502006-02-22 H.J. Lu <hongjiu.lu@intel.com>
1651
1652 * config/tc-ia64.c (specify_resource): Add the rule 17 from
1653 SDM 2.2.
1654
f40d1643
PB		 16552005-02-22 Paul Brook <paul@codesourcery.com>
1656
1657 * config/tc-arm.c (do_pld): Remove incorrect write to
1658 inst.instruction.
1659 (encode_thumb32_addr_mode): Use correct operand.
1660
216d22bc
PB		 16612006-02-21 Paul Brook <paul@codesourcery.com>
1662
1663 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
1664
d70c5fc7
NC		 16652006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
1666 Anil Paranjape <anilp1@kpitcummins.com>
1667 Shilin Shakti <shilins@kpitcummins.com>
1668
1669 * Makefile.am: Add xc16x related entry.
1670 * Makefile.in: Regenerate.
1671 * configure.in: Added xc16x related entry.
1672 * configure: Regenerate.
1673 * config/tc-xc16x.h: New file
1674 * config/tc-xc16x.c: New file
1675 * doc/c-xc16x.texi: New file for xc16x
1676 * doc/all.texi: Entry for xc16x
1677 * doc/Makefile.texi: Added c-xc16x.texi
1678 * NEWS: Announce the support for the new target.
1679
aaa2ab3d
NH		 16802006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
1681
1682 * configure.tgt: set emulation for mips-*-netbsd*
1683
82de001f
JJ		 16842006-02-14 Jakub Jelinek <jakub@redhat.com>
1685
1686 * config.in: Rebuilt.
1687
431ad2d0
BW		 16882006-02-13 Bob Wilson <bob.wilson@acm.org>
1689
1690 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
1691 from 1, not 0, in error messages.
1692 (md_assemble): Simplify special-case check for ENTRY instructions.
1693 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
1694 operand in error message.
1695
94089a50
JM		 16962006-02-13 Joseph S. Myers <joseph@codesourcery.com>
1697
1698 * configure.tgt (arm-*-linux-gnueabi*): Change to
1699 arm-*-linux-*eabi*.
1700
52de4c06
NC		 17012006-02-10 Nick Clifton <nickc@redhat.com>
1702
70e45ad9
NC		 1703 * config/tc-crx.c (check_range): Ensure that the sign bit of a
1704 32-bit value is propagated into the upper bits of a 64-bit long.
1705
52de4c06
NC		 1706 * config/tc-arc.c (init_opcode_tables): Fix cast.
1707 (arc_extoper, md_operand): Likewise.
1708
21af2bbd
BW		 17092006-02-09 David Heine <dlheine@tensilica.com>
1710
1711 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
1712 each relaxation step.
1713
75a706fc
L		 17142006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
1715
1716 * configure.in (CHECK_DECLS): Add vsnprintf.
1717 * configure: Regenerate.
1718 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
1719 include/declare here, but...
1720 * as.h: Move code detecting VARARGS idiom to the top.
1721 (errno.h, stdarg.h, varargs.h, va_list): ...here.
1722 (vsnprintf): Declare if not already declared.
1723
0d474464
L		 17242006-02-08 H.J. Lu <hongjiu.lu@intel.com>
1725
1726 * as.c (close_output_file): New.
1727 (main): Register close_output_file with xatexit before
1728 dump_statistics. Don't call output_file_close.
1729
266abb8f
NS		 17302006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1731
1732 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
1733 mcf5329_control_regs): New.
1734 (not_current_architecture, selected_arch, selected_cpu): New.
1735 (m68k_archs, m68k_extensions): New.
1736 (archs): Renamed to ...
1737 (m68k_cpus): ... here. Adjust.
1738 (n_arches): Remove.
1739 (md_pseudo_table): Add arch and cpu directives.
1740 (find_cf_chip, m68k_ip): Adjust table scanning.
1741 (no_68851, no_68881): Remove.
1742 (md_assemble): Lazily initialize.
1743 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
1744 (md_init_after_args): Move functionality to m68k_init_arch.
1745 (mri_chip): Adjust table scanning.
1746 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
1747 options with saner parsing.
1748 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
1749 m68k_init_arch): New.
1750 (s_m68k_cpu, s_m68k_arch): New.
1751 (md_show_usage): Adjust.
1752 (m68k_elf_final_processing): Set CF EF flags.
1753 * config/tc-m68k.h (m68k_init_after_args): Remove.
1754 (tc_init_after_args): Remove.
1755 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
1756 (M68k-Directives): Document .arch and .cpu directives.
1757
134dcee5
AM		 17582006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
1759
1760 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
1761 synonyms for equ and defl.
1762 (z80_cons_fix_new): New function.
1763 (emit_byte): Disallow relative jumps to absolute locations.
1764 (emit_data): Only handle defb, prototype changed, because defb is
1765 now handled as pseudo-op rather than an instruction.
1766 (instab): Entries for defb,defw,db,dw moved from here...
1767 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
1768 Add entries for def24,def32,d24,d32.
1769 (md_assemble): Improved error handling.
1770 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
1771 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
1772 (z80_cons_fix_new): Declare.
1773 * doc/c-z80.texi (defb, db): Mention warning on overflow.
1774 (def24,d24,def32,d32): New pseudo-ops.
1775
a9931606
PB		 17762006-02-02 Paul Brook <paul@codesourcery.com>
1777
1778 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1779
ef8d22e6
PB		 17802005-02-02 Paul Brook <paul@codesourcery.com>
1781
1782 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1783 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1784 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1785 T2_OPCODE_RSB): Define.
1786 (thumb32_negate_data_op): New function.
1787 (md_apply_fix): Use it.
1788
e7da6241
BW		 17892006-01-31 Bob Wilson <bob.wilson@acm.org>
1790
1791 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1792 fields.
1793 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1794 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1795 subtracted symbols.
1796 (relaxation_requirements): Add pfinish_frag argument and use it to
1797 replace setting tinsn->record_fix fields.
1798 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1799 and vinsn_to_insnbuf. Remove references to record_fix and
1800 slot_sub_symbols fields.
1801 (xtensa_mark_narrow_branches): Delete unused code.
1802 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1803 a symbol.
1804 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1805 record_fix fields.
1806 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1807 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1808 of the record_fix field. Simplify error messages for unexpected
1809 symbolic operands.
1810 (set_expr_symbol_offset_diff): Delete.
1811
79134647
PB		 18122006-01-31 Paul Brook <paul@codesourcery.com>
1813
1814 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1815
e74cfd16
PB		 18162006-01-31 Paul Brook <paul@codesourcery.com>
1817 Richard Earnshaw <rearnsha@arm.com>
1818
1819 * config/tc-arm.c: Use arm_feature_set.
1820 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1821 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1822 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1823 New variables.
1824 (insns): Use them.
1825 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1826 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1827 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1828 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1829 feature flags.
1830 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1831 (arm_opts): Move old cpu/arch options from here...
1832 (arm_legacy_opts): ... to here.
1833 (md_parse_option): Search arm_legacy_opts.
1834 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1835 (arm_float_abis, arm_eabis): Make const.
1836
d47d412e
BW		 18372006-01-25 Bob Wilson <bob.wilson@acm.org>
1838
1839 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1840
b14273fe
JZ		 18412006-01-21 Jie Zhang <jie.zhang@analog.com>
1842
1843 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1844 in load immediate intruction.
1845
39cd1c76
JZ		 18462006-01-21 Jie Zhang <jie.zhang@analog.com>
1847
1848 * config/bfin-parse.y (value_match): Use correct conversion
1849 specifications in template string for __FILE__ and __LINE__.
1850 (binary): Ditto.
1851 (unary): Ditto.
1852
67a4f2b7
AO		 18532006-01-18 Alexandre Oliva <aoliva@redhat.com>
1854
1855 Introduce TLS descriptors for i386 and x86_64.
1856 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1857 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1858 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1859 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1860 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1861 displacement bits.
1862 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1863 (lex_got): Handle @tlsdesc and @tlscall.
1864 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1865
8ad7c533
NC		 18662006-01-11 Nick Clifton <nickc@redhat.com>
1867
1868 Fixes for building on 64-bit hosts:
1869 * config/tc-avr.c (mod_index): New union to allow conversion
1870 between pointers and integers.
1871 (md_begin, avr_ldi_expression): Use it.
1872 * config/tc-i370.c (md_assemble): Add cast for argument to print
1873 statement.
1874 * config/tc-tic54x.c (subsym_substitute): Likewise.
1875 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1876 opindex field of fr_cgen structure into a pointer so that it can
1877 be stored in a frag.
1878 * config/tc-mn10300.c (md_assemble): Likewise.
1879 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1880 types.
1881 * config/tc-v850.c: Replace uses of (int) casts with correct
1882 types.
1883
4dcb3903
L		 18842006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1885
1886 PR gas/2117
1887 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1888
e0f6ea40
HPN		 18892006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1890
1891 PR gas/2101
1892 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1893 a local-label reference.
1894
e88d958a 1895For older changes see ChangeLog-2005
08d56133
NC		 1896\f
1897Local Variables:
1898mode: change-log
1899left-margin: 8
1900fill-column: 74
1901version-control: never
1902End:
GDB Binutils - Deliverables
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