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6648b7cf
JM		 12006-06-07 Joseph S. Myers <joseph@codesourcery.com>
2
3 * po/Make-in (pdf, ps): New dummy targets.
4
037e8744
JB		 52006-06-07 Julian Brown <julian@codesourcery.com>
6
7 * config/tc-arm.c (stdarg.h): include.
8 (arm_it): Add uncond_value field. Add isvec and issingle to operand
9 array.
10 (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
11 REG_TYPE_NSDQ (single, double or quad vector reg).
12 (reg_expected_msgs): Update.
13 (BAD_FPU): Add macro for unsupported FPU instruction error.
14 (parse_neon_type): Support 'd' as an alias for .f64.
15 (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
16 sets of registers.
17 (parse_vfp_reg_list): Don't update first arg on error.
18 (parse_neon_mov): Support extra syntax for VFP moves.
19 (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
20 OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
21 (parse_operands): Support isvec, issingle operands fields, new parse
22 codes above.
23 (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
24 msr variants.
25 (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
26 (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
27 (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
28 (NEON_SHAPE_DEF): New macro. Define table of possible instruction
29 shapes.
30 (neon_shape): Redefine in terms of above.
31 (neon_shape_class): New enumeration, table of shape classes.
32 (neon_shape_el): New enumeration. One element of a shape.
33 (neon_shape_el_size): Register widths of above, where appropriate.
34 (neon_shape_info): New struct. Info for shape table.
35 (neon_shape_tab): New array.
36 (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
37 (neon_check_shape): Rewrite as...
38 (neon_select_shape): New function to classify instruction shapes,
39 driven by new table neon_shape_tab array.
40 (neon_quad): New function. Return 1 if shape should set Q flag in
41 instructions (or equivalent), 0 otherwise.
42 (type_chk_of_el_type): Support F64.
43 (el_type_of_type_chk): Likewise.
44 (neon_check_type): Add support for VFP type checking (VFP data
45 elements fill their containing registers).
46 (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
47 in thumb mode for VFP instructions.
48 (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
49 and encode the current instruction as if it were that opcode.
50 (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
51 arguments, call function in PFN.
52 (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
53 (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
54 (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
55 (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
56 (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
57 Redirect Neon-syntax VFP instructions to VFP instruction handlers.
58 (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
59 (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
60 (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
61 (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
62 (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
63 (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
64 (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
65 (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
66 (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
67 neon_quad.
68 (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
69 between VFP and Neon turns out to belong to Neon. Perform
70 architecture check and fill in condition field if appropriate.
71 (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
72 (do_neon_cvt): Add support for VFP variants of instructions.
73 (neon_cvt_flavour): Extend to cover VFP conversions.
74 (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
75 vmov variants.
76 (do_neon_ldr_str): Handle single-precision VFP load/store.
77 (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
78 NS_NULL not NS_IGNORE.
79 (opcode_tag): Add OT_csuffixF for operands which either take a
80 conditional suffix, or have 0xF in the condition field.
81 (md_assemble): Add support for OT_csuffixF.
82 (NCE): Replace macro with...
83 (NCE_tag, NCE, NCEF): New macros.
84 (nCE): Replace macro with...
85 (nCE_tag, nCE, nCEF): New macros.
86 (insns): Add support for VFP insns or VFP versions of insns msr,
87 mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
88 vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
89 vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
90 VFP/Neon insns together.
91
ebd1c875
AM		 922006-06-07 Alan Modra <amodra@bigpond.net.au>
93 Ladislav Michl <ladis@linux-mips.org>
94
95 * app.c: Don't include headers already included by as.h.
96 * as.c: Likewise.
97 * atof-generic.c: Likewise.
98 * cgen.c: Likewise.
99 * dwarf2dbg.c: Likewise.
100 * expr.c: Likewise.
101 * input-file.c: Likewise.
102 * input-scrub.c: Likewise.
103 * macro.c: Likewise.
104 * output-file.c: Likewise.
105 * read.c: Likewise.
106 * sb.c: Likewise.
107 * config/bfin-lex.l: Likewise.
108 * config/obj-coff.h: Likewise.
109 * config/obj-elf.h: Likewise.
110 * config/obj-som.h: Likewise.
111 * config/tc-arc.c: Likewise.
112 * config/tc-arm.c: Likewise.
113 * config/tc-avr.c: Likewise.
114 * config/tc-bfin.c: Likewise.
115 * config/tc-cris.c: Likewise.
116 * config/tc-d10v.c: Likewise.
117 * config/tc-d30v.c: Likewise.
118 * config/tc-dlx.h: Likewise.
119 * config/tc-fr30.c: Likewise.
120 * config/tc-frv.c: Likewise.
121 * config/tc-h8300.c: Likewise.
122 * config/tc-hppa.c: Likewise.
123 * config/tc-i370.c: Likewise.
124 * config/tc-i860.c: Likewise.
125 * config/tc-i960.c: Likewise.
126 * config/tc-ip2k.c: Likewise.
127 * config/tc-iq2000.c: Likewise.
128 * config/tc-m32c.c: Likewise.
129 * config/tc-m32r.c: Likewise.
130 * config/tc-maxq.c: Likewise.
131 * config/tc-mcore.c: Likewise.
132 * config/tc-mips.c: Likewise.
133 * config/tc-mmix.c: Likewise.
134 * config/tc-mn10200.c: Likewise.
135 * config/tc-mn10300.c: Likewise.
136 * config/tc-msp430.c: Likewise.
137 * config/tc-mt.c: Likewise.
138 * config/tc-ns32k.c: Likewise.
139 * config/tc-openrisc.c: Likewise.
140 * config/tc-ppc.c: Likewise.
141 * config/tc-s390.c: Likewise.
142 * config/tc-sh.c: Likewise.
143 * config/tc-sh64.c: Likewise.
144 * config/tc-sparc.c: Likewise.
145 * config/tc-tic30.c: Likewise.
146 * config/tc-tic4x.c: Likewise.
147 * config/tc-tic54x.c: Likewise.
148 * config/tc-v850.c: Likewise.
149 * config/tc-vax.c: Likewise.
150 * config/tc-xc16x.c: Likewise.
151 * config/tc-xstormy16.c: Likewise.
152 * config/tc-xtensa.c: Likewise.
153 * config/tc-z80.c: Likewise.
154 * config/tc-z8k.c: Likewise.
155 * macro.h: Don't include sb.h or ansidecl.h.
156 * sb.h: Don't include stdio.h or ansidecl.h.
157 * cond.c: Include sb.h.
158 * itbl-lex.l: Include as.h instead of other system headers.
159 * itbl-parse.y: Likewise.
160 * itbl-ops.c: Similarly.
161 * itbl-ops.h: Don't include as.h or ansidecl.h.
162 * config/bfin-defs.h: Don't include bfd.h or as.h.
163 * config/bfin-parse.y: Include as.h instead of other system headers.
164
9622b051
AM		 1652006-06-06 Ben Elliston <bje@au.ibm.com>
166 Anton Blanchard <anton@samba.org>
167
168 * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
169 (md_show_usage): Document it.
170 (ppc_setup_opcodes): Test power6 opcode flag bits.
171 * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
172
65263ce3
TS		 1732006-06-06 Thiemo Seufer <ths@mips.com>
174 Chao-ying Fu <fu@mips.com>
175
176 * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
177 (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
178 (macro_build): Update comment.
179 (mips_ip): Allow DSP64 instructions for MIPS64R2.
180 (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
181 CPU_HAS_MDMX.
182 (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
183 MIPS_CPU_ASE_MDMX flags for sb1.
184
a9e24354
TS		 1852006-06-05 Thiemo Seufer <ths@mips.com>
186
187 * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
188 appropriate.
189 (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
190 (mips_ip): Make overflowed/underflowed constant arguments in DSP
191 and MT instructions a fatal error. Use INSERT_OPERAND where
192 appropriate. Improve warnings for break and wait code overflows.
193 Use symbolic constant of OP_MASK_COPZ.
194 (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
195
4cfe2c59
DJ		 1962006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
197
198 * po/Make-in (top_builddir): Define.
199
e10fad12
JM		 2002006-06-02 Joseph S. Myers <joseph@codesourcery.com>
201
202 * doc/Makefile.am (TEXI2DVI): Define.
203 * doc/Makefile.in: Regenerate.
204 * doc/c-arc.texi: Fix typo.
205
12e64c2c
AM		 2062006-06-01 Alan Modra <amodra@bigpond.net.au>
207
208 * config/obj-ieee.c: Delete.
209 * config/obj-ieee.h: Delete.
210 * Makefile.am (OBJ_FORMATS): Remove ieee.
211 (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
212 (obj-ieee.o): Remove rule.
213 * Makefile.in: Regenerate.
214 * configure.in (atof): Remove tahoe.
215 (OBJ_MAYBE_IEEE): Don't define.
216 * configure: Regenerate.
217 * config.in: Regenerate.
218 * doc/Makefile.in: Regenerate.
219 * po/POTFILES.in: Regenerate.
220
20e95c23
DJ		 2212006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
222
223 * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
224 and LIBINTL_DEP everywhere.
225 (INTLLIBS): Remove.
226 (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
227 * acinclude.m4: Include new gettext macros.
228 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
229 Remove local code for po/Makefile.
230 * Makefile.in, configure, doc/Makefile.in: Regenerated.
231
eebf07fb
NC		 2322006-05-30 Nick Clifton <nickc@redhat.com>
233
234 * po/es.po: Updated Spanish translation.
235
b6aee19e
DC		 2362006-05-06 Denis Chertykov <denisc@overta.ru>
237
238 * doc/c-avr.texi: New file.
239 * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
240 * doc/all.texi: Set AVR
241 * doc/as.texinfo: Include c-avr.texi
242
f8fdc850
JZ		 2432006-05-28 Jie Zhang <jie.zhang@analog.com>
244
245 * config/bfin-parse.y (check_macfunc): Loose the condition of
246 calling check_multiply_halfregs ().
247
a3205465
JZ		 2482006-05-25 Jie Zhang <jie.zhang@analog.com>
249
250 * config/bfin-parse.y (asm_1): Better check and deal with
251 vector and scalar Multiply 16-Bit Operands instructions.
252
9b52905e
NC		 2532006-05-24 Nick Clifton <nickc@redhat.com>
254
255 * config/tc-hppa.c: Convert to ISO C90 format.
256 * config/tc-hppa.h: Likewise.
257
2582006-05-24 Carlos O'Donell <carlos@systemhalted.org>
259 Randolph Chung <randolph@tausq.org>
260
261 * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
262 is_tls_ieoff, is_tls_leoff): Define.
263 (fix_new_hppa): Handle TLS.
264 (cons_fix_new_hppa): Likewise.
265 (pa_ip): Likewise.
266 (md_apply_fix): Handle TLS relocs.
267 * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
268
28c9d252
NC		 2692006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
270
271 * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
272
ad3fea08
TS		 2732006-05-23 Thiemo Seufer <ths@mips.com>
274 David Ung <davidu@mips.com>
275 Nigel Stephens <nigel@mips.com>
276
277 [ gas/ChangeLog ]
278 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
279 (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
280 ISA_HAS_MXHC1): New macros.
281 (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
282 ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
283 (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
284 (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
285 MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
286 (mips_after_parse_args): Change default handling of float register
287 size to account for 32bit code with 64bit FP. Better sanity checking
288 of ISA/ASE/ABI option combinations.
289 (s_mipsset): Support switching of GPR and FPR sizes via
290 .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
291 options.
292 (mips_elf_final_processing): We should record the use of 64bit FP
293 registers in 32bit code but we don't, because ELF header flags are
294 a scarce ressource.
295 (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
296 extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
297 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
298 (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
299 * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
300 missing -march options. Document .set arch=CPU. Move .set smartmips
301 to ASE page. Use @code for .set FOO examples.
302
8b64503a
JZ		 3032006-05-23 Jie Zhang <jie.zhang@analog.com>
304
305 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
306 if needed.
307
403022e0
JZ		 3082006-05-23 Jie Zhang <jie.zhang@analog.com>
309
310 * config/bfin-defs.h (bfin_equals): Remove declaration.
311 * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
312 * config/tc-bfin.c (bfin_name_is_register): Remove.
313 (bfin_equals): Remove.
314 * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
315 (bfin_name_is_register): Remove declaration.
316
7455baf8
TS		 3172006-05-19 Thiemo Seufer <ths@mips.com>
318 Nigel Stephens <nigel@mips.com>
319
320 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
321 (mips_oddfpreg_ok): New function.
322 (mips_ip): Use it.
323
707bfff6
TS		 3242006-05-19 Thiemo Seufer <ths@mips.com>
325 David Ung <davidu@mips.com>
326
327 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
328 * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
329 ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
330 (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
331 RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
332 RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
333 FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
334 N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
335 SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
336 MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
337 reg_names_o32, reg_names_n32n64): Define register classes.
338 (reg_lookup): New function, use register classes.
339 (md_begin): Reserve register names in the symbol table. Simplify
340 OBJ_ELF defines.
341 (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
342 Use reg_lookup.
343 (mips16_ip): Use reg_lookup.
344 (tc_get_register): Likewise.
345 (tc_mips_regname_to_dw2regnum): New function.
346
1df69f4f
TS		 3472006-05-19 Thiemo Seufer <ths@mips.com>
348
349 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
350 Un-constify string argument.
351 * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
352 Likewise.
353 * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
354 Likewise.
355 * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
356 Likewise.
357 * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
358 Likewise.
359 * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
360 Likewise.
361 * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
362 Likewise.
363
377260ba
NS		 3642006-05-19 Nathan Sidwell <nathan@codesourcery.com>
365
366 * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
367 cfloat/m68881 to correct architecture before using it.
368
cce7653b
NC		 3692006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
370
371 * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
372 constant values.
373
b0796911
PB		 3742006-05-15 Paul Brook <paul@codesourcery.com>
375
376 * config/tc-arm.c (arm_adjust_symtab): Use
377 bfd_is_arm_special_symbol_name.
378
64b607e6
BW		 3792006-05-15 Bob Wilson <bob.wilson@acm.org>
380
381 * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
382 xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
383 xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
384 Handle errors from calls to xtensa_opcode_is_* functions.
385
9b3f89ee
TS		 3862006-05-14 Thiemo Seufer <ths@mips.com>
387
388 * config/tc-mips.c (macro_build): Test for currently active
389 mips16 option.
390 (mips16_ip): Reject invalid opcodes.
391
370b66a1
CD		 3922006-05-11 Carlos O'Donell <carlos@codesourcery.com>
393
394 * doc/as.texinfo: Rename "Index" to "AS Index",
395 and "ABORT" to "ABORT (COFF)".
396
b6895b4f
PB		 3972006-05-11 Paul Brook <paul@codesourcery.com>
398
399 * config/tc-arm.c (parse_half): New function.
400 (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
401 (parse_operands): Ditto.
402 (do_mov16): Reject invalid relocations.
403 (do_t_mov16): Ditto. Use Thumb reloc numbers.
404 (insns): Replace Iffff with HALF.
405 (md_apply_fix): Add MOVW and MOVT relocs.
406 (tc_gen_reloc): Ditto.
407 * doc/c-arm.texi: Document relocation operators
408
e28387c3
PB		 4092006-05-11 Paul Brook <paul@codesourcery.com>
410
411 * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
412
89ee2ebe
TS		 4132006-05-11 Thiemo Seufer <ths@mips.com>
414
415 * config/tc-mips.c (append_insn): Don't check the range of j or
416 jal addresses.
417
53baae48
NC		 4182006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
419
420 * config/tc-arm.c (md_pcrel_from_section): Force a bias for
421 relocs against external symbols for WinCE targets.
422 (md_apply_fix): Likewise.
423
4e2a74a8
TS		 4242006-05-09 David Ung <davidu@mips.com>
425
426 * config/tc-mips.c (append_insn): Only warn about an out-of-range
427 j or jal address.
428
337ff0a5
NC		 4292006-05-09 Nick Clifton <nickc@redhat.com>
430
431 * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
432 against symbols which are not going to be placed into the symbol
433 table.
434
8c9f705e
BE		 4352006-05-09 Ben Elliston <bje@au.ibm.com>
436
437 * expr.c (operand): Remove `if (0 && ..)' statement and
438 subsequently unused target_op label. Collapse `if (1 || ..)'
439 statement.
440 * app.c (do_scrub_chars): Remove unused case 0, as it is handled
441 separately above the switch.
442
2fd0d2ac
NC		 4432006-05-08 Nick Clifton <nickc@redhat.com>
444
445 PR gas/2623
446 * config/tc-msp430.c (line_separator_character): Define as |.
447
e16bfa71
TS		 4482006-05-08 Thiemo Seufer <ths@mips.com>
449 Nigel Stephens <nigel@mips.com>
450 David Ung <davidu@mips.com>
451
452 * config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
453 (mips_opts): Likewise.
454 (file_ase_smartmips): New variable.
455 (ISA_HAS_ROR): SmartMIPS implements rotate instructions.
456 (macro_build): Handle SmartMIPS instructions.
457 (mips_ip): Likewise.
458 (md_longopts): Add argument handling for smartmips.
459 (md_parse_options, mips_after_parse_args): Likewise.
460 (s_mipsset): Add .set smartmips support.
461 (md_show_usage): Document -msmartmips/-mno-smartmips.
462 * doc/as.texinfo: Document -msmartmips/-mno-smartmips and
463 .set smartmips.
464 * doc/c-mips.texi: Likewise.
465
32638454
AM		 4662006-05-08 Alan Modra <amodra@bigpond.net.au>
467
468 * write.c (relax_segment): Add pass count arg. Don't error on
469 negative org/space on first two passes.
470 (relax_seg_info): New struct.
471 (relax_seg, write_object_file): Adjust.
472 * write.h (relax_segment): Update prototype.
473
b7fc2769
JB		 4742006-05-05 Julian Brown <julian@codesourcery.com>
475
476 * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
477 checking.
478 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
479 architecture version checks.
480 (insns): Allow overlapping instructions to be used in VFP mode.
481
7f841127
L		 4822006-05-05 H.J. Lu <hongjiu.lu@intel.com>
483
484 PR gas/2598
485 * config/obj-elf.c (obj_elf_change_section): Allow user
486 specified SHF_ALPHA_GPREL.
487
73160847
NC		 4882006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
489
490 * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
491 for PMEM related expressions.
492
56487c55
NC		 4932006-05-05 Nick Clifton <nickc@redhat.com>
494
495 PR gas/2582
496 * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
497 insertion of a directory separator character into a string at a
498 given offset. Uses heuristics to decide when to use a backslash
499 character rather than a forward-slash character.
500 (dwarf2_directive_loc): Use the macro.
501 (out_debug_info): Likewise.
502
d43b4baf
TS		 5032006-05-05 Thiemo Seufer <ths@mips.com>
504 David Ung <davidu@mips.com>
505
506 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
507 instruction.
508 (macro): Add new case M_CACHE_AB.
509
088fa78e
KH		 5102006-05-04 Kazu Hirata <kazu@codesourcery.com>
511
512 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
513 (opcode_lookup): Issue a warning for opcode with
514 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
515 identical to OT_cinfix3.
516 (TxC3w, TC3w, tC3w): New.
517 (insns): Use tC3w and TC3w for comparison instructions with
518 's' suffix.
519
c9049d30
AM		 5202006-05-04 Alan Modra <amodra@bigpond.net.au>
521
522 * subsegs.h (struct frchain): Delete frch_seg.
523 (frchain_root): Delete.
524 (seg_info): Define as macro.
525 * subsegs.c (frchain_root): Delete.
526 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
527 (subsegs_begin, subseg_change): Adjust for above.
528 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
529 rather than to one big list.
530 (subseg_get): Don't special case abs, und sections.
531 (subseg_new, subseg_force_new): Don't set frchainP here.
532 (seg_info): Delete.
533 (subsegs_print_statistics): Adjust frag chain control list traversal.
534 * debug.c (dmp_frags): Likewise.
535 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
536 at frchain_root. Make use of known frchain ordering.
537 (last_frag_for_seg): Likewise.
538 (get_frag_fix): Likewise. Add seg param.
539 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
540 * write.c (chain_frchains_together_1): Adjust for struct frchain.
541 (SUB_SEGMENT_ALIGN): Likewise.
542 (subsegs_finish): Adjust frchain list traversal.
543 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
544 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
545 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
546 (xtensa_fix_b_j_loop_end_frags): Likewise.
547 (xtensa_fix_close_loop_end_frags): Likewise.
548 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
549 (retrieve_segment_info): Delete frch_seg initialisation.
550
f592407e
AM		 5512006-05-03 Alan Modra <amodra@bigpond.net.au>
552
553 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
554 * config/obj-elf.h (obj_sec_set_private_data): Delete.
555 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
556 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
557
df7849c5
JM		 5582006-05-02 Joseph Myers <joseph@codesourcery.com>
559
560 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
561 here.
562 (md_apply_fix3): Multiply offset by 4 here for
563 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
564
2d545b82
L		 5652006-05-02 H.J. Lu <hongjiu.lu@intel.com>
566 Jan Beulich <jbeulich@novell.com>
567
568 * config/tc-i386.c (output_invalid_buf): Change size for
569 unsigned char.
570 * config/tc-tic30.c (output_invalid_buf): Likewise.
571
572 * config/tc-i386.c (output_invalid): Cast none-ascii char to
573 unsigned char.
574 * config/tc-tic30.c (output_invalid): Likewise.
575
38fc1cb1
DJ		 5762006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
577
578 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
579 (TEXI2POD): Use AM_MAKEINFOFLAGS.
580 (asconfig.texi): Don't set top_srcdir.
581 * doc/as.texinfo: Don't use top_srcdir.
582 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
583
2d545b82
L		 5842006-05-02 H.J. Lu <hongjiu.lu@intel.com>
585
586 * config/tc-i386.c (output_invalid_buf): Change size to 16.
587 * config/tc-tic30.c (output_invalid_buf): Likewise.
588
589 * config/tc-i386.c (output_invalid): Use snprintf instead of
590 sprintf.
591 * config/tc-ia64.c (declare_register_set): Likewise.
592 (emit_one_bundle): Likewise.
593 (check_dependencies): Likewise.
594 * config/tc-tic30.c (output_invalid): Likewise.
595
a8bc6c78
PB		 5962006-05-02 Paul Brook <paul@codesourcery.com>
597
598 * config/tc-arm.c (arm_optimize_expr): New function.
599 * config/tc-arm.h (md_optimize_expr): Define
600 (arm_optimize_expr): Add prototype.
601 (TC_FORCE_RELOCATION_SUB_SAME): Define.
602
58633d9a
BE		 6032006-05-02 Ben Elliston <bje@au.ibm.com>
604
22772e33
BE		 605 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
606 field unsigned.
607
58633d9a
BE		 608 * sb.h (sb_list_vector): Move to sb.c.
609 * sb.c (free_list): Use type of sb_list_vector directly.
610 (sb_build): Fix off-by-one error in assertion about `size'.
611
89cdfe57
BE		 6122006-05-01 Ben Elliston <bje@au.ibm.com>
613
614 * listing.c (listing_listing): Remove useless loop.
615 * macro.c (macro_expand): Remove is_positional local variable.
616 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
617 and simplify surrounding expressions, where possible.
618 (assign_symbol): Likewise.
619 (s_weakref): Likewise.
620 * symbols.c (colon): Likewise.
621
c35da140
AM		 6222006-05-01 James Lemke <jwlemke@wasabisystems.com>
623
624 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
625
9bcd4f99
TS		 6262006-04-30 Thiemo Seufer <ths@mips.com>
627 David Ung <davidu@mips.com>
628
629 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
630 (mips_immed): New table that records various handling of udi
631 instruction patterns.
632 (mips_ip): Adds udi handling.
633
001ae1a4
AM		 6342006-04-28 Alan Modra <amodra@bigpond.net.au>
635
636 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
637 of list rather than beginning.
638
136da414
JB		 6392006-04-26 Julian Brown <julian@codesourcery.com>
640
641 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
642 (is_quarter_float): Rename from above. Simplify slightly.
643 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
644 number.
645 (parse_neon_mov): Parse floating-point constants.
646 (neon_qfloat_bits): Fix encoding.
647 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
648 preference to integer encoding when using the F32 type.
649
dcbf9037
JB		 6502006-04-26 Julian Brown <julian@codesourcery.com>
651
652 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
653 zero-initialising structures containing it will lead to invalid types).
654 (arm_it): Add vectype to each operand.
655 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
656 defined field.
657 (neon_typed_alias): New structure. Extra information for typed
658 register aliases.
659 (reg_entry): Add neon type info field.
660 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
661 Break out alternative syntax for coprocessor registers, etc. into...
662 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
663 out from arm_reg_parse.
664 (parse_neon_type): Move. Return SUCCESS/FAIL.
665 (first_error): New function. Call to ensure first error which occurs is
666 reported.
667 (parse_neon_operand_type): Parse exactly one type.
668 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
669 (parse_typed_reg_or_scalar): New function. Handle core of both
670 arm_typed_reg_parse and parse_scalar.
671 (arm_typed_reg_parse): Parse a register with an optional type.
672 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
673 result.
674 (parse_scalar): Parse a Neon scalar with optional type.
675 (parse_reg_list): Use first_error.
676 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
677 (neon_alias_types_same): New function. Return true if two (alias) types
678 are the same.
679 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
680 of elements.
681 (insert_reg_alias): Return new reg_entry not void.
682 (insert_neon_reg_alias): New function. Insert type/index information as
683 well as register for alias.
684 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
685 make typed register aliases accordingly.
686 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
687 of line.
688 (s_unreq): Delete type information if present.
689 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
690 (s_arm_unwind_save_mmxwcg): Likewise.
691 (s_arm_unwind_movsp): Likewise.
692 (s_arm_unwind_setfp): Likewise.
693 (parse_shift): Likewise.
694 (parse_shifter_operand): Likewise.
695 (parse_address): Likewise.
696 (parse_tb): Likewise.
697 (tc_arm_regname_to_dw2regnum): Likewise.
698 (md_pseudo_table): Add dn, qn.
699 (parse_neon_mov): Handle typed operands.
700 (parse_operands): Likewise.
701 (neon_type_mask): Add N_SIZ.
702 (N_ALLMODS): New macro.
703 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
704 (el_type_of_type_chk): Add some safeguards.
705 (modify_types_allowed): Fix logic bug.
706 (neon_check_type): Handle operands with types.
707 (neon_three_same): Remove redundant optional arg handling.
708 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
709 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
710 (do_neon_step): Adjust accordingly.
711 (neon_cmode_for_logic_imm): Use first_error.
712 (do_neon_bitfield): Call neon_check_type.
713 (neon_dyadic): Rename to...
714 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
715 to allow modification of type of the destination.
716 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
717 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
718 (do_neon_compare): Make destination be an untyped bitfield.
719 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
720 (neon_mul_mac): Return early in case of errors.
721 (neon_move_immediate): Use first_error.
722 (neon_mac_reg_scalar_long): Fix type to include scalar.
723 (do_neon_dup): Likewise.
724 (do_neon_mov): Likewise (in several places).
725 (do_neon_tbl_tbx): Fix type.
726 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
727 (do_neon_ld_dup): Exit early in case of errors and/or use
728 first_error.
729 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
730 Handle .dn/.qn directives.
731 (REGDEF): Add zero for reg_entry neon field.
732
5287ad62
JB		 7332006-04-26 Julian Brown <julian@codesourcery.com>
734
735 * config/tc-arm.c (limits.h): Include.
736 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
737 (fpu_vfp_v3_or_neon_ext): Declare constants.
738 (neon_el_type): New enumeration of types for Neon vector elements.
739 (neon_type_el): New struct. Define type and size of a vector element.
740 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
741 instruction.
742 (neon_type): Define struct. The type of an instruction.
743 (arm_it): Add 'vectype' for the current instruction.
744 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
745 (vfp_sp_reg_pos): Rename to...
746 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
747 tags.
748 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
749 (Neon D or Q register).
750 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
751 register.
752 (GE_OPT_PREFIX_BIG): Define constant, for use in...
753 (my_get_expression): Allow above constant as argument to accept
754 64-bit constants with optional prefix.
755 (arm_reg_parse): Add extra argument to return the specific type of
756 register in when either a D or Q register (REG_TYPE_NDQ) is
757 requested. Can be NULL.
758 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
759 (parse_reg_list): Update for new arm_reg_parse args.
760 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
761 (parse_neon_el_struct_list): New function. Parse element/structure
762 register lists for VLD<n>/VST<n> instructions.
763 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
764 (s_arm_unwind_save_mmxwr): Likewise.
765 (s_arm_unwind_save_mmxwcg): Likewise.
766 (s_arm_unwind_movsp): Likewise.
767 (s_arm_unwind_setfp): Likewise.
768 (parse_big_immediate): New function. Parse an immediate, which may be
769 64 bits wide. Put results in inst.operands[i].
770 (parse_shift): Update for new arm_reg_parse args.
771 (parse_address): Likewise. Add parsing of alignment specifiers.
772 (parse_neon_mov): Parse the operands of a VMOV instruction.
773 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
774 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
775 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
776 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
777 (parse_operands): Handle new codes above.
778 (encode_arm_vfp_sp_reg): Rename to...
779 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
780 selected VFP version only supports D0-D15.
781 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
782 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
783 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
784 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
785 encode_arm_vfp_reg name, and allow 32 D regs.
786 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
787 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
788 regs.
789 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
790 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
791 constant-load and conversion insns introduced with VFPv3.
792 (neon_tab_entry): New struct.
793 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
794 those which are the targets of pseudo-instructions.
795 (neon_opc): Enumerate opcodes, use as indices into...
796 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
797 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
798 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
799 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
800 neon_enc_tab.
801 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
802 Neon instructions.
803 (neon_type_mask): New. Compact type representation for type checking.
804 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
805 permitted type combinations.
806 (N_IGNORE_TYPE): New macro.
807 (neon_check_shape): New function. Check an instruction shape for
808 multiple alternatives. Return the specific shape for the current
809 instruction.
810 (neon_modify_type_size): New function. Modify a vector type and size,
811 depending on the bit mask in argument 1.
812 (neon_type_promote): New function. Convert a given "key" type (of an
813 operand) into the correct type for a different operand, based on a bit
814 mask.
815 (type_chk_of_el_type): New function. Convert a type and size into the
816 compact representation used for type checking.
817 (el_type_of_type_ckh): New function. Reverse of above (only when a
818 single bit is set in the bit mask).
819 (modify_types_allowed): New function. Alter a mask of allowed types
820 based on a bit mask of modifications.
821 (neon_check_type): New function. Check the type of the current
822 instruction against the variable argument list. The "key" type of the
823 instruction is returned.
824 (neon_dp_fixup): New function. Fill in and modify instruction bits for
825 a Neon data-processing instruction depending on whether we're in ARM
826 mode or Thumb-2 mode.
827 (neon_logbits): New function.
828 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
829 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
830 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
831 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
832 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
833 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
834 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
835 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
836 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
837 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
838 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
839 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
840 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
841 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
842 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
843 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
844 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
845 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
846 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
847 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
848 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
849 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
850 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
851 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
852 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
853 helpers.
854 (parse_neon_type): New function. Parse Neon type specifier.
855 (opcode_lookup): Allow parsing of Neon type specifiers.
856 (REGNUM2, REGSETH, REGSET2): New macros.
857 (reg_names): Add new VFPv3 and Neon registers.
858 (NUF, nUF, NCE, nCE): New macros for opcode table.
859 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
860 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
861 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
862 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
863 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
864 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
865 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
866 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
867 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
868 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
869 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
870 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
871 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
872 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
873 fto[us][lh][sd].
874 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
875 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
876 (arm_option_cpu_value): Add vfp3 and neon.
877 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
878 VFPv1 attribute.
879
1946c96e
BW		 8802006-04-25 Bob Wilson <bob.wilson@acm.org>
881
882 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
883 syntax instead of hardcoded opcodes with ".w18" suffixes.
884 (wide_branch_opcode): New.
885 (build_transition): Use it to check for wide branch opcodes with
886 either ".w18" or ".w15" suffixes.
887
5033a645
BW		 8882006-04-25 Bob Wilson <bob.wilson@acm.org>
889
890 * config/tc-xtensa.c (xtensa_create_literal_symbol,
891 xg_assemble_literal, xg_assemble_literal_space): Do not set the
892 frag's is_literal flag.
893
395fa56f
BW		 8942006-04-25 Bob Wilson <bob.wilson@acm.org>
895
896 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
897
708587a4
KH		 8982006-04-23 Kazu Hirata <kazu@codesourcery.com>
899
900 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
901 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
902 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
903 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
904 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
905
8463be01
PB		 9062005-04-20 Paul Brook <paul@codesourcery.com>
907
908 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
909 all targets.
910 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
911
f26a5955
AM		 9122006-04-19 Alan Modra <amodra@bigpond.net.au>
913
914 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
915 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
916 Make some cpus unsupported on ELF. Run "make dep-am".
917 * Makefile.in: Regenerate.
918
241a6c40
AM		 9192006-04-19 Alan Modra <amodra@bigpond.net.au>
920
921 * configure.in (--enable-targets): Indent help message.
922 * configure: Regenerate.
923
bb8f5920
L		 9242006-04-18 H.J. Lu <hongjiu.lu@intel.com>
925
926 PR gas/2533
927 * config/tc-i386.c (i386_immediate): Check illegal immediate
928 register operand.
929
23d9d9de
AM		 9302006-04-18 Alan Modra <amodra@bigpond.net.au>
931
64e74474
AM		 932 * config/tc-i386.c: Formatting.
933 (output_disp, output_imm): ISO C90 params.
934
6cbe03fb
AM		 935 * frags.c (frag_offset_fixed_p): Constify args.
936 * frags.h (frag_offset_fixed_p): Ditto.
937
23d9d9de
AM		 938 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
939 (COFF_MAGIC): Delete.
a37d486e
AM		 940
941 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
942
e7403566
DJ		 9432006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
944
945 * po/POTFILES.in: Regenerated.
946
58ab4f3d
MM		 9472006-04-16 Mark Mitchell <mark@codesourcery.com>
948
949 * doc/as.texinfo: Mention that some .type syntaxes are not
950 supported on all architectures.
951
482fd9f9
BW		 9522006-04-14 Sterling Augustine <sterling@tensilica.com>
953
954 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
955 instructions when such transformations have been disabled.
956
05d58145
BW		 9572006-04-10 Sterling Augustine <sterling@tensilica.com>
958
959 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
960 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
961 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
962 decoding the loop instructions. Remove current_offset variable.
963 (xtensa_fix_short_loop_frags): Likewise.
964 (min_bytes_to_other_loop_end): Remove current_offset argument.
965
9e75b3fa
AM		 9662006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
967
a37d486e 968 * config/tc-z80.c (z80_optimize_expr): Removed.
9e75b3fa
AM		 969 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
970
d727e8c2
NC		 9712006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
972
973 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
974 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
975 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
976 atmega644, atmega329, atmega3290, atmega649, atmega6490,
977 atmega406, atmega640, atmega1280, atmega1281, at90can32,
978 at90can64, at90usb646, at90usb647, at90usb1286 and
979 at90usb1287.
980 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
981
d252fdde
PB		 9822006-04-07 Paul Brook <paul@codesourcery.com>
983
984 * config/tc-arm.c (parse_operands): Set default error message.
985
ab1eb5fe
PB		 9862006-04-07 Paul Brook <paul@codesourcery.com>
987
988 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
989
7ae2971b
PB		 9902006-04-07 Paul Brook <paul@codesourcery.com>
991
992 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
993
53365c0d
PB		 9942006-04-07 Paul Brook <paul@codesourcery.com>
995
996 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
997 (move_or_literal_pool): Handle Thumb-2 instructions.
998 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
999
45aa61fe
AM		 10002006-04-07 Alan Modra <amodra@bigpond.net.au>
1001
1002 PR 2512.
1003 * config/tc-i386.c (match_template): Move 64-bit operand tests
1004 inside loop.
1005
108a6f8e
CD		 10062006-04-06 Carlos O'Donell <carlos@codesourcery.com>
1007
1008 * po/Make-in: Add install-html target.
1009 * Makefile.am: Add install-html and install-html-recursive targets.
1010 * Makefile.in: Regenerate.
1011 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
1012 * configure: Regenerate.
1013 * doc/Makefile.am: Add install-html and install-html-am targets.
1014 * doc/Makefile.in: Regenerate.
1015
ec651a3b
AM		 10162006-04-06 Alan Modra <amodra@bigpond.net.au>
1017
1018 * frags.c (frag_offset_fixed_p): Reinitialise offset before
1019 second scan.
1020
910600e9
RS		 10212006-04-05 Richard Sandiford <richard@codesourcery.com>
1022 Daniel Jacobowitz <dan@codesourcery.com>
1023
1024 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
1025 (GOTT_BASE, GOTT_INDEX): New.
1026 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
1027 GOTT_INDEX when generating VxWorks PIC.
1028 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
1029 use the generic *-*-vxworks* stanza instead.
1030
99630778
AM		 10312006-04-04 Alan Modra <amodra@bigpond.net.au>
1032
1033 PR 997
1034 * frags.c (frag_offset_fixed_p): New function.
1035 * frags.h (frag_offset_fixed_p): Declare.
1036 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
1037 (resolve_expression): Likewise.
1038
a02728c8
BW		 10392006-04-03 Sterling Augustine <sterling@tensilica.com>
1040
1041 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
1042 of the same length but different numbers of slots.
1043
9dfde49d
AS		 10442006-03-30 Andreas Schwab <schwab@suse.de>
1045
1046 * configure.in: Fix help string for --enable-targets option.
1047 * configure: Regenerate.
1048
2da12c60
NS		 10492006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1050
6d89cc8f
NS		 1051 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
1052 (m68k_ip): ... here. Use for all chips. Protect against buffer
1053 overrun and avoid excessive copying.
1054
2da12c60
NS		 1055 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
1056 m68020_control_regs, m68040_control_regs, m68060_control_regs,
1057 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
1058 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
1059 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
1060 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
1061 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
1062 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
1063 mcf5282_ctrl, mcfv4e_ctrl): ... these.
1064 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
1065 (struct m68k_cpu): Change chip field to control_regs.
1066 (current_chip): Remove.
1067 (control_regs): New.
1068 (m68k_archs, m68k_extensions): Adjust.
1069 (m68k_cpus): Reorder to be in cpu number order. Adjust.
1070 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
1071 (find_cf_chip): Reimplement for new organization of cpu table.
1072 (select_control_regs): Remove.
1073 (mri_chip): Adjust.
1074 (struct save_opts): Save control regs, not chip.
1075 (s_save, s_restore): Adjust.
1076 (m68k_lookup_cpu): Give deprecated warning when necessary.
1077 (m68k_init_arch): Adjust.
1078 (md_show_usage): Adjust for new cpu table organization.
1079
1ac4baed
BS		 10802006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
1081
1082 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
1083 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
1084 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
1085 "elf/bfin.h".
1086 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
1087 (any_gotrel): New rule.
1088 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
1089 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
1090 "elf/bfin.h".
1091 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
1092 (bfin_pic_ptr): New function.
1093 (md_pseudo_table): Add it for ".picptr".
1094 (OPTION_FDPIC): New macro.
1095 (md_longopts): Add -mfdpic.
1096 (md_parse_option): Handle it.
1097 (md_begin): Set BFD flags.
1098 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
1099 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
1100 us for GOT relocs.
1101 * Makefile.am (bfin-parse.o): Update dependencies.
1102 (DEPTC_bfin_elf): Likewise.
1103 * Makefile.in: Regenerate.
1104
a9d34880
RS		 11052006-03-25 Richard Sandiford <richard@codesourcery.com>
1106
1107 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
1108 mcfemac instead of mcfmac.
1109
9ca26584
AJ		 11102006-03-23 Michael Matz <matz@suse.de>
1111
1112 * config/tc-i386.c (type_names): Correct placement of 'static'.
1113 (reloc): Map some more relocs to their 64 bit counterpart when
1114 size is 8.
1115 (output_insn): Work around breakage if DEBUG386 is defined.
1116 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
1117 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
1118 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
1119 different from i386.
1120 (output_imm): Ditto.
1121 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
1122 Imm64.
1123 (md_convert_frag): Jumps can now be larger than 2GB away, error
1124 out in that case.
1125 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
1126 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
1127
0a44bf69
RS		 11282006-03-22 Richard Sandiford <richard@codesourcery.com>
1129 Daniel Jacobowitz <dan@codesourcery.com>
1130 Phil Edwards <phil@codesourcery.com>
1131 Zack Weinberg <zack@codesourcery.com>
1132 Mark Mitchell <mark@codesourcery.com>
1133 Nathan Sidwell <nathan@codesourcery.com>
1134
1135 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
1136 (md_begin): Complain about -G being used for PIC. Don't change
1137 the text, data and bss alignments on VxWorks.
1138 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
1139 generating VxWorks PIC.
1140 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
1141 (macro): Likewise, but do not treat la $25 specially for
1142 VxWorks PIC, and do not handle jal.
1143 (OPTION_MVXWORKS_PIC): New macro.
1144 (md_longopts): Add -mvxworks-pic.
1145 (md_parse_option): Don't complain about using PIC and -G together here.
1146 Handle OPTION_MVXWORKS_PIC.
1147 (md_estimate_size_before_relax): Always use the first relaxation
1148 sequence on VxWorks.
1149 * config/tc-mips.h (VXWORKS_PIC): New.
1150
080eb7fe
PB		 11512006-03-21 Paul Brook <paul@codesourcery.com>
1152
1153 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
1154
03aaa593
BW		 11552006-03-21 Sterling Augustine <sterling@tensilica.com>
1156
1157 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
1158 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
1159 (get_loop_align_size): New.
1160 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
1161 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
1162 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
1163 (get_noop_aligned_address): Use get_loop_align_size.
1164 (get_aligned_diff): Likewise.
1165
3e94bf1a
PB		 11662006-03-21 Paul Brook <paul@codesourcery.com>
1167
1168 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
1169
dfa9f0d5
PB		 11702006-03-20 Paul Brook <paul@codesourcery.com>
1171
1172 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
1173 (do_t_branch): Encode branches inside IT blocks as unconditional.
1174 (do_t_cps): New function.
1175 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
1176 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
1177 (opcode_lookup): Allow conditional suffixes on all instructions in
1178 Thumb mode.
1179 (md_assemble): Advance condexec state before checking for errors.
1180 (insns): Use do_t_cps.
1181
6e1cb1a6
PB		 11822006-03-20 Paul Brook <paul@codesourcery.com>
1183
1184 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
1185 outputting the insn.
1186
0a966e2d
JBG		 11872006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1188
1189 * config/tc-vax.c: Update copyright year.
1190 * config/tc-vax.h: Likewise.
1191
a49fcc17
JBG		 11922006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1193
1194 * config/tc-vax.c (md_chars_to_number): Used only locally, so
1195 make it static.
1196 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
1197
f5208ef2
PB		 11982006-03-17 Paul Brook <paul@codesourcery.com>
1199
1200 * config/tc-arm.c (insns): Add ldm and stm.
1201
cb4c78d6
BE		 12022006-03-17 Ben Elliston <bje@au.ibm.com>
1203
1204 PR gas/2446
1205 * doc/as.texinfo (Ident): Document this directive more thoroughly.
1206
c16d2bf0
PB		 12072006-03-16 Paul Brook <paul@codesourcery.com>
1208
1209 * config/tc-arm.c (insns): Add "svc".
1210
80ca4e2c
BW		 12112006-03-13 Bob Wilson <bob.wilson@acm.org>
1212
1213 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
1214 flag and avoid double underscore prefixes.
1215
3a4a14e9
PB		 12162006-03-10 Paul Brook <paul@codesourcery.com>
1217
1218 * config/tc-arm.c (md_begin): Handle EABIv5.
1219 (arm_eabis): Add EF_ARM_EABI_VER5.
1220 * doc/c-arm.texi: Document -meabi=5.
1221
518051dc
BE		 12222006-03-10 Ben Elliston <bje@au.ibm.com>
1223
1224 * app.c (do_scrub_chars): Simplify string handling.
1225
00a97672
RS		 12262006-03-07 Richard Sandiford <richard@codesourcery.com>
1227 Daniel Jacobowitz <dan@codesourcery.com>
1228 Zack Weinberg <zack@codesourcery.com>
1229 Nathan Sidwell <nathan@codesourcery.com>
1230 Paul Brook <paul@codesourcery.com>
1231 Ricardo Anguiano <anguiano@codesourcery.com>
1232 Phil Edwards <phil@codesourcery.com>
1233
1234 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
1235 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
1236 R_ARM_ABS12 reloc.
1237 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
1238 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
1239 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
1240
b29757dc
BW		 12412006-03-06 Bob Wilson <bob.wilson@acm.org>
1242
1243 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
1244 even when using the text-section-literals option.
1245
0b2e31dc
NS		 12462006-03-06 Nathan Sidwell <nathan@codesourcery.com>
1247
1248 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
1249 and cf.
1250 (m68k_ip): <case 'J'> Check we have some control regs.
1251 (md_parse_option): Allow raw arch switch.
1252 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
1253 whether 68881 or cfloat was meant by -mfloat.
1254 (md_show_usage): Adjust extension display.
1255 (m68k_elf_final_processing): Adjust.
1256
df406460
NC		 12572006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
1258
1259 * config/tc-avr.c (avr_mod_hash_value): New function.
1260 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
1261 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
1262 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
1263 instead of int avr_ldi_expression: use avr_mod_hash_value instead
1264 of (int).
1265 (tc_gen_reloc): Handle substractions of symbols, if possible do
1266 fixups, abort otherwise.
1267 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
1268 tc_fix_adjustable): Define.
1269
53022e4a
JW		 12702006-03-02 James E Wilson <wilson@specifix.com>
1271
1272 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
1273 change the template, then clear md.slot[curr].end_of_insn_group.
1274
9f6f925e
JB		 12752006-02-28 Jan Beulich <jbeulich@novell.com>
1276
1277 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
1278
0e31b3e1
JB		 12792006-02-28 Jan Beulich <jbeulich@novell.com>
1280
1281 PR/1070
1282 * macro.c (getstring): Don't treat parentheses special anymore.
1283 (get_any_string): Don't consider '(' and ')' as quoting anymore.
1284 Special-case '(', ')', '[', and ']' when dealing with non-quoting
1285 characters.
1286
10cd14b4
AM		 12872006-02-28 Mat <mat@csail.mit.edu>
1288
1289 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
1290
63752a75
JJ		 12912006-02-27 Jakub Jelinek <jakub@redhat.com>
1292
1293 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
1294 field.
1295 (CFI_signal_frame): Define.
1296 (cfi_pseudo_table): Add .cfi_signal_frame.
1297 (dot_cfi): Handle CFI_signal_frame.
1298 (output_cie): Handle cie->signal_frame.
1299 (select_cie_for_fde): Don't share CIE if signal_frame flag is
1300 different. Copy signal_frame from FDE to newly created CIE.
1301 * doc/as.texinfo: Document .cfi_signal_frame.
1302
f7d9e5c3
CD		 13032006-02-27 Carlos O'Donell <carlos@codesourcery.com>
1304
1305 * doc/Makefile.am: Add html target.
1306 * doc/Makefile.in: Regenerate.
1307 * po/Make-in: Add html target.
1308
331d2d0d
L		 13092006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1310
8502d882 1311 * config/tc-i386.c (output_insn): Support Intel Merom New
331d2d0d
L		 1312 Instructions.
1313
8502d882 1314 * config/tc-i386.h (CpuMNI): New.
331d2d0d
L		 1315 (CpuUnknownFlags): Add CpuMNI.
1316
10156f83
DM		 13172006-02-24 David S. Miller <davem@sunset.davemloft.net>
1318
1319 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
1320 (hpriv_reg_table): New table for hyperprivileged registers.
1321 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
1322 register encoding.
1323
6772dd07
DD		 13242006-02-24 DJ Delorie <dj@redhat.com>
1325
1326 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
1327 (tc_gen_reloc): Don't define.
1328 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
1329 (OPTION_LINKRELAX): New.
1330 (md_longopts): Add it.
1331 (m32c_relax): New.
1332 (md_parse_options): Set it.
1333 (md_assemble): Emit relaxation relocs as needed.
1334 (md_convert_frag): Emit relaxation relocs as needed.
1335 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
1336 (m32c_apply_fix): New.
1337 (tc_gen_reloc): New.
1338 (m32c_force_relocation): Force out jump relocs when relaxing.
1339 (m32c_fix_adjustable): Return false if relaxing.
1340
62b3e311
PB		 13412006-02-24 Paul Brook <paul@codesourcery.com>
1342
1343 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
1344 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
1345 (struct asm_barrier_opt): Define.
1346 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
1347 (parse_psr): Accept V7M psr names.
1348 (parse_barrier): New function.
1349 (enum operand_parse_code): Add OP_oBARRIER.
1350 (parse_operands): Implement OP_oBARRIER.
1351 (do_barrier): New function.
1352 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
1353 (do_t_cpsi): Add V7M restrictions.
1354 (do_t_mrs, do_t_msr): Validate V7M variants.
1355 (md_assemble): Check for NULL variants.
1356 (v7m_psrs, barrier_opt_names): New tables.
1357 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
1358 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
1359 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
1360 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
1361 (struct cpu_arch_ver_table): Define.
1362 (cpu_arch_ver): New.
1363 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
1364 Tag_CPU_arch_profile.
1365 * doc/c-arm.texi: Document new cpu and arch options.
1366
59cf82fe
L		 13672006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1368
1369 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
1370
19a7219f
L		 13712006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1372
1373 * config/tc-ia64.c: Update copyright years.
1374
7f3dfb9c
L		 13752006-02-22 H.J. Lu <hongjiu.lu@intel.com>
1376
1377 * config/tc-ia64.c (specify_resource): Add the rule 17 from
1378 SDM 2.2.
1379
f40d1643
PB		 13802005-02-22 Paul Brook <paul@codesourcery.com>
1381
1382 * config/tc-arm.c (do_pld): Remove incorrect write to
1383 inst.instruction.
1384 (encode_thumb32_addr_mode): Use correct operand.
1385
216d22bc
PB		 13862006-02-21 Paul Brook <paul@codesourcery.com>
1387
1388 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
1389
d70c5fc7
NC		 13902006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
1391 Anil Paranjape <anilp1@kpitcummins.com>
1392 Shilin Shakti <shilins@kpitcummins.com>
1393
1394 * Makefile.am: Add xc16x related entry.
1395 * Makefile.in: Regenerate.
1396 * configure.in: Added xc16x related entry.
1397 * configure: Regenerate.
1398 * config/tc-xc16x.h: New file
1399 * config/tc-xc16x.c: New file
1400 * doc/c-xc16x.texi: New file for xc16x
1401 * doc/all.texi: Entry for xc16x
1402 * doc/Makefile.texi: Added c-xc16x.texi
1403 * NEWS: Announce the support for the new target.
1404
aaa2ab3d
NH		 14052006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
1406
1407 * configure.tgt: set emulation for mips-*-netbsd*
1408
82de001f
JJ		 14092006-02-14 Jakub Jelinek <jakub@redhat.com>
1410
1411 * config.in: Rebuilt.
1412
431ad2d0
BW		 14132006-02-13 Bob Wilson <bob.wilson@acm.org>
1414
1415 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
1416 from 1, not 0, in error messages.
1417 (md_assemble): Simplify special-case check for ENTRY instructions.
1418 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
1419 operand in error message.
1420
94089a50
JM		 14212006-02-13 Joseph S. Myers <joseph@codesourcery.com>
1422
1423 * configure.tgt (arm-*-linux-gnueabi*): Change to
1424 arm-*-linux-*eabi*.
1425
52de4c06
NC		 14262006-02-10 Nick Clifton <nickc@redhat.com>
1427
70e45ad9
NC		 1428 * config/tc-crx.c (check_range): Ensure that the sign bit of a
1429 32-bit value is propagated into the upper bits of a 64-bit long.
1430
52de4c06
NC		 1431 * config/tc-arc.c (init_opcode_tables): Fix cast.
1432 (arc_extoper, md_operand): Likewise.
1433
21af2bbd
BW		 14342006-02-09 David Heine <dlheine@tensilica.com>
1435
1436 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
1437 each relaxation step.
1438
75a706fc
L		 14392006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
1440
1441 * configure.in (CHECK_DECLS): Add vsnprintf.
1442 * configure: Regenerate.
1443 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
1444 include/declare here, but...
1445 * as.h: Move code detecting VARARGS idiom to the top.
1446 (errno.h, stdarg.h, varargs.h, va_list): ...here.
1447 (vsnprintf): Declare if not already declared.
1448
0d474464
L		 14492006-02-08 H.J. Lu <hongjiu.lu@intel.com>
1450
1451 * as.c (close_output_file): New.
1452 (main): Register close_output_file with xatexit before
1453 dump_statistics. Don't call output_file_close.
1454
266abb8f
NS		 14552006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1456
1457 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
1458 mcf5329_control_regs): New.
1459 (not_current_architecture, selected_arch, selected_cpu): New.
1460 (m68k_archs, m68k_extensions): New.
1461 (archs): Renamed to ...
1462 (m68k_cpus): ... here. Adjust.
1463 (n_arches): Remove.
1464 (md_pseudo_table): Add arch and cpu directives.
1465 (find_cf_chip, m68k_ip): Adjust table scanning.
1466 (no_68851, no_68881): Remove.
1467 (md_assemble): Lazily initialize.
1468 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
1469 (md_init_after_args): Move functionality to m68k_init_arch.
1470 (mri_chip): Adjust table scanning.
1471 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
1472 options with saner parsing.
1473 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
1474 m68k_init_arch): New.
1475 (s_m68k_cpu, s_m68k_arch): New.
1476 (md_show_usage): Adjust.
1477 (m68k_elf_final_processing): Set CF EF flags.
1478 * config/tc-m68k.h (m68k_init_after_args): Remove.
1479 (tc_init_after_args): Remove.
1480 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
1481 (M68k-Directives): Document .arch and .cpu directives.
1482
134dcee5
AM		 14832006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
1484
1485 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
1486 synonyms for equ and defl.
1487 (z80_cons_fix_new): New function.
1488 (emit_byte): Disallow relative jumps to absolute locations.
1489 (emit_data): Only handle defb, prototype changed, because defb is
1490 now handled as pseudo-op rather than an instruction.
1491 (instab): Entries for defb,defw,db,dw moved from here...
1492 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
1493 Add entries for def24,def32,d24,d32.
1494 (md_assemble): Improved error handling.
1495 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
1496 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
1497 (z80_cons_fix_new): Declare.
1498 * doc/c-z80.texi (defb, db): Mention warning on overflow.
1499 (def24,d24,def32,d32): New pseudo-ops.
1500
a9931606
PB		 15012006-02-02 Paul Brook <paul@codesourcery.com>
1502
1503 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1504
ef8d22e6
PB		 15052005-02-02 Paul Brook <paul@codesourcery.com>
1506
1507 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1508 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1509 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1510 T2_OPCODE_RSB): Define.
1511 (thumb32_negate_data_op): New function.
1512 (md_apply_fix): Use it.
1513
e7da6241
BW		 15142006-01-31 Bob Wilson <bob.wilson@acm.org>
1515
1516 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1517 fields.
1518 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1519 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1520 subtracted symbols.
1521 (relaxation_requirements): Add pfinish_frag argument and use it to
1522 replace setting tinsn->record_fix fields.
1523 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1524 and vinsn_to_insnbuf. Remove references to record_fix and
1525 slot_sub_symbols fields.
1526 (xtensa_mark_narrow_branches): Delete unused code.
1527 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1528 a symbol.
1529 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1530 record_fix fields.
1531 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1532 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1533 of the record_fix field. Simplify error messages for unexpected
1534 symbolic operands.
1535 (set_expr_symbol_offset_diff): Delete.
1536
79134647
PB		 15372006-01-31 Paul Brook <paul@codesourcery.com>
1538
1539 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1540
e74cfd16
PB		 15412006-01-31 Paul Brook <paul@codesourcery.com>
1542 Richard Earnshaw <rearnsha@arm.com>
1543
1544 * config/tc-arm.c: Use arm_feature_set.
1545 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1546 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1547 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1548 New variables.
1549 (insns): Use them.
1550 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1551 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1552 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1553 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1554 feature flags.
1555 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1556 (arm_opts): Move old cpu/arch options from here...
1557 (arm_legacy_opts): ... to here.
1558 (md_parse_option): Search arm_legacy_opts.
1559 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1560 (arm_float_abis, arm_eabis): Make const.
1561
d47d412e
BW		 15622006-01-25 Bob Wilson <bob.wilson@acm.org>
1563
1564 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1565
b14273fe
JZ		 15662006-01-21 Jie Zhang <jie.zhang@analog.com>
1567
1568 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1569 in load immediate intruction.
1570
39cd1c76
JZ		 15712006-01-21 Jie Zhang <jie.zhang@analog.com>
1572
1573 * config/bfin-parse.y (value_match): Use correct conversion
1574 specifications in template string for __FILE__ and __LINE__.
1575 (binary): Ditto.
1576 (unary): Ditto.
1577
67a4f2b7
AO		 15782006-01-18 Alexandre Oliva <aoliva@redhat.com>
1579
1580 Introduce TLS descriptors for i386 and x86_64.
1581 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1582 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1583 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1584 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1585 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1586 displacement bits.
1587 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1588 (lex_got): Handle @tlsdesc and @tlscall.
1589 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1590
8ad7c533
NC		 15912006-01-11 Nick Clifton <nickc@redhat.com>
1592
1593 Fixes for building on 64-bit hosts:
1594 * config/tc-avr.c (mod_index): New union to allow conversion
1595 between pointers and integers.
1596 (md_begin, avr_ldi_expression): Use it.
1597 * config/tc-i370.c (md_assemble): Add cast for argument to print
1598 statement.
1599 * config/tc-tic54x.c (subsym_substitute): Likewise.
1600 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1601 opindex field of fr_cgen structure into a pointer so that it can
1602 be stored in a frag.
1603 * config/tc-mn10300.c (md_assemble): Likewise.
1604 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1605 types.
1606 * config/tc-v850.c: Replace uses of (int) casts with correct
1607 types.
1608
4dcb3903
L		 16092006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1610
1611 PR gas/2117
1612 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1613
e0f6ea40
HPN		 16142006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1615
1616 PR gas/2101
1617 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1618 a local-label reference.
1619
e88d958a 1620For older changes see ChangeLog-2005
08d56133
NC		 1621\f
1622Local Variables:
1623mode: change-log
1624left-margin: 8
1625fill-column: 74
1626version-control: never
1627End:
GDB Binutils - Deliverables
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