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d436c1c2
RS		 12013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * config/tc-mips.c (match_expression): Report uses of registers here.
4 Add a "must be an immediate expression" error. Handle elided offsets
5 here rather than...
6 (match_int_operand): ...here.
7
1a00e612
RS		 82013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
9
10 * config/tc-mips.c (mips_arg_info): Remove soft_match.
11 (match_out_of_range, match_not_constant): New functions.
12 (match_const_int): Remove fallback parameter and check for soft_match.
13 Use match_not_constant.
14 (match_mapped_int_operand, match_addiusp_operand)
15 (match_perf_reg_operand, match_save_restore_list_operand)
16 (match_mdmx_imm_reg_operand): Update accordingly. Use
17 match_out_of_range and set_insn_error* instead of as_bad.
18 (match_int_operand): Likewise. Use match_not_constant in the
19 !allows_nonconst case.
20 (match_float_constant): Report invalid float constants.
21 (match_insn, match_mips16_insn): Remove soft_match code. Rely on
22 match_float_constant to check for invalid constants. Fail the
23 match if match_const_int or match_float_constant return false.
24 (mips_ip): Update accordingly.
25 (mips16_ip): Likewise. Undo null termination of instruction name
26 once lookup is complete.
27
e3de51ce
RS		 282013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
29
30 * config/tc-mips.c (mips_insn_error_format): New enum.
31 (mips_insn_error): New struct.
32 (insn_error): Change to a mips_insn_error.
33 (clear_insn_error, set_insn_error_format, set_insn_error)
34 (set_insn_error_i, set_insn_error_ss, report_insn_error): New
35 functions.
36 (mips_parse_argument_token, md_assemble, match_insn)
37 (match_mips16_insn): Use them instead of manipulating insn_error
38 directly.
39 (mips_ip, mips16_ip): Likewise. Simplify control flow.
40
97d87491
RS		 412013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
42
43 * config/tc-mips.c (normalize_constant_expr): Move further up file.
44 (normalize_address_expr): Likewise.
45 (match_insn, match_mips16_insn): New functions, split out from...
46 (mips_ip, mips16_ip): ...here.
47
0f35dbc4
RS		 482013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
49
50 * config/tc-mips.c (operand_reg_mask, match_operand): Handle
51 OP_OPTIONAL_REG.
52 (mips_ip, mips16_ip): Use mips_optional_operand_p to check
53 for optional operands.
54
27285eed
AM		 552013-08-16 Alan Modra <amodra@gmail.com>
56
57 * config/tc-ppc.c (ppc_elf_cons): Allow @l and other reloc
58 modifiers generally.
59
cbe02d4f
AM		 602013-08-16 Alan Modra <amodra@gmail.com>
61
62 * config/tc-ppc.c (ppc_elf_lcomm): Use subsection 1.
63
3c02c47f
DE		 642013-08-14 David Edelsohn <dje.gcc@gmail.com>
65
66 * config/tc-ppc.c (ppc_comm): Accept optional fourth .lcomm
67 argument as alignment.
68
4046d87a
NC		 692013-08-09 Nick Clifton <nickc@redhat.com>
70
71 * config/tc-rl78.c (elf_flags): New variable.
72 (enum options): Add OPTION_G10.
73 (md_longopts): Add mg10.
74 (md_parse_option): Parse -mg10.
75 (rl78_elf_final_processing): New function.
76 * config/tc-rl78.c (tc_final_processing): Define.
77 * doc/c-rl78.texi: Document -mg10 option.
78
ee5734f0
RS		 792013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
80
81 * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
82 suffixes to be elided too.
83 (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
84 (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N
85 to be omitted too.
86
13896403
RS		 872013-08-05 John Tytgat <john@bass-software.com>
88
89 * po/POTFILES.in: Regenerate.
90
d6787ef9
EB		 912013-08-05 Eric Botcazou <ebotcazou@adacore.com>
92 Konrad Eisele <konrad@gaisler.com>
93
94 * config/tc-sparc.c (sparc_arch_types): Add leon.
95 (sparc_arch): Move sparc4 around and add leon.
96 (sparc_target_format): Document -Aleon.
97 * doc/c-sparc.texi: Likewise.
98
da8bca91
RS		 992013-08-05 Richard Sandiford <rdsandiford@googlemail.com>
100
101 * config/tc-mips.c (mips_lookup_insn): Make length and opend signed.
102
14daeee3
RS		 1032013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
104 Richard Sandiford <rdsandiford@googlemail.com>
105
106 * config/tc-mips.c (MAX_OPERANDS): Bump to 6.
107 (RWARN): Bump to 0x8000000.
108 (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
109 (RTYPE_R5900_ACC): New register types.
110 (RTYPE_MASK): Include them.
111 (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
112 macros.
113 (reg_names): Include them.
114 (mips_parse_register_1): New function, split out from...
115 (mips_parse_register): ...here. Add a channels_ptr parameter.
116 Look for VU0 channel suffixes when nonnull.
117 (reg_lookup): Update the call to mips_parse_register.
118 (mips_parse_vu0_channels): New function.
119 (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
120 (mips_operand_token): Add a "channels" field to the union.
121 Extend the comment above "ch" to OT_DOUBLE_CHAR.
122 (mips_parse_base_start): Match -- and ++. Handle channel suffixes.
123 (mips_parse_argument_token): Handle channel suffixes here too.
124 (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
125 Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
126 Handle '#' formats.
127 (md_begin): Register $vfN and $vfI registers.
128 (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
129 (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
130 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
131 (match_vu0_suffix_operand): New function.
132 (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
133 (macro): Use "+7" rather than "E" for LDQ2 and STQ2.
134 (mips_lookup_insn): New function.
135 (mips_ip): Use it. Allow "+K" operands to be elided at the end
136 of an instruction. Handle '#' sequences.
137
c0ebe874
RS		 1382013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
139
140 * config/tc-mips.c (macro, mips16_macro): Create an array of operand
141 values and use it instead of sreg, treg, xreg, etc.
142
3ccad066
RS		 1432013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
144
145 * config/tc-mips.c (match_int_operand): Use mips_int_operand_min
146 and mips_int_operand_max.
147 (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
148 Delete.
149 (mips16_immed_operand, mips16_immed_in_range_p): New functions.
150 (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
151 instead of mips16_immed_operand.
152
0acfaea6
RS		 1532013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
154
155 * config/tc-mips.c (mips16_macro): Don't use move_register.
156 (mips16_ip): Allow macros to use 'p'.
157
fc76e730
RS		 1582013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
159
160 * config/tc-mips.c (MAX_OPERANDS): New macro.
161 (mips_operand_array): New structure.
162 (mips_operands, mips16_operands, micromips_operands): New arrays.
163 (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
164 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
165 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
166 (micromips_to_32_reg_q_map): Delete.
167 (insn_operands, insn_opno, insn_extract_operand): New functions.
168 (validate_mips_insn): Take a mips_operand_array as argument and
169 use it to build up a list of operands. Extend to handle INSN_MACRO
170 and MIPS16.
171 (validate_mips16_insn): New function.
172 (validate_micromips_insn): Take a mips_operand_array as argument.
173 Handle INSN_MACRO.
174 (md_begin): Initialize mips_operands, mips16_operands and
175 micromips_operands. Call validate_mips_insn and
176 validate_micromips_insn for macro instructions too.
177 Call validate_mips16_insn for MIPS16 instructions.
178 (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
179 New functions.
180 (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
181 them. Handle INSN_UDI.
182 (get_append_method): Use gpr_read_mask.
183
26545944
RS		 1842013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
185
186 * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
187 flags for MIPS16 and non-MIPS16 instructions.
188 (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
189 (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
190 (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
191 (can_swap_branch_p, get_append_method): Use the same flags for MIPS16
192 and non-MIPS16 instructions. Fix formatting.
193
85fcb30f
RS		 1942013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
195
196 * config/tc-mips.c (reg_needs_delay): Move later in file.
197 Use gpr_write_mask.
198 (insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND.
199
43234a1e
L		 2002013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
201 Alexander Ivchenko <alexander.ivchenko@intel.com>
202 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
203 Sergey Lega <sergey.s.lega@intel.com>
204 Anna Tikhonova <anna.tikhonova@intel.com>
205 Ilya Tocar <ilya.tocar@intel.com>
206 Andrey Turetskiy <andrey.turetskiy@intel.com>
207 Ilya Verbin <ilya.verbin@intel.com>
208 Kirill Yukhin <kirill.yukhin@intel.com>
209 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
210
211 * config/tc-i386-intel.c (O_zmmword_ptr): New.
212 (i386_types): Add zmmword.
213 (i386_intel_simplify_register): Allow regzmm.
214 (i386_intel_simplify): Handle zmmwords.
215 (i386_intel_operand): Handle RC/SAE, vector operations and
216 zmmwords.
217 * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
218 (struct RC_Operation): New.
219 (struct Mask_Operation): New.
220 (struct Broadcast_Operation): New.
221 (vex_prefix): Size of bytes increased to 4 to support EVEX
222 encoding.
223 (enum i386_error): Add new error codes: unsupported_broadcast,
224 broadcast_not_on_src_operand, broadcast_needed,
225 unsupported_masking, mask_not_on_destination, no_default_mask,
226 unsupported_rc_sae, rc_sae_operand_not_last_imm,
227 invalid_register_operand, try_vector_disp8.
228 (struct _i386_insn): Add new fields vrex, need_vrex, mask,
229 rounding, broadcast, memshift.
230 (struct RC_name): New.
231 (RC_NamesTable): New.
232 (evexlig): New.
233 (evexwig): New.
234 (extra_symbol_chars): Add '{'.
235 (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
236 (i386_operand_type): Add regzmm, regmask and vec_disp8.
237 (match_mem_size): Handle zmmwords.
238 (operand_type_match): Handle zmm-registers.
239 (mode_from_disp_size): Handle vec_disp8.
240 (fits_in_vec_disp8): New.
241 (md_begin): Handle {} properly.
242 (type_names): Add "rZMM", "Mask reg" and "Vector d8".
243 (build_vex_prefix): Handle vrex.
244 (build_evex_prefix): New.
245 (process_immext): Adjust to properly handle EVEX.
246 (md_assemble): Add EVEX encoding support.
247 (swap_2_operands): Correctly handle operands with masking,
248 broadcasting or RC/SAE.
249 (check_VecOperands): Support EVEX features.
250 (VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
251 (match_template): Support regzmm and handle new error codes.
252 (process_suffix): Handle zmmwords and zmm-registers.
253 (check_byte_reg): Extend to zmm-registers.
254 (process_operands): Extend to zmm-registers.
255 (build_modrm_byte): Handle EVEX.
256 (output_insn): Adjust to properly handle EVEX case.
257 (disp_size): Handle vec_disp8.
258 (output_disp): Support compressed disp8*N evex feature.
259 (output_imm): Handle RC/SAE immediates properly.
260 (check_VecOperations): New.
261 (i386_immediate): Handle EVEX features.
262 (i386_index_check): Handle zmmwords and zmm-registers.
263 (RC_SAE_immediate): New.
264 (i386_att_operand): Handle EVEX features.
265 (parse_real_register): Add a check for ZMM/Mask registers.
266 (OPTION_MEVEXLIG): New.
267 (OPTION_MEVEXWIG): New.
268 (md_longopts): Add mevexlig and mevexwig.
269 (md_parse_option): Handle mevexlig and mevexwig options.
270 (md_show_usage): Add description for mevexlig and mevexwig.
271 * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
272 avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
273
a0046408
L		 2742013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
275
276 * config/tc-i386.c (cpu_arch): Add .sha.
277 * doc/c-i386.texi: Document sha/.sha.
278
7e8b059b
L		 2792013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
280 Kirill Yukhin <kirill.yukhin@intel.com>
281 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
282
283 * config/tc-i386.c (BND_PREFIX): New.
284 (struct _i386_insn): Add new field bnd_prefix.
285 (add_bnd_prefix): New.
286 (cpu_arch): Add MPX.
287 (i386_operand_type): Add regbnd.
288 (md_assemble): Handle BND prefixes.
289 (parse_insn): Likewise.
290 (output_branch): Likewise.
291 (output_jump): Likewise.
292 (build_modrm_byte): Handle regbnd.
293 (OPTION_MADD_BND_PREFIX): New.
294 (md_longopts): Add entry for 'madd-bnd-prefix'.
295 (md_parse_option): Handle madd-bnd-prefix option.
296 (md_show_usage): Add description for madd-bnd-prefix
297 option.
298 * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
299
7fa9fcb6
TG		 3002013-07-24 Tristan Gingold <gingold@adacore.com>
301
302 * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on
303 xcoff targets.
304
614eb277
AK		 3052013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
306
307 * config/tc-s390.c (s390_machine): Don't force the .machine
308 argument to lower case.
309
e673710a
KT		 3102013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
311
312 * config/tc-arm.c (s_arm_arch_extension): Improve error message
313 for invalid extension.
314
69091a2c
YZ		 3152013-07-19 Yufeng Zhang <yufeng.zhang@arm.com>
316
317 * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
318 (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
319 (aarch64_abi): New variable.
320 (ilp32_p): Change to be a macro.
321 (aarch64_opts): Remove the support for option -milp32 and -mlp64.
322 (struct aarch64_option_abi_value_table): New struct.
323 (aarch64_abis): New table.
324 (aarch64_parse_abi): New function.
325 (aarch64_long_opts): Add entry for -mabi=.
326 * doc/as.texinfo (Target AArch64 options): Document -mabi.
327 * doc/c-aarch64.texi: Likewise.
328
faf786e6
NC		 3292013-07-18 Jim Thomas <thomas@cfht.hawaii.edu>
330
331 * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs
332 unsigned comparison.
333
f0c00282
NC		 3342013-07-18 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
335
cbe02d4f 336 * config/rx-defs.h: Add macros for RX100, RX200, RX600, and
f0c00282 337 RX610.
cbe02d4f 338 * config/rx-parse.y: (rx_check_float_support): Add function to
f0c00282
NC		 339 check floating point operation support for target RX100 and
340 RX200.
cbe02d4f
AM		 341 * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610.
342 * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100,
343 RX200, RX600, and RX610
f0c00282 344
8c997c27
NC		 3452013-07-18 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
346
347 * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text
348
8be59acb
NC		 3492013-07-18 Vishnu K.S <vishnu.k_s@atmel.com>
350
351 * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4.
352 * doc/c-avr.texi: Likewise.
353
4a06e5a2
RS		 3542013-07-15 Richard Sandiford <rdsandiford@googlemail.com>
355
356 * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat
357 error with older GCCs.
358 (mips16_macro_build): Dereference args.
359
a92713e6
RS		 3602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
361
362 * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
363 New functions, split out from...
364 (reg_lookup): ...here. Remove itbl support.
365 (reglist_lookup): Delete.
366 (mips_operand_token_type): New enum.
367 (mips_operand_token): New structure.
368 (mips_operand_tokens): New variable.
369 (mips_add_token, mips_parse_base_start, mips_parse_argument_token)
370 (mips_parse_arguments): New functions.
371 (md_begin): Initialize mips_operand_tokens.
372 (mips_arg_info): Add a token field. Remove optional_reg field.
373 (match_char, match_expression): New functions.
374 (match_const_int): Use match_expression. Remove "s" argument
375 and return a boolean result. Remove O_register handling.
376 (match_regno, match_reg, match_reg_range): New functions.
377 (match_int_operand, match_mapped_int_operand, match_msb_operand)
378 (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
379 (match_addiusp_operand, match_clo_clz_dest_operand)
380 (match_lwm_swm_list_operand, match_entry_exit_operand)
381 (match_save_restore_list_operand, match_mdmx_imm_reg_operand)
382 (match_tied_reg_operand): Remove "s" argument and return a boolean
383 result. Match tokens rather than text. Update calls to
384 match_const_int. Rely on match_regno to call check_regno.
385 (match_pcrel_operand, match_pc_operand): Replace "s" argument with
386 "arg" argument. Return a boolean result.
387 (parse_float_constant): Replace with...
388 (match_float_constant): ...this new function.
389 (match_operand): Remove "s" argument and return a boolean result.
390 Update calls to subfunctions.
391 (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
392 rather than string-parsing routines. Update handling of optional
393 registers for token scheme.
394
89565f1b
RS		 3952013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
396
397 * config/tc-mips.c (parse_float_constant): Split out from...
398 (mips_ip): ...here.
399
3c14a432
RS		 4002013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
401
402 * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND):
403 Delete.
404
364215c8
RS		 4052013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
406
407 * config/tc-mips.c (mips32_to_16_reg_map): Delete.
408 (match_entry_exit_operand): New function.
409 (match_save_restore_list_operand): Likewise.
410 (match_operand): Use them.
411 (check_absolute_expr): Delete.
412 (mips16_ip): Rewrite main parsing loop to use mips_operands.
413
9e12b7a2
RS		 4142013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
415
416 * config/tc-mips.c: Enable functions commented out in previous patch.
417 (SKIP_SPACE_TABS): Move further up file.
418 (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
419 (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
420 (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
421 (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
422 (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
423 (micromips_imm_b_map, micromips_imm_c_map): Delete.
424 (mips_lookup_reg_pair): Delete.
425 (macro): Use report_bad_range and report_bad_field.
426 (mips_immed, expr_const_in_range): Delete.
427 (mips_ip): Rewrite main parsing loop to use new functions.
428
a1d78564
RS		 4292013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
430
431 * config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
432 Change return type to bfd_boolean.
433 (report_bad_range, report_bad_field): New functions.
434 (mips_arg_info): New structure.
435 (match_const_int, convert_reg_type, check_regno, match_int_operand)
436 (match_mapped_int_operand, match_msb_operand, match_reg_operand)
437 (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
438 (match_addiusp_operand, match_clo_clz_dest_operand)
439 (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
440 (match_pc_operand, match_tied_reg_operand, match_operand)
441 (check_completed_insn): New functions, commented out for now.
442
e077a1c8
RS		 4432013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
444
445 * config/tc-mips.c (insn_insert_operand): New function.
446 (macro_build, mips16_macro_build): Put null character check
447 in the for loop and convert continues to breaks. Use operand
448 structures to handle constant operands.
449
ab902481
RS		 4502013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
451
452 * config/tc-mips.c (validate_mips_insn): Move further up file.
453 Add insn_bits and decode_operand arguments. Use the mips_operand
454 fields to work out which bits an operand occupies. Detect double
455 definitions.
456 (validate_micromips_insn): Move further up file. Call into
457 validate_mips_insn.
458
2f8b73cc
RS		 4592013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
460
461 * config/tc-mips.c (mips16_macro_build): Remove 'Y' case.
462
c8276761
RS		 4632013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
464
465 * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\"
466 and "~".
467 (macro): Update accordingly.
468
77bd4346
RS		 4692013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
470
471 * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary.
472 (imm_reloc): Delete.
473 (md_assemble): Remove imm_reloc handling.
474 (mips_ip): Update commentary. Use offset_expr and offset_reloc
475 rather than imm_expr and imm_reloc for 'i', 'j' and 'u'.
476 Use a temporary array rather than imm_reloc when parsing
477 constant expressions. Remove imm_reloc initialization.
478 (mips16_ip): Update commentary. Use offset_expr and offset_reloc
479 for the relaxable field. Use a relax_char variable to track the
480 type of this field. Remove imm_reloc initialization.
481
cc537e56
RS		 4822013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
483
484 * config/tc-mips.c (mips16_ip): Handle "I".
485
ba92f887
MR		 4862013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
487
488 * config/tc-mips.c (mips_flag_nan2008): New variable.
489 (options): Add OPTION_NAN enum value.
490 (md_longopts): Handle it.
491 (md_parse_option): Likewise.
492 (s_nan): New function.
493 (mips_elf_final_processing): Handle EF_MIPS_NAN2008.
494 (md_show_usage): Add -mnan.
495
496 * doc/as.texinfo (Overview): Add -mnan.
497 * doc/c-mips.texi (MIPS Opts): Document -mnan.
498 (MIPS NaN Encodings): New node. Document .nan directive.
499 (MIPS-Dependent): List the new node.
500
c1094734
TG		 5012013-07-09 Tristan Gingold <gingold@adacore.com>
502
503 * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
504
0cbbe1b8
RS		 5052013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
506
507 * config/tc-mips.c (mips_ip): Unconditionally parse an expression
508 for 'A' and assume that the constant has been elided if the result
509 is an O_register.
510
f2ae14a1
RS		 5112013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
512
513 * config/tc-mips.c (gprel16_reloc_p): New function.
514 (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
515 BFD_RELOC_UNUSED.
516 (offset_high_part, small_offset_p): New functions.
517 (nacro): Use them. Remove *_OB and *_DOB cases. For single-
518 register load and store macros, handle the 16-bit offset case first.
519 If a 16-bit offset is not suitable for the instruction we're
520 generating, load it into the temporary register using
521 ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
522 M_L_DAB code once the address has been constructed. For double load
523 and store macros, again handle the 16-bit offset case first.
524 If the second register cannot be accessed from the same high
525 part as the first, load it into AT using ADDRESS_ADDI_INSN.
526 Fix the handling of LD in cases where the first register is the
527 same as the base. Also handle the case where the offset is
528 not 16 bits and the second register cannot be accessed from the
529 same high part as the first. For unaligned loads and stores,
530 fuse the offbits == 12 and old "ab" handling. Apply this handling
531 whenever the second offset needs a different high part from the first.
532 Construct the offset using ADDRESS_ADDI_INSN where possible,
533 for offbits == 16 as well as offbits == 12. Use offset_reloc
534 when constructing the individual loads and stores.
535 (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
536 and offset_reloc before matching against a particular opcode.
537 Handle elided 'A' constants. Allow 'A' constants to use
538 relocation operators.
539
5c324c16
RS		 5402013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
541
542 * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
543 (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
544 Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
545
23e69e47
RS		 5462013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
547
548 * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
549 Require the msb to be <= 31 for "+s". Check that the size is <= 31
550 for both "+s" and "+S".
551
27c5c572
RS		 5522013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
553
554 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
555 (mips_ip, mips16_ip): Handle "+i".
556
e76ff5ab
RS		 5572013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
558
559 * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
560 (micromips_to_32_reg_h_map): Rename to...
561 (micromips_to_32_reg_h_map1): ...this.
562 (micromips_to_32_reg_i_map): Rename to...
563 (micromips_to_32_reg_h_map2): ...this.
564 (mips_lookup_reg_pair): New function.
565 (gpr_write_mask, macro): Adjust after above renaming.
566 (validate_micromips_insn): Remove "mi" handling.
567 (mips_ip): Likewise. Parse both registers in a pair for "mh".
568
fa7616a4
RS		 5692013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
570
571 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
572 (mips_ip): Remove "+D" and "+T" handling.
573
fb798c50
AK		 5742013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
575
576 * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
577 relocs.
578
2c0a3565
MS		 5792013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
580
4aa2c5e2
MS		 581 * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
582
5832013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
584
2c0a3565
MS		 585 * config/tc-aarch64.c (md_apply_fix): Reorder case values.
586 (aarch64_force_relocation): Likewise.
587
f40da81b
AM		 5882013-07-02 Alan Modra <amodra@gmail.com>
589
590 * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
591
81566a9b
MR		 5922013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
593
594 * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
595 * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
596 Replace @sc{mips16} with literal `MIPS16'.
597 (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
598
a6bb11b2
YZ		 5992013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
600
601 * config/tc-aarch64.c (reloc_table): Replace
602 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
603 BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
604 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
605 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
606 (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
607 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
608 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
609 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
610 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
611 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
612 (aarch64_force_relocation): Likewise.
613
cec5225b
YZ		 6142013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
615
616 * config/tc-aarch64.c (ilp32_p): New static variable.
617 (elf64_aarch64_target_format): Return the target according to the
618 value of 'ilp32_p'.
619 (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
620 (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
621 (aarch64_dwarf2_addr_size): New function.
622 * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
623 (DWARF2_ADDR_SIZE): New define.
624
e335d9cb
RS		 6252013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
626
627 * doc/c-mips.texi: Use ISA instead of @sc{isa}.
628
18870af7
RS		 6292013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
630
631 * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
632
833794fc
MR		 6332013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
634
635 * config/tc-mips.c (mips_set_options): Add insn32 member.
636 (mips_opts): Initialize it.
637 (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
638 (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
639 (md_longopts): Add "minsn32" and "mno-insn32" options.
640 (is_size_valid): Handle insn32 mode.
641 (md_assemble): Pass instruction string down to macro.
642 (brk_fmt): Add second dimension and insn32 mode initializers.
643 (mfhl_fmt): Likewise.
644 (BRK_FMT, MFHL_FMT): Handle insn32 mode.
645 (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
646 (macro_build_jalr, move_register): Handle insn32 mode.
647 (macro_build_branch_rs): Likewise.
648 (macro): Handle insn32 mode.
649 <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
650 (mips_ip): Handle insn32 mode.
651 (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
652 (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
653 (mips_handle_align): Handle insn32 mode.
654 (md_show_usage): Add -minsn32 and -mno-insn32.
655
656 * doc/as.texinfo (Target MIPS options): Add -minsn32 and
657 -mno-insn32 options.
658 (-minsn32, -mno-insn32): New options.
659 * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
660 options.
661 (MIPS assembly options): New node. Document .set insn32 and
662 .set noinsn32.
663 (MIPS-Dependent): List the new node.
664
d1706f38
NC		 6652013-06-25 Nick Clifton <nickc@redhat.com>
666
667 * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
668 the PC in indirect addressing on 430xv2 parts.
669 (msp430_operands): Add version test to hardware bug encoding
670 restrictions.
671
477330fc
RM		 6722013-06-24 Roland McGrath <mcgrathr@google.com>
673
d996d970
RM		 674 * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
675 so it skips whitespace before it.
676 (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
677
477330fc
RM		 678 * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
679 (arm_reg_parse_multi): Skip whitespace first.
680 (parse_reg_list): Likewise.
681 (parse_vfp_reg_list): Likewise.
682 (s_arm_unwind_save_mmxwcg): Likewise.
683
24382199
NC		 6842013-06-24 Nick Clifton <nickc@redhat.com>
685
686 PR gas/15623
687 * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
688
c3678916
RS		 6892013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
690
691 * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
692
42429eac
RS		 6932013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
694
695 * config/tc-mips.c: Assert that offsetT and valueT are at least
696 8 bytes in size.
697 (GPR_SMIN, GPR_SMAX): New macros.
698 (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
699
f3ded42a
RS		 7002013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
701
702 * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
703 conditions. Remove any code deselected by them.
704 (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
705
e8044f35
RS		 7062013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
707
708 * NEWS: Note removal of ECOFF support.
709 * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
710 * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
711 (MULTI_CFILES): Remove config/e-mipsecoff.c.
712 * Makefile.in: Regenerate.
713 * configure.in: Remove MIPS ECOFF references.
714 (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
715 Delete cases.
716 (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
717 (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
718 (mips-*-*): ...this single case.
719 (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
720 MIPS emulations to be e-mipself*.
721 * configure: Regenerate.
722 * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
723 (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
724 (mips-*-sysv*): Remove coff and ecoff cases.
725 * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
726 * ecoff.c: Remove reference to MIPS ECOFF.
727 * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
728 * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
729 (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
730 (mips_hi_fixup): Tweak comment.
731 (append_insn): Require a howto.
732 (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
733
98508b2a
RS		 7342013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
735
736 * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
737 Use "CPU" instead of "cpu".
738 * doc/c-mips.texi: Likewise.
739 (MIPS Opts): Rename to MIPS Options.
740 (MIPS option stack): Rename to MIPS Option Stack.
741 (MIPS ASE instruction generation overrides): Rename to
742 MIPS ASE Instruction Generation Overrides (for now).
743 (MIPS floating-point): Rename to MIPS Floating-Point.
744
fc16f8cc
RS		 7452013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
746
747 * doc/c-mips.texi (MIPS Macros): New section.
748 (MIPS Object): Replace with...
749 (MIPS Small Data): ...this new section.
750
5a7560b5
RS		 7512013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
752
753 * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
754 Capitalize name. Use @kindex instead of @cindex for .set entries.
755
a1b86ab7
RS		 7562013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
757
758 * doc/c-mips.texi (MIPS Stabs): Remove section.
759
c6278170
RS		 7602013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
761
762 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
763 (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
764 (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
765 (ISA_SUPPORTS_VIRT64_ASE): Delete.
766 (mips_ase): New structure.
767 (mips_ases): New table.
768 (FP64_ASES): New macro.
769 (mips_ase_groups): New array.
770 (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
771 (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
772 functions.
773 (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
774 (md_parse_option): Use mips_ases and mips_set_ase instead of
775 separate case statements for each ASE option.
776 (mips_after_parse_args): Use FP64_ASES. Use
777 mips_check_isa_supports_ases to check the ASEs against
778 other options.
779 (s_mipsset): Use mips_ases and mips_set_ase instead of
780 separate if statements for each ASE option. Use
781 mips_check_isa_supports_ases, even when a non-ASE option
782 is specified.
783
63a4bc21
KT		 7842013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
785
786 * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
787
c31f3936
RS		 7882013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
789
790 * config/tc-mips.c (md_shortopts, options, md_longopts)
791 (md_longopts_size): Move earlier in file.
792
846ef2d0
RS		 7932013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
794
795 * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
796 with a single "ase" bitmask.
797 (mips_opts): Update accordingly.
798 (file_ase, file_ase_explicit): New variables.
799 (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
800 (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
801 (ISA_HAS_ROR): Adjust for mips_set_options change.
802 (is_opcode_valid): Take the base ase mask directly from mips_opts.
803 (mips_ip): Adjust for mips_set_options change.
804 (md_parse_option): Likewise. Update file_ase_explicit.
805 (mips_after_parse_args): Adjust for mips_set_options change.
806 Use bitmask operations to select the default ASEs. Set file_ase
807 rather than individual per-ASE variables.
808 (s_mipsset): Adjust for mips_set_options change.
809 (mips_elf_final_processing): Test file_ase rather than
810 file_ase_mdmx. Remove commented-out code.
811
d16afab6
RS		 8122013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
813
814 * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
815 (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
816 (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
817 (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
818 (mips_after_parse_args): Use the new "ase" field to choose
819 the default ASEs.
820 (mips_cpu_info_table): Move ASEs from the "flags" field to the
821 "ase" field.
822
e83a675f
RE		 8232013-06-18 Richard Earnshaw <rearnsha@arm.com>
824
825 * config/tc-arm.c (symbol_preemptible): New function.
826 (relax_branch): Use it.
827
7f3c4072
CM		 8282013-06-17 Catherine Moore <clm@codesourcery.com>
829 Maciej W. Rozycki <macro@codesourcery.com>
830 Chao-Ying Fu <fu@mips.com>
831
832 * config/tc-mips.c (mips_set_options): Add ase_eva.
833 (mips_set_options mips_opts): Add ase_eva.
834 (file_ase_eva): Declare.
835 (ISA_SUPPORTS_EVA_ASE): Define.
836 (IS_SEXT_9BIT_NUM): Define.
837 (MIPS_CPU_ASE_EVA): Define.
838 (is_opcode_valid): Add support for ase_eva.
839 (macro_build): Likewise.
840 (macro): Likewise.
841 (validate_mips_insn): Likewise.
842 (validate_micromips_insn): Likewise.
843 (mips_ip): Likewise.
844 (options): Add OPTION_EVA and OPTION_NO_EVA.
845 (md_longopts): Add -meva and -mno-eva.
846 (md_parse_option): Process new options.
847 (mips_after_parse_args): Check for valid EVA combinations.
848 (s_mipsset): Likewise.
849
e410add4
RS		 8502013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
851
852 * dwarf2dbg.h (dwarf2_move_insn): Declare.
853 * dwarf2dbg.c (line_subseg): Add pmove_tail.
854 (get_line_subseg): Add create_p argument. Initialize pmove_tail.
855 (dwarf2_gen_line_info_1): Update call accordingly.
856 (dwarf2_move_insn): New function.
857 * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
858
6a50d470
RS		 8592013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
860
861 Revert:
862
863 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
864
865 PR gas/13024
866 * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
867 (dwarf2_gen_line_info_1): Delete.
868 (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
869 (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
870 (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
871 (dwarf2_directive_loc): Push previous .locs instead of generating
872 them immediately.
873
f122319e
CF		 8742013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
875
876 * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
877 (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
878
909c7f9c
NC		 8792013-06-13 Nick Clifton <nickc@redhat.com>
880
881 PR gas/15602
882 * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
883 * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
884 function. Generates an error if the adjusted offset is out of a
885 16-bit range.
886
5d5755a7
SL		 8872013-06-12 Sandra Loosemore <sandra@codesourcery.com>
888
889 * config/tc-nios2.c (md_apply_fix): Mask constant
890 BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
891
3bf0dbfb
MR		 8922013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
893
894 * config/tc-mips.c (append_insn): Don't do branch relaxation for
895 MIPS-3D instructions either.
896 (md_convert_frag): Update the COPx branch mask accordingly.
897
898 * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
899 option.
900 * doc/as.texinfo (Overview): Add --relax-branch and
901 --no-relax-branch.
902 * doc/c-mips.texi (MIPS Opts): Document --relax-branch and
903 --no-relax-branch.
904
9daf7bab
SL		 9052013-06-09 Sandra Loosemore <sandra@codesourcery.com>
906
907 * config/tc-nios2.c (nios2_parse_args): Allow trap argument to
908 omitted.
909
d301a56b
RS		 9102013-06-08 Catherine Moore <clm@codesourcery.com>
911
912 * config/tc-mips.c (is_opcode_valid): Build ASE mask.
913 (is_opcode_valid_16): Pass ase value to opcode_is_member.
914 (append_insn): Change INSN_xxxx to ASE_xxxx.
915
7bab7634
DC		 9162013-06-01 George Thomas <george.thomas@atmel.com>
917
cbe02d4f 918 * gas/config/tc-avr.c: Change ISA for devices with USB support to
7bab7634
DC		 919 AVR_ISA_XMEGAU
920
f60cf82f
L		 9212013-05-31 H.J. Lu <hongjiu.lu@intel.com>
922
923 * config/tc-i386.c (md_begin): Don't align text/data/bss sections
924 for ELF.
925
a3f278e2
CM		 9262013-05-31 Paul Brook <paul@codesourcery.com>
927
a3f278e2
CM		 928 * config/tc-mips.c (s_ehword): New.
929
067ec077
CM		 9302013-05-30 Paul Brook <paul@codesourcery.com>
931
932 * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
933
d6101ac2
MR		 9342013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
935
936 * write.c (resolve_reloc_expr_symbols): On REL targets don't
937 convert relocs who have no relocatable field either. Rephrase
938 the conditional so that the PC-relative check is only applied
939 for REL targets.
940
f19ccbda
MR		 9412013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
942
943 * config/tc-mips.c (macro) <ld>: Don't use $zero for address
944 calculation.
945
418009c2
YZ		 9462013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
947
948 * config/tc-aarch64.c (reloc_table): Update to use
477330fc 949 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
418009c2
YZ		 950 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
951 (md_apply_fix): Likewise.
952 (aarch64_force_relocation): Likewise.
953
0a8897c7
KT		 9542013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
955
956 * config/tc-arm.c (it_fsm_post_encode): Improve
957 warning messages about deprecated IT block formats.
958
89d2a2a3
MS		 9592013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
960
961 * config/tc-aarch64.c (md_apply_fix): Move value range checking
962 inside fx_done condition.
963
c77c0862
RS		 9642013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
965
966 * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
967
c0637f3a
PB		 9682013-05-20 Peter Bergner <bergner@vnet.ibm.com>
969
970 * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
971 and clean up warning when using PRINT_OPCODE_TABLE.
972
5656a981
AM		 9732013-05-20 Alan Modra <amodra@gmail.com>
974
975 * config/tc-ppc.c (md_apply_fix): Hoist code common to insn
976 and data fixups performing shift/high adjust/sign extension on
977 fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
978 when writing data fixups rather than recalculating size.
979
997b26e8
JBG		 9802013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
981
982 * doc/c-msp430.texi: Fix typo.
983
9f6e76f4
TG		 9842013-05-16 Tristan Gingold <gingold@adacore.com>
985
986 * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
987 are also TOC symbols.
988
638d3803
NC		 9892013-05-16 Nick Clifton <nickc@redhat.com>
990
991 * config/tc-msp430.c: Make -mmcu recognise more part numbers.
992 Add -mcpu command to specify core type.
997b26e8 993 * doc/c-msp430.texi: Update documentation.
638d3803 994
b015e599
AP		 9952013-05-09 Andrew Pinski <apinski@cavium.com>
996
997 * config/tc-mips.c (struct mips_set_options): New ase_virt field.
998 (mips_opts): Update for the new field.
999 (file_ase_virt): New variable.
1000 (ISA_SUPPORTS_VIRT_ASE): New macro.
1001 (ISA_SUPPORTS_VIRT64_ASE): New macro.
1002 (MIPS_CPU_ASE_VIRT): New define.
1003 (is_opcode_valid): Handle ase_virt.
1004 (macro_build): Handle "+J".
1005 (validate_mips_insn): Likewise.
1006 (mips_ip): Likewise.
1007 (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
1008 (md_longopts): Add mvirt and mnovirt
1009 (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
1010 (mips_after_parse_args): Handle ase_virt field.
1011 (s_mipsset): Handle "virt" and "novirt".
1012 (mips_elf_final_processing): Add a comment about virt ASE might need
1013 a new flag.
1014 (md_show_usage): Print out the usage of -mvirt and mno-virt options.
1015 * doc/c-mips.texi: Document -mvirt and -mno-virt.
1016 Document ".set virt" and ".set novirt".
1017
da8094d7
AM		 10182013-05-09 Alan Modra <amodra@gmail.com>
1019
1020 * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
1021 control of operand flag bits.
1022
c5f8c205
AM		 10232013-05-07 Alan Modra <amodra@gmail.com>
1024
1025 * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
1026 (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
1027 (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
1028 (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
1029 (md_apply_fix): Set fx_no_overflow for assorted relocations.
1030 Shift and sign-extend fieldval for use by some VLE reloc
1031 operand->insert functions.
1032
b47468a6
CM		 10332013-05-06 Paul Brook <paul@codesourcery.com>
1034 Catherine Moore <clm@codesourcery.com>
1035
c5f8c205
AM		 1036 * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
1037 (limited_pcrel_reloc_p): Likewise.
b47468a6
CM		 1038 (md_apply_fix): Likewise.
1039 (tc_gen_reloc): Likewise.
1040
2de39019
CM		 10412013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
1042
1043 * config/tc-mips.c (limited_pcrel_reloc_p): New function.
1044 (mips_fix_adjustable): Adjust pc-relative check to use
1045 limited_pc_reloc_p.
1046
754e2bb9
RS		 10472013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
1048
1049 * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
1050 (s_mips_stab): Do not restrict to stabn only.
1051
13761a11
NC		 10522013-05-02 Nick Clifton <nickc@redhat.com>
1053
1054 * config/tc-msp430.c: Add support for the MSP430X architecture.
1055 Add code to insert a NOP instruction after any instruction that
1056 might change the interrupt state.
1057 Add support for the LARGE memory model.
1058 Add code to initialise the .MSP430.attributes section.
1059 * config/tc-msp430.h: Add support for the MSP430X architecture.
1060 * doc/c-msp430.texi: Document the new -mL and -mN command line
1061 options.
1062 * NEWS: Mention support for the MSP430X architecture.
1063
df26367c
MR		 10642013-05-01 Maciej W. Rozycki <macro@codesourcery.com>
1065
1066 * configure.tgt: Replace alpha*-*-linuxecoff* pattern with
1067 alpha*-*-linux*ecoff*.
1068
f02d8318
CF		 10692013-04-30 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
1070
1071 * config/tc-mips.c (mips_ip): Add sizelo.
1072 For "+C", "+G", and "+H", set sizelo and compare against it.
1073
b40bf0a2
NC		 10742013-04-29 Nick Clifton <nickc@redhat.com>
1075
1076 * as.c (Options): Add -gdwarf-sections.
1077 (parse_args): Likewise.
1078 * as.h (flag_dwarf_sections): Declare.
1079 * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes.
1080 (process_entries): When -gdwarf-sections is enabled generate
1081 fragmentary .debug_line sections.
1082 (out_debug_line): Set the section for the .debug_line section end
1083 symbol.
1084 * doc/as.texinfo: Document -gdwarf-sections.
1085 * NEWS: Mention -gdwarf-sections.
1086
8eeccb77 10872013-04-26 Christian Groessler <chris@groessler.org>
00a3147e
CG		 1088
1089 * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline
1090 according to the target parameter. Don't call s_segm since s_segm
1091 calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
1092 initialized yet.
1093 (md_begin): Call s_segm according to target parameter from command
1094 line.
1095
49926cd0
AM		 10962013-04-25 Alan Modra <amodra@gmail.com>
1097
1098 * configure.in: Allow little-endian linux.
1099 * configure: Regenerate.
1100
e3031850
SL		 11012013-04-24 Sandra Loosemore <sandra@codesourcery.com>
1102
1103 * config/tc-nios2.c (nios2_control_register_arg_p): Rename
1104 "fstatus" control register to "eccinj".
1105
cb948fc0
KT		 11062013-04-19 Kai Tietz <ktietz@redhat.com>
1107
1108 * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin.
1109
4455e9ad
JB		 11102013-04-15 Julian Brown <julian@codesourcery.com>
1111
1112 * expr.c (add_to_result, subtract_from_result): Make global.
1113 * expr.h (add_to_result, subtract_from_result): Add prototypes.
1114 * config/tc-sh.c (sh_optimize_expr): Use add_to_result,
1115 subtract_from_result to handle extra bit of precision for .sleb128
1116 directive operands.
1117
956a6ba3
JB		 11182013-04-10 Julian Brown <julian@codesourcery.com>
1119
1120 * read.c (convert_to_bignum): Add sign parameter. Use it
1121 instead of X_unsigned to determine sign of resulting bignum.
1122 (emit_expr): Pass extra argument to convert_to_bignum.
1123 (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass
1124 X_extrabit to convert_to_bignum.
1125 (parse_bitfield_cons): Set X_extrabit.
1126 * expr.c (make_expr_symbol, expr_build_uconstant, operand):
1127 Initialise X_extrabit field as appropriate.
1128 (add_to_result): New.
1129 (subtract_from_result): New.
1130 (expr): Use above.
1131 * expr.h (expressionS): Add X_extrabit field.
1132
eb9f3f00
JB		 11332013-04-10 Jan Beulich <jbeulich@suse.com>
1134
1135 * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
1136 register being PC when is_t or writeback, and use distinct
1137 diagnostic for the latter case.
1138
ccb84d65
JB		 11392013-04-10 Jan Beulich <jbeulich@suse.com>
1140
1141 * gas/config/tc-arm.c (parse_operands): Re-write
1142 po_barrier_or_imm().
1143 (do_barrier): Remove bogus constraint().
1144 (do_t_barrier): Remove.
1145
4d13caa0
NC		 11462013-04-09 Joerg Wunsch <joerg.wunsch@atmel.com>
1147
1148 * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2,
1149 ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2,
1150 ATmega2564RFR2
1151 * gas/doc/c-avr.texi (-mmcu documentation): Likewise.
1152
16d02dc9
JB		 11532013-04-09 Jan Beulich <jbeulich@suse.com>
1154
1155 * gas/config/tc-arm.c (do_vmrs): Accept all control registers.
1156 Use local variable Rt in more places.
1157 (do_vmsr): Accept all control registers.
1158
05ac0ffb
JB		 11592013-04-09 Jan Beulich <jbeulich@suse.com>
1160
1161 * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
1162 if there was none specified for moves between scalar and core
1163 register.
1164
2d51fb74
JB		 11652013-04-09 Jan Beulich <jbeulich@suse.com>
1166
1167 * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
1168 NEON_ALL_LANES case.
1169
94dcf8bf
JB		 11702013-04-08 Jan Beulich <jbeulich@suse.com>
1171
1172 * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for
1173 PC-relative VSTR.
1174
1472d06f
JB		 11752013-04-08 Jan Beulich <jbeulich@suse.com>
1176
1177 * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq
1178 entry to sp_fiq.
1179
0c76cae8
AM		 11802013-04-03 Alan Modra <amodra@gmail.com>
1181
1182 * doc/as.texinfo: Add support to generate man options for h8300.
1183 * doc/c-h8300.texi: Likewise.
1184
92eb40d9
RR		 11852013-03-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1186
1187 * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and
1188 Cortex-A57.
1189
51dcdd4d
NC		 11902013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1191
1192 PR binutils/15068
1193 * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
1194
c5d685bf
NC		 11952013-03-26 Nick Clifton <nickc@redhat.com>
1196
9b978282
NC		 1197 PR gas/15295
1198 * listing.c (rebuffer_line): Rewrite to avoid seeking back to the
1199 start of the file each time.
1200
c5d685bf
NC		 1201 PR gas/15178
1202 * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for
1203 FreeBSD targets.
1204
9699c833
TG		 12052013-03-26 Douglas B Rupp <rupp@gnat.com>
1206
1207 * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
1208 after fixup.
1209
4755303e
WN		 12102013-03-21 Will Newton <will.newton@linaro.org>
1211
1212 * config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
1213 pc-relative str instructions in Thumb mode.
1214
81f5558e
NC		 12152013-03-21 Michael Schewe <michael.schewe@gmx.net>
1216
1217 * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
1218 @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
1219 R_H8_DISP32A16.
1220 * config/tc-h8300.h: Remove duplicated defines.
1221
71863e73
NC		 12222013-03-21 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
1223
1224 PR gas/15282
1225 * tc-avr.c (mcu_has_3_byte_pc): New function.
1226 (tc_cfi_frame_initial_instructions): Call it to find return
1227 address size.
1228
795b8e6b
NC		 12292013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1230
1231 PR gas/15095
1232 * config/tc-tic6x.c (tic6x_try_encode): Handle
1233 tic6x_coding_dreg_(msb|lsb) field coding types and use it to
1234 encode register pair numbers when required.
1235
ba86b375
WN		 12362013-03-15 Will Newton <will.newton@linaro.org>
1237
1238 * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
1239 in vstr in Thumb mode for pre-ARMv7 cores.
1240
9e6f3811
AS		 12412013-03-14 Andreas Schwab <schwab@suse.de>
1242
1243 * doc/c-arc.texi (ARC Directives): Revert last change and use
1244 @itemize instead of @table.
1245 * doc/c-arm.texi (ARM-Instruction-Set): Likewise.
1246
b10bf8c5
NC		 12472013-03-14 Nick Clifton <nickc@redhat.com>
1248
1249 PR gas/15273
1250 * config/tc-arm.c (do_co_reg): Do not call check_obsolete with a
1251 NULL message, instead just check ARM_CPU_IS_ANY directly.
1252
ba724cfc
NC		 12532013-03-14 Nick Clifton <nickc@redhat.com>
1254
1255 PR gas/15212
9e6f3811 1256 * doc/c-arc.texi (ARC Directives): Use @code instead of @bullet
ba724cfc
NC		 1257 for table format.
1258 * doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text
1259 to the @item directives.
1260 (ARM-Neon-Alignment): Move to correct place in the document.
1261 * doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table
1262 formatting.
1263 * doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of
1264 @smallexample.
1265
531a94fd
SL		 12662013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>
1267
1268 * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o'
1269 case. Add default BAD_CASE to switch.
1270
dad60f8e
SL		 12712013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1272
1273 * config/tc-nios2.c (nios2_assemble_args_ds): New function.
1274 (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries.
1275
dd5181d5
KT		 12762013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1277
1278 * config/tc-arm.c (crc_ext_armv8): New feature set.
1279 (UNPRED_REG): New macro.
1280 (do_crc32_1): New function.
1281 (do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
1282 do_crc32ch, do_crc32cw): Likewise.
1283 (TUEc): New macro.
1284 (insns): Add entries for crc32 mnemonics.
1285 (arm_extensions): Add entry for crc.
1286
8e723a10
CLT		 12872013-03-08 Chung-Lin Tang <cltang@codesourcery.com>
1288
1289 * write.h (struct fix): Add fx_dot_frag field.
1290 (dot_frag): Declare.
1291 * write.c (dot_frag): New variable.
1292 (fix_new_internal): Set fx_dot_frag field with dot_frag.
1293 (fixup_segment): Base calculation of fx_offset with fx_dot_frag.
1294 * expr.c (expr): Save value of frag_now in dot_frag when setting
1295 dot_value.
1296 * read.c (emit_expr): Likewise. Delete comments.
1297
be05d201
L		 12982013-03-07 H.J. Lu <hongjiu.lu@intel.com>
1299
1300 * config/tc-i386.c (flag_code_names): Removed.
1301 (i386_index_check): Rewrote.
1302
62b0d0d5
YZ		 13032013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
1304
1305 * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
1306 add comment.
1307 (aarch64_double_precision_fmovable): New function.
1308 (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
1309 function; handle hexadecimal representation of IEEE754 encoding.
1310 (parse_operands): Update the call to parse_aarch64_imm_float.
1311
165de32a
L		 13122013-02-28 H.J. Lu <hongjiu.lu@intel.com>
1313
1314 * config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix.
1315 (check_hle): Updated.
1316 (md_assemble): Likewise.
1317 (parse_insn): Likewise.
1318
d5de92cf
L		 13192013-02-28 H.J. Lu <hongjiu.lu@intel.com>
1320
1321 * config/tc-i386.c (_i386_insn): Add rep_prefix.
9e6f3811 1322 (md_assemble): Check if REP prefix is OK.
d5de92cf
L		 1323 (parse_insn): Remove expecting_string_instruction. Set
1324 i.rep_prefix.
1325
e60bb1dd
YZ		 13262013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1327
1328 * config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
1329
aeebdd9b
YZ		 13302013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1331
1332 * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
1333 for system registers.
1334
4107ae22
DD		 13352013-02-27 DJ Delorie <dj@redhat.com>
1336
1337 * config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE.
1338 (rl78_op): Handle %code().
1339 (rl78_cons_fix_new): Likewise, but ignore for 20-bit operands.
1340 (tc_gen_reloc): Likwise; convert to a computed reloc.
1341 (md_apply_fix): Likewise.
1342
151fa98f
NC		 13432013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1344
1345 * config/rl78-parse.y: Fix encoding of DIVWU insn.
1346
70a8bc5b 13472013-02-25 Terry Guo <terry.guo@arm.com>
1348
1349 * config/tc-arm.c (arm_cpus): Add cortex-r7 entry.
1350 * doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to
1351 list of accepted CPUs.
1352
5c111e37
L		 13532013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1354
1355 PR gas/15159
1356 * config/tc-i386.c (cpu_arch): Add ".smap".
1357
1358 * doc/c-i386.texi: Document smap.
1359
8a75745d
MR		 13602013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
1361
1362 * config/tc-mips.c (s_cpload): Call mips_mark_labels and set
1363 mips_assembling_insn appropriately.
1364 (s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise.
1365
79850f26
MR		 13662013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
1367
cf29fc61 1368 * config/tc-mips.c (append_insn): Correct indentation, remove
79850f26
MR		 1369 extraneous braces.
1370
4c261dff
NC		 13712013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1372
5c111e37 1373 * config/tc-arm.c (do_neon_mov): Break on NS_NULL.
4c261dff 1374
ea33f281
NC		 13752013-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
1376
1377 * configure.tgt: Add nios2-*-rtems*.
1378
a1ccaec9
YZ		 13792013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1380
1381 * config/tc-aarch64.c (md_begin): Change to check if 'name' is
1382 NULL.
1383
0aa27725
RS		 13842013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1385
1386 * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
1387 (macro): Use it. Assert that trunc.w.s is not used for r5900.
1388
da4339ed
NC		 13892013-02-08 Yi-Hsiu, Hsu <ahsu@marvell.com>
1390
1391 * gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4
1392 core.
1393
36591ba1 13942013-02-06 Sandra Loosemore <sandra@codesourcery.com>
5c111e37 1395 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 1396
1397 Based on patches from Altera Corporation.
1398
1399 * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c.
1400 (TARGET_CPU_HFILES): Add config/tc-nios2.h.
1401 * Makefile.in: Regenerated.
1402 * configure.tgt: Add case for nios2*-linux*.
1403 * config/obj-elf.c: Conditionally include elf/nios2.h.
1404 * config/tc-nios2.c: New file.
1405 * config/tc-nios2.h: New file.
1406 * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi.
1407 * doc/Makefile.in: Regenerated.
1408 * doc/all.texi: Set NIOSII.
1409 * doc/as.texinfo (Overview): Add Nios II options.
1410 (Machine Dependencies): Include c-nios2.texi.
1411 * doc/c-nios2.texi: New file.
1412 * NEWS: Note Altera Nios II support.
1413
94d4433a
AM		 14142013-02-06 Alan Modra <amodra@gmail.com>
1415
1416 PR gas/14255
1417 * config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc.
1418 Don't skip fixups with fx_subsy non-NULL.
1419 * config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups
1420 with fx_subsy non-NULL.
1421
ace9af6f
L		 14222013-02-04 H.J. Lu <hongjiu.lu@intel.com>
1423
1424 * doc/c-metag.texi: Add "@c man" markers.
1425
89d67ed9
AM		 14262013-02-04 Alan Modra <amodra@gmail.com>
1427
1428 * write.c (fixup_segment): Return void. Delete seg_reloc_count
1429 related code.
1430 (TC_ADJUST_RELOC_COUNT): Delete.
1431 * config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete.
1432
89072bd6
AM		 14332013-02-04 Alan Modra <amodra@gmail.com>
1434
1435 * po/POTFILES.in: Regenerate.
1436
f9b2d544
NC		 14372013-01-30 Markos Chandras <markos.chandras@imgtec.com>
1438
1439 * config/tc-metag.c: Make SWAP instruction less permissive with
1440 its operands.
1441
392ca752
DD		 14422013-01-29 DJ Delorie <dj@redhat.com>
1443
1444 * config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified
1445 relocs in .word/.etc statements.
1446
427d0db6
RM		 14472013-01-29 Roland McGrath <mcgrathr@google.com>
1448
1449 * config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad
1450 immediate value for 8-bit offset" error so it shows line info.
1451
4faf939a
JM		 14522013-01-24 Joseph Myers <joseph@codesourcery.com>
1453
1454 * config/tc-ppc.c (md_assemble): Do not generate APUinfo sections
1455 for 64-bit output.
1456
78c8d46c
NC		 14572013-01-24 Nick Clifton <nickc@redhat.com>
1458
1459 * config/tc-v850.c: Add support for e3v5 architecture.
1460 * doc/c-v850.texi: Mention new support.
1461
fb5b7503
NC		 14622013-01-23 Nick Clifton <nickc@redhat.com>
1463
1464 PR gas/15039
1465 * config/tc-avr.c: Include dwarf2dbg.h.
1466
8ce3d284
L		 14672013-01-18 H.J. Lu <hongjiu.lu@intel.com>
1468
1469 * config/tc-i386.c (reloc): Support size relocation only for ELF.
1470 (tc_i386_fix_adjustable): Likewise.
1471 (lex_got): Likewise.
1472 (tc_gen_reloc): Likewise.
1473
f5555712
YZ		 14742013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1475
1476 * config/tc-aarch64.c (output_operand_error_record): Change to output
1477 the out-of-range error message as value-expected message if there is
1478 only one single value in the expected range.
1479 (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
1480 LSL #0 as a programmer-friendly feature.
1481
8fd4256d
L		 14822013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1483
1484 * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32.
1485 (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and
1486 BFD_RELOC_64_SIZE relocations.
1487 (lex_got): Support "symbol@SIZE" and don't create GOT symbol
1488 for it.
1489 (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64
1490 relocations against local symbols.
1491
a5840dce
AM		 14922013-01-16 Alan Modra <amodra@gmail.com>
1493
1494 * config/tc-ppc.c (md_assemble <TE_PE>): Ignore line after
1495 finding some sort of toc syntax error, and break to avoid
1496 compiler uninit warning.
1497
af89796a
L		 14982013-01-15 H.J. Lu <hongjiu.lu@intel.com>
1499
1500 PR gas/15019
1501 * config/tc-i386.c (lex_got): Increment length by 1 if the
1502 relocation token is removed.
1503
dd42f060
NC		 15042013-01-15 Nick Clifton <nickc@redhat.com>
1505
1506 * config/tc-v850.c (md_assemble): Allow signed values for
1507 V850E_IMMEDIATE.
1508
464e3686
SK		 15092013-01-11 Sean Keys <skeys@ipdatasys.com>
1510
1511 * config/tc-xgate.c (md_begin): Fix mistake made when going from
af89796a 1512 git to cvs.
464e3686 1513
5817ffd1
PB		 15142013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1515
1516 * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
1517 * doc/c-ppc.texi (PowerPC-Opts): Likewise.
1518 * config/tc-ppc.c (md_show_usage): Likewise.
1519 (ppc_handle_align): Handle power8's group ending nop.
1520
f4b1f6a9
SK		 15212013-01-10 Sean Keys <skeys@ipdatasys.com>
1522
1523 * config/tc-xgate.c (md_begin): Fix the printing of opcodes so
af89796a 1524 that the assember exits after the opcodes have been printed.
f4b1f6a9 1525
34bca508
L		 15262013-01-10 H.J. Lu <hongjiu.lu@intel.com>
1527
1528 * app.c: Remove trailing white spaces.
1529 * as.c: Likewise.
1530 * as.h: Likewise.
1531 * cond.c: Likewise.
1532 * dw2gencfi.c: Likewise.
1533 * dwarf2dbg.h: Likewise.
1534 * ecoff.c: Likewise.
1535 * input-file.c: Likewise.
1536 * itbl-lex.h: Likewise.
1537 * output-file.c: Likewise.
1538 * read.c: Likewise.
1539 * sb.c: Likewise.
1540 * subsegs.c: Likewise.
1541 * symbols.c: Likewise.
1542 * write.c: Likewise.
1543 * config/tc-i386.c: Likewise.
1544 * doc/Makefile.am: Likewise.
1545 * doc/Makefile.in: Likewise.
1546 * doc/c-aarch64.texi: Likewise.
1547 * doc/c-alpha.texi: Likewise.
1548 * doc/c-arc.texi: Likewise.
1549 * doc/c-arm.texi: Likewise.
1550 * doc/c-avr.texi: Likewise.
1551 * doc/c-bfin.texi: Likewise.
1552 * doc/c-cr16.texi: Likewise.
1553 * doc/c-d10v.texi: Likewise.
1554 * doc/c-d30v.texi: Likewise.
1555 * doc/c-h8300.texi: Likewise.
1556 * doc/c-hppa.texi: Likewise.
1557 * doc/c-i370.texi: Likewise.
1558 * doc/c-i386.texi: Likewise.
1559 * doc/c-i860.texi: Likewise.
1560 * doc/c-m32c.texi: Likewise.
1561 * doc/c-m32r.texi: Likewise.
1562 * doc/c-m68hc11.texi: Likewise.
1563 * doc/c-m68k.texi: Likewise.
1564 * doc/c-microblaze.texi: Likewise.
1565 * doc/c-mips.texi: Likewise.
1566 * doc/c-msp430.texi: Likewise.
1567 * doc/c-mt.texi: Likewise.
1568 * doc/c-s390.texi: Likewise.
1569 * doc/c-score.texi: Likewise.
1570 * doc/c-sh.texi: Likewise.
1571 * doc/c-sh64.texi: Likewise.
1572 * doc/c-tic54x.texi: Likewise.
1573 * doc/c-tic6x.texi: Likewise.
1574 * doc/c-v850.texi: Likewise.
1575 * doc/c-xc16x.texi: Likewise.
1576 * doc/c-xgate.texi: Likewise.
1577 * doc/c-xtensa.texi: Likewise.
1578 * doc/c-z80.texi: Likewise.
1579 * doc/internals.texi: Likewise.
1580
4c665b71
RM		 15812013-01-10 Roland McGrath <mcgrathr@google.com>
1582
1583 * hash.c (hash_new_sized): Make it global.
1584 * hash.h: Declare it.
1585 * macro.c (define_macro): Use hash_new_sized instead of hash_new,
1586 pass a small size.
1587
a3c62988
NC		 15882013-01-10 Will Newton <will.newton@imgtec.com>
1589
1590 * Makefile.am: Add Meta.
1591 * Makefile.in: Regenerate.
1592 * config/tc-metag.c: New file.
1593 * config/tc-metag.h: New file.
1594 * configure.tgt: Add Meta.
1595 * doc/Makefile.am: Add Meta.
1596 * doc/Makefile.in: Regenerate.
1597 * doc/all.texi: Add Meta.
1598 * doc/as.texiinfo: Document Meta options.
1599 * doc/c-metag.texi: New file.
1600
b37df7c4
SE		 16012013-01-09 Steve Ellcey <sellcey@mips.com>
1602
1603 * config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal
1604 calls.
1605 * config/tc-mips.c (internalError): Remove, replace with abort.
1606
a3251895
YZ		 16072013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
1608
1609 * config/tc-aarch64.c (parse_operands): Change to compare the result
1610 of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'.
1611
8ab8155f
NC		 16122013-01-07 Nick Clifton <nickc@redhat.com>
1613
1614 PR gas/14887
1615 * config/tc-arm.c (skip_past_char): Skip whitespace before the
1616 anticipated character.
1617 * config/tc-arm.c (parse_address_main): Delete skip of whitespace
1618 here as it is no longer needed.
1619
a4ac1c42
AS		 16202013-01-06 Andreas Schwab <schwab@linux-m68k.org>
1621
1622 * doc/c-mips.texi (MIPS Opts): Fix use of @itemx.
1623 * doc/c-score.texi (SCORE-Opts): Likewise.
1624 * doc/c-tic54x.texi (TIC54X-Directives): Likewise.
1625
e407c74b
NC		 16262013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1627
1628 * config/tc-mips.c: Add support for MIPS r5900.
1629 Add M_LQ_AB and M_SQ_AB to support large values for instructions
1630 lq and sq.
1631 (can_swap_branch_p, get_append_method): Detect some conditional
1632 short loops to fix a bug on the r5900 by NOP in the branch delay
1633 slot.
1634 (M_MUL): Support 3 operands in multu on r5900.
1635 (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
1636 (s_mipsset): Force 32 bit floating point on r5900.
1637 (mips_ip): Check parameter range of instructions mfps and mtps on
1638 r5900.
1639 * configure.in: Detect CPU type when target string contains r5900
1640 (e.g. mips64r5900el-linux-gnu).
1641
62658407
L		 16422013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1643
1644 * as.c (parse_args): Update copyright year to 2013.
1645
95830fd1
YZ		 16462013-01-02 Yufeng Zhang <yufeng.zhang@arm.com>
1647
1648 * config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53"
1649 and "cortex57".
1650
517bb291 16512013-01-02 Nick Clifton <nickc@redhat.com>
d709e4e6 1652
517bb291
NC		 1653 PR gas/14987
1654 * config/tc-arm.c (parse_address_main): Skip whitespace before a
1655 closing bracket.
d709e4e6 1656
517bb291 1657For older changes see ChangeLog-2012
08d56133 1658\f
517bb291 1659Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1660
1661Copying and distribution of this file, with or without modification,
1662are permitted in any medium without royalty provided the copyright
1663notice and this notice are preserved.
1664
08d56133
NC		 1665Local Variables:
1666mode: change-log
1667left-margin: 8
1668fill-column: 74
1669version-control: never
1670End:
GDB Binutils - Deliverables
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