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d43b4baf
TS		 12006-05-05 Thiemo Seufer <ths@mips.com>
2 David Ung <davidu@mips.com>
3
4 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
5 instruction.
6 (macro): Add new case M_CACHE_AB.
7
088fa78e
KH		 82006-05-04 Kazu Hirata <kazu@codesourcery.com>
9
10 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
11 (opcode_lookup): Issue a warning for opcode with
12 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
13 identical to OT_cinfix3.
14 (TxC3w, TC3w, tC3w): New.
15 (insns): Use tC3w and TC3w for comparison instructions with
16 's' suffix.
17
c9049d30
AM		 182006-05-04 Alan Modra <amodra@bigpond.net.au>
19
20 * subsegs.h (struct frchain): Delete frch_seg.
21 (frchain_root): Delete.
22 (seg_info): Define as macro.
23 * subsegs.c (frchain_root): Delete.
24 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
25 (subsegs_begin, subseg_change): Adjust for above.
26 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
27 rather than to one big list.
28 (subseg_get): Don't special case abs, und sections.
29 (subseg_new, subseg_force_new): Don't set frchainP here.
30 (seg_info): Delete.
31 (subsegs_print_statistics): Adjust frag chain control list traversal.
32 * debug.c (dmp_frags): Likewise.
33 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
34 at frchain_root. Make use of known frchain ordering.
35 (last_frag_for_seg): Likewise.
36 (get_frag_fix): Likewise. Add seg param.
37 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
38 * write.c (chain_frchains_together_1): Adjust for struct frchain.
39 (SUB_SEGMENT_ALIGN): Likewise.
40 (subsegs_finish): Adjust frchain list traversal.
41 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
42 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
43 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
44 (xtensa_fix_b_j_loop_end_frags): Likewise.
45 (xtensa_fix_close_loop_end_frags): Likewise.
46 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
47 (retrieve_segment_info): Delete frch_seg initialisation.
48
f592407e
AM		 492006-05-03 Alan Modra <amodra@bigpond.net.au>
50
51 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
52 * config/obj-elf.h (obj_sec_set_private_data): Delete.
53 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
54 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
55
df7849c5
JM		 562006-05-02 Joseph Myers <joseph@codesourcery.com>
57
58 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
59 here.
60 (md_apply_fix3): Multiply offset by 4 here for
61 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
62
2d545b82
L		 632006-05-02 H.J. Lu <hongjiu.lu@intel.com>
64 Jan Beulich <jbeulich@novell.com>
65
66 * config/tc-i386.c (output_invalid_buf): Change size for
67 unsigned char.
68 * config/tc-tic30.c (output_invalid_buf): Likewise.
69
70 * config/tc-i386.c (output_invalid): Cast none-ascii char to
71 unsigned char.
72 * config/tc-tic30.c (output_invalid): Likewise.
73
38fc1cb1
DJ		 742006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
75
76 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
77 (TEXI2POD): Use AM_MAKEINFOFLAGS.
78 (asconfig.texi): Don't set top_srcdir.
79 * doc/as.texinfo: Don't use top_srcdir.
80 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
81
2d545b82
L		 822006-05-02 H.J. Lu <hongjiu.lu@intel.com>
83
84 * config/tc-i386.c (output_invalid_buf): Change size to 16.
85 * config/tc-tic30.c (output_invalid_buf): Likewise.
86
87 * config/tc-i386.c (output_invalid): Use snprintf instead of
88 sprintf.
89 * config/tc-ia64.c (declare_register_set): Likewise.
90 (emit_one_bundle): Likewise.
91 (check_dependencies): Likewise.
92 * config/tc-tic30.c (output_invalid): Likewise.
93
a8bc6c78
PB		 942006-05-02 Paul Brook <paul@codesourcery.com>
95
96 * config/tc-arm.c (arm_optimize_expr): New function.
97 * config/tc-arm.h (md_optimize_expr): Define
98 (arm_optimize_expr): Add prototype.
99 (TC_FORCE_RELOCATION_SUB_SAME): Define.
100
58633d9a
BE		 1012006-05-02 Ben Elliston <bje@au.ibm.com>
102
22772e33
BE		 103 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
104 field unsigned.
105
58633d9a
BE		 106 * sb.h (sb_list_vector): Move to sb.c.
107 * sb.c (free_list): Use type of sb_list_vector directly.
108 (sb_build): Fix off-by-one error in assertion about `size'.
109
89cdfe57
BE		 1102006-05-01 Ben Elliston <bje@au.ibm.com>
111
112 * listing.c (listing_listing): Remove useless loop.
113 * macro.c (macro_expand): Remove is_positional local variable.
114 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
115 and simplify surrounding expressions, where possible.
116 (assign_symbol): Likewise.
117 (s_weakref): Likewise.
118 * symbols.c (colon): Likewise.
119
c35da140
AM		 1202006-05-01 James Lemke <jwlemke@wasabisystems.com>
121
122 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
123
9bcd4f99
TS		 1242006-04-30 Thiemo Seufer <ths@mips.com>
125 David Ung <davidu@mips.com>
126
127 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
128 (mips_immed): New table that records various handling of udi
129 instruction patterns.
130 (mips_ip): Adds udi handling.
131
001ae1a4
AM		 1322006-04-28 Alan Modra <amodra@bigpond.net.au>
133
134 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
135 of list rather than beginning.
136
136da414
JB		 1372006-04-26 Julian Brown <julian@codesourcery.com>
138
139 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
140 (is_quarter_float): Rename from above. Simplify slightly.
141 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
142 number.
143 (parse_neon_mov): Parse floating-point constants.
144 (neon_qfloat_bits): Fix encoding.
145 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
146 preference to integer encoding when using the F32 type.
147
dcbf9037
JB		 1482006-04-26 Julian Brown <julian@codesourcery.com>
149
150 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
151 zero-initialising structures containing it will lead to invalid types).
152 (arm_it): Add vectype to each operand.
153 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
154 defined field.
155 (neon_typed_alias): New structure. Extra information for typed
156 register aliases.
157 (reg_entry): Add neon type info field.
158 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
159 Break out alternative syntax for coprocessor registers, etc. into...
160 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
161 out from arm_reg_parse.
162 (parse_neon_type): Move. Return SUCCESS/FAIL.
163 (first_error): New function. Call to ensure first error which occurs is
164 reported.
165 (parse_neon_operand_type): Parse exactly one type.
166 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
167 (parse_typed_reg_or_scalar): New function. Handle core of both
168 arm_typed_reg_parse and parse_scalar.
169 (arm_typed_reg_parse): Parse a register with an optional type.
170 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
171 result.
172 (parse_scalar): Parse a Neon scalar with optional type.
173 (parse_reg_list): Use first_error.
174 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
175 (neon_alias_types_same): New function. Return true if two (alias) types
176 are the same.
177 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
178 of elements.
179 (insert_reg_alias): Return new reg_entry not void.
180 (insert_neon_reg_alias): New function. Insert type/index information as
181 well as register for alias.
182 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
183 make typed register aliases accordingly.
184 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
185 of line.
186 (s_unreq): Delete type information if present.
187 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
188 (s_arm_unwind_save_mmxwcg): Likewise.
189 (s_arm_unwind_movsp): Likewise.
190 (s_arm_unwind_setfp): Likewise.
191 (parse_shift): Likewise.
192 (parse_shifter_operand): Likewise.
193 (parse_address): Likewise.
194 (parse_tb): Likewise.
195 (tc_arm_regname_to_dw2regnum): Likewise.
196 (md_pseudo_table): Add dn, qn.
197 (parse_neon_mov): Handle typed operands.
198 (parse_operands): Likewise.
199 (neon_type_mask): Add N_SIZ.
200 (N_ALLMODS): New macro.
201 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
202 (el_type_of_type_chk): Add some safeguards.
203 (modify_types_allowed): Fix logic bug.
204 (neon_check_type): Handle operands with types.
205 (neon_three_same): Remove redundant optional arg handling.
206 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
207 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
208 (do_neon_step): Adjust accordingly.
209 (neon_cmode_for_logic_imm): Use first_error.
210 (do_neon_bitfield): Call neon_check_type.
211 (neon_dyadic): Rename to...
212 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
213 to allow modification of type of the destination.
214 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
215 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
216 (do_neon_compare): Make destination be an untyped bitfield.
217 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
218 (neon_mul_mac): Return early in case of errors.
219 (neon_move_immediate): Use first_error.
220 (neon_mac_reg_scalar_long): Fix type to include scalar.
221 (do_neon_dup): Likewise.
222 (do_neon_mov): Likewise (in several places).
223 (do_neon_tbl_tbx): Fix type.
224 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
225 (do_neon_ld_dup): Exit early in case of errors and/or use
226 first_error.
227 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
228 Handle .dn/.qn directives.
229 (REGDEF): Add zero for reg_entry neon field.
230
5287ad62
JB		 2312006-04-26 Julian Brown <julian@codesourcery.com>
232
233 * config/tc-arm.c (limits.h): Include.
234 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
235 (fpu_vfp_v3_or_neon_ext): Declare constants.
236 (neon_el_type): New enumeration of types for Neon vector elements.
237 (neon_type_el): New struct. Define type and size of a vector element.
238 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
239 instruction.
240 (neon_type): Define struct. The type of an instruction.
241 (arm_it): Add 'vectype' for the current instruction.
242 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
243 (vfp_sp_reg_pos): Rename to...
244 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
245 tags.
246 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
247 (Neon D or Q register).
248 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
249 register.
250 (GE_OPT_PREFIX_BIG): Define constant, for use in...
251 (my_get_expression): Allow above constant as argument to accept
252 64-bit constants with optional prefix.
253 (arm_reg_parse): Add extra argument to return the specific type of
254 register in when either a D or Q register (REG_TYPE_NDQ) is
255 requested. Can be NULL.
256 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
257 (parse_reg_list): Update for new arm_reg_parse args.
258 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
259 (parse_neon_el_struct_list): New function. Parse element/structure
260 register lists for VLD<n>/VST<n> instructions.
261 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
262 (s_arm_unwind_save_mmxwr): Likewise.
263 (s_arm_unwind_save_mmxwcg): Likewise.
264 (s_arm_unwind_movsp): Likewise.
265 (s_arm_unwind_setfp): Likewise.
266 (parse_big_immediate): New function. Parse an immediate, which may be
267 64 bits wide. Put results in inst.operands[i].
268 (parse_shift): Update for new arm_reg_parse args.
269 (parse_address): Likewise. Add parsing of alignment specifiers.
270 (parse_neon_mov): Parse the operands of a VMOV instruction.
271 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
272 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
273 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
274 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
275 (parse_operands): Handle new codes above.
276 (encode_arm_vfp_sp_reg): Rename to...
277 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
278 selected VFP version only supports D0-D15.
279 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
280 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
281 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
282 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
283 encode_arm_vfp_reg name, and allow 32 D regs.
284 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
285 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
286 regs.
287 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
288 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
289 constant-load and conversion insns introduced with VFPv3.
290 (neon_tab_entry): New struct.
291 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
292 those which are the targets of pseudo-instructions.
293 (neon_opc): Enumerate opcodes, use as indices into...
294 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
295 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
296 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
297 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
298 neon_enc_tab.
299 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
300 Neon instructions.
301 (neon_type_mask): New. Compact type representation for type checking.
302 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
303 permitted type combinations.
304 (N_IGNORE_TYPE): New macro.
305 (neon_check_shape): New function. Check an instruction shape for
306 multiple alternatives. Return the specific shape for the current
307 instruction.
308 (neon_modify_type_size): New function. Modify a vector type and size,
309 depending on the bit mask in argument 1.
310 (neon_type_promote): New function. Convert a given "key" type (of an
311 operand) into the correct type for a different operand, based on a bit
312 mask.
313 (type_chk_of_el_type): New function. Convert a type and size into the
314 compact representation used for type checking.
315 (el_type_of_type_ckh): New function. Reverse of above (only when a
316 single bit is set in the bit mask).
317 (modify_types_allowed): New function. Alter a mask of allowed types
318 based on a bit mask of modifications.
319 (neon_check_type): New function. Check the type of the current
320 instruction against the variable argument list. The "key" type of the
321 instruction is returned.
322 (neon_dp_fixup): New function. Fill in and modify instruction bits for
323 a Neon data-processing instruction depending on whether we're in ARM
324 mode or Thumb-2 mode.
325 (neon_logbits): New function.
326 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
327 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
328 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
329 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
330 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
331 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
332 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
333 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
334 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
335 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
336 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
337 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
338 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
339 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
340 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
341 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
342 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
343 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
344 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
345 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
346 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
347 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
348 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
349 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
350 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
351 helpers.
352 (parse_neon_type): New function. Parse Neon type specifier.
353 (opcode_lookup): Allow parsing of Neon type specifiers.
354 (REGNUM2, REGSETH, REGSET2): New macros.
355 (reg_names): Add new VFPv3 and Neon registers.
356 (NUF, nUF, NCE, nCE): New macros for opcode table.
357 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
358 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
359 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
360 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
361 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
362 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
363 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
364 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
365 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
366 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
367 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
368 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
369 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
370 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
371 fto[us][lh][sd].
372 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
373 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
374 (arm_option_cpu_value): Add vfp3 and neon.
375 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
376 VFPv1 attribute.
377
1946c96e
BW		 3782006-04-25 Bob Wilson <bob.wilson@acm.org>
379
380 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
381 syntax instead of hardcoded opcodes with ".w18" suffixes.
382 (wide_branch_opcode): New.
383 (build_transition): Use it to check for wide branch opcodes with
384 either ".w18" or ".w15" suffixes.
385
5033a645
BW		 3862006-04-25 Bob Wilson <bob.wilson@acm.org>
387
388 * config/tc-xtensa.c (xtensa_create_literal_symbol,
389 xg_assemble_literal, xg_assemble_literal_space): Do not set the
390 frag's is_literal flag.
391
395fa56f
BW		 3922006-04-25 Bob Wilson <bob.wilson@acm.org>
393
394 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
395
708587a4
KH		 3962006-04-23 Kazu Hirata <kazu@codesourcery.com>
397
398 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
399 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
400 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
401 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
402 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
403
8463be01
PB		 4042005-04-20 Paul Brook <paul@codesourcery.com>
405
406 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
407 all targets.
408 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
409
f26a5955
AM		 4102006-04-19 Alan Modra <amodra@bigpond.net.au>
411
412 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
413 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
414 Make some cpus unsupported on ELF. Run "make dep-am".
415 * Makefile.in: Regenerate.
416
241a6c40
AM		 4172006-04-19 Alan Modra <amodra@bigpond.net.au>
418
419 * configure.in (--enable-targets): Indent help message.
420 * configure: Regenerate.
421
bb8f5920
L		 4222006-04-18 H.J. Lu <hongjiu.lu@intel.com>
423
424 PR gas/2533
425 * config/tc-i386.c (i386_immediate): Check illegal immediate
426 register operand.
427
23d9d9de
AM		 4282006-04-18 Alan Modra <amodra@bigpond.net.au>
429
64e74474
AM		 430 * config/tc-i386.c: Formatting.
431 (output_disp, output_imm): ISO C90 params.
432
6cbe03fb
AM		 433 * frags.c (frag_offset_fixed_p): Constify args.
434 * frags.h (frag_offset_fixed_p): Ditto.
435
23d9d9de
AM		 436 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
437 (COFF_MAGIC): Delete.
a37d486e
AM		 438
439 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
440
e7403566
DJ		 4412006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
442
443 * po/POTFILES.in: Regenerated.
444
58ab4f3d
MM		 4452006-04-16 Mark Mitchell <mark@codesourcery.com>
446
447 * doc/as.texinfo: Mention that some .type syntaxes are not
448 supported on all architectures.
449
482fd9f9
BW		 4502006-04-14 Sterling Augustine <sterling@tensilica.com>
451
452 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
453 instructions when such transformations have been disabled.
454
05d58145
BW		 4552006-04-10 Sterling Augustine <sterling@tensilica.com>
456
457 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
458 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
459 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
460 decoding the loop instructions. Remove current_offset variable.
461 (xtensa_fix_short_loop_frags): Likewise.
462 (min_bytes_to_other_loop_end): Remove current_offset argument.
463
9e75b3fa
AM		 4642006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
465
a37d486e 466 * config/tc-z80.c (z80_optimize_expr): Removed.
9e75b3fa
AM		 467 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
468
d727e8c2
NC		 4692006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
470
471 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
472 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
473 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
474 atmega644, atmega329, atmega3290, atmega649, atmega6490,
475 atmega406, atmega640, atmega1280, atmega1281, at90can32,
476 at90can64, at90usb646, at90usb647, at90usb1286 and
477 at90usb1287.
478 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
479
d252fdde
PB		 4802006-04-07 Paul Brook <paul@codesourcery.com>
481
482 * config/tc-arm.c (parse_operands): Set default error message.
483
ab1eb5fe
PB		 4842006-04-07 Paul Brook <paul@codesourcery.com>
485
486 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
487
7ae2971b
PB		 4882006-04-07 Paul Brook <paul@codesourcery.com>
489
490 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
491
53365c0d
PB		 4922006-04-07 Paul Brook <paul@codesourcery.com>
493
494 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
495 (move_or_literal_pool): Handle Thumb-2 instructions.
496 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
497
45aa61fe
AM		 4982006-04-07 Alan Modra <amodra@bigpond.net.au>
499
500 PR 2512.
501 * config/tc-i386.c (match_template): Move 64-bit operand tests
502 inside loop.
503
108a6f8e
CD		 5042006-04-06 Carlos O'Donell <carlos@codesourcery.com>
505
506 * po/Make-in: Add install-html target.
507 * Makefile.am: Add install-html and install-html-recursive targets.
508 * Makefile.in: Regenerate.
509 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
510 * configure: Regenerate.
511 * doc/Makefile.am: Add install-html and install-html-am targets.
512 * doc/Makefile.in: Regenerate.
513
ec651a3b
AM		 5142006-04-06 Alan Modra <amodra@bigpond.net.au>
515
516 * frags.c (frag_offset_fixed_p): Reinitialise offset before
517 second scan.
518
910600e9
RS		 5192006-04-05 Richard Sandiford <richard@codesourcery.com>
520 Daniel Jacobowitz <dan@codesourcery.com>
521
522 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
523 (GOTT_BASE, GOTT_INDEX): New.
524 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
525 GOTT_INDEX when generating VxWorks PIC.
526 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
527 use the generic *-*-vxworks* stanza instead.
528
99630778
AM		 5292006-04-04 Alan Modra <amodra@bigpond.net.au>
530
531 PR 997
532 * frags.c (frag_offset_fixed_p): New function.
533 * frags.h (frag_offset_fixed_p): Declare.
534 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
535 (resolve_expression): Likewise.
536
a02728c8
BW		 5372006-04-03 Sterling Augustine <sterling@tensilica.com>
538
539 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
540 of the same length but different numbers of slots.
541
9dfde49d
AS		 5422006-03-30 Andreas Schwab <schwab@suse.de>
543
544 * configure.in: Fix help string for --enable-targets option.
545 * configure: Regenerate.
546
2da12c60
NS		 5472006-03-28 Nathan Sidwell <nathan@codesourcery.com>
548
6d89cc8f
NS		 549 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
550 (m68k_ip): ... here. Use for all chips. Protect against buffer
551 overrun and avoid excessive copying.
552
2da12c60
NS		 553 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
554 m68020_control_regs, m68040_control_regs, m68060_control_regs,
555 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
556 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
557 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
558 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
559 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
560 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
561 mcf5282_ctrl, mcfv4e_ctrl): ... these.
562 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
563 (struct m68k_cpu): Change chip field to control_regs.
564 (current_chip): Remove.
565 (control_regs): New.
566 (m68k_archs, m68k_extensions): Adjust.
567 (m68k_cpus): Reorder to be in cpu number order. Adjust.
568 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
569 (find_cf_chip): Reimplement for new organization of cpu table.
570 (select_control_regs): Remove.
571 (mri_chip): Adjust.
572 (struct save_opts): Save control regs, not chip.
573 (s_save, s_restore): Adjust.
574 (m68k_lookup_cpu): Give deprecated warning when necessary.
575 (m68k_init_arch): Adjust.
576 (md_show_usage): Adjust for new cpu table organization.
577
1ac4baed
BS		 5782006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
579
580 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
581 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
582 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
583 "elf/bfin.h".
584 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
585 (any_gotrel): New rule.
586 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
587 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
588 "elf/bfin.h".
589 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
590 (bfin_pic_ptr): New function.
591 (md_pseudo_table): Add it for ".picptr".
592 (OPTION_FDPIC): New macro.
593 (md_longopts): Add -mfdpic.
594 (md_parse_option): Handle it.
595 (md_begin): Set BFD flags.
596 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
597 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
598 us for GOT relocs.
599 * Makefile.am (bfin-parse.o): Update dependencies.
600 (DEPTC_bfin_elf): Likewise.
601 * Makefile.in: Regenerate.
602
a9d34880
RS		 6032006-03-25 Richard Sandiford <richard@codesourcery.com>
604
605 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
606 mcfemac instead of mcfmac.
607
9ca26584
AJ		 6082006-03-23 Michael Matz <matz@suse.de>
609
610 * config/tc-i386.c (type_names): Correct placement of 'static'.
611 (reloc): Map some more relocs to their 64 bit counterpart when
612 size is 8.
613 (output_insn): Work around breakage if DEBUG386 is defined.
614 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
615 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
616 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
617 different from i386.
618 (output_imm): Ditto.
619 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
620 Imm64.
621 (md_convert_frag): Jumps can now be larger than 2GB away, error
622 out in that case.
623 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
624 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
625
0a44bf69
RS		 6262006-03-22 Richard Sandiford <richard@codesourcery.com>
627 Daniel Jacobowitz <dan@codesourcery.com>
628 Phil Edwards <phil@codesourcery.com>
629 Zack Weinberg <zack@codesourcery.com>
630 Mark Mitchell <mark@codesourcery.com>
631 Nathan Sidwell <nathan@codesourcery.com>
632
633 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
634 (md_begin): Complain about -G being used for PIC. Don't change
635 the text, data and bss alignments on VxWorks.
636 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
637 generating VxWorks PIC.
638 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
639 (macro): Likewise, but do not treat la $25 specially for
640 VxWorks PIC, and do not handle jal.
641 (OPTION_MVXWORKS_PIC): New macro.
642 (md_longopts): Add -mvxworks-pic.
643 (md_parse_option): Don't complain about using PIC and -G together here.
644 Handle OPTION_MVXWORKS_PIC.
645 (md_estimate_size_before_relax): Always use the first relaxation
646 sequence on VxWorks.
647 * config/tc-mips.h (VXWORKS_PIC): New.
648
080eb7fe
PB		 6492006-03-21 Paul Brook <paul@codesourcery.com>
650
651 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
652
03aaa593
BW		 6532006-03-21 Sterling Augustine <sterling@tensilica.com>
654
655 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
656 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
657 (get_loop_align_size): New.
658 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
659 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
660 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
661 (get_noop_aligned_address): Use get_loop_align_size.
662 (get_aligned_diff): Likewise.
663
3e94bf1a
PB		 6642006-03-21 Paul Brook <paul@codesourcery.com>
665
666 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
667
dfa9f0d5
PB		 6682006-03-20 Paul Brook <paul@codesourcery.com>
669
670 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
671 (do_t_branch): Encode branches inside IT blocks as unconditional.
672 (do_t_cps): New function.
673 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
674 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
675 (opcode_lookup): Allow conditional suffixes on all instructions in
676 Thumb mode.
677 (md_assemble): Advance condexec state before checking for errors.
678 (insns): Use do_t_cps.
679
6e1cb1a6
PB		 6802006-03-20 Paul Brook <paul@codesourcery.com>
681
682 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
683 outputting the insn.
684
0a966e2d
JBG		 6852006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
686
687 * config/tc-vax.c: Update copyright year.
688 * config/tc-vax.h: Likewise.
689
a49fcc17
JBG		 6902006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
691
692 * config/tc-vax.c (md_chars_to_number): Used only locally, so
693 make it static.
694 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
695
f5208ef2
PB		 6962006-03-17 Paul Brook <paul@codesourcery.com>
697
698 * config/tc-arm.c (insns): Add ldm and stm.
699
cb4c78d6
BE		 7002006-03-17 Ben Elliston <bje@au.ibm.com>
701
702 PR gas/2446
703 * doc/as.texinfo (Ident): Document this directive more thoroughly.
704
c16d2bf0
PB		 7052006-03-16 Paul Brook <paul@codesourcery.com>
706
707 * config/tc-arm.c (insns): Add "svc".
708
80ca4e2c
BW		 7092006-03-13 Bob Wilson <bob.wilson@acm.org>
710
711 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
712 flag and avoid double underscore prefixes.
713
3a4a14e9
PB		 7142006-03-10 Paul Brook <paul@codesourcery.com>
715
716 * config/tc-arm.c (md_begin): Handle EABIv5.
717 (arm_eabis): Add EF_ARM_EABI_VER5.
718 * doc/c-arm.texi: Document -meabi=5.
719
518051dc
BE		 7202006-03-10 Ben Elliston <bje@au.ibm.com>
721
722 * app.c (do_scrub_chars): Simplify string handling.
723
00a97672
RS		 7242006-03-07 Richard Sandiford <richard@codesourcery.com>
725 Daniel Jacobowitz <dan@codesourcery.com>
726 Zack Weinberg <zack@codesourcery.com>
727 Nathan Sidwell <nathan@codesourcery.com>
728 Paul Brook <paul@codesourcery.com>
729 Ricardo Anguiano <anguiano@codesourcery.com>
730 Phil Edwards <phil@codesourcery.com>
731
732 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
733 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
734 R_ARM_ABS12 reloc.
735 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
736 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
737 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
738
b29757dc
BW		 7392006-03-06 Bob Wilson <bob.wilson@acm.org>
740
741 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
742 even when using the text-section-literals option.
743
0b2e31dc
NS		 7442006-03-06 Nathan Sidwell <nathan@codesourcery.com>
745
746 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
747 and cf.
748 (m68k_ip): <case 'J'> Check we have some control regs.
749 (md_parse_option): Allow raw arch switch.
750 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
751 whether 68881 or cfloat was meant by -mfloat.
752 (md_show_usage): Adjust extension display.
753 (m68k_elf_final_processing): Adjust.
754
df406460
NC		 7552006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
756
757 * config/tc-avr.c (avr_mod_hash_value): New function.
758 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
759 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
760 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
761 instead of int avr_ldi_expression: use avr_mod_hash_value instead
762 of (int).
763 (tc_gen_reloc): Handle substractions of symbols, if possible do
764 fixups, abort otherwise.
765 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
766 tc_fix_adjustable): Define.
767
53022e4a
JW		 7682006-03-02 James E Wilson <wilson@specifix.com>
769
770 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
771 change the template, then clear md.slot[curr].end_of_insn_group.
772
9f6f925e
JB		 7732006-02-28 Jan Beulich <jbeulich@novell.com>
774
775 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
776
0e31b3e1
JB		 7772006-02-28 Jan Beulich <jbeulich@novell.com>
778
779 PR/1070
780 * macro.c (getstring): Don't treat parentheses special anymore.
781 (get_any_string): Don't consider '(' and ')' as quoting anymore.
782 Special-case '(', ')', '[', and ']' when dealing with non-quoting
783 characters.
784
10cd14b4
AM		 7852006-02-28 Mat <mat@csail.mit.edu>
786
787 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
788
63752a75
JJ		 7892006-02-27 Jakub Jelinek <jakub@redhat.com>
790
791 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
792 field.
793 (CFI_signal_frame): Define.
794 (cfi_pseudo_table): Add .cfi_signal_frame.
795 (dot_cfi): Handle CFI_signal_frame.
796 (output_cie): Handle cie->signal_frame.
797 (select_cie_for_fde): Don't share CIE if signal_frame flag is
798 different. Copy signal_frame from FDE to newly created CIE.
799 * doc/as.texinfo: Document .cfi_signal_frame.
800
f7d9e5c3
CD		 8012006-02-27 Carlos O'Donell <carlos@codesourcery.com>
802
803 * doc/Makefile.am: Add html target.
804 * doc/Makefile.in: Regenerate.
805 * po/Make-in: Add html target.
806
331d2d0d
L		 8072006-02-27 H.J. Lu <hongjiu.lu@intel.com>
808
8502d882 809 * config/tc-i386.c (output_insn): Support Intel Merom New
331d2d0d
L		 810 Instructions.
811
8502d882 812 * config/tc-i386.h (CpuMNI): New.
331d2d0d
L		 813 (CpuUnknownFlags): Add CpuMNI.
814
10156f83
DM		 8152006-02-24 David S. Miller <davem@sunset.davemloft.net>
816
817 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
818 (hpriv_reg_table): New table for hyperprivileged registers.
819 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
820 register encoding.
821
6772dd07
DD		 8222006-02-24 DJ Delorie <dj@redhat.com>
823
824 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
825 (tc_gen_reloc): Don't define.
826 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
827 (OPTION_LINKRELAX): New.
828 (md_longopts): Add it.
829 (m32c_relax): New.
830 (md_parse_options): Set it.
831 (md_assemble): Emit relaxation relocs as needed.
832 (md_convert_frag): Emit relaxation relocs as needed.
833 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
834 (m32c_apply_fix): New.
835 (tc_gen_reloc): New.
836 (m32c_force_relocation): Force out jump relocs when relaxing.
837 (m32c_fix_adjustable): Return false if relaxing.
838
62b3e311
PB		 8392006-02-24 Paul Brook <paul@codesourcery.com>
840
841 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
842 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
843 (struct asm_barrier_opt): Define.
844 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
845 (parse_psr): Accept V7M psr names.
846 (parse_barrier): New function.
847 (enum operand_parse_code): Add OP_oBARRIER.
848 (parse_operands): Implement OP_oBARRIER.
849 (do_barrier): New function.
850 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
851 (do_t_cpsi): Add V7M restrictions.
852 (do_t_mrs, do_t_msr): Validate V7M variants.
853 (md_assemble): Check for NULL variants.
854 (v7m_psrs, barrier_opt_names): New tables.
855 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
856 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
857 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
858 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
859 (struct cpu_arch_ver_table): Define.
860 (cpu_arch_ver): New.
861 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
862 Tag_CPU_arch_profile.
863 * doc/c-arm.texi: Document new cpu and arch options.
864
59cf82fe
L		 8652006-02-23 H.J. Lu <hongjiu.lu@intel.com>
866
867 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
868
19a7219f
L		 8692006-02-23 H.J. Lu <hongjiu.lu@intel.com>
870
871 * config/tc-ia64.c: Update copyright years.
872
7f3dfb9c
L		 8732006-02-22 H.J. Lu <hongjiu.lu@intel.com>
874
875 * config/tc-ia64.c (specify_resource): Add the rule 17 from
876 SDM 2.2.
877
f40d1643
PB		 8782005-02-22 Paul Brook <paul@codesourcery.com>
879
880 * config/tc-arm.c (do_pld): Remove incorrect write to
881 inst.instruction.
882 (encode_thumb32_addr_mode): Use correct operand.
883
216d22bc
PB		 8842006-02-21 Paul Brook <paul@codesourcery.com>
885
886 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
887
d70c5fc7
NC		 8882006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
889 Anil Paranjape <anilp1@kpitcummins.com>
890 Shilin Shakti <shilins@kpitcummins.com>
891
892 * Makefile.am: Add xc16x related entry.
893 * Makefile.in: Regenerate.
894 * configure.in: Added xc16x related entry.
895 * configure: Regenerate.
896 * config/tc-xc16x.h: New file
897 * config/tc-xc16x.c: New file
898 * doc/c-xc16x.texi: New file for xc16x
899 * doc/all.texi: Entry for xc16x
900 * doc/Makefile.texi: Added c-xc16x.texi
901 * NEWS: Announce the support for the new target.
902
aaa2ab3d
NH		 9032006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
904
905 * configure.tgt: set emulation for mips-*-netbsd*
906
82de001f
JJ		 9072006-02-14 Jakub Jelinek <jakub@redhat.com>
908
909 * config.in: Rebuilt.
910
431ad2d0
BW		 9112006-02-13 Bob Wilson <bob.wilson@acm.org>
912
913 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
914 from 1, not 0, in error messages.
915 (md_assemble): Simplify special-case check for ENTRY instructions.
916 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
917 operand in error message.
918
94089a50
JM		 9192006-02-13 Joseph S. Myers <joseph@codesourcery.com>
920
921 * configure.tgt (arm-*-linux-gnueabi*): Change to
922 arm-*-linux-*eabi*.
923
52de4c06
NC		 9242006-02-10 Nick Clifton <nickc@redhat.com>
925
70e45ad9
NC		 926 * config/tc-crx.c (check_range): Ensure that the sign bit of a
927 32-bit value is propagated into the upper bits of a 64-bit long.
928
52de4c06
NC		 929 * config/tc-arc.c (init_opcode_tables): Fix cast.
930 (arc_extoper, md_operand): Likewise.
931
21af2bbd
BW		 9322006-02-09 David Heine <dlheine@tensilica.com>
933
934 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
935 each relaxation step.
936
75a706fc
L		 9372006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
938
939 * configure.in (CHECK_DECLS): Add vsnprintf.
940 * configure: Regenerate.
941 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
942 include/declare here, but...
943 * as.h: Move code detecting VARARGS idiom to the top.
944 (errno.h, stdarg.h, varargs.h, va_list): ...here.
945 (vsnprintf): Declare if not already declared.
946
0d474464
L		 9472006-02-08 H.J. Lu <hongjiu.lu@intel.com>
948
949 * as.c (close_output_file): New.
950 (main): Register close_output_file with xatexit before
951 dump_statistics. Don't call output_file_close.
952
266abb8f
NS		 9532006-02-07 Nathan Sidwell <nathan@codesourcery.com>
954
955 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
956 mcf5329_control_regs): New.
957 (not_current_architecture, selected_arch, selected_cpu): New.
958 (m68k_archs, m68k_extensions): New.
959 (archs): Renamed to ...
960 (m68k_cpus): ... here. Adjust.
961 (n_arches): Remove.
962 (md_pseudo_table): Add arch and cpu directives.
963 (find_cf_chip, m68k_ip): Adjust table scanning.
964 (no_68851, no_68881): Remove.
965 (md_assemble): Lazily initialize.
966 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
967 (md_init_after_args): Move functionality to m68k_init_arch.
968 (mri_chip): Adjust table scanning.
969 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
970 options with saner parsing.
971 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
972 m68k_init_arch): New.
973 (s_m68k_cpu, s_m68k_arch): New.
974 (md_show_usage): Adjust.
975 (m68k_elf_final_processing): Set CF EF flags.
976 * config/tc-m68k.h (m68k_init_after_args): Remove.
977 (tc_init_after_args): Remove.
978 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
979 (M68k-Directives): Document .arch and .cpu directives.
980
134dcee5
AM		 9812006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
982
983 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
984 synonyms for equ and defl.
985 (z80_cons_fix_new): New function.
986 (emit_byte): Disallow relative jumps to absolute locations.
987 (emit_data): Only handle defb, prototype changed, because defb is
988 now handled as pseudo-op rather than an instruction.
989 (instab): Entries for defb,defw,db,dw moved from here...
990 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
991 Add entries for def24,def32,d24,d32.
992 (md_assemble): Improved error handling.
993 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
994 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
995 (z80_cons_fix_new): Declare.
996 * doc/c-z80.texi (defb, db): Mention warning on overflow.
997 (def24,d24,def32,d32): New pseudo-ops.
998
a9931606
PB		 9992006-02-02 Paul Brook <paul@codesourcery.com>
1000
1001 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1002
ef8d22e6
PB		 10032005-02-02 Paul Brook <paul@codesourcery.com>
1004
1005 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1006 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1007 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1008 T2_OPCODE_RSB): Define.
1009 (thumb32_negate_data_op): New function.
1010 (md_apply_fix): Use it.
1011
e7da6241
BW		 10122006-01-31 Bob Wilson <bob.wilson@acm.org>
1013
1014 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1015 fields.
1016 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1017 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1018 subtracted symbols.
1019 (relaxation_requirements): Add pfinish_frag argument and use it to
1020 replace setting tinsn->record_fix fields.
1021 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1022 and vinsn_to_insnbuf. Remove references to record_fix and
1023 slot_sub_symbols fields.
1024 (xtensa_mark_narrow_branches): Delete unused code.
1025 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1026 a symbol.
1027 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1028 record_fix fields.
1029 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1030 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1031 of the record_fix field. Simplify error messages for unexpected
1032 symbolic operands.
1033 (set_expr_symbol_offset_diff): Delete.
1034
79134647
PB		 10352006-01-31 Paul Brook <paul@codesourcery.com>
1036
1037 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1038
e74cfd16
PB		 10392006-01-31 Paul Brook <paul@codesourcery.com>
1040 Richard Earnshaw <rearnsha@arm.com>
1041
1042 * config/tc-arm.c: Use arm_feature_set.
1043 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1044 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1045 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1046 New variables.
1047 (insns): Use them.
1048 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1049 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1050 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1051 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1052 feature flags.
1053 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1054 (arm_opts): Move old cpu/arch options from here...
1055 (arm_legacy_opts): ... to here.
1056 (md_parse_option): Search arm_legacy_opts.
1057 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1058 (arm_float_abis, arm_eabis): Make const.
1059
d47d412e
BW		 10602006-01-25 Bob Wilson <bob.wilson@acm.org>
1061
1062 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1063
b14273fe
JZ		 10642006-01-21 Jie Zhang <jie.zhang@analog.com>
1065
1066 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1067 in load immediate intruction.
1068
39cd1c76
JZ		 10692006-01-21 Jie Zhang <jie.zhang@analog.com>
1070
1071 * config/bfin-parse.y (value_match): Use correct conversion
1072 specifications in template string for __FILE__ and __LINE__.
1073 (binary): Ditto.
1074 (unary): Ditto.
1075
67a4f2b7
AO		 10762006-01-18 Alexandre Oliva <aoliva@redhat.com>
1077
1078 Introduce TLS descriptors for i386 and x86_64.
1079 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1080 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1081 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1082 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1083 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1084 displacement bits.
1085 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1086 (lex_got): Handle @tlsdesc and @tlscall.
1087 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1088
8ad7c533
NC		 10892006-01-11 Nick Clifton <nickc@redhat.com>
1090
1091 Fixes for building on 64-bit hosts:
1092 * config/tc-avr.c (mod_index): New union to allow conversion
1093 between pointers and integers.
1094 (md_begin, avr_ldi_expression): Use it.
1095 * config/tc-i370.c (md_assemble): Add cast for argument to print
1096 statement.
1097 * config/tc-tic54x.c (subsym_substitute): Likewise.
1098 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1099 opindex field of fr_cgen structure into a pointer so that it can
1100 be stored in a frag.
1101 * config/tc-mn10300.c (md_assemble): Likewise.
1102 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1103 types.
1104 * config/tc-v850.c: Replace uses of (int) casts with correct
1105 types.
1106
4dcb3903
L		 11072006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1108
1109 PR gas/2117
1110 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1111
e0f6ea40
HPN		 11122006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1113
1114 PR gas/2101
1115 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1116 a local-label reference.
1117
e88d958a 1118For older changes see ChangeLog-2005
08d56133
NC		 1119\f
1120Local Variables:
1121mode: change-log
1122left-margin: 8
1123fill-column: 74
1124version-control: never
1125End:
GDB Binutils - Deliverables
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