* alphanbsd-tdep.c: Include "target.h".
[deliverable/binutils-gdb.git] / gas / ChangeLog
CommitLineData
783d3e71
KK
12008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
2
3 PR gas/6043
4 * config/tc-sh64.c (shmedia_md_pcrel_from_section): Use
5 md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL.
6
1b6e95c2
BW
72008-04-04 Adrian Bunk <bunk@stusta.de>
8 Bob Wilson <bob.wilson@acm.org>
9
10 * config/tc-xtensa.c (xg_apply_fix_value): Check return code from
11 call to decode_reloc.
12
594ab6a3
L
132008-04-04 H.J. Lu <hongjiu.lu@intel.com>
14
15 * NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
16
17 * config/tc-i386.c (cpu_arch): Add .pclmul.
18 (md_show_usage): Replace clmul with pclmul.
19 * doc/c-i386.texi: Likewise.
20
c0f3af97
L
212008-04-03 H.J. Lu <hongjiu.lu@intel.com>
22
23 * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
24
25 * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
26 Document -msse2avx, .avx, .aes, .clmul and .fma.
27
28 * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
29 (vex_prefix): Likewise.
30 (sse2avx): Likewise.
31 (CPU_FLAGS_ARCH_MATCH): Likewise.
32 (CPU_FLAGS_64BIT_MATCH): Likewise.
33 (CPU_FLAGS_32BIT_MATCH): Likewise.
34 (CPU_FLAGS_PERFECT_MATCH): Likewise.
35 (regymm): Likewise.
36 (vex_imm4): Likewise.
37 (fits_in_imm4): Likewise.
38 (build_vex_prefix): Likewise.
39 (VEX_check_operands): Likewise.
40 (bad_implicit_operand): Likewise.
41 (OPTION_MSSE2AVX): Likewise.
42 (T_YMMWORD): Likewise.
43 (_i386_insn): Add vex.
44 (cpu_arch): Add .avx, .aes, .clmul and .fma.
45 (cpu_flags_match): Changed to take a pointer to const template.
46 Enable encoding SSE instructions with VEX prefix for -msse2avx.
47 (match_mem_size): Also check ymmword.
48 (operand_type_match): Clear ymmword.
49 (md_begin): Allow '_' in mnemonic.
50 (type_names): Add OPERAND_TYPE_VEX_IMM4.
51 (process_immext): Update assert.
52 (md_assemble): Don't call process_immext if sse2avx and immext
53 are true. Call build_vex_prefix if vex is true.
54 (parse_insn): Updated for cpu_flags_match.
55 (swap_operands): Handle 5 operands.
56 (match_template): Handle 5 operands. Updated for cpu_flags_match.
57 Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
58 (process_suffix): Handle YMMWORD_MNEM_SUFFIX.
59 (check_byte_reg): Check regymm.
60 (process_operands): Duplicate the destination register for
61 -msse2avx if needed.
62 (build_modrm_byte): Updated for instructions with VEX encoding.
63 (output_insn): Output VEX prefix if needed.
64 (md_longopts): Add msse2avx.
65 (md_parse_option): Handle OPTION_MSSE2AVX.
66 (md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
67 (intel_e09): Support YMMWORD.
68 (intel_e11): Likewise.
69 (intel_get_token): Likewise.
70
2460c166
EW
712008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
72
73 * config/tc-avr.c (mcu_types): Add attiny167.
74 * doc/c-avr.texi: Likewise.
75
70881657
EW
762008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
77
78 * config/tc-avr.c (mcu_types): Add atmega32u4.
79 * doc/c-avr.texi: Likewise.
80
25755480
EW
812008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
82
83 * config/tc-avr.c (mcu_types): Add atmega32c1.
84 * doc/c-avr.texi: Likewise.
85
4641781c
PB
862008-03-28 Paul Brook <paul@codesourcery.com>
87
88 * config/tc-arm.c (parse_neon_mov): Parse register before immediate
89 to avoid spurious symbols.
90
025987ea
NS
912008-03-28 Nathan Sidwell <nathan@codesourcery.com>
92
93 * config/tc-m68k.c (md_convert_frag_1): Replace as_fatal with
94 as_bad_where.
95
38de72b9
NC
962008-03-27 Eric B. Weddington <eric.weddington@atmel.com>
97
98 * config/tc-avr.c (mcu_types): Add atmega32m1.
99 * doc/c-avr.texi: Likewise.
100
35997600
NC
1012008-03-27 Ineiev <ineiev@yahoo.co.uk>
102
103 * config/tc-arm.c (do_neon_cvt): Move variable declarations to
104 start of block.
105 (do_neon_ext): Fix sign of comparison.
106
99bfa74a
BS
1072008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
108
109 From Jie Zhang <jie.zhang@analog.com>
110 * config/bfin-parse.y (asm_1): Check AREGS in comparison
c1db045b 111 instructions. And call yyerror when comparing PREG with
99bfa74a 112 DREG.
c1db045b 113 (check_macfunc_option): New.
4641781c 114 (check_macfuncs): Check option by calling check_macfunc_option.
c1db045b
BS
115 Fix comparison always true warnings. Both scalar instructions
116 of vector instruction must share the same mode option. Only allow
117 option mode at the end of the second instruction of the vector.
4641781c 118 (asm_1): Check option by calling check_macfunc_option.
99bfa74a 119
ee171c8f
BS
120 * config/bfin-parse.y (check_macfunc_option): Allow (IU)
121 option for multiply and multiply-accumulate to data register
4641781c 122 instruction.
ee171c8f
BS
123 (check_macfuncs): Don't check if accumulator matches the data register
124 here.
125 (assign_macfunc): Check if accumulator matches the
126 data register in each rule that moves to the data
127 register.
128
e2c038d3
BS
129 * config/tc-bfin.c (bfin_start_line_hook): Localize the labels
130 generated for LOOP_BEGIN and LOOP_END instructions.
131 (bfin_gen_loop): Likewise.
132
5746fb46
AK
1332008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
134
135 * config/tc-s390.c (md_parse_option): z10 option added.
136
58c85be7
RW
1372008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
138
139 * aclocal.m4: Regenerate.
140 * configure: Likewise.
141 * Makefile.in: Likewise.
142 * doc/Makefile.in: Likewise.
143
da6b876e
AM
1442008-03-17 Adrian Bunk <bunk@stusta.de>
145
146 PR 5946
147 * config/tc-hppa.c (is_same_frag): Delete.
148
3b492825
BW
1492008-03-14 Sterling Augustine <sterling@tensilica.com>
150
151 * config/tc-xtensa.h (xtensa_relax_statesE): Update comment for
152 RELAX_LOOP_END_ADD_NOP.
153
5808f4a6
NC
1542008-03-13 Evandro Menezes <evandro@yahoo.com>
155
156 PR gas/5895
157 * read.c (s_mexit): Warn if attempting to exit a macro when not
158 inside a macro definition.
159
50e7d84b
AM
1602008-03-13 Alan Modra <amodra@bigpond.net.au>
161
162 * Makefile.am: Run "make dep-am".
163 * Makefile.in: Regenerate.
164 * configure: Regenerate.
165
15290f0a
PB
1662008-03-09 Paul Brook <paul@codesourcery.com>
167
168 * config/tc-arm.c (arm_cpu_option_table): Add cortex-a9.
169 * doc/c-arm.texi: Add cortex-a9.
170
b1cc4aeb
PB
1712008-03-09 Paul Brook <paul@codesourcery.com>
172
173 * config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
174 (parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
175 (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
176 (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
177 * doc/c-arm.texi: Document new ARM FPU variants.
178
39623e12
PB
1792008-03-07 Paul Brook <paul@codesourcery.com>
180
181 * config/tc-arm.c (md_apply_fix): Use correct offset range.
182
d815f1a9
AM
1832008-03-07 Alan Modra <amodra@bigpond.net.au>
184
185 * config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to test
186 for strict ordering of powerpc_opcodes, but disable for now.
187
7e806470
PB
1882008-03-04 Paul Brook <paul@codesourcery.com>
189
190 * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
191 (arm_ext_v7m): Rename...
192 (arm_ext_m): ... to this. Include v6-M.
193 (do_t_add_sub): Allow narrow low-reg non flag setting adds.
194 (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
195 (md_assemble): Allow wide msr instructions.
196 (insns): Add classifications for v6-m instructions.
197 (arm_cpu_option_table): Add cortex-m1.
198 (arm_arch_option_table): Add armv6-m.
199 (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
200
77cba8a3
BW
2012008-03-03 Sterling Augustine <sterling@tensilica.com>
202 Bob Wilson <bob.wilson@acm.org>
203
204 * config/tc-xtensa.c (xtensa_num_pipe_stages): New.
205 (md_begin): Initialize it.
206 (resources_conflict): Use it.
207
58502fec
BW
2082008-03-03 Sterling Augustine <sterling@tensilica.com>
209
210 * config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
211
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2122008-03-03 Denys Vlasenko <vda.linux@googlemail.com>
213 H.J. Lu <hongjiu.lu@intel.com>
214
215 PR gas/5543
216 * read.c (pseudo_set): Don't allow global register symbol.
217
218 * symbols.c (S_SET_EXTERNAL): Don't allow register symbol
219 global.
220
2212008-03-03 H.J. Lu <hongjiu.lu@intel.com>
222
223 PR gas/5543
224 * write.c (write_object_file): Don't allow symbols which were
225 equated to register. Stop if there is an error.
226
783de163
AM
2272008-03-01 Alan Modra <amodra@bigpond.net.au>
228
229 * config/tc-ppc.h (struct _ppc_fix_extra): New.
230 (ppc_cpu): Declare.
231 (TC_FIX_TYPE, TC_INIT_FIX_DATA): Define.
232 * config/tc-ppc.c (ppu_cpu): Make global.
233 (ppc_insert_operand): Add ppu_cpu parameter.
234 (md_assemble): Adjust for above change.
235 (md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
236
5ad34203
NC
2372008-02-22 Nick Clifton <nickc@redhat.com>
238
239 * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELF
584206db 240 targeted ARM ports, otherwise just skip generating the reloc.
5ad34203 241
1ceab344
L
2422008-02-18 H.J. Lu <hongjiu.lu@intel.com>
243
244 * doc/c-i386.texi: Update -march= and .arch.
245
ca75ed2d
NC
2462008-02-18 Nick Clifton <nickc@redhat.com>
247
248 * config/tc-mn10300.c (has_known_symbol_location): New function.
249 Do not regard weak symbols as having a known location.
250 (md_estimate_size_before_relax): Use new function.
251 (md_pcrel_from): Do not compute a pcrel against a weak symbol.
252
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JB
2532008-02-18 Jan Beulich <jbeulich@novell.com>
254
255 * config/tc-i386.c (match_template): Disallow 'l' suffix when
256 currently selected CPU has no 32-bit support.
257 (parse_real_register): Do not return registers not available on
258 currently selected CPU.
259
1fed0ba1
L
2602008-02-16 H.J. Lu <hongjiu.lu@intel.com>
261
262 * config/tc-i386.c (process_immext): Fix format.
263
65da13b5
L
2642008-02-16 H.J. Lu <hongjiu.lu@intel.com>
265
266 * config/tc-i386.c (inoutportreg): New.
267 (process_immext): New.
268 (md_assemble): Use it.
269 (update_imm): Use imm16 and imm32s.
270 (i386_att_operand): Use inoutportreg.
271
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L
2722008-02-14 H.J. Lu <hongjiu.lu@intel.com>
273
274 * config/tc-i386.c (operand_type_all_zero): New.
275 (operand_type_set): Likewise.
276 (operand_type_equal): Likewise.
277 (cpu_flags_all_zero): Likewise.
278 (cpu_flags_set): Likewise.
279 (cpu_flags_equal): Likewise.
280 (UINTS_ALL_ZERO): Removed.
281 (UINTS_SET): Likewise.
282 (UINTS_CLEAR): Likewise.
283 (UINTS_EQUAL): Likewise.
284 (cpu_flags_match): Updated.
285 (smallest_imm_type): Likewise.
286 (set_cpu_arch): Likewise.
287 (md_assemble): Likewise.
288 (optimize_imm): Likewise.
289 (match_template): Likewise.
290 (process_suffix): Likewise.
291 (update_imm): Likewise.
292 (process_drex): Likewise.
293 (process_operands): Likewise.
294 (build_modrm_byte): Likewise.
295 (i386_immediate): Likewise.
296 (i386_displacement): Likewise.
297 (i386_att_operand): Likewise.
298 (parse_real_register): Likewise.
299 (md_parse_option): Likewise.
300 (i386_target_format): Likewise.
301
93ac2687
NC
3022008-02-14 Dimitry Andric <dimitry@andric.com>
303
304 PR gas/5712
305 * config/tc-arm.c (s_arm_unwind_save): Advance the input line
306 pointer past the comma after parsing a floating point register
307 name.
308
d669d37f
NC
3092008-02-14 Hakan Ardo <hakan@debian.org>
310
311 PR gas/2626
312 * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26
313 to AVR_ISA_2xxe.
314 (avr_operand): Disallow post-increment addressing in the lpm
315 instruction for the attiny26.
316
b7240065
JB
3172008-02-13 Jan Beulich <jbeulich@novell.com>
318
319 * config/tc-i386.c (parse_real_register): Don't return 'FLAT'
320 if not in Intel mode.
321 (i386_intel_operand): Ignore segment overrides in immediate and
322 offset operands.
323 (intel_e11): Range-check i.mem_operands before use as array
324 index. Filter out FLAT for uses other than as segment override.
325 (intel_get_token): Remove broken promotion of "FLAT:" to mean
326 "offset FLAT:".
327
34b772a6
JB
3282008-02-13 Jan Beulich <jbeulich@novell.com>
329
330 * config/tc-i386.c (intel_e09): Also special-case 'bound'.
331
a60de03c
JB
3322008-02-13 Jan Beulich <jbeulich@novell.com>
333
334 * config/tc-i386.c (allow_pseudo_reg): New.
335 (parse_real_register): Check for NULL just once. Allow all
336 register table entries when allow_pseudo_reg is non-zero.
337 Don't allow any registers without type when allow_pseudo_reg
338 is zero.
339 (tc_x86_regname_to_dw2regnum): Replace with ...
340 (tc_x86_parse_to_dw2regnum): ... this.
341 (tc_x86_frame_initial_instructions): Adjust for above change.
342 * config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
343 (tc_parse_to_dw2regnum): New.
344 (tc_x86_regname_to_dw2regnum): Replace with ...
345 (tc_x86_parse_to_dw2regnum): ... this.
346 * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
347 (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
348 error handling.
349
9c95b521
NC
3502008-02-12 Nick Clifton <nickc@redhat.com>
351
352 * config/tc-tic4x.c (tic4x_insn_insert): Add const qualifier to
353 argument.
354 (tic4x_insn_add): Likewise.
355 (md_begin): Drop cast that was discarding a const qualifier.
356 * config/tc-d30v.c (get_reloc): Add const qualifier to op
357 argument.
358 (build_insn): Drop cast that was discarding a const qualifier.
359
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L
3602008-02-11 H.J. Lu <hongjiu.lu@intel.com>
361
362 * config/tc-i386.c (cpu_arch): Add .xsave.
363 (md_show_usage): Add .xsave.
364
365 * doc/c-i386.texi: Add xsave to -march=.
366
1bf57e9f
AM
3672008-02-07 Alan Modra <amodra@bigpond.net.au>
368
369 * read.c (s_weakref): Don't pass unadorned NULL to concat.
370 * config/tc-i386.c (set_cpu_arch, md_parse_option): Likewise.
371
2276bc20
BW
3722008-02-05 Sterling Augustine <sterling@tensilica.com>
373
374 * config/tc-xtensa.c (relax_frag_immed): Change internal consistency
375 checks into assertions. When relaxation produces an operation that
376 does not fit in the current FLIX instruction, make sure that the
377 operation is relaxed as needed to account for being placed following
378 the current instruction.
379
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3802008-02-04 H.J. Lu <hongjiu.lu@intel.com>
381
382 PR 5715
383 * configure: Regenerated.
384
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AN
3852008-02-04 Adam Nemet <anemet@caviumnetworks.com>
386
387 * config/tc-mips.c (mips_cpu_info_table): Add Octeon.
388
f8a52b59
BW
3892008-01-31 Marc Gauthier <marc@tensilica.com>
390
391 * configure.tgt (xtensa*-*-*): Recognize processor variants.
392
6e3d6dc1
NC
3932008-01-25 Kai Tietz <kai.tietz@onevision.com>
394
395 * read.c: (emit_expr): Correct for mingw use of printf size
396 specifier.
397
cec28c98
BW
3982008-01-24 Bob Wilson <bob.wilson@acm.org>
399
400 * doc/c-xtensa.texi (Xtensa Syntax): Clarify handling of opcodes that
401 can only be encoded in FLIX instructions but are not specified as such.
402 (Xtensa Automatic Alignment): Remove obsolete comment about debugging
403 labels.
404
ae40c993
L
4052008-01-24 H.J. Lu <hongjiu.lu@intel.com>
406
407 * NEWS: Mention new command line options for x86 targets.
408
599121aa
L
4092008-01-23 H.J. Lu <hongjiu.lu@intel.com>
410
411 * config/tc-i386.c (md_show_usage): Replace tabs with spaces.
412
2b1ed17b
EW
4132008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
414
415 * config/tc-avr.c (mcu_types): Change opcode set for at86rf401.
416
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4172008-01-23 H.J. Lu <hongjiu.lu@intel.com>
418
419 * config/tc-i386.c (md_show_usage): Show more processors for
420 -march=/-mtune=.
421
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L
4222008-01-22 H.J. Lu <hongjiu.lu@intel.com>
423
424 * config/tc-i386.c (i386_target_format): Remove cpummx2.
425
6305a203
L
4262008-01-22 H.J. Lu <hongjiu.lu@intel.com>
427
428 * config/tc-i386.c (XXX_PREFIX): Moved from tc-i386.h.
429 (XXX_MNEM_SUFFIX): Likewise.
430 (END_OF_INSN): Likewise.
431 (templates): Likewise.
432 (modrm_byte): Likewise.
433 (rex_byte): Likewise.
434 (DREX_XXX): Likewise.
435 (drex_byte): Likewise.
436 (sib_byte): Likewise.
437 (processor_type): Likewise.
438 (arch_entry): Likewise.
439 (cpu_sub_arch_name): Remove const.
440 (cpu_arch): Add .vmx and .smx.
441 (set_cpu_arch): Append cpu_sub_arch_name.
442 (md_parse_option): Support -march=CPU[,+EXTENSION...].
443 (md_show_usage): Updated.
444
445 * config/tc-i386.h (XXX_PREFIX): Moved to tc-i386.c.
446 (XXX_MNEM_SUFFIX): Likewise.
447 (END_OF_INSN): Likewise.
448 (templates): Likewise.
449 (modrm_byte): Likewise.
450 (rex_byte): Likewise.
451 (DREX_XXX): Likewise.
452 (drex_byte): Likewise.
453 (sib_byte): Likewise.
454 (processor_type): Likewise.
455 (arch_entry): Likewise.
456
457 * doc/as.texinfo: Update i386 -march option.
458
459 * doc/c-i386.texi: Update -march= for ISA.
460
fb227da0
BW
4612008-01-18 Bob Wilson <bob.wilson@acm.org>
462
463 * config/tc-xtensa.c (xtensa_leb128): New function.
464 (md_pseudo_table): Use it for sleb128 and uleb128.
465 (is_leb128_expr): New internal flag.
466 (xtensa_symbol_new_hook): Check new flag.
467
982b62a0
EW
4682008-01-16 Eric B. Weddington <eric.weddington@atmel.com>
469
470 * config/tc-avr.c (mcu_types): Change opcode set for avr3,
471 at90usb82, at90usb162.
472 * doc/c-avr.texi: Change architecture grouping for at90usb82,
473 at90usb162.
474 These changes support the new avr35 architecture group in gcc.
475
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4762008-01-15 H.J. Lu <hongjiu.lu@intel.com>
477
478 * config/tc-i386.c (md_assemble): Also zap movzx and movsx
479 suffix for AT&T syntax.
480
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L
4812008-01-14 H.J. Lu <hongjiu.lu@intel.com>
482
483 * config/tc-i386.c (match_reg_size): New.
484 (match_mem_size): Likewise.
485 (operand_size_match): Likewise.
486 (operand_type_match): Also clear all size fields.
487 (match_template): Skip Intel syntax when in AT&T syntax.
488 Call operand_size_match to check operand size.
489 (i386_att_operand): Set the mem field to 1 for memory
490 operand.
491 (i386_intel_operand): Likewise.
492
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4932008-01-12 H.J. Lu <hongjiu.lu@intel.com>
494
495 PR gas/5534
496 * config/tc-i386.c (_i386_insn): Update comment.
497 (operand_type_match): Also clear unspecified.
498 (operand_type_register_match): Likewise.
499 (parse_operands): Initialize unspecified.
500 (i386_intel_operand): Likewise.
501 (match_template): Check memory and accumulator operand size.
502 (i386_att_operand): Clear unspecified on register operand.
503 (intel_e11): Likewise.
504 (intel_e09): Set operand size and clean unspecified for
505 "XXX PTR".
506
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AS
5072008-01-11 Andreas Schwab <schwab@suse.de>
508
509 * read.c (s_space): Declare `repeat' as offsetT.
510
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5112008-01-10 H.J. Lu <hongjiu.lu@intel.com>
512
513 * config/tc-i386.c (match_template): Check processor support
514 first.
515
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5162008-01-10 H.J. Lu <hongjiu.lu@intel.com>
517
518 * config/tc-i386.c (match_template): Continue if processor
519 doesn't match.
520
417c21b7
AO
5212008-01-09 Alexandre Oliva <aoliva@redhat.com>
522
523 * config/tc-ia64.c (ia64_convert_frag): Zero-initialize room for
524 unwind personality function address.
525
7ddd14de
BW
5262008-01-09 Bob Wilson <bob.wilson@acm.org>
527
528 * dwarf2dbg.c (out_sleb128): Delete.
529 (size_fixed_inc_line_addr, emit_fixed_inc_line_addr): New.
530 (out_fixed_inc_line_addr): Delete.
531 (relax_inc_line_addr, dwarf2dbg_estimate_size_before_relax): Call new
532 size_fixed_inc_line_addr if DWARF2_USE_FIXED_ADVANCE_PC is set.
533 (dwarf2dbg_convert_frag): Likewise for emit_fixed_inc_line_addr.
534 (process_entries): Remove calls to out_fixed_inc_line_addr. When
535 DWARF2_USE_FIXED_ADVANCE_PC is set, call relax_inc_line_addr.
536 * read.h (emit_expr_fix): New prototype.
537 * read.c (emit_expr): Move code to emit_expr_fix and use it here.
538 (emit_expr_fix): New.
539
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5402008-01-09 H.J. Lu <hongjiu.lu@intel.com>
541
542 * config/tc-i386.c (match_template): Check register size
543 only when size of operands can be encoded the canonical way.
544
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5452008-01-08 H.J. Lu <hongjiu.lu@intel.com>
546
547 * config/tc-i386.c (i386_operand): Renamed to ...
548 (i386_att_operand): This.
549 (parse_operands): Updated.
550
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5512008-01-05 H.J. Lu <hongjiu.lu@intel.com>
552
553 * doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic.
554
555 * config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic
556 only.
557 (md_assemble): Remove Intel mode workaround.
558 (match_template): Check support for old gcc, AT&T mnemonic
559 and Intel Syntax.
560 (md_parse_option): Don't set intel_mnemonic to 0 for
561 OPTION_MOLD_GCC.
562
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5632008-01-04 H.J. Lu <hongjiu.lu@intel.com>
564
565 * config/tc-i386.h: Update copyright to 2008.
566
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5672008-01-04 Nick Clifton <nickc@redhat.com>
568
569 * config/tc-ppc.c (parse_cpu): Preserve the settings of the
570 PPC_OPCODE_ALTIVEC and PPC_OPCODE_SPE flags.
571
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5722008-01-03 H.J. Lu <hongjiu.lu@intel.com>
573
574 * config/tc-i386.c (md_assemble): Use !intel_mnemonic instead
575 of SYSV386_COMPAT.
576
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5772008-01-03 H.J. Lu <hongjiu.lu@intel.com>
578
579 * gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
580 (cpu_flags_not): Likewise.
581 (cpu_flags_match): Updated to check 64bit and arch.
582 (set_code_flag): Remove cpu_arch_flags_not.
583 (set_16bit_gcc_code_flag): Likewise.
584 (set_cpu_arch): Likewise.
585 (md_begin): Likewise.
586 (parse_insn): Call cpu_flags_match to check 64bit and arch.
587 (match_template): Likewise.
588
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5892008-01-03 Jakub Jelinek <jakub@redhat.com>
590
591 * config/tc-i386.c (process_drex): Initialize modrm_reg and
592 modrm_regmem to 0 instead of None.
593
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5942008-01-03 H.J. Lu <hongjiu.lu@intel.com>
595
596 * config/tc-i386.c (match_template): Use the xmmword field
597 instead of no_xsuf.
598
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5992008-01-02 H.J. Lu <hongjiu.lu@intel.com>
600
601 * config/tc-i386.c (process_suffix): Fix a typo.
602
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6032008-01-02 H.J. Lu <hongjiu.lu@intel.com>
604
605 PR gas/5534
606 * config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX.
607 Check memory size in Intel mode.
608 (process_suffix): Handle XMMWORD_MNEM_SUFFIX.
609 (intel_e09): Likewise.
610
611 * config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New.
612
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6132008-01-02 Catherine Moore <clm@codesourcery.com>
614
615 * config/tc-mips.c (mips_ip): Check operands on jalr instruction.
616
6c7ac64e 617For older changes see ChangeLog-2007
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618\f
619Local Variables:
620mode: change-log
621left-margin: 8
622fill-column: 74
623version-control: never
624End:
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