Commit | Line | Data |
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07c1b327 | 1 | /* bfin-aux.h ADI Blackfin Header file for gas\r |
ec2655a6 | 2 | Copyright 2005, 2007\r |
07c1b327 CM |
3 | Free Software Foundation, Inc.\r |
4 | \r | |
5 | This file is part of GAS, the GNU Assembler.\r | |
6 | \r | |
7 | GAS is free software; you can redistribute it and/or modify\r | |
8 | it under the terms of the GNU General Public License as published by\r | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option)\r |
07c1b327 CM |
10 | any later version.\r |
11 | \r | |
12 | GAS is distributed in the hope that it will be useful,\r | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of\r | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r | |
15 | GNU General Public License for more details.\r | |
16 | \r | |
17 | You should have received a copy of the GNU General Public License\r | |
18 | along with GAS; see the file COPYING. If not, write to the Free\r | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA\r | |
20 | 02110-1301, USA. */\r | |
21 | \r | |
22 | #include "bfin-defs.h"\r | |
23 | \r | |
24 | #define REG_T Register *\r | |
25 | \r | |
26 | INSTR_T\r | |
27 | bfin_gen_dsp32mac (int op1, int mm, int mmod, int w1, int p,\r | |
28 | int h01, int h11, int h00, int h10,\r | |
29 | int op0, REG_T dst, REG_T src0, REG_T src1, int w0);\r | |
30 | \r | |
31 | INSTR_T\r | |
32 | bfin_gen_dsp32mult (int op1, int mm, int mmod, int w1, int p,\r | |
33 | int h01, int h11, int h00, int h10,\r | |
34 | int op0, REG_T dst, REG_T src0, REG_T src1, int w0);\r | |
35 | \r | |
36 | INSTR_T\r | |
37 | bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,\r | |
38 | REG_T dst0, REG_T dst1, REG_T src0, REG_T src1);\r | |
39 | \r | |
40 | INSTR_T\r | |
41 | bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, REG_T src1,\r | |
42 | int sop, int hls);\r | |
43 | \r | |
44 | INSTR_T\r | |
45 | bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, REG_T src1,\r | |
46 | int sop, int hls);\r | |
47 | \r | |
48 | INSTR_T\r | |
49 | bfin_gen_ldimmhalf (REG_T reg, int h, int s, int z, Expr_Node *hword,\r | |
50 | int reloc);\r | |
51 | \r | |
52 | INSTR_T\r | |
53 | bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int w, int sz, int z,\r | |
54 | Expr_Node *offset);\r | |
55 | \r | |
56 | INSTR_T\r | |
57 | bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int z, int w);\r | |
58 | \r | |
59 | INSTR_T\r | |
60 | bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node *offset, int w, int op);\r | |
61 | \r | |
62 | INSTR_T\r | |
63 | bfin_gen_ldstiifp (REG_T reg, Expr_Node *offset, int w);\r | |
64 | \r | |
65 | INSTR_T\r | |
66 | bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int w, REG_T idx);\r | |
67 | \r | |
68 | INSTR_T\r | |
69 | bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int w, int m);\r | |
70 | \r | |
71 | INSTR_T\r | |
72 | bfin_gen_alu2op (REG_T dst, REG_T src, int opc);\r | |
73 | \r | |
74 | INSTR_T\r | |
75 | bfin_gen_compi2opd (REG_T dst, int src, int op);\r | |
76 | \r | |
77 | INSTR_T\r | |
78 | bfin_gen_compi2opp (REG_T dst, int src, int op);\r | |
79 | \r | |
80 | INSTR_T\r | |
81 | bfin_gen_dagmodik (REG_T i, int op);\r | |
82 | \r | |
83 | INSTR_T\r | |
84 | bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br);\r | |
85 | \r | |
86 | INSTR_T\r | |
87 | bfin_gen_ptr2op (REG_T dst, REG_T src, int opc);\r | |
88 | \r | |
89 | INSTR_T\r | |
90 | bfin_gen_logi2op (int dst, int src, int opc);\r | |
91 | \r | |
92 | INSTR_T\r | |
93 | bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc);\r | |
94 | \r | |
95 | INSTR_T\r | |
96 | bfin_gen_ccmv (REG_T src, REG_T dst, int t);\r | |
97 | \r | |
98 | INSTR_T\r | |
99 | bfin_gen_ccflag (REG_T x, int y, int opc, int i, int g);\r | |
100 | \r | |
101 | INSTR_T\r | |
102 | bfin_gen_cc2stat (int cbit, int op, int d);\r | |
103 | \r | |
104 | INSTR_T\r | |
105 | bfin_gen_regmv (REG_T src, REG_T dst);\r | |
106 | \r | |
107 | INSTR_T\r | |
108 | bfin_gen_cc2dreg (int op, REG_T reg);\r | |
109 | \r | |
110 | INSTR_T\r | |
111 | bfin_gen_brcc (int t, int b, Expr_Node *offset);\r | |
112 | \r | |
113 | INSTR_T\r | |
114 | bfin_gen_ujump (Expr_Node *offset);\r | |
115 | \r | |
116 | INSTR_T\r | |
117 | bfin_gen_cactrl (REG_T reg, int a, int op);\r | |
118 | \r | |
119 | INSTR_T\r | |
120 | bfin_gen_progctrl (int prgfunc, int poprnd);\r | |
121 | \r | |
122 | INSTR_T\r | |
123 | bfin_gen_loopsetup (Expr_Node *soffset, REG_T c, int rop,\r | |
124 | Expr_Node *eoffset, REG_T reg);\r | |
125 | \r | |
126 | INSTR_T\r | |
127 | bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg);\r | |
128 | \r | |
129 | INSTR_T\r | |
130 | bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int w);\r | |
131 | \r | |
132 | INSTR_T\r | |
133 | bfin_gen_pushpopreg (REG_T reg, int w);\r | |
134 | \r | |
135 | INSTR_T\r | |
136 | bfin_gen_calla (Expr_Node *addr, int s);\r | |
137 | \r | |
138 | INSTR_T\r | |
139 | bfin_gen_linkage (int r, int framesize);\r | |
140 | \r | |
141 | INSTR_T\r | |
142 | bfin_gen_pseudodbg (int fn, int reg, int grp);\r | |
143 | \r | |
144 | INSTR_T\r | |
145 | bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected);\r | |
146 | \r | |
147 | bfd_boolean\r | |
148 | bfin_resource_conflict (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2);\r | |
149 | \r | |
150 | INSTR_T\r | |
151 | bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2);\r |