[binutils][aarch64] New SVE_ADDR_ZX operand.
[deliverable/binutils-gdb.git] / gas / config / tc-aarch64.c
CommitLineData
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1/* tc-aarch64.c -- Assemble for the AArch64 ISA
2
82704155 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
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4 Contributed by ARM Ltd.
5
6 This file is part of GAS.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#include "as.h"
23#include <limits.h>
24#include <stdarg.h>
25#include "bfd_stdint.h"
26#define NO_RELOC 0
27#include "safe-ctype.h"
28#include "subsegs.h"
29#include "obstack.h"
30
31#ifdef OBJ_ELF
32#include "elf/aarch64.h"
33#include "dw2gencfi.h"
34#endif
35
36#include "dwarf2dbg.h"
37
38/* Types of processor to assemble for. */
39#ifndef CPU_DEFAULT
40#define CPU_DEFAULT AARCH64_ARCH_V8
41#endif
42
43#define streq(a, b) (strcmp (a, b) == 0)
44
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JW
45#define END_OF_INSN '\0'
46
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47static aarch64_feature_set cpu_variant;
48
49/* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
51 assembly flags. */
52static const aarch64_feature_set *mcpu_cpu_opt = NULL;
53static const aarch64_feature_set *march_cpu_opt = NULL;
54
55/* Constants for known architecture features. */
56static const aarch64_feature_set cpu_default = CPU_DEFAULT;
57
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58/* Currently active instruction sequence. */
59static aarch64_instr_sequence *insn_sequence = NULL;
60
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61#ifdef OBJ_ELF
62/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63static symbolS *GOT_symbol;
cec5225b 64
69091a2c
YZ
65/* Which ABI to use. */
66enum aarch64_abi_type
67{
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68 AARCH64_ABI_NONE = 0,
69 AARCH64_ABI_LP64 = 1,
70 AARCH64_ABI_ILP32 = 2
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71};
72
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JW
73#ifndef DEFAULT_ARCH
74#define DEFAULT_ARCH "aarch64"
75#endif
76
77/* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78static const char *default_arch = DEFAULT_ARCH;
79
69091a2c 80/* AArch64 ABI for the output file. */
3c0367d0 81static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_NONE;
69091a2c 82
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83/* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
69091a2c 87#define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
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88#endif
89
f06935a5 90enum vector_el_type
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91{
92 NT_invtype = -1,
93 NT_b,
94 NT_h,
95 NT_s,
96 NT_d,
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97 NT_q,
98 NT_zero,
99 NT_merge
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100};
101
8f9a77af 102/* Bits for DEFINED field in vector_type_el. */
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103#define NTA_HASTYPE 1
104#define NTA_HASINDEX 2
105#define NTA_HASVARWIDTH 4
a06ea964 106
8f9a77af 107struct vector_type_el
a06ea964 108{
f06935a5 109 enum vector_el_type type;
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110 unsigned char defined;
111 unsigned width;
112 int64_t index;
113};
114
115#define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
116
117struct reloc
118{
119 bfd_reloc_code_real_type type;
120 expressionS exp;
121 int pc_rel;
122 enum aarch64_opnd opnd;
123 uint32_t flags;
124 unsigned need_libopcodes_p : 1;
125};
126
127struct aarch64_instruction
128{
129 /* libopcodes structure for instruction intermediate representation. */
130 aarch64_inst base;
131 /* Record assembly errors found during the parsing. */
132 struct
133 {
134 enum aarch64_operand_error_kind kind;
135 const char *error;
136 } parsing_error;
137 /* The condition that appears in the assembly line. */
138 int cond;
139 /* Relocation information (including the GAS internal fixup). */
140 struct reloc reloc;
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool : 1;
143};
144
145typedef struct aarch64_instruction aarch64_instruction;
146
147static aarch64_instruction inst;
148
149static bfd_boolean parse_operands (char *, const aarch64_opcode *);
150static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
151
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152#ifdef OBJ_ELF
153# define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
155#else
156static struct aarch64_instr_sequence now_instr_sequence;
157#endif
158
33eaf5de 159/* Diagnostics inline function utilities.
a06ea964 160
33eaf5de 161 These are lightweight utilities which should only be called by parse_operands
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162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
171
33eaf5de 172 Remember that the objective is to help GAS pick up the most appropriate
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173 error message in the case of multiple templates, e.g. FMOV which has 8
174 templates. */
175
176static inline void
177clear_error (void)
178{
179 inst.parsing_error.kind = AARCH64_OPDE_NIL;
180 inst.parsing_error.error = NULL;
181}
182
183static inline bfd_boolean
184error_p (void)
185{
186 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
187}
188
189static inline const char *
190get_error_message (void)
191{
192 return inst.parsing_error.error;
193}
194
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195static inline enum aarch64_operand_error_kind
196get_error_kind (void)
197{
198 return inst.parsing_error.kind;
199}
200
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201static inline void
202set_error (enum aarch64_operand_error_kind kind, const char *error)
203{
204 inst.parsing_error.kind = kind;
205 inst.parsing_error.error = error;
206}
207
208static inline void
209set_recoverable_error (const char *error)
210{
211 set_error (AARCH64_OPDE_RECOVERABLE, error);
212}
213
214/* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
216static inline void
217set_default_error (void)
218{
219 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
220}
221
222static inline void
223set_syntax_error (const char *error)
224{
225 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
226}
227
228static inline void
229set_first_syntax_error (const char *error)
230{
231 if (! error_p ())
232 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
233}
234
235static inline void
236set_fatal_syntax_error (const char *error)
237{
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
239}
240\f
241/* Number of littlenums required to hold an extended precision number. */
242#define MAX_LITTLENUMS 6
243
244/* Return value for certain parsers when the parsing fails; those parsers
245 return the information of the parsed result, e.g. register number, on
246 success. */
247#define PARSE_FAIL -1
248
249/* This is an invalid condition code that means no conditional field is
250 present. */
251#define COND_ALWAYS 0x10
252
253typedef struct
254{
255 const char *template;
256 unsigned long value;
257} asm_barrier_opt;
258
259typedef struct
260{
261 const char *template;
262 uint32_t value;
263} asm_nzcv;
264
265struct reloc_entry
266{
267 char *name;
268 bfd_reloc_code_real_type reloc;
269};
270
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271/* Macros to define the register types and masks for the purpose
272 of parsing. */
273
274#undef AARCH64_REG_TYPES
275#define AARCH64_REG_TYPES \
276 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
277 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
278 BASIC_REG_TYPE(SP_32) /* wsp */ \
279 BASIC_REG_TYPE(SP_64) /* sp */ \
280 BASIC_REG_TYPE(Z_32) /* wzr */ \
281 BASIC_REG_TYPE(Z_64) /* xzr */ \
282 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
283 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
284 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
285 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
286 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
a06ea964 287 BASIC_REG_TYPE(VN) /* v[0-31] */ \
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288 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
289 BASIC_REG_TYPE(PN) /* p[0-15] */ \
e1b988bb 290 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
a06ea964 291 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
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292 /* Typecheck: same, plus SVE registers. */ \
293 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
294 | REG_TYPE(ZN)) \
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295 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
296 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
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298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
301 | REG_TYPE(ZN)) \
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302 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
303 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
305 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
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306 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Typecheck: any [BHSDQ]P FP. */ \
310 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
311 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
e1b988bb 312 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
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313 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
315 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
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317 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
318 be used for SVE instructions, since Zn and Pn are valid symbols \
c0890d26 319 in other contexts. */ \
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JB
320 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
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RS
322 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
323 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
325 | REG_TYPE(ZN) | REG_TYPE(PN)) \
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326 /* Any integer register; used for error messages only. */ \
327 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
329 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
330 /* Pseudo type to mark the end of the enumerator sequence. */ \
331 BASIC_REG_TYPE(MAX)
332
333#undef BASIC_REG_TYPE
334#define BASIC_REG_TYPE(T) REG_TYPE_##T,
335#undef MULTI_REG_TYPE
336#define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
337
338/* Register type enumerators. */
8a0b252a 339typedef enum aarch64_reg_type_
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340{
341 /* A list of REG_TYPE_*. */
342 AARCH64_REG_TYPES
343} aarch64_reg_type;
344
345#undef BASIC_REG_TYPE
346#define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
347#undef REG_TYPE
348#define REG_TYPE(T) (1 << REG_TYPE_##T)
349#undef MULTI_REG_TYPE
350#define MULTI_REG_TYPE(T,V) V,
351
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352/* Structure for a hash table entry for a register. */
353typedef struct
354{
355 const char *name;
356 unsigned char number;
357 ENUM_BITFIELD (aarch64_reg_type_) type : 8;
358 unsigned char builtin;
359} reg_entry;
360
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361/* Values indexed by aarch64_reg_type to assist the type checking. */
362static const unsigned reg_type_masks[] =
363{
364 AARCH64_REG_TYPES
365};
366
367#undef BASIC_REG_TYPE
368#undef REG_TYPE
369#undef MULTI_REG_TYPE
370#undef AARCH64_REG_TYPES
371
372/* Diagnostics used when we don't get a register of the expected type.
373 Note: this has to synchronized with aarch64_reg_type definitions
374 above. */
375static const char *
376get_reg_expected_msg (aarch64_reg_type reg_type)
377{
378 const char *msg;
379
380 switch (reg_type)
381 {
382 case REG_TYPE_R_32:
383 msg = N_("integer 32-bit register expected");
384 break;
385 case REG_TYPE_R_64:
386 msg = N_("integer 64-bit register expected");
387 break;
388 case REG_TYPE_R_N:
389 msg = N_("integer register expected");
390 break;
e1b988bb
RS
391 case REG_TYPE_R64_SP:
392 msg = N_("64-bit integer or SP register expected");
393 break;
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RS
394 case REG_TYPE_SVE_BASE:
395 msg = N_("base register expected");
396 break;
e1b988bb
RS
397 case REG_TYPE_R_Z:
398 msg = N_("integer or zero register expected");
399 break;
4df068de
RS
400 case REG_TYPE_SVE_OFFSET:
401 msg = N_("offset register expected");
402 break;
e1b988bb
RS
403 case REG_TYPE_R_SP:
404 msg = N_("integer or SP register expected");
405 break;
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406 case REG_TYPE_R_Z_SP:
407 msg = N_("integer, zero or SP register expected");
408 break;
409 case REG_TYPE_FP_B:
410 msg = N_("8-bit SIMD scalar register expected");
411 break;
412 case REG_TYPE_FP_H:
413 msg = N_("16-bit SIMD scalar or floating-point half precision "
414 "register expected");
415 break;
416 case REG_TYPE_FP_S:
417 msg = N_("32-bit SIMD scalar or floating-point single precision "
418 "register expected");
419 break;
420 case REG_TYPE_FP_D:
421 msg = N_("64-bit SIMD scalar or floating-point double precision "
422 "register expected");
423 break;
424 case REG_TYPE_FP_Q:
425 msg = N_("128-bit SIMD scalar or floating-point quad precision "
426 "register expected");
427 break;
a06ea964 428 case REG_TYPE_R_Z_BHSDQ_V:
5b2b928e 429 case REG_TYPE_R_Z_SP_BHSDQ_VZP:
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430 msg = N_("register expected");
431 break;
432 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
433 msg = N_("SIMD scalar or floating-point register expected");
434 break;
435 case REG_TYPE_VN: /* any V reg */
436 msg = N_("vector register expected");
437 break;
f11ad6bc
RS
438 case REG_TYPE_ZN:
439 msg = N_("SVE vector register expected");
440 break;
441 case REG_TYPE_PN:
442 msg = N_("SVE predicate register expected");
443 break;
a06ea964
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444 default:
445 as_fatal (_("invalid register type %d"), reg_type);
446 }
447 return msg;
448}
449
450/* Some well known registers that we refer to directly elsewhere. */
451#define REG_SP 31
c469c864 452#define REG_ZR 31
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453
454/* Instructions take 4 bytes in the object file. */
455#define INSN_SIZE 4
456
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457static struct hash_control *aarch64_ops_hsh;
458static struct hash_control *aarch64_cond_hsh;
459static struct hash_control *aarch64_shift_hsh;
460static struct hash_control *aarch64_sys_regs_hsh;
461static struct hash_control *aarch64_pstatefield_hsh;
462static struct hash_control *aarch64_sys_regs_ic_hsh;
463static struct hash_control *aarch64_sys_regs_dc_hsh;
464static struct hash_control *aarch64_sys_regs_at_hsh;
465static struct hash_control *aarch64_sys_regs_tlbi_hsh;
2ac435d4 466static struct hash_control *aarch64_sys_regs_sr_hsh;
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467static struct hash_control *aarch64_reg_hsh;
468static struct hash_control *aarch64_barrier_opt_hsh;
469static struct hash_control *aarch64_nzcv_hsh;
470static struct hash_control *aarch64_pldop_hsh;
1e6f4800 471static struct hash_control *aarch64_hint_opt_hsh;
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472
473/* Stuff needed to resolve the label ambiguity
474 As:
475 ...
476 label: <insn>
477 may differ from:
478 ...
479 label:
480 <insn> */
481
482static symbolS *last_label_seen;
483
484/* Literal pool structure. Held on a per-section
485 and per-sub-section basis. */
486
487#define MAX_LITERAL_POOL_SIZE 1024
55d9b4c1
NC
488typedef struct literal_expression
489{
490 expressionS exp;
491 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
492 LITTLENUM_TYPE * bignum;
493} literal_expression;
494
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495typedef struct literal_pool
496{
55d9b4c1 497 literal_expression literals[MAX_LITERAL_POOL_SIZE];
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498 unsigned int next_free_entry;
499 unsigned int id;
500 symbolS *symbol;
501 segT section;
502 subsegT sub_section;
503 int size;
504 struct literal_pool *next;
505} literal_pool;
506
507/* Pointer to a linked list of literal pools. */
508static literal_pool *list_of_pools = NULL;
509\f
510/* Pure syntax. */
511
512/* This array holds the chars that always start a comment. If the
513 pre-processor is disabled, these aren't very useful. */
514const char comment_chars[] = "";
515
516/* This array holds the chars that only start a comment at the beginning of
517 a line. If the line seems to have the form '# 123 filename'
518 .line and .file directives will appear in the pre-processed output. */
519/* Note that input_file.c hand checks for '#' at the beginning of the
520 first line of the input file. This is because the compiler outputs
521 #NO_APP at the beginning of its output. */
522/* Also note that comments like this one will always work. */
523const char line_comment_chars[] = "#";
524
525const char line_separator_chars[] = ";";
526
527/* Chars that can be used to separate mant
528 from exp in floating point numbers. */
529const char EXP_CHARS[] = "eE";
530
531/* Chars that mean this number is a floating point constant. */
532/* As in 0f12.456 */
533/* or 0d1.2345e12 */
534
535const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
536
537/* Prefix character that indicates the start of an immediate value. */
538#define is_immediate_prefix(C) ((C) == '#')
539
540/* Separator character handling. */
541
542#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543
544static inline bfd_boolean
545skip_past_char (char **str, char c)
546{
547 if (**str == c)
548 {
549 (*str)++;
550 return TRUE;
551 }
552 else
553 return FALSE;
554}
555
556#define skip_past_comma(str) skip_past_char (str, ',')
557
558/* Arithmetic expressions (possibly involving symbols). */
559
a06ea964
NC
560static bfd_boolean in_my_get_expression_p = FALSE;
561
562/* Third argument to my_get_expression. */
563#define GE_NO_PREFIX 0
564#define GE_OPT_PREFIX 1
565
566/* Return TRUE if the string pointed by *STR is successfully parsed
567 as an valid expression; *EP will be filled with the information of
568 such an expression. Otherwise return FALSE. */
569
570static bfd_boolean
571my_get_expression (expressionS * ep, char **str, int prefix_mode,
572 int reject_absent)
573{
574 char *save_in;
575 segT seg;
576 int prefix_present_p = 0;
577
578 switch (prefix_mode)
579 {
580 case GE_NO_PREFIX:
581 break;
582 case GE_OPT_PREFIX:
583 if (is_immediate_prefix (**str))
584 {
585 (*str)++;
586 prefix_present_p = 1;
587 }
588 break;
589 default:
590 abort ();
591 }
592
593 memset (ep, 0, sizeof (expressionS));
594
595 save_in = input_line_pointer;
596 input_line_pointer = *str;
597 in_my_get_expression_p = TRUE;
598 seg = expression (ep);
599 in_my_get_expression_p = FALSE;
600
601 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
602 {
603 /* We found a bad expression in md_operand(). */
604 *str = input_line_pointer;
605 input_line_pointer = save_in;
606 if (prefix_present_p && ! error_p ())
607 set_fatal_syntax_error (_("bad expression"));
608 else
609 set_first_syntax_error (_("bad expression"));
610 return FALSE;
611 }
612
613#ifdef OBJ_AOUT
614 if (seg != absolute_section
615 && seg != text_section
616 && seg != data_section
617 && seg != bss_section && seg != undefined_section)
618 {
619 set_syntax_error (_("bad segment"));
620 *str = input_line_pointer;
621 input_line_pointer = save_in;
622 return FALSE;
623 }
624#else
625 (void) seg;
626#endif
627
a06ea964
NC
628 *str = input_line_pointer;
629 input_line_pointer = save_in;
630 return TRUE;
631}
632
633/* Turn a string in input_line_pointer into a floating point constant
634 of type TYPE, and store the appropriate bytes in *LITP. The number
635 of LITTLENUMS emitted is stored in *SIZEP. An error message is
636 returned, or NULL on OK. */
637
6d4af3c2 638const char *
a06ea964
NC
639md_atof (int type, char *litP, int *sizeP)
640{
641 return ieee_md_atof (type, litP, sizeP, target_big_endian);
642}
643
644/* We handle all bad expressions here, so that we can report the faulty
645 instruction in the error message. */
646void
647md_operand (expressionS * exp)
648{
649 if (in_my_get_expression_p)
650 exp->X_op = O_illegal;
651}
652
653/* Immediate values. */
654
655/* Errors may be set multiple times during parsing or bit encoding
656 (particularly in the Neon bits), but usually the earliest error which is set
657 will be the most meaningful. Avoid overwriting it with later (cascading)
658 errors by calling this function. */
659
660static void
661first_error (const char *error)
662{
663 if (! error_p ())
664 set_syntax_error (error);
665}
666
2b0f3761 667/* Similar to first_error, but this function accepts formatted error
a06ea964
NC
668 message. */
669static void
670first_error_fmt (const char *format, ...)
671{
672 va_list args;
673 enum
674 { size = 100 };
675 /* N.B. this single buffer will not cause error messages for different
676 instructions to pollute each other; this is because at the end of
677 processing of each assembly line, error message if any will be
678 collected by as_bad. */
679 static char buffer[size];
680
681 if (! error_p ())
682 {
3e0baa28 683 int ret ATTRIBUTE_UNUSED;
a06ea964
NC
684 va_start (args, format);
685 ret = vsnprintf (buffer, size, format, args);
686 know (ret <= size - 1 && ret >= 0);
687 va_end (args);
688 set_syntax_error (buffer);
689 }
690}
691
692/* Register parsing. */
693
694/* Generic register parser which is called by other specialized
695 register parsers.
696 CCP points to what should be the beginning of a register name.
697 If it is indeed a valid register name, advance CCP over it and
698 return the reg_entry structure; otherwise return NULL.
699 It does not issue diagnostics. */
700
701static reg_entry *
702parse_reg (char **ccp)
703{
704 char *start = *ccp;
705 char *p;
706 reg_entry *reg;
707
708#ifdef REGISTER_PREFIX
709 if (*start != REGISTER_PREFIX)
710 return NULL;
711 start++;
712#endif
713
714 p = start;
715 if (!ISALPHA (*p) || !is_name_beginner (*p))
716 return NULL;
717
718 do
719 p++;
720 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
721
722 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
723
724 if (!reg)
725 return NULL;
726
727 *ccp = p;
728 return reg;
729}
730
731/* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
732 return FALSE. */
733static bfd_boolean
734aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
735{
e1b988bb 736 return (reg_type_masks[type] & (1 << reg->type)) != 0;
a06ea964
NC
737}
738
4df068de
RS
739/* Try to parse a base or offset register. Allow SVE base and offset
740 registers if REG_TYPE includes SVE registers. Return the register
741 entry on success, setting *QUALIFIER to the register qualifier.
742 Return null otherwise.
e1b988bb 743
a06ea964
NC
744 Note that this function does not issue any diagnostics. */
745
e1b988bb 746static const reg_entry *
4df068de
RS
747aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
748 aarch64_opnd_qualifier_t *qualifier)
a06ea964
NC
749{
750 char *str = *ccp;
751 const reg_entry *reg = parse_reg (&str);
752
753 if (reg == NULL)
e1b988bb 754 return NULL;
a06ea964
NC
755
756 switch (reg->type)
757 {
e1b988bb 758 case REG_TYPE_R_32:
a06ea964 759 case REG_TYPE_SP_32:
e1b988bb
RS
760 case REG_TYPE_Z_32:
761 *qualifier = AARCH64_OPND_QLF_W;
a06ea964 762 break;
e1b988bb 763
a06ea964 764 case REG_TYPE_R_64:
e1b988bb 765 case REG_TYPE_SP_64:
a06ea964 766 case REG_TYPE_Z_64:
e1b988bb 767 *qualifier = AARCH64_OPND_QLF_X;
a06ea964 768 break;
e1b988bb 769
4df068de
RS
770 case REG_TYPE_ZN:
771 if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) == 0
772 || str[0] != '.')
773 return NULL;
774 switch (TOLOWER (str[1]))
775 {
776 case 's':
777 *qualifier = AARCH64_OPND_QLF_S_S;
778 break;
779 case 'd':
780 *qualifier = AARCH64_OPND_QLF_S_D;
781 break;
782 default:
783 return NULL;
784 }
785 str += 2;
786 break;
787
a06ea964 788 default:
e1b988bb 789 return NULL;
a06ea964
NC
790 }
791
792 *ccp = str;
793
e1b988bb 794 return reg;
a06ea964
NC
795}
796
4df068de
RS
797/* Try to parse a base or offset register. Return the register entry
798 on success, setting *QUALIFIER to the register qualifier. Return null
799 otherwise.
800
801 Note that this function does not issue any diagnostics. */
802
803static const reg_entry *
804aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
805{
806 return aarch64_addr_reg_parse (ccp, REG_TYPE_R_Z_SP, qualifier);
807}
808
f11ad6bc
RS
809/* Parse the qualifier of a vector register or vector element of type
810 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
811 succeeds; otherwise return FALSE.
a06ea964
NC
812
813 Accept only one occurrence of:
65a55fbb 814 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
a06ea964
NC
815 b h s d q */
816static bfd_boolean
f11ad6bc
RS
817parse_vector_type_for_operand (aarch64_reg_type reg_type,
818 struct vector_type_el *parsed_type, char **str)
a06ea964
NC
819{
820 char *ptr = *str;
821 unsigned width;
822 unsigned element_size;
f06935a5 823 enum vector_el_type type;
a06ea964
NC
824
825 /* skip '.' */
d50c751e 826 gas_assert (*ptr == '.');
a06ea964
NC
827 ptr++;
828
f11ad6bc 829 if (reg_type == REG_TYPE_ZN || reg_type == REG_TYPE_PN || !ISDIGIT (*ptr))
a06ea964
NC
830 {
831 width = 0;
832 goto elt_size;
833 }
834 width = strtoul (ptr, &ptr, 10);
835 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
836 {
837 first_error_fmt (_("bad size %d in vector width specifier"), width);
838 return FALSE;
839 }
840
841elt_size:
842 switch (TOLOWER (*ptr))
843 {
844 case 'b':
845 type = NT_b;
846 element_size = 8;
847 break;
848 case 'h':
849 type = NT_h;
850 element_size = 16;
851 break;
852 case 's':
853 type = NT_s;
854 element_size = 32;
855 break;
856 case 'd':
857 type = NT_d;
858 element_size = 64;
859 break;
860 case 'q':
582e12bf 861 if (reg_type == REG_TYPE_ZN || width == 1)
a06ea964
NC
862 {
863 type = NT_q;
864 element_size = 128;
865 break;
866 }
867 /* fall through. */
868 default:
869 if (*ptr != '\0')
870 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
871 else
872 first_error (_("missing element size"));
873 return FALSE;
874 }
65a55fbb
TC
875 if (width != 0 && width * element_size != 64
876 && width * element_size != 128
877 && !(width == 2 && element_size == 16)
878 && !(width == 4 && element_size == 8))
a06ea964
NC
879 {
880 first_error_fmt (_
881 ("invalid element size %d and vector size combination %c"),
882 width, *ptr);
883 return FALSE;
884 }
885 ptr++;
886
887 parsed_type->type = type;
888 parsed_type->width = width;
889
890 *str = ptr;
891
892 return TRUE;
893}
894
d50c751e
RS
895/* *STR contains an SVE zero/merge predication suffix. Parse it into
896 *PARSED_TYPE and point *STR at the end of the suffix. */
897
898static bfd_boolean
899parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
900{
901 char *ptr = *str;
902
903 /* Skip '/'. */
904 gas_assert (*ptr == '/');
905 ptr++;
906 switch (TOLOWER (*ptr))
907 {
908 case 'z':
909 parsed_type->type = NT_zero;
910 break;
911 case 'm':
912 parsed_type->type = NT_merge;
913 break;
914 default:
915 if (*ptr != '\0' && *ptr != ',')
916 first_error_fmt (_("unexpected character `%c' in predication type"),
917 *ptr);
918 else
919 first_error (_("missing predication type"));
920 return FALSE;
921 }
922 parsed_type->width = 0;
923 *str = ptr + 1;
924 return TRUE;
925}
926
a06ea964
NC
927/* Parse a register of the type TYPE.
928
929 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
930 name or the parsed register is not of TYPE.
931
932 Otherwise return the register number, and optionally fill in the actual
933 type of the register in *RTYPE when multiple alternatives were given, and
934 return the register shape and element index information in *TYPEINFO.
935
936 IN_REG_LIST should be set with TRUE if the caller is parsing a register
937 list. */
938
939static int
940parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
8f9a77af 941 struct vector_type_el *typeinfo, bfd_boolean in_reg_list)
a06ea964
NC
942{
943 char *str = *ccp;
944 const reg_entry *reg = parse_reg (&str);
8f9a77af
RS
945 struct vector_type_el atype;
946 struct vector_type_el parsetype;
a06ea964
NC
947 bfd_boolean is_typed_vecreg = FALSE;
948
949 atype.defined = 0;
950 atype.type = NT_invtype;
951 atype.width = -1;
952 atype.index = 0;
953
954 if (reg == NULL)
955 {
956 if (typeinfo)
957 *typeinfo = atype;
958 set_default_error ();
959 return PARSE_FAIL;
960 }
961
962 if (! aarch64_check_reg_type (reg, type))
963 {
964 DEBUG_TRACE ("reg type check failed");
965 set_default_error ();
966 return PARSE_FAIL;
967 }
968 type = reg->type;
969
f11ad6bc 970 if ((type == REG_TYPE_VN || type == REG_TYPE_ZN || type == REG_TYPE_PN)
d50c751e 971 && (*str == '.' || (type == REG_TYPE_PN && *str == '/')))
a06ea964 972 {
d50c751e
RS
973 if (*str == '.')
974 {
975 if (!parse_vector_type_for_operand (type, &parsetype, &str))
976 return PARSE_FAIL;
977 }
978 else
979 {
980 if (!parse_predication_for_operand (&parsetype, &str))
981 return PARSE_FAIL;
982 }
a235d3ae 983
a06ea964
NC
984 /* Register if of the form Vn.[bhsdq]. */
985 is_typed_vecreg = TRUE;
986
f11ad6bc
RS
987 if (type == REG_TYPE_ZN || type == REG_TYPE_PN)
988 {
989 /* The width is always variable; we don't allow an integer width
990 to be specified. */
991 gas_assert (parsetype.width == 0);
992 atype.defined |= NTA_HASVARWIDTH | NTA_HASTYPE;
993 }
994 else if (parsetype.width == 0)
a06ea964
NC
995 /* Expect index. In the new scheme we cannot have
996 Vn.[bhsdq] represent a scalar. Therefore any
997 Vn.[bhsdq] should have an index following it.
33eaf5de 998 Except in reglists of course. */
a06ea964
NC
999 atype.defined |= NTA_HASINDEX;
1000 else
1001 atype.defined |= NTA_HASTYPE;
1002
1003 atype.type = parsetype.type;
1004 atype.width = parsetype.width;
1005 }
1006
1007 if (skip_past_char (&str, '['))
1008 {
1009 expressionS exp;
1010
1011 /* Reject Sn[index] syntax. */
1012 if (!is_typed_vecreg)
1013 {
1014 first_error (_("this type of register can't be indexed"));
1015 return PARSE_FAIL;
1016 }
1017
535b785f 1018 if (in_reg_list)
a06ea964
NC
1019 {
1020 first_error (_("index not allowed inside register list"));
1021 return PARSE_FAIL;
1022 }
1023
1024 atype.defined |= NTA_HASINDEX;
1025
1026 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1027
1028 if (exp.X_op != O_constant)
1029 {
1030 first_error (_("constant expression required"));
1031 return PARSE_FAIL;
1032 }
1033
1034 if (! skip_past_char (&str, ']'))
1035 return PARSE_FAIL;
1036
1037 atype.index = exp.X_add_number;
1038 }
1039 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
1040 {
1041 /* Indexed vector register expected. */
1042 first_error (_("indexed vector register expected"));
1043 return PARSE_FAIL;
1044 }
1045
1046 /* A vector reg Vn should be typed or indexed. */
1047 if (type == REG_TYPE_VN && atype.defined == 0)
1048 {
1049 first_error (_("invalid use of vector register"));
1050 }
1051
1052 if (typeinfo)
1053 *typeinfo = atype;
1054
1055 if (rtype)
1056 *rtype = type;
1057
1058 *ccp = str;
1059
1060 return reg->number;
1061}
1062
1063/* Parse register.
1064
1065 Return the register number on success; return PARSE_FAIL otherwise.
1066
1067 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1068 the register (e.g. NEON double or quad reg when either has been requested).
1069
1070 If this is a NEON vector register with additional type information, fill
1071 in the struct pointed to by VECTYPE (if non-NULL).
1072
1073 This parser does not handle register list. */
1074
1075static int
1076aarch64_reg_parse (char **ccp, aarch64_reg_type type,
8f9a77af 1077 aarch64_reg_type *rtype, struct vector_type_el *vectype)
a06ea964 1078{
8f9a77af 1079 struct vector_type_el atype;
a06ea964
NC
1080 char *str = *ccp;
1081 int reg = parse_typed_reg (&str, type, rtype, &atype,
1082 /*in_reg_list= */ FALSE);
1083
1084 if (reg == PARSE_FAIL)
1085 return PARSE_FAIL;
1086
1087 if (vectype)
1088 *vectype = atype;
1089
1090 *ccp = str;
1091
1092 return reg;
1093}
1094
1095static inline bfd_boolean
8f9a77af 1096eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
a06ea964
NC
1097{
1098 return
1099 e1.type == e2.type
1100 && e1.defined == e2.defined
1101 && e1.width == e2.width && e1.index == e2.index;
1102}
1103
10d76650
RS
1104/* This function parses a list of vector registers of type TYPE.
1105 On success, it returns the parsed register list information in the
1106 following encoded format:
a06ea964
NC
1107
1108 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1109 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1110
1111 The information of the register shape and/or index is returned in
1112 *VECTYPE.
1113
1114 It returns PARSE_FAIL if the register list is invalid.
1115
1116 The list contains one to four registers.
1117 Each register can be one of:
1118 <Vt>.<T>[<index>]
1119 <Vt>.<T>
1120 All <T> should be identical.
1121 All <index> should be identical.
1122 There are restrictions on <Vt> numbers which are checked later
1123 (by reg_list_valid_p). */
1124
1125static int
10d76650
RS
1126parse_vector_reg_list (char **ccp, aarch64_reg_type type,
1127 struct vector_type_el *vectype)
a06ea964
NC
1128{
1129 char *str = *ccp;
1130 int nb_regs;
8f9a77af 1131 struct vector_type_el typeinfo, typeinfo_first;
a06ea964
NC
1132 int val, val_range;
1133 int in_range;
1134 int ret_val;
1135 int i;
1136 bfd_boolean error = FALSE;
1137 bfd_boolean expect_index = FALSE;
1138
1139 if (*str != '{')
1140 {
1141 set_syntax_error (_("expecting {"));
1142 return PARSE_FAIL;
1143 }
1144 str++;
1145
1146 nb_regs = 0;
1147 typeinfo_first.defined = 0;
1148 typeinfo_first.type = NT_invtype;
1149 typeinfo_first.width = -1;
1150 typeinfo_first.index = 0;
1151 ret_val = 0;
1152 val = -1;
1153 val_range = -1;
1154 in_range = 0;
1155 do
1156 {
1157 if (in_range)
1158 {
1159 str++; /* skip over '-' */
1160 val_range = val;
1161 }
10d76650 1162 val = parse_typed_reg (&str, type, NULL, &typeinfo,
a06ea964
NC
1163 /*in_reg_list= */ TRUE);
1164 if (val == PARSE_FAIL)
1165 {
1166 set_first_syntax_error (_("invalid vector register in list"));
1167 error = TRUE;
1168 continue;
1169 }
1170 /* reject [bhsd]n */
f11ad6bc 1171 if (type == REG_TYPE_VN && typeinfo.defined == 0)
a06ea964
NC
1172 {
1173 set_first_syntax_error (_("invalid scalar register in list"));
1174 error = TRUE;
1175 continue;
1176 }
1177
1178 if (typeinfo.defined & NTA_HASINDEX)
1179 expect_index = TRUE;
1180
1181 if (in_range)
1182 {
1183 if (val < val_range)
1184 {
1185 set_first_syntax_error
1186 (_("invalid range in vector register list"));
1187 error = TRUE;
1188 }
1189 val_range++;
1190 }
1191 else
1192 {
1193 val_range = val;
1194 if (nb_regs == 0)
1195 typeinfo_first = typeinfo;
8f9a77af 1196 else if (! eq_vector_type_el (typeinfo_first, typeinfo))
a06ea964
NC
1197 {
1198 set_first_syntax_error
1199 (_("type mismatch in vector register list"));
1200 error = TRUE;
1201 }
1202 }
1203 if (! error)
1204 for (i = val_range; i <= val; i++)
1205 {
1206 ret_val |= i << (5 * nb_regs);
1207 nb_regs++;
1208 }
1209 in_range = 0;
1210 }
1211 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1212
1213 skip_whitespace (str);
1214 if (*str != '}')
1215 {
1216 set_first_syntax_error (_("end of vector register list not found"));
1217 error = TRUE;
1218 }
1219 str++;
1220
1221 skip_whitespace (str);
1222
1223 if (expect_index)
1224 {
1225 if (skip_past_char (&str, '['))
1226 {
1227 expressionS exp;
1228
1229 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1230 if (exp.X_op != O_constant)
1231 {
1232 set_first_syntax_error (_("constant expression required."));
1233 error = TRUE;
1234 }
1235 if (! skip_past_char (&str, ']'))
1236 error = TRUE;
1237 else
1238 typeinfo_first.index = exp.X_add_number;
1239 }
1240 else
1241 {
1242 set_first_syntax_error (_("expected index"));
1243 error = TRUE;
1244 }
1245 }
1246
1247 if (nb_regs > 4)
1248 {
1249 set_first_syntax_error (_("too many registers in vector register list"));
1250 error = TRUE;
1251 }
1252 else if (nb_regs == 0)
1253 {
1254 set_first_syntax_error (_("empty vector register list"));
1255 error = TRUE;
1256 }
1257
1258 *ccp = str;
1259 if (! error)
1260 *vectype = typeinfo_first;
1261
1262 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1263}
1264
1265/* Directives: register aliases. */
1266
1267static reg_entry *
1268insert_reg_alias (char *str, int number, aarch64_reg_type type)
1269{
1270 reg_entry *new;
1271 const char *name;
1272
1273 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1274 {
1275 if (new->builtin)
1276 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1277 str);
1278
1279 /* Only warn about a redefinition if it's not defined as the
1280 same register. */
1281 else if (new->number != number || new->type != type)
1282 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1283
1284 return NULL;
1285 }
1286
1287 name = xstrdup (str);
add39d23 1288 new = XNEW (reg_entry);
a06ea964
NC
1289
1290 new->name = name;
1291 new->number = number;
1292 new->type = type;
1293 new->builtin = FALSE;
1294
1295 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1296 abort ();
1297
1298 return new;
1299}
1300
1301/* Look for the .req directive. This is of the form:
1302
1303 new_register_name .req existing_register_name
1304
1305 If we find one, or if it looks sufficiently like one that we want to
1306 handle any error here, return TRUE. Otherwise return FALSE. */
1307
1308static bfd_boolean
1309create_register_alias (char *newname, char *p)
1310{
1311 const reg_entry *old;
1312 char *oldname, *nbuf;
1313 size_t nlen;
1314
1315 /* The input scrubber ensures that whitespace after the mnemonic is
1316 collapsed to single spaces. */
1317 oldname = p;
1318 if (strncmp (oldname, " .req ", 6) != 0)
1319 return FALSE;
1320
1321 oldname += 6;
1322 if (*oldname == '\0')
1323 return FALSE;
1324
1325 old = hash_find (aarch64_reg_hsh, oldname);
1326 if (!old)
1327 {
1328 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1329 return TRUE;
1330 }
1331
1332 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1333 the desired alias name, and p points to its end. If not, then
1334 the desired alias name is in the global original_case_string. */
1335#ifdef TC_CASE_SENSITIVE
1336 nlen = p - newname;
1337#else
1338 newname = original_case_string;
1339 nlen = strlen (newname);
1340#endif
1341
29a2809e 1342 nbuf = xmemdup0 (newname, nlen);
a06ea964
NC
1343
1344 /* Create aliases under the new name as stated; an all-lowercase
1345 version of the new name; and an all-uppercase version of the new
1346 name. */
1347 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1348 {
1349 for (p = nbuf; *p; p++)
1350 *p = TOUPPER (*p);
1351
1352 if (strncmp (nbuf, newname, nlen))
1353 {
1354 /* If this attempt to create an additional alias fails, do not bother
1355 trying to create the all-lower case alias. We will fail and issue
1356 a second, duplicate error message. This situation arises when the
1357 programmer does something like:
1358 foo .req r0
1359 Foo .req r1
1360 The second .req creates the "Foo" alias but then fails to create
1361 the artificial FOO alias because it has already been created by the
1362 first .req. */
1363 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
e1fa0163
NC
1364 {
1365 free (nbuf);
1366 return TRUE;
1367 }
a06ea964
NC
1368 }
1369
1370 for (p = nbuf; *p; p++)
1371 *p = TOLOWER (*p);
1372
1373 if (strncmp (nbuf, newname, nlen))
1374 insert_reg_alias (nbuf, old->number, old->type);
1375 }
1376
e1fa0163 1377 free (nbuf);
a06ea964
NC
1378 return TRUE;
1379}
1380
1381/* Should never be called, as .req goes between the alias and the
1382 register name, not at the beginning of the line. */
1383static void
1384s_req (int a ATTRIBUTE_UNUSED)
1385{
1386 as_bad (_("invalid syntax for .req directive"));
1387}
1388
1389/* The .unreq directive deletes an alias which was previously defined
1390 by .req. For example:
1391
1392 my_alias .req r11
1393 .unreq my_alias */
1394
1395static void
1396s_unreq (int a ATTRIBUTE_UNUSED)
1397{
1398 char *name;
1399 char saved_char;
1400
1401 name = input_line_pointer;
1402
1403 while (*input_line_pointer != 0
1404 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1405 ++input_line_pointer;
1406
1407 saved_char = *input_line_pointer;
1408 *input_line_pointer = 0;
1409
1410 if (!*name)
1411 as_bad (_("invalid syntax for .unreq directive"));
1412 else
1413 {
1414 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1415
1416 if (!reg)
1417 as_bad (_("unknown register alias '%s'"), name);
1418 else if (reg->builtin)
1419 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1420 name);
1421 else
1422 {
1423 char *p;
1424 char *nbuf;
1425
1426 hash_delete (aarch64_reg_hsh, name, FALSE);
1427 free ((char *) reg->name);
1428 free (reg);
1429
1430 /* Also locate the all upper case and all lower case versions.
1431 Do not complain if we cannot find one or the other as it
1432 was probably deleted above. */
1433
1434 nbuf = strdup (name);
1435 for (p = nbuf; *p; p++)
1436 *p = TOUPPER (*p);
1437 reg = hash_find (aarch64_reg_hsh, nbuf);
1438 if (reg)
1439 {
1440 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1441 free ((char *) reg->name);
1442 free (reg);
1443 }
1444
1445 for (p = nbuf; *p; p++)
1446 *p = TOLOWER (*p);
1447 reg = hash_find (aarch64_reg_hsh, nbuf);
1448 if (reg)
1449 {
1450 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1451 free ((char *) reg->name);
1452 free (reg);
1453 }
1454
1455 free (nbuf);
1456 }
1457 }
1458
1459 *input_line_pointer = saved_char;
1460 demand_empty_rest_of_line ();
1461}
1462
1463/* Directives: Instruction set selection. */
1464
1465#ifdef OBJ_ELF
1466/* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1467 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1468 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1469 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1470
1471/* Create a new mapping symbol for the transition to STATE. */
1472
1473static void
1474make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1475{
1476 symbolS *symbolP;
1477 const char *symname;
1478 int type;
1479
1480 switch (state)
1481 {
1482 case MAP_DATA:
1483 symname = "$d";
1484 type = BSF_NO_FLAGS;
1485 break;
1486 case MAP_INSN:
1487 symname = "$x";
1488 type = BSF_NO_FLAGS;
1489 break;
1490 default:
1491 abort ();
1492 }
1493
1494 symbolP = symbol_new (symname, now_seg, value, frag);
1495 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1496
1497 /* Save the mapping symbols for future reference. Also check that
1498 we do not place two mapping symbols at the same offset within a
1499 frag. We'll handle overlap between frags in
1500 check_mapping_symbols.
1501
1502 If .fill or other data filling directive generates zero sized data,
1503 the mapping symbol for the following code will have the same value
1504 as the one generated for the data filling directive. In this case,
1505 we replace the old symbol with the new one at the same address. */
1506 if (value == 0)
1507 {
1508 if (frag->tc_frag_data.first_map != NULL)
1509 {
1510 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1511 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1512 &symbol_lastP);
1513 }
1514 frag->tc_frag_data.first_map = symbolP;
1515 }
1516 if (frag->tc_frag_data.last_map != NULL)
1517 {
1518 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1519 S_GET_VALUE (symbolP));
1520 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1521 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1522 &symbol_lastP);
1523 }
1524 frag->tc_frag_data.last_map = symbolP;
1525}
1526
1527/* We must sometimes convert a region marked as code to data during
1528 code alignment, if an odd number of bytes have to be padded. The
1529 code mapping symbol is pushed to an aligned address. */
1530
1531static void
1532insert_data_mapping_symbol (enum mstate state,
1533 valueT value, fragS * frag, offsetT bytes)
1534{
1535 /* If there was already a mapping symbol, remove it. */
1536 if (frag->tc_frag_data.last_map != NULL
1537 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1538 frag->fr_address + value)
1539 {
1540 symbolS *symp = frag->tc_frag_data.last_map;
1541
1542 if (value == 0)
1543 {
1544 know (frag->tc_frag_data.first_map == symp);
1545 frag->tc_frag_data.first_map = NULL;
1546 }
1547 frag->tc_frag_data.last_map = NULL;
1548 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1549 }
1550
1551 make_mapping_symbol (MAP_DATA, value, frag);
1552 make_mapping_symbol (state, value + bytes, frag);
1553}
1554
1555static void mapping_state_2 (enum mstate state, int max_chars);
1556
1557/* Set the mapping state to STATE. Only call this when about to
1558 emit some STATE bytes to the file. */
1559
1560void
1561mapping_state (enum mstate state)
1562{
1563 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1564
a578ef7e
JW
1565 if (state == MAP_INSN)
1566 /* AArch64 instructions require 4-byte alignment. When emitting
1567 instructions into any section, record the appropriate section
1568 alignment. */
1569 record_alignment (now_seg, 2);
1570
448eb63d
RL
1571 if (mapstate == state)
1572 /* The mapping symbol has already been emitted.
1573 There is nothing else to do. */
1574 return;
1575
c1baaddf 1576#define TRANSITION(from, to) (mapstate == (from) && state == (to))
a97902de
RL
1577 if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg))
1578 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
c1baaddf 1579 evaluated later in the next else. */
a06ea964 1580 return;
c1baaddf
RL
1581 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1582 {
1583 /* Only add the symbol if the offset is > 0:
1584 if we're at the first frag, check it's size > 0;
1585 if we're not at the first frag, then for sure
1586 the offset is > 0. */
1587 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1588 const int add_symbol = (frag_now != frag_first)
1589 || (frag_now_fix () > 0);
1590
1591 if (add_symbol)
1592 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1593 }
1594#undef TRANSITION
a06ea964
NC
1595
1596 mapping_state_2 (state, 0);
a06ea964
NC
1597}
1598
1599/* Same as mapping_state, but MAX_CHARS bytes have already been
1600 allocated. Put the mapping symbol that far back. */
1601
1602static void
1603mapping_state_2 (enum mstate state, int max_chars)
1604{
1605 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1606
1607 if (!SEG_NORMAL (now_seg))
1608 return;
1609
1610 if (mapstate == state)
1611 /* The mapping symbol has already been emitted.
1612 There is nothing else to do. */
1613 return;
1614
1615 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1616 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1617}
1618#else
1619#define mapping_state(x) /* nothing */
1620#define mapping_state_2(x, y) /* nothing */
1621#endif
1622
1623/* Directives: sectioning and alignment. */
1624
1625static void
1626s_bss (int ignore ATTRIBUTE_UNUSED)
1627{
1628 /* We don't support putting frags in the BSS segment, we fake it by
1629 marking in_bss, then looking at s_skip for clues. */
1630 subseg_set (bss_section, 0);
1631 demand_empty_rest_of_line ();
1632 mapping_state (MAP_DATA);
1633}
1634
1635static void
1636s_even (int ignore ATTRIBUTE_UNUSED)
1637{
1638 /* Never make frag if expect extra pass. */
1639 if (!need_pass_2)
1640 frag_align (1, 0, 0);
1641
1642 record_alignment (now_seg, 1);
1643
1644 demand_empty_rest_of_line ();
1645}
1646
1647/* Directives: Literal pools. */
1648
1649static literal_pool *
1650find_literal_pool (int size)
1651{
1652 literal_pool *pool;
1653
1654 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1655 {
1656 if (pool->section == now_seg
1657 && pool->sub_section == now_subseg && pool->size == size)
1658 break;
1659 }
1660
1661 return pool;
1662}
1663
1664static literal_pool *
1665find_or_make_literal_pool (int size)
1666{
1667 /* Next literal pool ID number. */
1668 static unsigned int latest_pool_num = 1;
1669 literal_pool *pool;
1670
1671 pool = find_literal_pool (size);
1672
1673 if (pool == NULL)
1674 {
1675 /* Create a new pool. */
add39d23 1676 pool = XNEW (literal_pool);
a06ea964
NC
1677 if (!pool)
1678 return NULL;
1679
1680 /* Currently we always put the literal pool in the current text
1681 section. If we were generating "small" model code where we
1682 knew that all code and initialised data was within 1MB then
1683 we could output literals to mergeable, read-only data
1684 sections. */
1685
1686 pool->next_free_entry = 0;
1687 pool->section = now_seg;
1688 pool->sub_section = now_subseg;
1689 pool->size = size;
1690 pool->next = list_of_pools;
1691 pool->symbol = NULL;
1692
1693 /* Add it to the list. */
1694 list_of_pools = pool;
1695 }
1696
1697 /* New pools, and emptied pools, will have a NULL symbol. */
1698 if (pool->symbol == NULL)
1699 {
1700 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1701 (valueT) 0, &zero_address_frag);
1702 pool->id = latest_pool_num++;
1703 }
1704
1705 /* Done. */
1706 return pool;
1707}
1708
1709/* Add the literal of size SIZE in *EXP to the relevant literal pool.
1710 Return TRUE on success, otherwise return FALSE. */
1711static bfd_boolean
1712add_to_lit_pool (expressionS *exp, int size)
1713{
1714 literal_pool *pool;
1715 unsigned int entry;
1716
1717 pool = find_or_make_literal_pool (size);
1718
1719 /* Check if this literal value is already in the pool. */
1720 for (entry = 0; entry < pool->next_free_entry; entry++)
1721 {
55d9b4c1
NC
1722 expressionS * litexp = & pool->literals[entry].exp;
1723
1724 if ((litexp->X_op == exp->X_op)
a06ea964 1725 && (exp->X_op == O_constant)
55d9b4c1
NC
1726 && (litexp->X_add_number == exp->X_add_number)
1727 && (litexp->X_unsigned == exp->X_unsigned))
a06ea964
NC
1728 break;
1729
55d9b4c1 1730 if ((litexp->X_op == exp->X_op)
a06ea964 1731 && (exp->X_op == O_symbol)
55d9b4c1
NC
1732 && (litexp->X_add_number == exp->X_add_number)
1733 && (litexp->X_add_symbol == exp->X_add_symbol)
1734 && (litexp->X_op_symbol == exp->X_op_symbol))
a06ea964
NC
1735 break;
1736 }
1737
1738 /* Do we need to create a new entry? */
1739 if (entry == pool->next_free_entry)
1740 {
1741 if (entry >= MAX_LITERAL_POOL_SIZE)
1742 {
1743 set_syntax_error (_("literal pool overflow"));
1744 return FALSE;
1745 }
1746
55d9b4c1 1747 pool->literals[entry].exp = *exp;
a06ea964 1748 pool->next_free_entry += 1;
55d9b4c1
NC
1749 if (exp->X_op == O_big)
1750 {
1751 /* PR 16688: Bignums are held in a single global array. We must
1752 copy and preserve that value now, before it is overwritten. */
add39d23
TS
1753 pool->literals[entry].bignum = XNEWVEC (LITTLENUM_TYPE,
1754 exp->X_add_number);
55d9b4c1
NC
1755 memcpy (pool->literals[entry].bignum, generic_bignum,
1756 CHARS_PER_LITTLENUM * exp->X_add_number);
1757 }
1758 else
1759 pool->literals[entry].bignum = NULL;
a06ea964
NC
1760 }
1761
1762 exp->X_op = O_symbol;
1763 exp->X_add_number = ((int) entry) * size;
1764 exp->X_add_symbol = pool->symbol;
1765
1766 return TRUE;
1767}
1768
1769/* Can't use symbol_new here, so have to create a symbol and then at
33eaf5de 1770 a later date assign it a value. That's what these functions do. */
a06ea964
NC
1771
1772static void
1773symbol_locate (symbolS * symbolP,
1774 const char *name,/* It is copied, the caller can modify. */
1775 segT segment, /* Segment identifier (SEG_<something>). */
1776 valueT valu, /* Symbol value. */
1777 fragS * frag) /* Associated fragment. */
1778{
e57e6ddc 1779 size_t name_length;
a06ea964
NC
1780 char *preserved_copy_of_name;
1781
1782 name_length = strlen (name) + 1; /* +1 for \0. */
1783 obstack_grow (&notes, name, name_length);
1784 preserved_copy_of_name = obstack_finish (&notes);
1785
1786#ifdef tc_canonicalize_symbol_name
1787 preserved_copy_of_name =
1788 tc_canonicalize_symbol_name (preserved_copy_of_name);
1789#endif
1790
1791 S_SET_NAME (symbolP, preserved_copy_of_name);
1792
1793 S_SET_SEGMENT (symbolP, segment);
1794 S_SET_VALUE (symbolP, valu);
1795 symbol_clear_list_pointers (symbolP);
1796
1797 symbol_set_frag (symbolP, frag);
1798
1799 /* Link to end of symbol chain. */
1800 {
1801 extern int symbol_table_frozen;
1802
1803 if (symbol_table_frozen)
1804 abort ();
1805 }
1806
1807 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1808
1809 obj_symbol_new_hook (symbolP);
1810
1811#ifdef tc_symbol_new_hook
1812 tc_symbol_new_hook (symbolP);
1813#endif
1814
1815#ifdef DEBUG_SYMS
1816 verify_symbol_chain (symbol_rootP, symbol_lastP);
1817#endif /* DEBUG_SYMS */
1818}
1819
1820
1821static void
1822s_ltorg (int ignored ATTRIBUTE_UNUSED)
1823{
1824 unsigned int entry;
1825 literal_pool *pool;
1826 char sym_name[20];
1827 int align;
1828
67a32447 1829 for (align = 2; align <= 4; align++)
a06ea964
NC
1830 {
1831 int size = 1 << align;
1832
1833 pool = find_literal_pool (size);
1834 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1835 continue;
1836
a06ea964
NC
1837 /* Align pool as you have word accesses.
1838 Only make a frag if we have to. */
1839 if (!need_pass_2)
1840 frag_align (align, 0, 0);
1841
7ea12e5c
NC
1842 mapping_state (MAP_DATA);
1843
a06ea964
NC
1844 record_alignment (now_seg, align);
1845
1846 sprintf (sym_name, "$$lit_\002%x", pool->id);
1847
1848 symbol_locate (pool->symbol, sym_name, now_seg,
1849 (valueT) frag_now_fix (), frag_now);
1850 symbol_table_insert (pool->symbol);
1851
1852 for (entry = 0; entry < pool->next_free_entry; entry++)
55d9b4c1
NC
1853 {
1854 expressionS * exp = & pool->literals[entry].exp;
1855
1856 if (exp->X_op == O_big)
1857 {
1858 /* PR 16688: Restore the global bignum value. */
1859 gas_assert (pool->literals[entry].bignum != NULL);
1860 memcpy (generic_bignum, pool->literals[entry].bignum,
1861 CHARS_PER_LITTLENUM * exp->X_add_number);
1862 }
1863
1864 /* First output the expression in the instruction to the pool. */
1865 emit_expr (exp, size); /* .word|.xword */
1866
1867 if (exp->X_op == O_big)
1868 {
1869 free (pool->literals[entry].bignum);
1870 pool->literals[entry].bignum = NULL;
1871 }
1872 }
a06ea964
NC
1873
1874 /* Mark the pool as empty. */
1875 pool->next_free_entry = 0;
1876 pool->symbol = NULL;
1877 }
1878}
1879
1880#ifdef OBJ_ELF
1881/* Forward declarations for functions below, in the MD interface
1882 section. */
1883static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1884static struct reloc_table_entry * find_reloc_table_entry (char **);
1885
1886/* Directives: Data. */
1887/* N.B. the support for relocation suffix in this directive needs to be
1888 implemented properly. */
1889
1890static void
1891s_aarch64_elf_cons (int nbytes)
1892{
1893 expressionS exp;
1894
1895#ifdef md_flush_pending_output
1896 md_flush_pending_output ();
1897#endif
1898
1899 if (is_it_end_of_statement ())
1900 {
1901 demand_empty_rest_of_line ();
1902 return;
1903 }
1904
1905#ifdef md_cons_align
1906 md_cons_align (nbytes);
1907#endif
1908
1909 mapping_state (MAP_DATA);
1910 do
1911 {
1912 struct reloc_table_entry *reloc;
1913
1914 expression (&exp);
1915
1916 if (exp.X_op != O_symbol)
1917 emit_expr (&exp, (unsigned int) nbytes);
1918 else
1919 {
1920 skip_past_char (&input_line_pointer, '#');
1921 if (skip_past_char (&input_line_pointer, ':'))
1922 {
1923 reloc = find_reloc_table_entry (&input_line_pointer);
1924 if (reloc == NULL)
1925 as_bad (_("unrecognized relocation suffix"));
1926 else
1927 as_bad (_("unimplemented relocation suffix"));
1928 ignore_rest_of_line ();
1929 return;
1930 }
1931 else
1932 emit_expr (&exp, (unsigned int) nbytes);
1933 }
1934 }
1935 while (*input_line_pointer++ == ',');
1936
1937 /* Put terminator back into stream. */
1938 input_line_pointer--;
1939 demand_empty_rest_of_line ();
1940}
1941
1942#endif /* OBJ_ELF */
1943
1944/* Output a 32-bit word, but mark as an instruction. */
1945
1946static void
1947s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1948{
1949 expressionS exp;
1950
1951#ifdef md_flush_pending_output
1952 md_flush_pending_output ();
1953#endif
1954
1955 if (is_it_end_of_statement ())
1956 {
1957 demand_empty_rest_of_line ();
1958 return;
1959 }
1960
a97902de 1961 /* Sections are assumed to start aligned. In executable section, there is no
c1baaddf
RL
1962 MAP_DATA symbol pending. So we only align the address during
1963 MAP_DATA --> MAP_INSN transition.
eb9d6cc9 1964 For other sections, this is not guaranteed. */
c1baaddf 1965 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
eb9d6cc9 1966 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
a06ea964 1967 frag_align_code (2, 0);
c1baaddf 1968
a06ea964
NC
1969#ifdef OBJ_ELF
1970 mapping_state (MAP_INSN);
1971#endif
1972
1973 do
1974 {
1975 expression (&exp);
1976 if (exp.X_op != O_constant)
1977 {
1978 as_bad (_("constant expression required"));
1979 ignore_rest_of_line ();
1980 return;
1981 }
1982
1983 if (target_big_endian)
1984 {
1985 unsigned int val = exp.X_add_number;
1986 exp.X_add_number = SWAP_32 (val);
1987 }
1988 emit_expr (&exp, 4);
1989 }
1990 while (*input_line_pointer++ == ',');
1991
1992 /* Put terminator back into stream. */
1993 input_line_pointer--;
1994 demand_empty_rest_of_line ();
1995}
1996
3a67e1a6
ST
1997static void
1998s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED)
1999{
2000 demand_empty_rest_of_line ();
2001 struct fde_entry *fde = frchain_now->frch_cfi_data->cur_fde_data;
2002 fde->pauth_key = AARCH64_PAUTH_KEY_B;
2003}
2004
a06ea964 2005#ifdef OBJ_ELF
43a357f9
RL
2006/* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2007
2008static void
2009s_tlsdescadd (int ignored ATTRIBUTE_UNUSED)
2010{
2011 expressionS exp;
2012
2013 expression (&exp);
2014 frag_grow (4);
2015 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
2016 BFD_RELOC_AARCH64_TLSDESC_ADD);
2017
2018 demand_empty_rest_of_line ();
2019}
2020
a06ea964
NC
2021/* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2022
2023static void
2024s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
2025{
2026 expressionS exp;
2027
2028 /* Since we're just labelling the code, there's no need to define a
2029 mapping symbol. */
2030 expression (&exp);
2031 /* Make sure there is enough room in this frag for the following
2032 blr. This trick only works if the blr follows immediately after
2033 the .tlsdesc directive. */
2034 frag_grow (4);
2035 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
2036 BFD_RELOC_AARCH64_TLSDESC_CALL);
2037
2038 demand_empty_rest_of_line ();
2039}
43a357f9
RL
2040
2041/* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2042
2043static void
2044s_tlsdescldr (int ignored ATTRIBUTE_UNUSED)
2045{
2046 expressionS exp;
2047
2048 expression (&exp);
2049 frag_grow (4);
2050 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
2051 BFD_RELOC_AARCH64_TLSDESC_LDR);
2052
2053 demand_empty_rest_of_line ();
2054}
a06ea964
NC
2055#endif /* OBJ_ELF */
2056
2057static void s_aarch64_arch (int);
2058static void s_aarch64_cpu (int);
ae527cd8 2059static void s_aarch64_arch_extension (int);
a06ea964
NC
2060
2061/* This table describes all the machine specific pseudo-ops the assembler
2062 has to support. The fields are:
2063 pseudo-op name without dot
2064 function to call to execute this pseudo-op
2065 Integer arg to pass to the function. */
2066
2067const pseudo_typeS md_pseudo_table[] = {
2068 /* Never called because '.req' does not start a line. */
2069 {"req", s_req, 0},
2070 {"unreq", s_unreq, 0},
2071 {"bss", s_bss, 0},
2072 {"even", s_even, 0},
2073 {"ltorg", s_ltorg, 0},
2074 {"pool", s_ltorg, 0},
2075 {"cpu", s_aarch64_cpu, 0},
2076 {"arch", s_aarch64_arch, 0},
ae527cd8 2077 {"arch_extension", s_aarch64_arch_extension, 0},
a06ea964 2078 {"inst", s_aarch64_inst, 0},
3a67e1a6 2079 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame, 0},
a06ea964 2080#ifdef OBJ_ELF
43a357f9 2081 {"tlsdescadd", s_tlsdescadd, 0},
a06ea964 2082 {"tlsdesccall", s_tlsdesccall, 0},
43a357f9 2083 {"tlsdescldr", s_tlsdescldr, 0},
a06ea964
NC
2084 {"word", s_aarch64_elf_cons, 4},
2085 {"long", s_aarch64_elf_cons, 4},
2086 {"xword", s_aarch64_elf_cons, 8},
2087 {"dword", s_aarch64_elf_cons, 8},
2088#endif
2089 {0, 0, 0}
2090};
2091\f
2092
2093/* Check whether STR points to a register name followed by a comma or the
2094 end of line; REG_TYPE indicates which register types are checked
2095 against. Return TRUE if STR is such a register name; otherwise return
2096 FALSE. The function does not intend to produce any diagnostics, but since
2097 the register parser aarch64_reg_parse, which is called by this function,
2098 does produce diagnostics, we call clear_error to clear any diagnostics
2099 that may be generated by aarch64_reg_parse.
2100 Also, the function returns FALSE directly if there is any user error
2101 present at the function entry. This prevents the existing diagnostics
2102 state from being spoiled.
2103 The function currently serves parse_constant_immediate and
2104 parse_big_immediate only. */
2105static bfd_boolean
2106reg_name_p (char *str, aarch64_reg_type reg_type)
2107{
2108 int reg;
2109
2110 /* Prevent the diagnostics state from being spoiled. */
2111 if (error_p ())
2112 return FALSE;
2113
2114 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
2115
2116 /* Clear the parsing error that may be set by the reg parser. */
2117 clear_error ();
2118
2119 if (reg == PARSE_FAIL)
2120 return FALSE;
2121
2122 skip_whitespace (str);
2123 if (*str == ',' || is_end_of_line[(unsigned int) *str])
2124 return TRUE;
2125
2126 return FALSE;
2127}
2128
2129/* Parser functions used exclusively in instruction operands. */
2130
2131/* Parse an immediate expression which may not be constant.
2132
2133 To prevent the expression parser from pushing a register name
2134 into the symbol table as an undefined symbol, firstly a check is
1799c0d0
RS
2135 done to find out whether STR is a register of type REG_TYPE followed
2136 by a comma or the end of line. Return FALSE if STR is such a string. */
a06ea964
NC
2137
2138static bfd_boolean
1799c0d0
RS
2139parse_immediate_expression (char **str, expressionS *exp,
2140 aarch64_reg_type reg_type)
a06ea964 2141{
1799c0d0 2142 if (reg_name_p (*str, reg_type))
a06ea964
NC
2143 {
2144 set_recoverable_error (_("immediate operand required"));
2145 return FALSE;
2146 }
2147
2148 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
2149
2150 if (exp->X_op == O_absent)
2151 {
2152 set_fatal_syntax_error (_("missing immediate expression"));
2153 return FALSE;
2154 }
2155
2156 return TRUE;
2157}
2158
2159/* Constant immediate-value read function for use in insn parsing.
2160 STR points to the beginning of the immediate (with the optional
1799c0d0
RS
2161 leading #); *VAL receives the value. REG_TYPE says which register
2162 names should be treated as registers rather than as symbolic immediates.
a06ea964
NC
2163
2164 Return TRUE on success; otherwise return FALSE. */
2165
2166static bfd_boolean
1799c0d0 2167parse_constant_immediate (char **str, int64_t *val, aarch64_reg_type reg_type)
a06ea964
NC
2168{
2169 expressionS exp;
2170
1799c0d0 2171 if (! parse_immediate_expression (str, &exp, reg_type))
a06ea964
NC
2172 return FALSE;
2173
2174 if (exp.X_op != O_constant)
2175 {
2176 set_syntax_error (_("constant expression required"));
2177 return FALSE;
2178 }
2179
2180 *val = exp.X_add_number;
2181 return TRUE;
2182}
2183
2184static uint32_t
2185encode_imm_float_bits (uint32_t imm)
2186{
2187 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2188 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2189}
2190
62b0d0d5
YZ
2191/* Return TRUE if the single-precision floating-point value encoded in IMM
2192 can be expressed in the AArch64 8-bit signed floating-point format with
2193 3-bit exponent and normalized 4 bits of precision; in other words, the
2194 floating-point value must be expressable as
2195 (+/-) n / 16 * power (2, r)
2196 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2197
a06ea964
NC
2198static bfd_boolean
2199aarch64_imm_float_p (uint32_t imm)
2200{
62b0d0d5
YZ
2201 /* If a single-precision floating-point value has the following bit
2202 pattern, it can be expressed in the AArch64 8-bit floating-point
2203 format:
2204
2205 3 32222222 2221111111111
a06ea964 2206 1 09876543 21098765432109876543210
62b0d0d5
YZ
2207 n Eeeeeexx xxxx0000000000000000000
2208
2209 where n, e and each x are either 0 or 1 independently, with
2210 E == ~ e. */
a06ea964 2211
62b0d0d5
YZ
2212 uint32_t pattern;
2213
2214 /* Prepare the pattern for 'Eeeeee'. */
2215 if (((imm >> 30) & 0x1) == 0)
2216 pattern = 0x3e000000;
a06ea964 2217 else
62b0d0d5
YZ
2218 pattern = 0x40000000;
2219
2220 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2221 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
a06ea964
NC
2222}
2223
04a3379a
RS
2224/* Return TRUE if the IEEE double value encoded in IMM can be expressed
2225 as an IEEE float without any loss of precision. Store the value in
2226 *FPWORD if so. */
62b0d0d5 2227
a06ea964 2228static bfd_boolean
04a3379a 2229can_convert_double_to_float (uint64_t imm, uint32_t *fpword)
62b0d0d5
YZ
2230{
2231 /* If a double-precision floating-point value has the following bit
04a3379a 2232 pattern, it can be expressed in a float:
62b0d0d5 2233
04a3379a
RS
2234 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2235 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2236 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
62b0d0d5 2237
04a3379a
RS
2238 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2239 if Eeee_eeee != 1111_1111
2240
2241 where n, e, s and S are either 0 or 1 independently and where ~ is the
2242 inverse of E. */
62b0d0d5
YZ
2243
2244 uint32_t pattern;
2245 uint32_t high32 = imm >> 32;
04a3379a 2246 uint32_t low32 = imm;
62b0d0d5 2247
04a3379a
RS
2248 /* Lower 29 bits need to be 0s. */
2249 if ((imm & 0x1fffffff) != 0)
62b0d0d5
YZ
2250 return FALSE;
2251
2252 /* Prepare the pattern for 'Eeeeeeeee'. */
2253 if (((high32 >> 30) & 0x1) == 0)
04a3379a 2254 pattern = 0x38000000;
62b0d0d5
YZ
2255 else
2256 pattern = 0x40000000;
2257
04a3379a
RS
2258 /* Check E~~~. */
2259 if ((high32 & 0x78000000) != pattern)
62b0d0d5 2260 return FALSE;
04a3379a
RS
2261
2262 /* Check Eeee_eeee != 1111_1111. */
2263 if ((high32 & 0x7ff00000) == 0x47f00000)
2264 return FALSE;
2265
2266 *fpword = ((high32 & 0xc0000000) /* 1 n bit and 1 E bit. */
2267 | ((high32 << 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2268 | (low32 >> 29)); /* 3 S bits. */
2269 return TRUE;
62b0d0d5
YZ
2270}
2271
165d4950
RS
2272/* Return true if we should treat OPERAND as a double-precision
2273 floating-point operand rather than a single-precision one. */
2274static bfd_boolean
2275double_precision_operand_p (const aarch64_opnd_info *operand)
2276{
2277 /* Check for unsuffixed SVE registers, which are allowed
2278 for LDR and STR but not in instructions that require an
2279 immediate. We get better error messages if we arbitrarily
2280 pick one size, parse the immediate normally, and then
2281 report the match failure in the normal way. */
2282 return (operand->qualifier == AARCH64_OPND_QLF_NIL
2283 || aarch64_get_qualifier_esize (operand->qualifier) == 8);
2284}
2285
62b0d0d5
YZ
2286/* Parse a floating-point immediate. Return TRUE on success and return the
2287 value in *IMMED in the format of IEEE754 single-precision encoding.
2288 *CCP points to the start of the string; DP_P is TRUE when the immediate
2289 is expected to be in double-precision (N.B. this only matters when
1799c0d0
RS
2290 hexadecimal representation is involved). REG_TYPE says which register
2291 names should be treated as registers rather than as symbolic immediates.
62b0d0d5 2292
874d7e6e
RS
2293 This routine accepts any IEEE float; it is up to the callers to reject
2294 invalid ones. */
62b0d0d5
YZ
2295
2296static bfd_boolean
1799c0d0
RS
2297parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
2298 aarch64_reg_type reg_type)
a06ea964
NC
2299{
2300 char *str = *ccp;
2301 char *fpnum;
2302 LITTLENUM_TYPE words[MAX_LITTLENUMS];
62b0d0d5
YZ
2303 int64_t val = 0;
2304 unsigned fpword = 0;
2305 bfd_boolean hex_p = FALSE;
a06ea964
NC
2306
2307 skip_past_char (&str, '#');
2308
a06ea964
NC
2309 fpnum = str;
2310 skip_whitespace (fpnum);
2311
2312 if (strncmp (fpnum, "0x", 2) == 0)
62b0d0d5
YZ
2313 {
2314 /* Support the hexadecimal representation of the IEEE754 encoding.
2315 Double-precision is expected when DP_P is TRUE, otherwise the
2316 representation should be in single-precision. */
1799c0d0 2317 if (! parse_constant_immediate (&str, &val, reg_type))
62b0d0d5
YZ
2318 goto invalid_fp;
2319
2320 if (dp_p)
2321 {
04a3379a 2322 if (!can_convert_double_to_float (val, &fpword))
62b0d0d5
YZ
2323 goto invalid_fp;
2324 }
2325 else if ((uint64_t) val > 0xffffffff)
2326 goto invalid_fp;
2327 else
2328 fpword = val;
2329
2330 hex_p = TRUE;
2331 }
66881839
TC
2332 else if (reg_name_p (str, reg_type))
2333 {
2334 set_recoverable_error (_("immediate operand required"));
2335 return FALSE;
a06ea964
NC
2336 }
2337
62b0d0d5 2338 if (! hex_p)
a06ea964 2339 {
a06ea964
NC
2340 int i;
2341
62b0d0d5
YZ
2342 if ((str = atof_ieee (str, 's', words)) == NULL)
2343 goto invalid_fp;
2344
a06ea964
NC
2345 /* Our FP word must be 32 bits (single-precision FP). */
2346 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2347 {
2348 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2349 fpword |= words[i];
2350 }
62b0d0d5 2351 }
a06ea964 2352
874d7e6e
RS
2353 *immed = fpword;
2354 *ccp = str;
2355 return TRUE;
a06ea964
NC
2356
2357invalid_fp:
2358 set_fatal_syntax_error (_("invalid floating-point constant"));
2359 return FALSE;
2360}
2361
2362/* Less-generic immediate-value read function with the possibility of loading
2363 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2364 instructions.
2365
2366 To prevent the expression parser from pushing a register name into the
2367 symbol table as an undefined symbol, a check is firstly done to find
1799c0d0
RS
2368 out whether STR is a register of type REG_TYPE followed by a comma or
2369 the end of line. Return FALSE if STR is such a register. */
a06ea964
NC
2370
2371static bfd_boolean
1799c0d0 2372parse_big_immediate (char **str, int64_t *imm, aarch64_reg_type reg_type)
a06ea964
NC
2373{
2374 char *ptr = *str;
2375
1799c0d0 2376 if (reg_name_p (ptr, reg_type))
a06ea964
NC
2377 {
2378 set_syntax_error (_("immediate operand required"));
2379 return FALSE;
2380 }
2381
2382 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2383
2384 if (inst.reloc.exp.X_op == O_constant)
2385 *imm = inst.reloc.exp.X_add_number;
2386
2387 *str = ptr;
2388
2389 return TRUE;
2390}
2391
2392/* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2393 if NEED_LIBOPCODES is non-zero, the fixup will need
2394 assistance from the libopcodes. */
2395
2396static inline void
2397aarch64_set_gas_internal_fixup (struct reloc *reloc,
2398 const aarch64_opnd_info *operand,
2399 int need_libopcodes_p)
2400{
2401 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2402 reloc->opnd = operand->type;
2403 if (need_libopcodes_p)
2404 reloc->need_libopcodes_p = 1;
2405};
2406
2407/* Return TRUE if the instruction needs to be fixed up later internally by
2408 the GAS; otherwise return FALSE. */
2409
2410static inline bfd_boolean
2411aarch64_gas_internal_fixup_p (void)
2412{
2413 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2414}
2415
33eaf5de 2416/* Assign the immediate value to the relevant field in *OPERAND if
a06ea964
NC
2417 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2418 needs an internal fixup in a later stage.
2419 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2420 IMM.VALUE that may get assigned with the constant. */
2421static inline void
2422assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2423 aarch64_opnd_info *operand,
2424 int addr_off_p,
2425 int need_libopcodes_p,
2426 int skip_p)
2427{
2428 if (reloc->exp.X_op == O_constant)
2429 {
2430 if (addr_off_p)
2431 operand->addr.offset.imm = reloc->exp.X_add_number;
2432 else
2433 operand->imm.value = reloc->exp.X_add_number;
2434 reloc->type = BFD_RELOC_UNUSED;
2435 }
2436 else
2437 {
2438 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2439 /* Tell libopcodes to ignore this operand or not. This is helpful
2440 when one of the operands needs to be fixed up later but we need
2441 libopcodes to check the other operands. */
2442 operand->skip = skip_p;
2443 }
2444}
2445
2446/* Relocation modifiers. Each entry in the table contains the textual
2447 name for the relocation which may be placed before a symbol used as
2448 a load/store offset, or add immediate. It must be surrounded by a
2449 leading and trailing colon, for example:
2450
2451 ldr x0, [x1, #:rello:varsym]
2452 add x0, x1, #:rello:varsym */
2453
2454struct reloc_table_entry
2455{
2456 const char *name;
2457 int pc_rel;
6f4a313b 2458 bfd_reloc_code_real_type adr_type;
a06ea964
NC
2459 bfd_reloc_code_real_type adrp_type;
2460 bfd_reloc_code_real_type movw_type;
2461 bfd_reloc_code_real_type add_type;
2462 bfd_reloc_code_real_type ldst_type;
74ad790c 2463 bfd_reloc_code_real_type ld_literal_type;
a06ea964
NC
2464};
2465
2466static struct reloc_table_entry reloc_table[] = {
2467 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2468 {"lo12", 0,
6f4a313b 2469 0, /* adr_type */
a06ea964
NC
2470 0,
2471 0,
2472 BFD_RELOC_AARCH64_ADD_LO12,
74ad790c
MS
2473 BFD_RELOC_AARCH64_LDST_LO12,
2474 0},
a06ea964
NC
2475
2476 /* Higher 21 bits of pc-relative page offset: ADRP */
2477 {"pg_hi21", 1,
6f4a313b 2478 0, /* adr_type */
a06ea964
NC
2479 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2480 0,
2481 0,
74ad790c 2482 0,
a06ea964
NC
2483 0},
2484
2485 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2486 {"pg_hi21_nc", 1,
6f4a313b 2487 0, /* adr_type */
a06ea964
NC
2488 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2489 0,
2490 0,
74ad790c 2491 0,
a06ea964
NC
2492 0},
2493
2494 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2495 {"abs_g0", 0,
6f4a313b 2496 0, /* adr_type */
a06ea964
NC
2497 0,
2498 BFD_RELOC_AARCH64_MOVW_G0,
2499 0,
74ad790c 2500 0,
a06ea964
NC
2501 0},
2502
2503 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2504 {"abs_g0_s", 0,
6f4a313b 2505 0, /* adr_type */
a06ea964
NC
2506 0,
2507 BFD_RELOC_AARCH64_MOVW_G0_S,
2508 0,
74ad790c 2509 0,
a06ea964
NC
2510 0},
2511
2512 /* Less significant bits 0-15 of address/value: MOVK, no check */
2513 {"abs_g0_nc", 0,
6f4a313b 2514 0, /* adr_type */
a06ea964
NC
2515 0,
2516 BFD_RELOC_AARCH64_MOVW_G0_NC,
2517 0,
74ad790c 2518 0,
a06ea964
NC
2519 0},
2520
2521 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2522 {"abs_g1", 0,
6f4a313b 2523 0, /* adr_type */
a06ea964
NC
2524 0,
2525 BFD_RELOC_AARCH64_MOVW_G1,
2526 0,
74ad790c 2527 0,
a06ea964
NC
2528 0},
2529
2530 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2531 {"abs_g1_s", 0,
6f4a313b 2532 0, /* adr_type */
a06ea964
NC
2533 0,
2534 BFD_RELOC_AARCH64_MOVW_G1_S,
2535 0,
74ad790c 2536 0,
a06ea964
NC
2537 0},
2538
2539 /* Less significant bits 16-31 of address/value: MOVK, no check */
2540 {"abs_g1_nc", 0,
6f4a313b 2541 0, /* adr_type */
a06ea964
NC
2542 0,
2543 BFD_RELOC_AARCH64_MOVW_G1_NC,
2544 0,
74ad790c 2545 0,
a06ea964
NC
2546 0},
2547
2548 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2549 {"abs_g2", 0,
6f4a313b 2550 0, /* adr_type */
a06ea964
NC
2551 0,
2552 BFD_RELOC_AARCH64_MOVW_G2,
2553 0,
74ad790c 2554 0,
a06ea964
NC
2555 0},
2556
2557 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2558 {"abs_g2_s", 0,
6f4a313b 2559 0, /* adr_type */
a06ea964
NC
2560 0,
2561 BFD_RELOC_AARCH64_MOVW_G2_S,
2562 0,
74ad790c 2563 0,
a06ea964
NC
2564 0},
2565
2566 /* Less significant bits 32-47 of address/value: MOVK, no check */
2567 {"abs_g2_nc", 0,
6f4a313b 2568 0, /* adr_type */
a06ea964
NC
2569 0,
2570 BFD_RELOC_AARCH64_MOVW_G2_NC,
2571 0,
74ad790c 2572 0,
a06ea964
NC
2573 0},
2574
2575 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2576 {"abs_g3", 0,
6f4a313b 2577 0, /* adr_type */
a06ea964
NC
2578 0,
2579 BFD_RELOC_AARCH64_MOVW_G3,
2580 0,
74ad790c 2581 0,
a06ea964 2582 0},
4aa2c5e2 2583
32247401
RL
2584 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2585 {"prel_g0", 1,
2586 0, /* adr_type */
2587 0,
2588 BFD_RELOC_AARCH64_MOVW_PREL_G0,
2589 0,
2590 0,
2591 0},
2592
2593 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2594 {"prel_g0_nc", 1,
2595 0, /* adr_type */
2596 0,
2597 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
2598 0,
2599 0,
2600 0},
2601
2602 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2603 {"prel_g1", 1,
2604 0, /* adr_type */
2605 0,
2606 BFD_RELOC_AARCH64_MOVW_PREL_G1,
2607 0,
2608 0,
2609 0},
2610
2611 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2612 {"prel_g1_nc", 1,
2613 0, /* adr_type */
2614 0,
2615 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
2616 0,
2617 0,
2618 0},
2619
2620 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2621 {"prel_g2", 1,
2622 0, /* adr_type */
2623 0,
2624 BFD_RELOC_AARCH64_MOVW_PREL_G2,
2625 0,
2626 0,
2627 0},
2628
2629 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2630 {"prel_g2_nc", 1,
2631 0, /* adr_type */
2632 0,
2633 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
2634 0,
2635 0,
2636 0},
2637
2638 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2639 {"prel_g3", 1,
2640 0, /* adr_type */
2641 0,
2642 BFD_RELOC_AARCH64_MOVW_PREL_G3,
2643 0,
2644 0,
2645 0},
2646
a06ea964
NC
2647 /* Get to the page containing GOT entry for a symbol. */
2648 {"got", 1,
6f4a313b 2649 0, /* adr_type */
a06ea964
NC
2650 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2651 0,
2652 0,
74ad790c 2653 0,
4aa2c5e2
MS
2654 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2655
a06ea964
NC
2656 /* 12 bit offset into the page containing GOT entry for that symbol. */
2657 {"got_lo12", 0,
6f4a313b 2658 0, /* adr_type */
a06ea964
NC
2659 0,
2660 0,
2661 0,
74ad790c
MS
2662 BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
2663 0},
a06ea964 2664
ca632371
RL
2665 /* 0-15 bits of address/value: MOVk, no check. */
2666 {"gotoff_g0_nc", 0,
2667 0, /* adr_type */
2668 0,
2669 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
2670 0,
2671 0,
2672 0},
2673
654248e7
RL
2674 /* Most significant bits 16-31 of address/value: MOVZ. */
2675 {"gotoff_g1", 0,
2676 0, /* adr_type */
2677 0,
2678 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1,
2679 0,
2680 0,
2681 0},
2682
87f5fbcc
RL
2683 /* 15 bit offset into the page containing GOT entry for that symbol. */
2684 {"gotoff_lo15", 0,
2685 0, /* adr_type */
2686 0,
2687 0,
2688 0,
2689 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15,
2690 0},
2691
3b957e5b
RL
2692 /* Get to the page containing GOT TLS entry for a symbol */
2693 {"gottprel_g0_nc", 0,
2694 0, /* adr_type */
2695 0,
2696 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
2697 0,
2698 0,
2699 0},
2700
2701 /* Get to the page containing GOT TLS entry for a symbol */
2702 {"gottprel_g1", 0,
2703 0, /* adr_type */
2704 0,
2705 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
2706 0,
2707 0,
2708 0},
2709
a06ea964
NC
2710 /* Get to the page containing GOT TLS entry for a symbol */
2711 {"tlsgd", 0,
3c12b054 2712 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */
a06ea964
NC
2713 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2714 0,
2715 0,
74ad790c 2716 0,
a06ea964
NC
2717 0},
2718
2719 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2720 {"tlsgd_lo12", 0,
6f4a313b 2721 0, /* adr_type */
a06ea964
NC
2722 0,
2723 0,
2724 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
74ad790c 2725 0,
a06ea964
NC
2726 0},
2727
3e8286c0
RL
2728 /* Lower 16 bits address/value: MOVk. */
2729 {"tlsgd_g0_nc", 0,
2730 0, /* adr_type */
2731 0,
2732 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC,
2733 0,
2734 0,
2735 0},
2736
1aa66fb1
RL
2737 /* Most significant bits 16-31 of address/value: MOVZ. */
2738 {"tlsgd_g1", 0,
2739 0, /* adr_type */
2740 0,
2741 BFD_RELOC_AARCH64_TLSGD_MOVW_G1,
2742 0,
2743 0,
2744 0},
2745
a06ea964
NC
2746 /* Get to the page containing GOT TLS entry for a symbol */
2747 {"tlsdesc", 0,
389b8029 2748 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */
418009c2 2749 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
a06ea964
NC
2750 0,
2751 0,
74ad790c 2752 0,
1ada945d 2753 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19},
a06ea964
NC
2754
2755 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2756 {"tlsdesc_lo12", 0,
6f4a313b 2757 0, /* adr_type */
a06ea964
NC
2758 0,
2759 0,
f955cccf 2760 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12,
74ad790c
MS
2761 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
2762 0},
a06ea964 2763
6c37fedc
JW
2764 /* Get to the page containing GOT TLS entry for a symbol.
2765 The same as GD, we allocate two consecutive GOT slots
2766 for module index and module offset, the only difference
33eaf5de 2767 with GD is the module offset should be initialized to
6c37fedc
JW
2768 zero without any outstanding runtime relocation. */
2769 {"tlsldm", 0,
2770 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
1107e076 2771 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21,
6c37fedc
JW
2772 0,
2773 0,
2774 0,
2775 0},
2776
a12fad50
JW
2777 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2778 {"tlsldm_lo12_nc", 0,
2779 0, /* adr_type */
2780 0,
2781 0,
2782 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
2783 0,
2784 0},
2785
70151fb5
JW
2786 /* 12 bit offset into the module TLS base address. */
2787 {"dtprel_lo12", 0,
2788 0, /* adr_type */
2789 0,
2790 0,
2791 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
4c562523 2792 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
70151fb5
JW
2793 0},
2794
13289c10
JW
2795 /* Same as dtprel_lo12, no overflow check. */
2796 {"dtprel_lo12_nc", 0,
2797 0, /* adr_type */
2798 0,
2799 0,
2800 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
4c562523 2801 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
13289c10
JW
2802 0},
2803
49df5539
JW
2804 /* bits[23:12] of offset to the module TLS base address. */
2805 {"dtprel_hi12", 0,
2806 0, /* adr_type */
2807 0,
2808 0,
2809 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
2810 0,
2811 0},
2812
2813 /* bits[15:0] of offset to the module TLS base address. */
2814 {"dtprel_g0", 0,
2815 0, /* adr_type */
2816 0,
2817 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
2818 0,
2819 0,
2820 0},
2821
2822 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2823 {"dtprel_g0_nc", 0,
2824 0, /* adr_type */
2825 0,
2826 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
2827 0,
2828 0,
2829 0},
2830
2831 /* bits[31:16] of offset to the module TLS base address. */
2832 {"dtprel_g1", 0,
2833 0, /* adr_type */
2834 0,
2835 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
2836 0,
2837 0,
2838 0},
2839
2840 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2841 {"dtprel_g1_nc", 0,
2842 0, /* adr_type */
2843 0,
2844 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
2845 0,
2846 0,
2847 0},
2848
2849 /* bits[47:32] of offset to the module TLS base address. */
2850 {"dtprel_g2", 0,
2851 0, /* adr_type */
2852 0,
2853 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2,
2854 0,
2855 0,
2856 0},
2857
43a357f9
RL
2858 /* Lower 16 bit offset into GOT entry for a symbol */
2859 {"tlsdesc_off_g0_nc", 0,
2860 0, /* adr_type */
2861 0,
2862 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
2863 0,
2864 0,
2865 0},
2866
2867 /* Higher 16 bit offset into GOT entry for a symbol */
2868 {"tlsdesc_off_g1", 0,
2869 0, /* adr_type */
2870 0,
2871 BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
2872 0,
2873 0,
2874 0},
2875
a06ea964
NC
2876 /* Get to the page containing GOT TLS entry for a symbol */
2877 {"gottprel", 0,
6f4a313b 2878 0, /* adr_type */
a06ea964
NC
2879 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2880 0,
2881 0,
74ad790c 2882 0,
043bf05a 2883 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
a06ea964
NC
2884
2885 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2886 {"gottprel_lo12", 0,
6f4a313b 2887 0, /* adr_type */
a06ea964
NC
2888 0,
2889 0,
2890 0,
74ad790c
MS
2891 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
2892 0},
a06ea964
NC
2893
2894 /* Get tp offset for a symbol. */
2895 {"tprel", 0,
6f4a313b 2896 0, /* adr_type */
a06ea964
NC
2897 0,
2898 0,
2899 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
74ad790c 2900 0,
a06ea964
NC
2901 0},
2902
2903 /* Get tp offset for a symbol. */
2904 {"tprel_lo12", 0,
6f4a313b 2905 0, /* adr_type */
a06ea964
NC
2906 0,
2907 0,
2908 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
84f1b9fb 2909 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12,
a06ea964
NC
2910 0},
2911
2912 /* Get tp offset for a symbol. */
2913 {"tprel_hi12", 0,
6f4a313b 2914 0, /* adr_type */
a06ea964
NC
2915 0,
2916 0,
2917 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
74ad790c 2918 0,
a06ea964
NC
2919 0},
2920
2921 /* Get tp offset for a symbol. */
2922 {"tprel_lo12_nc", 0,
6f4a313b 2923 0, /* adr_type */
a06ea964
NC
2924 0,
2925 0,
2926 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
84f1b9fb 2927 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC,
a06ea964
NC
2928 0},
2929
2930 /* Most significant bits 32-47 of address/value: MOVZ. */
2931 {"tprel_g2", 0,
6f4a313b 2932 0, /* adr_type */
a06ea964
NC
2933 0,
2934 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2935 0,
74ad790c 2936 0,
a06ea964
NC
2937 0},
2938
2939 /* Most significant bits 16-31 of address/value: MOVZ. */
2940 {"tprel_g1", 0,
6f4a313b 2941 0, /* adr_type */
a06ea964
NC
2942 0,
2943 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2944 0,
74ad790c 2945 0,
a06ea964
NC
2946 0},
2947
2948 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2949 {"tprel_g1_nc", 0,
6f4a313b 2950 0, /* adr_type */
a06ea964
NC
2951 0,
2952 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2953 0,
74ad790c 2954 0,
a06ea964
NC
2955 0},
2956
2957 /* Most significant bits 0-15 of address/value: MOVZ. */
2958 {"tprel_g0", 0,
6f4a313b 2959 0, /* adr_type */
a06ea964
NC
2960 0,
2961 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2962 0,
74ad790c 2963 0,
a06ea964
NC
2964 0},
2965
2966 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2967 {"tprel_g0_nc", 0,
6f4a313b 2968 0, /* adr_type */
a06ea964
NC
2969 0,
2970 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2971 0,
74ad790c 2972 0,
a06ea964 2973 0},
a921b5bd
JW
2974
2975 /* 15bit offset from got entry to base address of GOT table. */
2976 {"gotpage_lo15", 0,
2977 0,
2978 0,
2979 0,
2980 0,
2981 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
2982 0},
3d715ce4
JW
2983
2984 /* 14bit offset from got entry to base address of GOT table. */
2985 {"gotpage_lo14", 0,
2986 0,
2987 0,
2988 0,
2989 0,
2990 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14,
2991 0},
a06ea964
NC
2992};
2993
2994/* Given the address of a pointer pointing to the textual name of a
2995 relocation as may appear in assembler source, attempt to find its
2996 details in reloc_table. The pointer will be updated to the character
2997 after the trailing colon. On failure, NULL will be returned;
2998 otherwise return the reloc_table_entry. */
2999
3000static struct reloc_table_entry *
3001find_reloc_table_entry (char **str)
3002{
3003 unsigned int i;
3004 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
3005 {
3006 int length = strlen (reloc_table[i].name);
3007
3008 if (strncasecmp (reloc_table[i].name, *str, length) == 0
3009 && (*str)[length] == ':')
3010 {
3011 *str += (length + 1);
3012 return &reloc_table[i];
3013 }
3014 }
3015
3016 return NULL;
3017}
3018
3019/* Mode argument to parse_shift and parser_shifter_operand. */
3020enum parse_shift_mode
3021{
98907a70 3022 SHIFTED_NONE, /* no shifter allowed */
a06ea964
NC
3023 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3024 "#imm{,lsl #n}" */
3025 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3026 "#imm" */
3027 SHIFTED_LSL, /* bare "lsl #n" */
2442d846 3028 SHIFTED_MUL, /* bare "mul #n" */
a06ea964 3029 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
98907a70 3030 SHIFTED_MUL_VL, /* "mul vl" */
a06ea964
NC
3031 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
3032};
3033
3034/* Parse a <shift> operator on an AArch64 data processing instruction.
3035 Return TRUE on success; otherwise return FALSE. */
3036static bfd_boolean
3037parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
3038{
3039 const struct aarch64_name_value_pair *shift_op;
3040 enum aarch64_modifier_kind kind;
3041 expressionS exp;
3042 int exp_has_prefix;
3043 char *s = *str;
3044 char *p = s;
3045
3046 for (p = *str; ISALPHA (*p); p++)
3047 ;
3048
3049 if (p == *str)
3050 {
3051 set_syntax_error (_("shift expression expected"));
3052 return FALSE;
3053 }
3054
3055 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
3056
3057 if (shift_op == NULL)
3058 {
3059 set_syntax_error (_("shift operator expected"));
3060 return FALSE;
3061 }
3062
3063 kind = aarch64_get_operand_modifier (shift_op);
3064
3065 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
3066 {
3067 set_syntax_error (_("invalid use of 'MSL'"));
3068 return FALSE;
3069 }
3070
2442d846 3071 if (kind == AARCH64_MOD_MUL
98907a70
RS
3072 && mode != SHIFTED_MUL
3073 && mode != SHIFTED_MUL_VL)
2442d846
RS
3074 {
3075 set_syntax_error (_("invalid use of 'MUL'"));
3076 return FALSE;
3077 }
3078
a06ea964
NC
3079 switch (mode)
3080 {
3081 case SHIFTED_LOGIC_IMM:
535b785f 3082 if (aarch64_extend_operator_p (kind))
a06ea964
NC
3083 {
3084 set_syntax_error (_("extending shift is not permitted"));
3085 return FALSE;
3086 }
3087 break;
3088
3089 case SHIFTED_ARITH_IMM:
3090 if (kind == AARCH64_MOD_ROR)
3091 {
3092 set_syntax_error (_("'ROR' shift is not permitted"));
3093 return FALSE;
3094 }
3095 break;
3096
3097 case SHIFTED_LSL:
3098 if (kind != AARCH64_MOD_LSL)
3099 {
3100 set_syntax_error (_("only 'LSL' shift is permitted"));
3101 return FALSE;
3102 }
3103 break;
3104
2442d846
RS
3105 case SHIFTED_MUL:
3106 if (kind != AARCH64_MOD_MUL)
3107 {
3108 set_syntax_error (_("only 'MUL' is permitted"));
3109 return FALSE;
3110 }
3111 break;
3112
98907a70
RS
3113 case SHIFTED_MUL_VL:
3114 /* "MUL VL" consists of two separate tokens. Require the first
3115 token to be "MUL" and look for a following "VL". */
3116 if (kind == AARCH64_MOD_MUL)
3117 {
3118 skip_whitespace (p);
3119 if (strncasecmp (p, "vl", 2) == 0 && !ISALPHA (p[2]))
3120 {
3121 p += 2;
3122 kind = AARCH64_MOD_MUL_VL;
3123 break;
3124 }
3125 }
3126 set_syntax_error (_("only 'MUL VL' is permitted"));
3127 return FALSE;
3128
a06ea964
NC
3129 case SHIFTED_REG_OFFSET:
3130 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
3131 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
3132 {
3133 set_fatal_syntax_error
3134 (_("invalid shift for the register offset addressing mode"));
3135 return FALSE;
3136 }
3137 break;
3138
3139 case SHIFTED_LSL_MSL:
3140 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
3141 {
3142 set_syntax_error (_("invalid shift operator"));
3143 return FALSE;
3144 }
3145 break;
3146
3147 default:
3148 abort ();
3149 }
3150
3151 /* Whitespace can appear here if the next thing is a bare digit. */
3152 skip_whitespace (p);
3153
3154 /* Parse shift amount. */
3155 exp_has_prefix = 0;
98907a70 3156 if ((mode == SHIFTED_REG_OFFSET && *p == ']') || kind == AARCH64_MOD_MUL_VL)
a06ea964
NC
3157 exp.X_op = O_absent;
3158 else
3159 {
3160 if (is_immediate_prefix (*p))
3161 {
3162 p++;
3163 exp_has_prefix = 1;
3164 }
3165 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
3166 }
98907a70
RS
3167 if (kind == AARCH64_MOD_MUL_VL)
3168 /* For consistency, give MUL VL the same shift amount as an implicit
3169 MUL #1. */
3170 operand->shifter.amount = 1;
3171 else if (exp.X_op == O_absent)
a06ea964 3172 {
535b785f 3173 if (!aarch64_extend_operator_p (kind) || exp_has_prefix)
a06ea964
NC
3174 {
3175 set_syntax_error (_("missing shift amount"));
3176 return FALSE;
3177 }
3178 operand->shifter.amount = 0;
3179 }
3180 else if (exp.X_op != O_constant)
3181 {
3182 set_syntax_error (_("constant shift amount required"));
3183 return FALSE;
3184 }
2442d846
RS
3185 /* For parsing purposes, MUL #n has no inherent range. The range
3186 depends on the operand and will be checked by operand-specific
3187 routines. */
3188 else if (kind != AARCH64_MOD_MUL
3189 && (exp.X_add_number < 0 || exp.X_add_number > 63))
a06ea964
NC
3190 {
3191 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3192 return FALSE;
3193 }
3194 else
3195 {
3196 operand->shifter.amount = exp.X_add_number;
3197 operand->shifter.amount_present = 1;
3198 }
3199
3200 operand->shifter.operator_present = 1;
3201 operand->shifter.kind = kind;
3202
3203 *str = p;
3204 return TRUE;
3205}
3206
3207/* Parse a <shifter_operand> for a data processing instruction:
3208
3209 #<immediate>
3210 #<immediate>, LSL #imm
3211
3212 Validation of immediate operands is deferred to md_apply_fix.
3213
3214 Return TRUE on success; otherwise return FALSE. */
3215
3216static bfd_boolean
3217parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
3218 enum parse_shift_mode mode)
3219{
3220 char *p;
3221
3222 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
3223 return FALSE;
3224
3225 p = *str;
3226
3227 /* Accept an immediate expression. */
3228 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
3229 return FALSE;
3230
3231 /* Accept optional LSL for arithmetic immediate values. */
3232 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
3233 if (! parse_shift (&p, operand, SHIFTED_LSL))
3234 return FALSE;
3235
3236 /* Not accept any shifter for logical immediate values. */
3237 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
3238 && parse_shift (&p, operand, mode))
3239 {
3240 set_syntax_error (_("unexpected shift operator"));
3241 return FALSE;
3242 }
3243
3244 *str = p;
3245 return TRUE;
3246}
3247
3248/* Parse a <shifter_operand> for a data processing instruction:
3249
3250 <Rm>
3251 <Rm>, <shift>
3252 #<immediate>
3253 #<immediate>, LSL #imm
3254
3255 where <shift> is handled by parse_shift above, and the last two
3256 cases are handled by the function above.
3257
3258 Validation of immediate operands is deferred to md_apply_fix.
3259
3260 Return TRUE on success; otherwise return FALSE. */
3261
3262static bfd_boolean
3263parse_shifter_operand (char **str, aarch64_opnd_info *operand,
3264 enum parse_shift_mode mode)
3265{
e1b988bb
RS
3266 const reg_entry *reg;
3267 aarch64_opnd_qualifier_t qualifier;
a06ea964
NC
3268 enum aarch64_operand_class opd_class
3269 = aarch64_get_operand_class (operand->type);
3270
e1b988bb
RS
3271 reg = aarch64_reg_parse_32_64 (str, &qualifier);
3272 if (reg)
a06ea964
NC
3273 {
3274 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
3275 {
3276 set_syntax_error (_("unexpected register in the immediate operand"));
3277 return FALSE;
3278 }
3279
e1b988bb 3280 if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
a06ea964 3281 {
e1b988bb 3282 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
a06ea964
NC
3283 return FALSE;
3284 }
3285
e1b988bb
RS
3286 operand->reg.regno = reg->number;
3287 operand->qualifier = qualifier;
a06ea964
NC
3288
3289 /* Accept optional shift operation on register. */
3290 if (! skip_past_comma (str))
3291 return TRUE;
3292
3293 if (! parse_shift (str, operand, mode))
3294 return FALSE;
3295
3296 return TRUE;
3297 }
3298 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
3299 {
3300 set_syntax_error
3301 (_("integer register expected in the extended/shifted operand "
3302 "register"));
3303 return FALSE;
3304 }
3305
3306 /* We have a shifted immediate variable. */
3307 return parse_shifter_operand_imm (str, operand, mode);
3308}
3309
3310/* Return TRUE on success; return FALSE otherwise. */
3311
3312static bfd_boolean
3313parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
3314 enum parse_shift_mode mode)
3315{
3316 char *p = *str;
3317
3318 /* Determine if we have the sequence of characters #: or just :
3319 coming next. If we do, then we check for a :rello: relocation
3320 modifier. If we don't, punt the whole lot to
3321 parse_shifter_operand. */
3322
3323 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
3324 {
3325 struct reloc_table_entry *entry;
3326
3327 if (p[0] == '#')
3328 p += 2;
3329 else
3330 p++;
3331 *str = p;
3332
3333 /* Try to parse a relocation. Anything else is an error. */
3334 if (!(entry = find_reloc_table_entry (str)))
3335 {
3336 set_syntax_error (_("unknown relocation modifier"));
3337 return FALSE;
3338 }
3339
3340 if (entry->add_type == 0)
3341 {
3342 set_syntax_error
3343 (_("this relocation modifier is not allowed on this instruction"));
3344 return FALSE;
3345 }
3346
3347 /* Save str before we decompose it. */
3348 p = *str;
3349
3350 /* Next, we parse the expression. */
3351 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
3352 return FALSE;
3353
3354 /* Record the relocation type (use the ADD variant here). */
3355 inst.reloc.type = entry->add_type;
3356 inst.reloc.pc_rel = entry->pc_rel;
3357
3358 /* If str is empty, we've reached the end, stop here. */
3359 if (**str == '\0')
3360 return TRUE;
3361
55d9b4c1 3362 /* Otherwise, we have a shifted reloc modifier, so rewind to
a06ea964
NC
3363 recover the variable name and continue parsing for the shifter. */
3364 *str = p;
3365 return parse_shifter_operand_imm (str, operand, mode);
3366 }
3367
3368 return parse_shifter_operand (str, operand, mode);
3369}
3370
3371/* Parse all forms of an address expression. Information is written
3372 to *OPERAND and/or inst.reloc.
3373
3374 The A64 instruction set has the following addressing modes:
3375
3376 Offset
4df068de
RS
3377 [base] // in SIMD ld/st structure
3378 [base{,#0}] // in ld/st exclusive
a06ea964
NC
3379 [base{,#imm}]
3380 [base,Xm{,LSL #imm}]
3381 [base,Xm,SXTX {#imm}]
3382 [base,Wm,(S|U)XTW {#imm}]
3383 Pre-indexed
3384 [base,#imm]!
3385 Post-indexed
3386 [base],#imm
4df068de 3387 [base],Xm // in SIMD ld/st structure
a06ea964
NC
3388 PC-relative (literal)
3389 label
4df068de 3390 SVE:
98907a70 3391 [base,#imm,MUL VL]
4df068de
RS
3392 [base,Zm.D{,LSL #imm}]
3393 [base,Zm.S,(S|U)XTW {#imm}]
3394 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3395 [Zn.S,#imm]
3396 [Zn.D,#imm]
c469c864 3397 [Zn.S{, Xm}]
4df068de
RS
3398 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3399 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3400 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
a06ea964
NC
3401
3402 (As a convenience, the notation "=immediate" is permitted in conjunction
3403 with the pc-relative literal load instructions to automatically place an
3404 immediate value or symbolic address in a nearby literal pool and generate
3405 a hidden label which references it.)
3406
3407 Upon a successful parsing, the address structure in *OPERAND will be
3408 filled in the following way:
3409
3410 .base_regno = <base>
3411 .offset.is_reg // 1 if the offset is a register
3412 .offset.imm = <imm>
3413 .offset.regno = <Rm>
3414
3415 For different addressing modes defined in the A64 ISA:
3416
3417 Offset
3418 .pcrel=0; .preind=1; .postind=0; .writeback=0
3419 Pre-indexed
3420 .pcrel=0; .preind=1; .postind=0; .writeback=1
3421 Post-indexed
3422 .pcrel=0; .preind=0; .postind=1; .writeback=1
3423 PC-relative (literal)
3424 .pcrel=1; .preind=1; .postind=0; .writeback=0
3425
3426 The shift/extension information, if any, will be stored in .shifter.
4df068de
RS
3427 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3428 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3429 corresponding register.
a06ea964 3430
4df068de 3431 BASE_TYPE says which types of base register should be accepted and
98907a70
RS
3432 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3433 is the type of shifter that is allowed for immediate offsets,
3434 or SHIFTED_NONE if none.
3435
3436 In all other respects, it is the caller's responsibility to check
3437 for addressing modes not supported by the instruction, and to set
3438 inst.reloc.type. */
a06ea964
NC
3439
3440static bfd_boolean
4df068de
RS
3441parse_address_main (char **str, aarch64_opnd_info *operand,
3442 aarch64_opnd_qualifier_t *base_qualifier,
3443 aarch64_opnd_qualifier_t *offset_qualifier,
98907a70
RS
3444 aarch64_reg_type base_type, aarch64_reg_type offset_type,
3445 enum parse_shift_mode imm_shift_mode)
a06ea964
NC
3446{
3447 char *p = *str;
e1b988bb 3448 const reg_entry *reg;
a06ea964
NC
3449 expressionS *exp = &inst.reloc.exp;
3450
4df068de
RS
3451 *base_qualifier = AARCH64_OPND_QLF_NIL;
3452 *offset_qualifier = AARCH64_OPND_QLF_NIL;
a06ea964
NC
3453 if (! skip_past_char (&p, '['))
3454 {
3455 /* =immediate or label. */
3456 operand->addr.pcrel = 1;
3457 operand->addr.preind = 1;
3458
f41aef5f
RE
3459 /* #:<reloc_op>:<symbol> */
3460 skip_past_char (&p, '#');
73866052 3461 if (skip_past_char (&p, ':'))
f41aef5f 3462 {
6f4a313b 3463 bfd_reloc_code_real_type ty;
f41aef5f
RE
3464 struct reloc_table_entry *entry;
3465
3466 /* Try to parse a relocation modifier. Anything else is
3467 an error. */
3468 entry = find_reloc_table_entry (&p);
3469 if (! entry)
3470 {
3471 set_syntax_error (_("unknown relocation modifier"));
3472 return FALSE;
3473 }
3474
6f4a313b
MS
3475 switch (operand->type)
3476 {
3477 case AARCH64_OPND_ADDR_PCREL21:
3478 /* adr */
3479 ty = entry->adr_type;
3480 break;
3481
3482 default:
74ad790c 3483 ty = entry->ld_literal_type;
6f4a313b
MS
3484 break;
3485 }
3486
3487 if (ty == 0)
f41aef5f
RE
3488 {
3489 set_syntax_error
3490 (_("this relocation modifier is not allowed on this "
3491 "instruction"));
3492 return FALSE;
3493 }
3494
3495 /* #:<reloc_op>: */
3496 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3497 {
3498 set_syntax_error (_("invalid relocation expression"));
3499 return FALSE;
3500 }
a06ea964 3501
f41aef5f 3502 /* #:<reloc_op>:<expr> */
6f4a313b
MS
3503 /* Record the relocation type. */
3504 inst.reloc.type = ty;
f41aef5f
RE
3505 inst.reloc.pc_rel = entry->pc_rel;
3506 }
3507 else
a06ea964 3508 {
f41aef5f
RE
3509
3510 if (skip_past_char (&p, '='))
3511 /* =immediate; need to generate the literal in the literal pool. */
3512 inst.gen_lit_pool = 1;
3513
3514 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3515 {
3516 set_syntax_error (_("invalid address"));
3517 return FALSE;
3518 }
a06ea964
NC
3519 }
3520
3521 *str = p;
3522 return TRUE;
3523 }
3524
3525 /* [ */
3526
4df068de
RS
3527 reg = aarch64_addr_reg_parse (&p, base_type, base_qualifier);
3528 if (!reg || !aarch64_check_reg_type (reg, base_type))
a06ea964 3529 {
4df068de 3530 set_syntax_error (_(get_reg_expected_msg (base_type)));
a06ea964
NC
3531 return FALSE;
3532 }
e1b988bb 3533 operand->addr.base_regno = reg->number;
a06ea964
NC
3534
3535 /* [Xn */
3536 if (skip_past_comma (&p))
3537 {
3538 /* [Xn, */
3539 operand->addr.preind = 1;
3540
4df068de 3541 reg = aarch64_addr_reg_parse (&p, offset_type, offset_qualifier);
e1b988bb 3542 if (reg)
a06ea964 3543 {
4df068de 3544 if (!aarch64_check_reg_type (reg, offset_type))
e1b988bb 3545 {
4df068de 3546 set_syntax_error (_(get_reg_expected_msg (offset_type)));
e1b988bb
RS
3547 return FALSE;
3548 }
3549
a06ea964 3550 /* [Xn,Rm */
e1b988bb 3551 operand->addr.offset.regno = reg->number;
a06ea964
NC
3552 operand->addr.offset.is_reg = 1;
3553 /* Shifted index. */
3554 if (skip_past_comma (&p))
3555 {
3556 /* [Xn,Rm, */
3557 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
3558 /* Use the diagnostics set in parse_shift, so not set new
3559 error message here. */
3560 return FALSE;
3561 }
3562 /* We only accept:
c469c864 3563 [base,Xm] # For vector plus scalar SVE2 indexing.
a06ea964
NC
3564 [base,Xm{,LSL #imm}]
3565 [base,Xm,SXTX {#imm}]
3566 [base,Wm,(S|U)XTW {#imm}] */
3567 if (operand->shifter.kind == AARCH64_MOD_NONE
3568 || operand->shifter.kind == AARCH64_MOD_LSL
3569 || operand->shifter.kind == AARCH64_MOD_SXTX)
3570 {
4df068de 3571 if (*offset_qualifier == AARCH64_OPND_QLF_W)
a06ea964
NC
3572 {
3573 set_syntax_error (_("invalid use of 32-bit register offset"));
3574 return FALSE;
3575 }
4df068de 3576 if (aarch64_get_qualifier_esize (*base_qualifier)
c469c864
MM
3577 != aarch64_get_qualifier_esize (*offset_qualifier)
3578 && (operand->type != AARCH64_OPND_SVE_ADDR_ZX
3579 || *base_qualifier != AARCH64_OPND_QLF_S_S
3580 || *offset_qualifier != AARCH64_OPND_QLF_X))
4df068de
RS
3581 {
3582 set_syntax_error (_("offset has different size from base"));
3583 return FALSE;
3584 }
a06ea964 3585 }
4df068de 3586 else if (*offset_qualifier == AARCH64_OPND_QLF_X)
a06ea964
NC
3587 {
3588 set_syntax_error (_("invalid use of 64-bit register offset"));
3589 return FALSE;
3590 }
3591 }
3592 else
3593 {
3594 /* [Xn,#:<reloc_op>:<symbol> */
3595 skip_past_char (&p, '#');
73866052 3596 if (skip_past_char (&p, ':'))
a06ea964
NC
3597 {
3598 struct reloc_table_entry *entry;
3599
3600 /* Try to parse a relocation modifier. Anything else is
3601 an error. */
3602 if (!(entry = find_reloc_table_entry (&p)))
3603 {
3604 set_syntax_error (_("unknown relocation modifier"));
3605 return FALSE;
3606 }
3607
3608 if (entry->ldst_type == 0)
3609 {
3610 set_syntax_error
3611 (_("this relocation modifier is not allowed on this "
3612 "instruction"));
3613 return FALSE;
3614 }
3615
3616 /* [Xn,#:<reloc_op>: */
3617 /* We now have the group relocation table entry corresponding to
3618 the name in the assembler source. Next, we parse the
3619 expression. */
3620 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3621 {
3622 set_syntax_error (_("invalid relocation expression"));
3623 return FALSE;
3624 }
3625
3626 /* [Xn,#:<reloc_op>:<expr> */
3627 /* Record the load/store relocation type. */
3628 inst.reloc.type = entry->ldst_type;
3629 inst.reloc.pc_rel = entry->pc_rel;
3630 }
98907a70 3631 else
a06ea964 3632 {
98907a70
RS
3633 if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3634 {
3635 set_syntax_error (_("invalid expression in the address"));
3636 return FALSE;
3637 }
3638 /* [Xn,<expr> */
3639 if (imm_shift_mode != SHIFTED_NONE && skip_past_comma (&p))
3640 /* [Xn,<expr>,<shifter> */
3641 if (! parse_shift (&p, operand, imm_shift_mode))
3642 return FALSE;
a06ea964 3643 }
a06ea964
NC
3644 }
3645 }
3646
3647 if (! skip_past_char (&p, ']'))
3648 {
3649 set_syntax_error (_("']' expected"));
3650 return FALSE;
3651 }
3652
3653 if (skip_past_char (&p, '!'))
3654 {
3655 if (operand->addr.preind && operand->addr.offset.is_reg)
3656 {
3657 set_syntax_error (_("register offset not allowed in pre-indexed "
3658 "addressing mode"));
3659 return FALSE;
3660 }
3661 /* [Xn]! */
3662 operand->addr.writeback = 1;
3663 }
3664 else if (skip_past_comma (&p))
3665 {
3666 /* [Xn], */
3667 operand->addr.postind = 1;
3668 operand->addr.writeback = 1;
3669
3670 if (operand->addr.preind)
3671 {
3672 set_syntax_error (_("cannot combine pre- and post-indexing"));
3673 return FALSE;
3674 }
3675
4df068de 3676 reg = aarch64_reg_parse_32_64 (&p, offset_qualifier);
73866052 3677 if (reg)
a06ea964
NC
3678 {
3679 /* [Xn],Xm */
e1b988bb 3680 if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
a06ea964 3681 {
e1b988bb 3682 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
a06ea964
NC
3683 return FALSE;
3684 }
e1b988bb
RS
3685
3686 operand->addr.offset.regno = reg->number;
a06ea964
NC
3687 operand->addr.offset.is_reg = 1;
3688 }
3689 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3690 {
3691 /* [Xn],#expr */
3692 set_syntax_error (_("invalid expression in the address"));
3693 return FALSE;
3694 }
3695 }
3696
3697 /* If at this point neither .preind nor .postind is set, we have a
c469c864
MM
3698 bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0].
3699 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3700 [Zn.<T>, xzr]. */
a06ea964
NC
3701 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3702 {
550fd7bf 3703 if (operand->addr.writeback)
a06ea964
NC
3704 {
3705 /* Reject [Rn]! */
3706 set_syntax_error (_("missing offset in the pre-indexed address"));
3707 return FALSE;
3708 }
c8d59609 3709
a06ea964 3710 operand->addr.preind = 1;
c469c864
MM
3711 if (operand->type == AARCH64_OPND_SVE_ADDR_ZX)
3712 {
3713 operand->addr.offset.is_reg = 1;
3714 operand->addr.offset.regno = REG_ZR;
3715 *offset_qualifier = AARCH64_OPND_QLF_X;
3716 }
3717 else
3718 {
3719 inst.reloc.exp.X_op = O_constant;
3720 inst.reloc.exp.X_add_number = 0;
3721 }
a06ea964
NC
3722 }
3723
3724 *str = p;
3725 return TRUE;
3726}
3727
73866052
RS
3728/* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3729 on success. */
a06ea964 3730static bfd_boolean
73866052 3731parse_address (char **str, aarch64_opnd_info *operand)
a06ea964 3732{
4df068de
RS
3733 aarch64_opnd_qualifier_t base_qualifier, offset_qualifier;
3734 return parse_address_main (str, operand, &base_qualifier, &offset_qualifier,
98907a70 3735 REG_TYPE_R64_SP, REG_TYPE_R_Z, SHIFTED_NONE);
4df068de
RS
3736}
3737
98907a70 3738/* Parse an address in which SVE vector registers and MUL VL are allowed.
4df068de
RS
3739 The arguments have the same meaning as for parse_address_main.
3740 Return TRUE on success. */
3741static bfd_boolean
3742parse_sve_address (char **str, aarch64_opnd_info *operand,
3743 aarch64_opnd_qualifier_t *base_qualifier,
3744 aarch64_opnd_qualifier_t *offset_qualifier)
3745{
3746 return parse_address_main (str, operand, base_qualifier, offset_qualifier,
98907a70
RS
3747 REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET,
3748 SHIFTED_MUL_VL);
a06ea964
NC
3749}
3750
3751/* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3752 Return TRUE on success; otherwise return FALSE. */
3753static bfd_boolean
3754parse_half (char **str, int *internal_fixup_p)
3755{
671eeb28 3756 char *p = *str;
a06ea964 3757
a06ea964
NC
3758 skip_past_char (&p, '#');
3759
3760 gas_assert (internal_fixup_p);
3761 *internal_fixup_p = 0;
3762
3763 if (*p == ':')
3764 {
3765 struct reloc_table_entry *entry;
3766
3767 /* Try to parse a relocation. Anything else is an error. */
3768 ++p;
3769 if (!(entry = find_reloc_table_entry (&p)))
3770 {
3771 set_syntax_error (_("unknown relocation modifier"));
3772 return FALSE;
3773 }
3774
3775 if (entry->movw_type == 0)
3776 {
3777 set_syntax_error
3778 (_("this relocation modifier is not allowed on this instruction"));
3779 return FALSE;
3780 }
3781
3782 inst.reloc.type = entry->movw_type;
3783 }
3784 else
3785 *internal_fixup_p = 1;
3786
a06ea964
NC
3787 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3788 return FALSE;
3789
3790 *str = p;
3791 return TRUE;
3792}
3793
3794/* Parse an operand for an ADRP instruction:
3795 ADRP <Xd>, <label>
3796 Return TRUE on success; otherwise return FALSE. */
3797
3798static bfd_boolean
3799parse_adrp (char **str)
3800{
3801 char *p;
3802
3803 p = *str;
3804 if (*p == ':')
3805 {
3806 struct reloc_table_entry *entry;
3807
3808 /* Try to parse a relocation. Anything else is an error. */
3809 ++p;
3810 if (!(entry = find_reloc_table_entry (&p)))
3811 {
3812 set_syntax_error (_("unknown relocation modifier"));
3813 return FALSE;
3814 }
3815
3816 if (entry->adrp_type == 0)
3817 {
3818 set_syntax_error
3819 (_("this relocation modifier is not allowed on this instruction"));
3820 return FALSE;
3821 }
3822
3823 inst.reloc.type = entry->adrp_type;
3824 }
3825 else
3826 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3827
3828 inst.reloc.pc_rel = 1;
3829
3830 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3831 return FALSE;
3832
3833 *str = p;
3834 return TRUE;
3835}
3836
3837/* Miscellaneous. */
3838
245d2e3f
RS
3839/* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3840 of SIZE tokens in which index I gives the token for field value I,
3841 or is null if field value I is invalid. REG_TYPE says which register
3842 names should be treated as registers rather than as symbolic immediates.
3843
3844 Return true on success, moving *STR past the operand and storing the
3845 field value in *VAL. */
3846
3847static int
3848parse_enum_string (char **str, int64_t *val, const char *const *array,
3849 size_t size, aarch64_reg_type reg_type)
3850{
3851 expressionS exp;
3852 char *p, *q;
3853 size_t i;
3854
3855 /* Match C-like tokens. */
3856 p = q = *str;
3857 while (ISALNUM (*q))
3858 q++;
3859
3860 for (i = 0; i < size; ++i)
3861 if (array[i]
3862 && strncasecmp (array[i], p, q - p) == 0
3863 && array[i][q - p] == 0)
3864 {
3865 *val = i;
3866 *str = q;
3867 return TRUE;
3868 }
3869
3870 if (!parse_immediate_expression (&p, &exp, reg_type))
3871 return FALSE;
3872
3873 if (exp.X_op == O_constant
3874 && (uint64_t) exp.X_add_number < size)
3875 {
3876 *val = exp.X_add_number;
3877 *str = p;
3878 return TRUE;
3879 }
3880
3881 /* Use the default error for this operand. */
3882 return FALSE;
3883}
3884
a06ea964
NC
3885/* Parse an option for a preload instruction. Returns the encoding for the
3886 option, or PARSE_FAIL. */
3887
3888static int
3889parse_pldop (char **str)
3890{
3891 char *p, *q;
3892 const struct aarch64_name_value_pair *o;
3893
3894 p = q = *str;
3895 while (ISALNUM (*q))
3896 q++;
3897
3898 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3899 if (!o)
3900 return PARSE_FAIL;
3901
3902 *str = q;
3903 return o->value;
3904}
3905
3906/* Parse an option for a barrier instruction. Returns the encoding for the
3907 option, or PARSE_FAIL. */
3908
3909static int
3910parse_barrier (char **str)
3911{
3912 char *p, *q;
3913 const asm_barrier_opt *o;
3914
3915 p = q = *str;
3916 while (ISALPHA (*q))
3917 q++;
3918
3919 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3920 if (!o)
3921 return PARSE_FAIL;
3922
3923 *str = q;
3924 return o->value;
3925}
3926
1e6f4800
MW
3927/* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3928 return 0 if successful. Otherwise return PARSE_FAIL. */
3929
3930static int
3931parse_barrier_psb (char **str,
3932 const struct aarch64_name_value_pair ** hint_opt)
3933{
3934 char *p, *q;
3935 const struct aarch64_name_value_pair *o;
3936
3937 p = q = *str;
3938 while (ISALPHA (*q))
3939 q++;
3940
3941 o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
3942 if (!o)
3943 {
3944 set_fatal_syntax_error
3945 ( _("unknown or missing option to PSB"));
3946 return PARSE_FAIL;
3947 }
3948
3949 if (o->value != 0x11)
3950 {
3951 /* PSB only accepts option name 'CSYNC'. */
3952 set_syntax_error
3953 (_("the specified option is not accepted for PSB"));
3954 return PARSE_FAIL;
3955 }
3956
3957 *str = q;
3958 *hint_opt = o;
3959 return 0;
3960}
3961
ff605452
SD
3962/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3963 return 0 if successful. Otherwise return PARSE_FAIL. */
3964
3965static int
3966parse_bti_operand (char **str,
3967 const struct aarch64_name_value_pair ** hint_opt)
3968{
3969 char *p, *q;
3970 const struct aarch64_name_value_pair *o;
3971
3972 p = q = *str;
3973 while (ISALPHA (*q))
3974 q++;
3975
3976 o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
3977 if (!o)
3978 {
3979 set_fatal_syntax_error
3980 ( _("unknown option to BTI"));
3981 return PARSE_FAIL;
3982 }
3983
3984 switch (o->value)
3985 {
3986 /* Valid BTI operands. */
3987 case HINT_OPD_C:
3988 case HINT_OPD_J:
3989 case HINT_OPD_JC:
3990 break;
3991
3992 default:
3993 set_syntax_error
3994 (_("unknown option to BTI"));
3995 return PARSE_FAIL;
3996 }
3997
3998 *str = q;
3999 *hint_opt = o;
4000 return 0;
4001}
4002
a06ea964 4003/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
a203d9b7 4004 Returns the encoding for the option, or PARSE_FAIL.
a06ea964
NC
4005
4006 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
72ca8fad
MW
4007 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4008
4009 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4010 field, otherwise as a system register.
4011*/
a06ea964
NC
4012
4013static int
72ca8fad 4014parse_sys_reg (char **str, struct hash_control *sys_regs,
561a72d4
TC
4015 int imple_defined_p, int pstatefield_p,
4016 uint32_t* flags)
a06ea964
NC
4017{
4018 char *p, *q;
4019 char buf[32];
49eec193 4020 const aarch64_sys_reg *o;
a06ea964
NC
4021 int value;
4022
4023 p = buf;
4024 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
4025 if (p < buf + 31)
4026 *p++ = TOLOWER (*q);
4027 *p = '\0';
4028 /* Assert that BUF be large enough. */
4029 gas_assert (p - buf == q - *str);
4030
4031 o = hash_find (sys_regs, buf);
4032 if (!o)
4033 {
4034 if (!imple_defined_p)
4035 return PARSE_FAIL;
4036 else
4037 {
df7b4545 4038 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
a06ea964 4039 unsigned int op0, op1, cn, cm, op2;
df7b4545
JW
4040
4041 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2)
4042 != 5)
a06ea964 4043 return PARSE_FAIL;
df7b4545 4044 if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
a06ea964
NC
4045 return PARSE_FAIL;
4046 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
561a72d4
TC
4047 if (flags)
4048 *flags = 0;
a06ea964
NC
4049 }
4050 }
4051 else
49eec193 4052 {
72ca8fad
MW
4053 if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
4054 as_bad (_("selected processor does not support PSTATE field "
4055 "name '%s'"), buf);
4056 if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
4057 as_bad (_("selected processor does not support system register "
4058 "name '%s'"), buf);
9a73e520 4059 if (aarch64_sys_reg_deprecated_p (o))
49eec193 4060 as_warn (_("system register name '%s' is deprecated and may be "
72ca8fad 4061 "removed in a future release"), buf);
49eec193 4062 value = o->value;
561a72d4
TC
4063 if (flags)
4064 *flags = o->flags;
49eec193 4065 }
a06ea964
NC
4066
4067 *str = q;
4068 return value;
4069}
4070
4071/* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4072 for the option, or NULL. */
4073
4074static const aarch64_sys_ins_reg *
4075parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
4076{
4077 char *p, *q;
4078 char buf[32];
4079 const aarch64_sys_ins_reg *o;
4080
4081 p = buf;
4082 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
4083 if (p < buf + 31)
4084 *p++ = TOLOWER (*q);
4085 *p = '\0';
4086
4087 o = hash_find (sys_ins_regs, buf);
4088 if (!o)
4089 return NULL;
4090
d6bf7ce6
MW
4091 if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
4092 as_bad (_("selected processor does not support system register "
4093 "name '%s'"), buf);
4094
a06ea964
NC
4095 *str = q;
4096 return o;
4097}
4098\f
4099#define po_char_or_fail(chr) do { \
4100 if (! skip_past_char (&str, chr)) \
4101 goto failure; \
4102} while (0)
4103
4104#define po_reg_or_fail(regtype) do { \
4105 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4106 if (val == PARSE_FAIL) \
4107 { \
4108 set_default_error (); \
4109 goto failure; \
4110 } \
4111 } while (0)
4112
e1b988bb
RS
4113#define po_int_reg_or_fail(reg_type) do { \
4114 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4115 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
a06ea964
NC
4116 { \
4117 set_default_error (); \
4118 goto failure; \
4119 } \
e1b988bb
RS
4120 info->reg.regno = reg->number; \
4121 info->qualifier = qualifier; \
a06ea964
NC
4122 } while (0)
4123
4124#define po_imm_nc_or_fail() do { \
1799c0d0 4125 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
a06ea964
NC
4126 goto failure; \
4127 } while (0)
4128
4129#define po_imm_or_fail(min, max) do { \
1799c0d0 4130 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
a06ea964
NC
4131 goto failure; \
4132 if (val < min || val > max) \
4133 { \
4134 set_fatal_syntax_error (_("immediate value out of range "\
4135#min " to "#max)); \
4136 goto failure; \
4137 } \
4138 } while (0)
4139
245d2e3f
RS
4140#define po_enum_or_fail(array) do { \
4141 if (!parse_enum_string (&str, &val, array, \
4142 ARRAY_SIZE (array), imm_reg_type)) \
4143 goto failure; \
4144 } while (0)
4145
a06ea964
NC
4146#define po_misc_or_fail(expr) do { \
4147 if (!expr) \
4148 goto failure; \
4149 } while (0)
4150\f
4151/* encode the 12-bit imm field of Add/sub immediate */
4152static inline uint32_t
4153encode_addsub_imm (uint32_t imm)
4154{
4155 return imm << 10;
4156}
4157
4158/* encode the shift amount field of Add/sub immediate */
4159static inline uint32_t
4160encode_addsub_imm_shift_amount (uint32_t cnt)
4161{
4162 return cnt << 22;
4163}
4164
4165
4166/* encode the imm field of Adr instruction */
4167static inline uint32_t
4168encode_adr_imm (uint32_t imm)
4169{
4170 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
4171 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4172}
4173
4174/* encode the immediate field of Move wide immediate */
4175static inline uint32_t
4176encode_movw_imm (uint32_t imm)
4177{
4178 return imm << 5;
4179}
4180
4181/* encode the 26-bit offset of unconditional branch */
4182static inline uint32_t
4183encode_branch_ofs_26 (uint32_t ofs)
4184{
4185 return ofs & ((1 << 26) - 1);
4186}
4187
4188/* encode the 19-bit offset of conditional branch and compare & branch */
4189static inline uint32_t
4190encode_cond_branch_ofs_19 (uint32_t ofs)
4191{
4192 return (ofs & ((1 << 19) - 1)) << 5;
4193}
4194
4195/* encode the 19-bit offset of ld literal */
4196static inline uint32_t
4197encode_ld_lit_ofs_19 (uint32_t ofs)
4198{
4199 return (ofs & ((1 << 19) - 1)) << 5;
4200}
4201
4202/* Encode the 14-bit offset of test & branch. */
4203static inline uint32_t
4204encode_tst_branch_ofs_14 (uint32_t ofs)
4205{
4206 return (ofs & ((1 << 14) - 1)) << 5;
4207}
4208
4209/* Encode the 16-bit imm field of svc/hvc/smc. */
4210static inline uint32_t
4211encode_svc_imm (uint32_t imm)
4212{
4213 return imm << 5;
4214}
4215
4216/* Reencode add(s) to sub(s), or sub(s) to add(s). */
4217static inline uint32_t
4218reencode_addsub_switch_add_sub (uint32_t opcode)
4219{
4220 return opcode ^ (1 << 30);
4221}
4222
4223static inline uint32_t
4224reencode_movzn_to_movz (uint32_t opcode)
4225{
4226 return opcode | (1 << 30);
4227}
4228
4229static inline uint32_t
4230reencode_movzn_to_movn (uint32_t opcode)
4231{
4232 return opcode & ~(1 << 30);
4233}
4234
4235/* Overall per-instruction processing. */
4236
4237/* We need to be able to fix up arbitrary expressions in some statements.
4238 This is so that we can handle symbols that are an arbitrary distance from
4239 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4240 which returns part of an address in a form which will be valid for
4241 a data instruction. We do this by pushing the expression into a symbol
4242 in the expr_section, and creating a fix for that. */
4243
4244static fixS *
4245fix_new_aarch64 (fragS * frag,
4246 int where,
4247 short int size, expressionS * exp, int pc_rel, int reloc)
4248{
4249 fixS *new_fix;
4250
4251 switch (exp->X_op)
4252 {
4253 case O_constant:
4254 case O_symbol:
4255 case O_add:
4256 case O_subtract:
4257 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
4258 break;
4259
4260 default:
4261 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
4262 pc_rel, reloc);
4263 break;
4264 }
4265 return new_fix;
4266}
4267\f
4268/* Diagnostics on operands errors. */
4269
a52e6fd3
YZ
4270/* By default, output verbose error message.
4271 Disable the verbose error message by -mno-verbose-error. */
4272static int verbose_error_p = 1;
a06ea964
NC
4273
4274#ifdef DEBUG_AARCH64
4275/* N.B. this is only for the purpose of debugging. */
4276const char* operand_mismatch_kind_names[] =
4277{
4278 "AARCH64_OPDE_NIL",
4279 "AARCH64_OPDE_RECOVERABLE",
4280 "AARCH64_OPDE_SYNTAX_ERROR",
4281 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4282 "AARCH64_OPDE_INVALID_VARIANT",
4283 "AARCH64_OPDE_OUT_OF_RANGE",
4284 "AARCH64_OPDE_UNALIGNED",
4285 "AARCH64_OPDE_REG_LIST",
4286 "AARCH64_OPDE_OTHER_ERROR",
4287};
4288#endif /* DEBUG_AARCH64 */
4289
4290/* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4291
4292 When multiple errors of different kinds are found in the same assembly
4293 line, only the error of the highest severity will be picked up for
4294 issuing the diagnostics. */
4295
4296static inline bfd_boolean
4297operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
4298 enum aarch64_operand_error_kind rhs)
4299{
4300 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
4301 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
4302 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
4303 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
4304 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
4305 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
4306 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
4307 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
4308 return lhs > rhs;
4309}
4310
4311/* Helper routine to get the mnemonic name from the assembly instruction
4312 line; should only be called for the diagnosis purpose, as there is
4313 string copy operation involved, which may affect the runtime
4314 performance if used in elsewhere. */
4315
4316static const char*
4317get_mnemonic_name (const char *str)
4318{
4319 static char mnemonic[32];
4320 char *ptr;
4321
4322 /* Get the first 15 bytes and assume that the full name is included. */
4323 strncpy (mnemonic, str, 31);
4324 mnemonic[31] = '\0';
4325
4326 /* Scan up to the end of the mnemonic, which must end in white space,
4327 '.', or end of string. */
4328 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
4329 ;
4330
4331 *ptr = '\0';
4332
4333 /* Append '...' to the truncated long name. */
4334 if (ptr - mnemonic == 31)
4335 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
4336
4337 return mnemonic;
4338}
4339
4340static void
4341reset_aarch64_instruction (aarch64_instruction *instruction)
4342{
4343 memset (instruction, '\0', sizeof (aarch64_instruction));
4344 instruction->reloc.type = BFD_RELOC_UNUSED;
4345}
4346
33eaf5de 4347/* Data structures storing one user error in the assembly code related to
a06ea964
NC
4348 operands. */
4349
4350struct operand_error_record
4351{
4352 const aarch64_opcode *opcode;
4353 aarch64_operand_error detail;
4354 struct operand_error_record *next;
4355};
4356
4357typedef struct operand_error_record operand_error_record;
4358
4359struct operand_errors
4360{
4361 operand_error_record *head;
4362 operand_error_record *tail;
4363};
4364
4365typedef struct operand_errors operand_errors;
4366
4367/* Top-level data structure reporting user errors for the current line of
4368 the assembly code.
4369 The way md_assemble works is that all opcodes sharing the same mnemonic
4370 name are iterated to find a match to the assembly line. In this data
4371 structure, each of the such opcodes will have one operand_error_record
4372 allocated and inserted. In other words, excessive errors related with
4373 a single opcode are disregarded. */
4374operand_errors operand_error_report;
4375
4376/* Free record nodes. */
4377static operand_error_record *free_opnd_error_record_nodes = NULL;
4378
4379/* Initialize the data structure that stores the operand mismatch
4380 information on assembling one line of the assembly code. */
4381static void
4382init_operand_error_report (void)
4383{
4384 if (operand_error_report.head != NULL)
4385 {
4386 gas_assert (operand_error_report.tail != NULL);
4387 operand_error_report.tail->next = free_opnd_error_record_nodes;
4388 free_opnd_error_record_nodes = operand_error_report.head;
4389 operand_error_report.head = NULL;
4390 operand_error_report.tail = NULL;
4391 return;
4392 }
4393 gas_assert (operand_error_report.tail == NULL);
4394}
4395
4396/* Return TRUE if some operand error has been recorded during the
4397 parsing of the current assembly line using the opcode *OPCODE;
4398 otherwise return FALSE. */
4399static inline bfd_boolean
4400opcode_has_operand_error_p (const aarch64_opcode *opcode)
4401{
4402 operand_error_record *record = operand_error_report.head;
4403 return record && record->opcode == opcode;
4404}
4405
4406/* Add the error record *NEW_RECORD to operand_error_report. The record's
4407 OPCODE field is initialized with OPCODE.
4408 N.B. only one record for each opcode, i.e. the maximum of one error is
4409 recorded for each instruction template. */
4410
4411static void
4412add_operand_error_record (const operand_error_record* new_record)
4413{
4414 const aarch64_opcode *opcode = new_record->opcode;
4415 operand_error_record* record = operand_error_report.head;
4416
4417 /* The record may have been created for this opcode. If not, we need
4418 to prepare one. */
4419 if (! opcode_has_operand_error_p (opcode))
4420 {
4421 /* Get one empty record. */
4422 if (free_opnd_error_record_nodes == NULL)
4423 {
325801bd 4424 record = XNEW (operand_error_record);
a06ea964
NC
4425 }
4426 else
4427 {
4428 record = free_opnd_error_record_nodes;
4429 free_opnd_error_record_nodes = record->next;
4430 }
4431 record->opcode = opcode;
4432 /* Insert at the head. */
4433 record->next = operand_error_report.head;
4434 operand_error_report.head = record;
4435 if (operand_error_report.tail == NULL)
4436 operand_error_report.tail = record;
4437 }
4438 else if (record->detail.kind != AARCH64_OPDE_NIL
4439 && record->detail.index <= new_record->detail.index
4440 && operand_error_higher_severity_p (record->detail.kind,
4441 new_record->detail.kind))
4442 {
4443 /* In the case of multiple errors found on operands related with a
4444 single opcode, only record the error of the leftmost operand and
4445 only if the error is of higher severity. */
4446 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4447 " the existing error %s on operand %d",
4448 operand_mismatch_kind_names[new_record->detail.kind],
4449 new_record->detail.index,
4450 operand_mismatch_kind_names[record->detail.kind],
4451 record->detail.index);
4452 return;
4453 }
4454
4455 record->detail = new_record->detail;
4456}
4457
4458static inline void
4459record_operand_error_info (const aarch64_opcode *opcode,
4460 aarch64_operand_error *error_info)
4461{
4462 operand_error_record record;
4463 record.opcode = opcode;
4464 record.detail = *error_info;
4465 add_operand_error_record (&record);
4466}
4467
4468/* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4469 error message *ERROR, for operand IDX (count from 0). */
4470
4471static void
4472record_operand_error (const aarch64_opcode *opcode, int idx,
4473 enum aarch64_operand_error_kind kind,
4474 const char* error)
4475{
4476 aarch64_operand_error info;
4477 memset(&info, 0, sizeof (info));
4478 info.index = idx;
4479 info.kind = kind;
4480 info.error = error;
2a9b2c1a 4481 info.non_fatal = FALSE;
a06ea964
NC
4482 record_operand_error_info (opcode, &info);
4483}
4484
4485static void
4486record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
4487 enum aarch64_operand_error_kind kind,
4488 const char* error, const int *extra_data)
4489{
4490 aarch64_operand_error info;
4491 info.index = idx;
4492 info.kind = kind;
4493 info.error = error;
4494 info.data[0] = extra_data[0];
4495 info.data[1] = extra_data[1];
4496 info.data[2] = extra_data[2];
2a9b2c1a 4497 info.non_fatal = FALSE;
a06ea964
NC
4498 record_operand_error_info (opcode, &info);
4499}
4500
4501static void
4502record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
4503 const char* error, int lower_bound,
4504 int upper_bound)
4505{
4506 int data[3] = {lower_bound, upper_bound, 0};
4507 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
4508 error, data);
4509}
4510
4511/* Remove the operand error record for *OPCODE. */
4512static void ATTRIBUTE_UNUSED
4513remove_operand_error_record (const aarch64_opcode *opcode)
4514{
4515 if (opcode_has_operand_error_p (opcode))
4516 {
4517 operand_error_record* record = operand_error_report.head;
4518 gas_assert (record != NULL && operand_error_report.tail != NULL);
4519 operand_error_report.head = record->next;
4520 record->next = free_opnd_error_record_nodes;
4521 free_opnd_error_record_nodes = record;
4522 if (operand_error_report.head == NULL)
4523 {
4524 gas_assert (operand_error_report.tail == record);
4525 operand_error_report.tail = NULL;
4526 }
4527 }
4528}
4529
4530/* Given the instruction in *INSTR, return the index of the best matched
4531 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4532
4533 Return -1 if there is no qualifier sequence; return the first match
4534 if there is multiple matches found. */
4535
4536static int
4537find_best_match (const aarch64_inst *instr,
4538 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
4539{
4540 int i, num_opnds, max_num_matched, idx;
4541
4542 num_opnds = aarch64_num_of_operands (instr->opcode);
4543 if (num_opnds == 0)
4544 {
4545 DEBUG_TRACE ("no operand");
4546 return -1;
4547 }
4548
4549 max_num_matched = 0;
4989adac 4550 idx = 0;
a06ea964
NC
4551
4552 /* For each pattern. */
4553 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4554 {
4555 int j, num_matched;
4556 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
4557
4558 /* Most opcodes has much fewer patterns in the list. */
535b785f 4559 if (empty_qualifier_sequence_p (qualifiers))
a06ea964
NC
4560 {
4561 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
a06ea964
NC
4562 break;
4563 }
4564
4565 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
4566 if (*qualifiers == instr->operands[j].qualifier)
4567 ++num_matched;
4568
4569 if (num_matched > max_num_matched)
4570 {
4571 max_num_matched = num_matched;
4572 idx = i;
4573 }
4574 }
4575
4576 DEBUG_TRACE ("return with %d", idx);
4577 return idx;
4578}
4579
33eaf5de 4580/* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
a06ea964
NC
4581 corresponding operands in *INSTR. */
4582
4583static inline void
4584assign_qualifier_sequence (aarch64_inst *instr,
4585 const aarch64_opnd_qualifier_t *qualifiers)
4586{
4587 int i = 0;
4588 int num_opnds = aarch64_num_of_operands (instr->opcode);
4589 gas_assert (num_opnds);
4590 for (i = 0; i < num_opnds; ++i, ++qualifiers)
4591 instr->operands[i].qualifier = *qualifiers;
4592}
4593
4594/* Print operands for the diagnosis purpose. */
4595
4596static void
4597print_operands (char *buf, const aarch64_opcode *opcode,
4598 const aarch64_opnd_info *opnds)
4599{
4600 int i;
4601
4602 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
4603 {
08d3b0cc 4604 char str[128];
a06ea964
NC
4605
4606 /* We regard the opcode operand info more, however we also look into
4607 the inst->operands to support the disassembling of the optional
4608 operand.
4609 The two operand code should be the same in all cases, apart from
4610 when the operand can be optional. */
4611 if (opcode->operands[i] == AARCH64_OPND_NIL
4612 || opnds[i].type == AARCH64_OPND_NIL)
4613 break;
4614
4615 /* Generate the operand string in STR. */
7d02540a
TC
4616 aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL,
4617 NULL);
a06ea964
NC
4618
4619 /* Delimiter. */
4620 if (str[0] != '\0')
ad43e107 4621 strcat (buf, i == 0 ? " " : ", ");
a06ea964
NC
4622
4623 /* Append the operand string. */
4624 strcat (buf, str);
4625 }
4626}
4627
4628/* Send to stderr a string as information. */
4629
4630static void
4631output_info (const char *format, ...)
4632{
3b4dbbbf 4633 const char *file;
a06ea964
NC
4634 unsigned int line;
4635 va_list args;
4636
3b4dbbbf 4637 file = as_where (&line);
a06ea964
NC
4638 if (file)
4639 {
4640 if (line != 0)
4641 fprintf (stderr, "%s:%u: ", file, line);
4642 else
4643 fprintf (stderr, "%s: ", file);
4644 }
4645 fprintf (stderr, _("Info: "));
4646 va_start (args, format);
4647 vfprintf (stderr, format, args);
4648 va_end (args);
4649 (void) putc ('\n', stderr);
4650}
4651
4652/* Output one operand error record. */
4653
4654static void
4655output_operand_error_record (const operand_error_record *record, char *str)
4656{
28f013d5
JB
4657 const aarch64_operand_error *detail = &record->detail;
4658 int idx = detail->index;
a06ea964 4659 const aarch64_opcode *opcode = record->opcode;
28f013d5 4660 enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
a06ea964 4661 : AARCH64_OPND_NIL);
a06ea964 4662
7d02540a
TC
4663 typedef void (*handler_t)(const char *format, ...);
4664 handler_t handler = detail->non_fatal ? as_warn : as_bad;
4665
a06ea964
NC
4666 switch (detail->kind)
4667 {
4668 case AARCH64_OPDE_NIL:
4669 gas_assert (0);
4670 break;
a06ea964
NC
4671 case AARCH64_OPDE_SYNTAX_ERROR:
4672 case AARCH64_OPDE_RECOVERABLE:
4673 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
4674 case AARCH64_OPDE_OTHER_ERROR:
a06ea964
NC
4675 /* Use the prepared error message if there is, otherwise use the
4676 operand description string to describe the error. */
4677 if (detail->error != NULL)
4678 {
28f013d5 4679 if (idx < 0)
7d02540a 4680 handler (_("%s -- `%s'"), detail->error, str);
a06ea964 4681 else
7d02540a
TC
4682 handler (_("%s at operand %d -- `%s'"),
4683 detail->error, idx + 1, str);
a06ea964
NC
4684 }
4685 else
28f013d5
JB
4686 {
4687 gas_assert (idx >= 0);
7d02540a
TC
4688 handler (_("operand %d must be %s -- `%s'"), idx + 1,
4689 aarch64_get_operand_desc (opd_code), str);
28f013d5 4690 }
a06ea964
NC
4691 break;
4692
4693 case AARCH64_OPDE_INVALID_VARIANT:
7d02540a 4694 handler (_("operand mismatch -- `%s'"), str);
a06ea964
NC
4695 if (verbose_error_p)
4696 {
4697 /* We will try to correct the erroneous instruction and also provide
4698 more information e.g. all other valid variants.
4699
4700 The string representation of the corrected instruction and other
4701 valid variants are generated by
4702
4703 1) obtaining the intermediate representation of the erroneous
4704 instruction;
4705 2) manipulating the IR, e.g. replacing the operand qualifier;
4706 3) printing out the instruction by calling the printer functions
4707 shared with the disassembler.
4708
4709 The limitation of this method is that the exact input assembly
4710 line cannot be accurately reproduced in some cases, for example an
4711 optional operand present in the actual assembly line will be
4712 omitted in the output; likewise for the optional syntax rules,
4713 e.g. the # before the immediate. Another limitation is that the
4714 assembly symbols and relocation operations in the assembly line
4715 currently cannot be printed out in the error report. Last but not
4716 least, when there is other error(s) co-exist with this error, the
4717 'corrected' instruction may be still incorrect, e.g. given
4718 'ldnp h0,h1,[x0,#6]!'
4719 this diagnosis will provide the version:
4720 'ldnp s0,s1,[x0,#6]!'
4721 which is still not right. */
4722 size_t len = strlen (get_mnemonic_name (str));
4723 int i, qlf_idx;
4724 bfd_boolean result;
08d3b0cc 4725 char buf[2048];
a06ea964
NC
4726 aarch64_inst *inst_base = &inst.base;
4727 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
4728
4729 /* Init inst. */
4730 reset_aarch64_instruction (&inst);
4731 inst_base->opcode = opcode;
4732
4733 /* Reset the error report so that there is no side effect on the
4734 following operand parsing. */
4735 init_operand_error_report ();
4736
4737 /* Fill inst. */
4738 result = parse_operands (str + len, opcode)
4739 && programmer_friendly_fixup (&inst);
4740 gas_assert (result);
4741 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
7e84b55d 4742 NULL, NULL, insn_sequence);
a06ea964
NC
4743 gas_assert (!result);
4744
4745 /* Find the most matched qualifier sequence. */
4746 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
4747 gas_assert (qlf_idx > -1);
4748
4749 /* Assign the qualifiers. */
4750 assign_qualifier_sequence (inst_base,
4751 opcode->qualifiers_list[qlf_idx]);
4752
4753 /* Print the hint. */
4754 output_info (_(" did you mean this?"));
08d3b0cc 4755 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
a06ea964
NC
4756 print_operands (buf, opcode, inst_base->operands);
4757 output_info (_(" %s"), buf);
4758
4759 /* Print out other variant(s) if there is any. */
4760 if (qlf_idx != 0 ||
4761 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4762 output_info (_(" other valid variant(s):"));
4763
4764 /* For each pattern. */
4765 qualifiers_list = opcode->qualifiers_list;
4766 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4767 {
4768 /* Most opcodes has much fewer patterns in the list.
4769 First NIL qualifier indicates the end in the list. */
535b785f 4770 if (empty_qualifier_sequence_p (*qualifiers_list))
a06ea964
NC
4771 break;
4772
4773 if (i != qlf_idx)
4774 {
4775 /* Mnemonics name. */
08d3b0cc 4776 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
a06ea964
NC
4777
4778 /* Assign the qualifiers. */
4779 assign_qualifier_sequence (inst_base, *qualifiers_list);
4780
4781 /* Print instruction. */
4782 print_operands (buf, opcode, inst_base->operands);
4783
4784 output_info (_(" %s"), buf);
4785 }
4786 }
4787 }
4788 break;
4789
0c608d6b 4790 case AARCH64_OPDE_UNTIED_OPERAND:
7d02540a
TC
4791 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4792 detail->index + 1, str);
0c608d6b
RS
4793 break;
4794
a06ea964 4795 case AARCH64_OPDE_OUT_OF_RANGE:
f5555712 4796 if (detail->data[0] != detail->data[1])
7d02540a
TC
4797 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4798 detail->error ? detail->error : _("immediate value"),
4799 detail->data[0], detail->data[1], idx + 1, str);
f5555712 4800 else
7d02540a
TC
4801 handler (_("%s must be %d at operand %d -- `%s'"),
4802 detail->error ? detail->error : _("immediate value"),
4803 detail->data[0], idx + 1, str);
a06ea964
NC
4804 break;
4805
4806 case AARCH64_OPDE_REG_LIST:
4807 if (detail->data[0] == 1)
7d02540a
TC
4808 handler (_("invalid number of registers in the list; "
4809 "only 1 register is expected at operand %d -- `%s'"),
4810 idx + 1, str);
a06ea964 4811 else
7d02540a
TC
4812 handler (_("invalid number of registers in the list; "
4813 "%d registers are expected at operand %d -- `%s'"),
4814 detail->data[0], idx + 1, str);
a06ea964
NC
4815 break;
4816
4817 case AARCH64_OPDE_UNALIGNED:
7d02540a
TC
4818 handler (_("immediate value must be a multiple of "
4819 "%d at operand %d -- `%s'"),
4820 detail->data[0], idx + 1, str);
a06ea964
NC
4821 break;
4822
4823 default:
4824 gas_assert (0);
4825 break;
4826 }
4827}
4828
4829/* Process and output the error message about the operand mismatching.
4830
4831 When this function is called, the operand error information had
4832 been collected for an assembly line and there will be multiple
33eaf5de 4833 errors in the case of multiple instruction templates; output the
7d02540a
TC
4834 error message that most closely describes the problem.
4835
4836 The errors to be printed can be filtered on printing all errors
4837 or only non-fatal errors. This distinction has to be made because
4838 the error buffer may already be filled with fatal errors we don't want to
4839 print due to the different instruction templates. */
a06ea964
NC
4840
4841static void
7d02540a 4842output_operand_error_report (char *str, bfd_boolean non_fatal_only)
a06ea964
NC
4843{
4844 int largest_error_pos;
4845 const char *msg = NULL;
4846 enum aarch64_operand_error_kind kind;
4847 operand_error_record *curr;
4848 operand_error_record *head = operand_error_report.head;
4849 operand_error_record *record = NULL;
4850
4851 /* No error to report. */
4852 if (head == NULL)
4853 return;
4854
4855 gas_assert (head != NULL && operand_error_report.tail != NULL);
4856
4857 /* Only one error. */
4858 if (head == operand_error_report.tail)
4859 {
7d02540a
TC
4860 /* If the only error is a non-fatal one and we don't want to print it,
4861 just exit. */
4862 if (!non_fatal_only || head->detail.non_fatal)
4863 {
4864 DEBUG_TRACE ("single opcode entry with error kind: %s",
4865 operand_mismatch_kind_names[head->detail.kind]);
4866 output_operand_error_record (head, str);
4867 }
a06ea964
NC
4868 return;
4869 }
4870
4871 /* Find the error kind of the highest severity. */
33eaf5de 4872 DEBUG_TRACE ("multiple opcode entries with error kind");
a06ea964
NC
4873 kind = AARCH64_OPDE_NIL;
4874 for (curr = head; curr != NULL; curr = curr->next)
4875 {
4876 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4877 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
a68f4cd2
TC
4878 if (operand_error_higher_severity_p (curr->detail.kind, kind)
4879 && (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
a06ea964
NC
4880 kind = curr->detail.kind;
4881 }
a68f4cd2
TC
4882
4883 gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
a06ea964
NC
4884
4885 /* Pick up one of errors of KIND to report. */
4886 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4887 for (curr = head; curr != NULL; curr = curr->next)
4888 {
7d02540a
TC
4889 /* If we don't want to print non-fatal errors then don't consider them
4890 at all. */
4891 if (curr->detail.kind != kind
af81c43b 4892 || (non_fatal_only && !curr->detail.non_fatal))
a06ea964
NC
4893 continue;
4894 /* If there are multiple errors, pick up the one with the highest
4895 mismatching operand index. In the case of multiple errors with
4896 the equally highest operand index, pick up the first one or the
4897 first one with non-NULL error message. */
4898 if (curr->detail.index > largest_error_pos
4899 || (curr->detail.index == largest_error_pos && msg == NULL
4900 && curr->detail.error != NULL))
4901 {
4902 largest_error_pos = curr->detail.index;
4903 record = curr;
4904 msg = record->detail.error;
4905 }
4906 }
4907
7d02540a
TC
4908 /* The way errors are collected in the back-end is a bit non-intuitive. But
4909 essentially, because each operand template is tried recursively you may
4910 always have errors collected from the previous tried OPND. These are
4911 usually skipped if there is one successful match. However now with the
4912 non-fatal errors we have to ignore those previously collected hard errors
4913 when we're only interested in printing the non-fatal ones. This condition
4914 prevents us from printing errors that are not appropriate, since we did
4915 match a condition, but it also has warnings that it wants to print. */
4916 if (non_fatal_only && !record)
4917 return;
4918
a06ea964
NC
4919 gas_assert (largest_error_pos != -2 && record != NULL);
4920 DEBUG_TRACE ("Pick up error kind %s to report",
4921 operand_mismatch_kind_names[record->detail.kind]);
4922
4923 /* Output. */
4924 output_operand_error_record (record, str);
4925}
4926\f
4927/* Write an AARCH64 instruction to buf - always little-endian. */
4928static void
4929put_aarch64_insn (char *buf, uint32_t insn)
4930{
4931 unsigned char *where = (unsigned char *) buf;
4932 where[0] = insn;
4933 where[1] = insn >> 8;
4934 where[2] = insn >> 16;
4935 where[3] = insn >> 24;
4936}
4937
4938static uint32_t
4939get_aarch64_insn (char *buf)
4940{
4941 unsigned char *where = (unsigned char *) buf;
4942 uint32_t result;
4943 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4944 return result;
4945}
4946
4947static void
4948output_inst (struct aarch64_inst *new_inst)
4949{
4950 char *to = NULL;
4951
4952 to = frag_more (INSN_SIZE);
4953
4954 frag_now->tc_frag_data.recorded = 1;
4955
4956 put_aarch64_insn (to, inst.base.value);
4957
4958 if (inst.reloc.type != BFD_RELOC_UNUSED)
4959 {
4960 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4961 INSN_SIZE, &inst.reloc.exp,
4962 inst.reloc.pc_rel,
4963 inst.reloc.type);
4964 DEBUG_TRACE ("Prepared relocation fix up");
4965 /* Don't check the addend value against the instruction size,
4966 that's the job of our code in md_apply_fix(). */
4967 fixp->fx_no_overflow = 1;
4968 if (new_inst != NULL)
4969 fixp->tc_fix_data.inst = new_inst;
4970 if (aarch64_gas_internal_fixup_p ())
4971 {
4972 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4973 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4974 fixp->fx_addnumber = inst.reloc.flags;
4975 }
4976 }
4977
4978 dwarf2_emit_insn (INSN_SIZE);
4979}
4980
4981/* Link together opcodes of the same name. */
4982
4983struct templates
4984{
4985 aarch64_opcode *opcode;
4986 struct templates *next;
4987};
4988
4989typedef struct templates templates;
4990
4991static templates *
4992lookup_mnemonic (const char *start, int len)
4993{
4994 templates *templ = NULL;
4995
4996 templ = hash_find_n (aarch64_ops_hsh, start, len);
4997 return templ;
4998}
4999
5000/* Subroutine of md_assemble, responsible for looking up the primary
5001 opcode from the mnemonic the user wrote. STR points to the
5002 beginning of the mnemonic. */
5003
5004static templates *
5005opcode_lookup (char **str)
5006{
bb7eff52 5007 char *end, *base, *dot;
a06ea964
NC
5008 const aarch64_cond *cond;
5009 char condname[16];
5010 int len;
5011
5012 /* Scan up to the end of the mnemonic, which must end in white space,
5013 '.', or end of string. */
bb7eff52 5014 dot = 0;
a06ea964 5015 for (base = end = *str; is_part_of_name(*end); end++)
bb7eff52
RS
5016 if (*end == '.' && !dot)
5017 dot = end;
a06ea964 5018
bb7eff52 5019 if (end == base || dot == base)
a06ea964
NC
5020 return 0;
5021
5022 inst.cond = COND_ALWAYS;
5023
5024 /* Handle a possible condition. */
bb7eff52 5025 if (dot)
a06ea964 5026 {
bb7eff52 5027 cond = hash_find_n (aarch64_cond_hsh, dot + 1, end - dot - 1);
a06ea964
NC
5028 if (cond)
5029 {
5030 inst.cond = cond->value;
bb7eff52 5031 *str = end;
a06ea964
NC
5032 }
5033 else
5034 {
bb7eff52 5035 *str = dot;
a06ea964
NC
5036 return 0;
5037 }
bb7eff52 5038 len = dot - base;
a06ea964
NC
5039 }
5040 else
bb7eff52
RS
5041 {
5042 *str = end;
5043 len = end - base;
5044 }
a06ea964
NC
5045
5046 if (inst.cond == COND_ALWAYS)
5047 {
5048 /* Look for unaffixed mnemonic. */
5049 return lookup_mnemonic (base, len);
5050 }
5051 else if (len <= 13)
5052 {
5053 /* append ".c" to mnemonic if conditional */
5054 memcpy (condname, base, len);
5055 memcpy (condname + len, ".c", 2);
5056 base = condname;
5057 len += 2;
5058 return lookup_mnemonic (base, len);
5059 }
5060
5061 return NULL;
5062}
5063
8f9a77af
RS
5064/* Internal helper routine converting a vector_type_el structure *VECTYPE
5065 to a corresponding operand qualifier. */
a06ea964
NC
5066
5067static inline aarch64_opnd_qualifier_t
8f9a77af 5068vectype_to_qualifier (const struct vector_type_el *vectype)
a06ea964 5069{
f06935a5 5070 /* Element size in bytes indexed by vector_el_type. */
a06ea964
NC
5071 const unsigned char ele_size[5]
5072 = {1, 2, 4, 8, 16};
65f2205d
MW
5073 const unsigned int ele_base [5] =
5074 {
a3b3345a 5075 AARCH64_OPND_QLF_V_4B,
3067d3b9 5076 AARCH64_OPND_QLF_V_2H,
65f2205d
MW
5077 AARCH64_OPND_QLF_V_2S,
5078 AARCH64_OPND_QLF_V_1D,
5079 AARCH64_OPND_QLF_V_1Q
5080 };
a06ea964
NC
5081
5082 if (!vectype->defined || vectype->type == NT_invtype)
5083 goto vectype_conversion_fail;
5084
d50c751e
RS
5085 if (vectype->type == NT_zero)
5086 return AARCH64_OPND_QLF_P_Z;
5087 if (vectype->type == NT_merge)
5088 return AARCH64_OPND_QLF_P_M;
5089
a06ea964
NC
5090 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
5091
f11ad6bc 5092 if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
00c2093f
TC
5093 {
5094 /* Special case S_4B. */
5095 if (vectype->type == NT_b && vectype->width == 4)
5096 return AARCH64_OPND_QLF_S_4B;
5097
5098 /* Vector element register. */
5099 return AARCH64_OPND_QLF_S_B + vectype->type;
5100 }
a06ea964
NC
5101 else
5102 {
5103 /* Vector register. */
5104 int reg_size = ele_size[vectype->type] * vectype->width;
5105 unsigned offset;
65f2205d 5106 unsigned shift;
3067d3b9 5107 if (reg_size != 16 && reg_size != 8 && reg_size != 4)
a06ea964 5108 goto vectype_conversion_fail;
65f2205d
MW
5109
5110 /* The conversion is by calculating the offset from the base operand
5111 qualifier for the vector type. The operand qualifiers are regular
5112 enough that the offset can established by shifting the vector width by
5113 a vector-type dependent amount. */
5114 shift = 0;
5115 if (vectype->type == NT_b)
a3b3345a 5116 shift = 3;
3067d3b9 5117 else if (vectype->type == NT_h || vectype->type == NT_s)
65f2205d
MW
5118 shift = 2;
5119 else if (vectype->type >= NT_d)
5120 shift = 1;
5121 else
5122 gas_assert (0);
5123
5124 offset = ele_base [vectype->type] + (vectype->width >> shift);
a3b3345a 5125 gas_assert (AARCH64_OPND_QLF_V_4B <= offset
65f2205d
MW
5126 && offset <= AARCH64_OPND_QLF_V_1Q);
5127 return offset;
a06ea964
NC
5128 }
5129
5130vectype_conversion_fail:
5131 first_error (_("bad vector arrangement type"));
5132 return AARCH64_OPND_QLF_NIL;
5133}
5134
5135/* Process an optional operand that is found omitted from the assembly line.
5136 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5137 instruction's opcode entry while IDX is the index of this omitted operand.
5138 */
5139
5140static void
5141process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
5142 int idx, aarch64_opnd_info *operand)
5143{
5144 aarch64_insn default_value = get_optional_operand_default_value (opcode);
5145 gas_assert (optional_operand_p (opcode, idx));
5146 gas_assert (!operand->present);
5147
5148 switch (type)
5149 {
5150 case AARCH64_OPND_Rd:
5151 case AARCH64_OPND_Rn:
5152 case AARCH64_OPND_Rm:
5153 case AARCH64_OPND_Rt:
5154 case AARCH64_OPND_Rt2:
bd7ceb8d 5155 case AARCH64_OPND_Rt_SP:
a06ea964
NC
5156 case AARCH64_OPND_Rs:
5157 case AARCH64_OPND_Ra:
5158 case AARCH64_OPND_Rt_SYS:
5159 case AARCH64_OPND_Rd_SP:
5160 case AARCH64_OPND_Rn_SP:
c84364ec 5161 case AARCH64_OPND_Rm_SP:
a06ea964
NC
5162 case AARCH64_OPND_Fd:
5163 case AARCH64_OPND_Fn:
5164 case AARCH64_OPND_Fm:
5165 case AARCH64_OPND_Fa:
5166 case AARCH64_OPND_Ft:
5167 case AARCH64_OPND_Ft2:
5168 case AARCH64_OPND_Sd:
5169 case AARCH64_OPND_Sn:
5170 case AARCH64_OPND_Sm:
f42f1a1d 5171 case AARCH64_OPND_Va:
a06ea964
NC
5172 case AARCH64_OPND_Vd:
5173 case AARCH64_OPND_Vn:
5174 case AARCH64_OPND_Vm:
5175 case AARCH64_OPND_VdD1:
5176 case AARCH64_OPND_VnD1:
5177 operand->reg.regno = default_value;
5178 break;
5179
5180 case AARCH64_OPND_Ed:
5181 case AARCH64_OPND_En:
5182 case AARCH64_OPND_Em:
369c9167 5183 case AARCH64_OPND_Em16:
f42f1a1d 5184 case AARCH64_OPND_SM3_IMM2:
a06ea964
NC
5185 operand->reglane.regno = default_value;
5186 break;
5187
5188 case AARCH64_OPND_IDX:
5189 case AARCH64_OPND_BIT_NUM:
5190 case AARCH64_OPND_IMMR:
5191 case AARCH64_OPND_IMMS:
5192 case AARCH64_OPND_SHLL_IMM:
5193 case AARCH64_OPND_IMM_VLSL:
5194 case AARCH64_OPND_IMM_VLSR:
5195 case AARCH64_OPND_CCMP_IMM:
5196 case AARCH64_OPND_FBITS:
5197 case AARCH64_OPND_UIMM4:
5198 case AARCH64_OPND_UIMM3_OP1:
5199 case AARCH64_OPND_UIMM3_OP2:
5200 case AARCH64_OPND_IMM:
f42f1a1d 5201 case AARCH64_OPND_IMM_2:
a06ea964
NC
5202 case AARCH64_OPND_WIDTH:
5203 case AARCH64_OPND_UIMM7:
5204 case AARCH64_OPND_NZCV:
245d2e3f
RS
5205 case AARCH64_OPND_SVE_PATTERN:
5206 case AARCH64_OPND_SVE_PRFOP:
a06ea964
NC
5207 operand->imm.value = default_value;
5208 break;
5209
2442d846
RS
5210 case AARCH64_OPND_SVE_PATTERN_SCALED:
5211 operand->imm.value = default_value;
5212 operand->shifter.kind = AARCH64_MOD_MUL;
5213 operand->shifter.amount = 1;
5214 break;
5215
a06ea964
NC
5216 case AARCH64_OPND_EXCEPTION:
5217 inst.reloc.type = BFD_RELOC_UNUSED;
5218 break;
5219
5220 case AARCH64_OPND_BARRIER_ISB:
5221 operand->barrier = aarch64_barrier_options + default_value;
ff605452
SD
5222 break;
5223
5224 case AARCH64_OPND_BTI_TARGET:
5225 operand->hint_option = aarch64_hint_options + default_value;
5226 break;
a06ea964
NC
5227
5228 default:
5229 break;
5230 }
5231}
5232
5233/* Process the relocation type for move wide instructions.
5234 Return TRUE on success; otherwise return FALSE. */
5235
5236static bfd_boolean
5237process_movw_reloc_info (void)
5238{
5239 int is32;
5240 unsigned shift;
5241
5242 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
5243
5244 if (inst.base.opcode->op == OP_MOVK)
5245 switch (inst.reloc.type)
5246 {
5247 case BFD_RELOC_AARCH64_MOVW_G0_S:
5248 case BFD_RELOC_AARCH64_MOVW_G1_S:
5249 case BFD_RELOC_AARCH64_MOVW_G2_S:
32247401
RL
5250 case BFD_RELOC_AARCH64_MOVW_PREL_G0:
5251 case BFD_RELOC_AARCH64_MOVW_PREL_G1:
5252 case BFD_RELOC_AARCH64_MOVW_PREL_G2:
5253 case BFD_RELOC_AARCH64_MOVW_PREL_G3:
1aa66fb1 5254 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
a06ea964 5255 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
a06ea964 5256 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
a06ea964
NC
5257 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
5258 set_syntax_error
5259 (_("the specified relocation type is not allowed for MOVK"));
5260 return FALSE;
5261 default:
5262 break;
5263 }
5264
5265 switch (inst.reloc.type)
5266 {
5267 case BFD_RELOC_AARCH64_MOVW_G0:
a06ea964 5268 case BFD_RELOC_AARCH64_MOVW_G0_NC:
f09c556a 5269 case BFD_RELOC_AARCH64_MOVW_G0_S:
ca632371 5270 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
32247401
RL
5271 case BFD_RELOC_AARCH64_MOVW_PREL_G0:
5272 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
43a357f9 5273 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
3e8286c0 5274 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
3b957e5b 5275 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
49df5539
JW
5276 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
5277 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
a06ea964
NC
5278 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
5279 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
5280 shift = 0;
5281 break;
5282 case BFD_RELOC_AARCH64_MOVW_G1:
a06ea964 5283 case BFD_RELOC_AARCH64_MOVW_G1_NC:
f09c556a 5284 case BFD_RELOC_AARCH64_MOVW_G1_S:
654248e7 5285 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
32247401
RL
5286 case BFD_RELOC_AARCH64_MOVW_PREL_G1:
5287 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
43a357f9 5288 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
1aa66fb1 5289 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
3b957e5b 5290 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
49df5539
JW
5291 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
5292 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
a06ea964
NC
5293 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
5294 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
5295 shift = 16;
5296 break;
5297 case BFD_RELOC_AARCH64_MOVW_G2:
a06ea964 5298 case BFD_RELOC_AARCH64_MOVW_G2_NC:
f09c556a 5299 case BFD_RELOC_AARCH64_MOVW_G2_S:
32247401
RL
5300 case BFD_RELOC_AARCH64_MOVW_PREL_G2:
5301 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
49df5539 5302 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
a06ea964
NC
5303 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
5304 if (is32)
5305 {
5306 set_fatal_syntax_error
5307 (_("the specified relocation type is not allowed for 32-bit "
5308 "register"));
5309 return FALSE;
5310 }
5311 shift = 32;
5312 break;
5313 case BFD_RELOC_AARCH64_MOVW_G3:
32247401 5314 case BFD_RELOC_AARCH64_MOVW_PREL_G3:
a06ea964
NC
5315 if (is32)
5316 {
5317 set_fatal_syntax_error
5318 (_("the specified relocation type is not allowed for 32-bit "
5319 "register"));
5320 return FALSE;
5321 }
5322 shift = 48;
5323 break;
5324 default:
5325 /* More cases should be added when more MOVW-related relocation types
5326 are supported in GAS. */
5327 gas_assert (aarch64_gas_internal_fixup_p ());
5328 /* The shift amount should have already been set by the parser. */
5329 return TRUE;
5330 }
5331 inst.base.operands[1].shifter.amount = shift;
5332 return TRUE;
5333}
5334
33eaf5de 5335/* A primitive log calculator. */
a06ea964
NC
5336
5337static inline unsigned int
5338get_logsz (unsigned int size)
5339{
5340 const unsigned char ls[16] =
5341 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5342 if (size > 16)
5343 {
5344 gas_assert (0);
5345 return -1;
5346 }
5347 gas_assert (ls[size - 1] != (unsigned char)-1);
5348 return ls[size - 1];
5349}
5350
5351/* Determine and return the real reloc type code for an instruction
5352 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5353
5354static inline bfd_reloc_code_real_type
5355ldst_lo12_determine_real_reloc_type (void)
5356{
4c562523 5357 unsigned logsz;
a06ea964
NC
5358 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
5359 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
5360
84f1b9fb 5361 const bfd_reloc_code_real_type reloc_ldst_lo12[5][5] = {
4c562523
JW
5362 {
5363 BFD_RELOC_AARCH64_LDST8_LO12,
5364 BFD_RELOC_AARCH64_LDST16_LO12,
5365 BFD_RELOC_AARCH64_LDST32_LO12,
5366 BFD_RELOC_AARCH64_LDST64_LO12,
a06ea964 5367 BFD_RELOC_AARCH64_LDST128_LO12
4c562523
JW
5368 },
5369 {
5370 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
5371 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
5372 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
5373 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
5374 BFD_RELOC_AARCH64_NONE
5375 },
5376 {
5377 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
5378 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
5379 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
5380 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
5381 BFD_RELOC_AARCH64_NONE
84f1b9fb
RL
5382 },
5383 {
5384 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12,
5385 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12,
5386 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12,
5387 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12,
5388 BFD_RELOC_AARCH64_NONE
5389 },
5390 {
5391 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC,
5392 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC,
5393 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC,
5394 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC,
5395 BFD_RELOC_AARCH64_NONE
4c562523 5396 }
a06ea964
NC
5397 };
5398
4c562523
JW
5399 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
5400 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5401 || (inst.reloc.type
84f1b9fb
RL
5402 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
5403 || (inst.reloc.type
5404 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12)
5405 || (inst.reloc.type
5406 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC));
a06ea964
NC
5407 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
5408
5409 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
5410 opd1_qlf =
5411 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
5412 1, opd0_qlf, 0);
5413 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
5414
5415 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4c562523 5416 if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
84f1b9fb
RL
5417 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5418 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5419 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)
4c562523
JW
5420 gas_assert (logsz <= 3);
5421 else
5422 gas_assert (logsz <= 4);
a06ea964 5423
4c562523 5424 /* In reloc.c, these pseudo relocation types should be defined in similar
33eaf5de 5425 order as above reloc_ldst_lo12 array. Because the array index calculation
4c562523
JW
5426 below relies on this. */
5427 return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
a06ea964
NC
5428}
5429
5430/* Check whether a register list REGINFO is valid. The registers must be
5431 numbered in increasing order (modulo 32), in increments of one or two.
5432
5433 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5434 increments of two.
5435
5436 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5437
5438static bfd_boolean
5439reg_list_valid_p (uint32_t reginfo, int accept_alternate)
5440{
5441 uint32_t i, nb_regs, prev_regno, incr;
5442
5443 nb_regs = 1 + (reginfo & 0x3);
5444 reginfo >>= 2;
5445 prev_regno = reginfo & 0x1f;
5446 incr = accept_alternate ? 2 : 1;
5447
5448 for (i = 1; i < nb_regs; ++i)
5449 {
5450 uint32_t curr_regno;
5451 reginfo >>= 5;
5452 curr_regno = reginfo & 0x1f;
5453 if (curr_regno != ((prev_regno + incr) & 0x1f))
5454 return FALSE;
5455 prev_regno = curr_regno;
5456 }
5457
5458 return TRUE;
5459}
5460
5461/* Generic instruction operand parser. This does no encoding and no
5462 semantic validation; it merely squirrels values away in the inst
5463 structure. Returns TRUE or FALSE depending on whether the
5464 specified grammar matched. */
5465
5466static bfd_boolean
5467parse_operands (char *str, const aarch64_opcode *opcode)
5468{
5469 int i;
5470 char *backtrack_pos = 0;
5471 const enum aarch64_opnd *operands = opcode->operands;
1799c0d0 5472 aarch64_reg_type imm_reg_type;
a06ea964
NC
5473
5474 clear_error ();
5475 skip_whitespace (str);
5476
c0890d26 5477 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant))
5b2b928e 5478 imm_reg_type = REG_TYPE_R_Z_SP_BHSDQ_VZP;
c0890d26
RS
5479 else
5480 imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
1799c0d0 5481
a06ea964
NC
5482 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
5483 {
5484 int64_t val;
e1b988bb 5485 const reg_entry *reg;
a06ea964
NC
5486 int comma_skipped_p = 0;
5487 aarch64_reg_type rtype;
8f9a77af 5488 struct vector_type_el vectype;
4df068de 5489 aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier;
a06ea964 5490 aarch64_opnd_info *info = &inst.base.operands[i];
f11ad6bc 5491 aarch64_reg_type reg_type;
a06ea964
NC
5492
5493 DEBUG_TRACE ("parse operand %d", i);
5494
5495 /* Assign the operand code. */
5496 info->type = operands[i];
5497
5498 if (optional_operand_p (opcode, i))
5499 {
5500 /* Remember where we are in case we need to backtrack. */
5501 gas_assert (!backtrack_pos);
5502 backtrack_pos = str;
5503 }
5504
33eaf5de 5505 /* Expect comma between operands; the backtrack mechanism will take
a06ea964
NC
5506 care of cases of omitted optional operand. */
5507 if (i > 0 && ! skip_past_char (&str, ','))
5508 {
5509 set_syntax_error (_("comma expected between operands"));
5510 goto failure;
5511 }
5512 else
5513 comma_skipped_p = 1;
5514
5515 switch (operands[i])
5516 {
5517 case AARCH64_OPND_Rd:
5518 case AARCH64_OPND_Rn:
5519 case AARCH64_OPND_Rm:
5520 case AARCH64_OPND_Rt:
5521 case AARCH64_OPND_Rt2:
5522 case AARCH64_OPND_Rs:
5523 case AARCH64_OPND_Ra:
5524 case AARCH64_OPND_Rt_SYS:
ee804238 5525 case AARCH64_OPND_PAIRREG:
047cd301 5526 case AARCH64_OPND_SVE_Rm:
e1b988bb 5527 po_int_reg_or_fail (REG_TYPE_R_Z);
a06ea964
NC
5528 break;
5529
5530 case AARCH64_OPND_Rd_SP:
5531 case AARCH64_OPND_Rn_SP:
bd7ceb8d 5532 case AARCH64_OPND_Rt_SP:
047cd301 5533 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 5534 case AARCH64_OPND_Rm_SP:
e1b988bb 5535 po_int_reg_or_fail (REG_TYPE_R_SP);
a06ea964
NC
5536 break;
5537
5538 case AARCH64_OPND_Rm_EXT:
5539 case AARCH64_OPND_Rm_SFT:
5540 po_misc_or_fail (parse_shifter_operand
5541 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
5542 ? SHIFTED_ARITH_IMM
5543 : SHIFTED_LOGIC_IMM)));
5544 if (!info->shifter.operator_present)
5545 {
5546 /* Default to LSL if not present. Libopcodes prefers shifter
5547 kind to be explicit. */
5548 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5549 info->shifter.kind = AARCH64_MOD_LSL;
5550 /* For Rm_EXT, libopcodes will carry out further check on whether
5551 or not stack pointer is used in the instruction (Recall that
5552 "the extend operator is not optional unless at least one of
5553 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5554 }
5555 break;
5556
5557 case AARCH64_OPND_Fd:
5558 case AARCH64_OPND_Fn:
5559 case AARCH64_OPND_Fm:
5560 case AARCH64_OPND_Fa:
5561 case AARCH64_OPND_Ft:
5562 case AARCH64_OPND_Ft2:
5563 case AARCH64_OPND_Sd:
5564 case AARCH64_OPND_Sn:
5565 case AARCH64_OPND_Sm:
047cd301
RS
5566 case AARCH64_OPND_SVE_VZn:
5567 case AARCH64_OPND_SVE_Vd:
5568 case AARCH64_OPND_SVE_Vm:
5569 case AARCH64_OPND_SVE_Vn:
a06ea964
NC
5570 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
5571 if (val == PARSE_FAIL)
5572 {
5573 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
5574 goto failure;
5575 }
5576 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
5577
5578 info->reg.regno = val;
5579 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
5580 break;
5581
f11ad6bc
RS
5582 case AARCH64_OPND_SVE_Pd:
5583 case AARCH64_OPND_SVE_Pg3:
5584 case AARCH64_OPND_SVE_Pg4_5:
5585 case AARCH64_OPND_SVE_Pg4_10:
5586 case AARCH64_OPND_SVE_Pg4_16:
5587 case AARCH64_OPND_SVE_Pm:
5588 case AARCH64_OPND_SVE_Pn:
5589 case AARCH64_OPND_SVE_Pt:
5590 reg_type = REG_TYPE_PN;
5591 goto vector_reg;
5592
5593 case AARCH64_OPND_SVE_Za_5:
5594 case AARCH64_OPND_SVE_Za_16:
5595 case AARCH64_OPND_SVE_Zd:
5596 case AARCH64_OPND_SVE_Zm_5:
5597 case AARCH64_OPND_SVE_Zm_16:
5598 case AARCH64_OPND_SVE_Zn:
5599 case AARCH64_OPND_SVE_Zt:
5600 reg_type = REG_TYPE_ZN;
5601 goto vector_reg;
5602
f42f1a1d 5603 case AARCH64_OPND_Va:
a06ea964
NC
5604 case AARCH64_OPND_Vd:
5605 case AARCH64_OPND_Vn:
5606 case AARCH64_OPND_Vm:
f11ad6bc
RS
5607 reg_type = REG_TYPE_VN;
5608 vector_reg:
5609 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
a06ea964
NC
5610 if (val == PARSE_FAIL)
5611 {
f11ad6bc 5612 first_error (_(get_reg_expected_msg (reg_type)));
a06ea964
NC
5613 goto failure;
5614 }
5615 if (vectype.defined & NTA_HASINDEX)
5616 goto failure;
5617
5618 info->reg.regno = val;
f11ad6bc
RS
5619 if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN)
5620 && vectype.type == NT_invtype)
5621 /* Unqualified Pn and Zn registers are allowed in certain
5622 contexts. Rely on F_STRICT qualifier checking to catch
5623 invalid uses. */
5624 info->qualifier = AARCH64_OPND_QLF_NIL;
5625 else
5626 {
5627 info->qualifier = vectype_to_qualifier (&vectype);
5628 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5629 goto failure;
5630 }
a06ea964
NC
5631 break;
5632
5633 case AARCH64_OPND_VdD1:
5634 case AARCH64_OPND_VnD1:
5635 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5636 if (val == PARSE_FAIL)
5637 {
5638 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5639 goto failure;
5640 }
5641 if (vectype.type != NT_d || vectype.index != 1)
5642 {
5643 set_fatal_syntax_error
5644 (_("the top half of a 128-bit FP/SIMD register is expected"));
5645 goto failure;
5646 }
5647 info->reg.regno = val;
5648 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5649 here; it is correct for the purpose of encoding/decoding since
5650 only the register number is explicitly encoded in the related
5651 instructions, although this appears a bit hacky. */
5652 info->qualifier = AARCH64_OPND_QLF_S_D;
5653 break;
5654
582e12bf
RS
5655 case AARCH64_OPND_SVE_Zm3_INDEX:
5656 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 5657 case AARCH64_OPND_SVE_Zm3_11_INDEX:
582e12bf 5658 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS
5659 case AARCH64_OPND_SVE_Zn_INDEX:
5660 reg_type = REG_TYPE_ZN;
5661 goto vector_reg_index;
5662
a06ea964
NC
5663 case AARCH64_OPND_Ed:
5664 case AARCH64_OPND_En:
5665 case AARCH64_OPND_Em:
369c9167 5666 case AARCH64_OPND_Em16:
f42f1a1d 5667 case AARCH64_OPND_SM3_IMM2:
f11ad6bc
RS
5668 reg_type = REG_TYPE_VN;
5669 vector_reg_index:
5670 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
a06ea964
NC
5671 if (val == PARSE_FAIL)
5672 {
f11ad6bc 5673 first_error (_(get_reg_expected_msg (reg_type)));
a06ea964
NC
5674 goto failure;
5675 }
5676 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
5677 goto failure;
5678
5679 info->reglane.regno = val;
5680 info->reglane.index = vectype.index;
5681 info->qualifier = vectype_to_qualifier (&vectype);
5682 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5683 goto failure;
5684 break;
5685
f11ad6bc
RS
5686 case AARCH64_OPND_SVE_ZnxN:
5687 case AARCH64_OPND_SVE_ZtxN:
5688 reg_type = REG_TYPE_ZN;
5689 goto vector_reg_list;
5690
a06ea964
NC
5691 case AARCH64_OPND_LVn:
5692 case AARCH64_OPND_LVt:
5693 case AARCH64_OPND_LVt_AL:
5694 case AARCH64_OPND_LEt:
f11ad6bc
RS
5695 reg_type = REG_TYPE_VN;
5696 vector_reg_list:
5697 if (reg_type == REG_TYPE_ZN
5698 && get_opcode_dependent_value (opcode) == 1
5699 && *str != '{')
a06ea964 5700 {
f11ad6bc
RS
5701 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5702 if (val == PARSE_FAIL)
5703 {
5704 first_error (_(get_reg_expected_msg (reg_type)));
5705 goto failure;
5706 }
5707 info->reglist.first_regno = val;
5708 info->reglist.num_regs = 1;
5709 }
5710 else
5711 {
5712 val = parse_vector_reg_list (&str, reg_type, &vectype);
5713 if (val == PARSE_FAIL)
5714 goto failure;
5715 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
5716 {
5717 set_fatal_syntax_error (_("invalid register list"));
5718 goto failure;
5719 }
5720 info->reglist.first_regno = (val >> 2) & 0x1f;
5721 info->reglist.num_regs = (val & 0x3) + 1;
a06ea964 5722 }
a06ea964
NC
5723 if (operands[i] == AARCH64_OPND_LEt)
5724 {
5725 if (!(vectype.defined & NTA_HASINDEX))
5726 goto failure;
5727 info->reglist.has_index = 1;
5728 info->reglist.index = vectype.index;
5729 }
f11ad6bc
RS
5730 else
5731 {
5732 if (vectype.defined & NTA_HASINDEX)
5733 goto failure;
5734 if (!(vectype.defined & NTA_HASTYPE))
5735 {
5736 if (reg_type == REG_TYPE_ZN)
5737 set_fatal_syntax_error (_("missing type suffix"));
5738 goto failure;
5739 }
5740 }
a06ea964
NC
5741 info->qualifier = vectype_to_qualifier (&vectype);
5742 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5743 goto failure;
5744 break;
5745
a6a51754
RL
5746 case AARCH64_OPND_CRn:
5747 case AARCH64_OPND_CRm:
a06ea964 5748 {
a6a51754
RL
5749 char prefix = *(str++);
5750 if (prefix != 'c' && prefix != 'C')
5751 goto failure;
5752
5753 po_imm_nc_or_fail ();
5754 if (val > 15)
5755 {
5756 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5757 goto failure;
5758 }
5759 info->qualifier = AARCH64_OPND_QLF_CR;
5760 info->imm.value = val;
5761 break;
a06ea964 5762 }
a06ea964
NC
5763
5764 case AARCH64_OPND_SHLL_IMM:
5765 case AARCH64_OPND_IMM_VLSR:
5766 po_imm_or_fail (1, 64);
5767 info->imm.value = val;
5768 break;
5769
5770 case AARCH64_OPND_CCMP_IMM:
e950b345 5771 case AARCH64_OPND_SIMM5:
a06ea964 5772 case AARCH64_OPND_FBITS:
b83b4b13 5773 case AARCH64_OPND_TME_UIMM16:
a06ea964 5774 case AARCH64_OPND_UIMM4:
193614f2
SD
5775 case AARCH64_OPND_UIMM4_ADDG:
5776 case AARCH64_OPND_UIMM10:
a06ea964
NC
5777 case AARCH64_OPND_UIMM3_OP1:
5778 case AARCH64_OPND_UIMM3_OP2:
5779 case AARCH64_OPND_IMM_VLSL:
5780 case AARCH64_OPND_IMM:
f42f1a1d 5781 case AARCH64_OPND_IMM_2:
a06ea964 5782 case AARCH64_OPND_WIDTH:
e950b345
RS
5783 case AARCH64_OPND_SVE_INV_LIMM:
5784 case AARCH64_OPND_SVE_LIMM:
5785 case AARCH64_OPND_SVE_LIMM_MOV:
5786 case AARCH64_OPND_SVE_SHLIMM_PRED:
5787 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
5788 case AARCH64_OPND_SVE_SHRIMM_PRED:
5789 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
5790 case AARCH64_OPND_SVE_SIMM5:
5791 case AARCH64_OPND_SVE_SIMM5B:
5792 case AARCH64_OPND_SVE_SIMM6:
5793 case AARCH64_OPND_SVE_SIMM8:
5794 case AARCH64_OPND_SVE_UIMM3:
5795 case AARCH64_OPND_SVE_UIMM7:
5796 case AARCH64_OPND_SVE_UIMM8:
5797 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN
5798 case AARCH64_OPND_IMM_ROT1:
5799 case AARCH64_OPND_IMM_ROT2:
5800 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS
5801 case AARCH64_OPND_SVE_IMM_ROT1:
5802 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 5803 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC
5804 po_imm_nc_or_fail ();
5805 info->imm.value = val;
5806 break;
5807
e950b345
RS
5808 case AARCH64_OPND_SVE_AIMM:
5809 case AARCH64_OPND_SVE_ASIMM:
5810 po_imm_nc_or_fail ();
5811 info->imm.value = val;
5812 skip_whitespace (str);
5813 if (skip_past_comma (&str))
5814 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
5815 else
5816 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
5817 break;
5818
245d2e3f
RS
5819 case AARCH64_OPND_SVE_PATTERN:
5820 po_enum_or_fail (aarch64_sve_pattern_array);
5821 info->imm.value = val;
5822 break;
5823
2442d846
RS
5824 case AARCH64_OPND_SVE_PATTERN_SCALED:
5825 po_enum_or_fail (aarch64_sve_pattern_array);
5826 info->imm.value = val;
5827 if (skip_past_comma (&str)
5828 && !parse_shift (&str, info, SHIFTED_MUL))
5829 goto failure;
5830 if (!info->shifter.operator_present)
5831 {
5832 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5833 info->shifter.kind = AARCH64_MOD_MUL;
5834 info->shifter.amount = 1;
5835 }
5836 break;
5837
245d2e3f
RS
5838 case AARCH64_OPND_SVE_PRFOP:
5839 po_enum_or_fail (aarch64_sve_prfop_array);
5840 info->imm.value = val;
5841 break;
5842
a06ea964
NC
5843 case AARCH64_OPND_UIMM7:
5844 po_imm_or_fail (0, 127);
5845 info->imm.value = val;
5846 break;
5847
5848 case AARCH64_OPND_IDX:
f42f1a1d 5849 case AARCH64_OPND_MASK:
a06ea964
NC
5850 case AARCH64_OPND_BIT_NUM:
5851 case AARCH64_OPND_IMMR:
5852 case AARCH64_OPND_IMMS:
5853 po_imm_or_fail (0, 63);
5854 info->imm.value = val;
5855 break;
5856
5857 case AARCH64_OPND_IMM0:
5858 po_imm_nc_or_fail ();
5859 if (val != 0)
5860 {
5861 set_fatal_syntax_error (_("immediate zero expected"));
5862 goto failure;
5863 }
5864 info->imm.value = 0;
5865 break;
5866
5867 case AARCH64_OPND_FPIMM0:
5868 {
5869 int qfloat;
5870 bfd_boolean res1 = FALSE, res2 = FALSE;
5871 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5872 it is probably not worth the effort to support it. */
1799c0d0
RS
5873 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE,
5874 imm_reg_type))
6a9deabe
RS
5875 && (error_p ()
5876 || !(res2 = parse_constant_immediate (&str, &val,
5877 imm_reg_type))))
a06ea964
NC
5878 goto failure;
5879 if ((res1 && qfloat == 0) || (res2 && val == 0))
5880 {
5881 info->imm.value = 0;
5882 info->imm.is_fp = 1;
5883 break;
5884 }
5885 set_fatal_syntax_error (_("immediate zero expected"));
5886 goto failure;
5887 }
5888
5889 case AARCH64_OPND_IMM_MOV:
5890 {
5891 char *saved = str;
8db49cc2
WN
5892 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
5893 reg_name_p (str, REG_TYPE_VN))
a06ea964
NC
5894 goto failure;
5895 str = saved;
5896 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5897 GE_OPT_PREFIX, 1));
5898 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5899 later. fix_mov_imm_insn will try to determine a machine
5900 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5901 message if the immediate cannot be moved by a single
5902 instruction. */
5903 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5904 inst.base.operands[i].skip = 1;
5905 }
5906 break;
5907
5908 case AARCH64_OPND_SIMD_IMM:
5909 case AARCH64_OPND_SIMD_IMM_SFT:
1799c0d0 5910 if (! parse_big_immediate (&str, &val, imm_reg_type))
a06ea964
NC
5911 goto failure;
5912 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5913 /* addr_off_p */ 0,
5914 /* need_libopcodes_p */ 1,
5915 /* skip_p */ 1);
5916 /* Parse shift.
5917 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5918 shift, we don't check it here; we leave the checking to
5919 the libopcodes (operand_general_constraint_met_p). By
5920 doing this, we achieve better diagnostics. */
5921 if (skip_past_comma (&str)
5922 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
5923 goto failure;
5924 if (!info->shifter.operator_present
5925 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
5926 {
5927 /* Default to LSL if not present. Libopcodes prefers shifter
5928 kind to be explicit. */
5929 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5930 info->shifter.kind = AARCH64_MOD_LSL;
5931 }
5932 break;
5933
5934 case AARCH64_OPND_FPIMM:
5935 case AARCH64_OPND_SIMD_FPIMM:
165d4950 5936 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC
5937 {
5938 int qfloat;
165d4950
RS
5939 bfd_boolean dp_p;
5940
5941 dp_p = double_precision_operand_p (&inst.base.operands[0]);
6a9deabe 5942 if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)
874d7e6e 5943 || !aarch64_imm_float_p (qfloat))
a06ea964 5944 {
6a9deabe
RS
5945 if (!error_p ())
5946 set_fatal_syntax_error (_("invalid floating-point"
5947 " constant"));
a06ea964
NC
5948 goto failure;
5949 }
5950 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
5951 inst.base.operands[i].imm.is_fp = 1;
5952 }
5953 break;
5954
165d4950
RS
5955 case AARCH64_OPND_SVE_I1_HALF_ONE:
5956 case AARCH64_OPND_SVE_I1_HALF_TWO:
5957 case AARCH64_OPND_SVE_I1_ZERO_ONE:
5958 {
5959 int qfloat;
5960 bfd_boolean dp_p;
5961
5962 dp_p = double_precision_operand_p (&inst.base.operands[0]);
5963 if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type))
5964 {
5965 if (!error_p ())
5966 set_fatal_syntax_error (_("invalid floating-point"
5967 " constant"));
5968 goto failure;
5969 }
5970 inst.base.operands[i].imm.value = qfloat;
5971 inst.base.operands[i].imm.is_fp = 1;
5972 }
5973 break;
5974
a06ea964
NC
5975 case AARCH64_OPND_LIMM:
5976 po_misc_or_fail (parse_shifter_operand (&str, info,
5977 SHIFTED_LOGIC_IMM));
5978 if (info->shifter.operator_present)
5979 {
5980 set_fatal_syntax_error
5981 (_("shift not allowed for bitmask immediate"));
5982 goto failure;
5983 }
5984 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5985 /* addr_off_p */ 0,
5986 /* need_libopcodes_p */ 1,
5987 /* skip_p */ 1);
5988 break;
5989
5990 case AARCH64_OPND_AIMM:
5991 if (opcode->op == OP_ADD)
5992 /* ADD may have relocation types. */
5993 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
5994 SHIFTED_ARITH_IMM));
5995 else
5996 po_misc_or_fail (parse_shifter_operand (&str, info,
5997 SHIFTED_ARITH_IMM));
5998 switch (inst.reloc.type)
5999 {
6000 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6001 info->shifter.amount = 12;
6002 break;
6003 case BFD_RELOC_UNUSED:
6004 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
6005 if (info->shifter.kind != AARCH64_MOD_NONE)
6006 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
6007 inst.reloc.pc_rel = 0;
6008 break;
6009 default:
6010 break;
6011 }
6012 info->imm.value = 0;
6013 if (!info->shifter.operator_present)
6014 {
6015 /* Default to LSL if not present. Libopcodes prefers shifter
6016 kind to be explicit. */
6017 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
6018 info->shifter.kind = AARCH64_MOD_LSL;
6019 }
6020 break;
6021
6022 case AARCH64_OPND_HALF:
6023 {
6024 /* #<imm16> or relocation. */
6025 int internal_fixup_p;
6026 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
6027 if (internal_fixup_p)
6028 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
6029 skip_whitespace (str);
6030 if (skip_past_comma (&str))
6031 {
6032 /* {, LSL #<shift>} */
6033 if (! aarch64_gas_internal_fixup_p ())
6034 {
6035 set_fatal_syntax_error (_("can't mix relocation modifier "
6036 "with explicit shift"));
6037 goto failure;
6038 }
6039 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
6040 }
6041 else
6042 inst.base.operands[i].shifter.amount = 0;
6043 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
6044 inst.base.operands[i].imm.value = 0;
6045 if (! process_movw_reloc_info ())
6046 goto failure;
6047 }
6048 break;
6049
6050 case AARCH64_OPND_EXCEPTION:
1799c0d0
RS
6051 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp,
6052 imm_reg_type));
a06ea964
NC
6053 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
6054 /* addr_off_p */ 0,
6055 /* need_libopcodes_p */ 0,
6056 /* skip_p */ 1);
6057 break;
6058
6059 case AARCH64_OPND_NZCV:
6060 {
6061 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
6062 if (nzcv != NULL)
6063 {
6064 str += 4;
6065 info->imm.value = nzcv->value;
6066 break;
6067 }
6068 po_imm_or_fail (0, 15);
6069 info->imm.value = val;
6070 }
6071 break;
6072
6073 case AARCH64_OPND_COND:
68a64283 6074 case AARCH64_OPND_COND1:
bb7eff52
RS
6075 {
6076 char *start = str;
6077 do
6078 str++;
6079 while (ISALPHA (*str));
6080 info->cond = hash_find_n (aarch64_cond_hsh, start, str - start);
6081 if (info->cond == NULL)
6082 {
6083 set_syntax_error (_("invalid condition"));
6084 goto failure;
6085 }
6086 else if (operands[i] == AARCH64_OPND_COND1
6087 && (info->cond->value & 0xe) == 0xe)
6088 {
6089 /* Do not allow AL or NV. */
6090 set_default_error ();
6091 goto failure;
6092 }
6093 }
a06ea964
NC
6094 break;
6095
6096 case AARCH64_OPND_ADDR_ADRP:
6097 po_misc_or_fail (parse_adrp (&str));
6098 /* Clear the value as operand needs to be relocated. */
6099 info->imm.value = 0;
6100 break;
6101
6102 case AARCH64_OPND_ADDR_PCREL14:
6103 case AARCH64_OPND_ADDR_PCREL19:
6104 case AARCH64_OPND_ADDR_PCREL21:
6105 case AARCH64_OPND_ADDR_PCREL26:
73866052 6106 po_misc_or_fail (parse_address (&str, info));
a06ea964
NC
6107 if (!info->addr.pcrel)
6108 {
6109 set_syntax_error (_("invalid pc-relative address"));
6110 goto failure;
6111 }
6112 if (inst.gen_lit_pool
6113 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
6114 {
6115 /* Only permit "=value" in the literal load instructions.
6116 The literal will be generated by programmer_friendly_fixup. */
6117 set_syntax_error (_("invalid use of \"=immediate\""));
6118 goto failure;
6119 }
6120 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
6121 {
6122 set_syntax_error (_("unrecognized relocation suffix"));
6123 goto failure;
6124 }
6125 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
6126 {
6127 info->imm.value = inst.reloc.exp.X_add_number;
6128 inst.reloc.type = BFD_RELOC_UNUSED;
6129 }
6130 else
6131 {
6132 info->imm.value = 0;
f41aef5f
RE
6133 if (inst.reloc.type == BFD_RELOC_UNUSED)
6134 switch (opcode->iclass)
6135 {
6136 case compbranch:
6137 case condbranch:
6138 /* e.g. CBZ or B.COND */
6139 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
6140 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
6141 break;
6142 case testbranch:
6143 /* e.g. TBZ */
6144 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
6145 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
6146 break;
6147 case branch_imm:
6148 /* e.g. B or BL */
6149 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
6150 inst.reloc.type =
6151 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
6152 : BFD_RELOC_AARCH64_JUMP26;
6153 break;
6154 case loadlit:
6155 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
6156 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
6157 break;
6158 case pcreladdr:
6159 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
6160 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
6161 break;
6162 default:
6163 gas_assert (0);
6164 abort ();
6165 }
a06ea964
NC
6166 inst.reloc.pc_rel = 1;
6167 }
6168 break;
6169
6170 case AARCH64_OPND_ADDR_SIMPLE:
6171 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
e1b988bb
RS
6172 {
6173 /* [<Xn|SP>{, #<simm>}] */
6174 char *start = str;
6175 /* First use the normal address-parsing routines, to get
6176 the usual syntax errors. */
73866052 6177 po_misc_or_fail (parse_address (&str, info));
e1b988bb
RS
6178 if (info->addr.pcrel || info->addr.offset.is_reg
6179 || !info->addr.preind || info->addr.postind
550fd7bf 6180 || info->addr.writeback)
e1b988bb
RS
6181 {
6182 set_syntax_error (_("invalid addressing mode"));
6183 goto failure;
6184 }
6185
6186 /* Then retry, matching the specific syntax of these addresses. */
6187 str = start;
6188 po_char_or_fail ('[');
6189 po_reg_or_fail (REG_TYPE_R64_SP);
6190 /* Accept optional ", #0". */
6191 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
6192 && skip_past_char (&str, ','))
6193 {
6194 skip_past_char (&str, '#');
6195 if (! skip_past_char (&str, '0'))
6196 {
6197 set_fatal_syntax_error
6198 (_("the optional immediate offset can only be 0"));
6199 goto failure;
6200 }
6201 }
6202 po_char_or_fail (']');
6203 break;
6204 }
a06ea964
NC
6205
6206 case AARCH64_OPND_ADDR_REGOFF:
6207 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
73866052 6208 po_misc_or_fail (parse_address (&str, info));
4df068de 6209 regoff_addr:
a06ea964
NC
6210 if (info->addr.pcrel || !info->addr.offset.is_reg
6211 || !info->addr.preind || info->addr.postind
6212 || info->addr.writeback)
6213 {
6214 set_syntax_error (_("invalid addressing mode"));
6215 goto failure;
6216 }
6217 if (!info->shifter.operator_present)
6218 {
6219 /* Default to LSL if not present. Libopcodes prefers shifter
6220 kind to be explicit. */
6221 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
6222 info->shifter.kind = AARCH64_MOD_LSL;
6223 }
6224 /* Qualifier to be deduced by libopcodes. */
6225 break;
6226
6227 case AARCH64_OPND_ADDR_SIMM7:
73866052 6228 po_misc_or_fail (parse_address (&str, info));
a06ea964
NC
6229 if (info->addr.pcrel || info->addr.offset.is_reg
6230 || (!info->addr.preind && !info->addr.postind))
6231 {
6232 set_syntax_error (_("invalid addressing mode"));
6233 goto failure;
6234 }
73866052
RS
6235 if (inst.reloc.type != BFD_RELOC_UNUSED)
6236 {
6237 set_syntax_error (_("relocation not allowed"));
6238 goto failure;
6239 }
a06ea964
NC
6240 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
6241 /* addr_off_p */ 1,
6242 /* need_libopcodes_p */ 1,
6243 /* skip_p */ 0);
6244 break;
6245
6246 case AARCH64_OPND_ADDR_SIMM9:
6247 case AARCH64_OPND_ADDR_SIMM9_2:
fb3265b3
SD
6248 case AARCH64_OPND_ADDR_SIMM11:
6249 case AARCH64_OPND_ADDR_SIMM13:
73866052 6250 po_misc_or_fail (parse_address (&str, info));
a06ea964
NC
6251 if (info->addr.pcrel || info->addr.offset.is_reg
6252 || (!info->addr.preind && !info->addr.postind)
6253 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
6254 && info->addr.writeback))
6255 {
6256 set_syntax_error (_("invalid addressing mode"));
6257 goto failure;
6258 }
6259 if (inst.reloc.type != BFD_RELOC_UNUSED)
6260 {
6261 set_syntax_error (_("relocation not allowed"));
6262 goto failure;
6263 }
6264 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
6265 /* addr_off_p */ 1,
6266 /* need_libopcodes_p */ 1,
6267 /* skip_p */ 0);
6268 break;
6269
3f06e550 6270 case AARCH64_OPND_ADDR_SIMM10:
f42f1a1d 6271 case AARCH64_OPND_ADDR_OFFSET:
3f06e550
SN
6272 po_misc_or_fail (parse_address (&str, info));
6273 if (info->addr.pcrel || info->addr.offset.is_reg
6274 || !info->addr.preind || info->addr.postind)
6275 {
6276 set_syntax_error (_("invalid addressing mode"));
6277 goto failure;
6278 }
6279 if (inst.reloc.type != BFD_RELOC_UNUSED)
6280 {
6281 set_syntax_error (_("relocation not allowed"));
6282 goto failure;
6283 }
6284 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
6285 /* addr_off_p */ 1,
6286 /* need_libopcodes_p */ 1,
6287 /* skip_p */ 0);
6288 break;
6289
a06ea964 6290 case AARCH64_OPND_ADDR_UIMM12:
73866052 6291 po_misc_or_fail (parse_address (&str, info));
a06ea964
NC
6292 if (info->addr.pcrel || info->addr.offset.is_reg
6293 || !info->addr.preind || info->addr.writeback)
6294 {
6295 set_syntax_error (_("invalid addressing mode"));
6296 goto failure;
6297 }
6298 if (inst.reloc.type == BFD_RELOC_UNUSED)
6299 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
4c562523
JW
6300 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
6301 || (inst.reloc.type
6302 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
6303 || (inst.reloc.type
84f1b9fb
RL
6304 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
6305 || (inst.reloc.type
6306 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12)
6307 || (inst.reloc.type
6308 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC))
a06ea964
NC
6309 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
6310 /* Leave qualifier to be determined by libopcodes. */
6311 break;
6312
6313 case AARCH64_OPND_SIMD_ADDR_POST:
6314 /* [<Xn|SP>], <Xm|#<amount>> */
73866052 6315 po_misc_or_fail (parse_address (&str, info));
a06ea964
NC
6316 if (!info->addr.postind || !info->addr.writeback)
6317 {
6318 set_syntax_error (_("invalid addressing mode"));
6319 goto failure;
6320 }
6321 if (!info->addr.offset.is_reg)
6322 {
6323 if (inst.reloc.exp.X_op == O_constant)
6324 info->addr.offset.imm = inst.reloc.exp.X_add_number;
6325 else
6326 {
6327 set_fatal_syntax_error
ab3b8fcf 6328 (_("writeback value must be an immediate constant"));
a06ea964
NC
6329 goto failure;
6330 }
6331 }
6332 /* No qualifier. */
6333 break;
6334
582e12bf 6335 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
98907a70
RS
6336 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
6337 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
6338 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
6339 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
6340 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
6341 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS
6342 case AARCH64_OPND_SVE_ADDR_RI_U6:
6343 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
6344 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
6345 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
98907a70
RS
6346 /* [X<n>{, #imm, MUL VL}]
6347 [X<n>{, #imm}]
4df068de
RS
6348 but recognizing SVE registers. */
6349 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6350 &offset_qualifier));
6351 if (base_qualifier != AARCH64_OPND_QLF_X)
6352 {
6353 set_syntax_error (_("invalid addressing mode"));
6354 goto failure;
6355 }
6356 sve_regimm:
6357 if (info->addr.pcrel || info->addr.offset.is_reg
6358 || !info->addr.preind || info->addr.writeback)
6359 {
6360 set_syntax_error (_("invalid addressing mode"));
6361 goto failure;
6362 }
6363 if (inst.reloc.type != BFD_RELOC_UNUSED
6364 || inst.reloc.exp.X_op != O_constant)
6365 {
6366 /* Make sure this has priority over
6367 "invalid addressing mode". */
6368 set_fatal_syntax_error (_("constant offset required"));
6369 goto failure;
6370 }
6371 info->addr.offset.imm = inst.reloc.exp.X_add_number;
6372 break;
6373
c8d59609
NC
6374 case AARCH64_OPND_SVE_ADDR_R:
6375 /* [<Xn|SP>{, <R><m>}]
6376 but recognizing SVE registers. */
6377 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6378 &offset_qualifier));
6379 if (offset_qualifier == AARCH64_OPND_QLF_NIL)
6380 {
6381 offset_qualifier = AARCH64_OPND_QLF_X;
6382 info->addr.offset.is_reg = 1;
6383 info->addr.offset.regno = 31;
6384 }
6385 else if (base_qualifier != AARCH64_OPND_QLF_X
6386 || offset_qualifier != AARCH64_OPND_QLF_X)
6387 {
6388 set_syntax_error (_("invalid addressing mode"));
6389 goto failure;
6390 }
6391 goto regoff_addr;
6392
4df068de
RS
6393 case AARCH64_OPND_SVE_ADDR_RR:
6394 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
6395 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
6396 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
6397 case AARCH64_OPND_SVE_ADDR_RX:
6398 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
6399 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
6400 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
6401 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6402 but recognizing SVE registers. */
6403 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6404 &offset_qualifier));
6405 if (base_qualifier != AARCH64_OPND_QLF_X
6406 || offset_qualifier != AARCH64_OPND_QLF_X)
6407 {
6408 set_syntax_error (_("invalid addressing mode"));
6409 goto failure;
6410 }
6411 goto regoff_addr;
6412
6413 case AARCH64_OPND_SVE_ADDR_RZ:
6414 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
6415 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
6416 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
6417 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
6418 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
6419 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
6420 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
6421 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
6422 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
6423 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
6424 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
6425 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6426 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6427 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6428 &offset_qualifier));
6429 if (base_qualifier != AARCH64_OPND_QLF_X
6430 || (offset_qualifier != AARCH64_OPND_QLF_S_S
6431 && offset_qualifier != AARCH64_OPND_QLF_S_D))
6432 {
6433 set_syntax_error (_("invalid addressing mode"));
6434 goto failure;
6435 }
6436 info->qualifier = offset_qualifier;
6437 goto regoff_addr;
6438
c469c864
MM
6439 case AARCH64_OPND_SVE_ADDR_ZX:
6440 /* [Zn.<T>{, <Xm>}]. */
6441 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6442 &offset_qualifier));
6443 /* Things to check:
6444 base_qualifier either S_S or S_D
6445 offset_qualifier must be X
6446 */
6447 if ((base_qualifier != AARCH64_OPND_QLF_S_S
6448 && base_qualifier != AARCH64_OPND_QLF_S_D)
6449 || offset_qualifier != AARCH64_OPND_QLF_X)
6450 {
6451 set_syntax_error (_("invalid addressing mode"));
6452 goto failure;
6453 }
6454 info->qualifier = base_qualifier;
6455 if (!info->addr.offset.is_reg || info->addr.pcrel
6456 || !info->addr.preind || info->addr.writeback
6457 || info->shifter.operator_present != 0)
6458 {
6459 set_syntax_error (_("invalid addressing mode"));
6460 goto failure;
6461 }
6462 info->shifter.kind = AARCH64_MOD_LSL;
6463 break;
6464
6465
4df068de
RS
6466 case AARCH64_OPND_SVE_ADDR_ZI_U5:
6467 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
6468 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
6469 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
6470 /* [Z<n>.<T>{, #imm}] */
6471 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6472 &offset_qualifier));
6473 if (base_qualifier != AARCH64_OPND_QLF_S_S
6474 && base_qualifier != AARCH64_OPND_QLF_S_D)
6475 {
6476 set_syntax_error (_("invalid addressing mode"));
6477 goto failure;
6478 }
6479 info->qualifier = base_qualifier;
6480 goto sve_regimm;
6481
6482 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
6483 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
6484 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
6485 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6486 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6487
6488 We don't reject:
6489
6490 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6491
6492 here since we get better error messages by leaving it to
6493 the qualifier checking routines. */
6494 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6495 &offset_qualifier));
6496 if ((base_qualifier != AARCH64_OPND_QLF_S_S
6497 && base_qualifier != AARCH64_OPND_QLF_S_D)
6498 || offset_qualifier != base_qualifier)
6499 {
6500 set_syntax_error (_("invalid addressing mode"));
6501 goto failure;
6502 }
6503 info->qualifier = base_qualifier;
6504 goto regoff_addr;
6505
a06ea964 6506 case AARCH64_OPND_SYSREG:
7d02540a
TC
6507 {
6508 uint32_t sysreg_flags;
6509 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0,
6510 &sysreg_flags)) == PARSE_FAIL)
6511 {
6512 set_syntax_error (_("unknown or missing system register name"));
6513 goto failure;
6514 }
6515 inst.base.operands[i].sysreg.value = val;
6516 inst.base.operands[i].sysreg.flags = sysreg_flags;
6517 break;
6518 }
a06ea964
NC
6519
6520 case AARCH64_OPND_PSTATEFIELD:
561a72d4 6521 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL))
a3251895 6522 == PARSE_FAIL)
a06ea964
NC
6523 {
6524 set_syntax_error (_("unknown or missing PSTATE field name"));
6525 goto failure;
6526 }
6527 inst.base.operands[i].pstatefield = val;
6528 break;
6529
6530 case AARCH64_OPND_SYSREG_IC:
6531 inst.base.operands[i].sysins_op =
6532 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
6533 goto sys_reg_ins;
2ac435d4 6534
a06ea964
NC
6535 case AARCH64_OPND_SYSREG_DC:
6536 inst.base.operands[i].sysins_op =
6537 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
6538 goto sys_reg_ins;
2ac435d4 6539
a06ea964
NC
6540 case AARCH64_OPND_SYSREG_AT:
6541 inst.base.operands[i].sysins_op =
6542 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
6543 goto sys_reg_ins;
2ac435d4
SD
6544
6545 case AARCH64_OPND_SYSREG_SR:
6546 inst.base.operands[i].sysins_op =
6547 parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
6548 goto sys_reg_ins;
6549
a06ea964
NC
6550 case AARCH64_OPND_SYSREG_TLBI:
6551 inst.base.operands[i].sysins_op =
6552 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
6553sys_reg_ins:
6554 if (inst.base.operands[i].sysins_op == NULL)
6555 {
6556 set_fatal_syntax_error ( _("unknown or missing operation name"));
6557 goto failure;
6558 }
6559 break;
6560
6561 case AARCH64_OPND_BARRIER:
6562 case AARCH64_OPND_BARRIER_ISB:
6563 val = parse_barrier (&str);
6564 if (val != PARSE_FAIL
6565 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
6566 {
6567 /* ISB only accepts options name 'sy'. */
6568 set_syntax_error
6569 (_("the specified option is not accepted in ISB"));
6570 /* Turn off backtrack as this optional operand is present. */
6571 backtrack_pos = 0;
6572 goto failure;
6573 }
6574 /* This is an extension to accept a 0..15 immediate. */
6575 if (val == PARSE_FAIL)
6576 po_imm_or_fail (0, 15);
6577 info->barrier = aarch64_barrier_options + val;
6578 break;
6579
6580 case AARCH64_OPND_PRFOP:
6581 val = parse_pldop (&str);
6582 /* This is an extension to accept a 0..31 immediate. */
6583 if (val == PARSE_FAIL)
6584 po_imm_or_fail (0, 31);
6585 inst.base.operands[i].prfop = aarch64_prfops + val;
6586 break;
6587
1e6f4800
MW
6588 case AARCH64_OPND_BARRIER_PSB:
6589 val = parse_barrier_psb (&str, &(info->hint_option));
6590 if (val == PARSE_FAIL)
6591 goto failure;
6592 break;
6593
ff605452
SD
6594 case AARCH64_OPND_BTI_TARGET:
6595 val = parse_bti_operand (&str, &(info->hint_option));
6596 if (val == PARSE_FAIL)
6597 goto failure;
6598 break;
6599
a06ea964
NC
6600 default:
6601 as_fatal (_("unhandled operand code %d"), operands[i]);
6602 }
6603
6604 /* If we get here, this operand was successfully parsed. */
6605 inst.base.operands[i].present = 1;
6606 continue;
6607
6608failure:
6609 /* The parse routine should already have set the error, but in case
6610 not, set a default one here. */
6611 if (! error_p ())
6612 set_default_error ();
6613
6614 if (! backtrack_pos)
6615 goto parse_operands_return;
6616
f4c51f60
JW
6617 {
6618 /* We reach here because this operand is marked as optional, and
6619 either no operand was supplied or the operand was supplied but it
6620 was syntactically incorrect. In the latter case we report an
6621 error. In the former case we perform a few more checks before
6622 dropping through to the code to insert the default operand. */
6623
6624 char *tmp = backtrack_pos;
6625 char endchar = END_OF_INSN;
6626
6627 if (i != (aarch64_num_of_operands (opcode) - 1))
6628 endchar = ',';
6629 skip_past_char (&tmp, ',');
6630
6631 if (*tmp != endchar)
6632 /* The user has supplied an operand in the wrong format. */
6633 goto parse_operands_return;
6634
6635 /* Make sure there is not a comma before the optional operand.
6636 For example the fifth operand of 'sys' is optional:
6637
6638 sys #0,c0,c0,#0, <--- wrong
6639 sys #0,c0,c0,#0 <--- correct. */
6640 if (comma_skipped_p && i && endchar == END_OF_INSN)
6641 {
6642 set_fatal_syntax_error
6643 (_("unexpected comma before the omitted optional operand"));
6644 goto parse_operands_return;
6645 }
6646 }
6647
a06ea964
NC
6648 /* Reaching here means we are dealing with an optional operand that is
6649 omitted from the assembly line. */
6650 gas_assert (optional_operand_p (opcode, i));
6651 info->present = 0;
6652 process_omitted_operand (operands[i], opcode, i, info);
6653
6654 /* Try again, skipping the optional operand at backtrack_pos. */
6655 str = backtrack_pos;
6656 backtrack_pos = 0;
6657
a06ea964
NC
6658 /* Clear any error record after the omitted optional operand has been
6659 successfully handled. */
6660 clear_error ();
6661 }
6662
6663 /* Check if we have parsed all the operands. */
6664 if (*str != '\0' && ! error_p ())
6665 {
6666 /* Set I to the index of the last present operand; this is
6667 for the purpose of diagnostics. */
6668 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
6669 ;
6670 set_fatal_syntax_error
6671 (_("unexpected characters following instruction"));
6672 }
6673
6674parse_operands_return:
6675
6676 if (error_p ())
6677 {
6678 DEBUG_TRACE ("parsing FAIL: %s - %s",
6679 operand_mismatch_kind_names[get_error_kind ()],
6680 get_error_message ());
6681 /* Record the operand error properly; this is useful when there
6682 are multiple instruction templates for a mnemonic name, so that
6683 later on, we can select the error that most closely describes
6684 the problem. */
6685 record_operand_error (opcode, i, get_error_kind (),
6686 get_error_message ());
6687 return FALSE;
6688 }
6689 else
6690 {
6691 DEBUG_TRACE ("parsing SUCCESS");
6692 return TRUE;
6693 }
6694}
6695
6696/* It does some fix-up to provide some programmer friendly feature while
6697 keeping the libopcodes happy, i.e. libopcodes only accepts
6698 the preferred architectural syntax.
6699 Return FALSE if there is any failure; otherwise return TRUE. */
6700
6701static bfd_boolean
6702programmer_friendly_fixup (aarch64_instruction *instr)
6703{
6704 aarch64_inst *base = &instr->base;
6705 const aarch64_opcode *opcode = base->opcode;
6706 enum aarch64_op op = opcode->op;
6707 aarch64_opnd_info *operands = base->operands;
6708
6709 DEBUG_TRACE ("enter");
6710
6711 switch (opcode->iclass)
6712 {
6713 case testbranch:
6714 /* TBNZ Xn|Wn, #uimm6, label
6715 Test and Branch Not Zero: conditionally jumps to label if bit number
6716 uimm6 in register Xn is not zero. The bit number implies the width of
6717 the register, which may be written and should be disassembled as Wn if
6718 uimm is less than 32. */
6719 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
6720 {
6721 if (operands[1].imm.value >= 32)
6722 {
6723 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
6724 0, 31);
6725 return FALSE;
6726 }
6727 operands[0].qualifier = AARCH64_OPND_QLF_X;
6728 }
6729 break;
6730 case loadlit:
6731 /* LDR Wt, label | =value
6732 As a convenience assemblers will typically permit the notation
6733 "=value" in conjunction with the pc-relative literal load instructions
6734 to automatically place an immediate value or symbolic address in a
6735 nearby literal pool and generate a hidden label which references it.
6736 ISREG has been set to 0 in the case of =value. */
6737 if (instr->gen_lit_pool
6738 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
6739 {
6740 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
6741 if (op == OP_LDRSW_LIT)
6742 size = 4;
6743 if (instr->reloc.exp.X_op != O_constant
67a32447 6744 && instr->reloc.exp.X_op != O_big
a06ea964
NC
6745 && instr->reloc.exp.X_op != O_symbol)
6746 {
6747 record_operand_error (opcode, 1,
6748 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
6749 _("constant expression expected"));
6750 return FALSE;
6751 }
6752 if (! add_to_lit_pool (&instr->reloc.exp, size))
6753 {
6754 record_operand_error (opcode, 1,
6755 AARCH64_OPDE_OTHER_ERROR,
6756 _("literal pool insertion failed"));
6757 return FALSE;
6758 }
6759 }
6760 break;
a06ea964
NC
6761 case log_shift:
6762 case bitfield:
6763 /* UXT[BHW] Wd, Wn
6764 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6765 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6766 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6767 A programmer-friendly assembler should accept a destination Xd in
6768 place of Wd, however that is not the preferred form for disassembly.
6769 */
6770 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
6771 && operands[1].qualifier == AARCH64_OPND_QLF_W
6772 && operands[0].qualifier == AARCH64_OPND_QLF_X)
6773 operands[0].qualifier = AARCH64_OPND_QLF_W;
6774 break;
6775
6776 case addsub_ext:
6777 {
6778 /* In the 64-bit form, the final register operand is written as Wm
6779 for all but the (possibly omitted) UXTX/LSL and SXTX
6780 operators.
6781 As a programmer-friendly assembler, we accept e.g.
6782 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6783 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6784 int idx = aarch64_operand_index (opcode->operands,
6785 AARCH64_OPND_Rm_EXT);
6786 gas_assert (idx == 1 || idx == 2);
6787 if (operands[0].qualifier == AARCH64_OPND_QLF_X
6788 && operands[idx].qualifier == AARCH64_OPND_QLF_X
6789 && operands[idx].shifter.kind != AARCH64_MOD_LSL
6790 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
6791 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
6792 operands[idx].qualifier = AARCH64_OPND_QLF_W;
6793 }
6794 break;
6795
6796 default:
6797 break;
6798 }
6799
6800 DEBUG_TRACE ("exit with SUCCESS");
6801 return TRUE;
6802}
6803
5c47e525 6804/* Check for loads and stores that will cause unpredictable behavior. */
54a28c4c
JW
6805
6806static void
6807warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
6808{
6809 aarch64_inst *base = &instr->base;
6810 const aarch64_opcode *opcode = base->opcode;
6811 const aarch64_opnd_info *opnds = base->operands;
6812 switch (opcode->iclass)
6813 {
6814 case ldst_pos:
6815 case ldst_imm9:
3f06e550 6816 case ldst_imm10:
54a28c4c
JW
6817 case ldst_unscaled:
6818 case ldst_unpriv:
5c47e525
RE
6819 /* Loading/storing the base register is unpredictable if writeback. */
6820 if ((aarch64_get_operand_class (opnds[0].type)
6821 == AARCH64_OPND_CLASS_INT_REG)
6822 && opnds[0].reg.regno == opnds[1].addr.base_regno
4bf8c6e8 6823 && opnds[1].addr.base_regno != REG_SP
69105ce4
SD
6824 /* Exempt STG/STZG/ST2G/STZ2G. */
6825 && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13)
54a28c4c 6826 && opnds[1].addr.writeback)
5c47e525 6827 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
54a28c4c 6828 break;
503ba600 6829
54a28c4c
JW
6830 case ldstpair_off:
6831 case ldstnapair_offs:
6832 case ldstpair_indexed:
5c47e525
RE
6833 /* Loading/storing the base register is unpredictable if writeback. */
6834 if ((aarch64_get_operand_class (opnds[0].type)
6835 == AARCH64_OPND_CLASS_INT_REG)
6836 && (opnds[0].reg.regno == opnds[2].addr.base_regno
6837 || opnds[1].reg.regno == opnds[2].addr.base_regno)
4bf8c6e8 6838 && opnds[2].addr.base_regno != REG_SP
fb3265b3
SD
6839 /* Exempt STGP. */
6840 && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)
54a28c4c 6841 && opnds[2].addr.writeback)
5c47e525
RE
6842 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
6843 /* Load operations must load different registers. */
54a28c4c
JW
6844 if ((opcode->opcode & (1 << 22))
6845 && opnds[0].reg.regno == opnds[1].reg.regno)
6846 as_warn (_("unpredictable load of register pair -- `%s'"), str);
6847 break;
ee943970
RR
6848
6849 case ldstexcl:
6850 /* It is unpredictable if the destination and status registers are the
6851 same. */
6852 if ((aarch64_get_operand_class (opnds[0].type)
6853 == AARCH64_OPND_CLASS_INT_REG)
6854 && (aarch64_get_operand_class (opnds[1].type)
6855 == AARCH64_OPND_CLASS_INT_REG)
6856 && (opnds[0].reg.regno == opnds[1].reg.regno
6857 || opnds[0].reg.regno == opnds[2].reg.regno))
6858 as_warn (_("unpredictable: identical transfer and status registers"
6859 " --`%s'"),
6860 str);
6861
6862 break;
6863
54a28c4c
JW
6864 default:
6865 break;
6866 }
6867}
6868
4f5d2536
TC
6869static void
6870force_automatic_sequence_close (void)
6871{
6872 if (now_instr_sequence.instr)
6873 {
6874 as_warn (_("previous `%s' sequence has not been closed"),
6875 now_instr_sequence.instr->opcode->name);
6876 init_insn_sequence (NULL, &now_instr_sequence);
6877 }
6878}
6879
a06ea964
NC
6880/* A wrapper function to interface with libopcodes on encoding and
6881 record the error message if there is any.
6882
6883 Return TRUE on success; otherwise return FALSE. */
6884
6885static bfd_boolean
6886do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
6887 aarch64_insn *code)
6888{
6889 aarch64_operand_error error_info;
7d02540a 6890 memset (&error_info, '\0', sizeof (error_info));
a06ea964 6891 error_info.kind = AARCH64_OPDE_NIL;
7e84b55d 6892 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info, insn_sequence)
7d02540a 6893 && !error_info.non_fatal)
a06ea964 6894 return TRUE;
7d02540a
TC
6895
6896 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
6897 record_operand_error_info (opcode, &error_info);
6898 return error_info.non_fatal;
a06ea964
NC
6899}
6900
6901#ifdef DEBUG_AARCH64
6902static inline void
6903dump_opcode_operands (const aarch64_opcode *opcode)
6904{
6905 int i = 0;
6906 while (opcode->operands[i] != AARCH64_OPND_NIL)
6907 {
6908 aarch64_verbose ("\t\t opnd%d: %s", i,
6909 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
6910 ? aarch64_get_operand_name (opcode->operands[i])
6911 : aarch64_get_operand_desc (opcode->operands[i]));
6912 ++i;
6913 }
6914}
6915#endif /* DEBUG_AARCH64 */
6916
6917/* This is the guts of the machine-dependent assembler. STR points to a
6918 machine dependent instruction. This function is supposed to emit
6919 the frags/bytes it assembles to. */
6920
6921void
6922md_assemble (char *str)
6923{
6924 char *p = str;
6925 templates *template;
6926 aarch64_opcode *opcode;
6927 aarch64_inst *inst_base;
6928 unsigned saved_cond;
6929
6930 /* Align the previous label if needed. */
6931 if (last_label_seen != NULL)
6932 {
6933 symbol_set_frag (last_label_seen, frag_now);
6934 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6935 S_SET_SEGMENT (last_label_seen, now_seg);
6936 }
6937
7e84b55d
TC
6938 /* Update the current insn_sequence from the segment. */
6939 insn_sequence = &seg_info (now_seg)->tc_segment_info_data.insn_sequence;
6940
a06ea964
NC
6941 inst.reloc.type = BFD_RELOC_UNUSED;
6942
6943 DEBUG_TRACE ("\n\n");
6944 DEBUG_TRACE ("==============================");
6945 DEBUG_TRACE ("Enter md_assemble with %s", str);
6946
6947 template = opcode_lookup (&p);
6948 if (!template)
6949 {
6950 /* It wasn't an instruction, but it might be a register alias of
6951 the form alias .req reg directive. */
6952 if (!create_register_alias (str, p))
6953 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
6954 str);
6955 return;
6956 }
6957
6958 skip_whitespace (p);
6959 if (*p == ',')
6960 {
6961 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6962 get_mnemonic_name (str), str);
6963 return;
6964 }
6965
6966 init_operand_error_report ();
6967
eb9d6cc9
RL
6968 /* Sections are assumed to start aligned. In executable section, there is no
6969 MAP_DATA symbol pending. So we only align the address during
6970 MAP_DATA --> MAP_INSN transition.
6971 For other sections, this is not guaranteed. */
6972 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
6973 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
6974 frag_align_code (2, 0);
6975
a06ea964
NC
6976 saved_cond = inst.cond;
6977 reset_aarch64_instruction (&inst);
6978 inst.cond = saved_cond;
6979
6980 /* Iterate through all opcode entries with the same mnemonic name. */
6981 do
6982 {
6983 opcode = template->opcode;
6984
6985 DEBUG_TRACE ("opcode %s found", opcode->name);
6986#ifdef DEBUG_AARCH64
6987 if (debug_dump)
6988 dump_opcode_operands (opcode);
6989#endif /* DEBUG_AARCH64 */
6990
a06ea964
NC
6991 mapping_state (MAP_INSN);
6992
6993 inst_base = &inst.base;
6994 inst_base->opcode = opcode;
6995
6996 /* Truly conditionally executed instructions, e.g. b.cond. */
6997 if (opcode->flags & F_COND)
6998 {
6999 gas_assert (inst.cond != COND_ALWAYS);
7000 inst_base->cond = get_cond_from_value (inst.cond);
7001 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
7002 }
7003 else if (inst.cond != COND_ALWAYS)
7004 {
7005 /* It shouldn't arrive here, where the assembly looks like a
7006 conditional instruction but the found opcode is unconditional. */
7007 gas_assert (0);
7008 continue;
7009 }
7010
7011 if (parse_operands (p, opcode)
7012 && programmer_friendly_fixup (&inst)
7013 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
7014 {
3f06bfce
YZ
7015 /* Check that this instruction is supported for this CPU. */
7016 if (!opcode->avariant
93d8990c 7017 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
3f06bfce
YZ
7018 {
7019 as_bad (_("selected processor does not support `%s'"), str);
7020 return;
7021 }
7022
54a28c4c
JW
7023 warn_unpredictable_ldst (&inst, str);
7024
a06ea964
NC
7025 if (inst.reloc.type == BFD_RELOC_UNUSED
7026 || !inst.reloc.need_libopcodes_p)
7027 output_inst (NULL);
7028 else
7029 {
7030 /* If there is relocation generated for the instruction,
7031 store the instruction information for the future fix-up. */
7032 struct aarch64_inst *copy;
7033 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
325801bd 7034 copy = XNEW (struct aarch64_inst);
a06ea964
NC
7035 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
7036 output_inst (copy);
7037 }
7d02540a
TC
7038
7039 /* Issue non-fatal messages if any. */
7040 output_operand_error_report (str, TRUE);
a06ea964
NC
7041 return;
7042 }
7043
7044 template = template->next;
7045 if (template != NULL)
7046 {
7047 reset_aarch64_instruction (&inst);
7048 inst.cond = saved_cond;
7049 }
7050 }
7051 while (template != NULL);
7052
7053 /* Issue the error messages if any. */
7d02540a 7054 output_operand_error_report (str, FALSE);
a06ea964
NC
7055}
7056
7057/* Various frobbings of labels and their addresses. */
7058
7059void
7060aarch64_start_line_hook (void)
7061{
7062 last_label_seen = NULL;
7063}
7064
7065void
7066aarch64_frob_label (symbolS * sym)
7067{
7068 last_label_seen = sym;
7069
7070 dwarf2_emit_label (sym);
7071}
7072
4f5d2536
TC
7073void
7074aarch64_frob_section (asection *sec ATTRIBUTE_UNUSED)
7075{
7076 /* Check to see if we have a block to close. */
7077 force_automatic_sequence_close ();
7078}
7079
a06ea964
NC
7080int
7081aarch64_data_in_code (void)
7082{
7083 if (!strncmp (input_line_pointer + 1, "data:", 5))
7084 {
7085 *input_line_pointer = '/';
7086 input_line_pointer += 5;
7087 *input_line_pointer = 0;
7088 return 1;
7089 }
7090
7091 return 0;
7092}
7093
7094char *
7095aarch64_canonicalize_symbol_name (char *name)
7096{
7097 int len;
7098
7099 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
7100 *(name + len - 5) = 0;
7101
7102 return name;
7103}
7104\f
7105/* Table of all register names defined by default. The user can
7106 define additional names with .req. Note that all register names
7107 should appear in both upper and lowercase variants. Some registers
7108 also have mixed-case names. */
7109
7110#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8975f864 7111#define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
a06ea964 7112#define REGNUM(p,n,t) REGDEF(p##n, n, t)
f11ad6bc 7113#define REGSET16(p,t) \
a06ea964
NC
7114 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7115 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7116 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
f11ad6bc
RS
7117 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7118#define REGSET31(p,t) \
7119 REGSET16(p, t), \
a06ea964
NC
7120 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7121 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7122 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7123 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7124#define REGSET(p,t) \
7125 REGSET31(p,t), REGNUM(p,31,t)
7126
7127/* These go into aarch64_reg_hsh hash-table. */
7128static const reg_entry reg_names[] = {
7129 /* Integer registers. */
7130 REGSET31 (x, R_64), REGSET31 (X, R_64),
7131 REGSET31 (w, R_32), REGSET31 (W, R_32),
7132
8975f864 7133 REGDEF_ALIAS (ip0, 16, R_64), REGDEF_ALIAS (IP0, 16, R_64),
f10e937a 7134 REGDEF_ALIAS (ip1, 17, R_64), REGDEF_ALIAS (IP1, 17, R_64),
8975f864
RR
7135 REGDEF_ALIAS (fp, 29, R_64), REGDEF_ALIAS (FP, 29, R_64),
7136 REGDEF_ALIAS (lr, 30, R_64), REGDEF_ALIAS (LR, 30, R_64),
a06ea964
NC
7137 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
7138 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
7139
7140 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
7141 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
7142
a06ea964
NC
7143 /* Floating-point single precision registers. */
7144 REGSET (s, FP_S), REGSET (S, FP_S),
7145
7146 /* Floating-point double precision registers. */
7147 REGSET (d, FP_D), REGSET (D, FP_D),
7148
7149 /* Floating-point half precision registers. */
7150 REGSET (h, FP_H), REGSET (H, FP_H),
7151
7152 /* Floating-point byte precision registers. */
7153 REGSET (b, FP_B), REGSET (B, FP_B),
7154
7155 /* Floating-point quad precision registers. */
7156 REGSET (q, FP_Q), REGSET (Q, FP_Q),
7157
7158 /* FP/SIMD registers. */
7159 REGSET (v, VN), REGSET (V, VN),
f11ad6bc
RS
7160
7161 /* SVE vector registers. */
7162 REGSET (z, ZN), REGSET (Z, ZN),
7163
7164 /* SVE predicate registers. */
7165 REGSET16 (p, PN), REGSET16 (P, PN)
a06ea964
NC
7166};
7167
7168#undef REGDEF
8975f864 7169#undef REGDEF_ALIAS
a06ea964 7170#undef REGNUM
f11ad6bc
RS
7171#undef REGSET16
7172#undef REGSET31
a06ea964
NC
7173#undef REGSET
7174
7175#define N 1
7176#define n 0
7177#define Z 1
7178#define z 0
7179#define C 1
7180#define c 0
7181#define V 1
7182#define v 0
7183#define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7184static const asm_nzcv nzcv_names[] = {
7185 {"nzcv", B (n, z, c, v)},
7186 {"nzcV", B (n, z, c, V)},
7187 {"nzCv", B (n, z, C, v)},
7188 {"nzCV", B (n, z, C, V)},
7189 {"nZcv", B (n, Z, c, v)},
7190 {"nZcV", B (n, Z, c, V)},
7191 {"nZCv", B (n, Z, C, v)},
7192 {"nZCV", B (n, Z, C, V)},
7193 {"Nzcv", B (N, z, c, v)},
7194 {"NzcV", B (N, z, c, V)},
7195 {"NzCv", B (N, z, C, v)},
7196 {"NzCV", B (N, z, C, V)},
7197 {"NZcv", B (N, Z, c, v)},
7198 {"NZcV", B (N, Z, c, V)},
7199 {"NZCv", B (N, Z, C, v)},
7200 {"NZCV", B (N, Z, C, V)}
7201};
7202
7203#undef N
7204#undef n
7205#undef Z
7206#undef z
7207#undef C
7208#undef c
7209#undef V
7210#undef v
7211#undef B
7212\f
7213/* MD interface: bits in the object file. */
7214
7215/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7216 for use in the a.out file, and stores them in the array pointed to by buf.
7217 This knows about the endian-ness of the target machine and does
7218 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7219 2 (short) and 4 (long) Floating numbers are put out as a series of
7220 LITTLENUMS (shorts, here at least). */
7221
7222void
7223md_number_to_chars (char *buf, valueT val, int n)
7224{
7225 if (target_big_endian)
7226 number_to_chars_bigendian (buf, val, n);
7227 else
7228 number_to_chars_littleendian (buf, val, n);
7229}
7230
7231/* MD interface: Sections. */
7232
7233/* Estimate the size of a frag before relaxing. Assume everything fits in
7234 4 bytes. */
7235
7236int
7237md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
7238{
7239 fragp->fr_var = 4;
7240 return 4;
7241}
7242
7243/* Round up a section size to the appropriate boundary. */
7244
7245valueT
7246md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7247{
7248 return size;
7249}
7250
7251/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
f803aa8e
DPT
7252 of an rs_align_code fragment.
7253
7254 Here we fill the frag with the appropriate info for padding the
7255 output stream. The resulting frag will consist of a fixed (fr_fix)
7256 and of a repeating (fr_var) part.
7257
7258 The fixed content is always emitted before the repeating content and
7259 these two parts are used as follows in constructing the output:
7260 - the fixed part will be used to align to a valid instruction word
7261 boundary, in case that we start at a misaligned address; as no
7262 executable instruction can live at the misaligned location, we
7263 simply fill with zeros;
7264 - the variable part will be used to cover the remaining padding and
7265 we fill using the AArch64 NOP instruction.
7266
7267 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7268 enough storage space for up to 3 bytes for padding the back to a valid
7269 instruction alignment and exactly 4 bytes to store the NOP pattern. */
a06ea964
NC
7270
7271void
7272aarch64_handle_align (fragS * fragP)
7273{
7274 /* NOP = d503201f */
7275 /* AArch64 instructions are always little-endian. */
d9235011 7276 static unsigned char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
a06ea964
NC
7277
7278 int bytes, fix, noop_size;
7279 char *p;
a06ea964
NC
7280
7281 if (fragP->fr_type != rs_align_code)
7282 return;
7283
7284 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
7285 p = fragP->fr_literal + fragP->fr_fix;
a06ea964
NC
7286
7287#ifdef OBJ_ELF
7288 gas_assert (fragP->tc_frag_data.recorded);
7289#endif
7290
a06ea964 7291 noop_size = sizeof (aarch64_noop);
a06ea964 7292
f803aa8e
DPT
7293 fix = bytes & (noop_size - 1);
7294 if (fix)
a06ea964 7295 {
a06ea964
NC
7296#ifdef OBJ_ELF
7297 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
7298#endif
7299 memset (p, 0, fix);
7300 p += fix;
f803aa8e 7301 fragP->fr_fix += fix;
a06ea964
NC
7302 }
7303
f803aa8e
DPT
7304 if (noop_size)
7305 memcpy (p, aarch64_noop, noop_size);
7306 fragP->fr_var = noop_size;
a06ea964
NC
7307}
7308
7309/* Perform target specific initialisation of a frag.
7310 Note - despite the name this initialisation is not done when the frag
7311 is created, but only when its type is assigned. A frag can be created
7312 and used a long time before its type is set, so beware of assuming that
33eaf5de 7313 this initialisation is performed first. */
a06ea964
NC
7314
7315#ifndef OBJ_ELF
7316void
7317aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
7318 int max_chars ATTRIBUTE_UNUSED)
7319{
7320}
7321
7322#else /* OBJ_ELF is defined. */
7323void
7324aarch64_init_frag (fragS * fragP, int max_chars)
7325{
7326 /* Record a mapping symbol for alignment frags. We will delete this
7327 later if the alignment ends up empty. */
7328 if (!fragP->tc_frag_data.recorded)
c7ad08e6
RL
7329 fragP->tc_frag_data.recorded = 1;
7330
e8d84ca1
NC
7331 /* PR 21809: Do not set a mapping state for debug sections
7332 - it just confuses other tools. */
7333 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
7334 return;
7335
c7ad08e6 7336 switch (fragP->fr_type)
a06ea964 7337 {
c7ad08e6
RL
7338 case rs_align_test:
7339 case rs_fill:
7340 mapping_state_2 (MAP_DATA, max_chars);
7341 break;
7ea12e5c
NC
7342 case rs_align:
7343 /* PR 20364: We can get alignment frags in code sections,
7344 so do not just assume that we should use the MAP_DATA state. */
7345 mapping_state_2 (subseg_text_p (now_seg) ? MAP_INSN : MAP_DATA, max_chars);
7346 break;
c7ad08e6
RL
7347 case rs_align_code:
7348 mapping_state_2 (MAP_INSN, max_chars);
7349 break;
7350 default:
7351 break;
a06ea964
NC
7352 }
7353}
7354\f
7355/* Initialize the DWARF-2 unwind information for this procedure. */
7356
7357void
7358tc_aarch64_frame_initial_instructions (void)
7359{
7360 cfi_add_CFA_def_cfa (REG_SP, 0);
7361}
7362#endif /* OBJ_ELF */
7363
7364/* Convert REGNAME to a DWARF-2 register number. */
7365
7366int
7367tc_aarch64_regname_to_dw2regnum (char *regname)
7368{
7369 const reg_entry *reg = parse_reg (&regname);
7370 if (reg == NULL)
7371 return -1;
7372
7373 switch (reg->type)
7374 {
7375 case REG_TYPE_SP_32:
7376 case REG_TYPE_SP_64:
7377 case REG_TYPE_R_32:
7378 case REG_TYPE_R_64:
a2cac51c
RH
7379 return reg->number;
7380
a06ea964
NC
7381 case REG_TYPE_FP_B:
7382 case REG_TYPE_FP_H:
7383 case REG_TYPE_FP_S:
7384 case REG_TYPE_FP_D:
7385 case REG_TYPE_FP_Q:
a2cac51c
RH
7386 return reg->number + 64;
7387
a06ea964
NC
7388 default:
7389 break;
7390 }
7391 return -1;
7392}
7393
cec5225b
YZ
7394/* Implement DWARF2_ADDR_SIZE. */
7395
7396int
7397aarch64_dwarf2_addr_size (void)
7398{
7399#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7400 if (ilp32_p)
7401 return 4;
7402#endif
7403 return bfd_arch_bits_per_address (stdoutput) / 8;
7404}
7405
a06ea964
NC
7406/* MD interface: Symbol and relocation handling. */
7407
7408/* Return the address within the segment that a PC-relative fixup is
7409 relative to. For AArch64 PC-relative fixups applied to instructions
7410 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7411
7412long
7413md_pcrel_from_section (fixS * fixP, segT seg)
7414{
7415 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
7416
7417 /* If this is pc-relative and we are going to emit a relocation
7418 then we just want to put out any pipeline compensation that the linker
7419 will need. Otherwise we want to use the calculated base. */
7420 if (fixP->fx_pcrel
7421 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
7422 || aarch64_force_relocation (fixP)))
7423 base = 0;
7424
7425 /* AArch64 should be consistent for all pc-relative relocations. */
7426 return base + AARCH64_PCREL_OFFSET;
7427}
7428
7429/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7430 Otherwise we have no need to default values of symbols. */
7431
7432symbolS *
7433md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7434{
7435#ifdef OBJ_ELF
7436 if (name[0] == '_' && name[1] == 'G'
7437 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
7438 {
7439 if (!GOT_symbol)
7440 {
7441 if (symbol_find (name))
7442 as_bad (_("GOT already in the symbol table"));
7443
7444 GOT_symbol = symbol_new (name, undefined_section,
7445 (valueT) 0, &zero_address_frag);
7446 }
7447
7448 return GOT_symbol;
7449 }
7450#endif
7451
7452 return 0;
7453}
7454
7455/* Return non-zero if the indicated VALUE has overflowed the maximum
7456 range expressible by a unsigned number with the indicated number of
7457 BITS. */
7458
7459static bfd_boolean
7460unsigned_overflow (valueT value, unsigned bits)
7461{
7462 valueT lim;
7463 if (bits >= sizeof (valueT) * 8)
7464 return FALSE;
7465 lim = (valueT) 1 << bits;
7466 return (value >= lim);
7467}
7468
7469
7470/* Return non-zero if the indicated VALUE has overflowed the maximum
7471 range expressible by an signed number with the indicated number of
7472 BITS. */
7473
7474static bfd_boolean
7475signed_overflow (offsetT value, unsigned bits)
7476{
7477 offsetT lim;
7478 if (bits >= sizeof (offsetT) * 8)
7479 return FALSE;
7480 lim = (offsetT) 1 << (bits - 1);
7481 return (value < -lim || value >= lim);
7482}
7483
7484/* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7485 unsigned immediate offset load/store instruction, try to encode it as
7486 an unscaled, 9-bit, signed immediate offset load/store instruction.
7487 Return TRUE if it is successful; otherwise return FALSE.
7488
7489 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7490 in response to the standard LDR/STR mnemonics when the immediate offset is
7491 unambiguous, i.e. when it is negative or unaligned. */
7492
7493static bfd_boolean
7494try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
7495{
7496 int idx;
7497 enum aarch64_op new_op;
7498 const aarch64_opcode *new_opcode;
7499
7500 gas_assert (instr->opcode->iclass == ldst_pos);
7501
7502 switch (instr->opcode->op)
7503 {
7504 case OP_LDRB_POS:new_op = OP_LDURB; break;
7505 case OP_STRB_POS: new_op = OP_STURB; break;
7506 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
7507 case OP_LDRH_POS: new_op = OP_LDURH; break;
7508 case OP_STRH_POS: new_op = OP_STURH; break;
7509 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
7510 case OP_LDR_POS: new_op = OP_LDUR; break;
7511 case OP_STR_POS: new_op = OP_STUR; break;
7512 case OP_LDRF_POS: new_op = OP_LDURV; break;
7513 case OP_STRF_POS: new_op = OP_STURV; break;
7514 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
7515 case OP_PRFM_POS: new_op = OP_PRFUM; break;
7516 default: new_op = OP_NIL; break;
7517 }
7518
7519 if (new_op == OP_NIL)
7520 return FALSE;
7521
7522 new_opcode = aarch64_get_opcode (new_op);
7523 gas_assert (new_opcode != NULL);
7524
7525 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7526 instr->opcode->op, new_opcode->op);
7527
7528 aarch64_replace_opcode (instr, new_opcode);
7529
7530 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7531 qualifier matching may fail because the out-of-date qualifier will
7532 prevent the operand being updated with a new and correct qualifier. */
7533 idx = aarch64_operand_index (instr->opcode->operands,
7534 AARCH64_OPND_ADDR_SIMM9);
7535 gas_assert (idx == 1);
7536 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
7537
7538 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7539
7e84b55d
TC
7540 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL,
7541 insn_sequence))
a06ea964
NC
7542 return FALSE;
7543
7544 return TRUE;
7545}
7546
7547/* Called by fix_insn to fix a MOV immediate alias instruction.
7548
7549 Operand for a generic move immediate instruction, which is an alias
7550 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7551 a 32-bit/64-bit immediate value into general register. An assembler error
7552 shall result if the immediate cannot be created by a single one of these
7553 instructions. If there is a choice, then to ensure reversability an
7554 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7555
7556static void
7557fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
7558{
7559 const aarch64_opcode *opcode;
7560
7561 /* Need to check if the destination is SP/ZR. The check has to be done
7562 before any aarch64_replace_opcode. */
7563 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
7564 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
7565
7566 instr->operands[1].imm.value = value;
7567 instr->operands[1].skip = 0;
7568
7569 if (try_mov_wide_p)
7570 {
7571 /* Try the MOVZ alias. */
7572 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
7573 aarch64_replace_opcode (instr, opcode);
7574 if (aarch64_opcode_encode (instr->opcode, instr,
7e84b55d 7575 &instr->value, NULL, NULL, insn_sequence))
a06ea964
NC
7576 {
7577 put_aarch64_insn (buf, instr->value);
7578 return;
7579 }
7580 /* Try the MOVK alias. */
7581 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
7582 aarch64_replace_opcode (instr, opcode);
7583 if (aarch64_opcode_encode (instr->opcode, instr,
7e84b55d 7584 &instr->value, NULL, NULL, insn_sequence))
a06ea964
NC
7585 {
7586 put_aarch64_insn (buf, instr->value);
7587 return;
7588 }
7589 }
7590
7591 if (try_mov_bitmask_p)
7592 {
7593 /* Try the ORR alias. */
7594 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
7595 aarch64_replace_opcode (instr, opcode);
7596 if (aarch64_opcode_encode (instr->opcode, instr,
7e84b55d 7597 &instr->value, NULL, NULL, insn_sequence))
a06ea964
NC
7598 {
7599 put_aarch64_insn (buf, instr->value);
7600 return;
7601 }
7602 }
7603
7604 as_bad_where (fixP->fx_file, fixP->fx_line,
7605 _("immediate cannot be moved by a single instruction"));
7606}
7607
7608/* An instruction operand which is immediate related may have symbol used
7609 in the assembly, e.g.
7610
7611 mov w0, u32
7612 .set u32, 0x00ffff00
7613
7614 At the time when the assembly instruction is parsed, a referenced symbol,
7615 like 'u32' in the above example may not have been seen; a fixS is created
7616 in such a case and is handled here after symbols have been resolved.
7617 Instruction is fixed up with VALUE using the information in *FIXP plus
7618 extra information in FLAGS.
7619
7620 This function is called by md_apply_fix to fix up instructions that need
7621 a fix-up described above but does not involve any linker-time relocation. */
7622
7623static void
7624fix_insn (fixS *fixP, uint32_t flags, offsetT value)
7625{
7626 int idx;
7627 uint32_t insn;
7628 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
7629 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
7630 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
7631
7632 if (new_inst)
7633 {
7634 /* Now the instruction is about to be fixed-up, so the operand that
7635 was previously marked as 'ignored' needs to be unmarked in order
7636 to get the encoding done properly. */
7637 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
7638 new_inst->operands[idx].skip = 0;
7639 }
7640
7641 gas_assert (opnd != AARCH64_OPND_NIL);
7642
7643 switch (opnd)
7644 {
7645 case AARCH64_OPND_EXCEPTION:
7646 if (unsigned_overflow (value, 16))
7647 as_bad_where (fixP->fx_file, fixP->fx_line,
7648 _("immediate out of range"));
7649 insn = get_aarch64_insn (buf);
7650 insn |= encode_svc_imm (value);
7651 put_aarch64_insn (buf, insn);
7652 break;
7653
7654 case AARCH64_OPND_AIMM:
7655 /* ADD or SUB with immediate.
7656 NOTE this assumes we come here with a add/sub shifted reg encoding
7657 3 322|2222|2 2 2 21111 111111
7658 1 098|7654|3 2 1 09876 543210 98765 43210
7659 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7660 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7661 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7662 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7663 ->
7664 3 322|2222|2 2 221111111111
7665 1 098|7654|3 2 109876543210 98765 43210
7666 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7667 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7668 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7669 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7670 Fields sf Rn Rd are already set. */
7671 insn = get_aarch64_insn (buf);
7672 if (value < 0)
7673 {
7674 /* Add <-> sub. */
7675 insn = reencode_addsub_switch_add_sub (insn);
7676 value = -value;
7677 }
7678
7679 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
7680 && unsigned_overflow (value, 12))
7681 {
7682 /* Try to shift the value by 12 to make it fit. */
7683 if (((value >> 12) << 12) == value
7684 && ! unsigned_overflow (value, 12 + 12))
7685 {
7686 value >>= 12;
7687 insn |= encode_addsub_imm_shift_amount (1);
7688 }
7689 }
7690
7691 if (unsigned_overflow (value, 12))
7692 as_bad_where (fixP->fx_file, fixP->fx_line,
7693 _("immediate out of range"));
7694
7695 insn |= encode_addsub_imm (value);
7696
7697 put_aarch64_insn (buf, insn);
7698 break;
7699
7700 case AARCH64_OPND_SIMD_IMM:
7701 case AARCH64_OPND_SIMD_IMM_SFT:
7702 case AARCH64_OPND_LIMM:
7703 /* Bit mask immediate. */
7704 gas_assert (new_inst != NULL);
7705 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
7706 new_inst->operands[idx].imm.value = value;
7707 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
7e84b55d 7708 &new_inst->value, NULL, NULL, insn_sequence))
a06ea964
NC
7709 put_aarch64_insn (buf, new_inst->value);
7710 else
7711 as_bad_where (fixP->fx_file, fixP->fx_line,
7712 _("invalid immediate"));
7713 break;
7714
7715 case AARCH64_OPND_HALF:
7716 /* 16-bit unsigned immediate. */
7717 if (unsigned_overflow (value, 16))
7718 as_bad_where (fixP->fx_file, fixP->fx_line,
7719 _("immediate out of range"));
7720 insn = get_aarch64_insn (buf);
7721 insn |= encode_movw_imm (value & 0xffff);
7722 put_aarch64_insn (buf, insn);
7723 break;
7724
7725 case AARCH64_OPND_IMM_MOV:
7726 /* Operand for a generic move immediate instruction, which is
7727 an alias instruction that generates a single MOVZ, MOVN or ORR
7728 instruction to loads a 32-bit/64-bit immediate value into general
7729 register. An assembler error shall result if the immediate cannot be
7730 created by a single one of these instructions. If there is a choice,
7731 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7732 and MOVZ or MOVN to ORR. */
7733 gas_assert (new_inst != NULL);
7734 fix_mov_imm_insn (fixP, buf, new_inst, value);
7735 break;
7736
7737 case AARCH64_OPND_ADDR_SIMM7:
7738 case AARCH64_OPND_ADDR_SIMM9:
7739 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 7740 case AARCH64_OPND_ADDR_SIMM10:
a06ea964 7741 case AARCH64_OPND_ADDR_UIMM12:
fb3265b3
SD
7742 case AARCH64_OPND_ADDR_SIMM11:
7743 case AARCH64_OPND_ADDR_SIMM13:
a06ea964
NC
7744 /* Immediate offset in an address. */
7745 insn = get_aarch64_insn (buf);
7746
7747 gas_assert (new_inst != NULL && new_inst->value == insn);
7748 gas_assert (new_inst->opcode->operands[1] == opnd
7749 || new_inst->opcode->operands[2] == opnd);
7750
7751 /* Get the index of the address operand. */
7752 if (new_inst->opcode->operands[1] == opnd)
7753 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7754 idx = 1;
7755 else
7756 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7757 idx = 2;
7758
7759 /* Update the resolved offset value. */
7760 new_inst->operands[idx].addr.offset.imm = value;
7761
7762 /* Encode/fix-up. */
7763 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
7e84b55d 7764 &new_inst->value, NULL, NULL, insn_sequence))
a06ea964
NC
7765 {
7766 put_aarch64_insn (buf, new_inst->value);
7767 break;
7768 }
7769 else if (new_inst->opcode->iclass == ldst_pos
7770 && try_to_encode_as_unscaled_ldst (new_inst))
7771 {
7772 put_aarch64_insn (buf, new_inst->value);
7773 break;
7774 }
7775
7776 as_bad_where (fixP->fx_file, fixP->fx_line,
7777 _("immediate offset out of range"));
7778 break;
7779
7780 default:
7781 gas_assert (0);
7782 as_fatal (_("unhandled operand code %d"), opnd);
7783 }
7784}
7785
7786/* Apply a fixup (fixP) to segment data, once it has been determined
7787 by our caller that we have all the info we need to fix it up.
7788
7789 Parameter valP is the pointer to the value of the bits. */
7790
7791void
7792md_apply_fix (fixS * fixP, valueT * valP, segT seg)
7793{
7794 offsetT value = *valP;
7795 uint32_t insn;
7796 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
7797 int scale;
7798 unsigned flags = fixP->fx_addnumber;
7799
7800 DEBUG_TRACE ("\n\n");
7801 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7802 DEBUG_TRACE ("Enter md_apply_fix");
7803
7804 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
7805
7806 /* Note whether this will delete the relocation. */
7807
7808 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
7809 fixP->fx_done = 1;
7810
7811 /* Process the relocations. */
7812 switch (fixP->fx_r_type)
7813 {
7814 case BFD_RELOC_NONE:
7815 /* This will need to go in the object file. */
7816 fixP->fx_done = 0;
7817 break;
7818
7819 case BFD_RELOC_8:
7820 case BFD_RELOC_8_PCREL:
7821 if (fixP->fx_done || !seg->use_rela_p)
7822 md_number_to_chars (buf, value, 1);
7823 break;
7824
7825 case BFD_RELOC_16:
7826 case BFD_RELOC_16_PCREL:
7827 if (fixP->fx_done || !seg->use_rela_p)
7828 md_number_to_chars (buf, value, 2);
7829 break;
7830
7831 case BFD_RELOC_32:
7832 case BFD_RELOC_32_PCREL:
7833 if (fixP->fx_done || !seg->use_rela_p)
7834 md_number_to_chars (buf, value, 4);
7835 break;
7836
7837 case BFD_RELOC_64:
7838 case BFD_RELOC_64_PCREL:
7839 if (fixP->fx_done || !seg->use_rela_p)
7840 md_number_to_chars (buf, value, 8);
7841 break;
7842
7843 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7844 /* We claim that these fixups have been processed here, even if
7845 in fact we generate an error because we do not have a reloc
7846 for them, so tc_gen_reloc() will reject them. */
7847 fixP->fx_done = 1;
7848 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
7849 {
7850 as_bad_where (fixP->fx_file, fixP->fx_line,
7851 _("undefined symbol %s used as an immediate value"),
7852 S_GET_NAME (fixP->fx_addsy));
7853 goto apply_fix_return;
7854 }
7855 fix_insn (fixP, flags, value);
7856 break;
7857
7858 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
a06ea964
NC
7859 if (fixP->fx_done || !seg->use_rela_p)
7860 {
89d2a2a3
MS
7861 if (value & 3)
7862 as_bad_where (fixP->fx_file, fixP->fx_line,
7863 _("pc-relative load offset not word aligned"));
7864 if (signed_overflow (value, 21))
7865 as_bad_where (fixP->fx_file, fixP->fx_line,
7866 _("pc-relative load offset out of range"));
a06ea964
NC
7867 insn = get_aarch64_insn (buf);
7868 insn |= encode_ld_lit_ofs_19 (value >> 2);
7869 put_aarch64_insn (buf, insn);
7870 }
7871 break;
7872
7873 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
a06ea964
NC
7874 if (fixP->fx_done || !seg->use_rela_p)
7875 {
89d2a2a3
MS
7876 if (signed_overflow (value, 21))
7877 as_bad_where (fixP->fx_file, fixP->fx_line,
7878 _("pc-relative address offset out of range"));
a06ea964
NC
7879 insn = get_aarch64_insn (buf);
7880 insn |= encode_adr_imm (value);
7881 put_aarch64_insn (buf, insn);
7882 }
7883 break;
7884
7885 case BFD_RELOC_AARCH64_BRANCH19:
a06ea964
NC
7886 if (fixP->fx_done || !seg->use_rela_p)
7887 {
89d2a2a3
MS
7888 if (value & 3)
7889 as_bad_where (fixP->fx_file, fixP->fx_line,
7890 _("conditional branch target not word aligned"));
7891 if (signed_overflow (value, 21))
7892 as_bad_where (fixP->fx_file, fixP->fx_line,
7893 _("conditional branch out of range"));
a06ea964
NC
7894 insn = get_aarch64_insn (buf);
7895 insn |= encode_cond_branch_ofs_19 (value >> 2);
7896 put_aarch64_insn (buf, insn);
7897 }
7898 break;
7899
7900 case BFD_RELOC_AARCH64_TSTBR14:
a06ea964
NC
7901 if (fixP->fx_done || !seg->use_rela_p)
7902 {
89d2a2a3
MS
7903 if (value & 3)
7904 as_bad_where (fixP->fx_file, fixP->fx_line,
7905 _("conditional branch target not word aligned"));
7906 if (signed_overflow (value, 16))
7907 as_bad_where (fixP->fx_file, fixP->fx_line,
7908 _("conditional branch out of range"));
a06ea964
NC
7909 insn = get_aarch64_insn (buf);
7910 insn |= encode_tst_branch_ofs_14 (value >> 2);
7911 put_aarch64_insn (buf, insn);
7912 }
7913 break;
7914
a06ea964 7915 case BFD_RELOC_AARCH64_CALL26:
f09c556a 7916 case BFD_RELOC_AARCH64_JUMP26:
a06ea964
NC
7917 if (fixP->fx_done || !seg->use_rela_p)
7918 {
89d2a2a3
MS
7919 if (value & 3)
7920 as_bad_where (fixP->fx_file, fixP->fx_line,
7921 _("branch target not word aligned"));
7922 if (signed_overflow (value, 28))
7923 as_bad_where (fixP->fx_file, fixP->fx_line,
7924 _("branch out of range"));
a06ea964
NC
7925 insn = get_aarch64_insn (buf);
7926 insn |= encode_branch_ofs_26 (value >> 2);
7927 put_aarch64_insn (buf, insn);
7928 }
7929 break;
7930
7931 case BFD_RELOC_AARCH64_MOVW_G0:
a06ea964 7932 case BFD_RELOC_AARCH64_MOVW_G0_NC:
f09c556a 7933 case BFD_RELOC_AARCH64_MOVW_G0_S:
ca632371 7934 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
32247401
RL
7935 case BFD_RELOC_AARCH64_MOVW_PREL_G0:
7936 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
a06ea964
NC
7937 scale = 0;
7938 goto movw_common;
7939 case BFD_RELOC_AARCH64_MOVW_G1:
a06ea964 7940 case BFD_RELOC_AARCH64_MOVW_G1_NC:
f09c556a 7941 case BFD_RELOC_AARCH64_MOVW_G1_S:
654248e7 7942 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
32247401
RL
7943 case BFD_RELOC_AARCH64_MOVW_PREL_G1:
7944 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
a06ea964
NC
7945 scale = 16;
7946 goto movw_common;
43a357f9
RL
7947 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7948 scale = 0;
7949 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7950 /* Should always be exported to object file, see
7951 aarch64_force_relocation(). */
7952 gas_assert (!fixP->fx_done);
7953 gas_assert (seg->use_rela_p);
7954 goto movw_common;
7955 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7956 scale = 16;
7957 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7958 /* Should always be exported to object file, see
7959 aarch64_force_relocation(). */
7960 gas_assert (!fixP->fx_done);
7961 gas_assert (seg->use_rela_p);
7962 goto movw_common;
a06ea964 7963 case BFD_RELOC_AARCH64_MOVW_G2:
a06ea964 7964 case BFD_RELOC_AARCH64_MOVW_G2_NC:
f09c556a 7965 case BFD_RELOC_AARCH64_MOVW_G2_S:
32247401
RL
7966 case BFD_RELOC_AARCH64_MOVW_PREL_G2:
7967 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
a06ea964
NC
7968 scale = 32;
7969 goto movw_common;
7970 case BFD_RELOC_AARCH64_MOVW_G3:
32247401 7971 case BFD_RELOC_AARCH64_MOVW_PREL_G3:
a06ea964
NC
7972 scale = 48;
7973 movw_common:
7974 if (fixP->fx_done || !seg->use_rela_p)
7975 {
7976 insn = get_aarch64_insn (buf);
7977
7978 if (!fixP->fx_done)
7979 {
7980 /* REL signed addend must fit in 16 bits */
7981 if (signed_overflow (value, 16))
7982 as_bad_where (fixP->fx_file, fixP->fx_line,
7983 _("offset out of range"));
7984 }
7985 else
7986 {
7987 /* Check for overflow and scale. */
7988 switch (fixP->fx_r_type)
7989 {
7990 case BFD_RELOC_AARCH64_MOVW_G0:
7991 case BFD_RELOC_AARCH64_MOVW_G1:
7992 case BFD_RELOC_AARCH64_MOVW_G2:
7993 case BFD_RELOC_AARCH64_MOVW_G3:
654248e7 7994 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
43a357f9 7995 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
a06ea964
NC
7996 if (unsigned_overflow (value, scale + 16))
7997 as_bad_where (fixP->fx_file, fixP->fx_line,
7998 _("unsigned value out of range"));
7999 break;
8000 case BFD_RELOC_AARCH64_MOVW_G0_S:
8001 case BFD_RELOC_AARCH64_MOVW_G1_S:
8002 case BFD_RELOC_AARCH64_MOVW_G2_S:
32247401
RL
8003 case BFD_RELOC_AARCH64_MOVW_PREL_G0:
8004 case BFD_RELOC_AARCH64_MOVW_PREL_G1:
8005 case BFD_RELOC_AARCH64_MOVW_PREL_G2:
a06ea964
NC
8006 /* NOTE: We can only come here with movz or movn. */
8007 if (signed_overflow (value, scale + 16))
8008 as_bad_where (fixP->fx_file, fixP->fx_line,
8009 _("signed value out of range"));
8010 if (value < 0)
8011 {
8012 /* Force use of MOVN. */
8013 value = ~value;
8014 insn = reencode_movzn_to_movn (insn);
8015 }
8016 else
8017 {
8018 /* Force use of MOVZ. */
8019 insn = reencode_movzn_to_movz (insn);
8020 }
8021 break;
8022 default:
8023 /* Unchecked relocations. */
8024 break;
8025 }
8026 value >>= scale;
8027 }
8028
8029 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8030 insn |= encode_movw_imm (value & 0xffff);
8031
8032 put_aarch64_insn (buf, insn);
8033 }
8034 break;
8035
a6bb11b2
YZ
8036 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
8037 fixP->fx_r_type = (ilp32_p
8038 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8039 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
8040 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8041 /* Should always be exported to object file, see
8042 aarch64_force_relocation(). */
8043 gas_assert (!fixP->fx_done);
8044 gas_assert (seg->use_rela_p);
8045 break;
8046
8047 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
8048 fixP->fx_r_type = (ilp32_p
8049 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
f955cccf 8050 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12);
a6bb11b2
YZ
8051 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8052 /* Should always be exported to object file, see
8053 aarch64_force_relocation(). */
8054 gas_assert (!fixP->fx_done);
8055 gas_assert (seg->use_rela_p);
8056 break;
8057
f955cccf 8058 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:
2c0a3565 8059 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
389b8029 8060 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
2c0a3565 8061 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
f955cccf 8062 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:
1ada945d 8063 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
a06ea964 8064 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
2c0a3565 8065 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
3c12b054 8066 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
3e8286c0 8067 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
1aa66fb1 8068 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
a06ea964 8069 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
a6bb11b2 8070 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
2c0a3565 8071 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
043bf05a 8072 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
3b957e5b
RL
8073 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
8074 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
49df5539 8075 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
70151fb5 8076 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
13289c10 8077 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
a12fad50 8078 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
1107e076 8079 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
6c37fedc 8080 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
4c562523
JW
8081 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
8082 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
8083 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
8084 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
8085 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
8086 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
8087 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
8088 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
49df5539
JW
8089 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
8090 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
8091 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
8092 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
8093 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
84f1b9fb
RL
8094 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
8095 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
8096 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
8097 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
8098 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
8099 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
8100 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
8101 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
a06ea964 8102 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
2c0a3565 8103 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
a06ea964 8104 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
a06ea964
NC
8105 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
8106 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
2c0a3565
MS
8107 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
8108 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
8109 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
a06ea964
NC
8110 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8111 /* Should always be exported to object file, see
8112 aarch64_force_relocation(). */
8113 gas_assert (!fixP->fx_done);
8114 gas_assert (seg->use_rela_p);
8115 break;
8116
a6bb11b2
YZ
8117 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
8118 /* Should always be exported to object file, see
8119 aarch64_force_relocation(). */
8120 fixP->fx_r_type = (ilp32_p
8121 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8122 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
8123 gas_assert (!fixP->fx_done);
8124 gas_assert (seg->use_rela_p);
8125 break;
8126
a06ea964 8127 case BFD_RELOC_AARCH64_ADD_LO12:
f09c556a
JW
8128 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
8129 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
8130 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
8131 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
8132 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
3d715ce4 8133 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
87f5fbcc 8134 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
a921b5bd 8135 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
f09c556a
JW
8136 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
8137 case BFD_RELOC_AARCH64_LDST128_LO12:
a06ea964
NC
8138 case BFD_RELOC_AARCH64_LDST16_LO12:
8139 case BFD_RELOC_AARCH64_LDST32_LO12:
8140 case BFD_RELOC_AARCH64_LDST64_LO12:
f09c556a 8141 case BFD_RELOC_AARCH64_LDST8_LO12:
a06ea964
NC
8142 /* Should always be exported to object file, see
8143 aarch64_force_relocation(). */
8144 gas_assert (!fixP->fx_done);
8145 gas_assert (seg->use_rela_p);
8146 break;
8147
8148 case BFD_RELOC_AARCH64_TLSDESC_ADD:
a06ea964 8149 case BFD_RELOC_AARCH64_TLSDESC_CALL:
f09c556a 8150 case BFD_RELOC_AARCH64_TLSDESC_LDR:
a06ea964
NC
8151 break;
8152
b97e87cc
NC
8153 case BFD_RELOC_UNUSED:
8154 /* An error will already have been reported. */
8155 break;
8156
a06ea964
NC
8157 default:
8158 as_bad_where (fixP->fx_file, fixP->fx_line,
8159 _("unexpected %s fixup"),
8160 bfd_get_reloc_code_name (fixP->fx_r_type));
8161 break;
8162 }
8163
8164apply_fix_return:
8165 /* Free the allocated the struct aarch64_inst.
8166 N.B. currently there are very limited number of fix-up types actually use
8167 this field, so the impact on the performance should be minimal . */
8168 if (fixP->tc_fix_data.inst != NULL)
8169 free (fixP->tc_fix_data.inst);
8170
8171 return;
8172}
8173
8174/* Translate internal representation of relocation info to BFD target
8175 format. */
8176
8177arelent *
8178tc_gen_reloc (asection * section, fixS * fixp)
8179{
8180 arelent *reloc;
8181 bfd_reloc_code_real_type code;
8182
325801bd 8183 reloc = XNEW (arelent);
a06ea964 8184
325801bd 8185 reloc->sym_ptr_ptr = XNEW (asymbol *);
a06ea964
NC
8186 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8187 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
8188
8189 if (fixp->fx_pcrel)
8190 {
8191 if (section->use_rela_p)
8192 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
8193 else
8194 fixp->fx_offset = reloc->address;
8195 }
8196 reloc->addend = fixp->fx_offset;
8197
8198 code = fixp->fx_r_type;
8199 switch (code)
8200 {
8201 case BFD_RELOC_16:
8202 if (fixp->fx_pcrel)
8203 code = BFD_RELOC_16_PCREL;
8204 break;
8205
8206 case BFD_RELOC_32:
8207 if (fixp->fx_pcrel)
8208 code = BFD_RELOC_32_PCREL;
8209 break;
8210
8211 case BFD_RELOC_64:
8212 if (fixp->fx_pcrel)
8213 code = BFD_RELOC_64_PCREL;
8214 break;
8215
8216 default:
8217 break;
8218 }
8219
8220 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
8221 if (reloc->howto == NULL)
8222 {
8223 as_bad_where (fixp->fx_file, fixp->fx_line,
8224 _
8225 ("cannot represent %s relocation in this object file format"),
8226 bfd_get_reloc_code_name (code));
8227 return NULL;
8228 }
8229
8230 return reloc;
8231}
8232
8233/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8234
8235void
8236cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
8237{
8238 bfd_reloc_code_real_type type;
8239 int pcrel = 0;
8240
8241 /* Pick a reloc.
8242 FIXME: @@ Should look at CPU word size. */
8243 switch (size)
8244 {
8245 case 1:
8246 type = BFD_RELOC_8;
8247 break;
8248 case 2:
8249 type = BFD_RELOC_16;
8250 break;
8251 case 4:
8252 type = BFD_RELOC_32;
8253 break;
8254 case 8:
8255 type = BFD_RELOC_64;
8256 break;
8257 default:
8258 as_bad (_("cannot do %u-byte relocation"), size);
8259 type = BFD_RELOC_UNUSED;
8260 break;
8261 }
8262
8263 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
8264}
8265
8266int
8267aarch64_force_relocation (struct fix *fixp)
8268{
8269 switch (fixp->fx_r_type)
8270 {
8271 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
8272 /* Perform these "immediate" internal relocations
8273 even if the symbol is extern or weak. */
8274 return 0;
8275
a6bb11b2 8276 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
f09c556a
JW
8277 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
8278 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
a6bb11b2
YZ
8279 /* Pseudo relocs that need to be fixed up according to
8280 ilp32_p. */
8281 return 0;
8282
2c0a3565
MS
8283 case BFD_RELOC_AARCH64_ADD_LO12:
8284 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
8285 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
8286 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
8287 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
8288 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
3d715ce4 8289 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
87f5fbcc 8290 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
a921b5bd 8291 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
2c0a3565
MS
8292 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
8293 case BFD_RELOC_AARCH64_LDST128_LO12:
8294 case BFD_RELOC_AARCH64_LDST16_LO12:
8295 case BFD_RELOC_AARCH64_LDST32_LO12:
8296 case BFD_RELOC_AARCH64_LDST64_LO12:
8297 case BFD_RELOC_AARCH64_LDST8_LO12:
f955cccf 8298 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:
2c0a3565 8299 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
389b8029 8300 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
2c0a3565 8301 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
f955cccf 8302 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:
1ada945d 8303 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
43a357f9
RL
8304 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
8305 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
a06ea964 8306 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
2c0a3565 8307 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
3c12b054 8308 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
3e8286c0 8309 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
1aa66fb1 8310 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
a06ea964 8311 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
a6bb11b2 8312 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
2c0a3565 8313 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
043bf05a 8314 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
3b957e5b
RL
8315 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
8316 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
8317 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
70151fb5 8318 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
13289c10 8319 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
a12fad50 8320 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
1107e076 8321 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
6c37fedc 8322 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
4c562523
JW
8323 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
8324 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
8325 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
8326 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
8327 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
8328 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
8329 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
8330 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
49df5539
JW
8331 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
8332 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
8333 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
8334 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
8335 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
84f1b9fb
RL
8336 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
8337 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
8338 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
8339 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
8340 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
8341 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
8342 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
8343 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
a06ea964 8344 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
2c0a3565 8345 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
a06ea964 8346 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
a06ea964
NC
8347 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
8348 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
2c0a3565
MS
8349 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
8350 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
8351 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
a06ea964
NC
8352 /* Always leave these relocations for the linker. */
8353 return 1;
8354
8355 default:
8356 break;
8357 }
8358
8359 return generic_force_reloc (fixp);
8360}
8361
8362#ifdef OBJ_ELF
8363
3c0367d0
JW
8364/* Implement md_after_parse_args. This is the earliest time we need to decide
8365 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8366
8367void
8368aarch64_after_parse_args (void)
8369{
8370 if (aarch64_abi != AARCH64_ABI_NONE)
8371 return;
8372
8373 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8374 if (strlen (default_arch) > 7 && strcmp (default_arch + 7, ":32") == 0)
8375 aarch64_abi = AARCH64_ABI_ILP32;
8376 else
8377 aarch64_abi = AARCH64_ABI_LP64;
8378}
8379
a06ea964
NC
8380const char *
8381elf64_aarch64_target_format (void)
8382{
12400dcc
AM
8383#ifdef TE_CLOUDABI
8384 /* FIXME: What to do for ilp32_p ? */
8385 if (target_big_endian)
8386 return "elf64-bigaarch64-cloudabi";
8387 else
8388 return "elf64-littleaarch64-cloudabi";
8389#else
a06ea964 8390 if (target_big_endian)
cec5225b 8391 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
a06ea964 8392 else
cec5225b 8393 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
12400dcc 8394#endif
a06ea964
NC
8395}
8396
8397void
8398aarch64elf_frob_symbol (symbolS * symp, int *puntp)
8399{
8400 elf_frob_symbol (symp, puntp);
8401}
8402#endif
8403
8404/* MD interface: Finalization. */
8405
8406/* A good place to do this, although this was probably not intended
8407 for this kind of use. We need to dump the literal pool before
8408 references are made to a null symbol pointer. */
8409
8410void
8411aarch64_cleanup (void)
8412{
8413 literal_pool *pool;
8414
8415 for (pool = list_of_pools; pool; pool = pool->next)
8416 {
8417 /* Put it at the end of the relevant section. */
8418 subseg_set (pool->section, pool->sub_section);
8419 s_ltorg (0);
8420 }
8421}
8422
8423#ifdef OBJ_ELF
8424/* Remove any excess mapping symbols generated for alignment frags in
8425 SEC. We may have created a mapping symbol before a zero byte
8426 alignment; remove it if there's a mapping symbol after the
8427 alignment. */
8428static void
8429check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
8430 void *dummy ATTRIBUTE_UNUSED)
8431{
8432 segment_info_type *seginfo = seg_info (sec);
8433 fragS *fragp;
8434
8435 if (seginfo == NULL || seginfo->frchainP == NULL)
8436 return;
8437
8438 for (fragp = seginfo->frchainP->frch_root;
8439 fragp != NULL; fragp = fragp->fr_next)
8440 {
8441 symbolS *sym = fragp->tc_frag_data.last_map;
8442 fragS *next = fragp->fr_next;
8443
8444 /* Variable-sized frags have been converted to fixed size by
8445 this point. But if this was variable-sized to start with,
8446 there will be a fixed-size frag after it. So don't handle
8447 next == NULL. */
8448 if (sym == NULL || next == NULL)
8449 continue;
8450
8451 if (S_GET_VALUE (sym) < next->fr_address)
8452 /* Not at the end of this frag. */
8453 continue;
8454 know (S_GET_VALUE (sym) == next->fr_address);
8455
8456 do
8457 {
8458 if (next->tc_frag_data.first_map != NULL)
8459 {
8460 /* Next frag starts with a mapping symbol. Discard this
8461 one. */
8462 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
8463 break;
8464 }
8465
8466 if (next->fr_next == NULL)
8467 {
8468 /* This mapping symbol is at the end of the section. Discard
8469 it. */
8470 know (next->fr_fix == 0 && next->fr_var == 0);
8471 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
8472 break;
8473 }
8474
8475 /* As long as we have empty frags without any mapping symbols,
8476 keep looking. */
8477 /* If the next frag is non-empty and does not start with a
8478 mapping symbol, then this mapping symbol is required. */
8479 if (next->fr_address != next->fr_next->fr_address)
8480 break;
8481
8482 next = next->fr_next;
8483 }
8484 while (next != NULL);
8485 }
8486}
8487#endif
8488
8489/* Adjust the symbol table. */
8490
8491void
8492aarch64_adjust_symtab (void)
8493{
8494#ifdef OBJ_ELF
8495 /* Remove any overlapping mapping symbols generated by alignment frags. */
8496 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
8497 /* Now do generic ELF adjustments. */
8498 elf_adjust_symtab ();
8499#endif
8500}
8501
8502static void
8503checked_hash_insert (struct hash_control *table, const char *key, void *value)
8504{
8505 const char *hash_err;
8506
8507 hash_err = hash_insert (table, key, value);
8508 if (hash_err)
8509 printf ("Internal Error: Can't hash %s\n", key);
8510}
8511
8512static void
8513fill_instruction_hash_table (void)
8514{
8515 aarch64_opcode *opcode = aarch64_opcode_table;
8516
8517 while (opcode->name != NULL)
8518 {
8519 templates *templ, *new_templ;
8520 templ = hash_find (aarch64_ops_hsh, opcode->name);
8521
add39d23 8522 new_templ = XNEW (templates);
a06ea964
NC
8523 new_templ->opcode = opcode;
8524 new_templ->next = NULL;
8525
8526 if (!templ)
8527 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
8528 else
8529 {
8530 new_templ->next = templ->next;
8531 templ->next = new_templ;
8532 }
8533 ++opcode;
8534 }
8535}
8536
8537static inline void
8538convert_to_upper (char *dst, const char *src, size_t num)
8539{
8540 unsigned int i;
8541 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
8542 *dst = TOUPPER (*src);
8543 *dst = '\0';
8544}
8545
8546/* Assume STR point to a lower-case string, allocate, convert and return
8547 the corresponding upper-case string. */
8548static inline const char*
8549get_upper_str (const char *str)
8550{
8551 char *ret;
8552 size_t len = strlen (str);
325801bd 8553 ret = XNEWVEC (char, len + 1);
a06ea964
NC
8554 convert_to_upper (ret, str, len);
8555 return ret;
8556}
8557
8558/* MD interface: Initialization. */
8559
8560void
8561md_begin (void)
8562{
8563 unsigned mach;
8564 unsigned int i;
8565
8566 if ((aarch64_ops_hsh = hash_new ()) == NULL
8567 || (aarch64_cond_hsh = hash_new ()) == NULL
8568 || (aarch64_shift_hsh = hash_new ()) == NULL
8569 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
8570 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
8571 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
8572 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
8573 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
8574 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
2ac435d4 8575 || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL
a06ea964
NC
8576 || (aarch64_reg_hsh = hash_new ()) == NULL
8577 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
8578 || (aarch64_nzcv_hsh = hash_new ()) == NULL
1e6f4800
MW
8579 || (aarch64_pldop_hsh = hash_new ()) == NULL
8580 || (aarch64_hint_opt_hsh = hash_new ()) == NULL)
a06ea964
NC
8581 as_fatal (_("virtual memory exhausted"));
8582
8583 fill_instruction_hash_table ();
8584
8585 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
8586 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
8587 (void *) (aarch64_sys_regs + i));
8588
8589 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
8590 checked_hash_insert (aarch64_pstatefield_hsh,
8591 aarch64_pstatefields[i].name,
8592 (void *) (aarch64_pstatefields + i));
8593
875880c6 8594 for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++)
a06ea964 8595 checked_hash_insert (aarch64_sys_regs_ic_hsh,
875880c6 8596 aarch64_sys_regs_ic[i].name,
a06ea964
NC
8597 (void *) (aarch64_sys_regs_ic + i));
8598
875880c6 8599 for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++)
a06ea964 8600 checked_hash_insert (aarch64_sys_regs_dc_hsh,
875880c6 8601 aarch64_sys_regs_dc[i].name,
a06ea964
NC
8602 (void *) (aarch64_sys_regs_dc + i));
8603
875880c6 8604 for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++)
a06ea964 8605 checked_hash_insert (aarch64_sys_regs_at_hsh,
875880c6 8606 aarch64_sys_regs_at[i].name,
a06ea964
NC
8607 (void *) (aarch64_sys_regs_at + i));
8608
875880c6 8609 for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++)
a06ea964 8610 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
875880c6 8611 aarch64_sys_regs_tlbi[i].name,
a06ea964
NC
8612 (void *) (aarch64_sys_regs_tlbi + i));
8613
2ac435d4
SD
8614 for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
8615 checked_hash_insert (aarch64_sys_regs_sr_hsh,
8616 aarch64_sys_regs_sr[i].name,
8617 (void *) (aarch64_sys_regs_sr + i));
8618
a06ea964
NC
8619 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
8620 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
8621 (void *) (reg_names + i));
8622
8623 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
8624 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
8625 (void *) (nzcv_names + i));
8626
8627 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
8628 {
8629 const char *name = aarch64_operand_modifiers[i].name;
8630 checked_hash_insert (aarch64_shift_hsh, name,
8631 (void *) (aarch64_operand_modifiers + i));
8632 /* Also hash the name in the upper case. */
8633 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
8634 (void *) (aarch64_operand_modifiers + i));
8635 }
8636
8637 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
8638 {
8639 unsigned int j;
8640 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8641 the same condition code. */
8642 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
8643 {
8644 const char *name = aarch64_conds[i].names[j];
8645 if (name == NULL)
8646 break;
8647 checked_hash_insert (aarch64_cond_hsh, name,
8648 (void *) (aarch64_conds + i));
8649 /* Also hash the name in the upper case. */
8650 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
8651 (void *) (aarch64_conds + i));
8652 }
8653 }
8654
8655 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
8656 {
8657 const char *name = aarch64_barrier_options[i].name;
8658 /* Skip xx00 - the unallocated values of option. */
8659 if ((i & 0x3) == 0)
8660 continue;
8661 checked_hash_insert (aarch64_barrier_opt_hsh, name,
8662 (void *) (aarch64_barrier_options + i));
8663 /* Also hash the name in the upper case. */
8664 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
8665 (void *) (aarch64_barrier_options + i));
8666 }
8667
8668 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
8669 {
8670 const char* name = aarch64_prfops[i].name;
a1ccaec9
YZ
8671 /* Skip the unallocated hint encodings. */
8672 if (name == NULL)
a06ea964
NC
8673 continue;
8674 checked_hash_insert (aarch64_pldop_hsh, name,
8675 (void *) (aarch64_prfops + i));
8676 /* Also hash the name in the upper case. */
8677 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
8678 (void *) (aarch64_prfops + i));
8679 }
8680
1e6f4800
MW
8681 for (i = 0; aarch64_hint_options[i].name != NULL; i++)
8682 {
8683 const char* name = aarch64_hint_options[i].name;
8684
8685 checked_hash_insert (aarch64_hint_opt_hsh, name,
8686 (void *) (aarch64_hint_options + i));
8687 /* Also hash the name in the upper case. */
8688 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
8689 (void *) (aarch64_hint_options + i));
8690 }
8691
a06ea964
NC
8692 /* Set the cpu variant based on the command-line options. */
8693 if (!mcpu_cpu_opt)
8694 mcpu_cpu_opt = march_cpu_opt;
8695
8696 if (!mcpu_cpu_opt)
8697 mcpu_cpu_opt = &cpu_default;
8698
8699 cpu_variant = *mcpu_cpu_opt;
8700
8701 /* Record the CPU type. */
cec5225b 8702 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
a06ea964
NC
8703
8704 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
8705}
8706
8707/* Command line processing. */
8708
8709const char *md_shortopts = "m:";
8710
8711#ifdef AARCH64_BI_ENDIAN
8712#define OPTION_EB (OPTION_MD_BASE + 0)
8713#define OPTION_EL (OPTION_MD_BASE + 1)
8714#else
8715#if TARGET_BYTES_BIG_ENDIAN
8716#define OPTION_EB (OPTION_MD_BASE + 0)
8717#else
8718#define OPTION_EL (OPTION_MD_BASE + 1)
8719#endif
8720#endif
8721
8722struct option md_longopts[] = {
8723#ifdef OPTION_EB
8724 {"EB", no_argument, NULL, OPTION_EB},
8725#endif
8726#ifdef OPTION_EL
8727 {"EL", no_argument, NULL, OPTION_EL},
8728#endif
8729 {NULL, no_argument, NULL, 0}
8730};
8731
8732size_t md_longopts_size = sizeof (md_longopts);
8733
8734struct aarch64_option_table
8735{
e0471c16
TS
8736 const char *option; /* Option name to match. */
8737 const char *help; /* Help information. */
a06ea964
NC
8738 int *var; /* Variable to change. */
8739 int value; /* What to change it to. */
8740 char *deprecated; /* If non-null, print this message. */
8741};
8742
8743static struct aarch64_option_table aarch64_opts[] = {
8744 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
8745 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
8746 NULL},
8747#ifdef DEBUG_AARCH64
8748 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
8749#endif /* DEBUG_AARCH64 */
8750 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
8751 NULL},
a52e6fd3
YZ
8752 {"mno-verbose-error", N_("do not output verbose error messages"),
8753 &verbose_error_p, 0, NULL},
a06ea964
NC
8754 {NULL, NULL, NULL, 0, NULL}
8755};
8756
8757struct aarch64_cpu_option_table
8758{
e0471c16 8759 const char *name;
a06ea964
NC
8760 const aarch64_feature_set value;
8761 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8762 case. */
8763 const char *canonical_name;
8764};
8765
8766/* This list should, at a minimum, contain all the cpu names
8767 recognized by GCC. */
8768static const struct aarch64_cpu_option_table aarch64_cpus[] = {
8769 {"all", AARCH64_ANY, NULL},
9c352f1c
JG
8770 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
8771 AARCH64_FEATURE_CRC), "Cortex-A35"},
aa31c464
JW
8772 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
8773 AARCH64_FEATURE_CRC), "Cortex-A53"},
8774 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8,
8775 AARCH64_FEATURE_CRC), "Cortex-A57"},
2abdd192
JW
8776 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8,
8777 AARCH64_FEATURE_CRC), "Cortex-A72"},
1aa70332
KT
8778 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
8779 AARCH64_FEATURE_CRC), "Cortex-A73"},
1e292627 8780 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
1c5c938a 8781 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
1e292627
JG
8782 "Cortex-A55"},
8783 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
1c5c938a 8784 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
1e292627 8785 "Cortex-A75"},
c2a0f929 8786 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
8787 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
8788 "Cortex-A76"},
c8fcc360
KT
8789 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
8790 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
8791 | AARCH64_FEATURE_DOTPROD
8792 | AARCH64_FEATURE_PROFILE),
8793 "Ares"},
2412d878
EM
8794 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
8795 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
8796 "Samsung Exynos M1"},
2fe9c2a0 8797 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8,
e58ff055
JW
8798 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO
8799 | AARCH64_FEATURE_RDMA),
2fe9c2a0 8800 "Qualcomm Falkor"},
516dbc44
KT
8801 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
8802 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
8803 | AARCH64_FEATURE_DOTPROD
8804 | AARCH64_FEATURE_SSBS),
8805 "Neoverse E1"},
38e75bf2
KT
8806 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
8807 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
8808 | AARCH64_FEATURE_DOTPROD
8809 | AARCH64_FEATURE_PROFILE),
8810 "Neoverse N1"},
6b21c2bf 8811 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
e58ff055
JW
8812 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO
8813 | AARCH64_FEATURE_RDMA),
6b21c2bf 8814 "Qualcomm QDF24XX"},
eb5c42e5 8815 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4,
7605d944
SP
8816 AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_PROFILE),
8817 "Qualcomm Saphira"},
faade851
JW
8818 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
8819 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
8820 "Cavium ThunderX"},
9f99c22e
VP
8821 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1,
8822 AARCH64_FEATURE_CRYPTO),
0a8be2fe 8823 "Broadcom Vulcan"},
070cb956
PT
8824 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8825 in earlier releases and is superseded by 'xgene1' in all
8826 tools. */
9877c63c 8827 {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
070cb956 8828 {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
aa31c464
JW
8829 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8,
8830 AARCH64_FEATURE_CRC), "APM X-Gene 2"},
a06ea964
NC
8831 {"generic", AARCH64_ARCH_V8, NULL},
8832
a06ea964
NC
8833 {NULL, AARCH64_ARCH_NONE, NULL}
8834};
8835
8836struct aarch64_arch_option_table
8837{
e0471c16 8838 const char *name;
a06ea964
NC
8839 const aarch64_feature_set value;
8840};
8841
8842/* This list should, at a minimum, contain all the architecture names
8843 recognized by GCC. */
8844static const struct aarch64_arch_option_table aarch64_archs[] = {
8845 {"all", AARCH64_ANY},
5a1ad39d 8846 {"armv8-a", AARCH64_ARCH_V8},
88f0ea34 8847 {"armv8.1-a", AARCH64_ARCH_V8_1},
acb787b0 8848 {"armv8.2-a", AARCH64_ARCH_V8_2},
1924ff75 8849 {"armv8.3-a", AARCH64_ARCH_V8_3},
b6b9ca0c 8850 {"armv8.4-a", AARCH64_ARCH_V8_4},
70d56181 8851 {"armv8.5-a", AARCH64_ARCH_V8_5},
a06ea964
NC
8852 {NULL, AARCH64_ARCH_NONE}
8853};
8854
8855/* ISA extensions. */
8856struct aarch64_option_cpu_value_table
8857{
e0471c16 8858 const char *name;
a06ea964 8859 const aarch64_feature_set value;
93d8990c 8860 const aarch64_feature_set require; /* Feature dependencies. */
a06ea964
NC
8861};
8862
8863static const struct aarch64_option_cpu_value_table aarch64_features[] = {
93d8990c
SN
8864 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
8865 AARCH64_ARCH_NONE},
c0e7cef7
NC
8866 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8867 | AARCH64_FEATURE_AES
8868 | AARCH64_FEATURE_SHA2, 0),
fa09f4ea 8869 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
93d8990c
SN
8870 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
8871 AARCH64_ARCH_NONE},
8872 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
8873 AARCH64_ARCH_NONE},
8874 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
fa09f4ea 8875 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
93d8990c
SN
8876 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
8877 AARCH64_ARCH_NONE},
8878 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
8879 AARCH64_ARCH_NONE},
8880 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0),
8881 AARCH64_ARCH_NONE},
8882 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0),
8883 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
8884 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
8885 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
d0f7791c
TC
8886 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML, 0),
8887 AARCH64_FEATURE (AARCH64_FEATURE_FP
8888 | AARCH64_FEATURE_F16, 0)},
93d8990c
SN
8889 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
8890 AARCH64_ARCH_NONE},
c0890d26 8891 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
582e12bf
RS
8892 AARCH64_FEATURE (AARCH64_FEATURE_F16
8893 | AARCH64_FEATURE_SIMD
8894 | AARCH64_FEATURE_COMPNUM, 0)},
b83b4b13
SD
8895 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME, 0),
8896 AARCH64_ARCH_NONE},
f482d304
RS
8897 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
8898 AARCH64_FEATURE (AARCH64_FEATURE_F16
8899 | AARCH64_FEATURE_SIMD, 0)},
d74d4880
SN
8900 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
8901 AARCH64_ARCH_NONE},
65a55fbb
TC
8902 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD, 0),
8903 AARCH64_ARCH_NONE},
c0e7cef7
NC
8904 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0),
8905 AARCH64_ARCH_NONE},
68dfbb92
SD
8906 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB, 0),
8907 AARCH64_ARCH_NONE},
2ac435d4
SD
8908 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0),
8909 AARCH64_ARCH_NONE},
c0e7cef7
NC
8910 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
8911 AARCH64_ARCH_NONE},
b6b9ca0c
TC
8912 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
8913 AARCH64_ARCH_NONE},
8914 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8915 | AARCH64_FEATURE_SHA3, 0),
8916 AARCH64_ARCH_NONE},
af4bcb4c
SD
8917 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
8918 AARCH64_ARCH_NONE},
104fefee
SD
8919 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
8920 AARCH64_ARCH_NONE},
73b605ec
SD
8921 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0),
8922 AARCH64_ARCH_NONE},
7ce2460a
MM
8923 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0),
8924 AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
8925 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0),
8926 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8927 | AARCH64_FEATURE_SM4, 0)},
8928 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0),
8929 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8930 | AARCH64_FEATURE_AES, 0)},
8931 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0),
8932 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8933 | AARCH64_FEATURE_SHA3, 0)},
8934 {"bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
8935 AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
93d8990c 8936 {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
a06ea964
NC
8937};
8938
8939struct aarch64_long_option_table
8940{
e0471c16
TS
8941 const char *option; /* Substring to match. */
8942 const char *help; /* Help information. */
17b9d67d 8943 int (*func) (const char *subopt); /* Function to decode sub-option. */
a06ea964
NC
8944 char *deprecated; /* If non-null, print this message. */
8945};
8946
93d8990c
SN
8947/* Transitive closure of features depending on set. */
8948static aarch64_feature_set
8949aarch64_feature_disable_set (aarch64_feature_set set)
8950{
8951 const struct aarch64_option_cpu_value_table *opt;
8952 aarch64_feature_set prev = 0;
8953
8954 while (prev != set) {
8955 prev = set;
8956 for (opt = aarch64_features; opt->name != NULL; opt++)
8957 if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set))
8958 AARCH64_MERGE_FEATURE_SETS (set, set, opt->value);
8959 }
8960 return set;
8961}
8962
8963/* Transitive closure of dependencies of set. */
8964static aarch64_feature_set
8965aarch64_feature_enable_set (aarch64_feature_set set)
8966{
8967 const struct aarch64_option_cpu_value_table *opt;
8968 aarch64_feature_set prev = 0;
8969
8970 while (prev != set) {
8971 prev = set;
8972 for (opt = aarch64_features; opt->name != NULL; opt++)
8973 if (AARCH64_CPU_HAS_FEATURE (set, opt->value))
8974 AARCH64_MERGE_FEATURE_SETS (set, set, opt->require);
8975 }
8976 return set;
8977}
8978
a06ea964 8979static int
82b8a785 8980aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
ae527cd8 8981 bfd_boolean ext_only)
a06ea964
NC
8982{
8983 /* We insist on extensions being added before being removed. We achieve
8984 this by using the ADDING_VALUE variable to indicate whether we are
8985 adding an extension (1) or removing it (0) and only allowing it to
8986 change in the order -1 -> 1 -> 0. */
8987 int adding_value = -1;
325801bd 8988 aarch64_feature_set *ext_set = XNEW (aarch64_feature_set);
a06ea964
NC
8989
8990 /* Copy the feature set, so that we can modify it. */
8991 *ext_set = **opt_p;
8992 *opt_p = ext_set;
8993
8994 while (str != NULL && *str != 0)
8995 {
8996 const struct aarch64_option_cpu_value_table *opt;
82b8a785 8997 const char *ext = NULL;
a06ea964
NC
8998 int optlen;
8999
ae527cd8 9000 if (!ext_only)
a06ea964 9001 {
ae527cd8
JB
9002 if (*str != '+')
9003 {
9004 as_bad (_("invalid architectural extension"));
9005 return 0;
9006 }
a06ea964 9007
ae527cd8
JB
9008 ext = strchr (++str, '+');
9009 }
a06ea964
NC
9010
9011 if (ext != NULL)
9012 optlen = ext - str;
9013 else
9014 optlen = strlen (str);
9015
9016 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
9017 {
9018 if (adding_value != 0)
9019 adding_value = 0;
9020 optlen -= 2;
9021 str += 2;
9022 }
9023 else if (optlen > 0)
9024 {
9025 if (adding_value == -1)
9026 adding_value = 1;
9027 else if (adding_value != 1)
9028 {
9029 as_bad (_("must specify extensions to add before specifying "
9030 "those to remove"));
9031 return FALSE;
9032 }
9033 }
9034
9035 if (optlen == 0)
9036 {
9037 as_bad (_("missing architectural extension"));
9038 return 0;
9039 }
9040
9041 gas_assert (adding_value != -1);
9042
9043 for (opt = aarch64_features; opt->name != NULL; opt++)
9044 if (strncmp (opt->name, str, optlen) == 0)
9045 {
93d8990c
SN
9046 aarch64_feature_set set;
9047
a06ea964
NC
9048 /* Add or remove the extension. */
9049 if (adding_value)
93d8990c
SN
9050 {
9051 set = aarch64_feature_enable_set (opt->value);
9052 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set);
9053 }
a06ea964 9054 else
93d8990c
SN
9055 {
9056 set = aarch64_feature_disable_set (opt->value);
9057 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set);
9058 }
a06ea964
NC
9059 break;
9060 }
9061
9062 if (opt->name == NULL)
9063 {
9064 as_bad (_("unknown architectural extension `%s'"), str);
9065 return 0;
9066 }
9067
9068 str = ext;
9069 };
9070
9071 return 1;
9072}
9073
9074static int
17b9d67d 9075aarch64_parse_cpu (const char *str)
a06ea964
NC
9076{
9077 const struct aarch64_cpu_option_table *opt;
82b8a785 9078 const char *ext = strchr (str, '+');
a06ea964
NC
9079 size_t optlen;
9080
9081 if (ext != NULL)
9082 optlen = ext - str;
9083 else
9084 optlen = strlen (str);
9085
9086 if (optlen == 0)
9087 {
9088 as_bad (_("missing cpu name `%s'"), str);
9089 return 0;
9090 }
9091
9092 for (opt = aarch64_cpus; opt->name != NULL; opt++)
9093 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
9094 {
9095 mcpu_cpu_opt = &opt->value;
9096 if (ext != NULL)
ae527cd8 9097 return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
a06ea964
NC
9098
9099 return 1;
9100 }
9101
9102 as_bad (_("unknown cpu `%s'"), str);
9103 return 0;
9104}
9105
9106static int
17b9d67d 9107aarch64_parse_arch (const char *str)
a06ea964
NC
9108{
9109 const struct aarch64_arch_option_table *opt;
82b8a785 9110 const char *ext = strchr (str, '+');
a06ea964
NC
9111 size_t optlen;
9112
9113 if (ext != NULL)
9114 optlen = ext - str;
9115 else
9116 optlen = strlen (str);
9117
9118 if (optlen == 0)
9119 {
9120 as_bad (_("missing architecture name `%s'"), str);
9121 return 0;
9122 }
9123
9124 for (opt = aarch64_archs; opt->name != NULL; opt++)
9125 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
9126 {
9127 march_cpu_opt = &opt->value;
9128 if (ext != NULL)
ae527cd8 9129 return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
a06ea964
NC
9130
9131 return 1;
9132 }
9133
9134 as_bad (_("unknown architecture `%s'\n"), str);
9135 return 0;
9136}
9137
69091a2c
YZ
9138/* ABIs. */
9139struct aarch64_option_abi_value_table
9140{
e0471c16 9141 const char *name;
69091a2c
YZ
9142 enum aarch64_abi_type value;
9143};
9144
9145static const struct aarch64_option_abi_value_table aarch64_abis[] = {
9146 {"ilp32", AARCH64_ABI_ILP32},
9147 {"lp64", AARCH64_ABI_LP64},
69091a2c
YZ
9148};
9149
9150static int
17b9d67d 9151aarch64_parse_abi (const char *str)
69091a2c 9152{
5703197e 9153 unsigned int i;
69091a2c 9154
5703197e 9155 if (str[0] == '\0')
69091a2c
YZ
9156 {
9157 as_bad (_("missing abi name `%s'"), str);
9158 return 0;
9159 }
9160
5703197e
TS
9161 for (i = 0; i < ARRAY_SIZE (aarch64_abis); i++)
9162 if (strcmp (str, aarch64_abis[i].name) == 0)
69091a2c 9163 {
5703197e 9164 aarch64_abi = aarch64_abis[i].value;
69091a2c
YZ
9165 return 1;
9166 }
9167
9168 as_bad (_("unknown abi `%s'\n"), str);
9169 return 0;
9170}
9171
a06ea964 9172static struct aarch64_long_option_table aarch64_long_opts[] = {
69091a2c
YZ
9173#ifdef OBJ_ELF
9174 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9175 aarch64_parse_abi, NULL},
9176#endif /* OBJ_ELF */
a06ea964
NC
9177 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9178 aarch64_parse_cpu, NULL},
9179 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9180 aarch64_parse_arch, NULL},
9181 {NULL, NULL, 0, NULL}
9182};
9183
9184int
17b9d67d 9185md_parse_option (int c, const char *arg)
a06ea964
NC
9186{
9187 struct aarch64_option_table *opt;
9188 struct aarch64_long_option_table *lopt;
9189
9190 switch (c)
9191 {
9192#ifdef OPTION_EB
9193 case OPTION_EB:
9194 target_big_endian = 1;
9195 break;
9196#endif
9197
9198#ifdef OPTION_EL
9199 case OPTION_EL:
9200 target_big_endian = 0;
9201 break;
9202#endif
9203
9204 case 'a':
9205 /* Listing option. Just ignore these, we don't support additional
9206 ones. */
9207 return 0;
9208
9209 default:
9210 for (opt = aarch64_opts; opt->option != NULL; opt++)
9211 {
9212 if (c == opt->option[0]
9213 && ((arg == NULL && opt->option[1] == 0)
9214 || streq (arg, opt->option + 1)))
9215 {
9216 /* If the option is deprecated, tell the user. */
9217 if (opt->deprecated != NULL)
9218 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
9219 arg ? arg : "", _(opt->deprecated));
9220
9221 if (opt->var != NULL)
9222 *opt->var = opt->value;
9223
9224 return 1;
9225 }
9226 }
9227
9228 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
9229 {
9230 /* These options are expected to have an argument. */
9231 if (c == lopt->option[0]
9232 && arg != NULL
9233 && strncmp (arg, lopt->option + 1,
9234 strlen (lopt->option + 1)) == 0)
9235 {
9236 /* If the option is deprecated, tell the user. */
9237 if (lopt->deprecated != NULL)
9238 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
9239 _(lopt->deprecated));
9240
9241 /* Call the sup-option parser. */
9242 return lopt->func (arg + strlen (lopt->option) - 1);
9243 }
9244 }
9245
9246 return 0;
9247 }
9248
9249 return 1;
9250}
9251
9252void
9253md_show_usage (FILE * fp)
9254{
9255 struct aarch64_option_table *opt;
9256 struct aarch64_long_option_table *lopt;
9257
9258 fprintf (fp, _(" AArch64-specific assembler options:\n"));
9259
9260 for (opt = aarch64_opts; opt->option != NULL; opt++)
9261 if (opt->help != NULL)
9262 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
9263
9264 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
9265 if (lopt->help != NULL)
9266 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
9267
9268#ifdef OPTION_EB
9269 fprintf (fp, _("\
9270 -EB assemble code for a big-endian cpu\n"));
9271#endif
9272
9273#ifdef OPTION_EL
9274 fprintf (fp, _("\
9275 -EL assemble code for a little-endian cpu\n"));
9276#endif
9277}
9278
9279/* Parse a .cpu directive. */
9280
9281static void
9282s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
9283{
9284 const struct aarch64_cpu_option_table *opt;
9285 char saved_char;
9286 char *name;
9287 char *ext;
9288 size_t optlen;
9289
9290 name = input_line_pointer;
9291 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
9292 input_line_pointer++;
9293 saved_char = *input_line_pointer;
9294 *input_line_pointer = 0;
9295
9296 ext = strchr (name, '+');
9297
9298 if (ext != NULL)
9299 optlen = ext - name;
9300 else
9301 optlen = strlen (name);
9302
9303 /* Skip the first "all" entry. */
9304 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
9305 if (strlen (opt->name) == optlen
9306 && strncmp (name, opt->name, optlen) == 0)
9307 {
9308 mcpu_cpu_opt = &opt->value;
9309 if (ext != NULL)
ae527cd8 9310 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
a06ea964
NC
9311 return;
9312
9313 cpu_variant = *mcpu_cpu_opt;
9314
9315 *input_line_pointer = saved_char;
9316 demand_empty_rest_of_line ();
9317 return;
9318 }
9319 as_bad (_("unknown cpu `%s'"), name);
9320 *input_line_pointer = saved_char;
9321 ignore_rest_of_line ();
9322}
9323
9324
9325/* Parse a .arch directive. */
9326
9327static void
9328s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
9329{
9330 const struct aarch64_arch_option_table *opt;
9331 char saved_char;
9332 char *name;
9333 char *ext;
9334 size_t optlen;
9335
9336 name = input_line_pointer;
9337 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
9338 input_line_pointer++;
9339 saved_char = *input_line_pointer;
9340 *input_line_pointer = 0;
9341
9342 ext = strchr (name, '+');
9343
9344 if (ext != NULL)
9345 optlen = ext - name;
9346 else
9347 optlen = strlen (name);
9348
9349 /* Skip the first "all" entry. */
9350 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
9351 if (strlen (opt->name) == optlen
9352 && strncmp (name, opt->name, optlen) == 0)
9353 {
9354 mcpu_cpu_opt = &opt->value;
9355 if (ext != NULL)
ae527cd8 9356 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
a06ea964
NC
9357 return;
9358
9359 cpu_variant = *mcpu_cpu_opt;
9360
9361 *input_line_pointer = saved_char;
9362 demand_empty_rest_of_line ();
9363 return;
9364 }
9365
9366 as_bad (_("unknown architecture `%s'\n"), name);
9367 *input_line_pointer = saved_char;
9368 ignore_rest_of_line ();
9369}
9370
ae527cd8
JB
9371/* Parse a .arch_extension directive. */
9372
9373static void
9374s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED)
9375{
9376 char saved_char;
9377 char *ext = input_line_pointer;;
9378
9379 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
9380 input_line_pointer++;
9381 saved_char = *input_line_pointer;
9382 *input_line_pointer = 0;
9383
9384 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
9385 return;
9386
9387 cpu_variant = *mcpu_cpu_opt;
9388
9389 *input_line_pointer = saved_char;
9390 demand_empty_rest_of_line ();
9391}
9392
a06ea964
NC
9393/* Copy symbol information. */
9394
9395void
9396aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
9397{
9398 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);
9399}
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