Commit | Line | Data |
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252b5132 | 1 | /* tc-arc.c -- Assembler for the ARC |
6f2750fe | 2 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributor: Claudiu Zissulescu <claziss@synopsys.com> | |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19203624 | 19 | along with GAS; see the file COPYING. If not, write to the Free |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
886a2506 | 24 | #include "subsegs.h" |
a161fe53 | 25 | #include "struc-symbol.h" |
886a2506 | 26 | #include "dwarf2dbg.h" |
726c18e1 | 27 | #include "dw2gencfi.h" |
3882b010 | 28 | #include "safe-ctype.h" |
886a2506 | 29 | |
252b5132 RH |
30 | #include "opcode/arc.h" |
31 | #include "elf/arc.h" | |
32 | ||
886a2506 | 33 | /* Defines section. */ |
0d2bcfaf | 34 | |
886a2506 NC |
35 | #define MAX_INSN_FIXUPS 2 |
36 | #define MAX_CONSTR_STR 20 | |
4670103e | 37 | #define FRAG_MAX_GROWTH 8 |
0d2bcfaf | 38 | |
886a2506 NC |
39 | #ifdef DEBUG |
40 | # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args) | |
41 | #else | |
42 | # define pr_debug(fmt, args...) | |
43 | #endif | |
44 | ||
45 | #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27) | |
46 | #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16) | |
4670103e | 47 | #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \ |
886a2506 NC |
48 | (SUB_OPCODE (x) == 0x28)) |
49 | ||
50 | /* Equal to MAX_PRECISION in atof-ieee.c. */ | |
51 | #define MAX_LITTLENUMS 6 | |
52 | ||
4670103e CZ |
53 | /* Enum used to enumerate the relaxable ins operands. */ |
54 | enum rlx_operand_type | |
55 | { | |
56 | EMPTY = 0, | |
57 | REGISTER, | |
58 | REGISTER_S, /* Register for short instruction(s). */ | |
59 | REGISTER_NO_GP, /* Is a register but not gp register specifically. */ | |
60 | REGISTER_DUP, /* Duplication of previous operand of type register. */ | |
61 | IMMEDIATE, | |
62 | BRACKET | |
63 | }; | |
64 | ||
65 | enum arc_rlx_types | |
66 | { | |
67 | ARC_RLX_NONE = 0, | |
68 | ARC_RLX_BL_S, | |
69 | ARC_RLX_BL, | |
70 | ARC_RLX_B_S, | |
71 | ARC_RLX_B, | |
72 | ARC_RLX_ADD_U3, | |
73 | ARC_RLX_ADD_U6, | |
74 | ARC_RLX_ADD_LIMM, | |
75 | ARC_RLX_LD_U7, | |
76 | ARC_RLX_LD_S9, | |
77 | ARC_RLX_LD_LIMM, | |
78 | ARC_RLX_MOV_U8, | |
79 | ARC_RLX_MOV_S12, | |
80 | ARC_RLX_MOV_LIMM, | |
81 | ARC_RLX_SUB_U3, | |
82 | ARC_RLX_SUB_U6, | |
83 | ARC_RLX_SUB_LIMM, | |
84 | ARC_RLX_MPY_U6, | |
85 | ARC_RLX_MPY_LIMM, | |
86 | ARC_RLX_MOV_RU6, | |
87 | ARC_RLX_MOV_RLIMM, | |
88 | ARC_RLX_ADD_RRU6, | |
89 | ARC_RLX_ADD_RRLIMM, | |
90 | }; | |
91 | ||
886a2506 NC |
92 | /* Macros section. */ |
93 | ||
94 | #define regno(x) ((x) & 0x3F) | |
95 | #define is_ir_num(x) (((x) & ~0x3F) == 0) | |
8ddf6b2a CZ |
96 | #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2)) |
97 | #define is_spfp_p(op) (((sc) == SPX)) | |
98 | #define is_dpfp_p(op) (((sc) == DPX)) | |
99 | #define is_fpuda_p(op) (((sc) == DPA)) | |
886a2506 NC |
100 | #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP)) |
101 | #define is_kernel_insn_p(op) (((op)->class == KERNEL)) | |
0d2bcfaf | 102 | |
886a2506 NC |
103 | /* Generic assembler global variables which must be defined by all |
104 | targets. */ | |
0d2bcfaf | 105 | |
886a2506 | 106 | /* Characters which always start a comment. */ |
252b5132 RH |
107 | const char comment_chars[] = "#;"; |
108 | ||
886a2506 | 109 | /* Characters which start a comment at the beginning of a line. */ |
252b5132 RH |
110 | const char line_comment_chars[] = "#"; |
111 | ||
886a2506 NC |
112 | /* Characters which may be used to separate multiple commands on a |
113 | single line. */ | |
114 | const char line_separator_chars[] = "`"; | |
252b5132 | 115 | |
886a2506 NC |
116 | /* Characters which are used to indicate an exponent in a floating |
117 | point number. */ | |
252b5132 RH |
118 | const char EXP_CHARS[] = "eE"; |
119 | ||
bcee8eb8 AM |
120 | /* Chars that mean this number is a floating point constant |
121 | As in 0f12.456 or 0d1.2345e12. */ | |
252b5132 RH |
122 | const char FLT_CHARS[] = "rRsSfFdD"; |
123 | ||
124 | /* Byte order. */ | |
125 | extern int target_big_endian; | |
126 | const char *arc_target_format = DEFAULT_TARGET_FORMAT; | |
127 | static int byte_order = DEFAULT_BYTE_ORDER; | |
128 | ||
4670103e CZ |
129 | /* By default relaxation is disabled. */ |
130 | static int relaxation_state = 0; | |
131 | ||
886a2506 | 132 | extern int arc_get_mach (char *); |
0d2bcfaf | 133 | |
4670103e | 134 | /* Forward declarations. */ |
886a2506 NC |
135 | static void arc_lcomm (int); |
136 | static void arc_option (int); | |
137 | static void arc_extra_reloc (int); | |
252b5132 | 138 | |
4670103e | 139 | |
886a2506 | 140 | const pseudo_typeS md_pseudo_table[] = |
6f4b1afc CM |
141 | { |
142 | /* Make sure that .word is 32 bits. */ | |
143 | { "word", cons, 4 }, | |
886a2506 | 144 | |
6f4b1afc CM |
145 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
146 | { "lcomm", arc_lcomm, 0 }, | |
147 | { "lcommon", arc_lcomm, 0 }, | |
148 | { "cpu", arc_option, 0 }, | |
252b5132 | 149 | |
6f4b1afc CM |
150 | { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD }, |
151 | { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL }, | |
886a2506 | 152 | |
6f4b1afc CM |
153 | { NULL, NULL, 0 } |
154 | }; | |
252b5132 | 155 | |
252b5132 | 156 | const char *md_shortopts = ""; |
ea1562b3 NC |
157 | |
158 | enum options | |
6f4b1afc CM |
159 | { |
160 | OPTION_EB = OPTION_MD_BASE, | |
161 | OPTION_EL, | |
162 | ||
163 | OPTION_ARC600, | |
164 | OPTION_ARC601, | |
165 | OPTION_ARC700, | |
166 | OPTION_ARCEM, | |
167 | OPTION_ARCHS, | |
168 | ||
169 | OPTION_MCPU, | |
170 | OPTION_CD, | |
4670103e | 171 | OPTION_RELAX, |
6f4b1afc CM |
172 | |
173 | /* The following options are deprecated and provided here only for | |
174 | compatibility reasons. */ | |
175 | OPTION_USER_MODE, | |
176 | OPTION_LD_EXT_MASK, | |
177 | OPTION_SWAP, | |
178 | OPTION_NORM, | |
179 | OPTION_BARREL_SHIFT, | |
180 | OPTION_MIN_MAX, | |
181 | OPTION_NO_MPY, | |
182 | OPTION_EA, | |
183 | OPTION_MUL64, | |
184 | OPTION_SIMD, | |
185 | OPTION_SPFP, | |
186 | OPTION_DPFP, | |
187 | OPTION_XMAC_D16, | |
188 | OPTION_XMAC_24, | |
189 | OPTION_DSP_PACKA, | |
190 | OPTION_CRC, | |
191 | OPTION_DVBF, | |
192 | OPTION_TELEPHONY, | |
193 | OPTION_XYMEMORY, | |
194 | OPTION_LOCK, | |
195 | OPTION_SWAPE, | |
196 | OPTION_RTSC, | |
197 | OPTION_FPUDA | |
198 | }; | |
ea1562b3 NC |
199 | |
200 | struct option md_longopts[] = | |
6f4b1afc CM |
201 | { |
202 | { "EB", no_argument, NULL, OPTION_EB }, | |
203 | { "EL", no_argument, NULL, OPTION_EL }, | |
204 | { "mcpu", required_argument, NULL, OPTION_MCPU }, | |
205 | { "mA6", no_argument, NULL, OPTION_ARC600 }, | |
24b368f8 CZ |
206 | { "mARC600", no_argument, NULL, OPTION_ARC600 }, |
207 | { "mARC601", no_argument, NULL, OPTION_ARC601 }, | |
208 | { "mARC700", no_argument, NULL, OPTION_ARC700 }, | |
6f4b1afc CM |
209 | { "mA7", no_argument, NULL, OPTION_ARC700 }, |
210 | { "mEM", no_argument, NULL, OPTION_ARCEM }, | |
211 | { "mHS", no_argument, NULL, OPTION_ARCHS }, | |
212 | { "mcode-density", no_argument, NULL, OPTION_CD }, | |
4670103e | 213 | { "mrelax", no_argument, NULL, OPTION_RELAX }, |
6f4b1afc CM |
214 | |
215 | /* The following options are deprecated and provided here only for | |
216 | compatibility reasons. */ | |
217 | { "mav2em", no_argument, NULL, OPTION_ARCEM }, | |
218 | { "mav2hs", no_argument, NULL, OPTION_ARCHS }, | |
219 | { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE }, | |
220 | { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK }, | |
221 | { "mswap", no_argument, NULL, OPTION_SWAP }, | |
222 | { "mnorm", no_argument, NULL, OPTION_NORM }, | |
223 | { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, | |
224 | { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, | |
225 | { "mmin-max", no_argument, NULL, OPTION_MIN_MAX }, | |
226 | { "mmin_max", no_argument, NULL, OPTION_MIN_MAX }, | |
227 | { "mno-mpy", no_argument, NULL, OPTION_NO_MPY }, | |
228 | { "mea", no_argument, NULL, OPTION_EA }, | |
229 | { "mEA", no_argument, NULL, OPTION_EA }, | |
230 | { "mmul64", no_argument, NULL, OPTION_MUL64 }, | |
231 | { "msimd", no_argument, NULL, OPTION_SIMD}, | |
232 | { "mspfp", no_argument, NULL, OPTION_SPFP}, | |
233 | { "mspfp-compact", no_argument, NULL, OPTION_SPFP}, | |
234 | { "mspfp_compact", no_argument, NULL, OPTION_SPFP}, | |
235 | { "mspfp-fast", no_argument, NULL, OPTION_SPFP}, | |
236 | { "mspfp_fast", no_argument, NULL, OPTION_SPFP}, | |
237 | { "mdpfp", no_argument, NULL, OPTION_DPFP}, | |
238 | { "mdpfp-compact", no_argument, NULL, OPTION_DPFP}, | |
239 | { "mdpfp_compact", no_argument, NULL, OPTION_DPFP}, | |
240 | { "mdpfp-fast", no_argument, NULL, OPTION_DPFP}, | |
241 | { "mdpfp_fast", no_argument, NULL, OPTION_DPFP}, | |
242 | { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16}, | |
243 | { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16}, | |
244 | { "mmac-24", no_argument, NULL, OPTION_XMAC_24}, | |
245 | { "mmac_24", no_argument, NULL, OPTION_XMAC_24}, | |
246 | { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA}, | |
247 | { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA}, | |
248 | { "mcrc", no_argument, NULL, OPTION_CRC}, | |
249 | { "mdvbf", no_argument, NULL, OPTION_DVBF}, | |
250 | { "mtelephony", no_argument, NULL, OPTION_TELEPHONY}, | |
251 | { "mxy", no_argument, NULL, OPTION_XYMEMORY}, | |
252 | { "mlock", no_argument, NULL, OPTION_LOCK}, | |
253 | { "mswape", no_argument, NULL, OPTION_SWAPE}, | |
254 | { "mrtsc", no_argument, NULL, OPTION_RTSC}, | |
255 | { "mfpuda", no_argument, NULL, OPTION_FPUDA}, | |
256 | ||
257 | { NULL, no_argument, NULL, 0 } | |
258 | }; | |
252b5132 | 259 | |
886a2506 | 260 | size_t md_longopts_size = sizeof (md_longopts); |
0d2bcfaf | 261 | |
886a2506 | 262 | /* Local data and data types. */ |
252b5132 | 263 | |
886a2506 NC |
264 | /* Used since new relocation types are introduced in this |
265 | file (DUMMY_RELOC_LITUSE_*). */ | |
266 | typedef int extended_bfd_reloc_code_real_type; | |
252b5132 | 267 | |
886a2506 | 268 | struct arc_fixup |
252b5132 | 269 | { |
886a2506 | 270 | expressionS exp; |
252b5132 | 271 | |
886a2506 | 272 | extended_bfd_reloc_code_real_type reloc; |
252b5132 | 273 | |
886a2506 NC |
274 | /* index into arc_operands. */ |
275 | unsigned int opindex; | |
252b5132 | 276 | |
886a2506 NC |
277 | /* PC-relative, used by internals fixups. */ |
278 | unsigned char pcrel; | |
252b5132 | 279 | |
886a2506 NC |
280 | /* TRUE if this fixup is for LIMM operand. */ |
281 | bfd_boolean islong; | |
282 | }; | |
252b5132 | 283 | |
886a2506 NC |
284 | struct arc_insn |
285 | { | |
286 | unsigned int insn; | |
287 | int nfixups; | |
288 | struct arc_fixup fixups[MAX_INSN_FIXUPS]; | |
289 | long limm; | |
290 | bfd_boolean short_insn; /* Boolean value: TRUE if current insn is | |
291 | short. */ | |
292 | bfd_boolean has_limm; /* Boolean value: TRUE if limm field is | |
293 | valid. */ | |
4670103e CZ |
294 | bfd_boolean relax; /* Boolean value: TRUE if needs |
295 | relaxation. */ | |
886a2506 | 296 | }; |
ea1562b3 | 297 | |
886a2506 NC |
298 | /* Structure to hold any last two instructions. */ |
299 | static struct arc_last_insn | |
252b5132 | 300 | { |
886a2506 NC |
301 | /* Saved instruction opcode. */ |
302 | const struct arc_opcode *opcode; | |
252b5132 | 303 | |
886a2506 NC |
304 | /* Boolean value: TRUE if current insn is short. */ |
305 | bfd_boolean has_limm; | |
252b5132 | 306 | |
886a2506 NC |
307 | /* Boolean value: TRUE if current insn has delay slot. */ |
308 | bfd_boolean has_delay_slot; | |
309 | } arc_last_insns[2]; | |
252b5132 | 310 | |
da5be039 AB |
311 | /* Structure to hold an entry in ARC_OPCODE_HASH. */ |
312 | struct arc_opcode_hash_entry | |
313 | { | |
314 | /* The number of pointers in the OPCODE list. */ | |
315 | size_t count; | |
316 | ||
317 | /* Points to a list of opcode pointers. */ | |
318 | const struct arc_opcode **opcode; | |
319 | }; | |
320 | ||
1328504b AB |
321 | /* Structure used for iterating through an arc_opcode_hash_entry. */ |
322 | struct arc_opcode_hash_entry_iterator | |
323 | { | |
324 | /* Index into the OPCODE element of the arc_opcode_hash_entry. */ | |
325 | size_t index; | |
326 | ||
327 | /* The specific ARC_OPCODE from the ARC_OPCODES table that was last | |
328 | returned by this iterator. */ | |
329 | const struct arc_opcode *opcode; | |
330 | }; | |
331 | ||
4670103e CZ |
332 | /* Forward declaration. */ |
333 | static void assemble_insn | |
334 | (const struct arc_opcode *, const expressionS *, int, | |
335 | const struct arc_flags *, int, struct arc_insn *); | |
336 | ||
886a2506 | 337 | /* The cpu for which we are generating code. */ |
24740d83 AB |
338 | static unsigned arc_target; |
339 | static const char *arc_target_name; | |
340 | static unsigned arc_features; | |
252b5132 | 341 | |
886a2506 | 342 | /* The default architecture. */ |
24740d83 | 343 | static int arc_mach_type; |
252b5132 | 344 | |
886a2506 NC |
345 | /* Non-zero if the cpu type has been explicitly specified. */ |
346 | static int mach_type_specified_p = 0; | |
0d2bcfaf | 347 | |
886a2506 NC |
348 | /* The hash table of instruction opcodes. */ |
349 | static struct hash_control *arc_opcode_hash; | |
0d2bcfaf | 350 | |
886a2506 NC |
351 | /* The hash table of register symbols. */ |
352 | static struct hash_control *arc_reg_hash; | |
252b5132 | 353 | |
886a2506 NC |
354 | /* A table of CPU names and opcode sets. */ |
355 | static const struct cpu_type | |
356 | { | |
357 | const char *name; | |
358 | unsigned flags; | |
359 | int mach; | |
360 | unsigned eflags; | |
361 | unsigned features; | |
252b5132 | 362 | } |
886a2506 | 363 | cpu_types[] = |
252b5132 | 364 | { |
886a2506 NC |
365 | { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, |
366 | E_ARC_MACH_ARC600, 0x00}, | |
367 | { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, | |
368 | E_ARC_MACH_ARC700, 0x00}, | |
8699fc3e AB |
369 | { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400, |
370 | E_ARC_MACH_NPS400, 0x00}, | |
886a2506 | 371 | { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, |
7e458899 | 372 | EF_ARC_CPU_ARCV2EM, ARC_CD}, |
886a2506 NC |
373 | { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, |
374 | EF_ARC_CPU_ARCV2HS, ARC_CD}, | |
886a2506 NC |
375 | { 0, 0, 0, 0, 0 } |
376 | }; | |
252b5132 | 377 | |
886a2506 NC |
378 | /* Used by the arc_reloc_op table. Order is important. */ |
379 | #define O_gotoff O_md1 /* @gotoff relocation. */ | |
380 | #define O_gotpc O_md2 /* @gotpc relocation. */ | |
381 | #define O_plt O_md3 /* @plt relocation. */ | |
382 | #define O_sda O_md4 /* @sda relocation. */ | |
383 | #define O_pcl O_md5 /* @pcl relocation. */ | |
384 | #define O_tlsgd O_md6 /* @tlsgd relocation. */ | |
385 | #define O_tlsie O_md7 /* @tlsie relocation. */ | |
386 | #define O_tpoff9 O_md8 /* @tpoff9 relocation. */ | |
387 | #define O_tpoff O_md9 /* @tpoff relocation. */ | |
388 | #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */ | |
389 | #define O_dtpoff O_md11 /* @dtpoff relocation. */ | |
390 | #define O_last O_dtpoff | |
391 | ||
392 | /* Used to define a bracket as operand in tokens. */ | |
393 | #define O_bracket O_md32 | |
394 | ||
395 | /* Dummy relocation, to be sorted out. */ | |
396 | #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1) | |
397 | ||
398 | #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last) | |
399 | ||
400 | /* A table to map the spelling of a relocation operand into an appropriate | |
401 | bfd_reloc_code_real_type type. The table is assumed to be ordered such | |
402 | that op-O_literal indexes into it. */ | |
403 | #define ARC_RELOC_TABLE(op) \ | |
404 | (&arc_reloc_op[ ((!USER_RELOC_P (op)) \ | |
405 | ? (abort (), 0) \ | |
406 | : (int) (op) - (int) O_gotoff) ]) | |
407 | ||
408 | #define DEF(NAME, RELOC, REQ) \ | |
409 | { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ} | |
410 | ||
411 | static const struct arc_reloc_op_tag | |
412 | { | |
413 | /* String to lookup. */ | |
414 | const char *name; | |
415 | /* Size of the string. */ | |
416 | size_t length; | |
417 | /* Which operator to use. */ | |
418 | operatorT op; | |
419 | extended_bfd_reloc_code_real_type reloc; | |
420 | /* Allows complex relocation expression like identifier@reloc + | |
421 | const. */ | |
422 | unsigned int complex_expr : 1; | |
423 | } | |
424 | arc_reloc_op[] = | |
6f4b1afc CM |
425 | { |
426 | DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1), | |
427 | DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0), | |
428 | DEF (plt, BFD_RELOC_ARC_PLT32, 0), | |
429 | DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1), | |
430 | DEF (pcl, BFD_RELOC_ARC_PC32, 1), | |
431 | DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0), | |
432 | DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0), | |
433 | DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0), | |
b125bd17 | 434 | DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1), |
6f4b1afc CM |
435 | DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0), |
436 | DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0), | |
437 | }; | |
252b5132 | 438 | |
886a2506 NC |
439 | static const int arc_num_reloc_op |
440 | = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op); | |
441 | ||
4670103e CZ |
442 | /* Structure for relaxable instruction that have to be swapped with a |
443 | smaller alternative instruction. */ | |
444 | struct arc_relaxable_ins | |
445 | { | |
446 | /* Mnemonic that should be checked. */ | |
447 | const char *mnemonic_r; | |
448 | ||
449 | /* Operands that should be checked. | |
450 | Indexes of operands from operand array. */ | |
451 | enum rlx_operand_type operands[6]; | |
452 | ||
453 | /* Flags that should be checked. */ | |
454 | unsigned flag_classes[5]; | |
455 | ||
456 | /* Mnemonic (smaller) alternative to be used later for relaxation. */ | |
457 | const char *mnemonic_alt; | |
458 | ||
459 | /* Index of operand that generic relaxation has to check. */ | |
460 | unsigned opcheckidx; | |
461 | ||
462 | /* Base subtype index used. */ | |
463 | enum arc_rlx_types subtype; | |
464 | }; | |
465 | ||
466 | #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \ | |
467 | { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \ | |
468 | (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \ | |
469 | (SIZE), \ | |
470 | (NEXT) } \ | |
471 | ||
472 | #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \ | |
473 | { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \ | |
474 | (ISSIGNED) ? -(0x7FFFFFFF) : 0, \ | |
475 | (SIZE), \ | |
476 | (NEXT) } \ | |
477 | ||
478 | ||
479 | /* ARC relaxation table. */ | |
480 | const relax_typeS md_relax_table[] = | |
481 | { | |
482 | /* Fake entry. */ | |
483 | {0, 0, 0, 0}, | |
484 | ||
485 | /* BL_S s13 -> | |
486 | BL s25. */ | |
487 | RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL), | |
488 | RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE), | |
489 | ||
490 | /* B_S s10 -> | |
491 | B s25. */ | |
492 | RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B), | |
493 | RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE), | |
494 | ||
495 | /* ADD_S c,b, u3 -> | |
496 | ADD<.f> a,b,u6 -> | |
497 | ADD<.f> a,b,limm. */ | |
498 | RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6), | |
499 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM), | |
500 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
501 | ||
502 | /* LD_S a, [b, u7] -> | |
503 | LD<zz><.x><.aa><.di> a, [b, s9] -> | |
504 | LD<zz><.x><.aa><.di> a, [b, limm] */ | |
505 | RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9), | |
506 | RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM), | |
507 | RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE), | |
508 | ||
509 | /* MOV_S b, u8 -> | |
510 | MOV<.f> b, s12 -> | |
511 | MOV<.f> b, limm. */ | |
512 | RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12), | |
513 | RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM), | |
514 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
515 | ||
516 | /* SUB_S c, b, u3 -> | |
517 | SUB<.f> a, b, u6 -> | |
518 | SUB<.f> a, b, limm. */ | |
519 | RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6), | |
520 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM), | |
521 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
522 | ||
523 | /* MPY<.f> a, b, u6 -> | |
524 | MPY<.f> a, b, limm. */ | |
525 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM), | |
526 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
527 | ||
528 | /* MOV<.f><.cc> b, u6 -> | |
529 | MOV<.f><.cc> b, limm. */ | |
530 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM), | |
531 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
532 | ||
533 | /* ADD<.f><.cc> b, b, u6 -> | |
534 | ADD<.f><.cc> b, b, limm. */ | |
535 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM), | |
536 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
537 | }; | |
538 | ||
539 | /* Order of this table's entries matters! */ | |
540 | const struct arc_relaxable_ins arc_relaxable_insns[] = | |
541 | { | |
542 | { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S }, | |
543 | { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S }, | |
544 | { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add", | |
545 | 2, ARC_RLX_ADD_RRU6}, | |
546 | { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2, | |
547 | ARC_RLX_ADD_U3 }, | |
548 | { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2, | |
549 | ARC_RLX_ADD_U6 }, | |
550 | { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET }, | |
551 | { 0 }, "ld_s", 3, ARC_RLX_LD_U7 }, | |
552 | { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET }, | |
553 | { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 }, | |
554 | { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 }, | |
555 | { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 }, | |
556 | { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 }, | |
557 | { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2, | |
558 | ARC_RLX_SUB_U3 }, | |
559 | { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2, | |
560 | ARC_RLX_SUB_U6 }, | |
561 | { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2, | |
562 | ARC_RLX_MPY_U6 }, | |
563 | }; | |
564 | ||
565 | const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns); | |
566 | ||
886a2506 NC |
567 | /* Flags to set in the elf header. */ |
568 | static flagword arc_eflag = 0x00; | |
569 | ||
570 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ | |
571 | symbolS * GOT_symbol = 0; | |
572 | ||
573 | /* Set to TRUE when we assemble instructions. */ | |
574 | static bfd_boolean assembling_insn = FALSE; | |
575 | ||
886a2506 NC |
576 | /* Functions implementation. */ |
577 | ||
b9b47ab7 AB |
578 | /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all |
579 | ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there | |
580 | are no matching entries in ARC_OPCODE_HASH. */ | |
da5be039 | 581 | |
b9b47ab7 | 582 | static const struct arc_opcode_hash_entry * |
da5be039 AB |
583 | arc_find_opcode (const char *name) |
584 | { | |
585 | const struct arc_opcode_hash_entry *entry; | |
da5be039 AB |
586 | |
587 | entry = hash_find (arc_opcode_hash, name); | |
b9b47ab7 | 588 | return entry; |
da5be039 AB |
589 | } |
590 | ||
1328504b AB |
591 | /* Initialise the iterator ITER. */ |
592 | ||
593 | static void | |
594 | arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter) | |
595 | { | |
596 | iter->index = 0; | |
597 | iter->opcode = NULL; | |
598 | } | |
599 | ||
600 | /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between | |
601 | calls to this function. Return NULL when all ARC_OPCODE entries have | |
602 | been returned. */ | |
603 | ||
604 | static const struct arc_opcode * | |
605 | arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry, | |
606 | struct arc_opcode_hash_entry_iterator *iter) | |
607 | { | |
608 | if (iter->opcode == NULL && iter->index == 0) | |
609 | { | |
610 | gas_assert (entry->count > 0); | |
611 | iter->opcode = entry->opcode[iter->index]; | |
612 | } | |
613 | else if (iter->opcode != NULL) | |
614 | { | |
615 | const char *old_name = iter->opcode->name; | |
616 | ||
617 | iter->opcode++; | |
618 | if ((iter->opcode - arc_opcodes >= (int) arc_num_opcodes) | |
619 | || (strcmp (old_name, iter->opcode->name) != 0)) | |
620 | { | |
621 | iter->index++; | |
622 | if (iter->index == entry->count) | |
623 | iter->opcode = NULL; | |
624 | else | |
625 | iter->opcode = entry->opcode[iter->index]; | |
626 | } | |
627 | } | |
628 | ||
629 | return iter->opcode; | |
630 | } | |
631 | ||
886a2506 NC |
632 | /* Like md_number_to_chars but used for limms. The 4-byte limm value, |
633 | is encoded as 'middle-endian' for a little-endian target. FIXME! | |
634 | this function is used for regular 4 byte instructions as well. */ | |
635 | ||
636 | static void | |
6f4b1afc | 637 | md_number_to_chars_midend (char *buf, valueT val, int n) |
886a2506 NC |
638 | { |
639 | if (n == 4) | |
640 | { | |
641 | md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2); | |
642 | md_number_to_chars (buf + 2, (val & 0xffff), 2); | |
252b5132 RH |
643 | } |
644 | else | |
886a2506 NC |
645 | { |
646 | md_number_to_chars (buf, val, n); | |
647 | } | |
252b5132 RH |
648 | } |
649 | ||
24740d83 AB |
650 | /* Select an appropriate entry from CPU_TYPES based on ARG and initialise |
651 | the relevant static global variables. */ | |
652 | ||
653 | static void | |
654 | arc_select_cpu (const char *arg) | |
655 | { | |
a9522a21 | 656 | int cpu_flags = 0; |
24740d83 AB |
657 | int i; |
658 | ||
659 | for (i = 0; cpu_types[i].name; ++i) | |
660 | { | |
661 | if (!strcasecmp (cpu_types[i].name, arg)) | |
662 | { | |
663 | arc_target = cpu_types[i].flags; | |
664 | arc_target_name = cpu_types[i].name; | |
665 | arc_features = cpu_types[i].features; | |
666 | arc_mach_type = cpu_types[i].mach; | |
667 | cpu_flags = cpu_types[i].eflags; | |
668 | break; | |
669 | } | |
670 | } | |
671 | ||
672 | if (!cpu_types[i].name) | |
673 | as_fatal (_("unknown architecture: %s\n"), arg); | |
a9522a21 AB |
674 | gas_assert (cpu_flags != 0); |
675 | arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags; | |
24740d83 AB |
676 | } |
677 | ||
886a2506 NC |
678 | /* Here ends all the ARCompact extension instruction assembling |
679 | stuff. */ | |
252b5132 | 680 | |
886a2506 NC |
681 | static void |
682 | arc_extra_reloc (int r_type) | |
ea1562b3 | 683 | { |
886a2506 NC |
684 | char *sym_name, c; |
685 | symbolS *sym, *lab = NULL; | |
686 | ||
687 | if (*input_line_pointer == '@') | |
688 | input_line_pointer++; | |
689 | c = get_symbol_name (&sym_name); | |
690 | sym = symbol_find_or_make (sym_name); | |
691 | restore_line_pointer (c); | |
692 | if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD) | |
693 | { | |
694 | ++input_line_pointer; | |
695 | char *lab_name; | |
696 | c = get_symbol_name (&lab_name); | |
697 | lab = symbol_find_or_make (lab_name); | |
698 | restore_line_pointer (c); | |
699 | } | |
841fdfcd CZ |
700 | |
701 | /* These relocations exist as a mechanism for the compiler to tell the | |
702 | linker how to patch the code if the tls model is optimised. However, | |
703 | the relocation itself does not require any space within the assembler | |
704 | fragment, and so we pass a size of 0. | |
705 | ||
706 | The lines that generate these relocations look like this: | |
707 | ||
708 | .tls_gd_ld @.tdata`bl __tls_get_addr@plt | |
709 | ||
710 | The '.tls_gd_ld @.tdata' is processed first and generates the | |
711 | additional relocation, while the 'bl __tls_get_addr@plt' is processed | |
712 | second and generates the additional branch. | |
713 | ||
714 | It is possible that the additional relocation generated by the | |
715 | '.tls_gd_ld @.tdata' will be attached at the very end of one fragment, | |
716 | while the 'bl __tls_get_addr@plt' will be generated as the first thing | |
717 | in the next fragment. This will be fine; both relocations will still | |
718 | appear to be at the same address in the generated object file. | |
719 | However, this only works as the additional relocation is generated | |
720 | with size of 0 bytes. */ | |
886a2506 NC |
721 | fixS *fixP |
722 | = fix_new (frag_now, /* Which frag? */ | |
723 | frag_now_fix (), /* Where in that frag? */ | |
841fdfcd | 724 | 0, /* size: 1, 2, or 4 usually. */ |
886a2506 NC |
725 | sym, /* X_add_symbol. */ |
726 | 0, /* X_add_number. */ | |
727 | FALSE, /* TRUE if PC-relative relocation. */ | |
728 | r_type /* Relocation type. */); | |
729 | fixP->fx_subsy = lab; | |
730 | } | |
252b5132 | 731 | |
886a2506 NC |
732 | static symbolS * |
733 | arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED, | |
734 | symbolS *symbolP, addressT size) | |
735 | { | |
736 | addressT align = 0; | |
737 | SKIP_WHITESPACE (); | |
252b5132 | 738 | |
886a2506 NC |
739 | if (*input_line_pointer == ',') |
740 | { | |
741 | align = parse_align (1); | |
252b5132 | 742 | |
886a2506 NC |
743 | if (align == (addressT) -1) |
744 | return NULL; | |
745 | } | |
746 | else | |
747 | { | |
748 | if (size >= 8) | |
749 | align = 3; | |
750 | else if (size >= 4) | |
751 | align = 2; | |
752 | else if (size >= 2) | |
753 | align = 1; | |
754 | else | |
755 | align = 0; | |
756 | } | |
252b5132 | 757 | |
886a2506 NC |
758 | bss_alloc (symbolP, size, align); |
759 | S_CLEAR_EXTERNAL (symbolP); | |
ea1562b3 | 760 | |
886a2506 NC |
761 | return symbolP; |
762 | } | |
ea1562b3 | 763 | |
886a2506 NC |
764 | static void |
765 | arc_lcomm (int ignore) | |
766 | { | |
767 | symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal); | |
ea1562b3 | 768 | |
886a2506 NC |
769 | if (symbolP) |
770 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; | |
771 | } | |
ea1562b3 | 772 | |
886a2506 | 773 | /* Select the cpu we're assembling for. */ |
ea1562b3 | 774 | |
886a2506 NC |
775 | static void |
776 | arc_option (int ignore ATTRIBUTE_UNUSED) | |
252b5132 | 777 | { |
886a2506 NC |
778 | int mach = -1; |
779 | char c; | |
780 | char *cpu; | |
252b5132 | 781 | |
886a2506 NC |
782 | c = get_symbol_name (&cpu); |
783 | mach = arc_get_mach (cpu); | |
252b5132 | 784 | |
886a2506 NC |
785 | if (mach == -1) |
786 | goto bad_cpu; | |
787 | ||
788 | if (!mach_type_specified_p) | |
ea1562b3 | 789 | { |
24b368f8 CZ |
790 | if ((!strcmp ("ARC600", cpu)) |
791 | || (!strcmp ("ARC601", cpu)) | |
792 | || (!strcmp ("A6", cpu))) | |
793 | { | |
794 | md_parse_option (OPTION_MCPU, "arc600"); | |
795 | } | |
796 | else if ((!strcmp ("ARC700", cpu)) | |
797 | || (!strcmp ("A7", cpu))) | |
798 | { | |
799 | md_parse_option (OPTION_MCPU, "arc700"); | |
800 | } | |
801 | else if (!strcmp ("EM", cpu)) | |
802 | { | |
803 | md_parse_option (OPTION_MCPU, "arcem"); | |
804 | } | |
805 | else if (!strcmp ("HS", cpu)) | |
806 | { | |
807 | md_parse_option (OPTION_MCPU, "archs"); | |
808 | } | |
809 | else | |
e6ba1cba | 810 | as_fatal (_("could not find the architecture")); |
24b368f8 | 811 | |
886a2506 | 812 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach)) |
e6ba1cba | 813 | as_fatal (_("could not set architecture and machine")); |
ea1562b3 NC |
814 | } |
815 | else | |
886a2506 | 816 | if (arc_mach_type != mach) |
e6ba1cba | 817 | as_warn (_("Command-line value overrides \".cpu\" directive")); |
886a2506 | 818 | |
24b368f8 | 819 | restore_line_pointer (c); |
886a2506 | 820 | demand_empty_rest_of_line (); |
886a2506 NC |
821 | return; |
822 | ||
823 | bad_cpu: | |
24b368f8 | 824 | restore_line_pointer (c); |
e6ba1cba | 825 | as_bad (_("invalid identifier for \".cpu\"")); |
886a2506 | 826 | ignore_rest_of_line (); |
ea1562b3 | 827 | } |
252b5132 | 828 | |
886a2506 NC |
829 | /* Smartly print an expression. */ |
830 | ||
ea1562b3 | 831 | static void |
886a2506 | 832 | debug_exp (expressionS *t) |
ea1562b3 | 833 | { |
886a2506 NC |
834 | const char *name ATTRIBUTE_UNUSED; |
835 | const char *namemd ATTRIBUTE_UNUSED; | |
252b5132 | 836 | |
886a2506 | 837 | pr_debug ("debug_exp: "); |
252b5132 | 838 | |
886a2506 | 839 | switch (t->X_op) |
252b5132 | 840 | { |
886a2506 NC |
841 | default: name = "unknown"; break; |
842 | case O_illegal: name = "O_illegal"; break; | |
843 | case O_absent: name = "O_absent"; break; | |
844 | case O_constant: name = "O_constant"; break; | |
845 | case O_symbol: name = "O_symbol"; break; | |
846 | case O_symbol_rva: name = "O_symbol_rva"; break; | |
847 | case O_register: name = "O_register"; break; | |
848 | case O_big: name = "O_big"; break; | |
849 | case O_uminus: name = "O_uminus"; break; | |
850 | case O_bit_not: name = "O_bit_not"; break; | |
851 | case O_logical_not: name = "O_logical_not"; break; | |
852 | case O_multiply: name = "O_multiply"; break; | |
853 | case O_divide: name = "O_divide"; break; | |
854 | case O_modulus: name = "O_modulus"; break; | |
855 | case O_left_shift: name = "O_left_shift"; break; | |
856 | case O_right_shift: name = "O_right_shift"; break; | |
857 | case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break; | |
858 | case O_bit_or_not: name = "O_bit_or_not"; break; | |
859 | case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break; | |
860 | case O_bit_and: name = "O_bit_and"; break; | |
861 | case O_add: name = "O_add"; break; | |
862 | case O_subtract: name = "O_subtract"; break; | |
863 | case O_eq: name = "O_eq"; break; | |
864 | case O_ne: name = "O_ne"; break; | |
865 | case O_lt: name = "O_lt"; break; | |
866 | case O_le: name = "O_le"; break; | |
867 | case O_ge: name = "O_ge"; break; | |
868 | case O_gt: name = "O_gt"; break; | |
869 | case O_logical_and: name = "O_logical_and"; break; | |
870 | case O_logical_or: name = "O_logical_or"; break; | |
871 | case O_index: name = "O_index"; break; | |
872 | case O_bracket: name = "O_bracket"; break; | |
ea1562b3 | 873 | } |
252b5132 | 874 | |
886a2506 | 875 | switch (t->X_md) |
ea1562b3 | 876 | { |
886a2506 NC |
877 | default: namemd = "unknown"; break; |
878 | case O_gotoff: namemd = "O_gotoff"; break; | |
879 | case O_gotpc: namemd = "O_gotpc"; break; | |
880 | case O_plt: namemd = "O_plt"; break; | |
881 | case O_sda: namemd = "O_sda"; break; | |
882 | case O_pcl: namemd = "O_pcl"; break; | |
883 | case O_tlsgd: namemd = "O_tlsgd"; break; | |
884 | case O_tlsie: namemd = "O_tlsie"; break; | |
885 | case O_tpoff9: namemd = "O_tpoff9"; break; | |
886 | case O_tpoff: namemd = "O_tpoff"; break; | |
887 | case O_dtpoff9: namemd = "O_dtpoff9"; break; | |
888 | case O_dtpoff: namemd = "O_dtpoff"; break; | |
ea1562b3 | 889 | } |
252b5132 | 890 | |
886a2506 NC |
891 | pr_debug ("%s (%s, %s, %d, %s)", name, |
892 | (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--", | |
893 | (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--", | |
894 | (int) t->X_add_number, | |
895 | (t->X_md) ? namemd : "--"); | |
896 | pr_debug ("\n"); | |
897 | fflush (stderr); | |
898 | } | |
252b5132 | 899 | |
886a2506 NC |
900 | /* Parse the arguments to an opcode. */ |
901 | ||
902 | static int | |
903 | tokenize_arguments (char *str, | |
904 | expressionS *tok, | |
905 | int ntok) | |
906 | { | |
907 | char *old_input_line_pointer; | |
908 | bfd_boolean saw_comma = FALSE; | |
909 | bfd_boolean saw_arg = FALSE; | |
910 | int brk_lvl = 0; | |
911 | int num_args = 0; | |
886a2506 NC |
912 | int i; |
913 | size_t len; | |
914 | const struct arc_reloc_op_tag *r; | |
915 | expressionS tmpE; | |
6f4b1afc | 916 | char *reloc_name, c; |
886a2506 NC |
917 | |
918 | memset (tok, 0, sizeof (*tok) * ntok); | |
919 | ||
920 | /* Save and restore input_line_pointer around this function. */ | |
921 | old_input_line_pointer = input_line_pointer; | |
922 | input_line_pointer = str; | |
ea1562b3 | 923 | |
886a2506 | 924 | while (*input_line_pointer) |
ea1562b3 NC |
925 | { |
926 | SKIP_WHITESPACE (); | |
886a2506 | 927 | switch (*input_line_pointer) |
252b5132 | 928 | { |
886a2506 NC |
929 | case '\0': |
930 | goto fini; | |
931 | ||
932 | case ',': | |
933 | input_line_pointer++; | |
934 | if (saw_comma || !saw_arg) | |
935 | goto err; | |
936 | saw_comma = TRUE; | |
937 | break; | |
252b5132 | 938 | |
886a2506 NC |
939 | case '}': |
940 | case ']': | |
941 | ++input_line_pointer; | |
942 | --brk_lvl; | |
943 | if (!saw_arg) | |
944 | goto err; | |
945 | tok->X_op = O_bracket; | |
946 | ++tok; | |
947 | ++num_args; | |
948 | break; | |
ea1562b3 | 949 | |
886a2506 NC |
950 | case '{': |
951 | case '[': | |
952 | input_line_pointer++; | |
953 | if (brk_lvl) | |
954 | goto err; | |
955 | ++brk_lvl; | |
956 | tok->X_op = O_bracket; | |
957 | ++tok; | |
958 | ++num_args; | |
959 | break; | |
960 | ||
961 | case '@': | |
962 | /* We have labels, function names and relocations, all | |
963 | starting with @ symbol. Sort them out. */ | |
964 | if (saw_arg && !saw_comma) | |
965 | goto err; | |
966 | ||
967 | /* Parse @label. */ | |
968 | tok->X_op = O_symbol; | |
969 | tok->X_md = O_absent; | |
970 | expression (tok); | |
971 | if (*input_line_pointer != '@') | |
972 | goto normalsymbol; /* This is not a relocation. */ | |
973 | ||
6f4b1afc CM |
974 | relocationsym: |
975 | ||
886a2506 NC |
976 | /* A relocation opernad has the following form |
977 | @identifier@relocation_type. The identifier is already | |
978 | in tok! */ | |
979 | if (tok->X_op != O_symbol) | |
ea1562b3 | 980 | { |
886a2506 NC |
981 | as_bad (_("No valid label relocation operand")); |
982 | goto err; | |
252b5132 | 983 | } |
886a2506 NC |
984 | |
985 | /* Parse @relocation_type. */ | |
6f4b1afc CM |
986 | input_line_pointer++; |
987 | c = get_symbol_name (&reloc_name); | |
988 | len = input_line_pointer - reloc_name; | |
989 | if (len == 0) | |
252b5132 | 990 | { |
886a2506 NC |
991 | as_bad (_("No relocation operand")); |
992 | goto err; | |
252b5132 | 993 | } |
252b5132 | 994 | |
886a2506 NC |
995 | /* Go through known relocation and try to find a match. */ |
996 | r = &arc_reloc_op[0]; | |
997 | for (i = arc_num_reloc_op - 1; i >= 0; i--, r++) | |
6f4b1afc CM |
998 | if (len == r->length |
999 | && memcmp (reloc_name, r->name, len) == 0) | |
886a2506 | 1000 | break; |
886a2506 | 1001 | if (i < 0) |
252b5132 | 1002 | { |
6f4b1afc | 1003 | as_bad (_("Unknown relocation operand: @%s"), reloc_name); |
886a2506 NC |
1004 | goto err; |
1005 | } | |
1006 | ||
6f4b1afc CM |
1007 | *input_line_pointer = c; |
1008 | SKIP_WHITESPACE_AFTER_NAME (); | |
886a2506 NC |
1009 | /* Extra check for TLS: base. */ |
1010 | if (*input_line_pointer == '@') | |
1011 | { | |
1012 | symbolS *base; | |
1013 | if (tok->X_op_symbol != NULL | |
1014 | || tok->X_op != O_symbol) | |
252b5132 | 1015 | { |
6f4b1afc CM |
1016 | as_bad (_("Unable to parse TLS base: %s"), |
1017 | input_line_pointer); | |
886a2506 | 1018 | goto err; |
252b5132 | 1019 | } |
886a2506 NC |
1020 | input_line_pointer++; |
1021 | char *sym_name; | |
6f4b1afc | 1022 | c = get_symbol_name (&sym_name); |
886a2506 NC |
1023 | base = symbol_find_or_make (sym_name); |
1024 | tok->X_op = O_subtract; | |
1025 | tok->X_op_symbol = base; | |
1026 | restore_line_pointer (c); | |
6f4b1afc CM |
1027 | tmpE.X_add_number = 0; |
1028 | } | |
1029 | else if ((*input_line_pointer != '+') | |
1030 | && (*input_line_pointer != '-')) | |
1031 | { | |
1032 | tmpE.X_add_number = 0; | |
ea1562b3 | 1033 | } |
6f4b1afc CM |
1034 | else |
1035 | { | |
1036 | /* Parse the constant of a complex relocation expression | |
1037 | like @identifier@reloc +/- const. */ | |
1038 | if (! r->complex_expr) | |
1039 | { | |
1040 | as_bad (_("@%s is not a complex relocation."), r->name); | |
1041 | goto err; | |
1042 | } | |
1043 | expression (&tmpE); | |
1044 | if (tmpE.X_op != O_constant) | |
1045 | { | |
1046 | as_bad (_("Bad expression: @%s + %s."), | |
1047 | r->name, input_line_pointer); | |
1048 | goto err; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | tok->X_md = r->op; | |
1053 | tok->X_add_number = tmpE.X_add_number; | |
1e07b820 | 1054 | |
886a2506 | 1055 | debug_exp (tok); |
ea1562b3 | 1056 | |
886a2506 NC |
1057 | saw_comma = FALSE; |
1058 | saw_arg = TRUE; | |
1059 | tok++; | |
1060 | num_args++; | |
1061 | break; | |
252b5132 | 1062 | |
886a2506 NC |
1063 | case '%': |
1064 | /* Can be a register. */ | |
1065 | ++input_line_pointer; | |
1066 | /* Fall through. */ | |
1067 | default: | |
252b5132 | 1068 | |
886a2506 NC |
1069 | if (saw_arg && !saw_comma) |
1070 | goto err; | |
252b5132 | 1071 | |
886a2506 | 1072 | tok->X_op = O_absent; |
6f4b1afc | 1073 | tok->X_md = O_absent; |
886a2506 | 1074 | expression (tok); |
252b5132 | 1075 | |
6f4b1afc CM |
1076 | /* Legacy: There are cases when we have |
1077 | identifier@relocation_type, if it is the case parse the | |
1078 | relocation type as well. */ | |
1079 | if (*input_line_pointer == '@') | |
1080 | goto relocationsym; | |
1081 | ||
886a2506 NC |
1082 | normalsymbol: |
1083 | debug_exp (tok); | |
252b5132 | 1084 | |
886a2506 NC |
1085 | if (tok->X_op == O_illegal || tok->X_op == O_absent) |
1086 | goto err; | |
252b5132 | 1087 | |
886a2506 NC |
1088 | saw_comma = FALSE; |
1089 | saw_arg = TRUE; | |
1090 | tok++; | |
1091 | num_args++; | |
1092 | break; | |
1093 | } | |
ea1562b3 | 1094 | } |
252b5132 | 1095 | |
886a2506 NC |
1096 | fini: |
1097 | if (saw_comma || brk_lvl) | |
1098 | goto err; | |
1099 | input_line_pointer = old_input_line_pointer; | |
252b5132 | 1100 | |
886a2506 | 1101 | return num_args; |
252b5132 | 1102 | |
886a2506 NC |
1103 | err: |
1104 | if (brk_lvl) | |
1105 | as_bad (_("Brackets in operand field incorrect")); | |
1106 | else if (saw_comma) | |
1107 | as_bad (_("extra comma")); | |
1108 | else if (!saw_arg) | |
1109 | as_bad (_("missing argument")); | |
1110 | else | |
1111 | as_bad (_("missing comma or colon")); | |
1112 | input_line_pointer = old_input_line_pointer; | |
1113 | return -1; | |
252b5132 | 1114 | } |
ea1562b3 | 1115 | |
886a2506 NC |
1116 | /* Parse the flags to a structure. */ |
1117 | ||
1118 | static int | |
1119 | tokenize_flags (const char *str, | |
1120 | struct arc_flags flags[], | |
1121 | int nflg) | |
252b5132 | 1122 | { |
886a2506 NC |
1123 | char *old_input_line_pointer; |
1124 | bfd_boolean saw_flg = FALSE; | |
1125 | bfd_boolean saw_dot = FALSE; | |
1126 | int num_flags = 0; | |
1127 | size_t flgnamelen; | |
252b5132 | 1128 | |
886a2506 | 1129 | memset (flags, 0, sizeof (*flags) * nflg); |
0d2bcfaf | 1130 | |
886a2506 NC |
1131 | /* Save and restore input_line_pointer around this function. */ |
1132 | old_input_line_pointer = input_line_pointer; | |
1133 | input_line_pointer = (char *) str; | |
0d2bcfaf | 1134 | |
886a2506 NC |
1135 | while (*input_line_pointer) |
1136 | { | |
1137 | switch (*input_line_pointer) | |
1138 | { | |
1139 | case ' ': | |
1140 | case '\0': | |
1141 | goto fini; | |
1142 | ||
1143 | case '.': | |
1144 | input_line_pointer++; | |
1145 | if (saw_dot) | |
1146 | goto err; | |
1147 | saw_dot = TRUE; | |
1148 | saw_flg = FALSE; | |
1149 | break; | |
ea1562b3 | 1150 | |
886a2506 NC |
1151 | default: |
1152 | if (saw_flg && !saw_dot) | |
1153 | goto err; | |
0d2bcfaf | 1154 | |
886a2506 NC |
1155 | if (num_flags >= nflg) |
1156 | goto err; | |
0d2bcfaf | 1157 | |
692166c2 AB |
1158 | flgnamelen = strspn (input_line_pointer, |
1159 | "abcdefghijklmnopqrstuvwxyz0123456789"); | |
83cda17b | 1160 | if (flgnamelen > MAX_FLAG_NAME_LENGTH) |
886a2506 | 1161 | goto err; |
0d2bcfaf | 1162 | |
886a2506 | 1163 | memcpy (flags->name, input_line_pointer, flgnamelen); |
0d2bcfaf | 1164 | |
886a2506 NC |
1165 | input_line_pointer += flgnamelen; |
1166 | flags++; | |
1167 | saw_dot = FALSE; | |
1168 | saw_flg = TRUE; | |
1169 | num_flags++; | |
1170 | break; | |
1e07b820 | 1171 | } |
0d2bcfaf NC |
1172 | } |
1173 | ||
886a2506 NC |
1174 | fini: |
1175 | input_line_pointer = old_input_line_pointer; | |
1176 | return num_flags; | |
0d2bcfaf | 1177 | |
886a2506 NC |
1178 | err: |
1179 | if (saw_dot) | |
1180 | as_bad (_("extra dot")); | |
1181 | else if (!saw_flg) | |
1182 | as_bad (_("unrecognized flag")); | |
1183 | else | |
1184 | as_bad (_("failed to parse flags")); | |
1185 | input_line_pointer = old_input_line_pointer; | |
1186 | return -1; | |
1187 | } | |
0d2bcfaf | 1188 | |
4670103e | 1189 | /* Apply the fixups in order. */ |
0d2bcfaf | 1190 | |
4670103e CZ |
1191 | static void |
1192 | apply_fixups (struct arc_insn *insn, fragS *fragP, int fix) | |
886a2506 | 1193 | { |
4670103e | 1194 | int i; |
0d2bcfaf | 1195 | |
4670103e | 1196 | for (i = 0; i < insn->nfixups; i++) |
252b5132 | 1197 | { |
4670103e CZ |
1198 | struct arc_fixup *fixup = &insn->fixups[i]; |
1199 | int size, pcrel, offset = 0; | |
0d2bcfaf | 1200 | |
4670103e CZ |
1201 | /* FIXME! the reloc size is wrong in the BFD file. |
1202 | When it is fixed please delete me. */ | |
1203 | size = (insn->short_insn && !fixup->islong) ? 2 : 4; | |
0d2bcfaf | 1204 | |
4670103e CZ |
1205 | if (fixup->islong) |
1206 | offset = (insn->short_insn) ? 2 : 4; | |
252b5132 | 1207 | |
4670103e CZ |
1208 | /* Some fixups are only used internally, thus no howto. */ |
1209 | if ((int) fixup->reloc == 0) | |
1210 | as_fatal (_("Unhandled reloc type")); | |
886a2506 | 1211 | |
4670103e CZ |
1212 | if ((int) fixup->reloc < 0) |
1213 | { | |
1214 | /* FIXME! the reloc size is wrong in the BFD file. | |
1215 | When it is fixed please enable me. | |
1216 | size = (insn->short_insn && !fixup->islong) ? 2 : 4; */ | |
1217 | pcrel = fixup->pcrel; | |
1218 | } | |
1219 | else | |
1220 | { | |
1221 | reloc_howto_type *reloc_howto = | |
1222 | bfd_reloc_type_lookup (stdoutput, | |
1223 | (bfd_reloc_code_real_type) fixup->reloc); | |
1224 | gas_assert (reloc_howto); | |
0d2bcfaf | 1225 | |
4670103e CZ |
1226 | /* FIXME! the reloc size is wrong in the BFD file. |
1227 | When it is fixed please enable me. | |
1228 | size = bfd_get_reloc_size (reloc_howto); */ | |
1229 | pcrel = reloc_howto->pc_relative; | |
1230 | } | |
0d2bcfaf | 1231 | |
4670103e CZ |
1232 | pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \ |
1233 | offset %d + %d\n", | |
1234 | fragP->fr_file, fragP->fr_line, | |
1235 | (fixup->reloc < 0) ? "Internal" : | |
1236 | bfd_get_reloc_code_name (fixup->reloc), | |
1237 | pcrel ? "Y" : "N", | |
1238 | size, fix, offset); | |
1239 | fix_new_exp (fragP, fix + offset, | |
1240 | size, &fixup->exp, pcrel, fixup->reloc); | |
0d2bcfaf | 1241 | |
4670103e CZ |
1242 | /* Check for ZOLs, and update symbol info if any. */ |
1243 | if (LP_INSN (insn->insn)) | |
886a2506 | 1244 | { |
4670103e CZ |
1245 | gas_assert (fixup->exp.X_add_symbol); |
1246 | ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL); | |
886a2506 NC |
1247 | } |
1248 | } | |
252b5132 RH |
1249 | } |
1250 | ||
4670103e | 1251 | /* Actually output an instruction with its fixup. */ |
886a2506 | 1252 | |
4670103e CZ |
1253 | static void |
1254 | emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax) | |
252b5132 | 1255 | { |
4670103e | 1256 | char *f = where; |
252b5132 | 1257 | |
4670103e CZ |
1258 | pr_debug ("Emit insn : 0x%x\n", insn->insn); |
1259 | pr_debug ("\tShort : 0x%d\n", insn->short_insn); | |
1260 | pr_debug ("\tLong imm: 0x%lx\n", insn->limm); | |
0d2bcfaf | 1261 | |
4670103e CZ |
1262 | /* Write out the instruction. */ |
1263 | if (insn->short_insn) | |
0d2bcfaf | 1264 | { |
4670103e CZ |
1265 | if (insn->has_limm) |
1266 | { | |
1267 | if (!relax) | |
1268 | f = frag_more (6); | |
1269 | md_number_to_chars (f, insn->insn, 2); | |
1270 | md_number_to_chars_midend (f + 2, insn->limm, 4); | |
1271 | dwarf2_emit_insn (6); | |
1272 | } | |
1273 | else | |
1274 | { | |
1275 | if (!relax) | |
1276 | f = frag_more (2); | |
1277 | md_number_to_chars (f, insn->insn, 2); | |
1278 | dwarf2_emit_insn (2); | |
1279 | } | |
1280 | } | |
1281 | else | |
1282 | { | |
1283 | if (insn->has_limm) | |
1284 | { | |
1285 | if (!relax) | |
1286 | f = frag_more (8); | |
1287 | md_number_to_chars_midend (f, insn->insn, 4); | |
1288 | md_number_to_chars_midend (f + 4, insn->limm, 4); | |
1289 | dwarf2_emit_insn (8); | |
1290 | } | |
1291 | else | |
1292 | { | |
1293 | if (!relax) | |
1294 | f = frag_more (4); | |
1295 | md_number_to_chars_midend (f, insn->insn, 4); | |
1296 | dwarf2_emit_insn (4); | |
1297 | } | |
252b5132 | 1298 | } |
252b5132 | 1299 | |
4670103e CZ |
1300 | if (!relax) |
1301 | apply_fixups (insn, frag_now, (f - frag_now->fr_literal)); | |
1302 | } | |
252b5132 | 1303 | |
4670103e CZ |
1304 | static void |
1305 | emit_insn1 (struct arc_insn *insn) | |
1306 | { | |
1307 | /* How frag_var's args are currently configured: | |
1308 | - rs_machine_dependent, to dictate it's a relaxation frag. | |
1309 | - FRAG_MAX_GROWTH, maximum size of instruction | |
1310 | - 0, variable size that might grow...unused by generic relaxation. | |
1311 | - frag_now->fr_subtype, fr_subtype starting value, set previously. | |
1312 | - s, opand expression. | |
1313 | - 0, offset but it's unused. | |
1314 | - 0, opcode but it's unused. */ | |
1315 | symbolS *s = make_expr_symbol (&insn->fixups[0].exp); | |
1316 | frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel; | |
1317 | ||
1318 | if (frag_room () < FRAG_MAX_GROWTH) | |
1319 | { | |
1320 | /* Handle differently when frag literal memory is exhausted. | |
1321 | This is used because when there's not enough memory left in | |
1322 | the current frag, a new frag is created and the information | |
1323 | we put into frag_now->tc_frag_data is disregarded. */ | |
252b5132 | 1324 | |
4670103e CZ |
1325 | struct arc_relax_type relax_info_copy; |
1326 | relax_substateT subtype = frag_now->fr_subtype; | |
252b5132 | 1327 | |
4670103e CZ |
1328 | memcpy (&relax_info_copy, &frag_now->tc_frag_data, |
1329 | sizeof (struct arc_relax_type)); | |
0d2bcfaf | 1330 | |
4670103e CZ |
1331 | frag_wane (frag_now); |
1332 | frag_grow (FRAG_MAX_GROWTH); | |
0d2bcfaf | 1333 | |
4670103e CZ |
1334 | memcpy (&frag_now->tc_frag_data, &relax_info_copy, |
1335 | sizeof (struct arc_relax_type)); | |
252b5132 | 1336 | |
4670103e CZ |
1337 | frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0, |
1338 | subtype, s, 0, 0); | |
1339 | } | |
1340 | else | |
1341 | frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0, | |
1342 | frag_now->fr_subtype, s, 0, 0); | |
1343 | } | |
252b5132 | 1344 | |
4670103e CZ |
1345 | static void |
1346 | emit_insn (struct arc_insn *insn) | |
252b5132 | 1347 | { |
4670103e CZ |
1348 | if (insn->relax) |
1349 | emit_insn1 (insn); | |
252b5132 | 1350 | else |
4670103e | 1351 | emit_insn0 (insn, NULL, FALSE); |
252b5132 RH |
1352 | } |
1353 | ||
4670103e | 1354 | /* Check whether a symbol involves a register. */ |
252b5132 | 1355 | |
4670103e CZ |
1356 | static bfd_boolean |
1357 | contains_register (symbolS *sym) | |
252b5132 | 1358 | { |
4670103e CZ |
1359 | if (sym) |
1360 | { | |
1361 | expressionS *ex = symbol_get_value_expression (sym); | |
252b5132 | 1362 | |
4670103e CZ |
1363 | return ((O_register == ex->X_op) |
1364 | && !contains_register (ex->X_add_symbol) | |
1365 | && !contains_register (ex->X_op_symbol)); | |
1366 | } | |
1367 | ||
1368 | return FALSE; | |
252b5132 RH |
1369 | } |
1370 | ||
4670103e | 1371 | /* Returns the register number within a symbol. */ |
252b5132 | 1372 | |
4670103e CZ |
1373 | static int |
1374 | get_register (symbolS *sym) | |
252b5132 | 1375 | { |
4670103e CZ |
1376 | if (!contains_register (sym)) |
1377 | return -1; | |
0d2bcfaf | 1378 | |
4670103e CZ |
1379 | expressionS *ex = symbol_get_value_expression (sym); |
1380 | return regno (ex->X_add_number); | |
1381 | } | |
252b5132 | 1382 | |
4670103e CZ |
1383 | /* Return true if a RELOC is generic. A generic reloc is PC-rel of a |
1384 | simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */ | |
f17c130b | 1385 | |
4670103e CZ |
1386 | static bfd_boolean |
1387 | generic_reloc_p (extended_bfd_reloc_code_real_type reloc) | |
1388 | { | |
1389 | if (!reloc) | |
1390 | return FALSE; | |
886a2506 | 1391 | |
4670103e CZ |
1392 | switch (reloc) |
1393 | { | |
1394 | case BFD_RELOC_ARC_SDA_LDST: | |
1395 | case BFD_RELOC_ARC_SDA_LDST1: | |
1396 | case BFD_RELOC_ARC_SDA_LDST2: | |
1397 | case BFD_RELOC_ARC_SDA16_LD: | |
1398 | case BFD_RELOC_ARC_SDA16_LD1: | |
1399 | case BFD_RELOC_ARC_SDA16_LD2: | |
1400 | case BFD_RELOC_ARC_SDA16_ST2: | |
1401 | case BFD_RELOC_ARC_SDA32_ME: | |
1402 | return FALSE; | |
1403 | default: | |
1404 | return TRUE; | |
f17c130b | 1405 | } |
252b5132 RH |
1406 | } |
1407 | ||
4670103e | 1408 | /* Allocates a tok entry. */ |
252b5132 | 1409 | |
4670103e CZ |
1410 | static int |
1411 | allocate_tok (expressionS *tok, int ntok, int cidx) | |
252b5132 | 1412 | { |
4670103e CZ |
1413 | if (ntok > MAX_INSN_ARGS - 2) |
1414 | return 0; /* No space left. */ | |
252b5132 | 1415 | |
4670103e CZ |
1416 | if (cidx > ntok) |
1417 | return 0; /* Incorect args. */ | |
252b5132 | 1418 | |
4670103e | 1419 | memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok)); |
252b5132 | 1420 | |
4670103e CZ |
1421 | if (cidx == ntok) |
1422 | return 1; /* Success. */ | |
1423 | return allocate_tok (tok, ntok - 1, cidx); | |
1424 | } | |
886a2506 | 1425 | |
8ddf6b2a CZ |
1426 | /* Check if an particular ARC feature is enabled. */ |
1427 | ||
1428 | static bfd_boolean | |
1429 | check_cpu_feature (insn_subclass_t sc) | |
1430 | { | |
1431 | if (!(arc_features & ARC_CD) | |
1432 | && is_code_density_p (sc)) | |
1433 | return FALSE; | |
1434 | ||
1435 | if (!(arc_features & ARC_SPFP) | |
1436 | && is_spfp_p (sc)) | |
1437 | return FALSE; | |
1438 | ||
1439 | if (!(arc_features & ARC_DPFP) | |
1440 | && is_dpfp_p (sc)) | |
1441 | return FALSE; | |
1442 | ||
1443 | if (!(arc_features & ARC_FPUDA) | |
1444 | && is_fpuda_p (sc)) | |
1445 | return FALSE; | |
1446 | ||
1447 | return TRUE; | |
1448 | } | |
1449 | ||
4670103e CZ |
1450 | /* Search forward through all variants of an opcode looking for a |
1451 | syntax match. */ | |
886a2506 | 1452 | |
4670103e | 1453 | static const struct arc_opcode * |
b9b47ab7 | 1454 | find_opcode_match (const struct arc_opcode_hash_entry *entry, |
4670103e CZ |
1455 | expressionS *tok, |
1456 | int *pntok, | |
1457 | struct arc_flags *first_pflag, | |
1458 | int nflgs, | |
1459 | int *pcpumatch) | |
1460 | { | |
1328504b AB |
1461 | const struct arc_opcode *opcode; |
1462 | struct arc_opcode_hash_entry_iterator iter; | |
4670103e CZ |
1463 | int ntok = *pntok; |
1464 | int got_cpu_match = 0; | |
1465 | expressionS bktok[MAX_INSN_ARGS]; | |
1466 | int bkntok; | |
1467 | expressionS emptyE; | |
886a2506 | 1468 | |
1328504b | 1469 | arc_opcode_hash_entry_iterator_init (&iter); |
4670103e CZ |
1470 | memset (&emptyE, 0, sizeof (emptyE)); |
1471 | memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok)); | |
1472 | bkntok = ntok; | |
a161fe53 | 1473 | |
1328504b AB |
1474 | for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter); |
1475 | opcode != NULL; | |
1476 | opcode = arc_opcode_hash_entry_iterator_next (entry, &iter)) | |
252b5132 | 1477 | { |
4670103e CZ |
1478 | const unsigned char *opidx; |
1479 | const unsigned char *flgidx; | |
1ae8ab47 | 1480 | int tokidx = 0, lnflg, i; |
4670103e | 1481 | const expressionS *t = &emptyE; |
252b5132 | 1482 | |
4670103e CZ |
1483 | pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ", |
1484 | frag_now->fr_file, frag_now->fr_line, opcode->opcode); | |
886a2506 | 1485 | |
4670103e CZ |
1486 | /* Don't match opcodes that don't exist on this |
1487 | architecture. */ | |
1488 | if (!(opcode->cpu & arc_target)) | |
1489 | goto match_failed; | |
886a2506 | 1490 | |
8ddf6b2a | 1491 | if (!check_cpu_feature (opcode->subclass)) |
4670103e | 1492 | goto match_failed; |
886a2506 | 1493 | |
4670103e CZ |
1494 | got_cpu_match = 1; |
1495 | pr_debug ("cpu "); | |
886a2506 | 1496 | |
4670103e CZ |
1497 | /* Check the operands. */ |
1498 | for (opidx = opcode->operands; *opidx; ++opidx) | |
252b5132 | 1499 | { |
4670103e | 1500 | const struct arc_operand *operand = &arc_operands[*opidx]; |
252b5132 | 1501 | |
4670103e CZ |
1502 | /* Only take input from real operands. */ |
1503 | if ((operand->flags & ARC_OPERAND_FAKE) | |
1504 | && !(operand->flags & ARC_OPERAND_BRAKET)) | |
1505 | continue; | |
252b5132 | 1506 | |
4670103e CZ |
1507 | /* When we expect input, make sure we have it. */ |
1508 | if (tokidx >= ntok) | |
1509 | goto match_failed; | |
6f4b1afc | 1510 | |
4670103e CZ |
1511 | /* Match operand type with expression type. */ |
1512 | switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK) | |
1513 | { | |
1514 | case ARC_OPERAND_IR: | |
1515 | /* Check to be a register. */ | |
1516 | if ((tok[tokidx].X_op != O_register | |
1517 | || !is_ir_num (tok[tokidx].X_add_number)) | |
1518 | && !(operand->flags & ARC_OPERAND_IGNORE)) | |
1519 | goto match_failed; | |
1520 | ||
1521 | /* If expect duplicate, make sure it is duplicate. */ | |
1522 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
1523 | { | |
1524 | /* Check for duplicate. */ | |
1525 | if (t->X_op != O_register | |
1526 | || !is_ir_num (t->X_add_number) | |
1527 | || (regno (t->X_add_number) != | |
1528 | regno (tok[tokidx].X_add_number))) | |
1529 | goto match_failed; | |
1530 | } | |
1531 | ||
1532 | /* Special handling? */ | |
1533 | if (operand->insert) | |
1534 | { | |
1535 | const char *errmsg = NULL; | |
1536 | (*operand->insert)(0, | |
1537 | regno (tok[tokidx].X_add_number), | |
1538 | &errmsg); | |
1539 | if (errmsg) | |
1540 | { | |
1541 | if (operand->flags & ARC_OPERAND_IGNORE) | |
1542 | { | |
1543 | /* Missing argument, create one. */ | |
1544 | if (!allocate_tok (tok, ntok - 1, tokidx)) | |
1545 | goto match_failed; | |
1546 | ||
1547 | tok[tokidx].X_op = O_absent; | |
1548 | ++ntok; | |
1549 | } | |
1550 | else | |
1551 | goto match_failed; | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | t = &tok[tokidx]; | |
1556 | break; | |
1557 | ||
1558 | case ARC_OPERAND_BRAKET: | |
1559 | /* Check if bracket is also in opcode table as | |
1560 | operand. */ | |
1561 | if (tok[tokidx].X_op != O_bracket) | |
1562 | goto match_failed; | |
1563 | break; | |
1564 | ||
1565 | case ARC_OPERAND_LIMM: | |
1566 | case ARC_OPERAND_SIGNED: | |
1567 | case ARC_OPERAND_UNSIGNED: | |
1568 | switch (tok[tokidx].X_op) | |
1569 | { | |
1570 | case O_illegal: | |
1571 | case O_absent: | |
1572 | case O_register: | |
1573 | goto match_failed; | |
1574 | ||
1575 | case O_bracket: | |
1576 | /* Got an (too) early bracket, check if it is an | |
1577 | ignored operand. N.B. This procedure works only | |
1578 | when bracket is the last operand! */ | |
1579 | if (!(operand->flags & ARC_OPERAND_IGNORE)) | |
1580 | goto match_failed; | |
1581 | /* Insert the missing operand. */ | |
1582 | if (!allocate_tok (tok, ntok - 1, tokidx)) | |
1583 | goto match_failed; | |
1584 | ||
1585 | tok[tokidx].X_op = O_absent; | |
1586 | ++ntok; | |
1587 | break; | |
1588 | ||
22b92fc4 AB |
1589 | case O_symbol: |
1590 | { | |
1591 | const char *p; | |
1592 | size_t len; | |
1593 | const struct arc_aux_reg *auxr; | |
1594 | unsigned j; | |
1595 | ||
1596 | if (opcode->class != AUXREG) | |
1597 | goto de_fault; | |
1598 | p = S_GET_NAME (tok[tokidx].X_add_symbol); | |
1599 | len = strlen (p); | |
1600 | ||
1601 | auxr = &arc_aux_regs[0]; | |
1602 | for (j = 0; j < arc_num_aux_regs; j++, auxr++) | |
1603 | if (len == auxr->length | |
1604 | && strcasecmp (auxr->name, p) == 0 | |
1605 | && ((auxr->subclass == NONE) | |
1606 | || check_cpu_feature (auxr->subclass))) | |
1607 | { | |
1608 | /* We modify the token array here, safe in the | |
1609 | knowledge, that if this was the wrong choice | |
1610 | then the original contents will be restored | |
1611 | from BKTOK. */ | |
1612 | tok[tokidx].X_op = O_constant; | |
1613 | tok[tokidx].X_add_number = auxr->address; | |
1614 | break; | |
1615 | } | |
1616 | ||
1617 | if (tok[tokidx].X_op != O_constant) | |
1618 | goto de_fault; | |
1619 | } | |
1620 | /* Fall-through */ | |
4670103e CZ |
1621 | case O_constant: |
1622 | /* Check the range. */ | |
1623 | if (operand->bits != 32 | |
1624 | && !(operand->flags & ARC_OPERAND_NCHK)) | |
1625 | { | |
1626 | offsetT min, max, val; | |
1627 | val = tok[tokidx].X_add_number; | |
1628 | ||
1629 | if (operand->flags & ARC_OPERAND_SIGNED) | |
1630 | { | |
1631 | max = (1 << (operand->bits - 1)) - 1; | |
1632 | min = -(1 << (operand->bits - 1)); | |
1633 | } | |
1634 | else | |
1635 | { | |
1636 | max = (1 << operand->bits) - 1; | |
1637 | min = 0; | |
1638 | } | |
1639 | ||
1640 | if (val < min || val > max) | |
1641 | goto match_failed; | |
1642 | ||
1643 | /* Check alignmets. */ | |
1644 | if ((operand->flags & ARC_OPERAND_ALIGNED32) | |
1645 | && (val & 0x03)) | |
1646 | goto match_failed; | |
1647 | ||
1648 | if ((operand->flags & ARC_OPERAND_ALIGNED16) | |
1649 | && (val & 0x01)) | |
1650 | goto match_failed; | |
1651 | } | |
1652 | else if (operand->flags & ARC_OPERAND_NCHK) | |
1653 | { | |
1654 | if (operand->insert) | |
1655 | { | |
1656 | const char *errmsg = NULL; | |
1657 | (*operand->insert)(0, | |
1658 | tok[tokidx].X_add_number, | |
1659 | &errmsg); | |
1660 | if (errmsg) | |
1661 | goto match_failed; | |
1662 | } | |
1663 | else | |
1664 | goto match_failed; | |
1665 | } | |
1666 | break; | |
1667 | ||
1668 | case O_subtract: | |
1669 | /* Check if it is register range. */ | |
1670 | if ((tok[tokidx].X_add_number == 0) | |
1671 | && contains_register (tok[tokidx].X_add_symbol) | |
1672 | && contains_register (tok[tokidx].X_op_symbol)) | |
1673 | { | |
1674 | int regs; | |
1675 | ||
1676 | regs = get_register (tok[tokidx].X_add_symbol); | |
1677 | regs <<= 16; | |
1678 | regs |= get_register (tok[tokidx].X_op_symbol); | |
1679 | if (operand->insert) | |
1680 | { | |
1681 | const char *errmsg = NULL; | |
1682 | (*operand->insert)(0, | |
1683 | regs, | |
1684 | &errmsg); | |
1685 | if (errmsg) | |
1686 | goto match_failed; | |
1687 | } | |
1688 | else | |
1689 | goto match_failed; | |
1690 | break; | |
1691 | } | |
1692 | default: | |
22b92fc4 | 1693 | de_fault: |
4670103e CZ |
1694 | if (operand->default_reloc == 0) |
1695 | goto match_failed; /* The operand needs relocation. */ | |
1696 | ||
1697 | /* Relocs requiring long immediate. FIXME! make it | |
1698 | generic and move it to a function. */ | |
1699 | switch (tok[tokidx].X_md) | |
1700 | { | |
1701 | case O_gotoff: | |
1702 | case O_gotpc: | |
1703 | case O_pcl: | |
1704 | case O_tpoff: | |
1705 | case O_dtpoff: | |
1706 | case O_tlsgd: | |
1707 | case O_tlsie: | |
1708 | if (!(operand->flags & ARC_OPERAND_LIMM)) | |
1709 | goto match_failed; | |
1710 | case O_absent: | |
1711 | if (!generic_reloc_p (operand->default_reloc)) | |
1712 | goto match_failed; | |
1713 | default: | |
1714 | break; | |
1715 | } | |
1716 | break; | |
1717 | } | |
1718 | /* If expect duplicate, make sure it is duplicate. */ | |
1719 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
1720 | { | |
1721 | if (t->X_op == O_illegal | |
1722 | || t->X_op == O_absent | |
1723 | || t->X_op == O_register | |
1724 | || (t->X_add_number != tok[tokidx].X_add_number)) | |
1725 | goto match_failed; | |
1726 | } | |
1727 | t = &tok[tokidx]; | |
1728 | break; | |
1729 | ||
1730 | default: | |
1731 | /* Everything else should have been fake. */ | |
1732 | abort (); | |
1733 | } | |
1734 | ||
1735 | ++tokidx; | |
1736 | } | |
1737 | pr_debug ("opr "); | |
1738 | ||
1ae8ab47 AB |
1739 | /* Setup ready for flag parsing. */ |
1740 | lnflg = nflgs; | |
1741 | for (i = 0; i < nflgs; i++) | |
1742 | first_pflag [i].code = 0; | |
4670103e | 1743 | |
1ae8ab47 AB |
1744 | /* Check the flags. Iterate over the valid flag classes. */ |
1745 | for (flgidx = opcode->flags; *flgidx; ++flgidx) | |
4670103e CZ |
1746 | { |
1747 | /* Get a valid flag class. */ | |
1748 | const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; | |
1749 | const unsigned *flgopridx; | |
1ae8ab47 | 1750 | int cl_matches = 0; |
4670103e CZ |
1751 | |
1752 | for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) | |
1753 | { | |
1754 | const struct arc_flag_operand *flg_operand; | |
1755 | struct arc_flags *pflag = first_pflag; | |
4670103e CZ |
1756 | |
1757 | flg_operand = &arc_flag_operands[*flgopridx]; | |
1758 | for (i = 0; i < nflgs; i++, pflag++) | |
1759 | { | |
1760 | /* Match against the parsed flags. */ | |
1761 | if (!strcmp (flg_operand->name, pflag->name)) | |
1762 | { | |
1ae8ab47 AB |
1763 | if (pflag->code != 0) |
1764 | goto match_failed; | |
1765 | cl_matches++; | |
4670103e CZ |
1766 | pflag->code = *flgopridx; |
1767 | lnflg--; | |
1768 | break; /* goto next flag class and parsed flag. */ | |
1769 | } | |
1770 | } | |
1771 | } | |
1ae8ab47 AB |
1772 | |
1773 | if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0) | |
1774 | goto match_failed; | |
1775 | if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1) | |
1776 | goto match_failed; | |
4670103e CZ |
1777 | } |
1778 | /* Did I check all the parsed flags? */ | |
1779 | if (lnflg) | |
1780 | goto match_failed; | |
1781 | ||
1782 | pr_debug ("flg"); | |
1783 | /* Possible match -- did we use all of our input? */ | |
1784 | if (tokidx == ntok) | |
1785 | { | |
1786 | *pntok = ntok; | |
1787 | pr_debug ("\n"); | |
1788 | return opcode; | |
1789 | } | |
1790 | ||
1791 | match_failed:; | |
1792 | pr_debug ("\n"); | |
1793 | /* Restore the original parameters. */ | |
1794 | memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok)); | |
1795 | ntok = bkntok; | |
1796 | } | |
4670103e CZ |
1797 | |
1798 | if (*pcpumatch) | |
1799 | *pcpumatch = got_cpu_match; | |
1800 | ||
1801 | return NULL; | |
1802 | } | |
1803 | ||
1804 | /* Swap operand tokens. */ | |
1805 | ||
1806 | static void | |
1807 | swap_operand (expressionS *operand_array, | |
1808 | unsigned source, | |
1809 | unsigned destination) | |
1810 | { | |
1811 | expressionS cpy_operand; | |
1812 | expressionS *src_operand; | |
1813 | expressionS *dst_operand; | |
1814 | size_t size; | |
1815 | ||
1816 | if (source == destination) | |
1817 | return; | |
1818 | ||
1819 | src_operand = &operand_array[source]; | |
1820 | dst_operand = &operand_array[destination]; | |
1821 | size = sizeof (expressionS); | |
1822 | ||
1823 | /* Make copy of operand to swap with and swap. */ | |
1824 | memcpy (&cpy_operand, dst_operand, size); | |
1825 | memcpy (dst_operand, src_operand, size); | |
1826 | memcpy (src_operand, &cpy_operand, size); | |
1827 | } | |
1828 | ||
1829 | /* Check if *op matches *tok type. | |
1830 | Returns FALSE if they don't match, TRUE if they match. */ | |
1831 | ||
1832 | static bfd_boolean | |
1833 | pseudo_operand_match (const expressionS *tok, | |
1834 | const struct arc_operand_operation *op) | |
1835 | { | |
1836 | offsetT min, max, val; | |
1837 | bfd_boolean ret; | |
1838 | const struct arc_operand *operand_real = &arc_operands[op->operand_idx]; | |
1839 | ||
1840 | ret = FALSE; | |
1841 | switch (tok->X_op) | |
1842 | { | |
1843 | case O_constant: | |
1844 | if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM)) | |
1845 | ret = 1; | |
1846 | else if (!(operand_real->flags & ARC_OPERAND_IR)) | |
1847 | { | |
1848 | val = tok->X_add_number + op->count; | |
1849 | if (operand_real->flags & ARC_OPERAND_SIGNED) | |
1850 | { | |
1851 | max = (1 << (operand_real->bits - 1)) - 1; | |
1852 | min = -(1 << (operand_real->bits - 1)); | |
1853 | } | |
1854 | else | |
1855 | { | |
1856 | max = (1 << operand_real->bits) - 1; | |
1857 | min = 0; | |
1858 | } | |
1859 | if (min <= val && val <= max) | |
1860 | ret = TRUE; | |
1861 | } | |
6f4b1afc CM |
1862 | break; |
1863 | ||
4670103e CZ |
1864 | case O_symbol: |
1865 | /* Handle all symbols as long immediates or signed 9. */ | |
1866 | if (operand_real->flags & ARC_OPERAND_LIMM || | |
1867 | ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9)) | |
1868 | ret = TRUE; | |
6f4b1afc CM |
1869 | break; |
1870 | ||
4670103e CZ |
1871 | case O_register: |
1872 | if (operand_real->flags & ARC_OPERAND_IR) | |
1873 | ret = TRUE; | |
1874 | break; | |
1875 | ||
1876 | case O_bracket: | |
1877 | if (operand_real->flags & ARC_OPERAND_BRAKET) | |
1878 | ret = TRUE; | |
6f4b1afc CM |
1879 | break; |
1880 | ||
1881 | default: | |
4670103e | 1882 | /* Unknown. */ |
6f4b1afc CM |
1883 | break; |
1884 | } | |
4670103e CZ |
1885 | return ret; |
1886 | } | |
6f4b1afc | 1887 | |
4670103e CZ |
1888 | /* Find pseudo instruction in array. */ |
1889 | ||
1890 | static const struct arc_pseudo_insn * | |
1891 | find_pseudo_insn (const char *opname, | |
1892 | int ntok, | |
1893 | const expressionS *tok) | |
1894 | { | |
1895 | const struct arc_pseudo_insn *pseudo_insn = NULL; | |
1896 | const struct arc_operand_operation *op; | |
1897 | unsigned int i; | |
1898 | int j; | |
1899 | ||
1900 | for (i = 0; i < arc_num_pseudo_insn; ++i) | |
6f4b1afc | 1901 | { |
4670103e CZ |
1902 | pseudo_insn = &arc_pseudo_insns[i]; |
1903 | if (strcmp (pseudo_insn->mnemonic_p, opname) == 0) | |
1904 | { | |
1905 | op = pseudo_insn->operand; | |
1906 | for (j = 0; j < ntok; ++j) | |
1907 | if (!pseudo_operand_match (&tok[j], &op[j])) | |
1908 | break; | |
1909 | ||
1910 | /* Found the right instruction. */ | |
1911 | if (j == ntok) | |
1912 | return pseudo_insn; | |
1913 | } | |
6f4b1afc | 1914 | } |
4670103e CZ |
1915 | return NULL; |
1916 | } | |
252b5132 | 1917 | |
4670103e | 1918 | /* Assumes the expressionS *tok is of sufficient size. */ |
252b5132 | 1919 | |
b9b47ab7 | 1920 | static const struct arc_opcode_hash_entry * |
4670103e CZ |
1921 | find_special_case_pseudo (const char *opname, |
1922 | int *ntok, | |
1923 | expressionS *tok, | |
1924 | int *nflgs, | |
1925 | struct arc_flags *pflags) | |
1926 | { | |
1927 | const struct arc_pseudo_insn *pseudo_insn = NULL; | |
1928 | const struct arc_operand_operation *operand_pseudo; | |
1929 | const struct arc_operand *operand_real; | |
1930 | unsigned i; | |
1931 | char construct_operand[MAX_CONSTR_STR]; | |
886a2506 | 1932 | |
4670103e CZ |
1933 | /* Find whether opname is in pseudo instruction array. */ |
1934 | pseudo_insn = find_pseudo_insn (opname, *ntok, tok); | |
1935 | ||
1936 | if (pseudo_insn == NULL) | |
1937 | return NULL; | |
1938 | ||
1939 | /* Handle flag, Limited to one flag at the moment. */ | |
1940 | if (pseudo_insn->flag_r != NULL) | |
1941 | *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs], | |
1942 | MAX_INSN_FLGS - *nflgs); | |
1943 | ||
1944 | /* Handle operand operations. */ | |
1945 | for (i = 0; i < pseudo_insn->operand_cnt; ++i) | |
252b5132 | 1946 | { |
4670103e CZ |
1947 | operand_pseudo = &pseudo_insn->operand[i]; |
1948 | operand_real = &arc_operands[operand_pseudo->operand_idx]; | |
886a2506 | 1949 | |
4670103e CZ |
1950 | if (operand_real->flags & ARC_OPERAND_BRAKET && |
1951 | !operand_pseudo->needs_insert) | |
1952 | continue; | |
b125bd17 | 1953 | |
4670103e CZ |
1954 | /* Has to be inserted (i.e. this token does not exist yet). */ |
1955 | if (operand_pseudo->needs_insert) | |
1956 | { | |
1957 | if (operand_real->flags & ARC_OPERAND_BRAKET) | |
1958 | { | |
1959 | tok[i].X_op = O_bracket; | |
1960 | ++(*ntok); | |
1961 | continue; | |
1962 | } | |
b125bd17 | 1963 | |
4670103e CZ |
1964 | /* Check if operand is a register or constant and handle it |
1965 | by type. */ | |
1966 | if (operand_real->flags & ARC_OPERAND_IR) | |
1967 | snprintf (construct_operand, MAX_CONSTR_STR, "r%d", | |
1968 | operand_pseudo->count); | |
1969 | else | |
1970 | snprintf (construct_operand, MAX_CONSTR_STR, "%d", | |
1971 | operand_pseudo->count); | |
886a2506 | 1972 | |
4670103e CZ |
1973 | tokenize_arguments (construct_operand, &tok[i], 1); |
1974 | ++(*ntok); | |
1975 | } | |
1976 | ||
1977 | else if (operand_pseudo->count) | |
1978 | { | |
1979 | /* Operand number has to be adjusted accordingly (by operand | |
1980 | type). */ | |
1981 | switch (tok[i].X_op) | |
1982 | { | |
1983 | case O_constant: | |
1984 | tok[i].X_add_number += operand_pseudo->count; | |
1985 | break; | |
1986 | ||
1987 | case O_symbol: | |
1988 | break; | |
1989 | ||
1990 | default: | |
1991 | /* Ignored. */ | |
1992 | break; | |
1993 | } | |
1994 | } | |
1995 | } | |
1996 | ||
1997 | /* Swap operands if necessary. Only supports one swap at the | |
1998 | moment. */ | |
1999 | for (i = 0; i < pseudo_insn->operand_cnt; ++i) | |
2000 | { | |
2001 | operand_pseudo = &pseudo_insn->operand[i]; | |
2002 | ||
2003 | if (operand_pseudo->swap_operand_idx == i) | |
2004 | continue; | |
2005 | ||
2006 | swap_operand (tok, i, operand_pseudo->swap_operand_idx); | |
2007 | ||
2008 | /* Prevent a swap back later by breaking out. */ | |
2009 | break; | |
2010 | } | |
2011 | ||
da5be039 | 2012 | return arc_find_opcode (pseudo_insn->mnemonic_r); |
4670103e CZ |
2013 | } |
2014 | ||
b9b47ab7 | 2015 | static const struct arc_opcode_hash_entry * |
4670103e CZ |
2016 | find_special_case_flag (const char *opname, |
2017 | int *nflgs, | |
2018 | struct arc_flags *pflags) | |
2019 | { | |
2020 | unsigned int i; | |
2021 | const char *flagnm; | |
2022 | unsigned flag_idx, flag_arr_idx; | |
2023 | size_t flaglen, oplen; | |
2024 | const struct arc_flag_special *arc_flag_special_opcode; | |
b9b47ab7 | 2025 | const struct arc_opcode_hash_entry *entry; |
4670103e CZ |
2026 | |
2027 | /* Search for special case instruction. */ | |
2028 | for (i = 0; i < arc_num_flag_special; i++) | |
2029 | { | |
2030 | arc_flag_special_opcode = &arc_flag_special_cases[i]; | |
2031 | oplen = strlen (arc_flag_special_opcode->name); | |
2032 | ||
2033 | if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0) | |
2034 | continue; | |
2035 | ||
2036 | /* Found a potential special case instruction, now test for | |
2037 | flags. */ | |
2038 | for (flag_arr_idx = 0;; ++flag_arr_idx) | |
2039 | { | |
2040 | flag_idx = arc_flag_special_opcode->flags[flag_arr_idx]; | |
2041 | if (flag_idx == 0) | |
2042 | break; /* End of array, nothing found. */ | |
886a2506 | 2043 | |
4670103e CZ |
2044 | flagnm = arc_flag_operands[flag_idx].name; |
2045 | flaglen = strlen (flagnm); | |
2046 | if (strcmp (opname + oplen, flagnm) == 0) | |
2047 | { | |
b9b47ab7 | 2048 | entry = arc_find_opcode (arc_flag_special_opcode->name); |
886a2506 | 2049 | |
4670103e CZ |
2050 | if (*nflgs + 1 > MAX_INSN_FLGS) |
2051 | break; | |
2052 | memcpy (pflags[*nflgs].name, flagnm, flaglen); | |
2053 | pflags[*nflgs].name[flaglen] = '\0'; | |
2054 | (*nflgs)++; | |
b9b47ab7 | 2055 | return entry; |
4670103e CZ |
2056 | } |
2057 | } | |
2058 | } | |
2059 | return NULL; | |
2060 | } | |
886a2506 | 2061 | |
4670103e | 2062 | /* Used to find special case opcode. */ |
886a2506 | 2063 | |
b9b47ab7 | 2064 | static const struct arc_opcode_hash_entry * |
4670103e CZ |
2065 | find_special_case (const char *opname, |
2066 | int *nflgs, | |
2067 | struct arc_flags *pflags, | |
2068 | expressionS *tok, | |
2069 | int *ntok) | |
2070 | { | |
b9b47ab7 | 2071 | const struct arc_opcode_hash_entry *entry; |
886a2506 | 2072 | |
b9b47ab7 | 2073 | entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags); |
886a2506 | 2074 | |
b9b47ab7 AB |
2075 | if (entry == NULL) |
2076 | entry = find_special_case_flag (opname, nflgs, pflags); | |
886a2506 | 2077 | |
b9b47ab7 | 2078 | return entry; |
4670103e | 2079 | } |
886a2506 | 2080 | |
4670103e CZ |
2081 | /* Given an opcode name, pre-tockenized set of argumenst and the |
2082 | opcode flags, take it all the way through emission. */ | |
886a2506 | 2083 | |
4670103e CZ |
2084 | static void |
2085 | assemble_tokens (const char *opname, | |
2086 | expressionS *tok, | |
2087 | int ntok, | |
2088 | struct arc_flags *pflags, | |
2089 | int nflgs) | |
2090 | { | |
2091 | bfd_boolean found_something = FALSE; | |
b9b47ab7 | 2092 | const struct arc_opcode_hash_entry *entry; |
4670103e | 2093 | int cpumatch = 1; |
886a2506 | 2094 | |
4670103e | 2095 | /* Search opcodes. */ |
b9b47ab7 | 2096 | entry = arc_find_opcode (opname); |
886a2506 | 2097 | |
4670103e | 2098 | /* Couldn't find opcode conventional way, try special cases. */ |
b9b47ab7 AB |
2099 | if (entry == NULL) |
2100 | entry = find_special_case (opname, &nflgs, pflags, tok, &ntok); | |
886a2506 | 2101 | |
b9b47ab7 | 2102 | if (entry != NULL) |
4670103e | 2103 | { |
b9b47ab7 AB |
2104 | const struct arc_opcode *opcode; |
2105 | ||
1328504b AB |
2106 | pr_debug ("%s:%d: assemble_tokens: %s\n", |
2107 | frag_now->fr_file, frag_now->fr_line, opname); | |
4670103e | 2108 | found_something = TRUE; |
b9b47ab7 AB |
2109 | opcode = find_opcode_match (entry, tok, &ntok, pflags, |
2110 | nflgs, &cpumatch); | |
2111 | if (opcode != NULL) | |
4670103e CZ |
2112 | { |
2113 | struct arc_insn insn; | |
b9b47ab7 | 2114 | |
4670103e CZ |
2115 | assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn); |
2116 | emit_insn (&insn); | |
2117 | return; | |
2118 | } | |
2119 | } | |
886a2506 | 2120 | |
4670103e CZ |
2121 | if (found_something) |
2122 | { | |
2123 | if (cpumatch) | |
2124 | as_bad (_("inappropriate arguments for opcode '%s'"), opname); | |
2125 | else | |
2126 | as_bad (_("opcode '%s' not supported for target %s"), opname, | |
2127 | arc_target_name); | |
2128 | } | |
2129 | else | |
2130 | as_bad (_("unknown opcode '%s'"), opname); | |
886a2506 NC |
2131 | } |
2132 | ||
4670103e | 2133 | /* The public interface to the instruction assembler. */ |
886a2506 | 2134 | |
4670103e CZ |
2135 | void |
2136 | md_assemble (char *str) | |
886a2506 | 2137 | { |
4670103e CZ |
2138 | char *opname; |
2139 | expressionS tok[MAX_INSN_ARGS]; | |
2140 | int ntok, nflg; | |
2141 | size_t opnamelen; | |
2142 | struct arc_flags flags[MAX_INSN_FLGS]; | |
886a2506 | 2143 | |
4670103e CZ |
2144 | /* Split off the opcode. */ |
2145 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468"); | |
2146 | opname = xmalloc (opnamelen + 1); | |
2147 | memcpy (opname, str, opnamelen); | |
2148 | opname[opnamelen] = '\0'; | |
886a2506 | 2149 | |
4670103e CZ |
2150 | /* Signalize we are assmbling the instructions. */ |
2151 | assembling_insn = TRUE; | |
886a2506 | 2152 | |
4670103e CZ |
2153 | /* Tokenize the flags. */ |
2154 | if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1) | |
2155 | { | |
2156 | as_bad (_("syntax error")); | |
2157 | return; | |
2158 | } | |
886a2506 | 2159 | |
4670103e CZ |
2160 | /* Scan up to the end of the mnemonic which must end in space or end |
2161 | of string. */ | |
2162 | str += opnamelen; | |
2163 | for (; *str != '\0'; str++) | |
2164 | if (*str == ' ') | |
2165 | break; | |
886a2506 | 2166 | |
4670103e CZ |
2167 | /* Tokenize the rest of the line. */ |
2168 | if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0) | |
886a2506 | 2169 | { |
4670103e CZ |
2170 | as_bad (_("syntax error")); |
2171 | return; | |
252b5132 RH |
2172 | } |
2173 | ||
4670103e CZ |
2174 | /* Finish it off. */ |
2175 | assemble_tokens (opname, tok, ntok, flags, nflg); | |
2176 | assembling_insn = FALSE; | |
2177 | } | |
2178 | ||
2179 | /* Callback to insert a register into the hash table. */ | |
2180 | ||
2181 | static void | |
f86f5863 | 2182 | declare_register (const char *name, int number) |
4670103e CZ |
2183 | { |
2184 | const char *err; | |
2185 | symbolS *regS = symbol_create (name, reg_section, | |
2186 | number, &zero_address_frag); | |
2187 | ||
2188 | err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS); | |
2189 | if (err) | |
e6ba1cba | 2190 | as_fatal (_("Inserting \"%s\" into register table failed: %s"), |
4670103e CZ |
2191 | name, err); |
2192 | } | |
252b5132 | 2193 | |
4670103e | 2194 | /* Construct symbols for each of the general registers. */ |
252b5132 | 2195 | |
4670103e CZ |
2196 | static void |
2197 | declare_register_set (void) | |
2198 | { | |
2199 | int i; | |
2200 | for (i = 0; i < 64; ++i) | |
886a2506 | 2201 | { |
4670103e CZ |
2202 | char name[7]; |
2203 | ||
2204 | sprintf (name, "r%d", i); | |
2205 | declare_register (name, i); | |
2206 | if ((i & 0x01) == 0) | |
886a2506 | 2207 | { |
4670103e CZ |
2208 | sprintf (name, "r%dr%d", i, i+1); |
2209 | declare_register (name, i); | |
886a2506 NC |
2210 | } |
2211 | } | |
252b5132 | 2212 | } |
ea1562b3 | 2213 | |
4670103e CZ |
2214 | /* Port-specific assembler initialization. This function is called |
2215 | once, at assembler startup time. */ | |
ea1562b3 NC |
2216 | |
2217 | void | |
4670103e | 2218 | md_begin (void) |
ea1562b3 | 2219 | { |
4670103e | 2220 | unsigned int i; |
886a2506 | 2221 | |
24740d83 AB |
2222 | if (!mach_type_specified_p) |
2223 | arc_select_cpu ("arc700"); | |
2224 | ||
4670103e CZ |
2225 | /* The endianness can be chosen "at the factory". */ |
2226 | target_big_endian = byte_order == BIG_ENDIAN; | |
886a2506 | 2227 | |
4670103e CZ |
2228 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type)) |
2229 | as_warn (_("could not set architecture and machine")); | |
2230 | ||
2231 | /* Set elf header flags. */ | |
2232 | bfd_set_private_flags (stdoutput, arc_eflag); | |
2233 | ||
2234 | /* Set up a hash table for the instructions. */ | |
2235 | arc_opcode_hash = hash_new (); | |
2236 | if (arc_opcode_hash == NULL) | |
2237 | as_fatal (_("Virtual memory exhausted")); | |
2238 | ||
2239 | /* Initialize the hash table with the insns. */ | |
2240 | for (i = 0; i < arc_num_opcodes;) | |
ea1562b3 | 2241 | { |
4670103e | 2242 | const char *name, *retval; |
da5be039 | 2243 | struct arc_opcode_hash_entry *entry; |
886a2506 | 2244 | |
4670103e | 2245 | name = arc_opcodes[i].name; |
da5be039 AB |
2246 | |
2247 | entry = hash_find (arc_opcode_hash, name); | |
2248 | if (entry == NULL) | |
2249 | { | |
2250 | entry = xmalloc (sizeof (*entry)); | |
2251 | entry->count = 0; | |
2252 | entry->opcode = NULL; | |
2253 | ||
2254 | retval = hash_insert (arc_opcode_hash, name, (void *) entry); | |
2255 | if (retval) | |
2256 | as_fatal (_("internal error: can't hash opcode '%s': %s"), | |
2257 | name, retval); | |
2258 | } | |
2259 | ||
2260 | entry->opcode = xrealloc (entry->opcode, | |
2261 | sizeof (const struct arc_opcode *) | |
2262 | * entry->count + 1); | |
2263 | entry->opcode [entry->count] = &arc_opcodes[i]; | |
2264 | entry->count++; | |
4670103e CZ |
2265 | |
2266 | while (++i < arc_num_opcodes | |
2267 | && (arc_opcodes[i].name == name | |
2268 | || !strcmp (arc_opcodes[i].name, name))) | |
2269 | continue; | |
ea1562b3 | 2270 | } |
4670103e CZ |
2271 | |
2272 | /* Register declaration. */ | |
2273 | arc_reg_hash = hash_new (); | |
2274 | if (arc_reg_hash == NULL) | |
2275 | as_fatal (_("Virtual memory exhausted")); | |
2276 | ||
2277 | declare_register_set (); | |
2278 | declare_register ("gp", 26); | |
2279 | declare_register ("fp", 27); | |
2280 | declare_register ("sp", 28); | |
2281 | declare_register ("ilink", 29); | |
2282 | declare_register ("ilink1", 29); | |
2283 | declare_register ("ilink2", 30); | |
2284 | declare_register ("blink", 31); | |
2285 | ||
2286 | declare_register ("mlo", 57); | |
2287 | declare_register ("mmid", 58); | |
2288 | declare_register ("mhi", 59); | |
2289 | ||
2290 | declare_register ("acc1", 56); | |
2291 | declare_register ("acc2", 57); | |
2292 | ||
2293 | declare_register ("lp_count", 60); | |
2294 | declare_register ("pcl", 63); | |
2295 | ||
2296 | /* Initialize the last instructions. */ | |
2297 | memset (&arc_last_insns[0], 0, sizeof (arc_last_insns)); | |
886a2506 | 2298 | } |
ea1562b3 | 2299 | |
4670103e CZ |
2300 | /* Write a value out to the object file, using the appropriate |
2301 | endianness. */ | |
ea1562b3 | 2302 | |
4670103e CZ |
2303 | void |
2304 | md_number_to_chars (char *buf, | |
2305 | valueT val, | |
2306 | int n) | |
886a2506 | 2307 | { |
4670103e CZ |
2308 | if (target_big_endian) |
2309 | number_to_chars_bigendian (buf, val, n); | |
2310 | else | |
2311 | number_to_chars_littleendian (buf, val, n); | |
886a2506 | 2312 | } |
ea1562b3 | 2313 | |
4670103e | 2314 | /* Round up a section size to the appropriate boundary. */ |
ea1562b3 | 2315 | |
4670103e CZ |
2316 | valueT |
2317 | md_section_align (segT segment, | |
2318 | valueT size) | |
886a2506 | 2319 | { |
4670103e CZ |
2320 | int align = bfd_get_section_alignment (stdoutput, segment); |
2321 | ||
2322 | return ((size + (1 << align) - 1) & (-((valueT) 1 << align))); | |
886a2506 | 2323 | } |
ea1562b3 | 2324 | |
4670103e CZ |
2325 | /* The location from which a PC relative jump should be calculated, |
2326 | given a PC relative reloc. */ | |
ea1562b3 | 2327 | |
4670103e CZ |
2328 | long |
2329 | md_pcrel_from_section (fixS *fixP, | |
2330 | segT sec) | |
886a2506 | 2331 | { |
4670103e | 2332 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
ea1562b3 | 2333 | |
4670103e | 2334 | pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset); |
ea1562b3 | 2335 | |
4670103e CZ |
2336 | if (fixP->fx_addsy != (symbolS *) NULL |
2337 | && (!S_IS_DEFINED (fixP->fx_addsy) | |
2338 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
2339 | { | |
2340 | pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy)); | |
ea1562b3 | 2341 | |
4670103e CZ |
2342 | /* The symbol is undefined (or is defined but not in this section). |
2343 | Let the linker figure it out. */ | |
2344 | return 0; | |
2345 | } | |
2346 | ||
2347 | if ((int) fixP->fx_r_type < 0) | |
886a2506 | 2348 | { |
4670103e CZ |
2349 | /* These are the "internal" relocations. Align them to |
2350 | 32 bit boundary (PCL), for the moment. */ | |
2351 | base &= ~3; | |
886a2506 | 2352 | } |
4670103e CZ |
2353 | else |
2354 | { | |
2355 | switch (fixP->fx_r_type) | |
2356 | { | |
2357 | case BFD_RELOC_ARC_PC32: | |
2358 | /* The hardware calculates relative to the start of the | |
2359 | insn, but this relocation is relative to location of the | |
2360 | LIMM, compensate. The base always needs to be | |
2361 | substracted by 4 as we do not support this type of PCrel | |
2362 | relocation for short instructions. */ | |
2363 | base -= 4; | |
2364 | /* Fall through. */ | |
2365 | case BFD_RELOC_ARC_PLT32: | |
2366 | case BFD_RELOC_ARC_S25H_PCREL_PLT: | |
2367 | case BFD_RELOC_ARC_S21H_PCREL_PLT: | |
2368 | case BFD_RELOC_ARC_S25W_PCREL_PLT: | |
2369 | case BFD_RELOC_ARC_S21W_PCREL_PLT: | |
2370 | ||
2371 | case BFD_RELOC_ARC_S21H_PCREL: | |
2372 | case BFD_RELOC_ARC_S25H_PCREL: | |
2373 | case BFD_RELOC_ARC_S13_PCREL: | |
2374 | case BFD_RELOC_ARC_S21W_PCREL: | |
2375 | case BFD_RELOC_ARC_S25W_PCREL: | |
2376 | base &= ~3; | |
2377 | break; | |
2378 | default: | |
2379 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2380 | _("unhandled reloc %s in md_pcrel_from_section"), | |
2381 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
2382 | break; | |
2383 | } | |
2384 | } | |
2385 | ||
2386 | pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n", | |
2387 | fixP->fx_frag->fr_address, fixP->fx_where, base, | |
2388 | fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)", | |
2389 | fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0); | |
2390 | ||
2391 | return base; | |
886a2506 | 2392 | } |
ea1562b3 | 2393 | |
4670103e | 2394 | /* Given a BFD relocation find the coresponding operand. */ |
ea1562b3 | 2395 | |
4670103e CZ |
2396 | static const struct arc_operand * |
2397 | find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc) | |
2398 | { | |
2399 | unsigned i; | |
ea1562b3 | 2400 | |
4670103e CZ |
2401 | for (i = 0; i < arc_num_operands; i++) |
2402 | if (arc_operands[i].default_reloc == reloc) | |
2403 | return &arc_operands[i]; | |
2404 | return NULL; | |
2405 | } | |
ea1562b3 | 2406 | |
4670103e | 2407 | /* Insert an operand value into an instruction. */ |
ea1562b3 | 2408 | |
4670103e CZ |
2409 | static unsigned |
2410 | insert_operand (unsigned insn, | |
2411 | const struct arc_operand *operand, | |
2412 | offsetT val, | |
3b4dbbbf | 2413 | const char *file, |
4670103e | 2414 | unsigned line) |
886a2506 | 2415 | { |
4670103e | 2416 | offsetT min = 0, max = 0; |
ea1562b3 | 2417 | |
4670103e CZ |
2418 | if (operand->bits != 32 |
2419 | && !(operand->flags & ARC_OPERAND_NCHK) | |
2420 | && !(operand->flags & ARC_OPERAND_FAKE)) | |
886a2506 | 2421 | { |
4670103e CZ |
2422 | if (operand->flags & ARC_OPERAND_SIGNED) |
2423 | { | |
2424 | max = (1 << (operand->bits - 1)) - 1; | |
2425 | min = -(1 << (operand->bits - 1)); | |
2426 | } | |
2427 | else | |
2428 | { | |
2429 | max = (1 << operand->bits) - 1; | |
2430 | min = 0; | |
2431 | } | |
886a2506 | 2432 | |
4670103e CZ |
2433 | if (val < min || val > max) |
2434 | as_bad_value_out_of_range (_("operand"), | |
2435 | val, min, max, file, line); | |
2436 | } | |
ea1562b3 | 2437 | |
4670103e CZ |
2438 | pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n", |
2439 | min, val, max, insn); | |
ea1562b3 | 2440 | |
4670103e CZ |
2441 | if ((operand->flags & ARC_OPERAND_ALIGNED32) |
2442 | && (val & 0x03)) | |
2443 | as_bad_where (file, line, | |
2444 | _("Unaligned operand. Needs to be 32bit aligned")); | |
ea1562b3 | 2445 | |
4670103e CZ |
2446 | if ((operand->flags & ARC_OPERAND_ALIGNED16) |
2447 | && (val & 0x01)) | |
2448 | as_bad_where (file, line, | |
2449 | _("Unaligned operand. Needs to be 16bit aligned")); | |
ea1562b3 | 2450 | |
4670103e CZ |
2451 | if (operand->insert) |
2452 | { | |
2453 | const char *errmsg = NULL; | |
ea1562b3 | 2454 | |
4670103e CZ |
2455 | insn = (*operand->insert) (insn, val, &errmsg); |
2456 | if (errmsg) | |
2457 | as_warn_where (file, line, "%s", errmsg); | |
2458 | } | |
2459 | else | |
2460 | { | |
2461 | if (operand->flags & ARC_OPERAND_TRUNCATE) | |
2462 | { | |
2463 | if (operand->flags & ARC_OPERAND_ALIGNED32) | |
2464 | val >>= 2; | |
2465 | if (operand->flags & ARC_OPERAND_ALIGNED16) | |
2466 | val >>= 1; | |
886a2506 | 2467 | } |
4670103e CZ |
2468 | insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift); |
2469 | } | |
2470 | return insn; | |
2471 | } | |
ea1562b3 | 2472 | |
4670103e CZ |
2473 | /* Apply a fixup to the object code. At this point all symbol values |
2474 | should be fully resolved, and we attempt to completely resolve the | |
2475 | reloc. If we can not do that, we determine the correct reloc code | |
2476 | and put it back in the fixup. To indicate that a fixup has been | |
2477 | eliminated, set fixP->fx_done. */ | |
ea1562b3 | 2478 | |
4670103e CZ |
2479 | void |
2480 | md_apply_fix (fixS *fixP, | |
2481 | valueT *valP, | |
2482 | segT seg) | |
2483 | { | |
2484 | char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
2485 | valueT value = *valP; | |
2486 | unsigned insn = 0; | |
2487 | symbolS *fx_addsy, *fx_subsy; | |
2488 | offsetT fx_offset; | |
2489 | segT add_symbol_segment = absolute_section; | |
2490 | segT sub_symbol_segment = absolute_section; | |
2491 | const struct arc_operand *operand = NULL; | |
2492 | extended_bfd_reloc_code_real_type reloc; | |
886a2506 | 2493 | |
4670103e CZ |
2494 | pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", |
2495 | fixP->fx_file, fixP->fx_line, fixP->fx_r_type, | |
2496 | ((int) fixP->fx_r_type < 0) ? "Internal": | |
2497 | bfd_get_reloc_code_name (fixP->fx_r_type), value, | |
2498 | fixP->fx_offset); | |
886a2506 | 2499 | |
4670103e CZ |
2500 | fx_addsy = fixP->fx_addsy; |
2501 | fx_subsy = fixP->fx_subsy; | |
2502 | fx_offset = 0; | |
886a2506 | 2503 | |
4670103e CZ |
2504 | if (fx_addsy) |
2505 | { | |
2506 | add_symbol_segment = S_GET_SEGMENT (fx_addsy); | |
886a2506 NC |
2507 | } |
2508 | ||
4670103e CZ |
2509 | if (fx_subsy |
2510 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF | |
2511 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9 | |
2512 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD) | |
2513 | { | |
2514 | resolve_symbol_value (fx_subsy); | |
2515 | sub_symbol_segment = S_GET_SEGMENT (fx_subsy); | |
886a2506 | 2516 | |
4670103e CZ |
2517 | if (sub_symbol_segment == absolute_section) |
2518 | { | |
2519 | /* The symbol is really a constant. */ | |
2520 | fx_offset -= S_GET_VALUE (fx_subsy); | |
2521 | fx_subsy = NULL; | |
2522 | } | |
2523 | else | |
2524 | { | |
2525 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2526 | _("can't resolve `%s' {%s section} - `%s' {%s section}"), | |
2527 | fx_addsy ? S_GET_NAME (fx_addsy) : "0", | |
2528 | segment_name (add_symbol_segment), | |
2529 | S_GET_NAME (fx_subsy), | |
2530 | segment_name (sub_symbol_segment)); | |
2531 | return; | |
2532 | } | |
2533 | } | |
886a2506 | 2534 | |
4670103e CZ |
2535 | if (fx_addsy |
2536 | && !S_IS_WEAK (fx_addsy)) | |
2537 | { | |
2538 | if (add_symbol_segment == seg | |
2539 | && fixP->fx_pcrel) | |
2540 | { | |
2541 | value += S_GET_VALUE (fx_addsy); | |
2542 | value -= md_pcrel_from_section (fixP, seg); | |
2543 | fx_addsy = NULL; | |
2544 | fixP->fx_pcrel = FALSE; | |
2545 | } | |
2546 | else if (add_symbol_segment == absolute_section) | |
2547 | { | |
2548 | value = fixP->fx_offset; | |
2549 | fx_offset += S_GET_VALUE (fixP->fx_addsy); | |
2550 | fx_addsy = NULL; | |
2551 | fixP->fx_pcrel = FALSE; | |
2552 | } | |
2553 | } | |
886a2506 | 2554 | |
4670103e CZ |
2555 | if (!fx_addsy) |
2556 | fixP->fx_done = TRUE; | |
886a2506 | 2557 | |
4670103e | 2558 | if (fixP->fx_pcrel) |
886a2506 | 2559 | { |
4670103e CZ |
2560 | if (fx_addsy |
2561 | && ((S_IS_DEFINED (fx_addsy) | |
2562 | && S_GET_SEGMENT (fx_addsy) != seg) | |
2563 | || S_IS_WEAK (fx_addsy))) | |
2564 | value += md_pcrel_from_section (fixP, seg); | |
886a2506 | 2565 | |
4670103e CZ |
2566 | switch (fixP->fx_r_type) |
2567 | { | |
2568 | case BFD_RELOC_ARC_32_ME: | |
2569 | /* This is a pc-relative value in a LIMM. Adjust it to the | |
2570 | address of the instruction not to the address of the | |
2571 | LIMM. Note: it is not anylonger valid this afirmation as | |
2572 | the linker consider ARC_PC32 a fixup to entire 64 bit | |
2573 | insn. */ | |
2574 | fixP->fx_offset += fixP->fx_frag->fr_address; | |
2575 | /* Fall through. */ | |
2576 | case BFD_RELOC_32: | |
2577 | fixP->fx_r_type = BFD_RELOC_ARC_PC32; | |
2578 | /* Fall through. */ | |
2579 | case BFD_RELOC_ARC_PC32: | |
2580 | /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */ | |
886a2506 NC |
2581 | break; |
2582 | default: | |
4670103e CZ |
2583 | if ((int) fixP->fx_r_type < 0) |
2584 | as_fatal (_("PC relative relocation not allowed for (internal) type %d"), | |
2585 | fixP->fx_r_type); | |
886a2506 | 2586 | break; |
ea1562b3 NC |
2587 | } |
2588 | } | |
2589 | ||
4670103e CZ |
2590 | pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", |
2591 | fixP->fx_file, fixP->fx_line, fixP->fx_r_type, | |
2592 | ((int) fixP->fx_r_type < 0) ? "Internal": | |
2593 | bfd_get_reloc_code_name (fixP->fx_r_type), value, | |
2594 | fixP->fx_offset); | |
886a2506 | 2595 | |
886a2506 | 2596 | |
4670103e CZ |
2597 | /* Now check for TLS relocations. */ |
2598 | reloc = fixP->fx_r_type; | |
2599 | switch (reloc) | |
886a2506 | 2600 | { |
4670103e CZ |
2601 | case BFD_RELOC_ARC_TLS_DTPOFF: |
2602 | case BFD_RELOC_ARC_TLS_LE_32: | |
2603 | if (fixP->fx_done) | |
2604 | break; | |
2605 | /* Fall through. */ | |
2606 | case BFD_RELOC_ARC_TLS_GD_GOT: | |
2607 | case BFD_RELOC_ARC_TLS_IE_GOT: | |
2608 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2609 | break; | |
886a2506 | 2610 | |
4670103e CZ |
2611 | case BFD_RELOC_ARC_TLS_GD_LD: |
2612 | gas_assert (!fixP->fx_offset); | |
2613 | if (fixP->fx_subsy) | |
2614 | fixP->fx_offset | |
2615 | = (S_GET_VALUE (fixP->fx_subsy) | |
2616 | - fixP->fx_frag->fr_address- fixP->fx_where); | |
2617 | fixP->fx_subsy = NULL; | |
2618 | /* Fall through. */ | |
2619 | case BFD_RELOC_ARC_TLS_GD_CALL: | |
2620 | /* These two relocs are there just to allow ld to change the tls | |
2621 | model for this symbol, by patching the code. The offset - | |
2622 | and scale, if any - will be installed by the linker. */ | |
2623 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2624 | break; | |
886a2506 | 2625 | |
4670103e CZ |
2626 | case BFD_RELOC_ARC_TLS_LE_S9: |
2627 | case BFD_RELOC_ARC_TLS_DTPOFF_S9: | |
2628 | as_bad (_("TLS_*_S9 relocs are not supported yet")); | |
2629 | break; | |
2630 | ||
2631 | default: | |
2632 | break; | |
886a2506 NC |
2633 | } |
2634 | ||
4670103e | 2635 | if (!fixP->fx_done) |
886a2506 | 2636 | { |
4670103e | 2637 | return; |
886a2506 | 2638 | } |
886a2506 | 2639 | |
4670103e CZ |
2640 | /* Addjust the value if we have a constant. */ |
2641 | value += fx_offset; | |
886a2506 | 2642 | |
4670103e CZ |
2643 | /* For hosts with longs bigger than 32-bits make sure that the top |
2644 | bits of a 32-bit negative value read in by the parser are set, | |
2645 | so that the correct comparisons are made. */ | |
2646 | if (value & 0x80000000) | |
2647 | value |= (-1L << 31); | |
886a2506 | 2648 | |
4670103e CZ |
2649 | reloc = fixP->fx_r_type; |
2650 | switch (reloc) | |
2651 | { | |
2652 | case BFD_RELOC_8: | |
2653 | case BFD_RELOC_16: | |
2654 | case BFD_RELOC_24: | |
2655 | case BFD_RELOC_32: | |
2656 | case BFD_RELOC_64: | |
2657 | case BFD_RELOC_ARC_32_PCREL: | |
2658 | md_number_to_chars (fixpos, value, fixP->fx_size); | |
2659 | return; | |
886a2506 | 2660 | |
4670103e CZ |
2661 | case BFD_RELOC_ARC_GOTPC32: |
2662 | /* I cannot fix an GOTPC relocation because I need to relax it | |
2663 | from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */ | |
2664 | as_bad (_("Unsupported operation on reloc")); | |
2665 | return; | |
886a2506 | 2666 | |
4670103e CZ |
2667 | case BFD_RELOC_ARC_TLS_DTPOFF: |
2668 | case BFD_RELOC_ARC_TLS_LE_32: | |
2669 | gas_assert (!fixP->fx_addsy); | |
2670 | gas_assert (!fixP->fx_subsy); | |
886a2506 | 2671 | |
4670103e CZ |
2672 | case BFD_RELOC_ARC_GOTOFF: |
2673 | case BFD_RELOC_ARC_32_ME: | |
2674 | case BFD_RELOC_ARC_PC32: | |
2675 | md_number_to_chars_midend (fixpos, value, fixP->fx_size); | |
2676 | return; | |
886a2506 | 2677 | |
4670103e CZ |
2678 | case BFD_RELOC_ARC_PLT32: |
2679 | md_number_to_chars_midend (fixpos, value, fixP->fx_size); | |
2680 | return; | |
886a2506 | 2681 | |
4670103e CZ |
2682 | case BFD_RELOC_ARC_S25H_PCREL_PLT: |
2683 | reloc = BFD_RELOC_ARC_S25W_PCREL; | |
2684 | goto solve_plt; | |
886a2506 | 2685 | |
4670103e CZ |
2686 | case BFD_RELOC_ARC_S21H_PCREL_PLT: |
2687 | reloc = BFD_RELOC_ARC_S21H_PCREL; | |
2688 | goto solve_plt; | |
886a2506 | 2689 | |
4670103e CZ |
2690 | case BFD_RELOC_ARC_S25W_PCREL_PLT: |
2691 | reloc = BFD_RELOC_ARC_S25W_PCREL; | |
2692 | goto solve_plt; | |
886a2506 | 2693 | |
4670103e CZ |
2694 | case BFD_RELOC_ARC_S21W_PCREL_PLT: |
2695 | reloc = BFD_RELOC_ARC_S21W_PCREL; | |
886a2506 | 2696 | |
4670103e CZ |
2697 | case BFD_RELOC_ARC_S25W_PCREL: |
2698 | case BFD_RELOC_ARC_S21W_PCREL: | |
2699 | case BFD_RELOC_ARC_S21H_PCREL: | |
2700 | case BFD_RELOC_ARC_S25H_PCREL: | |
2701 | case BFD_RELOC_ARC_S13_PCREL: | |
2702 | solve_plt: | |
2703 | operand = find_operand_for_reloc (reloc); | |
2704 | gas_assert (operand); | |
886a2506 NC |
2705 | break; |
2706 | ||
2707 | default: | |
4670103e CZ |
2708 | { |
2709 | if ((int) fixP->fx_r_type >= 0) | |
2710 | as_fatal (_("unhandled relocation type %s"), | |
2711 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
886a2506 | 2712 | |
4670103e CZ |
2713 | /* The rest of these fixups needs to be completely resolved as |
2714 | constants. */ | |
2715 | if (fixP->fx_addsy != 0 | |
2716 | && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section) | |
2717 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2718 | _("non-absolute expression in constant field")); | |
886a2506 | 2719 | |
4670103e CZ |
2720 | gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands); |
2721 | operand = &arc_operands[-(int) fixP->fx_r_type]; | |
2722 | break; | |
2723 | } | |
2724 | } | |
886a2506 | 2725 | |
4670103e | 2726 | if (target_big_endian) |
886a2506 | 2727 | { |
4670103e | 2728 | switch (fixP->fx_size) |
886a2506 | 2729 | { |
4670103e CZ |
2730 | case 4: |
2731 | insn = bfd_getb32 (fixpos); | |
2732 | break; | |
2733 | case 2: | |
2734 | insn = bfd_getb16 (fixpos); | |
2735 | break; | |
2736 | default: | |
2737 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2738 | _("unknown fixup size")); | |
2739 | } | |
2740 | } | |
2741 | else | |
2742 | { | |
2743 | insn = 0; | |
2744 | switch (fixP->fx_size) | |
2745 | { | |
2746 | case 4: | |
2747 | insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2); | |
2748 | break; | |
2749 | case 2: | |
2750 | insn = bfd_getl16 (fixpos); | |
2751 | break; | |
2752 | default: | |
2753 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2754 | _("unknown fixup size")); | |
886a2506 NC |
2755 | } |
2756 | } | |
886a2506 | 2757 | |
4670103e CZ |
2758 | insn = insert_operand (insn, operand, (offsetT) value, |
2759 | fixP->fx_file, fixP->fx_line); | |
886a2506 | 2760 | |
4670103e CZ |
2761 | md_number_to_chars_midend (fixpos, insn, fixP->fx_size); |
2762 | } | |
886a2506 | 2763 | |
4670103e | 2764 | /* Prepare machine-dependent frags for relaxation. |
886a2506 | 2765 | |
4670103e CZ |
2766 | Called just before relaxation starts. Any symbol that is now undefined |
2767 | will not become defined. | |
886a2506 | 2768 | |
4670103e | 2769 | Return the correct fr_subtype in the frag. |
886a2506 | 2770 | |
4670103e CZ |
2771 | Return the initial "guess for fr_var" to caller. The guess for fr_var |
2772 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
2773 | or fr_var contributes to our returned value. | |
886a2506 | 2774 | |
4670103e CZ |
2775 | Although it may not be explicit in the frag, pretend |
2776 | fr_var starts with a value. */ | |
886a2506 | 2777 | |
4670103e CZ |
2778 | int |
2779 | md_estimate_size_before_relax (fragS *fragP, | |
2780 | segT segment) | |
2781 | { | |
2782 | int growth; | |
2783 | ||
2784 | /* If the symbol is not located within the same section AND it's not | |
2785 | an absolute section, use the maximum. OR if the symbol is a | |
2786 | constant AND the insn is by nature not pc-rel, use the maximum. | |
2787 | OR if the symbol is being equated against another symbol, use the | |
2788 | maximum. OR if the symbol is weak use the maximum. */ | |
2789 | if ((S_GET_SEGMENT (fragP->fr_symbol) != segment | |
2790 | && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
2791 | || (symbol_constant_p (fragP->fr_symbol) | |
2792 | && !fragP->tc_frag_data.pcrel) | |
2793 | || symbol_equated_p (fragP->fr_symbol) | |
2794 | || S_IS_WEAK (fragP->fr_symbol)) | |
2795 | { | |
2796 | while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE) | |
2797 | ++fragP->fr_subtype; | |
2798 | } | |
886a2506 | 2799 | |
4670103e CZ |
2800 | growth = md_relax_table[fragP->fr_subtype].rlx_length; |
2801 | fragP->fr_var = growth; | |
886a2506 | 2802 | |
4670103e CZ |
2803 | pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n", |
2804 | fragP->fr_file, fragP->fr_line, growth); | |
886a2506 | 2805 | |
4670103e CZ |
2806 | return growth; |
2807 | } | |
886a2506 | 2808 | |
4670103e CZ |
2809 | /* Translate internal representation of relocation info to BFD target |
2810 | format. */ | |
886a2506 | 2811 | |
4670103e CZ |
2812 | arelent * |
2813 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, | |
2814 | fixS *fixP) | |
2815 | { | |
2816 | arelent *reloc; | |
2817 | bfd_reloc_code_real_type code; | |
886a2506 | 2818 | |
4670103e CZ |
2819 | reloc = (arelent *) xmalloc (sizeof (* reloc)); |
2820 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2821 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2822 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
886a2506 | 2823 | |
4670103e CZ |
2824 | /* Make sure none of our internal relocations make it this far. |
2825 | They'd better have been fully resolved by this point. */ | |
2826 | gas_assert ((int) fixP->fx_r_type > 0); | |
886a2506 | 2827 | |
4670103e | 2828 | code = fixP->fx_r_type; |
886a2506 | 2829 | |
4670103e CZ |
2830 | /* if we have something like add gp, pcl, |
2831 | _GLOBAL_OFFSET_TABLE_@gotpc. */ | |
2832 | if (code == BFD_RELOC_ARC_GOTPC32 | |
2833 | && GOT_symbol | |
2834 | && fixP->fx_addsy == GOT_symbol) | |
2835 | code = BFD_RELOC_ARC_GOTPC; | |
886a2506 | 2836 | |
4670103e CZ |
2837 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
2838 | if (reloc->howto == NULL) | |
886a2506 | 2839 | { |
4670103e CZ |
2840 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2841 | _("cannot represent `%s' relocation in object file"), | |
2842 | bfd_get_reloc_code_name (code)); | |
2843 | return NULL; | |
2844 | } | |
886a2506 | 2845 | |
4670103e CZ |
2846 | if (!fixP->fx_pcrel != !reloc->howto->pc_relative) |
2847 | as_fatal (_("internal error? cannot generate `%s' relocation"), | |
2848 | bfd_get_reloc_code_name (code)); | |
886a2506 | 2849 | |
4670103e | 2850 | gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); |
886a2506 | 2851 | |
4670103e CZ |
2852 | if (code == BFD_RELOC_ARC_TLS_DTPOFF |
2853 | || code == BFD_RELOC_ARC_TLS_DTPOFF_S9) | |
2854 | { | |
2855 | asymbol *sym | |
2856 | = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL; | |
2857 | /* We just want to store a 24 bit index, but we have to wait | |
2858 | till after write_contents has been called via | |
2859 | bfd_map_over_sections before we can get the index from | |
2860 | _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs | |
2861 | function is elf32-arc.c has to pick up the slack. | |
2862 | Unfortunately, this leads to problems with hosts that have | |
2863 | pointers wider than long (bfd_vma). There would be various | |
2864 | ways to handle this, all error-prone :-( */ | |
2865 | reloc->addend = (bfd_vma) sym; | |
2866 | if ((asymbol *) reloc->addend != sym) | |
2867 | { | |
2868 | as_bad ("Can't store pointer\n"); | |
2869 | return NULL; | |
886a2506 NC |
2870 | } |
2871 | } | |
4670103e CZ |
2872 | else |
2873 | reloc->addend = fixP->fx_offset; | |
2874 | ||
2875 | return reloc; | |
886a2506 NC |
2876 | } |
2877 | ||
4670103e CZ |
2878 | /* Perform post-processing of machine-dependent frags after relaxation. |
2879 | Called after relaxation is finished. | |
2880 | In: Address of frag. | |
2881 | fr_type == rs_machine_dependent. | |
2882 | fr_subtype is what the address relaxed to. | |
886a2506 | 2883 | |
4670103e CZ |
2884 | Out: Any fixS:s and constants are set up. */ |
2885 | ||
2886 | void | |
2887 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, | |
2888 | segT segment ATTRIBUTE_UNUSED, | |
2889 | fragS *fragP) | |
886a2506 | 2890 | { |
4670103e CZ |
2891 | const relax_typeS *table_entry; |
2892 | char *dest; | |
2893 | const struct arc_opcode *opcode; | |
2894 | struct arc_insn insn; | |
2895 | int size, fix; | |
2896 | struct arc_relax_type *relax_arg = &fragP->tc_frag_data; | |
886a2506 | 2897 | |
4670103e CZ |
2898 | fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix); |
2899 | dest = fragP->fr_literal + fix; | |
2900 | table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype; | |
886a2506 | 2901 | |
4670103e CZ |
2902 | pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n", |
2903 | fragP->fr_file, fragP->fr_line, | |
2904 | fragP->fr_subtype, fix, fragP->fr_var); | |
886a2506 | 2905 | |
4670103e CZ |
2906 | if (fragP->fr_subtype <= 0 |
2907 | && fragP->fr_subtype >= arc_num_relax_opcodes) | |
2908 | as_fatal (_("no relaxation found for this instruction.")); | |
886a2506 | 2909 | |
4670103e | 2910 | opcode = &arc_relax_opcodes[fragP->fr_subtype]; |
886a2506 | 2911 | |
4670103e CZ |
2912 | assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags, |
2913 | relax_arg->nflg, &insn); | |
886a2506 | 2914 | |
4670103e | 2915 | apply_fixups (&insn, fragP, fix); |
886a2506 | 2916 | |
4670103e CZ |
2917 | size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4); |
2918 | gas_assert (table_entry->rlx_length == size); | |
2919 | emit_insn0 (&insn, dest, TRUE); | |
886a2506 | 2920 | |
4670103e CZ |
2921 | fragP->fr_fix += table_entry->rlx_length; |
2922 | fragP->fr_var = 0; | |
886a2506 NC |
2923 | } |
2924 | ||
4670103e CZ |
2925 | /* We have no need to default values of symbols. We could catch |
2926 | register names here, but that is handled by inserting them all in | |
2927 | the symbol table to begin with. */ | |
886a2506 | 2928 | |
4670103e CZ |
2929 | symbolS * |
2930 | md_undefined_symbol (char *name) | |
886a2506 | 2931 | { |
4670103e CZ |
2932 | /* The arc abi demands that a GOT[0] should be referencible as |
2933 | [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a | |
2934 | GOTPC reference to _GLOBAL_OFFSET_TABLE_. */ | |
2935 | if (((*name == '_') | |
2936 | && (*(name+1) == 'G') | |
2937 | && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)) | |
2938 | || ((*name == '_') | |
2939 | && (*(name+1) == 'D') | |
2940 | && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0))) | |
886a2506 | 2941 | { |
4670103e CZ |
2942 | if (!GOT_symbol) |
2943 | { | |
2944 | if (symbol_find (name)) | |
2945 | as_bad ("GOT already in symbol table"); | |
2946 | ||
2947 | GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section, | |
2948 | (valueT) 0, &zero_address_frag); | |
2949 | }; | |
2950 | return GOT_symbol; | |
886a2506 | 2951 | } |
4670103e | 2952 | return NULL; |
886a2506 NC |
2953 | } |
2954 | ||
4670103e CZ |
2955 | /* Turn a string in input_line_pointer into a floating point constant |
2956 | of type type, and store the appropriate bytes in *litP. The number | |
2957 | of LITTLENUMS emitted is stored in *sizeP. An error message is | |
2958 | returned, or NULL on OK. */ | |
886a2506 | 2959 | |
6d4af3c2 | 2960 | const char * |
4670103e | 2961 | md_atof (int type, char *litP, int *sizeP) |
886a2506 | 2962 | { |
4670103e CZ |
2963 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
2964 | } | |
886a2506 | 2965 | |
4670103e CZ |
2966 | /* Called for any expression that can not be recognized. When the |
2967 | function is called, `input_line_pointer' will point to the start of | |
2968 | the expression. */ | |
886a2506 | 2969 | |
4670103e CZ |
2970 | void |
2971 | md_operand (expressionS *expressionP ATTRIBUTE_UNUSED) | |
2972 | { | |
2973 | char *p = input_line_pointer; | |
2974 | if (*p == '@') | |
886a2506 | 2975 | { |
4670103e CZ |
2976 | input_line_pointer++; |
2977 | expressionP->X_op = O_symbol; | |
2978 | expression (expressionP); | |
2979 | } | |
2980 | } | |
886a2506 | 2981 | |
4670103e CZ |
2982 | /* This function is called from the function 'expression', it attempts |
2983 | to parse special names (in our case register names). It fills in | |
2984 | the expression with the identified register. It returns TRUE if | |
2985 | it is a register and FALSE otherwise. */ | |
886a2506 | 2986 | |
4670103e CZ |
2987 | bfd_boolean |
2988 | arc_parse_name (const char *name, | |
2989 | struct expressionS *e) | |
2990 | { | |
2991 | struct symbol *sym; | |
886a2506 | 2992 | |
4670103e CZ |
2993 | if (!assembling_insn) |
2994 | return FALSE; | |
886a2506 | 2995 | |
4670103e CZ |
2996 | /* Handle only registers. */ |
2997 | if (e->X_op != O_absent) | |
2998 | return FALSE; | |
886a2506 | 2999 | |
4670103e CZ |
3000 | sym = hash_find (arc_reg_hash, name); |
3001 | if (sym) | |
3002 | { | |
3003 | e->X_op = O_register; | |
3004 | e->X_add_number = S_GET_VALUE (sym); | |
3005 | return TRUE; | |
3006 | } | |
3007 | return FALSE; | |
3008 | } | |
886a2506 | 3009 | |
4670103e CZ |
3010 | /* md_parse_option |
3011 | Invocation line includes a switch not recognized by the base assembler. | |
3012 | See if it's a processor-specific option. | |
886a2506 | 3013 | |
4670103e | 3014 | New options (supported) are: |
886a2506 | 3015 | |
4670103e CZ |
3016 | -mcpu=<cpu name> Assemble for selected processor |
3017 | -EB/-mbig-endian Big-endian | |
3018 | -EL/-mlittle-endian Little-endian | |
3019 | -mrelax Enable relaxation | |
886a2506 | 3020 | |
4670103e CZ |
3021 | The following CPU names are recognized: |
3022 | arc700, av2em, av2hs. */ | |
886a2506 | 3023 | |
4670103e | 3024 | int |
17b9d67d | 3025 | md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) |
4670103e | 3026 | { |
4670103e CZ |
3027 | switch (c) |
3028 | { | |
3029 | case OPTION_ARC600: | |
3030 | case OPTION_ARC601: | |
3031 | return md_parse_option (OPTION_MCPU, "arc600"); | |
886a2506 | 3032 | |
4670103e CZ |
3033 | case OPTION_ARC700: |
3034 | return md_parse_option (OPTION_MCPU, "arc700"); | |
886a2506 | 3035 | |
4670103e CZ |
3036 | case OPTION_ARCEM: |
3037 | return md_parse_option (OPTION_MCPU, "arcem"); | |
886a2506 | 3038 | |
4670103e CZ |
3039 | case OPTION_ARCHS: |
3040 | return md_parse_option (OPTION_MCPU, "archs"); | |
886a2506 | 3041 | |
4670103e CZ |
3042 | case OPTION_MCPU: |
3043 | { | |
24740d83 AB |
3044 | arc_select_cpu (arg); |
3045 | mach_type_specified_p = 1; | |
4670103e CZ |
3046 | break; |
3047 | } | |
886a2506 | 3048 | |
4670103e CZ |
3049 | case OPTION_EB: |
3050 | arc_target_format = "elf32-bigarc"; | |
3051 | byte_order = BIG_ENDIAN; | |
3052 | break; | |
886a2506 | 3053 | |
4670103e CZ |
3054 | case OPTION_EL: |
3055 | arc_target_format = "elf32-littlearc"; | |
3056 | byte_order = LITTLE_ENDIAN; | |
3057 | break; | |
886a2506 | 3058 | |
4670103e CZ |
3059 | case OPTION_CD: |
3060 | /* This option has an effect only on ARC EM. */ | |
3061 | if (arc_target & ARC_OPCODE_ARCv2EM) | |
3062 | arc_features |= ARC_CD; | |
8ddf6b2a CZ |
3063 | else |
3064 | as_warn (_("Code density option invalid for selected CPU")); | |
4670103e | 3065 | break; |
886a2506 | 3066 | |
4670103e CZ |
3067 | case OPTION_RELAX: |
3068 | relaxation_state = 1; | |
3069 | break; | |
886a2506 | 3070 | |
4670103e CZ |
3071 | case OPTION_USER_MODE: |
3072 | case OPTION_LD_EXT_MASK: | |
3073 | case OPTION_SWAP: | |
3074 | case OPTION_NORM: | |
3075 | case OPTION_BARREL_SHIFT: | |
3076 | case OPTION_MIN_MAX: | |
3077 | case OPTION_NO_MPY: | |
3078 | case OPTION_EA: | |
3079 | case OPTION_MUL64: | |
3080 | case OPTION_SIMD: | |
8ddf6b2a CZ |
3081 | /* Dummy options are accepted but have no effect. */ |
3082 | break; | |
3083 | ||
4670103e | 3084 | case OPTION_SPFP: |
8ddf6b2a CZ |
3085 | arc_features |= ARC_SPFP; |
3086 | break; | |
3087 | ||
4670103e | 3088 | case OPTION_DPFP: |
8ddf6b2a CZ |
3089 | arc_features |= ARC_DPFP; |
3090 | break; | |
3091 | ||
4670103e CZ |
3092 | case OPTION_XMAC_D16: |
3093 | case OPTION_XMAC_24: | |
3094 | case OPTION_DSP_PACKA: | |
3095 | case OPTION_CRC: | |
3096 | case OPTION_DVBF: | |
3097 | case OPTION_TELEPHONY: | |
3098 | case OPTION_XYMEMORY: | |
3099 | case OPTION_LOCK: | |
3100 | case OPTION_SWAPE: | |
3101 | case OPTION_RTSC: | |
4670103e CZ |
3102 | /* Dummy options are accepted but have no effect. */ |
3103 | break; | |
886a2506 | 3104 | |
8ddf6b2a CZ |
3105 | case OPTION_FPUDA: |
3106 | /* This option has an effect only on ARC EM. */ | |
3107 | if (arc_target & ARC_OPCODE_ARCv2EM) | |
3108 | arc_features |= ARC_FPUDA; | |
3109 | else | |
3110 | as_warn (_("FPUDA invalid for selected CPU")); | |
3111 | break; | |
3112 | ||
4670103e CZ |
3113 | default: |
3114 | return 0; | |
3115 | } | |
886a2506 | 3116 | |
4670103e CZ |
3117 | return 1; |
3118 | } | |
886a2506 | 3119 | |
4670103e CZ |
3120 | void |
3121 | md_show_usage (FILE *stream) | |
3122 | { | |
3123 | fprintf (stream, _("ARC-specific assembler options:\n")); | |
886a2506 | 3124 | |
4670103e CZ |
3125 | fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n"); |
3126 | fprintf (stream, | |
3127 | " -mcode-density\t enable code density option for ARC EM\n"); | |
3128 | ||
3129 | fprintf (stream, _("\ | |
3130 | -EB assemble code for a big-endian cpu\n")); | |
3131 | fprintf (stream, _("\ | |
3132 | -EL assemble code for a little-endian cpu\n")); | |
3133 | fprintf (stream, _("\ | |
3134 | -mrelax Enable relaxation\n")); | |
886a2506 | 3135 | |
886a2506 NC |
3136 | } |
3137 | ||
3138 | /* Find the proper relocation for the given opcode. */ | |
3139 | ||
3140 | static extended_bfd_reloc_code_real_type | |
3141 | find_reloc (const char *name, | |
3142 | const char *opcodename, | |
3143 | const struct arc_flags *pflags, | |
3144 | int nflg, | |
3145 | extended_bfd_reloc_code_real_type reloc) | |
3146 | { | |
3147 | unsigned int i; | |
3148 | int j; | |
24b368f8 | 3149 | bfd_boolean found_flag, tmp; |
886a2506 NC |
3150 | extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED; |
3151 | ||
3152 | for (i = 0; i < arc_num_equiv_tab; i++) | |
3153 | { | |
3154 | const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i]; | |
3155 | ||
3156 | /* Find the entry. */ | |
3157 | if (strcmp (name, r->name)) | |
3158 | continue; | |
3159 | if (r->mnemonic && (strcmp (r->mnemonic, opcodename))) | |
3160 | continue; | |
24b368f8 | 3161 | if (r->flags[0]) |
886a2506 NC |
3162 | { |
3163 | if (!nflg) | |
3164 | continue; | |
3165 | found_flag = FALSE; | |
24b368f8 CZ |
3166 | unsigned * psflg = (unsigned *)r->flags; |
3167 | do | |
3168 | { | |
3169 | tmp = FALSE; | |
3170 | for (j = 0; j < nflg; j++) | |
3171 | if (!strcmp (pflags[j].name, | |
3172 | arc_flag_operands[*psflg].name)) | |
3173 | { | |
3174 | tmp = TRUE; | |
3175 | break; | |
3176 | } | |
3177 | if (!tmp) | |
3178 | { | |
3179 | found_flag = FALSE; | |
3180 | break; | |
3181 | } | |
3182 | else | |
3183 | { | |
3184 | found_flag = TRUE; | |
3185 | } | |
3186 | ++ psflg; | |
3187 | } while (*psflg); | |
3188 | ||
886a2506 NC |
3189 | if (!found_flag) |
3190 | continue; | |
3191 | } | |
3192 | ||
3193 | if (reloc != r->oldreloc) | |
3194 | continue; | |
3195 | /* Found it. */ | |
3196 | ret = r->newreloc; | |
3197 | break; | |
3198 | } | |
3199 | ||
3200 | if (ret == BFD_RELOC_UNUSED) | |
3201 | as_bad (_("Unable to find %s relocation for instruction %s"), | |
3202 | name, opcodename); | |
3203 | return ret; | |
3204 | } | |
3205 | ||
4670103e CZ |
3206 | /* All the symbol types that are allowed to be used for |
3207 | relaxation. */ | |
3208 | ||
3209 | static bfd_boolean | |
3210 | may_relax_expr (expressionS tok) | |
3211 | { | |
3212 | /* Check if we have unrelaxable relocs. */ | |
3213 | switch (tok.X_md) | |
3214 | { | |
3215 | default: | |
3216 | break; | |
3217 | case O_plt: | |
3218 | return FALSE; | |
3219 | } | |
3220 | ||
3221 | switch (tok.X_op) | |
3222 | { | |
3223 | case O_symbol: | |
3224 | case O_multiply: | |
3225 | case O_divide: | |
3226 | case O_modulus: | |
3227 | case O_add: | |
3228 | case O_subtract: | |
3229 | break; | |
3230 | ||
3231 | default: | |
3232 | return FALSE; | |
3233 | } | |
3234 | return TRUE; | |
3235 | } | |
3236 | ||
3237 | /* Checks if flags are in line with relaxable insn. */ | |
3238 | ||
3239 | static bfd_boolean | |
3240 | relaxable_flag (const struct arc_relaxable_ins *ins, | |
3241 | const struct arc_flags *pflags, | |
3242 | int nflgs) | |
3243 | { | |
3244 | unsigned flag_class, | |
3245 | flag, | |
3246 | flag_class_idx = 0, | |
3247 | flag_idx = 0; | |
3248 | ||
3249 | const struct arc_flag_operand *flag_opand; | |
3250 | int i, counttrue = 0; | |
3251 | ||
3252 | /* Iterate through flags classes. */ | |
3253 | while ((flag_class = ins->flag_classes[flag_class_idx]) != 0) | |
3254 | { | |
3255 | /* Iterate through flags in flag class. */ | |
3256 | while ((flag = arc_flag_classes[flag_class].flags[flag_idx]) | |
3257 | != 0) | |
3258 | { | |
3259 | flag_opand = &arc_flag_operands[flag]; | |
3260 | /* Iterate through flags in ins to compare. */ | |
3261 | for (i = 0; i < nflgs; ++i) | |
3262 | { | |
3263 | if (strcmp (flag_opand->name, pflags[i].name) == 0) | |
3264 | ++counttrue; | |
3265 | } | |
3266 | ||
3267 | ++flag_idx; | |
3268 | } | |
3269 | ||
3270 | ++flag_class_idx; | |
3271 | flag_idx = 0; | |
3272 | } | |
3273 | ||
3274 | /* If counttrue == nflgs, then all flags have been found. */ | |
3275 | return (counttrue == nflgs ? TRUE : FALSE); | |
3276 | } | |
3277 | ||
3278 | /* Checks if operands are in line with relaxable insn. */ | |
3279 | ||
3280 | static bfd_boolean | |
3281 | relaxable_operand (const struct arc_relaxable_ins *ins, | |
3282 | const expressionS *tok, | |
3283 | int ntok) | |
3284 | { | |
3285 | const enum rlx_operand_type *operand = &ins->operands[0]; | |
3286 | int i = 0; | |
3287 | ||
3288 | while (*operand != EMPTY) | |
3289 | { | |
3290 | const expressionS *epr = &tok[i]; | |
3291 | ||
3292 | if (i != 0 && i >= ntok) | |
3293 | return FALSE; | |
3294 | ||
3295 | switch (*operand) | |
3296 | { | |
3297 | case IMMEDIATE: | |
3298 | if (!(epr->X_op == O_multiply | |
3299 | || epr->X_op == O_divide | |
3300 | || epr->X_op == O_modulus | |
3301 | || epr->X_op == O_add | |
3302 | || epr->X_op == O_subtract | |
3303 | || epr->X_op == O_symbol)) | |
3304 | return FALSE; | |
3305 | break; | |
3306 | ||
3307 | case REGISTER_DUP: | |
3308 | if ((i <= 0) | |
3309 | || (epr->X_add_number != tok[i - 1].X_add_number)) | |
3310 | return FALSE; | |
3311 | /* Fall through. */ | |
3312 | case REGISTER: | |
3313 | if (epr->X_op != O_register) | |
3314 | return FALSE; | |
3315 | break; | |
3316 | ||
3317 | case REGISTER_S: | |
3318 | if (epr->X_op != O_register) | |
3319 | return FALSE; | |
3320 | ||
3321 | switch (epr->X_add_number) | |
3322 | { | |
3323 | case 0: case 1: case 2: case 3: | |
3324 | case 12: case 13: case 14: case 15: | |
3325 | break; | |
3326 | default: | |
3327 | return FALSE; | |
3328 | } | |
3329 | break; | |
3330 | ||
3331 | case REGISTER_NO_GP: | |
3332 | if ((epr->X_op != O_register) | |
3333 | || (epr->X_add_number == 26)) /* 26 is the gp register. */ | |
3334 | return FALSE; | |
3335 | break; | |
3336 | ||
3337 | case BRACKET: | |
3338 | if (epr->X_op != O_bracket) | |
3339 | return FALSE; | |
3340 | break; | |
3341 | ||
3342 | default: | |
3343 | /* Don't understand, bail out. */ | |
3344 | return FALSE; | |
3345 | break; | |
3346 | } | |
3347 | ||
3348 | ++i; | |
3349 | operand = &ins->operands[i]; | |
3350 | } | |
3351 | ||
3352 | return (i == ntok ? TRUE : FALSE); | |
3353 | } | |
3354 | ||
3355 | /* Return TRUE if this OPDCODE is a candidate for relaxation. */ | |
3356 | ||
3357 | static bfd_boolean | |
3358 | relax_insn_p (const struct arc_opcode *opcode, | |
3359 | const expressionS *tok, | |
3360 | int ntok, | |
3361 | const struct arc_flags *pflags, | |
3362 | int nflg) | |
3363 | { | |
3364 | unsigned i; | |
3365 | bfd_boolean rv = FALSE; | |
3366 | ||
3367 | /* Check the relaxation table. */ | |
3368 | for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i) | |
3369 | { | |
3370 | const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i]; | |
3371 | ||
3372 | if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0) | |
3373 | && may_relax_expr (tok[arc_rlx_ins->opcheckidx]) | |
3374 | && relaxable_operand (arc_rlx_ins, tok, ntok) | |
3375 | && relaxable_flag (arc_rlx_ins, pflags, nflg)) | |
3376 | { | |
3377 | rv = TRUE; | |
3378 | frag_now->fr_subtype = arc_relaxable_insns[i].subtype; | |
3379 | memcpy (&frag_now->tc_frag_data.tok, tok, | |
3380 | sizeof (expressionS) * ntok); | |
3381 | memcpy (&frag_now->tc_frag_data.pflags, pflags, | |
3382 | sizeof (struct arc_flags) * nflg); | |
3383 | frag_now->tc_frag_data.nflg = nflg; | |
3384 | frag_now->tc_frag_data.ntok = ntok; | |
3385 | break; | |
3386 | } | |
3387 | } | |
3388 | ||
3389 | return rv; | |
3390 | } | |
3391 | ||
886a2506 NC |
3392 | /* Turn an opcode description and a set of arguments into |
3393 | an instruction and a fixup. */ | |
3394 | ||
3395 | static void | |
3396 | assemble_insn (const struct arc_opcode *opcode, | |
3397 | const expressionS *tok, | |
3398 | int ntok, | |
3399 | const struct arc_flags *pflags, | |
3400 | int nflg, | |
3401 | struct arc_insn *insn) | |
3402 | { | |
3403 | const expressionS *reloc_exp = NULL; | |
3404 | unsigned image; | |
3405 | const unsigned char *argidx; | |
3406 | int i; | |
3407 | int tokidx = 0; | |
3408 | unsigned char pcrel = 0; | |
3409 | bfd_boolean needGOTSymbol; | |
3410 | bfd_boolean has_delay_slot = FALSE; | |
3411 | extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
3412 | ||
3413 | memset (insn, 0, sizeof (*insn)); | |
3414 | image = opcode->opcode; | |
3415 | ||
3416 | pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n", | |
3417 | frag_now->fr_file, frag_now->fr_line, opcode->name, | |
3418 | opcode->opcode); | |
3419 | ||
3420 | /* Handle operands. */ | |
3421 | for (argidx = opcode->operands; *argidx; ++argidx) | |
3422 | { | |
3423 | const struct arc_operand *operand = &arc_operands[*argidx]; | |
3424 | const expressionS *t = (const expressionS *) 0; | |
3425 | ||
3426 | if ((operand->flags & ARC_OPERAND_FAKE) | |
3427 | && !(operand->flags & ARC_OPERAND_BRAKET)) | |
3428 | continue; | |
3429 | ||
3430 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
3431 | { | |
3432 | /* Duplicate operand, already inserted. */ | |
3433 | tokidx ++; | |
3434 | continue; | |
3435 | } | |
3436 | ||
3437 | if (tokidx >= ntok) | |
3438 | { | |
3439 | abort (); | |
3440 | } | |
3441 | else | |
3442 | t = &tok[tokidx++]; | |
3443 | ||
3444 | /* Regardless if we have a reloc or not mark the instruction | |
3445 | limm if it is the case. */ | |
3446 | if (operand->flags & ARC_OPERAND_LIMM) | |
3447 | insn->has_limm = TRUE; | |
3448 | ||
3449 | switch (t->X_op) | |
3450 | { | |
3451 | case O_register: | |
3452 | image = insert_operand (image, operand, regno (t->X_add_number), | |
3453 | NULL, 0); | |
3454 | break; | |
3455 | ||
3456 | case O_constant: | |
3457 | image = insert_operand (image, operand, t->X_add_number, NULL, 0); | |
3458 | reloc_exp = t; | |
3459 | if (operand->flags & ARC_OPERAND_LIMM) | |
3460 | insn->limm = t->X_add_number; | |
3461 | break; | |
3462 | ||
3463 | case O_bracket: | |
3464 | /* Ignore brackets. */ | |
3465 | break; | |
3466 | ||
3467 | case O_absent: | |
3468 | gas_assert (operand->flags & ARC_OPERAND_IGNORE); | |
3469 | break; | |
3470 | ||
3471 | case O_subtract: | |
3472 | /* Maybe register range. */ | |
3473 | if ((t->X_add_number == 0) | |
3474 | && contains_register (t->X_add_symbol) | |
3475 | && contains_register (t->X_op_symbol)) | |
3476 | { | |
3477 | int regs; | |
3478 | ||
3479 | regs = get_register (t->X_add_symbol); | |
3480 | regs <<= 16; | |
3481 | regs |= get_register (t->X_op_symbol); | |
3482 | image = insert_operand (image, operand, regs, NULL, 0); | |
3483 | break; | |
3484 | } | |
3485 | ||
3486 | default: | |
3487 | /* This operand needs a relocation. */ | |
3488 | needGOTSymbol = FALSE; | |
3489 | ||
3490 | switch (t->X_md) | |
3491 | { | |
3492 | case O_plt: | |
6ec1f282 CZ |
3493 | if (opcode->class == JUMP) |
3494 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
3495 | _("Unable to use @plt relocatio for insn %s"), | |
3496 | opcode->name); | |
886a2506 NC |
3497 | needGOTSymbol = TRUE; |
3498 | reloc = find_reloc ("plt", opcode->name, | |
3499 | pflags, nflg, | |
3500 | operand->default_reloc); | |
3501 | break; | |
3502 | ||
3503 | case O_gotoff: | |
3504 | case O_gotpc: | |
3505 | needGOTSymbol = TRUE; | |
3506 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3507 | break; | |
3508 | case O_pcl: | |
3509 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
6ec1f282 | 3510 | if (ARC_SHORT (opcode->mask) || opcode->class == JUMP) |
886a2506 NC |
3511 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
3512 | _("Unable to use @pcl relocation for insn %s"), | |
3513 | opcode->name); | |
3514 | break; | |
3515 | case O_sda: | |
3516 | reloc = find_reloc ("sda", opcode->name, | |
3517 | pflags, nflg, | |
3518 | operand->default_reloc); | |
3519 | break; | |
3520 | case O_tlsgd: | |
3521 | case O_tlsie: | |
3522 | needGOTSymbol = TRUE; | |
3523 | /* Fall-through. */ | |
3524 | ||
3525 | case O_tpoff: | |
3526 | case O_dtpoff: | |
3527 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3528 | break; | |
3529 | ||
3530 | case O_tpoff9: /*FIXME! Check for the conditionality of | |
3531 | the insn. */ | |
3532 | case O_dtpoff9: /*FIXME! Check for the conditionality of | |
3533 | the insn. */ | |
3534 | as_bad (_("TLS_*_S9 relocs are not supported yet")); | |
3535 | break; | |
3536 | ||
3537 | default: | |
3538 | /* Just consider the default relocation. */ | |
3539 | reloc = operand->default_reloc; | |
3540 | break; | |
3541 | } | |
3542 | ||
3543 | if (needGOTSymbol && (GOT_symbol == NULL)) | |
3544 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3545 | ||
3546 | reloc_exp = t; | |
3547 | ||
3548 | #if 0 | |
3549 | if (reloc > 0) | |
3550 | { | |
3551 | /* sanity checks. */ | |
3552 | reloc_howto_type *reloc_howto | |
3553 | = bfd_reloc_type_lookup (stdoutput, | |
3554 | (bfd_reloc_code_real_type) reloc); | |
3555 | unsigned reloc_bitsize = reloc_howto->bitsize; | |
3556 | if (reloc_howto->rightshift) | |
3557 | reloc_bitsize -= reloc_howto->rightshift; | |
3558 | if (reloc_bitsize != operand->bits) | |
3559 | { | |
3560 | as_bad (_("invalid relocation %s for field"), | |
3561 | bfd_get_reloc_code_name (reloc)); | |
3562 | return; | |
3563 | } | |
3564 | } | |
3565 | #endif | |
3566 | if (insn->nfixups >= MAX_INSN_FIXUPS) | |
3567 | as_fatal (_("too many fixups")); | |
3568 | ||
3569 | struct arc_fixup *fixup; | |
3570 | fixup = &insn->fixups[insn->nfixups++]; | |
3571 | fixup->exp = *t; | |
3572 | fixup->reloc = reloc; | |
3573 | pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0; | |
3574 | fixup->pcrel = pcrel; | |
3575 | fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ? | |
3576 | TRUE : FALSE; | |
3577 | break; | |
3578 | } | |
3579 | } | |
3580 | ||
3581 | /* Handle flags. */ | |
3582 | for (i = 0; i < nflg; i++) | |
3583 | { | |
3584 | const struct arc_flag_operand *flg_operand = | |
3585 | &arc_flag_operands[pflags[i].code]; | |
3586 | ||
3587 | /* Check if the instruction has a delay slot. */ | |
3588 | if (!strcmp (flg_operand->name, "d")) | |
3589 | has_delay_slot = TRUE; | |
3590 | ||
3591 | /* There is an exceptional case when we cannot insert a flag | |
3592 | just as it is. The .T flag must be handled in relation with | |
3593 | the relative address. */ | |
3594 | if (!strcmp (flg_operand->name, "t") | |
3595 | || !strcmp (flg_operand->name, "nt")) | |
3596 | { | |
3597 | unsigned bitYoperand = 0; | |
3598 | /* FIXME! move selection bbit/brcc in arc-opc.c. */ | |
3599 | if (!strcmp (flg_operand->name, "t")) | |
3600 | if (!strcmp (opcode->name, "bbit0") | |
3601 | || !strcmp (opcode->name, "bbit1")) | |
3602 | bitYoperand = arc_NToperand; | |
3603 | else | |
3604 | bitYoperand = arc_Toperand; | |
3605 | else | |
3606 | if (!strcmp (opcode->name, "bbit0") | |
3607 | || !strcmp (opcode->name, "bbit1")) | |
3608 | bitYoperand = arc_Toperand; | |
3609 | else | |
3610 | bitYoperand = arc_NToperand; | |
3611 | ||
3612 | gas_assert (reloc_exp != NULL); | |
3613 | if (reloc_exp->X_op == O_constant) | |
3614 | { | |
3615 | /* Check if we have a constant and solved it | |
3616 | immediately. */ | |
3617 | offsetT val = reloc_exp->X_add_number; | |
3618 | image |= insert_operand (image, &arc_operands[bitYoperand], | |
3619 | val, NULL, 0); | |
3620 | } | |
3621 | else | |
3622 | { | |
3623 | struct arc_fixup *fixup; | |
3624 | ||
3625 | if (insn->nfixups >= MAX_INSN_FIXUPS) | |
3626 | as_fatal (_("too many fixups")); | |
3627 | ||
3628 | fixup = &insn->fixups[insn->nfixups++]; | |
3629 | fixup->exp = *reloc_exp; | |
3630 | fixup->reloc = -bitYoperand; | |
3631 | fixup->pcrel = pcrel; | |
3632 | fixup->islong = FALSE; | |
3633 | } | |
3634 | } | |
3635 | else | |
3636 | image |= (flg_operand->code & ((1 << flg_operand->bits) - 1)) | |
3637 | << flg_operand->shift; | |
3638 | } | |
3639 | ||
4670103e CZ |
3640 | insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg); |
3641 | ||
886a2506 NC |
3642 | /* Short instruction? */ |
3643 | insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE; | |
3644 | ||
3645 | insn->insn = image; | |
3646 | ||
3647 | /* Update last insn status. */ | |
3648 | arc_last_insns[1] = arc_last_insns[0]; | |
3649 | arc_last_insns[0].opcode = opcode; | |
3650 | arc_last_insns[0].has_limm = insn->has_limm; | |
3651 | arc_last_insns[0].has_delay_slot = has_delay_slot; | |
3652 | ||
3653 | /* Check if the current instruction is legally used. */ | |
3654 | if (arc_last_insns[1].has_delay_slot | |
3655 | && is_br_jmp_insn_p (arc_last_insns[0].opcode)) | |
3656 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
3657 | _("A jump/branch instruction in delay slot.")); | |
3658 | } | |
3659 | ||
886a2506 NC |
3660 | void |
3661 | arc_handle_align (fragS* fragP) | |
3662 | { | |
3663 | if ((fragP)->fr_type == rs_align_code) | |
3664 | { | |
3665 | char *dest = (fragP)->fr_literal + (fragP)->fr_fix; | |
3666 | valueT count = ((fragP)->fr_next->fr_address | |
3667 | - (fragP)->fr_address - (fragP)->fr_fix); | |
3668 | ||
3669 | (fragP)->fr_var = 2; | |
3670 | ||
3671 | if (count & 1)/* Padding in the gap till the next 2-byte | |
3672 | boundary with 0s. */ | |
3673 | { | |
3674 | (fragP)->fr_fix++; | |
3675 | *dest++ = 0; | |
3676 | } | |
3677 | /* Writing nop_s. */ | |
3678 | md_number_to_chars (dest, NOP_OPCODE_S, 2); | |
3679 | } | |
3680 | } | |
3681 | ||
3682 | /* Here we decide which fixups can be adjusted to make them relative | |
3683 | to the beginning of the section instead of the symbol. Basically | |
3684 | we need to make sure that the dynamic relocations are done | |
3685 | correctly, so in some cases we force the original symbol to be | |
3686 | used. */ | |
3687 | ||
3688 | int | |
3689 | tc_arc_fix_adjustable (fixS *fixP) | |
3690 | { | |
3691 | ||
3692 | /* Prevent all adjustments to global symbols. */ | |
3693 | if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
3694 | return 0; | |
3695 | if (S_IS_WEAK (fixP->fx_addsy)) | |
3696 | return 0; | |
3697 | ||
3698 | /* Adjust_reloc_syms doesn't know about the GOT. */ | |
3699 | switch (fixP->fx_r_type) | |
3700 | { | |
3701 | case BFD_RELOC_ARC_GOTPC32: | |
3702 | case BFD_RELOC_ARC_PLT32: | |
3703 | case BFD_RELOC_ARC_S25H_PCREL_PLT: | |
3704 | case BFD_RELOC_ARC_S21H_PCREL_PLT: | |
3705 | case BFD_RELOC_ARC_S25W_PCREL_PLT: | |
3706 | case BFD_RELOC_ARC_S21W_PCREL_PLT: | |
3707 | return 0; | |
3708 | ||
3709 | default: | |
3710 | break; | |
3711 | } | |
3712 | ||
841fdfcd | 3713 | return 1; |
886a2506 NC |
3714 | } |
3715 | ||
3716 | /* Compute the reloc type of an expression EXP. */ | |
3717 | ||
3718 | static void | |
3719 | arc_check_reloc (expressionS *exp, | |
3720 | bfd_reloc_code_real_type *r_type_p) | |
3721 | { | |
3722 | if (*r_type_p == BFD_RELOC_32 | |
3723 | && exp->X_op == O_subtract | |
3724 | && exp->X_op_symbol != NULL | |
3725 | && exp->X_op_symbol->bsym->section == now_seg) | |
6f4b1afc | 3726 | *r_type_p = BFD_RELOC_ARC_32_PCREL; |
886a2506 NC |
3727 | } |
3728 | ||
3729 | ||
3730 | /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */ | |
3731 | ||
3732 | void | |
3733 | arc_cons_fix_new (fragS *frag, | |
3734 | int off, | |
3735 | int size, | |
3736 | expressionS *exp, | |
3737 | bfd_reloc_code_real_type r_type) | |
3738 | { | |
3739 | r_type = BFD_RELOC_UNUSED; | |
3740 | ||
3741 | switch (size) | |
3742 | { | |
3743 | case 1: | |
3744 | r_type = BFD_RELOC_8; | |
3745 | break; | |
3746 | ||
3747 | case 2: | |
3748 | r_type = BFD_RELOC_16; | |
3749 | break; | |
3750 | ||
3751 | case 3: | |
3752 | r_type = BFD_RELOC_24; | |
3753 | break; | |
3754 | ||
3755 | case 4: | |
3756 | r_type = BFD_RELOC_32; | |
3757 | arc_check_reloc (exp, &r_type); | |
3758 | break; | |
3759 | ||
3760 | case 8: | |
3761 | r_type = BFD_RELOC_64; | |
3762 | break; | |
3763 | ||
3764 | default: | |
3765 | as_bad (_("unsupported BFD relocation size %u"), size); | |
3766 | r_type = BFD_RELOC_UNUSED; | |
3767 | } | |
3768 | ||
3769 | fix_new_exp (frag, off, size, exp, 0, r_type); | |
3770 | } | |
3771 | ||
3772 | /* The actual routine that checks the ZOL conditions. */ | |
3773 | ||
3774 | static void | |
3775 | check_zol (symbolS *s) | |
3776 | { | |
3777 | switch (arc_mach_type) | |
3778 | { | |
3779 | case bfd_mach_arc_arcv2: | |
3780 | if (arc_target & ARC_OPCODE_ARCv2EM) | |
3781 | return; | |
3782 | ||
3783 | if (is_br_jmp_insn_p (arc_last_insns[0].opcode) | |
3784 | || arc_last_insns[1].has_delay_slot) | |
3785 | as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"), | |
3786 | S_GET_NAME (s)); | |
3787 | ||
3788 | break; | |
3789 | case bfd_mach_arc_arc600: | |
3790 | ||
3791 | if (is_kernel_insn_p (arc_last_insns[0].opcode)) | |
3792 | as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"), | |
3793 | S_GET_NAME (s)); | |
3794 | ||
3795 | if (arc_last_insns[0].has_limm | |
3796 | && is_br_jmp_insn_p (arc_last_insns[0].opcode)) | |
3797 | as_bad (_("A jump instruction with long immediate detected at the \ | |
3798 | end of the ZOL label @%s"), S_GET_NAME (s)); | |
3799 | ||
3800 | /* Fall through. */ | |
8699fc3e | 3801 | case bfd_mach_arc_nps400: |
886a2506 NC |
3802 | case bfd_mach_arc_arc700: |
3803 | if (arc_last_insns[0].has_delay_slot) | |
3804 | as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"), | |
3805 | S_GET_NAME (s)); | |
3806 | ||
3807 | break; | |
3808 | default: | |
3809 | break; | |
3810 | } | |
3811 | } | |
3812 | ||
3813 | /* If ZOL end check the last two instruction for illegals. */ | |
3814 | void | |
3815 | arc_frob_label (symbolS * sym) | |
3816 | { | |
3817 | if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL) | |
3818 | check_zol (sym); | |
3819 | ||
3820 | dwarf2_emit_label (sym); | |
ea1562b3 | 3821 | } |
4670103e CZ |
3822 | |
3823 | /* Used because generic relaxation assumes a pc-rel value whilst we | |
3824 | also relax instructions that use an absolute value resolved out of | |
3825 | relative values (if that makes any sense). An example: 'add r1, | |
3826 | r2, @.L2 - .' The symbols . and @.L2 are relative to the section | |
3827 | but if they're in the same section we can subtract the section | |
3828 | offset relocation which ends up in a resolved value. So if @.L2 is | |
3829 | .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 - | |
3830 | .text + 0x40 = 0x10. */ | |
3831 | int | |
3832 | arc_pcrel_adjust (fragS *fragP) | |
3833 | { | |
3834 | if (!fragP->tc_frag_data.pcrel) | |
3835 | return fragP->fr_address + fragP->fr_fix; | |
3836 | ||
3837 | return 0; | |
3838 | } | |
726c18e1 CZ |
3839 | |
3840 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
3841 | ||
3842 | void | |
3843 | tc_arc_frame_initial_instructions (void) | |
3844 | { | |
3845 | /* Stack pointer is register 28. */ | |
3846 | cfi_add_CFA_def_cfa_register (28); | |
3847 | } | |
3848 | ||
3849 | int | |
3850 | tc_arc_regname_to_dw2regnum (char *regname) | |
3851 | { | |
3852 | struct symbol *sym; | |
3853 | ||
3854 | sym = hash_find (arc_reg_hash, regname); | |
3855 | if (sym) | |
3856 | return S_GET_VALUE (sym); | |
3857 | ||
3858 | return -1; | |
3859 | } |