Commit | Line | Data |
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252b5132 | 1 | /* tc-arc.c -- Assembler for the ARC |
6f2750fe | 2 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributor: Claudiu Zissulescu <claziss@synopsys.com> | |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19203624 | 19 | along with GAS; see the file COPYING. If not, write to the Free |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
886a2506 | 24 | #include "subsegs.h" |
a161fe53 | 25 | #include "struc-symbol.h" |
886a2506 | 26 | #include "dwarf2dbg.h" |
726c18e1 | 27 | #include "dw2gencfi.h" |
3882b010 | 28 | #include "safe-ctype.h" |
886a2506 | 29 | |
252b5132 RH |
30 | #include "opcode/arc.h" |
31 | #include "elf/arc.h" | |
32 | ||
886a2506 | 33 | /* Defines section. */ |
0d2bcfaf | 34 | |
886a2506 NC |
35 | #define MAX_INSN_FIXUPS 2 |
36 | #define MAX_CONSTR_STR 20 | |
4670103e | 37 | #define FRAG_MAX_GROWTH 8 |
0d2bcfaf | 38 | |
886a2506 NC |
39 | #ifdef DEBUG |
40 | # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args) | |
41 | #else | |
42 | # define pr_debug(fmt, args...) | |
43 | #endif | |
44 | ||
45 | #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27) | |
46 | #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16) | |
4670103e | 47 | #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \ |
886a2506 NC |
48 | (SUB_OPCODE (x) == 0x28)) |
49 | ||
50 | /* Equal to MAX_PRECISION in atof-ieee.c. */ | |
51 | #define MAX_LITTLENUMS 6 | |
52 | ||
4670103e CZ |
53 | /* Enum used to enumerate the relaxable ins operands. */ |
54 | enum rlx_operand_type | |
55 | { | |
56 | EMPTY = 0, | |
57 | REGISTER, | |
58 | REGISTER_S, /* Register for short instruction(s). */ | |
59 | REGISTER_NO_GP, /* Is a register but not gp register specifically. */ | |
60 | REGISTER_DUP, /* Duplication of previous operand of type register. */ | |
61 | IMMEDIATE, | |
62 | BRACKET | |
63 | }; | |
64 | ||
65 | enum arc_rlx_types | |
66 | { | |
67 | ARC_RLX_NONE = 0, | |
68 | ARC_RLX_BL_S, | |
69 | ARC_RLX_BL, | |
70 | ARC_RLX_B_S, | |
71 | ARC_RLX_B, | |
72 | ARC_RLX_ADD_U3, | |
73 | ARC_RLX_ADD_U6, | |
74 | ARC_RLX_ADD_LIMM, | |
75 | ARC_RLX_LD_U7, | |
76 | ARC_RLX_LD_S9, | |
77 | ARC_RLX_LD_LIMM, | |
78 | ARC_RLX_MOV_U8, | |
79 | ARC_RLX_MOV_S12, | |
80 | ARC_RLX_MOV_LIMM, | |
81 | ARC_RLX_SUB_U3, | |
82 | ARC_RLX_SUB_U6, | |
83 | ARC_RLX_SUB_LIMM, | |
84 | ARC_RLX_MPY_U6, | |
85 | ARC_RLX_MPY_LIMM, | |
86 | ARC_RLX_MOV_RU6, | |
87 | ARC_RLX_MOV_RLIMM, | |
88 | ARC_RLX_ADD_RRU6, | |
89 | ARC_RLX_ADD_RRLIMM, | |
90 | }; | |
91 | ||
886a2506 NC |
92 | /* Macros section. */ |
93 | ||
94 | #define regno(x) ((x) & 0x3F) | |
95 | #define is_ir_num(x) (((x) & ~0x3F) == 0) | |
96 | #define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2)) | |
97 | #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP)) | |
98 | #define is_kernel_insn_p(op) (((op)->class == KERNEL)) | |
0d2bcfaf | 99 | |
886a2506 NC |
100 | /* Generic assembler global variables which must be defined by all |
101 | targets. */ | |
0d2bcfaf | 102 | |
886a2506 | 103 | /* Characters which always start a comment. */ |
252b5132 RH |
104 | const char comment_chars[] = "#;"; |
105 | ||
886a2506 | 106 | /* Characters which start a comment at the beginning of a line. */ |
252b5132 RH |
107 | const char line_comment_chars[] = "#"; |
108 | ||
886a2506 NC |
109 | /* Characters which may be used to separate multiple commands on a |
110 | single line. */ | |
111 | const char line_separator_chars[] = "`"; | |
252b5132 | 112 | |
886a2506 NC |
113 | /* Characters which are used to indicate an exponent in a floating |
114 | point number. */ | |
252b5132 RH |
115 | const char EXP_CHARS[] = "eE"; |
116 | ||
bcee8eb8 AM |
117 | /* Chars that mean this number is a floating point constant |
118 | As in 0f12.456 or 0d1.2345e12. */ | |
252b5132 RH |
119 | const char FLT_CHARS[] = "rRsSfFdD"; |
120 | ||
121 | /* Byte order. */ | |
122 | extern int target_big_endian; | |
123 | const char *arc_target_format = DEFAULT_TARGET_FORMAT; | |
124 | static int byte_order = DEFAULT_BYTE_ORDER; | |
125 | ||
4670103e CZ |
126 | /* By default relaxation is disabled. */ |
127 | static int relaxation_state = 0; | |
128 | ||
886a2506 | 129 | extern int arc_get_mach (char *); |
0d2bcfaf | 130 | |
4670103e | 131 | /* Forward declarations. */ |
886a2506 NC |
132 | static void arc_lcomm (int); |
133 | static void arc_option (int); | |
134 | static void arc_extra_reloc (int); | |
252b5132 | 135 | |
4670103e | 136 | |
886a2506 | 137 | const pseudo_typeS md_pseudo_table[] = |
6f4b1afc CM |
138 | { |
139 | /* Make sure that .word is 32 bits. */ | |
140 | { "word", cons, 4 }, | |
886a2506 | 141 | |
6f4b1afc CM |
142 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
143 | { "lcomm", arc_lcomm, 0 }, | |
144 | { "lcommon", arc_lcomm, 0 }, | |
145 | { "cpu", arc_option, 0 }, | |
252b5132 | 146 | |
6f4b1afc CM |
147 | { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD }, |
148 | { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL }, | |
886a2506 | 149 | |
6f4b1afc CM |
150 | { NULL, NULL, 0 } |
151 | }; | |
252b5132 | 152 | |
252b5132 | 153 | const char *md_shortopts = ""; |
ea1562b3 NC |
154 | |
155 | enum options | |
6f4b1afc CM |
156 | { |
157 | OPTION_EB = OPTION_MD_BASE, | |
158 | OPTION_EL, | |
159 | ||
160 | OPTION_ARC600, | |
161 | OPTION_ARC601, | |
162 | OPTION_ARC700, | |
163 | OPTION_ARCEM, | |
164 | OPTION_ARCHS, | |
165 | ||
166 | OPTION_MCPU, | |
167 | OPTION_CD, | |
4670103e | 168 | OPTION_RELAX, |
6f4b1afc CM |
169 | |
170 | /* The following options are deprecated and provided here only for | |
171 | compatibility reasons. */ | |
172 | OPTION_USER_MODE, | |
173 | OPTION_LD_EXT_MASK, | |
174 | OPTION_SWAP, | |
175 | OPTION_NORM, | |
176 | OPTION_BARREL_SHIFT, | |
177 | OPTION_MIN_MAX, | |
178 | OPTION_NO_MPY, | |
179 | OPTION_EA, | |
180 | OPTION_MUL64, | |
181 | OPTION_SIMD, | |
182 | OPTION_SPFP, | |
183 | OPTION_DPFP, | |
184 | OPTION_XMAC_D16, | |
185 | OPTION_XMAC_24, | |
186 | OPTION_DSP_PACKA, | |
187 | OPTION_CRC, | |
188 | OPTION_DVBF, | |
189 | OPTION_TELEPHONY, | |
190 | OPTION_XYMEMORY, | |
191 | OPTION_LOCK, | |
192 | OPTION_SWAPE, | |
193 | OPTION_RTSC, | |
194 | OPTION_FPUDA | |
195 | }; | |
ea1562b3 NC |
196 | |
197 | struct option md_longopts[] = | |
6f4b1afc CM |
198 | { |
199 | { "EB", no_argument, NULL, OPTION_EB }, | |
200 | { "EL", no_argument, NULL, OPTION_EL }, | |
201 | { "mcpu", required_argument, NULL, OPTION_MCPU }, | |
202 | { "mA6", no_argument, NULL, OPTION_ARC600 }, | |
24b368f8 CZ |
203 | { "mARC600", no_argument, NULL, OPTION_ARC600 }, |
204 | { "mARC601", no_argument, NULL, OPTION_ARC601 }, | |
205 | { "mARC700", no_argument, NULL, OPTION_ARC700 }, | |
6f4b1afc CM |
206 | { "mA7", no_argument, NULL, OPTION_ARC700 }, |
207 | { "mEM", no_argument, NULL, OPTION_ARCEM }, | |
208 | { "mHS", no_argument, NULL, OPTION_ARCHS }, | |
209 | { "mcode-density", no_argument, NULL, OPTION_CD }, | |
4670103e | 210 | { "mrelax", no_argument, NULL, OPTION_RELAX }, |
6f4b1afc CM |
211 | |
212 | /* The following options are deprecated and provided here only for | |
213 | compatibility reasons. */ | |
214 | { "mav2em", no_argument, NULL, OPTION_ARCEM }, | |
215 | { "mav2hs", no_argument, NULL, OPTION_ARCHS }, | |
216 | { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE }, | |
217 | { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK }, | |
218 | { "mswap", no_argument, NULL, OPTION_SWAP }, | |
219 | { "mnorm", no_argument, NULL, OPTION_NORM }, | |
220 | { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, | |
221 | { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, | |
222 | { "mmin-max", no_argument, NULL, OPTION_MIN_MAX }, | |
223 | { "mmin_max", no_argument, NULL, OPTION_MIN_MAX }, | |
224 | { "mno-mpy", no_argument, NULL, OPTION_NO_MPY }, | |
225 | { "mea", no_argument, NULL, OPTION_EA }, | |
226 | { "mEA", no_argument, NULL, OPTION_EA }, | |
227 | { "mmul64", no_argument, NULL, OPTION_MUL64 }, | |
228 | { "msimd", no_argument, NULL, OPTION_SIMD}, | |
229 | { "mspfp", no_argument, NULL, OPTION_SPFP}, | |
230 | { "mspfp-compact", no_argument, NULL, OPTION_SPFP}, | |
231 | { "mspfp_compact", no_argument, NULL, OPTION_SPFP}, | |
232 | { "mspfp-fast", no_argument, NULL, OPTION_SPFP}, | |
233 | { "mspfp_fast", no_argument, NULL, OPTION_SPFP}, | |
234 | { "mdpfp", no_argument, NULL, OPTION_DPFP}, | |
235 | { "mdpfp-compact", no_argument, NULL, OPTION_DPFP}, | |
236 | { "mdpfp_compact", no_argument, NULL, OPTION_DPFP}, | |
237 | { "mdpfp-fast", no_argument, NULL, OPTION_DPFP}, | |
238 | { "mdpfp_fast", no_argument, NULL, OPTION_DPFP}, | |
239 | { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16}, | |
240 | { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16}, | |
241 | { "mmac-24", no_argument, NULL, OPTION_XMAC_24}, | |
242 | { "mmac_24", no_argument, NULL, OPTION_XMAC_24}, | |
243 | { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA}, | |
244 | { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA}, | |
245 | { "mcrc", no_argument, NULL, OPTION_CRC}, | |
246 | { "mdvbf", no_argument, NULL, OPTION_DVBF}, | |
247 | { "mtelephony", no_argument, NULL, OPTION_TELEPHONY}, | |
248 | { "mxy", no_argument, NULL, OPTION_XYMEMORY}, | |
249 | { "mlock", no_argument, NULL, OPTION_LOCK}, | |
250 | { "mswape", no_argument, NULL, OPTION_SWAPE}, | |
251 | { "mrtsc", no_argument, NULL, OPTION_RTSC}, | |
252 | { "mfpuda", no_argument, NULL, OPTION_FPUDA}, | |
253 | ||
254 | { NULL, no_argument, NULL, 0 } | |
255 | }; | |
252b5132 | 256 | |
886a2506 | 257 | size_t md_longopts_size = sizeof (md_longopts); |
0d2bcfaf | 258 | |
886a2506 | 259 | /* Local data and data types. */ |
252b5132 | 260 | |
886a2506 NC |
261 | /* Used since new relocation types are introduced in this |
262 | file (DUMMY_RELOC_LITUSE_*). */ | |
263 | typedef int extended_bfd_reloc_code_real_type; | |
252b5132 | 264 | |
886a2506 | 265 | struct arc_fixup |
252b5132 | 266 | { |
886a2506 | 267 | expressionS exp; |
252b5132 | 268 | |
886a2506 | 269 | extended_bfd_reloc_code_real_type reloc; |
252b5132 | 270 | |
886a2506 NC |
271 | /* index into arc_operands. */ |
272 | unsigned int opindex; | |
252b5132 | 273 | |
886a2506 NC |
274 | /* PC-relative, used by internals fixups. */ |
275 | unsigned char pcrel; | |
252b5132 | 276 | |
886a2506 NC |
277 | /* TRUE if this fixup is for LIMM operand. */ |
278 | bfd_boolean islong; | |
279 | }; | |
252b5132 | 280 | |
886a2506 NC |
281 | struct arc_insn |
282 | { | |
283 | unsigned int insn; | |
284 | int nfixups; | |
285 | struct arc_fixup fixups[MAX_INSN_FIXUPS]; | |
286 | long limm; | |
287 | bfd_boolean short_insn; /* Boolean value: TRUE if current insn is | |
288 | short. */ | |
289 | bfd_boolean has_limm; /* Boolean value: TRUE if limm field is | |
290 | valid. */ | |
4670103e CZ |
291 | bfd_boolean relax; /* Boolean value: TRUE if needs |
292 | relaxation. */ | |
886a2506 | 293 | }; |
ea1562b3 | 294 | |
886a2506 NC |
295 | /* Structure to hold any last two instructions. */ |
296 | static struct arc_last_insn | |
252b5132 | 297 | { |
886a2506 NC |
298 | /* Saved instruction opcode. */ |
299 | const struct arc_opcode *opcode; | |
252b5132 | 300 | |
886a2506 NC |
301 | /* Boolean value: TRUE if current insn is short. */ |
302 | bfd_boolean has_limm; | |
252b5132 | 303 | |
886a2506 NC |
304 | /* Boolean value: TRUE if current insn has delay slot. */ |
305 | bfd_boolean has_delay_slot; | |
306 | } arc_last_insns[2]; | |
252b5132 | 307 | |
4670103e CZ |
308 | /* Forward declaration. */ |
309 | static void assemble_insn | |
310 | (const struct arc_opcode *, const expressionS *, int, | |
311 | const struct arc_flags *, int, struct arc_insn *); | |
312 | ||
886a2506 NC |
313 | /* The cpu for which we are generating code. */ |
314 | static unsigned arc_target = ARC_OPCODE_BASE; | |
315 | static const char *arc_target_name = "<all>"; | |
316 | static unsigned arc_features = 0x00; | |
252b5132 | 317 | |
886a2506 NC |
318 | /* The default architecture. */ |
319 | static int arc_mach_type = bfd_mach_arc_arcv2; | |
252b5132 | 320 | |
886a2506 NC |
321 | /* Non-zero if the cpu type has been explicitly specified. */ |
322 | static int mach_type_specified_p = 0; | |
0d2bcfaf | 323 | |
886a2506 NC |
324 | /* The hash table of instruction opcodes. */ |
325 | static struct hash_control *arc_opcode_hash; | |
0d2bcfaf | 326 | |
886a2506 NC |
327 | /* The hash table of register symbols. */ |
328 | static struct hash_control *arc_reg_hash; | |
252b5132 | 329 | |
886a2506 NC |
330 | /* A table of CPU names and opcode sets. */ |
331 | static const struct cpu_type | |
332 | { | |
333 | const char *name; | |
334 | unsigned flags; | |
335 | int mach; | |
336 | unsigned eflags; | |
337 | unsigned features; | |
252b5132 | 338 | } |
886a2506 | 339 | cpu_types[] = |
252b5132 | 340 | { |
886a2506 NC |
341 | { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, |
342 | E_ARC_MACH_ARC600, 0x00}, | |
343 | { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, | |
344 | E_ARC_MACH_ARC700, 0x00}, | |
345 | { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, | |
346 | EF_ARC_CPU_ARCV2EM, 0x00}, | |
347 | { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, | |
348 | EF_ARC_CPU_ARCV2HS, ARC_CD}, | |
349 | { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2, | |
350 | 0x00, 0x00 }, | |
351 | { 0, 0, 0, 0, 0 } | |
352 | }; | |
252b5132 | 353 | |
886a2506 NC |
354 | /* Used by the arc_reloc_op table. Order is important. */ |
355 | #define O_gotoff O_md1 /* @gotoff relocation. */ | |
356 | #define O_gotpc O_md2 /* @gotpc relocation. */ | |
357 | #define O_plt O_md3 /* @plt relocation. */ | |
358 | #define O_sda O_md4 /* @sda relocation. */ | |
359 | #define O_pcl O_md5 /* @pcl relocation. */ | |
360 | #define O_tlsgd O_md6 /* @tlsgd relocation. */ | |
361 | #define O_tlsie O_md7 /* @tlsie relocation. */ | |
362 | #define O_tpoff9 O_md8 /* @tpoff9 relocation. */ | |
363 | #define O_tpoff O_md9 /* @tpoff relocation. */ | |
364 | #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */ | |
365 | #define O_dtpoff O_md11 /* @dtpoff relocation. */ | |
366 | #define O_last O_dtpoff | |
367 | ||
368 | /* Used to define a bracket as operand in tokens. */ | |
369 | #define O_bracket O_md32 | |
370 | ||
371 | /* Dummy relocation, to be sorted out. */ | |
372 | #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1) | |
373 | ||
374 | #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last) | |
375 | ||
376 | /* A table to map the spelling of a relocation operand into an appropriate | |
377 | bfd_reloc_code_real_type type. The table is assumed to be ordered such | |
378 | that op-O_literal indexes into it. */ | |
379 | #define ARC_RELOC_TABLE(op) \ | |
380 | (&arc_reloc_op[ ((!USER_RELOC_P (op)) \ | |
381 | ? (abort (), 0) \ | |
382 | : (int) (op) - (int) O_gotoff) ]) | |
383 | ||
384 | #define DEF(NAME, RELOC, REQ) \ | |
385 | { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ} | |
386 | ||
387 | static const struct arc_reloc_op_tag | |
388 | { | |
389 | /* String to lookup. */ | |
390 | const char *name; | |
391 | /* Size of the string. */ | |
392 | size_t length; | |
393 | /* Which operator to use. */ | |
394 | operatorT op; | |
395 | extended_bfd_reloc_code_real_type reloc; | |
396 | /* Allows complex relocation expression like identifier@reloc + | |
397 | const. */ | |
398 | unsigned int complex_expr : 1; | |
399 | } | |
400 | arc_reloc_op[] = | |
6f4b1afc CM |
401 | { |
402 | DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1), | |
403 | DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0), | |
404 | DEF (plt, BFD_RELOC_ARC_PLT32, 0), | |
405 | DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1), | |
406 | DEF (pcl, BFD_RELOC_ARC_PC32, 1), | |
407 | DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0), | |
408 | DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0), | |
409 | DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0), | |
b125bd17 | 410 | DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1), |
6f4b1afc CM |
411 | DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0), |
412 | DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0), | |
413 | }; | |
252b5132 | 414 | |
886a2506 NC |
415 | static const int arc_num_reloc_op |
416 | = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op); | |
417 | ||
4670103e CZ |
418 | /* Structure for relaxable instruction that have to be swapped with a |
419 | smaller alternative instruction. */ | |
420 | struct arc_relaxable_ins | |
421 | { | |
422 | /* Mnemonic that should be checked. */ | |
423 | const char *mnemonic_r; | |
424 | ||
425 | /* Operands that should be checked. | |
426 | Indexes of operands from operand array. */ | |
427 | enum rlx_operand_type operands[6]; | |
428 | ||
429 | /* Flags that should be checked. */ | |
430 | unsigned flag_classes[5]; | |
431 | ||
432 | /* Mnemonic (smaller) alternative to be used later for relaxation. */ | |
433 | const char *mnemonic_alt; | |
434 | ||
435 | /* Index of operand that generic relaxation has to check. */ | |
436 | unsigned opcheckidx; | |
437 | ||
438 | /* Base subtype index used. */ | |
439 | enum arc_rlx_types subtype; | |
440 | }; | |
441 | ||
442 | #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \ | |
443 | { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \ | |
444 | (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \ | |
445 | (SIZE), \ | |
446 | (NEXT) } \ | |
447 | ||
448 | #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \ | |
449 | { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \ | |
450 | (ISSIGNED) ? -(0x7FFFFFFF) : 0, \ | |
451 | (SIZE), \ | |
452 | (NEXT) } \ | |
453 | ||
454 | ||
455 | /* ARC relaxation table. */ | |
456 | const relax_typeS md_relax_table[] = | |
457 | { | |
458 | /* Fake entry. */ | |
459 | {0, 0, 0, 0}, | |
460 | ||
461 | /* BL_S s13 -> | |
462 | BL s25. */ | |
463 | RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL), | |
464 | RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE), | |
465 | ||
466 | /* B_S s10 -> | |
467 | B s25. */ | |
468 | RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B), | |
469 | RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE), | |
470 | ||
471 | /* ADD_S c,b, u3 -> | |
472 | ADD<.f> a,b,u6 -> | |
473 | ADD<.f> a,b,limm. */ | |
474 | RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6), | |
475 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM), | |
476 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
477 | ||
478 | /* LD_S a, [b, u7] -> | |
479 | LD<zz><.x><.aa><.di> a, [b, s9] -> | |
480 | LD<zz><.x><.aa><.di> a, [b, limm] */ | |
481 | RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9), | |
482 | RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM), | |
483 | RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE), | |
484 | ||
485 | /* MOV_S b, u8 -> | |
486 | MOV<.f> b, s12 -> | |
487 | MOV<.f> b, limm. */ | |
488 | RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12), | |
489 | RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM), | |
490 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
491 | ||
492 | /* SUB_S c, b, u3 -> | |
493 | SUB<.f> a, b, u6 -> | |
494 | SUB<.f> a, b, limm. */ | |
495 | RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6), | |
496 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM), | |
497 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
498 | ||
499 | /* MPY<.f> a, b, u6 -> | |
500 | MPY<.f> a, b, limm. */ | |
501 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM), | |
502 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
503 | ||
504 | /* MOV<.f><.cc> b, u6 -> | |
505 | MOV<.f><.cc> b, limm. */ | |
506 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM), | |
507 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
508 | ||
509 | /* ADD<.f><.cc> b, b, u6 -> | |
510 | ADD<.f><.cc> b, b, limm. */ | |
511 | RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM), | |
512 | RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE), | |
513 | }; | |
514 | ||
515 | /* Order of this table's entries matters! */ | |
516 | const struct arc_relaxable_ins arc_relaxable_insns[] = | |
517 | { | |
518 | { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S }, | |
519 | { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S }, | |
520 | { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add", | |
521 | 2, ARC_RLX_ADD_RRU6}, | |
522 | { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2, | |
523 | ARC_RLX_ADD_U3 }, | |
524 | { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2, | |
525 | ARC_RLX_ADD_U6 }, | |
526 | { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET }, | |
527 | { 0 }, "ld_s", 3, ARC_RLX_LD_U7 }, | |
528 | { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET }, | |
529 | { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 }, | |
530 | { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 }, | |
531 | { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 }, | |
532 | { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 }, | |
533 | { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2, | |
534 | ARC_RLX_SUB_U3 }, | |
535 | { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2, | |
536 | ARC_RLX_SUB_U6 }, | |
537 | { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2, | |
538 | ARC_RLX_MPY_U6 }, | |
539 | }; | |
540 | ||
541 | const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns); | |
542 | ||
886a2506 NC |
543 | /* Flags to set in the elf header. */ |
544 | static flagword arc_eflag = 0x00; | |
545 | ||
546 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ | |
547 | symbolS * GOT_symbol = 0; | |
548 | ||
549 | /* Set to TRUE when we assemble instructions. */ | |
550 | static bfd_boolean assembling_insn = FALSE; | |
551 | ||
886a2506 NC |
552 | /* Functions implementation. */ |
553 | ||
554 | /* Like md_number_to_chars but used for limms. The 4-byte limm value, | |
555 | is encoded as 'middle-endian' for a little-endian target. FIXME! | |
556 | this function is used for regular 4 byte instructions as well. */ | |
557 | ||
558 | static void | |
6f4b1afc | 559 | md_number_to_chars_midend (char *buf, valueT val, int n) |
886a2506 NC |
560 | { |
561 | if (n == 4) | |
562 | { | |
563 | md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2); | |
564 | md_number_to_chars (buf + 2, (val & 0xffff), 2); | |
252b5132 RH |
565 | } |
566 | else | |
886a2506 NC |
567 | { |
568 | md_number_to_chars (buf, val, n); | |
569 | } | |
252b5132 RH |
570 | } |
571 | ||
886a2506 NC |
572 | /* Here ends all the ARCompact extension instruction assembling |
573 | stuff. */ | |
252b5132 | 574 | |
886a2506 NC |
575 | static void |
576 | arc_extra_reloc (int r_type) | |
ea1562b3 | 577 | { |
886a2506 NC |
578 | char *sym_name, c; |
579 | symbolS *sym, *lab = NULL; | |
580 | ||
581 | if (*input_line_pointer == '@') | |
582 | input_line_pointer++; | |
583 | c = get_symbol_name (&sym_name); | |
584 | sym = symbol_find_or_make (sym_name); | |
585 | restore_line_pointer (c); | |
586 | if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD) | |
587 | { | |
588 | ++input_line_pointer; | |
589 | char *lab_name; | |
590 | c = get_symbol_name (&lab_name); | |
591 | lab = symbol_find_or_make (lab_name); | |
592 | restore_line_pointer (c); | |
593 | } | |
594 | fixS *fixP | |
595 | = fix_new (frag_now, /* Which frag? */ | |
596 | frag_now_fix (), /* Where in that frag? */ | |
597 | 2, /* size: 1, 2, or 4 usually. */ | |
598 | sym, /* X_add_symbol. */ | |
599 | 0, /* X_add_number. */ | |
600 | FALSE, /* TRUE if PC-relative relocation. */ | |
601 | r_type /* Relocation type. */); | |
602 | fixP->fx_subsy = lab; | |
603 | } | |
252b5132 | 604 | |
886a2506 NC |
605 | static symbolS * |
606 | arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED, | |
607 | symbolS *symbolP, addressT size) | |
608 | { | |
609 | addressT align = 0; | |
610 | SKIP_WHITESPACE (); | |
252b5132 | 611 | |
886a2506 NC |
612 | if (*input_line_pointer == ',') |
613 | { | |
614 | align = parse_align (1); | |
252b5132 | 615 | |
886a2506 NC |
616 | if (align == (addressT) -1) |
617 | return NULL; | |
618 | } | |
619 | else | |
620 | { | |
621 | if (size >= 8) | |
622 | align = 3; | |
623 | else if (size >= 4) | |
624 | align = 2; | |
625 | else if (size >= 2) | |
626 | align = 1; | |
627 | else | |
628 | align = 0; | |
629 | } | |
252b5132 | 630 | |
886a2506 NC |
631 | bss_alloc (symbolP, size, align); |
632 | S_CLEAR_EXTERNAL (symbolP); | |
ea1562b3 | 633 | |
886a2506 NC |
634 | return symbolP; |
635 | } | |
ea1562b3 | 636 | |
886a2506 NC |
637 | static void |
638 | arc_lcomm (int ignore) | |
639 | { | |
640 | symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal); | |
ea1562b3 | 641 | |
886a2506 NC |
642 | if (symbolP) |
643 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; | |
644 | } | |
ea1562b3 | 645 | |
886a2506 | 646 | /* Select the cpu we're assembling for. */ |
ea1562b3 | 647 | |
886a2506 NC |
648 | static void |
649 | arc_option (int ignore ATTRIBUTE_UNUSED) | |
252b5132 | 650 | { |
886a2506 NC |
651 | int mach = -1; |
652 | char c; | |
653 | char *cpu; | |
252b5132 | 654 | |
886a2506 NC |
655 | c = get_symbol_name (&cpu); |
656 | mach = arc_get_mach (cpu); | |
252b5132 | 657 | |
886a2506 NC |
658 | if (mach == -1) |
659 | goto bad_cpu; | |
660 | ||
661 | if (!mach_type_specified_p) | |
ea1562b3 | 662 | { |
24b368f8 CZ |
663 | if ((!strcmp ("ARC600", cpu)) |
664 | || (!strcmp ("ARC601", cpu)) | |
665 | || (!strcmp ("A6", cpu))) | |
666 | { | |
667 | md_parse_option (OPTION_MCPU, "arc600"); | |
668 | } | |
669 | else if ((!strcmp ("ARC700", cpu)) | |
670 | || (!strcmp ("A7", cpu))) | |
671 | { | |
672 | md_parse_option (OPTION_MCPU, "arc700"); | |
673 | } | |
674 | else if (!strcmp ("EM", cpu)) | |
675 | { | |
676 | md_parse_option (OPTION_MCPU, "arcem"); | |
677 | } | |
678 | else if (!strcmp ("HS", cpu)) | |
679 | { | |
680 | md_parse_option (OPTION_MCPU, "archs"); | |
681 | } | |
682 | else | |
683 | as_fatal ("could not find the architecture"); | |
684 | ||
886a2506 NC |
685 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach)) |
686 | as_fatal ("could not set architecture and machine"); | |
ea1562b3 NC |
687 | } |
688 | else | |
886a2506 NC |
689 | if (arc_mach_type != mach) |
690 | as_warn ("Command-line value overrides \".cpu\" directive"); | |
691 | ||
24b368f8 | 692 | restore_line_pointer (c); |
886a2506 | 693 | demand_empty_rest_of_line (); |
886a2506 NC |
694 | return; |
695 | ||
696 | bad_cpu: | |
24b368f8 | 697 | restore_line_pointer (c); |
886a2506 NC |
698 | as_bad ("invalid identifier for \".cpu\""); |
699 | ignore_rest_of_line (); | |
ea1562b3 | 700 | } |
252b5132 | 701 | |
886a2506 NC |
702 | /* Smartly print an expression. */ |
703 | ||
ea1562b3 | 704 | static void |
886a2506 | 705 | debug_exp (expressionS *t) |
ea1562b3 | 706 | { |
886a2506 NC |
707 | const char *name ATTRIBUTE_UNUSED; |
708 | const char *namemd ATTRIBUTE_UNUSED; | |
252b5132 | 709 | |
886a2506 | 710 | pr_debug ("debug_exp: "); |
252b5132 | 711 | |
886a2506 | 712 | switch (t->X_op) |
252b5132 | 713 | { |
886a2506 NC |
714 | default: name = "unknown"; break; |
715 | case O_illegal: name = "O_illegal"; break; | |
716 | case O_absent: name = "O_absent"; break; | |
717 | case O_constant: name = "O_constant"; break; | |
718 | case O_symbol: name = "O_symbol"; break; | |
719 | case O_symbol_rva: name = "O_symbol_rva"; break; | |
720 | case O_register: name = "O_register"; break; | |
721 | case O_big: name = "O_big"; break; | |
722 | case O_uminus: name = "O_uminus"; break; | |
723 | case O_bit_not: name = "O_bit_not"; break; | |
724 | case O_logical_not: name = "O_logical_not"; break; | |
725 | case O_multiply: name = "O_multiply"; break; | |
726 | case O_divide: name = "O_divide"; break; | |
727 | case O_modulus: name = "O_modulus"; break; | |
728 | case O_left_shift: name = "O_left_shift"; break; | |
729 | case O_right_shift: name = "O_right_shift"; break; | |
730 | case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break; | |
731 | case O_bit_or_not: name = "O_bit_or_not"; break; | |
732 | case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break; | |
733 | case O_bit_and: name = "O_bit_and"; break; | |
734 | case O_add: name = "O_add"; break; | |
735 | case O_subtract: name = "O_subtract"; break; | |
736 | case O_eq: name = "O_eq"; break; | |
737 | case O_ne: name = "O_ne"; break; | |
738 | case O_lt: name = "O_lt"; break; | |
739 | case O_le: name = "O_le"; break; | |
740 | case O_ge: name = "O_ge"; break; | |
741 | case O_gt: name = "O_gt"; break; | |
742 | case O_logical_and: name = "O_logical_and"; break; | |
743 | case O_logical_or: name = "O_logical_or"; break; | |
744 | case O_index: name = "O_index"; break; | |
745 | case O_bracket: name = "O_bracket"; break; | |
ea1562b3 | 746 | } |
252b5132 | 747 | |
886a2506 | 748 | switch (t->X_md) |
ea1562b3 | 749 | { |
886a2506 NC |
750 | default: namemd = "unknown"; break; |
751 | case O_gotoff: namemd = "O_gotoff"; break; | |
752 | case O_gotpc: namemd = "O_gotpc"; break; | |
753 | case O_plt: namemd = "O_plt"; break; | |
754 | case O_sda: namemd = "O_sda"; break; | |
755 | case O_pcl: namemd = "O_pcl"; break; | |
756 | case O_tlsgd: namemd = "O_tlsgd"; break; | |
757 | case O_tlsie: namemd = "O_tlsie"; break; | |
758 | case O_tpoff9: namemd = "O_tpoff9"; break; | |
759 | case O_tpoff: namemd = "O_tpoff"; break; | |
760 | case O_dtpoff9: namemd = "O_dtpoff9"; break; | |
761 | case O_dtpoff: namemd = "O_dtpoff"; break; | |
ea1562b3 | 762 | } |
252b5132 | 763 | |
886a2506 NC |
764 | pr_debug ("%s (%s, %s, %d, %s)", name, |
765 | (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--", | |
766 | (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--", | |
767 | (int) t->X_add_number, | |
768 | (t->X_md) ? namemd : "--"); | |
769 | pr_debug ("\n"); | |
770 | fflush (stderr); | |
771 | } | |
252b5132 | 772 | |
886a2506 NC |
773 | /* Parse the arguments to an opcode. */ |
774 | ||
775 | static int | |
776 | tokenize_arguments (char *str, | |
777 | expressionS *tok, | |
778 | int ntok) | |
779 | { | |
780 | char *old_input_line_pointer; | |
781 | bfd_boolean saw_comma = FALSE; | |
782 | bfd_boolean saw_arg = FALSE; | |
783 | int brk_lvl = 0; | |
784 | int num_args = 0; | |
886a2506 NC |
785 | int i; |
786 | size_t len; | |
787 | const struct arc_reloc_op_tag *r; | |
788 | expressionS tmpE; | |
6f4b1afc | 789 | char *reloc_name, c; |
886a2506 NC |
790 | |
791 | memset (tok, 0, sizeof (*tok) * ntok); | |
792 | ||
793 | /* Save and restore input_line_pointer around this function. */ | |
794 | old_input_line_pointer = input_line_pointer; | |
795 | input_line_pointer = str; | |
ea1562b3 | 796 | |
886a2506 | 797 | while (*input_line_pointer) |
ea1562b3 NC |
798 | { |
799 | SKIP_WHITESPACE (); | |
886a2506 | 800 | switch (*input_line_pointer) |
252b5132 | 801 | { |
886a2506 NC |
802 | case '\0': |
803 | goto fini; | |
804 | ||
805 | case ',': | |
806 | input_line_pointer++; | |
807 | if (saw_comma || !saw_arg) | |
808 | goto err; | |
809 | saw_comma = TRUE; | |
810 | break; | |
252b5132 | 811 | |
886a2506 NC |
812 | case '}': |
813 | case ']': | |
814 | ++input_line_pointer; | |
815 | --brk_lvl; | |
816 | if (!saw_arg) | |
817 | goto err; | |
818 | tok->X_op = O_bracket; | |
819 | ++tok; | |
820 | ++num_args; | |
821 | break; | |
ea1562b3 | 822 | |
886a2506 NC |
823 | case '{': |
824 | case '[': | |
825 | input_line_pointer++; | |
826 | if (brk_lvl) | |
827 | goto err; | |
828 | ++brk_lvl; | |
829 | tok->X_op = O_bracket; | |
830 | ++tok; | |
831 | ++num_args; | |
832 | break; | |
833 | ||
834 | case '@': | |
835 | /* We have labels, function names and relocations, all | |
836 | starting with @ symbol. Sort them out. */ | |
837 | if (saw_arg && !saw_comma) | |
838 | goto err; | |
839 | ||
840 | /* Parse @label. */ | |
841 | tok->X_op = O_symbol; | |
842 | tok->X_md = O_absent; | |
843 | expression (tok); | |
844 | if (*input_line_pointer != '@') | |
845 | goto normalsymbol; /* This is not a relocation. */ | |
846 | ||
6f4b1afc CM |
847 | relocationsym: |
848 | ||
886a2506 NC |
849 | /* A relocation opernad has the following form |
850 | @identifier@relocation_type. The identifier is already | |
851 | in tok! */ | |
852 | if (tok->X_op != O_symbol) | |
ea1562b3 | 853 | { |
886a2506 NC |
854 | as_bad (_("No valid label relocation operand")); |
855 | goto err; | |
252b5132 | 856 | } |
886a2506 NC |
857 | |
858 | /* Parse @relocation_type. */ | |
6f4b1afc CM |
859 | input_line_pointer++; |
860 | c = get_symbol_name (&reloc_name); | |
861 | len = input_line_pointer - reloc_name; | |
862 | if (len == 0) | |
252b5132 | 863 | { |
886a2506 NC |
864 | as_bad (_("No relocation operand")); |
865 | goto err; | |
252b5132 | 866 | } |
252b5132 | 867 | |
886a2506 NC |
868 | /* Go through known relocation and try to find a match. */ |
869 | r = &arc_reloc_op[0]; | |
870 | for (i = arc_num_reloc_op - 1; i >= 0; i--, r++) | |
6f4b1afc CM |
871 | if (len == r->length |
872 | && memcmp (reloc_name, r->name, len) == 0) | |
886a2506 | 873 | break; |
886a2506 | 874 | if (i < 0) |
252b5132 | 875 | { |
6f4b1afc | 876 | as_bad (_("Unknown relocation operand: @%s"), reloc_name); |
886a2506 NC |
877 | goto err; |
878 | } | |
879 | ||
6f4b1afc CM |
880 | *input_line_pointer = c; |
881 | SKIP_WHITESPACE_AFTER_NAME (); | |
886a2506 NC |
882 | /* Extra check for TLS: base. */ |
883 | if (*input_line_pointer == '@') | |
884 | { | |
885 | symbolS *base; | |
886 | if (tok->X_op_symbol != NULL | |
887 | || tok->X_op != O_symbol) | |
252b5132 | 888 | { |
6f4b1afc CM |
889 | as_bad (_("Unable to parse TLS base: %s"), |
890 | input_line_pointer); | |
886a2506 | 891 | goto err; |
252b5132 | 892 | } |
886a2506 NC |
893 | input_line_pointer++; |
894 | char *sym_name; | |
6f4b1afc | 895 | c = get_symbol_name (&sym_name); |
886a2506 NC |
896 | base = symbol_find_or_make (sym_name); |
897 | tok->X_op = O_subtract; | |
898 | tok->X_op_symbol = base; | |
899 | restore_line_pointer (c); | |
6f4b1afc CM |
900 | tmpE.X_add_number = 0; |
901 | } | |
902 | else if ((*input_line_pointer != '+') | |
903 | && (*input_line_pointer != '-')) | |
904 | { | |
905 | tmpE.X_add_number = 0; | |
ea1562b3 | 906 | } |
6f4b1afc CM |
907 | else |
908 | { | |
909 | /* Parse the constant of a complex relocation expression | |
910 | like @identifier@reloc +/- const. */ | |
911 | if (! r->complex_expr) | |
912 | { | |
913 | as_bad (_("@%s is not a complex relocation."), r->name); | |
914 | goto err; | |
915 | } | |
916 | expression (&tmpE); | |
917 | if (tmpE.X_op != O_constant) | |
918 | { | |
919 | as_bad (_("Bad expression: @%s + %s."), | |
920 | r->name, input_line_pointer); | |
921 | goto err; | |
922 | } | |
923 | } | |
924 | ||
925 | tok->X_md = r->op; | |
926 | tok->X_add_number = tmpE.X_add_number; | |
1e07b820 | 927 | |
886a2506 | 928 | debug_exp (tok); |
ea1562b3 | 929 | |
886a2506 NC |
930 | saw_comma = FALSE; |
931 | saw_arg = TRUE; | |
932 | tok++; | |
933 | num_args++; | |
934 | break; | |
252b5132 | 935 | |
886a2506 NC |
936 | case '%': |
937 | /* Can be a register. */ | |
938 | ++input_line_pointer; | |
939 | /* Fall through. */ | |
940 | default: | |
252b5132 | 941 | |
886a2506 NC |
942 | if (saw_arg && !saw_comma) |
943 | goto err; | |
252b5132 | 944 | |
886a2506 | 945 | tok->X_op = O_absent; |
6f4b1afc | 946 | tok->X_md = O_absent; |
886a2506 | 947 | expression (tok); |
252b5132 | 948 | |
6f4b1afc CM |
949 | /* Legacy: There are cases when we have |
950 | identifier@relocation_type, if it is the case parse the | |
951 | relocation type as well. */ | |
952 | if (*input_line_pointer == '@') | |
953 | goto relocationsym; | |
954 | ||
886a2506 NC |
955 | normalsymbol: |
956 | debug_exp (tok); | |
252b5132 | 957 | |
886a2506 NC |
958 | if (tok->X_op == O_illegal || tok->X_op == O_absent) |
959 | goto err; | |
252b5132 | 960 | |
886a2506 NC |
961 | saw_comma = FALSE; |
962 | saw_arg = TRUE; | |
963 | tok++; | |
964 | num_args++; | |
965 | break; | |
966 | } | |
ea1562b3 | 967 | } |
252b5132 | 968 | |
886a2506 NC |
969 | fini: |
970 | if (saw_comma || brk_lvl) | |
971 | goto err; | |
972 | input_line_pointer = old_input_line_pointer; | |
252b5132 | 973 | |
886a2506 | 974 | return num_args; |
252b5132 | 975 | |
886a2506 NC |
976 | err: |
977 | if (brk_lvl) | |
978 | as_bad (_("Brackets in operand field incorrect")); | |
979 | else if (saw_comma) | |
980 | as_bad (_("extra comma")); | |
981 | else if (!saw_arg) | |
982 | as_bad (_("missing argument")); | |
983 | else | |
984 | as_bad (_("missing comma or colon")); | |
985 | input_line_pointer = old_input_line_pointer; | |
986 | return -1; | |
252b5132 | 987 | } |
ea1562b3 | 988 | |
886a2506 NC |
989 | /* Parse the flags to a structure. */ |
990 | ||
991 | static int | |
992 | tokenize_flags (const char *str, | |
993 | struct arc_flags flags[], | |
994 | int nflg) | |
252b5132 | 995 | { |
886a2506 NC |
996 | char *old_input_line_pointer; |
997 | bfd_boolean saw_flg = FALSE; | |
998 | bfd_boolean saw_dot = FALSE; | |
999 | int num_flags = 0; | |
1000 | size_t flgnamelen; | |
252b5132 | 1001 | |
886a2506 | 1002 | memset (flags, 0, sizeof (*flags) * nflg); |
0d2bcfaf | 1003 | |
886a2506 NC |
1004 | /* Save and restore input_line_pointer around this function. */ |
1005 | old_input_line_pointer = input_line_pointer; | |
1006 | input_line_pointer = (char *) str; | |
0d2bcfaf | 1007 | |
886a2506 NC |
1008 | while (*input_line_pointer) |
1009 | { | |
1010 | switch (*input_line_pointer) | |
1011 | { | |
1012 | case ' ': | |
1013 | case '\0': | |
1014 | goto fini; | |
1015 | ||
1016 | case '.': | |
1017 | input_line_pointer++; | |
1018 | if (saw_dot) | |
1019 | goto err; | |
1020 | saw_dot = TRUE; | |
1021 | saw_flg = FALSE; | |
1022 | break; | |
ea1562b3 | 1023 | |
886a2506 NC |
1024 | default: |
1025 | if (saw_flg && !saw_dot) | |
1026 | goto err; | |
0d2bcfaf | 1027 | |
886a2506 NC |
1028 | if (num_flags >= nflg) |
1029 | goto err; | |
0d2bcfaf | 1030 | |
886a2506 NC |
1031 | flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz"); |
1032 | if (flgnamelen > MAX_FLAG_NAME_LENGHT) | |
1033 | goto err; | |
0d2bcfaf | 1034 | |
886a2506 | 1035 | memcpy (flags->name, input_line_pointer, flgnamelen); |
0d2bcfaf | 1036 | |
886a2506 NC |
1037 | input_line_pointer += flgnamelen; |
1038 | flags++; | |
1039 | saw_dot = FALSE; | |
1040 | saw_flg = TRUE; | |
1041 | num_flags++; | |
1042 | break; | |
1e07b820 | 1043 | } |
0d2bcfaf NC |
1044 | } |
1045 | ||
886a2506 NC |
1046 | fini: |
1047 | input_line_pointer = old_input_line_pointer; | |
1048 | return num_flags; | |
0d2bcfaf | 1049 | |
886a2506 NC |
1050 | err: |
1051 | if (saw_dot) | |
1052 | as_bad (_("extra dot")); | |
1053 | else if (!saw_flg) | |
1054 | as_bad (_("unrecognized flag")); | |
1055 | else | |
1056 | as_bad (_("failed to parse flags")); | |
1057 | input_line_pointer = old_input_line_pointer; | |
1058 | return -1; | |
1059 | } | |
0d2bcfaf | 1060 | |
4670103e | 1061 | /* Apply the fixups in order. */ |
0d2bcfaf | 1062 | |
4670103e CZ |
1063 | static void |
1064 | apply_fixups (struct arc_insn *insn, fragS *fragP, int fix) | |
886a2506 | 1065 | { |
4670103e | 1066 | int i; |
0d2bcfaf | 1067 | |
4670103e | 1068 | for (i = 0; i < insn->nfixups; i++) |
252b5132 | 1069 | { |
4670103e CZ |
1070 | struct arc_fixup *fixup = &insn->fixups[i]; |
1071 | int size, pcrel, offset = 0; | |
0d2bcfaf | 1072 | |
4670103e CZ |
1073 | /* FIXME! the reloc size is wrong in the BFD file. |
1074 | When it is fixed please delete me. */ | |
1075 | size = (insn->short_insn && !fixup->islong) ? 2 : 4; | |
0d2bcfaf | 1076 | |
4670103e CZ |
1077 | if (fixup->islong) |
1078 | offset = (insn->short_insn) ? 2 : 4; | |
252b5132 | 1079 | |
4670103e CZ |
1080 | /* Some fixups are only used internally, thus no howto. */ |
1081 | if ((int) fixup->reloc == 0) | |
1082 | as_fatal (_("Unhandled reloc type")); | |
886a2506 | 1083 | |
4670103e CZ |
1084 | if ((int) fixup->reloc < 0) |
1085 | { | |
1086 | /* FIXME! the reloc size is wrong in the BFD file. | |
1087 | When it is fixed please enable me. | |
1088 | size = (insn->short_insn && !fixup->islong) ? 2 : 4; */ | |
1089 | pcrel = fixup->pcrel; | |
1090 | } | |
1091 | else | |
1092 | { | |
1093 | reloc_howto_type *reloc_howto = | |
1094 | bfd_reloc_type_lookup (stdoutput, | |
1095 | (bfd_reloc_code_real_type) fixup->reloc); | |
1096 | gas_assert (reloc_howto); | |
0d2bcfaf | 1097 | |
4670103e CZ |
1098 | /* FIXME! the reloc size is wrong in the BFD file. |
1099 | When it is fixed please enable me. | |
1100 | size = bfd_get_reloc_size (reloc_howto); */ | |
1101 | pcrel = reloc_howto->pc_relative; | |
1102 | } | |
0d2bcfaf | 1103 | |
4670103e CZ |
1104 | pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \ |
1105 | offset %d + %d\n", | |
1106 | fragP->fr_file, fragP->fr_line, | |
1107 | (fixup->reloc < 0) ? "Internal" : | |
1108 | bfd_get_reloc_code_name (fixup->reloc), | |
1109 | pcrel ? "Y" : "N", | |
1110 | size, fix, offset); | |
1111 | fix_new_exp (fragP, fix + offset, | |
1112 | size, &fixup->exp, pcrel, fixup->reloc); | |
0d2bcfaf | 1113 | |
4670103e CZ |
1114 | /* Check for ZOLs, and update symbol info if any. */ |
1115 | if (LP_INSN (insn->insn)) | |
886a2506 | 1116 | { |
4670103e CZ |
1117 | gas_assert (fixup->exp.X_add_symbol); |
1118 | ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL); | |
886a2506 NC |
1119 | } |
1120 | } | |
252b5132 RH |
1121 | } |
1122 | ||
4670103e | 1123 | /* Actually output an instruction with its fixup. */ |
886a2506 | 1124 | |
4670103e CZ |
1125 | static void |
1126 | emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax) | |
252b5132 | 1127 | { |
4670103e | 1128 | char *f = where; |
252b5132 | 1129 | |
4670103e CZ |
1130 | pr_debug ("Emit insn : 0x%x\n", insn->insn); |
1131 | pr_debug ("\tShort : 0x%d\n", insn->short_insn); | |
1132 | pr_debug ("\tLong imm: 0x%lx\n", insn->limm); | |
0d2bcfaf | 1133 | |
4670103e CZ |
1134 | /* Write out the instruction. */ |
1135 | if (insn->short_insn) | |
0d2bcfaf | 1136 | { |
4670103e CZ |
1137 | if (insn->has_limm) |
1138 | { | |
1139 | if (!relax) | |
1140 | f = frag_more (6); | |
1141 | md_number_to_chars (f, insn->insn, 2); | |
1142 | md_number_to_chars_midend (f + 2, insn->limm, 4); | |
1143 | dwarf2_emit_insn (6); | |
1144 | } | |
1145 | else | |
1146 | { | |
1147 | if (!relax) | |
1148 | f = frag_more (2); | |
1149 | md_number_to_chars (f, insn->insn, 2); | |
1150 | dwarf2_emit_insn (2); | |
1151 | } | |
1152 | } | |
1153 | else | |
1154 | { | |
1155 | if (insn->has_limm) | |
1156 | { | |
1157 | if (!relax) | |
1158 | f = frag_more (8); | |
1159 | md_number_to_chars_midend (f, insn->insn, 4); | |
1160 | md_number_to_chars_midend (f + 4, insn->limm, 4); | |
1161 | dwarf2_emit_insn (8); | |
1162 | } | |
1163 | else | |
1164 | { | |
1165 | if (!relax) | |
1166 | f = frag_more (4); | |
1167 | md_number_to_chars_midend (f, insn->insn, 4); | |
1168 | dwarf2_emit_insn (4); | |
1169 | } | |
252b5132 | 1170 | } |
252b5132 | 1171 | |
4670103e CZ |
1172 | if (!relax) |
1173 | apply_fixups (insn, frag_now, (f - frag_now->fr_literal)); | |
1174 | } | |
252b5132 | 1175 | |
4670103e CZ |
1176 | static void |
1177 | emit_insn1 (struct arc_insn *insn) | |
1178 | { | |
1179 | /* How frag_var's args are currently configured: | |
1180 | - rs_machine_dependent, to dictate it's a relaxation frag. | |
1181 | - FRAG_MAX_GROWTH, maximum size of instruction | |
1182 | - 0, variable size that might grow...unused by generic relaxation. | |
1183 | - frag_now->fr_subtype, fr_subtype starting value, set previously. | |
1184 | - s, opand expression. | |
1185 | - 0, offset but it's unused. | |
1186 | - 0, opcode but it's unused. */ | |
1187 | symbolS *s = make_expr_symbol (&insn->fixups[0].exp); | |
1188 | frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel; | |
1189 | ||
1190 | if (frag_room () < FRAG_MAX_GROWTH) | |
1191 | { | |
1192 | /* Handle differently when frag literal memory is exhausted. | |
1193 | This is used because when there's not enough memory left in | |
1194 | the current frag, a new frag is created and the information | |
1195 | we put into frag_now->tc_frag_data is disregarded. */ | |
252b5132 | 1196 | |
4670103e CZ |
1197 | struct arc_relax_type relax_info_copy; |
1198 | relax_substateT subtype = frag_now->fr_subtype; | |
252b5132 | 1199 | |
4670103e CZ |
1200 | memcpy (&relax_info_copy, &frag_now->tc_frag_data, |
1201 | sizeof (struct arc_relax_type)); | |
0d2bcfaf | 1202 | |
4670103e CZ |
1203 | frag_wane (frag_now); |
1204 | frag_grow (FRAG_MAX_GROWTH); | |
0d2bcfaf | 1205 | |
4670103e CZ |
1206 | memcpy (&frag_now->tc_frag_data, &relax_info_copy, |
1207 | sizeof (struct arc_relax_type)); | |
252b5132 | 1208 | |
4670103e CZ |
1209 | frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0, |
1210 | subtype, s, 0, 0); | |
1211 | } | |
1212 | else | |
1213 | frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0, | |
1214 | frag_now->fr_subtype, s, 0, 0); | |
1215 | } | |
252b5132 | 1216 | |
4670103e CZ |
1217 | static void |
1218 | emit_insn (struct arc_insn *insn) | |
252b5132 | 1219 | { |
4670103e CZ |
1220 | if (insn->relax) |
1221 | emit_insn1 (insn); | |
252b5132 | 1222 | else |
4670103e | 1223 | emit_insn0 (insn, NULL, FALSE); |
252b5132 RH |
1224 | } |
1225 | ||
4670103e | 1226 | /* Check whether a symbol involves a register. */ |
252b5132 | 1227 | |
4670103e CZ |
1228 | static bfd_boolean |
1229 | contains_register (symbolS *sym) | |
252b5132 | 1230 | { |
4670103e CZ |
1231 | if (sym) |
1232 | { | |
1233 | expressionS *ex = symbol_get_value_expression (sym); | |
252b5132 | 1234 | |
4670103e CZ |
1235 | return ((O_register == ex->X_op) |
1236 | && !contains_register (ex->X_add_symbol) | |
1237 | && !contains_register (ex->X_op_symbol)); | |
1238 | } | |
1239 | ||
1240 | return FALSE; | |
252b5132 RH |
1241 | } |
1242 | ||
4670103e | 1243 | /* Returns the register number within a symbol. */ |
252b5132 | 1244 | |
4670103e CZ |
1245 | static int |
1246 | get_register (symbolS *sym) | |
252b5132 | 1247 | { |
4670103e CZ |
1248 | if (!contains_register (sym)) |
1249 | return -1; | |
0d2bcfaf | 1250 | |
4670103e CZ |
1251 | expressionS *ex = symbol_get_value_expression (sym); |
1252 | return regno (ex->X_add_number); | |
1253 | } | |
252b5132 | 1254 | |
4670103e CZ |
1255 | /* Return true if a RELOC is generic. A generic reloc is PC-rel of a |
1256 | simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */ | |
f17c130b | 1257 | |
4670103e CZ |
1258 | static bfd_boolean |
1259 | generic_reloc_p (extended_bfd_reloc_code_real_type reloc) | |
1260 | { | |
1261 | if (!reloc) | |
1262 | return FALSE; | |
886a2506 | 1263 | |
4670103e CZ |
1264 | switch (reloc) |
1265 | { | |
1266 | case BFD_RELOC_ARC_SDA_LDST: | |
1267 | case BFD_RELOC_ARC_SDA_LDST1: | |
1268 | case BFD_RELOC_ARC_SDA_LDST2: | |
1269 | case BFD_RELOC_ARC_SDA16_LD: | |
1270 | case BFD_RELOC_ARC_SDA16_LD1: | |
1271 | case BFD_RELOC_ARC_SDA16_LD2: | |
1272 | case BFD_RELOC_ARC_SDA16_ST2: | |
1273 | case BFD_RELOC_ARC_SDA32_ME: | |
1274 | return FALSE; | |
1275 | default: | |
1276 | return TRUE; | |
f17c130b | 1277 | } |
252b5132 RH |
1278 | } |
1279 | ||
4670103e | 1280 | /* Allocates a tok entry. */ |
252b5132 | 1281 | |
4670103e CZ |
1282 | static int |
1283 | allocate_tok (expressionS *tok, int ntok, int cidx) | |
252b5132 | 1284 | { |
4670103e CZ |
1285 | if (ntok > MAX_INSN_ARGS - 2) |
1286 | return 0; /* No space left. */ | |
252b5132 | 1287 | |
4670103e CZ |
1288 | if (cidx > ntok) |
1289 | return 0; /* Incorect args. */ | |
252b5132 | 1290 | |
4670103e | 1291 | memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok)); |
252b5132 | 1292 | |
4670103e CZ |
1293 | if (cidx == ntok) |
1294 | return 1; /* Success. */ | |
1295 | return allocate_tok (tok, ntok - 1, cidx); | |
1296 | } | |
886a2506 | 1297 | |
4670103e CZ |
1298 | /* Search forward through all variants of an opcode looking for a |
1299 | syntax match. */ | |
886a2506 | 1300 | |
4670103e CZ |
1301 | static const struct arc_opcode * |
1302 | find_opcode_match (const struct arc_opcode *first_opcode, | |
1303 | expressionS *tok, | |
1304 | int *pntok, | |
1305 | struct arc_flags *first_pflag, | |
1306 | int nflgs, | |
1307 | int *pcpumatch) | |
1308 | { | |
1309 | const struct arc_opcode *opcode = first_opcode; | |
1310 | int ntok = *pntok; | |
1311 | int got_cpu_match = 0; | |
1312 | expressionS bktok[MAX_INSN_ARGS]; | |
1313 | int bkntok; | |
1314 | expressionS emptyE; | |
886a2506 | 1315 | |
4670103e CZ |
1316 | memset (&emptyE, 0, sizeof (emptyE)); |
1317 | memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok)); | |
1318 | bkntok = ntok; | |
a161fe53 | 1319 | |
4670103e | 1320 | do |
252b5132 | 1321 | { |
4670103e CZ |
1322 | const unsigned char *opidx; |
1323 | const unsigned char *flgidx; | |
1324 | int tokidx = 0; | |
1325 | const expressionS *t = &emptyE; | |
252b5132 | 1326 | |
4670103e CZ |
1327 | pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ", |
1328 | frag_now->fr_file, frag_now->fr_line, opcode->opcode); | |
886a2506 | 1329 | |
4670103e CZ |
1330 | /* Don't match opcodes that don't exist on this |
1331 | architecture. */ | |
1332 | if (!(opcode->cpu & arc_target)) | |
1333 | goto match_failed; | |
886a2506 | 1334 | |
4670103e CZ |
1335 | if (is_code_density_p (opcode) && !(arc_features & ARC_CD)) |
1336 | goto match_failed; | |
886a2506 | 1337 | |
4670103e CZ |
1338 | got_cpu_match = 1; |
1339 | pr_debug ("cpu "); | |
886a2506 | 1340 | |
4670103e CZ |
1341 | /* Check the operands. */ |
1342 | for (opidx = opcode->operands; *opidx; ++opidx) | |
252b5132 | 1343 | { |
4670103e | 1344 | const struct arc_operand *operand = &arc_operands[*opidx]; |
252b5132 | 1345 | |
4670103e CZ |
1346 | /* Only take input from real operands. */ |
1347 | if ((operand->flags & ARC_OPERAND_FAKE) | |
1348 | && !(operand->flags & ARC_OPERAND_BRAKET)) | |
1349 | continue; | |
252b5132 | 1350 | |
4670103e CZ |
1351 | /* When we expect input, make sure we have it. */ |
1352 | if (tokidx >= ntok) | |
1353 | goto match_failed; | |
6f4b1afc | 1354 | |
4670103e CZ |
1355 | /* Match operand type with expression type. */ |
1356 | switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK) | |
1357 | { | |
1358 | case ARC_OPERAND_IR: | |
1359 | /* Check to be a register. */ | |
1360 | if ((tok[tokidx].X_op != O_register | |
1361 | || !is_ir_num (tok[tokidx].X_add_number)) | |
1362 | && !(operand->flags & ARC_OPERAND_IGNORE)) | |
1363 | goto match_failed; | |
1364 | ||
1365 | /* If expect duplicate, make sure it is duplicate. */ | |
1366 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
1367 | { | |
1368 | /* Check for duplicate. */ | |
1369 | if (t->X_op != O_register | |
1370 | || !is_ir_num (t->X_add_number) | |
1371 | || (regno (t->X_add_number) != | |
1372 | regno (tok[tokidx].X_add_number))) | |
1373 | goto match_failed; | |
1374 | } | |
1375 | ||
1376 | /* Special handling? */ | |
1377 | if (operand->insert) | |
1378 | { | |
1379 | const char *errmsg = NULL; | |
1380 | (*operand->insert)(0, | |
1381 | regno (tok[tokidx].X_add_number), | |
1382 | &errmsg); | |
1383 | if (errmsg) | |
1384 | { | |
1385 | if (operand->flags & ARC_OPERAND_IGNORE) | |
1386 | { | |
1387 | /* Missing argument, create one. */ | |
1388 | if (!allocate_tok (tok, ntok - 1, tokidx)) | |
1389 | goto match_failed; | |
1390 | ||
1391 | tok[tokidx].X_op = O_absent; | |
1392 | ++ntok; | |
1393 | } | |
1394 | else | |
1395 | goto match_failed; | |
1396 | } | |
1397 | } | |
1398 | ||
1399 | t = &tok[tokidx]; | |
1400 | break; | |
1401 | ||
1402 | case ARC_OPERAND_BRAKET: | |
1403 | /* Check if bracket is also in opcode table as | |
1404 | operand. */ | |
1405 | if (tok[tokidx].X_op != O_bracket) | |
1406 | goto match_failed; | |
1407 | break; | |
1408 | ||
1409 | case ARC_OPERAND_LIMM: | |
1410 | case ARC_OPERAND_SIGNED: | |
1411 | case ARC_OPERAND_UNSIGNED: | |
1412 | switch (tok[tokidx].X_op) | |
1413 | { | |
1414 | case O_illegal: | |
1415 | case O_absent: | |
1416 | case O_register: | |
1417 | goto match_failed; | |
1418 | ||
1419 | case O_bracket: | |
1420 | /* Got an (too) early bracket, check if it is an | |
1421 | ignored operand. N.B. This procedure works only | |
1422 | when bracket is the last operand! */ | |
1423 | if (!(operand->flags & ARC_OPERAND_IGNORE)) | |
1424 | goto match_failed; | |
1425 | /* Insert the missing operand. */ | |
1426 | if (!allocate_tok (tok, ntok - 1, tokidx)) | |
1427 | goto match_failed; | |
1428 | ||
1429 | tok[tokidx].X_op = O_absent; | |
1430 | ++ntok; | |
1431 | break; | |
1432 | ||
1433 | case O_constant: | |
1434 | /* Check the range. */ | |
1435 | if (operand->bits != 32 | |
1436 | && !(operand->flags & ARC_OPERAND_NCHK)) | |
1437 | { | |
1438 | offsetT min, max, val; | |
1439 | val = tok[tokidx].X_add_number; | |
1440 | ||
1441 | if (operand->flags & ARC_OPERAND_SIGNED) | |
1442 | { | |
1443 | max = (1 << (operand->bits - 1)) - 1; | |
1444 | min = -(1 << (operand->bits - 1)); | |
1445 | } | |
1446 | else | |
1447 | { | |
1448 | max = (1 << operand->bits) - 1; | |
1449 | min = 0; | |
1450 | } | |
1451 | ||
1452 | if (val < min || val > max) | |
1453 | goto match_failed; | |
1454 | ||
1455 | /* Check alignmets. */ | |
1456 | if ((operand->flags & ARC_OPERAND_ALIGNED32) | |
1457 | && (val & 0x03)) | |
1458 | goto match_failed; | |
1459 | ||
1460 | if ((operand->flags & ARC_OPERAND_ALIGNED16) | |
1461 | && (val & 0x01)) | |
1462 | goto match_failed; | |
1463 | } | |
1464 | else if (operand->flags & ARC_OPERAND_NCHK) | |
1465 | { | |
1466 | if (operand->insert) | |
1467 | { | |
1468 | const char *errmsg = NULL; | |
1469 | (*operand->insert)(0, | |
1470 | tok[tokidx].X_add_number, | |
1471 | &errmsg); | |
1472 | if (errmsg) | |
1473 | goto match_failed; | |
1474 | } | |
1475 | else | |
1476 | goto match_failed; | |
1477 | } | |
1478 | break; | |
1479 | ||
1480 | case O_subtract: | |
1481 | /* Check if it is register range. */ | |
1482 | if ((tok[tokidx].X_add_number == 0) | |
1483 | && contains_register (tok[tokidx].X_add_symbol) | |
1484 | && contains_register (tok[tokidx].X_op_symbol)) | |
1485 | { | |
1486 | int regs; | |
1487 | ||
1488 | regs = get_register (tok[tokidx].X_add_symbol); | |
1489 | regs <<= 16; | |
1490 | regs |= get_register (tok[tokidx].X_op_symbol); | |
1491 | if (operand->insert) | |
1492 | { | |
1493 | const char *errmsg = NULL; | |
1494 | (*operand->insert)(0, | |
1495 | regs, | |
1496 | &errmsg); | |
1497 | if (errmsg) | |
1498 | goto match_failed; | |
1499 | } | |
1500 | else | |
1501 | goto match_failed; | |
1502 | break; | |
1503 | } | |
1504 | default: | |
1505 | if (operand->default_reloc == 0) | |
1506 | goto match_failed; /* The operand needs relocation. */ | |
1507 | ||
1508 | /* Relocs requiring long immediate. FIXME! make it | |
1509 | generic and move it to a function. */ | |
1510 | switch (tok[tokidx].X_md) | |
1511 | { | |
1512 | case O_gotoff: | |
1513 | case O_gotpc: | |
1514 | case O_pcl: | |
1515 | case O_tpoff: | |
1516 | case O_dtpoff: | |
1517 | case O_tlsgd: | |
1518 | case O_tlsie: | |
1519 | if (!(operand->flags & ARC_OPERAND_LIMM)) | |
1520 | goto match_failed; | |
1521 | case O_absent: | |
1522 | if (!generic_reloc_p (operand->default_reloc)) | |
1523 | goto match_failed; | |
1524 | default: | |
1525 | break; | |
1526 | } | |
1527 | break; | |
1528 | } | |
1529 | /* If expect duplicate, make sure it is duplicate. */ | |
1530 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
1531 | { | |
1532 | if (t->X_op == O_illegal | |
1533 | || t->X_op == O_absent | |
1534 | || t->X_op == O_register | |
1535 | || (t->X_add_number != tok[tokidx].X_add_number)) | |
1536 | goto match_failed; | |
1537 | } | |
1538 | t = &tok[tokidx]; | |
1539 | break; | |
1540 | ||
1541 | default: | |
1542 | /* Everything else should have been fake. */ | |
1543 | abort (); | |
1544 | } | |
1545 | ||
1546 | ++tokidx; | |
1547 | } | |
1548 | pr_debug ("opr "); | |
1549 | ||
1550 | /* Check the flags. Iterate over the valid flag classes. */ | |
1551 | int lnflg = nflgs; | |
1552 | ||
1553 | for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx) | |
1554 | { | |
1555 | /* Get a valid flag class. */ | |
1556 | const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; | |
1557 | const unsigned *flgopridx; | |
1558 | ||
1559 | for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) | |
1560 | { | |
1561 | const struct arc_flag_operand *flg_operand; | |
1562 | struct arc_flags *pflag = first_pflag; | |
1563 | int i; | |
1564 | ||
1565 | flg_operand = &arc_flag_operands[*flgopridx]; | |
1566 | for (i = 0; i < nflgs; i++, pflag++) | |
1567 | { | |
1568 | /* Match against the parsed flags. */ | |
1569 | if (!strcmp (flg_operand->name, pflag->name)) | |
1570 | { | |
1571 | /*TODO: Check if it is duplicated. */ | |
1572 | pflag->code = *flgopridx; | |
1573 | lnflg--; | |
1574 | break; /* goto next flag class and parsed flag. */ | |
1575 | } | |
1576 | } | |
1577 | } | |
1578 | } | |
1579 | /* Did I check all the parsed flags? */ | |
1580 | if (lnflg) | |
1581 | goto match_failed; | |
1582 | ||
1583 | pr_debug ("flg"); | |
1584 | /* Possible match -- did we use all of our input? */ | |
1585 | if (tokidx == ntok) | |
1586 | { | |
1587 | *pntok = ntok; | |
1588 | pr_debug ("\n"); | |
1589 | return opcode; | |
1590 | } | |
1591 | ||
1592 | match_failed:; | |
1593 | pr_debug ("\n"); | |
1594 | /* Restore the original parameters. */ | |
1595 | memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok)); | |
1596 | ntok = bkntok; | |
1597 | } | |
1598 | while (++opcode - arc_opcodes < (int) arc_num_opcodes | |
1599 | && !strcmp (opcode->name, first_opcode->name)); | |
1600 | ||
1601 | if (*pcpumatch) | |
1602 | *pcpumatch = got_cpu_match; | |
1603 | ||
1604 | return NULL; | |
1605 | } | |
1606 | ||
1607 | /* Swap operand tokens. */ | |
1608 | ||
1609 | static void | |
1610 | swap_operand (expressionS *operand_array, | |
1611 | unsigned source, | |
1612 | unsigned destination) | |
1613 | { | |
1614 | expressionS cpy_operand; | |
1615 | expressionS *src_operand; | |
1616 | expressionS *dst_operand; | |
1617 | size_t size; | |
1618 | ||
1619 | if (source == destination) | |
1620 | return; | |
1621 | ||
1622 | src_operand = &operand_array[source]; | |
1623 | dst_operand = &operand_array[destination]; | |
1624 | size = sizeof (expressionS); | |
1625 | ||
1626 | /* Make copy of operand to swap with and swap. */ | |
1627 | memcpy (&cpy_operand, dst_operand, size); | |
1628 | memcpy (dst_operand, src_operand, size); | |
1629 | memcpy (src_operand, &cpy_operand, size); | |
1630 | } | |
1631 | ||
1632 | /* Check if *op matches *tok type. | |
1633 | Returns FALSE if they don't match, TRUE if they match. */ | |
1634 | ||
1635 | static bfd_boolean | |
1636 | pseudo_operand_match (const expressionS *tok, | |
1637 | const struct arc_operand_operation *op) | |
1638 | { | |
1639 | offsetT min, max, val; | |
1640 | bfd_boolean ret; | |
1641 | const struct arc_operand *operand_real = &arc_operands[op->operand_idx]; | |
1642 | ||
1643 | ret = FALSE; | |
1644 | switch (tok->X_op) | |
1645 | { | |
1646 | case O_constant: | |
1647 | if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM)) | |
1648 | ret = 1; | |
1649 | else if (!(operand_real->flags & ARC_OPERAND_IR)) | |
1650 | { | |
1651 | val = tok->X_add_number + op->count; | |
1652 | if (operand_real->flags & ARC_OPERAND_SIGNED) | |
1653 | { | |
1654 | max = (1 << (operand_real->bits - 1)) - 1; | |
1655 | min = -(1 << (operand_real->bits - 1)); | |
1656 | } | |
1657 | else | |
1658 | { | |
1659 | max = (1 << operand_real->bits) - 1; | |
1660 | min = 0; | |
1661 | } | |
1662 | if (min <= val && val <= max) | |
1663 | ret = TRUE; | |
1664 | } | |
6f4b1afc CM |
1665 | break; |
1666 | ||
4670103e CZ |
1667 | case O_symbol: |
1668 | /* Handle all symbols as long immediates or signed 9. */ | |
1669 | if (operand_real->flags & ARC_OPERAND_LIMM || | |
1670 | ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9)) | |
1671 | ret = TRUE; | |
6f4b1afc CM |
1672 | break; |
1673 | ||
4670103e CZ |
1674 | case O_register: |
1675 | if (operand_real->flags & ARC_OPERAND_IR) | |
1676 | ret = TRUE; | |
1677 | break; | |
1678 | ||
1679 | case O_bracket: | |
1680 | if (operand_real->flags & ARC_OPERAND_BRAKET) | |
1681 | ret = TRUE; | |
6f4b1afc CM |
1682 | break; |
1683 | ||
1684 | default: | |
4670103e | 1685 | /* Unknown. */ |
6f4b1afc CM |
1686 | break; |
1687 | } | |
4670103e CZ |
1688 | return ret; |
1689 | } | |
6f4b1afc | 1690 | |
4670103e CZ |
1691 | /* Find pseudo instruction in array. */ |
1692 | ||
1693 | static const struct arc_pseudo_insn * | |
1694 | find_pseudo_insn (const char *opname, | |
1695 | int ntok, | |
1696 | const expressionS *tok) | |
1697 | { | |
1698 | const struct arc_pseudo_insn *pseudo_insn = NULL; | |
1699 | const struct arc_operand_operation *op; | |
1700 | unsigned int i; | |
1701 | int j; | |
1702 | ||
1703 | for (i = 0; i < arc_num_pseudo_insn; ++i) | |
6f4b1afc | 1704 | { |
4670103e CZ |
1705 | pseudo_insn = &arc_pseudo_insns[i]; |
1706 | if (strcmp (pseudo_insn->mnemonic_p, opname) == 0) | |
1707 | { | |
1708 | op = pseudo_insn->operand; | |
1709 | for (j = 0; j < ntok; ++j) | |
1710 | if (!pseudo_operand_match (&tok[j], &op[j])) | |
1711 | break; | |
1712 | ||
1713 | /* Found the right instruction. */ | |
1714 | if (j == ntok) | |
1715 | return pseudo_insn; | |
1716 | } | |
6f4b1afc | 1717 | } |
4670103e CZ |
1718 | return NULL; |
1719 | } | |
252b5132 | 1720 | |
4670103e | 1721 | /* Assumes the expressionS *tok is of sufficient size. */ |
252b5132 | 1722 | |
4670103e CZ |
1723 | static const struct arc_opcode * |
1724 | find_special_case_pseudo (const char *opname, | |
1725 | int *ntok, | |
1726 | expressionS *tok, | |
1727 | int *nflgs, | |
1728 | struct arc_flags *pflags) | |
1729 | { | |
1730 | const struct arc_pseudo_insn *pseudo_insn = NULL; | |
1731 | const struct arc_operand_operation *operand_pseudo; | |
1732 | const struct arc_operand *operand_real; | |
1733 | unsigned i; | |
1734 | char construct_operand[MAX_CONSTR_STR]; | |
886a2506 | 1735 | |
4670103e CZ |
1736 | /* Find whether opname is in pseudo instruction array. */ |
1737 | pseudo_insn = find_pseudo_insn (opname, *ntok, tok); | |
1738 | ||
1739 | if (pseudo_insn == NULL) | |
1740 | return NULL; | |
1741 | ||
1742 | /* Handle flag, Limited to one flag at the moment. */ | |
1743 | if (pseudo_insn->flag_r != NULL) | |
1744 | *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs], | |
1745 | MAX_INSN_FLGS - *nflgs); | |
1746 | ||
1747 | /* Handle operand operations. */ | |
1748 | for (i = 0; i < pseudo_insn->operand_cnt; ++i) | |
252b5132 | 1749 | { |
4670103e CZ |
1750 | operand_pseudo = &pseudo_insn->operand[i]; |
1751 | operand_real = &arc_operands[operand_pseudo->operand_idx]; | |
886a2506 | 1752 | |
4670103e CZ |
1753 | if (operand_real->flags & ARC_OPERAND_BRAKET && |
1754 | !operand_pseudo->needs_insert) | |
1755 | continue; | |
b125bd17 | 1756 | |
4670103e CZ |
1757 | /* Has to be inserted (i.e. this token does not exist yet). */ |
1758 | if (operand_pseudo->needs_insert) | |
1759 | { | |
1760 | if (operand_real->flags & ARC_OPERAND_BRAKET) | |
1761 | { | |
1762 | tok[i].X_op = O_bracket; | |
1763 | ++(*ntok); | |
1764 | continue; | |
1765 | } | |
b125bd17 | 1766 | |
4670103e CZ |
1767 | /* Check if operand is a register or constant and handle it |
1768 | by type. */ | |
1769 | if (operand_real->flags & ARC_OPERAND_IR) | |
1770 | snprintf (construct_operand, MAX_CONSTR_STR, "r%d", | |
1771 | operand_pseudo->count); | |
1772 | else | |
1773 | snprintf (construct_operand, MAX_CONSTR_STR, "%d", | |
1774 | operand_pseudo->count); | |
886a2506 | 1775 | |
4670103e CZ |
1776 | tokenize_arguments (construct_operand, &tok[i], 1); |
1777 | ++(*ntok); | |
1778 | } | |
1779 | ||
1780 | else if (operand_pseudo->count) | |
1781 | { | |
1782 | /* Operand number has to be adjusted accordingly (by operand | |
1783 | type). */ | |
1784 | switch (tok[i].X_op) | |
1785 | { | |
1786 | case O_constant: | |
1787 | tok[i].X_add_number += operand_pseudo->count; | |
1788 | break; | |
1789 | ||
1790 | case O_symbol: | |
1791 | break; | |
1792 | ||
1793 | default: | |
1794 | /* Ignored. */ | |
1795 | break; | |
1796 | } | |
1797 | } | |
1798 | } | |
1799 | ||
1800 | /* Swap operands if necessary. Only supports one swap at the | |
1801 | moment. */ | |
1802 | for (i = 0; i < pseudo_insn->operand_cnt; ++i) | |
1803 | { | |
1804 | operand_pseudo = &pseudo_insn->operand[i]; | |
1805 | ||
1806 | if (operand_pseudo->swap_operand_idx == i) | |
1807 | continue; | |
1808 | ||
1809 | swap_operand (tok, i, operand_pseudo->swap_operand_idx); | |
1810 | ||
1811 | /* Prevent a swap back later by breaking out. */ | |
1812 | break; | |
1813 | } | |
1814 | ||
1815 | return (const struct arc_opcode *) | |
1816 | hash_find (arc_opcode_hash, pseudo_insn->mnemonic_r); | |
1817 | } | |
1818 | ||
1819 | static const struct arc_opcode * | |
1820 | find_special_case_flag (const char *opname, | |
1821 | int *nflgs, | |
1822 | struct arc_flags *pflags) | |
1823 | { | |
1824 | unsigned int i; | |
1825 | const char *flagnm; | |
1826 | unsigned flag_idx, flag_arr_idx; | |
1827 | size_t flaglen, oplen; | |
1828 | const struct arc_flag_special *arc_flag_special_opcode; | |
1829 | const struct arc_opcode *opcode; | |
1830 | ||
1831 | /* Search for special case instruction. */ | |
1832 | for (i = 0; i < arc_num_flag_special; i++) | |
1833 | { | |
1834 | arc_flag_special_opcode = &arc_flag_special_cases[i]; | |
1835 | oplen = strlen (arc_flag_special_opcode->name); | |
1836 | ||
1837 | if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0) | |
1838 | continue; | |
1839 | ||
1840 | /* Found a potential special case instruction, now test for | |
1841 | flags. */ | |
1842 | for (flag_arr_idx = 0;; ++flag_arr_idx) | |
1843 | { | |
1844 | flag_idx = arc_flag_special_opcode->flags[flag_arr_idx]; | |
1845 | if (flag_idx == 0) | |
1846 | break; /* End of array, nothing found. */ | |
886a2506 | 1847 | |
4670103e CZ |
1848 | flagnm = arc_flag_operands[flag_idx].name; |
1849 | flaglen = strlen (flagnm); | |
1850 | if (strcmp (opname + oplen, flagnm) == 0) | |
1851 | { | |
1852 | opcode = (const struct arc_opcode *) | |
1853 | hash_find (arc_opcode_hash, | |
1854 | arc_flag_special_opcode->name); | |
886a2506 | 1855 | |
4670103e CZ |
1856 | if (*nflgs + 1 > MAX_INSN_FLGS) |
1857 | break; | |
1858 | memcpy (pflags[*nflgs].name, flagnm, flaglen); | |
1859 | pflags[*nflgs].name[flaglen] = '\0'; | |
1860 | (*nflgs)++; | |
1861 | return opcode; | |
1862 | } | |
1863 | } | |
1864 | } | |
1865 | return NULL; | |
1866 | } | |
886a2506 | 1867 | |
4670103e | 1868 | /* Used to find special case opcode. */ |
886a2506 | 1869 | |
4670103e CZ |
1870 | static const struct arc_opcode * |
1871 | find_special_case (const char *opname, | |
1872 | int *nflgs, | |
1873 | struct arc_flags *pflags, | |
1874 | expressionS *tok, | |
1875 | int *ntok) | |
1876 | { | |
1877 | const struct arc_opcode *opcode; | |
886a2506 | 1878 | |
4670103e | 1879 | opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags); |
886a2506 | 1880 | |
4670103e CZ |
1881 | if (opcode == NULL) |
1882 | opcode = find_special_case_flag (opname, nflgs, pflags); | |
886a2506 | 1883 | |
4670103e CZ |
1884 | return opcode; |
1885 | } | |
886a2506 | 1886 | |
4670103e CZ |
1887 | static void |
1888 | preprocess_operands (const struct arc_opcode *opcode, | |
1889 | expressionS *tok, | |
1890 | int ntok) | |
1891 | { | |
1892 | int i; | |
1893 | size_t len; | |
1894 | const char *p; | |
1895 | unsigned j; | |
1896 | const struct arc_aux_reg *auxr; | |
886a2506 | 1897 | |
4670103e | 1898 | for (i = 0; i < ntok; i++) |
886a2506 | 1899 | { |
4670103e | 1900 | switch (tok[i].X_op) |
886a2506 | 1901 | { |
4670103e CZ |
1902 | case O_illegal: |
1903 | case O_absent: | |
1904 | break; /* Throw and error. */ | |
1905 | ||
1906 | case O_symbol: | |
1907 | if (opcode->class != AUXREG) | |
1908 | break; | |
1909 | /* Convert the symbol to a constant if possible. */ | |
1910 | p = S_GET_NAME (tok[i].X_add_symbol); | |
1911 | len = strlen (p); | |
1912 | ||
1913 | auxr = &arc_aux_regs[0]; | |
1914 | for (j = 0; j < arc_num_aux_regs; j++, auxr++) | |
1915 | if (len == auxr->length | |
1916 | && strcasecmp (auxr->name, p) == 0) | |
1917 | { | |
1918 | tok[i].X_op = O_constant; | |
1919 | tok[i].X_add_number = auxr->address; | |
1920 | break; | |
1921 | } | |
886a2506 NC |
1922 | break; |
1923 | default: | |
886a2506 | 1924 | break; |
886a2506 NC |
1925 | } |
1926 | } | |
886a2506 NC |
1927 | } |
1928 | ||
4670103e CZ |
1929 | /* Given an opcode name, pre-tockenized set of argumenst and the |
1930 | opcode flags, take it all the way through emission. */ | |
886a2506 | 1931 | |
4670103e CZ |
1932 | static void |
1933 | assemble_tokens (const char *opname, | |
1934 | expressionS *tok, | |
1935 | int ntok, | |
1936 | struct arc_flags *pflags, | |
1937 | int nflgs) | |
1938 | { | |
1939 | bfd_boolean found_something = FALSE; | |
1940 | const struct arc_opcode *opcode; | |
1941 | int cpumatch = 1; | |
886a2506 | 1942 | |
4670103e CZ |
1943 | /* Search opcodes. */ |
1944 | opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname); | |
886a2506 | 1945 | |
4670103e CZ |
1946 | /* Couldn't find opcode conventional way, try special cases. */ |
1947 | if (!opcode) | |
1948 | opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok); | |
886a2506 | 1949 | |
4670103e CZ |
1950 | if (opcode) |
1951 | { | |
1952 | pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n", | |
1953 | frag_now->fr_file, frag_now->fr_line, opcode->name, | |
1954 | opcode->opcode); | |
886a2506 | 1955 | |
4670103e | 1956 | preprocess_operands (opcode, tok, ntok); |
886a2506 | 1957 | |
4670103e CZ |
1958 | found_something = TRUE; |
1959 | opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch); | |
1960 | if (opcode) | |
1961 | { | |
1962 | struct arc_insn insn; | |
1963 | assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn); | |
1964 | emit_insn (&insn); | |
1965 | return; | |
1966 | } | |
1967 | } | |
886a2506 | 1968 | |
4670103e CZ |
1969 | if (found_something) |
1970 | { | |
1971 | if (cpumatch) | |
1972 | as_bad (_("inappropriate arguments for opcode '%s'"), opname); | |
1973 | else | |
1974 | as_bad (_("opcode '%s' not supported for target %s"), opname, | |
1975 | arc_target_name); | |
1976 | } | |
1977 | else | |
1978 | as_bad (_("unknown opcode '%s'"), opname); | |
886a2506 NC |
1979 | } |
1980 | ||
4670103e | 1981 | /* The public interface to the instruction assembler. */ |
886a2506 | 1982 | |
4670103e CZ |
1983 | void |
1984 | md_assemble (char *str) | |
886a2506 | 1985 | { |
4670103e CZ |
1986 | char *opname; |
1987 | expressionS tok[MAX_INSN_ARGS]; | |
1988 | int ntok, nflg; | |
1989 | size_t opnamelen; | |
1990 | struct arc_flags flags[MAX_INSN_FLGS]; | |
886a2506 | 1991 | |
4670103e CZ |
1992 | /* Split off the opcode. */ |
1993 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468"); | |
1994 | opname = xmalloc (opnamelen + 1); | |
1995 | memcpy (opname, str, opnamelen); | |
1996 | opname[opnamelen] = '\0'; | |
886a2506 | 1997 | |
4670103e CZ |
1998 | /* Signalize we are assmbling the instructions. */ |
1999 | assembling_insn = TRUE; | |
886a2506 | 2000 | |
4670103e CZ |
2001 | /* Tokenize the flags. */ |
2002 | if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1) | |
2003 | { | |
2004 | as_bad (_("syntax error")); | |
2005 | return; | |
2006 | } | |
886a2506 | 2007 | |
4670103e CZ |
2008 | /* Scan up to the end of the mnemonic which must end in space or end |
2009 | of string. */ | |
2010 | str += opnamelen; | |
2011 | for (; *str != '\0'; str++) | |
2012 | if (*str == ' ') | |
2013 | break; | |
886a2506 | 2014 | |
4670103e CZ |
2015 | /* Tokenize the rest of the line. */ |
2016 | if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0) | |
886a2506 | 2017 | { |
4670103e CZ |
2018 | as_bad (_("syntax error")); |
2019 | return; | |
252b5132 RH |
2020 | } |
2021 | ||
4670103e CZ |
2022 | /* Finish it off. */ |
2023 | assemble_tokens (opname, tok, ntok, flags, nflg); | |
2024 | assembling_insn = FALSE; | |
2025 | } | |
2026 | ||
2027 | /* Callback to insert a register into the hash table. */ | |
2028 | ||
2029 | static void | |
2030 | declare_register (char *name, int number) | |
2031 | { | |
2032 | const char *err; | |
2033 | symbolS *regS = symbol_create (name, reg_section, | |
2034 | number, &zero_address_frag); | |
2035 | ||
2036 | err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS); | |
2037 | if (err) | |
2038 | as_fatal ("Inserting \"%s\" into register table failed: %s", | |
2039 | name, err); | |
2040 | } | |
252b5132 | 2041 | |
4670103e | 2042 | /* Construct symbols for each of the general registers. */ |
252b5132 | 2043 | |
4670103e CZ |
2044 | static void |
2045 | declare_register_set (void) | |
2046 | { | |
2047 | int i; | |
2048 | for (i = 0; i < 64; ++i) | |
886a2506 | 2049 | { |
4670103e CZ |
2050 | char name[7]; |
2051 | ||
2052 | sprintf (name, "r%d", i); | |
2053 | declare_register (name, i); | |
2054 | if ((i & 0x01) == 0) | |
886a2506 | 2055 | { |
4670103e CZ |
2056 | sprintf (name, "r%dr%d", i, i+1); |
2057 | declare_register (name, i); | |
886a2506 NC |
2058 | } |
2059 | } | |
252b5132 | 2060 | } |
ea1562b3 | 2061 | |
4670103e CZ |
2062 | /* Port-specific assembler initialization. This function is called |
2063 | once, at assembler startup time. */ | |
ea1562b3 NC |
2064 | |
2065 | void | |
4670103e | 2066 | md_begin (void) |
ea1562b3 | 2067 | { |
4670103e | 2068 | unsigned int i; |
886a2506 | 2069 | |
4670103e CZ |
2070 | /* The endianness can be chosen "at the factory". */ |
2071 | target_big_endian = byte_order == BIG_ENDIAN; | |
886a2506 | 2072 | |
4670103e CZ |
2073 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type)) |
2074 | as_warn (_("could not set architecture and machine")); | |
2075 | ||
2076 | /* Set elf header flags. */ | |
2077 | bfd_set_private_flags (stdoutput, arc_eflag); | |
2078 | ||
2079 | /* Set up a hash table for the instructions. */ | |
2080 | arc_opcode_hash = hash_new (); | |
2081 | if (arc_opcode_hash == NULL) | |
2082 | as_fatal (_("Virtual memory exhausted")); | |
2083 | ||
2084 | /* Initialize the hash table with the insns. */ | |
2085 | for (i = 0; i < arc_num_opcodes;) | |
ea1562b3 | 2086 | { |
4670103e | 2087 | const char *name, *retval; |
886a2506 | 2088 | |
4670103e CZ |
2089 | name = arc_opcodes[i].name; |
2090 | retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]); | |
2091 | if (retval) | |
2092 | as_fatal (_("internal error: can't hash opcode '%s': %s"), | |
2093 | name, retval); | |
2094 | ||
2095 | while (++i < arc_num_opcodes | |
2096 | && (arc_opcodes[i].name == name | |
2097 | || !strcmp (arc_opcodes[i].name, name))) | |
2098 | continue; | |
ea1562b3 | 2099 | } |
4670103e CZ |
2100 | |
2101 | /* Register declaration. */ | |
2102 | arc_reg_hash = hash_new (); | |
2103 | if (arc_reg_hash == NULL) | |
2104 | as_fatal (_("Virtual memory exhausted")); | |
2105 | ||
2106 | declare_register_set (); | |
2107 | declare_register ("gp", 26); | |
2108 | declare_register ("fp", 27); | |
2109 | declare_register ("sp", 28); | |
2110 | declare_register ("ilink", 29); | |
2111 | declare_register ("ilink1", 29); | |
2112 | declare_register ("ilink2", 30); | |
2113 | declare_register ("blink", 31); | |
2114 | ||
2115 | declare_register ("mlo", 57); | |
2116 | declare_register ("mmid", 58); | |
2117 | declare_register ("mhi", 59); | |
2118 | ||
2119 | declare_register ("acc1", 56); | |
2120 | declare_register ("acc2", 57); | |
2121 | ||
2122 | declare_register ("lp_count", 60); | |
2123 | declare_register ("pcl", 63); | |
2124 | ||
2125 | /* Initialize the last instructions. */ | |
2126 | memset (&arc_last_insns[0], 0, sizeof (arc_last_insns)); | |
886a2506 | 2127 | } |
ea1562b3 | 2128 | |
4670103e CZ |
2129 | /* Write a value out to the object file, using the appropriate |
2130 | endianness. */ | |
ea1562b3 | 2131 | |
4670103e CZ |
2132 | void |
2133 | md_number_to_chars (char *buf, | |
2134 | valueT val, | |
2135 | int n) | |
886a2506 | 2136 | { |
4670103e CZ |
2137 | if (target_big_endian) |
2138 | number_to_chars_bigendian (buf, val, n); | |
2139 | else | |
2140 | number_to_chars_littleendian (buf, val, n); | |
886a2506 | 2141 | } |
ea1562b3 | 2142 | |
4670103e | 2143 | /* Round up a section size to the appropriate boundary. */ |
ea1562b3 | 2144 | |
4670103e CZ |
2145 | valueT |
2146 | md_section_align (segT segment, | |
2147 | valueT size) | |
886a2506 | 2148 | { |
4670103e CZ |
2149 | int align = bfd_get_section_alignment (stdoutput, segment); |
2150 | ||
2151 | return ((size + (1 << align) - 1) & (-((valueT) 1 << align))); | |
886a2506 | 2152 | } |
ea1562b3 | 2153 | |
4670103e CZ |
2154 | /* The location from which a PC relative jump should be calculated, |
2155 | given a PC relative reloc. */ | |
ea1562b3 | 2156 | |
4670103e CZ |
2157 | long |
2158 | md_pcrel_from_section (fixS *fixP, | |
2159 | segT sec) | |
886a2506 | 2160 | { |
4670103e | 2161 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
ea1562b3 | 2162 | |
4670103e | 2163 | pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset); |
ea1562b3 | 2164 | |
4670103e CZ |
2165 | if (fixP->fx_addsy != (symbolS *) NULL |
2166 | && (!S_IS_DEFINED (fixP->fx_addsy) | |
2167 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
2168 | { | |
2169 | pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy)); | |
ea1562b3 | 2170 | |
4670103e CZ |
2171 | /* The symbol is undefined (or is defined but not in this section). |
2172 | Let the linker figure it out. */ | |
2173 | return 0; | |
2174 | } | |
2175 | ||
2176 | if ((int) fixP->fx_r_type < 0) | |
886a2506 | 2177 | { |
4670103e CZ |
2178 | /* These are the "internal" relocations. Align them to |
2179 | 32 bit boundary (PCL), for the moment. */ | |
2180 | base &= ~3; | |
886a2506 | 2181 | } |
4670103e CZ |
2182 | else |
2183 | { | |
2184 | switch (fixP->fx_r_type) | |
2185 | { | |
2186 | case BFD_RELOC_ARC_PC32: | |
2187 | /* The hardware calculates relative to the start of the | |
2188 | insn, but this relocation is relative to location of the | |
2189 | LIMM, compensate. The base always needs to be | |
2190 | substracted by 4 as we do not support this type of PCrel | |
2191 | relocation for short instructions. */ | |
2192 | base -= 4; | |
2193 | /* Fall through. */ | |
2194 | case BFD_RELOC_ARC_PLT32: | |
2195 | case BFD_RELOC_ARC_S25H_PCREL_PLT: | |
2196 | case BFD_RELOC_ARC_S21H_PCREL_PLT: | |
2197 | case BFD_RELOC_ARC_S25W_PCREL_PLT: | |
2198 | case BFD_RELOC_ARC_S21W_PCREL_PLT: | |
2199 | ||
2200 | case BFD_RELOC_ARC_S21H_PCREL: | |
2201 | case BFD_RELOC_ARC_S25H_PCREL: | |
2202 | case BFD_RELOC_ARC_S13_PCREL: | |
2203 | case BFD_RELOC_ARC_S21W_PCREL: | |
2204 | case BFD_RELOC_ARC_S25W_PCREL: | |
2205 | base &= ~3; | |
2206 | break; | |
2207 | default: | |
2208 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2209 | _("unhandled reloc %s in md_pcrel_from_section"), | |
2210 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
2211 | break; | |
2212 | } | |
2213 | } | |
2214 | ||
2215 | pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n", | |
2216 | fixP->fx_frag->fr_address, fixP->fx_where, base, | |
2217 | fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)", | |
2218 | fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0); | |
2219 | ||
2220 | return base; | |
886a2506 | 2221 | } |
ea1562b3 | 2222 | |
4670103e | 2223 | /* Given a BFD relocation find the coresponding operand. */ |
ea1562b3 | 2224 | |
4670103e CZ |
2225 | static const struct arc_operand * |
2226 | find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc) | |
2227 | { | |
2228 | unsigned i; | |
ea1562b3 | 2229 | |
4670103e CZ |
2230 | for (i = 0; i < arc_num_operands; i++) |
2231 | if (arc_operands[i].default_reloc == reloc) | |
2232 | return &arc_operands[i]; | |
2233 | return NULL; | |
2234 | } | |
ea1562b3 | 2235 | |
4670103e | 2236 | /* Insert an operand value into an instruction. */ |
ea1562b3 | 2237 | |
4670103e CZ |
2238 | static unsigned |
2239 | insert_operand (unsigned insn, | |
2240 | const struct arc_operand *operand, | |
2241 | offsetT val, | |
2242 | char *file, | |
2243 | unsigned line) | |
886a2506 | 2244 | { |
4670103e | 2245 | offsetT min = 0, max = 0; |
ea1562b3 | 2246 | |
4670103e CZ |
2247 | if (operand->bits != 32 |
2248 | && !(operand->flags & ARC_OPERAND_NCHK) | |
2249 | && !(operand->flags & ARC_OPERAND_FAKE)) | |
886a2506 | 2250 | { |
4670103e CZ |
2251 | if (operand->flags & ARC_OPERAND_SIGNED) |
2252 | { | |
2253 | max = (1 << (operand->bits - 1)) - 1; | |
2254 | min = -(1 << (operand->bits - 1)); | |
2255 | } | |
2256 | else | |
2257 | { | |
2258 | max = (1 << operand->bits) - 1; | |
2259 | min = 0; | |
2260 | } | |
886a2506 | 2261 | |
4670103e CZ |
2262 | if (val < min || val > max) |
2263 | as_bad_value_out_of_range (_("operand"), | |
2264 | val, min, max, file, line); | |
2265 | } | |
ea1562b3 | 2266 | |
4670103e CZ |
2267 | pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n", |
2268 | min, val, max, insn); | |
ea1562b3 | 2269 | |
4670103e CZ |
2270 | if ((operand->flags & ARC_OPERAND_ALIGNED32) |
2271 | && (val & 0x03)) | |
2272 | as_bad_where (file, line, | |
2273 | _("Unaligned operand. Needs to be 32bit aligned")); | |
ea1562b3 | 2274 | |
4670103e CZ |
2275 | if ((operand->flags & ARC_OPERAND_ALIGNED16) |
2276 | && (val & 0x01)) | |
2277 | as_bad_where (file, line, | |
2278 | _("Unaligned operand. Needs to be 16bit aligned")); | |
ea1562b3 | 2279 | |
4670103e CZ |
2280 | if (operand->insert) |
2281 | { | |
2282 | const char *errmsg = NULL; | |
ea1562b3 | 2283 | |
4670103e CZ |
2284 | insn = (*operand->insert) (insn, val, &errmsg); |
2285 | if (errmsg) | |
2286 | as_warn_where (file, line, "%s", errmsg); | |
2287 | } | |
2288 | else | |
2289 | { | |
2290 | if (operand->flags & ARC_OPERAND_TRUNCATE) | |
2291 | { | |
2292 | if (operand->flags & ARC_OPERAND_ALIGNED32) | |
2293 | val >>= 2; | |
2294 | if (operand->flags & ARC_OPERAND_ALIGNED16) | |
2295 | val >>= 1; | |
886a2506 | 2296 | } |
4670103e CZ |
2297 | insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift); |
2298 | } | |
2299 | return insn; | |
2300 | } | |
ea1562b3 | 2301 | |
4670103e CZ |
2302 | /* Apply a fixup to the object code. At this point all symbol values |
2303 | should be fully resolved, and we attempt to completely resolve the | |
2304 | reloc. If we can not do that, we determine the correct reloc code | |
2305 | and put it back in the fixup. To indicate that a fixup has been | |
2306 | eliminated, set fixP->fx_done. */ | |
ea1562b3 | 2307 | |
4670103e CZ |
2308 | void |
2309 | md_apply_fix (fixS *fixP, | |
2310 | valueT *valP, | |
2311 | segT seg) | |
2312 | { | |
2313 | char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
2314 | valueT value = *valP; | |
2315 | unsigned insn = 0; | |
2316 | symbolS *fx_addsy, *fx_subsy; | |
2317 | offsetT fx_offset; | |
2318 | segT add_symbol_segment = absolute_section; | |
2319 | segT sub_symbol_segment = absolute_section; | |
2320 | const struct arc_operand *operand = NULL; | |
2321 | extended_bfd_reloc_code_real_type reloc; | |
886a2506 | 2322 | |
4670103e CZ |
2323 | pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", |
2324 | fixP->fx_file, fixP->fx_line, fixP->fx_r_type, | |
2325 | ((int) fixP->fx_r_type < 0) ? "Internal": | |
2326 | bfd_get_reloc_code_name (fixP->fx_r_type), value, | |
2327 | fixP->fx_offset); | |
886a2506 | 2328 | |
4670103e CZ |
2329 | fx_addsy = fixP->fx_addsy; |
2330 | fx_subsy = fixP->fx_subsy; | |
2331 | fx_offset = 0; | |
886a2506 | 2332 | |
4670103e CZ |
2333 | if (fx_addsy) |
2334 | { | |
2335 | add_symbol_segment = S_GET_SEGMENT (fx_addsy); | |
886a2506 NC |
2336 | } |
2337 | ||
4670103e CZ |
2338 | if (fx_subsy |
2339 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF | |
2340 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9 | |
2341 | && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD) | |
2342 | { | |
2343 | resolve_symbol_value (fx_subsy); | |
2344 | sub_symbol_segment = S_GET_SEGMENT (fx_subsy); | |
886a2506 | 2345 | |
4670103e CZ |
2346 | if (sub_symbol_segment == absolute_section) |
2347 | { | |
2348 | /* The symbol is really a constant. */ | |
2349 | fx_offset -= S_GET_VALUE (fx_subsy); | |
2350 | fx_subsy = NULL; | |
2351 | } | |
2352 | else | |
2353 | { | |
2354 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2355 | _("can't resolve `%s' {%s section} - `%s' {%s section}"), | |
2356 | fx_addsy ? S_GET_NAME (fx_addsy) : "0", | |
2357 | segment_name (add_symbol_segment), | |
2358 | S_GET_NAME (fx_subsy), | |
2359 | segment_name (sub_symbol_segment)); | |
2360 | return; | |
2361 | } | |
2362 | } | |
886a2506 | 2363 | |
4670103e CZ |
2364 | if (fx_addsy |
2365 | && !S_IS_WEAK (fx_addsy)) | |
2366 | { | |
2367 | if (add_symbol_segment == seg | |
2368 | && fixP->fx_pcrel) | |
2369 | { | |
2370 | value += S_GET_VALUE (fx_addsy); | |
2371 | value -= md_pcrel_from_section (fixP, seg); | |
2372 | fx_addsy = NULL; | |
2373 | fixP->fx_pcrel = FALSE; | |
2374 | } | |
2375 | else if (add_symbol_segment == absolute_section) | |
2376 | { | |
2377 | value = fixP->fx_offset; | |
2378 | fx_offset += S_GET_VALUE (fixP->fx_addsy); | |
2379 | fx_addsy = NULL; | |
2380 | fixP->fx_pcrel = FALSE; | |
2381 | } | |
2382 | } | |
886a2506 | 2383 | |
4670103e CZ |
2384 | if (!fx_addsy) |
2385 | fixP->fx_done = TRUE; | |
886a2506 | 2386 | |
4670103e | 2387 | if (fixP->fx_pcrel) |
886a2506 | 2388 | { |
4670103e CZ |
2389 | if (fx_addsy |
2390 | && ((S_IS_DEFINED (fx_addsy) | |
2391 | && S_GET_SEGMENT (fx_addsy) != seg) | |
2392 | || S_IS_WEAK (fx_addsy))) | |
2393 | value += md_pcrel_from_section (fixP, seg); | |
886a2506 | 2394 | |
4670103e CZ |
2395 | switch (fixP->fx_r_type) |
2396 | { | |
2397 | case BFD_RELOC_ARC_32_ME: | |
2398 | /* This is a pc-relative value in a LIMM. Adjust it to the | |
2399 | address of the instruction not to the address of the | |
2400 | LIMM. Note: it is not anylonger valid this afirmation as | |
2401 | the linker consider ARC_PC32 a fixup to entire 64 bit | |
2402 | insn. */ | |
2403 | fixP->fx_offset += fixP->fx_frag->fr_address; | |
2404 | /* Fall through. */ | |
2405 | case BFD_RELOC_32: | |
2406 | fixP->fx_r_type = BFD_RELOC_ARC_PC32; | |
2407 | /* Fall through. */ | |
2408 | case BFD_RELOC_ARC_PC32: | |
2409 | /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */ | |
886a2506 NC |
2410 | break; |
2411 | default: | |
4670103e CZ |
2412 | if ((int) fixP->fx_r_type < 0) |
2413 | as_fatal (_("PC relative relocation not allowed for (internal) type %d"), | |
2414 | fixP->fx_r_type); | |
886a2506 | 2415 | break; |
ea1562b3 NC |
2416 | } |
2417 | } | |
2418 | ||
4670103e CZ |
2419 | pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", |
2420 | fixP->fx_file, fixP->fx_line, fixP->fx_r_type, | |
2421 | ((int) fixP->fx_r_type < 0) ? "Internal": | |
2422 | bfd_get_reloc_code_name (fixP->fx_r_type), value, | |
2423 | fixP->fx_offset); | |
886a2506 | 2424 | |
886a2506 | 2425 | |
4670103e CZ |
2426 | /* Now check for TLS relocations. */ |
2427 | reloc = fixP->fx_r_type; | |
2428 | switch (reloc) | |
886a2506 | 2429 | { |
4670103e CZ |
2430 | case BFD_RELOC_ARC_TLS_DTPOFF: |
2431 | case BFD_RELOC_ARC_TLS_LE_32: | |
2432 | if (fixP->fx_done) | |
2433 | break; | |
2434 | /* Fall through. */ | |
2435 | case BFD_RELOC_ARC_TLS_GD_GOT: | |
2436 | case BFD_RELOC_ARC_TLS_IE_GOT: | |
2437 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2438 | break; | |
886a2506 | 2439 | |
4670103e CZ |
2440 | case BFD_RELOC_ARC_TLS_GD_LD: |
2441 | gas_assert (!fixP->fx_offset); | |
2442 | if (fixP->fx_subsy) | |
2443 | fixP->fx_offset | |
2444 | = (S_GET_VALUE (fixP->fx_subsy) | |
2445 | - fixP->fx_frag->fr_address- fixP->fx_where); | |
2446 | fixP->fx_subsy = NULL; | |
2447 | /* Fall through. */ | |
2448 | case BFD_RELOC_ARC_TLS_GD_CALL: | |
2449 | /* These two relocs are there just to allow ld to change the tls | |
2450 | model for this symbol, by patching the code. The offset - | |
2451 | and scale, if any - will be installed by the linker. */ | |
2452 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2453 | break; | |
886a2506 | 2454 | |
4670103e CZ |
2455 | case BFD_RELOC_ARC_TLS_LE_S9: |
2456 | case BFD_RELOC_ARC_TLS_DTPOFF_S9: | |
2457 | as_bad (_("TLS_*_S9 relocs are not supported yet")); | |
2458 | break; | |
2459 | ||
2460 | default: | |
2461 | break; | |
886a2506 NC |
2462 | } |
2463 | ||
4670103e | 2464 | if (!fixP->fx_done) |
886a2506 | 2465 | { |
4670103e | 2466 | return; |
886a2506 | 2467 | } |
886a2506 | 2468 | |
4670103e CZ |
2469 | /* Addjust the value if we have a constant. */ |
2470 | value += fx_offset; | |
886a2506 | 2471 | |
4670103e CZ |
2472 | /* For hosts with longs bigger than 32-bits make sure that the top |
2473 | bits of a 32-bit negative value read in by the parser are set, | |
2474 | so that the correct comparisons are made. */ | |
2475 | if (value & 0x80000000) | |
2476 | value |= (-1L << 31); | |
886a2506 | 2477 | |
4670103e CZ |
2478 | reloc = fixP->fx_r_type; |
2479 | switch (reloc) | |
2480 | { | |
2481 | case BFD_RELOC_8: | |
2482 | case BFD_RELOC_16: | |
2483 | case BFD_RELOC_24: | |
2484 | case BFD_RELOC_32: | |
2485 | case BFD_RELOC_64: | |
2486 | case BFD_RELOC_ARC_32_PCREL: | |
2487 | md_number_to_chars (fixpos, value, fixP->fx_size); | |
2488 | return; | |
886a2506 | 2489 | |
4670103e CZ |
2490 | case BFD_RELOC_ARC_GOTPC32: |
2491 | /* I cannot fix an GOTPC relocation because I need to relax it | |
2492 | from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */ | |
2493 | as_bad (_("Unsupported operation on reloc")); | |
2494 | return; | |
886a2506 | 2495 | |
4670103e CZ |
2496 | case BFD_RELOC_ARC_TLS_DTPOFF: |
2497 | case BFD_RELOC_ARC_TLS_LE_32: | |
2498 | gas_assert (!fixP->fx_addsy); | |
2499 | gas_assert (!fixP->fx_subsy); | |
886a2506 | 2500 | |
4670103e CZ |
2501 | case BFD_RELOC_ARC_GOTOFF: |
2502 | case BFD_RELOC_ARC_32_ME: | |
2503 | case BFD_RELOC_ARC_PC32: | |
2504 | md_number_to_chars_midend (fixpos, value, fixP->fx_size); | |
2505 | return; | |
886a2506 | 2506 | |
4670103e CZ |
2507 | case BFD_RELOC_ARC_PLT32: |
2508 | md_number_to_chars_midend (fixpos, value, fixP->fx_size); | |
2509 | return; | |
886a2506 | 2510 | |
4670103e CZ |
2511 | case BFD_RELOC_ARC_S25H_PCREL_PLT: |
2512 | reloc = BFD_RELOC_ARC_S25W_PCREL; | |
2513 | goto solve_plt; | |
886a2506 | 2514 | |
4670103e CZ |
2515 | case BFD_RELOC_ARC_S21H_PCREL_PLT: |
2516 | reloc = BFD_RELOC_ARC_S21H_PCREL; | |
2517 | goto solve_plt; | |
886a2506 | 2518 | |
4670103e CZ |
2519 | case BFD_RELOC_ARC_S25W_PCREL_PLT: |
2520 | reloc = BFD_RELOC_ARC_S25W_PCREL; | |
2521 | goto solve_plt; | |
886a2506 | 2522 | |
4670103e CZ |
2523 | case BFD_RELOC_ARC_S21W_PCREL_PLT: |
2524 | reloc = BFD_RELOC_ARC_S21W_PCREL; | |
886a2506 | 2525 | |
4670103e CZ |
2526 | case BFD_RELOC_ARC_S25W_PCREL: |
2527 | case BFD_RELOC_ARC_S21W_PCREL: | |
2528 | case BFD_RELOC_ARC_S21H_PCREL: | |
2529 | case BFD_RELOC_ARC_S25H_PCREL: | |
2530 | case BFD_RELOC_ARC_S13_PCREL: | |
2531 | solve_plt: | |
2532 | operand = find_operand_for_reloc (reloc); | |
2533 | gas_assert (operand); | |
886a2506 NC |
2534 | break; |
2535 | ||
2536 | default: | |
4670103e CZ |
2537 | { |
2538 | if ((int) fixP->fx_r_type >= 0) | |
2539 | as_fatal (_("unhandled relocation type %s"), | |
2540 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
886a2506 | 2541 | |
4670103e CZ |
2542 | /* The rest of these fixups needs to be completely resolved as |
2543 | constants. */ | |
2544 | if (fixP->fx_addsy != 0 | |
2545 | && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section) | |
2546 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2547 | _("non-absolute expression in constant field")); | |
886a2506 | 2548 | |
4670103e CZ |
2549 | gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands); |
2550 | operand = &arc_operands[-(int) fixP->fx_r_type]; | |
2551 | break; | |
2552 | } | |
2553 | } | |
886a2506 | 2554 | |
4670103e | 2555 | if (target_big_endian) |
886a2506 | 2556 | { |
4670103e | 2557 | switch (fixP->fx_size) |
886a2506 | 2558 | { |
4670103e CZ |
2559 | case 4: |
2560 | insn = bfd_getb32 (fixpos); | |
2561 | break; | |
2562 | case 2: | |
2563 | insn = bfd_getb16 (fixpos); | |
2564 | break; | |
2565 | default: | |
2566 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2567 | _("unknown fixup size")); | |
2568 | } | |
2569 | } | |
2570 | else | |
2571 | { | |
2572 | insn = 0; | |
2573 | switch (fixP->fx_size) | |
2574 | { | |
2575 | case 4: | |
2576 | insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2); | |
2577 | break; | |
2578 | case 2: | |
2579 | insn = bfd_getl16 (fixpos); | |
2580 | break; | |
2581 | default: | |
2582 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2583 | _("unknown fixup size")); | |
886a2506 NC |
2584 | } |
2585 | } | |
886a2506 | 2586 | |
4670103e CZ |
2587 | insn = insert_operand (insn, operand, (offsetT) value, |
2588 | fixP->fx_file, fixP->fx_line); | |
886a2506 | 2589 | |
4670103e CZ |
2590 | md_number_to_chars_midend (fixpos, insn, fixP->fx_size); |
2591 | } | |
886a2506 | 2592 | |
4670103e | 2593 | /* Prepare machine-dependent frags for relaxation. |
886a2506 | 2594 | |
4670103e CZ |
2595 | Called just before relaxation starts. Any symbol that is now undefined |
2596 | will not become defined. | |
886a2506 | 2597 | |
4670103e | 2598 | Return the correct fr_subtype in the frag. |
886a2506 | 2599 | |
4670103e CZ |
2600 | Return the initial "guess for fr_var" to caller. The guess for fr_var |
2601 | is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix | |
2602 | or fr_var contributes to our returned value. | |
886a2506 | 2603 | |
4670103e CZ |
2604 | Although it may not be explicit in the frag, pretend |
2605 | fr_var starts with a value. */ | |
886a2506 | 2606 | |
4670103e CZ |
2607 | int |
2608 | md_estimate_size_before_relax (fragS *fragP, | |
2609 | segT segment) | |
2610 | { | |
2611 | int growth; | |
2612 | ||
2613 | /* If the symbol is not located within the same section AND it's not | |
2614 | an absolute section, use the maximum. OR if the symbol is a | |
2615 | constant AND the insn is by nature not pc-rel, use the maximum. | |
2616 | OR if the symbol is being equated against another symbol, use the | |
2617 | maximum. OR if the symbol is weak use the maximum. */ | |
2618 | if ((S_GET_SEGMENT (fragP->fr_symbol) != segment | |
2619 | && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) | |
2620 | || (symbol_constant_p (fragP->fr_symbol) | |
2621 | && !fragP->tc_frag_data.pcrel) | |
2622 | || symbol_equated_p (fragP->fr_symbol) | |
2623 | || S_IS_WEAK (fragP->fr_symbol)) | |
2624 | { | |
2625 | while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE) | |
2626 | ++fragP->fr_subtype; | |
2627 | } | |
886a2506 | 2628 | |
4670103e CZ |
2629 | growth = md_relax_table[fragP->fr_subtype].rlx_length; |
2630 | fragP->fr_var = growth; | |
886a2506 | 2631 | |
4670103e CZ |
2632 | pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n", |
2633 | fragP->fr_file, fragP->fr_line, growth); | |
886a2506 | 2634 | |
4670103e CZ |
2635 | return growth; |
2636 | } | |
886a2506 | 2637 | |
4670103e CZ |
2638 | /* Translate internal representation of relocation info to BFD target |
2639 | format. */ | |
886a2506 | 2640 | |
4670103e CZ |
2641 | arelent * |
2642 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, | |
2643 | fixS *fixP) | |
2644 | { | |
2645 | arelent *reloc; | |
2646 | bfd_reloc_code_real_type code; | |
886a2506 | 2647 | |
4670103e CZ |
2648 | reloc = (arelent *) xmalloc (sizeof (* reloc)); |
2649 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2650 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2651 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
886a2506 | 2652 | |
4670103e CZ |
2653 | /* Make sure none of our internal relocations make it this far. |
2654 | They'd better have been fully resolved by this point. */ | |
2655 | gas_assert ((int) fixP->fx_r_type > 0); | |
886a2506 | 2656 | |
4670103e | 2657 | code = fixP->fx_r_type; |
886a2506 | 2658 | |
4670103e CZ |
2659 | /* if we have something like add gp, pcl, |
2660 | _GLOBAL_OFFSET_TABLE_@gotpc. */ | |
2661 | if (code == BFD_RELOC_ARC_GOTPC32 | |
2662 | && GOT_symbol | |
2663 | && fixP->fx_addsy == GOT_symbol) | |
2664 | code = BFD_RELOC_ARC_GOTPC; | |
886a2506 | 2665 | |
4670103e CZ |
2666 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
2667 | if (reloc->howto == NULL) | |
886a2506 | 2668 | { |
4670103e CZ |
2669 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2670 | _("cannot represent `%s' relocation in object file"), | |
2671 | bfd_get_reloc_code_name (code)); | |
2672 | return NULL; | |
2673 | } | |
886a2506 | 2674 | |
4670103e CZ |
2675 | if (!fixP->fx_pcrel != !reloc->howto->pc_relative) |
2676 | as_fatal (_("internal error? cannot generate `%s' relocation"), | |
2677 | bfd_get_reloc_code_name (code)); | |
886a2506 | 2678 | |
4670103e | 2679 | gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); |
886a2506 | 2680 | |
4670103e CZ |
2681 | if (code == BFD_RELOC_ARC_TLS_DTPOFF |
2682 | || code == BFD_RELOC_ARC_TLS_DTPOFF_S9) | |
2683 | { | |
2684 | asymbol *sym | |
2685 | = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL; | |
2686 | /* We just want to store a 24 bit index, but we have to wait | |
2687 | till after write_contents has been called via | |
2688 | bfd_map_over_sections before we can get the index from | |
2689 | _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs | |
2690 | function is elf32-arc.c has to pick up the slack. | |
2691 | Unfortunately, this leads to problems with hosts that have | |
2692 | pointers wider than long (bfd_vma). There would be various | |
2693 | ways to handle this, all error-prone :-( */ | |
2694 | reloc->addend = (bfd_vma) sym; | |
2695 | if ((asymbol *) reloc->addend != sym) | |
2696 | { | |
2697 | as_bad ("Can't store pointer\n"); | |
2698 | return NULL; | |
886a2506 NC |
2699 | } |
2700 | } | |
4670103e CZ |
2701 | else |
2702 | reloc->addend = fixP->fx_offset; | |
2703 | ||
2704 | return reloc; | |
886a2506 NC |
2705 | } |
2706 | ||
4670103e CZ |
2707 | /* Perform post-processing of machine-dependent frags after relaxation. |
2708 | Called after relaxation is finished. | |
2709 | In: Address of frag. | |
2710 | fr_type == rs_machine_dependent. | |
2711 | fr_subtype is what the address relaxed to. | |
886a2506 | 2712 | |
4670103e CZ |
2713 | Out: Any fixS:s and constants are set up. */ |
2714 | ||
2715 | void | |
2716 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, | |
2717 | segT segment ATTRIBUTE_UNUSED, | |
2718 | fragS *fragP) | |
886a2506 | 2719 | { |
4670103e CZ |
2720 | const relax_typeS *table_entry; |
2721 | char *dest; | |
2722 | const struct arc_opcode *opcode; | |
2723 | struct arc_insn insn; | |
2724 | int size, fix; | |
2725 | struct arc_relax_type *relax_arg = &fragP->tc_frag_data; | |
886a2506 | 2726 | |
4670103e CZ |
2727 | fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix); |
2728 | dest = fragP->fr_literal + fix; | |
2729 | table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype; | |
886a2506 | 2730 | |
4670103e CZ |
2731 | pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n", |
2732 | fragP->fr_file, fragP->fr_line, | |
2733 | fragP->fr_subtype, fix, fragP->fr_var); | |
886a2506 | 2734 | |
4670103e CZ |
2735 | if (fragP->fr_subtype <= 0 |
2736 | && fragP->fr_subtype >= arc_num_relax_opcodes) | |
2737 | as_fatal (_("no relaxation found for this instruction.")); | |
886a2506 | 2738 | |
4670103e | 2739 | opcode = &arc_relax_opcodes[fragP->fr_subtype]; |
886a2506 | 2740 | |
4670103e CZ |
2741 | assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags, |
2742 | relax_arg->nflg, &insn); | |
886a2506 | 2743 | |
4670103e | 2744 | apply_fixups (&insn, fragP, fix); |
886a2506 | 2745 | |
4670103e CZ |
2746 | size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4); |
2747 | gas_assert (table_entry->rlx_length == size); | |
2748 | emit_insn0 (&insn, dest, TRUE); | |
886a2506 | 2749 | |
4670103e CZ |
2750 | fragP->fr_fix += table_entry->rlx_length; |
2751 | fragP->fr_var = 0; | |
886a2506 NC |
2752 | } |
2753 | ||
4670103e CZ |
2754 | /* We have no need to default values of symbols. We could catch |
2755 | register names here, but that is handled by inserting them all in | |
2756 | the symbol table to begin with. */ | |
886a2506 | 2757 | |
4670103e CZ |
2758 | symbolS * |
2759 | md_undefined_symbol (char *name) | |
886a2506 | 2760 | { |
4670103e CZ |
2761 | /* The arc abi demands that a GOT[0] should be referencible as |
2762 | [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a | |
2763 | GOTPC reference to _GLOBAL_OFFSET_TABLE_. */ | |
2764 | if (((*name == '_') | |
2765 | && (*(name+1) == 'G') | |
2766 | && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)) | |
2767 | || ((*name == '_') | |
2768 | && (*(name+1) == 'D') | |
2769 | && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0))) | |
886a2506 | 2770 | { |
4670103e CZ |
2771 | if (!GOT_symbol) |
2772 | { | |
2773 | if (symbol_find (name)) | |
2774 | as_bad ("GOT already in symbol table"); | |
2775 | ||
2776 | GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section, | |
2777 | (valueT) 0, &zero_address_frag); | |
2778 | }; | |
2779 | return GOT_symbol; | |
886a2506 | 2780 | } |
4670103e | 2781 | return NULL; |
886a2506 NC |
2782 | } |
2783 | ||
4670103e CZ |
2784 | /* Turn a string in input_line_pointer into a floating point constant |
2785 | of type type, and store the appropriate bytes in *litP. The number | |
2786 | of LITTLENUMS emitted is stored in *sizeP. An error message is | |
2787 | returned, or NULL on OK. */ | |
886a2506 | 2788 | |
4670103e CZ |
2789 | char * |
2790 | md_atof (int type, char *litP, int *sizeP) | |
886a2506 | 2791 | { |
4670103e CZ |
2792 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
2793 | } | |
886a2506 | 2794 | |
4670103e CZ |
2795 | /* Called for any expression that can not be recognized. When the |
2796 | function is called, `input_line_pointer' will point to the start of | |
2797 | the expression. */ | |
886a2506 | 2798 | |
4670103e CZ |
2799 | void |
2800 | md_operand (expressionS *expressionP ATTRIBUTE_UNUSED) | |
2801 | { | |
2802 | char *p = input_line_pointer; | |
2803 | if (*p == '@') | |
886a2506 | 2804 | { |
4670103e CZ |
2805 | input_line_pointer++; |
2806 | expressionP->X_op = O_symbol; | |
2807 | expression (expressionP); | |
2808 | } | |
2809 | } | |
886a2506 | 2810 | |
4670103e CZ |
2811 | /* This function is called from the function 'expression', it attempts |
2812 | to parse special names (in our case register names). It fills in | |
2813 | the expression with the identified register. It returns TRUE if | |
2814 | it is a register and FALSE otherwise. */ | |
886a2506 | 2815 | |
4670103e CZ |
2816 | bfd_boolean |
2817 | arc_parse_name (const char *name, | |
2818 | struct expressionS *e) | |
2819 | { | |
2820 | struct symbol *sym; | |
886a2506 | 2821 | |
4670103e CZ |
2822 | if (!assembling_insn) |
2823 | return FALSE; | |
886a2506 | 2824 | |
4670103e CZ |
2825 | /* Handle only registers. */ |
2826 | if (e->X_op != O_absent) | |
2827 | return FALSE; | |
886a2506 | 2828 | |
4670103e CZ |
2829 | sym = hash_find (arc_reg_hash, name); |
2830 | if (sym) | |
2831 | { | |
2832 | e->X_op = O_register; | |
2833 | e->X_add_number = S_GET_VALUE (sym); | |
2834 | return TRUE; | |
2835 | } | |
2836 | return FALSE; | |
2837 | } | |
886a2506 | 2838 | |
4670103e CZ |
2839 | /* md_parse_option |
2840 | Invocation line includes a switch not recognized by the base assembler. | |
2841 | See if it's a processor-specific option. | |
886a2506 | 2842 | |
4670103e | 2843 | New options (supported) are: |
886a2506 | 2844 | |
4670103e CZ |
2845 | -mcpu=<cpu name> Assemble for selected processor |
2846 | -EB/-mbig-endian Big-endian | |
2847 | -EL/-mlittle-endian Little-endian | |
2848 | -mrelax Enable relaxation | |
886a2506 | 2849 | |
4670103e CZ |
2850 | The following CPU names are recognized: |
2851 | arc700, av2em, av2hs. */ | |
886a2506 | 2852 | |
4670103e CZ |
2853 | int |
2854 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) | |
2855 | { | |
2856 | int cpu_flags = EF_ARC_CPU_GENERIC; | |
886a2506 | 2857 | |
4670103e CZ |
2858 | switch (c) |
2859 | { | |
2860 | case OPTION_ARC600: | |
2861 | case OPTION_ARC601: | |
2862 | return md_parse_option (OPTION_MCPU, "arc600"); | |
886a2506 | 2863 | |
4670103e CZ |
2864 | case OPTION_ARC700: |
2865 | return md_parse_option (OPTION_MCPU, "arc700"); | |
886a2506 | 2866 | |
4670103e CZ |
2867 | case OPTION_ARCEM: |
2868 | return md_parse_option (OPTION_MCPU, "arcem"); | |
886a2506 | 2869 | |
4670103e CZ |
2870 | case OPTION_ARCHS: |
2871 | return md_parse_option (OPTION_MCPU, "archs"); | |
886a2506 | 2872 | |
4670103e CZ |
2873 | case OPTION_MCPU: |
2874 | { | |
2875 | int i; | |
2876 | char *s = alloca (strlen (arg) + 1); | |
886a2506 | 2877 | |
4670103e CZ |
2878 | { |
2879 | char *t = s; | |
2880 | char *arg1 = arg; | |
886a2506 | 2881 | |
4670103e CZ |
2882 | do |
2883 | *t = TOLOWER (*arg1++); | |
2884 | while (*t++); | |
2885 | } | |
886a2506 | 2886 | |
4670103e CZ |
2887 | for (i = 0; cpu_types[i].name; ++i) |
2888 | { | |
2889 | if (!strcmp (cpu_types[i].name, s)) | |
2890 | { | |
2891 | arc_target = cpu_types[i].flags; | |
2892 | arc_target_name = cpu_types[i].name; | |
2893 | arc_features = cpu_types[i].features; | |
2894 | arc_mach_type = cpu_types[i].mach; | |
2895 | cpu_flags = cpu_types[i].eflags; | |
886a2506 | 2896 | |
4670103e CZ |
2897 | mach_type_specified_p = 1; |
2898 | break; | |
2899 | } | |
2900 | } | |
886a2506 | 2901 | |
4670103e CZ |
2902 | if (!cpu_types[i].name) |
2903 | { | |
2904 | as_fatal (_("unknown architecture: %s\n"), arg); | |
2905 | } | |
2906 | break; | |
2907 | } | |
886a2506 | 2908 | |
4670103e CZ |
2909 | case OPTION_EB: |
2910 | arc_target_format = "elf32-bigarc"; | |
2911 | byte_order = BIG_ENDIAN; | |
2912 | break; | |
886a2506 | 2913 | |
4670103e CZ |
2914 | case OPTION_EL: |
2915 | arc_target_format = "elf32-littlearc"; | |
2916 | byte_order = LITTLE_ENDIAN; | |
2917 | break; | |
886a2506 | 2918 | |
4670103e CZ |
2919 | case OPTION_CD: |
2920 | /* This option has an effect only on ARC EM. */ | |
2921 | if (arc_target & ARC_OPCODE_ARCv2EM) | |
2922 | arc_features |= ARC_CD; | |
2923 | break; | |
886a2506 | 2924 | |
4670103e CZ |
2925 | case OPTION_RELAX: |
2926 | relaxation_state = 1; | |
2927 | break; | |
886a2506 | 2928 | |
4670103e CZ |
2929 | case OPTION_USER_MODE: |
2930 | case OPTION_LD_EXT_MASK: | |
2931 | case OPTION_SWAP: | |
2932 | case OPTION_NORM: | |
2933 | case OPTION_BARREL_SHIFT: | |
2934 | case OPTION_MIN_MAX: | |
2935 | case OPTION_NO_MPY: | |
2936 | case OPTION_EA: | |
2937 | case OPTION_MUL64: | |
2938 | case OPTION_SIMD: | |
2939 | case OPTION_SPFP: | |
2940 | case OPTION_DPFP: | |
2941 | case OPTION_XMAC_D16: | |
2942 | case OPTION_XMAC_24: | |
2943 | case OPTION_DSP_PACKA: | |
2944 | case OPTION_CRC: | |
2945 | case OPTION_DVBF: | |
2946 | case OPTION_TELEPHONY: | |
2947 | case OPTION_XYMEMORY: | |
2948 | case OPTION_LOCK: | |
2949 | case OPTION_SWAPE: | |
2950 | case OPTION_RTSC: | |
2951 | case OPTION_FPUDA: | |
2952 | /* Dummy options are accepted but have no effect. */ | |
2953 | break; | |
886a2506 | 2954 | |
4670103e CZ |
2955 | default: |
2956 | return 0; | |
2957 | } | |
886a2506 | 2958 | |
4670103e CZ |
2959 | if (cpu_flags != EF_ARC_CPU_GENERIC) |
2960 | arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags; | |
886a2506 | 2961 | |
4670103e CZ |
2962 | return 1; |
2963 | } | |
886a2506 | 2964 | |
4670103e CZ |
2965 | void |
2966 | md_show_usage (FILE *stream) | |
2967 | { | |
2968 | fprintf (stream, _("ARC-specific assembler options:\n")); | |
886a2506 | 2969 | |
4670103e CZ |
2970 | fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n"); |
2971 | fprintf (stream, | |
2972 | " -mcode-density\t enable code density option for ARC EM\n"); | |
2973 | ||
2974 | fprintf (stream, _("\ | |
2975 | -EB assemble code for a big-endian cpu\n")); | |
2976 | fprintf (stream, _("\ | |
2977 | -EL assemble code for a little-endian cpu\n")); | |
2978 | fprintf (stream, _("\ | |
2979 | -mrelax Enable relaxation\n")); | |
886a2506 | 2980 | |
886a2506 NC |
2981 | } |
2982 | ||
2983 | /* Find the proper relocation for the given opcode. */ | |
2984 | ||
2985 | static extended_bfd_reloc_code_real_type | |
2986 | find_reloc (const char *name, | |
2987 | const char *opcodename, | |
2988 | const struct arc_flags *pflags, | |
2989 | int nflg, | |
2990 | extended_bfd_reloc_code_real_type reloc) | |
2991 | { | |
2992 | unsigned int i; | |
2993 | int j; | |
24b368f8 | 2994 | bfd_boolean found_flag, tmp; |
886a2506 NC |
2995 | extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED; |
2996 | ||
2997 | for (i = 0; i < arc_num_equiv_tab; i++) | |
2998 | { | |
2999 | const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i]; | |
3000 | ||
3001 | /* Find the entry. */ | |
3002 | if (strcmp (name, r->name)) | |
3003 | continue; | |
3004 | if (r->mnemonic && (strcmp (r->mnemonic, opcodename))) | |
3005 | continue; | |
24b368f8 | 3006 | if (r->flags[0]) |
886a2506 NC |
3007 | { |
3008 | if (!nflg) | |
3009 | continue; | |
3010 | found_flag = FALSE; | |
24b368f8 CZ |
3011 | unsigned * psflg = (unsigned *)r->flags; |
3012 | do | |
3013 | { | |
3014 | tmp = FALSE; | |
3015 | for (j = 0; j < nflg; j++) | |
3016 | if (!strcmp (pflags[j].name, | |
3017 | arc_flag_operands[*psflg].name)) | |
3018 | { | |
3019 | tmp = TRUE; | |
3020 | break; | |
3021 | } | |
3022 | if (!tmp) | |
3023 | { | |
3024 | found_flag = FALSE; | |
3025 | break; | |
3026 | } | |
3027 | else | |
3028 | { | |
3029 | found_flag = TRUE; | |
3030 | } | |
3031 | ++ psflg; | |
3032 | } while (*psflg); | |
3033 | ||
886a2506 NC |
3034 | if (!found_flag) |
3035 | continue; | |
3036 | } | |
3037 | ||
3038 | if (reloc != r->oldreloc) | |
3039 | continue; | |
3040 | /* Found it. */ | |
3041 | ret = r->newreloc; | |
3042 | break; | |
3043 | } | |
3044 | ||
3045 | if (ret == BFD_RELOC_UNUSED) | |
3046 | as_bad (_("Unable to find %s relocation for instruction %s"), | |
3047 | name, opcodename); | |
3048 | return ret; | |
3049 | } | |
3050 | ||
4670103e CZ |
3051 | /* All the symbol types that are allowed to be used for |
3052 | relaxation. */ | |
3053 | ||
3054 | static bfd_boolean | |
3055 | may_relax_expr (expressionS tok) | |
3056 | { | |
3057 | /* Check if we have unrelaxable relocs. */ | |
3058 | switch (tok.X_md) | |
3059 | { | |
3060 | default: | |
3061 | break; | |
3062 | case O_plt: | |
3063 | return FALSE; | |
3064 | } | |
3065 | ||
3066 | switch (tok.X_op) | |
3067 | { | |
3068 | case O_symbol: | |
3069 | case O_multiply: | |
3070 | case O_divide: | |
3071 | case O_modulus: | |
3072 | case O_add: | |
3073 | case O_subtract: | |
3074 | break; | |
3075 | ||
3076 | default: | |
3077 | return FALSE; | |
3078 | } | |
3079 | return TRUE; | |
3080 | } | |
3081 | ||
3082 | /* Checks if flags are in line with relaxable insn. */ | |
3083 | ||
3084 | static bfd_boolean | |
3085 | relaxable_flag (const struct arc_relaxable_ins *ins, | |
3086 | const struct arc_flags *pflags, | |
3087 | int nflgs) | |
3088 | { | |
3089 | unsigned flag_class, | |
3090 | flag, | |
3091 | flag_class_idx = 0, | |
3092 | flag_idx = 0; | |
3093 | ||
3094 | const struct arc_flag_operand *flag_opand; | |
3095 | int i, counttrue = 0; | |
3096 | ||
3097 | /* Iterate through flags classes. */ | |
3098 | while ((flag_class = ins->flag_classes[flag_class_idx]) != 0) | |
3099 | { | |
3100 | /* Iterate through flags in flag class. */ | |
3101 | while ((flag = arc_flag_classes[flag_class].flags[flag_idx]) | |
3102 | != 0) | |
3103 | { | |
3104 | flag_opand = &arc_flag_operands[flag]; | |
3105 | /* Iterate through flags in ins to compare. */ | |
3106 | for (i = 0; i < nflgs; ++i) | |
3107 | { | |
3108 | if (strcmp (flag_opand->name, pflags[i].name) == 0) | |
3109 | ++counttrue; | |
3110 | } | |
3111 | ||
3112 | ++flag_idx; | |
3113 | } | |
3114 | ||
3115 | ++flag_class_idx; | |
3116 | flag_idx = 0; | |
3117 | } | |
3118 | ||
3119 | /* If counttrue == nflgs, then all flags have been found. */ | |
3120 | return (counttrue == nflgs ? TRUE : FALSE); | |
3121 | } | |
3122 | ||
3123 | /* Checks if operands are in line with relaxable insn. */ | |
3124 | ||
3125 | static bfd_boolean | |
3126 | relaxable_operand (const struct arc_relaxable_ins *ins, | |
3127 | const expressionS *tok, | |
3128 | int ntok) | |
3129 | { | |
3130 | const enum rlx_operand_type *operand = &ins->operands[0]; | |
3131 | int i = 0; | |
3132 | ||
3133 | while (*operand != EMPTY) | |
3134 | { | |
3135 | const expressionS *epr = &tok[i]; | |
3136 | ||
3137 | if (i != 0 && i >= ntok) | |
3138 | return FALSE; | |
3139 | ||
3140 | switch (*operand) | |
3141 | { | |
3142 | case IMMEDIATE: | |
3143 | if (!(epr->X_op == O_multiply | |
3144 | || epr->X_op == O_divide | |
3145 | || epr->X_op == O_modulus | |
3146 | || epr->X_op == O_add | |
3147 | || epr->X_op == O_subtract | |
3148 | || epr->X_op == O_symbol)) | |
3149 | return FALSE; | |
3150 | break; | |
3151 | ||
3152 | case REGISTER_DUP: | |
3153 | if ((i <= 0) | |
3154 | || (epr->X_add_number != tok[i - 1].X_add_number)) | |
3155 | return FALSE; | |
3156 | /* Fall through. */ | |
3157 | case REGISTER: | |
3158 | if (epr->X_op != O_register) | |
3159 | return FALSE; | |
3160 | break; | |
3161 | ||
3162 | case REGISTER_S: | |
3163 | if (epr->X_op != O_register) | |
3164 | return FALSE; | |
3165 | ||
3166 | switch (epr->X_add_number) | |
3167 | { | |
3168 | case 0: case 1: case 2: case 3: | |
3169 | case 12: case 13: case 14: case 15: | |
3170 | break; | |
3171 | default: | |
3172 | return FALSE; | |
3173 | } | |
3174 | break; | |
3175 | ||
3176 | case REGISTER_NO_GP: | |
3177 | if ((epr->X_op != O_register) | |
3178 | || (epr->X_add_number == 26)) /* 26 is the gp register. */ | |
3179 | return FALSE; | |
3180 | break; | |
3181 | ||
3182 | case BRACKET: | |
3183 | if (epr->X_op != O_bracket) | |
3184 | return FALSE; | |
3185 | break; | |
3186 | ||
3187 | default: | |
3188 | /* Don't understand, bail out. */ | |
3189 | return FALSE; | |
3190 | break; | |
3191 | } | |
3192 | ||
3193 | ++i; | |
3194 | operand = &ins->operands[i]; | |
3195 | } | |
3196 | ||
3197 | return (i == ntok ? TRUE : FALSE); | |
3198 | } | |
3199 | ||
3200 | /* Return TRUE if this OPDCODE is a candidate for relaxation. */ | |
3201 | ||
3202 | static bfd_boolean | |
3203 | relax_insn_p (const struct arc_opcode *opcode, | |
3204 | const expressionS *tok, | |
3205 | int ntok, | |
3206 | const struct arc_flags *pflags, | |
3207 | int nflg) | |
3208 | { | |
3209 | unsigned i; | |
3210 | bfd_boolean rv = FALSE; | |
3211 | ||
3212 | /* Check the relaxation table. */ | |
3213 | for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i) | |
3214 | { | |
3215 | const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i]; | |
3216 | ||
3217 | if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0) | |
3218 | && may_relax_expr (tok[arc_rlx_ins->opcheckidx]) | |
3219 | && relaxable_operand (arc_rlx_ins, tok, ntok) | |
3220 | && relaxable_flag (arc_rlx_ins, pflags, nflg)) | |
3221 | { | |
3222 | rv = TRUE; | |
3223 | frag_now->fr_subtype = arc_relaxable_insns[i].subtype; | |
3224 | memcpy (&frag_now->tc_frag_data.tok, tok, | |
3225 | sizeof (expressionS) * ntok); | |
3226 | memcpy (&frag_now->tc_frag_data.pflags, pflags, | |
3227 | sizeof (struct arc_flags) * nflg); | |
3228 | frag_now->tc_frag_data.nflg = nflg; | |
3229 | frag_now->tc_frag_data.ntok = ntok; | |
3230 | break; | |
3231 | } | |
3232 | } | |
3233 | ||
3234 | return rv; | |
3235 | } | |
3236 | ||
886a2506 NC |
3237 | /* Turn an opcode description and a set of arguments into |
3238 | an instruction and a fixup. */ | |
3239 | ||
3240 | static void | |
3241 | assemble_insn (const struct arc_opcode *opcode, | |
3242 | const expressionS *tok, | |
3243 | int ntok, | |
3244 | const struct arc_flags *pflags, | |
3245 | int nflg, | |
3246 | struct arc_insn *insn) | |
3247 | { | |
3248 | const expressionS *reloc_exp = NULL; | |
3249 | unsigned image; | |
3250 | const unsigned char *argidx; | |
3251 | int i; | |
3252 | int tokidx = 0; | |
3253 | unsigned char pcrel = 0; | |
3254 | bfd_boolean needGOTSymbol; | |
3255 | bfd_boolean has_delay_slot = FALSE; | |
3256 | extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
3257 | ||
3258 | memset (insn, 0, sizeof (*insn)); | |
3259 | image = opcode->opcode; | |
3260 | ||
3261 | pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n", | |
3262 | frag_now->fr_file, frag_now->fr_line, opcode->name, | |
3263 | opcode->opcode); | |
3264 | ||
3265 | /* Handle operands. */ | |
3266 | for (argidx = opcode->operands; *argidx; ++argidx) | |
3267 | { | |
3268 | const struct arc_operand *operand = &arc_operands[*argidx]; | |
3269 | const expressionS *t = (const expressionS *) 0; | |
3270 | ||
3271 | if ((operand->flags & ARC_OPERAND_FAKE) | |
3272 | && !(operand->flags & ARC_OPERAND_BRAKET)) | |
3273 | continue; | |
3274 | ||
3275 | if (operand->flags & ARC_OPERAND_DUPLICATE) | |
3276 | { | |
3277 | /* Duplicate operand, already inserted. */ | |
3278 | tokidx ++; | |
3279 | continue; | |
3280 | } | |
3281 | ||
3282 | if (tokidx >= ntok) | |
3283 | { | |
3284 | abort (); | |
3285 | } | |
3286 | else | |
3287 | t = &tok[tokidx++]; | |
3288 | ||
3289 | /* Regardless if we have a reloc or not mark the instruction | |
3290 | limm if it is the case. */ | |
3291 | if (operand->flags & ARC_OPERAND_LIMM) | |
3292 | insn->has_limm = TRUE; | |
3293 | ||
3294 | switch (t->X_op) | |
3295 | { | |
3296 | case O_register: | |
3297 | image = insert_operand (image, operand, regno (t->X_add_number), | |
3298 | NULL, 0); | |
3299 | break; | |
3300 | ||
3301 | case O_constant: | |
3302 | image = insert_operand (image, operand, t->X_add_number, NULL, 0); | |
3303 | reloc_exp = t; | |
3304 | if (operand->flags & ARC_OPERAND_LIMM) | |
3305 | insn->limm = t->X_add_number; | |
3306 | break; | |
3307 | ||
3308 | case O_bracket: | |
3309 | /* Ignore brackets. */ | |
3310 | break; | |
3311 | ||
3312 | case O_absent: | |
3313 | gas_assert (operand->flags & ARC_OPERAND_IGNORE); | |
3314 | break; | |
3315 | ||
3316 | case O_subtract: | |
3317 | /* Maybe register range. */ | |
3318 | if ((t->X_add_number == 0) | |
3319 | && contains_register (t->X_add_symbol) | |
3320 | && contains_register (t->X_op_symbol)) | |
3321 | { | |
3322 | int regs; | |
3323 | ||
3324 | regs = get_register (t->X_add_symbol); | |
3325 | regs <<= 16; | |
3326 | regs |= get_register (t->X_op_symbol); | |
3327 | image = insert_operand (image, operand, regs, NULL, 0); | |
3328 | break; | |
3329 | } | |
3330 | ||
3331 | default: | |
3332 | /* This operand needs a relocation. */ | |
3333 | needGOTSymbol = FALSE; | |
3334 | ||
3335 | switch (t->X_md) | |
3336 | { | |
3337 | case O_plt: | |
3338 | needGOTSymbol = TRUE; | |
3339 | reloc = find_reloc ("plt", opcode->name, | |
3340 | pflags, nflg, | |
3341 | operand->default_reloc); | |
3342 | break; | |
3343 | ||
3344 | case O_gotoff: | |
3345 | case O_gotpc: | |
3346 | needGOTSymbol = TRUE; | |
3347 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3348 | break; | |
3349 | case O_pcl: | |
3350 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3351 | if (ARC_SHORT (opcode->mask)) | |
3352 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
3353 | _("Unable to use @pcl relocation for insn %s"), | |
3354 | opcode->name); | |
3355 | break; | |
3356 | case O_sda: | |
3357 | reloc = find_reloc ("sda", opcode->name, | |
3358 | pflags, nflg, | |
3359 | operand->default_reloc); | |
3360 | break; | |
3361 | case O_tlsgd: | |
3362 | case O_tlsie: | |
3363 | needGOTSymbol = TRUE; | |
3364 | /* Fall-through. */ | |
3365 | ||
3366 | case O_tpoff: | |
3367 | case O_dtpoff: | |
3368 | reloc = ARC_RELOC_TABLE (t->X_md)->reloc; | |
3369 | break; | |
3370 | ||
3371 | case O_tpoff9: /*FIXME! Check for the conditionality of | |
3372 | the insn. */ | |
3373 | case O_dtpoff9: /*FIXME! Check for the conditionality of | |
3374 | the insn. */ | |
3375 | as_bad (_("TLS_*_S9 relocs are not supported yet")); | |
3376 | break; | |
3377 | ||
3378 | default: | |
3379 | /* Just consider the default relocation. */ | |
3380 | reloc = operand->default_reloc; | |
3381 | break; | |
3382 | } | |
3383 | ||
3384 | if (needGOTSymbol && (GOT_symbol == NULL)) | |
3385 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3386 | ||
3387 | reloc_exp = t; | |
3388 | ||
3389 | #if 0 | |
3390 | if (reloc > 0) | |
3391 | { | |
3392 | /* sanity checks. */ | |
3393 | reloc_howto_type *reloc_howto | |
3394 | = bfd_reloc_type_lookup (stdoutput, | |
3395 | (bfd_reloc_code_real_type) reloc); | |
3396 | unsigned reloc_bitsize = reloc_howto->bitsize; | |
3397 | if (reloc_howto->rightshift) | |
3398 | reloc_bitsize -= reloc_howto->rightshift; | |
3399 | if (reloc_bitsize != operand->bits) | |
3400 | { | |
3401 | as_bad (_("invalid relocation %s for field"), | |
3402 | bfd_get_reloc_code_name (reloc)); | |
3403 | return; | |
3404 | } | |
3405 | } | |
3406 | #endif | |
3407 | if (insn->nfixups >= MAX_INSN_FIXUPS) | |
3408 | as_fatal (_("too many fixups")); | |
3409 | ||
3410 | struct arc_fixup *fixup; | |
3411 | fixup = &insn->fixups[insn->nfixups++]; | |
3412 | fixup->exp = *t; | |
3413 | fixup->reloc = reloc; | |
3414 | pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0; | |
3415 | fixup->pcrel = pcrel; | |
3416 | fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ? | |
3417 | TRUE : FALSE; | |
3418 | break; | |
3419 | } | |
3420 | } | |
3421 | ||
3422 | /* Handle flags. */ | |
3423 | for (i = 0; i < nflg; i++) | |
3424 | { | |
3425 | const struct arc_flag_operand *flg_operand = | |
3426 | &arc_flag_operands[pflags[i].code]; | |
3427 | ||
3428 | /* Check if the instruction has a delay slot. */ | |
3429 | if (!strcmp (flg_operand->name, "d")) | |
3430 | has_delay_slot = TRUE; | |
3431 | ||
3432 | /* There is an exceptional case when we cannot insert a flag | |
3433 | just as it is. The .T flag must be handled in relation with | |
3434 | the relative address. */ | |
3435 | if (!strcmp (flg_operand->name, "t") | |
3436 | || !strcmp (flg_operand->name, "nt")) | |
3437 | { | |
3438 | unsigned bitYoperand = 0; | |
3439 | /* FIXME! move selection bbit/brcc in arc-opc.c. */ | |
3440 | if (!strcmp (flg_operand->name, "t")) | |
3441 | if (!strcmp (opcode->name, "bbit0") | |
3442 | || !strcmp (opcode->name, "bbit1")) | |
3443 | bitYoperand = arc_NToperand; | |
3444 | else | |
3445 | bitYoperand = arc_Toperand; | |
3446 | else | |
3447 | if (!strcmp (opcode->name, "bbit0") | |
3448 | || !strcmp (opcode->name, "bbit1")) | |
3449 | bitYoperand = arc_Toperand; | |
3450 | else | |
3451 | bitYoperand = arc_NToperand; | |
3452 | ||
3453 | gas_assert (reloc_exp != NULL); | |
3454 | if (reloc_exp->X_op == O_constant) | |
3455 | { | |
3456 | /* Check if we have a constant and solved it | |
3457 | immediately. */ | |
3458 | offsetT val = reloc_exp->X_add_number; | |
3459 | image |= insert_operand (image, &arc_operands[bitYoperand], | |
3460 | val, NULL, 0); | |
3461 | } | |
3462 | else | |
3463 | { | |
3464 | struct arc_fixup *fixup; | |
3465 | ||
3466 | if (insn->nfixups >= MAX_INSN_FIXUPS) | |
3467 | as_fatal (_("too many fixups")); | |
3468 | ||
3469 | fixup = &insn->fixups[insn->nfixups++]; | |
3470 | fixup->exp = *reloc_exp; | |
3471 | fixup->reloc = -bitYoperand; | |
3472 | fixup->pcrel = pcrel; | |
3473 | fixup->islong = FALSE; | |
3474 | } | |
3475 | } | |
3476 | else | |
3477 | image |= (flg_operand->code & ((1 << flg_operand->bits) - 1)) | |
3478 | << flg_operand->shift; | |
3479 | } | |
3480 | ||
4670103e CZ |
3481 | insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg); |
3482 | ||
886a2506 NC |
3483 | /* Short instruction? */ |
3484 | insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE; | |
3485 | ||
3486 | insn->insn = image; | |
3487 | ||
3488 | /* Update last insn status. */ | |
3489 | arc_last_insns[1] = arc_last_insns[0]; | |
3490 | arc_last_insns[0].opcode = opcode; | |
3491 | arc_last_insns[0].has_limm = insn->has_limm; | |
3492 | arc_last_insns[0].has_delay_slot = has_delay_slot; | |
3493 | ||
3494 | /* Check if the current instruction is legally used. */ | |
3495 | if (arc_last_insns[1].has_delay_slot | |
3496 | && is_br_jmp_insn_p (arc_last_insns[0].opcode)) | |
3497 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
3498 | _("A jump/branch instruction in delay slot.")); | |
3499 | } | |
3500 | ||
886a2506 NC |
3501 | void |
3502 | arc_handle_align (fragS* fragP) | |
3503 | { | |
3504 | if ((fragP)->fr_type == rs_align_code) | |
3505 | { | |
3506 | char *dest = (fragP)->fr_literal + (fragP)->fr_fix; | |
3507 | valueT count = ((fragP)->fr_next->fr_address | |
3508 | - (fragP)->fr_address - (fragP)->fr_fix); | |
3509 | ||
3510 | (fragP)->fr_var = 2; | |
3511 | ||
3512 | if (count & 1)/* Padding in the gap till the next 2-byte | |
3513 | boundary with 0s. */ | |
3514 | { | |
3515 | (fragP)->fr_fix++; | |
3516 | *dest++ = 0; | |
3517 | } | |
3518 | /* Writing nop_s. */ | |
3519 | md_number_to_chars (dest, NOP_OPCODE_S, 2); | |
3520 | } | |
3521 | } | |
3522 | ||
3523 | /* Here we decide which fixups can be adjusted to make them relative | |
3524 | to the beginning of the section instead of the symbol. Basically | |
3525 | we need to make sure that the dynamic relocations are done | |
3526 | correctly, so in some cases we force the original symbol to be | |
3527 | used. */ | |
3528 | ||
3529 | int | |
3530 | tc_arc_fix_adjustable (fixS *fixP) | |
3531 | { | |
3532 | ||
3533 | /* Prevent all adjustments to global symbols. */ | |
3534 | if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
3535 | return 0; | |
3536 | if (S_IS_WEAK (fixP->fx_addsy)) | |
3537 | return 0; | |
3538 | ||
3539 | /* Adjust_reloc_syms doesn't know about the GOT. */ | |
3540 | switch (fixP->fx_r_type) | |
3541 | { | |
3542 | case BFD_RELOC_ARC_GOTPC32: | |
3543 | case BFD_RELOC_ARC_PLT32: | |
3544 | case BFD_RELOC_ARC_S25H_PCREL_PLT: | |
3545 | case BFD_RELOC_ARC_S21H_PCREL_PLT: | |
3546 | case BFD_RELOC_ARC_S25W_PCREL_PLT: | |
3547 | case BFD_RELOC_ARC_S21W_PCREL_PLT: | |
3548 | return 0; | |
3549 | ||
3550 | default: | |
3551 | break; | |
3552 | } | |
3553 | ||
3554 | return 0; /* FIXME! return 1, fix it in the linker. */ | |
3555 | } | |
3556 | ||
3557 | /* Compute the reloc type of an expression EXP. */ | |
3558 | ||
3559 | static void | |
3560 | arc_check_reloc (expressionS *exp, | |
3561 | bfd_reloc_code_real_type *r_type_p) | |
3562 | { | |
3563 | if (*r_type_p == BFD_RELOC_32 | |
3564 | && exp->X_op == O_subtract | |
3565 | && exp->X_op_symbol != NULL | |
3566 | && exp->X_op_symbol->bsym->section == now_seg) | |
6f4b1afc | 3567 | *r_type_p = BFD_RELOC_ARC_32_PCREL; |
886a2506 NC |
3568 | } |
3569 | ||
3570 | ||
3571 | /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */ | |
3572 | ||
3573 | void | |
3574 | arc_cons_fix_new (fragS *frag, | |
3575 | int off, | |
3576 | int size, | |
3577 | expressionS *exp, | |
3578 | bfd_reloc_code_real_type r_type) | |
3579 | { | |
3580 | r_type = BFD_RELOC_UNUSED; | |
3581 | ||
3582 | switch (size) | |
3583 | { | |
3584 | case 1: | |
3585 | r_type = BFD_RELOC_8; | |
3586 | break; | |
3587 | ||
3588 | case 2: | |
3589 | r_type = BFD_RELOC_16; | |
3590 | break; | |
3591 | ||
3592 | case 3: | |
3593 | r_type = BFD_RELOC_24; | |
3594 | break; | |
3595 | ||
3596 | case 4: | |
3597 | r_type = BFD_RELOC_32; | |
3598 | arc_check_reloc (exp, &r_type); | |
3599 | break; | |
3600 | ||
3601 | case 8: | |
3602 | r_type = BFD_RELOC_64; | |
3603 | break; | |
3604 | ||
3605 | default: | |
3606 | as_bad (_("unsupported BFD relocation size %u"), size); | |
3607 | r_type = BFD_RELOC_UNUSED; | |
3608 | } | |
3609 | ||
3610 | fix_new_exp (frag, off, size, exp, 0, r_type); | |
3611 | } | |
3612 | ||
3613 | /* The actual routine that checks the ZOL conditions. */ | |
3614 | ||
3615 | static void | |
3616 | check_zol (symbolS *s) | |
3617 | { | |
3618 | switch (arc_mach_type) | |
3619 | { | |
3620 | case bfd_mach_arc_arcv2: | |
3621 | if (arc_target & ARC_OPCODE_ARCv2EM) | |
3622 | return; | |
3623 | ||
3624 | if (is_br_jmp_insn_p (arc_last_insns[0].opcode) | |
3625 | || arc_last_insns[1].has_delay_slot) | |
3626 | as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"), | |
3627 | S_GET_NAME (s)); | |
3628 | ||
3629 | break; | |
3630 | case bfd_mach_arc_arc600: | |
3631 | ||
3632 | if (is_kernel_insn_p (arc_last_insns[0].opcode)) | |
3633 | as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"), | |
3634 | S_GET_NAME (s)); | |
3635 | ||
3636 | if (arc_last_insns[0].has_limm | |
3637 | && is_br_jmp_insn_p (arc_last_insns[0].opcode)) | |
3638 | as_bad (_("A jump instruction with long immediate detected at the \ | |
3639 | end of the ZOL label @%s"), S_GET_NAME (s)); | |
3640 | ||
3641 | /* Fall through. */ | |
3642 | case bfd_mach_arc_arc700: | |
3643 | if (arc_last_insns[0].has_delay_slot) | |
3644 | as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"), | |
3645 | S_GET_NAME (s)); | |
3646 | ||
3647 | break; | |
3648 | default: | |
3649 | break; | |
3650 | } | |
3651 | } | |
3652 | ||
3653 | /* If ZOL end check the last two instruction for illegals. */ | |
3654 | void | |
3655 | arc_frob_label (symbolS * sym) | |
3656 | { | |
3657 | if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL) | |
3658 | check_zol (sym); | |
3659 | ||
3660 | dwarf2_emit_label (sym); | |
ea1562b3 | 3661 | } |
4670103e CZ |
3662 | |
3663 | /* Used because generic relaxation assumes a pc-rel value whilst we | |
3664 | also relax instructions that use an absolute value resolved out of | |
3665 | relative values (if that makes any sense). An example: 'add r1, | |
3666 | r2, @.L2 - .' The symbols . and @.L2 are relative to the section | |
3667 | but if they're in the same section we can subtract the section | |
3668 | offset relocation which ends up in a resolved value. So if @.L2 is | |
3669 | .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 - | |
3670 | .text + 0x40 = 0x10. */ | |
3671 | int | |
3672 | arc_pcrel_adjust (fragS *fragP) | |
3673 | { | |
3674 | if (!fragP->tc_frag_data.pcrel) | |
3675 | return fragP->fr_address + fragP->fr_fix; | |
3676 | ||
3677 | return 0; | |
3678 | } | |
726c18e1 CZ |
3679 | |
3680 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
3681 | ||
3682 | void | |
3683 | tc_arc_frame_initial_instructions (void) | |
3684 | { | |
3685 | /* Stack pointer is register 28. */ | |
3686 | cfi_add_CFA_def_cfa_register (28); | |
3687 | } | |
3688 | ||
3689 | int | |
3690 | tc_arc_regname_to_dw2regnum (char *regname) | |
3691 | { | |
3692 | struct symbol *sym; | |
3693 | ||
3694 | sym = hash_find (arc_reg_hash, regname); | |
3695 | if (sym) | |
3696 | return S_GET_VALUE (sym); | |
3697 | ||
3698 | return -1; | |
3699 | } |