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objcopy: Close some memory leaks in error paths
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
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252b5132 1/* tc-arc.c -- Assembler for the ARC
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132
RH		 30#include "opcode/arc.h"
31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
886a2506
NC		 50
51/* Equal to MAX_PRECISION in atof-ieee.c. */
52#define MAX_LITTLENUMS 6
53
9004b6bd
AB		 54#ifndef TARGET_WITH_CPU
55#define TARGET_WITH_CPU "arc700"
56#endif /* TARGET_WITH_CPU */
57
4670103e
CZ		 58/* Enum used to enumerate the relaxable ins operands. */
59enum rlx_operand_type
60{
61 EMPTY = 0,
62 REGISTER,
63 REGISTER_S, /* Register for short instruction(s). */
64 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
65 REGISTER_DUP, /* Duplication of previous operand of type register. */
66 IMMEDIATE,
67 BRACKET
68};
69
70enum arc_rlx_types
71{
72 ARC_RLX_NONE = 0,
73 ARC_RLX_BL_S,
74 ARC_RLX_BL,
75 ARC_RLX_B_S,
76 ARC_RLX_B,
77 ARC_RLX_ADD_U3,
78 ARC_RLX_ADD_U6,
79 ARC_RLX_ADD_LIMM,
80 ARC_RLX_LD_U7,
81 ARC_RLX_LD_S9,
82 ARC_RLX_LD_LIMM,
83 ARC_RLX_MOV_U8,
84 ARC_RLX_MOV_S12,
85 ARC_RLX_MOV_LIMM,
86 ARC_RLX_SUB_U3,
87 ARC_RLX_SUB_U6,
88 ARC_RLX_SUB_LIMM,
89 ARC_RLX_MPY_U6,
90 ARC_RLX_MPY_LIMM,
91 ARC_RLX_MOV_RU6,
92 ARC_RLX_MOV_RLIMM,
93 ARC_RLX_ADD_RRU6,
94 ARC_RLX_ADD_RRLIMM,
95};
96
886a2506
NC		 97/* Macros section. */
98
99#define regno(x) ((x) & 0x3F)
100#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 101#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102#define is_spfp_p(op) (((sc) == SPX))
103#define is_dpfp_p(op) (((sc) == DPX))
104#define is_fpuda_p(op) (((sc) == DPA))
db18dbab
GM		 105#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
c810e0b8 107#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 108#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 109
886a2506
NC		 110/* Generic assembler global variables which must be defined by all
111 targets. */
0d2bcfaf 112
886a2506 113/* Characters which always start a comment. */
252b5132
RH		 114const char comment_chars[] = "#;";
115
886a2506 116/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 117const char line_comment_chars[] = "#";
118
886a2506
NC		 119/* Characters which may be used to separate multiple commands on a
120 single line. */
121const char line_separator_chars[] = "`";
252b5132 122
886a2506
NC		 123/* Characters which are used to indicate an exponent in a floating
124 point number. */
252b5132
RH		 125const char EXP_CHARS[] = "eE";
126
bcee8eb8
AM		 127/* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 129const char FLT_CHARS[] = "rRsSfFdD";
130
131/* Byte order. */
132extern int target_big_endian;
133const char *arc_target_format = DEFAULT_TARGET_FORMAT;
134static int byte_order = DEFAULT_BYTE_ORDER;
135
b99747ae
CZ		 136/* Arc extension section. */
137static segT arcext_section;
138
4670103e
CZ		 139/* By default relaxation is disabled. */
140static int relaxation_state = 0;
141
886a2506 142extern int arc_get_mach (char *);
0d2bcfaf 143
4670103e 144/* Forward declarations. */
886a2506
NC		 145static void arc_lcomm (int);
146static void arc_option (int);
147static void arc_extra_reloc (int);
b99747ae 148static void arc_extinsn (int);
f36e33da 149static void arc_extcorereg (int);
4670103e 150
886a2506 151const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 152{
153 /* Make sure that .word is 32 bits. */
154 { "word", cons, 4 },
886a2506 155
6f4b1afc
CM		 156 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm, 0 },
158 { "lcommon", arc_lcomm, 0 },
159 { "cpu", arc_option, 0 },
252b5132 160
f36e33da
CZ		 161 { "extinstruction", arc_extinsn, 0 },
162 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
163 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
164 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 165
6f4b1afc
CM		 166 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
167 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 168
6f4b1afc
CM		 169 { NULL, NULL, 0 }
170};
252b5132 171
252b5132 172const char *md_shortopts = "";
ea1562b3
NC		 173
174enum options
6f4b1afc
CM		 175{
176 OPTION_EB = OPTION_MD_BASE,
177 OPTION_EL,
178
179 OPTION_ARC600,
180 OPTION_ARC601,
181 OPTION_ARC700,
182 OPTION_ARCEM,
183 OPTION_ARCHS,
184
185 OPTION_MCPU,
186 OPTION_CD,
4670103e 187 OPTION_RELAX,
bdd582db 188 OPTION_NPS400,
6f4b1afc 189
ce440d63
GM		 190 OPTION_SPFP,
191 OPTION_DPFP,
192 OPTION_FPUDA,
193
6f4b1afc
CM		 194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
196 OPTION_USER_MODE,
197 OPTION_LD_EXT_MASK,
198 OPTION_SWAP,
199 OPTION_NORM,
200 OPTION_BARREL_SHIFT,
201 OPTION_MIN_MAX,
202 OPTION_NO_MPY,
203 OPTION_EA,
204 OPTION_MUL64,
205 OPTION_SIMD,
6f4b1afc
CM		 206 OPTION_XMAC_D16,
207 OPTION_XMAC_24,
208 OPTION_DSP_PACKA,
209 OPTION_CRC,
210 OPTION_DVBF,
211 OPTION_TELEPHONY,
212 OPTION_XYMEMORY,
213 OPTION_LOCK,
214 OPTION_SWAPE,
ce440d63 215 OPTION_RTSC
6f4b1afc 216};
ea1562b3
NC		 217
218struct option md_longopts[] =
6f4b1afc
CM		 219{
220 { "EB", no_argument, NULL, OPTION_EB },
221 { "EL", no_argument, NULL, OPTION_EL },
222 { "mcpu", required_argument, NULL, OPTION_MCPU },
223 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 224 { "mARC600", no_argument, NULL, OPTION_ARC600 },
225 { "mARC601", no_argument, NULL, OPTION_ARC601 },
226 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 227 { "mA7", no_argument, NULL, OPTION_ARC700 },
228 { "mEM", no_argument, NULL, OPTION_ARCEM },
229 { "mHS", no_argument, NULL, OPTION_ARCHS },
230 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 231 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 232 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 233
ce440d63
GM		 234 /* Floating point options */
235 { "mspfp", no_argument, NULL, OPTION_SPFP},
236 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
237 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
238 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
239 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
240 { "mdpfp", no_argument, NULL, OPTION_DPFP},
241 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
242 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
243 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
244 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
245 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
246
6f4b1afc
CM		 247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument, NULL, OPTION_ARCEM },
250 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
251 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
252 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
253 { "mswap", no_argument, NULL, OPTION_SWAP },
254 { "mnorm", no_argument, NULL, OPTION_NORM },
255 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
256 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
257 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
258 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
259 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
260 { "mea", no_argument, NULL, OPTION_EA },
261 { "mEA", no_argument, NULL, OPTION_EA },
262 { "mmul64", no_argument, NULL, OPTION_MUL64 },
263 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 264 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
265 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
266 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
267 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
268 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
269 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
270 { "mcrc", no_argument, NULL, OPTION_CRC},
271 { "mdvbf", no_argument, NULL, OPTION_DVBF},
272 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
273 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
274 { "mlock", no_argument, NULL, OPTION_LOCK},
275 { "mswape", no_argument, NULL, OPTION_SWAPE},
276 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 277
278 { NULL, no_argument, NULL, 0 }
279};
252b5132 280
886a2506 281size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 282
886a2506 283/* Local data and data types. */
252b5132 284
886a2506
NC		 285/* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287typedef int extended_bfd_reloc_code_real_type;
252b5132 288
886a2506 289struct arc_fixup
252b5132 290{
886a2506 291 expressionS exp;
252b5132 292
886a2506 293 extended_bfd_reloc_code_real_type reloc;
252b5132 294
886a2506
NC		 295 /* index into arc_operands. */
296 unsigned int opindex;
252b5132 297
886a2506
NC		 298 /* PC-relative, used by internals fixups. */
299 unsigned char pcrel;
252b5132 300
886a2506
NC		 301 /* TRUE if this fixup is for LIMM operand. */
302 bfd_boolean islong;
303};
252b5132 304
886a2506
NC		 305struct arc_insn
306{
bdfe53e3 307 unsigned long long int insn;
886a2506
NC		 308 int nfixups;
309 struct arc_fixup fixups[MAX_INSN_FIXUPS];
310 long limm;
91fdca6f 311 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 312 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
313 valid. */
4670103e
CZ		 314 bfd_boolean relax; /* Boolean value: TRUE if needs
315 relaxation. */
886a2506 316};
ea1562b3 317
886a2506
NC		 318/* Structure to hold any last two instructions. */
319static struct arc_last_insn
252b5132 320{
886a2506
NC		 321 /* Saved instruction opcode. */
322 const struct arc_opcode *opcode;
252b5132 323
886a2506
NC		 324 /* Boolean value: TRUE if current insn is short. */
325 bfd_boolean has_limm;
252b5132 326
886a2506
NC		 327 /* Boolean value: TRUE if current insn has delay slot. */
328 bfd_boolean has_delay_slot;
329} arc_last_insns[2];
252b5132 330
b99747ae
CZ		 331/* Extension instruction suffix classes. */
332typedef struct
333{
334 const char *name;
335 int len;
c810e0b8 336 int attr_class;
b99747ae
CZ		 337} attributes_t;
338
339static const attributes_t suffixclass[] =
340{
341 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
342 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
343 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
344};
345
346/* Extension instruction syntax classes. */
347static const attributes_t syntaxclass[] =
348{
349 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 350 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
351 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
352 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 353};
354
355/* Extension instruction syntax classes modifiers. */
356static const attributes_t syntaxclassmod[] =
357{
358 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
359 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
360};
361
f36e33da
CZ		 362/* Extension register type. */
363typedef struct
364{
365 char *name;
366 int number;
367 int imode;
368} extRegister_t;
369
370/* A structure to hold the additional conditional codes. */
371static struct
372{
373 struct arc_flag_operand *arc_ext_condcode;
374 int size;
375} ext_condcode = { NULL, 0 };
376
da5be039
AB		 377/* Structure to hold an entry in ARC_OPCODE_HASH. */
378struct arc_opcode_hash_entry
379{
380 /* The number of pointers in the OPCODE list. */
381 size_t count;
382
383 /* Points to a list of opcode pointers. */
384 const struct arc_opcode **opcode;
385};
386
1328504b
AB		 387/* Structure used for iterating through an arc_opcode_hash_entry. */
388struct arc_opcode_hash_entry_iterator
389{
390 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
391 size_t index;
392
393 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
394 returned by this iterator. */
395 const struct arc_opcode *opcode;
396};
397
4670103e
CZ		 398/* Forward declaration. */
399static void assemble_insn
400 (const struct arc_opcode *, const expressionS *, int,
401 const struct arc_flags *, int, struct arc_insn *);
402
bb65a718
AB		 403/* The selection of the machine type can come from different sources. This
404 enum is used to track how the selection was made in order to perform
405 error checks. */
406enum mach_selection_type
407 {
408 MACH_SELECTION_NONE,
409 MACH_SELECTION_FROM_DEFAULT,
410 MACH_SELECTION_FROM_CPU_DIRECTIVE,
411 MACH_SELECTION_FROM_COMMAND_LINE
412 };
413
414/* How the current machine type was selected. */
415static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 416
886a2506
NC		 417/* The hash table of instruction opcodes. */
418static struct hash_control *arc_opcode_hash;
0d2bcfaf 419
886a2506
NC		 420/* The hash table of register symbols. */
421static struct hash_control *arc_reg_hash;
252b5132 422
f36e33da
CZ		 423/* The hash table of aux register symbols. */
424static struct hash_control *arc_aux_hash;
425
db18dbab
GM		 426/* The hash table of address types. */
427static struct hash_control *arc_addrtype_hash;
428
886a2506
NC		 429/* A table of CPU names and opcode sets. */
430static const struct cpu_type
431{
432 const char *name;
433 unsigned flags;
434 int mach;
435 unsigned eflags;
436 unsigned features;
252b5132 437}
886a2506 438 cpu_types[] =
252b5132 439{
886a2506
NC		 440 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
441 E_ARC_MACH_ARC600, 0x00},
442 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
443 E_ARC_MACH_ARC700, 0x00},
bdd582db
GM		 444 { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
445 E_ARC_MACH_ARC700, ARC_NPS400},
886a2506 446 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
87789e08 447 EF_ARC_CPU_ARCV2EM, 0x00},
886a2506
NC		 448 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
449 EF_ARC_CPU_ARCV2HS, ARC_CD},
886a2506
NC		 450 { 0, 0, 0, 0, 0 }
451};
252b5132 452
bb65a718
AB		 453/* Information about the cpu/variant we're assembling for. */
454static struct cpu_type selected_cpu;
455
886a2506
NC		 456/* Used by the arc_reloc_op table. Order is important. */
457#define O_gotoff O_md1 /* @gotoff relocation. */
458#define O_gotpc O_md2 /* @gotpc relocation. */
459#define O_plt O_md3 /* @plt relocation. */
460#define O_sda O_md4 /* @sda relocation. */
461#define O_pcl O_md5 /* @pcl relocation. */
462#define O_tlsgd O_md6 /* @tlsgd relocation. */
463#define O_tlsie O_md7 /* @tlsie relocation. */
464#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
465#define O_tpoff O_md9 /* @tpoff relocation. */
466#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
467#define O_dtpoff O_md11 /* @dtpoff relocation. */
468#define O_last O_dtpoff
469
470/* Used to define a bracket as operand in tokens. */
471#define O_bracket O_md32
472
db18dbab
GM		 473/* Used to define a colon as an operand in tokens. */
474#define O_colon O_md31
475
476/* Used to define address types in nps400. */
477#define O_addrtype O_md30
478
886a2506
NC		 479/* Dummy relocation, to be sorted out. */
480#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
481
482#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
483
484/* A table to map the spelling of a relocation operand into an appropriate
485 bfd_reloc_code_real_type type. The table is assumed to be ordered such
486 that op-O_literal indexes into it. */
487#define ARC_RELOC_TABLE(op) \
488 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
489 ? (abort (), 0) \
490 : (int) (op) - (int) O_gotoff) ])
491
492#define DEF(NAME, RELOC, REQ) \
493 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
494
495static const struct arc_reloc_op_tag
496{
497 /* String to lookup. */
498 const char *name;
499 /* Size of the string. */
500 size_t length;
501 /* Which operator to use. */
502 operatorT op;
503 extended_bfd_reloc_code_real_type reloc;
504 /* Allows complex relocation expression like identifier@reloc +
505 const. */
506 unsigned int complex_expr : 1;
507}
508 arc_reloc_op[] =
6f4b1afc
CM		 509{
510 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
511 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
512 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
513 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
514 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
515 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
516 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
517 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 518 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 519 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 520 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 521};
252b5132 522
886a2506
NC		 523static const int arc_num_reloc_op
524= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
525
4670103e
CZ		 526/* Structure for relaxable instruction that have to be swapped with a
527 smaller alternative instruction. */
528struct arc_relaxable_ins
529{
530 /* Mnemonic that should be checked. */
531 const char *mnemonic_r;
532
533 /* Operands that should be checked.
534 Indexes of operands from operand array. */
535 enum rlx_operand_type operands[6];
536
537 /* Flags that should be checked. */
538 unsigned flag_classes[5];
539
540 /* Mnemonic (smaller) alternative to be used later for relaxation. */
541 const char *mnemonic_alt;
542
543 /* Index of operand that generic relaxation has to check. */
544 unsigned opcheckidx;
545
546 /* Base subtype index used. */
547 enum arc_rlx_types subtype;
548};
549
550#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
551 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
552 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
553 (SIZE), \
554 (NEXT) } \
555
556#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
557 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
558 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
559 (SIZE), \
560 (NEXT) } \
561
562
563/* ARC relaxation table. */
564const relax_typeS md_relax_table[] =
565{
566 /* Fake entry. */
567 {0, 0, 0, 0},
568
569 /* BL_S s13 ->
570 BL s25. */
db18dbab
GM		 571 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
572 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 573
574 /* B_S s10 ->
575 B s25. */
db18dbab
GM		 576 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
577 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 578
579 /* ADD_S c,b, u3 ->
580 ADD<.f> a,b,u6 ->
581 ADD<.f> a,b,limm. */
db18dbab
GM		 582 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
583 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
584 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 585
586 /* LD_S a, [b, u7] ->
587 LD<zz><.x><.aa><.di> a, [b, s9] ->
588 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 589 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
590 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
591 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 592
593 /* MOV_S b, u8 ->
594 MOV<.f> b, s12 ->
595 MOV<.f> b, limm. */
db18dbab
GM		 596 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
597 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
598 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 599
600 /* SUB_S c, b, u3 ->
601 SUB<.f> a, b, u6 ->
602 SUB<.f> a, b, limm. */
db18dbab
GM		 603 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
604 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
605 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 606
607 /* MPY<.f> a, b, u6 ->
608 MPY<.f> a, b, limm. */
db18dbab
GM		 609 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
610 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 611
612 /* MOV<.f><.cc> b, u6 ->
613 MOV<.f><.cc> b, limm. */
db18dbab
GM		 614 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
615 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 616
617 /* ADD<.f><.cc> b, b, u6 ->
618 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 621};
622
623/* Order of this table's entries matters! */
624const struct arc_relaxable_ins arc_relaxable_insns[] =
625{
626 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
627 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
628 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
629 2, ARC_RLX_ADD_RRU6},
630 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
631 ARC_RLX_ADD_U3 },
632 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
633 ARC_RLX_ADD_U6 },
634 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
635 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
636 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
637 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
638 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
639 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
640 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
641 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
642 ARC_RLX_SUB_U3 },
643 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
644 ARC_RLX_SUB_U6 },
645 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
646 ARC_RLX_MPY_U6 },
647};
648
649const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
650
886a2506 651/* Flags to set in the elf header. */
bb65a718 652static const flagword arc_initial_eflag = 0x00;
886a2506
NC		 653
654/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
655symbolS * GOT_symbol = 0;
656
657/* Set to TRUE when we assemble instructions. */
658static bfd_boolean assembling_insn = FALSE;
659
886a2506
NC		 660/* Functions implementation. */
661
b9b47ab7
AB		 662/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
663 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
664 are no matching entries in ARC_OPCODE_HASH. */
da5be039 665
b9b47ab7 666static const struct arc_opcode_hash_entry *
da5be039
AB		 667arc_find_opcode (const char *name)
668{
669 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 670
671 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 672 return entry;
da5be039
AB		 673}
674
1328504b
AB		 675/* Initialise the iterator ITER. */
676
677static void
678arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
679{
680 iter->index = 0;
681 iter->opcode = NULL;
682}
683
684/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
685 calls to this function. Return NULL when all ARC_OPCODE entries have
686 been returned. */
687
688static const struct arc_opcode *
689arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
690 struct arc_opcode_hash_entry_iterator *iter)
691{
692 if (iter->opcode == NULL && iter->index == 0)
693 {
694 gas_assert (entry->count > 0);
695 iter->opcode = entry->opcode[iter->index];
696 }
697 else if (iter->opcode != NULL)
698 {
699 const char *old_name = iter->opcode->name;
700
701 iter->opcode++;
fe779266
AB		 702 if (iter->opcode->name == NULL
703 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 704 {
705 iter->index++;
706 if (iter->index == entry->count)
707 iter->opcode = NULL;
708 else
709 iter->opcode = entry->opcode[iter->index];
710 }
711 }
712
713 return iter->opcode;
714}
715
b99747ae
CZ		 716/* Insert an opcode into opcode hash structure. */
717
718static void
719arc_insert_opcode (const struct arc_opcode *opcode)
720{
721 const char *name, *retval;
722 struct arc_opcode_hash_entry *entry;
723 name = opcode->name;
724
725 entry = hash_find (arc_opcode_hash, name);
726 if (entry == NULL)
727 {
add39d23 728 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 729 entry->count = 0;
730 entry->opcode = NULL;
731
732 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
733 if (retval)
734 as_fatal (_("internal error: can't hash opcode '%s': %s"),
735 name, retval);
736 }
737
add39d23
TS		 738 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
739 entry->count + 1);
b99747ae
CZ		 740
741 if (entry->opcode == NULL)
742 as_fatal (_("Virtual memory exhausted"));
743
744 entry->opcode[entry->count] = opcode;
745 entry->count++;
746}
747
748
bdfe53e3
AB		 749/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
750 value, is encoded as 'middle-endian' for a little-endian target. This
751 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 752
753static void
bdfe53e3 754md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 755{
bdfe53e3 756 switch (n)
886a2506 757 {
bdfe53e3
AB		 758 case 2:
759 md_number_to_chars (buf, val, n);
760 break;
761 case 6:
762 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
763 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
764 break;
765 case 4:
886a2506
NC		 766 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
767 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 768 break;
769 case 8:
770 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
771 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
772 break;
773 default:
774 abort ();
886a2506 775 }
252b5132
RH		 776}
777
24740d83 778/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 779 the relevant static global variables. Parameter SEL describes where
780 this selection originated from. */
24740d83
AB		 781
782static void
bb65a718 783arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 784{
a9522a21 785 int cpu_flags = 0;
24740d83
AB		 786 int i;
787
bb65a718
AB		 788 /* We should only set a default if we've not made a selection from some
789 other source. */
790 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
791 || mach_selection_mode == MACH_SELECTION_NONE);
792
793 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 794 for (i = 0; cpu_types[i].name; ++i)
795 {
796 if (!strcasecmp (cpu_types[i].name, arg))
797 {
bb65a718
AB		 798 /* If a previous selection was made on the command line, then we
799 allow later selections on the command line to override earlier
800 ones. However, a selection from a '.cpu NAME' directive must
801 match the command line selection, or we give a warning. */
802 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
803 {
804 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
805 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
806 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
807 && selected_cpu.mach != cpu_types[i].mach)
808 {
809 as_warn (_("Command-line value overrides \".cpu\" directive"));
810 return;
811 }
812 }
813
814 /* Initialise static global data about selected machine type. */
815 selected_cpu.flags = cpu_types[i].flags;
816 selected_cpu.name = cpu_types[i].name;
817 selected_cpu.features = cpu_types[i].features;
818 selected_cpu.mach = cpu_types[i].mach;
24740d83
AB		 819 cpu_flags = cpu_types[i].eflags;
820 break;
821 }
822 }
823
824 if (!cpu_types[i].name)
825 as_fatal (_("unknown architecture: %s\n"), arg);
a9522a21 826 gas_assert (cpu_flags != 0);
bb65a718
AB		 827 selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
828 mach_selection_mode = sel;
24740d83
AB		 829}
830
886a2506
NC		 831/* Here ends all the ARCompact extension instruction assembling
832 stuff. */
252b5132 833
886a2506
NC		 834static void
835arc_extra_reloc (int r_type)
ea1562b3 836{
886a2506
NC		 837 char *sym_name, c;
838 symbolS *sym, *lab = NULL;
839
840 if (*input_line_pointer == '@')
841 input_line_pointer++;
842 c = get_symbol_name (&sym_name);
843 sym = symbol_find_or_make (sym_name);
844 restore_line_pointer (c);
845 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
846 {
847 ++input_line_pointer;
848 char *lab_name;
849 c = get_symbol_name (&lab_name);
850 lab = symbol_find_or_make (lab_name);
851 restore_line_pointer (c);
852 }
841fdfcd
CZ		 853
854 /* These relocations exist as a mechanism for the compiler to tell the
855 linker how to patch the code if the tls model is optimised. However,
856 the relocation itself does not require any space within the assembler
857 fragment, and so we pass a size of 0.
858
859 The lines that generate these relocations look like this:
860
861 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
862
863 The '.tls_gd_ld @.tdata' is processed first and generates the
864 additional relocation, while the 'bl __tls_get_addr@plt' is processed
865 second and generates the additional branch.
866
867 It is possible that the additional relocation generated by the
868 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
869 while the 'bl __tls_get_addr@plt' will be generated as the first thing
870 in the next fragment. This will be fine; both relocations will still
871 appear to be at the same address in the generated object file.
872 However, this only works as the additional relocation is generated
873 with size of 0 bytes. */
886a2506
NC		 874 fixS *fixP
875 = fix_new (frag_now, /* Which frag? */
876 frag_now_fix (), /* Where in that frag? */
841fdfcd 877 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 878 sym, /* X_add_symbol. */
879 0, /* X_add_number. */
880 FALSE, /* TRUE if PC-relative relocation. */
881 r_type /* Relocation type. */);
882 fixP->fx_subsy = lab;
883}
252b5132 884
886a2506
NC		 885static symbolS *
886arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
887 symbolS *symbolP, addressT size)
888{
889 addressT align = 0;
890 SKIP_WHITESPACE ();
252b5132 891
886a2506
NC		 892 if (*input_line_pointer == ',')
893 {
894 align = parse_align (1);
252b5132 895
886a2506
NC		 896 if (align == (addressT) -1)
897 return NULL;
898 }
899 else
900 {
901 if (size >= 8)
902 align = 3;
903 else if (size >= 4)
904 align = 2;
905 else if (size >= 2)
906 align = 1;
907 else
908 align = 0;
909 }
252b5132 910
886a2506
NC		 911 bss_alloc (symbolP, size, align);
912 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 913
886a2506
NC		 914 return symbolP;
915}
ea1562b3 916
886a2506
NC		 917static void
918arc_lcomm (int ignore)
919{
920 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 921
886a2506
NC		 922 if (symbolP)
923 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
924}
ea1562b3 925
886a2506 926/* Select the cpu we're assembling for. */
ea1562b3 927
886a2506
NC		 928static void
929arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 930{
886a2506
NC		 931 char c;
932 char *cpu;
bb65a718 933 const char *cpu_name;
252b5132 934
886a2506 935 c = get_symbol_name (&cpu);
252b5132 936
bb65a718
AB		 937 if ((!strcmp ("ARC600", cpu))
938 || (!strcmp ("ARC601", cpu))
939 || (!strcmp ("A6", cpu)))
940 cpu_name = "arc600";
941 else if ((!strcmp ("ARC700", cpu))
942 || (!strcmp ("A7", cpu)))
943 cpu_name = "arc700";
944 else if (!strcmp ("EM", cpu))
945 cpu_name = "arcem";
946 else if (!strcmp ("HS", cpu))
947 cpu_name = "archs";
948 else if (!strcmp ("NPS400", cpu))
949 cpu_name = "nps400";
950 else
951 cpu_name = NULL;
886a2506 952
bb65a718
AB		 953 if (cpu_name != NULL)
954 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
955 else
956 as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu);
24b368f8 957
bb65a718
AB		 958 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
959 as_fatal (_("could not set architecture and machine"));
1adc8a9a 960
bb65a718
AB		 961 /* Set elf header flags. */
962 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
886a2506 963
24b368f8 964 restore_line_pointer (c);
886a2506 965 demand_empty_rest_of_line ();
ea1562b3 966}
252b5132 967
886a2506
NC		 968/* Smartly print an expression. */
969
ea1562b3 970static void
886a2506 971debug_exp (expressionS *t)
ea1562b3 972{
886a2506
NC		 973 const char *name ATTRIBUTE_UNUSED;
974 const char *namemd ATTRIBUTE_UNUSED;
252b5132 975
886a2506 976 pr_debug ("debug_exp: ");
252b5132 977
886a2506 978 switch (t->X_op)
252b5132 979 {
886a2506
NC		 980 default: name = "unknown"; break;
981 case O_illegal: name = "O_illegal"; break;
982 case O_absent: name = "O_absent"; break;
983 case O_constant: name = "O_constant"; break;
984 case O_symbol: name = "O_symbol"; break;
985 case O_symbol_rva: name = "O_symbol_rva"; break;
986 case O_register: name = "O_register"; break;
987 case O_big: name = "O_big"; break;
988 case O_uminus: name = "O_uminus"; break;
989 case O_bit_not: name = "O_bit_not"; break;
990 case O_logical_not: name = "O_logical_not"; break;
991 case O_multiply: name = "O_multiply"; break;
992 case O_divide: name = "O_divide"; break;
993 case O_modulus: name = "O_modulus"; break;
994 case O_left_shift: name = "O_left_shift"; break;
995 case O_right_shift: name = "O_right_shift"; break;
996 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
997 case O_bit_or_not: name = "O_bit_or_not"; break;
998 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
999 case O_bit_and: name = "O_bit_and"; break;
1000 case O_add: name = "O_add"; break;
1001 case O_subtract: name = "O_subtract"; break;
1002 case O_eq: name = "O_eq"; break;
1003 case O_ne: name = "O_ne"; break;
1004 case O_lt: name = "O_lt"; break;
1005 case O_le: name = "O_le"; break;
1006 case O_ge: name = "O_ge"; break;
1007 case O_gt: name = "O_gt"; break;
1008 case O_logical_and: name = "O_logical_and"; break;
1009 case O_logical_or: name = "O_logical_or"; break;
1010 case O_index: name = "O_index"; break;
1011 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1012 case O_colon: name = "O_colon"; break;
1013 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1014 }
252b5132 1015
886a2506 1016 switch (t->X_md)
ea1562b3 1017 {
886a2506
NC		 1018 default: namemd = "unknown"; break;
1019 case O_gotoff: namemd = "O_gotoff"; break;
1020 case O_gotpc: namemd = "O_gotpc"; break;
1021 case O_plt: namemd = "O_plt"; break;
1022 case O_sda: namemd = "O_sda"; break;
1023 case O_pcl: namemd = "O_pcl"; break;
1024 case O_tlsgd: namemd = "O_tlsgd"; break;
1025 case O_tlsie: namemd = "O_tlsie"; break;
1026 case O_tpoff9: namemd = "O_tpoff9"; break;
1027 case O_tpoff: namemd = "O_tpoff"; break;
1028 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1029 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1030 }
252b5132 1031
886a2506
NC		 1032 pr_debug ("%s (%s, %s, %d, %s)", name,
1033 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1034 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1035 (int) t->X_add_number,
1036 (t->X_md) ? namemd : "--");
1037 pr_debug ("\n");
1038 fflush (stderr);
1039}
252b5132 1040
886a2506
NC		 1041/* Parse the arguments to an opcode. */
1042
1043static int
1044tokenize_arguments (char *str,
1045 expressionS *tok,
1046 int ntok)
1047{
1048 char *old_input_line_pointer;
1049 bfd_boolean saw_comma = FALSE;
1050 bfd_boolean saw_arg = FALSE;
1051 int brk_lvl = 0;
1052 int num_args = 0;
886a2506
NC		 1053 int i;
1054 size_t len;
1055 const struct arc_reloc_op_tag *r;
1056 expressionS tmpE;
6f4b1afc 1057 char *reloc_name, c;
886a2506
NC		 1058
1059 memset (tok, 0, sizeof (*tok) * ntok);
1060
1061 /* Save and restore input_line_pointer around this function. */
1062 old_input_line_pointer = input_line_pointer;
1063 input_line_pointer = str;
ea1562b3 1064
886a2506 1065 while (*input_line_pointer)
ea1562b3
NC		 1066 {
1067 SKIP_WHITESPACE ();
886a2506 1068 switch (*input_line_pointer)
252b5132 1069 {
886a2506
NC		 1070 case '\0':
1071 goto fini;
1072
1073 case ',':
1074 input_line_pointer++;
1075 if (saw_comma || !saw_arg)
1076 goto err;
1077 saw_comma = TRUE;
1078 break;
252b5132 1079
886a2506
NC		 1080 case '}':
1081 case ']':
1082 ++input_line_pointer;
1083 --brk_lvl;
3b889a78 1084 if (!saw_arg || num_args == ntok)
886a2506
NC		 1085 goto err;
1086 tok->X_op = O_bracket;
1087 ++tok;
1088 ++num_args;
1089 break;
ea1562b3 1090
886a2506
NC		 1091 case '{':
1092 case '[':
1093 input_line_pointer++;
3b889a78 1094 if (brk_lvl || num_args == ntok)
886a2506
NC		 1095 goto err;
1096 ++brk_lvl;
1097 tok->X_op = O_bracket;
1098 ++tok;
1099 ++num_args;
1100 break;
1101
db18dbab
GM		 1102 case ':':
1103 input_line_pointer++;
1104 if (!saw_arg || num_args == ntok)
1105 goto err;
1106 tok->X_op = O_colon;
1107 saw_arg = FALSE;
1108 ++tok;
1109 ++num_args;
1110 break;
1111
886a2506
NC		 1112 case '@':
1113 /* We have labels, function names and relocations, all
1114 starting with @ symbol. Sort them out. */
3b889a78 1115 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1116 goto err;
1117
1118 /* Parse @label. */
1119 tok->X_op = O_symbol;
1120 tok->X_md = O_absent;
1121 expression (tok);
1122 if (*input_line_pointer != '@')
1123 goto normalsymbol; /* This is not a relocation. */
1124
6f4b1afc
CM		 1125 relocationsym:
1126
886a2506
NC		 1127 /* A relocation opernad has the following form
1128 @identifier@relocation_type. The identifier is already
1129 in tok! */
1130 if (tok->X_op != O_symbol)
ea1562b3 1131 {
886a2506
NC		 1132 as_bad (_("No valid label relocation operand"));
1133 goto err;
252b5132 1134 }
886a2506
NC		 1135
1136 /* Parse @relocation_type. */
6f4b1afc
CM		 1137 input_line_pointer++;
1138 c = get_symbol_name (&reloc_name);
1139 len = input_line_pointer - reloc_name;
1140 if (len == 0)
252b5132 1141 {
886a2506
NC		 1142 as_bad (_("No relocation operand"));
1143 goto err;
252b5132 1144 }
252b5132 1145
886a2506
NC		 1146 /* Go through known relocation and try to find a match. */
1147 r = &arc_reloc_op[0];
1148 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1149 if (len == r->length
1150 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1151 break;
886a2506 1152 if (i < 0)
252b5132 1153 {
6f4b1afc 1154 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1155 goto err;
1156 }
1157
6f4b1afc
CM		 1158 *input_line_pointer = c;
1159 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1160 /* Extra check for TLS: base. */
1161 if (*input_line_pointer == '@')
1162 {
1163 symbolS *base;
1164 if (tok->X_op_symbol != NULL
1165 || tok->X_op != O_symbol)
252b5132 1166 {
6f4b1afc
CM		 1167 as_bad (_("Unable to parse TLS base: %s"),
1168 input_line_pointer);
886a2506 1169 goto err;
252b5132 1170 }
886a2506
NC		 1171 input_line_pointer++;
1172 char *sym_name;
6f4b1afc 1173 c = get_symbol_name (&sym_name);
886a2506
NC		 1174 base = symbol_find_or_make (sym_name);
1175 tok->X_op = O_subtract;
1176 tok->X_op_symbol = base;
1177 restore_line_pointer (c);
6f4b1afc
CM		 1178 tmpE.X_add_number = 0;
1179 }
32348c58 1180 if ((*input_line_pointer != '+')
6f4b1afc
CM		 1181 && (*input_line_pointer != '-'))
1182 {
1183 tmpE.X_add_number = 0;
ea1562b3 1184 }
6f4b1afc
CM		 1185 else
1186 {
1187 /* Parse the constant of a complex relocation expression
1188 like @identifier@reloc +/- const. */
1189 if (! r->complex_expr)
1190 {
1191 as_bad (_("@%s is not a complex relocation."), r->name);
1192 goto err;
1193 }
1194 expression (&tmpE);
1195 if (tmpE.X_op != O_constant)
1196 {
1197 as_bad (_("Bad expression: @%s + %s."),
1198 r->name, input_line_pointer);
1199 goto err;
1200 }
1201 }
1202
1203 tok->X_md = r->op;
1204 tok->X_add_number = tmpE.X_add_number;
1e07b820 1205
886a2506 1206 debug_exp (tok);
ea1562b3 1207
886a2506
NC		 1208 saw_comma = FALSE;
1209 saw_arg = TRUE;
1210 tok++;
1211 num_args++;
1212 break;
252b5132 1213
886a2506
NC		 1214 case '%':
1215 /* Can be a register. */
1216 ++input_line_pointer;
1217 /* Fall through. */
1218 default:
252b5132 1219
3b889a78 1220 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1221 goto err;
252b5132 1222
886a2506 1223 tok->X_op = O_absent;
6f4b1afc 1224 tok->X_md = O_absent;
886a2506 1225 expression (tok);
252b5132 1226
6f4b1afc
CM		 1227 /* Legacy: There are cases when we have
1228 identifier@relocation_type, if it is the case parse the
1229 relocation type as well. */
1230 if (*input_line_pointer == '@')
1231 goto relocationsym;
1232
886a2506
NC		 1233 normalsymbol:
1234 debug_exp (tok);
252b5132 1235
3b889a78
AB		 1236 if (tok->X_op == O_illegal
1237 || tok->X_op == O_absent
1238 || num_args == ntok)
886a2506 1239 goto err;
252b5132 1240
886a2506
NC		 1241 saw_comma = FALSE;
1242 saw_arg = TRUE;
1243 tok++;
1244 num_args++;
1245 break;
1246 }
ea1562b3 1247 }
252b5132 1248
886a2506
NC		 1249 fini:
1250 if (saw_comma || brk_lvl)
1251 goto err;
1252 input_line_pointer = old_input_line_pointer;
252b5132 1253
886a2506 1254 return num_args;
252b5132 1255
886a2506
NC		 1256 err:
1257 if (brk_lvl)
1258 as_bad (_("Brackets in operand field incorrect"));
1259 else if (saw_comma)
1260 as_bad (_("extra comma"));
1261 else if (!saw_arg)
1262 as_bad (_("missing argument"));
1263 else
1264 as_bad (_("missing comma or colon"));
1265 input_line_pointer = old_input_line_pointer;
1266 return -1;
252b5132 1267}
ea1562b3 1268
886a2506
NC		 1269/* Parse the flags to a structure. */
1270
1271static int
1272tokenize_flags (const char *str,
1273 struct arc_flags flags[],
1274 int nflg)
252b5132 1275{
886a2506
NC		 1276 char *old_input_line_pointer;
1277 bfd_boolean saw_flg = FALSE;
1278 bfd_boolean saw_dot = FALSE;
1279 int num_flags = 0;
1280 size_t flgnamelen;
252b5132 1281
886a2506 1282 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1283
886a2506
NC		 1284 /* Save and restore input_line_pointer around this function. */
1285 old_input_line_pointer = input_line_pointer;
1286 input_line_pointer = (char *) str;
0d2bcfaf 1287
886a2506
NC		 1288 while (*input_line_pointer)
1289 {
1290 switch (*input_line_pointer)
1291 {
1292 case ' ':
1293 case '\0':
1294 goto fini;
1295
1296 case '.':
1297 input_line_pointer++;
1298 if (saw_dot)
1299 goto err;
1300 saw_dot = TRUE;
1301 saw_flg = FALSE;
1302 break;
ea1562b3 1303
886a2506
NC		 1304 default:
1305 if (saw_flg && !saw_dot)
1306 goto err;
0d2bcfaf 1307
886a2506
NC		 1308 if (num_flags >= nflg)
1309 goto err;
0d2bcfaf 1310
692166c2
AB		 1311 flgnamelen = strspn (input_line_pointer,
1312 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1313 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1314 goto err;
0d2bcfaf 1315
886a2506 1316 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1317
886a2506
NC		 1318 input_line_pointer += flgnamelen;
1319 flags++;
1320 saw_dot = FALSE;
1321 saw_flg = TRUE;
1322 num_flags++;
1323 break;
1e07b820 1324 }
0d2bcfaf
NC		 1325 }
1326
886a2506
NC		 1327 fini:
1328 input_line_pointer = old_input_line_pointer;
1329 return num_flags;
0d2bcfaf 1330
886a2506
NC		 1331 err:
1332 if (saw_dot)
1333 as_bad (_("extra dot"));
1334 else if (!saw_flg)
1335 as_bad (_("unrecognized flag"));
1336 else
1337 as_bad (_("failed to parse flags"));
1338 input_line_pointer = old_input_line_pointer;
1339 return -1;
1340}
0d2bcfaf 1341
4670103e 1342/* Apply the fixups in order. */
0d2bcfaf 1343
4670103e
CZ		 1344static void
1345apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1346{
4670103e 1347 int i;
0d2bcfaf 1348
4670103e 1349 for (i = 0; i < insn->nfixups; i++)
252b5132 1350 {
4670103e
CZ		 1351 struct arc_fixup *fixup = &insn->fixups[i];
1352 int size, pcrel, offset = 0;
0d2bcfaf 1353
4670103e
CZ		 1354 /* FIXME! the reloc size is wrong in the BFD file.
1355 When it is fixed please delete me. */
91fdca6f 1356 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1357
4670103e 1358 if (fixup->islong)
91fdca6f 1359 offset = insn->len;
252b5132 1360
4670103e
CZ		 1361 /* Some fixups are only used internally, thus no howto. */
1362 if ((int) fixup->reloc == 0)
1363 as_fatal (_("Unhandled reloc type"));
886a2506 1364
4670103e
CZ		 1365 if ((int) fixup->reloc < 0)
1366 {
1367 /* FIXME! the reloc size is wrong in the BFD file.
1368 When it is fixed please enable me.
91fdca6f 1369 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1370 pcrel = fixup->pcrel;
1371 }
1372 else
1373 {
1374 reloc_howto_type *reloc_howto =
1375 bfd_reloc_type_lookup (stdoutput,
1376 (bfd_reloc_code_real_type) fixup->reloc);
1377 gas_assert (reloc_howto);
0d2bcfaf 1378
4670103e
CZ		 1379 /* FIXME! the reloc size is wrong in the BFD file.
1380 When it is fixed please enable me.
1381 size = bfd_get_reloc_size (reloc_howto); */
1382 pcrel = reloc_howto->pc_relative;
1383 }
0d2bcfaf 1384
4670103e
CZ		 1385 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1386offset %d + %d\n",
1387 fragP->fr_file, fragP->fr_line,
1388 (fixup->reloc < 0) ? "Internal" :
1389 bfd_get_reloc_code_name (fixup->reloc),
1390 pcrel ? "Y" : "N",
1391 size, fix, offset);
1392 fix_new_exp (fragP, fix + offset,
1393 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1394
4670103e
CZ		 1395 /* Check for ZOLs, and update symbol info if any. */
1396 if (LP_INSN (insn->insn))
886a2506 1397 {
4670103e
CZ		 1398 gas_assert (fixup->exp.X_add_symbol);
1399 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1400 }
1401 }
252b5132
RH		 1402}
1403
4670103e 1404/* Actually output an instruction with its fixup. */
886a2506 1405
4670103e
CZ		 1406static void
1407emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1408{
4670103e 1409 char *f = where;
91fdca6f 1410 size_t total_len;
252b5132 1411
bdfe53e3
AB		 1412 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1413 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1414 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1415
4670103e 1416 /* Write out the instruction. */
91fdca6f
GM		 1417 total_len = insn->len + (insn->has_limm ? 4 : 0);
1418 if (!relax)
1419 f = frag_more (total_len);
1420
1421 md_number_to_chars_midend(f, insn->insn, insn->len);
1422
1423 if (insn->has_limm)
1424 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1425 dwarf2_emit_insn (total_len);
252b5132 1426
4670103e
CZ		 1427 if (!relax)
1428 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1429}
252b5132 1430
4670103e
CZ		 1431static void
1432emit_insn1 (struct arc_insn *insn)
1433{
1434 /* How frag_var's args are currently configured:
1435 - rs_machine_dependent, to dictate it's a relaxation frag.
1436 - FRAG_MAX_GROWTH, maximum size of instruction
1437 - 0, variable size that might grow...unused by generic relaxation.
1438 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1439 - s, opand expression.
1440 - 0, offset but it's unused.
1441 - 0, opcode but it's unused. */
1442 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1443 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1444
1445 if (frag_room () < FRAG_MAX_GROWTH)
1446 {
1447 /* Handle differently when frag literal memory is exhausted.
1448 This is used because when there's not enough memory left in
1449 the current frag, a new frag is created and the information
1450 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1451
4670103e
CZ		 1452 struct arc_relax_type relax_info_copy;
1453 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1454
4670103e
CZ		 1455 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1456 sizeof (struct arc_relax_type));
0d2bcfaf 1457
4670103e
CZ		 1458 frag_wane (frag_now);
1459 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1460
4670103e
CZ		 1461 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1462 sizeof (struct arc_relax_type));
252b5132 1463
4670103e
CZ		 1464 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1465 subtype, s, 0, 0);
1466 }
1467 else
1468 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1469 frag_now->fr_subtype, s, 0, 0);
1470}
252b5132 1471
4670103e
CZ		 1472static void
1473emit_insn (struct arc_insn *insn)
252b5132 1474{
4670103e
CZ		 1475 if (insn->relax)
1476 emit_insn1 (insn);
252b5132 1477 else
4670103e 1478 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1479}
1480
4670103e 1481/* Check whether a symbol involves a register. */
252b5132 1482
4670103e
CZ		 1483static bfd_boolean
1484contains_register (symbolS *sym)
252b5132 1485{
4670103e
CZ		 1486 if (sym)
1487 {
1488 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1489
4670103e
CZ		 1490 return ((O_register == ex->X_op)
1491 && !contains_register (ex->X_add_symbol)
1492 && !contains_register (ex->X_op_symbol));
1493 }
1494
1495 return FALSE;
252b5132
RH		 1496}
1497
4670103e 1498/* Returns the register number within a symbol. */
252b5132 1499
4670103e
CZ		 1500static int
1501get_register (symbolS *sym)
252b5132 1502{
4670103e
CZ		 1503 if (!contains_register (sym))
1504 return -1;
0d2bcfaf 1505
4670103e
CZ		 1506 expressionS *ex = symbol_get_value_expression (sym);
1507 return regno (ex->X_add_number);
1508}
252b5132 1509
4670103e
CZ		 1510/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1511 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1512
4670103e
CZ		 1513static bfd_boolean
1514generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1515{
1516 if (!reloc)
1517 return FALSE;
886a2506 1518
4670103e
CZ		 1519 switch (reloc)
1520 {
1521 case BFD_RELOC_ARC_SDA_LDST:
1522 case BFD_RELOC_ARC_SDA_LDST1:
1523 case BFD_RELOC_ARC_SDA_LDST2:
1524 case BFD_RELOC_ARC_SDA16_LD:
1525 case BFD_RELOC_ARC_SDA16_LD1:
1526 case BFD_RELOC_ARC_SDA16_LD2:
1527 case BFD_RELOC_ARC_SDA16_ST2:
1528 case BFD_RELOC_ARC_SDA32_ME:
1529 return FALSE;
1530 default:
1531 return TRUE;
f17c130b 1532 }
252b5132
RH		 1533}
1534
4670103e 1535/* Allocates a tok entry. */
252b5132 1536
4670103e
CZ		 1537static int
1538allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1539{
4670103e
CZ		 1540 if (ntok > MAX_INSN_ARGS - 2)
1541 return 0; /* No space left. */
252b5132 1542
4670103e
CZ		 1543 if (cidx > ntok)
1544 return 0; /* Incorect args. */
252b5132 1545
4670103e 1546 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1547
4670103e
CZ		 1548 if (cidx == ntok)
1549 return 1; /* Success. */
1550 return allocate_tok (tok, ntok - 1, cidx);
1551}
886a2506 1552
8ddf6b2a
CZ		 1553/* Check if an particular ARC feature is enabled. */
1554
1555static bfd_boolean
1556check_cpu_feature (insn_subclass_t sc)
1557{
bb65a718 1558 if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD))
8ddf6b2a
CZ		 1559 return FALSE;
1560
bb65a718 1561 if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP))
8ddf6b2a
CZ		 1562 return FALSE;
1563
bb65a718 1564 if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP))
8ddf6b2a
CZ		 1565 return FALSE;
1566
bb65a718 1567 if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA))
bdd582db
GM		 1568 return FALSE;
1569
bb65a718 1570 if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400))
8ddf6b2a
CZ		 1571 return FALSE;
1572
1573 return TRUE;
1574}
1575
4eb6f892
AB		 1576/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1577 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1578 array and returns TRUE if the flag operands all match, otherwise,
1579 returns FALSE, in which case the FIRST_PFLAG array may have been
1580 modified. */
1581
1582static bfd_boolean
1583parse_opcode_flags (const struct arc_opcode *opcode,
1584 int nflgs,
1585 struct arc_flags *first_pflag)
1586{
1587 int lnflg, i;
1588 const unsigned char *flgidx;
1589
1590 lnflg = nflgs;
1591 for (i = 0; i < nflgs; i++)
1592 first_pflag[i].flgp = NULL;
1593
1594 /* Check the flags. Iterate over the valid flag classes. */
1595 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1596 {
1597 /* Get a valid flag class. */
1598 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1599 const unsigned *flgopridx;
1600 int cl_matches = 0;
1601 struct arc_flags *pflag = NULL;
1602
1603 /* Check for extension conditional codes. */
1604 if (ext_condcode.arc_ext_condcode
1605 && cl_flags->flag_class & F_CLASS_EXTEND)
1606 {
1607 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1608 while (pf->name)
1609 {
1610 pflag = first_pflag;
1611 for (i = 0; i < nflgs; i++, pflag++)
1612 {
1613 if (!strcmp (pf->name, pflag->name))
1614 {
1615 if (pflag->flgp != NULL)
1616 return FALSE;
1617 /* Found it. */
1618 cl_matches++;
1619 pflag->flgp = pf;
1620 lnflg--;
1621 break;
1622 }
1623 }
1624 pf++;
1625 }
1626 }
1627
1628 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1629 {
1630 const struct arc_flag_operand *flg_operand;
1631
1632 pflag = first_pflag;
1633 flg_operand = &arc_flag_operands[*flgopridx];
1634 for (i = 0; i < nflgs; i++, pflag++)
1635 {
1636 /* Match against the parsed flags. */
1637 if (!strcmp (flg_operand->name, pflag->name))
1638 {
1639 if (pflag->flgp != NULL)
1640 return FALSE;
1641 cl_matches++;
1642 pflag->flgp = flg_operand;
1643 lnflg--;
1644 break; /* goto next flag class and parsed flag. */
1645 }
1646 }
1647 }
1648
1649 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1650 return FALSE;
1651 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1652 return FALSE;
1653 }
1654
1655 /* Did I check all the parsed flags? */
1656 return lnflg ? FALSE : TRUE;
1657}
1658
1659
4670103e
CZ		 1660/* Search forward through all variants of an opcode looking for a
1661 syntax match. */
886a2506 1662
4670103e 1663static const struct arc_opcode *
b9b47ab7 1664find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1665 expressionS *tok,
1666 int *pntok,
1667 struct arc_flags *first_pflag,
1668 int nflgs,
1669 int *pcpumatch)
1670{
1328504b
AB		 1671 const struct arc_opcode *opcode;
1672 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1673 int ntok = *pntok;
1674 int got_cpu_match = 0;
1675 expressionS bktok[MAX_INSN_ARGS];
1676 int bkntok;
1677 expressionS emptyE;
886a2506 1678
1328504b 1679 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1680 memset (&emptyE, 0, sizeof (emptyE));
1681 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1682 bkntok = ntok;
a161fe53 1683
1328504b
AB		 1684 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1685 opcode != NULL;
1686 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1687 {
4670103e 1688 const unsigned char *opidx;
4eb6f892 1689 int tokidx = 0;
4670103e 1690 const expressionS *t = &emptyE;
252b5132 1691
bdfe53e3 1692 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1693 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1694
4670103e
CZ		 1695 /* Don't match opcodes that don't exist on this
1696 architecture. */
bb65a718 1697 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1698 goto match_failed;
886a2506 1699
8ddf6b2a 1700 if (!check_cpu_feature (opcode->subclass))
4670103e 1701 goto match_failed;
886a2506 1702
4670103e
CZ		 1703 got_cpu_match = 1;
1704 pr_debug ("cpu ");
886a2506 1705
4670103e
CZ		 1706 /* Check the operands. */
1707 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1708 {
4670103e 1709 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1710
4670103e 1711 /* Only take input from real operands. */
db18dbab 1712 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1713 continue;
252b5132 1714
4670103e
CZ		 1715 /* When we expect input, make sure we have it. */
1716 if (tokidx >= ntok)
1717 goto match_failed;
6f4b1afc 1718
4670103e
CZ		 1719 /* Match operand type with expression type. */
1720 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1721 {
db18dbab
GM		 1722 case ARC_OPERAND_ADDRTYPE:
1723 /* Check to be an address type. */
1724 if (tok[tokidx].X_op != O_addrtype)
1725 goto match_failed;
1726 break;
1727
4670103e
CZ		 1728 case ARC_OPERAND_IR:
1729 /* Check to be a register. */
1730 if ((tok[tokidx].X_op != O_register
1731 || !is_ir_num (tok[tokidx].X_add_number))
1732 && !(operand->flags & ARC_OPERAND_IGNORE))
1733 goto match_failed;
1734
1735 /* If expect duplicate, make sure it is duplicate. */
1736 if (operand->flags & ARC_OPERAND_DUPLICATE)
1737 {
1738 /* Check for duplicate. */
1739 if (t->X_op != O_register
1740 || !is_ir_num (t->X_add_number)
1741 || (regno (t->X_add_number) !=
1742 regno (tok[tokidx].X_add_number)))
1743 goto match_failed;
1744 }
1745
1746 /* Special handling? */
1747 if (operand->insert)
1748 {
1749 const char *errmsg = NULL;
1750 (*operand->insert)(0,
1751 regno (tok[tokidx].X_add_number),
1752 &errmsg);
1753 if (errmsg)
1754 {
1755 if (operand->flags & ARC_OPERAND_IGNORE)
1756 {
1757 /* Missing argument, create one. */
1758 if (!allocate_tok (tok, ntok - 1, tokidx))
1759 goto match_failed;
1760
1761 tok[tokidx].X_op = O_absent;
1762 ++ntok;
1763 }
1764 else
1765 goto match_failed;
1766 }
1767 }
1768
1769 t = &tok[tokidx];
1770 break;
1771
1772 case ARC_OPERAND_BRAKET:
1773 /* Check if bracket is also in opcode table as
1774 operand. */
1775 if (tok[tokidx].X_op != O_bracket)
1776 goto match_failed;
1777 break;
1778
db18dbab
GM		 1779 case ARC_OPERAND_COLON:
1780 /* Check if colon is also in opcode table as operand. */
1781 if (tok[tokidx].X_op != O_colon)
1782 goto match_failed;
1783 break;
1784
4670103e
CZ		 1785 case ARC_OPERAND_LIMM:
1786 case ARC_OPERAND_SIGNED:
1787 case ARC_OPERAND_UNSIGNED:
1788 switch (tok[tokidx].X_op)
1789 {
1790 case O_illegal:
1791 case O_absent:
1792 case O_register:
1793 goto match_failed;
1794
1795 case O_bracket:
1796 /* Got an (too) early bracket, check if it is an
1797 ignored operand. N.B. This procedure works only
1798 when bracket is the last operand! */
1799 if (!(operand->flags & ARC_OPERAND_IGNORE))
1800 goto match_failed;
1801 /* Insert the missing operand. */
1802 if (!allocate_tok (tok, ntok - 1, tokidx))
1803 goto match_failed;
1804
1805 tok[tokidx].X_op = O_absent;
1806 ++ntok;
1807 break;
1808
22b92fc4
AB		 1809 case O_symbol:
1810 {
1811 const char *p;
22b92fc4 1812 const struct arc_aux_reg *auxr;
22b92fc4 1813
c810e0b8 1814 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1815 goto de_fault;
1816 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da
CZ		 1817
1818 auxr = hash_find (arc_aux_hash, p);
1819 if (auxr)
1820 {
1821 /* We modify the token array here, safe in the
1822 knowledge, that if this was the wrong
1823 choice then the original contents will be
1824 restored from BKTOK. */
1825 tok[tokidx].X_op = O_constant;
1826 tok[tokidx].X_add_number = auxr->address;
1827 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1828 }
22b92fc4
AB		 1829
1830 if (tok[tokidx].X_op != O_constant)
1831 goto de_fault;
1832 }
1a0670f3 1833 /* Fall through. */
4670103e
CZ		 1834 case O_constant:
1835 /* Check the range. */
1836 if (operand->bits != 32
1837 && !(operand->flags & ARC_OPERAND_NCHK))
1838 {
1839 offsetT min, max, val;
1840 val = tok[tokidx].X_add_number;
1841
1842 if (operand->flags & ARC_OPERAND_SIGNED)
1843 {
1844 max = (1 << (operand->bits - 1)) - 1;
1845 min = -(1 << (operand->bits - 1));
1846 }
1847 else
1848 {
1849 max = (1 << operand->bits) - 1;
1850 min = 0;
1851 }
1852
1853 if (val < min || val > max)
1854 goto match_failed;
1855
1856 /* Check alignmets. */
1857 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1858 && (val & 0x03))
1859 goto match_failed;
1860
1861 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1862 && (val & 0x01))
1863 goto match_failed;
1864 }
1865 else if (operand->flags & ARC_OPERAND_NCHK)
1866 {
1867 if (operand->insert)
1868 {
1869 const char *errmsg = NULL;
1870 (*operand->insert)(0,
1871 tok[tokidx].X_add_number,
1872 &errmsg);
1873 if (errmsg)
1874 goto match_failed;
1875 }
4eb6f892 1876 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1877 goto match_failed;
1878 }
1879 break;
1880
1881 case O_subtract:
1882 /* Check if it is register range. */
1883 if ((tok[tokidx].X_add_number == 0)
1884 && contains_register (tok[tokidx].X_add_symbol)
1885 && contains_register (tok[tokidx].X_op_symbol))
1886 {
1887 int regs;
1888
1889 regs = get_register (tok[tokidx].X_add_symbol);
1890 regs <<= 16;
1891 regs |= get_register (tok[tokidx].X_op_symbol);
1892 if (operand->insert)
1893 {
1894 const char *errmsg = NULL;
1895 (*operand->insert)(0,
1896 regs,
1897 &errmsg);
1898 if (errmsg)
1899 goto match_failed;
1900 }
1901 else
1902 goto match_failed;
1903 break;
1904 }
1a0670f3 1905 /* Fall through. */
4670103e 1906 default:
22b92fc4 1907 de_fault:
4670103e
CZ		 1908 if (operand->default_reloc == 0)
1909 goto match_failed; /* The operand needs relocation. */
1910
1911 /* Relocs requiring long immediate. FIXME! make it
1912 generic and move it to a function. */
1913 switch (tok[tokidx].X_md)
1914 {
1915 case O_gotoff:
1916 case O_gotpc:
1917 case O_pcl:
1918 case O_tpoff:
1919 case O_dtpoff:
1920 case O_tlsgd:
1921 case O_tlsie:
1922 if (!(operand->flags & ARC_OPERAND_LIMM))
1923 goto match_failed;
1a0670f3 1924 /* Fall through. */
4670103e
CZ		 1925 case O_absent:
1926 if (!generic_reloc_p (operand->default_reloc))
1927 goto match_failed;
2b804145 1928 break;
4670103e
CZ		 1929 default:
1930 break;
1931 }
1932 break;
1933 }
1934 /* If expect duplicate, make sure it is duplicate. */
1935 if (operand->flags & ARC_OPERAND_DUPLICATE)
1936 {
1937 if (t->X_op == O_illegal
1938 || t->X_op == O_absent
1939 || t->X_op == O_register
1940 || (t->X_add_number != tok[tokidx].X_add_number))
1941 goto match_failed;
1942 }
1943 t = &tok[tokidx];
1944 break;
1945
1946 default:
1947 /* Everything else should have been fake. */
1948 abort ();
1949 }
1950
1951 ++tokidx;
1952 }
1953 pr_debug ("opr ");
1954
1ae8ab47 1955 /* Setup ready for flag parsing. */
4eb6f892 1956 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 1957 goto match_failed;
1958
1959 pr_debug ("flg");
1960 /* Possible match -- did we use all of our input? */
1961 if (tokidx == ntok)
1962 {
1963 *pntok = ntok;
1964 pr_debug ("\n");
1965 return opcode;
1966 }
1967
1968 match_failed:;
1969 pr_debug ("\n");
1970 /* Restore the original parameters. */
1971 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
1972 ntok = bkntok;
1973 }
4670103e
CZ		 1974
1975 if (*pcpumatch)
1976 *pcpumatch = got_cpu_match;
1977
1978 return NULL;
1979}
1980
1981/* Swap operand tokens. */
1982
1983static void
1984swap_operand (expressionS *operand_array,
1985 unsigned source,
1986 unsigned destination)
1987{
1988 expressionS cpy_operand;
1989 expressionS *src_operand;
1990 expressionS *dst_operand;
1991 size_t size;
1992
1993 if (source == destination)
1994 return;
1995
1996 src_operand = &operand_array[source];
1997 dst_operand = &operand_array[destination];
1998 size = sizeof (expressionS);
1999
2000 /* Make copy of operand to swap with and swap. */
2001 memcpy (&cpy_operand, dst_operand, size);
2002 memcpy (dst_operand, src_operand, size);
2003 memcpy (src_operand, &cpy_operand, size);
2004}
2005
2006/* Check if *op matches *tok type.
2007 Returns FALSE if they don't match, TRUE if they match. */
2008
2009static bfd_boolean
2010pseudo_operand_match (const expressionS *tok,
2011 const struct arc_operand_operation *op)
2012{
2013 offsetT min, max, val;
2014 bfd_boolean ret;
2015 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2016
2017 ret = FALSE;
2018 switch (tok->X_op)
2019 {
2020 case O_constant:
2021 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2022 ret = 1;
2023 else if (!(operand_real->flags & ARC_OPERAND_IR))
2024 {
2025 val = tok->X_add_number + op->count;
2026 if (operand_real->flags & ARC_OPERAND_SIGNED)
2027 {
2028 max = (1 << (operand_real->bits - 1)) - 1;
2029 min = -(1 << (operand_real->bits - 1));
2030 }
2031 else
2032 {
2033 max = (1 << operand_real->bits) - 1;
2034 min = 0;
2035 }
2036 if (min <= val && val <= max)
2037 ret = TRUE;
2038 }
6f4b1afc
CM		 2039 break;
2040
4670103e
CZ		 2041 case O_symbol:
2042 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2043 if (operand_real->flags & ARC_OPERAND_LIMM
2044 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2045 && operand_real->bits == 9))
4670103e 2046 ret = TRUE;
6f4b1afc
CM		 2047 break;
2048
4670103e
CZ		 2049 case O_register:
2050 if (operand_real->flags & ARC_OPERAND_IR)
2051 ret = TRUE;
2052 break;
2053
2054 case O_bracket:
2055 if (operand_real->flags & ARC_OPERAND_BRAKET)
2056 ret = TRUE;
6f4b1afc
CM		 2057 break;
2058
2059 default:
4670103e 2060 /* Unknown. */
6f4b1afc
CM		 2061 break;
2062 }
4670103e
CZ		 2063 return ret;
2064}
6f4b1afc 2065
4670103e
CZ		 2066/* Find pseudo instruction in array. */
2067
2068static const struct arc_pseudo_insn *
2069find_pseudo_insn (const char *opname,
2070 int ntok,
2071 const expressionS *tok)
2072{
2073 const struct arc_pseudo_insn *pseudo_insn = NULL;
2074 const struct arc_operand_operation *op;
2075 unsigned int i;
2076 int j;
2077
2078 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2079 {
4670103e
CZ		 2080 pseudo_insn = &arc_pseudo_insns[i];
2081 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2082 {
2083 op = pseudo_insn->operand;
2084 for (j = 0; j < ntok; ++j)
2085 if (!pseudo_operand_match (&tok[j], &op[j]))
2086 break;
2087
2088 /* Found the right instruction. */
2089 if (j == ntok)
2090 return pseudo_insn;
2091 }
6f4b1afc 2092 }
4670103e
CZ		 2093 return NULL;
2094}
252b5132 2095
4670103e 2096/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2097
b9b47ab7 2098static const struct arc_opcode_hash_entry *
4670103e
CZ		 2099find_special_case_pseudo (const char *opname,
2100 int *ntok,
2101 expressionS *tok,
2102 int *nflgs,
2103 struct arc_flags *pflags)
2104{
2105 const struct arc_pseudo_insn *pseudo_insn = NULL;
2106 const struct arc_operand_operation *operand_pseudo;
2107 const struct arc_operand *operand_real;
2108 unsigned i;
2109 char construct_operand[MAX_CONSTR_STR];
886a2506 2110
4670103e
CZ		 2111 /* Find whether opname is in pseudo instruction array. */
2112 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2113
2114 if (pseudo_insn == NULL)
2115 return NULL;
2116
2117 /* Handle flag, Limited to one flag at the moment. */
2118 if (pseudo_insn->flag_r != NULL)
2119 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2120 MAX_INSN_FLGS - *nflgs);
2121
2122 /* Handle operand operations. */
2123 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2124 {
4670103e
CZ		 2125 operand_pseudo = &pseudo_insn->operand[i];
2126 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2127
db18dbab
GM		 2128 if (operand_real->flags & ARC_OPERAND_BRAKET
2129 && !operand_pseudo->needs_insert)
4670103e 2130 continue;
b125bd17 2131
4670103e
CZ		 2132 /* Has to be inserted (i.e. this token does not exist yet). */
2133 if (operand_pseudo->needs_insert)
2134 {
2135 if (operand_real->flags & ARC_OPERAND_BRAKET)
2136 {
2137 tok[i].X_op = O_bracket;
2138 ++(*ntok);
2139 continue;
2140 }
b125bd17 2141
4670103e
CZ		 2142 /* Check if operand is a register or constant and handle it
2143 by type. */
2144 if (operand_real->flags & ARC_OPERAND_IR)
2145 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2146 operand_pseudo->count);
2147 else
2148 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2149 operand_pseudo->count);
886a2506 2150
4670103e
CZ		 2151 tokenize_arguments (construct_operand, &tok[i], 1);
2152 ++(*ntok);
2153 }
2154
2155 else if (operand_pseudo->count)
2156 {
2157 /* Operand number has to be adjusted accordingly (by operand
2158 type). */
2159 switch (tok[i].X_op)
2160 {
2161 case O_constant:
2162 tok[i].X_add_number += operand_pseudo->count;
2163 break;
2164
2165 case O_symbol:
2166 break;
2167
2168 default:
2169 /* Ignored. */
2170 break;
2171 }
2172 }
2173 }
2174
2175 /* Swap operands if necessary. Only supports one swap at the
2176 moment. */
2177 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2178 {
2179 operand_pseudo = &pseudo_insn->operand[i];
2180
2181 if (operand_pseudo->swap_operand_idx == i)
2182 continue;
2183
2184 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2185
2186 /* Prevent a swap back later by breaking out. */
2187 break;
2188 }
2189
da5be039 2190 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2191}
2192
b9b47ab7 2193static const struct arc_opcode_hash_entry *
4670103e
CZ		 2194find_special_case_flag (const char *opname,
2195 int *nflgs,
2196 struct arc_flags *pflags)
2197{
2198 unsigned int i;
2199 const char *flagnm;
2200 unsigned flag_idx, flag_arr_idx;
2201 size_t flaglen, oplen;
2202 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2203 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2204
2205 /* Search for special case instruction. */
2206 for (i = 0; i < arc_num_flag_special; i++)
2207 {
2208 arc_flag_special_opcode = &arc_flag_special_cases[i];
2209 oplen = strlen (arc_flag_special_opcode->name);
2210
2211 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2212 continue;
2213
2214 /* Found a potential special case instruction, now test for
2215 flags. */
2216 for (flag_arr_idx = 0;; ++flag_arr_idx)
2217 {
2218 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2219 if (flag_idx == 0)
2220 break; /* End of array, nothing found. */
886a2506 2221
4670103e
CZ		 2222 flagnm = arc_flag_operands[flag_idx].name;
2223 flaglen = strlen (flagnm);
2224 if (strcmp (opname + oplen, flagnm) == 0)
2225 {
b9b47ab7 2226 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2227
4670103e
CZ		 2228 if (*nflgs + 1 > MAX_INSN_FLGS)
2229 break;
2230 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2231 pflags[*nflgs].name[flaglen] = '\0';
2232 (*nflgs)++;
b9b47ab7 2233 return entry;
4670103e
CZ		 2234 }
2235 }
2236 }
2237 return NULL;
2238}
886a2506 2239
4670103e 2240/* Used to find special case opcode. */
886a2506 2241
b9b47ab7 2242static const struct arc_opcode_hash_entry *
4670103e
CZ		 2243find_special_case (const char *opname,
2244 int *nflgs,
2245 struct arc_flags *pflags,
2246 expressionS *tok,
2247 int *ntok)
2248{
b9b47ab7 2249 const struct arc_opcode_hash_entry *entry;
886a2506 2250
b9b47ab7 2251 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2252
b9b47ab7
AB		 2253 if (entry == NULL)
2254 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2255
b9b47ab7 2256 return entry;
4670103e 2257}
886a2506 2258
4670103e
CZ		 2259/* Given an opcode name, pre-tockenized set of argumenst and the
2260 opcode flags, take it all the way through emission. */
886a2506 2261
4670103e
CZ		 2262static void
2263assemble_tokens (const char *opname,
2264 expressionS *tok,
2265 int ntok,
2266 struct arc_flags *pflags,
2267 int nflgs)
2268{
2269 bfd_boolean found_something = FALSE;
b9b47ab7 2270 const struct arc_opcode_hash_entry *entry;
4670103e 2271 int cpumatch = 1;
886a2506 2272
4670103e 2273 /* Search opcodes. */
b9b47ab7 2274 entry = arc_find_opcode (opname);
886a2506 2275
4670103e 2276 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2277 if (entry == NULL)
2278 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2279
b9b47ab7 2280 if (entry != NULL)
4670103e 2281 {
b9b47ab7
AB		 2282 const struct arc_opcode *opcode;
2283
1328504b
AB		 2284 pr_debug ("%s:%d: assemble_tokens: %s\n",
2285 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2286 found_something = TRUE;
b9b47ab7
AB		 2287 opcode = find_opcode_match (entry, tok, &ntok, pflags,
2288 nflgs, &cpumatch);
2289 if (opcode != NULL)
4670103e
CZ		 2290 {
2291 struct arc_insn insn;
b9b47ab7 2292
4670103e
CZ		 2293 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2294 emit_insn (&insn);
2295 return;
2296 }
2297 }
886a2506 2298
4670103e
CZ		 2299 if (found_something)
2300 {
2301 if (cpumatch)
2302 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2303 else
2304 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2305 selected_cpu.name);
4670103e
CZ		 2306 }
2307 else
2308 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2309}
2310
4670103e 2311/* The public interface to the instruction assembler. */
886a2506 2312
4670103e
CZ		 2313void
2314md_assemble (char *str)
886a2506 2315{
4670103e
CZ		 2316 char *opname;
2317 expressionS tok[MAX_INSN_ARGS];
2318 int ntok, nflg;
2319 size_t opnamelen;
2320 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2321
4670103e
CZ		 2322 /* Split off the opcode. */
2323 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2324 opname = xmemdup0 (str, opnamelen);
886a2506 2325
4670103e
CZ		 2326 /* Signalize we are assmbling the instructions. */
2327 assembling_insn = TRUE;
886a2506 2328
4670103e
CZ		 2329 /* Tokenize the flags. */
2330 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2331 {
2332 as_bad (_("syntax error"));
2333 return;
2334 }
886a2506 2335
4670103e
CZ		 2336 /* Scan up to the end of the mnemonic which must end in space or end
2337 of string. */
2338 str += opnamelen;
2339 for (; *str != '\0'; str++)
2340 if (*str == ' ')
2341 break;
886a2506 2342
4670103e
CZ		 2343 /* Tokenize the rest of the line. */
2344 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2345 {
4670103e
CZ		 2346 as_bad (_("syntax error"));
2347 return;
252b5132
RH		 2348 }
2349
4670103e
CZ		 2350 /* Finish it off. */
2351 assemble_tokens (opname, tok, ntok, flags, nflg);
2352 assembling_insn = FALSE;
2353}
2354
2355/* Callback to insert a register into the hash table. */
2356
2357static void
f86f5863 2358declare_register (const char *name, int number)
4670103e
CZ		 2359{
2360 const char *err;
2361 symbolS *regS = symbol_create (name, reg_section,
2362 number, &zero_address_frag);
2363
2364 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2365 if (err)
e6ba1cba 2366 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2367 name, err);
2368}
252b5132 2369
4670103e 2370/* Construct symbols for each of the general registers. */
252b5132 2371
4670103e
CZ		 2372static void
2373declare_register_set (void)
2374{
2375 int i;
2376 for (i = 0; i < 64; ++i)
886a2506 2377 {
4670103e
CZ		 2378 char name[7];
2379
2380 sprintf (name, "r%d", i);
2381 declare_register (name, i);
2382 if ((i & 0x01) == 0)
886a2506 2383 {
4670103e
CZ		 2384 sprintf (name, "r%dr%d", i, i+1);
2385 declare_register (name, i);
886a2506
NC		 2386 }
2387 }
252b5132 2388}
ea1562b3 2389
db18dbab
GM		 2390/* Construct a symbol for an address type. */
2391
2392static void
2393declare_addrtype (const char *name, int number)
2394{
2395 const char *err;
2396 symbolS *addrtypeS = symbol_create (name, undefined_section,
2397 number, &zero_address_frag);
2398
2399 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2400 (void *) addrtypeS);
2401 if (err)
2402 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2403 name, err);
2404}
2405
4670103e
CZ		 2406/* Port-specific assembler initialization. This function is called
2407 once, at assembler startup time. */
ea1562b3
NC		 2408
2409void
4670103e 2410md_begin (void)
ea1562b3 2411{
b99747ae 2412 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2413
bb65a718
AB		 2414 if (mach_selection_mode == MACH_SELECTION_NONE)
2415 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2416
4670103e
CZ		 2417 /* The endianness can be chosen "at the factory". */
2418 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2419
bb65a718 2420 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2421 as_warn (_("could not set architecture and machine"));
2422
2423 /* Set elf header flags. */
bb65a718 2424 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2425
2426 /* Set up a hash table for the instructions. */
2427 arc_opcode_hash = hash_new ();
2428 if (arc_opcode_hash == NULL)
2429 as_fatal (_("Virtual memory exhausted"));
2430
2431 /* Initialize the hash table with the insns. */
b99747ae 2432 do
ea1562b3 2433 {
b99747ae 2434 const char *name = opcode->name;
da5be039 2435
b99747ae 2436 arc_insert_opcode (opcode);
4670103e 2437
b99747ae
CZ		 2438 while (++opcode && opcode->name
2439 && (opcode->name == name
2440 || !strcmp (opcode->name, name)))
4670103e 2441 continue;
b99747ae 2442 }while (opcode->name);
4670103e
CZ		 2443
2444 /* Register declaration. */
2445 arc_reg_hash = hash_new ();
2446 if (arc_reg_hash == NULL)
2447 as_fatal (_("Virtual memory exhausted"));
2448
2449 declare_register_set ();
2450 declare_register ("gp", 26);
2451 declare_register ("fp", 27);
2452 declare_register ("sp", 28);
2453 declare_register ("ilink", 29);
2454 declare_register ("ilink1", 29);
2455 declare_register ("ilink2", 30);
2456 declare_register ("blink", 31);
2457
87789e08
CZ		 2458 /* XY memory registers. */
2459 declare_register ("x0_u0", 32);
2460 declare_register ("x0_u1", 33);
2461 declare_register ("x1_u0", 34);
2462 declare_register ("x1_u1", 35);
2463 declare_register ("x2_u0", 36);
2464 declare_register ("x2_u1", 37);
2465 declare_register ("x3_u0", 38);
2466 declare_register ("x3_u1", 39);
2467 declare_register ("y0_u0", 40);
2468 declare_register ("y0_u1", 41);
2469 declare_register ("y1_u0", 42);
2470 declare_register ("y1_u1", 43);
2471 declare_register ("y2_u0", 44);
2472 declare_register ("y2_u1", 45);
2473 declare_register ("y3_u0", 46);
2474 declare_register ("y3_u1", 47);
2475 declare_register ("x0_nu", 48);
2476 declare_register ("x1_nu", 49);
2477 declare_register ("x2_nu", 50);
2478 declare_register ("x3_nu", 51);
2479 declare_register ("y0_nu", 52);
2480 declare_register ("y1_nu", 53);
2481 declare_register ("y2_nu", 54);
2482 declare_register ("y3_nu", 55);
2483
4670103e
CZ		 2484 declare_register ("mlo", 57);
2485 declare_register ("mmid", 58);
2486 declare_register ("mhi", 59);
2487
2488 declare_register ("acc1", 56);
2489 declare_register ("acc2", 57);
2490
2491 declare_register ("lp_count", 60);
2492 declare_register ("pcl", 63);
2493
2494 /* Initialize the last instructions. */
2495 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2496
2497 /* Aux register declaration. */
2498 arc_aux_hash = hash_new ();
2499 if (arc_aux_hash == NULL)
2500 as_fatal (_("Virtual memory exhausted"));
2501
2502 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2503 unsigned int i;
2504 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2505 {
2506 const char *retval;
2507
bb65a718 2508 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2509 continue;
2510
2511 if ((auxr->subclass != NONE)
2512 && !check_cpu_feature (auxr->subclass))
2513 continue;
2514
2515 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2516 if (retval)
2517 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2518 auxr->name, retval);
2519 }
db18dbab
GM		 2520
2521 /* Address type declaration. */
2522 arc_addrtype_hash = hash_new ();
2523 if (arc_addrtype_hash == NULL)
2524 as_fatal (_("Virtual memory exhausted"));
2525
2526 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2527 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2528 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2529 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2530 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2531 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2532 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2533 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2534 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2535 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2536 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2537 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2538 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2539 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2540 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2541 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2542}
ea1562b3 2543
4670103e
CZ		 2544/* Write a value out to the object file, using the appropriate
2545 endianness. */
ea1562b3 2546
4670103e
CZ		 2547void
2548md_number_to_chars (char *buf,
2549 valueT val,
2550 int n)
886a2506 2551{
4670103e
CZ		 2552 if (target_big_endian)
2553 number_to_chars_bigendian (buf, val, n);
2554 else
2555 number_to_chars_littleendian (buf, val, n);
886a2506 2556}
ea1562b3 2557
4670103e 2558/* Round up a section size to the appropriate boundary. */
ea1562b3 2559
4670103e
CZ		 2560valueT
2561md_section_align (segT segment,
2562 valueT size)
886a2506 2563{
4670103e
CZ		 2564 int align = bfd_get_section_alignment (stdoutput, segment);
2565
2566 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2567}
ea1562b3 2568
4670103e
CZ		 2569/* The location from which a PC relative jump should be calculated,
2570 given a PC relative reloc. */
ea1562b3 2571
4670103e
CZ		 2572long
2573md_pcrel_from_section (fixS *fixP,
2574 segT sec)
886a2506 2575{
4670103e 2576 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2577
4670103e 2578 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2579
4670103e
CZ		 2580 if (fixP->fx_addsy != (symbolS *) NULL
2581 && (!S_IS_DEFINED (fixP->fx_addsy)
2582 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2583 {
2584 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2585
4670103e
CZ		 2586 /* The symbol is undefined (or is defined but not in this section).
2587 Let the linker figure it out. */
2588 return 0;
2589 }
2590
2591 if ((int) fixP->fx_r_type < 0)
886a2506 2592 {
4670103e
CZ		 2593 /* These are the "internal" relocations. Align them to
2594 32 bit boundary (PCL), for the moment. */
2595 base &= ~3;
886a2506 2596 }
4670103e
CZ		 2597 else
2598 {
2599 switch (fixP->fx_r_type)
2600 {
2601 case BFD_RELOC_ARC_PC32:
2602 /* The hardware calculates relative to the start of the
2603 insn, but this relocation is relative to location of the
2604 LIMM, compensate. The base always needs to be
2605 substracted by 4 as we do not support this type of PCrel
2606 relocation for short instructions. */
2607 base -= 4;
2608 /* Fall through. */
2609 case BFD_RELOC_ARC_PLT32:
2610 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2611 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2612 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2613 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2614
2615 case BFD_RELOC_ARC_S21H_PCREL:
2616 case BFD_RELOC_ARC_S25H_PCREL:
2617 case BFD_RELOC_ARC_S13_PCREL:
2618 case BFD_RELOC_ARC_S21W_PCREL:
2619 case BFD_RELOC_ARC_S25W_PCREL:
2620 base &= ~3;
2621 break;
2622 default:
2623 as_bad_where (fixP->fx_file, fixP->fx_line,
2624 _("unhandled reloc %s in md_pcrel_from_section"),
2625 bfd_get_reloc_code_name (fixP->fx_r_type));
2626 break;
2627 }
2628 }
2629
9e32d9ae
AB		 2630 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2631 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2632 fixP->fx_frag->fr_address, fixP->fx_where, base,
2633 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2634 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2635
2636 return base;
886a2506 2637}
ea1562b3 2638
4670103e 2639/* Given a BFD relocation find the coresponding operand. */
ea1562b3 2640
4670103e
CZ		 2641static const struct arc_operand *
2642find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2643{
2644 unsigned i;
ea1562b3 2645
4670103e
CZ		 2646 for (i = 0; i < arc_num_operands; i++)
2647 if (arc_operands[i].default_reloc == reloc)
2648 return &arc_operands[i];
2649 return NULL;
2650}
ea1562b3 2651
4670103e 2652/* Insert an operand value into an instruction. */
ea1562b3 2653
bdfe53e3
AB		 2654static unsigned long long
2655insert_operand (unsigned long long insn,
4670103e 2656 const struct arc_operand *operand,
bdfe53e3 2657 long long val,
3b4dbbbf 2658 const char *file,
4670103e 2659 unsigned line)
886a2506 2660{
4670103e 2661 offsetT min = 0, max = 0;
ea1562b3 2662
4670103e
CZ		 2663 if (operand->bits != 32
2664 && !(operand->flags & ARC_OPERAND_NCHK)
2665 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2666 {
4670103e
CZ		 2667 if (operand->flags & ARC_OPERAND_SIGNED)
2668 {
2669 max = (1 << (operand->bits - 1)) - 1;
2670 min = -(1 << (operand->bits - 1));
2671 }
2672 else
2673 {
2674 max = (1 << operand->bits) - 1;
2675 min = 0;
2676 }
886a2506 2677
4670103e
CZ		 2678 if (val < min || val > max)
2679 as_bad_value_out_of_range (_("operand"),
2680 val, min, max, file, line);
2681 }
ea1562b3 2682
bdfe53e3 2683 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n",
4670103e 2684 min, val, max, insn);
ea1562b3 2685
4670103e
CZ		 2686 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2687 && (val & 0x03))
2688 as_bad_where (file, line,
2689 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2690
4670103e
CZ		 2691 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2692 && (val & 0x01))
2693 as_bad_where (file, line,
2694 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2695
4670103e
CZ		 2696 if (operand->insert)
2697 {
2698 const char *errmsg = NULL;
ea1562b3 2699
4670103e
CZ		 2700 insn = (*operand->insert) (insn, val, &errmsg);
2701 if (errmsg)
2702 as_warn_where (file, line, "%s", errmsg);
2703 }
2704 else
2705 {
2706 if (operand->flags & ARC_OPERAND_TRUNCATE)
2707 {
2708 if (operand->flags & ARC_OPERAND_ALIGNED32)
2709 val >>= 2;
2710 if (operand->flags & ARC_OPERAND_ALIGNED16)
2711 val >>= 1;
886a2506 2712 }
4670103e
CZ		 2713 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2714 }
2715 return insn;
2716}
ea1562b3 2717
4670103e
CZ		 2718/* Apply a fixup to the object code. At this point all symbol values
2719 should be fully resolved, and we attempt to completely resolve the
2720 reloc. If we can not do that, we determine the correct reloc code
2721 and put it back in the fixup. To indicate that a fixup has been
2722 eliminated, set fixP->fx_done. */
ea1562b3 2723
4670103e
CZ		 2724void
2725md_apply_fix (fixS *fixP,
2726 valueT *valP,
2727 segT seg)
2728{
2729 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2730 valueT value = *valP;
2731 unsigned insn = 0;
2732 symbolS *fx_addsy, *fx_subsy;
2733 offsetT fx_offset;
2734 segT add_symbol_segment = absolute_section;
2735 segT sub_symbol_segment = absolute_section;
2736 const struct arc_operand *operand = NULL;
2737 extended_bfd_reloc_code_real_type reloc;
886a2506 2738
4670103e
CZ		 2739 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2740 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2741 ((int) fixP->fx_r_type < 0) ? "Internal":
2742 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2743 fixP->fx_offset);
886a2506 2744
4670103e
CZ		 2745 fx_addsy = fixP->fx_addsy;
2746 fx_subsy = fixP->fx_subsy;
2747 fx_offset = 0;
886a2506 2748
4670103e
CZ		 2749 if (fx_addsy)
2750 {
2751 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2752 }
2753
4670103e
CZ		 2754 if (fx_subsy
2755 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2756 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2757 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2758 {
2759 resolve_symbol_value (fx_subsy);
2760 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2761
4670103e
CZ		 2762 if (sub_symbol_segment == absolute_section)
2763 {
2764 /* The symbol is really a constant. */
2765 fx_offset -= S_GET_VALUE (fx_subsy);
2766 fx_subsy = NULL;
2767 }
2768 else
2769 {
2770 as_bad_where (fixP->fx_file, fixP->fx_line,
2771 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2772 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2773 segment_name (add_symbol_segment),
2774 S_GET_NAME (fx_subsy),
2775 segment_name (sub_symbol_segment));
2776 return;
2777 }
2778 }
886a2506 2779
4670103e
CZ		 2780 if (fx_addsy
2781 && !S_IS_WEAK (fx_addsy))
2782 {
2783 if (add_symbol_segment == seg
2784 && fixP->fx_pcrel)
2785 {
2786 value += S_GET_VALUE (fx_addsy);
2787 value -= md_pcrel_from_section (fixP, seg);
2788 fx_addsy = NULL;
2789 fixP->fx_pcrel = FALSE;
2790 }
2791 else if (add_symbol_segment == absolute_section)
2792 {
2793 value = fixP->fx_offset;
2794 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2795 fx_addsy = NULL;
2796 fixP->fx_pcrel = FALSE;
2797 }
2798 }
886a2506 2799
4670103e
CZ		 2800 if (!fx_addsy)
2801 fixP->fx_done = TRUE;
886a2506 2802
4670103e 2803 if (fixP->fx_pcrel)
886a2506 2804 {
4670103e
CZ		 2805 if (fx_addsy
2806 && ((S_IS_DEFINED (fx_addsy)
2807 && S_GET_SEGMENT (fx_addsy) != seg)
2808 || S_IS_WEAK (fx_addsy)))
2809 value += md_pcrel_from_section (fixP, seg);
886a2506 2810
4670103e
CZ		 2811 switch (fixP->fx_r_type)
2812 {
2813 case BFD_RELOC_ARC_32_ME:
2814 /* This is a pc-relative value in a LIMM. Adjust it to the
2815 address of the instruction not to the address of the
2816 LIMM. Note: it is not anylonger valid this afirmation as
2817 the linker consider ARC_PC32 a fixup to entire 64 bit
2818 insn. */
2819 fixP->fx_offset += fixP->fx_frag->fr_address;
2820 /* Fall through. */
2821 case BFD_RELOC_32:
2822 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2823 /* Fall through. */
2824 case BFD_RELOC_ARC_PC32:
2825 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2826 break;
2827 default:
4670103e
CZ		 2828 if ((int) fixP->fx_r_type < 0)
2829 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2830 fixP->fx_r_type);
886a2506 2831 break;
ea1562b3
NC		 2832 }
2833 }
2834
4670103e
CZ		 2835 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2836 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2837 ((int) fixP->fx_r_type < 0) ? "Internal":
2838 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2839 fixP->fx_offset);
886a2506 2840
886a2506 2841
4670103e
CZ		 2842 /* Now check for TLS relocations. */
2843 reloc = fixP->fx_r_type;
2844 switch (reloc)
886a2506 2845 {
4670103e
CZ		 2846 case BFD_RELOC_ARC_TLS_DTPOFF:
2847 case BFD_RELOC_ARC_TLS_LE_32:
2848 if (fixP->fx_done)
2849 break;
2850 /* Fall through. */
2851 case BFD_RELOC_ARC_TLS_GD_GOT:
2852 case BFD_RELOC_ARC_TLS_IE_GOT:
2853 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2854 break;
886a2506 2855
4670103e
CZ		 2856 case BFD_RELOC_ARC_TLS_GD_LD:
2857 gas_assert (!fixP->fx_offset);
2858 if (fixP->fx_subsy)
2859 fixP->fx_offset
2860 = (S_GET_VALUE (fixP->fx_subsy)
2861 - fixP->fx_frag->fr_address- fixP->fx_where);
2862 fixP->fx_subsy = NULL;
2863 /* Fall through. */
2864 case BFD_RELOC_ARC_TLS_GD_CALL:
2865 /* These two relocs are there just to allow ld to change the tls
2866 model for this symbol, by patching the code. The offset -
2867 and scale, if any - will be installed by the linker. */
2868 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2869 break;
886a2506 2870
4670103e
CZ		 2871 case BFD_RELOC_ARC_TLS_LE_S9:
2872 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2873 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2874 break;
2875
2876 default:
2877 break;
886a2506
NC		 2878 }
2879
4670103e 2880 if (!fixP->fx_done)
886a2506 2881 {
4670103e 2882 return;
886a2506 2883 }
886a2506 2884
4670103e
CZ		 2885 /* Addjust the value if we have a constant. */
2886 value += fx_offset;
886a2506 2887
4670103e
CZ		 2888 /* For hosts with longs bigger than 32-bits make sure that the top
2889 bits of a 32-bit negative value read in by the parser are set,
2890 so that the correct comparisons are made. */
2891 if (value & 0x80000000)
69c9e028 2892 value |= (-1UL << 31);
886a2506 2893
4670103e
CZ		 2894 reloc = fixP->fx_r_type;
2895 switch (reloc)
2896 {
2897 case BFD_RELOC_8:
2898 case BFD_RELOC_16:
2899 case BFD_RELOC_24:
2900 case BFD_RELOC_32:
2901 case BFD_RELOC_64:
2902 case BFD_RELOC_ARC_32_PCREL:
2903 md_number_to_chars (fixpos, value, fixP->fx_size);
2904 return;
886a2506 2905
4670103e
CZ		 2906 case BFD_RELOC_ARC_GOTPC32:
2907 /* I cannot fix an GOTPC relocation because I need to relax it
2908 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2909 as_bad (_("Unsupported operation on reloc"));
2910 return;
886a2506 2911
4670103e
CZ		 2912 case BFD_RELOC_ARC_TLS_DTPOFF:
2913 case BFD_RELOC_ARC_TLS_LE_32:
2914 gas_assert (!fixP->fx_addsy);
2915 gas_assert (!fixP->fx_subsy);
1a0670f3 2916 /* Fall through. */
886a2506 2917
4670103e
CZ		 2918 case BFD_RELOC_ARC_GOTOFF:
2919 case BFD_RELOC_ARC_32_ME:
2920 case BFD_RELOC_ARC_PC32:
2921 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2922 return;
886a2506 2923
4670103e
CZ		 2924 case BFD_RELOC_ARC_PLT32:
2925 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2926 return;
886a2506 2927
4670103e
CZ		 2928 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2929 reloc = BFD_RELOC_ARC_S25W_PCREL;
2930 goto solve_plt;
886a2506 2931
4670103e
CZ		 2932 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2933 reloc = BFD_RELOC_ARC_S21H_PCREL;
2934 goto solve_plt;
886a2506 2935
4670103e
CZ		 2936 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2937 reloc = BFD_RELOC_ARC_S25W_PCREL;
2938 goto solve_plt;
886a2506 2939
4670103e
CZ		 2940 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2941 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 2942 /* Fall through. */
886a2506 2943
4670103e
CZ		 2944 case BFD_RELOC_ARC_S25W_PCREL:
2945 case BFD_RELOC_ARC_S21W_PCREL:
2946 case BFD_RELOC_ARC_S21H_PCREL:
2947 case BFD_RELOC_ARC_S25H_PCREL:
2948 case BFD_RELOC_ARC_S13_PCREL:
2949 solve_plt:
2950 operand = find_operand_for_reloc (reloc);
2951 gas_assert (operand);
886a2506
NC		 2952 break;
2953
2954 default:
4670103e
CZ		 2955 {
2956 if ((int) fixP->fx_r_type >= 0)
2957 as_fatal (_("unhandled relocation type %s"),
2958 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 2959
4670103e
CZ		 2960 /* The rest of these fixups needs to be completely resolved as
2961 constants. */
2962 if (fixP->fx_addsy != 0
2963 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
2964 as_bad_where (fixP->fx_file, fixP->fx_line,
2965 _("non-absolute expression in constant field"));
886a2506 2966
4670103e
CZ		 2967 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
2968 operand = &arc_operands[-(int) fixP->fx_r_type];
2969 break;
2970 }
2971 }
886a2506 2972
4670103e 2973 if (target_big_endian)
886a2506 2974 {
4670103e 2975 switch (fixP->fx_size)
886a2506 2976 {
4670103e
CZ		 2977 case 4:
2978 insn = bfd_getb32 (fixpos);
2979 break;
2980 case 2:
2981 insn = bfd_getb16 (fixpos);
2982 break;
2983 default:
2984 as_bad_where (fixP->fx_file, fixP->fx_line,
2985 _("unknown fixup size"));
2986 }
2987 }
2988 else
2989 {
2990 insn = 0;
2991 switch (fixP->fx_size)
2992 {
2993 case 4:
2994 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
2995 break;
2996 case 2:
2997 insn = bfd_getl16 (fixpos);
2998 break;
2999 default:
3000 as_bad_where (fixP->fx_file, fixP->fx_line,
3001 _("unknown fixup size"));
886a2506
NC		 3002 }
3003 }
886a2506 3004
4670103e
CZ		 3005 insn = insert_operand (insn, operand, (offsetT) value,
3006 fixP->fx_file, fixP->fx_line);
886a2506 3007
4670103e
CZ		 3008 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3009}
886a2506 3010
4670103e 3011/* Prepare machine-dependent frags for relaxation.
886a2506 3012
4670103e
CZ		 3013 Called just before relaxation starts. Any symbol that is now undefined
3014 will not become defined.
886a2506 3015
4670103e 3016 Return the correct fr_subtype in the frag.
886a2506 3017
4670103e
CZ		 3018 Return the initial "guess for fr_var" to caller. The guess for fr_var
3019 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3020 or fr_var contributes to our returned value.
886a2506 3021
4670103e
CZ		 3022 Although it may not be explicit in the frag, pretend
3023 fr_var starts with a value. */
886a2506 3024
4670103e
CZ		 3025int
3026md_estimate_size_before_relax (fragS *fragP,
3027 segT segment)
3028{
3029 int growth;
3030
3031 /* If the symbol is not located within the same section AND it's not
3032 an absolute section, use the maximum. OR if the symbol is a
3033 constant AND the insn is by nature not pc-rel, use the maximum.
3034 OR if the symbol is being equated against another symbol, use the
3035 maximum. OR if the symbol is weak use the maximum. */
3036 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3037 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3038 || (symbol_constant_p (fragP->fr_symbol)
3039 && !fragP->tc_frag_data.pcrel)
3040 || symbol_equated_p (fragP->fr_symbol)
3041 || S_IS_WEAK (fragP->fr_symbol))
3042 {
3043 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3044 ++fragP->fr_subtype;
3045 }
886a2506 3046
4670103e
CZ		 3047 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3048 fragP->fr_var = growth;
886a2506 3049
4670103e
CZ		 3050 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3051 fragP->fr_file, fragP->fr_line, growth);
886a2506 3052
4670103e
CZ		 3053 return growth;
3054}
886a2506 3055
4670103e
CZ		 3056/* Translate internal representation of relocation info to BFD target
3057 format. */
886a2506 3058
4670103e
CZ		 3059arelent *
3060tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3061 fixS *fixP)
3062{
3063 arelent *reloc;
3064 bfd_reloc_code_real_type code;
886a2506 3065
add39d23
TS		 3066 reloc = XNEW (arelent);
3067 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3068 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3069 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3070
4670103e
CZ		 3071 /* Make sure none of our internal relocations make it this far.
3072 They'd better have been fully resolved by this point. */
3073 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3074
4670103e 3075 code = fixP->fx_r_type;
886a2506 3076
4670103e
CZ		 3077 /* if we have something like add gp, pcl,
3078 _GLOBAL_OFFSET_TABLE_@gotpc. */
3079 if (code == BFD_RELOC_ARC_GOTPC32
3080 && GOT_symbol
3081 && fixP->fx_addsy == GOT_symbol)
3082 code = BFD_RELOC_ARC_GOTPC;
886a2506 3083
4670103e
CZ		 3084 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3085 if (reloc->howto == NULL)
886a2506 3086 {
4670103e
CZ		 3087 as_bad_where (fixP->fx_file, fixP->fx_line,
3088 _("cannot represent `%s' relocation in object file"),
3089 bfd_get_reloc_code_name (code));
3090 return NULL;
3091 }
886a2506 3092
4670103e
CZ		 3093 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3094 as_fatal (_("internal error? cannot generate `%s' relocation"),
3095 bfd_get_reloc_code_name (code));
886a2506 3096
4670103e 3097 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3098
05bbf016 3099 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3100
3101 return reloc;
886a2506
NC		 3102}
3103
4670103e
CZ		 3104/* Perform post-processing of machine-dependent frags after relaxation.
3105 Called after relaxation is finished.
3106 In: Address of frag.
3107 fr_type == rs_machine_dependent.
3108 fr_subtype is what the address relaxed to.
886a2506 3109
4670103e
CZ		 3110 Out: Any fixS:s and constants are set up. */
3111
3112void
3113md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3114 segT segment ATTRIBUTE_UNUSED,
3115 fragS *fragP)
886a2506 3116{
4670103e
CZ		 3117 const relax_typeS *table_entry;
3118 char *dest;
3119 const struct arc_opcode *opcode;
3120 struct arc_insn insn;
3121 int size, fix;
3122 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3123
4670103e
CZ		 3124 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3125 dest = fragP->fr_literal + fix;
3126 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3127
9e32d9ae
AB		 3128 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3129 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3130 fragP->fr_file, fragP->fr_line,
3131 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3132
4670103e
CZ		 3133 if (fragP->fr_subtype <= 0
3134 && fragP->fr_subtype >= arc_num_relax_opcodes)
3135 as_fatal (_("no relaxation found for this instruction."));
886a2506 3136
4670103e 3137 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3138
4670103e
CZ		 3139 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3140 relax_arg->nflg, &insn);
886a2506 3141
4670103e 3142 apply_fixups (&insn, fragP, fix);
886a2506 3143
91fdca6f 3144 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3145 gas_assert (table_entry->rlx_length == size);
3146 emit_insn0 (&insn, dest, TRUE);
886a2506 3147
4670103e
CZ		 3148 fragP->fr_fix += table_entry->rlx_length;
3149 fragP->fr_var = 0;
886a2506
NC		 3150}
3151
4670103e
CZ		 3152/* We have no need to default values of symbols. We could catch
3153 register names here, but that is handled by inserting them all in
3154 the symbol table to begin with. */
886a2506 3155
4670103e
CZ		 3156symbolS *
3157md_undefined_symbol (char *name)
886a2506 3158{
4670103e
CZ		 3159 /* The arc abi demands that a GOT[0] should be referencible as
3160 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3161 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3162 if (((*name == '_')
3163 && (*(name+1) == 'G')
3164 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
3165 || ((*name == '_')
3166 && (*(name+1) == 'D')
3167 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
886a2506 3168 {
4670103e
CZ		 3169 if (!GOT_symbol)
3170 {
3171 if (symbol_find (name))
3172 as_bad ("GOT already in symbol table");
3173
3174 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3175 (valueT) 0, &zero_address_frag);
3176 };
3177 return GOT_symbol;
886a2506 3178 }
4670103e 3179 return NULL;
886a2506
NC		 3180}
3181
4670103e
CZ		 3182/* Turn a string in input_line_pointer into a floating point constant
3183 of type type, and store the appropriate bytes in *litP. The number
3184 of LITTLENUMS emitted is stored in *sizeP. An error message is
3185 returned, or NULL on OK. */
886a2506 3186
6d4af3c2 3187const char *
4670103e 3188md_atof (int type, char *litP, int *sizeP)
886a2506 3189{
4670103e
CZ		 3190 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3191}
886a2506 3192
4670103e
CZ		 3193/* Called for any expression that can not be recognized. When the
3194 function is called, `input_line_pointer' will point to the start of
3195 the expression. */
886a2506 3196
4670103e
CZ		 3197void
3198md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3199{
3200 char *p = input_line_pointer;
3201 if (*p == '@')
886a2506 3202 {
4670103e
CZ		 3203 input_line_pointer++;
3204 expressionP->X_op = O_symbol;
3205 expression (expressionP);
3206 }
3207}
886a2506 3208
4670103e
CZ		 3209/* This function is called from the function 'expression', it attempts
3210 to parse special names (in our case register names). It fills in
3211 the expression with the identified register. It returns TRUE if
3212 it is a register and FALSE otherwise. */
886a2506 3213
4670103e
CZ		 3214bfd_boolean
3215arc_parse_name (const char *name,
3216 struct expressionS *e)
3217{
3218 struct symbol *sym;
886a2506 3219
4670103e
CZ		 3220 if (!assembling_insn)
3221 return FALSE;
886a2506 3222
08ec958f 3223 if (e->X_op == O_symbol)
4670103e 3224 return FALSE;
886a2506 3225
4670103e
CZ		 3226 sym = hash_find (arc_reg_hash, name);
3227 if (sym)
3228 {
3229 e->X_op = O_register;
3230 e->X_add_number = S_GET_VALUE (sym);
3231 return TRUE;
3232 }
db18dbab
GM		 3233
3234 sym = hash_find (arc_addrtype_hash, name);
3235 if (sym)
3236 {
3237 e->X_op = O_addrtype;
3238 e->X_add_number = S_GET_VALUE (sym);
3239 return TRUE;
3240 }
3241
4670103e
CZ		 3242 return FALSE;
3243}
886a2506 3244
4670103e
CZ		 3245/* md_parse_option
3246 Invocation line includes a switch not recognized by the base assembler.
3247 See if it's a processor-specific option.
886a2506 3248
4670103e 3249 New options (supported) are:
886a2506 3250
4670103e
CZ		 3251 -mcpu=<cpu name> Assemble for selected processor
3252 -EB/-mbig-endian Big-endian
3253 -EL/-mlittle-endian Little-endian
3254 -mrelax Enable relaxation
886a2506 3255
4670103e 3256 The following CPU names are recognized:
ce440d63 3257 arc600, arc700, arcem, archs, nps400. */
886a2506 3258
4670103e 3259int
17b9d67d 3260md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3261{
4670103e
CZ		 3262 switch (c)
3263 {
3264 case OPTION_ARC600:
3265 case OPTION_ARC601:
3266 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3267
4670103e
CZ		 3268 case OPTION_ARC700:
3269 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3270
4670103e
CZ		 3271 case OPTION_ARCEM:
3272 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3273
4670103e
CZ		 3274 case OPTION_ARCHS:
3275 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3276
4670103e
CZ		 3277 case OPTION_MCPU:
3278 {
bb65a718 3279 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3280 break;
3281 }
886a2506 3282
4670103e
CZ		 3283 case OPTION_EB:
3284 arc_target_format = "elf32-bigarc";
3285 byte_order = BIG_ENDIAN;
3286 break;
886a2506 3287
4670103e
CZ		 3288 case OPTION_EL:
3289 arc_target_format = "elf32-littlearc";
3290 byte_order = LITTLE_ENDIAN;
3291 break;
886a2506 3292
4670103e
CZ		 3293 case OPTION_CD:
3294 /* This option has an effect only on ARC EM. */
bb65a718
AB		 3295 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
3296 selected_cpu.features |= ARC_CD;
8ddf6b2a
CZ		 3297 else
3298 as_warn (_("Code density option invalid for selected CPU"));
4670103e 3299 break;
886a2506 3300
4670103e
CZ		 3301 case OPTION_RELAX:
3302 relaxation_state = 1;
3303 break;
886a2506 3304
bdd582db 3305 case OPTION_NPS400:
bb65a718 3306 selected_cpu.features |= ARC_NPS400;
ce440d63 3307 break;
bdd582db 3308
ce440d63 3309 case OPTION_SPFP:
bb65a718 3310 selected_cpu.features |= ARC_SPFP;
ce440d63
GM		 3311 break;
3312
3313 case OPTION_DPFP:
bb65a718 3314 selected_cpu.features |= ARC_DPFP;
ce440d63
GM		 3315 break;
3316
3317 case OPTION_FPUDA:
3318 /* This option has an effect only on ARC EM. */
bb65a718
AB		 3319 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
3320 selected_cpu.features |= ARC_FPUDA;
ce440d63
GM		 3321 else
3322 as_warn (_("FPUDA invalid for selected CPU"));
3323 break;
3324
3325 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3326 case OPTION_USER_MODE:
3327 case OPTION_LD_EXT_MASK:
3328 case OPTION_SWAP:
3329 case OPTION_NORM:
3330 case OPTION_BARREL_SHIFT:
3331 case OPTION_MIN_MAX:
3332 case OPTION_NO_MPY:
3333 case OPTION_EA:
3334 case OPTION_MUL64:
3335 case OPTION_SIMD:
4670103e
CZ		 3336 case OPTION_XMAC_D16:
3337 case OPTION_XMAC_24:
3338 case OPTION_DSP_PACKA:
3339 case OPTION_CRC:
3340 case OPTION_DVBF:
3341 case OPTION_TELEPHONY:
3342 case OPTION_XYMEMORY:
3343 case OPTION_LOCK:
3344 case OPTION_SWAPE:
3345 case OPTION_RTSC:
8ddf6b2a
CZ		 3346 break;
3347
4670103e
CZ		 3348 default:
3349 return 0;
3350 }
886a2506 3351
4670103e
CZ		 3352 return 1;
3353}
886a2506 3354
4670103e
CZ		 3355void
3356md_show_usage (FILE *stream)
3357{
3358 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3359
9004b6bd
AB		 3360 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
3361 "(default: %s)\n", TARGET_WITH_CPU);
bdd582db
GM		 3362 fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3363 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3364 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3365 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3366 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3367
3368 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
3369 fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n");
3370 fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n");
3371 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3372 "point\n\t\t\t instructions for ARC EM\n");
3373
4670103e
CZ		 3374 fprintf (stream,
3375 " -mcode-density\t enable code density option for ARC EM\n");
3376
3377 fprintf (stream, _("\
3378 -EB assemble code for a big-endian cpu\n"));
3379 fprintf (stream, _("\
3380 -EL assemble code for a little-endian cpu\n"));
3381 fprintf (stream, _("\
bdd582db
GM		 3382 -mrelax enable relaxation\n"));
3383
3384 fprintf (stream, _("The following ARC-specific assembler options are "
3385 "deprecated and are accepted\nfor compatibility only:\n"));
3386
3387 fprintf (stream, _(" -mEA\n"
3388 " -mbarrel-shifter\n"
3389 " -mbarrel_shifter\n"
3390 " -mcrc\n"
3391 " -mdsp-packa\n"
3392 " -mdsp_packa\n"
3393 " -mdvbf\n"
3394 " -mld-extension-reg-mask\n"
3395 " -mlock\n"
3396 " -mmac-24\n"
3397 " -mmac-d16\n"
3398 " -mmac_24\n"
3399 " -mmac_d16\n"
3400 " -mmin-max\n"
3401 " -mmin_max\n"
3402 " -mmul64\n"
3403 " -mno-mpy\n"
3404 " -mnorm\n"
3405 " -mrtsc\n"
3406 " -msimd\n"
3407 " -mswap\n"
3408 " -mswape\n"
3409 " -mtelephony\n"
3410 " -muser-mode-only\n"
3411 " -mxy\n"));
886a2506
NC		 3412}
3413
3414/* Find the proper relocation for the given opcode. */
3415
3416static extended_bfd_reloc_code_real_type
3417find_reloc (const char *name,
3418 const char *opcodename,
3419 const struct arc_flags *pflags,
3420 int nflg,
3421 extended_bfd_reloc_code_real_type reloc)
3422{
3423 unsigned int i;
3424 int j;
24b368f8 3425 bfd_boolean found_flag, tmp;
886a2506
NC		 3426 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3427
3428 for (i = 0; i < arc_num_equiv_tab; i++)
3429 {
3430 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3431
3432 /* Find the entry. */
3433 if (strcmp (name, r->name))
3434 continue;
3435 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3436 continue;
24b368f8 3437 if (r->flags[0])
886a2506
NC		 3438 {
3439 if (!nflg)
3440 continue;
3441 found_flag = FALSE;
24b368f8
CZ		 3442 unsigned * psflg = (unsigned *)r->flags;
3443 do
3444 {
3445 tmp = FALSE;
3446 for (j = 0; j < nflg; j++)
3447 if (!strcmp (pflags[j].name,
3448 arc_flag_operands[*psflg].name))
3449 {
3450 tmp = TRUE;
3451 break;
3452 }
3453 if (!tmp)
3454 {
3455 found_flag = FALSE;
3456 break;
3457 }
3458 else
3459 {
3460 found_flag = TRUE;
3461 }
3462 ++ psflg;
3463 } while (*psflg);
3464
886a2506
NC		 3465 if (!found_flag)
3466 continue;
3467 }
3468
3469 if (reloc != r->oldreloc)
3470 continue;
3471 /* Found it. */
3472 ret = r->newreloc;
3473 break;
3474 }
3475
3476 if (ret == BFD_RELOC_UNUSED)
3477 as_bad (_("Unable to find %s relocation for instruction %s"),
3478 name, opcodename);
3479 return ret;
3480}
3481
4670103e
CZ		 3482/* All the symbol types that are allowed to be used for
3483 relaxation. */
3484
3485static bfd_boolean
3486may_relax_expr (expressionS tok)
3487{
3488 /* Check if we have unrelaxable relocs. */
3489 switch (tok.X_md)
3490 {
3491 default:
3492 break;
3493 case O_plt:
3494 return FALSE;
3495 }
3496
3497 switch (tok.X_op)
3498 {
3499 case O_symbol:
3500 case O_multiply:
3501 case O_divide:
3502 case O_modulus:
3503 case O_add:
3504 case O_subtract:
3505 break;
3506
3507 default:
3508 return FALSE;
3509 }
3510 return TRUE;
3511}
3512
3513/* Checks if flags are in line with relaxable insn. */
3514
3515static bfd_boolean
3516relaxable_flag (const struct arc_relaxable_ins *ins,
3517 const struct arc_flags *pflags,
3518 int nflgs)
3519{
3520 unsigned flag_class,
3521 flag,
3522 flag_class_idx = 0,
3523 flag_idx = 0;
3524
3525 const struct arc_flag_operand *flag_opand;
3526 int i, counttrue = 0;
3527
3528 /* Iterate through flags classes. */
3529 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3530 {
3531 /* Iterate through flags in flag class. */
3532 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3533 != 0)
3534 {
3535 flag_opand = &arc_flag_operands[flag];
3536 /* Iterate through flags in ins to compare. */
3537 for (i = 0; i < nflgs; ++i)
3538 {
3539 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3540 ++counttrue;
3541 }
3542
3543 ++flag_idx;
3544 }
3545
3546 ++flag_class_idx;
3547 flag_idx = 0;
3548 }
3549
3550 /* If counttrue == nflgs, then all flags have been found. */
3551 return (counttrue == nflgs ? TRUE : FALSE);
3552}
3553
3554/* Checks if operands are in line with relaxable insn. */
3555
3556static bfd_boolean
3557relaxable_operand (const struct arc_relaxable_ins *ins,
3558 const expressionS *tok,
3559 int ntok)
3560{
3561 const enum rlx_operand_type *operand = &ins->operands[0];
3562 int i = 0;
3563
3564 while (*operand != EMPTY)
3565 {
3566 const expressionS *epr = &tok[i];
3567
3568 if (i != 0 && i >= ntok)
3569 return FALSE;
3570
3571 switch (*operand)
3572 {
3573 case IMMEDIATE:
3574 if (!(epr->X_op == O_multiply
3575 || epr->X_op == O_divide
3576 || epr->X_op == O_modulus
3577 || epr->X_op == O_add
3578 || epr->X_op == O_subtract
3579 || epr->X_op == O_symbol))
3580 return FALSE;
3581 break;
3582
3583 case REGISTER_DUP:
3584 if ((i <= 0)
3585 || (epr->X_add_number != tok[i - 1].X_add_number))
3586 return FALSE;
3587 /* Fall through. */
3588 case REGISTER:
3589 if (epr->X_op != O_register)
3590 return FALSE;
3591 break;
3592
3593 case REGISTER_S:
3594 if (epr->X_op != O_register)
3595 return FALSE;
3596
3597 switch (epr->X_add_number)
3598 {
3599 case 0: case 1: case 2: case 3:
3600 case 12: case 13: case 14: case 15:
3601 break;
3602 default:
3603 return FALSE;
3604 }
3605 break;
3606
3607 case REGISTER_NO_GP:
3608 if ((epr->X_op != O_register)
3609 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3610 return FALSE;
3611 break;
3612
3613 case BRACKET:
3614 if (epr->X_op != O_bracket)
3615 return FALSE;
3616 break;
3617
3618 default:
3619 /* Don't understand, bail out. */
3620 return FALSE;
3621 break;
3622 }
3623
3624 ++i;
3625 operand = &ins->operands[i];
3626 }
3627
3628 return (i == ntok ? TRUE : FALSE);
3629}
3630
3631/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3632
3633static bfd_boolean
3634relax_insn_p (const struct arc_opcode *opcode,
3635 const expressionS *tok,
3636 int ntok,
3637 const struct arc_flags *pflags,
3638 int nflg)
3639{
3640 unsigned i;
3641 bfd_boolean rv = FALSE;
3642
3643 /* Check the relaxation table. */
3644 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3645 {
3646 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3647
3648 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3649 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3650 && relaxable_operand (arc_rlx_ins, tok, ntok)
3651 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3652 {
3653 rv = TRUE;
3654 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3655 memcpy (&frag_now->tc_frag_data.tok, tok,
3656 sizeof (expressionS) * ntok);
3657 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3658 sizeof (struct arc_flags) * nflg);
3659 frag_now->tc_frag_data.nflg = nflg;
3660 frag_now->tc_frag_data.ntok = ntok;
3661 break;
3662 }
3663 }
3664
3665 return rv;
3666}
3667
886a2506
NC		 3668/* Turn an opcode description and a set of arguments into
3669 an instruction and a fixup. */
3670
3671static void
3672assemble_insn (const struct arc_opcode *opcode,
3673 const expressionS *tok,
3674 int ntok,
3675 const struct arc_flags *pflags,
3676 int nflg,
3677 struct arc_insn *insn)
3678{
3679 const expressionS *reloc_exp = NULL;
bdfe53e3 3680 unsigned long long image;
886a2506
NC		 3681 const unsigned char *argidx;
3682 int i;
3683 int tokidx = 0;
3684 unsigned char pcrel = 0;
3685 bfd_boolean needGOTSymbol;
3686 bfd_boolean has_delay_slot = FALSE;
3687 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3688
3689 memset (insn, 0, sizeof (*insn));
3690 image = opcode->opcode;
3691
bdfe53e3 3692 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3693 frag_now->fr_file, frag_now->fr_line, opcode->name,
3694 opcode->opcode);
3695
3696 /* Handle operands. */
3697 for (argidx = opcode->operands; *argidx; ++argidx)
3698 {
3699 const struct arc_operand *operand = &arc_operands[*argidx];
3700 const expressionS *t = (const expressionS *) 0;
3701
db18dbab 3702 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3703 continue;
3704
3705 if (operand->flags & ARC_OPERAND_DUPLICATE)
3706 {
3707 /* Duplicate operand, already inserted. */
3708 tokidx ++;
3709 continue;
3710 }
3711
3712 if (tokidx >= ntok)
3713 {
3714 abort ();
3715 }
3716 else
3717 t = &tok[tokidx++];
3718
3719 /* Regardless if we have a reloc or not mark the instruction
3720 limm if it is the case. */
3721 if (operand->flags & ARC_OPERAND_LIMM)
3722 insn->has_limm = TRUE;
3723
3724 switch (t->X_op)
3725 {
3726 case O_register:
3727 image = insert_operand (image, operand, regno (t->X_add_number),
3728 NULL, 0);
3729 break;
3730
3731 case O_constant:
3732 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3733 reloc_exp = t;
3734 if (operand->flags & ARC_OPERAND_LIMM)
3735 insn->limm = t->X_add_number;
3736 break;
3737
3738 case O_bracket:
db18dbab
GM		 3739 case O_colon:
3740 case O_addrtype:
3741 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3742 break;
3743
3744 case O_absent:
3745 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3746 break;
3747
3748 case O_subtract:
3749 /* Maybe register range. */
3750 if ((t->X_add_number == 0)
3751 && contains_register (t->X_add_symbol)
3752 && contains_register (t->X_op_symbol))
3753 {
3754 int regs;
3755
3756 regs = get_register (t->X_add_symbol);
3757 regs <<= 16;
3758 regs |= get_register (t->X_op_symbol);
3759 image = insert_operand (image, operand, regs, NULL, 0);
3760 break;
3761 }
1a0670f3 3762 /* Fall through. */
886a2506
NC		 3763
3764 default:
3765 /* This operand needs a relocation. */
3766 needGOTSymbol = FALSE;
3767
3768 switch (t->X_md)
3769 {
3770 case O_plt:
c810e0b8 3771 if (opcode->insn_class == JUMP)
6ec1f282
CZ		 3772 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3773 _("Unable to use @plt relocatio for insn %s"),
3774 opcode->name);
886a2506
NC		 3775 needGOTSymbol = TRUE;
3776 reloc = find_reloc ("plt", opcode->name,
3777 pflags, nflg,
3778 operand->default_reloc);
3779 break;
3780
3781 case O_gotoff:
3782 case O_gotpc:
3783 needGOTSymbol = TRUE;
3784 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3785 break;
3786 case O_pcl:
3787 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
06fe285f
GM		 3788 if (arc_opcode_len (opcode) == 2
3789 || opcode->insn_class == JUMP)
886a2506
NC		 3790 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3791 _("Unable to use @pcl relocation for insn %s"),
3792 opcode->name);
3793 break;
3794 case O_sda:
3795 reloc = find_reloc ("sda", opcode->name,
3796 pflags, nflg,
3797 operand->default_reloc);
3798 break;
3799 case O_tlsgd:
3800 case O_tlsie:
3801 needGOTSymbol = TRUE;
3802 /* Fall-through. */
3803
3804 case O_tpoff:
3805 case O_dtpoff:
3806 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3807 break;
3808
3809 case O_tpoff9: /*FIXME! Check for the conditionality of
3810 the insn. */
3811 case O_dtpoff9: /*FIXME! Check for the conditionality of
3812 the insn. */
3813 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3814 break;
3815
3816 default:
3817 /* Just consider the default relocation. */
3818 reloc = operand->default_reloc;
3819 break;
3820 }
3821
3822 if (needGOTSymbol && (GOT_symbol == NULL))
3823 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3824
3825 reloc_exp = t;
3826
3827#if 0
3828 if (reloc > 0)
3829 {
3830 /* sanity checks. */
3831 reloc_howto_type *reloc_howto
3832 = bfd_reloc_type_lookup (stdoutput,
3833 (bfd_reloc_code_real_type) reloc);
3834 unsigned reloc_bitsize = reloc_howto->bitsize;
3835 if (reloc_howto->rightshift)
3836 reloc_bitsize -= reloc_howto->rightshift;
3837 if (reloc_bitsize != operand->bits)
3838 {
3839 as_bad (_("invalid relocation %s for field"),
3840 bfd_get_reloc_code_name (reloc));
3841 return;
3842 }
3843 }
3844#endif
3845 if (insn->nfixups >= MAX_INSN_FIXUPS)
3846 as_fatal (_("too many fixups"));
3847
3848 struct arc_fixup *fixup;
3849 fixup = &insn->fixups[insn->nfixups++];
3850 fixup->exp = *t;
3851 fixup->reloc = reloc;
3852 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3853 fixup->pcrel = pcrel;
3854 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3855 TRUE : FALSE;
3856 break;
3857 }
3858 }
3859
3860 /* Handle flags. */
3861 for (i = 0; i < nflg; i++)
3862 {
f36e33da 3863 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 3864
3865 /* Check if the instruction has a delay slot. */
3866 if (!strcmp (flg_operand->name, "d"))
3867 has_delay_slot = TRUE;
3868
3869 /* There is an exceptional case when we cannot insert a flag
3870 just as it is. The .T flag must be handled in relation with
3871 the relative address. */
3872 if (!strcmp (flg_operand->name, "t")
3873 || !strcmp (flg_operand->name, "nt"))
3874 {
3875 unsigned bitYoperand = 0;
3876 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3877 if (!strcmp (flg_operand->name, "t"))
3878 if (!strcmp (opcode->name, "bbit0")
3879 || !strcmp (opcode->name, "bbit1"))
3880 bitYoperand = arc_NToperand;
3881 else
3882 bitYoperand = arc_Toperand;
3883 else
3884 if (!strcmp (opcode->name, "bbit0")
3885 || !strcmp (opcode->name, "bbit1"))
3886 bitYoperand = arc_Toperand;
3887 else
3888 bitYoperand = arc_NToperand;
3889
3890 gas_assert (reloc_exp != NULL);
3891 if (reloc_exp->X_op == O_constant)
3892 {
3893 /* Check if we have a constant and solved it
3894 immediately. */
3895 offsetT val = reloc_exp->X_add_number;
3896 image |= insert_operand (image, &arc_operands[bitYoperand],
3897 val, NULL, 0);
3898 }
3899 else
3900 {
3901 struct arc_fixup *fixup;
3902
3903 if (insn->nfixups >= MAX_INSN_FIXUPS)
3904 as_fatal (_("too many fixups"));
3905
3906 fixup = &insn->fixups[insn->nfixups++];
3907 fixup->exp = *reloc_exp;
3908 fixup->reloc = -bitYoperand;
3909 fixup->pcrel = pcrel;
3910 fixup->islong = FALSE;
3911 }
3912 }
3913 else
3914 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
3915 << flg_operand->shift;
3916 }
3917
4670103e
CZ		 3918 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
3919
91fdca6f 3920 /* Instruction length. */
06fe285f 3921 insn->len = arc_opcode_len (opcode);
886a2506
NC		 3922
3923 insn->insn = image;
3924
3925 /* Update last insn status. */
3926 arc_last_insns[1] = arc_last_insns[0];
3927 arc_last_insns[0].opcode = opcode;
3928 arc_last_insns[0].has_limm = insn->has_limm;
3929 arc_last_insns[0].has_delay_slot = has_delay_slot;
3930
3931 /* Check if the current instruction is legally used. */
3932 if (arc_last_insns[1].has_delay_slot
3933 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3934 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3935 _("A jump/branch instruction in delay slot."));
3936}
3937
886a2506
NC		 3938void
3939arc_handle_align (fragS* fragP)
3940{
3941 if ((fragP)->fr_type == rs_align_code)
3942 {
3943 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
3944 valueT count = ((fragP)->fr_next->fr_address
3945 - (fragP)->fr_address - (fragP)->fr_fix);
3946
3947 (fragP)->fr_var = 2;
3948
3949 if (count & 1)/* Padding in the gap till the next 2-byte
3950 boundary with 0s. */
3951 {
3952 (fragP)->fr_fix++;
3953 *dest++ = 0;
3954 }
3955 /* Writing nop_s. */
3956 md_number_to_chars (dest, NOP_OPCODE_S, 2);
3957 }
3958}
3959
3960/* Here we decide which fixups can be adjusted to make them relative
3961 to the beginning of the section instead of the symbol. Basically
3962 we need to make sure that the dynamic relocations are done
3963 correctly, so in some cases we force the original symbol to be
3964 used. */
3965
3966int
3967tc_arc_fix_adjustable (fixS *fixP)
3968{
3969
3970 /* Prevent all adjustments to global symbols. */
3971 if (S_IS_EXTERNAL (fixP->fx_addsy))
3972 return 0;
3973 if (S_IS_WEAK (fixP->fx_addsy))
3974 return 0;
3975
3976 /* Adjust_reloc_syms doesn't know about the GOT. */
3977 switch (fixP->fx_r_type)
3978 {
3979 case BFD_RELOC_ARC_GOTPC32:
3980 case BFD_RELOC_ARC_PLT32:
3981 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3982 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3983 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3984 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3985 return 0;
3986
3987 default:
3988 break;
3989 }
3990
841fdfcd 3991 return 1;
886a2506
NC		 3992}
3993
3994/* Compute the reloc type of an expression EXP. */
3995
3996static void
3997arc_check_reloc (expressionS *exp,
3998 bfd_reloc_code_real_type *r_type_p)
3999{
4000 if (*r_type_p == BFD_RELOC_32
4001 && exp->X_op == O_subtract
4002 && exp->X_op_symbol != NULL
4003 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 4004 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4005}
4006
4007
4008/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4009
4010void
4011arc_cons_fix_new (fragS *frag,
4012 int off,
4013 int size,
4014 expressionS *exp,
4015 bfd_reloc_code_real_type r_type)
4016{
4017 r_type = BFD_RELOC_UNUSED;
4018
4019 switch (size)
4020 {
4021 case 1:
4022 r_type = BFD_RELOC_8;
4023 break;
4024
4025 case 2:
4026 r_type = BFD_RELOC_16;
4027 break;
4028
4029 case 3:
4030 r_type = BFD_RELOC_24;
4031 break;
4032
4033 case 4:
4034 r_type = BFD_RELOC_32;
4035 arc_check_reloc (exp, &r_type);
4036 break;
4037
4038 case 8:
4039 r_type = BFD_RELOC_64;
4040 break;
4041
4042 default:
4043 as_bad (_("unsupported BFD relocation size %u"), size);
4044 r_type = BFD_RELOC_UNUSED;
4045 }
4046
4047 fix_new_exp (frag, off, size, exp, 0, r_type);
4048}
4049
4050/* The actual routine that checks the ZOL conditions. */
4051
4052static void
4053check_zol (symbolS *s)
4054{
bb65a718 4055 switch (selected_cpu.mach)
886a2506
NC		 4056 {
4057 case bfd_mach_arc_arcv2:
bb65a718 4058 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4059 return;
4060
4061 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4062 || arc_last_insns[1].has_delay_slot)
4063 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4064 S_GET_NAME (s));
4065
4066 break;
4067 case bfd_mach_arc_arc600:
4068
4069 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4070 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4071 S_GET_NAME (s));
4072
4073 if (arc_last_insns[0].has_limm
4074 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4075 as_bad (_("A jump instruction with long immediate detected at the \
4076end of the ZOL label @%s"), S_GET_NAME (s));
4077
4078 /* Fall through. */
4079 case bfd_mach_arc_arc700:
4080 if (arc_last_insns[0].has_delay_slot)
4081 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4082 S_GET_NAME (s));
4083
4084 break;
4085 default:
4086 break;
4087 }
4088}
4089
4090/* If ZOL end check the last two instruction for illegals. */
4091void
4092arc_frob_label (symbolS * sym)
4093{
4094 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4095 check_zol (sym);
4096
4097 dwarf2_emit_label (sym);
ea1562b3 4098}
4670103e
CZ		 4099
4100/* Used because generic relaxation assumes a pc-rel value whilst we
4101 also relax instructions that use an absolute value resolved out of
4102 relative values (if that makes any sense). An example: 'add r1,
4103 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4104 but if they're in the same section we can subtract the section
4105 offset relocation which ends up in a resolved value. So if @.L2 is
4106 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4107 .text + 0x40 = 0x10. */
4108int
4109arc_pcrel_adjust (fragS *fragP)
4110{
4111 if (!fragP->tc_frag_data.pcrel)
4112 return fragP->fr_address + fragP->fr_fix;
4113
4114 return 0;
4115}
726c18e1
CZ		 4116
4117/* Initialize the DWARF-2 unwind information for this procedure. */
4118
4119void
4120tc_arc_frame_initial_instructions (void)
4121{
4122 /* Stack pointer is register 28. */
45a54ee5 4123 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4124}
4125
4126int
4127tc_arc_regname_to_dw2regnum (char *regname)
4128{
4129 struct symbol *sym;
4130
4131 sym = hash_find (arc_reg_hash, regname);
4132 if (sym)
4133 return S_GET_VALUE (sym);
4134
4135 return -1;
4136}
37ab9779
CZ		 4137
4138/* Adjust the symbol table. Delete found AUX register symbols. */
4139
4140void
4141arc_adjust_symtab (void)
4142{
4143 symbolS * sym;
4144
4145 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4146 {
4147 /* I've created a symbol during parsing process. Now, remove
4148 the symbol as it is found to be an AUX register. */
4149 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4150 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4151 }
4152
4153 /* Now do generic ELF adjustments. */
4154 elf_adjust_symtab ();
4155}
b99747ae
CZ		 4156
4157static void
4158tokenize_extinsn (extInstruction_t *einsn)
4159{
4160 char *p, c;
4161 char *insn_name;
4162 unsigned char major_opcode;
4163 unsigned char sub_opcode;
4164 unsigned char syntax_class = 0;
4165 unsigned char syntax_class_modifiers = 0;
4166 unsigned char suffix_class = 0;
4167 unsigned int i;
4168
4169 SKIP_WHITESPACE ();
4170
4171 /* 1st: get instruction name. */
4172 p = input_line_pointer;
4173 c = get_symbol_name (&p);
4174
4175 insn_name = xstrdup (p);
4176 restore_line_pointer (c);
4177
4178 /* 2nd: get major opcode. */
4179 if (*input_line_pointer != ',')
4180 {
4181 as_bad (_("expected comma after instruction name"));
4182 ignore_rest_of_line ();
4183 return;
4184 }
4185 input_line_pointer++;
4186 major_opcode = get_absolute_expression ();
4187
4188 /* 3rd: get sub-opcode. */
4189 SKIP_WHITESPACE ();
4190
4191 if (*input_line_pointer != ',')
4192 {
4193 as_bad (_("expected comma after major opcode"));
4194 ignore_rest_of_line ();
4195 return;
4196 }
4197 input_line_pointer++;
4198 sub_opcode = get_absolute_expression ();
4199
4200 /* 4th: get suffix class. */
4201 SKIP_WHITESPACE ();
4202
4203 if (*input_line_pointer != ',')
4204 {
4205 as_bad ("expected comma after sub opcode");
4206 ignore_rest_of_line ();
4207 return;
4208 }
4209 input_line_pointer++;
4210
4211 while (1)
4212 {
4213 SKIP_WHITESPACE ();
4214
4215 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4216 {
4217 if (!strncmp (suffixclass[i].name, input_line_pointer,
4218 suffixclass[i].len))
4219 {
c810e0b8 4220 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4221 input_line_pointer += suffixclass[i].len;
4222 break;
4223 }
4224 }
4225
4226 if (i == ARRAY_SIZE (suffixclass))
4227 {
4228 as_bad ("invalid suffix class");
4229 ignore_rest_of_line ();
4230 return;
4231 }
4232
4233 SKIP_WHITESPACE ();
4234
4235 if (*input_line_pointer == '|')
4236 input_line_pointer++;
4237 else
4238 break;
4239 }
4240
4241 /* 5th: get syntax class and syntax class modifiers. */
4242 if (*input_line_pointer != ',')
4243 {
4244 as_bad ("expected comma after suffix class");
4245 ignore_rest_of_line ();
4246 return;
4247 }
4248 input_line_pointer++;
4249
4250 while (1)
4251 {
4252 SKIP_WHITESPACE ();
4253
4254 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4255 {
4256 if (!strncmp (syntaxclassmod[i].name,
4257 input_line_pointer,
4258 syntaxclassmod[i].len))
4259 {
c810e0b8 4260 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4261 input_line_pointer += syntaxclassmod[i].len;
4262 break;
4263 }
4264 }
4265
4266 if (i == ARRAY_SIZE (syntaxclassmod))
4267 {
4268 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4269 {
4270 if (!strncmp (syntaxclass[i].name,
4271 input_line_pointer,
4272 syntaxclass[i].len))
4273 {
c810e0b8 4274 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4275 input_line_pointer += syntaxclass[i].len;
4276 break;
4277 }
4278 }
4279
4280 if (i == ARRAY_SIZE (syntaxclass))
4281 {
4282 as_bad ("missing syntax class");
4283 ignore_rest_of_line ();
4284 return;
4285 }
4286 }
4287
4288 SKIP_WHITESPACE ();
4289
4290 if (*input_line_pointer == '|')
4291 input_line_pointer++;
4292 else
4293 break;
4294 }
4295
4296 demand_empty_rest_of_line ();
4297
4298 einsn->name = insn_name;
4299 einsn->major = major_opcode;
4300 einsn->minor = sub_opcode;
4301 einsn->syntax = syntax_class;
4302 einsn->modsyn = syntax_class_modifiers;
4303 einsn->suffix = suffix_class;
4304 einsn->flags = syntax_class
4305 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4306}
4307
4308/* Generate an extension section. */
4309
4310static int
4311arc_set_ext_seg (void)
4312{
4313 if (!arcext_section)
4314 {
4315 arcext_section = subseg_new (".arcextmap", 0);
4316 bfd_set_section_flags (stdoutput, arcext_section,
4317 SEC_READONLY | SEC_HAS_CONTENTS);
4318 }
4319 else
4320 subseg_set (arcext_section, 0);
4321 return 1;
4322}
4323
4324/* Create an extension instruction description in the arc extension
4325 section of the output file.
4326 The structure for an instruction is like this:
4327 [0]: Length of the record.
4328 [1]: Type of the record.
4329
4330 [2]: Major opcode.
4331 [3]: Sub-opcode.
4332 [4]: Syntax (flags).
4333 [5]+ Name instruction.
4334
4335 The sequence is terminated by an empty entry. */
4336
4337static void
4338create_extinst_section (extInstruction_t *einsn)
4339{
4340
4341 segT old_sec = now_seg;
4342 int old_subsec = now_subseg;
4343 char *p;
4344 int name_len = strlen (einsn->name);
4345
4346 arc_set_ext_seg ();
4347
4348 p = frag_more (1);
4349 *p = 5 + name_len + 1;
4350 p = frag_more (1);
4351 *p = EXT_INSTRUCTION;
4352 p = frag_more (1);
4353 *p = einsn->major;
4354 p = frag_more (1);
4355 *p = einsn->minor;
4356 p = frag_more (1);
4357 *p = einsn->flags;
4358 p = frag_more (name_len + 1);
4359 strcpy (p, einsn->name);
4360
4361 subseg_set (old_sec, old_subsec);
4362}
4363
4364/* Handler .extinstruction pseudo-op. */
4365
4366static void
4367arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4368{
4369 extInstruction_t einsn;
4370 struct arc_opcode *arc_ext_opcodes;
4371 const char *errmsg = NULL;
4372 unsigned char moplow, mophigh;
4373
4374 memset (&einsn, 0, sizeof (einsn));
4375 tokenize_extinsn (&einsn);
4376
4377 /* Check if the name is already used. */
4378 if (arc_find_opcode (einsn.name))
4379 as_warn (_("Pseudocode already used %s"), einsn.name);
4380
4381 /* Check the opcode ranges. */
4382 moplow = 0x05;
bb65a718
AB		 4383 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4384 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4385
4386 if ((einsn.major > mophigh) || (einsn.major < moplow))
4387 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4388
4389 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4390 && (einsn.major != 5) && (einsn.major != 9))
4391 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4392
945e0f82 4393 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4394 {
4395 case ARC_SYNTAX_3OP:
4396 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4397 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4398 break;
4399 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4400 case ARC_SYNTAX_1OP:
4401 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4402 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4403 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4404 break;
4405 default:
4406 break;
4407 }
4408
bb65a718 4409 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4410 if (arc_ext_opcodes == NULL)
4411 {
4412 if (errmsg)
4413 as_fatal ("%s", errmsg);
4414 else
4415 as_fatal (_("Couldn't generate extension instruction opcodes"));
4416 }
4417 else if (errmsg)
4418 as_warn ("%s", errmsg);
4419
4420 /* Insert the extension instruction. */
4421 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4422
4423 create_extinst_section (&einsn);
4424}
4425
f36e33da
CZ		 4426static void
4427tokenize_extregister (extRegister_t *ereg, int opertype)
4428{
4429 char *name;
4430 char *mode;
4431 char c;
4432 char *p;
4433 int number, imode = 0;
4434 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4435 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4436 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4437
4438 /* 1st: get register name. */
4439 SKIP_WHITESPACE ();
4440 p = input_line_pointer;
4441 c = get_symbol_name (&p);
4442
4443 name = xstrdup (p);
4444 restore_line_pointer (c);
4445
4446 /* 2nd: get register number. */
4447 SKIP_WHITESPACE ();
4448
4449 if (*input_line_pointer != ',')
4450 {
4451 as_bad (_("expected comma after register name"));
4452 ignore_rest_of_line ();
4453 free (name);
4454 return;
4455 }
4456 input_line_pointer++;
4457 number = get_absolute_expression ();
4458
4459 if (number < 0)
4460 {
4461 as_bad (_("negative operand number %d"), number);
4462 ignore_rest_of_line ();
4463 free (name);
4464 return;
4465 }
4466
4467 if (isReg_p)
4468 {
4469 /* 3rd: get register mode. */
4470 SKIP_WHITESPACE ();
4471
4472 if (*input_line_pointer != ',')
4473 {
4474 as_bad (_("expected comma after register number"));
4475 ignore_rest_of_line ();
4476 free (name);
4477 return;
4478 }
4479
4480 input_line_pointer++;
4481 mode = input_line_pointer;
4482
4483 if (!strncmp (mode, "r|w", 3))
4484 {
4485 imode = 0;
4486 input_line_pointer += 3;
4487 }
4488 else if (!strncmp (mode, "r", 1))
4489 {
4490 imode = ARC_REGISTER_READONLY;
4491 input_line_pointer += 1;
4492 }
4493 else if (strncmp (mode, "w", 1))
4494 {
4495 as_bad (_("invalid mode"));
4496 ignore_rest_of_line ();
4497 free (name);
4498 return;
4499 }
4500 else
4501 {
4502 imode = ARC_REGISTER_WRITEONLY;
4503 input_line_pointer += 1;
4504 }
4505 }
4506
4507 if (isCore_p)
4508 {
4509 /* 4th: get core register shortcut. */
4510 SKIP_WHITESPACE ();
4511 if (*input_line_pointer != ',')
4512 {
4513 as_bad (_("expected comma after register mode"));
4514 ignore_rest_of_line ();
4515 free (name);
4516 return;
4517 }
4518
4519 input_line_pointer++;
4520
4521 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4522 {
4523 imode |= ARC_REGISTER_NOSHORT_CUT;
4524 input_line_pointer += 15;
4525 }
4526 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4527 {
4528 as_bad (_("shortcut designator invalid"));
4529 ignore_rest_of_line ();
4530 free (name);
4531 return;
4532 }
4533 else
4534 {
4535 input_line_pointer += 12;
4536 }
4537 }
4538 demand_empty_rest_of_line ();
4539
4540 ereg->name = name;
4541 ereg->number = number;
4542 ereg->imode = imode;
4543}
4544
4545/* Create an extension register/condition description in the arc
4546 extension section of the output file.
4547
4548 The structure for an instruction is like this:
4549 [0]: Length of the record.
4550 [1]: Type of the record.
4551
4552 For core regs and condition codes:
4553 [2]: Value.
4554 [3]+ Name.
4555
4556 For auxilirary registers:
4557 [2..5]: Value.
4558 [6]+ Name
4559
4560 The sequence is terminated by an empty entry. */
4561
4562static void
4563create_extcore_section (extRegister_t *ereg, int opertype)
4564{
4565 segT old_sec = now_seg;
4566 int old_subsec = now_subseg;
4567 char *p;
4568 int name_len = strlen (ereg->name);
4569
4570 arc_set_ext_seg ();
4571
4572 switch (opertype)
4573 {
4574 case EXT_COND_CODE:
4575 case EXT_CORE_REGISTER:
4576 p = frag_more (1);
4577 *p = 3 + name_len + 1;
4578 p = frag_more (1);
4579 *p = opertype;
4580 p = frag_more (1);
4581 *p = ereg->number;
4582 break;
4583 case EXT_AUX_REGISTER:
4584 p = frag_more (1);
4585 *p = 6 + name_len + 1;
4586 p = frag_more (1);
4587 *p = EXT_AUX_REGISTER;
4588 p = frag_more (1);
4589 *p = (ereg->number >> 24) & 0xff;
4590 p = frag_more (1);
4591 *p = (ereg->number >> 16) & 0xff;
4592 p = frag_more (1);
4593 *p = (ereg->number >> 8) & 0xff;
4594 p = frag_more (1);
4595 *p = (ereg->number) & 0xff;
4596 break;
4597 default:
4598 break;
4599 }
4600
4601 p = frag_more (name_len + 1);
4602 strcpy (p, ereg->name);
4603
4604 subseg_set (old_sec, old_subsec);
4605}
4606
4607/* Handler .extCoreRegister pseudo-op. */
4608
4609static void
4610arc_extcorereg (int opertype)
4611{
4612 extRegister_t ereg;
4613 struct arc_aux_reg *auxr;
4614 const char *retval;
4615 struct arc_flag_operand *ccode;
4616
4617 memset (&ereg, 0, sizeof (ereg));
4618 tokenize_extregister (&ereg, opertype);
4619
4620 switch (opertype)
4621 {
4622 case EXT_CORE_REGISTER:
4623 /* Core register. */
4624 if (ereg.number > 60)
4625 as_bad (_("core register %s value (%d) too large"), ereg.name,
4626 ereg.number);
4627 declare_register (ereg.name, ereg.number);
4628 break;
4629 case EXT_AUX_REGISTER:
4630 /* Auxiliary register. */
add39d23 4631 auxr = XNEW (struct arc_aux_reg);
f36e33da 4632 auxr->name = ereg.name;
bb65a718 4633 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4634 auxr->subclass = NONE;
4635 auxr->address = ereg.number;
4636 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4637 if (retval)
4638 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4639 auxr->name, retval);
4640 break;
4641 case EXT_COND_CODE:
4642 /* Condition code. */
4643 if (ereg.number > 31)
4644 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4645 ereg.number);
4646 ext_condcode.size ++;
4647 ext_condcode.arc_ext_condcode =
add39d23
TS		 4648 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4649 ext_condcode.size + 1);
f36e33da
CZ		 4650 if (ext_condcode.arc_ext_condcode == NULL)
4651 as_fatal (_("Virtual memory exhausted"));
4652
4653 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4654 ccode->name = ereg.name;
4655 ccode->code = ereg.number;
4656 ccode->bits = 5;
4657 ccode->shift = 0;
4658 ccode->favail = 0; /* not used. */
4659 ccode++;
4660 memset (ccode, 0, sizeof (struct arc_flag_operand));
4661 break;
4662 default:
4663 as_bad (_("Unknown extension"));
4664 break;
4665 }
4666 create_extcore_section (&ereg, opertype);
4667}
4668
b99747ae
CZ		 4669/* Local variables:
4670 eval: (c-set-style "gnu")
4671 indent-tabs-mode: t
4672 End: */
GDB Binutils - Deliverables
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