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[ARC] Fix fall through warnings.
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132 30#include "opcode/arc.h"
53a346d8 31#include "opcode/arc-attrs.h"
252b5132 32#include "elf/arc.h"
b99747ae 33#include "../opcodes/arc-ext.h"
252b5132 34
886a2506 35/* Defines section. */
0d2bcfaf 36
886a2506
NC		 37#define MAX_INSN_FIXUPS 2
38#define MAX_CONSTR_STR 20
4670103e 39#define FRAG_MAX_GROWTH 8
0d2bcfaf 40
886a2506
NC		 41#ifdef DEBUG
42# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43#else
44# define pr_debug(fmt, args...)
45#endif
46
47#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 49#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
886a2506
NC		 51
52/* Equal to MAX_PRECISION in atof-ieee.c. */
53#define MAX_LITTLENUMS 6
54
9004b6bd
AB		 55#ifndef TARGET_WITH_CPU
56#define TARGET_WITH_CPU "arc700"
57#endif /* TARGET_WITH_CPU */
58
53a346d8
CZ		 59#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61#define streq(a, b) (strcmp (a, b) == 0)
62
4670103e
CZ		 63/* Enum used to enumerate the relaxable ins operands. */
64enum rlx_operand_type
65{
66 EMPTY = 0,
67 REGISTER,
68 REGISTER_S, /* Register for short instruction(s). */
69 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
70 REGISTER_DUP, /* Duplication of previous operand of type register. */
71 IMMEDIATE,
72 BRACKET
73};
74
75enum arc_rlx_types
76{
77 ARC_RLX_NONE = 0,
78 ARC_RLX_BL_S,
79 ARC_RLX_BL,
80 ARC_RLX_B_S,
81 ARC_RLX_B,
82 ARC_RLX_ADD_U3,
83 ARC_RLX_ADD_U6,
84 ARC_RLX_ADD_LIMM,
85 ARC_RLX_LD_U7,
86 ARC_RLX_LD_S9,
87 ARC_RLX_LD_LIMM,
88 ARC_RLX_MOV_U8,
89 ARC_RLX_MOV_S12,
90 ARC_RLX_MOV_LIMM,
91 ARC_RLX_SUB_U3,
92 ARC_RLX_SUB_U6,
93 ARC_RLX_SUB_LIMM,
94 ARC_RLX_MPY_U6,
95 ARC_RLX_MPY_LIMM,
96 ARC_RLX_MOV_RU6,
97 ARC_RLX_MOV_RLIMM,
98 ARC_RLX_ADD_RRU6,
99 ARC_RLX_ADD_RRLIMM,
100};
101
886a2506
NC		 102/* Macros section. */
103
104#define regno(x) ((x) & 0x3F)
105#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 106#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107#define is_spfp_p(op) (((sc) == SPX))
108#define is_dpfp_p(op) (((sc) == DPX))
109#define is_fpuda_p(op) (((sc) == DPA))
db18dbab
GM		 110#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP))
c810e0b8 112#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 113#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 114
886a2506
NC		 115/* Generic assembler global variables which must be defined by all
116 targets. */
0d2bcfaf 117
886a2506 118/* Characters which always start a comment. */
252b5132
RH		 119const char comment_chars[] = "#;";
120
886a2506 121/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 122const char line_comment_chars[] = "#";
123
886a2506
NC		 124/* Characters which may be used to separate multiple commands on a
125 single line. */
126const char line_separator_chars[] = "`";
252b5132 127
886a2506
NC		 128/* Characters which are used to indicate an exponent in a floating
129 point number. */
252b5132
RH		 130const char EXP_CHARS[] = "eE";
131
bcee8eb8
AM		 132/* Chars that mean this number is a floating point constant
133 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 134const char FLT_CHARS[] = "rRsSfFdD";
135
136/* Byte order. */
137extern int target_big_endian;
138const char *arc_target_format = DEFAULT_TARGET_FORMAT;
139static int byte_order = DEFAULT_BYTE_ORDER;
140
b99747ae
CZ		 141/* Arc extension section. */
142static segT arcext_section;
143
4670103e
CZ		 144/* By default relaxation is disabled. */
145static int relaxation_state = 0;
146
886a2506 147extern int arc_get_mach (char *);
0d2bcfaf 148
4670103e 149/* Forward declarations. */
886a2506
NC		 150static void arc_lcomm (int);
151static void arc_option (int);
152static void arc_extra_reloc (int);
b99747ae 153static void arc_extinsn (int);
f36e33da 154static void arc_extcorereg (int);
53a346d8 155static void arc_attribute (int);
4670103e 156
886a2506 157const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 158{
159 /* Make sure that .word is 32 bits. */
160 { "word", cons, 4 },
886a2506 161
6f4b1afc
CM		 162 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
163 { "lcomm", arc_lcomm, 0 },
164 { "lcommon", arc_lcomm, 0 },
165 { "cpu", arc_option, 0 },
252b5132 166
53a346d8 167 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 168 { "extinstruction", arc_extinsn, 0 },
169 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
170 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
171 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 172
6f4b1afc
CM		 173 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
174 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 175
6f4b1afc
CM		 176 { NULL, NULL, 0 }
177};
252b5132 178
252b5132 179const char *md_shortopts = "";
ea1562b3
NC		 180
181enum options
6f4b1afc
CM		 182{
183 OPTION_EB = OPTION_MD_BASE,
184 OPTION_EL,
185
186 OPTION_ARC600,
187 OPTION_ARC601,
188 OPTION_ARC700,
189 OPTION_ARCEM,
190 OPTION_ARCHS,
191
192 OPTION_MCPU,
193 OPTION_CD,
4670103e 194 OPTION_RELAX,
bdd582db 195 OPTION_NPS400,
6f4b1afc 196
ce440d63
GM		 197 OPTION_SPFP,
198 OPTION_DPFP,
199 OPTION_FPUDA,
200
6f4b1afc
CM		 201 /* The following options are deprecated and provided here only for
202 compatibility reasons. */
203 OPTION_USER_MODE,
204 OPTION_LD_EXT_MASK,
205 OPTION_SWAP,
206 OPTION_NORM,
207 OPTION_BARREL_SHIFT,
208 OPTION_MIN_MAX,
209 OPTION_NO_MPY,
210 OPTION_EA,
211 OPTION_MUL64,
212 OPTION_SIMD,
6f4b1afc
CM		 213 OPTION_XMAC_D16,
214 OPTION_XMAC_24,
215 OPTION_DSP_PACKA,
216 OPTION_CRC,
217 OPTION_DVBF,
218 OPTION_TELEPHONY,
219 OPTION_XYMEMORY,
220 OPTION_LOCK,
221 OPTION_SWAPE,
ce440d63 222 OPTION_RTSC
6f4b1afc 223};
ea1562b3
NC		 224
225struct option md_longopts[] =
6f4b1afc
CM		 226{
227 { "EB", no_argument, NULL, OPTION_EB },
228 { "EL", no_argument, NULL, OPTION_EL },
229 { "mcpu", required_argument, NULL, OPTION_MCPU },
230 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 231 { "mARC600", no_argument, NULL, OPTION_ARC600 },
232 { "mARC601", no_argument, NULL, OPTION_ARC601 },
233 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 234 { "mA7", no_argument, NULL, OPTION_ARC700 },
235 { "mEM", no_argument, NULL, OPTION_ARCEM },
236 { "mHS", no_argument, NULL, OPTION_ARCHS },
237 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 238 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 239 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 240
ce440d63
GM		 241 /* Floating point options */
242 { "mspfp", no_argument, NULL, OPTION_SPFP},
243 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
244 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
245 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
246 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
247 { "mdpfp", no_argument, NULL, OPTION_DPFP},
248 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
249 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
250 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
251 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
252 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
253
6f4b1afc
CM		 254 /* The following options are deprecated and provided here only for
255 compatibility reasons. */
256 { "mav2em", no_argument, NULL, OPTION_ARCEM },
257 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
258 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
259 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
260 { "mswap", no_argument, NULL, OPTION_SWAP },
261 { "mnorm", no_argument, NULL, OPTION_NORM },
262 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
263 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
264 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
265 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
266 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
267 { "mea", no_argument, NULL, OPTION_EA },
268 { "mEA", no_argument, NULL, OPTION_EA },
269 { "mmul64", no_argument, NULL, OPTION_MUL64 },
270 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 271 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
272 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
273 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
274 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
275 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
276 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
277 { "mcrc", no_argument, NULL, OPTION_CRC},
278 { "mdvbf", no_argument, NULL, OPTION_DVBF},
279 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
280 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
281 { "mlock", no_argument, NULL, OPTION_LOCK},
282 { "mswape", no_argument, NULL, OPTION_SWAPE},
283 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 284
285 { NULL, no_argument, NULL, 0 }
286};
252b5132 287
886a2506 288size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 289
886a2506 290/* Local data and data types. */
252b5132 291
886a2506
NC		 292/* Used since new relocation types are introduced in this
293 file (DUMMY_RELOC_LITUSE_*). */
294typedef int extended_bfd_reloc_code_real_type;
252b5132 295
886a2506 296struct arc_fixup
252b5132 297{
886a2506 298 expressionS exp;
252b5132 299
886a2506 300 extended_bfd_reloc_code_real_type reloc;
252b5132 301
886a2506
NC		 302 /* index into arc_operands. */
303 unsigned int opindex;
252b5132 304
886a2506
NC		 305 /* PC-relative, used by internals fixups. */
306 unsigned char pcrel;
252b5132 307
886a2506
NC		 308 /* TRUE if this fixup is for LIMM operand. */
309 bfd_boolean islong;
310};
252b5132 311
886a2506
NC		 312struct arc_insn
313{
bdfe53e3 314 unsigned long long int insn;
886a2506
NC		 315 int nfixups;
316 struct arc_fixup fixups[MAX_INSN_FIXUPS];
317 long limm;
91fdca6f 318 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 319 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
320 valid. */
4670103e
CZ		 321 bfd_boolean relax; /* Boolean value: TRUE if needs
322 relaxation. */
886a2506 323};
ea1562b3 324
886a2506
NC		 325/* Structure to hold any last two instructions. */
326static struct arc_last_insn
252b5132 327{
886a2506
NC		 328 /* Saved instruction opcode. */
329 const struct arc_opcode *opcode;
252b5132 330
886a2506
NC		 331 /* Boolean value: TRUE if current insn is short. */
332 bfd_boolean has_limm;
252b5132 333
886a2506
NC		 334 /* Boolean value: TRUE if current insn has delay slot. */
335 bfd_boolean has_delay_slot;
336} arc_last_insns[2];
252b5132 337
b99747ae
CZ		 338/* Extension instruction suffix classes. */
339typedef struct
340{
341 const char *name;
342 int len;
c810e0b8 343 int attr_class;
b99747ae
CZ		 344} attributes_t;
345
346static const attributes_t suffixclass[] =
347{
348 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
349 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
350 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
351};
352
353/* Extension instruction syntax classes. */
354static const attributes_t syntaxclass[] =
355{
356 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 357 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
358 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
359 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 360};
361
362/* Extension instruction syntax classes modifiers. */
363static const attributes_t syntaxclassmod[] =
364{
365 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
366 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
367};
368
f36e33da
CZ		 369/* Extension register type. */
370typedef struct
371{
372 char *name;
373 int number;
374 int imode;
375} extRegister_t;
376
377/* A structure to hold the additional conditional codes. */
378static struct
379{
380 struct arc_flag_operand *arc_ext_condcode;
381 int size;
382} ext_condcode = { NULL, 0 };
383
da5be039
AB		 384/* Structure to hold an entry in ARC_OPCODE_HASH. */
385struct arc_opcode_hash_entry
386{
387 /* The number of pointers in the OPCODE list. */
388 size_t count;
389
390 /* Points to a list of opcode pointers. */
391 const struct arc_opcode **opcode;
392};
393
1328504b
AB		 394/* Structure used for iterating through an arc_opcode_hash_entry. */
395struct arc_opcode_hash_entry_iterator
396{
397 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
398 size_t index;
399
400 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
401 returned by this iterator. */
402 const struct arc_opcode *opcode;
403};
404
4670103e
CZ		 405/* Forward declaration. */
406static void assemble_insn
407 (const struct arc_opcode *, const expressionS *, int,
408 const struct arc_flags *, int, struct arc_insn *);
409
bb65a718
AB		 410/* The selection of the machine type can come from different sources. This
411 enum is used to track how the selection was made in order to perform
412 error checks. */
413enum mach_selection_type
414 {
415 MACH_SELECTION_NONE,
416 MACH_SELECTION_FROM_DEFAULT,
417 MACH_SELECTION_FROM_CPU_DIRECTIVE,
418 MACH_SELECTION_FROM_COMMAND_LINE
419 };
420
421/* How the current machine type was selected. */
422static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 423
886a2506
NC		 424/* The hash table of instruction opcodes. */
425static struct hash_control *arc_opcode_hash;
0d2bcfaf 426
886a2506
NC		 427/* The hash table of register symbols. */
428static struct hash_control *arc_reg_hash;
252b5132 429
f36e33da
CZ		 430/* The hash table of aux register symbols. */
431static struct hash_control *arc_aux_hash;
432
db18dbab
GM		 433/* The hash table of address types. */
434static struct hash_control *arc_addrtype_hash;
435
a9752fdf
CZ		 436#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
437 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
438 E_ARC_MACH_ARC600, EXTRA}
439#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
440 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
441 E_ARC_MACH_ARC700, EXTRA}
442#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
444 EF_ARC_CPU_ARCV2EM, EXTRA}
445#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
447 EF_ARC_CPU_ARCV2HS, EXTRA}
448
886a2506
NC		 449/* A table of CPU names and opcode sets. */
450static const struct cpu_type
451{
452 const char *name;
453 unsigned flags;
454 int mach;
455 unsigned eflags;
456 unsigned features;
252b5132 457}
886a2506 458 cpu_types[] =
252b5132 459{
a9752fdf 460 ARC_CPU_TYPE_A7xx (arc700, 0x00),
53a346d8 461 ARC_CPU_TYPE_A7xx (nps400, NPS400),
a9752fdf
CZ		 462
463 ARC_CPU_TYPE_AV2EM (arcem, 0x00),
464 ARC_CPU_TYPE_AV2EM (em, 0x00),
53a346d8
CZ		 465 ARC_CPU_TYPE_AV2EM (em4, CD),
466 ARC_CPU_TYPE_AV2EM (em4_dmips, CD),
467 ARC_CPU_TYPE_AV2EM (em4_fpus, CD),
468 ARC_CPU_TYPE_AV2EM (em4_fpuda, CD | DPA),
469 ARC_CPU_TYPE_AV2EM (quarkse_em, CD | SPX | DPX),
470
471 ARC_CPU_TYPE_AV2HS (archs, CD),
472 ARC_CPU_TYPE_AV2HS (hs, CD),
473 ARC_CPU_TYPE_AV2HS (hs34, CD),
474 ARC_CPU_TYPE_AV2HS (hs38, CD),
475 ARC_CPU_TYPE_AV2HS (hs38_linux, CD),
a9752fdf
CZ		 476
477 ARC_CPU_TYPE_A6xx (arc600, 0x00),
478 ARC_CPU_TYPE_A6xx (arc600_norm, 0x00),
479 ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00),
480 ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00),
481 ARC_CPU_TYPE_A6xx (arc601, 0x00),
482 ARC_CPU_TYPE_A6xx (arc601_norm, 0x00),
483 ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00),
484 ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00),
886a2506
NC		 485 { 0, 0, 0, 0, 0 }
486};
252b5132 487
bb65a718 488/* Information about the cpu/variant we're assembling for. */
53a346d8 489static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 490
53a346d8
CZ		 491/* MPY option. */
492static unsigned mpy_option = 0;
493
494/* Use PIC. */
495static unsigned pic_option = 0;
496
497/* Use small data. */
498static unsigned sda_option = 0;
499
500/* Use TLS. */
501static unsigned tls_option = 0;
bb65a718 502
a9752fdf
CZ		 503/* Command line given features. */
504static unsigned cl_features = 0;
505
886a2506
NC		 506/* Used by the arc_reloc_op table. Order is important. */
507#define O_gotoff O_md1 /* @gotoff relocation. */
508#define O_gotpc O_md2 /* @gotpc relocation. */
509#define O_plt O_md3 /* @plt relocation. */
510#define O_sda O_md4 /* @sda relocation. */
511#define O_pcl O_md5 /* @pcl relocation. */
512#define O_tlsgd O_md6 /* @tlsgd relocation. */
513#define O_tlsie O_md7 /* @tlsie relocation. */
514#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
515#define O_tpoff O_md9 /* @tpoff relocation. */
516#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
517#define O_dtpoff O_md11 /* @dtpoff relocation. */
518#define O_last O_dtpoff
519
520/* Used to define a bracket as operand in tokens. */
521#define O_bracket O_md32
522
db18dbab
GM		 523/* Used to define a colon as an operand in tokens. */
524#define O_colon O_md31
525
526/* Used to define address types in nps400. */
527#define O_addrtype O_md30
528
886a2506
NC		 529/* Dummy relocation, to be sorted out. */
530#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
531
532#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
533
534/* A table to map the spelling of a relocation operand into an appropriate
535 bfd_reloc_code_real_type type. The table is assumed to be ordered such
536 that op-O_literal indexes into it. */
537#define ARC_RELOC_TABLE(op) \
538 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
539 ? (abort (), 0) \
540 : (int) (op) - (int) O_gotoff) ])
541
542#define DEF(NAME, RELOC, REQ) \
543 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
544
545static const struct arc_reloc_op_tag
546{
547 /* String to lookup. */
548 const char *name;
549 /* Size of the string. */
550 size_t length;
551 /* Which operator to use. */
552 operatorT op;
553 extended_bfd_reloc_code_real_type reloc;
554 /* Allows complex relocation expression like identifier@reloc +
555 const. */
556 unsigned int complex_expr : 1;
557}
558 arc_reloc_op[] =
6f4b1afc
CM		 559{
560 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
561 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
562 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
563 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
564 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
565 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
566 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
567 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 568 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 569 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 570 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 571};
252b5132 572
886a2506
NC		 573static const int arc_num_reloc_op
574= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
575
4670103e
CZ		 576/* Structure for relaxable instruction that have to be swapped with a
577 smaller alternative instruction. */
578struct arc_relaxable_ins
579{
580 /* Mnemonic that should be checked. */
581 const char *mnemonic_r;
582
583 /* Operands that should be checked.
584 Indexes of operands from operand array. */
585 enum rlx_operand_type operands[6];
586
587 /* Flags that should be checked. */
588 unsigned flag_classes[5];
589
590 /* Mnemonic (smaller) alternative to be used later for relaxation. */
591 const char *mnemonic_alt;
592
593 /* Index of operand that generic relaxation has to check. */
594 unsigned opcheckidx;
595
596 /* Base subtype index used. */
597 enum arc_rlx_types subtype;
598};
599
600#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
601 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
602 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
603 (SIZE), \
604 (NEXT) } \
605
606#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
607 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
608 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
609 (SIZE), \
610 (NEXT) } \
611
612
613/* ARC relaxation table. */
614const relax_typeS md_relax_table[] =
615{
616 /* Fake entry. */
617 {0, 0, 0, 0},
618
619 /* BL_S s13 ->
620 BL s25. */
db18dbab
GM		 621 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
622 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 623
624 /* B_S s10 ->
625 B s25. */
db18dbab
GM		 626 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
627 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 628
629 /* ADD_S c,b, u3 ->
630 ADD<.f> a,b,u6 ->
631 ADD<.f> a,b,limm. */
db18dbab
GM		 632 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
633 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 635
636 /* LD_S a, [b, u7] ->
637 LD<zz><.x><.aa><.di> a, [b, s9] ->
638 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 639 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
640 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
641 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 642
643 /* MOV_S b, u8 ->
644 MOV<.f> b, s12 ->
645 MOV<.f> b, limm. */
db18dbab
GM		 646 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
647 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
648 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 649
650 /* SUB_S c, b, u3 ->
651 SUB<.f> a, b, u6 ->
652 SUB<.f> a, b, limm. */
db18dbab
GM		 653 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
654 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
655 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 656
657 /* MPY<.f> a, b, u6 ->
658 MPY<.f> a, b, limm. */
db18dbab
GM		 659 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
660 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 661
662 /* MOV<.f><.cc> b, u6 ->
663 MOV<.f><.cc> b, limm. */
db18dbab
GM		 664 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
665 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 666
667 /* ADD<.f><.cc> b, b, u6 ->
668 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 669 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
670 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 671};
672
673/* Order of this table's entries matters! */
674const struct arc_relaxable_ins arc_relaxable_insns[] =
675{
676 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
677 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
678 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
679 2, ARC_RLX_ADD_RRU6},
680 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
681 ARC_RLX_ADD_U3 },
682 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
683 ARC_RLX_ADD_U6 },
684 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
685 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
686 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
687 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
688 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
689 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
690 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
691 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
692 ARC_RLX_SUB_U3 },
693 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
694 ARC_RLX_SUB_U6 },
695 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
696 ARC_RLX_MPY_U6 },
697};
698
699const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
700
886a2506
NC		 701/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
702symbolS * GOT_symbol = 0;
703
704/* Set to TRUE when we assemble instructions. */
705static bfd_boolean assembling_insn = FALSE;
706
53a346d8
CZ		 707/* List with attributes set explicitly. */
708static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
709
886a2506
NC		 710/* Functions implementation. */
711
b9b47ab7
AB		 712/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
713 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
714 are no matching entries in ARC_OPCODE_HASH. */
da5be039 715
b9b47ab7 716static const struct arc_opcode_hash_entry *
da5be039
AB		 717arc_find_opcode (const char *name)
718{
719 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 720
721 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 722 return entry;
da5be039
AB		 723}
724
1328504b
AB		 725/* Initialise the iterator ITER. */
726
727static void
728arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
729{
730 iter->index = 0;
731 iter->opcode = NULL;
732}
733
734/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
735 calls to this function. Return NULL when all ARC_OPCODE entries have
736 been returned. */
737
738static const struct arc_opcode *
739arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
740 struct arc_opcode_hash_entry_iterator *iter)
741{
742 if (iter->opcode == NULL && iter->index == 0)
743 {
744 gas_assert (entry->count > 0);
745 iter->opcode = entry->opcode[iter->index];
746 }
747 else if (iter->opcode != NULL)
748 {
749 const char *old_name = iter->opcode->name;
750
751 iter->opcode++;
fe779266
AB		 752 if (iter->opcode->name == NULL
753 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 754 {
755 iter->index++;
756 if (iter->index == entry->count)
757 iter->opcode = NULL;
758 else
759 iter->opcode = entry->opcode[iter->index];
760 }
761 }
762
763 return iter->opcode;
764}
765
b99747ae
CZ		 766/* Insert an opcode into opcode hash structure. */
767
768static void
769arc_insert_opcode (const struct arc_opcode *opcode)
770{
771 const char *name, *retval;
772 struct arc_opcode_hash_entry *entry;
773 name = opcode->name;
774
775 entry = hash_find (arc_opcode_hash, name);
776 if (entry == NULL)
777 {
add39d23 778 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 779 entry->count = 0;
780 entry->opcode = NULL;
781
782 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
783 if (retval)
784 as_fatal (_("internal error: can't hash opcode '%s': %s"),
785 name, retval);
786 }
787
add39d23
TS		 788 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
789 entry->count + 1);
b99747ae
CZ		 790
791 if (entry->opcode == NULL)
792 as_fatal (_("Virtual memory exhausted"));
793
794 entry->opcode[entry->count] = opcode;
795 entry->count++;
796}
797
798
bdfe53e3
AB		 799/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
800 value, is encoded as 'middle-endian' for a little-endian target. This
801 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 802
803static void
bdfe53e3 804md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 805{
bdfe53e3 806 switch (n)
886a2506 807 {
bdfe53e3
AB		 808 case 2:
809 md_number_to_chars (buf, val, n);
810 break;
811 case 6:
812 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
813 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
814 break;
815 case 4:
886a2506
NC		 816 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
817 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 818 break;
819 case 8:
820 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
821 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
822 break;
823 default:
824 abort ();
886a2506 825 }
252b5132
RH		 826}
827
bb050a69
CZ		 828/* Check if a feature is allowed for a specific CPU. */
829
830static void
831arc_check_feature (void)
832{
833 unsigned i;
834
835 if (!selected_cpu.features
836 || !selected_cpu.name)
837 return;
53a346d8
CZ		 838
839 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
840 if ((selected_cpu.features & feature_list[i].feature)
841 && !(selected_cpu.flags & feature_list[i].cpus))
842 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
843 selected_cpu.name);
844
845 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
846 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
847 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 848}
849
24740d83 850/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 851 the relevant static global variables. Parameter SEL describes where
852 this selection originated from. */
24740d83
AB		 853
854static void
bb65a718 855arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 856{
24740d83
AB		 857 int i;
858
bb65a718
AB		 859 /* We should only set a default if we've not made a selection from some
860 other source. */
861 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
862 || mach_selection_mode == MACH_SELECTION_NONE);
863
bb050a69
CZ		 864 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
865 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
866 as_bad (_("Multiple .cpu directives found"));
867
bb65a718 868 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 869 for (i = 0; cpu_types[i].name; ++i)
870 {
871 if (!strcasecmp (cpu_types[i].name, arg))
872 {
bb65a718
AB		 873 /* If a previous selection was made on the command line, then we
874 allow later selections on the command line to override earlier
875 ones. However, a selection from a '.cpu NAME' directive must
876 match the command line selection, or we give a warning. */
877 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
878 {
879 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
880 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
881 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
882 && selected_cpu.mach != cpu_types[i].mach)
883 {
884 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 885 }
bb050a69 886 return;
bb65a718
AB		 887 }
888
bb050a69
CZ		 889 /* Initialise static global data about selected machine type. */
890 selected_cpu.flags = cpu_types[i].flags;
891 selected_cpu.name = cpu_types[i].name;
a9752fdf 892 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 893 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 894 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
895 | cpu_types[i].eflags);
24740d83
AB		 896 break;
897 }
898 }
899
900 if (!cpu_types[i].name)
901 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 902
903 /* Check if set features are compatible with the chosen CPU. */
904 arc_check_feature ();
53a346d8 905
bb65a718 906 mach_selection_mode = sel;
24740d83
AB		 907}
908
886a2506
NC		 909/* Here ends all the ARCompact extension instruction assembling
910 stuff. */
252b5132 911
886a2506
NC		 912static void
913arc_extra_reloc (int r_type)
ea1562b3 914{
886a2506
NC		 915 char *sym_name, c;
916 symbolS *sym, *lab = NULL;
917
918 if (*input_line_pointer == '@')
919 input_line_pointer++;
920 c = get_symbol_name (&sym_name);
921 sym = symbol_find_or_make (sym_name);
922 restore_line_pointer (c);
923 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
924 {
925 ++input_line_pointer;
926 char *lab_name;
927 c = get_symbol_name (&lab_name);
928 lab = symbol_find_or_make (lab_name);
929 restore_line_pointer (c);
930 }
841fdfcd
CZ		 931
932 /* These relocations exist as a mechanism for the compiler to tell the
933 linker how to patch the code if the tls model is optimised. However,
934 the relocation itself does not require any space within the assembler
935 fragment, and so we pass a size of 0.
936
937 The lines that generate these relocations look like this:
938
939 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
940
941 The '.tls_gd_ld @.tdata' is processed first and generates the
942 additional relocation, while the 'bl __tls_get_addr@plt' is processed
943 second and generates the additional branch.
944
945 It is possible that the additional relocation generated by the
946 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
947 while the 'bl __tls_get_addr@plt' will be generated as the first thing
948 in the next fragment. This will be fine; both relocations will still
949 appear to be at the same address in the generated object file.
950 However, this only works as the additional relocation is generated
951 with size of 0 bytes. */
886a2506
NC		 952 fixS *fixP
953 = fix_new (frag_now, /* Which frag? */
954 frag_now_fix (), /* Where in that frag? */
841fdfcd 955 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 956 sym, /* X_add_symbol. */
957 0, /* X_add_number. */
958 FALSE, /* TRUE if PC-relative relocation. */
959 r_type /* Relocation type. */);
960 fixP->fx_subsy = lab;
961}
252b5132 962
886a2506
NC		 963static symbolS *
964arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
965 symbolS *symbolP, addressT size)
966{
967 addressT align = 0;
968 SKIP_WHITESPACE ();
252b5132 969
886a2506
NC		 970 if (*input_line_pointer == ',')
971 {
972 align = parse_align (1);
252b5132 973
886a2506
NC		 974 if (align == (addressT) -1)
975 return NULL;
976 }
977 else
978 {
979 if (size >= 8)
980 align = 3;
981 else if (size >= 4)
982 align = 2;
983 else if (size >= 2)
984 align = 1;
985 else
986 align = 0;
987 }
252b5132 988
886a2506
NC		 989 bss_alloc (symbolP, size, align);
990 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 991
886a2506
NC		 992 return symbolP;
993}
ea1562b3 994
886a2506
NC		 995static void
996arc_lcomm (int ignore)
997{
998 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 999
886a2506
NC		 1000 if (symbolP)
1001 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
1002}
ea1562b3 1003
886a2506 1004/* Select the cpu we're assembling for. */
ea1562b3 1005
886a2506
NC		 1006static void
1007arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 1008{
886a2506
NC		 1009 char c;
1010 char *cpu;
bb65a718 1011 const char *cpu_name;
252b5132 1012
886a2506 1013 c = get_symbol_name (&cpu);
252b5132 1014
a9752fdf 1015 cpu_name = cpu;
bb65a718
AB		 1016 if ((!strcmp ("ARC600", cpu))
1017 || (!strcmp ("ARC601", cpu))
1018 || (!strcmp ("A6", cpu)))
1019 cpu_name = "arc600";
1020 else if ((!strcmp ("ARC700", cpu))
1021 || (!strcmp ("A7", cpu)))
1022 cpu_name = "arc700";
1023 else if (!strcmp ("EM", cpu))
1024 cpu_name = "arcem";
1025 else if (!strcmp ("HS", cpu))
1026 cpu_name = "archs";
1027 else if (!strcmp ("NPS400", cpu))
1028 cpu_name = "nps400";
886a2506 1029
a9752fdf 1030 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1031
24b368f8 1032 restore_line_pointer (c);
886a2506 1033 demand_empty_rest_of_line ();
ea1562b3 1034}
252b5132 1035
886a2506
NC		 1036/* Smartly print an expression. */
1037
ea1562b3 1038static void
886a2506 1039debug_exp (expressionS *t)
ea1562b3 1040{
886a2506
NC		 1041 const char *name ATTRIBUTE_UNUSED;
1042 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1043
886a2506 1044 pr_debug ("debug_exp: ");
252b5132 1045
886a2506 1046 switch (t->X_op)
252b5132 1047 {
886a2506
NC		 1048 default: name = "unknown"; break;
1049 case O_illegal: name = "O_illegal"; break;
1050 case O_absent: name = "O_absent"; break;
1051 case O_constant: name = "O_constant"; break;
1052 case O_symbol: name = "O_symbol"; break;
1053 case O_symbol_rva: name = "O_symbol_rva"; break;
1054 case O_register: name = "O_register"; break;
1055 case O_big: name = "O_big"; break;
1056 case O_uminus: name = "O_uminus"; break;
1057 case O_bit_not: name = "O_bit_not"; break;
1058 case O_logical_not: name = "O_logical_not"; break;
1059 case O_multiply: name = "O_multiply"; break;
1060 case O_divide: name = "O_divide"; break;
1061 case O_modulus: name = "O_modulus"; break;
1062 case O_left_shift: name = "O_left_shift"; break;
1063 case O_right_shift: name = "O_right_shift"; break;
1064 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1065 case O_bit_or_not: name = "O_bit_or_not"; break;
1066 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1067 case O_bit_and: name = "O_bit_and"; break;
1068 case O_add: name = "O_add"; break;
1069 case O_subtract: name = "O_subtract"; break;
1070 case O_eq: name = "O_eq"; break;
1071 case O_ne: name = "O_ne"; break;
1072 case O_lt: name = "O_lt"; break;
1073 case O_le: name = "O_le"; break;
1074 case O_ge: name = "O_ge"; break;
1075 case O_gt: name = "O_gt"; break;
1076 case O_logical_and: name = "O_logical_and"; break;
1077 case O_logical_or: name = "O_logical_or"; break;
1078 case O_index: name = "O_index"; break;
1079 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1080 case O_colon: name = "O_colon"; break;
1081 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1082 }
252b5132 1083
886a2506 1084 switch (t->X_md)
ea1562b3 1085 {
886a2506
NC		 1086 default: namemd = "unknown"; break;
1087 case O_gotoff: namemd = "O_gotoff"; break;
1088 case O_gotpc: namemd = "O_gotpc"; break;
1089 case O_plt: namemd = "O_plt"; break;
1090 case O_sda: namemd = "O_sda"; break;
1091 case O_pcl: namemd = "O_pcl"; break;
1092 case O_tlsgd: namemd = "O_tlsgd"; break;
1093 case O_tlsie: namemd = "O_tlsie"; break;
1094 case O_tpoff9: namemd = "O_tpoff9"; break;
1095 case O_tpoff: namemd = "O_tpoff"; break;
1096 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1097 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1098 }
252b5132 1099
886a2506
NC		 1100 pr_debug ("%s (%s, %s, %d, %s)", name,
1101 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1102 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1103 (int) t->X_add_number,
1104 (t->X_md) ? namemd : "--");
1105 pr_debug ("\n");
1106 fflush (stderr);
1107}
252b5132 1108
886a2506
NC		 1109/* Parse the arguments to an opcode. */
1110
1111static int
1112tokenize_arguments (char *str,
1113 expressionS *tok,
1114 int ntok)
1115{
1116 char *old_input_line_pointer;
1117 bfd_boolean saw_comma = FALSE;
1118 bfd_boolean saw_arg = FALSE;
1119 int brk_lvl = 0;
1120 int num_args = 0;
886a2506
NC		 1121 int i;
1122 size_t len;
1123 const struct arc_reloc_op_tag *r;
1124 expressionS tmpE;
6f4b1afc 1125 char *reloc_name, c;
886a2506
NC		 1126
1127 memset (tok, 0, sizeof (*tok) * ntok);
1128
1129 /* Save and restore input_line_pointer around this function. */
1130 old_input_line_pointer = input_line_pointer;
1131 input_line_pointer = str;
ea1562b3 1132
886a2506 1133 while (*input_line_pointer)
ea1562b3
NC		 1134 {
1135 SKIP_WHITESPACE ();
886a2506 1136 switch (*input_line_pointer)
252b5132 1137 {
886a2506
NC		 1138 case '\0':
1139 goto fini;
1140
1141 case ',':
1142 input_line_pointer++;
1143 if (saw_comma || !saw_arg)
1144 goto err;
1145 saw_comma = TRUE;
1146 break;
252b5132 1147
886a2506
NC		 1148 case '}':
1149 case ']':
1150 ++input_line_pointer;
1151 --brk_lvl;
3b889a78 1152 if (!saw_arg || num_args == ntok)
886a2506
NC		 1153 goto err;
1154 tok->X_op = O_bracket;
1155 ++tok;
1156 ++num_args;
1157 break;
ea1562b3 1158
886a2506
NC		 1159 case '{':
1160 case '[':
1161 input_line_pointer++;
3b889a78 1162 if (brk_lvl || num_args == ntok)
886a2506
NC		 1163 goto err;
1164 ++brk_lvl;
1165 tok->X_op = O_bracket;
1166 ++tok;
1167 ++num_args;
1168 break;
1169
db18dbab
GM		 1170 case ':':
1171 input_line_pointer++;
1172 if (!saw_arg || num_args == ntok)
1173 goto err;
1174 tok->X_op = O_colon;
1175 saw_arg = FALSE;
1176 ++tok;
1177 ++num_args;
1178 break;
1179
886a2506
NC		 1180 case '@':
1181 /* We have labels, function names and relocations, all
1182 starting with @ symbol. Sort them out. */
3b889a78 1183 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1184 goto err;
1185
1186 /* Parse @label. */
1187 tok->X_op = O_symbol;
1188 tok->X_md = O_absent;
1189 expression (tok);
1190 if (*input_line_pointer != '@')
1191 goto normalsymbol; /* This is not a relocation. */
1192
6f4b1afc
CM		 1193 relocationsym:
1194
33eaf5de 1195 /* A relocation operand has the following form
886a2506
NC		 1196 @identifier@relocation_type. The identifier is already
1197 in tok! */
1198 if (tok->X_op != O_symbol)
ea1562b3 1199 {
886a2506
NC		 1200 as_bad (_("No valid label relocation operand"));
1201 goto err;
252b5132 1202 }
886a2506
NC		 1203
1204 /* Parse @relocation_type. */
6f4b1afc
CM		 1205 input_line_pointer++;
1206 c = get_symbol_name (&reloc_name);
1207 len = input_line_pointer - reloc_name;
1208 if (len == 0)
252b5132 1209 {
886a2506
NC		 1210 as_bad (_("No relocation operand"));
1211 goto err;
252b5132 1212 }
252b5132 1213
886a2506
NC		 1214 /* Go through known relocation and try to find a match. */
1215 r = &arc_reloc_op[0];
1216 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1217 if (len == r->length
1218 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1219 break;
886a2506 1220 if (i < 0)
252b5132 1221 {
6f4b1afc 1222 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1223 goto err;
1224 }
1225
6f4b1afc
CM		 1226 *input_line_pointer = c;
1227 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1228 /* Extra check for TLS: base. */
1229 if (*input_line_pointer == '@')
1230 {
1231 symbolS *base;
1232 if (tok->X_op_symbol != NULL
1233 || tok->X_op != O_symbol)
252b5132 1234 {
6f4b1afc
CM		 1235 as_bad (_("Unable to parse TLS base: %s"),
1236 input_line_pointer);
886a2506 1237 goto err;
252b5132 1238 }
886a2506
NC		 1239 input_line_pointer++;
1240 char *sym_name;
6f4b1afc 1241 c = get_symbol_name (&sym_name);
886a2506
NC		 1242 base = symbol_find_or_make (sym_name);
1243 tok->X_op = O_subtract;
1244 tok->X_op_symbol = base;
1245 restore_line_pointer (c);
6f4b1afc
CM		 1246 tmpE.X_add_number = 0;
1247 }
32348c58 1248 if ((*input_line_pointer != '+')
6f4b1afc
CM		 1249 && (*input_line_pointer != '-'))
1250 {
1251 tmpE.X_add_number = 0;
ea1562b3 1252 }
6f4b1afc
CM		 1253 else
1254 {
1255 /* Parse the constant of a complex relocation expression
1256 like @identifier@reloc +/- const. */
1257 if (! r->complex_expr)
1258 {
1259 as_bad (_("@%s is not a complex relocation."), r->name);
1260 goto err;
1261 }
1262 expression (&tmpE);
1263 if (tmpE.X_op != O_constant)
1264 {
1265 as_bad (_("Bad expression: @%s + %s."),
1266 r->name, input_line_pointer);
1267 goto err;
1268 }
1269 }
1270
1271 tok->X_md = r->op;
1272 tok->X_add_number = tmpE.X_add_number;
1e07b820 1273
886a2506 1274 debug_exp (tok);
ea1562b3 1275
886a2506
NC		 1276 saw_comma = FALSE;
1277 saw_arg = TRUE;
1278 tok++;
1279 num_args++;
1280 break;
252b5132 1281
886a2506
NC		 1282 case '%':
1283 /* Can be a register. */
1284 ++input_line_pointer;
1285 /* Fall through. */
1286 default:
252b5132 1287
3b889a78 1288 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1289 goto err;
252b5132 1290
886a2506 1291 tok->X_op = O_absent;
6f4b1afc 1292 tok->X_md = O_absent;
886a2506 1293 expression (tok);
252b5132 1294
6f4b1afc
CM		 1295 /* Legacy: There are cases when we have
1296 identifier@relocation_type, if it is the case parse the
1297 relocation type as well. */
1298 if (*input_line_pointer == '@')
1299 goto relocationsym;
1300
886a2506
NC		 1301 normalsymbol:
1302 debug_exp (tok);
252b5132 1303
3b889a78
AB		 1304 if (tok->X_op == O_illegal
1305 || tok->X_op == O_absent
1306 || num_args == ntok)
886a2506 1307 goto err;
252b5132 1308
886a2506
NC		 1309 saw_comma = FALSE;
1310 saw_arg = TRUE;
1311 tok++;
1312 num_args++;
1313 break;
1314 }
ea1562b3 1315 }
252b5132 1316
886a2506
NC		 1317 fini:
1318 if (saw_comma || brk_lvl)
1319 goto err;
1320 input_line_pointer = old_input_line_pointer;
252b5132 1321
886a2506 1322 return num_args;
252b5132 1323
886a2506
NC		 1324 err:
1325 if (brk_lvl)
1326 as_bad (_("Brackets in operand field incorrect"));
1327 else if (saw_comma)
1328 as_bad (_("extra comma"));
1329 else if (!saw_arg)
1330 as_bad (_("missing argument"));
1331 else
1332 as_bad (_("missing comma or colon"));
1333 input_line_pointer = old_input_line_pointer;
1334 return -1;
252b5132 1335}
ea1562b3 1336
886a2506
NC		 1337/* Parse the flags to a structure. */
1338
1339static int
1340tokenize_flags (const char *str,
1341 struct arc_flags flags[],
1342 int nflg)
252b5132 1343{
886a2506
NC		 1344 char *old_input_line_pointer;
1345 bfd_boolean saw_flg = FALSE;
1346 bfd_boolean saw_dot = FALSE;
1347 int num_flags = 0;
1348 size_t flgnamelen;
252b5132 1349
886a2506 1350 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1351
886a2506
NC		 1352 /* Save and restore input_line_pointer around this function. */
1353 old_input_line_pointer = input_line_pointer;
1354 input_line_pointer = (char *) str;
0d2bcfaf 1355
886a2506
NC		 1356 while (*input_line_pointer)
1357 {
1358 switch (*input_line_pointer)
1359 {
1360 case ' ':
1361 case '\0':
1362 goto fini;
1363
1364 case '.':
1365 input_line_pointer++;
1366 if (saw_dot)
1367 goto err;
1368 saw_dot = TRUE;
1369 saw_flg = FALSE;
1370 break;
ea1562b3 1371
886a2506
NC		 1372 default:
1373 if (saw_flg && !saw_dot)
1374 goto err;
0d2bcfaf 1375
886a2506
NC		 1376 if (num_flags >= nflg)
1377 goto err;
0d2bcfaf 1378
692166c2
AB		 1379 flgnamelen = strspn (input_line_pointer,
1380 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1381 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1382 goto err;
0d2bcfaf 1383
886a2506 1384 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1385
886a2506
NC		 1386 input_line_pointer += flgnamelen;
1387 flags++;
1388 saw_dot = FALSE;
1389 saw_flg = TRUE;
1390 num_flags++;
1391 break;
1e07b820 1392 }
0d2bcfaf
NC		 1393 }
1394
886a2506
NC		 1395 fini:
1396 input_line_pointer = old_input_line_pointer;
1397 return num_flags;
0d2bcfaf 1398
886a2506
NC		 1399 err:
1400 if (saw_dot)
1401 as_bad (_("extra dot"));
1402 else if (!saw_flg)
1403 as_bad (_("unrecognized flag"));
1404 else
1405 as_bad (_("failed to parse flags"));
1406 input_line_pointer = old_input_line_pointer;
1407 return -1;
1408}
0d2bcfaf 1409
4670103e 1410/* Apply the fixups in order. */
0d2bcfaf 1411
4670103e
CZ		 1412static void
1413apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1414{
4670103e 1415 int i;
0d2bcfaf 1416
4670103e 1417 for (i = 0; i < insn->nfixups; i++)
252b5132 1418 {
4670103e
CZ		 1419 struct arc_fixup *fixup = &insn->fixups[i];
1420 int size, pcrel, offset = 0;
0d2bcfaf 1421
4670103e
CZ		 1422 /* FIXME! the reloc size is wrong in the BFD file.
1423 When it is fixed please delete me. */
91fdca6f 1424 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1425
4670103e 1426 if (fixup->islong)
91fdca6f 1427 offset = insn->len;
252b5132 1428
4670103e
CZ		 1429 /* Some fixups are only used internally, thus no howto. */
1430 if ((int) fixup->reloc == 0)
1431 as_fatal (_("Unhandled reloc type"));
886a2506 1432
4670103e
CZ		 1433 if ((int) fixup->reloc < 0)
1434 {
1435 /* FIXME! the reloc size is wrong in the BFD file.
1436 When it is fixed please enable me.
91fdca6f 1437 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1438 pcrel = fixup->pcrel;
1439 }
1440 else
1441 {
1442 reloc_howto_type *reloc_howto =
1443 bfd_reloc_type_lookup (stdoutput,
1444 (bfd_reloc_code_real_type) fixup->reloc);
1445 gas_assert (reloc_howto);
0d2bcfaf 1446
4670103e
CZ		 1447 /* FIXME! the reloc size is wrong in the BFD file.
1448 When it is fixed please enable me.
1449 size = bfd_get_reloc_size (reloc_howto); */
1450 pcrel = reloc_howto->pc_relative;
1451 }
0d2bcfaf 1452
4670103e
CZ		 1453 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1454offset %d + %d\n",
1455 fragP->fr_file, fragP->fr_line,
1456 (fixup->reloc < 0) ? "Internal" :
1457 bfd_get_reloc_code_name (fixup->reloc),
1458 pcrel ? "Y" : "N",
1459 size, fix, offset);
1460 fix_new_exp (fragP, fix + offset,
1461 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1462
4670103e
CZ		 1463 /* Check for ZOLs, and update symbol info if any. */
1464 if (LP_INSN (insn->insn))
886a2506 1465 {
4670103e
CZ		 1466 gas_assert (fixup->exp.X_add_symbol);
1467 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1468 }
1469 }
252b5132
RH		 1470}
1471
4670103e 1472/* Actually output an instruction with its fixup. */
886a2506 1473
4670103e
CZ		 1474static void
1475emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1476{
4670103e 1477 char *f = where;
91fdca6f 1478 size_t total_len;
252b5132 1479
bdfe53e3
AB		 1480 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1481 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1482 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1483
4670103e 1484 /* Write out the instruction. */
91fdca6f
GM		 1485 total_len = insn->len + (insn->has_limm ? 4 : 0);
1486 if (!relax)
1487 f = frag_more (total_len);
1488
1489 md_number_to_chars_midend(f, insn->insn, insn->len);
1490
1491 if (insn->has_limm)
1492 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1493 dwarf2_emit_insn (total_len);
252b5132 1494
4670103e
CZ		 1495 if (!relax)
1496 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1497}
252b5132 1498
4670103e
CZ		 1499static void
1500emit_insn1 (struct arc_insn *insn)
1501{
1502 /* How frag_var's args are currently configured:
1503 - rs_machine_dependent, to dictate it's a relaxation frag.
1504 - FRAG_MAX_GROWTH, maximum size of instruction
1505 - 0, variable size that might grow...unused by generic relaxation.
1506 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1507 - s, opand expression.
1508 - 0, offset but it's unused.
1509 - 0, opcode but it's unused. */
1510 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1511 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1512
1513 if (frag_room () < FRAG_MAX_GROWTH)
1514 {
1515 /* Handle differently when frag literal memory is exhausted.
1516 This is used because when there's not enough memory left in
1517 the current frag, a new frag is created and the information
1518 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1519
4670103e
CZ		 1520 struct arc_relax_type relax_info_copy;
1521 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1522
4670103e
CZ		 1523 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1524 sizeof (struct arc_relax_type));
0d2bcfaf 1525
4670103e
CZ		 1526 frag_wane (frag_now);
1527 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1528
4670103e
CZ		 1529 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1530 sizeof (struct arc_relax_type));
252b5132 1531
4670103e
CZ		 1532 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1533 subtype, s, 0, 0);
1534 }
1535 else
1536 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1537 frag_now->fr_subtype, s, 0, 0);
1538}
252b5132 1539
4670103e
CZ		 1540static void
1541emit_insn (struct arc_insn *insn)
252b5132 1542{
4670103e
CZ		 1543 if (insn->relax)
1544 emit_insn1 (insn);
252b5132 1545 else
4670103e 1546 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1547}
1548
4670103e 1549/* Check whether a symbol involves a register. */
252b5132 1550
4670103e
CZ		 1551static bfd_boolean
1552contains_register (symbolS *sym)
252b5132 1553{
4670103e
CZ		 1554 if (sym)
1555 {
1556 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1557
4670103e
CZ		 1558 return ((O_register == ex->X_op)
1559 && !contains_register (ex->X_add_symbol)
1560 && !contains_register (ex->X_op_symbol));
1561 }
1562
1563 return FALSE;
252b5132
RH		 1564}
1565
4670103e 1566/* Returns the register number within a symbol. */
252b5132 1567
4670103e
CZ		 1568static int
1569get_register (symbolS *sym)
252b5132 1570{
4670103e
CZ		 1571 if (!contains_register (sym))
1572 return -1;
0d2bcfaf 1573
4670103e
CZ		 1574 expressionS *ex = symbol_get_value_expression (sym);
1575 return regno (ex->X_add_number);
1576}
252b5132 1577
4670103e
CZ		 1578/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1579 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1580
4670103e
CZ		 1581static bfd_boolean
1582generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1583{
1584 if (!reloc)
1585 return FALSE;
886a2506 1586
4670103e
CZ		 1587 switch (reloc)
1588 {
1589 case BFD_RELOC_ARC_SDA_LDST:
1590 case BFD_RELOC_ARC_SDA_LDST1:
1591 case BFD_RELOC_ARC_SDA_LDST2:
1592 case BFD_RELOC_ARC_SDA16_LD:
1593 case BFD_RELOC_ARC_SDA16_LD1:
1594 case BFD_RELOC_ARC_SDA16_LD2:
1595 case BFD_RELOC_ARC_SDA16_ST2:
1596 case BFD_RELOC_ARC_SDA32_ME:
1597 return FALSE;
1598 default:
1599 return TRUE;
f17c130b 1600 }
252b5132
RH		 1601}
1602
4670103e 1603/* Allocates a tok entry. */
252b5132 1604
4670103e
CZ		 1605static int
1606allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1607{
4670103e
CZ		 1608 if (ntok > MAX_INSN_ARGS - 2)
1609 return 0; /* No space left. */
252b5132 1610
4670103e 1611 if (cidx > ntok)
33eaf5de 1612 return 0; /* Incorrect args. */
252b5132 1613
4670103e 1614 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1615
4670103e
CZ		 1616 if (cidx == ntok)
1617 return 1; /* Success. */
1618 return allocate_tok (tok, ntok - 1, cidx);
1619}
886a2506 1620
8ddf6b2a
CZ		 1621/* Check if an particular ARC feature is enabled. */
1622
1623static bfd_boolean
1624check_cpu_feature (insn_subclass_t sc)
1625{
53a346d8 1626 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
8ddf6b2a
CZ		 1627 return FALSE;
1628
53a346d8 1629 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
8ddf6b2a
CZ		 1630 return FALSE;
1631
53a346d8 1632 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
8ddf6b2a
CZ		 1633 return FALSE;
1634
53a346d8 1635 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
bdd582db
GM		 1636 return FALSE;
1637
53a346d8 1638 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
8ddf6b2a
CZ		 1639 return FALSE;
1640
1641 return TRUE;
1642}
1643
4eb6f892
AB		 1644/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1645 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1646 array and returns TRUE if the flag operands all match, otherwise,
1647 returns FALSE, in which case the FIRST_PFLAG array may have been
1648 modified. */
1649
1650static bfd_boolean
1651parse_opcode_flags (const struct arc_opcode *opcode,
1652 int nflgs,
1653 struct arc_flags *first_pflag)
1654{
1655 int lnflg, i;
1656 const unsigned char *flgidx;
1657
1658 lnflg = nflgs;
1659 for (i = 0; i < nflgs; i++)
1660 first_pflag[i].flgp = NULL;
1661
1662 /* Check the flags. Iterate over the valid flag classes. */
1663 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1664 {
1665 /* Get a valid flag class. */
1666 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1667 const unsigned *flgopridx;
1668 int cl_matches = 0;
1669 struct arc_flags *pflag = NULL;
1670
6ec7c1ae
CZ		 1671 /* Check if opcode has implicit flag classes. */
1672 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1673 continue;
1674
4eb6f892
AB		 1675 /* Check for extension conditional codes. */
1676 if (ext_condcode.arc_ext_condcode
1677 && cl_flags->flag_class & F_CLASS_EXTEND)
1678 {
1679 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1680 while (pf->name)
1681 {
1682 pflag = first_pflag;
1683 for (i = 0; i < nflgs; i++, pflag++)
1684 {
1685 if (!strcmp (pf->name, pflag->name))
1686 {
1687 if (pflag->flgp != NULL)
1688 return FALSE;
1689 /* Found it. */
1690 cl_matches++;
1691 pflag->flgp = pf;
1692 lnflg--;
1693 break;
1694 }
1695 }
1696 pf++;
1697 }
1698 }
1699
1700 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1701 {
1702 const struct arc_flag_operand *flg_operand;
1703
1704 pflag = first_pflag;
1705 flg_operand = &arc_flag_operands[*flgopridx];
1706 for (i = 0; i < nflgs; i++, pflag++)
1707 {
1708 /* Match against the parsed flags. */
1709 if (!strcmp (flg_operand->name, pflag->name))
1710 {
1711 if (pflag->flgp != NULL)
1712 return FALSE;
1713 cl_matches++;
1714 pflag->flgp = flg_operand;
1715 lnflg--;
1716 break; /* goto next flag class and parsed flag. */
1717 }
1718 }
1719 }
1720
1721 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1722 return FALSE;
1723 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1724 return FALSE;
1725 }
1726
1727 /* Did I check all the parsed flags? */
1728 return lnflg ? FALSE : TRUE;
1729}
1730
1731
4670103e
CZ		 1732/* Search forward through all variants of an opcode looking for a
1733 syntax match. */
886a2506 1734
4670103e 1735static const struct arc_opcode *
b9b47ab7 1736find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1737 expressionS *tok,
1738 int *pntok,
1739 struct arc_flags *first_pflag,
1740 int nflgs,
abe7c33b
CZ		 1741 int *pcpumatch,
1742 const char **errmsg)
4670103e 1743{
1328504b
AB		 1744 const struct arc_opcode *opcode;
1745 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1746 int ntok = *pntok;
1747 int got_cpu_match = 0;
1748 expressionS bktok[MAX_INSN_ARGS];
1749 int bkntok;
1750 expressionS emptyE;
886a2506 1751
1328504b 1752 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1753 memset (&emptyE, 0, sizeof (emptyE));
1754 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1755 bkntok = ntok;
a161fe53 1756
1328504b
AB		 1757 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1758 opcode != NULL;
1759 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1760 {
4670103e 1761 const unsigned char *opidx;
4eb6f892 1762 int tokidx = 0;
4670103e 1763 const expressionS *t = &emptyE;
252b5132 1764
bdfe53e3 1765 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1766 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1767
4670103e
CZ		 1768 /* Don't match opcodes that don't exist on this
1769 architecture. */
bb65a718 1770 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1771 goto match_failed;
886a2506 1772
8ddf6b2a 1773 if (!check_cpu_feature (opcode->subclass))
4670103e 1774 goto match_failed;
886a2506 1775
4670103e
CZ		 1776 got_cpu_match = 1;
1777 pr_debug ("cpu ");
886a2506 1778
4670103e
CZ		 1779 /* Check the operands. */
1780 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1781 {
4670103e 1782 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1783
4670103e 1784 /* Only take input from real operands. */
db18dbab 1785 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1786 continue;
252b5132 1787
4670103e
CZ		 1788 /* When we expect input, make sure we have it. */
1789 if (tokidx >= ntok)
1790 goto match_failed;
6f4b1afc 1791
4670103e
CZ		 1792 /* Match operand type with expression type. */
1793 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1794 {
db18dbab 1795 case ARC_OPERAND_ADDRTYPE:
b437d035 1796 {
abe7c33b 1797 *errmsg = NULL;
b437d035
AB		 1798
1799 /* Check to be an address type. */
1800 if (tok[tokidx].X_op != O_addrtype)
1801 goto match_failed;
1802
1803 /* All address type operands need to have an insert
1804 method in order to check that we have the correct
1805 address type. */
1806 gas_assert (operand->insert != NULL);
1807 (*operand->insert) (0, tok[tokidx].X_add_number,
abe7c33b
CZ		 1808 errmsg);
1809 if (*errmsg != NULL)
b437d035
AB		 1810 goto match_failed;
1811 }
db18dbab
GM		 1812 break;
1813
4670103e
CZ		 1814 case ARC_OPERAND_IR:
1815 /* Check to be a register. */
1816 if ((tok[tokidx].X_op != O_register
1817 || !is_ir_num (tok[tokidx].X_add_number))
1818 && !(operand->flags & ARC_OPERAND_IGNORE))
1819 goto match_failed;
1820
1821 /* If expect duplicate, make sure it is duplicate. */
1822 if (operand->flags & ARC_OPERAND_DUPLICATE)
1823 {
1824 /* Check for duplicate. */
1825 if (t->X_op != O_register
1826 || !is_ir_num (t->X_add_number)
1827 || (regno (t->X_add_number) !=
1828 regno (tok[tokidx].X_add_number)))
1829 goto match_failed;
1830 }
1831
1832 /* Special handling? */
1833 if (operand->insert)
1834 {
abe7c33b 1835 *errmsg = NULL;
4670103e
CZ		 1836 (*operand->insert)(0,
1837 regno (tok[tokidx].X_add_number),
abe7c33b
CZ		 1838 errmsg);
1839 if (*errmsg)
4670103e
CZ		 1840 {
1841 if (operand->flags & ARC_OPERAND_IGNORE)
1842 {
1843 /* Missing argument, create one. */
1844 if (!allocate_tok (tok, ntok - 1, tokidx))
1845 goto match_failed;
1846
1847 tok[tokidx].X_op = O_absent;
1848 ++ntok;
1849 }
1850 else
1851 goto match_failed;
1852 }
1853 }
1854
1855 t = &tok[tokidx];
1856 break;
1857
1858 case ARC_OPERAND_BRAKET:
1859 /* Check if bracket is also in opcode table as
1860 operand. */
1861 if (tok[tokidx].X_op != O_bracket)
1862 goto match_failed;
1863 break;
1864
db18dbab
GM		 1865 case ARC_OPERAND_COLON:
1866 /* Check if colon is also in opcode table as operand. */
1867 if (tok[tokidx].X_op != O_colon)
1868 goto match_failed;
1869 break;
1870
4670103e
CZ		 1871 case ARC_OPERAND_LIMM:
1872 case ARC_OPERAND_SIGNED:
1873 case ARC_OPERAND_UNSIGNED:
1874 switch (tok[tokidx].X_op)
1875 {
1876 case O_illegal:
1877 case O_absent:
1878 case O_register:
1879 goto match_failed;
1880
1881 case O_bracket:
1882 /* Got an (too) early bracket, check if it is an
1883 ignored operand. N.B. This procedure works only
1884 when bracket is the last operand! */
1885 if (!(operand->flags & ARC_OPERAND_IGNORE))
1886 goto match_failed;
1887 /* Insert the missing operand. */
1888 if (!allocate_tok (tok, ntok - 1, tokidx))
1889 goto match_failed;
1890
1891 tok[tokidx].X_op = O_absent;
1892 ++ntok;
1893 break;
1894
22b92fc4
AB		 1895 case O_symbol:
1896 {
1897 const char *p;
22b92fc4 1898 const struct arc_aux_reg *auxr;
22b92fc4 1899
c810e0b8 1900 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1901 goto de_fault;
1902 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da
CZ		 1903
1904 auxr = hash_find (arc_aux_hash, p);
1905 if (auxr)
1906 {
1907 /* We modify the token array here, safe in the
1908 knowledge, that if this was the wrong
1909 choice then the original contents will be
1910 restored from BKTOK. */
1911 tok[tokidx].X_op = O_constant;
1912 tok[tokidx].X_add_number = auxr->address;
1913 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1914 }
22b92fc4
AB		 1915
1916 if (tok[tokidx].X_op != O_constant)
1917 goto de_fault;
1918 }
1a0670f3 1919 /* Fall through. */
4670103e
CZ		 1920 case O_constant:
1921 /* Check the range. */
1922 if (operand->bits != 32
1923 && !(operand->flags & ARC_OPERAND_NCHK))
1924 {
1925 offsetT min, max, val;
1926 val = tok[tokidx].X_add_number;
1927
1928 if (operand->flags & ARC_OPERAND_SIGNED)
1929 {
1930 max = (1 << (operand->bits - 1)) - 1;
1931 min = -(1 << (operand->bits - 1));
1932 }
1933 else
1934 {
1935 max = (1 << operand->bits) - 1;
1936 min = 0;
1937 }
1938
1939 if (val < min || val > max)
1940 goto match_failed;
1941
33eaf5de 1942 /* Check alignments. */
4670103e
CZ		 1943 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1944 && (val & 0x03))
1945 goto match_failed;
1946
1947 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1948 && (val & 0x01))
1949 goto match_failed;
1950 }
1951 else if (operand->flags & ARC_OPERAND_NCHK)
1952 {
1953 if (operand->insert)
1954 {
abe7c33b 1955 *errmsg = NULL;
4670103e
CZ		 1956 (*operand->insert)(0,
1957 tok[tokidx].X_add_number,
abe7c33b
CZ		 1958 errmsg);
1959 if (*errmsg)
4670103e
CZ		 1960 goto match_failed;
1961 }
4eb6f892 1962 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1963 goto match_failed;
1964 }
1965 break;
1966
1967 case O_subtract:
1968 /* Check if it is register range. */
1969 if ((tok[tokidx].X_add_number == 0)
1970 && contains_register (tok[tokidx].X_add_symbol)
1971 && contains_register (tok[tokidx].X_op_symbol))
1972 {
1973 int regs;
1974
1975 regs = get_register (tok[tokidx].X_add_symbol);
1976 regs <<= 16;
1977 regs |= get_register (tok[tokidx].X_op_symbol);
1978 if (operand->insert)
1979 {
abe7c33b 1980 *errmsg = NULL;
4670103e
CZ		 1981 (*operand->insert)(0,
1982 regs,
abe7c33b
CZ		 1983 errmsg);
1984 if (*errmsg)
4670103e
CZ		 1985 goto match_failed;
1986 }
1987 else
1988 goto match_failed;
1989 break;
1990 }
1a0670f3 1991 /* Fall through. */
4670103e 1992 default:
22b92fc4 1993 de_fault:
4670103e
CZ		 1994 if (operand->default_reloc == 0)
1995 goto match_failed; /* The operand needs relocation. */
1996
1997 /* Relocs requiring long immediate. FIXME! make it
1998 generic and move it to a function. */
1999 switch (tok[tokidx].X_md)
2000 {
2001 case O_gotoff:
2002 case O_gotpc:
2003 case O_pcl:
2004 case O_tpoff:
2005 case O_dtpoff:
2006 case O_tlsgd:
2007 case O_tlsie:
2008 if (!(operand->flags & ARC_OPERAND_LIMM))
2009 goto match_failed;
1a0670f3 2010 /* Fall through. */
4670103e
CZ		 2011 case O_absent:
2012 if (!generic_reloc_p (operand->default_reloc))
2013 goto match_failed;
2b804145 2014 break;
4670103e
CZ		 2015 default:
2016 break;
2017 }
2018 break;
2019 }
2020 /* If expect duplicate, make sure it is duplicate. */
2021 if (operand->flags & ARC_OPERAND_DUPLICATE)
2022 {
2023 if (t->X_op == O_illegal
2024 || t->X_op == O_absent
2025 || t->X_op == O_register
2026 || (t->X_add_number != tok[tokidx].X_add_number))
2027 goto match_failed;
2028 }
2029 t = &tok[tokidx];
2030 break;
2031
2032 default:
2033 /* Everything else should have been fake. */
2034 abort ();
2035 }
2036
2037 ++tokidx;
2038 }
2039 pr_debug ("opr ");
2040
1ae8ab47 2041 /* Setup ready for flag parsing. */
4eb6f892 2042 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 2043 goto match_failed;
2044
2045 pr_debug ("flg");
2046 /* Possible match -- did we use all of our input? */
2047 if (tokidx == ntok)
2048 {
2049 *pntok = ntok;
2050 pr_debug ("\n");
2051 return opcode;
2052 }
2053
2054 match_failed:;
2055 pr_debug ("\n");
2056 /* Restore the original parameters. */
2057 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2058 ntok = bkntok;
2059 }
4670103e
CZ		 2060
2061 if (*pcpumatch)
2062 *pcpumatch = got_cpu_match;
2063
2064 return NULL;
2065}
2066
2067/* Swap operand tokens. */
2068
2069static void
2070swap_operand (expressionS *operand_array,
2071 unsigned source,
2072 unsigned destination)
2073{
2074 expressionS cpy_operand;
2075 expressionS *src_operand;
2076 expressionS *dst_operand;
2077 size_t size;
2078
2079 if (source == destination)
2080 return;
2081
2082 src_operand = &operand_array[source];
2083 dst_operand = &operand_array[destination];
2084 size = sizeof (expressionS);
2085
2086 /* Make copy of operand to swap with and swap. */
2087 memcpy (&cpy_operand, dst_operand, size);
2088 memcpy (dst_operand, src_operand, size);
2089 memcpy (src_operand, &cpy_operand, size);
2090}
2091
2092/* Check if *op matches *tok type.
2093 Returns FALSE if they don't match, TRUE if they match. */
2094
2095static bfd_boolean
2096pseudo_operand_match (const expressionS *tok,
2097 const struct arc_operand_operation *op)
2098{
2099 offsetT min, max, val;
2100 bfd_boolean ret;
2101 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2102
2103 ret = FALSE;
2104 switch (tok->X_op)
2105 {
2106 case O_constant:
2107 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2108 ret = 1;
2109 else if (!(operand_real->flags & ARC_OPERAND_IR))
2110 {
2111 val = tok->X_add_number + op->count;
2112 if (operand_real->flags & ARC_OPERAND_SIGNED)
2113 {
2114 max = (1 << (operand_real->bits - 1)) - 1;
2115 min = -(1 << (operand_real->bits - 1));
2116 }
2117 else
2118 {
2119 max = (1 << operand_real->bits) - 1;
2120 min = 0;
2121 }
2122 if (min <= val && val <= max)
2123 ret = TRUE;
2124 }
6f4b1afc
CM		 2125 break;
2126
4670103e
CZ		 2127 case O_symbol:
2128 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2129 if (operand_real->flags & ARC_OPERAND_LIMM
2130 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2131 && operand_real->bits == 9))
4670103e 2132 ret = TRUE;
6f4b1afc
CM		 2133 break;
2134
4670103e
CZ		 2135 case O_register:
2136 if (operand_real->flags & ARC_OPERAND_IR)
2137 ret = TRUE;
2138 break;
2139
2140 case O_bracket:
2141 if (operand_real->flags & ARC_OPERAND_BRAKET)
2142 ret = TRUE;
6f4b1afc
CM		 2143 break;
2144
2145 default:
4670103e 2146 /* Unknown. */
6f4b1afc
CM		 2147 break;
2148 }
4670103e
CZ		 2149 return ret;
2150}
6f4b1afc 2151
4670103e
CZ		 2152/* Find pseudo instruction in array. */
2153
2154static const struct arc_pseudo_insn *
2155find_pseudo_insn (const char *opname,
2156 int ntok,
2157 const expressionS *tok)
2158{
2159 const struct arc_pseudo_insn *pseudo_insn = NULL;
2160 const struct arc_operand_operation *op;
2161 unsigned int i;
2162 int j;
2163
2164 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2165 {
4670103e
CZ		 2166 pseudo_insn = &arc_pseudo_insns[i];
2167 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2168 {
2169 op = pseudo_insn->operand;
2170 for (j = 0; j < ntok; ++j)
2171 if (!pseudo_operand_match (&tok[j], &op[j]))
2172 break;
2173
2174 /* Found the right instruction. */
2175 if (j == ntok)
2176 return pseudo_insn;
2177 }
6f4b1afc 2178 }
4670103e
CZ		 2179 return NULL;
2180}
252b5132 2181
4670103e 2182/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2183
b9b47ab7 2184static const struct arc_opcode_hash_entry *
4670103e
CZ		 2185find_special_case_pseudo (const char *opname,
2186 int *ntok,
2187 expressionS *tok,
2188 int *nflgs,
2189 struct arc_flags *pflags)
2190{
2191 const struct arc_pseudo_insn *pseudo_insn = NULL;
2192 const struct arc_operand_operation *operand_pseudo;
2193 const struct arc_operand *operand_real;
2194 unsigned i;
2195 char construct_operand[MAX_CONSTR_STR];
886a2506 2196
4670103e
CZ		 2197 /* Find whether opname is in pseudo instruction array. */
2198 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2199
2200 if (pseudo_insn == NULL)
2201 return NULL;
2202
2203 /* Handle flag, Limited to one flag at the moment. */
2204 if (pseudo_insn->flag_r != NULL)
2205 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2206 MAX_INSN_FLGS - *nflgs);
2207
2208 /* Handle operand operations. */
2209 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2210 {
4670103e
CZ		 2211 operand_pseudo = &pseudo_insn->operand[i];
2212 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2213
db18dbab
GM		 2214 if (operand_real->flags & ARC_OPERAND_BRAKET
2215 && !operand_pseudo->needs_insert)
4670103e 2216 continue;
b125bd17 2217
4670103e
CZ		 2218 /* Has to be inserted (i.e. this token does not exist yet). */
2219 if (operand_pseudo->needs_insert)
2220 {
2221 if (operand_real->flags & ARC_OPERAND_BRAKET)
2222 {
2223 tok[i].X_op = O_bracket;
2224 ++(*ntok);
2225 continue;
2226 }
b125bd17 2227
4670103e
CZ		 2228 /* Check if operand is a register or constant and handle it
2229 by type. */
2230 if (operand_real->flags & ARC_OPERAND_IR)
2231 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2232 operand_pseudo->count);
2233 else
2234 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2235 operand_pseudo->count);
886a2506 2236
4670103e
CZ		 2237 tokenize_arguments (construct_operand, &tok[i], 1);
2238 ++(*ntok);
2239 }
2240
2241 else if (operand_pseudo->count)
2242 {
2243 /* Operand number has to be adjusted accordingly (by operand
2244 type). */
2245 switch (tok[i].X_op)
2246 {
2247 case O_constant:
2248 tok[i].X_add_number += operand_pseudo->count;
2249 break;
2250
2251 case O_symbol:
2252 break;
2253
2254 default:
2255 /* Ignored. */
2256 break;
2257 }
2258 }
2259 }
2260
2261 /* Swap operands if necessary. Only supports one swap at the
2262 moment. */
2263 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2264 {
2265 operand_pseudo = &pseudo_insn->operand[i];
2266
2267 if (operand_pseudo->swap_operand_idx == i)
2268 continue;
2269
2270 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2271
2272 /* Prevent a swap back later by breaking out. */
2273 break;
2274 }
2275
da5be039 2276 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2277}
2278
b9b47ab7 2279static const struct arc_opcode_hash_entry *
4670103e
CZ		 2280find_special_case_flag (const char *opname,
2281 int *nflgs,
2282 struct arc_flags *pflags)
2283{
2284 unsigned int i;
2285 const char *flagnm;
2286 unsigned flag_idx, flag_arr_idx;
2287 size_t flaglen, oplen;
2288 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2289 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2290
2291 /* Search for special case instruction. */
2292 for (i = 0; i < arc_num_flag_special; i++)
2293 {
2294 arc_flag_special_opcode = &arc_flag_special_cases[i];
2295 oplen = strlen (arc_flag_special_opcode->name);
2296
2297 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2298 continue;
2299
2300 /* Found a potential special case instruction, now test for
2301 flags. */
2302 for (flag_arr_idx = 0;; ++flag_arr_idx)
2303 {
2304 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2305 if (flag_idx == 0)
2306 break; /* End of array, nothing found. */
886a2506 2307
4670103e
CZ		 2308 flagnm = arc_flag_operands[flag_idx].name;
2309 flaglen = strlen (flagnm);
2310 if (strcmp (opname + oplen, flagnm) == 0)
2311 {
b9b47ab7 2312 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2313
4670103e
CZ		 2314 if (*nflgs + 1 > MAX_INSN_FLGS)
2315 break;
2316 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2317 pflags[*nflgs].name[flaglen] = '\0';
2318 (*nflgs)++;
b9b47ab7 2319 return entry;
4670103e
CZ		 2320 }
2321 }
2322 }
2323 return NULL;
2324}
886a2506 2325
4670103e 2326/* Used to find special case opcode. */
886a2506 2327
b9b47ab7 2328static const struct arc_opcode_hash_entry *
4670103e
CZ		 2329find_special_case (const char *opname,
2330 int *nflgs,
2331 struct arc_flags *pflags,
2332 expressionS *tok,
2333 int *ntok)
2334{
b9b47ab7 2335 const struct arc_opcode_hash_entry *entry;
886a2506 2336
b9b47ab7 2337 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2338
b9b47ab7
AB		 2339 if (entry == NULL)
2340 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2341
b9b47ab7 2342 return entry;
4670103e 2343}
886a2506 2344
53a346d8
CZ		 2345/* Autodetect cpu attribute list. */
2346
2347static void
2348autodetect_attributes (const struct arc_opcode *opcode,
2349 const expressionS *tok,
2350 int ntok)
2351{
2352 unsigned i;
2353 struct mpy_type
2354 {
2355 unsigned feature;
2356 unsigned encoding;
2357 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2358 { MPY9E, 9 }};
2359
2360 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2361 if (opcode->subclass == feature_list[i].feature)
2362 selected_cpu.features |= feature_list[i].feature;
2363
2364 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2365 if (opcode->subclass == mpy_list[i].feature)
2366 mpy_option = mpy_list[i].encoding;
2367
2368 for (i = 0; i < (unsigned) ntok; i++)
2369 {
2370 switch (tok[i].X_md)
2371 {
2372 case O_gotoff:
2373 case O_gotpc:
2374 case O_plt:
2375 pic_option = 2;
2376 break;
2377 case O_sda:
2378 sda_option = 2;
2379 break;
2380 case O_tlsgd:
2381 case O_tlsie:
2382 case O_tpoff9:
2383 case O_tpoff:
2384 case O_dtpoff9:
2385 case O_dtpoff:
2386 tls_option = 1;
2387 break;
2388 default:
2389 break;
2390 }
2391 }
2392}
2393
2394/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2395 opcode flags, take it all the way through emission. */
886a2506 2396
4670103e
CZ		 2397static void
2398assemble_tokens (const char *opname,
2399 expressionS *tok,
2400 int ntok,
2401 struct arc_flags *pflags,
2402 int nflgs)
2403{
2404 bfd_boolean found_something = FALSE;
b9b47ab7 2405 const struct arc_opcode_hash_entry *entry;
4670103e 2406 int cpumatch = 1;
abe7c33b 2407 const char *errmsg = NULL;
886a2506 2408
4670103e 2409 /* Search opcodes. */
b9b47ab7 2410 entry = arc_find_opcode (opname);
886a2506 2411
4670103e 2412 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2413 if (entry == NULL)
2414 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2415
b9b47ab7 2416 if (entry != NULL)
4670103e 2417 {
b9b47ab7
AB		 2418 const struct arc_opcode *opcode;
2419
1328504b
AB		 2420 pr_debug ("%s:%d: assemble_tokens: %s\n",
2421 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2422 found_something = TRUE;
b9b47ab7 2423 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2424 nflgs, &cpumatch, &errmsg);
b9b47ab7 2425 if (opcode != NULL)
4670103e
CZ		 2426 {
2427 struct arc_insn insn;
b9b47ab7 2428
53a346d8 2429 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2430 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2431 emit_insn (&insn);
2432 return;
2433 }
2434 }
886a2506 2435
4670103e
CZ		 2436 if (found_something)
2437 {
2438 if (cpumatch)
abe7c33b
CZ		 2439 if (errmsg)
2440 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2441 else
2442 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2443 else
2444 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2445 selected_cpu.name);
4670103e
CZ		 2446 }
2447 else
2448 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2449}
2450
4670103e 2451/* The public interface to the instruction assembler. */
886a2506 2452
4670103e
CZ		 2453void
2454md_assemble (char *str)
886a2506 2455{
4670103e
CZ		 2456 char *opname;
2457 expressionS tok[MAX_INSN_ARGS];
2458 int ntok, nflg;
2459 size_t opnamelen;
2460 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2461
4670103e
CZ		 2462 /* Split off the opcode. */
2463 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2464 opname = xmemdup0 (str, opnamelen);
886a2506 2465
33eaf5de 2466 /* Signalize we are assembling the instructions. */
4670103e 2467 assembling_insn = TRUE;
886a2506 2468
4670103e
CZ		 2469 /* Tokenize the flags. */
2470 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2471 {
2472 as_bad (_("syntax error"));
2473 return;
2474 }
886a2506 2475
4670103e
CZ		 2476 /* Scan up to the end of the mnemonic which must end in space or end
2477 of string. */
2478 str += opnamelen;
2479 for (; *str != '\0'; str++)
2480 if (*str == ' ')
2481 break;
886a2506 2482
4670103e
CZ		 2483 /* Tokenize the rest of the line. */
2484 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2485 {
4670103e
CZ		 2486 as_bad (_("syntax error"));
2487 return;
252b5132
RH		 2488 }
2489
4670103e
CZ		 2490 /* Finish it off. */
2491 assemble_tokens (opname, tok, ntok, flags, nflg);
2492 assembling_insn = FALSE;
2493}
2494
2495/* Callback to insert a register into the hash table. */
2496
2497static void
f86f5863 2498declare_register (const char *name, int number)
4670103e
CZ		 2499{
2500 const char *err;
2501 symbolS *regS = symbol_create (name, reg_section,
2502 number, &zero_address_frag);
2503
2504 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2505 if (err)
e6ba1cba 2506 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2507 name, err);
2508}
252b5132 2509
4670103e 2510/* Construct symbols for each of the general registers. */
252b5132 2511
4670103e
CZ		 2512static void
2513declare_register_set (void)
2514{
2515 int i;
2516 for (i = 0; i < 64; ++i)
886a2506 2517 {
4670103e
CZ		 2518 char name[7];
2519
2520 sprintf (name, "r%d", i);
2521 declare_register (name, i);
2522 if ((i & 0x01) == 0)
886a2506 2523 {
4670103e
CZ		 2524 sprintf (name, "r%dr%d", i, i+1);
2525 declare_register (name, i);
886a2506
NC		 2526 }
2527 }
252b5132 2528}
ea1562b3 2529
db18dbab
GM		 2530/* Construct a symbol for an address type. */
2531
2532static void
2533declare_addrtype (const char *name, int number)
2534{
2535 const char *err;
2536 symbolS *addrtypeS = symbol_create (name, undefined_section,
2537 number, &zero_address_frag);
2538
2539 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2540 (void *) addrtypeS);
2541 if (err)
2542 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2543 name, err);
2544}
2545
4670103e
CZ		 2546/* Port-specific assembler initialization. This function is called
2547 once, at assembler startup time. */
ea1562b3
NC		 2548
2549void
4670103e 2550md_begin (void)
ea1562b3 2551{
b99747ae 2552 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2553
bb65a718
AB		 2554 if (mach_selection_mode == MACH_SELECTION_NONE)
2555 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2556
4670103e
CZ		 2557 /* The endianness can be chosen "at the factory". */
2558 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2559
bb65a718 2560 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2561 as_warn (_("could not set architecture and machine"));
2562
2563 /* Set elf header flags. */
bb65a718 2564 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2565
2566 /* Set up a hash table for the instructions. */
2567 arc_opcode_hash = hash_new ();
2568 if (arc_opcode_hash == NULL)
2569 as_fatal (_("Virtual memory exhausted"));
2570
2571 /* Initialize the hash table with the insns. */
b99747ae 2572 do
ea1562b3 2573 {
b99747ae 2574 const char *name = opcode->name;
da5be039 2575
b99747ae 2576 arc_insert_opcode (opcode);
4670103e 2577
b99747ae
CZ		 2578 while (++opcode && opcode->name
2579 && (opcode->name == name
2580 || !strcmp (opcode->name, name)))
4670103e 2581 continue;
b99747ae 2582 }while (opcode->name);
4670103e
CZ		 2583
2584 /* Register declaration. */
2585 arc_reg_hash = hash_new ();
2586 if (arc_reg_hash == NULL)
2587 as_fatal (_("Virtual memory exhausted"));
2588
2589 declare_register_set ();
2590 declare_register ("gp", 26);
2591 declare_register ("fp", 27);
2592 declare_register ("sp", 28);
2593 declare_register ("ilink", 29);
2594 declare_register ("ilink1", 29);
2595 declare_register ("ilink2", 30);
2596 declare_register ("blink", 31);
2597
87789e08
CZ		 2598 /* XY memory registers. */
2599 declare_register ("x0_u0", 32);
2600 declare_register ("x0_u1", 33);
2601 declare_register ("x1_u0", 34);
2602 declare_register ("x1_u1", 35);
2603 declare_register ("x2_u0", 36);
2604 declare_register ("x2_u1", 37);
2605 declare_register ("x3_u0", 38);
2606 declare_register ("x3_u1", 39);
2607 declare_register ("y0_u0", 40);
2608 declare_register ("y0_u1", 41);
2609 declare_register ("y1_u0", 42);
2610 declare_register ("y1_u1", 43);
2611 declare_register ("y2_u0", 44);
2612 declare_register ("y2_u1", 45);
2613 declare_register ("y3_u0", 46);
2614 declare_register ("y3_u1", 47);
2615 declare_register ("x0_nu", 48);
2616 declare_register ("x1_nu", 49);
2617 declare_register ("x2_nu", 50);
2618 declare_register ("x3_nu", 51);
2619 declare_register ("y0_nu", 52);
2620 declare_register ("y1_nu", 53);
2621 declare_register ("y2_nu", 54);
2622 declare_register ("y3_nu", 55);
2623
4670103e
CZ		 2624 declare_register ("mlo", 57);
2625 declare_register ("mmid", 58);
2626 declare_register ("mhi", 59);
2627
2628 declare_register ("acc1", 56);
2629 declare_register ("acc2", 57);
2630
2631 declare_register ("lp_count", 60);
2632 declare_register ("pcl", 63);
2633
2634 /* Initialize the last instructions. */
2635 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2636
2637 /* Aux register declaration. */
2638 arc_aux_hash = hash_new ();
2639 if (arc_aux_hash == NULL)
2640 as_fatal (_("Virtual memory exhausted"));
2641
2642 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2643 unsigned int i;
2644 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2645 {
2646 const char *retval;
2647
bb65a718 2648 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2649 continue;
2650
2651 if ((auxr->subclass != NONE)
2652 && !check_cpu_feature (auxr->subclass))
2653 continue;
2654
2655 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2656 if (retval)
2657 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2658 auxr->name, retval);
2659 }
db18dbab
GM		 2660
2661 /* Address type declaration. */
2662 arc_addrtype_hash = hash_new ();
2663 if (arc_addrtype_hash == NULL)
2664 as_fatal (_("Virtual memory exhausted"));
2665
2666 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2667 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2668 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2669 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2670 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2671 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2672 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2673 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2674 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2675 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2676 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2677 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2678 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2679 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2680 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2681 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2682}
ea1562b3 2683
4670103e
CZ		 2684/* Write a value out to the object file, using the appropriate
2685 endianness. */
ea1562b3 2686
4670103e
CZ		 2687void
2688md_number_to_chars (char *buf,
2689 valueT val,
2690 int n)
886a2506 2691{
4670103e
CZ		 2692 if (target_big_endian)
2693 number_to_chars_bigendian (buf, val, n);
2694 else
2695 number_to_chars_littleendian (buf, val, n);
886a2506 2696}
ea1562b3 2697
4670103e 2698/* Round up a section size to the appropriate boundary. */
ea1562b3 2699
4670103e
CZ		 2700valueT
2701md_section_align (segT segment,
2702 valueT size)
886a2506 2703{
4670103e
CZ		 2704 int align = bfd_get_section_alignment (stdoutput, segment);
2705
2706 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2707}
ea1562b3 2708
4670103e
CZ		 2709/* The location from which a PC relative jump should be calculated,
2710 given a PC relative reloc. */
ea1562b3 2711
4670103e
CZ		 2712long
2713md_pcrel_from_section (fixS *fixP,
2714 segT sec)
886a2506 2715{
4670103e 2716 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2717
4670103e 2718 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2719
4670103e
CZ		 2720 if (fixP->fx_addsy != (symbolS *) NULL
2721 && (!S_IS_DEFINED (fixP->fx_addsy)
2722 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2723 {
2724 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2725
4670103e
CZ		 2726 /* The symbol is undefined (or is defined but not in this section).
2727 Let the linker figure it out. */
2728 return 0;
2729 }
2730
2731 if ((int) fixP->fx_r_type < 0)
886a2506 2732 {
4670103e
CZ		 2733 /* These are the "internal" relocations. Align them to
2734 32 bit boundary (PCL), for the moment. */
2735 base &= ~3;
886a2506 2736 }
4670103e
CZ		 2737 else
2738 {
2739 switch (fixP->fx_r_type)
2740 {
2741 case BFD_RELOC_ARC_PC32:
2742 /* The hardware calculates relative to the start of the
2743 insn, but this relocation is relative to location of the
2744 LIMM, compensate. The base always needs to be
2b0f3761 2745 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2746 relocation for short instructions. */
2747 base -= 4;
2748 /* Fall through. */
2749 case BFD_RELOC_ARC_PLT32:
2750 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2751 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2752 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2753 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2754
2755 case BFD_RELOC_ARC_S21H_PCREL:
2756 case BFD_RELOC_ARC_S25H_PCREL:
2757 case BFD_RELOC_ARC_S13_PCREL:
2758 case BFD_RELOC_ARC_S21W_PCREL:
2759 case BFD_RELOC_ARC_S25W_PCREL:
2760 base &= ~3;
2761 break;
2762 default:
2763 as_bad_where (fixP->fx_file, fixP->fx_line,
2764 _("unhandled reloc %s in md_pcrel_from_section"),
2765 bfd_get_reloc_code_name (fixP->fx_r_type));
2766 break;
2767 }
2768 }
2769
9e32d9ae
AB		 2770 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2771 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2772 fixP->fx_frag->fr_address, fixP->fx_where, base,
2773 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2774 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2775
2776 return base;
886a2506 2777}
ea1562b3 2778
33eaf5de 2779/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2780
4670103e
CZ		 2781static const struct arc_operand *
2782find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2783{
2784 unsigned i;
ea1562b3 2785
4670103e
CZ		 2786 for (i = 0; i < arc_num_operands; i++)
2787 if (arc_operands[i].default_reloc == reloc)
2788 return &arc_operands[i];
2789 return NULL;
2790}
ea1562b3 2791
4670103e 2792/* Insert an operand value into an instruction. */
ea1562b3 2793
bdfe53e3
AB		 2794static unsigned long long
2795insert_operand (unsigned long long insn,
4670103e 2796 const struct arc_operand *operand,
bdfe53e3 2797 long long val,
3b4dbbbf 2798 const char *file,
4670103e 2799 unsigned line)
886a2506 2800{
4670103e 2801 offsetT min = 0, max = 0;
ea1562b3 2802
4670103e
CZ		 2803 if (operand->bits != 32
2804 && !(operand->flags & ARC_OPERAND_NCHK)
2805 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2806 {
4670103e
CZ		 2807 if (operand->flags & ARC_OPERAND_SIGNED)
2808 {
2809 max = (1 << (operand->bits - 1)) - 1;
2810 min = -(1 << (operand->bits - 1));
2811 }
2812 else
2813 {
2814 max = (1 << operand->bits) - 1;
2815 min = 0;
2816 }
886a2506 2817
4670103e
CZ		 2818 if (val < min || val > max)
2819 as_bad_value_out_of_range (_("operand"),
2820 val, min, max, file, line);
2821 }
ea1562b3 2822
cc07cda6 2823 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2824 min, val, max, insn);
ea1562b3 2825
4670103e
CZ		 2826 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2827 && (val & 0x03))
2828 as_bad_where (file, line,
2829 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2830
4670103e
CZ		 2831 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2832 && (val & 0x01))
2833 as_bad_where (file, line,
2834 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2835
4670103e
CZ		 2836 if (operand->insert)
2837 {
2838 const char *errmsg = NULL;
ea1562b3 2839
4670103e
CZ		 2840 insn = (*operand->insert) (insn, val, &errmsg);
2841 if (errmsg)
2842 as_warn_where (file, line, "%s", errmsg);
2843 }
2844 else
2845 {
2846 if (operand->flags & ARC_OPERAND_TRUNCATE)
2847 {
2848 if (operand->flags & ARC_OPERAND_ALIGNED32)
2849 val >>= 2;
2850 if (operand->flags & ARC_OPERAND_ALIGNED16)
2851 val >>= 1;
886a2506 2852 }
4670103e
CZ		 2853 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2854 }
2855 return insn;
2856}
ea1562b3 2857
4670103e
CZ		 2858/* Apply a fixup to the object code. At this point all symbol values
2859 should be fully resolved, and we attempt to completely resolve the
2860 reloc. If we can not do that, we determine the correct reloc code
2861 and put it back in the fixup. To indicate that a fixup has been
2862 eliminated, set fixP->fx_done. */
ea1562b3 2863
4670103e
CZ		 2864void
2865md_apply_fix (fixS *fixP,
2866 valueT *valP,
2867 segT seg)
2868{
2869 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2870 valueT value = *valP;
2871 unsigned insn = 0;
2872 symbolS *fx_addsy, *fx_subsy;
2873 offsetT fx_offset;
2874 segT add_symbol_segment = absolute_section;
2875 segT sub_symbol_segment = absolute_section;
2876 const struct arc_operand *operand = NULL;
2877 extended_bfd_reloc_code_real_type reloc;
886a2506 2878
4670103e
CZ		 2879 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2880 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2881 ((int) fixP->fx_r_type < 0) ? "Internal":
2882 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2883 fixP->fx_offset);
886a2506 2884
4670103e
CZ		 2885 fx_addsy = fixP->fx_addsy;
2886 fx_subsy = fixP->fx_subsy;
2887 fx_offset = 0;
886a2506 2888
4670103e
CZ		 2889 if (fx_addsy)
2890 {
2891 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2892 }
2893
4670103e
CZ		 2894 if (fx_subsy
2895 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2896 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2897 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2898 {
2899 resolve_symbol_value (fx_subsy);
2900 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2901
4670103e
CZ		 2902 if (sub_symbol_segment == absolute_section)
2903 {
2904 /* The symbol is really a constant. */
2905 fx_offset -= S_GET_VALUE (fx_subsy);
2906 fx_subsy = NULL;
2907 }
2908 else
2909 {
2910 as_bad_where (fixP->fx_file, fixP->fx_line,
2911 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2912 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2913 segment_name (add_symbol_segment),
2914 S_GET_NAME (fx_subsy),
2915 segment_name (sub_symbol_segment));
2916 return;
2917 }
2918 }
886a2506 2919
4670103e
CZ		 2920 if (fx_addsy
2921 && !S_IS_WEAK (fx_addsy))
2922 {
2923 if (add_symbol_segment == seg
2924 && fixP->fx_pcrel)
2925 {
2926 value += S_GET_VALUE (fx_addsy);
2927 value -= md_pcrel_from_section (fixP, seg);
2928 fx_addsy = NULL;
2929 fixP->fx_pcrel = FALSE;
2930 }
2931 else if (add_symbol_segment == absolute_section)
2932 {
2933 value = fixP->fx_offset;
2934 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2935 fx_addsy = NULL;
2936 fixP->fx_pcrel = FALSE;
2937 }
2938 }
886a2506 2939
4670103e
CZ		 2940 if (!fx_addsy)
2941 fixP->fx_done = TRUE;
886a2506 2942
4670103e 2943 if (fixP->fx_pcrel)
886a2506 2944 {
4670103e
CZ		 2945 if (fx_addsy
2946 && ((S_IS_DEFINED (fx_addsy)
2947 && S_GET_SEGMENT (fx_addsy) != seg)
2948 || S_IS_WEAK (fx_addsy)))
2949 value += md_pcrel_from_section (fixP, seg);
886a2506 2950
4670103e
CZ		 2951 switch (fixP->fx_r_type)
2952 {
2953 case BFD_RELOC_ARC_32_ME:
2954 /* This is a pc-relative value in a LIMM. Adjust it to the
2955 address of the instruction not to the address of the
33eaf5de 2956 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2957 the linker consider ARC_PC32 a fixup to entire 64 bit
2958 insn. */
2959 fixP->fx_offset += fixP->fx_frag->fr_address;
2960 /* Fall through. */
2961 case BFD_RELOC_32:
2962 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2963 /* Fall through. */
2964 case BFD_RELOC_ARC_PC32:
2965 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2966 break;
2967 default:
4670103e
CZ		 2968 if ((int) fixP->fx_r_type < 0)
2969 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2970 fixP->fx_r_type);
886a2506 2971 break;
ea1562b3
NC		 2972 }
2973 }
2974
4670103e
CZ		 2975 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2976 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2977 ((int) fixP->fx_r_type < 0) ? "Internal":
2978 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2979 fixP->fx_offset);
886a2506 2980
886a2506 2981
4670103e
CZ		 2982 /* Now check for TLS relocations. */
2983 reloc = fixP->fx_r_type;
2984 switch (reloc)
886a2506 2985 {
4670103e
CZ		 2986 case BFD_RELOC_ARC_TLS_DTPOFF:
2987 case BFD_RELOC_ARC_TLS_LE_32:
2988 if (fixP->fx_done)
2989 break;
2990 /* Fall through. */
2991 case BFD_RELOC_ARC_TLS_GD_GOT:
2992 case BFD_RELOC_ARC_TLS_IE_GOT:
2993 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2994 break;
886a2506 2995
4670103e
CZ		 2996 case BFD_RELOC_ARC_TLS_GD_LD:
2997 gas_assert (!fixP->fx_offset);
2998 if (fixP->fx_subsy)
2999 fixP->fx_offset
3000 = (S_GET_VALUE (fixP->fx_subsy)
3001 - fixP->fx_frag->fr_address- fixP->fx_where);
3002 fixP->fx_subsy = NULL;
3003 /* Fall through. */
3004 case BFD_RELOC_ARC_TLS_GD_CALL:
3005 /* These two relocs are there just to allow ld to change the tls
3006 model for this symbol, by patching the code. The offset -
3007 and scale, if any - will be installed by the linker. */
3008 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3009 break;
886a2506 3010
4670103e
CZ		 3011 case BFD_RELOC_ARC_TLS_LE_S9:
3012 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3013 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3014 break;
3015
3016 default:
3017 break;
886a2506
NC		 3018 }
3019
4670103e 3020 if (!fixP->fx_done)
886a2506 3021 {
4670103e 3022 return;
886a2506 3023 }
886a2506 3024
33eaf5de 3025 /* Adjust the value if we have a constant. */
4670103e 3026 value += fx_offset;
886a2506 3027
4670103e
CZ		 3028 /* For hosts with longs bigger than 32-bits make sure that the top
3029 bits of a 32-bit negative value read in by the parser are set,
3030 so that the correct comparisons are made. */
3031 if (value & 0x80000000)
69c9e028 3032 value |= (-1UL << 31);
886a2506 3033
4670103e
CZ		 3034 reloc = fixP->fx_r_type;
3035 switch (reloc)
3036 {
3037 case BFD_RELOC_8:
3038 case BFD_RELOC_16:
3039 case BFD_RELOC_24:
3040 case BFD_RELOC_32:
3041 case BFD_RELOC_64:
3042 case BFD_RELOC_ARC_32_PCREL:
3043 md_number_to_chars (fixpos, value, fixP->fx_size);
3044 return;
886a2506 3045
4670103e
CZ		 3046 case BFD_RELOC_ARC_GOTPC32:
3047 /* I cannot fix an GOTPC relocation because I need to relax it
3048 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3049 as_bad (_("Unsupported operation on reloc"));
3050 return;
886a2506 3051
4670103e
CZ		 3052 case BFD_RELOC_ARC_TLS_DTPOFF:
3053 case BFD_RELOC_ARC_TLS_LE_32:
3054 gas_assert (!fixP->fx_addsy);
3055 gas_assert (!fixP->fx_subsy);
1a0670f3 3056 /* Fall through. */
886a2506 3057
4670103e
CZ		 3058 case BFD_RELOC_ARC_GOTOFF:
3059 case BFD_RELOC_ARC_32_ME:
3060 case BFD_RELOC_ARC_PC32:
3061 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3062 return;
886a2506 3063
4670103e
CZ		 3064 case BFD_RELOC_ARC_PLT32:
3065 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3066 return;
886a2506 3067
4670103e
CZ		 3068 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3069 reloc = BFD_RELOC_ARC_S25W_PCREL;
3070 goto solve_plt;
886a2506 3071
4670103e
CZ		 3072 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3073 reloc = BFD_RELOC_ARC_S21H_PCREL;
3074 goto solve_plt;
886a2506 3075
4670103e
CZ		 3076 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3077 reloc = BFD_RELOC_ARC_S25W_PCREL;
3078 goto solve_plt;
886a2506 3079
4670103e
CZ		 3080 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3081 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3082 /* Fall through. */
886a2506 3083
4670103e
CZ		 3084 case BFD_RELOC_ARC_S25W_PCREL:
3085 case BFD_RELOC_ARC_S21W_PCREL:
3086 case BFD_RELOC_ARC_S21H_PCREL:
3087 case BFD_RELOC_ARC_S25H_PCREL:
3088 case BFD_RELOC_ARC_S13_PCREL:
3089 solve_plt:
3090 operand = find_operand_for_reloc (reloc);
3091 gas_assert (operand);
886a2506
NC		 3092 break;
3093
3094 default:
4670103e
CZ		 3095 {
3096 if ((int) fixP->fx_r_type >= 0)
3097 as_fatal (_("unhandled relocation type %s"),
3098 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3099
4670103e
CZ		 3100 /* The rest of these fixups needs to be completely resolved as
3101 constants. */
3102 if (fixP->fx_addsy != 0
3103 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3104 as_bad_where (fixP->fx_file, fixP->fx_line,
3105 _("non-absolute expression in constant field"));
886a2506 3106
4670103e
CZ		 3107 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3108 operand = &arc_operands[-(int) fixP->fx_r_type];
3109 break;
3110 }
3111 }
886a2506 3112
4670103e 3113 if (target_big_endian)
886a2506 3114 {
4670103e 3115 switch (fixP->fx_size)
886a2506 3116 {
4670103e
CZ		 3117 case 4:
3118 insn = bfd_getb32 (fixpos);
3119 break;
3120 case 2:
3121 insn = bfd_getb16 (fixpos);
3122 break;
3123 default:
3124 as_bad_where (fixP->fx_file, fixP->fx_line,
3125 _("unknown fixup size"));
3126 }
3127 }
3128 else
3129 {
3130 insn = 0;
3131 switch (fixP->fx_size)
3132 {
3133 case 4:
3134 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3135 break;
3136 case 2:
3137 insn = bfd_getl16 (fixpos);
3138 break;
3139 default:
3140 as_bad_where (fixP->fx_file, fixP->fx_line,
3141 _("unknown fixup size"));
886a2506
NC		 3142 }
3143 }
886a2506 3144
4670103e
CZ		 3145 insn = insert_operand (insn, operand, (offsetT) value,
3146 fixP->fx_file, fixP->fx_line);
886a2506 3147
4670103e
CZ		 3148 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3149}
886a2506 3150
4670103e 3151/* Prepare machine-dependent frags for relaxation.
886a2506 3152
4670103e
CZ		 3153 Called just before relaxation starts. Any symbol that is now undefined
3154 will not become defined.
886a2506 3155
4670103e 3156 Return the correct fr_subtype in the frag.
886a2506 3157
4670103e
CZ		 3158 Return the initial "guess for fr_var" to caller. The guess for fr_var
3159 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3160 or fr_var contributes to our returned value.
886a2506 3161
4670103e
CZ		 3162 Although it may not be explicit in the frag, pretend
3163 fr_var starts with a value. */
886a2506 3164
4670103e
CZ		 3165int
3166md_estimate_size_before_relax (fragS *fragP,
3167 segT segment)
3168{
3169 int growth;
3170
3171 /* If the symbol is not located within the same section AND it's not
3172 an absolute section, use the maximum. OR if the symbol is a
3173 constant AND the insn is by nature not pc-rel, use the maximum.
3174 OR if the symbol is being equated against another symbol, use the
3175 maximum. OR if the symbol is weak use the maximum. */
3176 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3177 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3178 || (symbol_constant_p (fragP->fr_symbol)
3179 && !fragP->tc_frag_data.pcrel)
3180 || symbol_equated_p (fragP->fr_symbol)
3181 || S_IS_WEAK (fragP->fr_symbol))
3182 {
3183 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3184 ++fragP->fr_subtype;
3185 }
886a2506 3186
4670103e
CZ		 3187 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3188 fragP->fr_var = growth;
886a2506 3189
4670103e
CZ		 3190 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3191 fragP->fr_file, fragP->fr_line, growth);
886a2506 3192
4670103e
CZ		 3193 return growth;
3194}
886a2506 3195
4670103e
CZ		 3196/* Translate internal representation of relocation info to BFD target
3197 format. */
886a2506 3198
4670103e
CZ		 3199arelent *
3200tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3201 fixS *fixP)
3202{
3203 arelent *reloc;
3204 bfd_reloc_code_real_type code;
886a2506 3205
add39d23
TS		 3206 reloc = XNEW (arelent);
3207 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3208 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3209 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3210
4670103e
CZ		 3211 /* Make sure none of our internal relocations make it this far.
3212 They'd better have been fully resolved by this point. */
3213 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3214
4670103e 3215 code = fixP->fx_r_type;
886a2506 3216
4670103e
CZ		 3217 /* if we have something like add gp, pcl,
3218 _GLOBAL_OFFSET_TABLE_@gotpc. */
3219 if (code == BFD_RELOC_ARC_GOTPC32
3220 && GOT_symbol
3221 && fixP->fx_addsy == GOT_symbol)
3222 code = BFD_RELOC_ARC_GOTPC;
886a2506 3223
4670103e
CZ		 3224 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3225 if (reloc->howto == NULL)
886a2506 3226 {
4670103e
CZ		 3227 as_bad_where (fixP->fx_file, fixP->fx_line,
3228 _("cannot represent `%s' relocation in object file"),
3229 bfd_get_reloc_code_name (code));
3230 return NULL;
3231 }
886a2506 3232
4670103e
CZ		 3233 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3234 as_fatal (_("internal error? cannot generate `%s' relocation"),
3235 bfd_get_reloc_code_name (code));
886a2506 3236
4670103e 3237 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3238
05bbf016 3239 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3240
3241 return reloc;
886a2506
NC		 3242}
3243
4670103e
CZ		 3244/* Perform post-processing of machine-dependent frags after relaxation.
3245 Called after relaxation is finished.
3246 In: Address of frag.
3247 fr_type == rs_machine_dependent.
3248 fr_subtype is what the address relaxed to.
886a2506 3249
4670103e
CZ		 3250 Out: Any fixS:s and constants are set up. */
3251
3252void
3253md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3254 segT segment ATTRIBUTE_UNUSED,
3255 fragS *fragP)
886a2506 3256{
4670103e
CZ		 3257 const relax_typeS *table_entry;
3258 char *dest;
3259 const struct arc_opcode *opcode;
3260 struct arc_insn insn;
3261 int size, fix;
3262 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3263
4670103e
CZ		 3264 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3265 dest = fragP->fr_literal + fix;
3266 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3267
9e32d9ae
AB		 3268 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3269 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3270 fragP->fr_file, fragP->fr_line,
3271 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3272
4670103e
CZ		 3273 if (fragP->fr_subtype <= 0
3274 && fragP->fr_subtype >= arc_num_relax_opcodes)
3275 as_fatal (_("no relaxation found for this instruction."));
886a2506 3276
4670103e 3277 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3278
4670103e
CZ		 3279 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3280 relax_arg->nflg, &insn);
886a2506 3281
4670103e 3282 apply_fixups (&insn, fragP, fix);
886a2506 3283
91fdca6f 3284 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3285 gas_assert (table_entry->rlx_length == size);
3286 emit_insn0 (&insn, dest, TRUE);
886a2506 3287
4670103e
CZ		 3288 fragP->fr_fix += table_entry->rlx_length;
3289 fragP->fr_var = 0;
886a2506
NC		 3290}
3291
4670103e
CZ		 3292/* We have no need to default values of symbols. We could catch
3293 register names here, but that is handled by inserting them all in
3294 the symbol table to begin with. */
886a2506 3295
4670103e
CZ		 3296symbolS *
3297md_undefined_symbol (char *name)
886a2506 3298{
4670103e
CZ		 3299 /* The arc abi demands that a GOT[0] should be referencible as
3300 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3301 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3302 if (((*name == '_')
3303 && (*(name+1) == 'G')
3304 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
3305 || ((*name == '_')
3306 && (*(name+1) == 'D')
3307 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
886a2506 3308 {
4670103e
CZ		 3309 if (!GOT_symbol)
3310 {
3311 if (symbol_find (name))
3312 as_bad ("GOT already in symbol table");
3313
3314 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3315 (valueT) 0, &zero_address_frag);
3316 };
3317 return GOT_symbol;
886a2506 3318 }
4670103e 3319 return NULL;
886a2506
NC		 3320}
3321
4670103e
CZ		 3322/* Turn a string in input_line_pointer into a floating point constant
3323 of type type, and store the appropriate bytes in *litP. The number
3324 of LITTLENUMS emitted is stored in *sizeP. An error message is
3325 returned, or NULL on OK. */
886a2506 3326
6d4af3c2 3327const char *
4670103e 3328md_atof (int type, char *litP, int *sizeP)
886a2506 3329{
4670103e
CZ		 3330 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3331}
886a2506 3332
4670103e
CZ		 3333/* Called for any expression that can not be recognized. When the
3334 function is called, `input_line_pointer' will point to the start of
3335 the expression. */
886a2506 3336
4670103e
CZ		 3337void
3338md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3339{
3340 char *p = input_line_pointer;
3341 if (*p == '@')
886a2506 3342 {
4670103e
CZ		 3343 input_line_pointer++;
3344 expressionP->X_op = O_symbol;
3345 expression (expressionP);
3346 }
3347}
886a2506 3348
4670103e
CZ		 3349/* This function is called from the function 'expression', it attempts
3350 to parse special names (in our case register names). It fills in
3351 the expression with the identified register. It returns TRUE if
3352 it is a register and FALSE otherwise. */
886a2506 3353
4670103e
CZ		 3354bfd_boolean
3355arc_parse_name (const char *name,
3356 struct expressionS *e)
3357{
3358 struct symbol *sym;
886a2506 3359
4670103e
CZ		 3360 if (!assembling_insn)
3361 return FALSE;
886a2506 3362
08ec958f 3363 if (e->X_op == O_symbol)
4670103e 3364 return FALSE;
886a2506 3365
4670103e
CZ		 3366 sym = hash_find (arc_reg_hash, name);
3367 if (sym)
3368 {
3369 e->X_op = O_register;
3370 e->X_add_number = S_GET_VALUE (sym);
3371 return TRUE;
3372 }
db18dbab
GM		 3373
3374 sym = hash_find (arc_addrtype_hash, name);
3375 if (sym)
3376 {
3377 e->X_op = O_addrtype;
3378 e->X_add_number = S_GET_VALUE (sym);
3379 return TRUE;
3380 }
3381
4670103e
CZ		 3382 return FALSE;
3383}
886a2506 3384
4670103e
CZ		 3385/* md_parse_option
3386 Invocation line includes a switch not recognized by the base assembler.
3387 See if it's a processor-specific option.
886a2506 3388
4670103e 3389 New options (supported) are:
886a2506 3390
4670103e
CZ		 3391 -mcpu=<cpu name> Assemble for selected processor
3392 -EB/-mbig-endian Big-endian
3393 -EL/-mlittle-endian Little-endian
3394 -mrelax Enable relaxation
886a2506 3395
4670103e 3396 The following CPU names are recognized:
ce440d63 3397 arc600, arc700, arcem, archs, nps400. */
886a2506 3398
4670103e 3399int
17b9d67d 3400md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3401{
4670103e
CZ		 3402 switch (c)
3403 {
3404 case OPTION_ARC600:
3405 case OPTION_ARC601:
3406 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3407
4670103e
CZ		 3408 case OPTION_ARC700:
3409 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3410
4670103e
CZ		 3411 case OPTION_ARCEM:
3412 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3413
4670103e
CZ		 3414 case OPTION_ARCHS:
3415 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3416
4670103e
CZ		 3417 case OPTION_MCPU:
3418 {
bb65a718 3419 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3420 break;
3421 }
886a2506 3422
4670103e
CZ		 3423 case OPTION_EB:
3424 arc_target_format = "elf32-bigarc";
3425 byte_order = BIG_ENDIAN;
3426 break;
886a2506 3427
4670103e
CZ		 3428 case OPTION_EL:
3429 arc_target_format = "elf32-littlearc";
3430 byte_order = LITTLE_ENDIAN;
3431 break;
886a2506 3432
4670103e 3433 case OPTION_CD:
53a346d8
CZ		 3434 selected_cpu.features |= CD;
3435 cl_features |= CD;
bb050a69 3436 arc_check_feature ();
4670103e 3437 break;
886a2506 3438
4670103e
CZ		 3439 case OPTION_RELAX:
3440 relaxation_state = 1;
3441 break;
886a2506 3442
bdd582db 3443 case OPTION_NPS400:
53a346d8
CZ		 3444 selected_cpu.features |= NPS400;
3445 cl_features |= NPS400;
bb050a69 3446 arc_check_feature ();
ce440d63 3447 break;
bdd582db 3448
ce440d63 3449 case OPTION_SPFP:
53a346d8
CZ		 3450 selected_cpu.features |= SPX;
3451 cl_features |= SPX;
bb050a69 3452 arc_check_feature ();
ce440d63
GM		 3453 break;
3454
3455 case OPTION_DPFP:
53a346d8
CZ		 3456 selected_cpu.features |= DPX;
3457 cl_features |= DPX;
bb050a69 3458 arc_check_feature ();
ce440d63
GM		 3459 break;
3460
3461 case OPTION_FPUDA:
53a346d8
CZ		 3462 selected_cpu.features |= DPA;
3463 cl_features |= DPA;
bb050a69 3464 arc_check_feature ();
ce440d63
GM		 3465 break;
3466
3467 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3468 case OPTION_USER_MODE:
3469 case OPTION_LD_EXT_MASK:
3470 case OPTION_SWAP:
3471 case OPTION_NORM:
3472 case OPTION_BARREL_SHIFT:
3473 case OPTION_MIN_MAX:
3474 case OPTION_NO_MPY:
3475 case OPTION_EA:
3476 case OPTION_MUL64:
3477 case OPTION_SIMD:
4670103e
CZ		 3478 case OPTION_XMAC_D16:
3479 case OPTION_XMAC_24:
3480 case OPTION_DSP_PACKA:
3481 case OPTION_CRC:
3482 case OPTION_DVBF:
3483 case OPTION_TELEPHONY:
3484 case OPTION_XYMEMORY:
3485 case OPTION_LOCK:
3486 case OPTION_SWAPE:
3487 case OPTION_RTSC:
8ddf6b2a
CZ		 3488 break;
3489
4670103e
CZ		 3490 default:
3491 return 0;
3492 }
886a2506 3493
4670103e
CZ		 3494 return 1;
3495}
886a2506 3496
a9752fdf
CZ		 3497/* Display the list of cpu names for use in the help text. */
3498
3499static void
3500arc_show_cpu_list (FILE *stream)
3501{
3502 int i, offset;
731f7c4e 3503 static const char *space_buf = " ";
a9752fdf 3504
731f7c4e
MR		 3505 fprintf (stream, "%s", space_buf);
3506 offset = strlen (space_buf);
a9752fdf
CZ		 3507 for (i = 0; cpu_types[i].name != NULL; ++i)
3508 {
3509 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3510
3511 /* If displaying the new cpu name string, and the ', ' (for all
3512 but the last one) will take us past a target width of 80
3513 characters, then it's time for a new line. */
3514 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3515 {
731f7c4e
MR		 3516 fprintf (stream, "\n%s", space_buf);
3517 offset = strlen (space_buf);
a9752fdf
CZ		 3518 }
3519
3520 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3521 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3522 }
3523}
3524
4670103e
CZ		 3525void
3526md_show_usage (FILE *stream)
3527{
3528 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3529
a9752fdf
CZ		 3530 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3531 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3532 arc_show_cpu_list (stream);
3533 fprintf (stream, "\n");
bdd582db
GM		 3534 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3535 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3536 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3537 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3538
3539 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3540 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3541 " instructions\n");
3542 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3543 " instructions\n");
bdd582db
GM		 3544 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3545 "point\n\t\t\t instructions for ARC EM\n");
3546
4670103e
CZ		 3547 fprintf (stream,
3548 " -mcode-density\t enable code density option for ARC EM\n");
3549
3550 fprintf (stream, _("\
3551 -EB assemble code for a big-endian cpu\n"));
3552 fprintf (stream, _("\
3553 -EL assemble code for a little-endian cpu\n"));
3554 fprintf (stream, _("\
bdd582db
GM		 3555 -mrelax enable relaxation\n"));
3556
3557 fprintf (stream, _("The following ARC-specific assembler options are "
3558 "deprecated and are accepted\nfor compatibility only:\n"));
3559
3560 fprintf (stream, _(" -mEA\n"
3561 " -mbarrel-shifter\n"
3562 " -mbarrel_shifter\n"
3563 " -mcrc\n"
3564 " -mdsp-packa\n"
3565 " -mdsp_packa\n"
3566 " -mdvbf\n"
3567 " -mld-extension-reg-mask\n"
3568 " -mlock\n"
3569 " -mmac-24\n"
3570 " -mmac-d16\n"
3571 " -mmac_24\n"
3572 " -mmac_d16\n"
3573 " -mmin-max\n"
3574 " -mmin_max\n"
3575 " -mmul64\n"
3576 " -mno-mpy\n"
3577 " -mnorm\n"
3578 " -mrtsc\n"
3579 " -msimd\n"
3580 " -mswap\n"
3581 " -mswape\n"
3582 " -mtelephony\n"
3583 " -muser-mode-only\n"
3584 " -mxy\n"));
886a2506
NC		 3585}
3586
3587/* Find the proper relocation for the given opcode. */
3588
3589static extended_bfd_reloc_code_real_type
3590find_reloc (const char *name,
3591 const char *opcodename,
3592 const struct arc_flags *pflags,
3593 int nflg,
3594 extended_bfd_reloc_code_real_type reloc)
3595{
3596 unsigned int i;
3597 int j;
24b368f8 3598 bfd_boolean found_flag, tmp;
886a2506
NC		 3599 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3600
3601 for (i = 0; i < arc_num_equiv_tab; i++)
3602 {
3603 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3604
3605 /* Find the entry. */
3606 if (strcmp (name, r->name))
3607 continue;
3608 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3609 continue;
24b368f8 3610 if (r->flags[0])
886a2506
NC		 3611 {
3612 if (!nflg)
3613 continue;
3614 found_flag = FALSE;
24b368f8
CZ		 3615 unsigned * psflg = (unsigned *)r->flags;
3616 do
3617 {
3618 tmp = FALSE;
3619 for (j = 0; j < nflg; j++)
3620 if (!strcmp (pflags[j].name,
3621 arc_flag_operands[*psflg].name))
3622 {
3623 tmp = TRUE;
3624 break;
3625 }
3626 if (!tmp)
3627 {
3628 found_flag = FALSE;
3629 break;
3630 }
3631 else
3632 {
3633 found_flag = TRUE;
3634 }
3635 ++ psflg;
3636 } while (*psflg);
3637
886a2506
NC		 3638 if (!found_flag)
3639 continue;
3640 }
3641
3642 if (reloc != r->oldreloc)
3643 continue;
3644 /* Found it. */
3645 ret = r->newreloc;
3646 break;
3647 }
3648
3649 if (ret == BFD_RELOC_UNUSED)
3650 as_bad (_("Unable to find %s relocation for instruction %s"),
3651 name, opcodename);
3652 return ret;
3653}
3654
4670103e
CZ		 3655/* All the symbol types that are allowed to be used for
3656 relaxation. */
3657
3658static bfd_boolean
3659may_relax_expr (expressionS tok)
3660{
3661 /* Check if we have unrelaxable relocs. */
3662 switch (tok.X_md)
3663 {
3664 default:
3665 break;
3666 case O_plt:
3667 return FALSE;
3668 }
3669
3670 switch (tok.X_op)
3671 {
3672 case O_symbol:
3673 case O_multiply:
3674 case O_divide:
3675 case O_modulus:
3676 case O_add:
3677 case O_subtract:
3678 break;
3679
3680 default:
3681 return FALSE;
3682 }
3683 return TRUE;
3684}
3685
3686/* Checks if flags are in line with relaxable insn. */
3687
3688static bfd_boolean
3689relaxable_flag (const struct arc_relaxable_ins *ins,
3690 const struct arc_flags *pflags,
3691 int nflgs)
3692{
3693 unsigned flag_class,
3694 flag,
3695 flag_class_idx = 0,
3696 flag_idx = 0;
3697
3698 const struct arc_flag_operand *flag_opand;
3699 int i, counttrue = 0;
3700
3701 /* Iterate through flags classes. */
3702 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3703 {
3704 /* Iterate through flags in flag class. */
3705 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3706 != 0)
3707 {
3708 flag_opand = &arc_flag_operands[flag];
3709 /* Iterate through flags in ins to compare. */
3710 for (i = 0; i < nflgs; ++i)
3711 {
3712 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3713 ++counttrue;
3714 }
3715
3716 ++flag_idx;
3717 }
3718
3719 ++flag_class_idx;
3720 flag_idx = 0;
3721 }
3722
3723 /* If counttrue == nflgs, then all flags have been found. */
3724 return (counttrue == nflgs ? TRUE : FALSE);
3725}
3726
3727/* Checks if operands are in line with relaxable insn. */
3728
3729static bfd_boolean
3730relaxable_operand (const struct arc_relaxable_ins *ins,
3731 const expressionS *tok,
3732 int ntok)
3733{
3734 const enum rlx_operand_type *operand = &ins->operands[0];
3735 int i = 0;
3736
3737 while (*operand != EMPTY)
3738 {
3739 const expressionS *epr = &tok[i];
3740
3741 if (i != 0 && i >= ntok)
3742 return FALSE;
3743
3744 switch (*operand)
3745 {
3746 case IMMEDIATE:
3747 if (!(epr->X_op == O_multiply
3748 || epr->X_op == O_divide
3749 || epr->X_op == O_modulus
3750 || epr->X_op == O_add
3751 || epr->X_op == O_subtract
3752 || epr->X_op == O_symbol))
3753 return FALSE;
3754 break;
3755
3756 case REGISTER_DUP:
3757 if ((i <= 0)
3758 || (epr->X_add_number != tok[i - 1].X_add_number))
3759 return FALSE;
3760 /* Fall through. */
3761 case REGISTER:
3762 if (epr->X_op != O_register)
3763 return FALSE;
3764 break;
3765
3766 case REGISTER_S:
3767 if (epr->X_op != O_register)
3768 return FALSE;
3769
3770 switch (epr->X_add_number)
3771 {
3772 case 0: case 1: case 2: case 3:
3773 case 12: case 13: case 14: case 15:
3774 break;
3775 default:
3776 return FALSE;
3777 }
3778 break;
3779
3780 case REGISTER_NO_GP:
3781 if ((epr->X_op != O_register)
3782 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3783 return FALSE;
3784 break;
3785
3786 case BRACKET:
3787 if (epr->X_op != O_bracket)
3788 return FALSE;
3789 break;
3790
3791 default:
3792 /* Don't understand, bail out. */
3793 return FALSE;
3794 break;
3795 }
3796
3797 ++i;
3798 operand = &ins->operands[i];
3799 }
3800
3801 return (i == ntok ? TRUE : FALSE);
3802}
3803
3804/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3805
3806static bfd_boolean
3807relax_insn_p (const struct arc_opcode *opcode,
3808 const expressionS *tok,
3809 int ntok,
3810 const struct arc_flags *pflags,
3811 int nflg)
3812{
3813 unsigned i;
3814 bfd_boolean rv = FALSE;
3815
3816 /* Check the relaxation table. */
3817 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3818 {
3819 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3820
3821 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3822 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3823 && relaxable_operand (arc_rlx_ins, tok, ntok)
3824 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3825 {
3826 rv = TRUE;
3827 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3828 memcpy (&frag_now->tc_frag_data.tok, tok,
3829 sizeof (expressionS) * ntok);
3830 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3831 sizeof (struct arc_flags) * nflg);
3832 frag_now->tc_frag_data.nflg = nflg;
3833 frag_now->tc_frag_data.ntok = ntok;
3834 break;
3835 }
3836 }
3837
3838 return rv;
3839}
3840
886a2506
NC		 3841/* Turn an opcode description and a set of arguments into
3842 an instruction and a fixup. */
3843
3844static void
3845assemble_insn (const struct arc_opcode *opcode,
3846 const expressionS *tok,
3847 int ntok,
3848 const struct arc_flags *pflags,
3849 int nflg,
3850 struct arc_insn *insn)
3851{
3852 const expressionS *reloc_exp = NULL;
bdfe53e3 3853 unsigned long long image;
886a2506
NC		 3854 const unsigned char *argidx;
3855 int i;
3856 int tokidx = 0;
3857 unsigned char pcrel = 0;
3858 bfd_boolean needGOTSymbol;
3859 bfd_boolean has_delay_slot = FALSE;
3860 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3861
3862 memset (insn, 0, sizeof (*insn));
3863 image = opcode->opcode;
3864
bdfe53e3 3865 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3866 frag_now->fr_file, frag_now->fr_line, opcode->name,
3867 opcode->opcode);
3868
3869 /* Handle operands. */
3870 for (argidx = opcode->operands; *argidx; ++argidx)
3871 {
3872 const struct arc_operand *operand = &arc_operands[*argidx];
3873 const expressionS *t = (const expressionS *) 0;
3874
db18dbab 3875 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3876 continue;
3877
3878 if (operand->flags & ARC_OPERAND_DUPLICATE)
3879 {
3880 /* Duplicate operand, already inserted. */
3881 tokidx ++;
3882 continue;
3883 }
3884
3885 if (tokidx >= ntok)
3886 {
3887 abort ();
3888 }
3889 else
3890 t = &tok[tokidx++];
3891
3892 /* Regardless if we have a reloc or not mark the instruction
3893 limm if it is the case. */
3894 if (operand->flags & ARC_OPERAND_LIMM)
3895 insn->has_limm = TRUE;
3896
3897 switch (t->X_op)
3898 {
3899 case O_register:
3900 image = insert_operand (image, operand, regno (t->X_add_number),
3901 NULL, 0);
3902 break;
3903
3904 case O_constant:
3905 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3906 reloc_exp = t;
3907 if (operand->flags & ARC_OPERAND_LIMM)
3908 insn->limm = t->X_add_number;
3909 break;
3910
3911 case O_bracket:
db18dbab
GM		 3912 case O_colon:
3913 case O_addrtype:
3914 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3915 break;
3916
3917 case O_absent:
3918 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3919 break;
3920
3921 case O_subtract:
3922 /* Maybe register range. */
3923 if ((t->X_add_number == 0)
3924 && contains_register (t->X_add_symbol)
3925 && contains_register (t->X_op_symbol))
3926 {
3927 int regs;
3928
3929 regs = get_register (t->X_add_symbol);
3930 regs <<= 16;
3931 regs |= get_register (t->X_op_symbol);
3932 image = insert_operand (image, operand, regs, NULL, 0);
3933 break;
3934 }
1a0670f3 3935 /* Fall through. */
886a2506
NC		 3936
3937 default:
3938 /* This operand needs a relocation. */
3939 needGOTSymbol = FALSE;
3940
3941 switch (t->X_md)
3942 {
3943 case O_plt:
c810e0b8 3944 if (opcode->insn_class == JUMP)
6ec1f282 3945 as_bad_where (frag_now->fr_file, frag_now->fr_line,
33eaf5de 3946 _("Unable to use @plt relocation for insn %s"),
6ec1f282 3947 opcode->name);
886a2506
NC		 3948 needGOTSymbol = TRUE;
3949 reloc = find_reloc ("plt", opcode->name,
3950 pflags, nflg,
3951 operand->default_reloc);
3952 break;
3953
3954 case O_gotoff:
3955 case O_gotpc:
3956 needGOTSymbol = TRUE;
3957 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3958 break;
3959 case O_pcl:
cc07cda6
CZ		 3960 if (operand->flags & ARC_OPERAND_LIMM)
3961 {
3962 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3963 if (arc_opcode_len (opcode) == 2
3964 || opcode->insn_class == JUMP)
3965 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3966 _("Unable to use @pcl relocation for insn %s"),
3967 opcode->name);
3968 }
3969 else
3970 {
3971 /* This is a relaxed operand which initially was
3972 limm, choose whatever we have defined in the
3973 opcode as reloc. */
3974 reloc = operand->default_reloc;
3975 }
886a2506
NC		 3976 break;
3977 case O_sda:
3978 reloc = find_reloc ("sda", opcode->name,
3979 pflags, nflg,
3980 operand->default_reloc);
3981 break;
3982 case O_tlsgd:
3983 case O_tlsie:
3984 needGOTSymbol = TRUE;
3985 /* Fall-through. */
3986
3987 case O_tpoff:
3988 case O_dtpoff:
3989 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3990 break;
3991
3992 case O_tpoff9: /*FIXME! Check for the conditionality of
3993 the insn. */
3994 case O_dtpoff9: /*FIXME! Check for the conditionality of
3995 the insn. */
3996 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3997 break;
3998
3999 default:
4000 /* Just consider the default relocation. */
4001 reloc = operand->default_reloc;
4002 break;
4003 }
4004
4005 if (needGOTSymbol && (GOT_symbol == NULL))
4006 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4007
4008 reloc_exp = t;
4009
4010#if 0
4011 if (reloc > 0)
4012 {
4013 /* sanity checks. */
4014 reloc_howto_type *reloc_howto
4015 = bfd_reloc_type_lookup (stdoutput,
4016 (bfd_reloc_code_real_type) reloc);
4017 unsigned reloc_bitsize = reloc_howto->bitsize;
4018 if (reloc_howto->rightshift)
4019 reloc_bitsize -= reloc_howto->rightshift;
4020 if (reloc_bitsize != operand->bits)
4021 {
4022 as_bad (_("invalid relocation %s for field"),
4023 bfd_get_reloc_code_name (reloc));
4024 return;
4025 }
4026 }
4027#endif
4028 if (insn->nfixups >= MAX_INSN_FIXUPS)
4029 as_fatal (_("too many fixups"));
4030
4031 struct arc_fixup *fixup;
4032 fixup = &insn->fixups[insn->nfixups++];
4033 fixup->exp = *t;
4034 fixup->reloc = reloc;
cc07cda6
CZ		 4035 if ((int) reloc < 0)
4036 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4037 else
4038 {
4039 reloc_howto_type *reloc_howto =
4040 bfd_reloc_type_lookup (stdoutput,
4041 (bfd_reloc_code_real_type) fixup->reloc);
4042 pcrel = reloc_howto->pc_relative;
4043 }
886a2506
NC		 4044 fixup->pcrel = pcrel;
4045 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4046 TRUE : FALSE;
4047 break;
4048 }
4049 }
4050
4051 /* Handle flags. */
4052 for (i = 0; i < nflg; i++)
4053 {
f36e33da 4054 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4055
4056 /* Check if the instruction has a delay slot. */
4057 if (!strcmp (flg_operand->name, "d"))
4058 has_delay_slot = TRUE;
4059
2c52e2e8
RZ		 4060 /* There is an exceptional case when we cannot insert a flag just as
4061 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4062 relation with the relative address. Unfortunately, some of the
4063 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4064 handled in the normal way.
4065
4066 Flag operands don't have an architecture field, so we can't
4067 directly validate that FLAG_OPERAND is valid for the current
4068 architecture, what we do instead is just validate that we're
4069 assembling for an ARCv2 architecture. */
4070 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4071 && (!strcmp (flg_operand->name, "t")
4072 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4073 {
4074 unsigned bitYoperand = 0;
4075 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4076 if (!strcmp (flg_operand->name, "t"))
4077 if (!strcmp (opcode->name, "bbit0")
4078 || !strcmp (opcode->name, "bbit1"))
4079 bitYoperand = arc_NToperand;
4080 else
4081 bitYoperand = arc_Toperand;
4082 else
4083 if (!strcmp (opcode->name, "bbit0")
4084 || !strcmp (opcode->name, "bbit1"))
4085 bitYoperand = arc_Toperand;
4086 else
4087 bitYoperand = arc_NToperand;
4088
4089 gas_assert (reloc_exp != NULL);
4090 if (reloc_exp->X_op == O_constant)
4091 {
4092 /* Check if we have a constant and solved it
4093 immediately. */
4094 offsetT val = reloc_exp->X_add_number;
4095 image |= insert_operand (image, &arc_operands[bitYoperand],
4096 val, NULL, 0);
4097 }
4098 else
4099 {
4100 struct arc_fixup *fixup;
4101
4102 if (insn->nfixups >= MAX_INSN_FIXUPS)
4103 as_fatal (_("too many fixups"));
4104
4105 fixup = &insn->fixups[insn->nfixups++];
4106 fixup->exp = *reloc_exp;
4107 fixup->reloc = -bitYoperand;
4108 fixup->pcrel = pcrel;
4109 fixup->islong = FALSE;
4110 }
4111 }
4112 else
4113 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4114 << flg_operand->shift;
4115 }
4116
4670103e
CZ		 4117 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4118
91fdca6f 4119 /* Instruction length. */
06fe285f 4120 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4121
4122 insn->insn = image;
4123
4124 /* Update last insn status. */
4125 arc_last_insns[1] = arc_last_insns[0];
4126 arc_last_insns[0].opcode = opcode;
4127 arc_last_insns[0].has_limm = insn->has_limm;
4128 arc_last_insns[0].has_delay_slot = has_delay_slot;
4129
4130 /* Check if the current instruction is legally used. */
4131 if (arc_last_insns[1].has_delay_slot
4132 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4133 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4134 _("A jump/branch instruction in delay slot."));
4135}
4136
886a2506
NC		 4137void
4138arc_handle_align (fragS* fragP)
4139{
4140 if ((fragP)->fr_type == rs_align_code)
4141 {
4142 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4143 valueT count = ((fragP)->fr_next->fr_address
4144 - (fragP)->fr_address - (fragP)->fr_fix);
4145
4146 (fragP)->fr_var = 2;
4147
4148 if (count & 1)/* Padding in the gap till the next 2-byte
4149 boundary with 0s. */
4150 {
4151 (fragP)->fr_fix++;
4152 *dest++ = 0;
4153 }
4154 /* Writing nop_s. */
4155 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4156 }
4157}
4158
4159/* Here we decide which fixups can be adjusted to make them relative
4160 to the beginning of the section instead of the symbol. Basically
4161 we need to make sure that the dynamic relocations are done
4162 correctly, so in some cases we force the original symbol to be
4163 used. */
4164
4165int
4166tc_arc_fix_adjustable (fixS *fixP)
4167{
4168
4169 /* Prevent all adjustments to global symbols. */
4170 if (S_IS_EXTERNAL (fixP->fx_addsy))
4171 return 0;
4172 if (S_IS_WEAK (fixP->fx_addsy))
4173 return 0;
4174
4175 /* Adjust_reloc_syms doesn't know about the GOT. */
4176 switch (fixP->fx_r_type)
4177 {
4178 case BFD_RELOC_ARC_GOTPC32:
4179 case BFD_RELOC_ARC_PLT32:
4180 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4181 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4182 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4183 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4184 return 0;
4185
4186 default:
4187 break;
4188 }
4189
841fdfcd 4190 return 1;
886a2506
NC		 4191}
4192
4193/* Compute the reloc type of an expression EXP. */
4194
4195static void
4196arc_check_reloc (expressionS *exp,
4197 bfd_reloc_code_real_type *r_type_p)
4198{
4199 if (*r_type_p == BFD_RELOC_32
4200 && exp->X_op == O_subtract
4201 && exp->X_op_symbol != NULL
4202 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 4203 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4204}
4205
4206
4207/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4208
4209void
4210arc_cons_fix_new (fragS *frag,
4211 int off,
4212 int size,
4213 expressionS *exp,
4214 bfd_reloc_code_real_type r_type)
4215{
4216 r_type = BFD_RELOC_UNUSED;
4217
4218 switch (size)
4219 {
4220 case 1:
4221 r_type = BFD_RELOC_8;
4222 break;
4223
4224 case 2:
4225 r_type = BFD_RELOC_16;
4226 break;
4227
4228 case 3:
4229 r_type = BFD_RELOC_24;
4230 break;
4231
4232 case 4:
4233 r_type = BFD_RELOC_32;
4234 arc_check_reloc (exp, &r_type);
4235 break;
4236
4237 case 8:
4238 r_type = BFD_RELOC_64;
4239 break;
4240
4241 default:
4242 as_bad (_("unsupported BFD relocation size %u"), size);
4243 r_type = BFD_RELOC_UNUSED;
4244 }
4245
4246 fix_new_exp (frag, off, size, exp, 0, r_type);
4247}
4248
4249/* The actual routine that checks the ZOL conditions. */
4250
4251static void
4252check_zol (symbolS *s)
4253{
bb65a718 4254 switch (selected_cpu.mach)
886a2506
NC		 4255 {
4256 case bfd_mach_arc_arcv2:
bb65a718 4257 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4258 return;
4259
4260 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4261 || arc_last_insns[1].has_delay_slot)
4262 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4263 S_GET_NAME (s));
4264
4265 break;
4266 case bfd_mach_arc_arc600:
4267
4268 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4269 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4270 S_GET_NAME (s));
4271
4272 if (arc_last_insns[0].has_limm
4273 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4274 as_bad (_("A jump instruction with long immediate detected at the \
4275end of the ZOL label @%s"), S_GET_NAME (s));
4276
4277 /* Fall through. */
4278 case bfd_mach_arc_arc700:
4279 if (arc_last_insns[0].has_delay_slot)
4280 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4281 S_GET_NAME (s));
4282
4283 break;
4284 default:
4285 break;
4286 }
4287}
4288
4289/* If ZOL end check the last two instruction for illegals. */
4290void
4291arc_frob_label (symbolS * sym)
4292{
4293 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4294 check_zol (sym);
4295
4296 dwarf2_emit_label (sym);
ea1562b3 4297}
4670103e
CZ		 4298
4299/* Used because generic relaxation assumes a pc-rel value whilst we
4300 also relax instructions that use an absolute value resolved out of
4301 relative values (if that makes any sense). An example: 'add r1,
4302 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4303 but if they're in the same section we can subtract the section
4304 offset relocation which ends up in a resolved value. So if @.L2 is
4305 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4306 .text + 0x40 = 0x10. */
4307int
4308arc_pcrel_adjust (fragS *fragP)
4309{
cc07cda6
CZ		 4310 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4311 fragP->fr_address, fragP->fr_fix,
4312 fragP->tc_frag_data.pcrel ? "Y" : "N");
4313
4670103e
CZ		 4314 if (!fragP->tc_frag_data.pcrel)
4315 return fragP->fr_address + fragP->fr_fix;
4316
cc07cda6
CZ		 4317 /* Take into account the PCL rounding. */
4318 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4319}
726c18e1
CZ		 4320
4321/* Initialize the DWARF-2 unwind information for this procedure. */
4322
4323void
4324tc_arc_frame_initial_instructions (void)
4325{
4326 /* Stack pointer is register 28. */
45a54ee5 4327 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4328}
4329
4330int
4331tc_arc_regname_to_dw2regnum (char *regname)
4332{
4333 struct symbol *sym;
4334
4335 sym = hash_find (arc_reg_hash, regname);
4336 if (sym)
4337 return S_GET_VALUE (sym);
4338
4339 return -1;
4340}
37ab9779
CZ		 4341
4342/* Adjust the symbol table. Delete found AUX register symbols. */
4343
4344void
4345arc_adjust_symtab (void)
4346{
4347 symbolS * sym;
4348
4349 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4350 {
4351 /* I've created a symbol during parsing process. Now, remove
4352 the symbol as it is found to be an AUX register. */
4353 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4354 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4355 }
4356
4357 /* Now do generic ELF adjustments. */
4358 elf_adjust_symtab ();
4359}
b99747ae
CZ		 4360
4361static void
4362tokenize_extinsn (extInstruction_t *einsn)
4363{
4364 char *p, c;
4365 char *insn_name;
4366 unsigned char major_opcode;
4367 unsigned char sub_opcode;
4368 unsigned char syntax_class = 0;
4369 unsigned char syntax_class_modifiers = 0;
4370 unsigned char suffix_class = 0;
4371 unsigned int i;
4372
4373 SKIP_WHITESPACE ();
4374
4375 /* 1st: get instruction name. */
4376 p = input_line_pointer;
4377 c = get_symbol_name (&p);
4378
4379 insn_name = xstrdup (p);
4380 restore_line_pointer (c);
4381
4382 /* 2nd: get major opcode. */
4383 if (*input_line_pointer != ',')
4384 {
4385 as_bad (_("expected comma after instruction name"));
4386 ignore_rest_of_line ();
4387 return;
4388 }
4389 input_line_pointer++;
4390 major_opcode = get_absolute_expression ();
4391
4392 /* 3rd: get sub-opcode. */
4393 SKIP_WHITESPACE ();
4394
4395 if (*input_line_pointer != ',')
4396 {
4397 as_bad (_("expected comma after major opcode"));
4398 ignore_rest_of_line ();
4399 return;
4400 }
4401 input_line_pointer++;
4402 sub_opcode = get_absolute_expression ();
4403
4404 /* 4th: get suffix class. */
4405 SKIP_WHITESPACE ();
4406
4407 if (*input_line_pointer != ',')
4408 {
4409 as_bad ("expected comma after sub opcode");
4410 ignore_rest_of_line ();
4411 return;
4412 }
4413 input_line_pointer++;
4414
4415 while (1)
4416 {
4417 SKIP_WHITESPACE ();
4418
4419 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4420 {
4421 if (!strncmp (suffixclass[i].name, input_line_pointer,
4422 suffixclass[i].len))
4423 {
c810e0b8 4424 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4425 input_line_pointer += suffixclass[i].len;
4426 break;
4427 }
4428 }
4429
4430 if (i == ARRAY_SIZE (suffixclass))
4431 {
4432 as_bad ("invalid suffix class");
4433 ignore_rest_of_line ();
4434 return;
4435 }
4436
4437 SKIP_WHITESPACE ();
4438
4439 if (*input_line_pointer == '|')
4440 input_line_pointer++;
4441 else
4442 break;
4443 }
4444
4445 /* 5th: get syntax class and syntax class modifiers. */
4446 if (*input_line_pointer != ',')
4447 {
4448 as_bad ("expected comma after suffix class");
4449 ignore_rest_of_line ();
4450 return;
4451 }
4452 input_line_pointer++;
4453
4454 while (1)
4455 {
4456 SKIP_WHITESPACE ();
4457
4458 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4459 {
4460 if (!strncmp (syntaxclassmod[i].name,
4461 input_line_pointer,
4462 syntaxclassmod[i].len))
4463 {
c810e0b8 4464 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4465 input_line_pointer += syntaxclassmod[i].len;
4466 break;
4467 }
4468 }
4469
4470 if (i == ARRAY_SIZE (syntaxclassmod))
4471 {
4472 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4473 {
4474 if (!strncmp (syntaxclass[i].name,
4475 input_line_pointer,
4476 syntaxclass[i].len))
4477 {
c810e0b8 4478 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4479 input_line_pointer += syntaxclass[i].len;
4480 break;
4481 }
4482 }
4483
4484 if (i == ARRAY_SIZE (syntaxclass))
4485 {
4486 as_bad ("missing syntax class");
4487 ignore_rest_of_line ();
4488 return;
4489 }
4490 }
4491
4492 SKIP_WHITESPACE ();
4493
4494 if (*input_line_pointer == '|')
4495 input_line_pointer++;
4496 else
4497 break;
4498 }
4499
4500 demand_empty_rest_of_line ();
4501
4502 einsn->name = insn_name;
4503 einsn->major = major_opcode;
4504 einsn->minor = sub_opcode;
4505 einsn->syntax = syntax_class;
4506 einsn->modsyn = syntax_class_modifiers;
4507 einsn->suffix = suffix_class;
4508 einsn->flags = syntax_class
4509 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4510}
4511
4512/* Generate an extension section. */
4513
4514static int
4515arc_set_ext_seg (void)
4516{
4517 if (!arcext_section)
4518 {
4519 arcext_section = subseg_new (".arcextmap", 0);
4520 bfd_set_section_flags (stdoutput, arcext_section,
4521 SEC_READONLY | SEC_HAS_CONTENTS);
4522 }
4523 else
4524 subseg_set (arcext_section, 0);
4525 return 1;
4526}
4527
4528/* Create an extension instruction description in the arc extension
4529 section of the output file.
4530 The structure for an instruction is like this:
4531 [0]: Length of the record.
4532 [1]: Type of the record.
4533
4534 [2]: Major opcode.
4535 [3]: Sub-opcode.
4536 [4]: Syntax (flags).
4537 [5]+ Name instruction.
4538
4539 The sequence is terminated by an empty entry. */
4540
4541static void
4542create_extinst_section (extInstruction_t *einsn)
4543{
4544
4545 segT old_sec = now_seg;
4546 int old_subsec = now_subseg;
4547 char *p;
4548 int name_len = strlen (einsn->name);
4549
4550 arc_set_ext_seg ();
4551
4552 p = frag_more (1);
4553 *p = 5 + name_len + 1;
4554 p = frag_more (1);
4555 *p = EXT_INSTRUCTION;
4556 p = frag_more (1);
4557 *p = einsn->major;
4558 p = frag_more (1);
4559 *p = einsn->minor;
4560 p = frag_more (1);
4561 *p = einsn->flags;
4562 p = frag_more (name_len + 1);
4563 strcpy (p, einsn->name);
4564
4565 subseg_set (old_sec, old_subsec);
4566}
4567
4568/* Handler .extinstruction pseudo-op. */
4569
4570static void
4571arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4572{
4573 extInstruction_t einsn;
4574 struct arc_opcode *arc_ext_opcodes;
4575 const char *errmsg = NULL;
4576 unsigned char moplow, mophigh;
4577
4578 memset (&einsn, 0, sizeof (einsn));
4579 tokenize_extinsn (&einsn);
4580
4581 /* Check if the name is already used. */
4582 if (arc_find_opcode (einsn.name))
4583 as_warn (_("Pseudocode already used %s"), einsn.name);
4584
4585 /* Check the opcode ranges. */
4586 moplow = 0x05;
bb65a718
AB		 4587 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4588 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4589
4590 if ((einsn.major > mophigh) || (einsn.major < moplow))
4591 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4592
4593 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4594 && (einsn.major != 5) && (einsn.major != 9))
4595 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4596
945e0f82 4597 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4598 {
4599 case ARC_SYNTAX_3OP:
4600 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4601 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4602 break;
4603 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4604 case ARC_SYNTAX_1OP:
4605 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4606 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4607 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4608 break;
4609 default:
4610 break;
4611 }
4612
bb65a718 4613 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4614 if (arc_ext_opcodes == NULL)
4615 {
4616 if (errmsg)
4617 as_fatal ("%s", errmsg);
4618 else
4619 as_fatal (_("Couldn't generate extension instruction opcodes"));
4620 }
4621 else if (errmsg)
4622 as_warn ("%s", errmsg);
4623
4624 /* Insert the extension instruction. */
4625 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4626
4627 create_extinst_section (&einsn);
4628}
4629
06911889 4630static bfd_boolean
f36e33da
CZ		 4631tokenize_extregister (extRegister_t *ereg, int opertype)
4632{
4633 char *name;
4634 char *mode;
4635 char c;
4636 char *p;
4637 int number, imode = 0;
4638 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4639 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4640 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4641
4642 /* 1st: get register name. */
4643 SKIP_WHITESPACE ();
4644 p = input_line_pointer;
4645 c = get_symbol_name (&p);
4646
4647 name = xstrdup (p);
4648 restore_line_pointer (c);
4649
4650 /* 2nd: get register number. */
4651 SKIP_WHITESPACE ();
4652
4653 if (*input_line_pointer != ',')
4654 {
06911889 4655 as_bad (_("expected comma after name"));
f36e33da
CZ		 4656 ignore_rest_of_line ();
4657 free (name);
06911889 4658 return FALSE;
f36e33da
CZ		 4659 }
4660 input_line_pointer++;
4661 number = get_absolute_expression ();
4662
06911889
CZ		 4663 if ((number < 0)
4664 && (opertype != EXT_AUX_REGISTER))
f36e33da 4665 {
06911889
CZ		 4666 as_bad (_("%s second argument cannot be a negative number %d"),
4667 isCore_p ? "extCoreRegister's" : "extCondCode's",
4668 number);
f36e33da
CZ		 4669 ignore_rest_of_line ();
4670 free (name);
06911889 4671 return FALSE;
f36e33da
CZ		 4672 }
4673
4674 if (isReg_p)
4675 {
4676 /* 3rd: get register mode. */
4677 SKIP_WHITESPACE ();
4678
4679 if (*input_line_pointer != ',')
4680 {
4681 as_bad (_("expected comma after register number"));
4682 ignore_rest_of_line ();
4683 free (name);
06911889 4684 return FALSE;
f36e33da
CZ		 4685 }
4686
4687 input_line_pointer++;
4688 mode = input_line_pointer;
4689
4690 if (!strncmp (mode, "r|w", 3))
4691 {
4692 imode = 0;
4693 input_line_pointer += 3;
4694 }
4695 else if (!strncmp (mode, "r", 1))
4696 {
4697 imode = ARC_REGISTER_READONLY;
4698 input_line_pointer += 1;
4699 }
4700 else if (strncmp (mode, "w", 1))
4701 {
4702 as_bad (_("invalid mode"));
4703 ignore_rest_of_line ();
4704 free (name);
06911889 4705 return FALSE;
f36e33da
CZ		 4706 }
4707 else
4708 {
4709 imode = ARC_REGISTER_WRITEONLY;
4710 input_line_pointer += 1;
4711 }
4712 }
4713
4714 if (isCore_p)
4715 {
4716 /* 4th: get core register shortcut. */
4717 SKIP_WHITESPACE ();
4718 if (*input_line_pointer != ',')
4719 {
4720 as_bad (_("expected comma after register mode"));
4721 ignore_rest_of_line ();
4722 free (name);
06911889 4723 return FALSE;
f36e33da
CZ		 4724 }
4725
4726 input_line_pointer++;
4727
4728 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4729 {
4730 imode |= ARC_REGISTER_NOSHORT_CUT;
4731 input_line_pointer += 15;
4732 }
4733 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4734 {
4735 as_bad (_("shortcut designator invalid"));
4736 ignore_rest_of_line ();
4737 free (name);
06911889 4738 return FALSE;
f36e33da
CZ		 4739 }
4740 else
4741 {
4742 input_line_pointer += 12;
4743 }
4744 }
4745 demand_empty_rest_of_line ();
4746
4747 ereg->name = name;
4748 ereg->number = number;
4749 ereg->imode = imode;
06911889 4750 return TRUE;
f36e33da
CZ		 4751}
4752
4753/* Create an extension register/condition description in the arc
4754 extension section of the output file.
4755
4756 The structure for an instruction is like this:
4757 [0]: Length of the record.
4758 [1]: Type of the record.
4759
4760 For core regs and condition codes:
4761 [2]: Value.
4762 [3]+ Name.
4763
33eaf5de 4764 For auxiliary registers:
f36e33da
CZ		 4765 [2..5]: Value.
4766 [6]+ Name
4767
4768 The sequence is terminated by an empty entry. */
4769
4770static void
4771create_extcore_section (extRegister_t *ereg, int opertype)
4772{
4773 segT old_sec = now_seg;
4774 int old_subsec = now_subseg;
4775 char *p;
4776 int name_len = strlen (ereg->name);
4777
4778 arc_set_ext_seg ();
4779
4780 switch (opertype)
4781 {
4782 case EXT_COND_CODE:
4783 case EXT_CORE_REGISTER:
4784 p = frag_more (1);
4785 *p = 3 + name_len + 1;
4786 p = frag_more (1);
4787 *p = opertype;
4788 p = frag_more (1);
4789 *p = ereg->number;
4790 break;
4791 case EXT_AUX_REGISTER:
4792 p = frag_more (1);
4793 *p = 6 + name_len + 1;
4794 p = frag_more (1);
4795 *p = EXT_AUX_REGISTER;
4796 p = frag_more (1);
4797 *p = (ereg->number >> 24) & 0xff;
4798 p = frag_more (1);
4799 *p = (ereg->number >> 16) & 0xff;
4800 p = frag_more (1);
4801 *p = (ereg->number >> 8) & 0xff;
4802 p = frag_more (1);
4803 *p = (ereg->number) & 0xff;
4804 break;
4805 default:
4806 break;
4807 }
4808
4809 p = frag_more (name_len + 1);
4810 strcpy (p, ereg->name);
4811
4812 subseg_set (old_sec, old_subsec);
4813}
4814
4815/* Handler .extCoreRegister pseudo-op. */
4816
4817static void
4818arc_extcorereg (int opertype)
4819{
4820 extRegister_t ereg;
4821 struct arc_aux_reg *auxr;
4822 const char *retval;
4823 struct arc_flag_operand *ccode;
4824
4825 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4826 if (!tokenize_extregister (&ereg, opertype))
4827 return;
f36e33da
CZ		 4828
4829 switch (opertype)
4830 {
4831 case EXT_CORE_REGISTER:
4832 /* Core register. */
4833 if (ereg.number > 60)
4834 as_bad (_("core register %s value (%d) too large"), ereg.name,
4835 ereg.number);
4836 declare_register (ereg.name, ereg.number);
4837 break;
4838 case EXT_AUX_REGISTER:
4839 /* Auxiliary register. */
add39d23 4840 auxr = XNEW (struct arc_aux_reg);
f36e33da 4841 auxr->name = ereg.name;
bb65a718 4842 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4843 auxr->subclass = NONE;
4844 auxr->address = ereg.number;
4845 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4846 if (retval)
4847 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4848 auxr->name, retval);
4849 break;
4850 case EXT_COND_CODE:
4851 /* Condition code. */
4852 if (ereg.number > 31)
4853 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4854 ereg.number);
4855 ext_condcode.size ++;
4856 ext_condcode.arc_ext_condcode =
add39d23
TS		 4857 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4858 ext_condcode.size + 1);
f36e33da
CZ		 4859 if (ext_condcode.arc_ext_condcode == NULL)
4860 as_fatal (_("Virtual memory exhausted"));
4861
4862 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4863 ccode->name = ereg.name;
4864 ccode->code = ereg.number;
4865 ccode->bits = 5;
4866 ccode->shift = 0;
4867 ccode->favail = 0; /* not used. */
4868 ccode++;
4869 memset (ccode, 0, sizeof (struct arc_flag_operand));
4870 break;
4871 default:
4872 as_bad (_("Unknown extension"));
4873 break;
4874 }
4875 create_extcore_section (&ereg, opertype);
4876}
4877
53a346d8
CZ		 4878/* Parse a .arc_attribute directive. */
4879
4880static void
4881arc_attribute (int ignored ATTRIBUTE_UNUSED)
4882{
4883 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4884
4885 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4886 attributes_set_explicitly[tag] = TRUE;
4887}
4888
4889/* Set an attribute if it has not already been set by the user. */
4890
4891static void
4892arc_set_attribute_int (int tag, int value)
4893{
4894 if (tag < 1
4895 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4896 || !attributes_set_explicitly[tag])
4897 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4898}
4899
4900static void
4901arc_set_attribute_string (int tag, const char *value)
4902{
4903 if (tag < 1
4904 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4905 || !attributes_set_explicitly[tag])
4906 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4907}
4908
4909/* Allocate and concatenate two strings. s1 can be NULL but not
4910 s2. s1 pointer is freed at end of this procedure. */
4911
4912static char *
4913arc_stralloc (char * s1, const char * s2)
4914{
4915 char * p;
4916 int len = 0;
4917
4918 if (s1)
4919 len = strlen (s1) + 1;
4920
4921 /* Only s1 can be null. */
4922 gas_assert (s2);
4923 len += strlen (s2) + 1;
4924
4925 p = (char *) xmalloc (len);
4926 if (p == NULL)
4927 as_fatal (_("Virtual memory exhausted"));
4928
4929 if (s1)
4930 {
4931 strcpy (p, s1);
4932 strcat (p, ",");
4933 strcat (p, s2);
4934 free (s1);
4935 }
4936 else
4937 strcpy (p, s2);
4938
4939 return p;
4940}
4941
4942/* Set the public ARC object attributes. */
4943
4944static void
4945arc_set_public_attributes (void)
4946{
4947 int base = 0;
4948 char *s = NULL;
4949 unsigned int i;
4950
4951 /* Tag_ARC_CPU_name. */
4952 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4953
4954 /* Tag_ARC_CPU_base. */
4955 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4956 {
4957 case E_ARC_MACH_ARC600:
4958 case E_ARC_MACH_ARC601:
4959 base = TAG_CPU_ARC6xx;
4960 break;
4961 case E_ARC_MACH_ARC700:
4962 base = TAG_CPU_ARC7xx;
4963 break;
4964 case EF_ARC_CPU_ARCV2EM:
4965 base = TAG_CPU_ARCEM;
4966 break;
4967 case EF_ARC_CPU_ARCV2HS:
4968 base = TAG_CPU_ARCHS;
4969 break;
4970 default:
4971 base = 0;
4972 break;
4973 }
4974 if (attributes_set_explicitly[Tag_ARC_CPU_base]
4975 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4976 Tag_ARC_CPU_base)))
4977 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4978 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
4979
4980 /* Tag_ARC_ABI_osver. */
4981 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
4982 {
4983 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4984 Tag_ARC_ABI_osver);
4985
4986 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
4987 | (val & 0x0f << 8));
4988 }
4989 else
4990 {
4991 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
4992 }
4993
4994 /* Tag_ARC_ISA_config. */
4995 arc_check_feature();
4996
4997 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
4998 if (selected_cpu.features & feature_list[i].feature)
4999 s = arc_stralloc (s, feature_list[i].attr);
5000
5001 if (s)
5002 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5003
5004 /* Tag_ARC_ISA_mpy_option. */
5005 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5006
5007 /* Tag_ARC_ABI_pic. */
5008 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5009
5010 /* Tag_ARC_ABI_sda. */
5011 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5012
5013 /* Tag_ARC_ABI_tls. */
5014 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
5015}
5016
5017/* Add the default contents for the .ARC.attributes section. */
5018
5019void
5020arc_md_end (void)
5021{
5022 arc_set_public_attributes ();
5023
5024 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5025 as_fatal (_("could not set architecture and machine"));
5026
5027 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5028}
5029
5030void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5031{
5032 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5033}
5034
5035int arc_convert_symbolic_attribute (const char *name)
5036{
5037 static const struct
5038 {
5039 const char * name;
5040 const int tag;
5041 }
5042 attribute_table[] =
5043 {
5044#define T(tag) {#tag, tag}
5045 T (Tag_ARC_PCS_config),
5046 T (Tag_ARC_CPU_base),
5047 T (Tag_ARC_CPU_variation),
5048 T (Tag_ARC_CPU_name),
5049 T (Tag_ARC_ABI_rf16),
5050 T (Tag_ARC_ABI_osver),
5051 T (Tag_ARC_ABI_sda),
5052 T (Tag_ARC_ABI_pic),
5053 T (Tag_ARC_ABI_tls),
5054 T (Tag_ARC_ABI_enumsize),
5055 T (Tag_ARC_ABI_exceptions),
5056 T (Tag_ARC_ABI_double_size),
5057 T (Tag_ARC_ISA_config),
5058 T (Tag_ARC_ISA_apex),
5059 T (Tag_ARC_ISA_mpy_option)
5060#undef T
5061 };
5062 unsigned int i;
5063
5064 if (name == NULL)
5065 return -1;
5066
5067 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5068 if (streq (name, attribute_table[i].name))
5069 return attribute_table[i].tag;
5070
5071 return -1;
5072}
5073
b99747ae
CZ		 5074/* Local variables:
5075 eval: (c-set-style "gnu")
5076 indent-tabs-mode: t
5077 End: */
GDB Binutils - Deliverables
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