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gas/arc: Modify structure used to hold opcodes
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132
RH		 30#include "opcode/arc.h"
31#include "elf/arc.h"
32
886a2506 33/* Defines section. */
0d2bcfaf 34
886a2506
NC		 35#define MAX_INSN_FIXUPS 2
36#define MAX_CONSTR_STR 20
4670103e 37#define FRAG_MAX_GROWTH 8
0d2bcfaf 38
886a2506
NC		 39#ifdef DEBUG
40# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
41#else
42# define pr_debug(fmt, args...)
43#endif
44
45#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
46#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
4670103e 47#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
886a2506
NC		 48 (SUB_OPCODE (x) == 0x28))
49
50/* Equal to MAX_PRECISION in atof-ieee.c. */
51#define MAX_LITTLENUMS 6
52
4670103e
CZ		 53/* Enum used to enumerate the relaxable ins operands. */
54enum rlx_operand_type
55{
56 EMPTY = 0,
57 REGISTER,
58 REGISTER_S, /* Register for short instruction(s). */
59 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
60 REGISTER_DUP, /* Duplication of previous operand of type register. */
61 IMMEDIATE,
62 BRACKET
63};
64
65enum arc_rlx_types
66{
67 ARC_RLX_NONE = 0,
68 ARC_RLX_BL_S,
69 ARC_RLX_BL,
70 ARC_RLX_B_S,
71 ARC_RLX_B,
72 ARC_RLX_ADD_U3,
73 ARC_RLX_ADD_U6,
74 ARC_RLX_ADD_LIMM,
75 ARC_RLX_LD_U7,
76 ARC_RLX_LD_S9,
77 ARC_RLX_LD_LIMM,
78 ARC_RLX_MOV_U8,
79 ARC_RLX_MOV_S12,
80 ARC_RLX_MOV_LIMM,
81 ARC_RLX_SUB_U3,
82 ARC_RLX_SUB_U6,
83 ARC_RLX_SUB_LIMM,
84 ARC_RLX_MPY_U6,
85 ARC_RLX_MPY_LIMM,
86 ARC_RLX_MOV_RU6,
87 ARC_RLX_MOV_RLIMM,
88 ARC_RLX_ADD_RRU6,
89 ARC_RLX_ADD_RRLIMM,
90};
91
886a2506
NC		 92/* Macros section. */
93
94#define regno(x) ((x) & 0x3F)
95#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 96#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
97#define is_spfp_p(op) (((sc) == SPX))
98#define is_dpfp_p(op) (((sc) == DPX))
99#define is_fpuda_p(op) (((sc) == DPA))
886a2506
NC		 100#define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
101#define is_kernel_insn_p(op) (((op)->class == KERNEL))
0d2bcfaf 102
886a2506
NC		 103/* Generic assembler global variables which must be defined by all
104 targets. */
0d2bcfaf 105
886a2506 106/* Characters which always start a comment. */
252b5132
RH		 107const char comment_chars[] = "#;";
108
886a2506 109/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 110const char line_comment_chars[] = "#";
111
886a2506
NC		 112/* Characters which may be used to separate multiple commands on a
113 single line. */
114const char line_separator_chars[] = "`";
252b5132 115
886a2506
NC		 116/* Characters which are used to indicate an exponent in a floating
117 point number. */
252b5132
RH		 118const char EXP_CHARS[] = "eE";
119
bcee8eb8
AM		 120/* Chars that mean this number is a floating point constant
121 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 122const char FLT_CHARS[] = "rRsSfFdD";
123
124/* Byte order. */
125extern int target_big_endian;
126const char *arc_target_format = DEFAULT_TARGET_FORMAT;
127static int byte_order = DEFAULT_BYTE_ORDER;
128
4670103e
CZ		 129/* By default relaxation is disabled. */
130static int relaxation_state = 0;
131
886a2506 132extern int arc_get_mach (char *);
0d2bcfaf 133
4670103e 134/* Forward declarations. */
886a2506
NC		 135static void arc_lcomm (int);
136static void arc_option (int);
137static void arc_extra_reloc (int);
252b5132 138
4670103e 139
886a2506 140const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 141{
142 /* Make sure that .word is 32 bits. */
143 { "word", cons, 4 },
886a2506 144
6f4b1afc
CM		 145 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
146 { "lcomm", arc_lcomm, 0 },
147 { "lcommon", arc_lcomm, 0 },
148 { "cpu", arc_option, 0 },
252b5132 149
6f4b1afc
CM		 150 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
151 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 152
6f4b1afc
CM		 153 { NULL, NULL, 0 }
154};
252b5132 155
252b5132 156const char *md_shortopts = "";
ea1562b3
NC		 157
158enum options
6f4b1afc
CM		 159{
160 OPTION_EB = OPTION_MD_BASE,
161 OPTION_EL,
162
163 OPTION_ARC600,
164 OPTION_ARC601,
165 OPTION_ARC700,
166 OPTION_ARCEM,
167 OPTION_ARCHS,
168
169 OPTION_MCPU,
170 OPTION_CD,
4670103e 171 OPTION_RELAX,
6f4b1afc
CM		 172
173 /* The following options are deprecated and provided here only for
174 compatibility reasons. */
175 OPTION_USER_MODE,
176 OPTION_LD_EXT_MASK,
177 OPTION_SWAP,
178 OPTION_NORM,
179 OPTION_BARREL_SHIFT,
180 OPTION_MIN_MAX,
181 OPTION_NO_MPY,
182 OPTION_EA,
183 OPTION_MUL64,
184 OPTION_SIMD,
185 OPTION_SPFP,
186 OPTION_DPFP,
187 OPTION_XMAC_D16,
188 OPTION_XMAC_24,
189 OPTION_DSP_PACKA,
190 OPTION_CRC,
191 OPTION_DVBF,
192 OPTION_TELEPHONY,
193 OPTION_XYMEMORY,
194 OPTION_LOCK,
195 OPTION_SWAPE,
196 OPTION_RTSC,
197 OPTION_FPUDA
198};
ea1562b3
NC		 199
200struct option md_longopts[] =
6f4b1afc
CM		 201{
202 { "EB", no_argument, NULL, OPTION_EB },
203 { "EL", no_argument, NULL, OPTION_EL },
204 { "mcpu", required_argument, NULL, OPTION_MCPU },
205 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 206 { "mARC600", no_argument, NULL, OPTION_ARC600 },
207 { "mARC601", no_argument, NULL, OPTION_ARC601 },
208 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 209 { "mA7", no_argument, NULL, OPTION_ARC700 },
210 { "mEM", no_argument, NULL, OPTION_ARCEM },
211 { "mHS", no_argument, NULL, OPTION_ARCHS },
212 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 213 { "mrelax", no_argument, NULL, OPTION_RELAX },
6f4b1afc
CM		 214
215 /* The following options are deprecated and provided here only for
216 compatibility reasons. */
217 { "mav2em", no_argument, NULL, OPTION_ARCEM },
218 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
219 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
220 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
221 { "mswap", no_argument, NULL, OPTION_SWAP },
222 { "mnorm", no_argument, NULL, OPTION_NORM },
223 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
224 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
225 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
226 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
227 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
228 { "mea", no_argument, NULL, OPTION_EA },
229 { "mEA", no_argument, NULL, OPTION_EA },
230 { "mmul64", no_argument, NULL, OPTION_MUL64 },
231 { "msimd", no_argument, NULL, OPTION_SIMD},
232 { "mspfp", no_argument, NULL, OPTION_SPFP},
233 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
234 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
235 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
236 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
237 { "mdpfp", no_argument, NULL, OPTION_DPFP},
238 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
239 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
240 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
241 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
242 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
243 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
244 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
245 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
246 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
247 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
248 { "mcrc", no_argument, NULL, OPTION_CRC},
249 { "mdvbf", no_argument, NULL, OPTION_DVBF},
250 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
251 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
252 { "mlock", no_argument, NULL, OPTION_LOCK},
253 { "mswape", no_argument, NULL, OPTION_SWAPE},
254 { "mrtsc", no_argument, NULL, OPTION_RTSC},
255 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
256
257 { NULL, no_argument, NULL, 0 }
258};
252b5132 259
886a2506 260size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 261
886a2506 262/* Local data and data types. */
252b5132 263
886a2506
NC		 264/* Used since new relocation types are introduced in this
265 file (DUMMY_RELOC_LITUSE_*). */
266typedef int extended_bfd_reloc_code_real_type;
252b5132 267
886a2506 268struct arc_fixup
252b5132 269{
886a2506 270 expressionS exp;
252b5132 271
886a2506 272 extended_bfd_reloc_code_real_type reloc;
252b5132 273
886a2506
NC		 274 /* index into arc_operands. */
275 unsigned int opindex;
252b5132 276
886a2506
NC		 277 /* PC-relative, used by internals fixups. */
278 unsigned char pcrel;
252b5132 279
886a2506
NC		 280 /* TRUE if this fixup is for LIMM operand. */
281 bfd_boolean islong;
282};
252b5132 283
886a2506
NC		 284struct arc_insn
285{
286 unsigned int insn;
287 int nfixups;
288 struct arc_fixup fixups[MAX_INSN_FIXUPS];
289 long limm;
290 bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
291 short. */
292 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
293 valid. */
4670103e
CZ		 294 bfd_boolean relax; /* Boolean value: TRUE if needs
295 relaxation. */
886a2506 296};
ea1562b3 297
886a2506
NC		 298/* Structure to hold any last two instructions. */
299static struct arc_last_insn
252b5132 300{
886a2506
NC		 301 /* Saved instruction opcode. */
302 const struct arc_opcode *opcode;
252b5132 303
886a2506
NC		 304 /* Boolean value: TRUE if current insn is short. */
305 bfd_boolean has_limm;
252b5132 306
886a2506
NC		 307 /* Boolean value: TRUE if current insn has delay slot. */
308 bfd_boolean has_delay_slot;
309} arc_last_insns[2];
252b5132 310
da5be039
AB		 311/* Structure to hold an entry in ARC_OPCODE_HASH. */
312struct arc_opcode_hash_entry
313{
314 /* The number of pointers in the OPCODE list. */
315 size_t count;
316
317 /* Points to a list of opcode pointers. */
318 const struct arc_opcode **opcode;
319};
320
4670103e
CZ		 321/* Forward declaration. */
322static void assemble_insn
323 (const struct arc_opcode *, const expressionS *, int,
324 const struct arc_flags *, int, struct arc_insn *);
325
886a2506 326/* The cpu for which we are generating code. */
24740d83
AB		 327static unsigned arc_target;
328static const char *arc_target_name;
329static unsigned arc_features;
252b5132 330
886a2506 331/* The default architecture. */
24740d83 332static int arc_mach_type;
252b5132 333
886a2506
NC		 334/* Non-zero if the cpu type has been explicitly specified. */
335static int mach_type_specified_p = 0;
0d2bcfaf 336
886a2506
NC		 337/* The hash table of instruction opcodes. */
338static struct hash_control *arc_opcode_hash;
0d2bcfaf 339
886a2506
NC		 340/* The hash table of register symbols. */
341static struct hash_control *arc_reg_hash;
252b5132 342
886a2506
NC		 343/* A table of CPU names and opcode sets. */
344static const struct cpu_type
345{
346 const char *name;
347 unsigned flags;
348 int mach;
349 unsigned eflags;
350 unsigned features;
252b5132 351}
886a2506 352 cpu_types[] =
252b5132 353{
886a2506
NC		 354 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
355 E_ARC_MACH_ARC600, 0x00},
356 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
357 E_ARC_MACH_ARC700, 0x00},
8699fc3e
AB		 358 { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
359 E_ARC_MACH_NPS400, 0x00},
886a2506 360 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
7e458899 361 EF_ARC_CPU_ARCV2EM, ARC_CD},
886a2506
NC		 362 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
363 EF_ARC_CPU_ARCV2HS, ARC_CD},
886a2506
NC		 364 { 0, 0, 0, 0, 0 }
365};
252b5132 366
886a2506
NC		 367/* Used by the arc_reloc_op table. Order is important. */
368#define O_gotoff O_md1 /* @gotoff relocation. */
369#define O_gotpc O_md2 /* @gotpc relocation. */
370#define O_plt O_md3 /* @plt relocation. */
371#define O_sda O_md4 /* @sda relocation. */
372#define O_pcl O_md5 /* @pcl relocation. */
373#define O_tlsgd O_md6 /* @tlsgd relocation. */
374#define O_tlsie O_md7 /* @tlsie relocation. */
375#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
376#define O_tpoff O_md9 /* @tpoff relocation. */
377#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
378#define O_dtpoff O_md11 /* @dtpoff relocation. */
379#define O_last O_dtpoff
380
381/* Used to define a bracket as operand in tokens. */
382#define O_bracket O_md32
383
384/* Dummy relocation, to be sorted out. */
385#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
386
387#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
388
389/* A table to map the spelling of a relocation operand into an appropriate
390 bfd_reloc_code_real_type type. The table is assumed to be ordered such
391 that op-O_literal indexes into it. */
392#define ARC_RELOC_TABLE(op) \
393 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
394 ? (abort (), 0) \
395 : (int) (op) - (int) O_gotoff) ])
396
397#define DEF(NAME, RELOC, REQ) \
398 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
399
400static const struct arc_reloc_op_tag
401{
402 /* String to lookup. */
403 const char *name;
404 /* Size of the string. */
405 size_t length;
406 /* Which operator to use. */
407 operatorT op;
408 extended_bfd_reloc_code_real_type reloc;
409 /* Allows complex relocation expression like identifier@reloc +
410 const. */
411 unsigned int complex_expr : 1;
412}
413 arc_reloc_op[] =
6f4b1afc
CM		 414{
415 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
416 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
417 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
418 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
419 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
420 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
421 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
422 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 423 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc
CM		 424 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
425 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0),
426};
252b5132 427
886a2506
NC		 428static const int arc_num_reloc_op
429= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
430
4670103e
CZ		 431/* Structure for relaxable instruction that have to be swapped with a
432 smaller alternative instruction. */
433struct arc_relaxable_ins
434{
435 /* Mnemonic that should be checked. */
436 const char *mnemonic_r;
437
438 /* Operands that should be checked.
439 Indexes of operands from operand array. */
440 enum rlx_operand_type operands[6];
441
442 /* Flags that should be checked. */
443 unsigned flag_classes[5];
444
445 /* Mnemonic (smaller) alternative to be used later for relaxation. */
446 const char *mnemonic_alt;
447
448 /* Index of operand that generic relaxation has to check. */
449 unsigned opcheckidx;
450
451 /* Base subtype index used. */
452 enum arc_rlx_types subtype;
453};
454
455#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
456 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
457 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
458 (SIZE), \
459 (NEXT) } \
460
461#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
462 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
463 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
464 (SIZE), \
465 (NEXT) } \
466
467
468/* ARC relaxation table. */
469const relax_typeS md_relax_table[] =
470{
471 /* Fake entry. */
472 {0, 0, 0, 0},
473
474 /* BL_S s13 ->
475 BL s25. */
476 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL),
477 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
478
479 /* B_S s10 ->
480 B s25. */
481 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B),
482 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
483
484 /* ADD_S c,b, u3 ->
485 ADD<.f> a,b,u6 ->
486 ADD<.f> a,b,limm. */
487 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6),
488 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM),
489 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
490
491 /* LD_S a, [b, u7] ->
492 LD<zz><.x><.aa><.di> a, [b, s9] ->
493 LD<zz><.x><.aa><.di> a, [b, limm] */
494 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9),
495 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM),
496 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE),
497
498 /* MOV_S b, u8 ->
499 MOV<.f> b, s12 ->
500 MOV<.f> b, limm. */
501 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12),
502 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM),
503 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
504
505 /* SUB_S c, b, u3 ->
506 SUB<.f> a, b, u6 ->
507 SUB<.f> a, b, limm. */
508 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6),
509 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM),
510 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
511
512 /* MPY<.f> a, b, u6 ->
513 MPY<.f> a, b, limm. */
514 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM),
515 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
516
517 /* MOV<.f><.cc> b, u6 ->
518 MOV<.f><.cc> b, limm. */
519 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM),
520 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
521
522 /* ADD<.f><.cc> b, b, u6 ->
523 ADD<.f><.cc> b, b, limm. */
524 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM),
525 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
526};
527
528/* Order of this table's entries matters! */
529const struct arc_relaxable_ins arc_relaxable_insns[] =
530{
531 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
532 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
533 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
534 2, ARC_RLX_ADD_RRU6},
535 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
536 ARC_RLX_ADD_U3 },
537 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
538 ARC_RLX_ADD_U6 },
539 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
540 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
541 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
542 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
543 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
544 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
545 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
546 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
547 ARC_RLX_SUB_U3 },
548 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
549 ARC_RLX_SUB_U6 },
550 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
551 ARC_RLX_MPY_U6 },
552};
553
554const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
555
886a2506
NC		 556/* Flags to set in the elf header. */
557static flagword arc_eflag = 0x00;
558
559/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
560symbolS * GOT_symbol = 0;
561
562/* Set to TRUE when we assemble instructions. */
563static bfd_boolean assembling_insn = FALSE;
564
886a2506
NC		 565/* Functions implementation. */
566
da5be039
AB		 567/* Return a pointer to the first entry in ARC_OPCODE_HASH that matches
568 NAME, or NULL if there are no matching entries. */
569
570static const struct arc_opcode *
571arc_find_opcode (const char *name)
572{
573 const struct arc_opcode_hash_entry *entry;
574 const struct arc_opcode *opcode;
575
576 entry = hash_find (arc_opcode_hash, name);
577 if (entry != NULL)
578 {
579 if (entry->count > 1)
580 as_fatal (_("unable to lookup `%s', too many opcode chains"),
581 name);
582 opcode = *entry->opcode;
583 }
584 else
585 opcode = NULL;
586
587 return opcode;
588}
589
886a2506
NC		 590/* Like md_number_to_chars but used for limms. The 4-byte limm value,
591 is encoded as 'middle-endian' for a little-endian target. FIXME!
592 this function is used for regular 4 byte instructions as well. */
593
594static void
6f4b1afc 595md_number_to_chars_midend (char *buf, valueT val, int n)
886a2506
NC		 596{
597 if (n == 4)
598 {
599 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
600 md_number_to_chars (buf + 2, (val & 0xffff), 2);
252b5132
RH		 601 }
602 else
886a2506
NC		 603 {
604 md_number_to_chars (buf, val, n);
605 }
252b5132
RH		 606}
607
24740d83
AB		 608/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
609 the relevant static global variables. */
610
611static void
612arc_select_cpu (const char *arg)
613{
a9522a21 614 int cpu_flags = 0;
24740d83
AB		 615 int i;
616
617 for (i = 0; cpu_types[i].name; ++i)
618 {
619 if (!strcasecmp (cpu_types[i].name, arg))
620 {
621 arc_target = cpu_types[i].flags;
622 arc_target_name = cpu_types[i].name;
623 arc_features = cpu_types[i].features;
624 arc_mach_type = cpu_types[i].mach;
625 cpu_flags = cpu_types[i].eflags;
626 break;
627 }
628 }
629
630 if (!cpu_types[i].name)
631 as_fatal (_("unknown architecture: %s\n"), arg);
a9522a21
AB		 632 gas_assert (cpu_flags != 0);
633 arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
24740d83
AB		 634}
635
886a2506
NC		 636/* Here ends all the ARCompact extension instruction assembling
637 stuff. */
252b5132 638
886a2506
NC		 639static void
640arc_extra_reloc (int r_type)
ea1562b3 641{
886a2506
NC		 642 char *sym_name, c;
643 symbolS *sym, *lab = NULL;
644
645 if (*input_line_pointer == '@')
646 input_line_pointer++;
647 c = get_symbol_name (&sym_name);
648 sym = symbol_find_or_make (sym_name);
649 restore_line_pointer (c);
650 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
651 {
652 ++input_line_pointer;
653 char *lab_name;
654 c = get_symbol_name (&lab_name);
655 lab = symbol_find_or_make (lab_name);
656 restore_line_pointer (c);
657 }
841fdfcd
CZ		 658
659 /* These relocations exist as a mechanism for the compiler to tell the
660 linker how to patch the code if the tls model is optimised. However,
661 the relocation itself does not require any space within the assembler
662 fragment, and so we pass a size of 0.
663
664 The lines that generate these relocations look like this:
665
666 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
667
668 The '.tls_gd_ld @.tdata' is processed first and generates the
669 additional relocation, while the 'bl __tls_get_addr@plt' is processed
670 second and generates the additional branch.
671
672 It is possible that the additional relocation generated by the
673 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
674 while the 'bl __tls_get_addr@plt' will be generated as the first thing
675 in the next fragment. This will be fine; both relocations will still
676 appear to be at the same address in the generated object file.
677 However, this only works as the additional relocation is generated
678 with size of 0 bytes. */
886a2506
NC		 679 fixS *fixP
680 = fix_new (frag_now, /* Which frag? */
681 frag_now_fix (), /* Where in that frag? */
841fdfcd 682 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 683 sym, /* X_add_symbol. */
684 0, /* X_add_number. */
685 FALSE, /* TRUE if PC-relative relocation. */
686 r_type /* Relocation type. */);
687 fixP->fx_subsy = lab;
688}
252b5132 689
886a2506
NC		 690static symbolS *
691arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
692 symbolS *symbolP, addressT size)
693{
694 addressT align = 0;
695 SKIP_WHITESPACE ();
252b5132 696
886a2506
NC		 697 if (*input_line_pointer == ',')
698 {
699 align = parse_align (1);
252b5132 700
886a2506
NC		 701 if (align == (addressT) -1)
702 return NULL;
703 }
704 else
705 {
706 if (size >= 8)
707 align = 3;
708 else if (size >= 4)
709 align = 2;
710 else if (size >= 2)
711 align = 1;
712 else
713 align = 0;
714 }
252b5132 715
886a2506
NC		 716 bss_alloc (symbolP, size, align);
717 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 718
886a2506
NC		 719 return symbolP;
720}
ea1562b3 721
886a2506
NC		 722static void
723arc_lcomm (int ignore)
724{
725 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 726
886a2506
NC		 727 if (symbolP)
728 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
729}
ea1562b3 730
886a2506 731/* Select the cpu we're assembling for. */
ea1562b3 732
886a2506
NC		 733static void
734arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 735{
886a2506
NC		 736 int mach = -1;
737 char c;
738 char *cpu;
252b5132 739
886a2506
NC		 740 c = get_symbol_name (&cpu);
741 mach = arc_get_mach (cpu);
252b5132 742
886a2506
NC		 743 if (mach == -1)
744 goto bad_cpu;
745
746 if (!mach_type_specified_p)
ea1562b3 747 {
24b368f8
CZ		 748 if ((!strcmp ("ARC600", cpu))
749 || (!strcmp ("ARC601", cpu))
750 || (!strcmp ("A6", cpu)))
751 {
752 md_parse_option (OPTION_MCPU, "arc600");
753 }
754 else if ((!strcmp ("ARC700", cpu))
755 || (!strcmp ("A7", cpu)))
756 {
757 md_parse_option (OPTION_MCPU, "arc700");
758 }
759 else if (!strcmp ("EM", cpu))
760 {
761 md_parse_option (OPTION_MCPU, "arcem");
762 }
763 else if (!strcmp ("HS", cpu))
764 {
765 md_parse_option (OPTION_MCPU, "archs");
766 }
767 else
e6ba1cba 768 as_fatal (_("could not find the architecture"));
24b368f8 769
886a2506 770 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
e6ba1cba 771 as_fatal (_("could not set architecture and machine"));
ea1562b3
NC		 772 }
773 else
886a2506 774 if (arc_mach_type != mach)
e6ba1cba 775 as_warn (_("Command-line value overrides \".cpu\" directive"));
886a2506 776
24b368f8 777 restore_line_pointer (c);
886a2506 778 demand_empty_rest_of_line ();
886a2506
NC		 779 return;
780
781 bad_cpu:
24b368f8 782 restore_line_pointer (c);
e6ba1cba 783 as_bad (_("invalid identifier for \".cpu\""));
886a2506 784 ignore_rest_of_line ();
ea1562b3 785}
252b5132 786
886a2506
NC		 787/* Smartly print an expression. */
788
ea1562b3 789static void
886a2506 790debug_exp (expressionS *t)
ea1562b3 791{
886a2506
NC		 792 const char *name ATTRIBUTE_UNUSED;
793 const char *namemd ATTRIBUTE_UNUSED;
252b5132 794
886a2506 795 pr_debug ("debug_exp: ");
252b5132 796
886a2506 797 switch (t->X_op)
252b5132 798 {
886a2506
NC		 799 default: name = "unknown"; break;
800 case O_illegal: name = "O_illegal"; break;
801 case O_absent: name = "O_absent"; break;
802 case O_constant: name = "O_constant"; break;
803 case O_symbol: name = "O_symbol"; break;
804 case O_symbol_rva: name = "O_symbol_rva"; break;
805 case O_register: name = "O_register"; break;
806 case O_big: name = "O_big"; break;
807 case O_uminus: name = "O_uminus"; break;
808 case O_bit_not: name = "O_bit_not"; break;
809 case O_logical_not: name = "O_logical_not"; break;
810 case O_multiply: name = "O_multiply"; break;
811 case O_divide: name = "O_divide"; break;
812 case O_modulus: name = "O_modulus"; break;
813 case O_left_shift: name = "O_left_shift"; break;
814 case O_right_shift: name = "O_right_shift"; break;
815 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
816 case O_bit_or_not: name = "O_bit_or_not"; break;
817 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
818 case O_bit_and: name = "O_bit_and"; break;
819 case O_add: name = "O_add"; break;
820 case O_subtract: name = "O_subtract"; break;
821 case O_eq: name = "O_eq"; break;
822 case O_ne: name = "O_ne"; break;
823 case O_lt: name = "O_lt"; break;
824 case O_le: name = "O_le"; break;
825 case O_ge: name = "O_ge"; break;
826 case O_gt: name = "O_gt"; break;
827 case O_logical_and: name = "O_logical_and"; break;
828 case O_logical_or: name = "O_logical_or"; break;
829 case O_index: name = "O_index"; break;
830 case O_bracket: name = "O_bracket"; break;
ea1562b3 831 }
252b5132 832
886a2506 833 switch (t->X_md)
ea1562b3 834 {
886a2506
NC		 835 default: namemd = "unknown"; break;
836 case O_gotoff: namemd = "O_gotoff"; break;
837 case O_gotpc: namemd = "O_gotpc"; break;
838 case O_plt: namemd = "O_plt"; break;
839 case O_sda: namemd = "O_sda"; break;
840 case O_pcl: namemd = "O_pcl"; break;
841 case O_tlsgd: namemd = "O_tlsgd"; break;
842 case O_tlsie: namemd = "O_tlsie"; break;
843 case O_tpoff9: namemd = "O_tpoff9"; break;
844 case O_tpoff: namemd = "O_tpoff"; break;
845 case O_dtpoff9: namemd = "O_dtpoff9"; break;
846 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 847 }
252b5132 848
886a2506
NC		 849 pr_debug ("%s (%s, %s, %d, %s)", name,
850 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
851 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
852 (int) t->X_add_number,
853 (t->X_md) ? namemd : "--");
854 pr_debug ("\n");
855 fflush (stderr);
856}
252b5132 857
886a2506
NC		 858/* Parse the arguments to an opcode. */
859
860static int
861tokenize_arguments (char *str,
862 expressionS *tok,
863 int ntok)
864{
865 char *old_input_line_pointer;
866 bfd_boolean saw_comma = FALSE;
867 bfd_boolean saw_arg = FALSE;
868 int brk_lvl = 0;
869 int num_args = 0;
886a2506
NC		 870 int i;
871 size_t len;
872 const struct arc_reloc_op_tag *r;
873 expressionS tmpE;
6f4b1afc 874 char *reloc_name, c;
886a2506
NC		 875
876 memset (tok, 0, sizeof (*tok) * ntok);
877
878 /* Save and restore input_line_pointer around this function. */
879 old_input_line_pointer = input_line_pointer;
880 input_line_pointer = str;
ea1562b3 881
886a2506 882 while (*input_line_pointer)
ea1562b3
NC		 883 {
884 SKIP_WHITESPACE ();
886a2506 885 switch (*input_line_pointer)
252b5132 886 {
886a2506
NC		 887 case '\0':
888 goto fini;
889
890 case ',':
891 input_line_pointer++;
892 if (saw_comma || !saw_arg)
893 goto err;
894 saw_comma = TRUE;
895 break;
252b5132 896
886a2506
NC		 897 case '}':
898 case ']':
899 ++input_line_pointer;
900 --brk_lvl;
901 if (!saw_arg)
902 goto err;
903 tok->X_op = O_bracket;
904 ++tok;
905 ++num_args;
906 break;
ea1562b3 907
886a2506
NC		 908 case '{':
909 case '[':
910 input_line_pointer++;
911 if (brk_lvl)
912 goto err;
913 ++brk_lvl;
914 tok->X_op = O_bracket;
915 ++tok;
916 ++num_args;
917 break;
918
919 case '@':
920 /* We have labels, function names and relocations, all
921 starting with @ symbol. Sort them out. */
922 if (saw_arg && !saw_comma)
923 goto err;
924
925 /* Parse @label. */
926 tok->X_op = O_symbol;
927 tok->X_md = O_absent;
928 expression (tok);
929 if (*input_line_pointer != '@')
930 goto normalsymbol; /* This is not a relocation. */
931
6f4b1afc
CM		 932 relocationsym:
933
886a2506
NC		 934 /* A relocation opernad has the following form
935 @identifier@relocation_type. The identifier is already
936 in tok! */
937 if (tok->X_op != O_symbol)
ea1562b3 938 {
886a2506
NC		 939 as_bad (_("No valid label relocation operand"));
940 goto err;
252b5132 941 }
886a2506
NC		 942
943 /* Parse @relocation_type. */
6f4b1afc
CM		 944 input_line_pointer++;
945 c = get_symbol_name (&reloc_name);
946 len = input_line_pointer - reloc_name;
947 if (len == 0)
252b5132 948 {
886a2506
NC		 949 as_bad (_("No relocation operand"));
950 goto err;
252b5132 951 }
252b5132 952
886a2506
NC		 953 /* Go through known relocation and try to find a match. */
954 r = &arc_reloc_op[0];
955 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 956 if (len == r->length
957 && memcmp (reloc_name, r->name, len) == 0)
886a2506 958 break;
886a2506 959 if (i < 0)
252b5132 960 {
6f4b1afc 961 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 962 goto err;
963 }
964
6f4b1afc
CM		 965 *input_line_pointer = c;
966 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 967 /* Extra check for TLS: base. */
968 if (*input_line_pointer == '@')
969 {
970 symbolS *base;
971 if (tok->X_op_symbol != NULL
972 || tok->X_op != O_symbol)
252b5132 973 {
6f4b1afc
CM		 974 as_bad (_("Unable to parse TLS base: %s"),
975 input_line_pointer);
886a2506 976 goto err;
252b5132 977 }
886a2506
NC		 978 input_line_pointer++;
979 char *sym_name;
6f4b1afc 980 c = get_symbol_name (&sym_name);
886a2506
NC		 981 base = symbol_find_or_make (sym_name);
982 tok->X_op = O_subtract;
983 tok->X_op_symbol = base;
984 restore_line_pointer (c);
6f4b1afc
CM		 985 tmpE.X_add_number = 0;
986 }
987 else if ((*input_line_pointer != '+')
988 && (*input_line_pointer != '-'))
989 {
990 tmpE.X_add_number = 0;
ea1562b3 991 }
6f4b1afc
CM		 992 else
993 {
994 /* Parse the constant of a complex relocation expression
995 like @identifier@reloc +/- const. */
996 if (! r->complex_expr)
997 {
998 as_bad (_("@%s is not a complex relocation."), r->name);
999 goto err;
1000 }
1001 expression (&tmpE);
1002 if (tmpE.X_op != O_constant)
1003 {
1004 as_bad (_("Bad expression: @%s + %s."),
1005 r->name, input_line_pointer);
1006 goto err;
1007 }
1008 }
1009
1010 tok->X_md = r->op;
1011 tok->X_add_number = tmpE.X_add_number;
1e07b820 1012
886a2506 1013 debug_exp (tok);
ea1562b3 1014
886a2506
NC		 1015 saw_comma = FALSE;
1016 saw_arg = TRUE;
1017 tok++;
1018 num_args++;
1019 break;
252b5132 1020
886a2506
NC		 1021 case '%':
1022 /* Can be a register. */
1023 ++input_line_pointer;
1024 /* Fall through. */
1025 default:
252b5132 1026
886a2506
NC		 1027 if (saw_arg && !saw_comma)
1028 goto err;
252b5132 1029
886a2506 1030 tok->X_op = O_absent;
6f4b1afc 1031 tok->X_md = O_absent;
886a2506 1032 expression (tok);
252b5132 1033
6f4b1afc
CM		 1034 /* Legacy: There are cases when we have
1035 identifier@relocation_type, if it is the case parse the
1036 relocation type as well. */
1037 if (*input_line_pointer == '@')
1038 goto relocationsym;
1039
886a2506
NC		 1040 normalsymbol:
1041 debug_exp (tok);
252b5132 1042
886a2506
NC		 1043 if (tok->X_op == O_illegal || tok->X_op == O_absent)
1044 goto err;
252b5132 1045
886a2506
NC		 1046 saw_comma = FALSE;
1047 saw_arg = TRUE;
1048 tok++;
1049 num_args++;
1050 break;
1051 }
ea1562b3 1052 }
252b5132 1053
886a2506
NC		 1054 fini:
1055 if (saw_comma || brk_lvl)
1056 goto err;
1057 input_line_pointer = old_input_line_pointer;
252b5132 1058
886a2506 1059 return num_args;
252b5132 1060
886a2506
NC		 1061 err:
1062 if (brk_lvl)
1063 as_bad (_("Brackets in operand field incorrect"));
1064 else if (saw_comma)
1065 as_bad (_("extra comma"));
1066 else if (!saw_arg)
1067 as_bad (_("missing argument"));
1068 else
1069 as_bad (_("missing comma or colon"));
1070 input_line_pointer = old_input_line_pointer;
1071 return -1;
252b5132 1072}
ea1562b3 1073
886a2506
NC		 1074/* Parse the flags to a structure. */
1075
1076static int
1077tokenize_flags (const char *str,
1078 struct arc_flags flags[],
1079 int nflg)
252b5132 1080{
886a2506
NC		 1081 char *old_input_line_pointer;
1082 bfd_boolean saw_flg = FALSE;
1083 bfd_boolean saw_dot = FALSE;
1084 int num_flags = 0;
1085 size_t flgnamelen;
252b5132 1086
886a2506 1087 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1088
886a2506
NC		 1089 /* Save and restore input_line_pointer around this function. */
1090 old_input_line_pointer = input_line_pointer;
1091 input_line_pointer = (char *) str;
0d2bcfaf 1092
886a2506
NC		 1093 while (*input_line_pointer)
1094 {
1095 switch (*input_line_pointer)
1096 {
1097 case ' ':
1098 case '\0':
1099 goto fini;
1100
1101 case '.':
1102 input_line_pointer++;
1103 if (saw_dot)
1104 goto err;
1105 saw_dot = TRUE;
1106 saw_flg = FALSE;
1107 break;
ea1562b3 1108
886a2506
NC		 1109 default:
1110 if (saw_flg && !saw_dot)
1111 goto err;
0d2bcfaf 1112
886a2506
NC		 1113 if (num_flags >= nflg)
1114 goto err;
0d2bcfaf 1115
692166c2
AB		 1116 flgnamelen = strspn (input_line_pointer,
1117 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1118 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1119 goto err;
0d2bcfaf 1120
886a2506 1121 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1122
886a2506
NC		 1123 input_line_pointer += flgnamelen;
1124 flags++;
1125 saw_dot = FALSE;
1126 saw_flg = TRUE;
1127 num_flags++;
1128 break;
1e07b820 1129 }
0d2bcfaf
NC		 1130 }
1131
886a2506
NC		 1132 fini:
1133 input_line_pointer = old_input_line_pointer;
1134 return num_flags;
0d2bcfaf 1135
886a2506
NC		 1136 err:
1137 if (saw_dot)
1138 as_bad (_("extra dot"));
1139 else if (!saw_flg)
1140 as_bad (_("unrecognized flag"));
1141 else
1142 as_bad (_("failed to parse flags"));
1143 input_line_pointer = old_input_line_pointer;
1144 return -1;
1145}
0d2bcfaf 1146
4670103e 1147/* Apply the fixups in order. */
0d2bcfaf 1148
4670103e
CZ		 1149static void
1150apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1151{
4670103e 1152 int i;
0d2bcfaf 1153
4670103e 1154 for (i = 0; i < insn->nfixups; i++)
252b5132 1155 {
4670103e
CZ		 1156 struct arc_fixup *fixup = &insn->fixups[i];
1157 int size, pcrel, offset = 0;
0d2bcfaf 1158
4670103e
CZ		 1159 /* FIXME! the reloc size is wrong in the BFD file.
1160 When it is fixed please delete me. */
1161 size = (insn->short_insn && !fixup->islong) ? 2 : 4;
0d2bcfaf 1162
4670103e
CZ		 1163 if (fixup->islong)
1164 offset = (insn->short_insn) ? 2 : 4;
252b5132 1165
4670103e
CZ		 1166 /* Some fixups are only used internally, thus no howto. */
1167 if ((int) fixup->reloc == 0)
1168 as_fatal (_("Unhandled reloc type"));
886a2506 1169
4670103e
CZ		 1170 if ((int) fixup->reloc < 0)
1171 {
1172 /* FIXME! the reloc size is wrong in the BFD file.
1173 When it is fixed please enable me.
1174 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1175 pcrel = fixup->pcrel;
1176 }
1177 else
1178 {
1179 reloc_howto_type *reloc_howto =
1180 bfd_reloc_type_lookup (stdoutput,
1181 (bfd_reloc_code_real_type) fixup->reloc);
1182 gas_assert (reloc_howto);
0d2bcfaf 1183
4670103e
CZ		 1184 /* FIXME! the reloc size is wrong in the BFD file.
1185 When it is fixed please enable me.
1186 size = bfd_get_reloc_size (reloc_howto); */
1187 pcrel = reloc_howto->pc_relative;
1188 }
0d2bcfaf 1189
4670103e
CZ		 1190 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1191offset %d + %d\n",
1192 fragP->fr_file, fragP->fr_line,
1193 (fixup->reloc < 0) ? "Internal" :
1194 bfd_get_reloc_code_name (fixup->reloc),
1195 pcrel ? "Y" : "N",
1196 size, fix, offset);
1197 fix_new_exp (fragP, fix + offset,
1198 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1199
4670103e
CZ		 1200 /* Check for ZOLs, and update symbol info if any. */
1201 if (LP_INSN (insn->insn))
886a2506 1202 {
4670103e
CZ		 1203 gas_assert (fixup->exp.X_add_symbol);
1204 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1205 }
1206 }
252b5132
RH		 1207}
1208
4670103e 1209/* Actually output an instruction with its fixup. */
886a2506 1210
4670103e
CZ		 1211static void
1212emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1213{
4670103e 1214 char *f = where;
252b5132 1215
4670103e
CZ		 1216 pr_debug ("Emit insn : 0x%x\n", insn->insn);
1217 pr_debug ("\tShort : 0x%d\n", insn->short_insn);
1218 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1219
4670103e
CZ		 1220 /* Write out the instruction. */
1221 if (insn->short_insn)
0d2bcfaf 1222 {
4670103e
CZ		 1223 if (insn->has_limm)
1224 {
1225 if (!relax)
1226 f = frag_more (6);
1227 md_number_to_chars (f, insn->insn, 2);
1228 md_number_to_chars_midend (f + 2, insn->limm, 4);
1229 dwarf2_emit_insn (6);
1230 }
1231 else
1232 {
1233 if (!relax)
1234 f = frag_more (2);
1235 md_number_to_chars (f, insn->insn, 2);
1236 dwarf2_emit_insn (2);
1237 }
1238 }
1239 else
1240 {
1241 if (insn->has_limm)
1242 {
1243 if (!relax)
1244 f = frag_more (8);
1245 md_number_to_chars_midend (f, insn->insn, 4);
1246 md_number_to_chars_midend (f + 4, insn->limm, 4);
1247 dwarf2_emit_insn (8);
1248 }
1249 else
1250 {
1251 if (!relax)
1252 f = frag_more (4);
1253 md_number_to_chars_midend (f, insn->insn, 4);
1254 dwarf2_emit_insn (4);
1255 }
252b5132 1256 }
252b5132 1257
4670103e
CZ		 1258 if (!relax)
1259 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1260}
252b5132 1261
4670103e
CZ		 1262static void
1263emit_insn1 (struct arc_insn *insn)
1264{
1265 /* How frag_var's args are currently configured:
1266 - rs_machine_dependent, to dictate it's a relaxation frag.
1267 - FRAG_MAX_GROWTH, maximum size of instruction
1268 - 0, variable size that might grow...unused by generic relaxation.
1269 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1270 - s, opand expression.
1271 - 0, offset but it's unused.
1272 - 0, opcode but it's unused. */
1273 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1274 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1275
1276 if (frag_room () < FRAG_MAX_GROWTH)
1277 {
1278 /* Handle differently when frag literal memory is exhausted.
1279 This is used because when there's not enough memory left in
1280 the current frag, a new frag is created and the information
1281 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1282
4670103e
CZ		 1283 struct arc_relax_type relax_info_copy;
1284 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1285
4670103e
CZ		 1286 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1287 sizeof (struct arc_relax_type));
0d2bcfaf 1288
4670103e
CZ		 1289 frag_wane (frag_now);
1290 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1291
4670103e
CZ		 1292 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1293 sizeof (struct arc_relax_type));
252b5132 1294
4670103e
CZ		 1295 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1296 subtype, s, 0, 0);
1297 }
1298 else
1299 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1300 frag_now->fr_subtype, s, 0, 0);
1301}
252b5132 1302
4670103e
CZ		 1303static void
1304emit_insn (struct arc_insn *insn)
252b5132 1305{
4670103e
CZ		 1306 if (insn->relax)
1307 emit_insn1 (insn);
252b5132 1308 else
4670103e 1309 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1310}
1311
4670103e 1312/* Check whether a symbol involves a register. */
252b5132 1313
4670103e
CZ		 1314static bfd_boolean
1315contains_register (symbolS *sym)
252b5132 1316{
4670103e
CZ		 1317 if (sym)
1318 {
1319 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1320
4670103e
CZ		 1321 return ((O_register == ex->X_op)
1322 && !contains_register (ex->X_add_symbol)
1323 && !contains_register (ex->X_op_symbol));
1324 }
1325
1326 return FALSE;
252b5132
RH		 1327}
1328
4670103e 1329/* Returns the register number within a symbol. */
252b5132 1330
4670103e
CZ		 1331static int
1332get_register (symbolS *sym)
252b5132 1333{
4670103e
CZ		 1334 if (!contains_register (sym))
1335 return -1;
0d2bcfaf 1336
4670103e
CZ		 1337 expressionS *ex = symbol_get_value_expression (sym);
1338 return regno (ex->X_add_number);
1339}
252b5132 1340
4670103e
CZ		 1341/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1342 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1343
4670103e
CZ		 1344static bfd_boolean
1345generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1346{
1347 if (!reloc)
1348 return FALSE;
886a2506 1349
4670103e
CZ		 1350 switch (reloc)
1351 {
1352 case BFD_RELOC_ARC_SDA_LDST:
1353 case BFD_RELOC_ARC_SDA_LDST1:
1354 case BFD_RELOC_ARC_SDA_LDST2:
1355 case BFD_RELOC_ARC_SDA16_LD:
1356 case BFD_RELOC_ARC_SDA16_LD1:
1357 case BFD_RELOC_ARC_SDA16_LD2:
1358 case BFD_RELOC_ARC_SDA16_ST2:
1359 case BFD_RELOC_ARC_SDA32_ME:
1360 return FALSE;
1361 default:
1362 return TRUE;
f17c130b 1363 }
252b5132
RH		 1364}
1365
4670103e 1366/* Allocates a tok entry. */
252b5132 1367
4670103e
CZ		 1368static int
1369allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1370{
4670103e
CZ		 1371 if (ntok > MAX_INSN_ARGS - 2)
1372 return 0; /* No space left. */
252b5132 1373
4670103e
CZ		 1374 if (cidx > ntok)
1375 return 0; /* Incorect args. */
252b5132 1376
4670103e 1377 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1378
4670103e
CZ		 1379 if (cidx == ntok)
1380 return 1; /* Success. */
1381 return allocate_tok (tok, ntok - 1, cidx);
1382}
886a2506 1383
8ddf6b2a
CZ		 1384/* Check if an particular ARC feature is enabled. */
1385
1386static bfd_boolean
1387check_cpu_feature (insn_subclass_t sc)
1388{
1389 if (!(arc_features & ARC_CD)
1390 && is_code_density_p (sc))
1391 return FALSE;
1392
1393 if (!(arc_features & ARC_SPFP)
1394 && is_spfp_p (sc))
1395 return FALSE;
1396
1397 if (!(arc_features & ARC_DPFP)
1398 && is_dpfp_p (sc))
1399 return FALSE;
1400
1401 if (!(arc_features & ARC_FPUDA)
1402 && is_fpuda_p (sc))
1403 return FALSE;
1404
1405 return TRUE;
1406}
1407
4670103e
CZ		 1408/* Search forward through all variants of an opcode looking for a
1409 syntax match. */
886a2506 1410
4670103e
CZ		 1411static const struct arc_opcode *
1412find_opcode_match (const struct arc_opcode *first_opcode,
1413 expressionS *tok,
1414 int *pntok,
1415 struct arc_flags *first_pflag,
1416 int nflgs,
1417 int *pcpumatch)
1418{
1419 const struct arc_opcode *opcode = first_opcode;
1420 int ntok = *pntok;
1421 int got_cpu_match = 0;
1422 expressionS bktok[MAX_INSN_ARGS];
1423 int bkntok;
1424 expressionS emptyE;
886a2506 1425
4670103e
CZ		 1426 memset (&emptyE, 0, sizeof (emptyE));
1427 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1428 bkntok = ntok;
a161fe53 1429
4670103e 1430 do
252b5132 1431 {
4670103e
CZ		 1432 const unsigned char *opidx;
1433 const unsigned char *flgidx;
1ae8ab47 1434 int tokidx = 0, lnflg, i;
4670103e 1435 const expressionS *t = &emptyE;
252b5132 1436
4670103e
CZ		 1437 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1438 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1439
4670103e
CZ		 1440 /* Don't match opcodes that don't exist on this
1441 architecture. */
1442 if (!(opcode->cpu & arc_target))
1443 goto match_failed;
886a2506 1444
8ddf6b2a 1445 if (!check_cpu_feature (opcode->subclass))
4670103e 1446 goto match_failed;
886a2506 1447
4670103e
CZ		 1448 got_cpu_match = 1;
1449 pr_debug ("cpu ");
886a2506 1450
4670103e
CZ		 1451 /* Check the operands. */
1452 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1453 {
4670103e 1454 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1455
4670103e
CZ		 1456 /* Only take input from real operands. */
1457 if ((operand->flags & ARC_OPERAND_FAKE)
1458 && !(operand->flags & ARC_OPERAND_BRAKET))
1459 continue;
252b5132 1460
4670103e
CZ		 1461 /* When we expect input, make sure we have it. */
1462 if (tokidx >= ntok)
1463 goto match_failed;
6f4b1afc 1464
4670103e
CZ		 1465 /* Match operand type with expression type. */
1466 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1467 {
1468 case ARC_OPERAND_IR:
1469 /* Check to be a register. */
1470 if ((tok[tokidx].X_op != O_register
1471 || !is_ir_num (tok[tokidx].X_add_number))
1472 && !(operand->flags & ARC_OPERAND_IGNORE))
1473 goto match_failed;
1474
1475 /* If expect duplicate, make sure it is duplicate. */
1476 if (operand->flags & ARC_OPERAND_DUPLICATE)
1477 {
1478 /* Check for duplicate. */
1479 if (t->X_op != O_register
1480 || !is_ir_num (t->X_add_number)
1481 || (regno (t->X_add_number) !=
1482 regno (tok[tokidx].X_add_number)))
1483 goto match_failed;
1484 }
1485
1486 /* Special handling? */
1487 if (operand->insert)
1488 {
1489 const char *errmsg = NULL;
1490 (*operand->insert)(0,
1491 regno (tok[tokidx].X_add_number),
1492 &errmsg);
1493 if (errmsg)
1494 {
1495 if (operand->flags & ARC_OPERAND_IGNORE)
1496 {
1497 /* Missing argument, create one. */
1498 if (!allocate_tok (tok, ntok - 1, tokidx))
1499 goto match_failed;
1500
1501 tok[tokidx].X_op = O_absent;
1502 ++ntok;
1503 }
1504 else
1505 goto match_failed;
1506 }
1507 }
1508
1509 t = &tok[tokidx];
1510 break;
1511
1512 case ARC_OPERAND_BRAKET:
1513 /* Check if bracket is also in opcode table as
1514 operand. */
1515 if (tok[tokidx].X_op != O_bracket)
1516 goto match_failed;
1517 break;
1518
1519 case ARC_OPERAND_LIMM:
1520 case ARC_OPERAND_SIGNED:
1521 case ARC_OPERAND_UNSIGNED:
1522 switch (tok[tokidx].X_op)
1523 {
1524 case O_illegal:
1525 case O_absent:
1526 case O_register:
1527 goto match_failed;
1528
1529 case O_bracket:
1530 /* Got an (too) early bracket, check if it is an
1531 ignored operand. N.B. This procedure works only
1532 when bracket is the last operand! */
1533 if (!(operand->flags & ARC_OPERAND_IGNORE))
1534 goto match_failed;
1535 /* Insert the missing operand. */
1536 if (!allocate_tok (tok, ntok - 1, tokidx))
1537 goto match_failed;
1538
1539 tok[tokidx].X_op = O_absent;
1540 ++ntok;
1541 break;
1542
22b92fc4
AB		 1543 case O_symbol:
1544 {
1545 const char *p;
1546 size_t len;
1547 const struct arc_aux_reg *auxr;
1548 unsigned j;
1549
1550 if (opcode->class != AUXREG)
1551 goto de_fault;
1552 p = S_GET_NAME (tok[tokidx].X_add_symbol);
1553 len = strlen (p);
1554
1555 auxr = &arc_aux_regs[0];
1556 for (j = 0; j < arc_num_aux_regs; j++, auxr++)
1557 if (len == auxr->length
1558 && strcasecmp (auxr->name, p) == 0
1559 && ((auxr->subclass == NONE)
1560 || check_cpu_feature (auxr->subclass)))
1561 {
1562 /* We modify the token array here, safe in the
1563 knowledge, that if this was the wrong choice
1564 then the original contents will be restored
1565 from BKTOK. */
1566 tok[tokidx].X_op = O_constant;
1567 tok[tokidx].X_add_number = auxr->address;
1568 break;
1569 }
1570
1571 if (tok[tokidx].X_op != O_constant)
1572 goto de_fault;
1573 }
1574 /* Fall-through */
4670103e
CZ		 1575 case O_constant:
1576 /* Check the range. */
1577 if (operand->bits != 32
1578 && !(operand->flags & ARC_OPERAND_NCHK))
1579 {
1580 offsetT min, max, val;
1581 val = tok[tokidx].X_add_number;
1582
1583 if (operand->flags & ARC_OPERAND_SIGNED)
1584 {
1585 max = (1 << (operand->bits - 1)) - 1;
1586 min = -(1 << (operand->bits - 1));
1587 }
1588 else
1589 {
1590 max = (1 << operand->bits) - 1;
1591 min = 0;
1592 }
1593
1594 if (val < min || val > max)
1595 goto match_failed;
1596
1597 /* Check alignmets. */
1598 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1599 && (val & 0x03))
1600 goto match_failed;
1601
1602 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1603 && (val & 0x01))
1604 goto match_failed;
1605 }
1606 else if (operand->flags & ARC_OPERAND_NCHK)
1607 {
1608 if (operand->insert)
1609 {
1610 const char *errmsg = NULL;
1611 (*operand->insert)(0,
1612 tok[tokidx].X_add_number,
1613 &errmsg);
1614 if (errmsg)
1615 goto match_failed;
1616 }
1617 else
1618 goto match_failed;
1619 }
1620 break;
1621
1622 case O_subtract:
1623 /* Check if it is register range. */
1624 if ((tok[tokidx].X_add_number == 0)
1625 && contains_register (tok[tokidx].X_add_symbol)
1626 && contains_register (tok[tokidx].X_op_symbol))
1627 {
1628 int regs;
1629
1630 regs = get_register (tok[tokidx].X_add_symbol);
1631 regs <<= 16;
1632 regs |= get_register (tok[tokidx].X_op_symbol);
1633 if (operand->insert)
1634 {
1635 const char *errmsg = NULL;
1636 (*operand->insert)(0,
1637 regs,
1638 &errmsg);
1639 if (errmsg)
1640 goto match_failed;
1641 }
1642 else
1643 goto match_failed;
1644 break;
1645 }
1646 default:
22b92fc4 1647 de_fault:
4670103e
CZ		 1648 if (operand->default_reloc == 0)
1649 goto match_failed; /* The operand needs relocation. */
1650
1651 /* Relocs requiring long immediate. FIXME! make it
1652 generic and move it to a function. */
1653 switch (tok[tokidx].X_md)
1654 {
1655 case O_gotoff:
1656 case O_gotpc:
1657 case O_pcl:
1658 case O_tpoff:
1659 case O_dtpoff:
1660 case O_tlsgd:
1661 case O_tlsie:
1662 if (!(operand->flags & ARC_OPERAND_LIMM))
1663 goto match_failed;
1664 case O_absent:
1665 if (!generic_reloc_p (operand->default_reloc))
1666 goto match_failed;
1667 default:
1668 break;
1669 }
1670 break;
1671 }
1672 /* If expect duplicate, make sure it is duplicate. */
1673 if (operand->flags & ARC_OPERAND_DUPLICATE)
1674 {
1675 if (t->X_op == O_illegal
1676 || t->X_op == O_absent
1677 || t->X_op == O_register
1678 || (t->X_add_number != tok[tokidx].X_add_number))
1679 goto match_failed;
1680 }
1681 t = &tok[tokidx];
1682 break;
1683
1684 default:
1685 /* Everything else should have been fake. */
1686 abort ();
1687 }
1688
1689 ++tokidx;
1690 }
1691 pr_debug ("opr ");
1692
1ae8ab47
AB		 1693 /* Setup ready for flag parsing. */
1694 lnflg = nflgs;
1695 for (i = 0; i < nflgs; i++)
1696 first_pflag [i].code = 0;
4670103e 1697
1ae8ab47
AB		 1698 /* Check the flags. Iterate over the valid flag classes. */
1699 for (flgidx = opcode->flags; *flgidx; ++flgidx)
4670103e
CZ		 1700 {
1701 /* Get a valid flag class. */
1702 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1703 const unsigned *flgopridx;
1ae8ab47 1704 int cl_matches = 0;
4670103e
CZ		 1705
1706 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1707 {
1708 const struct arc_flag_operand *flg_operand;
1709 struct arc_flags *pflag = first_pflag;
4670103e
CZ		 1710
1711 flg_operand = &arc_flag_operands[*flgopridx];
1712 for (i = 0; i < nflgs; i++, pflag++)
1713 {
1714 /* Match against the parsed flags. */
1715 if (!strcmp (flg_operand->name, pflag->name))
1716 {
1ae8ab47
AB		 1717 if (pflag->code != 0)
1718 goto match_failed;
1719 cl_matches++;
4670103e
CZ		 1720 pflag->code = *flgopridx;
1721 lnflg--;
1722 break; /* goto next flag class and parsed flag. */
1723 }
1724 }
1725 }
1ae8ab47
AB		 1726
1727 if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0)
1728 goto match_failed;
1729 if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1)
1730 goto match_failed;
4670103e
CZ		 1731 }
1732 /* Did I check all the parsed flags? */
1733 if (lnflg)
1734 goto match_failed;
1735
1736 pr_debug ("flg");
1737 /* Possible match -- did we use all of our input? */
1738 if (tokidx == ntok)
1739 {
1740 *pntok = ntok;
1741 pr_debug ("\n");
1742 return opcode;
1743 }
1744
1745 match_failed:;
1746 pr_debug ("\n");
1747 /* Restore the original parameters. */
1748 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
1749 ntok = bkntok;
1750 }
1751 while (++opcode - arc_opcodes < (int) arc_num_opcodes
1752 && !strcmp (opcode->name, first_opcode->name));
1753
1754 if (*pcpumatch)
1755 *pcpumatch = got_cpu_match;
1756
1757 return NULL;
1758}
1759
1760/* Swap operand tokens. */
1761
1762static void
1763swap_operand (expressionS *operand_array,
1764 unsigned source,
1765 unsigned destination)
1766{
1767 expressionS cpy_operand;
1768 expressionS *src_operand;
1769 expressionS *dst_operand;
1770 size_t size;
1771
1772 if (source == destination)
1773 return;
1774
1775 src_operand = &operand_array[source];
1776 dst_operand = &operand_array[destination];
1777 size = sizeof (expressionS);
1778
1779 /* Make copy of operand to swap with and swap. */
1780 memcpy (&cpy_operand, dst_operand, size);
1781 memcpy (dst_operand, src_operand, size);
1782 memcpy (src_operand, &cpy_operand, size);
1783}
1784
1785/* Check if *op matches *tok type.
1786 Returns FALSE if they don't match, TRUE if they match. */
1787
1788static bfd_boolean
1789pseudo_operand_match (const expressionS *tok,
1790 const struct arc_operand_operation *op)
1791{
1792 offsetT min, max, val;
1793 bfd_boolean ret;
1794 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
1795
1796 ret = FALSE;
1797 switch (tok->X_op)
1798 {
1799 case O_constant:
1800 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
1801 ret = 1;
1802 else if (!(operand_real->flags & ARC_OPERAND_IR))
1803 {
1804 val = tok->X_add_number + op->count;
1805 if (operand_real->flags & ARC_OPERAND_SIGNED)
1806 {
1807 max = (1 << (operand_real->bits - 1)) - 1;
1808 min = -(1 << (operand_real->bits - 1));
1809 }
1810 else
1811 {
1812 max = (1 << operand_real->bits) - 1;
1813 min = 0;
1814 }
1815 if (min <= val && val <= max)
1816 ret = TRUE;
1817 }
6f4b1afc
CM		 1818 break;
1819
4670103e
CZ		 1820 case O_symbol:
1821 /* Handle all symbols as long immediates or signed 9. */
1822 if (operand_real->flags & ARC_OPERAND_LIMM ||
1823 ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
1824 ret = TRUE;
6f4b1afc
CM		 1825 break;
1826
4670103e
CZ		 1827 case O_register:
1828 if (operand_real->flags & ARC_OPERAND_IR)
1829 ret = TRUE;
1830 break;
1831
1832 case O_bracket:
1833 if (operand_real->flags & ARC_OPERAND_BRAKET)
1834 ret = TRUE;
6f4b1afc
CM		 1835 break;
1836
1837 default:
4670103e 1838 /* Unknown. */
6f4b1afc
CM		 1839 break;
1840 }
4670103e
CZ		 1841 return ret;
1842}
6f4b1afc 1843
4670103e
CZ		 1844/* Find pseudo instruction in array. */
1845
1846static const struct arc_pseudo_insn *
1847find_pseudo_insn (const char *opname,
1848 int ntok,
1849 const expressionS *tok)
1850{
1851 const struct arc_pseudo_insn *pseudo_insn = NULL;
1852 const struct arc_operand_operation *op;
1853 unsigned int i;
1854 int j;
1855
1856 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 1857 {
4670103e
CZ		 1858 pseudo_insn = &arc_pseudo_insns[i];
1859 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
1860 {
1861 op = pseudo_insn->operand;
1862 for (j = 0; j < ntok; ++j)
1863 if (!pseudo_operand_match (&tok[j], &op[j]))
1864 break;
1865
1866 /* Found the right instruction. */
1867 if (j == ntok)
1868 return pseudo_insn;
1869 }
6f4b1afc 1870 }
4670103e
CZ		 1871 return NULL;
1872}
252b5132 1873
4670103e 1874/* Assumes the expressionS *tok is of sufficient size. */
252b5132 1875
4670103e
CZ		 1876static const struct arc_opcode *
1877find_special_case_pseudo (const char *opname,
1878 int *ntok,
1879 expressionS *tok,
1880 int *nflgs,
1881 struct arc_flags *pflags)
1882{
1883 const struct arc_pseudo_insn *pseudo_insn = NULL;
1884 const struct arc_operand_operation *operand_pseudo;
1885 const struct arc_operand *operand_real;
1886 unsigned i;
1887 char construct_operand[MAX_CONSTR_STR];
886a2506 1888
4670103e
CZ		 1889 /* Find whether opname is in pseudo instruction array. */
1890 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
1891
1892 if (pseudo_insn == NULL)
1893 return NULL;
1894
1895 /* Handle flag, Limited to one flag at the moment. */
1896 if (pseudo_insn->flag_r != NULL)
1897 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
1898 MAX_INSN_FLGS - *nflgs);
1899
1900 /* Handle operand operations. */
1901 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 1902 {
4670103e
CZ		 1903 operand_pseudo = &pseudo_insn->operand[i];
1904 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 1905
4670103e
CZ		 1906 if (operand_real->flags & ARC_OPERAND_BRAKET &&
1907 !operand_pseudo->needs_insert)
1908 continue;
b125bd17 1909
4670103e
CZ		 1910 /* Has to be inserted (i.e. this token does not exist yet). */
1911 if (operand_pseudo->needs_insert)
1912 {
1913 if (operand_real->flags & ARC_OPERAND_BRAKET)
1914 {
1915 tok[i].X_op = O_bracket;
1916 ++(*ntok);
1917 continue;
1918 }
b125bd17 1919
4670103e
CZ		 1920 /* Check if operand is a register or constant and handle it
1921 by type. */
1922 if (operand_real->flags & ARC_OPERAND_IR)
1923 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
1924 operand_pseudo->count);
1925 else
1926 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
1927 operand_pseudo->count);
886a2506 1928
4670103e
CZ		 1929 tokenize_arguments (construct_operand, &tok[i], 1);
1930 ++(*ntok);
1931 }
1932
1933 else if (operand_pseudo->count)
1934 {
1935 /* Operand number has to be adjusted accordingly (by operand
1936 type). */
1937 switch (tok[i].X_op)
1938 {
1939 case O_constant:
1940 tok[i].X_add_number += operand_pseudo->count;
1941 break;
1942
1943 case O_symbol:
1944 break;
1945
1946 default:
1947 /* Ignored. */
1948 break;
1949 }
1950 }
1951 }
1952
1953 /* Swap operands if necessary. Only supports one swap at the
1954 moment. */
1955 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
1956 {
1957 operand_pseudo = &pseudo_insn->operand[i];
1958
1959 if (operand_pseudo->swap_operand_idx == i)
1960 continue;
1961
1962 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
1963
1964 /* Prevent a swap back later by breaking out. */
1965 break;
1966 }
1967
da5be039 1968 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 1969}
1970
1971static const struct arc_opcode *
1972find_special_case_flag (const char *opname,
1973 int *nflgs,
1974 struct arc_flags *pflags)
1975{
1976 unsigned int i;
1977 const char *flagnm;
1978 unsigned flag_idx, flag_arr_idx;
1979 size_t flaglen, oplen;
1980 const struct arc_flag_special *arc_flag_special_opcode;
1981 const struct arc_opcode *opcode;
1982
1983 /* Search for special case instruction. */
1984 for (i = 0; i < arc_num_flag_special; i++)
1985 {
1986 arc_flag_special_opcode = &arc_flag_special_cases[i];
1987 oplen = strlen (arc_flag_special_opcode->name);
1988
1989 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
1990 continue;
1991
1992 /* Found a potential special case instruction, now test for
1993 flags. */
1994 for (flag_arr_idx = 0;; ++flag_arr_idx)
1995 {
1996 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
1997 if (flag_idx == 0)
1998 break; /* End of array, nothing found. */
886a2506 1999
4670103e
CZ		 2000 flagnm = arc_flag_operands[flag_idx].name;
2001 flaglen = strlen (flagnm);
2002 if (strcmp (opname + oplen, flagnm) == 0)
2003 {
da5be039 2004 opcode = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2005
4670103e
CZ		 2006 if (*nflgs + 1 > MAX_INSN_FLGS)
2007 break;
2008 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2009 pflags[*nflgs].name[flaglen] = '\0';
2010 (*nflgs)++;
2011 return opcode;
2012 }
2013 }
2014 }
2015 return NULL;
2016}
886a2506 2017
4670103e 2018/* Used to find special case opcode. */
886a2506 2019
4670103e
CZ		 2020static const struct arc_opcode *
2021find_special_case (const char *opname,
2022 int *nflgs,
2023 struct arc_flags *pflags,
2024 expressionS *tok,
2025 int *ntok)
2026{
2027 const struct arc_opcode *opcode;
886a2506 2028
4670103e 2029 opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2030
4670103e
CZ		 2031 if (opcode == NULL)
2032 opcode = find_special_case_flag (opname, nflgs, pflags);
886a2506 2033
4670103e
CZ		 2034 return opcode;
2035}
886a2506 2036
4670103e
CZ		 2037/* Given an opcode name, pre-tockenized set of argumenst and the
2038 opcode flags, take it all the way through emission. */
886a2506 2039
4670103e
CZ		 2040static void
2041assemble_tokens (const char *opname,
2042 expressionS *tok,
2043 int ntok,
2044 struct arc_flags *pflags,
2045 int nflgs)
2046{
2047 bfd_boolean found_something = FALSE;
2048 const struct arc_opcode *opcode;
2049 int cpumatch = 1;
886a2506 2050
4670103e 2051 /* Search opcodes. */
da5be039 2052 opcode = arc_find_opcode (opname);
886a2506 2053
4670103e
CZ		 2054 /* Couldn't find opcode conventional way, try special cases. */
2055 if (!opcode)
2056 opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2057
4670103e
CZ		 2058 if (opcode)
2059 {
2060 pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
2061 frag_now->fr_file, frag_now->fr_line, opcode->name,
2062 opcode->opcode);
886a2506 2063
4670103e
CZ		 2064 found_something = TRUE;
2065 opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch);
2066 if (opcode)
2067 {
2068 struct arc_insn insn;
2069 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2070 emit_insn (&insn);
2071 return;
2072 }
2073 }
886a2506 2074
4670103e
CZ		 2075 if (found_something)
2076 {
2077 if (cpumatch)
2078 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2079 else
2080 as_bad (_("opcode '%s' not supported for target %s"), opname,
2081 arc_target_name);
2082 }
2083 else
2084 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2085}
2086
4670103e 2087/* The public interface to the instruction assembler. */
886a2506 2088
4670103e
CZ		 2089void
2090md_assemble (char *str)
886a2506 2091{
4670103e
CZ		 2092 char *opname;
2093 expressionS tok[MAX_INSN_ARGS];
2094 int ntok, nflg;
2095 size_t opnamelen;
2096 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2097
4670103e
CZ		 2098 /* Split off the opcode. */
2099 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2100 opname = xmalloc (opnamelen + 1);
2101 memcpy (opname, str, opnamelen);
2102 opname[opnamelen] = '\0';
886a2506 2103
4670103e
CZ		 2104 /* Signalize we are assmbling the instructions. */
2105 assembling_insn = TRUE;
886a2506 2106
4670103e
CZ		 2107 /* Tokenize the flags. */
2108 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2109 {
2110 as_bad (_("syntax error"));
2111 return;
2112 }
886a2506 2113
4670103e
CZ		 2114 /* Scan up to the end of the mnemonic which must end in space or end
2115 of string. */
2116 str += opnamelen;
2117 for (; *str != '\0'; str++)
2118 if (*str == ' ')
2119 break;
886a2506 2120
4670103e
CZ		 2121 /* Tokenize the rest of the line. */
2122 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2123 {
4670103e
CZ		 2124 as_bad (_("syntax error"));
2125 return;
252b5132
RH		 2126 }
2127
4670103e
CZ		 2128 /* Finish it off. */
2129 assemble_tokens (opname, tok, ntok, flags, nflg);
2130 assembling_insn = FALSE;
2131}
2132
2133/* Callback to insert a register into the hash table. */
2134
2135static void
f86f5863 2136declare_register (const char *name, int number)
4670103e
CZ		 2137{
2138 const char *err;
2139 symbolS *regS = symbol_create (name, reg_section,
2140 number, &zero_address_frag);
2141
2142 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2143 if (err)
e6ba1cba 2144 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2145 name, err);
2146}
252b5132 2147
4670103e 2148/* Construct symbols for each of the general registers. */
252b5132 2149
4670103e
CZ		 2150static void
2151declare_register_set (void)
2152{
2153 int i;
2154 for (i = 0; i < 64; ++i)
886a2506 2155 {
4670103e
CZ		 2156 char name[7];
2157
2158 sprintf (name, "r%d", i);
2159 declare_register (name, i);
2160 if ((i & 0x01) == 0)
886a2506 2161 {
4670103e
CZ		 2162 sprintf (name, "r%dr%d", i, i+1);
2163 declare_register (name, i);
886a2506
NC		 2164 }
2165 }
252b5132 2166}
ea1562b3 2167
4670103e
CZ		 2168/* Port-specific assembler initialization. This function is called
2169 once, at assembler startup time. */
ea1562b3
NC		 2170
2171void
4670103e 2172md_begin (void)
ea1562b3 2173{
4670103e 2174 unsigned int i;
886a2506 2175
24740d83
AB		 2176 if (!mach_type_specified_p)
2177 arc_select_cpu ("arc700");
2178
4670103e
CZ		 2179 /* The endianness can be chosen "at the factory". */
2180 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2181
4670103e
CZ		 2182 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
2183 as_warn (_("could not set architecture and machine"));
2184
2185 /* Set elf header flags. */
2186 bfd_set_private_flags (stdoutput, arc_eflag);
2187
2188 /* Set up a hash table for the instructions. */
2189 arc_opcode_hash = hash_new ();
2190 if (arc_opcode_hash == NULL)
2191 as_fatal (_("Virtual memory exhausted"));
2192
2193 /* Initialize the hash table with the insns. */
2194 for (i = 0; i < arc_num_opcodes;)
ea1562b3 2195 {
4670103e 2196 const char *name, *retval;
da5be039 2197 struct arc_opcode_hash_entry *entry;
886a2506 2198
4670103e 2199 name = arc_opcodes[i].name;
da5be039
AB		 2200
2201 entry = hash_find (arc_opcode_hash, name);
2202 if (entry == NULL)
2203 {
2204 entry = xmalloc (sizeof (*entry));
2205 entry->count = 0;
2206 entry->opcode = NULL;
2207
2208 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
2209 if (retval)
2210 as_fatal (_("internal error: can't hash opcode '%s': %s"),
2211 name, retval);
2212 }
2213
2214 entry->opcode = xrealloc (entry->opcode,
2215 sizeof (const struct arc_opcode *)
2216 * entry->count + 1);
2217 entry->opcode [entry->count] = &arc_opcodes[i];
2218 entry->count++;
4670103e
CZ		 2219
2220 while (++i < arc_num_opcodes
2221 && (arc_opcodes[i].name == name
2222 || !strcmp (arc_opcodes[i].name, name)))
2223 continue;
ea1562b3 2224 }
4670103e
CZ		 2225
2226 /* Register declaration. */
2227 arc_reg_hash = hash_new ();
2228 if (arc_reg_hash == NULL)
2229 as_fatal (_("Virtual memory exhausted"));
2230
2231 declare_register_set ();
2232 declare_register ("gp", 26);
2233 declare_register ("fp", 27);
2234 declare_register ("sp", 28);
2235 declare_register ("ilink", 29);
2236 declare_register ("ilink1", 29);
2237 declare_register ("ilink2", 30);
2238 declare_register ("blink", 31);
2239
2240 declare_register ("mlo", 57);
2241 declare_register ("mmid", 58);
2242 declare_register ("mhi", 59);
2243
2244 declare_register ("acc1", 56);
2245 declare_register ("acc2", 57);
2246
2247 declare_register ("lp_count", 60);
2248 declare_register ("pcl", 63);
2249
2250 /* Initialize the last instructions. */
2251 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
886a2506 2252}
ea1562b3 2253
4670103e
CZ		 2254/* Write a value out to the object file, using the appropriate
2255 endianness. */
ea1562b3 2256
4670103e
CZ		 2257void
2258md_number_to_chars (char *buf,
2259 valueT val,
2260 int n)
886a2506 2261{
4670103e
CZ		 2262 if (target_big_endian)
2263 number_to_chars_bigendian (buf, val, n);
2264 else
2265 number_to_chars_littleendian (buf, val, n);
886a2506 2266}
ea1562b3 2267
4670103e 2268/* Round up a section size to the appropriate boundary. */
ea1562b3 2269
4670103e
CZ		 2270valueT
2271md_section_align (segT segment,
2272 valueT size)
886a2506 2273{
4670103e
CZ		 2274 int align = bfd_get_section_alignment (stdoutput, segment);
2275
2276 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2277}
ea1562b3 2278
4670103e
CZ		 2279/* The location from which a PC relative jump should be calculated,
2280 given a PC relative reloc. */
ea1562b3 2281
4670103e
CZ		 2282long
2283md_pcrel_from_section (fixS *fixP,
2284 segT sec)
886a2506 2285{
4670103e 2286 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2287
4670103e 2288 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2289
4670103e
CZ		 2290 if (fixP->fx_addsy != (symbolS *) NULL
2291 && (!S_IS_DEFINED (fixP->fx_addsy)
2292 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2293 {
2294 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2295
4670103e
CZ		 2296 /* The symbol is undefined (or is defined but not in this section).
2297 Let the linker figure it out. */
2298 return 0;
2299 }
2300
2301 if ((int) fixP->fx_r_type < 0)
886a2506 2302 {
4670103e
CZ		 2303 /* These are the "internal" relocations. Align them to
2304 32 bit boundary (PCL), for the moment. */
2305 base &= ~3;
886a2506 2306 }
4670103e
CZ		 2307 else
2308 {
2309 switch (fixP->fx_r_type)
2310 {
2311 case BFD_RELOC_ARC_PC32:
2312 /* The hardware calculates relative to the start of the
2313 insn, but this relocation is relative to location of the
2314 LIMM, compensate. The base always needs to be
2315 substracted by 4 as we do not support this type of PCrel
2316 relocation for short instructions. */
2317 base -= 4;
2318 /* Fall through. */
2319 case BFD_RELOC_ARC_PLT32:
2320 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2321 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2322 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2323 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2324
2325 case BFD_RELOC_ARC_S21H_PCREL:
2326 case BFD_RELOC_ARC_S25H_PCREL:
2327 case BFD_RELOC_ARC_S13_PCREL:
2328 case BFD_RELOC_ARC_S21W_PCREL:
2329 case BFD_RELOC_ARC_S25W_PCREL:
2330 base &= ~3;
2331 break;
2332 default:
2333 as_bad_where (fixP->fx_file, fixP->fx_line,
2334 _("unhandled reloc %s in md_pcrel_from_section"),
2335 bfd_get_reloc_code_name (fixP->fx_r_type));
2336 break;
2337 }
2338 }
2339
2340 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2341 fixP->fx_frag->fr_address, fixP->fx_where, base,
2342 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2343 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2344
2345 return base;
886a2506 2346}
ea1562b3 2347
4670103e 2348/* Given a BFD relocation find the coresponding operand. */
ea1562b3 2349
4670103e
CZ		 2350static const struct arc_operand *
2351find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2352{
2353 unsigned i;
ea1562b3 2354
4670103e
CZ		 2355 for (i = 0; i < arc_num_operands; i++)
2356 if (arc_operands[i].default_reloc == reloc)
2357 return &arc_operands[i];
2358 return NULL;
2359}
ea1562b3 2360
4670103e 2361/* Insert an operand value into an instruction. */
ea1562b3 2362
4670103e
CZ		 2363static unsigned
2364insert_operand (unsigned insn,
2365 const struct arc_operand *operand,
2366 offsetT val,
3b4dbbbf 2367 const char *file,
4670103e 2368 unsigned line)
886a2506 2369{
4670103e 2370 offsetT min = 0, max = 0;
ea1562b3 2371
4670103e
CZ		 2372 if (operand->bits != 32
2373 && !(operand->flags & ARC_OPERAND_NCHK)
2374 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2375 {
4670103e
CZ		 2376 if (operand->flags & ARC_OPERAND_SIGNED)
2377 {
2378 max = (1 << (operand->bits - 1)) - 1;
2379 min = -(1 << (operand->bits - 1));
2380 }
2381 else
2382 {
2383 max = (1 << operand->bits) - 1;
2384 min = 0;
2385 }
886a2506 2386
4670103e
CZ		 2387 if (val < min || val > max)
2388 as_bad_value_out_of_range (_("operand"),
2389 val, min, max, file, line);
2390 }
ea1562b3 2391
4670103e
CZ		 2392 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2393 min, val, max, insn);
ea1562b3 2394
4670103e
CZ		 2395 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2396 && (val & 0x03))
2397 as_bad_where (file, line,
2398 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2399
4670103e
CZ		 2400 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2401 && (val & 0x01))
2402 as_bad_where (file, line,
2403 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2404
4670103e
CZ		 2405 if (operand->insert)
2406 {
2407 const char *errmsg = NULL;
ea1562b3 2408
4670103e
CZ		 2409 insn = (*operand->insert) (insn, val, &errmsg);
2410 if (errmsg)
2411 as_warn_where (file, line, "%s", errmsg);
2412 }
2413 else
2414 {
2415 if (operand->flags & ARC_OPERAND_TRUNCATE)
2416 {
2417 if (operand->flags & ARC_OPERAND_ALIGNED32)
2418 val >>= 2;
2419 if (operand->flags & ARC_OPERAND_ALIGNED16)
2420 val >>= 1;
886a2506 2421 }
4670103e
CZ		 2422 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2423 }
2424 return insn;
2425}
ea1562b3 2426
4670103e
CZ		 2427/* Apply a fixup to the object code. At this point all symbol values
2428 should be fully resolved, and we attempt to completely resolve the
2429 reloc. If we can not do that, we determine the correct reloc code
2430 and put it back in the fixup. To indicate that a fixup has been
2431 eliminated, set fixP->fx_done. */
ea1562b3 2432
4670103e
CZ		 2433void
2434md_apply_fix (fixS *fixP,
2435 valueT *valP,
2436 segT seg)
2437{
2438 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2439 valueT value = *valP;
2440 unsigned insn = 0;
2441 symbolS *fx_addsy, *fx_subsy;
2442 offsetT fx_offset;
2443 segT add_symbol_segment = absolute_section;
2444 segT sub_symbol_segment = absolute_section;
2445 const struct arc_operand *operand = NULL;
2446 extended_bfd_reloc_code_real_type reloc;
886a2506 2447
4670103e
CZ		 2448 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2449 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2450 ((int) fixP->fx_r_type < 0) ? "Internal":
2451 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2452 fixP->fx_offset);
886a2506 2453
4670103e
CZ		 2454 fx_addsy = fixP->fx_addsy;
2455 fx_subsy = fixP->fx_subsy;
2456 fx_offset = 0;
886a2506 2457
4670103e
CZ		 2458 if (fx_addsy)
2459 {
2460 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2461 }
2462
4670103e
CZ		 2463 if (fx_subsy
2464 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2465 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2466 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2467 {
2468 resolve_symbol_value (fx_subsy);
2469 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2470
4670103e
CZ		 2471 if (sub_symbol_segment == absolute_section)
2472 {
2473 /* The symbol is really a constant. */
2474 fx_offset -= S_GET_VALUE (fx_subsy);
2475 fx_subsy = NULL;
2476 }
2477 else
2478 {
2479 as_bad_where (fixP->fx_file, fixP->fx_line,
2480 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2481 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2482 segment_name (add_symbol_segment),
2483 S_GET_NAME (fx_subsy),
2484 segment_name (sub_symbol_segment));
2485 return;
2486 }
2487 }
886a2506 2488
4670103e
CZ		 2489 if (fx_addsy
2490 && !S_IS_WEAK (fx_addsy))
2491 {
2492 if (add_symbol_segment == seg
2493 && fixP->fx_pcrel)
2494 {
2495 value += S_GET_VALUE (fx_addsy);
2496 value -= md_pcrel_from_section (fixP, seg);
2497 fx_addsy = NULL;
2498 fixP->fx_pcrel = FALSE;
2499 }
2500 else if (add_symbol_segment == absolute_section)
2501 {
2502 value = fixP->fx_offset;
2503 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2504 fx_addsy = NULL;
2505 fixP->fx_pcrel = FALSE;
2506 }
2507 }
886a2506 2508
4670103e
CZ		 2509 if (!fx_addsy)
2510 fixP->fx_done = TRUE;
886a2506 2511
4670103e 2512 if (fixP->fx_pcrel)
886a2506 2513 {
4670103e
CZ		 2514 if (fx_addsy
2515 && ((S_IS_DEFINED (fx_addsy)
2516 && S_GET_SEGMENT (fx_addsy) != seg)
2517 || S_IS_WEAK (fx_addsy)))
2518 value += md_pcrel_from_section (fixP, seg);
886a2506 2519
4670103e
CZ		 2520 switch (fixP->fx_r_type)
2521 {
2522 case BFD_RELOC_ARC_32_ME:
2523 /* This is a pc-relative value in a LIMM. Adjust it to the
2524 address of the instruction not to the address of the
2525 LIMM. Note: it is not anylonger valid this afirmation as
2526 the linker consider ARC_PC32 a fixup to entire 64 bit
2527 insn. */
2528 fixP->fx_offset += fixP->fx_frag->fr_address;
2529 /* Fall through. */
2530 case BFD_RELOC_32:
2531 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2532 /* Fall through. */
2533 case BFD_RELOC_ARC_PC32:
2534 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2535 break;
2536 default:
4670103e
CZ		 2537 if ((int) fixP->fx_r_type < 0)
2538 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2539 fixP->fx_r_type);
886a2506 2540 break;
ea1562b3
NC		 2541 }
2542 }
2543
4670103e
CZ		 2544 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2545 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2546 ((int) fixP->fx_r_type < 0) ? "Internal":
2547 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2548 fixP->fx_offset);
886a2506 2549
886a2506 2550
4670103e
CZ		 2551 /* Now check for TLS relocations. */
2552 reloc = fixP->fx_r_type;
2553 switch (reloc)
886a2506 2554 {
4670103e
CZ		 2555 case BFD_RELOC_ARC_TLS_DTPOFF:
2556 case BFD_RELOC_ARC_TLS_LE_32:
2557 if (fixP->fx_done)
2558 break;
2559 /* Fall through. */
2560 case BFD_RELOC_ARC_TLS_GD_GOT:
2561 case BFD_RELOC_ARC_TLS_IE_GOT:
2562 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2563 break;
886a2506 2564
4670103e
CZ		 2565 case BFD_RELOC_ARC_TLS_GD_LD:
2566 gas_assert (!fixP->fx_offset);
2567 if (fixP->fx_subsy)
2568 fixP->fx_offset
2569 = (S_GET_VALUE (fixP->fx_subsy)
2570 - fixP->fx_frag->fr_address- fixP->fx_where);
2571 fixP->fx_subsy = NULL;
2572 /* Fall through. */
2573 case BFD_RELOC_ARC_TLS_GD_CALL:
2574 /* These two relocs are there just to allow ld to change the tls
2575 model for this symbol, by patching the code. The offset -
2576 and scale, if any - will be installed by the linker. */
2577 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2578 break;
886a2506 2579
4670103e
CZ		 2580 case BFD_RELOC_ARC_TLS_LE_S9:
2581 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2582 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2583 break;
2584
2585 default:
2586 break;
886a2506
NC		 2587 }
2588
4670103e 2589 if (!fixP->fx_done)
886a2506 2590 {
4670103e 2591 return;
886a2506 2592 }
886a2506 2593
4670103e
CZ		 2594 /* Addjust the value if we have a constant. */
2595 value += fx_offset;
886a2506 2596
4670103e
CZ		 2597 /* For hosts with longs bigger than 32-bits make sure that the top
2598 bits of a 32-bit negative value read in by the parser are set,
2599 so that the correct comparisons are made. */
2600 if (value & 0x80000000)
2601 value |= (-1L << 31);
886a2506 2602
4670103e
CZ		 2603 reloc = fixP->fx_r_type;
2604 switch (reloc)
2605 {
2606 case BFD_RELOC_8:
2607 case BFD_RELOC_16:
2608 case BFD_RELOC_24:
2609 case BFD_RELOC_32:
2610 case BFD_RELOC_64:
2611 case BFD_RELOC_ARC_32_PCREL:
2612 md_number_to_chars (fixpos, value, fixP->fx_size);
2613 return;
886a2506 2614
4670103e
CZ		 2615 case BFD_RELOC_ARC_GOTPC32:
2616 /* I cannot fix an GOTPC relocation because I need to relax it
2617 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2618 as_bad (_("Unsupported operation on reloc"));
2619 return;
886a2506 2620
4670103e
CZ		 2621 case BFD_RELOC_ARC_TLS_DTPOFF:
2622 case BFD_RELOC_ARC_TLS_LE_32:
2623 gas_assert (!fixP->fx_addsy);
2624 gas_assert (!fixP->fx_subsy);
886a2506 2625
4670103e
CZ		 2626 case BFD_RELOC_ARC_GOTOFF:
2627 case BFD_RELOC_ARC_32_ME:
2628 case BFD_RELOC_ARC_PC32:
2629 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2630 return;
886a2506 2631
4670103e
CZ		 2632 case BFD_RELOC_ARC_PLT32:
2633 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2634 return;
886a2506 2635
4670103e
CZ		 2636 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2637 reloc = BFD_RELOC_ARC_S25W_PCREL;
2638 goto solve_plt;
886a2506 2639
4670103e
CZ		 2640 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2641 reloc = BFD_RELOC_ARC_S21H_PCREL;
2642 goto solve_plt;
886a2506 2643
4670103e
CZ		 2644 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2645 reloc = BFD_RELOC_ARC_S25W_PCREL;
2646 goto solve_plt;
886a2506 2647
4670103e
CZ		 2648 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2649 reloc = BFD_RELOC_ARC_S21W_PCREL;
886a2506 2650
4670103e
CZ		 2651 case BFD_RELOC_ARC_S25W_PCREL:
2652 case BFD_RELOC_ARC_S21W_PCREL:
2653 case BFD_RELOC_ARC_S21H_PCREL:
2654 case BFD_RELOC_ARC_S25H_PCREL:
2655 case BFD_RELOC_ARC_S13_PCREL:
2656 solve_plt:
2657 operand = find_operand_for_reloc (reloc);
2658 gas_assert (operand);
886a2506
NC		 2659 break;
2660
2661 default:
4670103e
CZ		 2662 {
2663 if ((int) fixP->fx_r_type >= 0)
2664 as_fatal (_("unhandled relocation type %s"),
2665 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 2666
4670103e
CZ		 2667 /* The rest of these fixups needs to be completely resolved as
2668 constants. */
2669 if (fixP->fx_addsy != 0
2670 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
2671 as_bad_where (fixP->fx_file, fixP->fx_line,
2672 _("non-absolute expression in constant field"));
886a2506 2673
4670103e
CZ		 2674 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
2675 operand = &arc_operands[-(int) fixP->fx_r_type];
2676 break;
2677 }
2678 }
886a2506 2679
4670103e 2680 if (target_big_endian)
886a2506 2681 {
4670103e 2682 switch (fixP->fx_size)
886a2506 2683 {
4670103e
CZ		 2684 case 4:
2685 insn = bfd_getb32 (fixpos);
2686 break;
2687 case 2:
2688 insn = bfd_getb16 (fixpos);
2689 break;
2690 default:
2691 as_bad_where (fixP->fx_file, fixP->fx_line,
2692 _("unknown fixup size"));
2693 }
2694 }
2695 else
2696 {
2697 insn = 0;
2698 switch (fixP->fx_size)
2699 {
2700 case 4:
2701 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
2702 break;
2703 case 2:
2704 insn = bfd_getl16 (fixpos);
2705 break;
2706 default:
2707 as_bad_where (fixP->fx_file, fixP->fx_line,
2708 _("unknown fixup size"));
886a2506
NC		 2709 }
2710 }
886a2506 2711
4670103e
CZ		 2712 insn = insert_operand (insn, operand, (offsetT) value,
2713 fixP->fx_file, fixP->fx_line);
886a2506 2714
4670103e
CZ		 2715 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
2716}
886a2506 2717
4670103e 2718/* Prepare machine-dependent frags for relaxation.
886a2506 2719
4670103e
CZ		 2720 Called just before relaxation starts. Any symbol that is now undefined
2721 will not become defined.
886a2506 2722
4670103e 2723 Return the correct fr_subtype in the frag.
886a2506 2724
4670103e
CZ		 2725 Return the initial "guess for fr_var" to caller. The guess for fr_var
2726 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2727 or fr_var contributes to our returned value.
886a2506 2728
4670103e
CZ		 2729 Although it may not be explicit in the frag, pretend
2730 fr_var starts with a value. */
886a2506 2731
4670103e
CZ		 2732int
2733md_estimate_size_before_relax (fragS *fragP,
2734 segT segment)
2735{
2736 int growth;
2737
2738 /* If the symbol is not located within the same section AND it's not
2739 an absolute section, use the maximum. OR if the symbol is a
2740 constant AND the insn is by nature not pc-rel, use the maximum.
2741 OR if the symbol is being equated against another symbol, use the
2742 maximum. OR if the symbol is weak use the maximum. */
2743 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
2744 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
2745 || (symbol_constant_p (fragP->fr_symbol)
2746 && !fragP->tc_frag_data.pcrel)
2747 || symbol_equated_p (fragP->fr_symbol)
2748 || S_IS_WEAK (fragP->fr_symbol))
2749 {
2750 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
2751 ++fragP->fr_subtype;
2752 }
886a2506 2753
4670103e
CZ		 2754 growth = md_relax_table[fragP->fr_subtype].rlx_length;
2755 fragP->fr_var = growth;
886a2506 2756
4670103e
CZ		 2757 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2758 fragP->fr_file, fragP->fr_line, growth);
886a2506 2759
4670103e
CZ		 2760 return growth;
2761}
886a2506 2762
4670103e
CZ		 2763/* Translate internal representation of relocation info to BFD target
2764 format. */
886a2506 2765
4670103e
CZ		 2766arelent *
2767tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
2768 fixS *fixP)
2769{
2770 arelent *reloc;
2771 bfd_reloc_code_real_type code;
886a2506 2772
4670103e
CZ		 2773 reloc = (arelent *) xmalloc (sizeof (* reloc));
2774 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2775 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2776 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 2777
4670103e
CZ		 2778 /* Make sure none of our internal relocations make it this far.
2779 They'd better have been fully resolved by this point. */
2780 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 2781
4670103e 2782 code = fixP->fx_r_type;
886a2506 2783
4670103e
CZ		 2784 /* if we have something like add gp, pcl,
2785 _GLOBAL_OFFSET_TABLE_@gotpc. */
2786 if (code == BFD_RELOC_ARC_GOTPC32
2787 && GOT_symbol
2788 && fixP->fx_addsy == GOT_symbol)
2789 code = BFD_RELOC_ARC_GOTPC;
886a2506 2790
4670103e
CZ		 2791 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2792 if (reloc->howto == NULL)
886a2506 2793 {
4670103e
CZ		 2794 as_bad_where (fixP->fx_file, fixP->fx_line,
2795 _("cannot represent `%s' relocation in object file"),
2796 bfd_get_reloc_code_name (code));
2797 return NULL;
2798 }
886a2506 2799
4670103e
CZ		 2800 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
2801 as_fatal (_("internal error? cannot generate `%s' relocation"),
2802 bfd_get_reloc_code_name (code));
886a2506 2803
4670103e 2804 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 2805
4670103e
CZ		 2806 if (code == BFD_RELOC_ARC_TLS_DTPOFF
2807 || code == BFD_RELOC_ARC_TLS_DTPOFF_S9)
2808 {
2809 asymbol *sym
2810 = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
2811 /* We just want to store a 24 bit index, but we have to wait
2812 till after write_contents has been called via
2813 bfd_map_over_sections before we can get the index from
2814 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2815 function is elf32-arc.c has to pick up the slack.
2816 Unfortunately, this leads to problems with hosts that have
2817 pointers wider than long (bfd_vma). There would be various
2818 ways to handle this, all error-prone :-( */
2819 reloc->addend = (bfd_vma) sym;
2820 if ((asymbol *) reloc->addend != sym)
2821 {
2822 as_bad ("Can't store pointer\n");
2823 return NULL;
886a2506
NC		 2824 }
2825 }
4670103e
CZ		 2826 else
2827 reloc->addend = fixP->fx_offset;
2828
2829 return reloc;
886a2506
NC		 2830}
2831
4670103e
CZ		 2832/* Perform post-processing of machine-dependent frags after relaxation.
2833 Called after relaxation is finished.
2834 In: Address of frag.
2835 fr_type == rs_machine_dependent.
2836 fr_subtype is what the address relaxed to.
886a2506 2837
4670103e
CZ		 2838 Out: Any fixS:s and constants are set up. */
2839
2840void
2841md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
2842 segT segment ATTRIBUTE_UNUSED,
2843 fragS *fragP)
886a2506 2844{
4670103e
CZ		 2845 const relax_typeS *table_entry;
2846 char *dest;
2847 const struct arc_opcode *opcode;
2848 struct arc_insn insn;
2849 int size, fix;
2850 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 2851
4670103e
CZ		 2852 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
2853 dest = fragP->fr_literal + fix;
2854 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 2855
4670103e
CZ		 2856 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
2857 fragP->fr_file, fragP->fr_line,
2858 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 2859
4670103e
CZ		 2860 if (fragP->fr_subtype <= 0
2861 && fragP->fr_subtype >= arc_num_relax_opcodes)
2862 as_fatal (_("no relaxation found for this instruction."));
886a2506 2863
4670103e 2864 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 2865
4670103e
CZ		 2866 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
2867 relax_arg->nflg, &insn);
886a2506 2868
4670103e 2869 apply_fixups (&insn, fragP, fix);
886a2506 2870
4670103e
CZ		 2871 size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4);
2872 gas_assert (table_entry->rlx_length == size);
2873 emit_insn0 (&insn, dest, TRUE);
886a2506 2874
4670103e
CZ		 2875 fragP->fr_fix += table_entry->rlx_length;
2876 fragP->fr_var = 0;
886a2506
NC		 2877}
2878
4670103e
CZ		 2879/* We have no need to default values of symbols. We could catch
2880 register names here, but that is handled by inserting them all in
2881 the symbol table to begin with. */
886a2506 2882
4670103e
CZ		 2883symbolS *
2884md_undefined_symbol (char *name)
886a2506 2885{
4670103e
CZ		 2886 /* The arc abi demands that a GOT[0] should be referencible as
2887 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
2888 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
2889 if (((*name == '_')
2890 && (*(name+1) == 'G')
2891 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
2892 || ((*name == '_')
2893 && (*(name+1) == 'D')
2894 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
886a2506 2895 {
4670103e
CZ		 2896 if (!GOT_symbol)
2897 {
2898 if (symbol_find (name))
2899 as_bad ("GOT already in symbol table");
2900
2901 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
2902 (valueT) 0, &zero_address_frag);
2903 };
2904 return GOT_symbol;
886a2506 2905 }
4670103e 2906 return NULL;
886a2506
NC		 2907}
2908
4670103e
CZ		 2909/* Turn a string in input_line_pointer into a floating point constant
2910 of type type, and store the appropriate bytes in *litP. The number
2911 of LITTLENUMS emitted is stored in *sizeP. An error message is
2912 returned, or NULL on OK. */
886a2506 2913
6d4af3c2 2914const char *
4670103e 2915md_atof (int type, char *litP, int *sizeP)
886a2506 2916{
4670103e
CZ		 2917 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2918}
886a2506 2919
4670103e
CZ		 2920/* Called for any expression that can not be recognized. When the
2921 function is called, `input_line_pointer' will point to the start of
2922 the expression. */
886a2506 2923
4670103e
CZ		 2924void
2925md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
2926{
2927 char *p = input_line_pointer;
2928 if (*p == '@')
886a2506 2929 {
4670103e
CZ		 2930 input_line_pointer++;
2931 expressionP->X_op = O_symbol;
2932 expression (expressionP);
2933 }
2934}
886a2506 2935
4670103e
CZ		 2936/* This function is called from the function 'expression', it attempts
2937 to parse special names (in our case register names). It fills in
2938 the expression with the identified register. It returns TRUE if
2939 it is a register and FALSE otherwise. */
886a2506 2940
4670103e
CZ		 2941bfd_boolean
2942arc_parse_name (const char *name,
2943 struct expressionS *e)
2944{
2945 struct symbol *sym;
886a2506 2946
4670103e
CZ		 2947 if (!assembling_insn)
2948 return FALSE;
886a2506 2949
4670103e
CZ		 2950 /* Handle only registers. */
2951 if (e->X_op != O_absent)
2952 return FALSE;
886a2506 2953
4670103e
CZ		 2954 sym = hash_find (arc_reg_hash, name);
2955 if (sym)
2956 {
2957 e->X_op = O_register;
2958 e->X_add_number = S_GET_VALUE (sym);
2959 return TRUE;
2960 }
2961 return FALSE;
2962}
886a2506 2963
4670103e
CZ		 2964/* md_parse_option
2965 Invocation line includes a switch not recognized by the base assembler.
2966 See if it's a processor-specific option.
886a2506 2967
4670103e 2968 New options (supported) are:
886a2506 2969
4670103e
CZ		 2970 -mcpu=<cpu name> Assemble for selected processor
2971 -EB/-mbig-endian Big-endian
2972 -EL/-mlittle-endian Little-endian
2973 -mrelax Enable relaxation
886a2506 2974
4670103e
CZ		 2975 The following CPU names are recognized:
2976 arc700, av2em, av2hs. */
886a2506 2977
4670103e 2978int
17b9d67d 2979md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 2980{
4670103e
CZ		 2981 switch (c)
2982 {
2983 case OPTION_ARC600:
2984 case OPTION_ARC601:
2985 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 2986
4670103e
CZ		 2987 case OPTION_ARC700:
2988 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 2989
4670103e
CZ		 2990 case OPTION_ARCEM:
2991 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 2992
4670103e
CZ		 2993 case OPTION_ARCHS:
2994 return md_parse_option (OPTION_MCPU, "archs");
886a2506 2995
4670103e
CZ		 2996 case OPTION_MCPU:
2997 {
24740d83
AB		 2998 arc_select_cpu (arg);
2999 mach_type_specified_p = 1;
4670103e
CZ		 3000 break;
3001 }
886a2506 3002
4670103e
CZ		 3003 case OPTION_EB:
3004 arc_target_format = "elf32-bigarc";
3005 byte_order = BIG_ENDIAN;
3006 break;
886a2506 3007
4670103e
CZ		 3008 case OPTION_EL:
3009 arc_target_format = "elf32-littlearc";
3010 byte_order = LITTLE_ENDIAN;
3011 break;
886a2506 3012
4670103e
CZ		 3013 case OPTION_CD:
3014 /* This option has an effect only on ARC EM. */
3015 if (arc_target & ARC_OPCODE_ARCv2EM)
3016 arc_features |= ARC_CD;
8ddf6b2a
CZ		 3017 else
3018 as_warn (_("Code density option invalid for selected CPU"));
4670103e 3019 break;
886a2506 3020
4670103e
CZ		 3021 case OPTION_RELAX:
3022 relaxation_state = 1;
3023 break;
886a2506 3024
4670103e
CZ		 3025 case OPTION_USER_MODE:
3026 case OPTION_LD_EXT_MASK:
3027 case OPTION_SWAP:
3028 case OPTION_NORM:
3029 case OPTION_BARREL_SHIFT:
3030 case OPTION_MIN_MAX:
3031 case OPTION_NO_MPY:
3032 case OPTION_EA:
3033 case OPTION_MUL64:
3034 case OPTION_SIMD:
8ddf6b2a
CZ		 3035 /* Dummy options are accepted but have no effect. */
3036 break;
3037
4670103e 3038 case OPTION_SPFP:
8ddf6b2a
CZ		 3039 arc_features |= ARC_SPFP;
3040 break;
3041
4670103e 3042 case OPTION_DPFP:
8ddf6b2a
CZ		 3043 arc_features |= ARC_DPFP;
3044 break;
3045
4670103e
CZ		 3046 case OPTION_XMAC_D16:
3047 case OPTION_XMAC_24:
3048 case OPTION_DSP_PACKA:
3049 case OPTION_CRC:
3050 case OPTION_DVBF:
3051 case OPTION_TELEPHONY:
3052 case OPTION_XYMEMORY:
3053 case OPTION_LOCK:
3054 case OPTION_SWAPE:
3055 case OPTION_RTSC:
4670103e
CZ		 3056 /* Dummy options are accepted but have no effect. */
3057 break;
886a2506 3058
8ddf6b2a
CZ		 3059 case OPTION_FPUDA:
3060 /* This option has an effect only on ARC EM. */
3061 if (arc_target & ARC_OPCODE_ARCv2EM)
3062 arc_features |= ARC_FPUDA;
3063 else
3064 as_warn (_("FPUDA invalid for selected CPU"));
3065 break;
3066
4670103e
CZ		 3067 default:
3068 return 0;
3069 }
886a2506 3070
4670103e
CZ		 3071 return 1;
3072}
886a2506 3073
4670103e
CZ		 3074void
3075md_show_usage (FILE *stream)
3076{
3077 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3078
4670103e
CZ		 3079 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3080 fprintf (stream,
3081 " -mcode-density\t enable code density option for ARC EM\n");
3082
3083 fprintf (stream, _("\
3084 -EB assemble code for a big-endian cpu\n"));
3085 fprintf (stream, _("\
3086 -EL assemble code for a little-endian cpu\n"));
3087 fprintf (stream, _("\
3088 -mrelax Enable relaxation\n"));
886a2506 3089
886a2506
NC		 3090}
3091
3092/* Find the proper relocation for the given opcode. */
3093
3094static extended_bfd_reloc_code_real_type
3095find_reloc (const char *name,
3096 const char *opcodename,
3097 const struct arc_flags *pflags,
3098 int nflg,
3099 extended_bfd_reloc_code_real_type reloc)
3100{
3101 unsigned int i;
3102 int j;
24b368f8 3103 bfd_boolean found_flag, tmp;
886a2506
NC		 3104 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3105
3106 for (i = 0; i < arc_num_equiv_tab; i++)
3107 {
3108 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3109
3110 /* Find the entry. */
3111 if (strcmp (name, r->name))
3112 continue;
3113 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3114 continue;
24b368f8 3115 if (r->flags[0])
886a2506
NC		 3116 {
3117 if (!nflg)
3118 continue;
3119 found_flag = FALSE;
24b368f8
CZ		 3120 unsigned * psflg = (unsigned *)r->flags;
3121 do
3122 {
3123 tmp = FALSE;
3124 for (j = 0; j < nflg; j++)
3125 if (!strcmp (pflags[j].name,
3126 arc_flag_operands[*psflg].name))
3127 {
3128 tmp = TRUE;
3129 break;
3130 }
3131 if (!tmp)
3132 {
3133 found_flag = FALSE;
3134 break;
3135 }
3136 else
3137 {
3138 found_flag = TRUE;
3139 }
3140 ++ psflg;
3141 } while (*psflg);
3142
886a2506
NC		 3143 if (!found_flag)
3144 continue;
3145 }
3146
3147 if (reloc != r->oldreloc)
3148 continue;
3149 /* Found it. */
3150 ret = r->newreloc;
3151 break;
3152 }
3153
3154 if (ret == BFD_RELOC_UNUSED)
3155 as_bad (_("Unable to find %s relocation for instruction %s"),
3156 name, opcodename);
3157 return ret;
3158}
3159
4670103e
CZ		 3160/* All the symbol types that are allowed to be used for
3161 relaxation. */
3162
3163static bfd_boolean
3164may_relax_expr (expressionS tok)
3165{
3166 /* Check if we have unrelaxable relocs. */
3167 switch (tok.X_md)
3168 {
3169 default:
3170 break;
3171 case O_plt:
3172 return FALSE;
3173 }
3174
3175 switch (tok.X_op)
3176 {
3177 case O_symbol:
3178 case O_multiply:
3179 case O_divide:
3180 case O_modulus:
3181 case O_add:
3182 case O_subtract:
3183 break;
3184
3185 default:
3186 return FALSE;
3187 }
3188 return TRUE;
3189}
3190
3191/* Checks if flags are in line with relaxable insn. */
3192
3193static bfd_boolean
3194relaxable_flag (const struct arc_relaxable_ins *ins,
3195 const struct arc_flags *pflags,
3196 int nflgs)
3197{
3198 unsigned flag_class,
3199 flag,
3200 flag_class_idx = 0,
3201 flag_idx = 0;
3202
3203 const struct arc_flag_operand *flag_opand;
3204 int i, counttrue = 0;
3205
3206 /* Iterate through flags classes. */
3207 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3208 {
3209 /* Iterate through flags in flag class. */
3210 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3211 != 0)
3212 {
3213 flag_opand = &arc_flag_operands[flag];
3214 /* Iterate through flags in ins to compare. */
3215 for (i = 0; i < nflgs; ++i)
3216 {
3217 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3218 ++counttrue;
3219 }
3220
3221 ++flag_idx;
3222 }
3223
3224 ++flag_class_idx;
3225 flag_idx = 0;
3226 }
3227
3228 /* If counttrue == nflgs, then all flags have been found. */
3229 return (counttrue == nflgs ? TRUE : FALSE);
3230}
3231
3232/* Checks if operands are in line with relaxable insn. */
3233
3234static bfd_boolean
3235relaxable_operand (const struct arc_relaxable_ins *ins,
3236 const expressionS *tok,
3237 int ntok)
3238{
3239 const enum rlx_operand_type *operand = &ins->operands[0];
3240 int i = 0;
3241
3242 while (*operand != EMPTY)
3243 {
3244 const expressionS *epr = &tok[i];
3245
3246 if (i != 0 && i >= ntok)
3247 return FALSE;
3248
3249 switch (*operand)
3250 {
3251 case IMMEDIATE:
3252 if (!(epr->X_op == O_multiply
3253 || epr->X_op == O_divide
3254 || epr->X_op == O_modulus
3255 || epr->X_op == O_add
3256 || epr->X_op == O_subtract
3257 || epr->X_op == O_symbol))
3258 return FALSE;
3259 break;
3260
3261 case REGISTER_DUP:
3262 if ((i <= 0)
3263 || (epr->X_add_number != tok[i - 1].X_add_number))
3264 return FALSE;
3265 /* Fall through. */
3266 case REGISTER:
3267 if (epr->X_op != O_register)
3268 return FALSE;
3269 break;
3270
3271 case REGISTER_S:
3272 if (epr->X_op != O_register)
3273 return FALSE;
3274
3275 switch (epr->X_add_number)
3276 {
3277 case 0: case 1: case 2: case 3:
3278 case 12: case 13: case 14: case 15:
3279 break;
3280 default:
3281 return FALSE;
3282 }
3283 break;
3284
3285 case REGISTER_NO_GP:
3286 if ((epr->X_op != O_register)
3287 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3288 return FALSE;
3289 break;
3290
3291 case BRACKET:
3292 if (epr->X_op != O_bracket)
3293 return FALSE;
3294 break;
3295
3296 default:
3297 /* Don't understand, bail out. */
3298 return FALSE;
3299 break;
3300 }
3301
3302 ++i;
3303 operand = &ins->operands[i];
3304 }
3305
3306 return (i == ntok ? TRUE : FALSE);
3307}
3308
3309/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3310
3311static bfd_boolean
3312relax_insn_p (const struct arc_opcode *opcode,
3313 const expressionS *tok,
3314 int ntok,
3315 const struct arc_flags *pflags,
3316 int nflg)
3317{
3318 unsigned i;
3319 bfd_boolean rv = FALSE;
3320
3321 /* Check the relaxation table. */
3322 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3323 {
3324 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3325
3326 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3327 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3328 && relaxable_operand (arc_rlx_ins, tok, ntok)
3329 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3330 {
3331 rv = TRUE;
3332 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3333 memcpy (&frag_now->tc_frag_data.tok, tok,
3334 sizeof (expressionS) * ntok);
3335 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3336 sizeof (struct arc_flags) * nflg);
3337 frag_now->tc_frag_data.nflg = nflg;
3338 frag_now->tc_frag_data.ntok = ntok;
3339 break;
3340 }
3341 }
3342
3343 return rv;
3344}
3345
886a2506
NC		 3346/* Turn an opcode description and a set of arguments into
3347 an instruction and a fixup. */
3348
3349static void
3350assemble_insn (const struct arc_opcode *opcode,
3351 const expressionS *tok,
3352 int ntok,
3353 const struct arc_flags *pflags,
3354 int nflg,
3355 struct arc_insn *insn)
3356{
3357 const expressionS *reloc_exp = NULL;
3358 unsigned image;
3359 const unsigned char *argidx;
3360 int i;
3361 int tokidx = 0;
3362 unsigned char pcrel = 0;
3363 bfd_boolean needGOTSymbol;
3364 bfd_boolean has_delay_slot = FALSE;
3365 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3366
3367 memset (insn, 0, sizeof (*insn));
3368 image = opcode->opcode;
3369
3370 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3371 frag_now->fr_file, frag_now->fr_line, opcode->name,
3372 opcode->opcode);
3373
3374 /* Handle operands. */
3375 for (argidx = opcode->operands; *argidx; ++argidx)
3376 {
3377 const struct arc_operand *operand = &arc_operands[*argidx];
3378 const expressionS *t = (const expressionS *) 0;
3379
3380 if ((operand->flags & ARC_OPERAND_FAKE)
3381 && !(operand->flags & ARC_OPERAND_BRAKET))
3382 continue;
3383
3384 if (operand->flags & ARC_OPERAND_DUPLICATE)
3385 {
3386 /* Duplicate operand, already inserted. */
3387 tokidx ++;
3388 continue;
3389 }
3390
3391 if (tokidx >= ntok)
3392 {
3393 abort ();
3394 }
3395 else
3396 t = &tok[tokidx++];
3397
3398 /* Regardless if we have a reloc or not mark the instruction
3399 limm if it is the case. */
3400 if (operand->flags & ARC_OPERAND_LIMM)
3401 insn->has_limm = TRUE;
3402
3403 switch (t->X_op)
3404 {
3405 case O_register:
3406 image = insert_operand (image, operand, regno (t->X_add_number),
3407 NULL, 0);
3408 break;
3409
3410 case O_constant:
3411 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3412 reloc_exp = t;
3413 if (operand->flags & ARC_OPERAND_LIMM)
3414 insn->limm = t->X_add_number;
3415 break;
3416
3417 case O_bracket:
3418 /* Ignore brackets. */
3419 break;
3420
3421 case O_absent:
3422 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3423 break;
3424
3425 case O_subtract:
3426 /* Maybe register range. */
3427 if ((t->X_add_number == 0)
3428 && contains_register (t->X_add_symbol)
3429 && contains_register (t->X_op_symbol))
3430 {
3431 int regs;
3432
3433 regs = get_register (t->X_add_symbol);
3434 regs <<= 16;
3435 regs |= get_register (t->X_op_symbol);
3436 image = insert_operand (image, operand, regs, NULL, 0);
3437 break;
3438 }
3439
3440 default:
3441 /* This operand needs a relocation. */
3442 needGOTSymbol = FALSE;
3443
3444 switch (t->X_md)
3445 {
3446 case O_plt:
6ec1f282
CZ		 3447 if (opcode->class == JUMP)
3448 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3449 _("Unable to use @plt relocatio for insn %s"),
3450 opcode->name);
886a2506
NC		 3451 needGOTSymbol = TRUE;
3452 reloc = find_reloc ("plt", opcode->name,
3453 pflags, nflg,
3454 operand->default_reloc);
3455 break;
3456
3457 case O_gotoff:
3458 case O_gotpc:
3459 needGOTSymbol = TRUE;
3460 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3461 break;
3462 case O_pcl:
3463 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
6ec1f282 3464 if (ARC_SHORT (opcode->mask) || opcode->class == JUMP)
886a2506
NC		 3465 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3466 _("Unable to use @pcl relocation for insn %s"),
3467 opcode->name);
3468 break;
3469 case O_sda:
3470 reloc = find_reloc ("sda", opcode->name,
3471 pflags, nflg,
3472 operand->default_reloc);
3473 break;
3474 case O_tlsgd:
3475 case O_tlsie:
3476 needGOTSymbol = TRUE;
3477 /* Fall-through. */
3478
3479 case O_tpoff:
3480 case O_dtpoff:
3481 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3482 break;
3483
3484 case O_tpoff9: /*FIXME! Check for the conditionality of
3485 the insn. */
3486 case O_dtpoff9: /*FIXME! Check for the conditionality of
3487 the insn. */
3488 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3489 break;
3490
3491 default:
3492 /* Just consider the default relocation. */
3493 reloc = operand->default_reloc;
3494 break;
3495 }
3496
3497 if (needGOTSymbol && (GOT_symbol == NULL))
3498 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3499
3500 reloc_exp = t;
3501
3502#if 0
3503 if (reloc > 0)
3504 {
3505 /* sanity checks. */
3506 reloc_howto_type *reloc_howto
3507 = bfd_reloc_type_lookup (stdoutput,
3508 (bfd_reloc_code_real_type) reloc);
3509 unsigned reloc_bitsize = reloc_howto->bitsize;
3510 if (reloc_howto->rightshift)
3511 reloc_bitsize -= reloc_howto->rightshift;
3512 if (reloc_bitsize != operand->bits)
3513 {
3514 as_bad (_("invalid relocation %s for field"),
3515 bfd_get_reloc_code_name (reloc));
3516 return;
3517 }
3518 }
3519#endif
3520 if (insn->nfixups >= MAX_INSN_FIXUPS)
3521 as_fatal (_("too many fixups"));
3522
3523 struct arc_fixup *fixup;
3524 fixup = &insn->fixups[insn->nfixups++];
3525 fixup->exp = *t;
3526 fixup->reloc = reloc;
3527 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3528 fixup->pcrel = pcrel;
3529 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3530 TRUE : FALSE;
3531 break;
3532 }
3533 }
3534
3535 /* Handle flags. */
3536 for (i = 0; i < nflg; i++)
3537 {
3538 const struct arc_flag_operand *flg_operand =
3539 &arc_flag_operands[pflags[i].code];
3540
3541 /* Check if the instruction has a delay slot. */
3542 if (!strcmp (flg_operand->name, "d"))
3543 has_delay_slot = TRUE;
3544
3545 /* There is an exceptional case when we cannot insert a flag
3546 just as it is. The .T flag must be handled in relation with
3547 the relative address. */
3548 if (!strcmp (flg_operand->name, "t")
3549 || !strcmp (flg_operand->name, "nt"))
3550 {
3551 unsigned bitYoperand = 0;
3552 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3553 if (!strcmp (flg_operand->name, "t"))
3554 if (!strcmp (opcode->name, "bbit0")
3555 || !strcmp (opcode->name, "bbit1"))
3556 bitYoperand = arc_NToperand;
3557 else
3558 bitYoperand = arc_Toperand;
3559 else
3560 if (!strcmp (opcode->name, "bbit0")
3561 || !strcmp (opcode->name, "bbit1"))
3562 bitYoperand = arc_Toperand;
3563 else
3564 bitYoperand = arc_NToperand;
3565
3566 gas_assert (reloc_exp != NULL);
3567 if (reloc_exp->X_op == O_constant)
3568 {
3569 /* Check if we have a constant and solved it
3570 immediately. */
3571 offsetT val = reloc_exp->X_add_number;
3572 image |= insert_operand (image, &arc_operands[bitYoperand],
3573 val, NULL, 0);
3574 }
3575 else
3576 {
3577 struct arc_fixup *fixup;
3578
3579 if (insn->nfixups >= MAX_INSN_FIXUPS)
3580 as_fatal (_("too many fixups"));
3581
3582 fixup = &insn->fixups[insn->nfixups++];
3583 fixup->exp = *reloc_exp;
3584 fixup->reloc = -bitYoperand;
3585 fixup->pcrel = pcrel;
3586 fixup->islong = FALSE;
3587 }
3588 }
3589 else
3590 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
3591 << flg_operand->shift;
3592 }
3593
4670103e
CZ		 3594 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
3595
886a2506
NC		 3596 /* Short instruction? */
3597 insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
3598
3599 insn->insn = image;
3600
3601 /* Update last insn status. */
3602 arc_last_insns[1] = arc_last_insns[0];
3603 arc_last_insns[0].opcode = opcode;
3604 arc_last_insns[0].has_limm = insn->has_limm;
3605 arc_last_insns[0].has_delay_slot = has_delay_slot;
3606
3607 /* Check if the current instruction is legally used. */
3608 if (arc_last_insns[1].has_delay_slot
3609 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3610 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3611 _("A jump/branch instruction in delay slot."));
3612}
3613
886a2506
NC		 3614void
3615arc_handle_align (fragS* fragP)
3616{
3617 if ((fragP)->fr_type == rs_align_code)
3618 {
3619 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
3620 valueT count = ((fragP)->fr_next->fr_address
3621 - (fragP)->fr_address - (fragP)->fr_fix);
3622
3623 (fragP)->fr_var = 2;
3624
3625 if (count & 1)/* Padding in the gap till the next 2-byte
3626 boundary with 0s. */
3627 {
3628 (fragP)->fr_fix++;
3629 *dest++ = 0;
3630 }
3631 /* Writing nop_s. */
3632 md_number_to_chars (dest, NOP_OPCODE_S, 2);
3633 }
3634}
3635
3636/* Here we decide which fixups can be adjusted to make them relative
3637 to the beginning of the section instead of the symbol. Basically
3638 we need to make sure that the dynamic relocations are done
3639 correctly, so in some cases we force the original symbol to be
3640 used. */
3641
3642int
3643tc_arc_fix_adjustable (fixS *fixP)
3644{
3645
3646 /* Prevent all adjustments to global symbols. */
3647 if (S_IS_EXTERNAL (fixP->fx_addsy))
3648 return 0;
3649 if (S_IS_WEAK (fixP->fx_addsy))
3650 return 0;
3651
3652 /* Adjust_reloc_syms doesn't know about the GOT. */
3653 switch (fixP->fx_r_type)
3654 {
3655 case BFD_RELOC_ARC_GOTPC32:
3656 case BFD_RELOC_ARC_PLT32:
3657 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3658 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3659 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3660 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3661 return 0;
3662
3663 default:
3664 break;
3665 }
3666
841fdfcd 3667 return 1;
886a2506
NC		 3668}
3669
3670/* Compute the reloc type of an expression EXP. */
3671
3672static void
3673arc_check_reloc (expressionS *exp,
3674 bfd_reloc_code_real_type *r_type_p)
3675{
3676 if (*r_type_p == BFD_RELOC_32
3677 && exp->X_op == O_subtract
3678 && exp->X_op_symbol != NULL
3679 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 3680 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 3681}
3682
3683
3684/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3685
3686void
3687arc_cons_fix_new (fragS *frag,
3688 int off,
3689 int size,
3690 expressionS *exp,
3691 bfd_reloc_code_real_type r_type)
3692{
3693 r_type = BFD_RELOC_UNUSED;
3694
3695 switch (size)
3696 {
3697 case 1:
3698 r_type = BFD_RELOC_8;
3699 break;
3700
3701 case 2:
3702 r_type = BFD_RELOC_16;
3703 break;
3704
3705 case 3:
3706 r_type = BFD_RELOC_24;
3707 break;
3708
3709 case 4:
3710 r_type = BFD_RELOC_32;
3711 arc_check_reloc (exp, &r_type);
3712 break;
3713
3714 case 8:
3715 r_type = BFD_RELOC_64;
3716 break;
3717
3718 default:
3719 as_bad (_("unsupported BFD relocation size %u"), size);
3720 r_type = BFD_RELOC_UNUSED;
3721 }
3722
3723 fix_new_exp (frag, off, size, exp, 0, r_type);
3724}
3725
3726/* The actual routine that checks the ZOL conditions. */
3727
3728static void
3729check_zol (symbolS *s)
3730{
3731 switch (arc_mach_type)
3732 {
3733 case bfd_mach_arc_arcv2:
3734 if (arc_target & ARC_OPCODE_ARCv2EM)
3735 return;
3736
3737 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
3738 || arc_last_insns[1].has_delay_slot)
3739 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3740 S_GET_NAME (s));
3741
3742 break;
3743 case bfd_mach_arc_arc600:
3744
3745 if (is_kernel_insn_p (arc_last_insns[0].opcode))
3746 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3747 S_GET_NAME (s));
3748
3749 if (arc_last_insns[0].has_limm
3750 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3751 as_bad (_("A jump instruction with long immediate detected at the \
3752end of the ZOL label @%s"), S_GET_NAME (s));
3753
3754 /* Fall through. */
8699fc3e 3755 case bfd_mach_arc_nps400:
886a2506
NC		 3756 case bfd_mach_arc_arc700:
3757 if (arc_last_insns[0].has_delay_slot)
3758 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3759 S_GET_NAME (s));
3760
3761 break;
3762 default:
3763 break;
3764 }
3765}
3766
3767/* If ZOL end check the last two instruction for illegals. */
3768void
3769arc_frob_label (symbolS * sym)
3770{
3771 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
3772 check_zol (sym);
3773
3774 dwarf2_emit_label (sym);
ea1562b3 3775}
4670103e
CZ		 3776
3777/* Used because generic relaxation assumes a pc-rel value whilst we
3778 also relax instructions that use an absolute value resolved out of
3779 relative values (if that makes any sense). An example: 'add r1,
3780 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3781 but if they're in the same section we can subtract the section
3782 offset relocation which ends up in a resolved value. So if @.L2 is
3783 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3784 .text + 0x40 = 0x10. */
3785int
3786arc_pcrel_adjust (fragS *fragP)
3787{
3788 if (!fragP->tc_frag_data.pcrel)
3789 return fragP->fr_address + fragP->fr_fix;
3790
3791 return 0;
3792}
726c18e1
CZ		 3793
3794/* Initialize the DWARF-2 unwind information for this procedure. */
3795
3796void
3797tc_arc_frame_initial_instructions (void)
3798{
3799 /* Stack pointer is register 28. */
3800 cfi_add_CFA_def_cfa_register (28);
3801}
3802
3803int
3804tc_arc_regname_to_dw2regnum (char *regname)
3805{
3806 struct symbol *sym;
3807
3808 sym = hash_find (arc_reg_hash, regname);
3809 if (sym)
3810 return S_GET_VALUE (sym);
3811
3812 return -1;
3813}
GDB Binutils - Deliverables
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