Commit | Line | Data |
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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
b90efa5b | 2 | Copyright (C) 1994-2015 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b RE |
34 | #include "opcode/arm.h" |
35 | ||
b99bd4ef NC |
36 | #ifdef OBJ_ELF |
37 | #include "elf/arm.h" | |
a394c00f | 38 | #include "dw2gencfi.h" |
b99bd4ef NC |
39 | #endif |
40 | ||
f0927246 NC |
41 | #include "dwarf2dbg.h" |
42 | ||
7ed4c4c5 NC |
43 | #ifdef OBJ_ELF |
44 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
45 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
46 | ||
47 | /* This structure holds the unwinding state. */ | |
48 | ||
49 | static struct | |
50 | { | |
c19d1205 ZW |
51 | symbolS * proc_start; |
52 | symbolS * table_entry; | |
53 | symbolS * personality_routine; | |
54 | int personality_index; | |
7ed4c4c5 | 55 | /* The segment containing the function. */ |
c19d1205 ZW |
56 | segT saved_seg; |
57 | subsegT saved_subseg; | |
7ed4c4c5 NC |
58 | /* Opcodes generated from this function. */ |
59 | unsigned char * opcodes; | |
c19d1205 ZW |
60 | int opcode_count; |
61 | int opcode_alloc; | |
7ed4c4c5 | 62 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 63 | offsetT frame_size; |
7ed4c4c5 NC |
64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
65 | multiple adjustments. We can also omit the final adjustment | |
66 | when using a frame pointer. */ | |
c19d1205 | 67 | offsetT pending_offset; |
7ed4c4c5 | 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
70 | offsetT fp_offset; | |
71 | int fp_reg; | |
7ed4c4c5 | 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 73 | unsigned fp_used:1; |
7ed4c4c5 | 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 75 | unsigned sp_restored:1; |
7ed4c4c5 NC |
76 | } unwind; |
77 | ||
8b1ad454 NC |
78 | #endif /* OBJ_ELF */ |
79 | ||
4962c51a MS |
80 | /* Results from operand parsing worker functions. */ |
81 | ||
82 | typedef enum | |
83 | { | |
84 | PARSE_OPERAND_SUCCESS, | |
85 | PARSE_OPERAND_FAIL, | |
86 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
87 | } parse_operand_result; | |
88 | ||
33a392fb PB |
89 | enum arm_float_abi |
90 | { | |
91 | ARM_FLOAT_ABI_HARD, | |
92 | ARM_FLOAT_ABI_SOFTFP, | |
93 | ARM_FLOAT_ABI_SOFT | |
94 | }; | |
95 | ||
c19d1205 | 96 | /* Types of processor to assemble for. */ |
b99bd4ef | 97 | #ifndef CPU_DEFAULT |
8a59fff3 | 98 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 99 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
100 | changing gas' default behaviour depending upon the build host. |
101 | ||
102 | If you have a target that requires a default CPU option then the you | |
103 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
104 | #endif |
105 | ||
106 | #ifndef FPU_DEFAULT | |
c820d418 MM |
107 | # ifdef TE_LINUX |
108 | # define FPU_DEFAULT FPU_ARCH_FPA | |
109 | # elif defined (TE_NetBSD) | |
110 | # ifdef OBJ_ELF | |
111 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
112 | # else | |
113 | /* Legacy a.out format. */ | |
114 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
115 | # endif | |
4e7fd91e PB |
116 | # elif defined (TE_VXWORKS) |
117 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
118 | # else |
119 | /* For backwards compatibility, default to FPA. */ | |
120 | # define FPU_DEFAULT FPU_ARCH_FPA | |
121 | # endif | |
122 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 123 | |
c19d1205 | 124 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 125 | |
e74cfd16 PB |
126 | static arm_feature_set cpu_variant; |
127 | static arm_feature_set arm_arch_used; | |
128 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 129 | |
b99bd4ef | 130 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
131 | static int uses_apcs_26 = FALSE; |
132 | static int atpcs = FALSE; | |
b34976b6 AM |
133 | static int support_interwork = FALSE; |
134 | static int uses_apcs_float = FALSE; | |
c19d1205 | 135 | static int pic_code = FALSE; |
845b51d6 | 136 | static int fix_v4bx = FALSE; |
278df34e NS |
137 | /* Warn on using deprecated features. */ |
138 | static int warn_on_deprecated = TRUE; | |
139 | ||
2e6976a8 DG |
140 | /* Understand CodeComposer Studio assembly syntax. */ |
141 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
823d2571 TG |
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); | |
e74cfd16 | 179 | static const arm_feature_set arm_ext_v4t_5 = |
823d2571 TG |
180 | ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); | |
187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); | |
188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M); | |
189 | static const arm_feature_set arm_ext_v6_notm = | |
190 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); | |
191 | static const arm_feature_set arm_ext_v6_dsp = | |
192 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); | |
193 | static const arm_feature_set arm_ext_barrier = | |
194 | ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); | |
195 | static const arm_feature_set arm_ext_msr = | |
196 | ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); | |
197 | static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); | |
198 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); | |
199 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); | |
200 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); | |
201 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); | |
202 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); | |
7e806470 | 203 | static const arm_feature_set arm_ext_m = |
823d2571 TG |
204 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M); |
205 | static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); | |
206 | static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); | |
207 | static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); | |
208 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); | |
209 | static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); | |
ddfded2f | 210 | static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); |
e74cfd16 PB |
211 | |
212 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
823d2571 | 213 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1); |
e74cfd16 PB |
214 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; |
215 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 216 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 217 | |
2d447fca | 218 | static const arm_feature_set arm_cext_iwmmxt2 = |
823d2571 | 219 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); |
e74cfd16 | 220 | static const arm_feature_set arm_cext_iwmmxt = |
823d2571 | 221 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); |
e74cfd16 | 222 | static const arm_feature_set arm_cext_xscale = |
823d2571 | 223 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); |
e74cfd16 | 224 | static const arm_feature_set arm_cext_maverick = |
823d2571 TG |
225 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); |
226 | static const arm_feature_set fpu_fpa_ext_v1 = | |
227 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); | |
228 | static const arm_feature_set fpu_fpa_ext_v2 = | |
229 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); | |
e74cfd16 | 230 | static const arm_feature_set fpu_vfp_ext_v1xd = |
823d2571 TG |
231 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); |
232 | static const arm_feature_set fpu_vfp_ext_v1 = | |
233 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); | |
234 | static const arm_feature_set fpu_vfp_ext_v2 = | |
235 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); | |
236 | static const arm_feature_set fpu_vfp_ext_v3xd = | |
237 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); | |
238 | static const arm_feature_set fpu_vfp_ext_v3 = | |
239 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); | |
b1cc4aeb | 240 | static const arm_feature_set fpu_vfp_ext_d32 = |
823d2571 TG |
241 | ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); |
242 | static const arm_feature_set fpu_neon_ext_v1 = | |
243 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); | |
5287ad62 | 244 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
823d2571 TG |
245 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
246 | static const arm_feature_set fpu_vfp_fp16 = | |
247 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); | |
248 | static const arm_feature_set fpu_neon_ext_fma = | |
249 | ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); | |
250 | static const arm_feature_set fpu_vfp_ext_fma = | |
251 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); | |
bca38921 | 252 | static const arm_feature_set fpu_vfp_ext_armv8 = |
823d2571 | 253 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); |
a715796b | 254 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
823d2571 | 255 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); |
bca38921 | 256 | static const arm_feature_set fpu_neon_ext_armv8 = |
823d2571 | 257 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); |
bca38921 | 258 | static const arm_feature_set fpu_crypto_ext_armv8 = |
823d2571 | 259 | ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); |
dd5181d5 | 260 | static const arm_feature_set crc_ext_armv8 = |
823d2571 | 261 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8); |
d6b4b13e MW |
262 | static const arm_feature_set fpu_neon_ext_v8_1 = |
263 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA); | |
e74cfd16 | 264 | |
33a392fb | 265 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
266 | /* Record user cpu selection for object attributes. */ |
267 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
268 | /* Must be long enough to hold any of the names in arm_cpus. */ |
269 | static char selected_cpu_name[16]; | |
8d67f500 | 270 | |
aacf0b33 KT |
271 | extern FLONUM_TYPE generic_floating_point_number; |
272 | ||
8d67f500 NC |
273 | /* Return if no cpu was selected on command-line. */ |
274 | static bfd_boolean | |
275 | no_cpu_selected (void) | |
276 | { | |
823d2571 | 277 | return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); |
8d67f500 NC |
278 | } |
279 | ||
7cc69913 | 280 | #ifdef OBJ_ELF |
deeaaff8 DJ |
281 | # ifdef EABI_DEFAULT |
282 | static int meabi_flags = EABI_DEFAULT; | |
283 | # else | |
d507cf36 | 284 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 285 | # endif |
e1da3f5b | 286 | |
ee3c0378 AS |
287 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
288 | ||
e1da3f5b | 289 | bfd_boolean |
5f4273c7 | 290 | arm_is_eabi (void) |
e1da3f5b PB |
291 | { |
292 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
293 | } | |
7cc69913 | 294 | #endif |
b99bd4ef | 295 | |
b99bd4ef | 296 | #ifdef OBJ_ELF |
c19d1205 | 297 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
298 | symbolS * GOT_symbol; |
299 | #endif | |
300 | ||
b99bd4ef NC |
301 | /* 0: assemble for ARM, |
302 | 1: assemble for Thumb, | |
303 | 2: assemble for Thumb even though target CPU does not support thumb | |
304 | instructions. */ | |
305 | static int thumb_mode = 0; | |
8dc2430f NC |
306 | /* A value distinct from the possible values for thumb_mode that we |
307 | can use to record whether thumb_mode has been copied into the | |
308 | tc_frag_data field of a frag. */ | |
309 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 310 | |
e07e6e58 NC |
311 | /* Specifies the intrinsic IT insn behavior mode. */ |
312 | enum implicit_it_mode | |
313 | { | |
314 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
315 | IMPLICIT_IT_MODE_ARM = 0x01, | |
316 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
317 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
318 | }; | |
319 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
320 | ||
c19d1205 ZW |
321 | /* If unified_syntax is true, we are processing the new unified |
322 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
323 | ||
324 | - Immediate operands do not require a # prefix. | |
325 | - Conditional affixes always appear at the end of the | |
326 | instruction. (For backward compatibility, those instructions | |
327 | that formerly had them in the middle, continue to accept them | |
328 | there.) | |
329 | - The IT instruction may appear, and if it does is validated | |
330 | against subsequent conditional affixes. It does not generate | |
331 | machine code. | |
332 | ||
333 | Important differences from the old Thumb mode: | |
334 | ||
335 | - Immediate operands do not require a # prefix. | |
336 | - Most of the V6T2 instructions are only available in unified mode. | |
337 | - The .N and .W suffixes are recognized and honored (it is an error | |
338 | if they cannot be honored). | |
339 | - All instructions set the flags if and only if they have an 's' affix. | |
340 | - Conditional affixes may be used. They are validated against | |
341 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
342 | conditional affix except in the scope of an IT instruction. */ | |
343 | ||
344 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 345 | |
bacebabc RM |
346 | /* An immediate operand can start with #, and ld*, st*, pld operands |
347 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
348 | before a [, which can appear as the first operand for pld. |
349 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
350 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 351 | |
5287ad62 JB |
352 | enum neon_el_type |
353 | { | |
dcbf9037 | 354 | NT_invtype, |
5287ad62 JB |
355 | NT_untyped, |
356 | NT_integer, | |
357 | NT_float, | |
358 | NT_poly, | |
359 | NT_signed, | |
dcbf9037 | 360 | NT_unsigned |
5287ad62 JB |
361 | }; |
362 | ||
363 | struct neon_type_el | |
364 | { | |
365 | enum neon_el_type type; | |
366 | unsigned size; | |
367 | }; | |
368 | ||
369 | #define NEON_MAX_TYPE_ELS 4 | |
370 | ||
371 | struct neon_type | |
372 | { | |
373 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
374 | unsigned elems; | |
375 | }; | |
376 | ||
e07e6e58 NC |
377 | enum it_instruction_type |
378 | { | |
379 | OUTSIDE_IT_INSN, | |
380 | INSIDE_IT_INSN, | |
381 | INSIDE_IT_LAST_INSN, | |
382 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 383 | if inside, should be the last one. */ |
e07e6e58 | 384 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 385 | i.e. BKPT and NOP. */ |
e07e6e58 NC |
386 | IT_INSN /* The IT insn has been parsed. */ |
387 | }; | |
388 | ||
ad6cec43 MGD |
389 | /* The maximum number of operands we need. */ |
390 | #define ARM_IT_MAX_OPERANDS 6 | |
391 | ||
b99bd4ef NC |
392 | struct arm_it |
393 | { | |
c19d1205 | 394 | const char * error; |
b99bd4ef | 395 | unsigned long instruction; |
c19d1205 ZW |
396 | int size; |
397 | int size_req; | |
398 | int cond; | |
037e8744 JB |
399 | /* "uncond_value" is set to the value in place of the conditional field in |
400 | unconditional versions of the instruction, or -1 if nothing is | |
401 | appropriate. */ | |
402 | int uncond_value; | |
5287ad62 | 403 | struct neon_type vectype; |
88714cb8 DG |
404 | /* This does not indicate an actual NEON instruction, only that |
405 | the mnemonic accepts neon-style type suffixes. */ | |
406 | int is_neon; | |
0110f2b8 PB |
407 | /* Set to the opcode if the instruction needs relaxation. |
408 | Zero if the instruction is not relaxed. */ | |
409 | unsigned long relax; | |
b99bd4ef NC |
410 | struct |
411 | { | |
412 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
413 | expressionS exp; |
414 | int pc_rel; | |
b99bd4ef | 415 | } reloc; |
b99bd4ef | 416 | |
e07e6e58 NC |
417 | enum it_instruction_type it_insn_type; |
418 | ||
c19d1205 ZW |
419 | struct |
420 | { | |
421 | unsigned reg; | |
ca3f61f7 | 422 | signed int imm; |
dcbf9037 | 423 | struct neon_type_el vectype; |
ca3f61f7 NC |
424 | unsigned present : 1; /* Operand present. */ |
425 | unsigned isreg : 1; /* Operand was a register. */ | |
426 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
427 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
428 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 429 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
430 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
431 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
432 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 433 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 434 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 435 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
436 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
437 | unsigned writeback : 1; /* Operand has trailing ! */ | |
438 | unsigned preind : 1; /* Preindexed address. */ | |
439 | unsigned postind : 1; /* Postindexed address. */ | |
440 | unsigned negative : 1; /* Index register was negated. */ | |
441 | unsigned shifted : 1; /* Shift applied to operation. */ | |
442 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 443 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
444 | }; |
445 | ||
c19d1205 | 446 | static struct arm_it inst; |
b99bd4ef NC |
447 | |
448 | #define NUM_FLOAT_VALS 8 | |
449 | ||
05d2d07e | 450 | const char * fp_const[] = |
b99bd4ef NC |
451 | { |
452 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
453 | }; | |
454 | ||
c19d1205 | 455 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
456 | #define MAX_LITTLENUMS 6 |
457 | ||
458 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
459 | ||
460 | #define FAIL (-1) | |
461 | #define SUCCESS (0) | |
462 | ||
463 | #define SUFF_S 1 | |
464 | #define SUFF_D 2 | |
465 | #define SUFF_E 3 | |
466 | #define SUFF_P 4 | |
467 | ||
c19d1205 ZW |
468 | #define CP_T_X 0x00008000 |
469 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 470 | |
c19d1205 ZW |
471 | #define CONDS_BIT 0x00100000 |
472 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
473 | |
474 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
475 | ||
476 | struct asm_cond | |
477 | { | |
d3ce72d0 | 478 | const char * template_name; |
c921be7d | 479 | unsigned long value; |
b99bd4ef NC |
480 | }; |
481 | ||
c19d1205 | 482 | #define COND_ALWAYS 0xE |
b99bd4ef | 483 | |
b99bd4ef NC |
484 | struct asm_psr |
485 | { | |
d3ce72d0 | 486 | const char * template_name; |
c921be7d | 487 | unsigned long field; |
b99bd4ef NC |
488 | }; |
489 | ||
62b3e311 PB |
490 | struct asm_barrier_opt |
491 | { | |
e797f7e0 MGD |
492 | const char * template_name; |
493 | unsigned long value; | |
494 | const arm_feature_set arch; | |
62b3e311 PB |
495 | }; |
496 | ||
2d2255b5 | 497 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
498 | #define SPSR_BIT (1 << 22) |
499 | ||
c19d1205 ZW |
500 | /* The individual PSR flag bits. */ |
501 | #define PSR_c (1 << 16) | |
502 | #define PSR_x (1 << 17) | |
503 | #define PSR_s (1 << 18) | |
504 | #define PSR_f (1 << 19) | |
b99bd4ef | 505 | |
c19d1205 | 506 | struct reloc_entry |
bfae80f2 | 507 | { |
c921be7d NC |
508 | char * name; |
509 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
510 | }; |
511 | ||
5287ad62 | 512 | enum vfp_reg_pos |
bfae80f2 | 513 | { |
5287ad62 JB |
514 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
515 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
516 | }; |
517 | ||
518 | enum vfp_ldstm_type | |
519 | { | |
520 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
521 | }; | |
522 | ||
dcbf9037 JB |
523 | /* Bits for DEFINED field in neon_typed_alias. */ |
524 | #define NTA_HASTYPE 1 | |
525 | #define NTA_HASINDEX 2 | |
526 | ||
527 | struct neon_typed_alias | |
528 | { | |
c921be7d NC |
529 | unsigned char defined; |
530 | unsigned char index; | |
531 | struct neon_type_el eltype; | |
dcbf9037 JB |
532 | }; |
533 | ||
c19d1205 ZW |
534 | /* ARM register categories. This includes coprocessor numbers and various |
535 | architecture extensions' registers. */ | |
536 | enum arm_reg_type | |
bfae80f2 | 537 | { |
c19d1205 ZW |
538 | REG_TYPE_RN, |
539 | REG_TYPE_CP, | |
540 | REG_TYPE_CN, | |
541 | REG_TYPE_FN, | |
542 | REG_TYPE_VFS, | |
543 | REG_TYPE_VFD, | |
5287ad62 | 544 | REG_TYPE_NQ, |
037e8744 | 545 | REG_TYPE_VFSD, |
5287ad62 | 546 | REG_TYPE_NDQ, |
037e8744 | 547 | REG_TYPE_NSDQ, |
c19d1205 ZW |
548 | REG_TYPE_VFC, |
549 | REG_TYPE_MVF, | |
550 | REG_TYPE_MVD, | |
551 | REG_TYPE_MVFX, | |
552 | REG_TYPE_MVDX, | |
553 | REG_TYPE_MVAX, | |
554 | REG_TYPE_DSPSC, | |
555 | REG_TYPE_MMXWR, | |
556 | REG_TYPE_MMXWC, | |
557 | REG_TYPE_MMXWCG, | |
558 | REG_TYPE_XSCALE, | |
90ec0d68 | 559 | REG_TYPE_RNB |
bfae80f2 RE |
560 | }; |
561 | ||
dcbf9037 JB |
562 | /* Structure for a hash table entry for a register. |
563 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
564 | information which states whether a vector type or index is specified (for a | |
565 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
566 | struct reg_entry |
567 | { | |
c921be7d | 568 | const char * name; |
90ec0d68 | 569 | unsigned int number; |
c921be7d NC |
570 | unsigned char type; |
571 | unsigned char builtin; | |
572 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
573 | }; |
574 | ||
c19d1205 | 575 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 576 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
577 | { |
578 | N_("ARM register expected"), | |
579 | N_("bad or missing co-processor number"), | |
580 | N_("co-processor register expected"), | |
581 | N_("FPA register expected"), | |
582 | N_("VFP single precision register expected"), | |
5287ad62 JB |
583 | N_("VFP/Neon double precision register expected"), |
584 | N_("Neon quad precision register expected"), | |
037e8744 | 585 | N_("VFP single or double precision register expected"), |
5287ad62 | 586 | N_("Neon double or quad precision register expected"), |
037e8744 | 587 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
588 | N_("VFP system register expected"), |
589 | N_("Maverick MVF register expected"), | |
590 | N_("Maverick MVD register expected"), | |
591 | N_("Maverick MVFX register expected"), | |
592 | N_("Maverick MVDX register expected"), | |
593 | N_("Maverick MVAX register expected"), | |
594 | N_("Maverick DSPSC register expected"), | |
595 | N_("iWMMXt data register expected"), | |
596 | N_("iWMMXt control register expected"), | |
597 | N_("iWMMXt scalar register expected"), | |
598 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
599 | }; |
600 | ||
c19d1205 | 601 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 602 | #define REG_R12 12 |
c19d1205 ZW |
603 | #define REG_SP 13 |
604 | #define REG_LR 14 | |
605 | #define REG_PC 15 | |
404ff6b5 | 606 | |
b99bd4ef NC |
607 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
608 | take 2: */ | |
c19d1205 | 609 | #define INSN_SIZE 4 |
b99bd4ef NC |
610 | |
611 | struct asm_opcode | |
612 | { | |
613 | /* Basic string to match. */ | |
d3ce72d0 | 614 | const char * template_name; |
c19d1205 ZW |
615 | |
616 | /* Parameters to instruction. */ | |
5be8be5d | 617 | unsigned int operands[8]; |
c19d1205 ZW |
618 | |
619 | /* Conditional tag - see opcode_lookup. */ | |
620 | unsigned int tag : 4; | |
b99bd4ef NC |
621 | |
622 | /* Basic instruction code. */ | |
c19d1205 | 623 | unsigned int avalue : 28; |
b99bd4ef | 624 | |
c19d1205 ZW |
625 | /* Thumb-format instruction code. */ |
626 | unsigned int tvalue; | |
b99bd4ef | 627 | |
90e4755a | 628 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
629 | const arm_feature_set * avariant; |
630 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
631 | |
632 | /* Function to call to encode instruction in ARM format. */ | |
633 | void (* aencode) (void); | |
b99bd4ef | 634 | |
c19d1205 ZW |
635 | /* Function to call to encode instruction in Thumb format. */ |
636 | void (* tencode) (void); | |
b99bd4ef NC |
637 | }; |
638 | ||
a737bd4d NC |
639 | /* Defines for various bits that we will want to toggle. */ |
640 | #define INST_IMMEDIATE 0x02000000 | |
641 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 642 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
643 | #define SHIFT_BY_REG 0x00000010 |
644 | #define PRE_INDEX 0x01000000 | |
645 | #define INDEX_UP 0x00800000 | |
646 | #define WRITE_BACK 0x00200000 | |
647 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 648 | #define CPSI_MMOD 0x00020000 |
90e4755a | 649 | |
a737bd4d NC |
650 | #define LITERAL_MASK 0xf000f000 |
651 | #define OPCODE_MASK 0xfe1fffff | |
652 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 653 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 654 | |
efd81785 PB |
655 | #define T2_SUBS_PC_LR 0xf3de8f00 |
656 | ||
a737bd4d | 657 | #define DATA_OP_SHIFT 21 |
90e4755a | 658 | |
ef8d22e6 PB |
659 | #define T2_OPCODE_MASK 0xfe1fffff |
660 | #define T2_DATA_OP_SHIFT 21 | |
661 | ||
6530b175 NC |
662 | #define A_COND_MASK 0xf0000000 |
663 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
664 | ||
665 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
666 | #define A1_OPCODE_PUSH 0x092d0000 | |
667 | #define A2_OPCODE_PUSH 0x052d0004 | |
668 | #define A2_OPCODE_POP 0x049d0004 | |
669 | ||
a737bd4d NC |
670 | /* Codes to distinguish the arithmetic instructions. */ |
671 | #define OPCODE_AND 0 | |
672 | #define OPCODE_EOR 1 | |
673 | #define OPCODE_SUB 2 | |
674 | #define OPCODE_RSB 3 | |
675 | #define OPCODE_ADD 4 | |
676 | #define OPCODE_ADC 5 | |
677 | #define OPCODE_SBC 6 | |
678 | #define OPCODE_RSC 7 | |
679 | #define OPCODE_TST 8 | |
680 | #define OPCODE_TEQ 9 | |
681 | #define OPCODE_CMP 10 | |
682 | #define OPCODE_CMN 11 | |
683 | #define OPCODE_ORR 12 | |
684 | #define OPCODE_MOV 13 | |
685 | #define OPCODE_BIC 14 | |
686 | #define OPCODE_MVN 15 | |
90e4755a | 687 | |
ef8d22e6 PB |
688 | #define T2_OPCODE_AND 0 |
689 | #define T2_OPCODE_BIC 1 | |
690 | #define T2_OPCODE_ORR 2 | |
691 | #define T2_OPCODE_ORN 3 | |
692 | #define T2_OPCODE_EOR 4 | |
693 | #define T2_OPCODE_ADD 8 | |
694 | #define T2_OPCODE_ADC 10 | |
695 | #define T2_OPCODE_SBC 11 | |
696 | #define T2_OPCODE_SUB 13 | |
697 | #define T2_OPCODE_RSB 14 | |
698 | ||
a737bd4d NC |
699 | #define T_OPCODE_MUL 0x4340 |
700 | #define T_OPCODE_TST 0x4200 | |
701 | #define T_OPCODE_CMN 0x42c0 | |
702 | #define T_OPCODE_NEG 0x4240 | |
703 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 704 | |
a737bd4d NC |
705 | #define T_OPCODE_ADD_R3 0x1800 |
706 | #define T_OPCODE_SUB_R3 0x1a00 | |
707 | #define T_OPCODE_ADD_HI 0x4400 | |
708 | #define T_OPCODE_ADD_ST 0xb000 | |
709 | #define T_OPCODE_SUB_ST 0xb080 | |
710 | #define T_OPCODE_ADD_SP 0xa800 | |
711 | #define T_OPCODE_ADD_PC 0xa000 | |
712 | #define T_OPCODE_ADD_I8 0x3000 | |
713 | #define T_OPCODE_SUB_I8 0x3800 | |
714 | #define T_OPCODE_ADD_I3 0x1c00 | |
715 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 716 | |
a737bd4d NC |
717 | #define T_OPCODE_ASR_R 0x4100 |
718 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
719 | #define T_OPCODE_LSR_R 0x40c0 |
720 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
721 | #define T_OPCODE_ASR_I 0x1000 |
722 | #define T_OPCODE_LSL_I 0x0000 | |
723 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 724 | |
a737bd4d NC |
725 | #define T_OPCODE_MOV_I8 0x2000 |
726 | #define T_OPCODE_CMP_I8 0x2800 | |
727 | #define T_OPCODE_CMP_LR 0x4280 | |
728 | #define T_OPCODE_MOV_HR 0x4600 | |
729 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 730 | |
a737bd4d NC |
731 | #define T_OPCODE_LDR_PC 0x4800 |
732 | #define T_OPCODE_LDR_SP 0x9800 | |
733 | #define T_OPCODE_STR_SP 0x9000 | |
734 | #define T_OPCODE_LDR_IW 0x6800 | |
735 | #define T_OPCODE_STR_IW 0x6000 | |
736 | #define T_OPCODE_LDR_IH 0x8800 | |
737 | #define T_OPCODE_STR_IH 0x8000 | |
738 | #define T_OPCODE_LDR_IB 0x7800 | |
739 | #define T_OPCODE_STR_IB 0x7000 | |
740 | #define T_OPCODE_LDR_RW 0x5800 | |
741 | #define T_OPCODE_STR_RW 0x5000 | |
742 | #define T_OPCODE_LDR_RH 0x5a00 | |
743 | #define T_OPCODE_STR_RH 0x5200 | |
744 | #define T_OPCODE_LDR_RB 0x5c00 | |
745 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 746 | |
a737bd4d NC |
747 | #define T_OPCODE_PUSH 0xb400 |
748 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 749 | |
2fc8bdac | 750 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 751 | |
a737bd4d | 752 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 753 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 754 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 755 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
756 | |
757 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 758 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
759 | #define BAD_PC _("r15 not allowed here") |
760 | #define BAD_COND _("instruction cannot be conditional") | |
761 | #define BAD_OVERLAP _("registers may not be the same") | |
762 | #define BAD_HIREG _("lo register required") | |
763 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 764 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
765 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
766 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 767 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
768 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
769 | #define BAD_IT_COND _("incorrect condition in IT block") | |
770 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 771 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
772 | #define BAD_PC_ADDRESSING \ |
773 | _("cannot use register index with PC-relative addressing") | |
774 | #define BAD_PC_WRITEBACK \ | |
775 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 776 | #define BAD_RANGE _("branch out of range") |
dd5181d5 | 777 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
c19d1205 | 778 | |
c921be7d NC |
779 | static struct hash_control * arm_ops_hsh; |
780 | static struct hash_control * arm_cond_hsh; | |
781 | static struct hash_control * arm_shift_hsh; | |
782 | static struct hash_control * arm_psr_hsh; | |
783 | static struct hash_control * arm_v7m_psr_hsh; | |
784 | static struct hash_control * arm_reg_hsh; | |
785 | static struct hash_control * arm_reloc_hsh; | |
786 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 787 | |
b99bd4ef NC |
788 | /* Stuff needed to resolve the label ambiguity |
789 | As: | |
790 | ... | |
791 | label: <insn> | |
792 | may differ from: | |
793 | ... | |
794 | label: | |
5f4273c7 | 795 | <insn> */ |
b99bd4ef NC |
796 | |
797 | symbolS * last_label_seen; | |
b34976b6 | 798 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 799 | |
3d0c9500 NC |
800 | /* Literal pool structure. Held on a per-section |
801 | and per-sub-section basis. */ | |
a737bd4d | 802 | |
c19d1205 | 803 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 804 | typedef struct literal_pool |
b99bd4ef | 805 | { |
c921be7d NC |
806 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
807 | unsigned int next_free_entry; | |
808 | unsigned int id; | |
809 | symbolS * symbol; | |
810 | segT section; | |
811 | subsegT sub_section; | |
a8040cf2 NC |
812 | #ifdef OBJ_ELF |
813 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
814 | #endif | |
c921be7d | 815 | struct literal_pool * next; |
8335d6aa | 816 | unsigned int alignment; |
3d0c9500 | 817 | } literal_pool; |
b99bd4ef | 818 | |
3d0c9500 NC |
819 | /* Pointer to a linked list of literal pools. */ |
820 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 821 | |
2e6976a8 DG |
822 | typedef enum asmfunc_states |
823 | { | |
824 | OUTSIDE_ASMFUNC, | |
825 | WAITING_ASMFUNC_NAME, | |
826 | WAITING_ENDASMFUNC | |
827 | } asmfunc_states; | |
828 | ||
829 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
830 | ||
e07e6e58 NC |
831 | #ifdef OBJ_ELF |
832 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
833 | #else | |
834 | static struct current_it now_it; | |
835 | #endif | |
836 | ||
837 | static inline int | |
838 | now_it_compatible (int cond) | |
839 | { | |
840 | return (cond & ~1) == (now_it.cc & ~1); | |
841 | } | |
842 | ||
843 | static inline int | |
844 | conditional_insn (void) | |
845 | { | |
846 | return inst.cond != COND_ALWAYS; | |
847 | } | |
848 | ||
849 | static int in_it_block (void); | |
850 | ||
851 | static int handle_it_state (void); | |
852 | ||
853 | static void force_automatic_it_block_close (void); | |
854 | ||
c921be7d NC |
855 | static void it_fsm_post_encode (void); |
856 | ||
e07e6e58 NC |
857 | #define set_it_insn_type(type) \ |
858 | do \ | |
859 | { \ | |
860 | inst.it_insn_type = type; \ | |
861 | if (handle_it_state () == FAIL) \ | |
477330fc | 862 | return; \ |
e07e6e58 NC |
863 | } \ |
864 | while (0) | |
865 | ||
c921be7d NC |
866 | #define set_it_insn_type_nonvoid(type, failret) \ |
867 | do \ | |
868 | { \ | |
869 | inst.it_insn_type = type; \ | |
870 | if (handle_it_state () == FAIL) \ | |
477330fc | 871 | return failret; \ |
c921be7d NC |
872 | } \ |
873 | while(0) | |
874 | ||
e07e6e58 NC |
875 | #define set_it_insn_type_last() \ |
876 | do \ | |
877 | { \ | |
878 | if (inst.cond == COND_ALWAYS) \ | |
477330fc | 879 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 880 | else \ |
477330fc | 881 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
882 | } \ |
883 | while (0) | |
884 | ||
c19d1205 | 885 | /* Pure syntax. */ |
b99bd4ef | 886 | |
c19d1205 ZW |
887 | /* This array holds the chars that always start a comment. If the |
888 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 889 | char arm_comment_chars[] = "@"; |
3d0c9500 | 890 | |
c19d1205 ZW |
891 | /* This array holds the chars that only start a comment at the beginning of |
892 | a line. If the line seems to have the form '# 123 filename' | |
893 | .line and .file directives will appear in the pre-processed output. */ | |
894 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
895 | first line of the input file. This is because the compiler outputs | |
896 | #NO_APP at the beginning of its output. */ | |
897 | /* Also note that comments like this one will always work. */ | |
898 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 899 | |
2e6976a8 | 900 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 901 | |
c19d1205 ZW |
902 | /* Chars that can be used to separate mant |
903 | from exp in floating point numbers. */ | |
904 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 905 | |
c19d1205 ZW |
906 | /* Chars that mean this number is a floating point constant. */ |
907 | /* As in 0f12.456 */ | |
908 | /* or 0d1.2345e12 */ | |
b99bd4ef | 909 | |
c19d1205 | 910 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 911 | |
c19d1205 ZW |
912 | /* Prefix characters that indicate the start of an immediate |
913 | value. */ | |
914 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 915 | |
c19d1205 ZW |
916 | /* Separator character handling. */ |
917 | ||
918 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
919 | ||
920 | static inline int | |
921 | skip_past_char (char ** str, char c) | |
922 | { | |
8ab8155f NC |
923 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
924 | skip_whitespace (*str); | |
427d0db6 | 925 | |
c19d1205 ZW |
926 | if (**str == c) |
927 | { | |
928 | (*str)++; | |
929 | return SUCCESS; | |
3d0c9500 | 930 | } |
c19d1205 ZW |
931 | else |
932 | return FAIL; | |
933 | } | |
c921be7d | 934 | |
c19d1205 | 935 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 936 | |
c19d1205 ZW |
937 | /* Arithmetic expressions (possibly involving symbols). */ |
938 | ||
939 | /* Return TRUE if anything in the expression is a bignum. */ | |
940 | ||
941 | static int | |
942 | walk_no_bignums (symbolS * sp) | |
943 | { | |
944 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
945 | return 1; | |
946 | ||
947 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 948 | { |
c19d1205 ZW |
949 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
950 | || (symbol_get_value_expression (sp)->X_op_symbol | |
951 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
952 | } |
953 | ||
c19d1205 | 954 | return 0; |
3d0c9500 NC |
955 | } |
956 | ||
c19d1205 ZW |
957 | static int in_my_get_expression = 0; |
958 | ||
959 | /* Third argument to my_get_expression. */ | |
960 | #define GE_NO_PREFIX 0 | |
961 | #define GE_IMM_PREFIX 1 | |
962 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
963 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
964 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
965 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 966 | |
b99bd4ef | 967 | static int |
c19d1205 | 968 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 969 | { |
c19d1205 ZW |
970 | char * save_in; |
971 | segT seg; | |
b99bd4ef | 972 | |
c19d1205 ZW |
973 | /* In unified syntax, all prefixes are optional. */ |
974 | if (unified_syntax) | |
5287ad62 | 975 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 976 | : GE_OPT_PREFIX; |
b99bd4ef | 977 | |
c19d1205 | 978 | switch (prefix_mode) |
b99bd4ef | 979 | { |
c19d1205 ZW |
980 | case GE_NO_PREFIX: break; |
981 | case GE_IMM_PREFIX: | |
982 | if (!is_immediate_prefix (**str)) | |
983 | { | |
984 | inst.error = _("immediate expression requires a # prefix"); | |
985 | return FAIL; | |
986 | } | |
987 | (*str)++; | |
988 | break; | |
989 | case GE_OPT_PREFIX: | |
5287ad62 | 990 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
991 | if (is_immediate_prefix (**str)) |
992 | (*str)++; | |
993 | break; | |
994 | default: abort (); | |
995 | } | |
b99bd4ef | 996 | |
c19d1205 | 997 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 998 | |
c19d1205 ZW |
999 | save_in = input_line_pointer; |
1000 | input_line_pointer = *str; | |
1001 | in_my_get_expression = 1; | |
1002 | seg = expression (ep); | |
1003 | in_my_get_expression = 0; | |
1004 | ||
f86adc07 | 1005 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 1006 | { |
f86adc07 | 1007 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
1008 | *str = input_line_pointer; |
1009 | input_line_pointer = save_in; | |
1010 | if (inst.error == NULL) | |
f86adc07 NS |
1011 | inst.error = (ep->X_op == O_absent |
1012 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
1013 | return 1; |
1014 | } | |
b99bd4ef | 1015 | |
c19d1205 ZW |
1016 | #ifdef OBJ_AOUT |
1017 | if (seg != absolute_section | |
1018 | && seg != text_section | |
1019 | && seg != data_section | |
1020 | && seg != bss_section | |
1021 | && seg != undefined_section) | |
1022 | { | |
1023 | inst.error = _("bad segment"); | |
1024 | *str = input_line_pointer; | |
1025 | input_line_pointer = save_in; | |
1026 | return 1; | |
b99bd4ef | 1027 | } |
87975d2a AM |
1028 | #else |
1029 | (void) seg; | |
c19d1205 | 1030 | #endif |
b99bd4ef | 1031 | |
c19d1205 ZW |
1032 | /* Get rid of any bignums now, so that we don't generate an error for which |
1033 | we can't establish a line number later on. Big numbers are never valid | |
1034 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1035 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1036 | && (ep->X_op == O_big | |
477330fc | 1037 | || (ep->X_add_symbol |
5287ad62 | 1038 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1039 | || (ep->X_op_symbol |
5287ad62 | 1040 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1041 | { |
1042 | inst.error = _("invalid constant"); | |
1043 | *str = input_line_pointer; | |
1044 | input_line_pointer = save_in; | |
1045 | return 1; | |
1046 | } | |
b99bd4ef | 1047 | |
c19d1205 ZW |
1048 | *str = input_line_pointer; |
1049 | input_line_pointer = save_in; | |
1050 | return 0; | |
b99bd4ef NC |
1051 | } |
1052 | ||
c19d1205 ZW |
1053 | /* Turn a string in input_line_pointer into a floating point constant |
1054 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1055 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1056 | returned, or NULL on OK. | |
b99bd4ef | 1057 | |
c19d1205 ZW |
1058 | Note that fp constants aren't represent in the normal way on the ARM. |
1059 | In big endian mode, things are as expected. However, in little endian | |
1060 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1061 | within the words. For example, (double) 1.1 in big endian mode is | |
1062 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1063 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1064 | |
c19d1205 | 1065 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1066 | |
c19d1205 ZW |
1067 | char * |
1068 | md_atof (int type, char * litP, int * sizeP) | |
1069 | { | |
1070 | int prec; | |
1071 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1072 | char *t; | |
1073 | int i; | |
b99bd4ef | 1074 | |
c19d1205 ZW |
1075 | switch (type) |
1076 | { | |
1077 | case 'f': | |
1078 | case 'F': | |
1079 | case 's': | |
1080 | case 'S': | |
1081 | prec = 2; | |
1082 | break; | |
b99bd4ef | 1083 | |
c19d1205 ZW |
1084 | case 'd': |
1085 | case 'D': | |
1086 | case 'r': | |
1087 | case 'R': | |
1088 | prec = 4; | |
1089 | break; | |
b99bd4ef | 1090 | |
c19d1205 ZW |
1091 | case 'x': |
1092 | case 'X': | |
499ac353 | 1093 | prec = 5; |
c19d1205 | 1094 | break; |
b99bd4ef | 1095 | |
c19d1205 ZW |
1096 | case 'p': |
1097 | case 'P': | |
499ac353 | 1098 | prec = 5; |
c19d1205 | 1099 | break; |
a737bd4d | 1100 | |
c19d1205 ZW |
1101 | default: |
1102 | *sizeP = 0; | |
499ac353 | 1103 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1104 | } |
b99bd4ef | 1105 | |
c19d1205 ZW |
1106 | t = atof_ieee (input_line_pointer, type, words); |
1107 | if (t) | |
1108 | input_line_pointer = t; | |
499ac353 | 1109 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1110 | |
c19d1205 ZW |
1111 | if (target_big_endian) |
1112 | { | |
1113 | for (i = 0; i < prec; i++) | |
1114 | { | |
499ac353 NC |
1115 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1116 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1117 | } |
1118 | } | |
1119 | else | |
1120 | { | |
e74cfd16 | 1121 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1122 | for (i = prec - 1; i >= 0; i--) |
1123 | { | |
499ac353 NC |
1124 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1125 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1126 | } |
1127 | else | |
1128 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1129 | For an 8 byte float the order is 1 0 3 2. */ | |
1130 | for (i = 0; i < prec; i += 2) | |
1131 | { | |
499ac353 NC |
1132 | md_number_to_chars (litP, (valueT) words[i + 1], |
1133 | sizeof (LITTLENUM_TYPE)); | |
1134 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1135 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1136 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1137 | } |
1138 | } | |
b99bd4ef | 1139 | |
499ac353 | 1140 | return NULL; |
c19d1205 | 1141 | } |
b99bd4ef | 1142 | |
c19d1205 ZW |
1143 | /* We handle all bad expressions here, so that we can report the faulty |
1144 | instruction in the error message. */ | |
1145 | void | |
91d6fa6a | 1146 | md_operand (expressionS * exp) |
c19d1205 ZW |
1147 | { |
1148 | if (in_my_get_expression) | |
91d6fa6a | 1149 | exp->X_op = O_illegal; |
b99bd4ef NC |
1150 | } |
1151 | ||
c19d1205 | 1152 | /* Immediate values. */ |
b99bd4ef | 1153 | |
c19d1205 ZW |
1154 | /* Generic immediate-value read function for use in directives. |
1155 | Accepts anything that 'expression' can fold to a constant. | |
1156 | *val receives the number. */ | |
1157 | #ifdef OBJ_ELF | |
1158 | static int | |
1159 | immediate_for_directive (int *val) | |
b99bd4ef | 1160 | { |
c19d1205 ZW |
1161 | expressionS exp; |
1162 | exp.X_op = O_illegal; | |
b99bd4ef | 1163 | |
c19d1205 ZW |
1164 | if (is_immediate_prefix (*input_line_pointer)) |
1165 | { | |
1166 | input_line_pointer++; | |
1167 | expression (&exp); | |
1168 | } | |
b99bd4ef | 1169 | |
c19d1205 ZW |
1170 | if (exp.X_op != O_constant) |
1171 | { | |
1172 | as_bad (_("expected #constant")); | |
1173 | ignore_rest_of_line (); | |
1174 | return FAIL; | |
1175 | } | |
1176 | *val = exp.X_add_number; | |
1177 | return SUCCESS; | |
b99bd4ef | 1178 | } |
c19d1205 | 1179 | #endif |
b99bd4ef | 1180 | |
c19d1205 | 1181 | /* Register parsing. */ |
b99bd4ef | 1182 | |
c19d1205 ZW |
1183 | /* Generic register parser. CCP points to what should be the |
1184 | beginning of a register name. If it is indeed a valid register | |
1185 | name, advance CCP over it and return the reg_entry structure; | |
1186 | otherwise return NULL. Does not issue diagnostics. */ | |
1187 | ||
1188 | static struct reg_entry * | |
1189 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1190 | { |
c19d1205 ZW |
1191 | char *start = *ccp; |
1192 | char *p; | |
1193 | struct reg_entry *reg; | |
b99bd4ef | 1194 | |
477330fc RM |
1195 | skip_whitespace (start); |
1196 | ||
c19d1205 ZW |
1197 | #ifdef REGISTER_PREFIX |
1198 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1199 | return NULL; |
c19d1205 ZW |
1200 | start++; |
1201 | #endif | |
1202 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1203 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1204 | start++; | |
1205 | #endif | |
b99bd4ef | 1206 | |
c19d1205 ZW |
1207 | p = start; |
1208 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1209 | return NULL; | |
b99bd4ef | 1210 | |
c19d1205 ZW |
1211 | do |
1212 | p++; | |
1213 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1214 | ||
1215 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1216 | ||
1217 | if (!reg) | |
1218 | return NULL; | |
1219 | ||
1220 | *ccp = p; | |
1221 | return reg; | |
b99bd4ef NC |
1222 | } |
1223 | ||
1224 | static int | |
dcbf9037 | 1225 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1226 | enum arm_reg_type type) |
b99bd4ef | 1227 | { |
c19d1205 ZW |
1228 | /* Alternative syntaxes are accepted for a few register classes. */ |
1229 | switch (type) | |
1230 | { | |
1231 | case REG_TYPE_MVF: | |
1232 | case REG_TYPE_MVD: | |
1233 | case REG_TYPE_MVFX: | |
1234 | case REG_TYPE_MVDX: | |
1235 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1236 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1237 | return reg->number; |
1238 | break; | |
69b97547 | 1239 | |
c19d1205 ZW |
1240 | case REG_TYPE_CP: |
1241 | /* For backward compatibility, a bare number is valid here. */ | |
1242 | { | |
1243 | unsigned long processor = strtoul (start, ccp, 10); | |
1244 | if (*ccp != start && processor <= 15) | |
1245 | return processor; | |
1246 | } | |
6057a28f | 1247 | |
c19d1205 ZW |
1248 | case REG_TYPE_MMXWC: |
1249 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1250 | instructions that take WC registers. */ | |
79134647 | 1251 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1252 | return reg->number; |
6057a28f | 1253 | break; |
c19d1205 | 1254 | |
6057a28f | 1255 | default: |
c19d1205 | 1256 | break; |
6057a28f NC |
1257 | } |
1258 | ||
dcbf9037 JB |
1259 | return FAIL; |
1260 | } | |
1261 | ||
1262 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1263 | return value is the register number or FAIL. */ | |
1264 | ||
1265 | static int | |
1266 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1267 | { | |
1268 | char *start = *ccp; | |
1269 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1270 | int ret; | |
1271 | ||
1272 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1273 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1274 | return FAIL; | |
1275 | ||
1276 | if (reg && reg->type == type) | |
1277 | return reg->number; | |
1278 | ||
1279 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1280 | return ret; | |
1281 | ||
c19d1205 ZW |
1282 | *ccp = start; |
1283 | return FAIL; | |
1284 | } | |
69b97547 | 1285 | |
dcbf9037 JB |
1286 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1287 | character. Does no verification at this stage that the type fits the opcode | |
1288 | properly. E.g., | |
1289 | ||
1290 | .i32.i32.s16 | |
1291 | .s32.f32 | |
1292 | .u16 | |
1293 | ||
1294 | Can all be legally parsed by this function. | |
1295 | ||
1296 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1297 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1298 | type, FAIL if not. */ | |
1299 | ||
1300 | static int | |
1301 | parse_neon_type (struct neon_type *type, char **str) | |
1302 | { | |
1303 | char *ptr = *str; | |
1304 | ||
1305 | if (type) | |
1306 | type->elems = 0; | |
1307 | ||
1308 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1309 | { | |
1310 | enum neon_el_type thistype = NT_untyped; | |
1311 | unsigned thissize = -1u; | |
1312 | ||
1313 | if (*ptr != '.') | |
1314 | break; | |
1315 | ||
1316 | ptr++; | |
1317 | ||
1318 | /* Just a size without an explicit type. */ | |
1319 | if (ISDIGIT (*ptr)) | |
1320 | goto parsesize; | |
1321 | ||
1322 | switch (TOLOWER (*ptr)) | |
1323 | { | |
1324 | case 'i': thistype = NT_integer; break; | |
1325 | case 'f': thistype = NT_float; break; | |
1326 | case 'p': thistype = NT_poly; break; | |
1327 | case 's': thistype = NT_signed; break; | |
1328 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1329 | case 'd': |
1330 | thistype = NT_float; | |
1331 | thissize = 64; | |
1332 | ptr++; | |
1333 | goto done; | |
dcbf9037 JB |
1334 | default: |
1335 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1336 | return FAIL; | |
1337 | } | |
1338 | ||
1339 | ptr++; | |
1340 | ||
1341 | /* .f is an abbreviation for .f32. */ | |
1342 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1343 | thissize = 32; | |
1344 | else | |
1345 | { | |
1346 | parsesize: | |
1347 | thissize = strtoul (ptr, &ptr, 10); | |
1348 | ||
1349 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1350 | && thissize != 64) |
1351 | { | |
1352 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1353 | return FAIL; |
1354 | } | |
1355 | } | |
1356 | ||
037e8744 | 1357 | done: |
dcbf9037 | 1358 | if (type) |
477330fc RM |
1359 | { |
1360 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1361 | type->el[type->elems].size = thissize; |
1362 | type->elems++; | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | /* Empty/missing type is not a successful parse. */ | |
1367 | if (type->elems == 0) | |
1368 | return FAIL; | |
1369 | ||
1370 | *str = ptr; | |
1371 | ||
1372 | return SUCCESS; | |
1373 | } | |
1374 | ||
1375 | /* Errors may be set multiple times during parsing or bit encoding | |
1376 | (particularly in the Neon bits), but usually the earliest error which is set | |
1377 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1378 | errors by calling this function. */ | |
1379 | ||
1380 | static void | |
1381 | first_error (const char *err) | |
1382 | { | |
1383 | if (!inst.error) | |
1384 | inst.error = err; | |
1385 | } | |
1386 | ||
1387 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1388 | static int | |
1389 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1390 | { | |
1391 | char *str = *ccp; | |
1392 | struct neon_type optype; | |
1393 | ||
1394 | if (*str == '.') | |
1395 | { | |
1396 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1397 | { |
1398 | if (optype.elems == 1) | |
1399 | *vectype = optype.el[0]; | |
1400 | else | |
1401 | { | |
1402 | first_error (_("only one type should be specified for operand")); | |
1403 | return FAIL; | |
1404 | } | |
1405 | } | |
dcbf9037 | 1406 | else |
477330fc RM |
1407 | { |
1408 | first_error (_("vector type expected")); | |
1409 | return FAIL; | |
1410 | } | |
dcbf9037 JB |
1411 | } |
1412 | else | |
1413 | return FAIL; | |
5f4273c7 | 1414 | |
dcbf9037 | 1415 | *ccp = str; |
5f4273c7 | 1416 | |
dcbf9037 JB |
1417 | return SUCCESS; |
1418 | } | |
1419 | ||
1420 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1421 | a 4-bit integer. */ | |
1422 | ||
1423 | #define NEON_ALL_LANES 15 | |
1424 | #define NEON_INTERLEAVE_LANES 14 | |
1425 | ||
1426 | /* Parse either a register or a scalar, with an optional type. Return the | |
1427 | register number, and optionally fill in the actual type of the register | |
1428 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1429 | type/index information in *TYPEINFO. */ | |
1430 | ||
1431 | static int | |
1432 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1433 | enum arm_reg_type *rtype, |
1434 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1435 | { |
1436 | char *str = *ccp; | |
1437 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1438 | struct neon_typed_alias atype; | |
1439 | struct neon_type_el parsetype; | |
1440 | ||
1441 | atype.defined = 0; | |
1442 | atype.index = -1; | |
1443 | atype.eltype.type = NT_invtype; | |
1444 | atype.eltype.size = -1; | |
1445 | ||
1446 | /* Try alternate syntax for some types of register. Note these are mutually | |
1447 | exclusive with the Neon syntax extensions. */ | |
1448 | if (reg == NULL) | |
1449 | { | |
1450 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1451 | if (altreg != FAIL) | |
477330fc | 1452 | *ccp = str; |
dcbf9037 | 1453 | if (typeinfo) |
477330fc | 1454 | *typeinfo = atype; |
dcbf9037 JB |
1455 | return altreg; |
1456 | } | |
1457 | ||
037e8744 JB |
1458 | /* Undo polymorphism when a set of register types may be accepted. */ |
1459 | if ((type == REG_TYPE_NDQ | |
1460 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1461 | || (type == REG_TYPE_VFSD | |
477330fc | 1462 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1463 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1464 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1465 | || reg->type == REG_TYPE_NQ)) | |
f512f76f NC |
1466 | || (type == REG_TYPE_MMXWC |
1467 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1468 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1469 | |
1470 | if (type != reg->type) | |
1471 | return FAIL; | |
1472 | ||
1473 | if (reg->neon) | |
1474 | atype = *reg->neon; | |
5f4273c7 | 1475 | |
dcbf9037 JB |
1476 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1477 | { | |
1478 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1479 | { |
1480 | first_error (_("can't redefine type for operand")); | |
1481 | return FAIL; | |
1482 | } | |
dcbf9037 JB |
1483 | atype.defined |= NTA_HASTYPE; |
1484 | atype.eltype = parsetype; | |
1485 | } | |
5f4273c7 | 1486 | |
dcbf9037 JB |
1487 | if (skip_past_char (&str, '[') == SUCCESS) |
1488 | { | |
1489 | if (type != REG_TYPE_VFD) | |
477330fc RM |
1490 | { |
1491 | first_error (_("only D registers may be indexed")); | |
1492 | return FAIL; | |
1493 | } | |
5f4273c7 | 1494 | |
dcbf9037 | 1495 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1496 | { |
1497 | first_error (_("can't change index for operand")); | |
1498 | return FAIL; | |
1499 | } | |
dcbf9037 JB |
1500 | |
1501 | atype.defined |= NTA_HASINDEX; | |
1502 | ||
1503 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1504 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1505 | else |
477330fc RM |
1506 | { |
1507 | expressionS exp; | |
dcbf9037 | 1508 | |
477330fc | 1509 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1510 | |
477330fc RM |
1511 | if (exp.X_op != O_constant) |
1512 | { | |
1513 | first_error (_("constant expression required")); | |
1514 | return FAIL; | |
1515 | } | |
dcbf9037 | 1516 | |
477330fc RM |
1517 | if (skip_past_char (&str, ']') == FAIL) |
1518 | return FAIL; | |
dcbf9037 | 1519 | |
477330fc RM |
1520 | atype.index = exp.X_add_number; |
1521 | } | |
dcbf9037 | 1522 | } |
5f4273c7 | 1523 | |
dcbf9037 JB |
1524 | if (typeinfo) |
1525 | *typeinfo = atype; | |
5f4273c7 | 1526 | |
dcbf9037 JB |
1527 | if (rtype) |
1528 | *rtype = type; | |
5f4273c7 | 1529 | |
dcbf9037 | 1530 | *ccp = str; |
5f4273c7 | 1531 | |
dcbf9037 JB |
1532 | return reg->number; |
1533 | } | |
1534 | ||
1535 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1536 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1537 | register (e.g. Neon double or quad reg when either has been requested). | |
1538 | - If this is a Neon vector type with additional type information, fill | |
1539 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1540 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1541 | |
1542 | static int | |
1543 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1544 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1545 | { |
1546 | struct neon_typed_alias atype; | |
1547 | char *str = *ccp; | |
1548 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1549 | ||
1550 | if (reg == FAIL) | |
1551 | return FAIL; | |
1552 | ||
0855e32b NS |
1553 | /* Do not allow regname(... to parse as a register. */ |
1554 | if (*str == '(') | |
1555 | return FAIL; | |
1556 | ||
dcbf9037 JB |
1557 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1558 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1559 | { | |
1560 | first_error (_("register operand expected, but got scalar")); | |
1561 | return FAIL; | |
1562 | } | |
1563 | ||
1564 | if (vectype) | |
1565 | *vectype = atype.eltype; | |
1566 | ||
1567 | *ccp = str; | |
1568 | ||
1569 | return reg; | |
1570 | } | |
1571 | ||
1572 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1573 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1574 | ||
5287ad62 JB |
1575 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1576 | have enough information to be able to do a good job bounds-checking. So, we | |
1577 | just do easy checks here, and do further checks later. */ | |
1578 | ||
1579 | static int | |
dcbf9037 | 1580 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1581 | { |
dcbf9037 | 1582 | int reg; |
5287ad62 | 1583 | char *str = *ccp; |
dcbf9037 | 1584 | struct neon_typed_alias atype; |
5f4273c7 | 1585 | |
dcbf9037 | 1586 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1587 | |
dcbf9037 | 1588 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1589 | return FAIL; |
5f4273c7 | 1590 | |
dcbf9037 | 1591 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1592 | { |
dcbf9037 | 1593 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1594 | return FAIL; |
1595 | } | |
dcbf9037 | 1596 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1597 | { |
dcbf9037 | 1598 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1599 | return FAIL; |
1600 | } | |
5f4273c7 | 1601 | |
dcbf9037 JB |
1602 | if (type) |
1603 | *type = atype.eltype; | |
5f4273c7 | 1604 | |
5287ad62 | 1605 | *ccp = str; |
5f4273c7 | 1606 | |
dcbf9037 | 1607 | return reg * 16 + atype.index; |
5287ad62 JB |
1608 | } |
1609 | ||
c19d1205 | 1610 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1611 | |
c19d1205 ZW |
1612 | static long |
1613 | parse_reg_list (char ** strp) | |
1614 | { | |
1615 | char * str = * strp; | |
1616 | long range = 0; | |
1617 | int another_range; | |
a737bd4d | 1618 | |
c19d1205 ZW |
1619 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1620 | do | |
6057a28f | 1621 | { |
477330fc RM |
1622 | skip_whitespace (str); |
1623 | ||
c19d1205 | 1624 | another_range = 0; |
a737bd4d | 1625 | |
c19d1205 ZW |
1626 | if (*str == '{') |
1627 | { | |
1628 | int in_range = 0; | |
1629 | int cur_reg = -1; | |
a737bd4d | 1630 | |
c19d1205 ZW |
1631 | str++; |
1632 | do | |
1633 | { | |
1634 | int reg; | |
6057a28f | 1635 | |
dcbf9037 | 1636 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1637 | { |
dcbf9037 | 1638 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1639 | return FAIL; |
1640 | } | |
a737bd4d | 1641 | |
c19d1205 ZW |
1642 | if (in_range) |
1643 | { | |
1644 | int i; | |
a737bd4d | 1645 | |
c19d1205 ZW |
1646 | if (reg <= cur_reg) |
1647 | { | |
dcbf9037 | 1648 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1649 | return FAIL; |
1650 | } | |
40a18ebd | 1651 | |
c19d1205 ZW |
1652 | for (i = cur_reg + 1; i < reg; i++) |
1653 | { | |
1654 | if (range & (1 << i)) | |
1655 | as_tsktsk | |
1656 | (_("Warning: duplicated register (r%d) in register list"), | |
1657 | i); | |
1658 | else | |
1659 | range |= 1 << i; | |
1660 | } | |
1661 | in_range = 0; | |
1662 | } | |
a737bd4d | 1663 | |
c19d1205 ZW |
1664 | if (range & (1 << reg)) |
1665 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1666 | reg); | |
1667 | else if (reg <= cur_reg) | |
1668 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1669 | |
c19d1205 ZW |
1670 | range |= 1 << reg; |
1671 | cur_reg = reg; | |
1672 | } | |
1673 | while (skip_past_comma (&str) != FAIL | |
1674 | || (in_range = 1, *str++ == '-')); | |
1675 | str--; | |
a737bd4d | 1676 | |
d996d970 | 1677 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1678 | { |
dcbf9037 | 1679 | first_error (_("missing `}'")); |
c19d1205 ZW |
1680 | return FAIL; |
1681 | } | |
1682 | } | |
1683 | else | |
1684 | { | |
91d6fa6a | 1685 | expressionS exp; |
40a18ebd | 1686 | |
91d6fa6a | 1687 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1688 | return FAIL; |
40a18ebd | 1689 | |
91d6fa6a | 1690 | if (exp.X_op == O_constant) |
c19d1205 | 1691 | { |
91d6fa6a NC |
1692 | if (exp.X_add_number |
1693 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1694 | { |
1695 | inst.error = _("invalid register mask"); | |
1696 | return FAIL; | |
1697 | } | |
a737bd4d | 1698 | |
91d6fa6a | 1699 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1700 | { |
91d6fa6a | 1701 | int regno = range & exp.X_add_number; |
a737bd4d | 1702 | |
c19d1205 ZW |
1703 | regno &= -regno; |
1704 | regno = (1 << regno) - 1; | |
1705 | as_tsktsk | |
1706 | (_("Warning: duplicated register (r%d) in register list"), | |
1707 | regno); | |
1708 | } | |
a737bd4d | 1709 | |
91d6fa6a | 1710 | range |= exp.X_add_number; |
c19d1205 ZW |
1711 | } |
1712 | else | |
1713 | { | |
1714 | if (inst.reloc.type != 0) | |
1715 | { | |
1716 | inst.error = _("expression too complex"); | |
1717 | return FAIL; | |
1718 | } | |
a737bd4d | 1719 | |
91d6fa6a | 1720 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1721 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1722 | inst.reloc.pc_rel = 0; | |
1723 | } | |
1724 | } | |
a737bd4d | 1725 | |
c19d1205 ZW |
1726 | if (*str == '|' || *str == '+') |
1727 | { | |
1728 | str++; | |
1729 | another_range = 1; | |
1730 | } | |
a737bd4d | 1731 | } |
c19d1205 | 1732 | while (another_range); |
a737bd4d | 1733 | |
c19d1205 ZW |
1734 | *strp = str; |
1735 | return range; | |
a737bd4d NC |
1736 | } |
1737 | ||
5287ad62 JB |
1738 | /* Types of registers in a list. */ |
1739 | ||
1740 | enum reg_list_els | |
1741 | { | |
1742 | REGLIST_VFP_S, | |
1743 | REGLIST_VFP_D, | |
1744 | REGLIST_NEON_D | |
1745 | }; | |
1746 | ||
c19d1205 ZW |
1747 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1748 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1749 | register. Parses registers of type ETYPE. |
1750 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1751 | - Q registers can be used to specify pairs of D registers | |
1752 | - { } can be omitted from around a singleton register list | |
477330fc RM |
1753 | FIXME: This is not implemented, as it would require backtracking in |
1754 | some cases, e.g.: | |
1755 | vtbl.8 d3,d4,d5 | |
1756 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1757 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1758 | - 32 D registers may be used (also true for VFPv3). |
1759 | FIXME: Types are ignored in these register lists, which is probably a | |
1760 | bug. */ | |
6057a28f | 1761 | |
c19d1205 | 1762 | static int |
037e8744 | 1763 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1764 | { |
037e8744 | 1765 | char *str = *ccp; |
c19d1205 ZW |
1766 | int base_reg; |
1767 | int new_base; | |
21d799b5 | 1768 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1769 | int max_regs = 0; |
c19d1205 ZW |
1770 | int count = 0; |
1771 | int warned = 0; | |
1772 | unsigned long mask = 0; | |
a737bd4d | 1773 | int i; |
6057a28f | 1774 | |
477330fc | 1775 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
1776 | { |
1777 | inst.error = _("expecting {"); | |
1778 | return FAIL; | |
1779 | } | |
6057a28f | 1780 | |
5287ad62 | 1781 | switch (etype) |
c19d1205 | 1782 | { |
5287ad62 | 1783 | case REGLIST_VFP_S: |
c19d1205 ZW |
1784 | regtype = REG_TYPE_VFS; |
1785 | max_regs = 32; | |
5287ad62 | 1786 | break; |
5f4273c7 | 1787 | |
5287ad62 JB |
1788 | case REGLIST_VFP_D: |
1789 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1790 | break; |
5f4273c7 | 1791 | |
b7fc2769 JB |
1792 | case REGLIST_NEON_D: |
1793 | regtype = REG_TYPE_NDQ; | |
1794 | break; | |
1795 | } | |
1796 | ||
1797 | if (etype != REGLIST_VFP_S) | |
1798 | { | |
b1cc4aeb PB |
1799 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1800 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
1801 | { |
1802 | max_regs = 32; | |
1803 | if (thumb_mode) | |
1804 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
1805 | fpu_vfp_ext_d32); | |
1806 | else | |
1807 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
1808 | fpu_vfp_ext_d32); | |
1809 | } | |
5287ad62 | 1810 | else |
477330fc | 1811 | max_regs = 16; |
c19d1205 | 1812 | } |
6057a28f | 1813 | |
c19d1205 | 1814 | base_reg = max_regs; |
a737bd4d | 1815 | |
c19d1205 ZW |
1816 | do |
1817 | { | |
5287ad62 | 1818 | int setmask = 1, addregs = 1; |
dcbf9037 | 1819 | |
037e8744 | 1820 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1821 | |
c19d1205 | 1822 | if (new_base == FAIL) |
a737bd4d | 1823 | { |
dcbf9037 | 1824 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1825 | return FAIL; |
1826 | } | |
5f4273c7 | 1827 | |
b7fc2769 | 1828 | if (new_base >= max_regs) |
477330fc RM |
1829 | { |
1830 | first_error (_("register out of range in list")); | |
1831 | return FAIL; | |
1832 | } | |
5f4273c7 | 1833 | |
5287ad62 JB |
1834 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1835 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
1836 | { |
1837 | setmask = 3; | |
1838 | addregs = 2; | |
1839 | } | |
5287ad62 | 1840 | |
c19d1205 ZW |
1841 | if (new_base < base_reg) |
1842 | base_reg = new_base; | |
a737bd4d | 1843 | |
5287ad62 | 1844 | if (mask & (setmask << new_base)) |
c19d1205 | 1845 | { |
dcbf9037 | 1846 | first_error (_("invalid register list")); |
c19d1205 | 1847 | return FAIL; |
a737bd4d | 1848 | } |
a737bd4d | 1849 | |
c19d1205 ZW |
1850 | if ((mask >> new_base) != 0 && ! warned) |
1851 | { | |
1852 | as_tsktsk (_("register list not in ascending order")); | |
1853 | warned = 1; | |
1854 | } | |
0bbf2aa4 | 1855 | |
5287ad62 JB |
1856 | mask |= setmask << new_base; |
1857 | count += addregs; | |
0bbf2aa4 | 1858 | |
037e8744 | 1859 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1860 | { |
1861 | int high_range; | |
0bbf2aa4 | 1862 | |
037e8744 | 1863 | str++; |
0bbf2aa4 | 1864 | |
037e8744 | 1865 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 1866 | == FAIL) |
c19d1205 ZW |
1867 | { |
1868 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1869 | return FAIL; | |
1870 | } | |
0bbf2aa4 | 1871 | |
477330fc RM |
1872 | if (high_range >= max_regs) |
1873 | { | |
1874 | first_error (_("register out of range in list")); | |
1875 | return FAIL; | |
1876 | } | |
b7fc2769 | 1877 | |
477330fc RM |
1878 | if (regtype == REG_TYPE_NQ) |
1879 | high_range = high_range + 1; | |
5287ad62 | 1880 | |
c19d1205 ZW |
1881 | if (high_range <= new_base) |
1882 | { | |
1883 | inst.error = _("register range not in ascending order"); | |
1884 | return FAIL; | |
1885 | } | |
0bbf2aa4 | 1886 | |
5287ad62 | 1887 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1888 | { |
5287ad62 | 1889 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1890 | { |
c19d1205 ZW |
1891 | inst.error = _("invalid register list"); |
1892 | return FAIL; | |
0bbf2aa4 | 1893 | } |
c19d1205 | 1894 | |
5287ad62 JB |
1895 | mask |= setmask << new_base; |
1896 | count += addregs; | |
0bbf2aa4 | 1897 | } |
0bbf2aa4 | 1898 | } |
0bbf2aa4 | 1899 | } |
037e8744 | 1900 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1901 | |
037e8744 | 1902 | str++; |
0bbf2aa4 | 1903 | |
c19d1205 ZW |
1904 | /* Sanity check -- should have raised a parse error above. */ |
1905 | if (count == 0 || count > max_regs) | |
1906 | abort (); | |
1907 | ||
1908 | *pbase = base_reg; | |
1909 | ||
1910 | /* Final test -- the registers must be consecutive. */ | |
1911 | mask >>= base_reg; | |
1912 | for (i = 0; i < count; i++) | |
1913 | { | |
1914 | if ((mask & (1u << i)) == 0) | |
1915 | { | |
1916 | inst.error = _("non-contiguous register range"); | |
1917 | return FAIL; | |
1918 | } | |
1919 | } | |
1920 | ||
037e8744 JB |
1921 | *ccp = str; |
1922 | ||
c19d1205 | 1923 | return count; |
b99bd4ef NC |
1924 | } |
1925 | ||
dcbf9037 JB |
1926 | /* True if two alias types are the same. */ |
1927 | ||
c921be7d | 1928 | static bfd_boolean |
dcbf9037 JB |
1929 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1930 | { | |
1931 | if (!a && !b) | |
c921be7d | 1932 | return TRUE; |
5f4273c7 | 1933 | |
dcbf9037 | 1934 | if (!a || !b) |
c921be7d | 1935 | return FALSE; |
dcbf9037 JB |
1936 | |
1937 | if (a->defined != b->defined) | |
c921be7d | 1938 | return FALSE; |
5f4273c7 | 1939 | |
dcbf9037 JB |
1940 | if ((a->defined & NTA_HASTYPE) != 0 |
1941 | && (a->eltype.type != b->eltype.type | |
477330fc | 1942 | || a->eltype.size != b->eltype.size)) |
c921be7d | 1943 | return FALSE; |
dcbf9037 JB |
1944 | |
1945 | if ((a->defined & NTA_HASINDEX) != 0 | |
1946 | && (a->index != b->index)) | |
c921be7d | 1947 | return FALSE; |
5f4273c7 | 1948 | |
c921be7d | 1949 | return TRUE; |
dcbf9037 JB |
1950 | } |
1951 | ||
5287ad62 JB |
1952 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1953 | The base register is put in *PBASE. | |
dcbf9037 | 1954 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1955 | the return value. |
1956 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1957 | Bits [6:5] encode the list length (minus one). |
1958 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1959 | |
5287ad62 | 1960 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1961 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1962 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1963 | ||
1964 | static int | |
dcbf9037 | 1965 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
477330fc | 1966 | struct neon_type_el *eltype) |
5287ad62 JB |
1967 | { |
1968 | char *ptr = *str; | |
1969 | int base_reg = -1; | |
1970 | int reg_incr = -1; | |
1971 | int count = 0; | |
1972 | int lane = -1; | |
1973 | int leading_brace = 0; | |
1974 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1975 | const char *const incr_error = _("register stride must be 1 or 2"); |
1976 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1977 | struct neon_typed_alias firsttype; |
5f4273c7 | 1978 | |
5287ad62 JB |
1979 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1980 | leading_brace = 1; | |
5f4273c7 | 1981 | |
5287ad62 JB |
1982 | do |
1983 | { | |
dcbf9037 JB |
1984 | struct neon_typed_alias atype; |
1985 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1986 | ||
5287ad62 | 1987 | if (getreg == FAIL) |
477330fc RM |
1988 | { |
1989 | first_error (_(reg_expected_msgs[rtype])); | |
1990 | return FAIL; | |
1991 | } | |
5f4273c7 | 1992 | |
5287ad62 | 1993 | if (base_reg == -1) |
477330fc RM |
1994 | { |
1995 | base_reg = getreg; | |
1996 | if (rtype == REG_TYPE_NQ) | |
1997 | { | |
1998 | reg_incr = 1; | |
1999 | } | |
2000 | firsttype = atype; | |
2001 | } | |
5287ad62 | 2002 | else if (reg_incr == -1) |
477330fc RM |
2003 | { |
2004 | reg_incr = getreg - base_reg; | |
2005 | if (reg_incr < 1 || reg_incr > 2) | |
2006 | { | |
2007 | first_error (_(incr_error)); | |
2008 | return FAIL; | |
2009 | } | |
2010 | } | |
5287ad62 | 2011 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
2012 | { |
2013 | first_error (_(incr_error)); | |
2014 | return FAIL; | |
2015 | } | |
dcbf9037 | 2016 | |
c921be7d | 2017 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2018 | { |
2019 | first_error (_(type_error)); | |
2020 | return FAIL; | |
2021 | } | |
5f4273c7 | 2022 | |
5287ad62 | 2023 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2024 | modes. */ |
5287ad62 | 2025 | if (ptr[0] == '-') |
477330fc RM |
2026 | { |
2027 | struct neon_typed_alias htype; | |
2028 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2029 | if (lane == -1) | |
2030 | lane = NEON_INTERLEAVE_LANES; | |
2031 | else if (lane != NEON_INTERLEAVE_LANES) | |
2032 | { | |
2033 | first_error (_(type_error)); | |
2034 | return FAIL; | |
2035 | } | |
2036 | if (reg_incr == -1) | |
2037 | reg_incr = 1; | |
2038 | else if (reg_incr != 1) | |
2039 | { | |
2040 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2041 | return FAIL; | |
2042 | } | |
2043 | ptr++; | |
2044 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2045 | if (hireg == FAIL) | |
2046 | { | |
2047 | first_error (_(reg_expected_msgs[rtype])); | |
2048 | return FAIL; | |
2049 | } | |
2050 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2051 | { | |
2052 | first_error (_(type_error)); | |
2053 | return FAIL; | |
2054 | } | |
2055 | count += hireg + dregs - getreg; | |
2056 | continue; | |
2057 | } | |
5f4273c7 | 2058 | |
5287ad62 JB |
2059 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2060 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2061 | { |
2062 | count += 2; | |
2063 | continue; | |
2064 | } | |
5f4273c7 | 2065 | |
dcbf9037 | 2066 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2067 | { |
2068 | if (lane == -1) | |
2069 | lane = atype.index; | |
2070 | else if (lane != atype.index) | |
2071 | { | |
2072 | first_error (_(type_error)); | |
2073 | return FAIL; | |
2074 | } | |
2075 | } | |
5287ad62 | 2076 | else if (lane == -1) |
477330fc | 2077 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2078 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2079 | { |
2080 | first_error (_(type_error)); | |
2081 | return FAIL; | |
2082 | } | |
5287ad62 JB |
2083 | count++; |
2084 | } | |
2085 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2086 | |
5287ad62 JB |
2087 | /* No lane set by [x]. We must be interleaving structures. */ |
2088 | if (lane == -1) | |
2089 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2090 | |
5287ad62 JB |
2091 | /* Sanity check. */ |
2092 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2093 | || (count > 1 && reg_incr == -1)) | |
2094 | { | |
dcbf9037 | 2095 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2096 | return FAIL; |
2097 | } | |
2098 | ||
2099 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2100 | { | |
dcbf9037 | 2101 | first_error (_("expected }")); |
5287ad62 JB |
2102 | return FAIL; |
2103 | } | |
5f4273c7 | 2104 | |
5287ad62 JB |
2105 | if (reg_incr == -1) |
2106 | reg_incr = 1; | |
2107 | ||
dcbf9037 JB |
2108 | if (eltype) |
2109 | *eltype = firsttype.eltype; | |
2110 | ||
5287ad62 JB |
2111 | *pbase = base_reg; |
2112 | *str = ptr; | |
5f4273c7 | 2113 | |
5287ad62 JB |
2114 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2115 | } | |
2116 | ||
c19d1205 ZW |
2117 | /* Parse an explicit relocation suffix on an expression. This is |
2118 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2119 | arm_reloc_hsh contains no entries, so this function can only | |
2120 | succeed if there is no () after the word. Returns -1 on error, | |
2121 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2122 | |
c19d1205 ZW |
2123 | static int |
2124 | parse_reloc (char **str) | |
b99bd4ef | 2125 | { |
c19d1205 ZW |
2126 | struct reloc_entry *r; |
2127 | char *p, *q; | |
b99bd4ef | 2128 | |
c19d1205 ZW |
2129 | if (**str != '(') |
2130 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2131 | |
c19d1205 ZW |
2132 | p = *str + 1; |
2133 | q = p; | |
2134 | ||
2135 | while (*q && *q != ')' && *q != ',') | |
2136 | q++; | |
2137 | if (*q != ')') | |
2138 | return -1; | |
2139 | ||
21d799b5 NC |
2140 | if ((r = (struct reloc_entry *) |
2141 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2142 | return -1; |
2143 | ||
2144 | *str = q + 1; | |
2145 | return r->reloc; | |
b99bd4ef NC |
2146 | } |
2147 | ||
c19d1205 ZW |
2148 | /* Directives: register aliases. */ |
2149 | ||
dcbf9037 | 2150 | static struct reg_entry * |
90ec0d68 | 2151 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2152 | { |
d3ce72d0 | 2153 | struct reg_entry *new_reg; |
c19d1205 | 2154 | const char *name; |
b99bd4ef | 2155 | |
d3ce72d0 | 2156 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2157 | { |
d3ce72d0 | 2158 | if (new_reg->builtin) |
c19d1205 | 2159 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2160 | |
c19d1205 ZW |
2161 | /* Only warn about a redefinition if it's not defined as the |
2162 | same register. */ | |
d3ce72d0 | 2163 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2164 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2165 | |
d929913e | 2166 | return NULL; |
c19d1205 | 2167 | } |
b99bd4ef | 2168 | |
c19d1205 | 2169 | name = xstrdup (str); |
d3ce72d0 | 2170 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2171 | |
d3ce72d0 NC |
2172 | new_reg->name = name; |
2173 | new_reg->number = number; | |
2174 | new_reg->type = type; | |
2175 | new_reg->builtin = FALSE; | |
2176 | new_reg->neon = NULL; | |
b99bd4ef | 2177 | |
d3ce72d0 | 2178 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2179 | abort (); |
5f4273c7 | 2180 | |
d3ce72d0 | 2181 | return new_reg; |
dcbf9037 JB |
2182 | } |
2183 | ||
2184 | static void | |
2185 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2186 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2187 | { |
2188 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2189 | |
dcbf9037 JB |
2190 | if (!reg) |
2191 | { | |
2192 | first_error (_("attempt to redefine typed alias")); | |
2193 | return; | |
2194 | } | |
5f4273c7 | 2195 | |
dcbf9037 JB |
2196 | if (atype) |
2197 | { | |
21d799b5 | 2198 | reg->neon = (struct neon_typed_alias *) |
477330fc | 2199 | xmalloc (sizeof (struct neon_typed_alias)); |
dcbf9037 JB |
2200 | *reg->neon = *atype; |
2201 | } | |
c19d1205 | 2202 | } |
b99bd4ef | 2203 | |
c19d1205 | 2204 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2205 | |
c19d1205 | 2206 | new_register_name .req existing_register_name |
b99bd4ef | 2207 | |
c19d1205 | 2208 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2209 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2210 | |
d929913e | 2211 | static bfd_boolean |
c19d1205 ZW |
2212 | create_register_alias (char * newname, char *p) |
2213 | { | |
2214 | struct reg_entry *old; | |
2215 | char *oldname, *nbuf; | |
2216 | size_t nlen; | |
b99bd4ef | 2217 | |
c19d1205 ZW |
2218 | /* The input scrubber ensures that whitespace after the mnemonic is |
2219 | collapsed to single spaces. */ | |
2220 | oldname = p; | |
2221 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2222 | return FALSE; |
b99bd4ef | 2223 | |
c19d1205 ZW |
2224 | oldname += 6; |
2225 | if (*oldname == '\0') | |
d929913e | 2226 | return FALSE; |
b99bd4ef | 2227 | |
21d799b5 | 2228 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2229 | if (!old) |
b99bd4ef | 2230 | { |
c19d1205 | 2231 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2232 | return TRUE; |
b99bd4ef NC |
2233 | } |
2234 | ||
c19d1205 ZW |
2235 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2236 | the desired alias name, and p points to its end. If not, then | |
2237 | the desired alias name is in the global original_case_string. */ | |
2238 | #ifdef TC_CASE_SENSITIVE | |
2239 | nlen = p - newname; | |
2240 | #else | |
2241 | newname = original_case_string; | |
2242 | nlen = strlen (newname); | |
2243 | #endif | |
b99bd4ef | 2244 | |
21d799b5 | 2245 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2246 | memcpy (nbuf, newname, nlen); |
2247 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2248 | |
c19d1205 ZW |
2249 | /* Create aliases under the new name as stated; an all-lowercase |
2250 | version of the new name; and an all-uppercase version of the new | |
2251 | name. */ | |
d929913e NC |
2252 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2253 | { | |
2254 | for (p = nbuf; *p; p++) | |
2255 | *p = TOUPPER (*p); | |
c19d1205 | 2256 | |
d929913e NC |
2257 | if (strncmp (nbuf, newname, nlen)) |
2258 | { | |
2259 | /* If this attempt to create an additional alias fails, do not bother | |
2260 | trying to create the all-lower case alias. We will fail and issue | |
2261 | a second, duplicate error message. This situation arises when the | |
2262 | programmer does something like: | |
2263 | foo .req r0 | |
2264 | Foo .req r1 | |
2265 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2266 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2267 | first .req. */ |
2268 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2269 | return TRUE; | |
2270 | } | |
c19d1205 | 2271 | |
d929913e NC |
2272 | for (p = nbuf; *p; p++) |
2273 | *p = TOLOWER (*p); | |
c19d1205 | 2274 | |
d929913e NC |
2275 | if (strncmp (nbuf, newname, nlen)) |
2276 | insert_reg_alias (nbuf, old->number, old->type); | |
2277 | } | |
c19d1205 | 2278 | |
d929913e | 2279 | return TRUE; |
b99bd4ef NC |
2280 | } |
2281 | ||
dcbf9037 JB |
2282 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2283 | X .dn d5.s32[1] | |
2284 | Y .qn 6.s16 | |
2285 | Z .dn d7 | |
2286 | T .dn Z[0] | |
2287 | These typed registers can be used instead of the types specified after the | |
2288 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2289 | specified directly, e.g.: | |
5f4273c7 | 2290 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2291 | |
c921be7d | 2292 | static bfd_boolean |
dcbf9037 JB |
2293 | create_neon_reg_alias (char *newname, char *p) |
2294 | { | |
2295 | enum arm_reg_type basetype; | |
2296 | struct reg_entry *basereg; | |
2297 | struct reg_entry mybasereg; | |
2298 | struct neon_type ntype; | |
2299 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2300 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2301 | int namelen; |
5f4273c7 | 2302 | |
dcbf9037 JB |
2303 | typeinfo.defined = 0; |
2304 | typeinfo.eltype.type = NT_invtype; | |
2305 | typeinfo.eltype.size = -1; | |
2306 | typeinfo.index = -1; | |
5f4273c7 | 2307 | |
dcbf9037 | 2308 | nameend = p; |
5f4273c7 | 2309 | |
dcbf9037 JB |
2310 | if (strncmp (p, " .dn ", 5) == 0) |
2311 | basetype = REG_TYPE_VFD; | |
2312 | else if (strncmp (p, " .qn ", 5) == 0) | |
2313 | basetype = REG_TYPE_NQ; | |
2314 | else | |
c921be7d | 2315 | return FALSE; |
5f4273c7 | 2316 | |
dcbf9037 | 2317 | p += 5; |
5f4273c7 | 2318 | |
dcbf9037 | 2319 | if (*p == '\0') |
c921be7d | 2320 | return FALSE; |
5f4273c7 | 2321 | |
dcbf9037 JB |
2322 | basereg = arm_reg_parse_multi (&p); |
2323 | ||
2324 | if (basereg && basereg->type != basetype) | |
2325 | { | |
2326 | as_bad (_("bad type for register")); | |
c921be7d | 2327 | return FALSE; |
dcbf9037 JB |
2328 | } |
2329 | ||
2330 | if (basereg == NULL) | |
2331 | { | |
2332 | expressionS exp; | |
2333 | /* Try parsing as an integer. */ | |
2334 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2335 | if (exp.X_op != O_constant) | |
477330fc RM |
2336 | { |
2337 | as_bad (_("expression must be constant")); | |
2338 | return FALSE; | |
2339 | } | |
dcbf9037 JB |
2340 | basereg = &mybasereg; |
2341 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2342 | : exp.X_add_number; |
dcbf9037 JB |
2343 | basereg->neon = 0; |
2344 | } | |
2345 | ||
2346 | if (basereg->neon) | |
2347 | typeinfo = *basereg->neon; | |
2348 | ||
2349 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2350 | { | |
2351 | /* We got a type. */ | |
2352 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2353 | { |
2354 | as_bad (_("can't redefine the type of a register alias")); | |
2355 | return FALSE; | |
2356 | } | |
5f4273c7 | 2357 | |
dcbf9037 JB |
2358 | typeinfo.defined |= NTA_HASTYPE; |
2359 | if (ntype.elems != 1) | |
477330fc RM |
2360 | { |
2361 | as_bad (_("you must specify a single type only")); | |
2362 | return FALSE; | |
2363 | } | |
dcbf9037 JB |
2364 | typeinfo.eltype = ntype.el[0]; |
2365 | } | |
5f4273c7 | 2366 | |
dcbf9037 JB |
2367 | if (skip_past_char (&p, '[') == SUCCESS) |
2368 | { | |
2369 | expressionS exp; | |
2370 | /* We got a scalar index. */ | |
5f4273c7 | 2371 | |
dcbf9037 | 2372 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2373 | { |
2374 | as_bad (_("can't redefine the index of a scalar alias")); | |
2375 | return FALSE; | |
2376 | } | |
5f4273c7 | 2377 | |
dcbf9037 | 2378 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2379 | |
dcbf9037 | 2380 | if (exp.X_op != O_constant) |
477330fc RM |
2381 | { |
2382 | as_bad (_("scalar index must be constant")); | |
2383 | return FALSE; | |
2384 | } | |
5f4273c7 | 2385 | |
dcbf9037 JB |
2386 | typeinfo.defined |= NTA_HASINDEX; |
2387 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2388 | |
dcbf9037 | 2389 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2390 | { |
2391 | as_bad (_("expecting ]")); | |
2392 | return FALSE; | |
2393 | } | |
dcbf9037 JB |
2394 | } |
2395 | ||
15735687 NS |
2396 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2397 | the desired alias name, and p points to its end. If not, then | |
2398 | the desired alias name is in the global original_case_string. */ | |
2399 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2400 | namelen = nameend - newname; |
15735687 NS |
2401 | #else |
2402 | newname = original_case_string; | |
2403 | namelen = strlen (newname); | |
2404 | #endif | |
2405 | ||
21d799b5 | 2406 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2407 | strncpy (namebuf, newname, namelen); |
2408 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2409 | |
dcbf9037 | 2410 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2411 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2412 | |
dcbf9037 JB |
2413 | /* Insert name in all uppercase. */ |
2414 | for (p = namebuf; *p; p++) | |
2415 | *p = TOUPPER (*p); | |
5f4273c7 | 2416 | |
dcbf9037 JB |
2417 | if (strncmp (namebuf, newname, namelen)) |
2418 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2419 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2420 | |
dcbf9037 JB |
2421 | /* Insert name in all lowercase. */ |
2422 | for (p = namebuf; *p; p++) | |
2423 | *p = TOLOWER (*p); | |
5f4273c7 | 2424 | |
dcbf9037 JB |
2425 | if (strncmp (namebuf, newname, namelen)) |
2426 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2427 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2428 | |
c921be7d | 2429 | return TRUE; |
dcbf9037 JB |
2430 | } |
2431 | ||
c19d1205 ZW |
2432 | /* Should never be called, as .req goes between the alias and the |
2433 | register name, not at the beginning of the line. */ | |
c921be7d | 2434 | |
b99bd4ef | 2435 | static void |
c19d1205 | 2436 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2437 | { |
c19d1205 ZW |
2438 | as_bad (_("invalid syntax for .req directive")); |
2439 | } | |
b99bd4ef | 2440 | |
dcbf9037 JB |
2441 | static void |
2442 | s_dn (int a ATTRIBUTE_UNUSED) | |
2443 | { | |
2444 | as_bad (_("invalid syntax for .dn directive")); | |
2445 | } | |
2446 | ||
2447 | static void | |
2448 | s_qn (int a ATTRIBUTE_UNUSED) | |
2449 | { | |
2450 | as_bad (_("invalid syntax for .qn directive")); | |
2451 | } | |
2452 | ||
c19d1205 ZW |
2453 | /* The .unreq directive deletes an alias which was previously defined |
2454 | by .req. For example: | |
b99bd4ef | 2455 | |
c19d1205 ZW |
2456 | my_alias .req r11 |
2457 | .unreq my_alias */ | |
b99bd4ef NC |
2458 | |
2459 | static void | |
c19d1205 | 2460 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2461 | { |
c19d1205 ZW |
2462 | char * name; |
2463 | char saved_char; | |
b99bd4ef | 2464 | |
c19d1205 ZW |
2465 | name = input_line_pointer; |
2466 | ||
2467 | while (*input_line_pointer != 0 | |
2468 | && *input_line_pointer != ' ' | |
2469 | && *input_line_pointer != '\n') | |
2470 | ++input_line_pointer; | |
2471 | ||
2472 | saved_char = *input_line_pointer; | |
2473 | *input_line_pointer = 0; | |
2474 | ||
2475 | if (!*name) | |
2476 | as_bad (_("invalid syntax for .unreq directive")); | |
2477 | else | |
2478 | { | |
21d799b5 | 2479 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2480 | name); |
c19d1205 ZW |
2481 | |
2482 | if (!reg) | |
2483 | as_bad (_("unknown register alias '%s'"), name); | |
2484 | else if (reg->builtin) | |
a1727c1a | 2485 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2486 | name); |
2487 | else | |
2488 | { | |
d929913e NC |
2489 | char * p; |
2490 | char * nbuf; | |
2491 | ||
db0bc284 | 2492 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2493 | free ((char *) reg->name); |
477330fc RM |
2494 | if (reg->neon) |
2495 | free (reg->neon); | |
c19d1205 | 2496 | free (reg); |
d929913e NC |
2497 | |
2498 | /* Also locate the all upper case and all lower case versions. | |
2499 | Do not complain if we cannot find one or the other as it | |
2500 | was probably deleted above. */ | |
5f4273c7 | 2501 | |
d929913e NC |
2502 | nbuf = strdup (name); |
2503 | for (p = nbuf; *p; p++) | |
2504 | *p = TOUPPER (*p); | |
21d799b5 | 2505 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2506 | if (reg) |
2507 | { | |
db0bc284 | 2508 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2509 | free ((char *) reg->name); |
2510 | if (reg->neon) | |
2511 | free (reg->neon); | |
2512 | free (reg); | |
2513 | } | |
2514 | ||
2515 | for (p = nbuf; *p; p++) | |
2516 | *p = TOLOWER (*p); | |
21d799b5 | 2517 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2518 | if (reg) |
2519 | { | |
db0bc284 | 2520 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2521 | free ((char *) reg->name); |
2522 | if (reg->neon) | |
2523 | free (reg->neon); | |
2524 | free (reg); | |
2525 | } | |
2526 | ||
2527 | free (nbuf); | |
c19d1205 ZW |
2528 | } |
2529 | } | |
b99bd4ef | 2530 | |
c19d1205 | 2531 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2532 | demand_empty_rest_of_line (); |
2533 | } | |
2534 | ||
c19d1205 ZW |
2535 | /* Directives: Instruction set selection. */ |
2536 | ||
2537 | #ifdef OBJ_ELF | |
2538 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2539 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2540 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2541 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2542 | ||
cd000bff DJ |
2543 | /* Create a new mapping symbol for the transition to STATE. */ |
2544 | ||
2545 | static void | |
2546 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2547 | { |
a737bd4d | 2548 | symbolS * symbolP; |
c19d1205 ZW |
2549 | const char * symname; |
2550 | int type; | |
b99bd4ef | 2551 | |
c19d1205 | 2552 | switch (state) |
b99bd4ef | 2553 | { |
c19d1205 ZW |
2554 | case MAP_DATA: |
2555 | symname = "$d"; | |
2556 | type = BSF_NO_FLAGS; | |
2557 | break; | |
2558 | case MAP_ARM: | |
2559 | symname = "$a"; | |
2560 | type = BSF_NO_FLAGS; | |
2561 | break; | |
2562 | case MAP_THUMB: | |
2563 | symname = "$t"; | |
2564 | type = BSF_NO_FLAGS; | |
2565 | break; | |
c19d1205 ZW |
2566 | default: |
2567 | abort (); | |
2568 | } | |
2569 | ||
cd000bff | 2570 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2571 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2572 | ||
2573 | switch (state) | |
2574 | { | |
2575 | case MAP_ARM: | |
2576 | THUMB_SET_FUNC (symbolP, 0); | |
2577 | ARM_SET_THUMB (symbolP, 0); | |
2578 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2579 | break; | |
2580 | ||
2581 | case MAP_THUMB: | |
2582 | THUMB_SET_FUNC (symbolP, 1); | |
2583 | ARM_SET_THUMB (symbolP, 1); | |
2584 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2585 | break; | |
2586 | ||
2587 | case MAP_DATA: | |
2588 | default: | |
cd000bff DJ |
2589 | break; |
2590 | } | |
2591 | ||
2592 | /* Save the mapping symbols for future reference. Also check that | |
2593 | we do not place two mapping symbols at the same offset within a | |
2594 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2595 | check_mapping_symbols. |
2596 | ||
2597 | If .fill or other data filling directive generates zero sized data, | |
2598 | the mapping symbol for the following code will have the same value | |
2599 | as the one generated for the data filling directive. In this case, | |
2600 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2601 | if (value == 0) |
2602 | { | |
2de7820f JZ |
2603 | if (frag->tc_frag_data.first_map != NULL) |
2604 | { | |
2605 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2606 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2607 | } | |
cd000bff DJ |
2608 | frag->tc_frag_data.first_map = symbolP; |
2609 | } | |
2610 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2611 | { |
2612 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2613 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2614 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2615 | } | |
cd000bff DJ |
2616 | frag->tc_frag_data.last_map = symbolP; |
2617 | } | |
2618 | ||
2619 | /* We must sometimes convert a region marked as code to data during | |
2620 | code alignment, if an odd number of bytes have to be padded. The | |
2621 | code mapping symbol is pushed to an aligned address. */ | |
2622 | ||
2623 | static void | |
2624 | insert_data_mapping_symbol (enum mstate state, | |
2625 | valueT value, fragS *frag, offsetT bytes) | |
2626 | { | |
2627 | /* If there was already a mapping symbol, remove it. */ | |
2628 | if (frag->tc_frag_data.last_map != NULL | |
2629 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2630 | { | |
2631 | symbolS *symp = frag->tc_frag_data.last_map; | |
2632 | ||
2633 | if (value == 0) | |
2634 | { | |
2635 | know (frag->tc_frag_data.first_map == symp); | |
2636 | frag->tc_frag_data.first_map = NULL; | |
2637 | } | |
2638 | frag->tc_frag_data.last_map = NULL; | |
2639 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2640 | } |
cd000bff DJ |
2641 | |
2642 | make_mapping_symbol (MAP_DATA, value, frag); | |
2643 | make_mapping_symbol (state, value + bytes, frag); | |
2644 | } | |
2645 | ||
2646 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2647 | ||
2648 | /* Set the mapping state to STATE. Only call this when about to | |
2649 | emit some STATE bytes to the file. */ | |
2650 | ||
4e9aaefb | 2651 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
cd000bff DJ |
2652 | void |
2653 | mapping_state (enum mstate state) | |
2654 | { | |
940b5ce0 DJ |
2655 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2656 | ||
cd000bff DJ |
2657 | if (mapstate == state) |
2658 | /* The mapping symbol has already been emitted. | |
2659 | There is nothing else to do. */ | |
2660 | return; | |
49c62a33 NC |
2661 | |
2662 | if (state == MAP_ARM || state == MAP_THUMB) | |
2663 | /* PR gas/12931 | |
2664 | All ARM instructions require 4-byte alignment. | |
2665 | (Almost) all Thumb instructions require 2-byte alignment. | |
2666 | ||
2667 | When emitting instructions into any section, mark the section | |
2668 | appropriately. | |
2669 | ||
2670 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2671 | but themselves require 2-byte alignment; this applies to some | |
2672 | PC- relative forms. However, these cases will invovle implicit | |
2673 | literal pool generation or an explicit .align >=2, both of | |
2674 | which will cause the section to me marked with sufficient | |
2675 | alignment. Thus, we don't handle those cases here. */ | |
2676 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2677 | ||
2678 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
4e9aaefb | 2679 | /* This case will be evaluated later. */ |
cd000bff | 2680 | return; |
cd000bff DJ |
2681 | |
2682 | mapping_state_2 (state, 0); | |
cd000bff DJ |
2683 | } |
2684 | ||
2685 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2686 | allocated. Put the mapping symbol that far back. */ | |
2687 | ||
2688 | static void | |
2689 | mapping_state_2 (enum mstate state, int max_chars) | |
2690 | { | |
940b5ce0 DJ |
2691 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2692 | ||
2693 | if (!SEG_NORMAL (now_seg)) | |
2694 | return; | |
2695 | ||
cd000bff DJ |
2696 | if (mapstate == state) |
2697 | /* The mapping symbol has already been emitted. | |
2698 | There is nothing else to do. */ | |
2699 | return; | |
2700 | ||
4e9aaefb SA |
2701 | if (TRANSITION (MAP_UNDEFINED, MAP_ARM) |
2702 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2703 | { | |
2704 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2705 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2706 | ||
2707 | if (add_symbol) | |
2708 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2709 | } | |
2710 | ||
cd000bff DJ |
2711 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2712 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 | 2713 | } |
4e9aaefb | 2714 | #undef TRANSITION |
c19d1205 | 2715 | #else |
d3106081 NS |
2716 | #define mapping_state(x) ((void)0) |
2717 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2718 | #endif |
2719 | ||
2720 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2721 | ||
4343666d | 2722 | #ifdef OBJ_COFF |
c19d1205 ZW |
2723 | static symbolS * |
2724 | find_real_start (symbolS * symbolP) | |
2725 | { | |
2726 | char * real_start; | |
2727 | const char * name = S_GET_NAME (symbolP); | |
2728 | symbolS * new_target; | |
2729 | ||
2730 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2731 | #define STUB_NAME ".real_start_of" | |
2732 | ||
2733 | if (name == NULL) | |
2734 | abort (); | |
2735 | ||
37f6032b ZW |
2736 | /* The compiler may generate BL instructions to local labels because |
2737 | it needs to perform a branch to a far away location. These labels | |
2738 | do not have a corresponding ".real_start_of" label. We check | |
2739 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2740 | the ".real_start_of" convention for nonlocal branches. */ | |
2741 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2742 | return symbolP; |
2743 | ||
37f6032b | 2744 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2745 | new_target = symbol_find (real_start); |
2746 | ||
2747 | if (new_target == NULL) | |
2748 | { | |
bd3ba5d1 | 2749 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2750 | new_target = symbolP; |
2751 | } | |
2752 | ||
c19d1205 ZW |
2753 | return new_target; |
2754 | } | |
4343666d | 2755 | #endif |
c19d1205 ZW |
2756 | |
2757 | static void | |
2758 | opcode_select (int width) | |
2759 | { | |
2760 | switch (width) | |
2761 | { | |
2762 | case 16: | |
2763 | if (! thumb_mode) | |
2764 | { | |
e74cfd16 | 2765 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2766 | as_bad (_("selected processor does not support THUMB opcodes")); |
2767 | ||
2768 | thumb_mode = 1; | |
2769 | /* No need to force the alignment, since we will have been | |
2770 | coming from ARM mode, which is word-aligned. */ | |
2771 | record_alignment (now_seg, 1); | |
2772 | } | |
c19d1205 ZW |
2773 | break; |
2774 | ||
2775 | case 32: | |
2776 | if (thumb_mode) | |
2777 | { | |
e74cfd16 | 2778 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2779 | as_bad (_("selected processor does not support ARM opcodes")); |
2780 | ||
2781 | thumb_mode = 0; | |
2782 | ||
2783 | if (!need_pass_2) | |
2784 | frag_align (2, 0, 0); | |
2785 | ||
2786 | record_alignment (now_seg, 1); | |
2787 | } | |
c19d1205 ZW |
2788 | break; |
2789 | ||
2790 | default: | |
2791 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2792 | } | |
2793 | } | |
2794 | ||
2795 | static void | |
2796 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2797 | { | |
2798 | opcode_select (32); | |
2799 | demand_empty_rest_of_line (); | |
2800 | } | |
2801 | ||
2802 | static void | |
2803 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2804 | { | |
2805 | opcode_select (16); | |
2806 | demand_empty_rest_of_line (); | |
2807 | } | |
2808 | ||
2809 | static void | |
2810 | s_code (int unused ATTRIBUTE_UNUSED) | |
2811 | { | |
2812 | int temp; | |
2813 | ||
2814 | temp = get_absolute_expression (); | |
2815 | switch (temp) | |
2816 | { | |
2817 | case 16: | |
2818 | case 32: | |
2819 | opcode_select (temp); | |
2820 | break; | |
2821 | ||
2822 | default: | |
2823 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2824 | } | |
2825 | } | |
2826 | ||
2827 | static void | |
2828 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2829 | { | |
2830 | /* If we are not already in thumb mode go into it, EVEN if | |
2831 | the target processor does not support thumb instructions. | |
2832 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2833 | to compile interworking support functions even if the | |
2834 | target processor should not support interworking. */ | |
2835 | if (! thumb_mode) | |
2836 | { | |
2837 | thumb_mode = 2; | |
2838 | record_alignment (now_seg, 1); | |
2839 | } | |
2840 | ||
2841 | demand_empty_rest_of_line (); | |
2842 | } | |
2843 | ||
2844 | static void | |
2845 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2846 | { | |
2847 | s_thumb (0); | |
2848 | ||
2849 | /* The following label is the name/address of the start of a Thumb function. | |
2850 | We need to know this for the interworking support. */ | |
2851 | label_is_thumb_function_name = TRUE; | |
2852 | } | |
2853 | ||
2854 | /* Perform a .set directive, but also mark the alias as | |
2855 | being a thumb function. */ | |
2856 | ||
2857 | static void | |
2858 | s_thumb_set (int equiv) | |
2859 | { | |
2860 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2861 | We cannot just call that code as we need to get at the symbol that | |
2862 | is created. */ | |
2863 | char * name; | |
2864 | char delim; | |
2865 | char * end_name; | |
2866 | symbolS * symbolP; | |
2867 | ||
2868 | /* Especial apologies for the random logic: | |
2869 | This just grew, and could be parsed much more simply! | |
2870 | Dean - in haste. */ | |
2871 | name = input_line_pointer; | |
2872 | delim = get_symbol_end (); | |
2873 | end_name = input_line_pointer; | |
2874 | *end_name = delim; | |
2875 | ||
2876 | if (*input_line_pointer != ',') | |
2877 | { | |
2878 | *end_name = 0; | |
2879 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2880 | *end_name = delim; |
2881 | ignore_rest_of_line (); | |
2882 | return; | |
2883 | } | |
2884 | ||
2885 | input_line_pointer++; | |
2886 | *end_name = 0; | |
2887 | ||
2888 | if (name[0] == '.' && name[1] == '\0') | |
2889 | { | |
2890 | /* XXX - this should not happen to .thumb_set. */ | |
2891 | abort (); | |
2892 | } | |
2893 | ||
2894 | if ((symbolP = symbol_find (name)) == NULL | |
2895 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2896 | { | |
2897 | #ifndef NO_LISTING | |
2898 | /* When doing symbol listings, play games with dummy fragments living | |
2899 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2900 | for this symbol. */ |
b99bd4ef NC |
2901 | if (listing & LISTING_SYMBOLS) |
2902 | { | |
2903 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2904 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2905 | |
2906 | memset (dummy_frag, 0, sizeof (fragS)); | |
2907 | dummy_frag->fr_type = rs_fill; | |
2908 | dummy_frag->line = listing_tail; | |
2909 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2910 | dummy_frag->fr_symbol = symbolP; | |
2911 | } | |
2912 | else | |
2913 | #endif | |
2914 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2915 | ||
2916 | #ifdef OBJ_COFF | |
2917 | /* "set" symbols are local unless otherwise specified. */ | |
2918 | SF_SET_LOCAL (symbolP); | |
2919 | #endif /* OBJ_COFF */ | |
2920 | } /* Make a new symbol. */ | |
2921 | ||
2922 | symbol_table_insert (symbolP); | |
2923 | ||
2924 | * end_name = delim; | |
2925 | ||
2926 | if (equiv | |
2927 | && S_IS_DEFINED (symbolP) | |
2928 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2929 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2930 | ||
2931 | pseudo_set (symbolP); | |
2932 | ||
2933 | demand_empty_rest_of_line (); | |
2934 | ||
c19d1205 | 2935 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2936 | |
2937 | THUMB_SET_FUNC (symbolP, 1); | |
2938 | ARM_SET_THUMB (symbolP, 1); | |
2939 | #if defined OBJ_ELF || defined OBJ_COFF | |
2940 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2941 | #endif | |
2942 | } | |
2943 | ||
c19d1205 | 2944 | /* Directives: Mode selection. */ |
b99bd4ef | 2945 | |
c19d1205 ZW |
2946 | /* .syntax [unified|divided] - choose the new unified syntax |
2947 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2948 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2949 | static void |
c19d1205 | 2950 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2951 | { |
c19d1205 ZW |
2952 | char *name, delim; |
2953 | ||
2954 | name = input_line_pointer; | |
2955 | delim = get_symbol_end (); | |
2956 | ||
2957 | if (!strcasecmp (name, "unified")) | |
2958 | unified_syntax = TRUE; | |
2959 | else if (!strcasecmp (name, "divided")) | |
2960 | unified_syntax = FALSE; | |
2961 | else | |
2962 | { | |
2963 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2964 | return; | |
2965 | } | |
2966 | *input_line_pointer = delim; | |
b99bd4ef NC |
2967 | demand_empty_rest_of_line (); |
2968 | } | |
2969 | ||
c19d1205 ZW |
2970 | /* Directives: sectioning and alignment. */ |
2971 | ||
2972 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2973 | ||
b99bd4ef | 2974 | static void |
c19d1205 | 2975 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2976 | { |
a737bd4d | 2977 | int temp; |
dce323d1 | 2978 | bfd_boolean fill_p; |
c19d1205 ZW |
2979 | long temp_fill; |
2980 | long max_alignment = 15; | |
b99bd4ef NC |
2981 | |
2982 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2983 | if (temp > max_alignment) |
2984 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2985 | else if (temp < 0) | |
b99bd4ef | 2986 | { |
c19d1205 ZW |
2987 | as_bad (_("alignment negative. 0 assumed.")); |
2988 | temp = 0; | |
2989 | } | |
b99bd4ef | 2990 | |
c19d1205 ZW |
2991 | if (*input_line_pointer == ',') |
2992 | { | |
2993 | input_line_pointer++; | |
2994 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2995 | fill_p = TRUE; |
b99bd4ef | 2996 | } |
c19d1205 | 2997 | else |
dce323d1 PB |
2998 | { |
2999 | fill_p = FALSE; | |
3000 | temp_fill = 0; | |
3001 | } | |
b99bd4ef | 3002 | |
c19d1205 ZW |
3003 | if (!temp) |
3004 | temp = 2; | |
b99bd4ef | 3005 | |
c19d1205 ZW |
3006 | /* Only make a frag if we HAVE to. */ |
3007 | if (temp && !need_pass_2) | |
dce323d1 PB |
3008 | { |
3009 | if (!fill_p && subseg_text_p (now_seg)) | |
3010 | frag_align_code (temp, 0); | |
3011 | else | |
3012 | frag_align (temp, (int) temp_fill, 0); | |
3013 | } | |
c19d1205 ZW |
3014 | demand_empty_rest_of_line (); |
3015 | ||
3016 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
3017 | } |
3018 | ||
c19d1205 ZW |
3019 | static void |
3020 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 3021 | { |
c19d1205 ZW |
3022 | /* We don't support putting frags in the BSS segment, we fake it by |
3023 | marking in_bss, then looking at s_skip for clues. */ | |
3024 | subseg_set (bss_section, 0); | |
3025 | demand_empty_rest_of_line (); | |
cd000bff DJ |
3026 | |
3027 | #ifdef md_elf_section_change_hook | |
3028 | md_elf_section_change_hook (); | |
3029 | #endif | |
c19d1205 | 3030 | } |
b99bd4ef | 3031 | |
c19d1205 ZW |
3032 | static void |
3033 | s_even (int ignore ATTRIBUTE_UNUSED) | |
3034 | { | |
3035 | /* Never make frag if expect extra pass. */ | |
3036 | if (!need_pass_2) | |
3037 | frag_align (1, 0, 0); | |
b99bd4ef | 3038 | |
c19d1205 | 3039 | record_alignment (now_seg, 1); |
b99bd4ef | 3040 | |
c19d1205 | 3041 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3042 | } |
3043 | ||
2e6976a8 DG |
3044 | /* Directives: CodeComposer Studio. */ |
3045 | ||
3046 | /* .ref (for CodeComposer Studio syntax only). */ | |
3047 | static void | |
3048 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3049 | { | |
3050 | if (codecomposer_syntax) | |
3051 | ignore_rest_of_line (); | |
3052 | else | |
3053 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3054 | } | |
3055 | ||
3056 | /* If name is not NULL, then it is used for marking the beginning of a | |
3057 | function, wherease if it is NULL then it means the function end. */ | |
3058 | static void | |
3059 | asmfunc_debug (const char * name) | |
3060 | { | |
3061 | static const char * last_name = NULL; | |
3062 | ||
3063 | if (name != NULL) | |
3064 | { | |
3065 | gas_assert (last_name == NULL); | |
3066 | last_name = name; | |
3067 | ||
3068 | if (debug_type == DEBUG_STABS) | |
3069 | stabs_generate_asm_func (name, name); | |
3070 | } | |
3071 | else | |
3072 | { | |
3073 | gas_assert (last_name != NULL); | |
3074 | ||
3075 | if (debug_type == DEBUG_STABS) | |
3076 | stabs_generate_asm_endfunc (last_name, last_name); | |
3077 | ||
3078 | last_name = NULL; | |
3079 | } | |
3080 | } | |
3081 | ||
3082 | static void | |
3083 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3084 | { | |
3085 | if (codecomposer_syntax) | |
3086 | { | |
3087 | switch (asmfunc_state) | |
3088 | { | |
3089 | case OUTSIDE_ASMFUNC: | |
3090 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3091 | break; | |
3092 | ||
3093 | case WAITING_ASMFUNC_NAME: | |
3094 | as_bad (_(".asmfunc repeated.")); | |
3095 | break; | |
3096 | ||
3097 | case WAITING_ENDASMFUNC: | |
3098 | as_bad (_(".asmfunc without function.")); | |
3099 | break; | |
3100 | } | |
3101 | demand_empty_rest_of_line (); | |
3102 | } | |
3103 | else | |
3104 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3105 | } | |
3106 | ||
3107 | static void | |
3108 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3109 | { | |
3110 | if (codecomposer_syntax) | |
3111 | { | |
3112 | switch (asmfunc_state) | |
3113 | { | |
3114 | case OUTSIDE_ASMFUNC: | |
3115 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3116 | break; | |
3117 | ||
3118 | case WAITING_ASMFUNC_NAME: | |
3119 | as_bad (_(".endasmfunc without function.")); | |
3120 | break; | |
3121 | ||
3122 | case WAITING_ENDASMFUNC: | |
3123 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3124 | asmfunc_debug (NULL); | |
3125 | break; | |
3126 | } | |
3127 | demand_empty_rest_of_line (); | |
3128 | } | |
3129 | else | |
3130 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3131 | } | |
3132 | ||
3133 | static void | |
3134 | s_ccs_def (int name) | |
3135 | { | |
3136 | if (codecomposer_syntax) | |
3137 | s_globl (name); | |
3138 | else | |
3139 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3140 | } | |
3141 | ||
c19d1205 | 3142 | /* Directives: Literal pools. */ |
a737bd4d | 3143 | |
c19d1205 ZW |
3144 | static literal_pool * |
3145 | find_literal_pool (void) | |
a737bd4d | 3146 | { |
c19d1205 | 3147 | literal_pool * pool; |
a737bd4d | 3148 | |
c19d1205 | 3149 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3150 | { |
c19d1205 ZW |
3151 | if (pool->section == now_seg |
3152 | && pool->sub_section == now_subseg) | |
3153 | break; | |
a737bd4d NC |
3154 | } |
3155 | ||
c19d1205 | 3156 | return pool; |
a737bd4d NC |
3157 | } |
3158 | ||
c19d1205 ZW |
3159 | static literal_pool * |
3160 | find_or_make_literal_pool (void) | |
a737bd4d | 3161 | { |
c19d1205 ZW |
3162 | /* Next literal pool ID number. */ |
3163 | static unsigned int latest_pool_num = 1; | |
3164 | literal_pool * pool; | |
a737bd4d | 3165 | |
c19d1205 | 3166 | pool = find_literal_pool (); |
a737bd4d | 3167 | |
c19d1205 | 3168 | if (pool == NULL) |
a737bd4d | 3169 | { |
c19d1205 | 3170 | /* Create a new pool. */ |
21d799b5 | 3171 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3172 | if (! pool) |
3173 | return NULL; | |
a737bd4d | 3174 | |
c19d1205 ZW |
3175 | pool->next_free_entry = 0; |
3176 | pool->section = now_seg; | |
3177 | pool->sub_section = now_subseg; | |
3178 | pool->next = list_of_pools; | |
3179 | pool->symbol = NULL; | |
8335d6aa | 3180 | pool->alignment = 2; |
c19d1205 ZW |
3181 | |
3182 | /* Add it to the list. */ | |
3183 | list_of_pools = pool; | |
a737bd4d | 3184 | } |
a737bd4d | 3185 | |
c19d1205 ZW |
3186 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3187 | if (pool->symbol == NULL) | |
a737bd4d | 3188 | { |
c19d1205 ZW |
3189 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3190 | (valueT) 0, &zero_address_frag); | |
3191 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3192 | } |
3193 | ||
c19d1205 ZW |
3194 | /* Done. */ |
3195 | return pool; | |
a737bd4d NC |
3196 | } |
3197 | ||
c19d1205 | 3198 | /* Add the literal in the global 'inst' |
5f4273c7 | 3199 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3200 | |
3201 | static int | |
8335d6aa | 3202 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3203 | { |
8335d6aa JW |
3204 | #define PADDING_SLOT 0x1 |
3205 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3206 | literal_pool * pool; |
8335d6aa JW |
3207 | unsigned int entry, pool_size = 0; |
3208 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3209 | unsigned imm1 = 0; |
8335d6aa JW |
3210 | unsigned imm2 = 0; |
3211 | ||
3212 | if (nbytes == 8) | |
3213 | { | |
3214 | imm1 = inst.operands[1].imm; | |
3215 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
3216 | : inst.reloc.exp.X_unsigned ? 0 | |
2569ceb0 | 3217 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3218 | if (target_big_endian) |
3219 | { | |
3220 | imm1 = imm2; | |
3221 | imm2 = inst.operands[1].imm; | |
3222 | } | |
3223 | } | |
b99bd4ef | 3224 | |
c19d1205 ZW |
3225 | pool = find_or_make_literal_pool (); |
3226 | ||
3227 | /* Check if this literal value is already in the pool. */ | |
3228 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3229 | { |
8335d6aa JW |
3230 | if (nbytes == 4) |
3231 | { | |
3232 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3233 | && (inst.reloc.exp.X_op == O_constant) | |
3234 | && (pool->literals[entry].X_add_number | |
3235 | == inst.reloc.exp.X_add_number) | |
3236 | && (pool->literals[entry].X_md == nbytes) | |
3237 | && (pool->literals[entry].X_unsigned | |
3238 | == inst.reloc.exp.X_unsigned)) | |
3239 | break; | |
3240 | ||
3241 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3242 | && (inst.reloc.exp.X_op == O_symbol) | |
3243 | && (pool->literals[entry].X_add_number | |
3244 | == inst.reloc.exp.X_add_number) | |
3245 | && (pool->literals[entry].X_add_symbol | |
3246 | == inst.reloc.exp.X_add_symbol) | |
3247 | && (pool->literals[entry].X_op_symbol | |
3248 | == inst.reloc.exp.X_op_symbol) | |
3249 | && (pool->literals[entry].X_md == nbytes)) | |
3250 | break; | |
3251 | } | |
3252 | else if ((nbytes == 8) | |
3253 | && !(pool_size & 0x7) | |
3254 | && ((entry + 1) != pool->next_free_entry) | |
3255 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3256 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa JW |
3257 | && (pool->literals[entry].X_unsigned |
3258 | == inst.reloc.exp.X_unsigned) | |
3259 | && (pool->literals[entry + 1].X_op == O_constant) | |
19f2f6a9 | 3260 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa JW |
3261 | && (pool->literals[entry + 1].X_unsigned |
3262 | == inst.reloc.exp.X_unsigned)) | |
c19d1205 ZW |
3263 | break; |
3264 | ||
8335d6aa JW |
3265 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3266 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3267 | break; |
8335d6aa JW |
3268 | |
3269 | pool_size += 4; | |
b99bd4ef NC |
3270 | } |
3271 | ||
c19d1205 ZW |
3272 | /* Do we need to create a new entry? */ |
3273 | if (entry == pool->next_free_entry) | |
3274 | { | |
3275 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3276 | { | |
3277 | inst.error = _("literal pool overflow"); | |
3278 | return FAIL; | |
3279 | } | |
3280 | ||
8335d6aa JW |
3281 | if (nbytes == 8) |
3282 | { | |
3283 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3284 | and split it into two 4-byte entries, because on 32-bit | |
3285 | host, 8-byte constants are treated as big num, thus | |
3286 | saved in "generic_bignum" which will be overwritten | |
3287 | by later assignments. | |
3288 | ||
3289 | We also need to make sure there is enough space for | |
3290 | the split. | |
3291 | ||
3292 | We also check to make sure the literal operand is a | |
3293 | constant number. */ | |
19f2f6a9 JW |
3294 | if (!(inst.reloc.exp.X_op == O_constant |
3295 | || inst.reloc.exp.X_op == O_big)) | |
8335d6aa JW |
3296 | { |
3297 | inst.error = _("invalid type for literal pool"); | |
3298 | return FAIL; | |
3299 | } | |
3300 | else if (pool_size & 0x7) | |
3301 | { | |
3302 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3303 | { | |
3304 | inst.error = _("literal pool overflow"); | |
3305 | return FAIL; | |
3306 | } | |
3307 | ||
3308 | pool->literals[entry] = inst.reloc.exp; | |
3309 | pool->literals[entry].X_add_number = 0; | |
3310 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3311 | pool->next_free_entry += 1; | |
3312 | pool_size += 4; | |
3313 | } | |
3314 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3315 | { | |
3316 | inst.error = _("literal pool overflow"); | |
3317 | return FAIL; | |
3318 | } | |
3319 | ||
3320 | pool->literals[entry] = inst.reloc.exp; | |
3321 | pool->literals[entry].X_op = O_constant; | |
3322 | pool->literals[entry].X_add_number = imm1; | |
3323 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3324 | pool->literals[entry++].X_md = 4; | |
3325 | pool->literals[entry] = inst.reloc.exp; | |
3326 | pool->literals[entry].X_op = O_constant; | |
3327 | pool->literals[entry].X_add_number = imm2; | |
3328 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3329 | pool->literals[entry].X_md = 4; | |
3330 | pool->alignment = 3; | |
3331 | pool->next_free_entry += 1; | |
3332 | } | |
3333 | else | |
3334 | { | |
3335 | pool->literals[entry] = inst.reloc.exp; | |
3336 | pool->literals[entry].X_md = 4; | |
3337 | } | |
3338 | ||
a8040cf2 NC |
3339 | #ifdef OBJ_ELF |
3340 | /* PR ld/12974: Record the location of the first source line to reference | |
3341 | this entry in the literal pool. If it turns out during linking that the | |
3342 | symbol does not exist we will be able to give an accurate line number for | |
3343 | the (first use of the) missing reference. */ | |
3344 | if (debug_type == DEBUG_DWARF2) | |
3345 | dwarf2_where (pool->locs + entry); | |
3346 | #endif | |
c19d1205 ZW |
3347 | pool->next_free_entry += 1; |
3348 | } | |
8335d6aa JW |
3349 | else if (padding_slot_p) |
3350 | { | |
3351 | pool->literals[entry] = inst.reloc.exp; | |
3352 | pool->literals[entry].X_md = nbytes; | |
3353 | } | |
b99bd4ef | 3354 | |
c19d1205 | 3355 | inst.reloc.exp.X_op = O_symbol; |
8335d6aa | 3356 | inst.reloc.exp.X_add_number = pool_size; |
c19d1205 | 3357 | inst.reloc.exp.X_add_symbol = pool->symbol; |
b99bd4ef | 3358 | |
c19d1205 | 3359 | return SUCCESS; |
b99bd4ef NC |
3360 | } |
3361 | ||
2e6976a8 DG |
3362 | bfd_boolean |
3363 | tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest) | |
3364 | { | |
3365 | bfd_boolean ret = TRUE; | |
3366 | ||
3367 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3368 | { | |
3369 | const char *label = rest; | |
3370 | ||
3371 | while (!is_end_of_line[(int) label[-1]]) | |
3372 | --label; | |
3373 | ||
3374 | if (*label == '.') | |
3375 | { | |
3376 | as_bad (_("Invalid label '%s'"), label); | |
3377 | ret = FALSE; | |
3378 | } | |
3379 | ||
3380 | asmfunc_debug (label); | |
3381 | ||
3382 | asmfunc_state = WAITING_ENDASMFUNC; | |
3383 | } | |
3384 | ||
3385 | return ret; | |
3386 | } | |
3387 | ||
c19d1205 ZW |
3388 | /* Can't use symbol_new here, so have to create a symbol and then at |
3389 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3390 | |
c19d1205 ZW |
3391 | static void |
3392 | symbol_locate (symbolS * symbolP, | |
3393 | const char * name, /* It is copied, the caller can modify. */ | |
3394 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3395 | valueT valu, /* Symbol value. */ | |
3396 | fragS * frag) /* Associated fragment. */ | |
3397 | { | |
e57e6ddc | 3398 | size_t name_length; |
c19d1205 | 3399 | char * preserved_copy_of_name; |
e16bb312 | 3400 | |
c19d1205 ZW |
3401 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3402 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3403 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3404 | |
c19d1205 ZW |
3405 | #ifdef tc_canonicalize_symbol_name |
3406 | preserved_copy_of_name = | |
3407 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3408 | #endif | |
b99bd4ef | 3409 | |
c19d1205 | 3410 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3411 | |
c19d1205 ZW |
3412 | S_SET_SEGMENT (symbolP, segment); |
3413 | S_SET_VALUE (symbolP, valu); | |
3414 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3415 | |
c19d1205 | 3416 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3417 | |
c19d1205 ZW |
3418 | /* Link to end of symbol chain. */ |
3419 | { | |
3420 | extern int symbol_table_frozen; | |
b99bd4ef | 3421 | |
c19d1205 ZW |
3422 | if (symbol_table_frozen) |
3423 | abort (); | |
3424 | } | |
b99bd4ef | 3425 | |
c19d1205 | 3426 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3427 | |
c19d1205 | 3428 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3429 | |
c19d1205 ZW |
3430 | #ifdef tc_symbol_new_hook |
3431 | tc_symbol_new_hook (symbolP); | |
3432 | #endif | |
3433 | ||
3434 | #ifdef DEBUG_SYMS | |
3435 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3436 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3437 | } |
3438 | ||
c19d1205 ZW |
3439 | static void |
3440 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3441 | { |
c19d1205 ZW |
3442 | unsigned int entry; |
3443 | literal_pool * pool; | |
3444 | char sym_name[20]; | |
b99bd4ef | 3445 | |
c19d1205 ZW |
3446 | pool = find_literal_pool (); |
3447 | if (pool == NULL | |
3448 | || pool->symbol == NULL | |
3449 | || pool->next_free_entry == 0) | |
3450 | return; | |
b99bd4ef | 3451 | |
c19d1205 ZW |
3452 | /* Align pool as you have word accesses. |
3453 | Only make a frag if we have to. */ | |
3454 | if (!need_pass_2) | |
8335d6aa | 3455 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3456 | |
c19d1205 | 3457 | record_alignment (now_seg, 2); |
b99bd4ef | 3458 | |
aaca88ef | 3459 | #ifdef OBJ_ELF |
47fc6e36 WN |
3460 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3461 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3462 | #endif |
c19d1205 | 3463 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3464 | |
c19d1205 ZW |
3465 | symbol_locate (pool->symbol, sym_name, now_seg, |
3466 | (valueT) frag_now_fix (), frag_now); | |
3467 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3468 | |
c19d1205 | 3469 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3470 | |
c19d1205 ZW |
3471 | #if defined OBJ_COFF || defined OBJ_ELF |
3472 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3473 | #endif | |
6c43fab6 | 3474 | |
c19d1205 | 3475 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3476 | { |
3477 | #ifdef OBJ_ELF | |
3478 | if (debug_type == DEBUG_DWARF2) | |
3479 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3480 | #endif | |
3481 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3482 | emit_expr (&(pool->literals[entry]), |
3483 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3484 | } |
b99bd4ef | 3485 | |
c19d1205 ZW |
3486 | /* Mark the pool as empty. */ |
3487 | pool->next_free_entry = 0; | |
3488 | pool->symbol = NULL; | |
b99bd4ef NC |
3489 | } |
3490 | ||
c19d1205 ZW |
3491 | #ifdef OBJ_ELF |
3492 | /* Forward declarations for functions below, in the MD interface | |
3493 | section. */ | |
3494 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3495 | static valueT create_unwind_entry (int); | |
3496 | static void start_unwind_section (const segT, int); | |
3497 | static void add_unwind_opcode (valueT, int); | |
3498 | static void flush_pending_unwind (void); | |
b99bd4ef | 3499 | |
c19d1205 | 3500 | /* Directives: Data. */ |
b99bd4ef | 3501 | |
c19d1205 ZW |
3502 | static void |
3503 | s_arm_elf_cons (int nbytes) | |
3504 | { | |
3505 | expressionS exp; | |
b99bd4ef | 3506 | |
c19d1205 ZW |
3507 | #ifdef md_flush_pending_output |
3508 | md_flush_pending_output (); | |
3509 | #endif | |
b99bd4ef | 3510 | |
c19d1205 | 3511 | if (is_it_end_of_statement ()) |
b99bd4ef | 3512 | { |
c19d1205 ZW |
3513 | demand_empty_rest_of_line (); |
3514 | return; | |
b99bd4ef NC |
3515 | } |
3516 | ||
c19d1205 ZW |
3517 | #ifdef md_cons_align |
3518 | md_cons_align (nbytes); | |
3519 | #endif | |
b99bd4ef | 3520 | |
c19d1205 ZW |
3521 | mapping_state (MAP_DATA); |
3522 | do | |
b99bd4ef | 3523 | { |
c19d1205 ZW |
3524 | int reloc; |
3525 | char *base = input_line_pointer; | |
b99bd4ef | 3526 | |
c19d1205 | 3527 | expression (& exp); |
b99bd4ef | 3528 | |
c19d1205 ZW |
3529 | if (exp.X_op != O_symbol) |
3530 | emit_expr (&exp, (unsigned int) nbytes); | |
3531 | else | |
3532 | { | |
3533 | char *before_reloc = input_line_pointer; | |
3534 | reloc = parse_reloc (&input_line_pointer); | |
3535 | if (reloc == -1) | |
3536 | { | |
3537 | as_bad (_("unrecognized relocation suffix")); | |
3538 | ignore_rest_of_line (); | |
3539 | return; | |
3540 | } | |
3541 | else if (reloc == BFD_RELOC_UNUSED) | |
3542 | emit_expr (&exp, (unsigned int) nbytes); | |
3543 | else | |
3544 | { | |
21d799b5 | 3545 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3546 | bfd_reloc_type_lookup (stdoutput, |
3547 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3548 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3549 | |
2fc8bdac ZW |
3550 | if (reloc == BFD_RELOC_ARM_PLT32) |
3551 | { | |
3552 | as_bad (_("(plt) is only valid on branch targets")); | |
3553 | reloc = BFD_RELOC_UNUSED; | |
3554 | size = 0; | |
3555 | } | |
3556 | ||
c19d1205 | 3557 | if (size > nbytes) |
2fc8bdac | 3558 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3559 | howto->name, nbytes); |
3560 | else | |
3561 | { | |
3562 | /* We've parsed an expression stopping at O_symbol. | |
3563 | But there may be more expression left now that we | |
3564 | have parsed the relocation marker. Parse it again. | |
3565 | XXX Surely there is a cleaner way to do this. */ | |
3566 | char *p = input_line_pointer; | |
3567 | int offset; | |
21d799b5 | 3568 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3569 | memcpy (save_buf, base, input_line_pointer - base); |
3570 | memmove (base + (input_line_pointer - before_reloc), | |
3571 | base, before_reloc - base); | |
3572 | ||
3573 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3574 | expression (&exp); | |
3575 | memcpy (base, save_buf, p - base); | |
3576 | ||
3577 | offset = nbytes - size; | |
4b1a927e AM |
3578 | p = frag_more (nbytes); |
3579 | memset (p, 0, nbytes); | |
c19d1205 | 3580 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3581 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3582 | } |
3583 | } | |
3584 | } | |
b99bd4ef | 3585 | } |
c19d1205 | 3586 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3587 | |
c19d1205 ZW |
3588 | /* Put terminator back into stream. */ |
3589 | input_line_pointer --; | |
3590 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3591 | } |
3592 | ||
c921be7d NC |
3593 | /* Emit an expression containing a 32-bit thumb instruction. |
3594 | Implementation based on put_thumb32_insn. */ | |
3595 | ||
3596 | static void | |
3597 | emit_thumb32_expr (expressionS * exp) | |
3598 | { | |
3599 | expressionS exp_high = *exp; | |
3600 | ||
3601 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3602 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3603 | exp->X_add_number &= 0xffff; | |
3604 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3605 | } | |
3606 | ||
3607 | /* Guess the instruction size based on the opcode. */ | |
3608 | ||
3609 | static int | |
3610 | thumb_insn_size (int opcode) | |
3611 | { | |
3612 | if ((unsigned int) opcode < 0xe800u) | |
3613 | return 2; | |
3614 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3615 | return 4; | |
3616 | else | |
3617 | return 0; | |
3618 | } | |
3619 | ||
3620 | static bfd_boolean | |
3621 | emit_insn (expressionS *exp, int nbytes) | |
3622 | { | |
3623 | int size = 0; | |
3624 | ||
3625 | if (exp->X_op == O_constant) | |
3626 | { | |
3627 | size = nbytes; | |
3628 | ||
3629 | if (size == 0) | |
3630 | size = thumb_insn_size (exp->X_add_number); | |
3631 | ||
3632 | if (size != 0) | |
3633 | { | |
3634 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3635 | { | |
3636 | as_bad (_(".inst.n operand too big. "\ | |
3637 | "Use .inst.w instead")); | |
3638 | size = 0; | |
3639 | } | |
3640 | else | |
3641 | { | |
3642 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3643 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3644 | else | |
3645 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3646 | ||
3647 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3648 | emit_thumb32_expr (exp); | |
3649 | else | |
3650 | emit_expr (exp, (unsigned int) size); | |
3651 | ||
3652 | it_fsm_post_encode (); | |
3653 | } | |
3654 | } | |
3655 | else | |
3656 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3657 | "Use .inst.n/.inst.w instead")); | |
3658 | } | |
3659 | else | |
3660 | as_bad (_("constant expression required")); | |
3661 | ||
3662 | return (size != 0); | |
3663 | } | |
3664 | ||
3665 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3666 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3667 | ||
3668 | static void | |
3669 | s_arm_elf_inst (int nbytes) | |
3670 | { | |
3671 | if (is_it_end_of_statement ()) | |
3672 | { | |
3673 | demand_empty_rest_of_line (); | |
3674 | return; | |
3675 | } | |
3676 | ||
3677 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3678 | but will ensure not to be in DATA state. */ | |
3679 | ||
3680 | if (thumb_mode) | |
3681 | mapping_state (MAP_THUMB); | |
3682 | else | |
3683 | { | |
3684 | if (nbytes != 0) | |
3685 | { | |
3686 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3687 | ignore_rest_of_line (); | |
3688 | return; | |
3689 | } | |
3690 | ||
3691 | nbytes = 4; | |
3692 | ||
3693 | mapping_state (MAP_ARM); | |
3694 | } | |
3695 | ||
3696 | do | |
3697 | { | |
3698 | expressionS exp; | |
3699 | ||
3700 | expression (& exp); | |
3701 | ||
3702 | if (! emit_insn (& exp, nbytes)) | |
3703 | { | |
3704 | ignore_rest_of_line (); | |
3705 | return; | |
3706 | } | |
3707 | } | |
3708 | while (*input_line_pointer++ == ','); | |
3709 | ||
3710 | /* Put terminator back into stream. */ | |
3711 | input_line_pointer --; | |
3712 | demand_empty_rest_of_line (); | |
3713 | } | |
b99bd4ef | 3714 | |
c19d1205 | 3715 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3716 | |
c19d1205 ZW |
3717 | static void |
3718 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3719 | { | |
3720 | expressionS exp; | |
3721 | char *p; | |
3722 | valueT highbit; | |
b99bd4ef | 3723 | |
c19d1205 ZW |
3724 | highbit = 0; |
3725 | if (*input_line_pointer == '1') | |
3726 | highbit = 0x80000000; | |
3727 | else if (*input_line_pointer != '0') | |
3728 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3729 | |
c19d1205 ZW |
3730 | input_line_pointer++; |
3731 | if (*input_line_pointer != ',') | |
3732 | as_bad (_("missing comma")); | |
3733 | input_line_pointer++; | |
b99bd4ef | 3734 | |
c19d1205 ZW |
3735 | #ifdef md_flush_pending_output |
3736 | md_flush_pending_output (); | |
3737 | #endif | |
b99bd4ef | 3738 | |
c19d1205 ZW |
3739 | #ifdef md_cons_align |
3740 | md_cons_align (4); | |
3741 | #endif | |
b99bd4ef | 3742 | |
c19d1205 | 3743 | mapping_state (MAP_DATA); |
b99bd4ef | 3744 | |
c19d1205 | 3745 | expression (&exp); |
b99bd4ef | 3746 | |
c19d1205 ZW |
3747 | p = frag_more (4); |
3748 | md_number_to_chars (p, highbit, 4); | |
3749 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3750 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3751 | |
c19d1205 | 3752 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3753 | } |
3754 | ||
c19d1205 | 3755 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3756 | |
c19d1205 | 3757 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3758 | |
c19d1205 ZW |
3759 | static void |
3760 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3761 | { | |
3762 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3763 | if (unwind.proc_start) |
3764 | { | |
c921be7d | 3765 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3766 | return; |
3767 | } | |
3768 | ||
c19d1205 ZW |
3769 | /* Mark the start of the function. */ |
3770 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3771 | |
c19d1205 ZW |
3772 | /* Reset the rest of the unwind info. */ |
3773 | unwind.opcode_count = 0; | |
3774 | unwind.table_entry = NULL; | |
3775 | unwind.personality_routine = NULL; | |
3776 | unwind.personality_index = -1; | |
3777 | unwind.frame_size = 0; | |
3778 | unwind.fp_offset = 0; | |
fdfde340 | 3779 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3780 | unwind.fp_used = 0; |
3781 | unwind.sp_restored = 0; | |
3782 | } | |
b99bd4ef | 3783 | |
b99bd4ef | 3784 | |
c19d1205 ZW |
3785 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3786 | for the function. */ | |
b99bd4ef | 3787 | |
c19d1205 ZW |
3788 | static void |
3789 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3790 | { | |
3791 | demand_empty_rest_of_line (); | |
921e5f0a | 3792 | if (!unwind.proc_start) |
c921be7d | 3793 | as_bad (MISSING_FNSTART); |
921e5f0a | 3794 | |
c19d1205 | 3795 | if (unwind.table_entry) |
6decc662 | 3796 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3797 | |
c19d1205 ZW |
3798 | create_unwind_entry (1); |
3799 | } | |
a737bd4d | 3800 | |
c19d1205 | 3801 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3802 | |
c19d1205 ZW |
3803 | static void |
3804 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3805 | { | |
3806 | long where; | |
3807 | char *ptr; | |
3808 | valueT val; | |
940b5ce0 | 3809 | unsigned int marked_pr_dependency; |
f02232aa | 3810 | |
c19d1205 | 3811 | demand_empty_rest_of_line (); |
f02232aa | 3812 | |
921e5f0a PB |
3813 | if (!unwind.proc_start) |
3814 | { | |
c921be7d | 3815 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3816 | return; |
3817 | } | |
3818 | ||
c19d1205 ZW |
3819 | /* Add eh table entry. */ |
3820 | if (unwind.table_entry == NULL) | |
3821 | val = create_unwind_entry (0); | |
3822 | else | |
3823 | val = 0; | |
f02232aa | 3824 | |
c19d1205 ZW |
3825 | /* Add index table entry. This is two words. */ |
3826 | start_unwind_section (unwind.saved_seg, 1); | |
3827 | frag_align (2, 0, 0); | |
3828 | record_alignment (now_seg, 2); | |
b99bd4ef | 3829 | |
c19d1205 | 3830 | ptr = frag_more (8); |
5011093d | 3831 | memset (ptr, 0, 8); |
c19d1205 | 3832 | where = frag_now_fix () - 8; |
f02232aa | 3833 | |
c19d1205 ZW |
3834 | /* Self relative offset of the function start. */ |
3835 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3836 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3837 | |
c19d1205 ZW |
3838 | /* Indicate dependency on EHABI-defined personality routines to the |
3839 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3840 | marked_pr_dependency |
3841 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3842 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3843 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3844 | { | |
5f4273c7 NC |
3845 | static const char *const name[] = |
3846 | { | |
3847 | "__aeabi_unwind_cpp_pr0", | |
3848 | "__aeabi_unwind_cpp_pr1", | |
3849 | "__aeabi_unwind_cpp_pr2" | |
3850 | }; | |
c19d1205 ZW |
3851 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3852 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3853 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3854 | |= 1 << unwind.personality_index; |
c19d1205 | 3855 | } |
f02232aa | 3856 | |
c19d1205 ZW |
3857 | if (val) |
3858 | /* Inline exception table entry. */ | |
3859 | md_number_to_chars (ptr + 4, val, 4); | |
3860 | else | |
3861 | /* Self relative offset of the table entry. */ | |
3862 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3863 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3864 | |
c19d1205 ZW |
3865 | /* Restore the original section. */ |
3866 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3867 | |
3868 | unwind.proc_start = NULL; | |
c19d1205 | 3869 | } |
f02232aa | 3870 | |
f02232aa | 3871 | |
c19d1205 | 3872 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3873 | |
c19d1205 ZW |
3874 | static void |
3875 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3876 | { | |
3877 | demand_empty_rest_of_line (); | |
921e5f0a | 3878 | if (!unwind.proc_start) |
c921be7d | 3879 | as_bad (MISSING_FNSTART); |
921e5f0a | 3880 | |
c19d1205 ZW |
3881 | if (unwind.personality_routine || unwind.personality_index != -1) |
3882 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3883 | |
c19d1205 ZW |
3884 | unwind.personality_index = -2; |
3885 | } | |
b99bd4ef | 3886 | |
b99bd4ef | 3887 | |
c19d1205 | 3888 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3889 | |
c19d1205 ZW |
3890 | static void |
3891 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3892 | { | |
3893 | expressionS exp; | |
b99bd4ef | 3894 | |
921e5f0a | 3895 | if (!unwind.proc_start) |
c921be7d | 3896 | as_bad (MISSING_FNSTART); |
921e5f0a | 3897 | |
c19d1205 ZW |
3898 | if (unwind.personality_routine || unwind.personality_index != -1) |
3899 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3900 | |
c19d1205 | 3901 | expression (&exp); |
b99bd4ef | 3902 | |
c19d1205 ZW |
3903 | if (exp.X_op != O_constant |
3904 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3905 | { |
c19d1205 ZW |
3906 | as_bad (_("bad personality routine number")); |
3907 | ignore_rest_of_line (); | |
3908 | return; | |
b99bd4ef NC |
3909 | } |
3910 | ||
c19d1205 | 3911 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3912 | |
c19d1205 ZW |
3913 | demand_empty_rest_of_line (); |
3914 | } | |
e16bb312 | 3915 | |
e16bb312 | 3916 | |
c19d1205 | 3917 | /* Parse a personality directive. */ |
e16bb312 | 3918 | |
c19d1205 ZW |
3919 | static void |
3920 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3921 | { | |
3922 | char *name, *p, c; | |
a737bd4d | 3923 | |
921e5f0a | 3924 | if (!unwind.proc_start) |
c921be7d | 3925 | as_bad (MISSING_FNSTART); |
921e5f0a | 3926 | |
c19d1205 ZW |
3927 | if (unwind.personality_routine || unwind.personality_index != -1) |
3928 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3929 | |
c19d1205 ZW |
3930 | name = input_line_pointer; |
3931 | c = get_symbol_end (); | |
3932 | p = input_line_pointer; | |
3933 | unwind.personality_routine = symbol_find_or_make (name); | |
3934 | *p = c; | |
3935 | demand_empty_rest_of_line (); | |
3936 | } | |
e16bb312 | 3937 | |
e16bb312 | 3938 | |
c19d1205 | 3939 | /* Parse a directive saving core registers. */ |
e16bb312 | 3940 | |
c19d1205 ZW |
3941 | static void |
3942 | s_arm_unwind_save_core (void) | |
e16bb312 | 3943 | { |
c19d1205 ZW |
3944 | valueT op; |
3945 | long range; | |
3946 | int n; | |
e16bb312 | 3947 | |
c19d1205 ZW |
3948 | range = parse_reg_list (&input_line_pointer); |
3949 | if (range == FAIL) | |
e16bb312 | 3950 | { |
c19d1205 ZW |
3951 | as_bad (_("expected register list")); |
3952 | ignore_rest_of_line (); | |
3953 | return; | |
3954 | } | |
e16bb312 | 3955 | |
c19d1205 | 3956 | demand_empty_rest_of_line (); |
e16bb312 | 3957 | |
c19d1205 ZW |
3958 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3959 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3960 | ip because it is clobbered by calls. */ | |
3961 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3962 | && (range & 0x3000) == 0x1000) | |
3963 | { | |
3964 | unwind.opcode_count--; | |
3965 | unwind.sp_restored = 0; | |
3966 | range = (range | 0x2000) & ~0x1000; | |
3967 | unwind.pending_offset = 0; | |
3968 | } | |
e16bb312 | 3969 | |
01ae4198 DJ |
3970 | /* Pop r4-r15. */ |
3971 | if (range & 0xfff0) | |
c19d1205 | 3972 | { |
01ae4198 DJ |
3973 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3974 | registers starting with r4, plus maybe r14. */ | |
3975 | for (n = 0; n < 8; n++) | |
3976 | { | |
3977 | /* Break at the first non-saved register. */ | |
3978 | if ((range & (1 << (n + 4))) == 0) | |
3979 | break; | |
3980 | } | |
3981 | /* See if there are any other bits set. */ | |
3982 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3983 | { | |
3984 | /* Use the long form. */ | |
3985 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3986 | add_unwind_opcode (op, 2); | |
3987 | } | |
0dd132b6 | 3988 | else |
01ae4198 DJ |
3989 | { |
3990 | /* Use the short form. */ | |
3991 | if (range & 0x4000) | |
3992 | op = 0xa8; /* Pop r14. */ | |
3993 | else | |
3994 | op = 0xa0; /* Do not pop r14. */ | |
3995 | op |= (n - 1); | |
3996 | add_unwind_opcode (op, 1); | |
3997 | } | |
c19d1205 | 3998 | } |
0dd132b6 | 3999 | |
c19d1205 ZW |
4000 | /* Pop r0-r3. */ |
4001 | if (range & 0xf) | |
4002 | { | |
4003 | op = 0xb100 | (range & 0xf); | |
4004 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
4005 | } |
4006 | ||
c19d1205 ZW |
4007 | /* Record the number of bytes pushed. */ |
4008 | for (n = 0; n < 16; n++) | |
4009 | { | |
4010 | if (range & (1 << n)) | |
4011 | unwind.frame_size += 4; | |
4012 | } | |
0dd132b6 NC |
4013 | } |
4014 | ||
c19d1205 ZW |
4015 | |
4016 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
4017 | |
4018 | static void | |
c19d1205 | 4019 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 4020 | { |
c19d1205 ZW |
4021 | expressionS exp; |
4022 | int num_regs; | |
4023 | valueT op; | |
b99bd4ef | 4024 | |
c19d1205 ZW |
4025 | /* Get Number of registers to transfer. */ |
4026 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4027 | expression (&exp); | |
4028 | else | |
4029 | exp.X_op = O_illegal; | |
b99bd4ef | 4030 | |
c19d1205 | 4031 | if (exp.X_op != O_constant) |
b99bd4ef | 4032 | { |
c19d1205 ZW |
4033 | as_bad (_("expected , <constant>")); |
4034 | ignore_rest_of_line (); | |
b99bd4ef NC |
4035 | return; |
4036 | } | |
4037 | ||
c19d1205 ZW |
4038 | num_regs = exp.X_add_number; |
4039 | ||
4040 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 4041 | { |
c19d1205 ZW |
4042 | as_bad (_("number of registers must be in the range [1:4]")); |
4043 | ignore_rest_of_line (); | |
b99bd4ef NC |
4044 | return; |
4045 | } | |
4046 | ||
c19d1205 | 4047 | demand_empty_rest_of_line (); |
b99bd4ef | 4048 | |
c19d1205 ZW |
4049 | if (reg == 4) |
4050 | { | |
4051 | /* Short form. */ | |
4052 | op = 0xb4 | (num_regs - 1); | |
4053 | add_unwind_opcode (op, 1); | |
4054 | } | |
b99bd4ef NC |
4055 | else |
4056 | { | |
c19d1205 ZW |
4057 | /* Long form. */ |
4058 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4059 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4060 | } |
c19d1205 | 4061 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4062 | } |
4063 | ||
c19d1205 | 4064 | |
fa073d69 MS |
4065 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4066 | ||
4067 | static void | |
4068 | s_arm_unwind_save_vfp_armv6 (void) | |
4069 | { | |
4070 | int count; | |
4071 | unsigned int start; | |
4072 | valueT op; | |
4073 | int num_vfpv3_regs = 0; | |
4074 | int num_regs_below_16; | |
4075 | ||
4076 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
4077 | if (count == FAIL) | |
4078 | { | |
4079 | as_bad (_("expected register list")); | |
4080 | ignore_rest_of_line (); | |
4081 | return; | |
4082 | } | |
4083 | ||
4084 | demand_empty_rest_of_line (); | |
4085 | ||
4086 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4087 | than FSTMX/FLDMX-style ones). */ | |
4088 | ||
4089 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4090 | if (start >= 16) | |
4091 | num_vfpv3_regs = count; | |
4092 | else if (start + count > 16) | |
4093 | num_vfpv3_regs = start + count - 16; | |
4094 | ||
4095 | if (num_vfpv3_regs > 0) | |
4096 | { | |
4097 | int start_offset = start > 16 ? start - 16 : 0; | |
4098 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4099 | add_unwind_opcode (op, 2); | |
4100 | } | |
4101 | ||
4102 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4103 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4104 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4105 | if (num_regs_below_16 > 0) |
4106 | { | |
4107 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4108 | add_unwind_opcode (op, 2); | |
4109 | } | |
4110 | ||
4111 | unwind.frame_size += count * 8; | |
4112 | } | |
4113 | ||
4114 | ||
4115 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4116 | |
4117 | static void | |
c19d1205 | 4118 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4119 | { |
c19d1205 | 4120 | int count; |
ca3f61f7 | 4121 | unsigned int reg; |
c19d1205 | 4122 | valueT op; |
b99bd4ef | 4123 | |
5287ad62 | 4124 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 4125 | if (count == FAIL) |
b99bd4ef | 4126 | { |
c19d1205 ZW |
4127 | as_bad (_("expected register list")); |
4128 | ignore_rest_of_line (); | |
b99bd4ef NC |
4129 | return; |
4130 | } | |
4131 | ||
c19d1205 | 4132 | demand_empty_rest_of_line (); |
b99bd4ef | 4133 | |
c19d1205 | 4134 | if (reg == 8) |
b99bd4ef | 4135 | { |
c19d1205 ZW |
4136 | /* Short form. */ |
4137 | op = 0xb8 | (count - 1); | |
4138 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4139 | } |
c19d1205 | 4140 | else |
b99bd4ef | 4141 | { |
c19d1205 ZW |
4142 | /* Long form. */ |
4143 | op = 0xb300 | (reg << 4) | (count - 1); | |
4144 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4145 | } |
c19d1205 ZW |
4146 | unwind.frame_size += count * 8 + 4; |
4147 | } | |
b99bd4ef | 4148 | |
b99bd4ef | 4149 | |
c19d1205 ZW |
4150 | /* Parse a directive saving iWMMXt data registers. */ |
4151 | ||
4152 | static void | |
4153 | s_arm_unwind_save_mmxwr (void) | |
4154 | { | |
4155 | int reg; | |
4156 | int hi_reg; | |
4157 | int i; | |
4158 | unsigned mask = 0; | |
4159 | valueT op; | |
b99bd4ef | 4160 | |
c19d1205 ZW |
4161 | if (*input_line_pointer == '{') |
4162 | input_line_pointer++; | |
b99bd4ef | 4163 | |
c19d1205 | 4164 | do |
b99bd4ef | 4165 | { |
dcbf9037 | 4166 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4167 | |
c19d1205 | 4168 | if (reg == FAIL) |
b99bd4ef | 4169 | { |
9b7132d3 | 4170 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4171 | goto error; |
b99bd4ef NC |
4172 | } |
4173 | ||
c19d1205 ZW |
4174 | if (mask >> reg) |
4175 | as_tsktsk (_("register list not in ascending order")); | |
4176 | mask |= 1 << reg; | |
b99bd4ef | 4177 | |
c19d1205 ZW |
4178 | if (*input_line_pointer == '-') |
4179 | { | |
4180 | input_line_pointer++; | |
dcbf9037 | 4181 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4182 | if (hi_reg == FAIL) |
4183 | { | |
9b7132d3 | 4184 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4185 | goto error; |
4186 | } | |
4187 | else if (reg >= hi_reg) | |
4188 | { | |
4189 | as_bad (_("bad register range")); | |
4190 | goto error; | |
4191 | } | |
4192 | for (; reg < hi_reg; reg++) | |
4193 | mask |= 1 << reg; | |
4194 | } | |
4195 | } | |
4196 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4197 | |
d996d970 | 4198 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4199 | |
c19d1205 | 4200 | demand_empty_rest_of_line (); |
b99bd4ef | 4201 | |
708587a4 | 4202 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4203 | the list. */ |
4204 | flush_pending_unwind (); | |
b99bd4ef | 4205 | |
c19d1205 | 4206 | for (i = 0; i < 16; i++) |
b99bd4ef | 4207 | { |
c19d1205 ZW |
4208 | if (mask & (1 << i)) |
4209 | unwind.frame_size += 8; | |
b99bd4ef NC |
4210 | } |
4211 | ||
c19d1205 ZW |
4212 | /* Attempt to combine with a previous opcode. We do this because gcc |
4213 | likes to output separate unwind directives for a single block of | |
4214 | registers. */ | |
4215 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4216 | { |
c19d1205 ZW |
4217 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4218 | if ((i & 0xf8) == 0xc0) | |
4219 | { | |
4220 | i &= 7; | |
4221 | /* Only merge if the blocks are contiguous. */ | |
4222 | if (i < 6) | |
4223 | { | |
4224 | if ((mask & 0xfe00) == (1 << 9)) | |
4225 | { | |
4226 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4227 | unwind.opcode_count--; | |
4228 | } | |
4229 | } | |
4230 | else if (i == 6 && unwind.opcode_count >= 2) | |
4231 | { | |
4232 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4233 | reg = i >> 4; | |
4234 | i &= 0xf; | |
b99bd4ef | 4235 | |
c19d1205 ZW |
4236 | op = 0xffff << (reg - 1); |
4237 | if (reg > 0 | |
87a1fd79 | 4238 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4239 | { |
4240 | op = (1 << (reg + i + 1)) - 1; | |
4241 | op &= ~((1 << reg) - 1); | |
4242 | mask |= op; | |
4243 | unwind.opcode_count -= 2; | |
4244 | } | |
4245 | } | |
4246 | } | |
b99bd4ef NC |
4247 | } |
4248 | ||
c19d1205 ZW |
4249 | hi_reg = 15; |
4250 | /* We want to generate opcodes in the order the registers have been | |
4251 | saved, ie. descending order. */ | |
4252 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4253 | { |
c19d1205 ZW |
4254 | /* Save registers in blocks. */ |
4255 | if (reg < 0 | |
4256 | || !(mask & (1 << reg))) | |
4257 | { | |
4258 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4259 | preceding block. */ |
c19d1205 ZW |
4260 | if (reg != hi_reg) |
4261 | { | |
4262 | if (reg == 9) | |
4263 | { | |
4264 | /* Short form. */ | |
4265 | op = 0xc0 | (hi_reg - 10); | |
4266 | add_unwind_opcode (op, 1); | |
4267 | } | |
4268 | else | |
4269 | { | |
4270 | /* Long form. */ | |
4271 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4272 | add_unwind_opcode (op, 2); | |
4273 | } | |
4274 | } | |
4275 | hi_reg = reg - 1; | |
4276 | } | |
b99bd4ef NC |
4277 | } |
4278 | ||
c19d1205 ZW |
4279 | return; |
4280 | error: | |
4281 | ignore_rest_of_line (); | |
b99bd4ef NC |
4282 | } |
4283 | ||
4284 | static void | |
c19d1205 | 4285 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4286 | { |
c19d1205 ZW |
4287 | int reg; |
4288 | int hi_reg; | |
4289 | unsigned mask = 0; | |
4290 | valueT op; | |
b99bd4ef | 4291 | |
c19d1205 ZW |
4292 | if (*input_line_pointer == '{') |
4293 | input_line_pointer++; | |
b99bd4ef | 4294 | |
477330fc RM |
4295 | skip_whitespace (input_line_pointer); |
4296 | ||
c19d1205 | 4297 | do |
b99bd4ef | 4298 | { |
dcbf9037 | 4299 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4300 | |
c19d1205 ZW |
4301 | if (reg == FAIL) |
4302 | { | |
9b7132d3 | 4303 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4304 | goto error; |
4305 | } | |
b99bd4ef | 4306 | |
c19d1205 ZW |
4307 | reg -= 8; |
4308 | if (mask >> reg) | |
4309 | as_tsktsk (_("register list not in ascending order")); | |
4310 | mask |= 1 << reg; | |
b99bd4ef | 4311 | |
c19d1205 ZW |
4312 | if (*input_line_pointer == '-') |
4313 | { | |
4314 | input_line_pointer++; | |
dcbf9037 | 4315 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4316 | if (hi_reg == FAIL) |
4317 | { | |
9b7132d3 | 4318 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4319 | goto error; |
4320 | } | |
4321 | else if (reg >= hi_reg) | |
4322 | { | |
4323 | as_bad (_("bad register range")); | |
4324 | goto error; | |
4325 | } | |
4326 | for (; reg < hi_reg; reg++) | |
4327 | mask |= 1 << reg; | |
4328 | } | |
b99bd4ef | 4329 | } |
c19d1205 | 4330 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4331 | |
d996d970 | 4332 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4333 | |
c19d1205 ZW |
4334 | demand_empty_rest_of_line (); |
4335 | ||
708587a4 | 4336 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4337 | the list. */ |
4338 | flush_pending_unwind (); | |
b99bd4ef | 4339 | |
c19d1205 | 4340 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4341 | { |
c19d1205 ZW |
4342 | if (mask & (1 << reg)) |
4343 | unwind.frame_size += 4; | |
b99bd4ef | 4344 | } |
c19d1205 ZW |
4345 | op = 0xc700 | mask; |
4346 | add_unwind_opcode (op, 2); | |
4347 | return; | |
4348 | error: | |
4349 | ignore_rest_of_line (); | |
b99bd4ef NC |
4350 | } |
4351 | ||
c19d1205 | 4352 | |
fa073d69 MS |
4353 | /* Parse an unwind_save directive. |
4354 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4355 | |
b99bd4ef | 4356 | static void |
fa073d69 | 4357 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4358 | { |
c19d1205 ZW |
4359 | char *peek; |
4360 | struct reg_entry *reg; | |
4361 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4362 | |
921e5f0a | 4363 | if (!unwind.proc_start) |
c921be7d | 4364 | as_bad (MISSING_FNSTART); |
921e5f0a | 4365 | |
c19d1205 ZW |
4366 | /* Figure out what sort of save we have. */ |
4367 | peek = input_line_pointer; | |
b99bd4ef | 4368 | |
c19d1205 | 4369 | if (*peek == '{') |
b99bd4ef | 4370 | { |
c19d1205 ZW |
4371 | had_brace = TRUE; |
4372 | peek++; | |
b99bd4ef NC |
4373 | } |
4374 | ||
c19d1205 | 4375 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4376 | |
c19d1205 | 4377 | if (!reg) |
b99bd4ef | 4378 | { |
c19d1205 ZW |
4379 | as_bad (_("register expected")); |
4380 | ignore_rest_of_line (); | |
b99bd4ef NC |
4381 | return; |
4382 | } | |
4383 | ||
c19d1205 | 4384 | switch (reg->type) |
b99bd4ef | 4385 | { |
c19d1205 ZW |
4386 | case REG_TYPE_FN: |
4387 | if (had_brace) | |
4388 | { | |
4389 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4390 | ignore_rest_of_line (); | |
4391 | return; | |
4392 | } | |
93ac2687 | 4393 | input_line_pointer = peek; |
c19d1205 | 4394 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4395 | return; |
c19d1205 | 4396 | |
1f5afe1c NC |
4397 | case REG_TYPE_RN: |
4398 | s_arm_unwind_save_core (); | |
4399 | return; | |
4400 | ||
fa073d69 MS |
4401 | case REG_TYPE_VFD: |
4402 | if (arch_v6) | |
477330fc | 4403 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4404 | else |
477330fc | 4405 | s_arm_unwind_save_vfp (); |
fa073d69 | 4406 | return; |
1f5afe1c NC |
4407 | |
4408 | case REG_TYPE_MMXWR: | |
4409 | s_arm_unwind_save_mmxwr (); | |
4410 | return; | |
4411 | ||
4412 | case REG_TYPE_MMXWCG: | |
4413 | s_arm_unwind_save_mmxwcg (); | |
4414 | return; | |
c19d1205 ZW |
4415 | |
4416 | default: | |
4417 | as_bad (_(".unwind_save does not support this kind of register")); | |
4418 | ignore_rest_of_line (); | |
b99bd4ef | 4419 | } |
c19d1205 | 4420 | } |
b99bd4ef | 4421 | |
b99bd4ef | 4422 | |
c19d1205 ZW |
4423 | /* Parse an unwind_movsp directive. */ |
4424 | ||
4425 | static void | |
4426 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4427 | { | |
4428 | int reg; | |
4429 | valueT op; | |
4fa3602b | 4430 | int offset; |
c19d1205 | 4431 | |
921e5f0a | 4432 | if (!unwind.proc_start) |
c921be7d | 4433 | as_bad (MISSING_FNSTART); |
921e5f0a | 4434 | |
dcbf9037 | 4435 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4436 | if (reg == FAIL) |
b99bd4ef | 4437 | { |
9b7132d3 | 4438 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4439 | ignore_rest_of_line (); |
b99bd4ef NC |
4440 | return; |
4441 | } | |
4fa3602b PB |
4442 | |
4443 | /* Optional constant. */ | |
4444 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4445 | { | |
4446 | if (immediate_for_directive (&offset) == FAIL) | |
4447 | return; | |
4448 | } | |
4449 | else | |
4450 | offset = 0; | |
4451 | ||
c19d1205 | 4452 | demand_empty_rest_of_line (); |
b99bd4ef | 4453 | |
c19d1205 | 4454 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4455 | { |
c19d1205 | 4456 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4457 | return; |
4458 | } | |
4459 | ||
c19d1205 ZW |
4460 | if (unwind.fp_reg != REG_SP) |
4461 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4462 | |
c19d1205 ZW |
4463 | /* Generate opcode to restore the value. */ |
4464 | op = 0x90 | reg; | |
4465 | add_unwind_opcode (op, 1); | |
4466 | ||
4467 | /* Record the information for later. */ | |
4468 | unwind.fp_reg = reg; | |
4fa3602b | 4469 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4470 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4471 | } |
4472 | ||
c19d1205 ZW |
4473 | /* Parse an unwind_pad directive. */ |
4474 | ||
b05fe5cf | 4475 | static void |
c19d1205 | 4476 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4477 | { |
c19d1205 | 4478 | int offset; |
b05fe5cf | 4479 | |
921e5f0a | 4480 | if (!unwind.proc_start) |
c921be7d | 4481 | as_bad (MISSING_FNSTART); |
921e5f0a | 4482 | |
c19d1205 ZW |
4483 | if (immediate_for_directive (&offset) == FAIL) |
4484 | return; | |
b99bd4ef | 4485 | |
c19d1205 ZW |
4486 | if (offset & 3) |
4487 | { | |
4488 | as_bad (_("stack increment must be multiple of 4")); | |
4489 | ignore_rest_of_line (); | |
4490 | return; | |
4491 | } | |
b99bd4ef | 4492 | |
c19d1205 ZW |
4493 | /* Don't generate any opcodes, just record the details for later. */ |
4494 | unwind.frame_size += offset; | |
4495 | unwind.pending_offset += offset; | |
4496 | ||
4497 | demand_empty_rest_of_line (); | |
4498 | } | |
4499 | ||
4500 | /* Parse an unwind_setfp directive. */ | |
4501 | ||
4502 | static void | |
4503 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4504 | { |
c19d1205 ZW |
4505 | int sp_reg; |
4506 | int fp_reg; | |
4507 | int offset; | |
4508 | ||
921e5f0a | 4509 | if (!unwind.proc_start) |
c921be7d | 4510 | as_bad (MISSING_FNSTART); |
921e5f0a | 4511 | |
dcbf9037 | 4512 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4513 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4514 | sp_reg = FAIL; | |
4515 | else | |
dcbf9037 | 4516 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4517 | |
c19d1205 ZW |
4518 | if (fp_reg == FAIL || sp_reg == FAIL) |
4519 | { | |
4520 | as_bad (_("expected <reg>, <reg>")); | |
4521 | ignore_rest_of_line (); | |
4522 | return; | |
4523 | } | |
b99bd4ef | 4524 | |
c19d1205 ZW |
4525 | /* Optional constant. */ |
4526 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4527 | { | |
4528 | if (immediate_for_directive (&offset) == FAIL) | |
4529 | return; | |
4530 | } | |
4531 | else | |
4532 | offset = 0; | |
a737bd4d | 4533 | |
c19d1205 | 4534 | demand_empty_rest_of_line (); |
a737bd4d | 4535 | |
fdfde340 | 4536 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4537 | { |
c19d1205 ZW |
4538 | as_bad (_("register must be either sp or set by a previous" |
4539 | "unwind_movsp directive")); | |
4540 | return; | |
a737bd4d NC |
4541 | } |
4542 | ||
c19d1205 ZW |
4543 | /* Don't generate any opcodes, just record the information for later. */ |
4544 | unwind.fp_reg = fp_reg; | |
4545 | unwind.fp_used = 1; | |
fdfde340 | 4546 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4547 | unwind.fp_offset = unwind.frame_size - offset; |
4548 | else | |
4549 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4550 | } |
4551 | ||
c19d1205 ZW |
4552 | /* Parse an unwind_raw directive. */ |
4553 | ||
4554 | static void | |
4555 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4556 | { |
c19d1205 | 4557 | expressionS exp; |
708587a4 | 4558 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4559 | unsigned char op[16]; |
4560 | int count; | |
a737bd4d | 4561 | |
921e5f0a | 4562 | if (!unwind.proc_start) |
c921be7d | 4563 | as_bad (MISSING_FNSTART); |
921e5f0a | 4564 | |
c19d1205 ZW |
4565 | expression (&exp); |
4566 | if (exp.X_op == O_constant | |
4567 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4568 | { |
c19d1205 ZW |
4569 | unwind.frame_size += exp.X_add_number; |
4570 | expression (&exp); | |
4571 | } | |
4572 | else | |
4573 | exp.X_op = O_illegal; | |
a737bd4d | 4574 | |
c19d1205 ZW |
4575 | if (exp.X_op != O_constant) |
4576 | { | |
4577 | as_bad (_("expected <offset>, <opcode>")); | |
4578 | ignore_rest_of_line (); | |
4579 | return; | |
4580 | } | |
a737bd4d | 4581 | |
c19d1205 | 4582 | count = 0; |
a737bd4d | 4583 | |
c19d1205 ZW |
4584 | /* Parse the opcode. */ |
4585 | for (;;) | |
4586 | { | |
4587 | if (count >= 16) | |
4588 | { | |
4589 | as_bad (_("unwind opcode too long")); | |
4590 | ignore_rest_of_line (); | |
a737bd4d | 4591 | } |
c19d1205 | 4592 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4593 | { |
c19d1205 ZW |
4594 | as_bad (_("invalid unwind opcode")); |
4595 | ignore_rest_of_line (); | |
4596 | return; | |
a737bd4d | 4597 | } |
c19d1205 | 4598 | op[count++] = exp.X_add_number; |
a737bd4d | 4599 | |
c19d1205 ZW |
4600 | /* Parse the next byte. */ |
4601 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4602 | break; | |
a737bd4d | 4603 | |
c19d1205 ZW |
4604 | expression (&exp); |
4605 | } | |
b99bd4ef | 4606 | |
c19d1205 ZW |
4607 | /* Add the opcode bytes in reverse order. */ |
4608 | while (count--) | |
4609 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4610 | |
c19d1205 | 4611 | demand_empty_rest_of_line (); |
b99bd4ef | 4612 | } |
ee065d83 PB |
4613 | |
4614 | ||
4615 | /* Parse a .eabi_attribute directive. */ | |
4616 | ||
4617 | static void | |
4618 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4619 | { | |
0420f52b | 4620 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 AS |
4621 | |
4622 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4623 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4624 | } |
4625 | ||
0855e32b NS |
4626 | /* Emit a tls fix for the symbol. */ |
4627 | ||
4628 | static void | |
4629 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4630 | { | |
4631 | char *p; | |
4632 | expressionS exp; | |
4633 | #ifdef md_flush_pending_output | |
4634 | md_flush_pending_output (); | |
4635 | #endif | |
4636 | ||
4637 | #ifdef md_cons_align | |
4638 | md_cons_align (4); | |
4639 | #endif | |
4640 | ||
4641 | /* Since we're just labelling the code, there's no need to define a | |
4642 | mapping symbol. */ | |
4643 | expression (&exp); | |
4644 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4645 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4646 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4647 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4648 | } | |
cdf9ccec | 4649 | #endif /* OBJ_ELF */ |
0855e32b | 4650 | |
ee065d83 | 4651 | static void s_arm_arch (int); |
7a1d4c38 | 4652 | static void s_arm_object_arch (int); |
ee065d83 PB |
4653 | static void s_arm_cpu (int); |
4654 | static void s_arm_fpu (int); | |
69133863 | 4655 | static void s_arm_arch_extension (int); |
b99bd4ef | 4656 | |
f0927246 NC |
4657 | #ifdef TE_PE |
4658 | ||
4659 | static void | |
5f4273c7 | 4660 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4661 | { |
4662 | expressionS exp; | |
4663 | ||
4664 | do | |
4665 | { | |
4666 | expression (&exp); | |
4667 | if (exp.X_op == O_symbol) | |
4668 | exp.X_op = O_secrel; | |
4669 | ||
4670 | emit_expr (&exp, 4); | |
4671 | } | |
4672 | while (*input_line_pointer++ == ','); | |
4673 | ||
4674 | input_line_pointer--; | |
4675 | demand_empty_rest_of_line (); | |
4676 | } | |
4677 | #endif /* TE_PE */ | |
4678 | ||
c19d1205 ZW |
4679 | /* This table describes all the machine specific pseudo-ops the assembler |
4680 | has to support. The fields are: | |
4681 | pseudo-op name without dot | |
4682 | function to call to execute this pseudo-op | |
4683 | Integer arg to pass to the function. */ | |
b99bd4ef | 4684 | |
c19d1205 | 4685 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4686 | { |
c19d1205 ZW |
4687 | /* Never called because '.req' does not start a line. */ |
4688 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4689 | /* Following two are likewise never called. */ |
4690 | { "dn", s_dn, 0 }, | |
4691 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4692 | { "unreq", s_unreq, 0 }, |
4693 | { "bss", s_bss, 0 }, | |
4694 | { "align", s_align, 0 }, | |
4695 | { "arm", s_arm, 0 }, | |
4696 | { "thumb", s_thumb, 0 }, | |
4697 | { "code", s_code, 0 }, | |
4698 | { "force_thumb", s_force_thumb, 0 }, | |
4699 | { "thumb_func", s_thumb_func, 0 }, | |
4700 | { "thumb_set", s_thumb_set, 0 }, | |
4701 | { "even", s_even, 0 }, | |
4702 | { "ltorg", s_ltorg, 0 }, | |
4703 | { "pool", s_ltorg, 0 }, | |
4704 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4705 | { "cpu", s_arm_cpu, 0 }, |
4706 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4707 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4708 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4709 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4710 | #ifdef OBJ_ELF |
c921be7d NC |
4711 | { "word", s_arm_elf_cons, 4 }, |
4712 | { "long", s_arm_elf_cons, 4 }, | |
4713 | { "inst.n", s_arm_elf_inst, 2 }, | |
4714 | { "inst.w", s_arm_elf_inst, 4 }, | |
4715 | { "inst", s_arm_elf_inst, 0 }, | |
4716 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4717 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4718 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4719 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4720 | { "personality", s_arm_unwind_personality, 0 }, | |
4721 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4722 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4723 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4724 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4725 | { "movsp", s_arm_unwind_movsp, 0 }, |
4726 | { "pad", s_arm_unwind_pad, 0 }, | |
4727 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4728 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4729 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4730 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4731 | #else |
4732 | { "word", cons, 4}, | |
f0927246 NC |
4733 | |
4734 | /* These are used for dwarf. */ | |
4735 | {"2byte", cons, 2}, | |
4736 | {"4byte", cons, 4}, | |
4737 | {"8byte", cons, 8}, | |
4738 | /* These are used for dwarf2. */ | |
4739 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4740 | { "loc", dwarf2_directive_loc, 0 }, | |
4741 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4742 | #endif |
4743 | { "extend", float_cons, 'x' }, | |
4744 | { "ldouble", float_cons, 'x' }, | |
4745 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4746 | #ifdef TE_PE |
4747 | {"secrel32", pe_directive_secrel, 0}, | |
4748 | #endif | |
2e6976a8 DG |
4749 | |
4750 | /* These are for compatibility with CodeComposer Studio. */ | |
4751 | {"ref", s_ccs_ref, 0}, | |
4752 | {"def", s_ccs_def, 0}, | |
4753 | {"asmfunc", s_ccs_asmfunc, 0}, | |
4754 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
4755 | ||
c19d1205 ZW |
4756 | { 0, 0, 0 } |
4757 | }; | |
4758 | \f | |
4759 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4760 | |
c19d1205 ZW |
4761 | /* Generic immediate-value read function for use in insn parsing. |
4762 | STR points to the beginning of the immediate (the leading #); | |
4763 | VAL receives the value; if the value is outside [MIN, MAX] | |
4764 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4765 | optional. */ | |
b99bd4ef | 4766 | |
c19d1205 ZW |
4767 | static int |
4768 | parse_immediate (char **str, int *val, int min, int max, | |
4769 | bfd_boolean prefix_opt) | |
4770 | { | |
4771 | expressionS exp; | |
4772 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4773 | if (exp.X_op != O_constant) | |
b99bd4ef | 4774 | { |
c19d1205 ZW |
4775 | inst.error = _("constant expression required"); |
4776 | return FAIL; | |
4777 | } | |
b99bd4ef | 4778 | |
c19d1205 ZW |
4779 | if (exp.X_add_number < min || exp.X_add_number > max) |
4780 | { | |
4781 | inst.error = _("immediate value out of range"); | |
4782 | return FAIL; | |
4783 | } | |
b99bd4ef | 4784 | |
c19d1205 ZW |
4785 | *val = exp.X_add_number; |
4786 | return SUCCESS; | |
4787 | } | |
b99bd4ef | 4788 | |
5287ad62 | 4789 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4790 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4791 | instructions. Puts the result directly in inst.operands[i]. */ |
4792 | ||
4793 | static int | |
8335d6aa JW |
4794 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
4795 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
4796 | { |
4797 | expressionS exp; | |
8335d6aa | 4798 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
4799 | char *ptr = *str; |
4800 | ||
8335d6aa | 4801 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 4802 | |
8335d6aa | 4803 | if (exp_p->X_op == O_constant) |
036dc3f7 | 4804 | { |
8335d6aa | 4805 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
4806 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
4807 | O_constant. We have to be careful not to break compilation for | |
4808 | 32-bit X_add_number, though. */ | |
8335d6aa | 4809 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 4810 | { |
8335d6aa JW |
4811 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
4812 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
4813 | & 0xffffffff); | |
036dc3f7 PB |
4814 | inst.operands[i].regisimm = 1; |
4815 | } | |
4816 | } | |
8335d6aa JW |
4817 | else if (exp_p->X_op == O_big |
4818 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
4819 | { |
4820 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4821 | |
5287ad62 | 4822 | /* Bignums have their least significant bits in |
477330fc RM |
4823 | generic_bignum[0]. Make sure we put 32 bits in imm and |
4824 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4825 | gas_assert (parts != 0); |
95b75c01 NC |
4826 | |
4827 | /* Make sure that the number is not too big. | |
4828 | PR 11972: Bignums can now be sign-extended to the | |
4829 | size of a .octa so check that the out of range bits | |
4830 | are all zero or all one. */ | |
8335d6aa | 4831 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
4832 | { |
4833 | LITTLENUM_TYPE m = -1; | |
4834 | ||
4835 | if (generic_bignum[parts * 2] != 0 | |
4836 | && generic_bignum[parts * 2] != m) | |
4837 | return FAIL; | |
4838 | ||
8335d6aa | 4839 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
4840 | if (generic_bignum[j] != generic_bignum[j-1]) |
4841 | return FAIL; | |
4842 | } | |
4843 | ||
5287ad62 JB |
4844 | inst.operands[i].imm = 0; |
4845 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4846 | inst.operands[i].imm |= generic_bignum[idx] |
4847 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4848 | inst.operands[i].reg = 0; |
4849 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4850 | inst.operands[i].reg |= generic_bignum[idx] |
4851 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4852 | inst.operands[i].regisimm = 1; |
4853 | } | |
8335d6aa | 4854 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 4855 | return FAIL; |
5f4273c7 | 4856 | |
5287ad62 JB |
4857 | *str = ptr; |
4858 | ||
4859 | return SUCCESS; | |
4860 | } | |
4861 | ||
c19d1205 ZW |
4862 | /* Returns the pseudo-register number of an FPA immediate constant, |
4863 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4864 | |
c19d1205 ZW |
4865 | static int |
4866 | parse_fpa_immediate (char ** str) | |
4867 | { | |
4868 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4869 | char * save_in; | |
4870 | expressionS exp; | |
4871 | int i; | |
4872 | int j; | |
b99bd4ef | 4873 | |
c19d1205 ZW |
4874 | /* First try and match exact strings, this is to guarantee |
4875 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4876 | |
c19d1205 ZW |
4877 | for (i = 0; fp_const[i]; i++) |
4878 | { | |
4879 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4880 | { |
c19d1205 | 4881 | char *start = *str; |
b99bd4ef | 4882 | |
c19d1205 ZW |
4883 | *str += strlen (fp_const[i]); |
4884 | if (is_end_of_line[(unsigned char) **str]) | |
4885 | return i + 8; | |
4886 | *str = start; | |
4887 | } | |
4888 | } | |
b99bd4ef | 4889 | |
c19d1205 ZW |
4890 | /* Just because we didn't get a match doesn't mean that the constant |
4891 | isn't valid, just that it is in a format that we don't | |
4892 | automatically recognize. Try parsing it with the standard | |
4893 | expression routines. */ | |
b99bd4ef | 4894 | |
c19d1205 | 4895 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4896 | |
c19d1205 ZW |
4897 | /* Look for a raw floating point number. */ |
4898 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4899 | && is_end_of_line[(unsigned char) *save_in]) | |
4900 | { | |
4901 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4902 | { | |
4903 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4904 | { |
c19d1205 ZW |
4905 | if (words[j] != fp_values[i][j]) |
4906 | break; | |
b99bd4ef NC |
4907 | } |
4908 | ||
c19d1205 | 4909 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4910 | { |
c19d1205 ZW |
4911 | *str = save_in; |
4912 | return i + 8; | |
b99bd4ef NC |
4913 | } |
4914 | } | |
4915 | } | |
b99bd4ef | 4916 | |
c19d1205 ZW |
4917 | /* Try and parse a more complex expression, this will probably fail |
4918 | unless the code uses a floating point prefix (eg "0f"). */ | |
4919 | save_in = input_line_pointer; | |
4920 | input_line_pointer = *str; | |
4921 | if (expression (&exp) == absolute_section | |
4922 | && exp.X_op == O_big | |
4923 | && exp.X_add_number < 0) | |
4924 | { | |
4925 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4926 | Ditto for 15. */ | |
ba592044 AM |
4927 | #define X_PRECISION 5 |
4928 | #define E_PRECISION 15L | |
4929 | if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0) | |
c19d1205 ZW |
4930 | { |
4931 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4932 | { | |
4933 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4934 | { | |
4935 | if (words[j] != fp_values[i][j]) | |
4936 | break; | |
4937 | } | |
b99bd4ef | 4938 | |
c19d1205 ZW |
4939 | if (j == MAX_LITTLENUMS) |
4940 | { | |
4941 | *str = input_line_pointer; | |
4942 | input_line_pointer = save_in; | |
4943 | return i + 8; | |
4944 | } | |
4945 | } | |
4946 | } | |
b99bd4ef NC |
4947 | } |
4948 | ||
c19d1205 ZW |
4949 | *str = input_line_pointer; |
4950 | input_line_pointer = save_in; | |
4951 | inst.error = _("invalid FPA immediate expression"); | |
4952 | return FAIL; | |
b99bd4ef NC |
4953 | } |
4954 | ||
136da414 JB |
4955 | /* Returns 1 if a number has "quarter-precision" float format |
4956 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4957 | ||
4958 | static int | |
4959 | is_quarter_float (unsigned imm) | |
4960 | { | |
4961 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4962 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4963 | } | |
4964 | ||
aacf0b33 KT |
4965 | |
4966 | /* Detect the presence of a floating point or integer zero constant, | |
4967 | i.e. #0.0 or #0. */ | |
4968 | ||
4969 | static bfd_boolean | |
4970 | parse_ifimm_zero (char **in) | |
4971 | { | |
4972 | int error_code; | |
4973 | ||
4974 | if (!is_immediate_prefix (**in)) | |
4975 | return FALSE; | |
4976 | ||
4977 | ++*in; | |
0900a05b JW |
4978 | |
4979 | /* Accept #0x0 as a synonym for #0. */ | |
4980 | if (strncmp (*in, "0x", 2) == 0) | |
4981 | { | |
4982 | int val; | |
4983 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) | |
4984 | return FALSE; | |
4985 | return TRUE; | |
4986 | } | |
4987 | ||
aacf0b33 KT |
4988 | error_code = atof_generic (in, ".", EXP_CHARS, |
4989 | &generic_floating_point_number); | |
4990 | ||
4991 | if (!error_code | |
4992 | && generic_floating_point_number.sign == '+' | |
4993 | && (generic_floating_point_number.low | |
4994 | > generic_floating_point_number.leader)) | |
4995 | return TRUE; | |
4996 | ||
4997 | return FALSE; | |
4998 | } | |
4999 | ||
136da414 JB |
5000 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
5001 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
5002 | The zero and minus-zero cases need special handling, since they can't be |
5003 | encoded in the "quarter-precision" float format, but can nonetheless be | |
5004 | loaded as integer constants. */ | |
136da414 JB |
5005 | |
5006 | static unsigned | |
5007 | parse_qfloat_immediate (char **ccp, int *immed) | |
5008 | { | |
5009 | char *str = *ccp; | |
c96612cc | 5010 | char *fpnum; |
136da414 | 5011 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 5012 | int found_fpchar = 0; |
5f4273c7 | 5013 | |
136da414 | 5014 | skip_past_char (&str, '#'); |
5f4273c7 | 5015 | |
c96612cc JB |
5016 | /* We must not accidentally parse an integer as a floating-point number. Make |
5017 | sure that the value we parse is not an integer by checking for special | |
5018 | characters '.' or 'e'. | |
5019 | FIXME: This is a horrible hack, but doing better is tricky because type | |
5020 | information isn't in a very usable state at parse time. */ | |
5021 | fpnum = str; | |
5022 | skip_whitespace (fpnum); | |
5023 | ||
5024 | if (strncmp (fpnum, "0x", 2) == 0) | |
5025 | return FAIL; | |
5026 | else | |
5027 | { | |
5028 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
5029 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
5030 | { | |
5031 | found_fpchar = 1; | |
5032 | break; | |
5033 | } | |
c96612cc JB |
5034 | |
5035 | if (!found_fpchar) | |
477330fc | 5036 | return FAIL; |
c96612cc | 5037 | } |
5f4273c7 | 5038 | |
136da414 JB |
5039 | if ((str = atof_ieee (str, 's', words)) != NULL) |
5040 | { | |
5041 | unsigned fpword = 0; | |
5042 | int i; | |
5f4273c7 | 5043 | |
136da414 JB |
5044 | /* Our FP word must be 32 bits (single-precision FP). */ |
5045 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
5046 | { |
5047 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5048 | fpword |= words[i]; | |
5049 | } | |
5f4273c7 | 5050 | |
c96612cc | 5051 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5052 | *immed = fpword; |
136da414 | 5053 | else |
477330fc | 5054 | return FAIL; |
136da414 JB |
5055 | |
5056 | *ccp = str; | |
5f4273c7 | 5057 | |
136da414 JB |
5058 | return SUCCESS; |
5059 | } | |
5f4273c7 | 5060 | |
136da414 JB |
5061 | return FAIL; |
5062 | } | |
5063 | ||
c19d1205 ZW |
5064 | /* Shift operands. */ |
5065 | enum shift_kind | |
b99bd4ef | 5066 | { |
c19d1205 ZW |
5067 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
5068 | }; | |
b99bd4ef | 5069 | |
c19d1205 ZW |
5070 | struct asm_shift_name |
5071 | { | |
5072 | const char *name; | |
5073 | enum shift_kind kind; | |
5074 | }; | |
b99bd4ef | 5075 | |
c19d1205 ZW |
5076 | /* Third argument to parse_shift. */ |
5077 | enum parse_shift_mode | |
5078 | { | |
5079 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5080 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5081 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5082 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5083 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
5084 | }; | |
b99bd4ef | 5085 | |
c19d1205 ZW |
5086 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5087 | This has three forms: | |
b99bd4ef | 5088 | |
c19d1205 ZW |
5089 | (LSL|LSR|ASL|ASR|ROR) Rs |
5090 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5091 | RRX | |
b99bd4ef | 5092 | |
c19d1205 ZW |
5093 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5094 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5095 | |
c19d1205 ZW |
5096 | static int |
5097 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5098 | { |
c19d1205 ZW |
5099 | const struct asm_shift_name *shift_name; |
5100 | enum shift_kind shift; | |
5101 | char *s = *str; | |
5102 | char *p = s; | |
5103 | int reg; | |
b99bd4ef | 5104 | |
c19d1205 ZW |
5105 | for (p = *str; ISALPHA (*p); p++) |
5106 | ; | |
b99bd4ef | 5107 | |
c19d1205 | 5108 | if (p == *str) |
b99bd4ef | 5109 | { |
c19d1205 ZW |
5110 | inst.error = _("shift expression expected"); |
5111 | return FAIL; | |
b99bd4ef NC |
5112 | } |
5113 | ||
21d799b5 | 5114 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5115 | p - *str); |
c19d1205 ZW |
5116 | |
5117 | if (shift_name == NULL) | |
b99bd4ef | 5118 | { |
c19d1205 ZW |
5119 | inst.error = _("shift expression expected"); |
5120 | return FAIL; | |
b99bd4ef NC |
5121 | } |
5122 | ||
c19d1205 | 5123 | shift = shift_name->kind; |
b99bd4ef | 5124 | |
c19d1205 ZW |
5125 | switch (mode) |
5126 | { | |
5127 | case NO_SHIFT_RESTRICT: | |
5128 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 5129 | |
c19d1205 ZW |
5130 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5131 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5132 | { | |
5133 | inst.error = _("'LSL' or 'ASR' required"); | |
5134 | return FAIL; | |
5135 | } | |
5136 | break; | |
b99bd4ef | 5137 | |
c19d1205 ZW |
5138 | case SHIFT_LSL_IMMEDIATE: |
5139 | if (shift != SHIFT_LSL) | |
5140 | { | |
5141 | inst.error = _("'LSL' required"); | |
5142 | return FAIL; | |
5143 | } | |
5144 | break; | |
b99bd4ef | 5145 | |
c19d1205 ZW |
5146 | case SHIFT_ASR_IMMEDIATE: |
5147 | if (shift != SHIFT_ASR) | |
5148 | { | |
5149 | inst.error = _("'ASR' required"); | |
5150 | return FAIL; | |
5151 | } | |
5152 | break; | |
b99bd4ef | 5153 | |
c19d1205 ZW |
5154 | default: abort (); |
5155 | } | |
b99bd4ef | 5156 | |
c19d1205 ZW |
5157 | if (shift != SHIFT_RRX) |
5158 | { | |
5159 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5160 | skip_whitespace (p); | |
b99bd4ef | 5161 | |
c19d1205 | 5162 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5163 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5164 | { |
5165 | inst.operands[i].imm = reg; | |
5166 | inst.operands[i].immisreg = 1; | |
5167 | } | |
5168 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5169 | return FAIL; | |
5170 | } | |
5171 | inst.operands[i].shift_kind = shift; | |
5172 | inst.operands[i].shifted = 1; | |
5173 | *str = p; | |
5174 | return SUCCESS; | |
b99bd4ef NC |
5175 | } |
5176 | ||
c19d1205 | 5177 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5178 | |
c19d1205 ZW |
5179 | #<immediate> |
5180 | #<immediate>, <rotate> | |
5181 | <Rm> | |
5182 | <Rm>, <shift> | |
b99bd4ef | 5183 | |
c19d1205 ZW |
5184 | where <shift> is defined by parse_shift above, and <rotate> is a |
5185 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5186 | is deferred to md_apply_fix. */ |
b99bd4ef | 5187 | |
c19d1205 ZW |
5188 | static int |
5189 | parse_shifter_operand (char **str, int i) | |
5190 | { | |
5191 | int value; | |
91d6fa6a | 5192 | expressionS exp; |
b99bd4ef | 5193 | |
dcbf9037 | 5194 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5195 | { |
5196 | inst.operands[i].reg = value; | |
5197 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5198 | |
c19d1205 ZW |
5199 | /* parse_shift will override this if appropriate */ |
5200 | inst.reloc.exp.X_op = O_constant; | |
5201 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 5202 | |
c19d1205 ZW |
5203 | if (skip_past_comma (str) == FAIL) |
5204 | return SUCCESS; | |
b99bd4ef | 5205 | |
c19d1205 ZW |
5206 | /* Shift operation on register. */ |
5207 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5208 | } |
5209 | ||
c19d1205 ZW |
5210 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
5211 | return FAIL; | |
b99bd4ef | 5212 | |
c19d1205 | 5213 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5214 | { |
c19d1205 | 5215 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5216 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5217 | return FAIL; |
b99bd4ef | 5218 | |
91d6fa6a | 5219 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
5220 | { |
5221 | inst.error = _("constant expression expected"); | |
5222 | return FAIL; | |
5223 | } | |
b99bd4ef | 5224 | |
91d6fa6a | 5225 | value = exp.X_add_number; |
c19d1205 ZW |
5226 | if (value < 0 || value > 30 || value % 2 != 0) |
5227 | { | |
5228 | inst.error = _("invalid rotation"); | |
5229 | return FAIL; | |
5230 | } | |
5231 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
5232 | { | |
5233 | inst.error = _("invalid constant"); | |
5234 | return FAIL; | |
5235 | } | |
09d92015 | 5236 | |
a415b1cd JB |
5237 | /* Encode as specified. */ |
5238 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
5239 | return SUCCESS; | |
09d92015 MM |
5240 | } |
5241 | ||
c19d1205 ZW |
5242 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
5243 | inst.reloc.pc_rel = 0; | |
5244 | return SUCCESS; | |
09d92015 MM |
5245 | } |
5246 | ||
4962c51a MS |
5247 | /* Group relocation information. Each entry in the table contains the |
5248 | textual name of the relocation as may appear in assembler source | |
5249 | and must end with a colon. | |
5250 | Along with this textual name are the relocation codes to be used if | |
5251 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5252 | an LDR, an LDRS, or an LDC. */ | |
5253 | ||
5254 | struct group_reloc_table_entry | |
5255 | { | |
5256 | const char *name; | |
5257 | int alu_code; | |
5258 | int ldr_code; | |
5259 | int ldrs_code; | |
5260 | int ldc_code; | |
5261 | }; | |
5262 | ||
5263 | typedef enum | |
5264 | { | |
5265 | /* Varieties of non-ALU group relocation. */ | |
5266 | ||
5267 | GROUP_LDR, | |
5268 | GROUP_LDRS, | |
5269 | GROUP_LDC | |
5270 | } group_reloc_type; | |
5271 | ||
5272 | static struct group_reloc_table_entry group_reloc_table[] = | |
5273 | { /* Program counter relative: */ | |
5274 | { "pc_g0_nc", | |
5275 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5276 | 0, /* LDR */ | |
5277 | 0, /* LDRS */ | |
5278 | 0 }, /* LDC */ | |
5279 | { "pc_g0", | |
5280 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5281 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5282 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5283 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5284 | { "pc_g1_nc", | |
5285 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5286 | 0, /* LDR */ | |
5287 | 0, /* LDRS */ | |
5288 | 0 }, /* LDC */ | |
5289 | { "pc_g1", | |
5290 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5291 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5292 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5293 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5294 | { "pc_g2", | |
5295 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5296 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5297 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5298 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5299 | /* Section base relative */ | |
5300 | { "sb_g0_nc", | |
5301 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5302 | 0, /* LDR */ | |
5303 | 0, /* LDRS */ | |
5304 | 0 }, /* LDC */ | |
5305 | { "sb_g0", | |
5306 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5307 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5308 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5309 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5310 | { "sb_g1_nc", | |
5311 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5312 | 0, /* LDR */ | |
5313 | 0, /* LDRS */ | |
5314 | 0 }, /* LDC */ | |
5315 | { "sb_g1", | |
5316 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5317 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5318 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5319 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5320 | { "sb_g2", | |
5321 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5322 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5323 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
5324 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
5325 | ||
5326 | /* Given the address of a pointer pointing to the textual name of a group | |
5327 | relocation as may appear in assembler source, attempt to find its details | |
5328 | in group_reloc_table. The pointer will be updated to the character after | |
5329 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5330 | otherwise. On success, *entry will be updated to point at the relevant | |
5331 | group_reloc_table entry. */ | |
5332 | ||
5333 | static int | |
5334 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5335 | { | |
5336 | unsigned int i; | |
5337 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5338 | { | |
5339 | int length = strlen (group_reloc_table[i].name); | |
5340 | ||
5f4273c7 NC |
5341 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5342 | && (*str)[length] == ':') | |
477330fc RM |
5343 | { |
5344 | *out = &group_reloc_table[i]; | |
5345 | *str += (length + 1); | |
5346 | return SUCCESS; | |
5347 | } | |
4962c51a MS |
5348 | } |
5349 | ||
5350 | return FAIL; | |
5351 | } | |
5352 | ||
5353 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5354 | (as for parse_shifter_operand) where group relocations are allowed: | |
5355 | ||
5356 | #<immediate> | |
5357 | #<immediate>, <rotate> | |
5358 | #:<group_reloc>:<expression> | |
5359 | <Rm> | |
5360 | <Rm>, <shift> | |
5361 | ||
5362 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5363 | The hashes are optional. | |
5364 | ||
5365 | Everything else is as for parse_shifter_operand. */ | |
5366 | ||
5367 | static parse_operand_result | |
5368 | parse_shifter_operand_group_reloc (char **str, int i) | |
5369 | { | |
5370 | /* Determine if we have the sequence of characters #: or just : | |
5371 | coming next. If we do, then we check for a group relocation. | |
5372 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5373 | ||
5374 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5375 | || (*str)[0] == ':') | |
5376 | { | |
5377 | struct group_reloc_table_entry *entry; | |
5378 | ||
5379 | if ((*str)[0] == '#') | |
477330fc | 5380 | (*str) += 2; |
4962c51a | 5381 | else |
477330fc | 5382 | (*str)++; |
4962c51a MS |
5383 | |
5384 | /* Try to parse a group relocation. Anything else is an error. */ | |
5385 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5386 | { |
5387 | inst.error = _("unknown group relocation"); | |
5388 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5389 | } | |
4962c51a MS |
5390 | |
5391 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5392 | the name in the assembler source. Next, we parse the expression. */ |
4962c51a | 5393 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) |
477330fc | 5394 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5395 | |
5396 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5397 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5398 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5399 | |
5400 | return PARSE_OPERAND_SUCCESS; | |
5401 | } | |
5402 | else | |
5403 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5404 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5405 | |
5406 | /* Never reached. */ | |
5407 | } | |
5408 | ||
8e560766 MGD |
5409 | /* Parse a Neon alignment expression. Information is written to |
5410 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5411 | |
8e560766 MGD |
5412 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5413 | static parse_operand_result | |
5414 | parse_neon_alignment (char **str, int i) | |
5415 | { | |
5416 | char *p = *str; | |
5417 | expressionS exp; | |
5418 | ||
5419 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5420 | ||
5421 | if (exp.X_op != O_constant) | |
5422 | { | |
5423 | inst.error = _("alignment must be constant"); | |
5424 | return PARSE_OPERAND_FAIL; | |
5425 | } | |
5426 | ||
5427 | inst.operands[i].imm = exp.X_add_number << 8; | |
5428 | inst.operands[i].immisalign = 1; | |
5429 | /* Alignments are not pre-indexes. */ | |
5430 | inst.operands[i].preind = 0; | |
5431 | ||
5432 | *str = p; | |
5433 | return PARSE_OPERAND_SUCCESS; | |
5434 | } | |
5435 | ||
c19d1205 ZW |
5436 | /* Parse all forms of an ARM address expression. Information is written |
5437 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5438 | |
c19d1205 | 5439 | Preindexed addressing (.preind=1): |
09d92015 | 5440 | |
c19d1205 ZW |
5441 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5442 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5443 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5444 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5445 | |
c19d1205 | 5446 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5447 | |
c19d1205 | 5448 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5449 | |
c19d1205 ZW |
5450 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5451 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5452 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5453 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5454 | |
c19d1205 | 5455 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5456 | |
c19d1205 | 5457 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5458 | |
c19d1205 | 5459 | Other: |
09d92015 | 5460 | |
c19d1205 ZW |
5461 | [Rn]{!} shorthand for [Rn,#0]{!} |
5462 | =immediate .isreg=0 .reloc.exp=immediate | |
5463 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5464 | |
c19d1205 ZW |
5465 | It is the caller's responsibility to check for addressing modes not |
5466 | supported by the instruction, and to set inst.reloc.type. */ | |
5467 | ||
4962c51a MS |
5468 | static parse_operand_result |
5469 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5470 | group_reloc_type group_type) |
09d92015 | 5471 | { |
c19d1205 ZW |
5472 | char *p = *str; |
5473 | int reg; | |
09d92015 | 5474 | |
c19d1205 | 5475 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5476 | { |
c19d1205 ZW |
5477 | if (skip_past_char (&p, '=') == FAIL) |
5478 | { | |
974da60d | 5479 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5480 | inst.reloc.pc_rel = 1; |
5481 | inst.operands[i].reg = REG_PC; | |
5482 | inst.operands[i].isreg = 1; | |
5483 | inst.operands[i].preind = 1; | |
09d92015 | 5484 | |
8335d6aa JW |
5485 | if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG)) |
5486 | return PARSE_OPERAND_FAIL; | |
5487 | } | |
5488 | else if (parse_big_immediate (&p, i, &inst.reloc.exp, | |
5489 | /*allow_symbol_p=*/TRUE)) | |
4962c51a | 5490 | return PARSE_OPERAND_FAIL; |
09d92015 | 5491 | |
c19d1205 | 5492 | *str = p; |
4962c51a | 5493 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5494 | } |
5495 | ||
8ab8155f NC |
5496 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5497 | skip_whitespace (p); | |
5498 | ||
dcbf9037 | 5499 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5500 | { |
c19d1205 | 5501 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5502 | return PARSE_OPERAND_FAIL; |
09d92015 | 5503 | } |
c19d1205 ZW |
5504 | inst.operands[i].reg = reg; |
5505 | inst.operands[i].isreg = 1; | |
09d92015 | 5506 | |
c19d1205 | 5507 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5508 | { |
c19d1205 | 5509 | inst.operands[i].preind = 1; |
09d92015 | 5510 | |
c19d1205 ZW |
5511 | if (*p == '+') p++; |
5512 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5513 | ||
dcbf9037 | 5514 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5515 | { |
c19d1205 ZW |
5516 | inst.operands[i].imm = reg; |
5517 | inst.operands[i].immisreg = 1; | |
5518 | ||
5519 | if (skip_past_comma (&p) == SUCCESS) | |
5520 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5521 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5522 | } |
5287ad62 | 5523 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5524 | { |
5525 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5526 | code before we get to see it here. This may be subject to | |
5527 | change. */ | |
5528 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5529 | |
8e560766 MGD |
5530 | if (result != PARSE_OPERAND_SUCCESS) |
5531 | return result; | |
5532 | } | |
c19d1205 ZW |
5533 | else |
5534 | { | |
5535 | if (inst.operands[i].negative) | |
5536 | { | |
5537 | inst.operands[i].negative = 0; | |
5538 | p--; | |
5539 | } | |
4962c51a | 5540 | |
5f4273c7 NC |
5541 | if (group_relocations |
5542 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5543 | { |
5544 | struct group_reloc_table_entry *entry; | |
5545 | ||
477330fc RM |
5546 | /* Skip over the #: or : sequence. */ |
5547 | if (*p == '#') | |
5548 | p += 2; | |
5549 | else | |
5550 | p++; | |
4962c51a MS |
5551 | |
5552 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5553 | error. */ |
4962c51a MS |
5554 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5555 | { | |
5556 | inst.error = _("unknown group relocation"); | |
5557 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5558 | } | |
5559 | ||
5560 | /* We now have the group relocation table entry corresponding to | |
5561 | the name in the assembler source. Next, we parse the | |
477330fc | 5562 | expression. */ |
4962c51a MS |
5563 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
5564 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5565 | ||
5566 | /* Record the relocation type. */ | |
477330fc RM |
5567 | switch (group_type) |
5568 | { | |
5569 | case GROUP_LDR: | |
5570 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; | |
5571 | break; | |
4962c51a | 5572 | |
477330fc RM |
5573 | case GROUP_LDRS: |
5574 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; | |
5575 | break; | |
4962c51a | 5576 | |
477330fc RM |
5577 | case GROUP_LDC: |
5578 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; | |
5579 | break; | |
4962c51a | 5580 | |
477330fc RM |
5581 | default: |
5582 | gas_assert (0); | |
5583 | } | |
4962c51a | 5584 | |
477330fc | 5585 | if (inst.reloc.type == 0) |
4962c51a MS |
5586 | { |
5587 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5588 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5589 | } | |
477330fc RM |
5590 | } |
5591 | else | |
26d97720 NS |
5592 | { |
5593 | char *q = p; | |
5594 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5595 | return PARSE_OPERAND_FAIL; | |
5596 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5597 | if (inst.reloc.exp.X_op == O_constant | |
5598 | && inst.reloc.exp.X_add_number == 0) | |
5599 | { | |
5600 | skip_whitespace (q); | |
5601 | if (*q == '#') | |
5602 | { | |
5603 | q++; | |
5604 | skip_whitespace (q); | |
5605 | } | |
5606 | if (*q == '-') | |
5607 | inst.operands[i].negative = 1; | |
5608 | } | |
5609 | } | |
09d92015 MM |
5610 | } |
5611 | } | |
8e560766 MGD |
5612 | else if (skip_past_char (&p, ':') == SUCCESS) |
5613 | { | |
5614 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5615 | before we get to see it here. This may be subject to change. */ | |
5616 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5617 | |
8e560766 MGD |
5618 | if (result != PARSE_OPERAND_SUCCESS) |
5619 | return result; | |
5620 | } | |
09d92015 | 5621 | |
c19d1205 | 5622 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5623 | { |
c19d1205 | 5624 | inst.error = _("']' expected"); |
4962c51a | 5625 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5626 | } |
5627 | ||
c19d1205 ZW |
5628 | if (skip_past_char (&p, '!') == SUCCESS) |
5629 | inst.operands[i].writeback = 1; | |
09d92015 | 5630 | |
c19d1205 | 5631 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5632 | { |
c19d1205 ZW |
5633 | if (skip_past_char (&p, '{') == SUCCESS) |
5634 | { | |
5635 | /* [Rn], {expr} - unindexed, with option */ | |
5636 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5637 | 0, 255, TRUE) == FAIL) |
4962c51a | 5638 | return PARSE_OPERAND_FAIL; |
09d92015 | 5639 | |
c19d1205 ZW |
5640 | if (skip_past_char (&p, '}') == FAIL) |
5641 | { | |
5642 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5643 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5644 | } |
5645 | if (inst.operands[i].preind) | |
5646 | { | |
5647 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5648 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5649 | } |
5650 | *str = p; | |
4962c51a | 5651 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5652 | } |
c19d1205 ZW |
5653 | else |
5654 | { | |
5655 | inst.operands[i].postind = 1; | |
5656 | inst.operands[i].writeback = 1; | |
09d92015 | 5657 | |
c19d1205 ZW |
5658 | if (inst.operands[i].preind) |
5659 | { | |
5660 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5661 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5662 | } |
09d92015 | 5663 | |
c19d1205 ZW |
5664 | if (*p == '+') p++; |
5665 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5666 | |
dcbf9037 | 5667 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5668 | { |
477330fc RM |
5669 | /* We might be using the immediate for alignment already. If we |
5670 | are, OR the register number into the low-order bits. */ | |
5671 | if (inst.operands[i].immisalign) | |
5672 | inst.operands[i].imm |= reg; | |
5673 | else | |
5674 | inst.operands[i].imm = reg; | |
c19d1205 | 5675 | inst.operands[i].immisreg = 1; |
a737bd4d | 5676 | |
c19d1205 ZW |
5677 | if (skip_past_comma (&p) == SUCCESS) |
5678 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5679 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5680 | } |
5681 | else | |
5682 | { | |
26d97720 | 5683 | char *q = p; |
c19d1205 ZW |
5684 | if (inst.operands[i].negative) |
5685 | { | |
5686 | inst.operands[i].negative = 0; | |
5687 | p--; | |
5688 | } | |
5689 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5690 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5691 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5692 | if (inst.reloc.exp.X_op == O_constant | |
5693 | && inst.reloc.exp.X_add_number == 0) | |
5694 | { | |
5695 | skip_whitespace (q); | |
5696 | if (*q == '#') | |
5697 | { | |
5698 | q++; | |
5699 | skip_whitespace (q); | |
5700 | } | |
5701 | if (*q == '-') | |
5702 | inst.operands[i].negative = 1; | |
5703 | } | |
c19d1205 ZW |
5704 | } |
5705 | } | |
a737bd4d NC |
5706 | } |
5707 | ||
c19d1205 ZW |
5708 | /* If at this point neither .preind nor .postind is set, we have a |
5709 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5710 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5711 | { | |
5712 | inst.operands[i].preind = 1; | |
5713 | inst.reloc.exp.X_op = O_constant; | |
5714 | inst.reloc.exp.X_add_number = 0; | |
5715 | } | |
5716 | *str = p; | |
4962c51a MS |
5717 | return PARSE_OPERAND_SUCCESS; |
5718 | } | |
5719 | ||
5720 | static int | |
5721 | parse_address (char **str, int i) | |
5722 | { | |
21d799b5 | 5723 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 5724 | ? SUCCESS : FAIL; |
4962c51a MS |
5725 | } |
5726 | ||
5727 | static parse_operand_result | |
5728 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5729 | { | |
5730 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5731 | } |
5732 | ||
b6895b4f PB |
5733 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5734 | static int | |
5735 | parse_half (char **str) | |
5736 | { | |
5737 | char * p; | |
5f4273c7 | 5738 | |
b6895b4f PB |
5739 | p = *str; |
5740 | skip_past_char (&p, '#'); | |
5f4273c7 | 5741 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5742 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5743 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5744 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5745 | ||
5746 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5747 | { | |
5748 | p += 9; | |
5f4273c7 | 5749 | skip_whitespace (p); |
b6895b4f PB |
5750 | } |
5751 | ||
5752 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5753 | return FAIL; | |
5754 | ||
5755 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5756 | { | |
5757 | if (inst.reloc.exp.X_op != O_constant) | |
5758 | { | |
5759 | inst.error = _("constant expression expected"); | |
5760 | return FAIL; | |
5761 | } | |
5762 | if (inst.reloc.exp.X_add_number < 0 | |
5763 | || inst.reloc.exp.X_add_number > 0xffff) | |
5764 | { | |
5765 | inst.error = _("immediate value out of range"); | |
5766 | return FAIL; | |
5767 | } | |
5768 | } | |
5769 | *str = p; | |
5770 | return SUCCESS; | |
5771 | } | |
5772 | ||
c19d1205 | 5773 | /* Miscellaneous. */ |
a737bd4d | 5774 | |
c19d1205 ZW |
5775 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5776 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5777 | static int | |
d2cd1205 | 5778 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5779 | { |
c19d1205 ZW |
5780 | char *p; |
5781 | unsigned long psr_field; | |
62b3e311 PB |
5782 | const struct asm_psr *psr; |
5783 | char *start; | |
d2cd1205 | 5784 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5785 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5786 | |
a4482bb6 NC |
5787 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5788 | be TRUE, but we want to ignore it in this case as we are building for any | |
5789 | CPU type, including non-m variants. */ | |
823d2571 | 5790 | if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) |
a4482bb6 NC |
5791 | m_profile = FALSE; |
5792 | ||
c19d1205 ZW |
5793 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5794 | feature for ease of use and backwards compatibility. */ | |
5795 | p = *str; | |
62b3e311 | 5796 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5797 | { |
5798 | if (m_profile) | |
5799 | goto unsupported_psr; | |
fa94de6b | 5800 | |
d2cd1205 JB |
5801 | psr_field = SPSR_BIT; |
5802 | } | |
5803 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5804 | { | |
5805 | if (m_profile) | |
5806 | goto unsupported_psr; | |
5807 | ||
5808 | psr_field = 0; | |
5809 | } | |
5810 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5811 | { | |
5812 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5813 | and ARMv7-R architecture CPUs. */ | |
5814 | is_apsr = TRUE; | |
5815 | psr_field = 0; | |
5816 | } | |
5817 | else if (m_profile) | |
62b3e311 PB |
5818 | { |
5819 | start = p; | |
5820 | do | |
5821 | p++; | |
5822 | while (ISALNUM (*p) || *p == '_'); | |
5823 | ||
d2cd1205 JB |
5824 | if (strncasecmp (start, "iapsr", 5) == 0 |
5825 | || strncasecmp (start, "eapsr", 5) == 0 | |
5826 | || strncasecmp (start, "xpsr", 4) == 0 | |
5827 | || strncasecmp (start, "psr", 3) == 0) | |
5828 | p = start + strcspn (start, "rR") + 1; | |
5829 | ||
21d799b5 | 5830 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 5831 | p - start); |
d2cd1205 | 5832 | |
62b3e311 PB |
5833 | if (!psr) |
5834 | return FAIL; | |
09d92015 | 5835 | |
d2cd1205 JB |
5836 | /* If APSR is being written, a bitfield may be specified. Note that |
5837 | APSR itself is handled above. */ | |
5838 | if (psr->field <= 3) | |
5839 | { | |
5840 | psr_field = psr->field; | |
5841 | is_apsr = TRUE; | |
5842 | goto check_suffix; | |
5843 | } | |
5844 | ||
62b3e311 | 5845 | *str = p; |
d2cd1205 JB |
5846 | /* M-profile MSR instructions have the mask field set to "10", except |
5847 | *PSR variants which modify APSR, which may use a different mask (and | |
5848 | have been handled already). Do that by setting the PSR_f field | |
5849 | here. */ | |
5850 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5851 | } |
d2cd1205 JB |
5852 | else |
5853 | goto unsupported_psr; | |
09d92015 | 5854 | |
62b3e311 | 5855 | p += 4; |
d2cd1205 | 5856 | check_suffix: |
c19d1205 ZW |
5857 | if (*p == '_') |
5858 | { | |
5859 | /* A suffix follows. */ | |
c19d1205 ZW |
5860 | p++; |
5861 | start = p; | |
a737bd4d | 5862 | |
c19d1205 ZW |
5863 | do |
5864 | p++; | |
5865 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5866 | |
d2cd1205 JB |
5867 | if (is_apsr) |
5868 | { | |
5869 | /* APSR uses a notation for bits, rather than fields. */ | |
5870 | unsigned int nzcvq_bits = 0; | |
5871 | unsigned int g_bit = 0; | |
5872 | char *bit; | |
fa94de6b | 5873 | |
d2cd1205 JB |
5874 | for (bit = start; bit != p; bit++) |
5875 | { | |
5876 | switch (TOLOWER (*bit)) | |
477330fc | 5877 | { |
d2cd1205 JB |
5878 | case 'n': |
5879 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5880 | break; | |
5881 | ||
5882 | case 'z': | |
5883 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5884 | break; | |
5885 | ||
5886 | case 'c': | |
5887 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5888 | break; | |
5889 | ||
5890 | case 'v': | |
5891 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5892 | break; | |
fa94de6b | 5893 | |
d2cd1205 JB |
5894 | case 'q': |
5895 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5896 | break; | |
fa94de6b | 5897 | |
d2cd1205 JB |
5898 | case 'g': |
5899 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5900 | break; | |
fa94de6b | 5901 | |
d2cd1205 JB |
5902 | default: |
5903 | inst.error = _("unexpected bit specified after APSR"); | |
5904 | return FAIL; | |
5905 | } | |
5906 | } | |
fa94de6b | 5907 | |
d2cd1205 JB |
5908 | if (nzcvq_bits == 0x1f) |
5909 | psr_field |= PSR_f; | |
fa94de6b | 5910 | |
d2cd1205 JB |
5911 | if (g_bit == 0x1) |
5912 | { | |
5913 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 5914 | { |
d2cd1205 JB |
5915 | inst.error = _("selected processor does not " |
5916 | "support DSP extension"); | |
5917 | return FAIL; | |
5918 | } | |
5919 | ||
5920 | psr_field |= PSR_s; | |
5921 | } | |
fa94de6b | 5922 | |
d2cd1205 JB |
5923 | if ((nzcvq_bits & 0x20) != 0 |
5924 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5925 | || (g_bit & 0x2) != 0) | |
5926 | { | |
5927 | inst.error = _("bad bitmask specified after APSR"); | |
5928 | return FAIL; | |
5929 | } | |
5930 | } | |
5931 | else | |
477330fc | 5932 | { |
d2cd1205 | 5933 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 5934 | p - start); |
d2cd1205 | 5935 | if (!psr) |
477330fc | 5936 | goto error; |
a737bd4d | 5937 | |
d2cd1205 JB |
5938 | psr_field |= psr->field; |
5939 | } | |
a737bd4d | 5940 | } |
c19d1205 | 5941 | else |
a737bd4d | 5942 | { |
c19d1205 ZW |
5943 | if (ISALNUM (*p)) |
5944 | goto error; /* Garbage after "[CS]PSR". */ | |
5945 | ||
d2cd1205 | 5946 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 5947 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
5948 | if (is_apsr && lhs) |
5949 | { | |
5950 | psr_field |= PSR_f; | |
5951 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5952 | "deprecated")); | |
5953 | } | |
5954 | else if (!m_profile) | |
5955 | /* These bits are never right for M-profile devices: don't set them | |
5956 | (only code paths which read/write APSR reach here). */ | |
5957 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5958 | } |
c19d1205 ZW |
5959 | *str = p; |
5960 | return psr_field; | |
a737bd4d | 5961 | |
d2cd1205 JB |
5962 | unsupported_psr: |
5963 | inst.error = _("selected processor does not support requested special " | |
5964 | "purpose register"); | |
5965 | return FAIL; | |
5966 | ||
c19d1205 ZW |
5967 | error: |
5968 | inst.error = _("flag for {c}psr instruction expected"); | |
5969 | return FAIL; | |
a737bd4d NC |
5970 | } |
5971 | ||
c19d1205 ZW |
5972 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5973 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5974 | |
c19d1205 ZW |
5975 | static int |
5976 | parse_cps_flags (char **str) | |
a737bd4d | 5977 | { |
c19d1205 ZW |
5978 | int val = 0; |
5979 | int saw_a_flag = 0; | |
5980 | char *s = *str; | |
a737bd4d | 5981 | |
c19d1205 ZW |
5982 | for (;;) |
5983 | switch (*s++) | |
5984 | { | |
5985 | case '\0': case ',': | |
5986 | goto done; | |
a737bd4d | 5987 | |
c19d1205 ZW |
5988 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5989 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5990 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5991 | |
c19d1205 ZW |
5992 | default: |
5993 | inst.error = _("unrecognized CPS flag"); | |
5994 | return FAIL; | |
5995 | } | |
a737bd4d | 5996 | |
c19d1205 ZW |
5997 | done: |
5998 | if (saw_a_flag == 0) | |
a737bd4d | 5999 | { |
c19d1205 ZW |
6000 | inst.error = _("missing CPS flags"); |
6001 | return FAIL; | |
a737bd4d | 6002 | } |
a737bd4d | 6003 | |
c19d1205 ZW |
6004 | *str = s - 1; |
6005 | return val; | |
a737bd4d NC |
6006 | } |
6007 | ||
c19d1205 ZW |
6008 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
6009 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
6010 | |
6011 | static int | |
c19d1205 | 6012 | parse_endian_specifier (char **str) |
a737bd4d | 6013 | { |
c19d1205 ZW |
6014 | int little_endian; |
6015 | char *s = *str; | |
a737bd4d | 6016 | |
c19d1205 ZW |
6017 | if (strncasecmp (s, "BE", 2)) |
6018 | little_endian = 0; | |
6019 | else if (strncasecmp (s, "LE", 2)) | |
6020 | little_endian = 1; | |
6021 | else | |
a737bd4d | 6022 | { |
c19d1205 | 6023 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6024 | return FAIL; |
6025 | } | |
6026 | ||
c19d1205 | 6027 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 6028 | { |
c19d1205 | 6029 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6030 | return FAIL; |
6031 | } | |
6032 | ||
c19d1205 ZW |
6033 | *str = s + 2; |
6034 | return little_endian; | |
6035 | } | |
a737bd4d | 6036 | |
c19d1205 ZW |
6037 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
6038 | value suitable for poking into the rotate field of an sxt or sxta | |
6039 | instruction, or FAIL on error. */ | |
6040 | ||
6041 | static int | |
6042 | parse_ror (char **str) | |
6043 | { | |
6044 | int rot; | |
6045 | char *s = *str; | |
6046 | ||
6047 | if (strncasecmp (s, "ROR", 3) == 0) | |
6048 | s += 3; | |
6049 | else | |
a737bd4d | 6050 | { |
c19d1205 | 6051 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6052 | return FAIL; |
6053 | } | |
c19d1205 ZW |
6054 | |
6055 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6056 | return FAIL; | |
6057 | ||
6058 | switch (rot) | |
a737bd4d | 6059 | { |
c19d1205 ZW |
6060 | case 0: *str = s; return 0x0; |
6061 | case 8: *str = s; return 0x1; | |
6062 | case 16: *str = s; return 0x2; | |
6063 | case 24: *str = s; return 0x3; | |
6064 | ||
6065 | default: | |
6066 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6067 | return FAIL; |
6068 | } | |
c19d1205 | 6069 | } |
a737bd4d | 6070 | |
c19d1205 ZW |
6071 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6072 | range 0 .. 14, or FAIL. */ | |
6073 | static int | |
6074 | parse_cond (char **str) | |
6075 | { | |
c462b453 | 6076 | char *q; |
c19d1205 | 6077 | const struct asm_cond *c; |
c462b453 PB |
6078 | int n; |
6079 | /* Condition codes are always 2 characters, so matching up to | |
6080 | 3 characters is sufficient. */ | |
6081 | char cond[3]; | |
a737bd4d | 6082 | |
c462b453 PB |
6083 | q = *str; |
6084 | n = 0; | |
6085 | while (ISALPHA (*q) && n < 3) | |
6086 | { | |
e07e6e58 | 6087 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6088 | q++; |
6089 | n++; | |
6090 | } | |
a737bd4d | 6091 | |
21d799b5 | 6092 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6093 | if (!c) |
a737bd4d | 6094 | { |
c19d1205 | 6095 | inst.error = _("condition required"); |
a737bd4d NC |
6096 | return FAIL; |
6097 | } | |
6098 | ||
c19d1205 ZW |
6099 | *str = q; |
6100 | return c->value; | |
6101 | } | |
6102 | ||
e797f7e0 MGD |
6103 | /* If the given feature available in the selected CPU, mark it as used. |
6104 | Returns TRUE iff feature is available. */ | |
6105 | static bfd_boolean | |
6106 | mark_feature_used (const arm_feature_set *feature) | |
6107 | { | |
6108 | /* Ensure the option is valid on the current architecture. */ | |
6109 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
6110 | return FALSE; | |
6111 | ||
6112 | /* Add the appropriate architecture feature for the barrier option used. | |
6113 | */ | |
6114 | if (thumb_mode) | |
6115 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
6116 | else | |
6117 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
6118 | ||
6119 | return TRUE; | |
6120 | } | |
6121 | ||
62b3e311 PB |
6122 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6123 | option, or FAIL. */ | |
6124 | static int | |
6125 | parse_barrier (char **str) | |
6126 | { | |
6127 | char *p, *q; | |
6128 | const struct asm_barrier_opt *o; | |
6129 | ||
6130 | p = q = *str; | |
6131 | while (ISALPHA (*q)) | |
6132 | q++; | |
6133 | ||
21d799b5 | 6134 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6135 | q - p); |
62b3e311 PB |
6136 | if (!o) |
6137 | return FAIL; | |
6138 | ||
e797f7e0 MGD |
6139 | if (!mark_feature_used (&o->arch)) |
6140 | return FAIL; | |
6141 | ||
62b3e311 PB |
6142 | *str = q; |
6143 | return o->value; | |
6144 | } | |
6145 | ||
92e90b6e PB |
6146 | /* Parse the operands of a table branch instruction. Similar to a memory |
6147 | operand. */ | |
6148 | static int | |
6149 | parse_tb (char **str) | |
6150 | { | |
6151 | char * p = *str; | |
6152 | int reg; | |
6153 | ||
6154 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6155 | { |
6156 | inst.error = _("'[' expected"); | |
6157 | return FAIL; | |
6158 | } | |
92e90b6e | 6159 | |
dcbf9037 | 6160 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6161 | { |
6162 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6163 | return FAIL; | |
6164 | } | |
6165 | inst.operands[0].reg = reg; | |
6166 | ||
6167 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6168 | { |
6169 | inst.error = _("',' expected"); | |
6170 | return FAIL; | |
6171 | } | |
5f4273c7 | 6172 | |
dcbf9037 | 6173 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6174 | { |
6175 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6176 | return FAIL; | |
6177 | } | |
6178 | inst.operands[0].imm = reg; | |
6179 | ||
6180 | if (skip_past_comma (&p) == SUCCESS) | |
6181 | { | |
6182 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6183 | return FAIL; | |
6184 | if (inst.reloc.exp.X_add_number != 1) | |
6185 | { | |
6186 | inst.error = _("invalid shift"); | |
6187 | return FAIL; | |
6188 | } | |
6189 | inst.operands[0].shifted = 1; | |
6190 | } | |
6191 | ||
6192 | if (skip_past_char (&p, ']') == FAIL) | |
6193 | { | |
6194 | inst.error = _("']' expected"); | |
6195 | return FAIL; | |
6196 | } | |
6197 | *str = p; | |
6198 | return SUCCESS; | |
6199 | } | |
6200 | ||
5287ad62 JB |
6201 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6202 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6203 | Up to four operands may be read; this function handles setting the |
6204 | ".present" field for each read operand itself. | |
5287ad62 JB |
6205 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6206 | else returns FAIL. */ | |
6207 | ||
6208 | static int | |
6209 | parse_neon_mov (char **str, int *which_operand) | |
6210 | { | |
6211 | int i = *which_operand, val; | |
6212 | enum arm_reg_type rtype; | |
6213 | char *ptr = *str; | |
dcbf9037 | 6214 | struct neon_type_el optype; |
5f4273c7 | 6215 | |
dcbf9037 | 6216 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
6217 | { |
6218 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6219 | inst.operands[i].reg = val; | |
6220 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6221 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6222 | inst.operands[i++].present = 1; |
6223 | ||
6224 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6225 | goto wanted_comma; |
5f4273c7 | 6226 | |
dcbf9037 | 6227 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6228 | goto wanted_arm; |
5f4273c7 | 6229 | |
5287ad62 JB |
6230 | inst.operands[i].reg = val; |
6231 | inst.operands[i].isreg = 1; | |
6232 | inst.operands[i].present = 1; | |
6233 | } | |
037e8744 | 6234 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
477330fc | 6235 | != FAIL) |
5287ad62 JB |
6236 | { |
6237 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6238 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6239 | goto wanted_comma; |
5f4273c7 | 6240 | |
5287ad62 JB |
6241 | inst.operands[i].reg = val; |
6242 | inst.operands[i].isreg = 1; | |
6243 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6244 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6245 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6246 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6247 | inst.operands[i++].present = 1; |
6248 | ||
dcbf9037 | 6249 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6250 | { |
6251 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6252 | Case 13: VMOV <Sd>, <Rm> */ | |
6253 | inst.operands[i].reg = val; | |
6254 | inst.operands[i].isreg = 1; | |
6255 | inst.operands[i].present = 1; | |
6256 | ||
6257 | if (rtype == REG_TYPE_NQ) | |
6258 | { | |
6259 | first_error (_("can't use Neon quad register here")); | |
6260 | return FAIL; | |
6261 | } | |
6262 | else if (rtype != REG_TYPE_VFS) | |
6263 | { | |
6264 | i++; | |
6265 | if (skip_past_comma (&ptr) == FAIL) | |
6266 | goto wanted_comma; | |
6267 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6268 | goto wanted_arm; | |
6269 | inst.operands[i].reg = val; | |
6270 | inst.operands[i].isreg = 1; | |
6271 | inst.operands[i].present = 1; | |
6272 | } | |
6273 | } | |
037e8744 | 6274 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
477330fc RM |
6275 | &optype)) != FAIL) |
6276 | { | |
6277 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6278 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6279 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6280 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6281 | ||
6282 | inst.operands[i].reg = val; | |
6283 | inst.operands[i].isreg = 1; | |
6284 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6285 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6286 | inst.operands[i].isvec = 1; | |
6287 | inst.operands[i].vectype = optype; | |
6288 | inst.operands[i].present = 1; | |
6289 | ||
6290 | if (skip_past_comma (&ptr) == SUCCESS) | |
6291 | { | |
6292 | /* Case 15. */ | |
6293 | i++; | |
6294 | ||
6295 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6296 | goto wanted_arm; | |
6297 | ||
6298 | inst.operands[i].reg = val; | |
6299 | inst.operands[i].isreg = 1; | |
6300 | inst.operands[i++].present = 1; | |
6301 | ||
6302 | if (skip_past_comma (&ptr) == FAIL) | |
6303 | goto wanted_comma; | |
6304 | ||
6305 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6306 | goto wanted_arm; | |
6307 | ||
6308 | inst.operands[i].reg = val; | |
6309 | inst.operands[i].isreg = 1; | |
6310 | inst.operands[i].present = 1; | |
6311 | } | |
6312 | } | |
4641781c | 6313 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6314 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6315 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6316 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6317 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6318 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6319 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6320 | == SUCCESS) | |
477330fc RM |
6321 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6322 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6323 | ; | |
5287ad62 | 6324 | else |
477330fc RM |
6325 | { |
6326 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6327 | return FAIL; | |
6328 | } | |
5287ad62 | 6329 | } |
dcbf9037 | 6330 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
6331 | { |
6332 | /* Cases 6, 7. */ | |
6333 | inst.operands[i].reg = val; | |
6334 | inst.operands[i].isreg = 1; | |
6335 | inst.operands[i++].present = 1; | |
5f4273c7 | 6336 | |
5287ad62 | 6337 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6338 | goto wanted_comma; |
5f4273c7 | 6339 | |
dcbf9037 | 6340 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
477330fc RM |
6341 | { |
6342 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6343 | inst.operands[i].reg = val; | |
6344 | inst.operands[i].isscalar = 1; | |
6345 | inst.operands[i].present = 1; | |
6346 | inst.operands[i].vectype = optype; | |
6347 | } | |
dcbf9037 | 6348 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6349 | { |
6350 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
6351 | inst.operands[i].reg = val; | |
6352 | inst.operands[i].isreg = 1; | |
6353 | inst.operands[i++].present = 1; | |
6354 | ||
6355 | if (skip_past_comma (&ptr) == FAIL) | |
6356 | goto wanted_comma; | |
6357 | ||
6358 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
6359 | == FAIL) | |
6360 | { | |
6361 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); | |
6362 | return FAIL; | |
6363 | } | |
6364 | ||
6365 | inst.operands[i].reg = val; | |
6366 | inst.operands[i].isreg = 1; | |
6367 | inst.operands[i].isvec = 1; | |
6368 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6369 | inst.operands[i].vectype = optype; | |
6370 | inst.operands[i].present = 1; | |
6371 | ||
6372 | if (rtype == REG_TYPE_VFS) | |
6373 | { | |
6374 | /* Case 14. */ | |
6375 | i++; | |
6376 | if (skip_past_comma (&ptr) == FAIL) | |
6377 | goto wanted_comma; | |
6378 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6379 | &optype)) == FAIL) | |
6380 | { | |
6381 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6382 | return FAIL; | |
6383 | } | |
6384 | inst.operands[i].reg = val; | |
6385 | inst.operands[i].isreg = 1; | |
6386 | inst.operands[i].isvec = 1; | |
6387 | inst.operands[i].issingle = 1; | |
6388 | inst.operands[i].vectype = optype; | |
6389 | inst.operands[i].present = 1; | |
6390 | } | |
6391 | } | |
037e8744 | 6392 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6393 | != FAIL) |
6394 | { | |
6395 | /* Case 13. */ | |
6396 | inst.operands[i].reg = val; | |
6397 | inst.operands[i].isreg = 1; | |
6398 | inst.operands[i].isvec = 1; | |
6399 | inst.operands[i].issingle = 1; | |
6400 | inst.operands[i].vectype = optype; | |
6401 | inst.operands[i].present = 1; | |
6402 | } | |
5287ad62 JB |
6403 | } |
6404 | else | |
6405 | { | |
dcbf9037 | 6406 | first_error (_("parse error")); |
5287ad62 JB |
6407 | return FAIL; |
6408 | } | |
6409 | ||
6410 | /* Successfully parsed the operands. Update args. */ | |
6411 | *which_operand = i; | |
6412 | *str = ptr; | |
6413 | return SUCCESS; | |
6414 | ||
5f4273c7 | 6415 | wanted_comma: |
dcbf9037 | 6416 | first_error (_("expected comma")); |
5287ad62 | 6417 | return FAIL; |
5f4273c7 NC |
6418 | |
6419 | wanted_arm: | |
dcbf9037 | 6420 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6421 | return FAIL; |
5287ad62 JB |
6422 | } |
6423 | ||
5be8be5d DG |
6424 | /* Use this macro when the operand constraints are different |
6425 | for ARM and THUMB (e.g. ldrd). */ | |
6426 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6427 | ((arm_operand) | ((thumb_operand) << 16)) | |
6428 | ||
c19d1205 ZW |
6429 | /* Matcher codes for parse_operands. */ |
6430 | enum operand_parse_code | |
6431 | { | |
6432 | OP_stop, /* end of line */ | |
6433 | ||
6434 | OP_RR, /* ARM register */ | |
6435 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6436 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6437 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6438 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6439 | optional trailing ! */ |
c19d1205 ZW |
6440 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6441 | OP_RCP, /* Coprocessor number */ | |
6442 | OP_RCN, /* Coprocessor register */ | |
6443 | OP_RF, /* FPA register */ | |
6444 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6445 | OP_RVD, /* VFP double precision register (0..15) */ |
6446 | OP_RND, /* Neon double precision register (0..31) */ | |
6447 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6448 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6449 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6450 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6451 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6452 | OP_RVC, /* VFP control register */ |
6453 | OP_RMF, /* Maverick F register */ | |
6454 | OP_RMD, /* Maverick D register */ | |
6455 | OP_RMFX, /* Maverick FX register */ | |
6456 | OP_RMDX, /* Maverick DX register */ | |
6457 | OP_RMAX, /* Maverick AX register */ | |
6458 | OP_RMDS, /* Maverick DSPSC register */ | |
6459 | OP_RIWR, /* iWMMXt wR register */ | |
6460 | OP_RIWC, /* iWMMXt wC register */ | |
6461 | OP_RIWG, /* iWMMXt wCG register */ | |
6462 | OP_RXA, /* XScale accumulator register */ | |
6463 | ||
6464 | OP_REGLST, /* ARM register list */ | |
6465 | OP_VRSLST, /* VFP single-precision register list */ | |
6466 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6467 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6468 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6469 | OP_NSTRLST, /* Neon element/structure list */ | |
6470 | ||
5287ad62 | 6471 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6472 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 6473 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
5287ad62 | 6474 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6475 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6476 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6477 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6478 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6479 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6480 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6481 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6482 | |
6483 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6484 | OP_I7, /* immediate value 0 .. 7 */ |
6485 | OP_I15, /* 0 .. 15 */ | |
6486 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6487 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6488 | OP_I31, /* 0 .. 31 */ |
6489 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6490 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6491 | OP_I32z, /* 0 .. 32 */ |
6492 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6493 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6494 | OP_I64, /* 1 .. 64 */ |
6495 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6496 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6497 | |
6498 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6499 | OP_I7b, /* 0 .. 7 */ | |
6500 | OP_I15b, /* 0 .. 15 */ | |
6501 | OP_I31b, /* 0 .. 31 */ | |
6502 | ||
6503 | OP_SH, /* shifter operand */ | |
4962c51a | 6504 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6505 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6506 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6507 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6508 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6509 | OP_EXP, /* arbitrary expression */ |
6510 | OP_EXPi, /* same, with optional immediate prefix */ | |
6511 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6512 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6513 | |
6514 | OP_CPSF, /* CPS flags */ | |
6515 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6516 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6517 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6518 | OP_COND, /* conditional code */ |
92e90b6e | 6519 | OP_TB, /* Table branch. */ |
c19d1205 | 6520 | |
037e8744 JB |
6521 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6522 | ||
c19d1205 ZW |
6523 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6524 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6525 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6526 | OP_RF_IF, /* FPA register or immediate */ | |
6527 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6528 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6529 | |
6530 | /* Optional operands. */ | |
6531 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6532 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6533 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6534 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6535 | OP_oIffffb, /* 0 .. 65535 */ |
6536 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6537 | ||
6538 | OP_oRR, /* ARM register */ | |
6539 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6540 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6541 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6542 | OP_oRND, /* Optional Neon double precision register */ |
6543 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6544 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6545 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6546 | OP_oSHll, /* LSL immediate */ |
6547 | OP_oSHar, /* ASR immediate */ | |
6548 | OP_oSHllar, /* LSL or ASR immediate */ | |
6549 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6550 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6551 | |
5be8be5d DG |
6552 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6553 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6554 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6555 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6556 | ||
c19d1205 ZW |
6557 | OP_FIRST_OPTIONAL = OP_oI7b |
6558 | }; | |
a737bd4d | 6559 | |
c19d1205 ZW |
6560 | /* Generic instruction operand parser. This does no encoding and no |
6561 | semantic validation; it merely squirrels values away in the inst | |
6562 | structure. Returns SUCCESS or FAIL depending on whether the | |
6563 | specified grammar matched. */ | |
6564 | static int | |
5be8be5d | 6565 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6566 | { |
5be8be5d | 6567 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6568 | char *backtrack_pos = 0; |
6569 | const char *backtrack_error = 0; | |
99aad254 | 6570 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6571 | enum arm_reg_type rtype; |
4962c51a | 6572 | parse_operand_result result; |
5be8be5d | 6573 | unsigned int op_parse_code; |
c19d1205 | 6574 | |
e07e6e58 NC |
6575 | #define po_char_or_fail(chr) \ |
6576 | do \ | |
6577 | { \ | |
6578 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 6579 | goto bad_args; \ |
e07e6e58 NC |
6580 | } \ |
6581 | while (0) | |
c19d1205 | 6582 | |
e07e6e58 NC |
6583 | #define po_reg_or_fail(regtype) \ |
6584 | do \ | |
dcbf9037 | 6585 | { \ |
e07e6e58 | 6586 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 6587 | & inst.operands[i].vectype); \ |
e07e6e58 | 6588 | if (val == FAIL) \ |
477330fc RM |
6589 | { \ |
6590 | first_error (_(reg_expected_msgs[regtype])); \ | |
6591 | goto failure; \ | |
6592 | } \ | |
e07e6e58 NC |
6593 | inst.operands[i].reg = val; \ |
6594 | inst.operands[i].isreg = 1; \ | |
6595 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6596 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6597 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
6598 | || rtype == REG_TYPE_VFD \ |
6599 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6600 | } \ |
e07e6e58 NC |
6601 | while (0) |
6602 | ||
6603 | #define po_reg_or_goto(regtype, label) \ | |
6604 | do \ | |
6605 | { \ | |
6606 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6607 | & inst.operands[i].vectype); \ | |
6608 | if (val == FAIL) \ | |
6609 | goto label; \ | |
dcbf9037 | 6610 | \ |
e07e6e58 NC |
6611 | inst.operands[i].reg = val; \ |
6612 | inst.operands[i].isreg = 1; \ | |
6613 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6614 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6615 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 6616 | || rtype == REG_TYPE_VFD \ |
e07e6e58 NC |
6617 | || rtype == REG_TYPE_NQ); \ |
6618 | } \ | |
6619 | while (0) | |
6620 | ||
6621 | #define po_imm_or_fail(min, max, popt) \ | |
6622 | do \ | |
6623 | { \ | |
6624 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6625 | goto failure; \ | |
6626 | inst.operands[i].imm = val; \ | |
6627 | } \ | |
6628 | while (0) | |
6629 | ||
6630 | #define po_scalar_or_goto(elsz, label) \ | |
6631 | do \ | |
6632 | { \ | |
6633 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6634 | if (val == FAIL) \ | |
6635 | goto label; \ | |
6636 | inst.operands[i].reg = val; \ | |
6637 | inst.operands[i].isscalar = 1; \ | |
6638 | } \ | |
6639 | while (0) | |
6640 | ||
6641 | #define po_misc_or_fail(expr) \ | |
6642 | do \ | |
6643 | { \ | |
6644 | if (expr) \ | |
6645 | goto failure; \ | |
6646 | } \ | |
6647 | while (0) | |
6648 | ||
6649 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6650 | do \ | |
6651 | { \ | |
6652 | result = expr; \ | |
6653 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6654 | backtrack_pos = 0; \ | |
6655 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6656 | goto failure; \ | |
6657 | } \ | |
6658 | while (0) | |
4962c51a | 6659 | |
52e7f43d RE |
6660 | #define po_barrier_or_imm(str) \ |
6661 | do \ | |
6662 | { \ | |
6663 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
6664 | if (val == FAIL && ! ISALPHA (*str)) \ |
6665 | goto immediate; \ | |
6666 | if (val == FAIL \ | |
6667 | /* ISB can only take SY as an option. */ \ | |
6668 | || ((inst.instruction & 0xf0) == 0x60 \ | |
6669 | && val != 0xf)) \ | |
52e7f43d | 6670 | { \ |
ccb84d65 JB |
6671 | inst.error = _("invalid barrier type"); \ |
6672 | backtrack_pos = 0; \ | |
6673 | goto failure; \ | |
52e7f43d RE |
6674 | } \ |
6675 | } \ | |
6676 | while (0) | |
6677 | ||
c19d1205 ZW |
6678 | skip_whitespace (str); |
6679 | ||
6680 | for (i = 0; upat[i] != OP_stop; i++) | |
6681 | { | |
5be8be5d DG |
6682 | op_parse_code = upat[i]; |
6683 | if (op_parse_code >= 1<<16) | |
6684 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6685 | : (op_parse_code & ((1<<16)-1)); | |
6686 | ||
6687 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6688 | { |
6689 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6690 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6691 | backtrack_pos = str; |
6692 | backtrack_error = inst.error; | |
6693 | backtrack_index = i; | |
6694 | } | |
6695 | ||
b6702015 | 6696 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6697 | po_char_or_fail (','); |
6698 | ||
5be8be5d | 6699 | switch (op_parse_code) |
c19d1205 ZW |
6700 | { |
6701 | /* Registers */ | |
6702 | case OP_oRRnpc: | |
5be8be5d | 6703 | case OP_oRRnpcsp: |
c19d1205 | 6704 | case OP_RRnpc: |
5be8be5d | 6705 | case OP_RRnpcsp: |
c19d1205 ZW |
6706 | case OP_oRR: |
6707 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6708 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6709 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6710 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6711 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6712 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 6713 | case OP_oRND: |
5287ad62 | 6714 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
6715 | case OP_RVC: |
6716 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6717 | break; | |
6718 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6719 | coproc_reg: | |
6720 | po_reg_or_fail (REG_TYPE_CN); | |
6721 | break; | |
c19d1205 ZW |
6722 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6723 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6724 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6725 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6726 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6727 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6728 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6729 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6730 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6731 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 6732 | case OP_oRNQ: |
5287ad62 | 6733 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
477330fc | 6734 | case OP_oRNDQ: |
5287ad62 | 6735 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
477330fc RM |
6736 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6737 | case OP_oRNSDQ: | |
6738 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
6739 | ||
6740 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6741 | scalars are accepted here, so deal with those in later code. */ | |
6742 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6743 | ||
6744 | case OP_RNDQ_I0: | |
6745 | { | |
6746 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6747 | break; | |
6748 | try_imm0: | |
6749 | po_imm_or_fail (0, 0, TRUE); | |
6750 | } | |
6751 | break; | |
6752 | ||
6753 | case OP_RVSD_I0: | |
6754 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6755 | break; | |
6756 | ||
aacf0b33 KT |
6757 | case OP_RSVD_FI0: |
6758 | { | |
6759 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
6760 | break; | |
6761 | try_ifimm0: | |
6762 | if (parse_ifimm_zero (&str)) | |
6763 | inst.operands[i].imm = 0; | |
6764 | else | |
6765 | { | |
6766 | inst.error | |
6767 | = _("only floating point zero is allowed as immediate value"); | |
6768 | goto failure; | |
6769 | } | |
6770 | } | |
6771 | break; | |
6772 | ||
477330fc RM |
6773 | case OP_RR_RNSC: |
6774 | { | |
6775 | po_scalar_or_goto (8, try_rr); | |
6776 | break; | |
6777 | try_rr: | |
6778 | po_reg_or_fail (REG_TYPE_RN); | |
6779 | } | |
6780 | break; | |
6781 | ||
6782 | case OP_RNSDQ_RNSC: | |
6783 | { | |
6784 | po_scalar_or_goto (8, try_nsdq); | |
6785 | break; | |
6786 | try_nsdq: | |
6787 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6788 | } | |
6789 | break; | |
6790 | ||
6791 | case OP_RNDQ_RNSC: | |
6792 | { | |
6793 | po_scalar_or_goto (8, try_ndq); | |
6794 | break; | |
6795 | try_ndq: | |
6796 | po_reg_or_fail (REG_TYPE_NDQ); | |
6797 | } | |
6798 | break; | |
6799 | ||
6800 | case OP_RND_RNSC: | |
6801 | { | |
6802 | po_scalar_or_goto (8, try_vfd); | |
6803 | break; | |
6804 | try_vfd: | |
6805 | po_reg_or_fail (REG_TYPE_VFD); | |
6806 | } | |
6807 | break; | |
6808 | ||
6809 | case OP_VMOV: | |
6810 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6811 | not careful then bad things might happen. */ | |
6812 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6813 | break; | |
6814 | ||
6815 | case OP_RNDQ_Ibig: | |
6816 | { | |
6817 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
6818 | break; | |
6819 | try_immbig: | |
6820 | /* There's a possibility of getting a 64-bit immediate here, so | |
6821 | we need special handling. */ | |
8335d6aa JW |
6822 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
6823 | == FAIL) | |
477330fc RM |
6824 | { |
6825 | inst.error = _("immediate value is out of range"); | |
6826 | goto failure; | |
6827 | } | |
6828 | } | |
6829 | break; | |
6830 | ||
6831 | case OP_RNDQ_I63b: | |
6832 | { | |
6833 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6834 | break; | |
6835 | try_shimm: | |
6836 | po_imm_or_fail (0, 63, TRUE); | |
6837 | } | |
6838 | break; | |
c19d1205 ZW |
6839 | |
6840 | case OP_RRnpcb: | |
6841 | po_char_or_fail ('['); | |
6842 | po_reg_or_fail (REG_TYPE_RN); | |
6843 | po_char_or_fail (']'); | |
6844 | break; | |
a737bd4d | 6845 | |
55881a11 | 6846 | case OP_RRnpctw: |
c19d1205 | 6847 | case OP_RRw: |
b6702015 | 6848 | case OP_oRRw: |
c19d1205 ZW |
6849 | po_reg_or_fail (REG_TYPE_RN); |
6850 | if (skip_past_char (&str, '!') == SUCCESS) | |
6851 | inst.operands[i].writeback = 1; | |
6852 | break; | |
6853 | ||
6854 | /* Immediates */ | |
6855 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6856 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6857 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 6858 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6859 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6860 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 6861 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6862 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
6863 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6864 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6865 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6866 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6867 | |
6868 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6869 | case OP_oI7b: | |
6870 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6871 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6872 | case OP_oI31b: | |
6873 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
6874 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
6875 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
6876 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6877 | ||
6878 | /* Immediate variants */ | |
6879 | case OP_oI255c: | |
6880 | po_char_or_fail ('{'); | |
6881 | po_imm_or_fail (0, 255, TRUE); | |
6882 | po_char_or_fail ('}'); | |
6883 | break; | |
6884 | ||
6885 | case OP_I31w: | |
6886 | /* The expression parser chokes on a trailing !, so we have | |
6887 | to find it first and zap it. */ | |
6888 | { | |
6889 | char *s = str; | |
6890 | while (*s && *s != ',') | |
6891 | s++; | |
6892 | if (s[-1] == '!') | |
6893 | { | |
6894 | s[-1] = '\0'; | |
6895 | inst.operands[i].writeback = 1; | |
6896 | } | |
6897 | po_imm_or_fail (0, 31, TRUE); | |
6898 | if (str == s - 1) | |
6899 | str = s; | |
6900 | } | |
6901 | break; | |
6902 | ||
6903 | /* Expressions */ | |
6904 | case OP_EXPi: EXPi: | |
6905 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6906 | GE_OPT_PREFIX)); | |
6907 | break; | |
6908 | ||
6909 | case OP_EXP: | |
6910 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6911 | GE_NO_PREFIX)); | |
6912 | break; | |
6913 | ||
6914 | case OP_EXPr: EXPr: | |
6915 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6916 | GE_NO_PREFIX)); | |
6917 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6918 | { |
c19d1205 ZW |
6919 | val = parse_reloc (&str); |
6920 | if (val == -1) | |
6921 | { | |
6922 | inst.error = _("unrecognized relocation suffix"); | |
6923 | goto failure; | |
6924 | } | |
6925 | else if (val != BFD_RELOC_UNUSED) | |
6926 | { | |
6927 | inst.operands[i].imm = val; | |
6928 | inst.operands[i].hasreloc = 1; | |
6929 | } | |
a737bd4d | 6930 | } |
c19d1205 | 6931 | break; |
a737bd4d | 6932 | |
b6895b4f PB |
6933 | /* Operand for MOVW or MOVT. */ |
6934 | case OP_HALF: | |
6935 | po_misc_or_fail (parse_half (&str)); | |
6936 | break; | |
6937 | ||
e07e6e58 | 6938 | /* Register or expression. */ |
c19d1205 ZW |
6939 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6940 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6941 | |
e07e6e58 | 6942 | /* Register or immediate. */ |
c19d1205 ZW |
6943 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6944 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6945 | |
c19d1205 ZW |
6946 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6947 | IF: | |
6948 | if (!is_immediate_prefix (*str)) | |
6949 | goto bad_args; | |
6950 | str++; | |
6951 | val = parse_fpa_immediate (&str); | |
6952 | if (val == FAIL) | |
6953 | goto failure; | |
6954 | /* FPA immediates are encoded as registers 8-15. | |
6955 | parse_fpa_immediate has already applied the offset. */ | |
6956 | inst.operands[i].reg = val; | |
6957 | inst.operands[i].isreg = 1; | |
6958 | break; | |
09d92015 | 6959 | |
2d447fca JM |
6960 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6961 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6962 | ||
e07e6e58 | 6963 | /* Two kinds of register. */ |
c19d1205 ZW |
6964 | case OP_RIWR_RIWC: |
6965 | { | |
6966 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6967 | if (!rege |
6968 | || (rege->type != REG_TYPE_MMXWR | |
6969 | && rege->type != REG_TYPE_MMXWC | |
6970 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6971 | { |
6972 | inst.error = _("iWMMXt data or control register expected"); | |
6973 | goto failure; | |
6974 | } | |
6975 | inst.operands[i].reg = rege->number; | |
6976 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6977 | } | |
6978 | break; | |
09d92015 | 6979 | |
41adaa5c JM |
6980 | case OP_RIWC_RIWG: |
6981 | { | |
6982 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6983 | if (!rege | |
6984 | || (rege->type != REG_TYPE_MMXWC | |
6985 | && rege->type != REG_TYPE_MMXWCG)) | |
6986 | { | |
6987 | inst.error = _("iWMMXt control register expected"); | |
6988 | goto failure; | |
6989 | } | |
6990 | inst.operands[i].reg = rege->number; | |
6991 | inst.operands[i].isreg = 1; | |
6992 | } | |
6993 | break; | |
6994 | ||
c19d1205 ZW |
6995 | /* Misc */ |
6996 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6997 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6998 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6999 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
7000 | case OP_oBARRIER_I15: |
7001 | po_barrier_or_imm (str); break; | |
7002 | immediate: | |
7003 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 7004 | goto failure; |
52e7f43d | 7005 | break; |
c19d1205 | 7006 | |
fa94de6b | 7007 | case OP_wPSR: |
d2cd1205 | 7008 | case OP_rPSR: |
90ec0d68 MGD |
7009 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
7010 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
7011 | { | |
7012 | inst.error = _("Banked registers are not available with this " | |
7013 | "architecture."); | |
7014 | goto failure; | |
7015 | } | |
7016 | break; | |
d2cd1205 JB |
7017 | try_psr: |
7018 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
7019 | break; | |
037e8744 | 7020 | |
477330fc RM |
7021 | case OP_APSR_RR: |
7022 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
7023 | break; | |
7024 | try_apsr: | |
7025 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
7026 | instruction). */ | |
7027 | if (strncasecmp (str, "APSR_", 5) == 0) | |
7028 | { | |
7029 | unsigned found = 0; | |
7030 | str += 5; | |
7031 | while (found < 15) | |
7032 | switch (*str++) | |
7033 | { | |
7034 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
7035 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
7036 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
7037 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
7038 | default: found = 16; | |
7039 | } | |
7040 | if (found != 15) | |
7041 | goto failure; | |
7042 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
7043 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
7044 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
7045 | } |
7046 | else | |
7047 | goto failure; | |
7048 | break; | |
037e8744 | 7049 | |
92e90b6e PB |
7050 | case OP_TB: |
7051 | po_misc_or_fail (parse_tb (&str)); | |
7052 | break; | |
7053 | ||
e07e6e58 | 7054 | /* Register lists. */ |
c19d1205 ZW |
7055 | case OP_REGLST: |
7056 | val = parse_reg_list (&str); | |
7057 | if (*str == '^') | |
7058 | { | |
5e0d7f77 | 7059 | inst.operands[i].writeback = 1; |
c19d1205 ZW |
7060 | str++; |
7061 | } | |
7062 | break; | |
09d92015 | 7063 | |
c19d1205 | 7064 | case OP_VRSLST: |
5287ad62 | 7065 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 7066 | break; |
09d92015 | 7067 | |
c19d1205 | 7068 | case OP_VRDLST: |
5287ad62 | 7069 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 7070 | break; |
a737bd4d | 7071 | |
477330fc RM |
7072 | case OP_VRSDLST: |
7073 | /* Allow Q registers too. */ | |
7074 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7075 | REGLIST_NEON_D); | |
7076 | if (val == FAIL) | |
7077 | { | |
7078 | inst.error = NULL; | |
7079 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7080 | REGLIST_VFP_S); | |
7081 | inst.operands[i].issingle = 1; | |
7082 | } | |
7083 | break; | |
7084 | ||
7085 | case OP_NRDLST: | |
7086 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7087 | REGLIST_NEON_D); | |
7088 | break; | |
5287ad62 JB |
7089 | |
7090 | case OP_NSTRLST: | |
477330fc RM |
7091 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
7092 | &inst.operands[i].vectype); | |
7093 | break; | |
5287ad62 | 7094 | |
c19d1205 ZW |
7095 | /* Addressing modes */ |
7096 | case OP_ADDR: | |
7097 | po_misc_or_fail (parse_address (&str, i)); | |
7098 | break; | |
09d92015 | 7099 | |
4962c51a MS |
7100 | case OP_ADDRGLDR: |
7101 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7102 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7103 | break; |
7104 | ||
7105 | case OP_ADDRGLDRS: | |
7106 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7107 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7108 | break; |
7109 | ||
7110 | case OP_ADDRGLDC: | |
7111 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7112 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7113 | break; |
7114 | ||
c19d1205 ZW |
7115 | case OP_SH: |
7116 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7117 | break; | |
09d92015 | 7118 | |
4962c51a MS |
7119 | case OP_SHG: |
7120 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7121 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7122 | break; |
7123 | ||
c19d1205 ZW |
7124 | case OP_oSHll: |
7125 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7126 | break; | |
09d92015 | 7127 | |
c19d1205 ZW |
7128 | case OP_oSHar: |
7129 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7130 | break; | |
09d92015 | 7131 | |
c19d1205 ZW |
7132 | case OP_oSHllar: |
7133 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7134 | break; | |
09d92015 | 7135 | |
c19d1205 | 7136 | default: |
5be8be5d | 7137 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7138 | } |
09d92015 | 7139 | |
c19d1205 ZW |
7140 | /* Various value-based sanity checks and shared operations. We |
7141 | do not signal immediate failures for the register constraints; | |
7142 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7143 | switch (op_parse_code) |
c19d1205 ZW |
7144 | { |
7145 | case OP_oRRnpc: | |
7146 | case OP_RRnpc: | |
7147 | case OP_RRnpcb: | |
7148 | case OP_RRw: | |
b6702015 | 7149 | case OP_oRRw: |
c19d1205 ZW |
7150 | case OP_RRnpc_I0: |
7151 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7152 | inst.error = BAD_PC; | |
7153 | break; | |
09d92015 | 7154 | |
5be8be5d DG |
7155 | case OP_oRRnpcsp: |
7156 | case OP_RRnpcsp: | |
7157 | if (inst.operands[i].isreg) | |
7158 | { | |
7159 | if (inst.operands[i].reg == REG_PC) | |
7160 | inst.error = BAD_PC; | |
7161 | else if (inst.operands[i].reg == REG_SP) | |
7162 | inst.error = BAD_SP; | |
7163 | } | |
7164 | break; | |
7165 | ||
55881a11 | 7166 | case OP_RRnpctw: |
fa94de6b RM |
7167 | if (inst.operands[i].isreg |
7168 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7169 | && (inst.operands[i].writeback || thumb)) |
7170 | inst.error = BAD_PC; | |
7171 | break; | |
7172 | ||
c19d1205 ZW |
7173 | case OP_CPSF: |
7174 | case OP_ENDI: | |
7175 | case OP_oROR: | |
d2cd1205 JB |
7176 | case OP_wPSR: |
7177 | case OP_rPSR: | |
c19d1205 | 7178 | case OP_COND: |
52e7f43d | 7179 | case OP_oBARRIER_I15: |
c19d1205 ZW |
7180 | case OP_REGLST: |
7181 | case OP_VRSLST: | |
7182 | case OP_VRDLST: | |
477330fc RM |
7183 | case OP_VRSDLST: |
7184 | case OP_NRDLST: | |
7185 | case OP_NSTRLST: | |
c19d1205 ZW |
7186 | if (val == FAIL) |
7187 | goto failure; | |
7188 | inst.operands[i].imm = val; | |
7189 | break; | |
a737bd4d | 7190 | |
c19d1205 ZW |
7191 | default: |
7192 | break; | |
7193 | } | |
09d92015 | 7194 | |
c19d1205 ZW |
7195 | /* If we get here, this operand was successfully parsed. */ |
7196 | inst.operands[i].present = 1; | |
7197 | continue; | |
09d92015 | 7198 | |
c19d1205 | 7199 | bad_args: |
09d92015 | 7200 | inst.error = BAD_ARGS; |
c19d1205 ZW |
7201 | |
7202 | failure: | |
7203 | if (!backtrack_pos) | |
d252fdde PB |
7204 | { |
7205 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 7206 | default here just in case. */ |
d252fdde PB |
7207 | if (!inst.error) |
7208 | inst.error = _("syntax error"); | |
7209 | return FAIL; | |
7210 | } | |
c19d1205 ZW |
7211 | |
7212 | /* Do not backtrack over a trailing optional argument that | |
7213 | absorbed some text. We will only fail again, with the | |
7214 | 'garbage following instruction' error message, which is | |
7215 | probably less helpful than the current one. */ | |
7216 | if (backtrack_index == i && backtrack_pos != str | |
7217 | && upat[i+1] == OP_stop) | |
d252fdde PB |
7218 | { |
7219 | if (!inst.error) | |
7220 | inst.error = _("syntax error"); | |
7221 | return FAIL; | |
7222 | } | |
c19d1205 ZW |
7223 | |
7224 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
7225 | str = backtrack_pos; | |
7226 | inst.error = backtrack_error; | |
7227 | inst.operands[backtrack_index].present = 0; | |
7228 | i = backtrack_index; | |
7229 | backtrack_pos = 0; | |
09d92015 | 7230 | } |
09d92015 | 7231 | |
c19d1205 ZW |
7232 | /* Check that we have parsed all the arguments. */ |
7233 | if (*str != '\0' && !inst.error) | |
7234 | inst.error = _("garbage following instruction"); | |
09d92015 | 7235 | |
c19d1205 | 7236 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
7237 | } |
7238 | ||
c19d1205 ZW |
7239 | #undef po_char_or_fail |
7240 | #undef po_reg_or_fail | |
7241 | #undef po_reg_or_goto | |
7242 | #undef po_imm_or_fail | |
5287ad62 | 7243 | #undef po_scalar_or_fail |
52e7f43d | 7244 | #undef po_barrier_or_imm |
e07e6e58 | 7245 | |
c19d1205 | 7246 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
7247 | #define constraint(expr, err) \ |
7248 | do \ | |
c19d1205 | 7249 | { \ |
e07e6e58 NC |
7250 | if (expr) \ |
7251 | { \ | |
7252 | inst.error = err; \ | |
7253 | return; \ | |
7254 | } \ | |
c19d1205 | 7255 | } \ |
e07e6e58 | 7256 | while (0) |
c19d1205 | 7257 | |
fdfde340 JM |
7258 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
7259 | instructions are unpredictable if these registers are used. This | |
7260 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
7261 | #define reject_bad_reg(reg) \ | |
7262 | do \ | |
7263 | if (reg == REG_SP || reg == REG_PC) \ | |
7264 | { \ | |
7265 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
7266 | return; \ | |
7267 | } \ | |
7268 | while (0) | |
7269 | ||
94206790 MM |
7270 | /* If REG is R13 (the stack pointer), warn that its use is |
7271 | deprecated. */ | |
7272 | #define warn_deprecated_sp(reg) \ | |
7273 | do \ | |
7274 | if (warn_on_deprecated && reg == REG_SP) \ | |
5c3696f8 | 7275 | as_tsktsk (_("use of r13 is deprecated")); \ |
94206790 MM |
7276 | while (0) |
7277 | ||
c19d1205 ZW |
7278 | /* Functions for operand encoding. ARM, then Thumb. */ |
7279 | ||
d840c081 | 7280 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 ZW |
7281 | |
7282 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
7283 | return the encoded form. Otherwise, return FAIL. */ | |
7284 | ||
7285 | static unsigned int | |
7286 | encode_arm_immediate (unsigned int val) | |
09d92015 | 7287 | { |
c19d1205 ZW |
7288 | unsigned int a, i; |
7289 | ||
7290 | for (i = 0; i < 32; i += 2) | |
7291 | if ((a = rotate_left (val, i)) <= 0xff) | |
7292 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
7293 | ||
7294 | return FAIL; | |
09d92015 MM |
7295 | } |
7296 | ||
c19d1205 ZW |
7297 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
7298 | return the encoded form. Otherwise, return FAIL. */ | |
7299 | static unsigned int | |
7300 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 7301 | { |
c19d1205 | 7302 | unsigned int a, i; |
09d92015 | 7303 | |
9c3c69f2 | 7304 | if (val <= 0xff) |
c19d1205 | 7305 | return val; |
a737bd4d | 7306 | |
9c3c69f2 | 7307 | for (i = 1; i <= 24; i++) |
09d92015 | 7308 | { |
9c3c69f2 PB |
7309 | a = val >> i; |
7310 | if ((val & ~(0xff << i)) == 0) | |
7311 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 7312 | } |
a737bd4d | 7313 | |
c19d1205 ZW |
7314 | a = val & 0xff; |
7315 | if (val == ((a << 16) | a)) | |
7316 | return 0x100 | a; | |
7317 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
7318 | return 0x300 | a; | |
09d92015 | 7319 | |
c19d1205 ZW |
7320 | a = val & 0xff00; |
7321 | if (val == ((a << 16) | a)) | |
7322 | return 0x200 | (a >> 8); | |
a737bd4d | 7323 | |
c19d1205 | 7324 | return FAIL; |
09d92015 | 7325 | } |
5287ad62 | 7326 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
7327 | |
7328 | static void | |
5287ad62 JB |
7329 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
7330 | { | |
7331 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
7332 | && reg > 15) | |
7333 | { | |
b1cc4aeb | 7334 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
7335 | { |
7336 | if (thumb_mode) | |
7337 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
7338 | fpu_vfp_ext_d32); | |
7339 | else | |
7340 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
7341 | fpu_vfp_ext_d32); | |
7342 | } | |
5287ad62 | 7343 | else |
477330fc RM |
7344 | { |
7345 | first_error (_("D register out of range for selected VFP version")); | |
7346 | return; | |
7347 | } | |
5287ad62 JB |
7348 | } |
7349 | ||
c19d1205 | 7350 | switch (pos) |
09d92015 | 7351 | { |
c19d1205 ZW |
7352 | case VFP_REG_Sd: |
7353 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
7354 | break; | |
7355 | ||
7356 | case VFP_REG_Sn: | |
7357 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
7358 | break; | |
7359 | ||
7360 | case VFP_REG_Sm: | |
7361 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
7362 | break; | |
7363 | ||
5287ad62 JB |
7364 | case VFP_REG_Dd: |
7365 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
7366 | break; | |
5f4273c7 | 7367 | |
5287ad62 JB |
7368 | case VFP_REG_Dn: |
7369 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7370 | break; | |
5f4273c7 | 7371 | |
5287ad62 JB |
7372 | case VFP_REG_Dm: |
7373 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7374 | break; | |
7375 | ||
c19d1205 ZW |
7376 | default: |
7377 | abort (); | |
09d92015 | 7378 | } |
09d92015 MM |
7379 | } |
7380 | ||
c19d1205 | 7381 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7382 | if any, is handled by md_apply_fix. */ |
09d92015 | 7383 | static void |
c19d1205 | 7384 | encode_arm_shift (int i) |
09d92015 | 7385 | { |
c19d1205 ZW |
7386 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7387 | inst.instruction |= SHIFT_ROR << 5; | |
7388 | else | |
09d92015 | 7389 | { |
c19d1205 ZW |
7390 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7391 | if (inst.operands[i].immisreg) | |
7392 | { | |
7393 | inst.instruction |= SHIFT_BY_REG; | |
7394 | inst.instruction |= inst.operands[i].imm << 8; | |
7395 | } | |
7396 | else | |
7397 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7398 | } |
c19d1205 | 7399 | } |
09d92015 | 7400 | |
c19d1205 ZW |
7401 | static void |
7402 | encode_arm_shifter_operand (int i) | |
7403 | { | |
7404 | if (inst.operands[i].isreg) | |
09d92015 | 7405 | { |
c19d1205 ZW |
7406 | inst.instruction |= inst.operands[i].reg; |
7407 | encode_arm_shift (i); | |
09d92015 | 7408 | } |
c19d1205 | 7409 | else |
a415b1cd JB |
7410 | { |
7411 | inst.instruction |= INST_IMMEDIATE; | |
7412 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7413 | inst.instruction |= inst.operands[i].imm; | |
7414 | } | |
09d92015 MM |
7415 | } |
7416 | ||
c19d1205 | 7417 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7418 | static void |
c19d1205 | 7419 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7420 | { |
2b2f5df9 NC |
7421 | /* PR 14260: |
7422 | Generate an error if the operand is not a register. */ | |
7423 | constraint (!inst.operands[i].isreg, | |
7424 | _("Instruction does not support =N addresses")); | |
7425 | ||
c19d1205 | 7426 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7427 | |
c19d1205 | 7428 | if (inst.operands[i].preind) |
09d92015 | 7429 | { |
c19d1205 ZW |
7430 | if (is_t) |
7431 | { | |
7432 | inst.error = _("instruction does not accept preindexed addressing"); | |
7433 | return; | |
7434 | } | |
7435 | inst.instruction |= PRE_INDEX; | |
7436 | if (inst.operands[i].writeback) | |
7437 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7438 | |
c19d1205 ZW |
7439 | } |
7440 | else if (inst.operands[i].postind) | |
7441 | { | |
9c2799c2 | 7442 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7443 | if (is_t) |
7444 | inst.instruction |= WRITE_BACK; | |
7445 | } | |
7446 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7447 | { |
c19d1205 | 7448 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7449 | return; |
7450 | } | |
7451 | ||
c19d1205 ZW |
7452 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7453 | && (((inst.instruction & 0x000f0000) >> 16) | |
7454 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7455 | as_warn ((inst.instruction & LOAD_BIT) | |
7456 | ? _("destination register same as write-back base") | |
7457 | : _("source register same as write-back base")); | |
09d92015 MM |
7458 | } |
7459 | ||
c19d1205 ZW |
7460 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7461 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7462 | reject forms that cannot be used with a T instruction (i.e. not | |
7463 | post-indexed). */ | |
a737bd4d | 7464 | static void |
c19d1205 | 7465 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7466 | { |
5be8be5d DG |
7467 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7468 | ||
c19d1205 | 7469 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7470 | |
c19d1205 | 7471 | if (inst.operands[i].immisreg) |
09d92015 | 7472 | { |
5be8be5d DG |
7473 | constraint ((inst.operands[i].imm == REG_PC |
7474 | || (is_pc && inst.operands[i].writeback)), | |
7475 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7476 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7477 | inst.instruction |= inst.operands[i].imm; | |
7478 | if (!inst.operands[i].negative) | |
7479 | inst.instruction |= INDEX_UP; | |
7480 | if (inst.operands[i].shifted) | |
7481 | { | |
7482 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7483 | inst.instruction |= SHIFT_ROR << 5; | |
7484 | else | |
7485 | { | |
7486 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7487 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7488 | } | |
7489 | } | |
09d92015 | 7490 | } |
c19d1205 | 7491 | else /* immediate offset in inst.reloc */ |
09d92015 | 7492 | { |
5be8be5d DG |
7493 | if (is_pc && !inst.reloc.pc_rel) |
7494 | { | |
7495 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7496 | |
7497 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7498 | cannot use PC in addressing. | |
7499 | PC cannot be used in writeback addressing, either. */ | |
7500 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7501 | BAD_PC_ADDRESSING); |
23a10334 | 7502 | |
dc5ec521 | 7503 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7504 | if (warn_on_deprecated |
7505 | && !is_load | |
7506 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
5c3696f8 | 7507 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
5be8be5d DG |
7508 | } |
7509 | ||
c19d1205 | 7510 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7511 | { |
7512 | /* Prefer + for zero encoded value. */ | |
7513 | if (!inst.operands[i].negative) | |
7514 | inst.instruction |= INDEX_UP; | |
7515 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7516 | } | |
09d92015 | 7517 | } |
09d92015 MM |
7518 | } |
7519 | ||
c19d1205 ZW |
7520 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7521 | ARM-format mode 3 load or store instruction. Reject forms that | |
7522 | cannot be used with such instructions. If is_t is true, reject | |
7523 | forms that cannot be used with a T instruction (i.e. not | |
7524 | post-indexed). */ | |
7525 | static void | |
7526 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7527 | { |
c19d1205 | 7528 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7529 | { |
c19d1205 ZW |
7530 | inst.error = _("instruction does not accept scaled register index"); |
7531 | return; | |
09d92015 | 7532 | } |
a737bd4d | 7533 | |
c19d1205 | 7534 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7535 | |
c19d1205 ZW |
7536 | if (inst.operands[i].immisreg) |
7537 | { | |
5be8be5d | 7538 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 7539 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 7540 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
7541 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
7542 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7543 | inst.instruction |= inst.operands[i].imm; |
7544 | if (!inst.operands[i].negative) | |
7545 | inst.instruction |= INDEX_UP; | |
7546 | } | |
7547 | else /* immediate offset in inst.reloc */ | |
7548 | { | |
5be8be5d DG |
7549 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7550 | && inst.operands[i].writeback), | |
7551 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7552 | inst.instruction |= HWOFFSET_IMM; |
7553 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7554 | { |
7555 | /* Prefer + for zero encoded value. */ | |
7556 | if (!inst.operands[i].negative) | |
7557 | inst.instruction |= INDEX_UP; | |
7558 | ||
7559 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7560 | } | |
c19d1205 | 7561 | } |
a737bd4d NC |
7562 | } |
7563 | ||
8335d6aa JW |
7564 | /* Write immediate bits [7:0] to the following locations: |
7565 | ||
7566 | |28/24|23 19|18 16|15 4|3 0| | |
7567 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
7568 | ||
7569 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
7570 | ||
7571 | static void | |
7572 | neon_write_immbits (unsigned immbits) | |
7573 | { | |
7574 | inst.instruction |= immbits & 0xf; | |
7575 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
7576 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
7577 | } | |
7578 | ||
7579 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
7580 | ||
7581 | static void | |
7582 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
7583 | { | |
7584 | unsigned immlo = xlo ? *xlo : 0; | |
7585 | unsigned immhi = xhi ? *xhi : 0; | |
7586 | ||
7587 | switch (size) | |
7588 | { | |
7589 | case 8: | |
7590 | immlo = (~immlo) & 0xff; | |
7591 | break; | |
7592 | ||
7593 | case 16: | |
7594 | immlo = (~immlo) & 0xffff; | |
7595 | break; | |
7596 | ||
7597 | case 64: | |
7598 | immhi = (~immhi) & 0xffffffff; | |
7599 | /* fall through. */ | |
7600 | ||
7601 | case 32: | |
7602 | immlo = (~immlo) & 0xffffffff; | |
7603 | break; | |
7604 | ||
7605 | default: | |
7606 | abort (); | |
7607 | } | |
7608 | ||
7609 | if (xlo) | |
7610 | *xlo = immlo; | |
7611 | ||
7612 | if (xhi) | |
7613 | *xhi = immhi; | |
7614 | } | |
7615 | ||
7616 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
7617 | A, B, C, D. */ | |
09d92015 | 7618 | |
c19d1205 | 7619 | static int |
8335d6aa | 7620 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 7621 | { |
8335d6aa JW |
7622 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
7623 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
7624 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
7625 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
7626 | } | |
a737bd4d | 7627 | |
8335d6aa | 7628 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 7629 | |
8335d6aa JW |
7630 | static unsigned |
7631 | neon_squash_bits (unsigned imm) | |
7632 | { | |
7633 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
7634 | | ((imm & 0x01000000) >> 21); | |
7635 | } | |
7636 | ||
7637 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
7638 | ||
7639 | static unsigned | |
7640 | neon_qfloat_bits (unsigned imm) | |
7641 | { | |
7642 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
7643 | } | |
7644 | ||
7645 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
7646 | the instruction. *OP is passed as the initial value of the op field, and | |
7647 | may be set to a different value depending on the constant (i.e. | |
7648 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
7649 | MVN). If the immediate looks like a repeated pattern then also | |
7650 | try smaller element sizes. */ | |
7651 | ||
7652 | static int | |
7653 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
7654 | unsigned *immbits, int *op, int size, | |
7655 | enum neon_el_type type) | |
7656 | { | |
7657 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
7658 | float. */ | |
7659 | if (type == NT_float && !float_p) | |
7660 | return FAIL; | |
7661 | ||
7662 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 7663 | { |
8335d6aa JW |
7664 | if (size != 32 || *op == 1) |
7665 | return FAIL; | |
7666 | *immbits = neon_qfloat_bits (immlo); | |
7667 | return 0xf; | |
7668 | } | |
7669 | ||
7670 | if (size == 64) | |
7671 | { | |
7672 | if (neon_bits_same_in_bytes (immhi) | |
7673 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 7674 | { |
8335d6aa JW |
7675 | if (*op == 1) |
7676 | return FAIL; | |
7677 | *immbits = (neon_squash_bits (immhi) << 4) | |
7678 | | neon_squash_bits (immlo); | |
7679 | *op = 1; | |
7680 | return 0xe; | |
c19d1205 | 7681 | } |
a737bd4d | 7682 | |
8335d6aa JW |
7683 | if (immhi != immlo) |
7684 | return FAIL; | |
7685 | } | |
a737bd4d | 7686 | |
8335d6aa | 7687 | if (size >= 32) |
09d92015 | 7688 | { |
8335d6aa | 7689 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 7690 | { |
8335d6aa JW |
7691 | *immbits = immlo; |
7692 | return 0x0; | |
c19d1205 | 7693 | } |
8335d6aa | 7694 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 7695 | { |
8335d6aa JW |
7696 | *immbits = immlo >> 8; |
7697 | return 0x2; | |
c19d1205 | 7698 | } |
8335d6aa JW |
7699 | else if (immlo == (immlo & 0x00ff0000)) |
7700 | { | |
7701 | *immbits = immlo >> 16; | |
7702 | return 0x4; | |
7703 | } | |
7704 | else if (immlo == (immlo & 0xff000000)) | |
7705 | { | |
7706 | *immbits = immlo >> 24; | |
7707 | return 0x6; | |
7708 | } | |
7709 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
7710 | { | |
7711 | *immbits = (immlo >> 8) & 0xff; | |
7712 | return 0xc; | |
7713 | } | |
7714 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
7715 | { | |
7716 | *immbits = (immlo >> 16) & 0xff; | |
7717 | return 0xd; | |
7718 | } | |
7719 | ||
7720 | if ((immlo & 0xffff) != (immlo >> 16)) | |
7721 | return FAIL; | |
7722 | immlo &= 0xffff; | |
09d92015 | 7723 | } |
a737bd4d | 7724 | |
8335d6aa | 7725 | if (size >= 16) |
4962c51a | 7726 | { |
8335d6aa JW |
7727 | if (immlo == (immlo & 0x000000ff)) |
7728 | { | |
7729 | *immbits = immlo; | |
7730 | return 0x8; | |
7731 | } | |
7732 | else if (immlo == (immlo & 0x0000ff00)) | |
7733 | { | |
7734 | *immbits = immlo >> 8; | |
7735 | return 0xa; | |
7736 | } | |
7737 | ||
7738 | if ((immlo & 0xff) != (immlo >> 8)) | |
7739 | return FAIL; | |
7740 | immlo &= 0xff; | |
4962c51a MS |
7741 | } |
7742 | ||
8335d6aa JW |
7743 | if (immlo == (immlo & 0x000000ff)) |
7744 | { | |
7745 | /* Don't allow MVN with 8-bit immediate. */ | |
7746 | if (*op == 1) | |
7747 | return FAIL; | |
7748 | *immbits = immlo; | |
7749 | return 0xe; | |
7750 | } | |
26d97720 | 7751 | |
8335d6aa | 7752 | return FAIL; |
c19d1205 | 7753 | } |
a737bd4d | 7754 | |
5fc177c8 | 7755 | #if defined BFD_HOST_64_BIT |
ba592044 AM |
7756 | /* Returns TRUE if double precision value V may be cast |
7757 | to single precision without loss of accuracy. */ | |
7758 | ||
7759 | static bfd_boolean | |
5fc177c8 | 7760 | is_double_a_single (bfd_int64_t v) |
ba592044 | 7761 | { |
5fc177c8 NC |
7762 | int exp = (int)((v >> 52) & 0x7FF); |
7763 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFF); | |
ba592044 AM |
7764 | |
7765 | return (exp == 0 || exp == 0x7FF | |
7766 | || (exp >= 1023 - 126 && exp <= 1023 + 127)) | |
7767 | && (mantissa & 0x1FFFFFFFl) == 0; | |
7768 | } | |
7769 | ||
7770 | /* Returns a double precision value casted to single precision | |
7771 | (ignoring the least significant bits in exponent and mantissa). */ | |
7772 | ||
7773 | static int | |
5fc177c8 | 7774 | double_to_single (bfd_int64_t v) |
ba592044 AM |
7775 | { |
7776 | int sign = (int) ((v >> 63) & 1l); | |
5fc177c8 NC |
7777 | int exp = (int) ((v >> 52) & 0x7FF); |
7778 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFF); | |
ba592044 AM |
7779 | |
7780 | if (exp == 0x7FF) | |
7781 | exp = 0xFF; | |
7782 | else | |
7783 | { | |
7784 | exp = exp - 1023 + 127; | |
7785 | if (exp >= 0xFF) | |
7786 | { | |
7787 | /* Infinity. */ | |
7788 | exp = 0x7F; | |
7789 | mantissa = 0; | |
7790 | } | |
7791 | else if (exp < 0) | |
7792 | { | |
7793 | /* No denormalized numbers. */ | |
7794 | exp = 0; | |
7795 | mantissa = 0; | |
7796 | } | |
7797 | } | |
7798 | mantissa >>= 29; | |
7799 | return (sign << 31) | (exp << 23) | mantissa; | |
7800 | } | |
5fc177c8 | 7801 | #endif /* BFD_HOST_64_BIT */ |
ba592044 | 7802 | |
8335d6aa JW |
7803 | enum lit_type |
7804 | { | |
7805 | CONST_THUMB, | |
7806 | CONST_ARM, | |
7807 | CONST_VEC | |
7808 | }; | |
7809 | ||
ba592044 AM |
7810 | static void do_vfp_nsyn_opcode (const char *); |
7811 | ||
c19d1205 ZW |
7812 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7813 | Determine whether it can be performed with a move instruction; if | |
7814 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7815 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7816 | load and return FALSE. If this is not a valid thing to do in the | |
7817 | current context, set inst.error and return TRUE. | |
a737bd4d | 7818 | |
c19d1205 ZW |
7819 | inst.operands[i] describes the destination register. */ |
7820 | ||
c921be7d | 7821 | static bfd_boolean |
8335d6aa | 7822 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 7823 | { |
53365c0d | 7824 | unsigned long tbit; |
8335d6aa JW |
7825 | bfd_boolean thumb_p = (t == CONST_THUMB); |
7826 | bfd_boolean arm_p = (t == CONST_ARM); | |
53365c0d PB |
7827 | |
7828 | if (thumb_p) | |
7829 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7830 | else | |
7831 | tbit = LOAD_BIT; | |
7832 | ||
7833 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7834 | { |
c19d1205 | 7835 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7836 | return TRUE; |
09d92015 | 7837 | } |
ba592044 | 7838 | |
8335d6aa JW |
7839 | if (inst.reloc.exp.X_op != O_constant |
7840 | && inst.reloc.exp.X_op != O_symbol | |
7841 | && inst.reloc.exp.X_op != O_big) | |
09d92015 MM |
7842 | { |
7843 | inst.error = _("constant expression expected"); | |
c921be7d | 7844 | return TRUE; |
09d92015 | 7845 | } |
ba592044 AM |
7846 | |
7847 | if (inst.reloc.exp.X_op == O_constant | |
7848 | || inst.reloc.exp.X_op == O_big) | |
8335d6aa | 7849 | { |
5fc177c8 NC |
7850 | #if defined BFD_HOST_64_BIT |
7851 | bfd_int64_t v; | |
7852 | #else | |
ba592044 | 7853 | offsetT v; |
5fc177c8 | 7854 | #endif |
ba592044 | 7855 | if (inst.reloc.exp.X_op == O_big) |
8335d6aa | 7856 | { |
ba592044 AM |
7857 | LITTLENUM_TYPE w[X_PRECISION]; |
7858 | LITTLENUM_TYPE * l; | |
7859 | ||
7860 | if (inst.reloc.exp.X_add_number == -1) | |
8335d6aa | 7861 | { |
ba592044 AM |
7862 | gen_to_words (w, X_PRECISION, E_PRECISION); |
7863 | l = w; | |
7864 | /* FIXME: Should we check words w[2..5] ? */ | |
8335d6aa | 7865 | } |
ba592044 AM |
7866 | else |
7867 | l = generic_bignum; | |
7868 | ||
5fc177c8 NC |
7869 | #if defined BFD_HOST_64_BIT |
7870 | v = | |
7871 | ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK) | |
7872 | << LITTLENUM_NUMBER_OF_BITS) | |
7873 | | ((bfd_int64_t) l[2] & LITTLENUM_MASK)) | |
7874 | << LITTLENUM_NUMBER_OF_BITS) | |
7875 | | ((bfd_int64_t) l[1] & LITTLENUM_MASK)) | |
7876 | << LITTLENUM_NUMBER_OF_BITS) | |
7877 | | ((bfd_int64_t) l[0] & LITTLENUM_MASK)); | |
7878 | #else | |
ba592044 AM |
7879 | v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS) |
7880 | | (l[0] & LITTLENUM_MASK); | |
5fc177c8 | 7881 | #endif |
8335d6aa | 7882 | } |
ba592044 AM |
7883 | else |
7884 | v = inst.reloc.exp.X_add_number; | |
7885 | ||
7886 | if (!inst.operands[i].issingle) | |
8335d6aa | 7887 | { |
12569877 | 7888 | if (thumb_p) |
8335d6aa | 7889 | { |
12569877 | 7890 | if ((v & ~0xFF) == 0) |
ba592044 AM |
7891 | { |
7892 | /* This can be done with a mov(1) instruction. */ | |
7893 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7894 | inst.instruction |= v; | |
7895 | return TRUE; | |
7896 | } | |
12569877 AM |
7897 | |
7898 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2) | |
7899 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
7900 | { | |
7901 | /* Check if on thumb2 it can be done with a mov.w or mvn.w instruction. */ | |
7902 | unsigned int newimm; | |
7903 | bfd_boolean isNegated; | |
7904 | ||
7905 | newimm = encode_thumb32_immediate (v); | |
7906 | if (newimm != (unsigned int) FAIL) | |
7907 | isNegated = FALSE; | |
7908 | else | |
7909 | { | |
7910 | newimm = encode_thumb32_immediate (~ v); | |
7911 | if (newimm != (unsigned int) FAIL) | |
7912 | isNegated = TRUE; | |
7913 | } | |
7914 | ||
7915 | if (newimm != (unsigned int) FAIL) | |
7916 | { | |
7917 | inst.instruction = 0xf04f0000 | (inst.operands[i].reg << 8); | |
7918 | inst.instruction |= (isNegated?0x200000:0); | |
7919 | inst.instruction |= (newimm & 0x800) << 15; | |
7920 | inst.instruction |= (newimm & 0x700) << 4; | |
7921 | inst.instruction |= (newimm & 0x0ff); | |
7922 | return TRUE; | |
7923 | } | |
7924 | else if ((v & ~0xFFFF) == 0 || (v & ~0xFFFF0000) == 0) | |
7925 | { | |
7926 | /* The number may be loaded with a movw/movt instruction. */ | |
7927 | int imm; | |
7928 | ||
7929 | if ((inst.reloc.exp.X_add_number & ~0xFFFF) == 0) | |
7930 | { | |
7931 | inst.instruction= 0xf2400000; | |
7932 | imm = v; | |
7933 | } | |
7934 | else | |
7935 | { | |
7936 | inst.instruction = 0xf2c00000; | |
7937 | imm = v >> 16; | |
7938 | } | |
7939 | ||
7940 | inst.instruction |= (inst.operands[i].reg << 8); | |
7941 | inst.instruction |= (imm & 0xf000) << 4; | |
7942 | inst.instruction |= (imm & 0x0800) << 15; | |
7943 | inst.instruction |= (imm & 0x0700) << 4; | |
7944 | inst.instruction |= (imm & 0x00ff); | |
7945 | return TRUE; | |
7946 | } | |
7947 | } | |
8335d6aa | 7948 | } |
12569877 | 7949 | else if (arm_p) |
ba592044 AM |
7950 | { |
7951 | int value = encode_arm_immediate (v); | |
12569877 | 7952 | |
ba592044 AM |
7953 | if (value != FAIL) |
7954 | { | |
7955 | /* This can be done with a mov instruction. */ | |
7956 | inst.instruction &= LITERAL_MASK; | |
7957 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7958 | inst.instruction |= value & 0xfff; | |
7959 | return TRUE; | |
7960 | } | |
8335d6aa | 7961 | |
ba592044 AM |
7962 | value = encode_arm_immediate (~ v); |
7963 | if (value != FAIL) | |
7964 | { | |
7965 | /* This can be done with a mvn instruction. */ | |
7966 | inst.instruction &= LITERAL_MASK; | |
7967 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7968 | inst.instruction |= value & 0xfff; | |
7969 | return TRUE; | |
7970 | } | |
7971 | } | |
7972 | else if (t == CONST_VEC) | |
8335d6aa | 7973 | { |
ba592044 AM |
7974 | int op = 0; |
7975 | unsigned immbits = 0; | |
7976 | unsigned immlo = inst.operands[1].imm; | |
7977 | unsigned immhi = inst.operands[1].regisimm | |
7978 | ? inst.operands[1].reg | |
7979 | : inst.reloc.exp.X_unsigned | |
7980 | ? 0 | |
7981 | : ((bfd_int64_t)((int) immlo)) >> 32; | |
7982 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
7983 | &op, 64, NT_invtype); | |
7984 | ||
7985 | if (cmode == FAIL) | |
7986 | { | |
7987 | neon_invert_size (&immlo, &immhi, 64); | |
7988 | op = !op; | |
7989 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
7990 | &op, 64, NT_invtype); | |
7991 | } | |
7992 | ||
7993 | if (cmode != FAIL) | |
7994 | { | |
7995 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
7996 | | (1 << 23) | |
7997 | | (cmode << 8) | |
7998 | | (op << 5) | |
7999 | | (1 << 4); | |
8000 | ||
8001 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
8002 | if (thumb_mode) | |
8003 | inst.instruction |= (0x7 << 29) | (0xF << 24); | |
8004 | else | |
8005 | inst.instruction |= (0xF << 28) | (0x1 << 25); | |
8006 | neon_write_immbits (immbits); | |
8007 | return TRUE; | |
8008 | } | |
8335d6aa JW |
8009 | } |
8010 | } | |
8335d6aa | 8011 | |
ba592044 AM |
8012 | if (t == CONST_VEC) |
8013 | { | |
8014 | /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */ | |
8015 | if (inst.operands[i].issingle | |
8016 | && is_quarter_float (inst.operands[1].imm) | |
8017 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd)) | |
8335d6aa | 8018 | { |
ba592044 AM |
8019 | inst.operands[1].imm = |
8020 | neon_qfloat_bits (v); | |
8021 | do_vfp_nsyn_opcode ("fconsts"); | |
8022 | return TRUE; | |
8335d6aa | 8023 | } |
5fc177c8 NC |
8024 | |
8025 | /* If our host does not support a 64-bit type then we cannot perform | |
8026 | the following optimization. This mean that there will be a | |
8027 | discrepancy between the output produced by an assembler built for | |
8028 | a 32-bit-only host and the output produced from a 64-bit host, but | |
8029 | this cannot be helped. */ | |
8030 | #if defined BFD_HOST_64_BIT | |
ba592044 AM |
8031 | else if (!inst.operands[1].issingle |
8032 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
8335d6aa | 8033 | { |
ba592044 AM |
8034 | if (is_double_a_single (v) |
8035 | && is_quarter_float (double_to_single (v))) | |
8036 | { | |
8037 | inst.operands[1].imm = | |
8038 | neon_qfloat_bits (double_to_single (v)); | |
8039 | do_vfp_nsyn_opcode ("fconstd"); | |
8040 | return TRUE; | |
8041 | } | |
8335d6aa | 8042 | } |
5fc177c8 | 8043 | #endif |
8335d6aa JW |
8044 | } |
8045 | } | |
8046 | ||
8047 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
8048 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
8049 | return TRUE; | |
8050 | ||
8051 | inst.operands[1].reg = REG_PC; | |
8052 | inst.operands[1].isreg = 1; | |
8053 | inst.operands[1].preind = 1; | |
8054 | inst.reloc.pc_rel = 1; | |
8055 | inst.reloc.type = (thumb_p | |
8056 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
8057 | : (mode_3 | |
8058 | ? BFD_RELOC_ARM_HWLITERAL | |
8059 | : BFD_RELOC_ARM_LITERAL)); | |
8060 | return FALSE; | |
8061 | } | |
8062 | ||
8063 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
8064 | ARM-format instruction. Reject all forms which cannot be encoded | |
8065 | into a coprocessor load/store instruction. If wb_ok is false, | |
8066 | reject use of writeback; if unind_ok is false, reject use of | |
8067 | unindexed addressing. If reloc_override is not 0, use it instead | |
8068 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
8069 | (in which case it is preserved). */ | |
8070 | ||
8071 | static int | |
8072 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
8073 | { | |
8074 | if (!inst.operands[i].isreg) | |
8075 | { | |
99b2a2dd NC |
8076 | /* PR 18256 */ |
8077 | if (! inst.operands[0].isvec) | |
8078 | { | |
8079 | inst.error = _("invalid co-processor operand"); | |
8080 | return FAIL; | |
8081 | } | |
8335d6aa JW |
8082 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) |
8083 | return SUCCESS; | |
8084 | } | |
8085 | ||
8086 | inst.instruction |= inst.operands[i].reg << 16; | |
8087 | ||
8088 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
8089 | ||
8090 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
8091 | { | |
8092 | gas_assert (!inst.operands[i].writeback); | |
8093 | if (!unind_ok) | |
8094 | { | |
8095 | inst.error = _("instruction does not support unindexed addressing"); | |
8096 | return FAIL; | |
8097 | } | |
8098 | inst.instruction |= inst.operands[i].imm; | |
8099 | inst.instruction |= INDEX_UP; | |
8100 | return SUCCESS; | |
8101 | } | |
8102 | ||
8103 | if (inst.operands[i].preind) | |
8104 | inst.instruction |= PRE_INDEX; | |
8105 | ||
8106 | if (inst.operands[i].writeback) | |
09d92015 | 8107 | { |
8335d6aa | 8108 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 8109 | { |
8335d6aa JW |
8110 | inst.error = _("pc may not be used with write-back"); |
8111 | return FAIL; | |
c19d1205 | 8112 | } |
8335d6aa | 8113 | if (!wb_ok) |
c19d1205 | 8114 | { |
8335d6aa JW |
8115 | inst.error = _("instruction does not support writeback"); |
8116 | return FAIL; | |
c19d1205 | 8117 | } |
8335d6aa | 8118 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
8119 | } |
8120 | ||
8335d6aa JW |
8121 | if (reloc_override) |
8122 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; | |
8123 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
8124 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
8125 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 8126 | { |
8335d6aa JW |
8127 | if (thumb_mode) |
8128 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
8129 | else | |
8130 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
c19d1205 | 8131 | } |
8335d6aa JW |
8132 | |
8133 | /* Prefer + for zero encoded value. */ | |
8134 | if (!inst.operands[i].negative) | |
8135 | inst.instruction |= INDEX_UP; | |
8136 | ||
8137 | return SUCCESS; | |
09d92015 MM |
8138 | } |
8139 | ||
5f4273c7 | 8140 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
8141 | First some generics; their names are taken from the conventional |
8142 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 8143 | |
a737bd4d | 8144 | static void |
c19d1205 | 8145 | do_noargs (void) |
09d92015 | 8146 | { |
c19d1205 | 8147 | } |
a737bd4d | 8148 | |
c19d1205 ZW |
8149 | static void |
8150 | do_rd (void) | |
8151 | { | |
8152 | inst.instruction |= inst.operands[0].reg << 12; | |
8153 | } | |
a737bd4d | 8154 | |
c19d1205 ZW |
8155 | static void |
8156 | do_rd_rm (void) | |
8157 | { | |
8158 | inst.instruction |= inst.operands[0].reg << 12; | |
8159 | inst.instruction |= inst.operands[1].reg; | |
8160 | } | |
09d92015 | 8161 | |
9eb6c0f1 MGD |
8162 | static void |
8163 | do_rm_rn (void) | |
8164 | { | |
8165 | inst.instruction |= inst.operands[0].reg; | |
8166 | inst.instruction |= inst.operands[1].reg << 16; | |
8167 | } | |
8168 | ||
c19d1205 ZW |
8169 | static void |
8170 | do_rd_rn (void) | |
8171 | { | |
8172 | inst.instruction |= inst.operands[0].reg << 12; | |
8173 | inst.instruction |= inst.operands[1].reg << 16; | |
8174 | } | |
a737bd4d | 8175 | |
c19d1205 ZW |
8176 | static void |
8177 | do_rn_rd (void) | |
8178 | { | |
8179 | inst.instruction |= inst.operands[0].reg << 16; | |
8180 | inst.instruction |= inst.operands[1].reg << 12; | |
8181 | } | |
09d92015 | 8182 | |
59d09be6 MGD |
8183 | static bfd_boolean |
8184 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
8185 | { | |
8186 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
8187 | { | |
5c3696f8 | 8188 | as_tsktsk ("%s", msg); |
59d09be6 MGD |
8189 | return TRUE; |
8190 | } | |
8191 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
8192 | { | |
8193 | as_bad ("%s", msg); | |
8194 | return TRUE; | |
8195 | } | |
8196 | ||
8197 | return FALSE; | |
8198 | } | |
8199 | ||
c19d1205 ZW |
8200 | static void |
8201 | do_rd_rm_rn (void) | |
8202 | { | |
9a64e435 | 8203 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 8204 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 8205 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
8206 | { |
8207 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
8208 | _("Rn must not overlap other operands")); | |
8209 | ||
59d09be6 MGD |
8210 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
8211 | */ | |
8212 | if (!check_obsolete (&arm_ext_v8, | |
8213 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
8214 | && warn_on_deprecated | |
8215 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
5c3696f8 | 8216 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
56adecf4 | 8217 | } |
59d09be6 | 8218 | |
c19d1205 ZW |
8219 | inst.instruction |= inst.operands[0].reg << 12; |
8220 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 8221 | inst.instruction |= Rn << 16; |
c19d1205 | 8222 | } |
09d92015 | 8223 | |
c19d1205 ZW |
8224 | static void |
8225 | do_rd_rn_rm (void) | |
8226 | { | |
8227 | inst.instruction |= inst.operands[0].reg << 12; | |
8228 | inst.instruction |= inst.operands[1].reg << 16; | |
8229 | inst.instruction |= inst.operands[2].reg; | |
8230 | } | |
a737bd4d | 8231 | |
c19d1205 ZW |
8232 | static void |
8233 | do_rm_rd_rn (void) | |
8234 | { | |
5be8be5d DG |
8235 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
8236 | constraint (((inst.reloc.exp.X_op != O_constant | |
8237 | && inst.reloc.exp.X_op != O_illegal) | |
8238 | || inst.reloc.exp.X_add_number != 0), | |
8239 | BAD_ADDR_MODE); | |
c19d1205 ZW |
8240 | inst.instruction |= inst.operands[0].reg; |
8241 | inst.instruction |= inst.operands[1].reg << 12; | |
8242 | inst.instruction |= inst.operands[2].reg << 16; | |
8243 | } | |
09d92015 | 8244 | |
c19d1205 ZW |
8245 | static void |
8246 | do_imm0 (void) | |
8247 | { | |
8248 | inst.instruction |= inst.operands[0].imm; | |
8249 | } | |
09d92015 | 8250 | |
c19d1205 ZW |
8251 | static void |
8252 | do_rd_cpaddr (void) | |
8253 | { | |
8254 | inst.instruction |= inst.operands[0].reg << 12; | |
8255 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 8256 | } |
a737bd4d | 8257 | |
c19d1205 ZW |
8258 | /* ARM instructions, in alphabetical order by function name (except |
8259 | that wrapper functions appear immediately after the function they | |
8260 | wrap). */ | |
09d92015 | 8261 | |
c19d1205 ZW |
8262 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
8263 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
8264 | |
8265 | static void | |
c19d1205 | 8266 | do_adr (void) |
09d92015 | 8267 | { |
c19d1205 | 8268 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 8269 | |
c19d1205 ZW |
8270 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8271 | out to be negative. */ | |
8272 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 8273 | inst.reloc.pc_rel = 1; |
2fc8bdac | 8274 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 8275 | } |
b99bd4ef | 8276 | |
c19d1205 ZW |
8277 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
8278 | into a relative address of the form: | |
8279 | add rd, pc, #low(label-.-8)" | |
8280 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 8281 | |
c19d1205 ZW |
8282 | static void |
8283 | do_adrl (void) | |
8284 | { | |
8285 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 8286 | |
c19d1205 ZW |
8287 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8288 | out to be negative. */ | |
8289 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
8290 | inst.reloc.pc_rel = 1; |
8291 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 8292 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
8293 | } |
8294 | ||
b99bd4ef | 8295 | static void |
c19d1205 | 8296 | do_arit (void) |
b99bd4ef | 8297 | { |
c19d1205 ZW |
8298 | if (!inst.operands[1].present) |
8299 | inst.operands[1].reg = inst.operands[0].reg; | |
8300 | inst.instruction |= inst.operands[0].reg << 12; | |
8301 | inst.instruction |= inst.operands[1].reg << 16; | |
8302 | encode_arm_shifter_operand (2); | |
8303 | } | |
b99bd4ef | 8304 | |
62b3e311 PB |
8305 | static void |
8306 | do_barrier (void) | |
8307 | { | |
8308 | if (inst.operands[0].present) | |
ccb84d65 | 8309 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
8310 | else |
8311 | inst.instruction |= 0xf; | |
8312 | } | |
8313 | ||
c19d1205 ZW |
8314 | static void |
8315 | do_bfc (void) | |
8316 | { | |
8317 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
8318 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8319 | /* The instruction encoding stores the LSB and MSB, | |
8320 | not the LSB and width. */ | |
8321 | inst.instruction |= inst.operands[0].reg << 12; | |
8322 | inst.instruction |= inst.operands[1].imm << 7; | |
8323 | inst.instruction |= (msb - 1) << 16; | |
8324 | } | |
b99bd4ef | 8325 | |
c19d1205 ZW |
8326 | static void |
8327 | do_bfi (void) | |
8328 | { | |
8329 | unsigned int msb; | |
b99bd4ef | 8330 | |
c19d1205 ZW |
8331 | /* #0 in second position is alternative syntax for bfc, which is |
8332 | the same instruction but with REG_PC in the Rm field. */ | |
8333 | if (!inst.operands[1].isreg) | |
8334 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 8335 | |
c19d1205 ZW |
8336 | msb = inst.operands[2].imm + inst.operands[3].imm; |
8337 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8338 | /* The instruction encoding stores the LSB and MSB, | |
8339 | not the LSB and width. */ | |
8340 | inst.instruction |= inst.operands[0].reg << 12; | |
8341 | inst.instruction |= inst.operands[1].reg; | |
8342 | inst.instruction |= inst.operands[2].imm << 7; | |
8343 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
8344 | } |
8345 | ||
b99bd4ef | 8346 | static void |
c19d1205 | 8347 | do_bfx (void) |
b99bd4ef | 8348 | { |
c19d1205 ZW |
8349 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
8350 | _("bit-field extends past end of register")); | |
8351 | inst.instruction |= inst.operands[0].reg << 12; | |
8352 | inst.instruction |= inst.operands[1].reg; | |
8353 | inst.instruction |= inst.operands[2].imm << 7; | |
8354 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
8355 | } | |
09d92015 | 8356 | |
c19d1205 ZW |
8357 | /* ARM V5 breakpoint instruction (argument parse) |
8358 | BKPT <16 bit unsigned immediate> | |
8359 | Instruction is not conditional. | |
8360 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
8361 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 8362 | |
c19d1205 ZW |
8363 | static void |
8364 | do_bkpt (void) | |
8365 | { | |
8366 | /* Top 12 of 16 bits to bits 19:8. */ | |
8367 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 8368 | |
c19d1205 ZW |
8369 | /* Bottom 4 of 16 bits to bits 3:0. */ |
8370 | inst.instruction |= inst.operands[0].imm & 0xf; | |
8371 | } | |
09d92015 | 8372 | |
c19d1205 ZW |
8373 | static void |
8374 | encode_branch (int default_reloc) | |
8375 | { | |
8376 | if (inst.operands[0].hasreloc) | |
8377 | { | |
0855e32b NS |
8378 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
8379 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
8380 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
8381 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
8382 | ? BFD_RELOC_ARM_PLT32 | |
8383 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 8384 | } |
b99bd4ef | 8385 | else |
9ae92b05 | 8386 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 8387 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
8388 | } |
8389 | ||
b99bd4ef | 8390 | static void |
c19d1205 | 8391 | do_branch (void) |
b99bd4ef | 8392 | { |
39b41c9c PB |
8393 | #ifdef OBJ_ELF |
8394 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8395 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8396 | else | |
8397 | #endif | |
8398 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
8399 | } | |
8400 | ||
8401 | static void | |
8402 | do_bl (void) | |
8403 | { | |
8404 | #ifdef OBJ_ELF | |
8405 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8406 | { | |
8407 | if (inst.cond == COND_ALWAYS) | |
8408 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
8409 | else | |
8410 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8411 | } | |
8412 | else | |
8413 | #endif | |
8414 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 8415 | } |
b99bd4ef | 8416 | |
c19d1205 ZW |
8417 | /* ARM V5 branch-link-exchange instruction (argument parse) |
8418 | BLX <target_addr> ie BLX(1) | |
8419 | BLX{<condition>} <Rm> ie BLX(2) | |
8420 | Unfortunately, there are two different opcodes for this mnemonic. | |
8421 | So, the insns[].value is not used, and the code here zaps values | |
8422 | into inst.instruction. | |
8423 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 8424 | |
c19d1205 ZW |
8425 | static void |
8426 | do_blx (void) | |
8427 | { | |
8428 | if (inst.operands[0].isreg) | |
b99bd4ef | 8429 | { |
c19d1205 ZW |
8430 | /* Arg is a register; the opcode provided by insns[] is correct. |
8431 | It is not illegal to do "blx pc", just useless. */ | |
8432 | if (inst.operands[0].reg == REG_PC) | |
8433 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 8434 | |
c19d1205 ZW |
8435 | inst.instruction |= inst.operands[0].reg; |
8436 | } | |
8437 | else | |
b99bd4ef | 8438 | { |
c19d1205 | 8439 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
8440 | conditionally, and the opcode must be adjusted. |
8441 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
8442 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 8443 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 8444 | inst.instruction = 0xfa000000; |
267bf995 | 8445 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 8446 | } |
c19d1205 ZW |
8447 | } |
8448 | ||
8449 | static void | |
8450 | do_bx (void) | |
8451 | { | |
845b51d6 PB |
8452 | bfd_boolean want_reloc; |
8453 | ||
c19d1205 ZW |
8454 | if (inst.operands[0].reg == REG_PC) |
8455 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 8456 | |
c19d1205 | 8457 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
8458 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
8459 | it is for ARMv4t or earlier. */ | |
8460 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
8461 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
8462 | want_reloc = TRUE; | |
8463 | ||
5ad34203 | 8464 | #ifdef OBJ_ELF |
845b51d6 | 8465 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 8466 | #endif |
584206db | 8467 | want_reloc = FALSE; |
845b51d6 PB |
8468 | |
8469 | if (want_reloc) | |
8470 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
8471 | } |
8472 | ||
c19d1205 ZW |
8473 | |
8474 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
8475 | |
8476 | static void | |
c19d1205 | 8477 | do_bxj (void) |
a737bd4d | 8478 | { |
c19d1205 ZW |
8479 | if (inst.operands[0].reg == REG_PC) |
8480 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
8481 | ||
8482 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
8483 | } |
8484 | ||
c19d1205 ZW |
8485 | /* Co-processor data operation: |
8486 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
8487 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
8488 | static void | |
8489 | do_cdp (void) | |
8490 | { | |
8491 | inst.instruction |= inst.operands[0].reg << 8; | |
8492 | inst.instruction |= inst.operands[1].imm << 20; | |
8493 | inst.instruction |= inst.operands[2].reg << 12; | |
8494 | inst.instruction |= inst.operands[3].reg << 16; | |
8495 | inst.instruction |= inst.operands[4].reg; | |
8496 | inst.instruction |= inst.operands[5].imm << 5; | |
8497 | } | |
a737bd4d NC |
8498 | |
8499 | static void | |
c19d1205 | 8500 | do_cmp (void) |
a737bd4d | 8501 | { |
c19d1205 ZW |
8502 | inst.instruction |= inst.operands[0].reg << 16; |
8503 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
8504 | } |
8505 | ||
c19d1205 ZW |
8506 | /* Transfer between coprocessor and ARM registers. |
8507 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
8508 | MRC2 | |
8509 | MCR{cond} | |
8510 | MCR2 | |
8511 | ||
8512 | No special properties. */ | |
09d92015 | 8513 | |
dcbd0d71 MGD |
8514 | struct deprecated_coproc_regs_s |
8515 | { | |
8516 | unsigned cp; | |
8517 | int opc1; | |
8518 | unsigned crn; | |
8519 | unsigned crm; | |
8520 | int opc2; | |
8521 | arm_feature_set deprecated; | |
8522 | arm_feature_set obsoleted; | |
8523 | const char *dep_msg; | |
8524 | const char *obs_msg; | |
8525 | }; | |
8526 | ||
8527 | #define DEPR_ACCESS_V8 \ | |
8528 | N_("This coprocessor register access is deprecated in ARMv8") | |
8529 | ||
8530 | /* Table of all deprecated coprocessor registers. */ | |
8531 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
8532 | { | |
8533 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
823d2571 | 8534 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8535 | DEPR_ACCESS_V8, NULL}, |
8536 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
823d2571 | 8537 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8538 | DEPR_ACCESS_V8, NULL}, |
8539 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
823d2571 | 8540 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8541 | DEPR_ACCESS_V8, NULL}, |
8542 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
823d2571 | 8543 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8544 | DEPR_ACCESS_V8, NULL}, |
8545 | {14, 6, 0, 0, 0, /* TEECR. */ | |
823d2571 | 8546 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8547 | DEPR_ACCESS_V8, NULL}, |
8548 | }; | |
8549 | ||
8550 | #undef DEPR_ACCESS_V8 | |
8551 | ||
8552 | static const size_t deprecated_coproc_reg_count = | |
8553 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
8554 | ||
09d92015 | 8555 | static void |
c19d1205 | 8556 | do_co_reg (void) |
09d92015 | 8557 | { |
fdfde340 | 8558 | unsigned Rd; |
dcbd0d71 | 8559 | size_t i; |
fdfde340 JM |
8560 | |
8561 | Rd = inst.operands[2].reg; | |
8562 | if (thumb_mode) | |
8563 | { | |
8564 | if (inst.instruction == 0xee000010 | |
8565 | || inst.instruction == 0xfe000010) | |
8566 | /* MCR, MCR2 */ | |
8567 | reject_bad_reg (Rd); | |
8568 | else | |
8569 | /* MRC, MRC2 */ | |
8570 | constraint (Rd == REG_SP, BAD_SP); | |
8571 | } | |
8572 | else | |
8573 | { | |
8574 | /* MCR */ | |
8575 | if (inst.instruction == 0xe000010) | |
8576 | constraint (Rd == REG_PC, BAD_PC); | |
8577 | } | |
8578 | ||
dcbd0d71 MGD |
8579 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
8580 | { | |
8581 | const struct deprecated_coproc_regs_s *r = | |
8582 | deprecated_coproc_regs + i; | |
8583 | ||
8584 | if (inst.operands[0].reg == r->cp | |
8585 | && inst.operands[1].imm == r->opc1 | |
8586 | && inst.operands[3].reg == r->crn | |
8587 | && inst.operands[4].reg == r->crm | |
8588 | && inst.operands[5].imm == r->opc2) | |
8589 | { | |
b10bf8c5 | 8590 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 8591 | && warn_on_deprecated |
dcbd0d71 | 8592 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
5c3696f8 | 8593 | as_tsktsk ("%s", r->dep_msg); |
dcbd0d71 MGD |
8594 | } |
8595 | } | |
fdfde340 | 8596 | |
c19d1205 ZW |
8597 | inst.instruction |= inst.operands[0].reg << 8; |
8598 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 8599 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
8600 | inst.instruction |= inst.operands[3].reg << 16; |
8601 | inst.instruction |= inst.operands[4].reg; | |
8602 | inst.instruction |= inst.operands[5].imm << 5; | |
8603 | } | |
09d92015 | 8604 | |
c19d1205 ZW |
8605 | /* Transfer between coprocessor register and pair of ARM registers. |
8606 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
8607 | MCRR2 | |
8608 | MRRC{cond} | |
8609 | MRRC2 | |
b99bd4ef | 8610 | |
c19d1205 | 8611 | Two XScale instructions are special cases of these: |
09d92015 | 8612 | |
c19d1205 ZW |
8613 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
8614 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 8615 | |
5f4273c7 | 8616 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 8617 | |
c19d1205 ZW |
8618 | static void |
8619 | do_co_reg2c (void) | |
8620 | { | |
fdfde340 JM |
8621 | unsigned Rd, Rn; |
8622 | ||
8623 | Rd = inst.operands[2].reg; | |
8624 | Rn = inst.operands[3].reg; | |
8625 | ||
8626 | if (thumb_mode) | |
8627 | { | |
8628 | reject_bad_reg (Rd); | |
8629 | reject_bad_reg (Rn); | |
8630 | } | |
8631 | else | |
8632 | { | |
8633 | constraint (Rd == REG_PC, BAD_PC); | |
8634 | constraint (Rn == REG_PC, BAD_PC); | |
8635 | } | |
8636 | ||
c19d1205 ZW |
8637 | inst.instruction |= inst.operands[0].reg << 8; |
8638 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
8639 | inst.instruction |= Rd << 12; |
8640 | inst.instruction |= Rn << 16; | |
c19d1205 | 8641 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
8642 | } |
8643 | ||
c19d1205 ZW |
8644 | static void |
8645 | do_cpsi (void) | |
8646 | { | |
8647 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
8648 | if (inst.operands[1].present) |
8649 | { | |
8650 | inst.instruction |= CPSI_MMOD; | |
8651 | inst.instruction |= inst.operands[1].imm; | |
8652 | } | |
c19d1205 | 8653 | } |
b99bd4ef | 8654 | |
62b3e311 PB |
8655 | static void |
8656 | do_dbg (void) | |
8657 | { | |
8658 | inst.instruction |= inst.operands[0].imm; | |
8659 | } | |
8660 | ||
eea54501 MGD |
8661 | static void |
8662 | do_div (void) | |
8663 | { | |
8664 | unsigned Rd, Rn, Rm; | |
8665 | ||
8666 | Rd = inst.operands[0].reg; | |
8667 | Rn = (inst.operands[1].present | |
8668 | ? inst.operands[1].reg : Rd); | |
8669 | Rm = inst.operands[2].reg; | |
8670 | ||
8671 | constraint ((Rd == REG_PC), BAD_PC); | |
8672 | constraint ((Rn == REG_PC), BAD_PC); | |
8673 | constraint ((Rm == REG_PC), BAD_PC); | |
8674 | ||
8675 | inst.instruction |= Rd << 16; | |
8676 | inst.instruction |= Rn << 0; | |
8677 | inst.instruction |= Rm << 8; | |
8678 | } | |
8679 | ||
b99bd4ef | 8680 | static void |
c19d1205 | 8681 | do_it (void) |
b99bd4ef | 8682 | { |
c19d1205 | 8683 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
8684 | process it to do the validation as if in |
8685 | thumb mode, just in case the code gets | |
8686 | assembled for thumb using the unified syntax. */ | |
8687 | ||
c19d1205 | 8688 | inst.size = 0; |
e07e6e58 NC |
8689 | if (unified_syntax) |
8690 | { | |
8691 | set_it_insn_type (IT_INSN); | |
8692 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
8693 | now_it.cc = inst.operands[0].imm; | |
8694 | } | |
09d92015 | 8695 | } |
b99bd4ef | 8696 | |
6530b175 NC |
8697 | /* If there is only one register in the register list, |
8698 | then return its register number. Otherwise return -1. */ | |
8699 | static int | |
8700 | only_one_reg_in_list (int range) | |
8701 | { | |
8702 | int i = ffs (range) - 1; | |
8703 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
8704 | } | |
8705 | ||
09d92015 | 8706 | static void |
6530b175 | 8707 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 8708 | { |
c19d1205 ZW |
8709 | int base_reg = inst.operands[0].reg; |
8710 | int range = inst.operands[1].imm; | |
6530b175 | 8711 | int one_reg; |
ea6ef066 | 8712 | |
c19d1205 ZW |
8713 | inst.instruction |= base_reg << 16; |
8714 | inst.instruction |= range; | |
ea6ef066 | 8715 | |
c19d1205 ZW |
8716 | if (inst.operands[1].writeback) |
8717 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 8718 | |
c19d1205 | 8719 | if (inst.operands[0].writeback) |
ea6ef066 | 8720 | { |
c19d1205 ZW |
8721 | inst.instruction |= WRITE_BACK; |
8722 | /* Check for unpredictable uses of writeback. */ | |
8723 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 8724 | { |
c19d1205 ZW |
8725 | /* Not allowed in LDM type 2. */ |
8726 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
8727 | && ((range & (1 << REG_PC)) == 0)) | |
8728 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8729 | /* Only allowed if base reg not in list for other types. */ | |
8730 | else if (range & (1 << base_reg)) | |
8731 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
8732 | } | |
8733 | else /* STM. */ | |
8734 | { | |
8735 | /* Not allowed for type 2. */ | |
8736 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
8737 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8738 | /* Only allowed if base reg not in list, or first in list. */ | |
8739 | else if ((range & (1 << base_reg)) | |
8740 | && (range & ((1 << base_reg) - 1))) | |
8741 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 8742 | } |
ea6ef066 | 8743 | } |
6530b175 NC |
8744 | |
8745 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
8746 | one_reg = only_one_reg_in_list (range); | |
8747 | if (from_push_pop_mnem && one_reg >= 0) | |
8748 | { | |
8749 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
8750 | ||
8751 | inst.instruction &= A_COND_MASK; | |
8752 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
8753 | inst.instruction |= one_reg << 12; | |
8754 | } | |
8755 | } | |
8756 | ||
8757 | static void | |
8758 | do_ldmstm (void) | |
8759 | { | |
8760 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
8761 | } |
8762 | ||
c19d1205 ZW |
8763 | /* ARMv5TE load-consecutive (argument parse) |
8764 | Mode is like LDRH. | |
8765 | ||
8766 | LDRccD R, mode | |
8767 | STRccD R, mode. */ | |
8768 | ||
a737bd4d | 8769 | static void |
c19d1205 | 8770 | do_ldrd (void) |
a737bd4d | 8771 | { |
c19d1205 | 8772 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 8773 | _("first transfer register must be even")); |
c19d1205 ZW |
8774 | constraint (inst.operands[1].present |
8775 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 8776 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
8777 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
8778 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 8779 | |
c19d1205 ZW |
8780 | if (!inst.operands[1].present) |
8781 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 8782 | |
c56791bb RE |
8783 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
8784 | register and the first register written; we have to diagnose | |
8785 | overlap between the base and the second register written here. */ | |
ea6ef066 | 8786 | |
c56791bb RE |
8787 | if (inst.operands[2].reg == inst.operands[1].reg |
8788 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
8789 | as_warn (_("base register written back, and overlaps " | |
8790 | "second transfer register")); | |
b05fe5cf | 8791 | |
c56791bb RE |
8792 | if (!(inst.instruction & V4_STR_BIT)) |
8793 | { | |
c19d1205 | 8794 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
8795 | destination (even if not write-back). */ |
8796 | if (inst.operands[2].immisreg | |
8797 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
8798 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
8799 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 8800 | } |
c19d1205 ZW |
8801 | inst.instruction |= inst.operands[0].reg << 12; |
8802 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8803 | } |
8804 | ||
8805 | static void | |
c19d1205 | 8806 | do_ldrex (void) |
b05fe5cf | 8807 | { |
c19d1205 ZW |
8808 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8809 | || inst.operands[1].postind || inst.operands[1].writeback | |
8810 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8811 | || inst.operands[1].negative |
8812 | /* This can arise if the programmer has written | |
8813 | strex rN, rM, foo | |
8814 | or if they have mistakenly used a register name as the last | |
8815 | operand, eg: | |
8816 | strex rN, rM, rX | |
8817 | It is very difficult to distinguish between these two cases | |
8818 | because "rX" might actually be a label. ie the register | |
8819 | name has been occluded by a symbol of the same name. So we | |
8820 | just generate a general 'bad addressing mode' type error | |
8821 | message and leave it up to the programmer to discover the | |
8822 | true cause and fix their mistake. */ | |
8823 | || (inst.operands[1].reg == REG_PC), | |
8824 | BAD_ADDR_MODE); | |
b05fe5cf | 8825 | |
c19d1205 ZW |
8826 | constraint (inst.reloc.exp.X_op != O_constant |
8827 | || inst.reloc.exp.X_add_number != 0, | |
8828 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 8829 | |
5be8be5d DG |
8830 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
8831 | ||
c19d1205 ZW |
8832 | inst.instruction |= inst.operands[0].reg << 12; |
8833 | inst.instruction |= inst.operands[1].reg << 16; | |
8834 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
8835 | } |
8836 | ||
8837 | static void | |
c19d1205 | 8838 | do_ldrexd (void) |
b05fe5cf | 8839 | { |
c19d1205 ZW |
8840 | constraint (inst.operands[0].reg % 2 != 0, |
8841 | _("even register required")); | |
8842 | constraint (inst.operands[1].present | |
8843 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
8844 | _("can only load two consecutive registers")); | |
8845 | /* If op 1 were present and equal to PC, this function wouldn't | |
8846 | have been called in the first place. */ | |
8847 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 8848 | |
c19d1205 ZW |
8849 | inst.instruction |= inst.operands[0].reg << 12; |
8850 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
8851 | } |
8852 | ||
1be5fd2e NC |
8853 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
8854 | which is not a multiple of four is UNPREDICTABLE. */ | |
8855 | static void | |
8856 | check_ldr_r15_aligned (void) | |
8857 | { | |
8858 | constraint (!(inst.operands[1].immisreg) | |
8859 | && (inst.operands[0].reg == REG_PC | |
8860 | && inst.operands[1].reg == REG_PC | |
8861 | && (inst.reloc.exp.X_add_number & 0x3)), | |
8862 | _("ldr to register 15 must be 4-byte alligned")); | |
8863 | } | |
8864 | ||
b05fe5cf | 8865 | static void |
c19d1205 | 8866 | do_ldst (void) |
b05fe5cf | 8867 | { |
c19d1205 ZW |
8868 | inst.instruction |= inst.operands[0].reg << 12; |
8869 | if (!inst.operands[1].isreg) | |
8335d6aa | 8870 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 8871 | return; |
c19d1205 | 8872 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 8873 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
8874 | } |
8875 | ||
8876 | static void | |
c19d1205 | 8877 | do_ldstt (void) |
b05fe5cf | 8878 | { |
c19d1205 ZW |
8879 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8880 | reject [Rn,...]. */ | |
8881 | if (inst.operands[1].preind) | |
b05fe5cf | 8882 | { |
bd3ba5d1 NC |
8883 | constraint (inst.reloc.exp.X_op != O_constant |
8884 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8885 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8886 | |
c19d1205 ZW |
8887 | inst.operands[1].preind = 0; |
8888 | inst.operands[1].postind = 1; | |
8889 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8890 | } |
c19d1205 ZW |
8891 | inst.instruction |= inst.operands[0].reg << 12; |
8892 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
8893 | } | |
b05fe5cf | 8894 | |
c19d1205 | 8895 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 8896 | |
c19d1205 ZW |
8897 | static void |
8898 | do_ldstv4 (void) | |
8899 | { | |
ff4a8d2b | 8900 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
8901 | inst.instruction |= inst.operands[0].reg << 12; |
8902 | if (!inst.operands[1].isreg) | |
8335d6aa | 8903 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 8904 | return; |
c19d1205 | 8905 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
8906 | } |
8907 | ||
8908 | static void | |
c19d1205 | 8909 | do_ldsttv4 (void) |
b05fe5cf | 8910 | { |
c19d1205 ZW |
8911 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8912 | reject [Rn,...]. */ | |
8913 | if (inst.operands[1].preind) | |
b05fe5cf | 8914 | { |
bd3ba5d1 NC |
8915 | constraint (inst.reloc.exp.X_op != O_constant |
8916 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8917 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8918 | |
c19d1205 ZW |
8919 | inst.operands[1].preind = 0; |
8920 | inst.operands[1].postind = 1; | |
8921 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8922 | } |
c19d1205 ZW |
8923 | inst.instruction |= inst.operands[0].reg << 12; |
8924 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
8925 | } | |
b05fe5cf | 8926 | |
c19d1205 ZW |
8927 | /* Co-processor register load/store. |
8928 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8929 | static void | |
8930 | do_lstc (void) | |
8931 | { | |
8932 | inst.instruction |= inst.operands[0].reg << 8; | |
8933 | inst.instruction |= inst.operands[1].reg << 12; | |
8934 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8935 | } |
8936 | ||
b05fe5cf | 8937 | static void |
c19d1205 | 8938 | do_mlas (void) |
b05fe5cf | 8939 | { |
8fb9d7b9 | 8940 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8941 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8942 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8943 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8944 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8945 | |
c19d1205 ZW |
8946 | inst.instruction |= inst.operands[0].reg << 16; |
8947 | inst.instruction |= inst.operands[1].reg; | |
8948 | inst.instruction |= inst.operands[2].reg << 8; | |
8949 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8950 | } |
b05fe5cf | 8951 | |
c19d1205 ZW |
8952 | static void |
8953 | do_mov (void) | |
8954 | { | |
8955 | inst.instruction |= inst.operands[0].reg << 12; | |
8956 | encode_arm_shifter_operand (1); | |
8957 | } | |
b05fe5cf | 8958 | |
c19d1205 ZW |
8959 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8960 | static void | |
8961 | do_mov16 (void) | |
8962 | { | |
b6895b4f PB |
8963 | bfd_vma imm; |
8964 | bfd_boolean top; | |
8965 | ||
8966 | top = (inst.instruction & 0x00400000) != 0; | |
8967 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8968 | _(":lower16: not allowed this instruction")); | |
8969 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8970 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8971 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8972 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8973 | { | |
8974 | imm = inst.reloc.exp.X_add_number; | |
8975 | /* The value is in two pieces: 0:11, 16:19. */ | |
8976 | inst.instruction |= (imm & 0x00000fff); | |
8977 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8978 | } | |
b05fe5cf | 8979 | } |
b99bd4ef | 8980 | |
037e8744 JB |
8981 | static int |
8982 | do_vfp_nsyn_mrs (void) | |
8983 | { | |
8984 | if (inst.operands[0].isvec) | |
8985 | { | |
8986 | if (inst.operands[1].reg != 1) | |
477330fc | 8987 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
8988 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
8989 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8990 | do_vfp_nsyn_opcode ("fmstat"); | |
8991 | } | |
8992 | else if (inst.operands[1].isvec) | |
8993 | do_vfp_nsyn_opcode ("fmrx"); | |
8994 | else | |
8995 | return FAIL; | |
5f4273c7 | 8996 | |
037e8744 JB |
8997 | return SUCCESS; |
8998 | } | |
8999 | ||
9000 | static int | |
9001 | do_vfp_nsyn_msr (void) | |
9002 | { | |
9003 | if (inst.operands[0].isvec) | |
9004 | do_vfp_nsyn_opcode ("fmxr"); | |
9005 | else | |
9006 | return FAIL; | |
9007 | ||
9008 | return SUCCESS; | |
9009 | } | |
9010 | ||
f7c21dc7 NC |
9011 | static void |
9012 | do_vmrs (void) | |
9013 | { | |
9014 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 9015 | |
16d02dc9 | 9016 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
9017 | { |
9018 | inst.error = BAD_SP; | |
9019 | return; | |
9020 | } | |
9021 | ||
9022 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
16d02dc9 | 9023 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
9024 | { |
9025 | inst.error = BAD_PC; | |
9026 | return; | |
9027 | } | |
9028 | ||
16d02dc9 JB |
9029 | /* If we get through parsing the register name, we just insert the number |
9030 | generated into the instruction without further validation. */ | |
9031 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
9032 | inst.instruction |= (Rt << 12); |
9033 | } | |
9034 | ||
9035 | static void | |
9036 | do_vmsr (void) | |
9037 | { | |
9038 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 9039 | |
f7c21dc7 NC |
9040 | if (thumb_mode) |
9041 | reject_bad_reg (Rt); | |
9042 | else if (Rt == REG_PC) | |
9043 | { | |
9044 | inst.error = BAD_PC; | |
9045 | return; | |
9046 | } | |
9047 | ||
16d02dc9 JB |
9048 | /* If we get through parsing the register name, we just insert the number |
9049 | generated into the instruction without further validation. */ | |
9050 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
9051 | inst.instruction |= (Rt << 12); |
9052 | } | |
9053 | ||
b99bd4ef | 9054 | static void |
c19d1205 | 9055 | do_mrs (void) |
b99bd4ef | 9056 | { |
90ec0d68 MGD |
9057 | unsigned br; |
9058 | ||
037e8744 JB |
9059 | if (do_vfp_nsyn_mrs () == SUCCESS) |
9060 | return; | |
9061 | ||
ff4a8d2b | 9062 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 9063 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
9064 | |
9065 | if (inst.operands[1].isreg) | |
9066 | { | |
9067 | br = inst.operands[1].reg; | |
9068 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
9069 | as_bad (_("bad register for mrs")); | |
9070 | } | |
9071 | else | |
9072 | { | |
9073 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
9074 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
9075 | != (PSR_c|PSR_f), | |
d2cd1205 | 9076 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
9077 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
9078 | } | |
9079 | ||
9080 | inst.instruction |= br; | |
c19d1205 | 9081 | } |
b99bd4ef | 9082 | |
c19d1205 ZW |
9083 | /* Two possible forms: |
9084 | "{C|S}PSR_<field>, Rm", | |
9085 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 9086 | |
c19d1205 ZW |
9087 | static void |
9088 | do_msr (void) | |
9089 | { | |
037e8744 JB |
9090 | if (do_vfp_nsyn_msr () == SUCCESS) |
9091 | return; | |
9092 | ||
c19d1205 ZW |
9093 | inst.instruction |= inst.operands[0].imm; |
9094 | if (inst.operands[1].isreg) | |
9095 | inst.instruction |= inst.operands[1].reg; | |
9096 | else | |
b99bd4ef | 9097 | { |
c19d1205 ZW |
9098 | inst.instruction |= INST_IMMEDIATE; |
9099 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
9100 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 9101 | } |
b99bd4ef NC |
9102 | } |
9103 | ||
c19d1205 ZW |
9104 | static void |
9105 | do_mul (void) | |
a737bd4d | 9106 | { |
ff4a8d2b NC |
9107 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
9108 | ||
c19d1205 ZW |
9109 | if (!inst.operands[2].present) |
9110 | inst.operands[2].reg = inst.operands[0].reg; | |
9111 | inst.instruction |= inst.operands[0].reg << 16; | |
9112 | inst.instruction |= inst.operands[1].reg; | |
9113 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 9114 | |
8fb9d7b9 MS |
9115 | if (inst.operands[0].reg == inst.operands[1].reg |
9116 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
9117 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
9118 | } |
9119 | ||
c19d1205 ZW |
9120 | /* Long Multiply Parser |
9121 | UMULL RdLo, RdHi, Rm, Rs | |
9122 | SMULL RdLo, RdHi, Rm, Rs | |
9123 | UMLAL RdLo, RdHi, Rm, Rs | |
9124 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
9125 | |
9126 | static void | |
c19d1205 | 9127 | do_mull (void) |
b99bd4ef | 9128 | { |
c19d1205 ZW |
9129 | inst.instruction |= inst.operands[0].reg << 12; |
9130 | inst.instruction |= inst.operands[1].reg << 16; | |
9131 | inst.instruction |= inst.operands[2].reg; | |
9132 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 9133 | |
682b27ad PB |
9134 | /* rdhi and rdlo must be different. */ |
9135 | if (inst.operands[0].reg == inst.operands[1].reg) | |
9136 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9137 | ||
9138 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
9139 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 9140 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 9141 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
9142 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
9143 | } | |
b99bd4ef | 9144 | |
c19d1205 ZW |
9145 | static void |
9146 | do_nop (void) | |
9147 | { | |
e7495e45 NS |
9148 | if (inst.operands[0].present |
9149 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
9150 | { |
9151 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
9152 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
9153 | inst.instruction |= 0x0320f000; |
9154 | if (inst.operands[0].present) | |
9155 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 9156 | } |
b99bd4ef NC |
9157 | } |
9158 | ||
c19d1205 ZW |
9159 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
9160 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
9161 | Condition defaults to COND_ALWAYS. | |
9162 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
9163 | |
9164 | static void | |
c19d1205 | 9165 | do_pkhbt (void) |
b99bd4ef | 9166 | { |
c19d1205 ZW |
9167 | inst.instruction |= inst.operands[0].reg << 12; |
9168 | inst.instruction |= inst.operands[1].reg << 16; | |
9169 | inst.instruction |= inst.operands[2].reg; | |
9170 | if (inst.operands[3].present) | |
9171 | encode_arm_shift (3); | |
9172 | } | |
b99bd4ef | 9173 | |
c19d1205 | 9174 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 9175 | |
c19d1205 ZW |
9176 | static void |
9177 | do_pkhtb (void) | |
9178 | { | |
9179 | if (!inst.operands[3].present) | |
b99bd4ef | 9180 | { |
c19d1205 ZW |
9181 | /* If the shift specifier is omitted, turn the instruction |
9182 | into pkhbt rd, rm, rn. */ | |
9183 | inst.instruction &= 0xfff00010; | |
9184 | inst.instruction |= inst.operands[0].reg << 12; | |
9185 | inst.instruction |= inst.operands[1].reg; | |
9186 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9187 | } |
9188 | else | |
9189 | { | |
c19d1205 ZW |
9190 | inst.instruction |= inst.operands[0].reg << 12; |
9191 | inst.instruction |= inst.operands[1].reg << 16; | |
9192 | inst.instruction |= inst.operands[2].reg; | |
9193 | encode_arm_shift (3); | |
b99bd4ef NC |
9194 | } |
9195 | } | |
9196 | ||
c19d1205 | 9197 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 9198 | MP Extensions: Preload for write |
c19d1205 | 9199 | |
60e5ef9f | 9200 | PLD(W) <addr_mode> |
c19d1205 ZW |
9201 | |
9202 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
9203 | |
9204 | static void | |
c19d1205 | 9205 | do_pld (void) |
b99bd4ef | 9206 | { |
c19d1205 ZW |
9207 | constraint (!inst.operands[0].isreg, |
9208 | _("'[' expected after PLD mnemonic")); | |
9209 | constraint (inst.operands[0].postind, | |
9210 | _("post-indexed expression used in preload instruction")); | |
9211 | constraint (inst.operands[0].writeback, | |
9212 | _("writeback used in preload instruction")); | |
9213 | constraint (!inst.operands[0].preind, | |
9214 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
9215 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
9216 | } | |
b99bd4ef | 9217 | |
62b3e311 PB |
9218 | /* ARMv7: PLI <addr_mode> */ |
9219 | static void | |
9220 | do_pli (void) | |
9221 | { | |
9222 | constraint (!inst.operands[0].isreg, | |
9223 | _("'[' expected after PLI mnemonic")); | |
9224 | constraint (inst.operands[0].postind, | |
9225 | _("post-indexed expression used in preload instruction")); | |
9226 | constraint (inst.operands[0].writeback, | |
9227 | _("writeback used in preload instruction")); | |
9228 | constraint (!inst.operands[0].preind, | |
9229 | _("unindexed addressing used in preload instruction")); | |
9230 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
9231 | inst.instruction &= ~PRE_INDEX; | |
9232 | } | |
9233 | ||
c19d1205 ZW |
9234 | static void |
9235 | do_push_pop (void) | |
9236 | { | |
5e0d7f77 MP |
9237 | constraint (inst.operands[0].writeback, |
9238 | _("push/pop do not support {reglist}^")); | |
c19d1205 ZW |
9239 | inst.operands[1] = inst.operands[0]; |
9240 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
9241 | inst.operands[0].isreg = 1; | |
9242 | inst.operands[0].writeback = 1; | |
9243 | inst.operands[0].reg = REG_SP; | |
6530b175 | 9244 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 9245 | } |
b99bd4ef | 9246 | |
c19d1205 ZW |
9247 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
9248 | word at the specified address and the following word | |
9249 | respectively. | |
9250 | Unconditionally executed. | |
9251 | Error if Rn is R15. */ | |
b99bd4ef | 9252 | |
c19d1205 ZW |
9253 | static void |
9254 | do_rfe (void) | |
9255 | { | |
9256 | inst.instruction |= inst.operands[0].reg << 16; | |
9257 | if (inst.operands[0].writeback) | |
9258 | inst.instruction |= WRITE_BACK; | |
9259 | } | |
b99bd4ef | 9260 | |
c19d1205 | 9261 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 9262 | |
c19d1205 ZW |
9263 | static void |
9264 | do_ssat (void) | |
9265 | { | |
9266 | inst.instruction |= inst.operands[0].reg << 12; | |
9267 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
9268 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9269 | |
c19d1205 ZW |
9270 | if (inst.operands[3].present) |
9271 | encode_arm_shift (3); | |
b99bd4ef NC |
9272 | } |
9273 | ||
c19d1205 | 9274 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
9275 | |
9276 | static void | |
c19d1205 | 9277 | do_usat (void) |
b99bd4ef | 9278 | { |
c19d1205 ZW |
9279 | inst.instruction |= inst.operands[0].reg << 12; |
9280 | inst.instruction |= inst.operands[1].imm << 16; | |
9281 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9282 | |
c19d1205 ZW |
9283 | if (inst.operands[3].present) |
9284 | encode_arm_shift (3); | |
b99bd4ef NC |
9285 | } |
9286 | ||
c19d1205 | 9287 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
9288 | |
9289 | static void | |
c19d1205 | 9290 | do_ssat16 (void) |
09d92015 | 9291 | { |
c19d1205 ZW |
9292 | inst.instruction |= inst.operands[0].reg << 12; |
9293 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
9294 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
9295 | } |
9296 | ||
c19d1205 ZW |
9297 | static void |
9298 | do_usat16 (void) | |
a737bd4d | 9299 | { |
c19d1205 ZW |
9300 | inst.instruction |= inst.operands[0].reg << 12; |
9301 | inst.instruction |= inst.operands[1].imm << 16; | |
9302 | inst.instruction |= inst.operands[2].reg; | |
9303 | } | |
a737bd4d | 9304 | |
c19d1205 ZW |
9305 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
9306 | preserving the other bits. | |
a737bd4d | 9307 | |
c19d1205 ZW |
9308 | setend <endian_specifier>, where <endian_specifier> is either |
9309 | BE or LE. */ | |
a737bd4d | 9310 | |
c19d1205 ZW |
9311 | static void |
9312 | do_setend (void) | |
9313 | { | |
12e37cbc MGD |
9314 | if (warn_on_deprecated |
9315 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 9316 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 9317 | |
c19d1205 ZW |
9318 | if (inst.operands[0].imm) |
9319 | inst.instruction |= 0x200; | |
a737bd4d NC |
9320 | } |
9321 | ||
9322 | static void | |
c19d1205 | 9323 | do_shift (void) |
a737bd4d | 9324 | { |
c19d1205 ZW |
9325 | unsigned int Rm = (inst.operands[1].present |
9326 | ? inst.operands[1].reg | |
9327 | : inst.operands[0].reg); | |
a737bd4d | 9328 | |
c19d1205 ZW |
9329 | inst.instruction |= inst.operands[0].reg << 12; |
9330 | inst.instruction |= Rm; | |
9331 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 9332 | { |
c19d1205 ZW |
9333 | inst.instruction |= inst.operands[2].reg << 8; |
9334 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
9335 | /* PR 12854: Error on extraneous shifts. */ |
9336 | constraint (inst.operands[2].shifted, | |
9337 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
9338 | } |
9339 | else | |
c19d1205 | 9340 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
9341 | } |
9342 | ||
09d92015 | 9343 | static void |
3eb17e6b | 9344 | do_smc (void) |
09d92015 | 9345 | { |
3eb17e6b | 9346 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 9347 | inst.reloc.pc_rel = 0; |
09d92015 MM |
9348 | } |
9349 | ||
90ec0d68 MGD |
9350 | static void |
9351 | do_hvc (void) | |
9352 | { | |
9353 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
9354 | inst.reloc.pc_rel = 0; | |
9355 | } | |
9356 | ||
09d92015 | 9357 | static void |
c19d1205 | 9358 | do_swi (void) |
09d92015 | 9359 | { |
c19d1205 ZW |
9360 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
9361 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
9362 | } |
9363 | ||
ddfded2f MW |
9364 | static void |
9365 | do_setpan (void) | |
9366 | { | |
9367 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
9368 | _("selected processor does not support SETPAN instruction")); | |
9369 | ||
9370 | inst.instruction |= ((inst.operands[0].imm & 1) << 9); | |
9371 | } | |
9372 | ||
9373 | static void | |
9374 | do_t_setpan (void) | |
9375 | { | |
9376 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
9377 | _("selected processor does not support SETPAN instruction")); | |
9378 | ||
9379 | inst.instruction |= (inst.operands[0].imm << 3); | |
9380 | } | |
9381 | ||
c19d1205 ZW |
9382 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
9383 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
9384 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
9385 | Error if any register is R15. */ | |
e16bb312 | 9386 | |
c19d1205 ZW |
9387 | static void |
9388 | do_smla (void) | |
e16bb312 | 9389 | { |
c19d1205 ZW |
9390 | inst.instruction |= inst.operands[0].reg << 16; |
9391 | inst.instruction |= inst.operands[1].reg; | |
9392 | inst.instruction |= inst.operands[2].reg << 8; | |
9393 | inst.instruction |= inst.operands[3].reg << 12; | |
9394 | } | |
a737bd4d | 9395 | |
c19d1205 ZW |
9396 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
9397 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
9398 | Error if any register is R15. | |
9399 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 9400 | |
c19d1205 ZW |
9401 | static void |
9402 | do_smlal (void) | |
9403 | { | |
9404 | inst.instruction |= inst.operands[0].reg << 12; | |
9405 | inst.instruction |= inst.operands[1].reg << 16; | |
9406 | inst.instruction |= inst.operands[2].reg; | |
9407 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 9408 | |
c19d1205 ZW |
9409 | if (inst.operands[0].reg == inst.operands[1].reg) |
9410 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9411 | } | |
a737bd4d | 9412 | |
c19d1205 ZW |
9413 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
9414 | SMULxy{cond} Rd,Rm,Rs | |
9415 | Error if any register is R15. */ | |
a737bd4d | 9416 | |
c19d1205 ZW |
9417 | static void |
9418 | do_smul (void) | |
9419 | { | |
9420 | inst.instruction |= inst.operands[0].reg << 16; | |
9421 | inst.instruction |= inst.operands[1].reg; | |
9422 | inst.instruction |= inst.operands[2].reg << 8; | |
9423 | } | |
a737bd4d | 9424 | |
b6702015 PB |
9425 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
9426 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 9427 | |
c19d1205 ZW |
9428 | static void |
9429 | do_srs (void) | |
9430 | { | |
b6702015 PB |
9431 | int reg; |
9432 | ||
9433 | if (inst.operands[0].present) | |
9434 | { | |
9435 | reg = inst.operands[0].reg; | |
fdfde340 | 9436 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
9437 | } |
9438 | else | |
fdfde340 | 9439 | reg = REG_SP; |
b6702015 PB |
9440 | |
9441 | inst.instruction |= reg << 16; | |
9442 | inst.instruction |= inst.operands[1].imm; | |
9443 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
9444 | inst.instruction |= WRITE_BACK; |
9445 | } | |
a737bd4d | 9446 | |
c19d1205 | 9447 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 9448 | |
c19d1205 ZW |
9449 | static void |
9450 | do_strex (void) | |
9451 | { | |
9452 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9453 | || inst.operands[2].postind || inst.operands[2].writeback | |
9454 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
9455 | || inst.operands[2].negative |
9456 | /* See comment in do_ldrex(). */ | |
9457 | || (inst.operands[2].reg == REG_PC), | |
9458 | BAD_ADDR_MODE); | |
a737bd4d | 9459 | |
c19d1205 ZW |
9460 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9461 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 9462 | |
c19d1205 ZW |
9463 | constraint (inst.reloc.exp.X_op != O_constant |
9464 | || inst.reloc.exp.X_add_number != 0, | |
9465 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 9466 | |
c19d1205 ZW |
9467 | inst.instruction |= inst.operands[0].reg << 12; |
9468 | inst.instruction |= inst.operands[1].reg; | |
9469 | inst.instruction |= inst.operands[2].reg << 16; | |
9470 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
9471 | } |
9472 | ||
877807f8 NC |
9473 | static void |
9474 | do_t_strexbh (void) | |
9475 | { | |
9476 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9477 | || inst.operands[2].postind || inst.operands[2].writeback | |
9478 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
9479 | || inst.operands[2].negative, | |
9480 | BAD_ADDR_MODE); | |
9481 | ||
9482 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9483 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9484 | ||
9485 | do_rm_rd_rn (); | |
9486 | } | |
9487 | ||
e16bb312 | 9488 | static void |
c19d1205 | 9489 | do_strexd (void) |
e16bb312 | 9490 | { |
c19d1205 ZW |
9491 | constraint (inst.operands[1].reg % 2 != 0, |
9492 | _("even register required")); | |
9493 | constraint (inst.operands[2].present | |
9494 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
9495 | _("can only store two consecutive registers")); | |
9496 | /* If op 2 were present and equal to PC, this function wouldn't | |
9497 | have been called in the first place. */ | |
9498 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 9499 | |
c19d1205 ZW |
9500 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9501 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
9502 | || inst.operands[0].reg == inst.operands[3].reg, | |
9503 | BAD_OVERLAP); | |
e16bb312 | 9504 | |
c19d1205 ZW |
9505 | inst.instruction |= inst.operands[0].reg << 12; |
9506 | inst.instruction |= inst.operands[1].reg; | |
9507 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
9508 | } |
9509 | ||
9eb6c0f1 MGD |
9510 | /* ARM V8 STRL. */ |
9511 | static void | |
4b8c8c02 | 9512 | do_stlex (void) |
9eb6c0f1 MGD |
9513 | { |
9514 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9515 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9516 | ||
9517 | do_rd_rm_rn (); | |
9518 | } | |
9519 | ||
9520 | static void | |
4b8c8c02 | 9521 | do_t_stlex (void) |
9eb6c0f1 MGD |
9522 | { |
9523 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9524 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9525 | ||
9526 | do_rm_rd_rn (); | |
9527 | } | |
9528 | ||
c19d1205 ZW |
9529 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
9530 | extends it to 32-bits, and adds the result to a value in another | |
9531 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
9532 | before extracting the 16-bit value. | |
9533 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
9534 | Condition defaults to COND_ALWAYS. | |
9535 | Error if any register uses R15. */ | |
9536 | ||
e16bb312 | 9537 | static void |
c19d1205 | 9538 | do_sxtah (void) |
e16bb312 | 9539 | { |
c19d1205 ZW |
9540 | inst.instruction |= inst.operands[0].reg << 12; |
9541 | inst.instruction |= inst.operands[1].reg << 16; | |
9542 | inst.instruction |= inst.operands[2].reg; | |
9543 | inst.instruction |= inst.operands[3].imm << 10; | |
9544 | } | |
e16bb312 | 9545 | |
c19d1205 | 9546 | /* ARM V6 SXTH. |
e16bb312 | 9547 | |
c19d1205 ZW |
9548 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
9549 | Condition defaults to COND_ALWAYS. | |
9550 | Error if any register uses R15. */ | |
e16bb312 NC |
9551 | |
9552 | static void | |
c19d1205 | 9553 | do_sxth (void) |
e16bb312 | 9554 | { |
c19d1205 ZW |
9555 | inst.instruction |= inst.operands[0].reg << 12; |
9556 | inst.instruction |= inst.operands[1].reg; | |
9557 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 9558 | } |
c19d1205 ZW |
9559 | \f |
9560 | /* VFP instructions. In a logical order: SP variant first, monad | |
9561 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
9562 | |
9563 | static void | |
c19d1205 | 9564 | do_vfp_sp_monadic (void) |
e16bb312 | 9565 | { |
5287ad62 JB |
9566 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9567 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9568 | } |
9569 | ||
9570 | static void | |
c19d1205 | 9571 | do_vfp_sp_dyadic (void) |
e16bb312 | 9572 | { |
5287ad62 JB |
9573 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9574 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
9575 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
9576 | } |
9577 | ||
9578 | static void | |
c19d1205 | 9579 | do_vfp_sp_compare_z (void) |
e16bb312 | 9580 | { |
5287ad62 | 9581 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
9582 | } |
9583 | ||
9584 | static void | |
c19d1205 | 9585 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 9586 | { |
5287ad62 JB |
9587 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
9588 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9589 | } |
9590 | ||
9591 | static void | |
c19d1205 | 9592 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 9593 | { |
5287ad62 JB |
9594 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9595 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
9596 | } |
9597 | ||
9598 | static void | |
c19d1205 | 9599 | do_vfp_reg_from_sp (void) |
e16bb312 | 9600 | { |
c19d1205 | 9601 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 9602 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
9603 | } |
9604 | ||
9605 | static void | |
c19d1205 | 9606 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 9607 | { |
c19d1205 ZW |
9608 | constraint (inst.operands[2].imm != 2, |
9609 | _("only two consecutive VFP SP registers allowed here")); | |
9610 | inst.instruction |= inst.operands[0].reg << 12; | |
9611 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 9612 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
9613 | } |
9614 | ||
9615 | static void | |
c19d1205 | 9616 | do_vfp_sp_from_reg (void) |
e16bb312 | 9617 | { |
5287ad62 | 9618 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 9619 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
9620 | } |
9621 | ||
9622 | static void | |
c19d1205 | 9623 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 9624 | { |
c19d1205 ZW |
9625 | constraint (inst.operands[0].imm != 2, |
9626 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 9627 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
9628 | inst.instruction |= inst.operands[1].reg << 12; |
9629 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
9630 | } |
9631 | ||
9632 | static void | |
c19d1205 | 9633 | do_vfp_sp_ldst (void) |
e16bb312 | 9634 | { |
5287ad62 | 9635 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 9636 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9637 | } |
9638 | ||
9639 | static void | |
c19d1205 | 9640 | do_vfp_dp_ldst (void) |
e16bb312 | 9641 | { |
5287ad62 | 9642 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 9643 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9644 | } |
9645 | ||
c19d1205 | 9646 | |
e16bb312 | 9647 | static void |
c19d1205 | 9648 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9649 | { |
c19d1205 ZW |
9650 | if (inst.operands[0].writeback) |
9651 | inst.instruction |= WRITE_BACK; | |
9652 | else | |
9653 | constraint (ldstm_type != VFP_LDSTMIA, | |
9654 | _("this addressing mode requires base-register writeback")); | |
9655 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 9656 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 9657 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
9658 | } |
9659 | ||
9660 | static void | |
c19d1205 | 9661 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9662 | { |
c19d1205 | 9663 | int count; |
e16bb312 | 9664 | |
c19d1205 ZW |
9665 | if (inst.operands[0].writeback) |
9666 | inst.instruction |= WRITE_BACK; | |
9667 | else | |
9668 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
9669 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 9670 | |
c19d1205 | 9671 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 9672 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 9673 | |
c19d1205 ZW |
9674 | count = inst.operands[1].imm << 1; |
9675 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
9676 | count += 1; | |
e16bb312 | 9677 | |
c19d1205 | 9678 | inst.instruction |= count; |
e16bb312 NC |
9679 | } |
9680 | ||
9681 | static void | |
c19d1205 | 9682 | do_vfp_sp_ldstmia (void) |
e16bb312 | 9683 | { |
c19d1205 | 9684 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9685 | } |
9686 | ||
9687 | static void | |
c19d1205 | 9688 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 9689 | { |
c19d1205 | 9690 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9691 | } |
9692 | ||
9693 | static void | |
c19d1205 | 9694 | do_vfp_dp_ldstmia (void) |
e16bb312 | 9695 | { |
c19d1205 | 9696 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9697 | } |
9698 | ||
9699 | static void | |
c19d1205 | 9700 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 9701 | { |
c19d1205 | 9702 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9703 | } |
9704 | ||
9705 | static void | |
c19d1205 | 9706 | do_vfp_xp_ldstmia (void) |
e16bb312 | 9707 | { |
c19d1205 ZW |
9708 | vfp_dp_ldstm (VFP_LDSTMIAX); |
9709 | } | |
e16bb312 | 9710 | |
c19d1205 ZW |
9711 | static void |
9712 | do_vfp_xp_ldstmdb (void) | |
9713 | { | |
9714 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 9715 | } |
5287ad62 JB |
9716 | |
9717 | static void | |
9718 | do_vfp_dp_rd_rm (void) | |
9719 | { | |
9720 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9721 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
9722 | } | |
9723 | ||
9724 | static void | |
9725 | do_vfp_dp_rn_rd (void) | |
9726 | { | |
9727 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
9728 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9729 | } | |
9730 | ||
9731 | static void | |
9732 | do_vfp_dp_rd_rn (void) | |
9733 | { | |
9734 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9735 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9736 | } | |
9737 | ||
9738 | static void | |
9739 | do_vfp_dp_rd_rn_rm (void) | |
9740 | { | |
9741 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9742 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9743 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
9744 | } | |
9745 | ||
9746 | static void | |
9747 | do_vfp_dp_rd (void) | |
9748 | { | |
9749 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9750 | } | |
9751 | ||
9752 | static void | |
9753 | do_vfp_dp_rm_rd_rn (void) | |
9754 | { | |
9755 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
9756 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9757 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
9758 | } | |
9759 | ||
9760 | /* VFPv3 instructions. */ | |
9761 | static void | |
9762 | do_vfp_sp_const (void) | |
9763 | { | |
9764 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
9765 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9766 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9767 | } |
9768 | ||
9769 | static void | |
9770 | do_vfp_dp_const (void) | |
9771 | { | |
9772 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
9773 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9774 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9775 | } |
9776 | ||
9777 | static void | |
9778 | vfp_conv (int srcsize) | |
9779 | { | |
5f1af56b MGD |
9780 | int immbits = srcsize - inst.operands[1].imm; |
9781 | ||
fa94de6b RM |
9782 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
9783 | { | |
5f1af56b | 9784 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 9785 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
9786 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
9787 | return; | |
9788 | } | |
fa94de6b | 9789 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
9790 | { |
9791 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 9792 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
9793 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
9794 | return; | |
9795 | } | |
9796 | ||
5287ad62 JB |
9797 | inst.instruction |= (immbits & 1) << 5; |
9798 | inst.instruction |= (immbits >> 1); | |
9799 | } | |
9800 | ||
9801 | static void | |
9802 | do_vfp_sp_conv_16 (void) | |
9803 | { | |
9804 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9805 | vfp_conv (16); | |
9806 | } | |
9807 | ||
9808 | static void | |
9809 | do_vfp_dp_conv_16 (void) | |
9810 | { | |
9811 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9812 | vfp_conv (16); | |
9813 | } | |
9814 | ||
9815 | static void | |
9816 | do_vfp_sp_conv_32 (void) | |
9817 | { | |
9818 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9819 | vfp_conv (32); | |
9820 | } | |
9821 | ||
9822 | static void | |
9823 | do_vfp_dp_conv_32 (void) | |
9824 | { | |
9825 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9826 | vfp_conv (32); | |
9827 | } | |
c19d1205 ZW |
9828 | \f |
9829 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 9830 | |
c19d1205 ZW |
9831 | static void |
9832 | do_fpa_cmp (void) | |
9833 | { | |
9834 | inst.instruction |= inst.operands[0].reg << 16; | |
9835 | inst.instruction |= inst.operands[1].reg; | |
9836 | } | |
b99bd4ef NC |
9837 | |
9838 | static void | |
c19d1205 | 9839 | do_fpa_ldmstm (void) |
b99bd4ef | 9840 | { |
c19d1205 ZW |
9841 | inst.instruction |= inst.operands[0].reg << 12; |
9842 | switch (inst.operands[1].imm) | |
9843 | { | |
9844 | case 1: inst.instruction |= CP_T_X; break; | |
9845 | case 2: inst.instruction |= CP_T_Y; break; | |
9846 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
9847 | case 4: break; | |
9848 | default: abort (); | |
9849 | } | |
b99bd4ef | 9850 | |
c19d1205 ZW |
9851 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
9852 | { | |
9853 | /* The instruction specified "ea" or "fd", so we can only accept | |
9854 | [Rn]{!}. The instruction does not really support stacking or | |
9855 | unstacking, so we have to emulate these by setting appropriate | |
9856 | bits and offsets. */ | |
9857 | constraint (inst.reloc.exp.X_op != O_constant | |
9858 | || inst.reloc.exp.X_add_number != 0, | |
9859 | _("this instruction does not support indexing")); | |
b99bd4ef | 9860 | |
c19d1205 ZW |
9861 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
9862 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 9863 | |
c19d1205 ZW |
9864 | if (!(inst.instruction & INDEX_UP)) |
9865 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 9866 | |
c19d1205 ZW |
9867 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
9868 | { | |
9869 | inst.operands[2].preind = 0; | |
9870 | inst.operands[2].postind = 1; | |
9871 | } | |
9872 | } | |
b99bd4ef | 9873 | |
c19d1205 | 9874 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 9875 | } |
c19d1205 ZW |
9876 | \f |
9877 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 9878 | |
c19d1205 ZW |
9879 | static void |
9880 | do_iwmmxt_tandorc (void) | |
9881 | { | |
9882 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
9883 | } | |
b99bd4ef | 9884 | |
c19d1205 ZW |
9885 | static void |
9886 | do_iwmmxt_textrc (void) | |
9887 | { | |
9888 | inst.instruction |= inst.operands[0].reg << 12; | |
9889 | inst.instruction |= inst.operands[1].imm; | |
9890 | } | |
b99bd4ef NC |
9891 | |
9892 | static void | |
c19d1205 | 9893 | do_iwmmxt_textrm (void) |
b99bd4ef | 9894 | { |
c19d1205 ZW |
9895 | inst.instruction |= inst.operands[0].reg << 12; |
9896 | inst.instruction |= inst.operands[1].reg << 16; | |
9897 | inst.instruction |= inst.operands[2].imm; | |
9898 | } | |
b99bd4ef | 9899 | |
c19d1205 ZW |
9900 | static void |
9901 | do_iwmmxt_tinsr (void) | |
9902 | { | |
9903 | inst.instruction |= inst.operands[0].reg << 16; | |
9904 | inst.instruction |= inst.operands[1].reg << 12; | |
9905 | inst.instruction |= inst.operands[2].imm; | |
9906 | } | |
b99bd4ef | 9907 | |
c19d1205 ZW |
9908 | static void |
9909 | do_iwmmxt_tmia (void) | |
9910 | { | |
9911 | inst.instruction |= inst.operands[0].reg << 5; | |
9912 | inst.instruction |= inst.operands[1].reg; | |
9913 | inst.instruction |= inst.operands[2].reg << 12; | |
9914 | } | |
b99bd4ef | 9915 | |
c19d1205 ZW |
9916 | static void |
9917 | do_iwmmxt_waligni (void) | |
9918 | { | |
9919 | inst.instruction |= inst.operands[0].reg << 12; | |
9920 | inst.instruction |= inst.operands[1].reg << 16; | |
9921 | inst.instruction |= inst.operands[2].reg; | |
9922 | inst.instruction |= inst.operands[3].imm << 20; | |
9923 | } | |
b99bd4ef | 9924 | |
2d447fca JM |
9925 | static void |
9926 | do_iwmmxt_wmerge (void) | |
9927 | { | |
9928 | inst.instruction |= inst.operands[0].reg << 12; | |
9929 | inst.instruction |= inst.operands[1].reg << 16; | |
9930 | inst.instruction |= inst.operands[2].reg; | |
9931 | inst.instruction |= inst.operands[3].imm << 21; | |
9932 | } | |
9933 | ||
c19d1205 ZW |
9934 | static void |
9935 | do_iwmmxt_wmov (void) | |
9936 | { | |
9937 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
9938 | inst.instruction |= inst.operands[0].reg << 12; | |
9939 | inst.instruction |= inst.operands[1].reg << 16; | |
9940 | inst.instruction |= inst.operands[1].reg; | |
9941 | } | |
b99bd4ef | 9942 | |
c19d1205 ZW |
9943 | static void |
9944 | do_iwmmxt_wldstbh (void) | |
9945 | { | |
8f06b2d8 | 9946 | int reloc; |
c19d1205 | 9947 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
9948 | if (thumb_mode) |
9949 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
9950 | else | |
9951 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
9952 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
9953 | } |
9954 | ||
c19d1205 ZW |
9955 | static void |
9956 | do_iwmmxt_wldstw (void) | |
9957 | { | |
9958 | /* RIWR_RIWC clears .isreg for a control register. */ | |
9959 | if (!inst.operands[0].isreg) | |
9960 | { | |
9961 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
9962 | inst.instruction |= 0xf0000000; | |
9963 | } | |
b99bd4ef | 9964 | |
c19d1205 ZW |
9965 | inst.instruction |= inst.operands[0].reg << 12; |
9966 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
9967 | } | |
b99bd4ef NC |
9968 | |
9969 | static void | |
c19d1205 | 9970 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9971 | { |
c19d1205 | 9972 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9973 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9974 | && inst.operands[1].immisreg) | |
9975 | { | |
9976 | inst.instruction &= ~0x1a000ff; | |
9977 | inst.instruction |= (0xf << 28); | |
9978 | if (inst.operands[1].preind) | |
9979 | inst.instruction |= PRE_INDEX; | |
9980 | if (!inst.operands[1].negative) | |
9981 | inst.instruction |= INDEX_UP; | |
9982 | if (inst.operands[1].writeback) | |
9983 | inst.instruction |= WRITE_BACK; | |
9984 | inst.instruction |= inst.operands[1].reg << 16; | |
9985 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9986 | inst.instruction |= inst.operands[1].imm; | |
9987 | } | |
9988 | else | |
9989 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9990 | } |
b99bd4ef | 9991 | |
c19d1205 ZW |
9992 | static void |
9993 | do_iwmmxt_wshufh (void) | |
9994 | { | |
9995 | inst.instruction |= inst.operands[0].reg << 12; | |
9996 | inst.instruction |= inst.operands[1].reg << 16; | |
9997 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9998 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9999 | } | |
b99bd4ef | 10000 | |
c19d1205 ZW |
10001 | static void |
10002 | do_iwmmxt_wzero (void) | |
10003 | { | |
10004 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
10005 | inst.instruction |= inst.operands[0].reg; | |
10006 | inst.instruction |= inst.operands[0].reg << 12; | |
10007 | inst.instruction |= inst.operands[0].reg << 16; | |
10008 | } | |
2d447fca JM |
10009 | |
10010 | static void | |
10011 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
10012 | { | |
10013 | if (inst.operands[2].isreg) | |
10014 | do_rd_rn_rm (); | |
10015 | else { | |
10016 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
10017 | _("immediate operand requires iWMMXt2")); | |
10018 | do_rd_rn (); | |
10019 | if (inst.operands[2].imm == 0) | |
10020 | { | |
10021 | switch ((inst.instruction >> 20) & 0xf) | |
10022 | { | |
10023 | case 4: | |
10024 | case 5: | |
10025 | case 6: | |
5f4273c7 | 10026 | case 7: |
2d447fca JM |
10027 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
10028 | inst.operands[2].imm = 16; | |
10029 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
10030 | break; | |
10031 | case 8: | |
10032 | case 9: | |
10033 | case 10: | |
10034 | case 11: | |
10035 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
10036 | inst.operands[2].imm = 32; | |
10037 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
10038 | break; | |
10039 | case 12: | |
10040 | case 13: | |
10041 | case 14: | |
10042 | case 15: | |
10043 | { | |
10044 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
10045 | unsigned long wrn; | |
10046 | wrn = (inst.instruction >> 16) & 0xf; | |
10047 | inst.instruction &= 0xff0fff0f; | |
10048 | inst.instruction |= wrn; | |
10049 | /* Bail out here; the instruction is now assembled. */ | |
10050 | return; | |
10051 | } | |
10052 | } | |
10053 | } | |
10054 | /* Map 32 -> 0, etc. */ | |
10055 | inst.operands[2].imm &= 0x1f; | |
10056 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
10057 | } | |
10058 | } | |
c19d1205 ZW |
10059 | \f |
10060 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
10061 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 10062 | |
c19d1205 | 10063 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 10064 | |
c19d1205 ZW |
10065 | static void |
10066 | do_mav_triple (void) | |
10067 | { | |
10068 | inst.instruction |= inst.operands[0].reg << 16; | |
10069 | inst.instruction |= inst.operands[1].reg; | |
10070 | inst.instruction |= inst.operands[2].reg << 12; | |
10071 | } | |
b99bd4ef | 10072 | |
c19d1205 ZW |
10073 | /* Insns like "foo W,X,Y,Z". |
10074 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 10075 | |
c19d1205 ZW |
10076 | static void |
10077 | do_mav_quad (void) | |
10078 | { | |
10079 | inst.instruction |= inst.operands[0].reg << 5; | |
10080 | inst.instruction |= inst.operands[1].reg << 12; | |
10081 | inst.instruction |= inst.operands[2].reg << 16; | |
10082 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
10083 | } |
10084 | ||
c19d1205 ZW |
10085 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
10086 | static void | |
10087 | do_mav_dspsc (void) | |
a737bd4d | 10088 | { |
c19d1205 ZW |
10089 | inst.instruction |= inst.operands[1].reg << 12; |
10090 | } | |
a737bd4d | 10091 | |
c19d1205 ZW |
10092 | /* Maverick shift immediate instructions. |
10093 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
10094 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 10095 | |
c19d1205 ZW |
10096 | static void |
10097 | do_mav_shift (void) | |
10098 | { | |
10099 | int imm = inst.operands[2].imm; | |
a737bd4d | 10100 | |
c19d1205 ZW |
10101 | inst.instruction |= inst.operands[0].reg << 12; |
10102 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 10103 | |
c19d1205 ZW |
10104 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
10105 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
10106 | Bit 4 should be 0. */ | |
10107 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 10108 | |
c19d1205 ZW |
10109 | inst.instruction |= imm; |
10110 | } | |
10111 | \f | |
10112 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 10113 | |
c19d1205 ZW |
10114 | /* Xscale multiply-accumulate (argument parse) |
10115 | MIAcc acc0,Rm,Rs | |
10116 | MIAPHcc acc0,Rm,Rs | |
10117 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 10118 | |
c19d1205 ZW |
10119 | static void |
10120 | do_xsc_mia (void) | |
10121 | { | |
10122 | inst.instruction |= inst.operands[1].reg; | |
10123 | inst.instruction |= inst.operands[2].reg << 12; | |
10124 | } | |
a737bd4d | 10125 | |
c19d1205 | 10126 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 10127 | |
c19d1205 | 10128 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 10129 | |
c19d1205 ZW |
10130 | static void |
10131 | do_xsc_mar (void) | |
10132 | { | |
10133 | inst.instruction |= inst.operands[1].reg << 12; | |
10134 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10135 | } |
10136 | ||
c19d1205 | 10137 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 10138 | |
c19d1205 | 10139 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
10140 | |
10141 | static void | |
c19d1205 | 10142 | do_xsc_mra (void) |
b99bd4ef | 10143 | { |
c19d1205 ZW |
10144 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
10145 | inst.instruction |= inst.operands[0].reg << 12; | |
10146 | inst.instruction |= inst.operands[1].reg << 16; | |
10147 | } | |
10148 | \f | |
10149 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 10150 | |
c19d1205 ZW |
10151 | /* inst.operands[i] is a shifted-register operand; encode |
10152 | it into inst.instruction in the format used by Thumb32. */ | |
10153 | ||
10154 | static void | |
10155 | encode_thumb32_shifted_operand (int i) | |
10156 | { | |
10157 | unsigned int value = inst.reloc.exp.X_add_number; | |
10158 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 10159 | |
9c3c69f2 PB |
10160 | constraint (inst.operands[i].immisreg, |
10161 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
10162 | inst.instruction |= inst.operands[i].reg; |
10163 | if (shift == SHIFT_RRX) | |
10164 | inst.instruction |= SHIFT_ROR << 4; | |
10165 | else | |
b99bd4ef | 10166 | { |
c19d1205 ZW |
10167 | constraint (inst.reloc.exp.X_op != O_constant, |
10168 | _("expression too complex")); | |
10169 | ||
10170 | constraint (value > 32 | |
10171 | || (value == 32 && (shift == SHIFT_LSL | |
10172 | || shift == SHIFT_ROR)), | |
10173 | _("shift expression is too large")); | |
10174 | ||
10175 | if (value == 0) | |
10176 | shift = SHIFT_LSL; | |
10177 | else if (value == 32) | |
10178 | value = 0; | |
10179 | ||
10180 | inst.instruction |= shift << 4; | |
10181 | inst.instruction |= (value & 0x1c) << 10; | |
10182 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 10183 | } |
c19d1205 | 10184 | } |
b99bd4ef | 10185 | |
b99bd4ef | 10186 | |
c19d1205 ZW |
10187 | /* inst.operands[i] was set up by parse_address. Encode it into a |
10188 | Thumb32 format load or store instruction. Reject forms that cannot | |
10189 | be used with such instructions. If is_t is true, reject forms that | |
10190 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
10191 | that cannot be used with a D instruction. If it is a store insn, |
10192 | reject PC in Rn. */ | |
b99bd4ef | 10193 | |
c19d1205 ZW |
10194 | static void |
10195 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
10196 | { | |
5be8be5d | 10197 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
10198 | |
10199 | constraint (!inst.operands[i].isreg, | |
53365c0d | 10200 | _("Instruction does not support =N addresses")); |
b99bd4ef | 10201 | |
c19d1205 ZW |
10202 | inst.instruction |= inst.operands[i].reg << 16; |
10203 | if (inst.operands[i].immisreg) | |
b99bd4ef | 10204 | { |
5be8be5d | 10205 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
10206 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
10207 | constraint (inst.operands[i].negative, | |
10208 | _("Thumb does not support negative register indexing")); | |
10209 | constraint (inst.operands[i].postind, | |
10210 | _("Thumb does not support register post-indexing")); | |
10211 | constraint (inst.operands[i].writeback, | |
10212 | _("Thumb does not support register indexing with writeback")); | |
10213 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
10214 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 10215 | |
f40d1643 | 10216 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 10217 | if (inst.operands[i].shifted) |
b99bd4ef | 10218 | { |
c19d1205 ZW |
10219 | constraint (inst.reloc.exp.X_op != O_constant, |
10220 | _("expression too complex")); | |
9c3c69f2 PB |
10221 | constraint (inst.reloc.exp.X_add_number < 0 |
10222 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 10223 | _("shift out of range")); |
9c3c69f2 | 10224 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
10225 | } |
10226 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10227 | } | |
10228 | else if (inst.operands[i].preind) | |
10229 | { | |
5be8be5d | 10230 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 10231 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 10232 | _("cannot use writeback with this instruction")); |
4755303e WN |
10233 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
10234 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
10235 | |
10236 | if (is_d) | |
10237 | { | |
10238 | inst.instruction |= 0x01000000; | |
10239 | if (inst.operands[i].writeback) | |
10240 | inst.instruction |= 0x00200000; | |
b99bd4ef | 10241 | } |
c19d1205 | 10242 | else |
b99bd4ef | 10243 | { |
c19d1205 ZW |
10244 | inst.instruction |= 0x00000c00; |
10245 | if (inst.operands[i].writeback) | |
10246 | inst.instruction |= 0x00000100; | |
b99bd4ef | 10247 | } |
c19d1205 | 10248 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 10249 | } |
c19d1205 | 10250 | else if (inst.operands[i].postind) |
b99bd4ef | 10251 | { |
9c2799c2 | 10252 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
10253 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
10254 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
10255 | ||
10256 | if (is_d) | |
10257 | inst.instruction |= 0x00200000; | |
10258 | else | |
10259 | inst.instruction |= 0x00000900; | |
10260 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10261 | } | |
10262 | else /* unindexed - only for coprocessor */ | |
10263 | inst.error = _("instruction does not accept unindexed addressing"); | |
10264 | } | |
10265 | ||
10266 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
10267 | encodings (the latter only in post-V6T2 cores). The index is the | |
10268 | value used in the insns table below. When there is more than one | |
10269 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
10270 | holds variant (1). |
10271 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 10272 | #define T16_32_TAB \ |
21d799b5 NC |
10273 | X(_adc, 4140, eb400000), \ |
10274 | X(_adcs, 4140, eb500000), \ | |
10275 | X(_add, 1c00, eb000000), \ | |
10276 | X(_adds, 1c00, eb100000), \ | |
10277 | X(_addi, 0000, f1000000), \ | |
10278 | X(_addis, 0000, f1100000), \ | |
10279 | X(_add_pc,000f, f20f0000), \ | |
10280 | X(_add_sp,000d, f10d0000), \ | |
10281 | X(_adr, 000f, f20f0000), \ | |
10282 | X(_and, 4000, ea000000), \ | |
10283 | X(_ands, 4000, ea100000), \ | |
10284 | X(_asr, 1000, fa40f000), \ | |
10285 | X(_asrs, 1000, fa50f000), \ | |
10286 | X(_b, e000, f000b000), \ | |
10287 | X(_bcond, d000, f0008000), \ | |
10288 | X(_bic, 4380, ea200000), \ | |
10289 | X(_bics, 4380, ea300000), \ | |
10290 | X(_cmn, 42c0, eb100f00), \ | |
10291 | X(_cmp, 2800, ebb00f00), \ | |
10292 | X(_cpsie, b660, f3af8400), \ | |
10293 | X(_cpsid, b670, f3af8600), \ | |
10294 | X(_cpy, 4600, ea4f0000), \ | |
10295 | X(_dec_sp,80dd, f1ad0d00), \ | |
10296 | X(_eor, 4040, ea800000), \ | |
10297 | X(_eors, 4040, ea900000), \ | |
10298 | X(_inc_sp,00dd, f10d0d00), \ | |
10299 | X(_ldmia, c800, e8900000), \ | |
10300 | X(_ldr, 6800, f8500000), \ | |
10301 | X(_ldrb, 7800, f8100000), \ | |
10302 | X(_ldrh, 8800, f8300000), \ | |
10303 | X(_ldrsb, 5600, f9100000), \ | |
10304 | X(_ldrsh, 5e00, f9300000), \ | |
10305 | X(_ldr_pc,4800, f85f0000), \ | |
10306 | X(_ldr_pc2,4800, f85f0000), \ | |
10307 | X(_ldr_sp,9800, f85d0000), \ | |
10308 | X(_lsl, 0000, fa00f000), \ | |
10309 | X(_lsls, 0000, fa10f000), \ | |
10310 | X(_lsr, 0800, fa20f000), \ | |
10311 | X(_lsrs, 0800, fa30f000), \ | |
10312 | X(_mov, 2000, ea4f0000), \ | |
10313 | X(_movs, 2000, ea5f0000), \ | |
10314 | X(_mul, 4340, fb00f000), \ | |
10315 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
10316 | X(_mvn, 43c0, ea6f0000), \ | |
10317 | X(_mvns, 43c0, ea7f0000), \ | |
10318 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
10319 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
10320 | X(_orr, 4300, ea400000), \ | |
10321 | X(_orrs, 4300, ea500000), \ | |
10322 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
10323 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
10324 | X(_rev, ba00, fa90f080), \ | |
10325 | X(_rev16, ba40, fa90f090), \ | |
10326 | X(_revsh, bac0, fa90f0b0), \ | |
10327 | X(_ror, 41c0, fa60f000), \ | |
10328 | X(_rors, 41c0, fa70f000), \ | |
10329 | X(_sbc, 4180, eb600000), \ | |
10330 | X(_sbcs, 4180, eb700000), \ | |
10331 | X(_stmia, c000, e8800000), \ | |
10332 | X(_str, 6000, f8400000), \ | |
10333 | X(_strb, 7000, f8000000), \ | |
10334 | X(_strh, 8000, f8200000), \ | |
10335 | X(_str_sp,9000, f84d0000), \ | |
10336 | X(_sub, 1e00, eba00000), \ | |
10337 | X(_subs, 1e00, ebb00000), \ | |
10338 | X(_subi, 8000, f1a00000), \ | |
10339 | X(_subis, 8000, f1b00000), \ | |
10340 | X(_sxtb, b240, fa4ff080), \ | |
10341 | X(_sxth, b200, fa0ff080), \ | |
10342 | X(_tst, 4200, ea100f00), \ | |
10343 | X(_uxtb, b2c0, fa5ff080), \ | |
10344 | X(_uxth, b280, fa1ff080), \ | |
10345 | X(_nop, bf00, f3af8000), \ | |
10346 | X(_yield, bf10, f3af8001), \ | |
10347 | X(_wfe, bf20, f3af8002), \ | |
10348 | X(_wfi, bf30, f3af8003), \ | |
53c4b28b | 10349 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
10350 | X(_sevl, bf50, f3af8005), \ |
10351 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
10352 | |
10353 | /* To catch errors in encoding functions, the codes are all offset by | |
10354 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
10355 | as 16-bit instructions. */ | |
21d799b5 | 10356 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
10357 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
10358 | #undef X | |
10359 | ||
10360 | #define X(a,b,c) 0x##b | |
10361 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
10362 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
10363 | #undef X | |
10364 | ||
10365 | #define X(a,b,c) 0x##c | |
10366 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
10367 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
10368 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
10369 | #undef X |
10370 | #undef T16_32_TAB | |
10371 | ||
10372 | /* Thumb instruction encoders, in alphabetical order. */ | |
10373 | ||
92e90b6e | 10374 | /* ADDW or SUBW. */ |
c921be7d | 10375 | |
92e90b6e PB |
10376 | static void |
10377 | do_t_add_sub_w (void) | |
10378 | { | |
10379 | int Rd, Rn; | |
10380 | ||
10381 | Rd = inst.operands[0].reg; | |
10382 | Rn = inst.operands[1].reg; | |
10383 | ||
539d4391 NC |
10384 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
10385 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
10386 | if (Rn == REG_SP) | |
10387 | constraint (Rd == REG_PC, BAD_PC); | |
10388 | else | |
10389 | reject_bad_reg (Rd); | |
fdfde340 | 10390 | |
92e90b6e PB |
10391 | inst.instruction |= (Rn << 16) | (Rd << 8); |
10392 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10393 | } | |
10394 | ||
c19d1205 ZW |
10395 | /* Parse an add or subtract instruction. We get here with inst.instruction |
10396 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
10397 | ||
10398 | static void | |
10399 | do_t_add_sub (void) | |
10400 | { | |
10401 | int Rd, Rs, Rn; | |
10402 | ||
10403 | Rd = inst.operands[0].reg; | |
10404 | Rs = (inst.operands[1].present | |
10405 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10406 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10407 | ||
e07e6e58 NC |
10408 | if (Rd == REG_PC) |
10409 | set_it_insn_type_last (); | |
10410 | ||
c19d1205 ZW |
10411 | if (unified_syntax) |
10412 | { | |
0110f2b8 PB |
10413 | bfd_boolean flags; |
10414 | bfd_boolean narrow; | |
10415 | int opcode; | |
10416 | ||
10417 | flags = (inst.instruction == T_MNEM_adds | |
10418 | || inst.instruction == T_MNEM_subs); | |
10419 | if (flags) | |
e07e6e58 | 10420 | narrow = !in_it_block (); |
0110f2b8 | 10421 | else |
e07e6e58 | 10422 | narrow = in_it_block (); |
c19d1205 | 10423 | if (!inst.operands[2].isreg) |
b99bd4ef | 10424 | { |
16805f35 PB |
10425 | int add; |
10426 | ||
fdfde340 JM |
10427 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
10428 | ||
16805f35 PB |
10429 | add = (inst.instruction == T_MNEM_add |
10430 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
10431 | opcode = 0; |
10432 | if (inst.size_req != 4) | |
10433 | { | |
0110f2b8 | 10434 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 10435 | appropriate. */ |
0110f2b8 PB |
10436 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
10437 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
10438 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
10439 | opcode = T_MNEM_add_sp; | |
10440 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
10441 | opcode = T_MNEM_add_pc; | |
10442 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
10443 | { | |
10444 | if (flags) | |
10445 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
10446 | else | |
10447 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
10448 | } | |
10449 | if (opcode) | |
10450 | { | |
10451 | inst.instruction = THUMB_OP16(opcode); | |
10452 | inst.instruction |= (Rd << 4) | Rs; | |
10453 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10454 | if (inst.size_req != 2) | |
10455 | inst.relax = opcode; | |
10456 | } | |
10457 | else | |
10458 | constraint (inst.size_req == 2, BAD_HIREG); | |
10459 | } | |
10460 | if (inst.size_req == 4 | |
10461 | || (inst.size_req != 2 && !opcode)) | |
10462 | { | |
efd81785 PB |
10463 | if (Rd == REG_PC) |
10464 | { | |
fdfde340 | 10465 | constraint (add, BAD_PC); |
efd81785 PB |
10466 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
10467 | _("only SUBS PC, LR, #const allowed")); | |
10468 | constraint (inst.reloc.exp.X_op != O_constant, | |
10469 | _("expression too complex")); | |
10470 | constraint (inst.reloc.exp.X_add_number < 0 | |
10471 | || inst.reloc.exp.X_add_number > 0xff, | |
10472 | _("immediate value out of range")); | |
10473 | inst.instruction = T2_SUBS_PC_LR | |
10474 | | inst.reloc.exp.X_add_number; | |
10475 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10476 | return; | |
10477 | } | |
10478 | else if (Rs == REG_PC) | |
16805f35 PB |
10479 | { |
10480 | /* Always use addw/subw. */ | |
10481 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
10482 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10483 | } | |
10484 | else | |
10485 | { | |
10486 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10487 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
10488 | | 0x10000000; | |
10489 | if (flags) | |
10490 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10491 | else | |
10492 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
10493 | } | |
dc4503c6 PB |
10494 | inst.instruction |= Rd << 8; |
10495 | inst.instruction |= Rs << 16; | |
0110f2b8 | 10496 | } |
b99bd4ef | 10497 | } |
c19d1205 ZW |
10498 | else |
10499 | { | |
5f4cb198 NC |
10500 | unsigned int value = inst.reloc.exp.X_add_number; |
10501 | unsigned int shift = inst.operands[2].shift_kind; | |
10502 | ||
c19d1205 ZW |
10503 | Rn = inst.operands[2].reg; |
10504 | /* See if we can do this with a 16-bit instruction. */ | |
10505 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
10506 | { | |
e27ec89e PB |
10507 | if (Rd > 7 || Rs > 7 || Rn > 7) |
10508 | narrow = FALSE; | |
10509 | ||
10510 | if (narrow) | |
c19d1205 | 10511 | { |
e27ec89e PB |
10512 | inst.instruction = ((inst.instruction == T_MNEM_adds |
10513 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
10514 | ? T_OPCODE_ADD_R3 |
10515 | : T_OPCODE_SUB_R3); | |
10516 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
10517 | return; | |
10518 | } | |
b99bd4ef | 10519 | |
7e806470 | 10520 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 10521 | { |
7e806470 PB |
10522 | /* Thumb-1 cores (except v6-M) require at least one high |
10523 | register in a narrow non flag setting add. */ | |
10524 | if (Rd > 7 || Rn > 7 | |
10525 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
10526 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 10527 | { |
7e806470 PB |
10528 | if (Rd == Rn) |
10529 | { | |
10530 | Rn = Rs; | |
10531 | Rs = Rd; | |
10532 | } | |
c19d1205 ZW |
10533 | inst.instruction = T_OPCODE_ADD_HI; |
10534 | inst.instruction |= (Rd & 8) << 4; | |
10535 | inst.instruction |= (Rd & 7); | |
10536 | inst.instruction |= Rn << 3; | |
10537 | return; | |
10538 | } | |
c19d1205 ZW |
10539 | } |
10540 | } | |
c921be7d | 10541 | |
fdfde340 JM |
10542 | constraint (Rd == REG_PC, BAD_PC); |
10543 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
10544 | constraint (Rs == REG_PC, BAD_PC); | |
10545 | reject_bad_reg (Rn); | |
10546 | ||
c19d1205 ZW |
10547 | /* If we get here, it can't be done in 16 bits. */ |
10548 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
10549 | _("shift must be constant")); | |
10550 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10551 | inst.instruction |= Rd << 8; | |
10552 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
10553 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
10554 | _("shift value over 3 not allowed in thumb mode")); | |
10555 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
10556 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
10557 | encode_thumb32_shifted_operand (2); |
10558 | } | |
10559 | } | |
10560 | else | |
10561 | { | |
10562 | constraint (inst.instruction == T_MNEM_adds | |
10563 | || inst.instruction == T_MNEM_subs, | |
10564 | BAD_THUMB32); | |
b99bd4ef | 10565 | |
c19d1205 | 10566 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 10567 | { |
c19d1205 ZW |
10568 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
10569 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
10570 | BAD_HIREG); | |
10571 | ||
10572 | inst.instruction = (inst.instruction == T_MNEM_add | |
10573 | ? 0x0000 : 0x8000); | |
10574 | inst.instruction |= (Rd << 4) | Rs; | |
10575 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
10576 | return; |
10577 | } | |
10578 | ||
c19d1205 ZW |
10579 | Rn = inst.operands[2].reg; |
10580 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 10581 | |
c19d1205 ZW |
10582 | /* We now have Rd, Rs, and Rn set to registers. */ |
10583 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 10584 | { |
c19d1205 ZW |
10585 | /* Can't do this for SUB. */ |
10586 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
10587 | inst.instruction = T_OPCODE_ADD_HI; | |
10588 | inst.instruction |= (Rd & 8) << 4; | |
10589 | inst.instruction |= (Rd & 7); | |
10590 | if (Rs == Rd) | |
10591 | inst.instruction |= Rn << 3; | |
10592 | else if (Rn == Rd) | |
10593 | inst.instruction |= Rs << 3; | |
10594 | else | |
10595 | constraint (1, _("dest must overlap one source register")); | |
10596 | } | |
10597 | else | |
10598 | { | |
10599 | inst.instruction = (inst.instruction == T_MNEM_add | |
10600 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
10601 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 10602 | } |
b99bd4ef | 10603 | } |
b99bd4ef NC |
10604 | } |
10605 | ||
c19d1205 ZW |
10606 | static void |
10607 | do_t_adr (void) | |
10608 | { | |
fdfde340 JM |
10609 | unsigned Rd; |
10610 | ||
10611 | Rd = inst.operands[0].reg; | |
10612 | reject_bad_reg (Rd); | |
10613 | ||
10614 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
10615 | { |
10616 | /* Defer to section relaxation. */ | |
10617 | inst.relax = inst.instruction; | |
10618 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 10619 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
10620 | } |
10621 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 10622 | { |
0110f2b8 | 10623 | /* Generate a 32-bit opcode. */ |
e9f89963 | 10624 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 10625 | inst.instruction |= Rd << 8; |
e9f89963 PB |
10626 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
10627 | inst.reloc.pc_rel = 1; | |
10628 | } | |
10629 | else | |
10630 | { | |
0110f2b8 | 10631 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
10632 | inst.instruction = THUMB_OP16 (inst.instruction); |
10633 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10634 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
10635 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 10636 | |
fdfde340 | 10637 | inst.instruction |= Rd << 4; |
e9f89963 | 10638 | } |
c19d1205 | 10639 | } |
b99bd4ef | 10640 | |
c19d1205 ZW |
10641 | /* Arithmetic instructions for which there is just one 16-bit |
10642 | instruction encoding, and it allows only two low registers. | |
10643 | For maximal compatibility with ARM syntax, we allow three register | |
10644 | operands even when Thumb-32 instructions are not available, as long | |
10645 | as the first two are identical. For instance, both "sbc r0,r1" and | |
10646 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 10647 | static void |
c19d1205 | 10648 | do_t_arit3 (void) |
b99bd4ef | 10649 | { |
c19d1205 | 10650 | int Rd, Rs, Rn; |
b99bd4ef | 10651 | |
c19d1205 ZW |
10652 | Rd = inst.operands[0].reg; |
10653 | Rs = (inst.operands[1].present | |
10654 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10655 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10656 | Rn = inst.operands[2].reg; | |
b99bd4ef | 10657 | |
fdfde340 JM |
10658 | reject_bad_reg (Rd); |
10659 | reject_bad_reg (Rs); | |
10660 | if (inst.operands[2].isreg) | |
10661 | reject_bad_reg (Rn); | |
10662 | ||
c19d1205 | 10663 | if (unified_syntax) |
b99bd4ef | 10664 | { |
c19d1205 ZW |
10665 | if (!inst.operands[2].isreg) |
10666 | { | |
10667 | /* For an immediate, we always generate a 32-bit opcode; | |
10668 | section relaxation will shrink it later if possible. */ | |
10669 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10670 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10671 | inst.instruction |= Rd << 8; | |
10672 | inst.instruction |= Rs << 16; | |
10673 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10674 | } | |
10675 | else | |
10676 | { | |
e27ec89e PB |
10677 | bfd_boolean narrow; |
10678 | ||
c19d1205 | 10679 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10680 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10681 | narrow = !in_it_block (); |
e27ec89e | 10682 | else |
e07e6e58 | 10683 | narrow = in_it_block (); |
e27ec89e PB |
10684 | |
10685 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10686 | narrow = FALSE; | |
10687 | if (inst.operands[2].shifted) | |
10688 | narrow = FALSE; | |
10689 | if (inst.size_req == 4) | |
10690 | narrow = FALSE; | |
10691 | ||
10692 | if (narrow | |
c19d1205 ZW |
10693 | && Rd == Rs) |
10694 | { | |
10695 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10696 | inst.instruction |= Rd; | |
10697 | inst.instruction |= Rn << 3; | |
10698 | return; | |
10699 | } | |
b99bd4ef | 10700 | |
c19d1205 ZW |
10701 | /* If we get here, it can't be done in 16 bits. */ |
10702 | constraint (inst.operands[2].shifted | |
10703 | && inst.operands[2].immisreg, | |
10704 | _("shift must be constant")); | |
10705 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10706 | inst.instruction |= Rd << 8; | |
10707 | inst.instruction |= Rs << 16; | |
10708 | encode_thumb32_shifted_operand (2); | |
10709 | } | |
a737bd4d | 10710 | } |
c19d1205 | 10711 | else |
b99bd4ef | 10712 | { |
c19d1205 ZW |
10713 | /* On its face this is a lie - the instruction does set the |
10714 | flags. However, the only supported mnemonic in this mode | |
10715 | says it doesn't. */ | |
10716 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10717 | |
c19d1205 ZW |
10718 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10719 | _("unshifted register required")); | |
10720 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10721 | constraint (Rd != Rs, | |
10722 | _("dest and source1 must be the same register")); | |
a737bd4d | 10723 | |
c19d1205 ZW |
10724 | inst.instruction = THUMB_OP16 (inst.instruction); |
10725 | inst.instruction |= Rd; | |
10726 | inst.instruction |= Rn << 3; | |
b99bd4ef | 10727 | } |
a737bd4d | 10728 | } |
b99bd4ef | 10729 | |
c19d1205 ZW |
10730 | /* Similarly, but for instructions where the arithmetic operation is |
10731 | commutative, so we can allow either of them to be different from | |
10732 | the destination operand in a 16-bit instruction. For instance, all | |
10733 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
10734 | accepted. */ | |
10735 | static void | |
10736 | do_t_arit3c (void) | |
a737bd4d | 10737 | { |
c19d1205 | 10738 | int Rd, Rs, Rn; |
b99bd4ef | 10739 | |
c19d1205 ZW |
10740 | Rd = inst.operands[0].reg; |
10741 | Rs = (inst.operands[1].present | |
10742 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10743 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10744 | Rn = inst.operands[2].reg; | |
c921be7d | 10745 | |
fdfde340 JM |
10746 | reject_bad_reg (Rd); |
10747 | reject_bad_reg (Rs); | |
10748 | if (inst.operands[2].isreg) | |
10749 | reject_bad_reg (Rn); | |
a737bd4d | 10750 | |
c19d1205 | 10751 | if (unified_syntax) |
a737bd4d | 10752 | { |
c19d1205 | 10753 | if (!inst.operands[2].isreg) |
b99bd4ef | 10754 | { |
c19d1205 ZW |
10755 | /* For an immediate, we always generate a 32-bit opcode; |
10756 | section relaxation will shrink it later if possible. */ | |
10757 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10758 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10759 | inst.instruction |= Rd << 8; | |
10760 | inst.instruction |= Rs << 16; | |
10761 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 10762 | } |
c19d1205 | 10763 | else |
a737bd4d | 10764 | { |
e27ec89e PB |
10765 | bfd_boolean narrow; |
10766 | ||
c19d1205 | 10767 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10768 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10769 | narrow = !in_it_block (); |
e27ec89e | 10770 | else |
e07e6e58 | 10771 | narrow = in_it_block (); |
e27ec89e PB |
10772 | |
10773 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10774 | narrow = FALSE; | |
10775 | if (inst.operands[2].shifted) | |
10776 | narrow = FALSE; | |
10777 | if (inst.size_req == 4) | |
10778 | narrow = FALSE; | |
10779 | ||
10780 | if (narrow) | |
a737bd4d | 10781 | { |
c19d1205 | 10782 | if (Rd == Rs) |
a737bd4d | 10783 | { |
c19d1205 ZW |
10784 | inst.instruction = THUMB_OP16 (inst.instruction); |
10785 | inst.instruction |= Rd; | |
10786 | inst.instruction |= Rn << 3; | |
10787 | return; | |
a737bd4d | 10788 | } |
c19d1205 | 10789 | if (Rd == Rn) |
a737bd4d | 10790 | { |
c19d1205 ZW |
10791 | inst.instruction = THUMB_OP16 (inst.instruction); |
10792 | inst.instruction |= Rd; | |
10793 | inst.instruction |= Rs << 3; | |
10794 | return; | |
a737bd4d NC |
10795 | } |
10796 | } | |
c19d1205 ZW |
10797 | |
10798 | /* If we get here, it can't be done in 16 bits. */ | |
10799 | constraint (inst.operands[2].shifted | |
10800 | && inst.operands[2].immisreg, | |
10801 | _("shift must be constant")); | |
10802 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10803 | inst.instruction |= Rd << 8; | |
10804 | inst.instruction |= Rs << 16; | |
10805 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 10806 | } |
b99bd4ef | 10807 | } |
c19d1205 ZW |
10808 | else |
10809 | { | |
10810 | /* On its face this is a lie - the instruction does set the | |
10811 | flags. However, the only supported mnemonic in this mode | |
10812 | says it doesn't. */ | |
10813 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10814 | |
c19d1205 ZW |
10815 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10816 | _("unshifted register required")); | |
10817 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10818 | ||
10819 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10820 | inst.instruction |= Rd; | |
10821 | ||
10822 | if (Rd == Rs) | |
10823 | inst.instruction |= Rn << 3; | |
10824 | else if (Rd == Rn) | |
10825 | inst.instruction |= Rs << 3; | |
10826 | else | |
10827 | constraint (1, _("dest must overlap one source register")); | |
10828 | } | |
a737bd4d NC |
10829 | } |
10830 | ||
c19d1205 ZW |
10831 | static void |
10832 | do_t_bfc (void) | |
a737bd4d | 10833 | { |
fdfde340 | 10834 | unsigned Rd; |
c19d1205 ZW |
10835 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
10836 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10837 | /* The instruction encoding stores the LSB and MSB, | |
10838 | not the LSB and width. */ | |
fdfde340 JM |
10839 | Rd = inst.operands[0].reg; |
10840 | reject_bad_reg (Rd); | |
10841 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
10842 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
10843 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
10844 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10845 | } |
10846 | ||
c19d1205 ZW |
10847 | static void |
10848 | do_t_bfi (void) | |
b99bd4ef | 10849 | { |
fdfde340 | 10850 | int Rd, Rn; |
c19d1205 | 10851 | unsigned int msb; |
b99bd4ef | 10852 | |
fdfde340 JM |
10853 | Rd = inst.operands[0].reg; |
10854 | reject_bad_reg (Rd); | |
10855 | ||
c19d1205 ZW |
10856 | /* #0 in second position is alternative syntax for bfc, which is |
10857 | the same instruction but with REG_PC in the Rm field. */ | |
10858 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
10859 | Rn = REG_PC; |
10860 | else | |
10861 | { | |
10862 | Rn = inst.operands[1].reg; | |
10863 | reject_bad_reg (Rn); | |
10864 | } | |
b99bd4ef | 10865 | |
c19d1205 ZW |
10866 | msb = inst.operands[2].imm + inst.operands[3].imm; |
10867 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10868 | /* The instruction encoding stores the LSB and MSB, | |
10869 | not the LSB and width. */ | |
fdfde340 JM |
10870 | inst.instruction |= Rd << 8; |
10871 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10872 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10873 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10874 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10875 | } |
10876 | ||
c19d1205 ZW |
10877 | static void |
10878 | do_t_bfx (void) | |
b99bd4ef | 10879 | { |
fdfde340 JM |
10880 | unsigned Rd, Rn; |
10881 | ||
10882 | Rd = inst.operands[0].reg; | |
10883 | Rn = inst.operands[1].reg; | |
10884 | ||
10885 | reject_bad_reg (Rd); | |
10886 | reject_bad_reg (Rn); | |
10887 | ||
c19d1205 ZW |
10888 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
10889 | _("bit-field extends past end of register")); | |
fdfde340 JM |
10890 | inst.instruction |= Rd << 8; |
10891 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10892 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10893 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10894 | inst.instruction |= inst.operands[3].imm - 1; | |
10895 | } | |
b99bd4ef | 10896 | |
c19d1205 ZW |
10897 | /* ARM V5 Thumb BLX (argument parse) |
10898 | BLX <target_addr> which is BLX(1) | |
10899 | BLX <Rm> which is BLX(2) | |
10900 | Unfortunately, there are two different opcodes for this mnemonic. | |
10901 | So, the insns[].value is not used, and the code here zaps values | |
10902 | into inst.instruction. | |
b99bd4ef | 10903 | |
c19d1205 ZW |
10904 | ??? How to take advantage of the additional two bits of displacement |
10905 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 10906 | |
c19d1205 ZW |
10907 | static void |
10908 | do_t_blx (void) | |
10909 | { | |
e07e6e58 NC |
10910 | set_it_insn_type_last (); |
10911 | ||
c19d1205 | 10912 | if (inst.operands[0].isreg) |
fdfde340 JM |
10913 | { |
10914 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
10915 | /* We have a register, so this is BLX(2). */ | |
10916 | inst.instruction |= inst.operands[0].reg << 3; | |
10917 | } | |
b99bd4ef NC |
10918 | else |
10919 | { | |
c19d1205 | 10920 | /* No register. This must be BLX(1). */ |
2fc8bdac | 10921 | inst.instruction = 0xf000e800; |
0855e32b | 10922 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
10923 | } |
10924 | } | |
10925 | ||
c19d1205 ZW |
10926 | static void |
10927 | do_t_branch (void) | |
b99bd4ef | 10928 | { |
0110f2b8 | 10929 | int opcode; |
dfa9f0d5 | 10930 | int cond; |
9ae92b05 | 10931 | int reloc; |
dfa9f0d5 | 10932 | |
e07e6e58 NC |
10933 | cond = inst.cond; |
10934 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
10935 | ||
10936 | if (in_it_block ()) | |
dfa9f0d5 PB |
10937 | { |
10938 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 10939 | branches. */ |
dfa9f0d5 | 10940 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
10941 | } |
10942 | else | |
10943 | cond = inst.cond; | |
10944 | ||
10945 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
10946 | opcode = T_MNEM_bcond; |
10947 | else | |
10948 | opcode = inst.instruction; | |
10949 | ||
12d6b0b7 RS |
10950 | if (unified_syntax |
10951 | && (inst.size_req == 4 | |
10960bfb PB |
10952 | || (inst.size_req != 2 |
10953 | && (inst.operands[0].hasreloc | |
10954 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10955 | { |
0110f2b8 | 10956 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10957 | if (cond == COND_ALWAYS) |
9ae92b05 | 10958 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10959 | else |
10960 | { | |
9c2799c2 | 10961 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10962 | inst.instruction |= cond << 22; |
9ae92b05 | 10963 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10964 | } |
10965 | } | |
b99bd4ef NC |
10966 | else |
10967 | { | |
0110f2b8 | 10968 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10969 | if (cond == COND_ALWAYS) |
9ae92b05 | 10970 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10971 | else |
b99bd4ef | 10972 | { |
dfa9f0d5 | 10973 | inst.instruction |= cond << 8; |
9ae92b05 | 10974 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10975 | } |
0110f2b8 PB |
10976 | /* Allow section relaxation. */ |
10977 | if (unified_syntax && inst.size_req != 2) | |
10978 | inst.relax = opcode; | |
b99bd4ef | 10979 | } |
9ae92b05 | 10980 | inst.reloc.type = reloc; |
c19d1205 | 10981 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10982 | } |
10983 | ||
8884b720 | 10984 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 10985 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 10986 | RANGE. */ |
b99bd4ef | 10987 | static void |
8884b720 | 10988 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 10989 | { |
dfa9f0d5 PB |
10990 | constraint (inst.cond != COND_ALWAYS, |
10991 | _("instruction is always unconditional")); | |
c19d1205 | 10992 | if (inst.operands[0].present) |
b99bd4ef | 10993 | { |
8884b720 | 10994 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
10995 | _("immediate value out of range")); |
10996 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 10997 | } |
8884b720 MGD |
10998 | |
10999 | set_it_insn_type (NEUTRAL_IT_INSN); | |
11000 | } | |
11001 | ||
11002 | static void | |
11003 | do_t_hlt (void) | |
11004 | { | |
11005 | do_t_bkpt_hlt1 (63); | |
11006 | } | |
11007 | ||
11008 | static void | |
11009 | do_t_bkpt (void) | |
11010 | { | |
11011 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
11012 | } |
11013 | ||
11014 | static void | |
c19d1205 | 11015 | do_t_branch23 (void) |
b99bd4ef | 11016 | { |
e07e6e58 | 11017 | set_it_insn_type_last (); |
0855e32b | 11018 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 11019 | |
0855e32b NS |
11020 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
11021 | this file. We used to simply ignore the PLT reloc type here -- | |
11022 | the branch encoding is now needed to deal with TLSCALL relocs. | |
11023 | So if we see a PLT reloc now, put it back to how it used to be to | |
11024 | keep the preexisting behaviour. */ | |
11025 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
11026 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 11027 | |
4343666d | 11028 | #if defined(OBJ_COFF) |
c19d1205 ZW |
11029 | /* If the destination of the branch is a defined symbol which does not have |
11030 | the THUMB_FUNC attribute, then we must be calling a function which has | |
11031 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
11032 | function and change the branch to refer to that function instead. */ | |
11033 | if ( inst.reloc.exp.X_op == O_symbol | |
11034 | && inst.reloc.exp.X_add_symbol != NULL | |
11035 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
11036 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
11037 | inst.reloc.exp.X_add_symbol = | |
11038 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 11039 | #endif |
90e4755a RE |
11040 | } |
11041 | ||
11042 | static void | |
c19d1205 | 11043 | do_t_bx (void) |
90e4755a | 11044 | { |
e07e6e58 | 11045 | set_it_insn_type_last (); |
c19d1205 ZW |
11046 | inst.instruction |= inst.operands[0].reg << 3; |
11047 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
11048 | should cause the alignment to be checked once it is known. This is | |
11049 | because BX PC only works if the instruction is word aligned. */ | |
11050 | } | |
90e4755a | 11051 | |
c19d1205 ZW |
11052 | static void |
11053 | do_t_bxj (void) | |
11054 | { | |
fdfde340 | 11055 | int Rm; |
90e4755a | 11056 | |
e07e6e58 | 11057 | set_it_insn_type_last (); |
fdfde340 JM |
11058 | Rm = inst.operands[0].reg; |
11059 | reject_bad_reg (Rm); | |
11060 | inst.instruction |= Rm << 16; | |
90e4755a RE |
11061 | } |
11062 | ||
11063 | static void | |
c19d1205 | 11064 | do_t_clz (void) |
90e4755a | 11065 | { |
fdfde340 JM |
11066 | unsigned Rd; |
11067 | unsigned Rm; | |
11068 | ||
11069 | Rd = inst.operands[0].reg; | |
11070 | Rm = inst.operands[1].reg; | |
11071 | ||
11072 | reject_bad_reg (Rd); | |
11073 | reject_bad_reg (Rm); | |
11074 | ||
11075 | inst.instruction |= Rd << 8; | |
11076 | inst.instruction |= Rm << 16; | |
11077 | inst.instruction |= Rm; | |
c19d1205 | 11078 | } |
90e4755a | 11079 | |
dfa9f0d5 PB |
11080 | static void |
11081 | do_t_cps (void) | |
11082 | { | |
e07e6e58 | 11083 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
11084 | inst.instruction |= inst.operands[0].imm; |
11085 | } | |
11086 | ||
c19d1205 ZW |
11087 | static void |
11088 | do_t_cpsi (void) | |
11089 | { | |
e07e6e58 | 11090 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 11091 | if (unified_syntax |
62b3e311 PB |
11092 | && (inst.operands[1].present || inst.size_req == 4) |
11093 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 11094 | { |
c19d1205 ZW |
11095 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
11096 | inst.instruction = 0xf3af8000; | |
11097 | inst.instruction |= imod << 9; | |
11098 | inst.instruction |= inst.operands[0].imm << 5; | |
11099 | if (inst.operands[1].present) | |
11100 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 11101 | } |
c19d1205 | 11102 | else |
90e4755a | 11103 | { |
62b3e311 PB |
11104 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
11105 | && (inst.operands[0].imm & 4), | |
11106 | _("selected processor does not support 'A' form " | |
11107 | "of this instruction")); | |
11108 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
11109 | _("Thumb does not support the 2-argument " |
11110 | "form of this instruction")); | |
11111 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 11112 | } |
90e4755a RE |
11113 | } |
11114 | ||
c19d1205 ZW |
11115 | /* THUMB CPY instruction (argument parse). */ |
11116 | ||
90e4755a | 11117 | static void |
c19d1205 | 11118 | do_t_cpy (void) |
90e4755a | 11119 | { |
c19d1205 | 11120 | if (inst.size_req == 4) |
90e4755a | 11121 | { |
c19d1205 ZW |
11122 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
11123 | inst.instruction |= inst.operands[0].reg << 8; | |
11124 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 11125 | } |
c19d1205 | 11126 | else |
90e4755a | 11127 | { |
c19d1205 ZW |
11128 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
11129 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
11130 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 11131 | } |
90e4755a RE |
11132 | } |
11133 | ||
90e4755a | 11134 | static void |
25fe350b | 11135 | do_t_cbz (void) |
90e4755a | 11136 | { |
e07e6e58 | 11137 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11138 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11139 | inst.instruction |= inst.operands[0].reg; | |
11140 | inst.reloc.pc_rel = 1; | |
11141 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
11142 | } | |
90e4755a | 11143 | |
62b3e311 PB |
11144 | static void |
11145 | do_t_dbg (void) | |
11146 | { | |
11147 | inst.instruction |= inst.operands[0].imm; | |
11148 | } | |
11149 | ||
11150 | static void | |
11151 | do_t_div (void) | |
11152 | { | |
fdfde340 JM |
11153 | unsigned Rd, Rn, Rm; |
11154 | ||
11155 | Rd = inst.operands[0].reg; | |
11156 | Rn = (inst.operands[1].present | |
11157 | ? inst.operands[1].reg : Rd); | |
11158 | Rm = inst.operands[2].reg; | |
11159 | ||
11160 | reject_bad_reg (Rd); | |
11161 | reject_bad_reg (Rn); | |
11162 | reject_bad_reg (Rm); | |
11163 | ||
11164 | inst.instruction |= Rd << 8; | |
11165 | inst.instruction |= Rn << 16; | |
11166 | inst.instruction |= Rm; | |
62b3e311 PB |
11167 | } |
11168 | ||
c19d1205 ZW |
11169 | static void |
11170 | do_t_hint (void) | |
11171 | { | |
11172 | if (unified_syntax && inst.size_req == 4) | |
11173 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11174 | else | |
11175 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11176 | } | |
90e4755a | 11177 | |
c19d1205 ZW |
11178 | static void |
11179 | do_t_it (void) | |
11180 | { | |
11181 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 11182 | |
e07e6e58 NC |
11183 | set_it_insn_type (IT_INSN); |
11184 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
11185 | now_it.cc = cond; | |
5a01bb1d | 11186 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
11187 | |
11188 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 11189 | if ((cond & 0x1) == 0x0) |
90e4755a | 11190 | { |
c19d1205 | 11191 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 11192 | |
c19d1205 | 11193 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
11194 | { |
11195 | /* No conversion needed. */ | |
11196 | now_it.block_length = 1; | |
11197 | } | |
c19d1205 | 11198 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
11199 | { |
11200 | mask ^= 0x8; | |
11201 | now_it.block_length = 2; | |
11202 | } | |
e27ec89e | 11203 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
11204 | { |
11205 | mask ^= 0xC; | |
11206 | now_it.block_length = 3; | |
11207 | } | |
c19d1205 | 11208 | else |
5a01bb1d MGD |
11209 | { |
11210 | mask ^= 0xE; | |
11211 | now_it.block_length = 4; | |
11212 | } | |
90e4755a | 11213 | |
e27ec89e PB |
11214 | inst.instruction &= 0xfff0; |
11215 | inst.instruction |= mask; | |
c19d1205 | 11216 | } |
90e4755a | 11217 | |
c19d1205 ZW |
11218 | inst.instruction |= cond << 4; |
11219 | } | |
90e4755a | 11220 | |
3c707909 PB |
11221 | /* Helper function used for both push/pop and ldm/stm. */ |
11222 | static void | |
11223 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
11224 | { | |
11225 | bfd_boolean load; | |
11226 | ||
11227 | load = (inst.instruction & (1 << 20)) != 0; | |
11228 | ||
11229 | if (mask & (1 << 13)) | |
11230 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
11231 | |
11232 | if ((mask & (1 << base)) != 0 | |
11233 | && writeback) | |
11234 | inst.error = _("having the base register in the register list when " | |
11235 | "using write back is UNPREDICTABLE"); | |
11236 | ||
3c707909 PB |
11237 | if (load) |
11238 | { | |
e07e6e58 | 11239 | if (mask & (1 << 15)) |
477330fc RM |
11240 | { |
11241 | if (mask & (1 << 14)) | |
11242 | inst.error = _("LR and PC should not both be in register list"); | |
11243 | else | |
11244 | set_it_insn_type_last (); | |
11245 | } | |
3c707909 PB |
11246 | } |
11247 | else | |
11248 | { | |
11249 | if (mask & (1 << 15)) | |
11250 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
11251 | } |
11252 | ||
11253 | if ((mask & (mask - 1)) == 0) | |
11254 | { | |
11255 | /* Single register transfers implemented as str/ldr. */ | |
11256 | if (writeback) | |
11257 | { | |
11258 | if (inst.instruction & (1 << 23)) | |
11259 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
11260 | else | |
11261 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
11262 | } | |
11263 | else | |
11264 | { | |
11265 | if (inst.instruction & (1 << 23)) | |
11266 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
11267 | else | |
11268 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
11269 | } | |
11270 | ||
11271 | inst.instruction |= 0xf8400000; | |
11272 | if (load) | |
11273 | inst.instruction |= 0x00100000; | |
11274 | ||
5f4273c7 | 11275 | mask = ffs (mask) - 1; |
3c707909 PB |
11276 | mask <<= 12; |
11277 | } | |
11278 | else if (writeback) | |
11279 | inst.instruction |= WRITE_BACK; | |
11280 | ||
11281 | inst.instruction |= mask; | |
11282 | inst.instruction |= base << 16; | |
11283 | } | |
11284 | ||
c19d1205 ZW |
11285 | static void |
11286 | do_t_ldmstm (void) | |
11287 | { | |
11288 | /* This really doesn't seem worth it. */ | |
11289 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11290 | _("expression too complex")); | |
11291 | constraint (inst.operands[1].writeback, | |
11292 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 11293 | |
c19d1205 ZW |
11294 | if (unified_syntax) |
11295 | { | |
3c707909 PB |
11296 | bfd_boolean narrow; |
11297 | unsigned mask; | |
11298 | ||
11299 | narrow = FALSE; | |
c19d1205 ZW |
11300 | /* See if we can use a 16-bit instruction. */ |
11301 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
11302 | && inst.size_req != 4 | |
3c707909 | 11303 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 11304 | { |
3c707909 | 11305 | mask = 1 << inst.operands[0].reg; |
90e4755a | 11306 | |
eab4f823 | 11307 | if (inst.operands[0].reg <= 7) |
90e4755a | 11308 | { |
3c707909 | 11309 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
11310 | ? inst.operands[0].writeback |
11311 | : (inst.operands[0].writeback | |
11312 | == !(inst.operands[1].imm & mask))) | |
477330fc | 11313 | { |
eab4f823 MGD |
11314 | if (inst.instruction == T_MNEM_stmia |
11315 | && (inst.operands[1].imm & mask) | |
11316 | && (inst.operands[1].imm & (mask - 1))) | |
11317 | as_warn (_("value stored for r%d is UNKNOWN"), | |
11318 | inst.operands[0].reg); | |
3c707909 | 11319 | |
eab4f823 MGD |
11320 | inst.instruction = THUMB_OP16 (inst.instruction); |
11321 | inst.instruction |= inst.operands[0].reg << 8; | |
11322 | inst.instruction |= inst.operands[1].imm; | |
11323 | narrow = TRUE; | |
11324 | } | |
11325 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11326 | { | |
11327 | /* This means 1 register in reg list one of 3 situations: | |
11328 | 1. Instruction is stmia, but without writeback. | |
11329 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 11330 | reglist. |
eab4f823 MGD |
11331 | 3. ldmia with writeback, but with Rn in reglist. |
11332 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
11333 | case 1 and 2 which can be converted into a 16-bit | |
11334 | str or ldr. The SP cases are handled below. */ | |
11335 | unsigned long opcode; | |
11336 | /* First, record an error for Case 3. */ | |
11337 | if (inst.operands[1].imm & mask | |
11338 | && inst.operands[0].writeback) | |
fa94de6b | 11339 | inst.error = |
eab4f823 MGD |
11340 | _("having the base register in the register list when " |
11341 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
11342 | |
11343 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
11344 | : T_MNEM_ldr); |
11345 | inst.instruction = THUMB_OP16 (opcode); | |
11346 | inst.instruction |= inst.operands[0].reg << 3; | |
11347 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
11348 | narrow = TRUE; | |
11349 | } | |
90e4755a | 11350 | } |
eab4f823 | 11351 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 11352 | { |
eab4f823 MGD |
11353 | if (inst.operands[0].writeback) |
11354 | { | |
fa94de6b | 11355 | inst.instruction = |
eab4f823 | 11356 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11357 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 11358 | inst.instruction |= inst.operands[1].imm; |
477330fc | 11359 | narrow = TRUE; |
eab4f823 MGD |
11360 | } |
11361 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11362 | { | |
fa94de6b | 11363 | inst.instruction = |
eab4f823 | 11364 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11365 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 11366 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 11367 | narrow = TRUE; |
eab4f823 | 11368 | } |
90e4755a | 11369 | } |
3c707909 PB |
11370 | } |
11371 | ||
11372 | if (!narrow) | |
11373 | { | |
c19d1205 ZW |
11374 | if (inst.instruction < 0xffff) |
11375 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 11376 | |
5f4273c7 NC |
11377 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
11378 | inst.operands[0].writeback); | |
90e4755a RE |
11379 | } |
11380 | } | |
c19d1205 | 11381 | else |
90e4755a | 11382 | { |
c19d1205 ZW |
11383 | constraint (inst.operands[0].reg > 7 |
11384 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
11385 | constraint (inst.instruction != T_MNEM_ldmia |
11386 | && inst.instruction != T_MNEM_stmia, | |
11387 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 11388 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 11389 | { |
c19d1205 ZW |
11390 | if (!inst.operands[0].writeback) |
11391 | as_warn (_("this instruction will write back the base register")); | |
11392 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
11393 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 11394 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 11395 | inst.operands[0].reg); |
f03698e6 | 11396 | } |
c19d1205 | 11397 | else |
90e4755a | 11398 | { |
c19d1205 ZW |
11399 | if (!inst.operands[0].writeback |
11400 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11401 | as_warn (_("this instruction will write back the base register")); | |
11402 | else if (inst.operands[0].writeback | |
11403 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11404 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
11405 | } |
11406 | ||
c19d1205 ZW |
11407 | inst.instruction = THUMB_OP16 (inst.instruction); |
11408 | inst.instruction |= inst.operands[0].reg << 8; | |
11409 | inst.instruction |= inst.operands[1].imm; | |
11410 | } | |
11411 | } | |
e28cd48c | 11412 | |
c19d1205 ZW |
11413 | static void |
11414 | do_t_ldrex (void) | |
11415 | { | |
11416 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
11417 | || inst.operands[1].postind || inst.operands[1].writeback | |
11418 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
11419 | || inst.operands[1].negative, | |
01cfc07f | 11420 | BAD_ADDR_MODE); |
e28cd48c | 11421 | |
5be8be5d DG |
11422 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
11423 | ||
c19d1205 ZW |
11424 | inst.instruction |= inst.operands[0].reg << 12; |
11425 | inst.instruction |= inst.operands[1].reg << 16; | |
11426 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
11427 | } | |
e28cd48c | 11428 | |
c19d1205 ZW |
11429 | static void |
11430 | do_t_ldrexd (void) | |
11431 | { | |
11432 | if (!inst.operands[1].present) | |
1cac9012 | 11433 | { |
c19d1205 ZW |
11434 | constraint (inst.operands[0].reg == REG_LR, |
11435 | _("r14 not allowed as first register " | |
11436 | "when second register is omitted")); | |
11437 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 11438 | } |
c19d1205 ZW |
11439 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
11440 | BAD_OVERLAP); | |
b99bd4ef | 11441 | |
c19d1205 ZW |
11442 | inst.instruction |= inst.operands[0].reg << 12; |
11443 | inst.instruction |= inst.operands[1].reg << 8; | |
11444 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11445 | } |
11446 | ||
11447 | static void | |
c19d1205 | 11448 | do_t_ldst (void) |
b99bd4ef | 11449 | { |
0110f2b8 PB |
11450 | unsigned long opcode; |
11451 | int Rn; | |
11452 | ||
e07e6e58 NC |
11453 | if (inst.operands[0].isreg |
11454 | && !inst.operands[0].preind | |
11455 | && inst.operands[0].reg == REG_PC) | |
11456 | set_it_insn_type_last (); | |
11457 | ||
0110f2b8 | 11458 | opcode = inst.instruction; |
c19d1205 | 11459 | if (unified_syntax) |
b99bd4ef | 11460 | { |
53365c0d PB |
11461 | if (!inst.operands[1].isreg) |
11462 | { | |
11463 | if (opcode <= 0xffff) | |
11464 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 11465 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
11466 | return; |
11467 | } | |
0110f2b8 PB |
11468 | if (inst.operands[1].isreg |
11469 | && !inst.operands[1].writeback | |
c19d1205 ZW |
11470 | && !inst.operands[1].shifted && !inst.operands[1].postind |
11471 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
11472 | && opcode <= 0xffff |
11473 | && inst.size_req != 4) | |
c19d1205 | 11474 | { |
0110f2b8 PB |
11475 | /* Insn may have a 16-bit form. */ |
11476 | Rn = inst.operands[1].reg; | |
11477 | if (inst.operands[1].immisreg) | |
11478 | { | |
11479 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 11480 | /* [Rn, Rik] */ |
0110f2b8 PB |
11481 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
11482 | goto op16; | |
5be8be5d DG |
11483 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
11484 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
11485 | } |
11486 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
11487 | && opcode != T_MNEM_ldrsb) | |
11488 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
11489 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
11490 | { | |
11491 | /* [Rn, #const] */ | |
11492 | if (Rn > 7) | |
11493 | { | |
11494 | if (Rn == REG_PC) | |
11495 | { | |
11496 | if (inst.reloc.pc_rel) | |
11497 | opcode = T_MNEM_ldr_pc2; | |
11498 | else | |
11499 | opcode = T_MNEM_ldr_pc; | |
11500 | } | |
11501 | else | |
11502 | { | |
11503 | if (opcode == T_MNEM_ldr) | |
11504 | opcode = T_MNEM_ldr_sp; | |
11505 | else | |
11506 | opcode = T_MNEM_str_sp; | |
11507 | } | |
11508 | inst.instruction = inst.operands[0].reg << 8; | |
11509 | } | |
11510 | else | |
11511 | { | |
11512 | inst.instruction = inst.operands[0].reg; | |
11513 | inst.instruction |= inst.operands[1].reg << 3; | |
11514 | } | |
11515 | inst.instruction |= THUMB_OP16 (opcode); | |
11516 | if (inst.size_req == 2) | |
11517 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11518 | else | |
11519 | inst.relax = opcode; | |
11520 | return; | |
11521 | } | |
c19d1205 | 11522 | } |
0110f2b8 | 11523 | /* Definitely a 32-bit variant. */ |
5be8be5d | 11524 | |
8d67f500 NC |
11525 | /* Warning for Erratum 752419. */ |
11526 | if (opcode == T_MNEM_ldr | |
11527 | && inst.operands[0].reg == REG_SP | |
11528 | && inst.operands[1].writeback == 1 | |
11529 | && !inst.operands[1].immisreg) | |
11530 | { | |
11531 | if (no_cpu_selected () | |
11532 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
11533 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
11534 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
11535 | as_warn (_("This instruction may be unpredictable " |
11536 | "if executed on M-profile cores " | |
11537 | "with interrupts enabled.")); | |
11538 | } | |
11539 | ||
5be8be5d | 11540 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 11541 | if (inst.operands[1].immisreg) |
5be8be5d DG |
11542 | reject_bad_reg (inst.operands[1].imm); |
11543 | ||
1be5fd2e NC |
11544 | constraint (inst.operands[1].writeback == 1 |
11545 | && inst.operands[0].reg == inst.operands[1].reg, | |
11546 | BAD_OVERLAP); | |
11547 | ||
0110f2b8 | 11548 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
11549 | inst.instruction |= inst.operands[0].reg << 12; |
11550 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 11551 | check_ldr_r15_aligned (); |
b99bd4ef NC |
11552 | return; |
11553 | } | |
11554 | ||
c19d1205 ZW |
11555 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11556 | ||
11557 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 11558 | { |
c19d1205 ZW |
11559 | /* Only [Rn,Rm] is acceptable. */ |
11560 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
11561 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
11562 | || inst.operands[1].postind || inst.operands[1].shifted | |
11563 | || inst.operands[1].negative, | |
11564 | _("Thumb does not support this addressing mode")); | |
11565 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11566 | goto op16; | |
b99bd4ef | 11567 | } |
5f4273c7 | 11568 | |
c19d1205 ZW |
11569 | inst.instruction = THUMB_OP16 (inst.instruction); |
11570 | if (!inst.operands[1].isreg) | |
8335d6aa | 11571 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 11572 | return; |
b99bd4ef | 11573 | |
c19d1205 ZW |
11574 | constraint (!inst.operands[1].preind |
11575 | || inst.operands[1].shifted | |
11576 | || inst.operands[1].writeback, | |
11577 | _("Thumb does not support this addressing mode")); | |
11578 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 11579 | { |
c19d1205 ZW |
11580 | constraint (inst.instruction & 0x0600, |
11581 | _("byte or halfword not valid for base register")); | |
11582 | constraint (inst.operands[1].reg == REG_PC | |
11583 | && !(inst.instruction & THUMB_LOAD_BIT), | |
11584 | _("r15 based store not allowed")); | |
11585 | constraint (inst.operands[1].immisreg, | |
11586 | _("invalid base register for register offset")); | |
b99bd4ef | 11587 | |
c19d1205 ZW |
11588 | if (inst.operands[1].reg == REG_PC) |
11589 | inst.instruction = T_OPCODE_LDR_PC; | |
11590 | else if (inst.instruction & THUMB_LOAD_BIT) | |
11591 | inst.instruction = T_OPCODE_LDR_SP; | |
11592 | else | |
11593 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 11594 | |
c19d1205 ZW |
11595 | inst.instruction |= inst.operands[0].reg << 8; |
11596 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11597 | return; | |
11598 | } | |
90e4755a | 11599 | |
c19d1205 ZW |
11600 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
11601 | if (!inst.operands[1].immisreg) | |
11602 | { | |
11603 | /* Immediate offset. */ | |
11604 | inst.instruction |= inst.operands[0].reg; | |
11605 | inst.instruction |= inst.operands[1].reg << 3; | |
11606 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11607 | return; | |
11608 | } | |
90e4755a | 11609 | |
c19d1205 ZW |
11610 | /* Register offset. */ |
11611 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
11612 | constraint (inst.operands[1].negative, | |
11613 | _("Thumb does not support this addressing mode")); | |
90e4755a | 11614 | |
c19d1205 ZW |
11615 | op16: |
11616 | switch (inst.instruction) | |
11617 | { | |
11618 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
11619 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
11620 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
11621 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
11622 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
11623 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
11624 | case 0x5600 /* ldrsb */: | |
11625 | case 0x5e00 /* ldrsh */: break; | |
11626 | default: abort (); | |
11627 | } | |
90e4755a | 11628 | |
c19d1205 ZW |
11629 | inst.instruction |= inst.operands[0].reg; |
11630 | inst.instruction |= inst.operands[1].reg << 3; | |
11631 | inst.instruction |= inst.operands[1].imm << 6; | |
11632 | } | |
90e4755a | 11633 | |
c19d1205 ZW |
11634 | static void |
11635 | do_t_ldstd (void) | |
11636 | { | |
11637 | if (!inst.operands[1].present) | |
b99bd4ef | 11638 | { |
c19d1205 ZW |
11639 | inst.operands[1].reg = inst.operands[0].reg + 1; |
11640 | constraint (inst.operands[0].reg == REG_LR, | |
11641 | _("r14 not allowed here")); | |
bd340a04 | 11642 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 11643 | _("r12 not allowed here")); |
b99bd4ef | 11644 | } |
bd340a04 MGD |
11645 | |
11646 | if (inst.operands[2].writeback | |
11647 | && (inst.operands[0].reg == inst.operands[2].reg | |
11648 | || inst.operands[1].reg == inst.operands[2].reg)) | |
11649 | as_warn (_("base register written back, and overlaps " | |
477330fc | 11650 | "one of transfer registers")); |
bd340a04 | 11651 | |
c19d1205 ZW |
11652 | inst.instruction |= inst.operands[0].reg << 12; |
11653 | inst.instruction |= inst.operands[1].reg << 8; | |
11654 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
11655 | } |
11656 | ||
c19d1205 ZW |
11657 | static void |
11658 | do_t_ldstt (void) | |
11659 | { | |
11660 | inst.instruction |= inst.operands[0].reg << 12; | |
11661 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
11662 | } | |
a737bd4d | 11663 | |
b99bd4ef | 11664 | static void |
c19d1205 | 11665 | do_t_mla (void) |
b99bd4ef | 11666 | { |
fdfde340 | 11667 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 11668 | |
fdfde340 JM |
11669 | Rd = inst.operands[0].reg; |
11670 | Rn = inst.operands[1].reg; | |
11671 | Rm = inst.operands[2].reg; | |
11672 | Ra = inst.operands[3].reg; | |
11673 | ||
11674 | reject_bad_reg (Rd); | |
11675 | reject_bad_reg (Rn); | |
11676 | reject_bad_reg (Rm); | |
11677 | reject_bad_reg (Ra); | |
11678 | ||
11679 | inst.instruction |= Rd << 8; | |
11680 | inst.instruction |= Rn << 16; | |
11681 | inst.instruction |= Rm; | |
11682 | inst.instruction |= Ra << 12; | |
c19d1205 | 11683 | } |
b99bd4ef | 11684 | |
c19d1205 ZW |
11685 | static void |
11686 | do_t_mlal (void) | |
11687 | { | |
fdfde340 JM |
11688 | unsigned RdLo, RdHi, Rn, Rm; |
11689 | ||
11690 | RdLo = inst.operands[0].reg; | |
11691 | RdHi = inst.operands[1].reg; | |
11692 | Rn = inst.operands[2].reg; | |
11693 | Rm = inst.operands[3].reg; | |
11694 | ||
11695 | reject_bad_reg (RdLo); | |
11696 | reject_bad_reg (RdHi); | |
11697 | reject_bad_reg (Rn); | |
11698 | reject_bad_reg (Rm); | |
11699 | ||
11700 | inst.instruction |= RdLo << 12; | |
11701 | inst.instruction |= RdHi << 8; | |
11702 | inst.instruction |= Rn << 16; | |
11703 | inst.instruction |= Rm; | |
c19d1205 | 11704 | } |
b99bd4ef | 11705 | |
c19d1205 ZW |
11706 | static void |
11707 | do_t_mov_cmp (void) | |
11708 | { | |
fdfde340 JM |
11709 | unsigned Rn, Rm; |
11710 | ||
11711 | Rn = inst.operands[0].reg; | |
11712 | Rm = inst.operands[1].reg; | |
11713 | ||
e07e6e58 NC |
11714 | if (Rn == REG_PC) |
11715 | set_it_insn_type_last (); | |
11716 | ||
c19d1205 | 11717 | if (unified_syntax) |
b99bd4ef | 11718 | { |
c19d1205 ZW |
11719 | int r0off = (inst.instruction == T_MNEM_mov |
11720 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 11721 | unsigned long opcode; |
3d388997 PB |
11722 | bfd_boolean narrow; |
11723 | bfd_boolean low_regs; | |
11724 | ||
fdfde340 | 11725 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 11726 | opcode = inst.instruction; |
e07e6e58 | 11727 | if (in_it_block ()) |
0110f2b8 | 11728 | narrow = opcode != T_MNEM_movs; |
3d388997 | 11729 | else |
0110f2b8 | 11730 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
11731 | if (inst.size_req == 4 |
11732 | || inst.operands[1].shifted) | |
11733 | narrow = FALSE; | |
11734 | ||
efd81785 PB |
11735 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
11736 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
11737 | && !inst.operands[1].shifted | |
fdfde340 JM |
11738 | && Rn == REG_PC |
11739 | && Rm == REG_LR) | |
efd81785 PB |
11740 | { |
11741 | inst.instruction = T2_SUBS_PC_LR; | |
11742 | return; | |
11743 | } | |
11744 | ||
fdfde340 JM |
11745 | if (opcode == T_MNEM_cmp) |
11746 | { | |
11747 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
11748 | if (narrow) |
11749 | { | |
11750 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
11751 | but valid. */ | |
11752 | warn_deprecated_sp (Rm); | |
11753 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
11754 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
11755 | tools reject R15, so we do too. */ | |
11756 | constraint (Rm == REG_PC, BAD_PC); | |
11757 | } | |
11758 | else | |
11759 | reject_bad_reg (Rm); | |
fdfde340 JM |
11760 | } |
11761 | else if (opcode == T_MNEM_mov | |
11762 | || opcode == T_MNEM_movs) | |
11763 | { | |
11764 | if (inst.operands[1].isreg) | |
11765 | { | |
11766 | if (opcode == T_MNEM_movs) | |
11767 | { | |
11768 | reject_bad_reg (Rn); | |
11769 | reject_bad_reg (Rm); | |
11770 | } | |
76fa04a4 MGD |
11771 | else if (narrow) |
11772 | { | |
11773 | /* This is mov.n. */ | |
11774 | if ((Rn == REG_SP || Rn == REG_PC) | |
11775 | && (Rm == REG_SP || Rm == REG_PC)) | |
11776 | { | |
5c3696f8 | 11777 | as_tsktsk (_("Use of r%u as a source register is " |
76fa04a4 MGD |
11778 | "deprecated when r%u is the destination " |
11779 | "register."), Rm, Rn); | |
11780 | } | |
11781 | } | |
11782 | else | |
11783 | { | |
11784 | /* This is mov.w. */ | |
11785 | constraint (Rn == REG_PC, BAD_PC); | |
11786 | constraint (Rm == REG_PC, BAD_PC); | |
11787 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
11788 | } | |
fdfde340 JM |
11789 | } |
11790 | else | |
11791 | reject_bad_reg (Rn); | |
11792 | } | |
11793 | ||
c19d1205 ZW |
11794 | if (!inst.operands[1].isreg) |
11795 | { | |
0110f2b8 | 11796 | /* Immediate operand. */ |
e07e6e58 | 11797 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
11798 | narrow = 0; |
11799 | if (low_regs && narrow) | |
11800 | { | |
11801 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 11802 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
11803 | if (inst.size_req == 2) |
11804 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
11805 | else | |
11806 | inst.relax = opcode; | |
11807 | } | |
11808 | else | |
11809 | { | |
11810 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11811 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11812 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
11813 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
11814 | } | |
c19d1205 | 11815 | } |
728ca7c9 PB |
11816 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
11817 | && (inst.instruction == T_MNEM_mov | |
11818 | || inst.instruction == T_MNEM_movs)) | |
11819 | { | |
11820 | /* Register shifts are encoded as separate shift instructions. */ | |
11821 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
11822 | ||
e07e6e58 | 11823 | if (in_it_block ()) |
728ca7c9 PB |
11824 | narrow = !flags; |
11825 | else | |
11826 | narrow = flags; | |
11827 | ||
11828 | if (inst.size_req == 4) | |
11829 | narrow = FALSE; | |
11830 | ||
11831 | if (!low_regs || inst.operands[1].imm > 7) | |
11832 | narrow = FALSE; | |
11833 | ||
fdfde340 | 11834 | if (Rn != Rm) |
728ca7c9 PB |
11835 | narrow = FALSE; |
11836 | ||
11837 | switch (inst.operands[1].shift_kind) | |
11838 | { | |
11839 | case SHIFT_LSL: | |
11840 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
11841 | break; | |
11842 | case SHIFT_ASR: | |
11843 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
11844 | break; | |
11845 | case SHIFT_LSR: | |
11846 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
11847 | break; | |
11848 | case SHIFT_ROR: | |
11849 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
11850 | break; | |
11851 | default: | |
5f4273c7 | 11852 | abort (); |
728ca7c9 PB |
11853 | } |
11854 | ||
11855 | inst.instruction = opcode; | |
11856 | if (narrow) | |
11857 | { | |
fdfde340 | 11858 | inst.instruction |= Rn; |
728ca7c9 PB |
11859 | inst.instruction |= inst.operands[1].imm << 3; |
11860 | } | |
11861 | else | |
11862 | { | |
11863 | if (flags) | |
11864 | inst.instruction |= CONDS_BIT; | |
11865 | ||
fdfde340 JM |
11866 | inst.instruction |= Rn << 8; |
11867 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
11868 | inst.instruction |= inst.operands[1].imm; |
11869 | } | |
11870 | } | |
3d388997 | 11871 | else if (!narrow) |
c19d1205 | 11872 | { |
728ca7c9 PB |
11873 | /* Some mov with immediate shift have narrow variants. |
11874 | Register shifts are handled above. */ | |
11875 | if (low_regs && inst.operands[1].shifted | |
11876 | && (inst.instruction == T_MNEM_mov | |
11877 | || inst.instruction == T_MNEM_movs)) | |
11878 | { | |
e07e6e58 | 11879 | if (in_it_block ()) |
728ca7c9 PB |
11880 | narrow = (inst.instruction == T_MNEM_mov); |
11881 | else | |
11882 | narrow = (inst.instruction == T_MNEM_movs); | |
11883 | } | |
11884 | ||
11885 | if (narrow) | |
11886 | { | |
11887 | switch (inst.operands[1].shift_kind) | |
11888 | { | |
11889 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11890 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
11891 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
11892 | default: narrow = FALSE; break; | |
11893 | } | |
11894 | } | |
11895 | ||
11896 | if (narrow) | |
11897 | { | |
fdfde340 JM |
11898 | inst.instruction |= Rn; |
11899 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
11900 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11901 | } | |
11902 | else | |
11903 | { | |
11904 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11905 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
11906 | encode_thumb32_shifted_operand (1); |
11907 | } | |
c19d1205 ZW |
11908 | } |
11909 | else | |
11910 | switch (inst.instruction) | |
11911 | { | |
11912 | case T_MNEM_mov: | |
837b3435 | 11913 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
11914 | results. Don't allow this. */ |
11915 | if (low_regs) | |
11916 | { | |
11917 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
11918 | "MOV Rd, Rs with two low registers is not " | |
11919 | "permitted on this architecture"); | |
fa94de6b | 11920 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
11921 | arm_ext_v6); |
11922 | } | |
11923 | ||
c19d1205 | 11924 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
11925 | inst.instruction |= (Rn & 0x8) << 4; |
11926 | inst.instruction |= (Rn & 0x7); | |
11927 | inst.instruction |= Rm << 3; | |
c19d1205 | 11928 | break; |
b99bd4ef | 11929 | |
c19d1205 ZW |
11930 | case T_MNEM_movs: |
11931 | /* We know we have low registers at this point. | |
941a8a52 MGD |
11932 | Generate LSLS Rd, Rs, #0. */ |
11933 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
11934 | inst.instruction |= Rn; |
11935 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11936 | break; |
11937 | ||
11938 | case T_MNEM_cmp: | |
3d388997 | 11939 | if (low_regs) |
c19d1205 ZW |
11940 | { |
11941 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
11942 | inst.instruction |= Rn; |
11943 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11944 | } |
11945 | else | |
11946 | { | |
11947 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
11948 | inst.instruction |= (Rn & 0x8) << 4; |
11949 | inst.instruction |= (Rn & 0x7); | |
11950 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11951 | } |
11952 | break; | |
11953 | } | |
b99bd4ef NC |
11954 | return; |
11955 | } | |
11956 | ||
c19d1205 | 11957 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
11958 | |
11959 | /* PR 10443: Do not silently ignore shifted operands. */ | |
11960 | constraint (inst.operands[1].shifted, | |
11961 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
11962 | ||
c19d1205 | 11963 | if (inst.operands[1].isreg) |
b99bd4ef | 11964 | { |
fdfde340 | 11965 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 11966 | { |
c19d1205 ZW |
11967 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
11968 | since a MOV instruction produces unpredictable results. */ | |
11969 | if (inst.instruction == T_OPCODE_MOV_I8) | |
11970 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 11971 | else |
c19d1205 | 11972 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 11973 | |
fdfde340 JM |
11974 | inst.instruction |= Rn; |
11975 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
11976 | } |
11977 | else | |
11978 | { | |
c19d1205 ZW |
11979 | if (inst.instruction == T_OPCODE_MOV_I8) |
11980 | inst.instruction = T_OPCODE_MOV_HR; | |
11981 | else | |
11982 | inst.instruction = T_OPCODE_CMP_HR; | |
11983 | do_t_cpy (); | |
b99bd4ef NC |
11984 | } |
11985 | } | |
c19d1205 | 11986 | else |
b99bd4ef | 11987 | { |
fdfde340 | 11988 | constraint (Rn > 7, |
c19d1205 | 11989 | _("only lo regs allowed with immediate")); |
fdfde340 | 11990 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11991 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11992 | } | |
11993 | } | |
b99bd4ef | 11994 | |
c19d1205 ZW |
11995 | static void |
11996 | do_t_mov16 (void) | |
11997 | { | |
fdfde340 | 11998 | unsigned Rd; |
b6895b4f PB |
11999 | bfd_vma imm; |
12000 | bfd_boolean top; | |
12001 | ||
12002 | top = (inst.instruction & 0x00800000) != 0; | |
12003 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
12004 | { | |
12005 | constraint (top, _(":lower16: not allowed this instruction")); | |
12006 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
12007 | } | |
12008 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
12009 | { | |
12010 | constraint (!top, _(":upper16: not allowed this instruction")); | |
12011 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
12012 | } | |
12013 | ||
fdfde340 JM |
12014 | Rd = inst.operands[0].reg; |
12015 | reject_bad_reg (Rd); | |
12016 | ||
12017 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
12018 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
12019 | { | |
12020 | imm = inst.reloc.exp.X_add_number; | |
12021 | inst.instruction |= (imm & 0xf000) << 4; | |
12022 | inst.instruction |= (imm & 0x0800) << 15; | |
12023 | inst.instruction |= (imm & 0x0700) << 4; | |
12024 | inst.instruction |= (imm & 0x00ff); | |
12025 | } | |
c19d1205 | 12026 | } |
b99bd4ef | 12027 | |
c19d1205 ZW |
12028 | static void |
12029 | do_t_mvn_tst (void) | |
12030 | { | |
fdfde340 | 12031 | unsigned Rn, Rm; |
c921be7d | 12032 | |
fdfde340 JM |
12033 | Rn = inst.operands[0].reg; |
12034 | Rm = inst.operands[1].reg; | |
12035 | ||
12036 | if (inst.instruction == T_MNEM_cmp | |
12037 | || inst.instruction == T_MNEM_cmn) | |
12038 | constraint (Rn == REG_PC, BAD_PC); | |
12039 | else | |
12040 | reject_bad_reg (Rn); | |
12041 | reject_bad_reg (Rm); | |
12042 | ||
c19d1205 ZW |
12043 | if (unified_syntax) |
12044 | { | |
12045 | int r0off = (inst.instruction == T_MNEM_mvn | |
12046 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
12047 | bfd_boolean narrow; |
12048 | ||
12049 | if (inst.size_req == 4 | |
12050 | || inst.instruction > 0xffff | |
12051 | || inst.operands[1].shifted | |
fdfde340 | 12052 | || Rn > 7 || Rm > 7) |
3d388997 | 12053 | narrow = FALSE; |
fe8b4cc3 KT |
12054 | else if (inst.instruction == T_MNEM_cmn |
12055 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
12056 | narrow = TRUE; |
12057 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12058 | narrow = !in_it_block (); |
3d388997 | 12059 | else |
e07e6e58 | 12060 | narrow = in_it_block (); |
3d388997 | 12061 | |
c19d1205 | 12062 | if (!inst.operands[1].isreg) |
b99bd4ef | 12063 | { |
c19d1205 ZW |
12064 | /* For an immediate, we always generate a 32-bit opcode; |
12065 | section relaxation will shrink it later if possible. */ | |
12066 | if (inst.instruction < 0xffff) | |
12067 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12068 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 12069 | inst.instruction |= Rn << r0off; |
c19d1205 | 12070 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 12071 | } |
c19d1205 | 12072 | else |
b99bd4ef | 12073 | { |
c19d1205 | 12074 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 12075 | if (narrow) |
b99bd4ef | 12076 | { |
c19d1205 | 12077 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12078 | inst.instruction |= Rn; |
12079 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12080 | } |
c19d1205 | 12081 | else |
b99bd4ef | 12082 | { |
c19d1205 ZW |
12083 | constraint (inst.operands[1].shifted |
12084 | && inst.operands[1].immisreg, | |
12085 | _("shift must be constant")); | |
12086 | if (inst.instruction < 0xffff) | |
12087 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 12088 | inst.instruction |= Rn << r0off; |
c19d1205 | 12089 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 12090 | } |
b99bd4ef NC |
12091 | } |
12092 | } | |
12093 | else | |
12094 | { | |
c19d1205 ZW |
12095 | constraint (inst.instruction > 0xffff |
12096 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
12097 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
12098 | _("unshifted register required")); | |
fdfde340 | 12099 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12100 | BAD_HIREG); |
b99bd4ef | 12101 | |
c19d1205 | 12102 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12103 | inst.instruction |= Rn; |
12104 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12105 | } |
b99bd4ef NC |
12106 | } |
12107 | ||
b05fe5cf | 12108 | static void |
c19d1205 | 12109 | do_t_mrs (void) |
b05fe5cf | 12110 | { |
fdfde340 | 12111 | unsigned Rd; |
037e8744 JB |
12112 | |
12113 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
12114 | return; | |
12115 | ||
90ec0d68 MGD |
12116 | Rd = inst.operands[0].reg; |
12117 | reject_bad_reg (Rd); | |
12118 | inst.instruction |= Rd << 8; | |
12119 | ||
12120 | if (inst.operands[1].isreg) | |
62b3e311 | 12121 | { |
90ec0d68 MGD |
12122 | unsigned br = inst.operands[1].reg; |
12123 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
12124 | as_bad (_("bad register for mrs")); | |
12125 | ||
12126 | inst.instruction |= br & (0xf << 16); | |
12127 | inst.instruction |= (br & 0x300) >> 4; | |
12128 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
12129 | } |
12130 | else | |
12131 | { | |
90ec0d68 | 12132 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 12133 | |
d2cd1205 | 12134 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
12135 | { |
12136 | /* PR gas/12698: The constraint is only applied for m_profile. | |
12137 | If the user has specified -march=all, we want to ignore it as | |
12138 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
12139 | bfd_boolean m_profile = |
12140 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf NC |
12141 | constraint ((flags != 0) && m_profile, _("selected processor does " |
12142 | "not support requested special purpose register")); | |
12143 | } | |
90ec0d68 | 12144 | else |
d2cd1205 JB |
12145 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
12146 | devices). */ | |
12147 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
12148 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 12149 | |
90ec0d68 MGD |
12150 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
12151 | inst.instruction |= inst.operands[1].imm & 0xff; | |
12152 | inst.instruction |= 0xf0000; | |
12153 | } | |
c19d1205 | 12154 | } |
b05fe5cf | 12155 | |
c19d1205 ZW |
12156 | static void |
12157 | do_t_msr (void) | |
12158 | { | |
62b3e311 | 12159 | int flags; |
fdfde340 | 12160 | unsigned Rn; |
62b3e311 | 12161 | |
037e8744 JB |
12162 | if (do_vfp_nsyn_msr () == SUCCESS) |
12163 | return; | |
12164 | ||
c19d1205 ZW |
12165 | constraint (!inst.operands[1].isreg, |
12166 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
12167 | |
12168 | if (inst.operands[0].isreg) | |
12169 | flags = (int)(inst.operands[0].reg); | |
12170 | else | |
12171 | flags = inst.operands[0].imm; | |
12172 | ||
d2cd1205 | 12173 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 12174 | { |
d2cd1205 JB |
12175 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
12176 | ||
1a43faaf | 12177 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
12178 | If the user has specified -march=all, we want to ignore it as |
12179 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
12180 | bfd_boolean m_profile = |
12181 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf | 12182 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
477330fc RM |
12183 | && (bits & ~(PSR_s | PSR_f)) != 0) |
12184 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
12185 | && bits != PSR_f)) && m_profile, | |
12186 | _("selected processor does not support requested special " | |
12187 | "purpose register")); | |
62b3e311 PB |
12188 | } |
12189 | else | |
d2cd1205 JB |
12190 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
12191 | "requested special purpose register")); | |
c921be7d | 12192 | |
fdfde340 JM |
12193 | Rn = inst.operands[1].reg; |
12194 | reject_bad_reg (Rn); | |
12195 | ||
62b3e311 | 12196 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
12197 | inst.instruction |= (flags & 0xf0000) >> 8; |
12198 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 12199 | inst.instruction |= (flags & 0xff); |
fdfde340 | 12200 | inst.instruction |= Rn << 16; |
c19d1205 | 12201 | } |
b05fe5cf | 12202 | |
c19d1205 ZW |
12203 | static void |
12204 | do_t_mul (void) | |
12205 | { | |
17828f45 | 12206 | bfd_boolean narrow; |
fdfde340 | 12207 | unsigned Rd, Rn, Rm; |
17828f45 | 12208 | |
c19d1205 ZW |
12209 | if (!inst.operands[2].present) |
12210 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 12211 | |
fdfde340 JM |
12212 | Rd = inst.operands[0].reg; |
12213 | Rn = inst.operands[1].reg; | |
12214 | Rm = inst.operands[2].reg; | |
12215 | ||
17828f45 | 12216 | if (unified_syntax) |
b05fe5cf | 12217 | { |
17828f45 | 12218 | if (inst.size_req == 4 |
fdfde340 JM |
12219 | || (Rd != Rn |
12220 | && Rd != Rm) | |
12221 | || Rn > 7 | |
12222 | || Rm > 7) | |
17828f45 JM |
12223 | narrow = FALSE; |
12224 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 12225 | narrow = !in_it_block (); |
17828f45 | 12226 | else |
e07e6e58 | 12227 | narrow = in_it_block (); |
b05fe5cf | 12228 | } |
c19d1205 | 12229 | else |
b05fe5cf | 12230 | { |
17828f45 | 12231 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 12232 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12233 | BAD_HIREG); |
17828f45 JM |
12234 | narrow = TRUE; |
12235 | } | |
b05fe5cf | 12236 | |
17828f45 JM |
12237 | if (narrow) |
12238 | { | |
12239 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 12240 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 12241 | inst.instruction |= Rd; |
b05fe5cf | 12242 | |
fdfde340 JM |
12243 | if (Rd == Rn) |
12244 | inst.instruction |= Rm << 3; | |
12245 | else if (Rd == Rm) | |
12246 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
12247 | else |
12248 | constraint (1, _("dest must overlap one source register")); | |
12249 | } | |
17828f45 JM |
12250 | else |
12251 | { | |
e07e6e58 NC |
12252 | constraint (inst.instruction != T_MNEM_mul, |
12253 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
12254 | /* 32-bit MUL. */ |
12255 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12256 | inst.instruction |= Rd << 8; |
12257 | inst.instruction |= Rn << 16; | |
12258 | inst.instruction |= Rm << 0; | |
12259 | ||
12260 | reject_bad_reg (Rd); | |
12261 | reject_bad_reg (Rn); | |
12262 | reject_bad_reg (Rm); | |
17828f45 | 12263 | } |
c19d1205 | 12264 | } |
b05fe5cf | 12265 | |
c19d1205 ZW |
12266 | static void |
12267 | do_t_mull (void) | |
12268 | { | |
fdfde340 | 12269 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 12270 | |
fdfde340 JM |
12271 | RdLo = inst.operands[0].reg; |
12272 | RdHi = inst.operands[1].reg; | |
12273 | Rn = inst.operands[2].reg; | |
12274 | Rm = inst.operands[3].reg; | |
12275 | ||
12276 | reject_bad_reg (RdLo); | |
12277 | reject_bad_reg (RdHi); | |
12278 | reject_bad_reg (Rn); | |
12279 | reject_bad_reg (Rm); | |
12280 | ||
12281 | inst.instruction |= RdLo << 12; | |
12282 | inst.instruction |= RdHi << 8; | |
12283 | inst.instruction |= Rn << 16; | |
12284 | inst.instruction |= Rm; | |
12285 | ||
12286 | if (RdLo == RdHi) | |
c19d1205 ZW |
12287 | as_tsktsk (_("rdhi and rdlo must be different")); |
12288 | } | |
b05fe5cf | 12289 | |
c19d1205 ZW |
12290 | static void |
12291 | do_t_nop (void) | |
12292 | { | |
e07e6e58 NC |
12293 | set_it_insn_type (NEUTRAL_IT_INSN); |
12294 | ||
c19d1205 ZW |
12295 | if (unified_syntax) |
12296 | { | |
12297 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 12298 | { |
c19d1205 ZW |
12299 | inst.instruction = THUMB_OP32 (inst.instruction); |
12300 | inst.instruction |= inst.operands[0].imm; | |
12301 | } | |
12302 | else | |
12303 | { | |
bc2d1808 NC |
12304 | /* PR9722: Check for Thumb2 availability before |
12305 | generating a thumb2 nop instruction. */ | |
afa62d5e | 12306 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
12307 | { |
12308 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12309 | inst.instruction |= inst.operands[0].imm << 4; | |
12310 | } | |
12311 | else | |
12312 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
12313 | } |
12314 | } | |
12315 | else | |
12316 | { | |
12317 | constraint (inst.operands[0].present, | |
12318 | _("Thumb does not support NOP with hints")); | |
12319 | inst.instruction = 0x46c0; | |
12320 | } | |
12321 | } | |
b05fe5cf | 12322 | |
c19d1205 ZW |
12323 | static void |
12324 | do_t_neg (void) | |
12325 | { | |
12326 | if (unified_syntax) | |
12327 | { | |
3d388997 PB |
12328 | bfd_boolean narrow; |
12329 | ||
12330 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12331 | narrow = !in_it_block (); |
3d388997 | 12332 | else |
e07e6e58 | 12333 | narrow = in_it_block (); |
3d388997 PB |
12334 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12335 | narrow = FALSE; | |
12336 | if (inst.size_req == 4) | |
12337 | narrow = FALSE; | |
12338 | ||
12339 | if (!narrow) | |
c19d1205 ZW |
12340 | { |
12341 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12342 | inst.instruction |= inst.operands[0].reg << 8; | |
12343 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
12344 | } |
12345 | else | |
12346 | { | |
c19d1205 ZW |
12347 | inst.instruction = THUMB_OP16 (inst.instruction); |
12348 | inst.instruction |= inst.operands[0].reg; | |
12349 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
12350 | } |
12351 | } | |
12352 | else | |
12353 | { | |
c19d1205 ZW |
12354 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
12355 | BAD_HIREG); | |
12356 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
12357 | ||
12358 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12359 | inst.instruction |= inst.operands[0].reg; | |
12360 | inst.instruction |= inst.operands[1].reg << 3; | |
12361 | } | |
12362 | } | |
12363 | ||
1c444d06 JM |
12364 | static void |
12365 | do_t_orn (void) | |
12366 | { | |
12367 | unsigned Rd, Rn; | |
12368 | ||
12369 | Rd = inst.operands[0].reg; | |
12370 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
12371 | ||
fdfde340 JM |
12372 | reject_bad_reg (Rd); |
12373 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
12374 | reject_bad_reg (Rn); | |
12375 | ||
1c444d06 JM |
12376 | inst.instruction |= Rd << 8; |
12377 | inst.instruction |= Rn << 16; | |
12378 | ||
12379 | if (!inst.operands[2].isreg) | |
12380 | { | |
12381 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12382 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12383 | } | |
12384 | else | |
12385 | { | |
12386 | unsigned Rm; | |
12387 | ||
12388 | Rm = inst.operands[2].reg; | |
fdfde340 | 12389 | reject_bad_reg (Rm); |
1c444d06 JM |
12390 | |
12391 | constraint (inst.operands[2].shifted | |
12392 | && inst.operands[2].immisreg, | |
12393 | _("shift must be constant")); | |
12394 | encode_thumb32_shifted_operand (2); | |
12395 | } | |
12396 | } | |
12397 | ||
c19d1205 ZW |
12398 | static void |
12399 | do_t_pkhbt (void) | |
12400 | { | |
fdfde340 JM |
12401 | unsigned Rd, Rn, Rm; |
12402 | ||
12403 | Rd = inst.operands[0].reg; | |
12404 | Rn = inst.operands[1].reg; | |
12405 | Rm = inst.operands[2].reg; | |
12406 | ||
12407 | reject_bad_reg (Rd); | |
12408 | reject_bad_reg (Rn); | |
12409 | reject_bad_reg (Rm); | |
12410 | ||
12411 | inst.instruction |= Rd << 8; | |
12412 | inst.instruction |= Rn << 16; | |
12413 | inst.instruction |= Rm; | |
c19d1205 ZW |
12414 | if (inst.operands[3].present) |
12415 | { | |
12416 | unsigned int val = inst.reloc.exp.X_add_number; | |
12417 | constraint (inst.reloc.exp.X_op != O_constant, | |
12418 | _("expression too complex")); | |
12419 | inst.instruction |= (val & 0x1c) << 10; | |
12420 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 12421 | } |
c19d1205 | 12422 | } |
b05fe5cf | 12423 | |
c19d1205 ZW |
12424 | static void |
12425 | do_t_pkhtb (void) | |
12426 | { | |
12427 | if (!inst.operands[3].present) | |
1ef52f49 NC |
12428 | { |
12429 | unsigned Rtmp; | |
12430 | ||
12431 | inst.instruction &= ~0x00000020; | |
12432 | ||
12433 | /* PR 10168. Swap the Rm and Rn registers. */ | |
12434 | Rtmp = inst.operands[1].reg; | |
12435 | inst.operands[1].reg = inst.operands[2].reg; | |
12436 | inst.operands[2].reg = Rtmp; | |
12437 | } | |
c19d1205 | 12438 | do_t_pkhbt (); |
b05fe5cf ZW |
12439 | } |
12440 | ||
c19d1205 ZW |
12441 | static void |
12442 | do_t_pld (void) | |
12443 | { | |
fdfde340 JM |
12444 | if (inst.operands[0].immisreg) |
12445 | reject_bad_reg (inst.operands[0].imm); | |
12446 | ||
c19d1205 ZW |
12447 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
12448 | } | |
b05fe5cf | 12449 | |
c19d1205 ZW |
12450 | static void |
12451 | do_t_push_pop (void) | |
b99bd4ef | 12452 | { |
e9f89963 | 12453 | unsigned mask; |
5f4273c7 | 12454 | |
c19d1205 ZW |
12455 | constraint (inst.operands[0].writeback, |
12456 | _("push/pop do not support {reglist}^")); | |
12457 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
12458 | _("expression too complex")); | |
b99bd4ef | 12459 | |
e9f89963 | 12460 | mask = inst.operands[0].imm; |
d3bfe16e | 12461 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 12462 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e JB |
12463 | else if (inst.size_req != 4 |
12464 | && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push | |
12465 | ? REG_LR : REG_PC))) | |
b99bd4ef | 12466 | { |
c19d1205 ZW |
12467 | inst.instruction = THUMB_OP16 (inst.instruction); |
12468 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 12469 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
12470 | } |
12471 | else if (unified_syntax) | |
12472 | { | |
3c707909 | 12473 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 12474 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
12475 | } |
12476 | else | |
12477 | { | |
12478 | inst.error = _("invalid register list to push/pop instruction"); | |
12479 | return; | |
12480 | } | |
c19d1205 | 12481 | } |
b99bd4ef | 12482 | |
c19d1205 ZW |
12483 | static void |
12484 | do_t_rbit (void) | |
12485 | { | |
fdfde340 JM |
12486 | unsigned Rd, Rm; |
12487 | ||
12488 | Rd = inst.operands[0].reg; | |
12489 | Rm = inst.operands[1].reg; | |
12490 | ||
12491 | reject_bad_reg (Rd); | |
12492 | reject_bad_reg (Rm); | |
12493 | ||
12494 | inst.instruction |= Rd << 8; | |
12495 | inst.instruction |= Rm << 16; | |
12496 | inst.instruction |= Rm; | |
c19d1205 | 12497 | } |
b99bd4ef | 12498 | |
c19d1205 ZW |
12499 | static void |
12500 | do_t_rev (void) | |
12501 | { | |
fdfde340 JM |
12502 | unsigned Rd, Rm; |
12503 | ||
12504 | Rd = inst.operands[0].reg; | |
12505 | Rm = inst.operands[1].reg; | |
12506 | ||
12507 | reject_bad_reg (Rd); | |
12508 | reject_bad_reg (Rm); | |
12509 | ||
12510 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
12511 | && inst.size_req != 4) |
12512 | { | |
12513 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
12514 | inst.instruction |= Rd; |
12515 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12516 | } |
12517 | else if (unified_syntax) | |
12518 | { | |
12519 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12520 | inst.instruction |= Rd << 8; |
12521 | inst.instruction |= Rm << 16; | |
12522 | inst.instruction |= Rm; | |
c19d1205 ZW |
12523 | } |
12524 | else | |
12525 | inst.error = BAD_HIREG; | |
12526 | } | |
b99bd4ef | 12527 | |
1c444d06 JM |
12528 | static void |
12529 | do_t_rrx (void) | |
12530 | { | |
12531 | unsigned Rd, Rm; | |
12532 | ||
12533 | Rd = inst.operands[0].reg; | |
12534 | Rm = inst.operands[1].reg; | |
12535 | ||
fdfde340 JM |
12536 | reject_bad_reg (Rd); |
12537 | reject_bad_reg (Rm); | |
c921be7d | 12538 | |
1c444d06 JM |
12539 | inst.instruction |= Rd << 8; |
12540 | inst.instruction |= Rm; | |
12541 | } | |
12542 | ||
c19d1205 ZW |
12543 | static void |
12544 | do_t_rsb (void) | |
12545 | { | |
fdfde340 | 12546 | unsigned Rd, Rs; |
b99bd4ef | 12547 | |
c19d1205 ZW |
12548 | Rd = inst.operands[0].reg; |
12549 | Rs = (inst.operands[1].present | |
12550 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
12551 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 12552 | |
fdfde340 JM |
12553 | reject_bad_reg (Rd); |
12554 | reject_bad_reg (Rs); | |
12555 | if (inst.operands[2].isreg) | |
12556 | reject_bad_reg (inst.operands[2].reg); | |
12557 | ||
c19d1205 ZW |
12558 | inst.instruction |= Rd << 8; |
12559 | inst.instruction |= Rs << 16; | |
12560 | if (!inst.operands[2].isreg) | |
12561 | { | |
026d3abb PB |
12562 | bfd_boolean narrow; |
12563 | ||
12564 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 12565 | narrow = !in_it_block (); |
026d3abb | 12566 | else |
e07e6e58 | 12567 | narrow = in_it_block (); |
026d3abb PB |
12568 | |
12569 | if (Rd > 7 || Rs > 7) | |
12570 | narrow = FALSE; | |
12571 | ||
12572 | if (inst.size_req == 4 || !unified_syntax) | |
12573 | narrow = FALSE; | |
12574 | ||
12575 | if (inst.reloc.exp.X_op != O_constant | |
12576 | || inst.reloc.exp.X_add_number != 0) | |
12577 | narrow = FALSE; | |
12578 | ||
12579 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 12580 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
12581 | if (narrow) |
12582 | { | |
12583 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12584 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
12585 | inst.instruction |= Rs << 3; | |
12586 | inst.instruction |= Rd; | |
12587 | } | |
12588 | else | |
12589 | { | |
12590 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12591 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12592 | } | |
c19d1205 ZW |
12593 | } |
12594 | else | |
12595 | encode_thumb32_shifted_operand (2); | |
12596 | } | |
b99bd4ef | 12597 | |
c19d1205 ZW |
12598 | static void |
12599 | do_t_setend (void) | |
12600 | { | |
12e37cbc MGD |
12601 | if (warn_on_deprecated |
12602 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 12603 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 12604 | |
e07e6e58 | 12605 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
12606 | if (inst.operands[0].imm) |
12607 | inst.instruction |= 0x8; | |
12608 | } | |
b99bd4ef | 12609 | |
c19d1205 ZW |
12610 | static void |
12611 | do_t_shift (void) | |
12612 | { | |
12613 | if (!inst.operands[1].present) | |
12614 | inst.operands[1].reg = inst.operands[0].reg; | |
12615 | ||
12616 | if (unified_syntax) | |
12617 | { | |
3d388997 PB |
12618 | bfd_boolean narrow; |
12619 | int shift_kind; | |
12620 | ||
12621 | switch (inst.instruction) | |
12622 | { | |
12623 | case T_MNEM_asr: | |
12624 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
12625 | case T_MNEM_lsl: | |
12626 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
12627 | case T_MNEM_lsr: | |
12628 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
12629 | case T_MNEM_ror: | |
12630 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
12631 | default: abort (); | |
12632 | } | |
12633 | ||
12634 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12635 | narrow = !in_it_block (); |
3d388997 | 12636 | else |
e07e6e58 | 12637 | narrow = in_it_block (); |
3d388997 PB |
12638 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12639 | narrow = FALSE; | |
12640 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
12641 | narrow = FALSE; | |
12642 | if (inst.operands[2].isreg | |
12643 | && (inst.operands[1].reg != inst.operands[0].reg | |
12644 | || inst.operands[2].reg > 7)) | |
12645 | narrow = FALSE; | |
12646 | if (inst.size_req == 4) | |
12647 | narrow = FALSE; | |
12648 | ||
fdfde340 JM |
12649 | reject_bad_reg (inst.operands[0].reg); |
12650 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 12651 | |
3d388997 | 12652 | if (!narrow) |
c19d1205 ZW |
12653 | { |
12654 | if (inst.operands[2].isreg) | |
b99bd4ef | 12655 | { |
fdfde340 | 12656 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
12657 | inst.instruction = THUMB_OP32 (inst.instruction); |
12658 | inst.instruction |= inst.operands[0].reg << 8; | |
12659 | inst.instruction |= inst.operands[1].reg << 16; | |
12660 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
12661 | |
12662 | /* PR 12854: Error on extraneous shifts. */ | |
12663 | constraint (inst.operands[2].shifted, | |
12664 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12665 | } |
12666 | else | |
12667 | { | |
12668 | inst.operands[1].shifted = 1; | |
3d388997 | 12669 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
12670 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
12671 | ? T_MNEM_movs : T_MNEM_mov); | |
12672 | inst.instruction |= inst.operands[0].reg << 8; | |
12673 | encode_thumb32_shifted_operand (1); | |
12674 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
12675 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
12676 | } |
12677 | } | |
12678 | else | |
12679 | { | |
c19d1205 | 12680 | if (inst.operands[2].isreg) |
b99bd4ef | 12681 | { |
3d388997 | 12682 | switch (shift_kind) |
b99bd4ef | 12683 | { |
3d388997 PB |
12684 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
12685 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
12686 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
12687 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 12688 | default: abort (); |
b99bd4ef | 12689 | } |
5f4273c7 | 12690 | |
c19d1205 ZW |
12691 | inst.instruction |= inst.operands[0].reg; |
12692 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12693 | |
12694 | /* PR 12854: Error on extraneous shifts. */ | |
12695 | constraint (inst.operands[2].shifted, | |
12696 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
12697 | } |
12698 | else | |
12699 | { | |
3d388997 | 12700 | switch (shift_kind) |
b99bd4ef | 12701 | { |
3d388997 PB |
12702 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
12703 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12704 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 12705 | default: abort (); |
b99bd4ef | 12706 | } |
c19d1205 ZW |
12707 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
12708 | inst.instruction |= inst.operands[0].reg; | |
12709 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12710 | } |
12711 | } | |
c19d1205 ZW |
12712 | } |
12713 | else | |
12714 | { | |
12715 | constraint (inst.operands[0].reg > 7 | |
12716 | || inst.operands[1].reg > 7, BAD_HIREG); | |
12717 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 12718 | |
c19d1205 ZW |
12719 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
12720 | { | |
12721 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
12722 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
12723 | _("source1 and dest must be same register")); | |
b99bd4ef | 12724 | |
c19d1205 ZW |
12725 | switch (inst.instruction) |
12726 | { | |
12727 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
12728 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
12729 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
12730 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
12731 | default: abort (); | |
12732 | } | |
5f4273c7 | 12733 | |
c19d1205 ZW |
12734 | inst.instruction |= inst.operands[0].reg; |
12735 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12736 | |
12737 | /* PR 12854: Error on extraneous shifts. */ | |
12738 | constraint (inst.operands[2].shifted, | |
12739 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12740 | } |
12741 | else | |
b99bd4ef | 12742 | { |
c19d1205 ZW |
12743 | switch (inst.instruction) |
12744 | { | |
12745 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
12746 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
12747 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
12748 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
12749 | default: abort (); | |
12750 | } | |
12751 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
12752 | inst.instruction |= inst.operands[0].reg; | |
12753 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12754 | } |
12755 | } | |
b99bd4ef NC |
12756 | } |
12757 | ||
12758 | static void | |
c19d1205 | 12759 | do_t_simd (void) |
b99bd4ef | 12760 | { |
fdfde340 JM |
12761 | unsigned Rd, Rn, Rm; |
12762 | ||
12763 | Rd = inst.operands[0].reg; | |
12764 | Rn = inst.operands[1].reg; | |
12765 | Rm = inst.operands[2].reg; | |
12766 | ||
12767 | reject_bad_reg (Rd); | |
12768 | reject_bad_reg (Rn); | |
12769 | reject_bad_reg (Rm); | |
12770 | ||
12771 | inst.instruction |= Rd << 8; | |
12772 | inst.instruction |= Rn << 16; | |
12773 | inst.instruction |= Rm; | |
c19d1205 | 12774 | } |
b99bd4ef | 12775 | |
03ee1b7f NC |
12776 | static void |
12777 | do_t_simd2 (void) | |
12778 | { | |
12779 | unsigned Rd, Rn, Rm; | |
12780 | ||
12781 | Rd = inst.operands[0].reg; | |
12782 | Rm = inst.operands[1].reg; | |
12783 | Rn = inst.operands[2].reg; | |
12784 | ||
12785 | reject_bad_reg (Rd); | |
12786 | reject_bad_reg (Rn); | |
12787 | reject_bad_reg (Rm); | |
12788 | ||
12789 | inst.instruction |= Rd << 8; | |
12790 | inst.instruction |= Rn << 16; | |
12791 | inst.instruction |= Rm; | |
12792 | } | |
12793 | ||
c19d1205 | 12794 | static void |
3eb17e6b | 12795 | do_t_smc (void) |
c19d1205 ZW |
12796 | { |
12797 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
12798 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
12799 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
12800 | constraint (inst.reloc.exp.X_op != O_constant, |
12801 | _("expression too complex")); | |
12802 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12803 | inst.instruction |= (value & 0xf000) >> 12; | |
12804 | inst.instruction |= (value & 0x0ff0); | |
12805 | inst.instruction |= (value & 0x000f) << 16; | |
24382199 NC |
12806 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
12807 | set_it_insn_type_last (); | |
c19d1205 | 12808 | } |
b99bd4ef | 12809 | |
90ec0d68 MGD |
12810 | static void |
12811 | do_t_hvc (void) | |
12812 | { | |
12813 | unsigned int value = inst.reloc.exp.X_add_number; | |
12814 | ||
12815 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12816 | inst.instruction |= (value & 0x0fff); | |
12817 | inst.instruction |= (value & 0xf000) << 4; | |
12818 | } | |
12819 | ||
c19d1205 | 12820 | static void |
3a21c15a | 12821 | do_t_ssat_usat (int bias) |
c19d1205 | 12822 | { |
fdfde340 JM |
12823 | unsigned Rd, Rn; |
12824 | ||
12825 | Rd = inst.operands[0].reg; | |
12826 | Rn = inst.operands[2].reg; | |
12827 | ||
12828 | reject_bad_reg (Rd); | |
12829 | reject_bad_reg (Rn); | |
12830 | ||
12831 | inst.instruction |= Rd << 8; | |
3a21c15a | 12832 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 12833 | inst.instruction |= Rn << 16; |
b99bd4ef | 12834 | |
c19d1205 | 12835 | if (inst.operands[3].present) |
b99bd4ef | 12836 | { |
3a21c15a NC |
12837 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
12838 | ||
12839 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12840 | ||
c19d1205 ZW |
12841 | constraint (inst.reloc.exp.X_op != O_constant, |
12842 | _("expression too complex")); | |
b99bd4ef | 12843 | |
3a21c15a | 12844 | if (shift_amount != 0) |
6189168b | 12845 | { |
3a21c15a NC |
12846 | constraint (shift_amount > 31, |
12847 | _("shift expression is too large")); | |
12848 | ||
c19d1205 | 12849 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
12850 | inst.instruction |= 0x00200000; /* sh bit. */ |
12851 | ||
12852 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
12853 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
12854 | } |
12855 | } | |
b99bd4ef | 12856 | } |
c921be7d | 12857 | |
3a21c15a NC |
12858 | static void |
12859 | do_t_ssat (void) | |
12860 | { | |
12861 | do_t_ssat_usat (1); | |
12862 | } | |
b99bd4ef | 12863 | |
0dd132b6 | 12864 | static void |
c19d1205 | 12865 | do_t_ssat16 (void) |
0dd132b6 | 12866 | { |
fdfde340 JM |
12867 | unsigned Rd, Rn; |
12868 | ||
12869 | Rd = inst.operands[0].reg; | |
12870 | Rn = inst.operands[2].reg; | |
12871 | ||
12872 | reject_bad_reg (Rd); | |
12873 | reject_bad_reg (Rn); | |
12874 | ||
12875 | inst.instruction |= Rd << 8; | |
c19d1205 | 12876 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 12877 | inst.instruction |= Rn << 16; |
c19d1205 | 12878 | } |
0dd132b6 | 12879 | |
c19d1205 ZW |
12880 | static void |
12881 | do_t_strex (void) | |
12882 | { | |
12883 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
12884 | || inst.operands[2].postind || inst.operands[2].writeback | |
12885 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
12886 | || inst.operands[2].negative, | |
01cfc07f | 12887 | BAD_ADDR_MODE); |
0dd132b6 | 12888 | |
5be8be5d DG |
12889 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
12890 | ||
c19d1205 ZW |
12891 | inst.instruction |= inst.operands[0].reg << 8; |
12892 | inst.instruction |= inst.operands[1].reg << 12; | |
12893 | inst.instruction |= inst.operands[2].reg << 16; | |
12894 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
12895 | } |
12896 | ||
b99bd4ef | 12897 | static void |
c19d1205 | 12898 | do_t_strexd (void) |
b99bd4ef | 12899 | { |
c19d1205 ZW |
12900 | if (!inst.operands[2].present) |
12901 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 12902 | |
c19d1205 ZW |
12903 | constraint (inst.operands[0].reg == inst.operands[1].reg |
12904 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 12905 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 12906 | BAD_OVERLAP); |
b99bd4ef | 12907 | |
c19d1205 ZW |
12908 | inst.instruction |= inst.operands[0].reg; |
12909 | inst.instruction |= inst.operands[1].reg << 12; | |
12910 | inst.instruction |= inst.operands[2].reg << 8; | |
12911 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
12912 | } |
12913 | ||
12914 | static void | |
c19d1205 | 12915 | do_t_sxtah (void) |
b99bd4ef | 12916 | { |
fdfde340 JM |
12917 | unsigned Rd, Rn, Rm; |
12918 | ||
12919 | Rd = inst.operands[0].reg; | |
12920 | Rn = inst.operands[1].reg; | |
12921 | Rm = inst.operands[2].reg; | |
12922 | ||
12923 | reject_bad_reg (Rd); | |
12924 | reject_bad_reg (Rn); | |
12925 | reject_bad_reg (Rm); | |
12926 | ||
12927 | inst.instruction |= Rd << 8; | |
12928 | inst.instruction |= Rn << 16; | |
12929 | inst.instruction |= Rm; | |
c19d1205 ZW |
12930 | inst.instruction |= inst.operands[3].imm << 4; |
12931 | } | |
b99bd4ef | 12932 | |
c19d1205 ZW |
12933 | static void |
12934 | do_t_sxth (void) | |
12935 | { | |
fdfde340 JM |
12936 | unsigned Rd, Rm; |
12937 | ||
12938 | Rd = inst.operands[0].reg; | |
12939 | Rm = inst.operands[1].reg; | |
12940 | ||
12941 | reject_bad_reg (Rd); | |
12942 | reject_bad_reg (Rm); | |
c921be7d NC |
12943 | |
12944 | if (inst.instruction <= 0xffff | |
12945 | && inst.size_req != 4 | |
fdfde340 | 12946 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 12947 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 12948 | { |
c19d1205 | 12949 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12950 | inst.instruction |= Rd; |
12951 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12952 | } |
c19d1205 | 12953 | else if (unified_syntax) |
b99bd4ef | 12954 | { |
c19d1205 ZW |
12955 | if (inst.instruction <= 0xffff) |
12956 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12957 | inst.instruction |= Rd << 8; |
12958 | inst.instruction |= Rm; | |
c19d1205 | 12959 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 12960 | } |
c19d1205 | 12961 | else |
b99bd4ef | 12962 | { |
c19d1205 ZW |
12963 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
12964 | _("Thumb encoding does not support rotation")); | |
12965 | constraint (1, BAD_HIREG); | |
b99bd4ef | 12966 | } |
c19d1205 | 12967 | } |
b99bd4ef | 12968 | |
c19d1205 ZW |
12969 | static void |
12970 | do_t_swi (void) | |
12971 | { | |
b2a5fbdc MGD |
12972 | /* We have to do the following check manually as ARM_EXT_OS only applies |
12973 | to ARM_EXT_V6M. */ | |
12974 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
12975 | { | |
ac7f631b NC |
12976 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
12977 | /* This only applies to the v6m howver, not later architectures. */ | |
12978 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
12979 | as_bad (_("SVC is not permitted on this architecture")); |
12980 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
12981 | } | |
12982 | ||
c19d1205 ZW |
12983 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
12984 | } | |
b99bd4ef | 12985 | |
92e90b6e PB |
12986 | static void |
12987 | do_t_tb (void) | |
12988 | { | |
fdfde340 | 12989 | unsigned Rn, Rm; |
92e90b6e PB |
12990 | int half; |
12991 | ||
12992 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 12993 | set_it_insn_type_last (); |
dfa9f0d5 PB |
12994 | constraint (inst.operands[0].immisreg, |
12995 | _("instruction requires register index")); | |
fdfde340 JM |
12996 | |
12997 | Rn = inst.operands[0].reg; | |
12998 | Rm = inst.operands[0].imm; | |
c921be7d | 12999 | |
fdfde340 JM |
13000 | constraint (Rn == REG_SP, BAD_SP); |
13001 | reject_bad_reg (Rm); | |
13002 | ||
92e90b6e PB |
13003 | constraint (!half && inst.operands[0].shifted, |
13004 | _("instruction does not allow shifted index")); | |
fdfde340 | 13005 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
13006 | } |
13007 | ||
74db7efb NC |
13008 | static void |
13009 | do_t_udf (void) | |
13010 | { | |
13011 | if (!inst.operands[0].present) | |
13012 | inst.operands[0].imm = 0; | |
13013 | ||
13014 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
13015 | { | |
13016 | constraint (inst.size_req == 2, | |
13017 | _("immediate value out of range")); | |
13018 | inst.instruction = THUMB_OP32 (inst.instruction); | |
13019 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
13020 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
13021 | } | |
13022 | else | |
13023 | { | |
13024 | inst.instruction = THUMB_OP16 (inst.instruction); | |
13025 | inst.instruction |= inst.operands[0].imm; | |
13026 | } | |
13027 | ||
13028 | set_it_insn_type (NEUTRAL_IT_INSN); | |
13029 | } | |
13030 | ||
13031 | ||
c19d1205 ZW |
13032 | static void |
13033 | do_t_usat (void) | |
13034 | { | |
3a21c15a | 13035 | do_t_ssat_usat (0); |
b99bd4ef NC |
13036 | } |
13037 | ||
13038 | static void | |
c19d1205 | 13039 | do_t_usat16 (void) |
b99bd4ef | 13040 | { |
fdfde340 JM |
13041 | unsigned Rd, Rn; |
13042 | ||
13043 | Rd = inst.operands[0].reg; | |
13044 | Rn = inst.operands[2].reg; | |
13045 | ||
13046 | reject_bad_reg (Rd); | |
13047 | reject_bad_reg (Rn); | |
13048 | ||
13049 | inst.instruction |= Rd << 8; | |
c19d1205 | 13050 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 13051 | inst.instruction |= Rn << 16; |
b99bd4ef | 13052 | } |
c19d1205 | 13053 | |
5287ad62 | 13054 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 13055 | |
5287ad62 | 13056 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 13057 | |
5287ad62 JB |
13058 | /* An "invalid" code for the following tables. */ |
13059 | #define N_INV -1u | |
13060 | ||
13061 | struct neon_tab_entry | |
b99bd4ef | 13062 | { |
5287ad62 JB |
13063 | unsigned integer; |
13064 | unsigned float_or_poly; | |
13065 | unsigned scalar_or_imm; | |
13066 | }; | |
5f4273c7 | 13067 | |
5287ad62 JB |
13068 | /* Map overloaded Neon opcodes to their respective encodings. */ |
13069 | #define NEON_ENC_TAB \ | |
13070 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
13071 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
13072 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
13073 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
13074 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
13075 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
13076 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
13077 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
13078 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
13079 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
13080 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
13081 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 13082 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
13083 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
13084 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
13085 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
13086 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
13087 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
13088 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
13089 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
13090 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
13091 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
13092 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
13093 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
13094 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
13095 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
13096 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
13097 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
d6b4b13e MW |
13098 | X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \ |
13099 | X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \ | |
5287ad62 JB |
13100 | X(vshl, 0x0000400, N_INV, 0x0800510), \ |
13101 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
13102 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
13103 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
13104 | X(veor, 0x1000110, N_INV, N_INV), \ | |
13105 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
13106 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
13107 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
13108 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
13109 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
13110 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
13111 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
13112 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
13113 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
13114 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
13115 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
13116 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
13117 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
13118 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
13119 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
13120 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
13121 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
13122 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
13123 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
13124 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
13125 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
13126 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
13127 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
13128 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
13129 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
13130 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
13131 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
13132 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
13133 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
13134 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
13135 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
13136 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 13137 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
13138 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
13139 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 13140 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 13141 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
13142 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
13143 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
13144 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
13145 | |
13146 | enum neon_opc | |
13147 | { | |
13148 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
13149 | NEON_ENC_TAB | |
13150 | #undef X | |
13151 | }; | |
b99bd4ef | 13152 | |
5287ad62 JB |
13153 | static const struct neon_tab_entry neon_enc_tab[] = |
13154 | { | |
13155 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
13156 | NEON_ENC_TAB | |
13157 | #undef X | |
13158 | }; | |
b99bd4ef | 13159 | |
88714cb8 DG |
13160 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
13161 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13162 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13163 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13164 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13165 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13166 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13167 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13168 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13169 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13170 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 13171 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 13172 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 13173 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
13174 | #define NEON_ENC_FPV8_(X) \ |
13175 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 13176 | |
88714cb8 DG |
13177 | #define NEON_ENCODE(type, inst) \ |
13178 | do \ | |
13179 | { \ | |
13180 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
13181 | inst.is_neon = 1; \ | |
13182 | } \ | |
13183 | while (0) | |
13184 | ||
13185 | #define check_neon_suffixes \ | |
13186 | do \ | |
13187 | { \ | |
13188 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
13189 | { \ | |
13190 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
13191 | return; \ | |
13192 | } \ | |
13193 | } \ | |
13194 | while (0) | |
13195 | ||
037e8744 JB |
13196 | /* Define shapes for instruction operands. The following mnemonic characters |
13197 | are used in this table: | |
5287ad62 | 13198 | |
037e8744 | 13199 | F - VFP S<n> register |
5287ad62 JB |
13200 | D - Neon D<n> register |
13201 | Q - Neon Q<n> register | |
13202 | I - Immediate | |
13203 | S - Scalar | |
13204 | R - ARM register | |
13205 | L - D<n> register list | |
5f4273c7 | 13206 | |
037e8744 JB |
13207 | This table is used to generate various data: |
13208 | - enumerations of the form NS_DDR to be used as arguments to | |
13209 | neon_select_shape. | |
13210 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 13211 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 13212 | |
037e8744 JB |
13213 | #define NEON_SHAPE_DEF \ |
13214 | X(3, (D, D, D), DOUBLE), \ | |
13215 | X(3, (Q, Q, Q), QUAD), \ | |
13216 | X(3, (D, D, I), DOUBLE), \ | |
13217 | X(3, (Q, Q, I), QUAD), \ | |
13218 | X(3, (D, D, S), DOUBLE), \ | |
13219 | X(3, (Q, Q, S), QUAD), \ | |
13220 | X(2, (D, D), DOUBLE), \ | |
13221 | X(2, (Q, Q), QUAD), \ | |
13222 | X(2, (D, S), DOUBLE), \ | |
13223 | X(2, (Q, S), QUAD), \ | |
13224 | X(2, (D, R), DOUBLE), \ | |
13225 | X(2, (Q, R), QUAD), \ | |
13226 | X(2, (D, I), DOUBLE), \ | |
13227 | X(2, (Q, I), QUAD), \ | |
13228 | X(3, (D, L, D), DOUBLE), \ | |
13229 | X(2, (D, Q), MIXED), \ | |
13230 | X(2, (Q, D), MIXED), \ | |
13231 | X(3, (D, Q, I), MIXED), \ | |
13232 | X(3, (Q, D, I), MIXED), \ | |
13233 | X(3, (Q, D, D), MIXED), \ | |
13234 | X(3, (D, Q, Q), MIXED), \ | |
13235 | X(3, (Q, Q, D), MIXED), \ | |
13236 | X(3, (Q, D, S), MIXED), \ | |
13237 | X(3, (D, Q, S), MIXED), \ | |
13238 | X(4, (D, D, D, I), DOUBLE), \ | |
13239 | X(4, (Q, Q, Q, I), QUAD), \ | |
13240 | X(2, (F, F), SINGLE), \ | |
13241 | X(3, (F, F, F), SINGLE), \ | |
13242 | X(2, (F, I), SINGLE), \ | |
13243 | X(2, (F, D), MIXED), \ | |
13244 | X(2, (D, F), MIXED), \ | |
13245 | X(3, (F, F, I), MIXED), \ | |
13246 | X(4, (R, R, F, F), SINGLE), \ | |
13247 | X(4, (F, F, R, R), SINGLE), \ | |
13248 | X(3, (D, R, R), DOUBLE), \ | |
13249 | X(3, (R, R, D), DOUBLE), \ | |
13250 | X(2, (S, R), SINGLE), \ | |
13251 | X(2, (R, S), SINGLE), \ | |
13252 | X(2, (F, R), SINGLE), \ | |
13253 | X(2, (R, F), SINGLE) | |
13254 | ||
13255 | #define S2(A,B) NS_##A##B | |
13256 | #define S3(A,B,C) NS_##A##B##C | |
13257 | #define S4(A,B,C,D) NS_##A##B##C##D | |
13258 | ||
13259 | #define X(N, L, C) S##N L | |
13260 | ||
5287ad62 JB |
13261 | enum neon_shape |
13262 | { | |
037e8744 JB |
13263 | NEON_SHAPE_DEF, |
13264 | NS_NULL | |
5287ad62 | 13265 | }; |
b99bd4ef | 13266 | |
037e8744 JB |
13267 | #undef X |
13268 | #undef S2 | |
13269 | #undef S3 | |
13270 | #undef S4 | |
13271 | ||
13272 | enum neon_shape_class | |
13273 | { | |
13274 | SC_SINGLE, | |
13275 | SC_DOUBLE, | |
13276 | SC_QUAD, | |
13277 | SC_MIXED | |
13278 | }; | |
13279 | ||
13280 | #define X(N, L, C) SC_##C | |
13281 | ||
13282 | static enum neon_shape_class neon_shape_class[] = | |
13283 | { | |
13284 | NEON_SHAPE_DEF | |
13285 | }; | |
13286 | ||
13287 | #undef X | |
13288 | ||
13289 | enum neon_shape_el | |
13290 | { | |
13291 | SE_F, | |
13292 | SE_D, | |
13293 | SE_Q, | |
13294 | SE_I, | |
13295 | SE_S, | |
13296 | SE_R, | |
13297 | SE_L | |
13298 | }; | |
13299 | ||
13300 | /* Register widths of above. */ | |
13301 | static unsigned neon_shape_el_size[] = | |
13302 | { | |
13303 | 32, | |
13304 | 64, | |
13305 | 128, | |
13306 | 0, | |
13307 | 32, | |
13308 | 32, | |
13309 | 0 | |
13310 | }; | |
13311 | ||
13312 | struct neon_shape_info | |
13313 | { | |
13314 | unsigned els; | |
13315 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
13316 | }; | |
13317 | ||
13318 | #define S2(A,B) { SE_##A, SE_##B } | |
13319 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
13320 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
13321 | ||
13322 | #define X(N, L, C) { N, S##N L } | |
13323 | ||
13324 | static struct neon_shape_info neon_shape_tab[] = | |
13325 | { | |
13326 | NEON_SHAPE_DEF | |
13327 | }; | |
13328 | ||
13329 | #undef X | |
13330 | #undef S2 | |
13331 | #undef S3 | |
13332 | #undef S4 | |
13333 | ||
5287ad62 JB |
13334 | /* Bit masks used in type checking given instructions. |
13335 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
13336 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
13337 | set, various other bits can be set as well in order to modify the meaning of | |
13338 | the type constraint. */ | |
13339 | ||
13340 | enum neon_type_mask | |
13341 | { | |
8e79c3df CM |
13342 | N_S8 = 0x0000001, |
13343 | N_S16 = 0x0000002, | |
13344 | N_S32 = 0x0000004, | |
13345 | N_S64 = 0x0000008, | |
13346 | N_U8 = 0x0000010, | |
13347 | N_U16 = 0x0000020, | |
13348 | N_U32 = 0x0000040, | |
13349 | N_U64 = 0x0000080, | |
13350 | N_I8 = 0x0000100, | |
13351 | N_I16 = 0x0000200, | |
13352 | N_I32 = 0x0000400, | |
13353 | N_I64 = 0x0000800, | |
13354 | N_8 = 0x0001000, | |
13355 | N_16 = 0x0002000, | |
13356 | N_32 = 0x0004000, | |
13357 | N_64 = 0x0008000, | |
13358 | N_P8 = 0x0010000, | |
13359 | N_P16 = 0x0020000, | |
13360 | N_F16 = 0x0040000, | |
13361 | N_F32 = 0x0080000, | |
13362 | N_F64 = 0x0100000, | |
4f51b4bd | 13363 | N_P64 = 0x0200000, |
c921be7d NC |
13364 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
13365 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 13366 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 13367 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
13368 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
13369 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
13370 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
13371 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
13372 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
13373 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
13374 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 13375 | N_UTYP = 0, |
4f51b4bd | 13376 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
13377 | }; |
13378 | ||
dcbf9037 JB |
13379 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
13380 | ||
5287ad62 JB |
13381 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
13382 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
13383 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
13384 | #define N_SUF_32 (N_SU_32 | N_F32) | |
13385 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
13386 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
13387 | ||
13388 | /* Pass this as the first type argument to neon_check_type to ignore types | |
13389 | altogether. */ | |
13390 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
13391 | ||
037e8744 JB |
13392 | /* Select a "shape" for the current instruction (describing register types or |
13393 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
13394 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
13395 | function of operand parsing, so this function doesn't need to be called. | |
13396 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
13397 | |
13398 | static enum neon_shape | |
037e8744 | 13399 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 13400 | { |
037e8744 JB |
13401 | va_list ap; |
13402 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
13403 | |
13404 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
13405 | many arguments we should have, so this makes the assumption that we have | |
13406 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
13407 | true in the future. */ | |
13408 | if (!inst.operands[1].present) | |
13409 | inst.operands[1] = inst.operands[0]; | |
13410 | ||
037e8744 | 13411 | va_start (ap, shape); |
5f4273c7 | 13412 | |
21d799b5 | 13413 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
13414 | { |
13415 | unsigned j; | |
13416 | int matches = 1; | |
13417 | ||
13418 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
13419 | { |
13420 | if (!inst.operands[j].present) | |
13421 | { | |
13422 | matches = 0; | |
13423 | break; | |
13424 | } | |
13425 | ||
13426 | switch (neon_shape_tab[shape].el[j]) | |
13427 | { | |
13428 | case SE_F: | |
13429 | if (!(inst.operands[j].isreg | |
13430 | && inst.operands[j].isvec | |
13431 | && inst.operands[j].issingle | |
13432 | && !inst.operands[j].isquad)) | |
13433 | matches = 0; | |
13434 | break; | |
13435 | ||
13436 | case SE_D: | |
13437 | if (!(inst.operands[j].isreg | |
13438 | && inst.operands[j].isvec | |
13439 | && !inst.operands[j].isquad | |
13440 | && !inst.operands[j].issingle)) | |
13441 | matches = 0; | |
13442 | break; | |
13443 | ||
13444 | case SE_R: | |
13445 | if (!(inst.operands[j].isreg | |
13446 | && !inst.operands[j].isvec)) | |
13447 | matches = 0; | |
13448 | break; | |
13449 | ||
13450 | case SE_Q: | |
13451 | if (!(inst.operands[j].isreg | |
13452 | && inst.operands[j].isvec | |
13453 | && inst.operands[j].isquad | |
13454 | && !inst.operands[j].issingle)) | |
13455 | matches = 0; | |
13456 | break; | |
13457 | ||
13458 | case SE_I: | |
13459 | if (!(!inst.operands[j].isreg | |
13460 | && !inst.operands[j].isscalar)) | |
13461 | matches = 0; | |
13462 | break; | |
13463 | ||
13464 | case SE_S: | |
13465 | if (!(!inst.operands[j].isreg | |
13466 | && inst.operands[j].isscalar)) | |
13467 | matches = 0; | |
13468 | break; | |
13469 | ||
13470 | case SE_L: | |
13471 | break; | |
13472 | } | |
3fde54a2 JZ |
13473 | if (!matches) |
13474 | break; | |
477330fc | 13475 | } |
ad6cec43 MGD |
13476 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
13477 | /* We've matched all the entries in the shape table, and we don't | |
13478 | have any left over operands which have not been matched. */ | |
477330fc | 13479 | break; |
037e8744 | 13480 | } |
5f4273c7 | 13481 | |
037e8744 | 13482 | va_end (ap); |
5287ad62 | 13483 | |
037e8744 JB |
13484 | if (shape == NS_NULL && first_shape != NS_NULL) |
13485 | first_error (_("invalid instruction shape")); | |
5287ad62 | 13486 | |
037e8744 JB |
13487 | return shape; |
13488 | } | |
5287ad62 | 13489 | |
037e8744 JB |
13490 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
13491 | means the Q bit should be set). */ | |
13492 | ||
13493 | static int | |
13494 | neon_quad (enum neon_shape shape) | |
13495 | { | |
13496 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 13497 | } |
037e8744 | 13498 | |
5287ad62 JB |
13499 | static void |
13500 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 13501 | unsigned *g_size) |
5287ad62 JB |
13502 | { |
13503 | /* Allow modification to be made to types which are constrained to be | |
13504 | based on the key element, based on bits set alongside N_EQK. */ | |
13505 | if ((typebits & N_EQK) != 0) | |
13506 | { | |
13507 | if ((typebits & N_HLF) != 0) | |
13508 | *g_size /= 2; | |
13509 | else if ((typebits & N_DBL) != 0) | |
13510 | *g_size *= 2; | |
13511 | if ((typebits & N_SGN) != 0) | |
13512 | *g_type = NT_signed; | |
13513 | else if ((typebits & N_UNS) != 0) | |
477330fc | 13514 | *g_type = NT_unsigned; |
5287ad62 | 13515 | else if ((typebits & N_INT) != 0) |
477330fc | 13516 | *g_type = NT_integer; |
5287ad62 | 13517 | else if ((typebits & N_FLT) != 0) |
477330fc | 13518 | *g_type = NT_float; |
dcbf9037 | 13519 | else if ((typebits & N_SIZ) != 0) |
477330fc | 13520 | *g_type = NT_untyped; |
5287ad62 JB |
13521 | } |
13522 | } | |
5f4273c7 | 13523 | |
5287ad62 JB |
13524 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
13525 | operand type, i.e. the single type specified in a Neon instruction when it | |
13526 | is the only one given. */ | |
13527 | ||
13528 | static struct neon_type_el | |
13529 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
13530 | { | |
13531 | struct neon_type_el dest = *key; | |
5f4273c7 | 13532 | |
9c2799c2 | 13533 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 13534 | |
5287ad62 JB |
13535 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
13536 | ||
13537 | return dest; | |
13538 | } | |
13539 | ||
13540 | /* Convert Neon type and size into compact bitmask representation. */ | |
13541 | ||
13542 | static enum neon_type_mask | |
13543 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
13544 | { | |
13545 | switch (type) | |
13546 | { | |
13547 | case NT_untyped: | |
13548 | switch (size) | |
477330fc RM |
13549 | { |
13550 | case 8: return N_8; | |
13551 | case 16: return N_16; | |
13552 | case 32: return N_32; | |
13553 | case 64: return N_64; | |
13554 | default: ; | |
13555 | } | |
5287ad62 JB |
13556 | break; |
13557 | ||
13558 | case NT_integer: | |
13559 | switch (size) | |
477330fc RM |
13560 | { |
13561 | case 8: return N_I8; | |
13562 | case 16: return N_I16; | |
13563 | case 32: return N_I32; | |
13564 | case 64: return N_I64; | |
13565 | default: ; | |
13566 | } | |
5287ad62 JB |
13567 | break; |
13568 | ||
13569 | case NT_float: | |
037e8744 | 13570 | switch (size) |
477330fc | 13571 | { |
8e79c3df | 13572 | case 16: return N_F16; |
477330fc RM |
13573 | case 32: return N_F32; |
13574 | case 64: return N_F64; | |
13575 | default: ; | |
13576 | } | |
5287ad62 JB |
13577 | break; |
13578 | ||
13579 | case NT_poly: | |
13580 | switch (size) | |
477330fc RM |
13581 | { |
13582 | case 8: return N_P8; | |
13583 | case 16: return N_P16; | |
4f51b4bd | 13584 | case 64: return N_P64; |
477330fc RM |
13585 | default: ; |
13586 | } | |
5287ad62 JB |
13587 | break; |
13588 | ||
13589 | case NT_signed: | |
13590 | switch (size) | |
477330fc RM |
13591 | { |
13592 | case 8: return N_S8; | |
13593 | case 16: return N_S16; | |
13594 | case 32: return N_S32; | |
13595 | case 64: return N_S64; | |
13596 | default: ; | |
13597 | } | |
5287ad62 JB |
13598 | break; |
13599 | ||
13600 | case NT_unsigned: | |
13601 | switch (size) | |
477330fc RM |
13602 | { |
13603 | case 8: return N_U8; | |
13604 | case 16: return N_U16; | |
13605 | case 32: return N_U32; | |
13606 | case 64: return N_U64; | |
13607 | default: ; | |
13608 | } | |
5287ad62 JB |
13609 | break; |
13610 | ||
13611 | default: ; | |
13612 | } | |
5f4273c7 | 13613 | |
5287ad62 JB |
13614 | return N_UTYP; |
13615 | } | |
13616 | ||
13617 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
13618 | handles the case where a single bit is set in the mask. */ | |
13619 | ||
dcbf9037 | 13620 | static int |
5287ad62 | 13621 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 13622 | enum neon_type_mask mask) |
5287ad62 | 13623 | { |
dcbf9037 JB |
13624 | if ((mask & N_EQK) != 0) |
13625 | return FAIL; | |
13626 | ||
5287ad62 JB |
13627 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
13628 | *size = 8; | |
c70a8987 | 13629 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 13630 | *size = 16; |
dcbf9037 | 13631 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 13632 | *size = 32; |
4f51b4bd | 13633 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 13634 | *size = 64; |
dcbf9037 JB |
13635 | else |
13636 | return FAIL; | |
13637 | ||
5287ad62 JB |
13638 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
13639 | *type = NT_signed; | |
dcbf9037 | 13640 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 13641 | *type = NT_unsigned; |
dcbf9037 | 13642 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 13643 | *type = NT_integer; |
dcbf9037 | 13644 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 13645 | *type = NT_untyped; |
4f51b4bd | 13646 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 13647 | *type = NT_poly; |
c70a8987 | 13648 | else if ((mask & (N_F16 | N_F32 | N_F64)) != 0) |
5287ad62 | 13649 | *type = NT_float; |
dcbf9037 JB |
13650 | else |
13651 | return FAIL; | |
5f4273c7 | 13652 | |
dcbf9037 | 13653 | return SUCCESS; |
5287ad62 JB |
13654 | } |
13655 | ||
13656 | /* Modify a bitmask of allowed types. This is only needed for type | |
13657 | relaxation. */ | |
13658 | ||
13659 | static unsigned | |
13660 | modify_types_allowed (unsigned allowed, unsigned mods) | |
13661 | { | |
13662 | unsigned size; | |
13663 | enum neon_el_type type; | |
13664 | unsigned destmask; | |
13665 | int i; | |
5f4273c7 | 13666 | |
5287ad62 | 13667 | destmask = 0; |
5f4273c7 | 13668 | |
5287ad62 JB |
13669 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
13670 | { | |
21d799b5 | 13671 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
13672 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
13673 | { | |
13674 | neon_modify_type_size (mods, &type, &size); | |
13675 | destmask |= type_chk_of_el_type (type, size); | |
13676 | } | |
5287ad62 | 13677 | } |
5f4273c7 | 13678 | |
5287ad62 JB |
13679 | return destmask; |
13680 | } | |
13681 | ||
13682 | /* Check type and return type classification. | |
13683 | The manual states (paraphrase): If one datatype is given, it indicates the | |
13684 | type given in: | |
13685 | - the second operand, if there is one | |
13686 | - the operand, if there is no second operand | |
13687 | - the result, if there are no operands. | |
13688 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
13689 | which is set on a per-instruction basis, which is the one which matters when | |
13690 | only one data type is written. | |
13691 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 13692 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
13693 | |
13694 | static struct neon_type_el | |
13695 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
13696 | { | |
13697 | va_list ap; | |
13698 | unsigned i, pass, key_el = 0; | |
13699 | unsigned types[NEON_MAX_TYPE_ELS]; | |
13700 | enum neon_el_type k_type = NT_invtype; | |
13701 | unsigned k_size = -1u; | |
13702 | struct neon_type_el badtype = {NT_invtype, -1}; | |
13703 | unsigned key_allowed = 0; | |
13704 | ||
13705 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
13706 | Fill in the missing operand here, if it was omitted. */ | |
13707 | if (els > 1 && !inst.operands[1].present) | |
13708 | inst.operands[1] = inst.operands[0]; | |
13709 | ||
13710 | /* Suck up all the varargs. */ | |
13711 | va_start (ap, ns); | |
13712 | for (i = 0; i < els; i++) | |
13713 | { | |
13714 | unsigned thisarg = va_arg (ap, unsigned); | |
13715 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
13716 | { |
13717 | va_end (ap); | |
13718 | return badtype; | |
13719 | } | |
5287ad62 JB |
13720 | types[i] = thisarg; |
13721 | if ((thisarg & N_KEY) != 0) | |
477330fc | 13722 | key_el = i; |
5287ad62 JB |
13723 | } |
13724 | va_end (ap); | |
13725 | ||
dcbf9037 JB |
13726 | if (inst.vectype.elems > 0) |
13727 | for (i = 0; i < els; i++) | |
13728 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
13729 | { |
13730 | first_error (_("types specified in both the mnemonic and operands")); | |
13731 | return badtype; | |
13732 | } | |
dcbf9037 | 13733 | |
5287ad62 JB |
13734 | /* Duplicate inst.vectype elements here as necessary. |
13735 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
13736 | particularly when an insn takes one register and one non-register | |
13737 | operand. */ | |
13738 | if (inst.vectype.elems == 1 && els > 1) | |
13739 | { | |
13740 | unsigned j; | |
13741 | inst.vectype.elems = els; | |
13742 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
13743 | for (j = 0; j < els; j++) | |
477330fc RM |
13744 | if (j != key_el) |
13745 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13746 | types[j]); | |
dcbf9037 JB |
13747 | } |
13748 | else if (inst.vectype.elems == 0 && els > 0) | |
13749 | { | |
13750 | unsigned j; | |
13751 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
13752 | after each operand. We allow some flexibility here; as long as the |
13753 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 13754 | for (j = 0; j < els; j++) |
477330fc RM |
13755 | if (inst.operands[j].vectype.type != NT_invtype) |
13756 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
13757 | |
13758 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
13759 | { |
13760 | for (j = 0; j < els; j++) | |
13761 | if (inst.operands[j].vectype.type == NT_invtype) | |
13762 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13763 | types[j]); | |
13764 | } | |
dcbf9037 | 13765 | else |
477330fc RM |
13766 | { |
13767 | first_error (_("operand types can't be inferred")); | |
13768 | return badtype; | |
13769 | } | |
5287ad62 JB |
13770 | } |
13771 | else if (inst.vectype.elems != els) | |
13772 | { | |
dcbf9037 | 13773 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
13774 | return badtype; |
13775 | } | |
13776 | ||
13777 | for (pass = 0; pass < 2; pass++) | |
13778 | { | |
13779 | for (i = 0; i < els; i++) | |
477330fc RM |
13780 | { |
13781 | unsigned thisarg = types[i]; | |
13782 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
13783 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
13784 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
13785 | unsigned g_size = inst.vectype.el[i].size; | |
13786 | ||
13787 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 13788 | integer types if sign-specific variants are unavailable. */ |
477330fc | 13789 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
13790 | && (types_allowed & N_SU_ALL) == 0) |
13791 | g_type = NT_integer; | |
13792 | ||
477330fc | 13793 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
13794 | them. Some instructions only care about signs for some element |
13795 | sizes, so handle that properly. */ | |
477330fc | 13796 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
13797 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
13798 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
13799 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
13800 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
13801 | g_type = NT_untyped; |
13802 | ||
477330fc RM |
13803 | if (pass == 0) |
13804 | { | |
13805 | if ((thisarg & N_KEY) != 0) | |
13806 | { | |
13807 | k_type = g_type; | |
13808 | k_size = g_size; | |
13809 | key_allowed = thisarg & ~N_KEY; | |
13810 | } | |
13811 | } | |
13812 | else | |
13813 | { | |
13814 | if ((thisarg & N_VFP) != 0) | |
13815 | { | |
13816 | enum neon_shape_el regshape; | |
13817 | unsigned regwidth, match; | |
99b253c5 NC |
13818 | |
13819 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
13820 | if (ns == NS_NULL) | |
13821 | { | |
13822 | first_error (_("invalid instruction shape")); | |
13823 | return badtype; | |
13824 | } | |
477330fc RM |
13825 | regshape = neon_shape_tab[ns].el[i]; |
13826 | regwidth = neon_shape_el_size[regshape]; | |
13827 | ||
13828 | /* In VFP mode, operands must match register widths. If we | |
13829 | have a key operand, use its width, else use the width of | |
13830 | the current operand. */ | |
13831 | if (k_size != -1u) | |
13832 | match = k_size; | |
13833 | else | |
13834 | match = g_size; | |
13835 | ||
13836 | if (regwidth != match) | |
13837 | { | |
13838 | first_error (_("operand size must match register width")); | |
13839 | return badtype; | |
13840 | } | |
13841 | } | |
13842 | ||
13843 | if ((thisarg & N_EQK) == 0) | |
13844 | { | |
13845 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
13846 | ||
13847 | if ((given_type & types_allowed) == 0) | |
13848 | { | |
13849 | first_error (_("bad type in Neon instruction")); | |
13850 | return badtype; | |
13851 | } | |
13852 | } | |
13853 | else | |
13854 | { | |
13855 | enum neon_el_type mod_k_type = k_type; | |
13856 | unsigned mod_k_size = k_size; | |
13857 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
13858 | if (g_type != mod_k_type || g_size != mod_k_size) | |
13859 | { | |
13860 | first_error (_("inconsistent types in Neon instruction")); | |
13861 | return badtype; | |
13862 | } | |
13863 | } | |
13864 | } | |
13865 | } | |
5287ad62 JB |
13866 | } |
13867 | ||
13868 | return inst.vectype.el[key_el]; | |
13869 | } | |
13870 | ||
037e8744 | 13871 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 13872 | |
037e8744 JB |
13873 | /* Thumb VFP instructions have 0xE in the condition field. */ |
13874 | ||
13875 | static void | |
13876 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 13877 | { |
88714cb8 DG |
13878 | inst.is_neon = 1; |
13879 | ||
5287ad62 | 13880 | if (thumb_mode) |
037e8744 | 13881 | inst.instruction |= 0xe0000000; |
5287ad62 | 13882 | else |
037e8744 | 13883 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
13884 | } |
13885 | ||
037e8744 JB |
13886 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
13887 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
13888 | etc. It is assumed that operand parsing has already been done, and that the | |
13889 | operands are in the form expected by the given opcode (this isn't necessarily | |
13890 | the same as the form in which they were parsed, hence some massaging must | |
13891 | take place before this function is called). | |
13892 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 13893 | |
037e8744 JB |
13894 | static void |
13895 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 13896 | { |
037e8744 | 13897 | const struct asm_opcode *opcode; |
5f4273c7 | 13898 | |
21d799b5 | 13899 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 13900 | |
037e8744 JB |
13901 | if (!opcode) |
13902 | abort (); | |
5287ad62 | 13903 | |
037e8744 | 13904 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
13905 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
13906 | _(BAD_FPU)); | |
5287ad62 | 13907 | |
88714cb8 DG |
13908 | inst.is_neon = 1; |
13909 | ||
037e8744 JB |
13910 | if (thumb_mode) |
13911 | { | |
13912 | inst.instruction = opcode->tvalue; | |
13913 | opcode->tencode (); | |
13914 | } | |
13915 | else | |
13916 | { | |
13917 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
13918 | opcode->aencode (); | |
13919 | } | |
13920 | } | |
5287ad62 JB |
13921 | |
13922 | static void | |
037e8744 | 13923 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 13924 | { |
037e8744 JB |
13925 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
13926 | ||
13927 | if (rs == NS_FFF) | |
13928 | { | |
13929 | if (is_add) | |
477330fc | 13930 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 13931 | else |
477330fc | 13932 | do_vfp_nsyn_opcode ("fsubs"); |
037e8744 JB |
13933 | } |
13934 | else | |
13935 | { | |
13936 | if (is_add) | |
477330fc | 13937 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 13938 | else |
477330fc | 13939 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
13940 | } |
13941 | } | |
13942 | ||
13943 | /* Check operand types to see if this is a VFP instruction, and if so call | |
13944 | PFN (). */ | |
13945 | ||
13946 | static int | |
13947 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
13948 | { | |
13949 | enum neon_shape rs; | |
13950 | struct neon_type_el et; | |
13951 | ||
13952 | switch (args) | |
13953 | { | |
13954 | case 2: | |
13955 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13956 | et = neon_check_type (2, rs, | |
477330fc | 13957 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 | 13958 | break; |
5f4273c7 | 13959 | |
037e8744 JB |
13960 | case 3: |
13961 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13962 | et = neon_check_type (3, rs, | |
477330fc | 13963 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 JB |
13964 | break; |
13965 | ||
13966 | default: | |
13967 | abort (); | |
13968 | } | |
13969 | ||
13970 | if (et.type != NT_invtype) | |
13971 | { | |
13972 | pfn (rs); | |
13973 | return SUCCESS; | |
13974 | } | |
037e8744 | 13975 | |
99b253c5 | 13976 | inst.error = NULL; |
037e8744 JB |
13977 | return FAIL; |
13978 | } | |
13979 | ||
13980 | static void | |
13981 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
13982 | { | |
13983 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 13984 | |
037e8744 JB |
13985 | if (rs == NS_FFF) |
13986 | { | |
13987 | if (is_mla) | |
477330fc | 13988 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 13989 | else |
477330fc | 13990 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
13991 | } |
13992 | else | |
13993 | { | |
13994 | if (is_mla) | |
477330fc | 13995 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 13996 | else |
477330fc | 13997 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
13998 | } |
13999 | } | |
14000 | ||
62f3b8c8 PB |
14001 | static void |
14002 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
14003 | { | |
14004 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
14005 | ||
14006 | if (rs == NS_FFF) | |
14007 | { | |
14008 | if (is_fma) | |
477330fc | 14009 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 14010 | else |
477330fc | 14011 | do_vfp_nsyn_opcode ("ffnmas"); |
62f3b8c8 PB |
14012 | } |
14013 | else | |
14014 | { | |
14015 | if (is_fma) | |
477330fc | 14016 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 14017 | else |
477330fc | 14018 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
14019 | } |
14020 | } | |
14021 | ||
037e8744 JB |
14022 | static void |
14023 | do_vfp_nsyn_mul (enum neon_shape rs) | |
14024 | { | |
14025 | if (rs == NS_FFF) | |
14026 | do_vfp_nsyn_opcode ("fmuls"); | |
14027 | else | |
14028 | do_vfp_nsyn_opcode ("fmuld"); | |
14029 | } | |
14030 | ||
14031 | static void | |
14032 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
14033 | { | |
14034 | int is_neg = (inst.instruction & 0x80) != 0; | |
14035 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
14036 | ||
14037 | if (rs == NS_FF) | |
14038 | { | |
14039 | if (is_neg) | |
477330fc | 14040 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 14041 | else |
477330fc | 14042 | do_vfp_nsyn_opcode ("fabss"); |
037e8744 JB |
14043 | } |
14044 | else | |
14045 | { | |
14046 | if (is_neg) | |
477330fc | 14047 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 14048 | else |
477330fc | 14049 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
14050 | } |
14051 | } | |
14052 | ||
14053 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
14054 | insns belong to Neon, and are handled elsewhere. */ | |
14055 | ||
14056 | static void | |
14057 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
14058 | { | |
14059 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
14060 | if (is_ldm) | |
14061 | { | |
14062 | if (is_dbmode) | |
477330fc | 14063 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 14064 | else |
477330fc | 14065 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
14066 | } |
14067 | else | |
14068 | { | |
14069 | if (is_dbmode) | |
477330fc | 14070 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 14071 | else |
477330fc | 14072 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
14073 | } |
14074 | } | |
14075 | ||
037e8744 JB |
14076 | static void |
14077 | do_vfp_nsyn_sqrt (void) | |
14078 | { | |
14079 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
14080 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14081 | |
037e8744 JB |
14082 | if (rs == NS_FF) |
14083 | do_vfp_nsyn_opcode ("fsqrts"); | |
14084 | else | |
14085 | do_vfp_nsyn_opcode ("fsqrtd"); | |
14086 | } | |
14087 | ||
14088 | static void | |
14089 | do_vfp_nsyn_div (void) | |
14090 | { | |
14091 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
14092 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
14093 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14094 | |
037e8744 JB |
14095 | if (rs == NS_FFF) |
14096 | do_vfp_nsyn_opcode ("fdivs"); | |
14097 | else | |
14098 | do_vfp_nsyn_opcode ("fdivd"); | |
14099 | } | |
14100 | ||
14101 | static void | |
14102 | do_vfp_nsyn_nmul (void) | |
14103 | { | |
14104 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
14105 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
14106 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14107 | |
037e8744 JB |
14108 | if (rs == NS_FFF) |
14109 | { | |
88714cb8 | 14110 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
14111 | do_vfp_sp_dyadic (); |
14112 | } | |
14113 | else | |
14114 | { | |
88714cb8 | 14115 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
14116 | do_vfp_dp_rd_rn_rm (); |
14117 | } | |
14118 | do_vfp_cond_or_thumb (); | |
14119 | } | |
14120 | ||
14121 | static void | |
14122 | do_vfp_nsyn_cmp (void) | |
14123 | { | |
14124 | if (inst.operands[1].isreg) | |
14125 | { | |
14126 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
14127 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14128 | |
037e8744 | 14129 | if (rs == NS_FF) |
477330fc RM |
14130 | { |
14131 | NEON_ENCODE (SINGLE, inst); | |
14132 | do_vfp_sp_monadic (); | |
14133 | } | |
037e8744 | 14134 | else |
477330fc RM |
14135 | { |
14136 | NEON_ENCODE (DOUBLE, inst); | |
14137 | do_vfp_dp_rd_rm (); | |
14138 | } | |
037e8744 JB |
14139 | } |
14140 | else | |
14141 | { | |
14142 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
14143 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
14144 | ||
14145 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
14146 | { |
14147 | case N_MNEM_vcmp: | |
14148 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
14149 | break; | |
14150 | case N_MNEM_vcmpe: | |
14151 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
14152 | break; | |
14153 | default: | |
14154 | abort (); | |
14155 | } | |
5f4273c7 | 14156 | |
037e8744 | 14157 | if (rs == NS_FI) |
477330fc RM |
14158 | { |
14159 | NEON_ENCODE (SINGLE, inst); | |
14160 | do_vfp_sp_compare_z (); | |
14161 | } | |
037e8744 | 14162 | else |
477330fc RM |
14163 | { |
14164 | NEON_ENCODE (DOUBLE, inst); | |
14165 | do_vfp_dp_rd (); | |
14166 | } | |
037e8744 JB |
14167 | } |
14168 | do_vfp_cond_or_thumb (); | |
14169 | } | |
14170 | ||
14171 | static void | |
14172 | nsyn_insert_sp (void) | |
14173 | { | |
14174 | inst.operands[1] = inst.operands[0]; | |
14175 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 14176 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
14177 | inst.operands[0].isreg = 1; |
14178 | inst.operands[0].writeback = 1; | |
14179 | inst.operands[0].present = 1; | |
14180 | } | |
14181 | ||
14182 | static void | |
14183 | do_vfp_nsyn_push (void) | |
14184 | { | |
14185 | nsyn_insert_sp (); | |
14186 | if (inst.operands[1].issingle) | |
14187 | do_vfp_nsyn_opcode ("fstmdbs"); | |
14188 | else | |
14189 | do_vfp_nsyn_opcode ("fstmdbd"); | |
14190 | } | |
14191 | ||
14192 | static void | |
14193 | do_vfp_nsyn_pop (void) | |
14194 | { | |
14195 | nsyn_insert_sp (); | |
14196 | if (inst.operands[1].issingle) | |
22b5b651 | 14197 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 14198 | else |
22b5b651 | 14199 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
14200 | } |
14201 | ||
14202 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
14203 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
14204 | ||
88714cb8 DG |
14205 | static void |
14206 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 14207 | { |
88714cb8 DG |
14208 | unsigned int i = insn->instruction; |
14209 | insn->is_neon = 1; | |
14210 | ||
037e8744 JB |
14211 | if (thumb_mode) |
14212 | { | |
14213 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
14214 | if (i & (1 << 24)) | |
477330fc | 14215 | i |= 1 << 28; |
5f4273c7 | 14216 | |
037e8744 | 14217 | i &= ~(1 << 24); |
5f4273c7 | 14218 | |
037e8744 JB |
14219 | i |= 0xef000000; |
14220 | } | |
14221 | else | |
14222 | i |= 0xf2000000; | |
5f4273c7 | 14223 | |
88714cb8 | 14224 | insn->instruction = i; |
037e8744 JB |
14225 | } |
14226 | ||
14227 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
14228 | (0, 1, 2, 3). */ | |
14229 | ||
14230 | static unsigned | |
14231 | neon_logbits (unsigned x) | |
14232 | { | |
14233 | return ffs (x) - 4; | |
14234 | } | |
14235 | ||
14236 | #define LOW4(R) ((R) & 0xf) | |
14237 | #define HI1(R) (((R) >> 4) & 1) | |
14238 | ||
14239 | /* Encode insns with bit pattern: | |
14240 | ||
14241 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
14242 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 14243 | |
037e8744 JB |
14244 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
14245 | different meaning for some instruction. */ | |
14246 | ||
14247 | static void | |
14248 | neon_three_same (int isquad, int ubit, int size) | |
14249 | { | |
14250 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14251 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14252 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14253 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14254 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14255 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14256 | inst.instruction |= (isquad != 0) << 6; | |
14257 | inst.instruction |= (ubit != 0) << 24; | |
14258 | if (size != -1) | |
14259 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14260 | |
88714cb8 | 14261 | neon_dp_fixup (&inst); |
037e8744 JB |
14262 | } |
14263 | ||
14264 | /* Encode instructions of the form: | |
14265 | ||
14266 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
14267 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
14268 | |
14269 | Don't write size if SIZE == -1. */ | |
14270 | ||
14271 | static void | |
14272 | neon_two_same (int qbit, int ubit, int size) | |
14273 | { | |
14274 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14275 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14276 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14277 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14278 | inst.instruction |= (qbit != 0) << 6; | |
14279 | inst.instruction |= (ubit != 0) << 24; | |
14280 | ||
14281 | if (size != -1) | |
14282 | inst.instruction |= neon_logbits (size) << 18; | |
14283 | ||
88714cb8 | 14284 | neon_dp_fixup (&inst); |
5287ad62 JB |
14285 | } |
14286 | ||
14287 | /* Neon instruction encoders, in approximate order of appearance. */ | |
14288 | ||
14289 | static void | |
14290 | do_neon_dyadic_i_su (void) | |
14291 | { | |
037e8744 | 14292 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14293 | struct neon_type_el et = neon_check_type (3, rs, |
14294 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 14295 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14296 | } |
14297 | ||
14298 | static void | |
14299 | do_neon_dyadic_i64_su (void) | |
14300 | { | |
037e8744 | 14301 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14302 | struct neon_type_el et = neon_check_type (3, rs, |
14303 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 14304 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14305 | } |
14306 | ||
14307 | static void | |
14308 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 14309 | unsigned immbits) |
5287ad62 JB |
14310 | { |
14311 | unsigned size = et.size >> 3; | |
14312 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14313 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14314 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14315 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14316 | inst.instruction |= (isquad != 0) << 6; | |
14317 | inst.instruction |= immbits << 16; | |
14318 | inst.instruction |= (size >> 3) << 7; | |
14319 | inst.instruction |= (size & 0x7) << 19; | |
14320 | if (write_ubit) | |
14321 | inst.instruction |= (uval != 0) << 24; | |
14322 | ||
88714cb8 | 14323 | neon_dp_fixup (&inst); |
5287ad62 JB |
14324 | } |
14325 | ||
14326 | static void | |
14327 | do_neon_shl_imm (void) | |
14328 | { | |
14329 | if (!inst.operands[2].isreg) | |
14330 | { | |
037e8744 | 14331 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14332 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
cb3b1e65 JB |
14333 | int imm = inst.operands[2].imm; |
14334 | ||
14335 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14336 | _("immediate out of range for shift")); | |
88714cb8 | 14337 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14338 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14339 | } |
14340 | else | |
14341 | { | |
037e8744 | 14342 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14343 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14344 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14345 | unsigned int tmp; |
14346 | ||
14347 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
477330fc RM |
14348 | vshl.xx Dd, Dm, Dn |
14349 | whereas other 3-register operations encoded by neon_three_same have | |
14350 | syntax like: | |
14351 | vadd.xx Dd, Dn, Dm | |
14352 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
14353 | here. */ | |
627907b7 JB |
14354 | tmp = inst.operands[2].reg; |
14355 | inst.operands[2].reg = inst.operands[1].reg; | |
14356 | inst.operands[1].reg = tmp; | |
88714cb8 | 14357 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14358 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14359 | } |
14360 | } | |
14361 | ||
14362 | static void | |
14363 | do_neon_qshl_imm (void) | |
14364 | { | |
14365 | if (!inst.operands[2].isreg) | |
14366 | { | |
037e8744 | 14367 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14368 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
cb3b1e65 | 14369 | int imm = inst.operands[2].imm; |
627907b7 | 14370 | |
cb3b1e65 JB |
14371 | constraint (imm < 0 || (unsigned)imm >= et.size, |
14372 | _("immediate out of range for shift")); | |
88714cb8 | 14373 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14374 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
5287ad62 JB |
14375 | } |
14376 | else | |
14377 | { | |
037e8744 | 14378 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14379 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14380 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14381 | unsigned int tmp; |
14382 | ||
14383 | /* See note in do_neon_shl_imm. */ | |
14384 | tmp = inst.operands[2].reg; | |
14385 | inst.operands[2].reg = inst.operands[1].reg; | |
14386 | inst.operands[1].reg = tmp; | |
88714cb8 | 14387 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14388 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14389 | } |
14390 | } | |
14391 | ||
627907b7 JB |
14392 | static void |
14393 | do_neon_rshl (void) | |
14394 | { | |
14395 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
14396 | struct neon_type_el et = neon_check_type (3, rs, | |
14397 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
14398 | unsigned int tmp; | |
14399 | ||
14400 | tmp = inst.operands[2].reg; | |
14401 | inst.operands[2].reg = inst.operands[1].reg; | |
14402 | inst.operands[1].reg = tmp; | |
14403 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
14404 | } | |
14405 | ||
5287ad62 JB |
14406 | static int |
14407 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
14408 | { | |
036dc3f7 PB |
14409 | /* Handle .I8 pseudo-instructions. */ |
14410 | if (size == 8) | |
5287ad62 | 14411 | { |
5287ad62 | 14412 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
14413 | FIXME is this the intended semantics? There doesn't seem much point in |
14414 | accepting .I8 if so. */ | |
5287ad62 JB |
14415 | immediate |= immediate << 8; |
14416 | size = 16; | |
036dc3f7 PB |
14417 | } |
14418 | ||
14419 | if (size >= 32) | |
14420 | { | |
14421 | if (immediate == (immediate & 0x000000ff)) | |
14422 | { | |
14423 | *immbits = immediate; | |
14424 | return 0x1; | |
14425 | } | |
14426 | else if (immediate == (immediate & 0x0000ff00)) | |
14427 | { | |
14428 | *immbits = immediate >> 8; | |
14429 | return 0x3; | |
14430 | } | |
14431 | else if (immediate == (immediate & 0x00ff0000)) | |
14432 | { | |
14433 | *immbits = immediate >> 16; | |
14434 | return 0x5; | |
14435 | } | |
14436 | else if (immediate == (immediate & 0xff000000)) | |
14437 | { | |
14438 | *immbits = immediate >> 24; | |
14439 | return 0x7; | |
14440 | } | |
14441 | if ((immediate & 0xffff) != (immediate >> 16)) | |
14442 | goto bad_immediate; | |
14443 | immediate &= 0xffff; | |
5287ad62 JB |
14444 | } |
14445 | ||
14446 | if (immediate == (immediate & 0x000000ff)) | |
14447 | { | |
14448 | *immbits = immediate; | |
036dc3f7 | 14449 | return 0x9; |
5287ad62 JB |
14450 | } |
14451 | else if (immediate == (immediate & 0x0000ff00)) | |
14452 | { | |
14453 | *immbits = immediate >> 8; | |
036dc3f7 | 14454 | return 0xb; |
5287ad62 JB |
14455 | } |
14456 | ||
14457 | bad_immediate: | |
dcbf9037 | 14458 | first_error (_("immediate value out of range")); |
5287ad62 JB |
14459 | return FAIL; |
14460 | } | |
14461 | ||
5287ad62 JB |
14462 | static void |
14463 | do_neon_logic (void) | |
14464 | { | |
14465 | if (inst.operands[2].present && inst.operands[2].isreg) | |
14466 | { | |
037e8744 | 14467 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14468 | neon_check_type (3, rs, N_IGNORE_TYPE); |
14469 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 14470 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14471 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14472 | } |
14473 | else | |
14474 | { | |
4316f0d2 DG |
14475 | const int three_ops_form = (inst.operands[2].present |
14476 | && !inst.operands[2].isreg); | |
14477 | const int immoperand = (three_ops_form ? 2 : 1); | |
14478 | enum neon_shape rs = (three_ops_form | |
14479 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
14480 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 | 14481 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14482 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); |
21d799b5 | 14483 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
14484 | unsigned immbits; |
14485 | int cmode; | |
5f4273c7 | 14486 | |
5287ad62 | 14487 | if (et.type == NT_invtype) |
477330fc | 14488 | return; |
5f4273c7 | 14489 | |
4316f0d2 DG |
14490 | if (three_ops_form) |
14491 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14492 | _("first and second operands shall be the same register")); | |
14493 | ||
88714cb8 | 14494 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 14495 | |
4316f0d2 | 14496 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
14497 | if (et.size == 64) |
14498 | { | |
14499 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
14500 | pattern. */ | |
4316f0d2 DG |
14501 | if (immbits != (inst.operands[immoperand].regisimm ? |
14502 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
14503 | { |
14504 | /* Set immbits to an invalid constant. */ | |
14505 | immbits = 0xdeadbeef; | |
14506 | } | |
14507 | } | |
14508 | ||
5287ad62 | 14509 | switch (opcode) |
477330fc RM |
14510 | { |
14511 | case N_MNEM_vbic: | |
14512 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14513 | break; | |
14514 | ||
14515 | case N_MNEM_vorr: | |
14516 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14517 | break; | |
14518 | ||
14519 | case N_MNEM_vand: | |
14520 | /* Pseudo-instruction for VBIC. */ | |
14521 | neon_invert_size (&immbits, 0, et.size); | |
14522 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14523 | break; | |
14524 | ||
14525 | case N_MNEM_vorn: | |
14526 | /* Pseudo-instruction for VORR. */ | |
14527 | neon_invert_size (&immbits, 0, et.size); | |
14528 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14529 | break; | |
14530 | ||
14531 | default: | |
14532 | abort (); | |
14533 | } | |
5287ad62 JB |
14534 | |
14535 | if (cmode == FAIL) | |
477330fc | 14536 | return; |
5287ad62 | 14537 | |
037e8744 | 14538 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14539 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14540 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14541 | inst.instruction |= cmode << 8; | |
14542 | neon_write_immbits (immbits); | |
5f4273c7 | 14543 | |
88714cb8 | 14544 | neon_dp_fixup (&inst); |
5287ad62 JB |
14545 | } |
14546 | } | |
14547 | ||
14548 | static void | |
14549 | do_neon_bitfield (void) | |
14550 | { | |
037e8744 | 14551 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14552 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 14553 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14554 | } |
14555 | ||
14556 | static void | |
dcbf9037 | 14557 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 14558 | unsigned destbits) |
5287ad62 | 14559 | { |
037e8744 | 14560 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14561 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 14562 | types | N_KEY); |
5287ad62 JB |
14563 | if (et.type == NT_float) |
14564 | { | |
88714cb8 | 14565 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 14566 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14567 | } |
14568 | else | |
14569 | { | |
88714cb8 | 14570 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14571 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
14572 | } |
14573 | } | |
14574 | ||
14575 | static void | |
14576 | do_neon_dyadic_if_su (void) | |
14577 | { | |
dcbf9037 | 14578 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14579 | } |
14580 | ||
14581 | static void | |
14582 | do_neon_dyadic_if_su_d (void) | |
14583 | { | |
14584 | /* This version only allow D registers, but that constraint is enforced during | |
14585 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 14586 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14587 | } |
14588 | ||
5287ad62 JB |
14589 | static void |
14590 | do_neon_dyadic_if_i_d (void) | |
14591 | { | |
428e3f1f PB |
14592 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14593 | affected if we specify unsigned args. */ | |
14594 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
14595 | } |
14596 | ||
037e8744 JB |
14597 | enum vfp_or_neon_is_neon_bits |
14598 | { | |
14599 | NEON_CHECK_CC = 1, | |
73924fbc MGD |
14600 | NEON_CHECK_ARCH = 2, |
14601 | NEON_CHECK_ARCH8 = 4 | |
037e8744 JB |
14602 | }; |
14603 | ||
14604 | /* Call this function if an instruction which may have belonged to the VFP or | |
14605 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
14606 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
14607 | things: | |
14608 | ||
14609 | - Make sure the user hasn't attempted to make a Neon instruction | |
14610 | conditional. | |
14611 | - Alter the value in the condition code field if necessary. | |
14612 | - Make sure that the arch supports Neon instructions. | |
14613 | ||
14614 | Which of these operations take place depends on bits from enum | |
14615 | vfp_or_neon_is_neon_bits. | |
14616 | ||
14617 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
14618 | current instruction's condition is COND_ALWAYS, the condition field is | |
14619 | changed to inst.uncond_value. This is necessary because instructions shared | |
14620 | between VFP and Neon may be conditional for the VFP variants only, and the | |
14621 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
14622 | ||
14623 | static int | |
14624 | vfp_or_neon_is_neon (unsigned check) | |
14625 | { | |
14626 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
14627 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
14628 | { | |
14629 | if (inst.cond != COND_ALWAYS) | |
477330fc RM |
14630 | { |
14631 | first_error (_(BAD_COND)); | |
14632 | return FAIL; | |
14633 | } | |
037e8744 | 14634 | if (inst.uncond_value != -1) |
477330fc | 14635 | inst.instruction |= inst.uncond_value << 28; |
037e8744 | 14636 | } |
5f4273c7 | 14637 | |
037e8744 | 14638 | if ((check & NEON_CHECK_ARCH) |
73924fbc MGD |
14639 | && !mark_feature_used (&fpu_neon_ext_v1)) |
14640 | { | |
14641 | first_error (_(BAD_FPU)); | |
14642 | return FAIL; | |
14643 | } | |
14644 | ||
14645 | if ((check & NEON_CHECK_ARCH8) | |
14646 | && !mark_feature_used (&fpu_neon_ext_armv8)) | |
037e8744 JB |
14647 | { |
14648 | first_error (_(BAD_FPU)); | |
14649 | return FAIL; | |
14650 | } | |
5f4273c7 | 14651 | |
037e8744 JB |
14652 | return SUCCESS; |
14653 | } | |
14654 | ||
5287ad62 JB |
14655 | static void |
14656 | do_neon_addsub_if_i (void) | |
14657 | { | |
037e8744 JB |
14658 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
14659 | return; | |
14660 | ||
14661 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14662 | return; | |
14663 | ||
5287ad62 JB |
14664 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14665 | affected if we specify unsigned args. */ | |
dcbf9037 | 14666 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
14667 | } |
14668 | ||
14669 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
14670 | result to be: | |
14671 | V<op> A,B (A is operand 0, B is operand 2) | |
14672 | to mean: | |
14673 | V<op> A,B,A | |
14674 | not: | |
14675 | V<op> A,B,B | |
14676 | so handle that case specially. */ | |
14677 | ||
14678 | static void | |
14679 | neon_exchange_operands (void) | |
14680 | { | |
14681 | void *scratch = alloca (sizeof (inst.operands[0])); | |
14682 | if (inst.operands[1].present) | |
14683 | { | |
14684 | /* Swap operands[1] and operands[2]. */ | |
14685 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
14686 | inst.operands[1] = inst.operands[2]; | |
14687 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
14688 | } | |
14689 | else | |
14690 | { | |
14691 | inst.operands[1] = inst.operands[2]; | |
14692 | inst.operands[2] = inst.operands[0]; | |
14693 | } | |
14694 | } | |
14695 | ||
14696 | static void | |
14697 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
14698 | { | |
14699 | if (inst.operands[2].isreg) | |
14700 | { | |
14701 | if (invert) | |
477330fc | 14702 | neon_exchange_operands (); |
dcbf9037 | 14703 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
14704 | } |
14705 | else | |
14706 | { | |
037e8744 | 14707 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 14708 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14709 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 14710 | |
88714cb8 | 14711 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14712 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14713 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14714 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14715 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14716 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14717 | inst.instruction |= (et.type == NT_float) << 10; |
14718 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14719 | |
88714cb8 | 14720 | neon_dp_fixup (&inst); |
5287ad62 JB |
14721 | } |
14722 | } | |
14723 | ||
14724 | static void | |
14725 | do_neon_cmp (void) | |
14726 | { | |
14727 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
14728 | } | |
14729 | ||
14730 | static void | |
14731 | do_neon_cmp_inv (void) | |
14732 | { | |
14733 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
14734 | } | |
14735 | ||
14736 | static void | |
14737 | do_neon_ceq (void) | |
14738 | { | |
14739 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
14740 | } | |
14741 | ||
14742 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
14743 | scalars, which are encoded in 5 bits, M : Rm. | |
14744 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
14745 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
14746 | index in M. */ | |
14747 | ||
14748 | static unsigned | |
14749 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
14750 | { | |
dcbf9037 JB |
14751 | unsigned regno = NEON_SCALAR_REG (scalar); |
14752 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
14753 | |
14754 | switch (elsize) | |
14755 | { | |
14756 | case 16: | |
14757 | if (regno > 7 || elno > 3) | |
477330fc | 14758 | goto bad_scalar; |
5287ad62 | 14759 | return regno | (elno << 3); |
5f4273c7 | 14760 | |
5287ad62 JB |
14761 | case 32: |
14762 | if (regno > 15 || elno > 1) | |
477330fc | 14763 | goto bad_scalar; |
5287ad62 JB |
14764 | return regno | (elno << 4); |
14765 | ||
14766 | default: | |
14767 | bad_scalar: | |
dcbf9037 | 14768 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
14769 | } |
14770 | ||
14771 | return 0; | |
14772 | } | |
14773 | ||
14774 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
14775 | ||
14776 | static void | |
14777 | neon_mul_mac (struct neon_type_el et, int ubit) | |
14778 | { | |
dcbf9037 JB |
14779 | unsigned scalar; |
14780 | ||
14781 | /* Give a more helpful error message if we have an invalid type. */ | |
14782 | if (et.type == NT_invtype) | |
14783 | return; | |
5f4273c7 | 14784 | |
dcbf9037 | 14785 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
14786 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14787 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14788 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14789 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14790 | inst.instruction |= LOW4 (scalar); | |
14791 | inst.instruction |= HI1 (scalar) << 5; | |
14792 | inst.instruction |= (et.type == NT_float) << 8; | |
14793 | inst.instruction |= neon_logbits (et.size) << 20; | |
14794 | inst.instruction |= (ubit != 0) << 24; | |
14795 | ||
88714cb8 | 14796 | neon_dp_fixup (&inst); |
5287ad62 JB |
14797 | } |
14798 | ||
14799 | static void | |
14800 | do_neon_mac_maybe_scalar (void) | |
14801 | { | |
037e8744 JB |
14802 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
14803 | return; | |
14804 | ||
14805 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14806 | return; | |
14807 | ||
5287ad62 JB |
14808 | if (inst.operands[2].isscalar) |
14809 | { | |
037e8744 | 14810 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14811 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14812 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); |
88714cb8 | 14813 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14814 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14815 | } |
14816 | else | |
428e3f1f PB |
14817 | { |
14818 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
14819 | affected if we specify unsigned args. */ | |
14820 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14821 | } | |
5287ad62 JB |
14822 | } |
14823 | ||
62f3b8c8 PB |
14824 | static void |
14825 | do_neon_fmac (void) | |
14826 | { | |
14827 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
14828 | return; | |
14829 | ||
14830 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14831 | return; | |
14832 | ||
14833 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14834 | } | |
14835 | ||
5287ad62 JB |
14836 | static void |
14837 | do_neon_tst (void) | |
14838 | { | |
037e8744 | 14839 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14840 | struct neon_type_el et = neon_check_type (3, rs, |
14841 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 14842 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14843 | } |
14844 | ||
14845 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
14846 | same types as the MAC equivalents. The polynomial type for this instruction | |
14847 | is encoded the same as the integer type. */ | |
14848 | ||
14849 | static void | |
14850 | do_neon_mul (void) | |
14851 | { | |
037e8744 JB |
14852 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
14853 | return; | |
14854 | ||
14855 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14856 | return; | |
14857 | ||
5287ad62 JB |
14858 | if (inst.operands[2].isscalar) |
14859 | do_neon_mac_maybe_scalar (); | |
14860 | else | |
dcbf9037 | 14861 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
14862 | } |
14863 | ||
14864 | static void | |
14865 | do_neon_qdmulh (void) | |
14866 | { | |
14867 | if (inst.operands[2].isscalar) | |
14868 | { | |
037e8744 | 14869 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14870 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14871 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14872 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14873 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14874 | } |
14875 | else | |
14876 | { | |
037e8744 | 14877 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14878 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14879 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14880 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14881 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14882 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14883 | } |
14884 | } | |
14885 | ||
14886 | static void | |
14887 | do_neon_fcmp_absolute (void) | |
14888 | { | |
037e8744 | 14889 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14890 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14891 | /* Size field comes from bit mask. */ | |
037e8744 | 14892 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14893 | } |
14894 | ||
14895 | static void | |
14896 | do_neon_fcmp_absolute_inv (void) | |
14897 | { | |
14898 | neon_exchange_operands (); | |
14899 | do_neon_fcmp_absolute (); | |
14900 | } | |
14901 | ||
14902 | static void | |
14903 | do_neon_step (void) | |
14904 | { | |
037e8744 | 14905 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14906 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14907 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14908 | } |
14909 | ||
14910 | static void | |
14911 | do_neon_abs_neg (void) | |
14912 | { | |
037e8744 JB |
14913 | enum neon_shape rs; |
14914 | struct neon_type_el et; | |
5f4273c7 | 14915 | |
037e8744 JB |
14916 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14917 | return; | |
14918 | ||
14919 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14920 | return; | |
14921 | ||
14922 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14923 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14924 | |
5287ad62 JB |
14925 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14926 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14927 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14928 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14929 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14930 | inst.instruction |= (et.type == NT_float) << 10; |
14931 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14932 | |
88714cb8 | 14933 | neon_dp_fixup (&inst); |
5287ad62 JB |
14934 | } |
14935 | ||
14936 | static void | |
14937 | do_neon_sli (void) | |
14938 | { | |
037e8744 | 14939 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14940 | struct neon_type_el et = neon_check_type (2, rs, |
14941 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14942 | int imm = inst.operands[2].imm; | |
14943 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14944 | _("immediate out of range for insert")); |
037e8744 | 14945 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14946 | } |
14947 | ||
14948 | static void | |
14949 | do_neon_sri (void) | |
14950 | { | |
037e8744 | 14951 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14952 | struct neon_type_el et = neon_check_type (2, rs, |
14953 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14954 | int imm = inst.operands[2].imm; | |
14955 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 14956 | _("immediate out of range for insert")); |
037e8744 | 14957 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14958 | } |
14959 | ||
14960 | static void | |
14961 | do_neon_qshlu_imm (void) | |
14962 | { | |
037e8744 | 14963 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14964 | struct neon_type_el et = neon_check_type (2, rs, |
14965 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14966 | int imm = inst.operands[2].imm; | |
14967 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14968 | _("immediate out of range for shift")); |
5287ad62 JB |
14969 | /* Only encodes the 'U present' variant of the instruction. |
14970 | In this case, signed types have OP (bit 8) set to 0. | |
14971 | Unsigned types have OP set to 1. */ | |
14972 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14973 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14974 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14975 | } |
14976 | ||
14977 | static void | |
14978 | do_neon_qmovn (void) | |
14979 | { | |
14980 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14981 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14982 | /* Saturating move where operands can be signed or unsigned, and the | |
14983 | destination has the same signedness. */ | |
88714cb8 | 14984 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14985 | if (et.type == NT_unsigned) |
14986 | inst.instruction |= 0xc0; | |
14987 | else | |
14988 | inst.instruction |= 0x80; | |
14989 | neon_two_same (0, 1, et.size / 2); | |
14990 | } | |
14991 | ||
14992 | static void | |
14993 | do_neon_qmovun (void) | |
14994 | { | |
14995 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14996 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14997 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14998 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14999 | neon_two_same (0, 1, et.size / 2); |
15000 | } | |
15001 | ||
15002 | static void | |
15003 | do_neon_rshift_sat_narrow (void) | |
15004 | { | |
15005 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
15006 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
15007 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15008 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
15009 | int imm = inst.operands[2].imm; | |
15010 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15011 | right. */ | |
15012 | et.size /= 2; | |
5f4273c7 | 15013 | |
5287ad62 JB |
15014 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
15015 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
15016 | if (imm == 0) | |
15017 | { | |
15018 | inst.operands[2].present = 0; | |
15019 | inst.instruction = N_MNEM_vqmovn; | |
15020 | do_neon_qmovn (); | |
15021 | return; | |
15022 | } | |
5f4273c7 | 15023 | |
5287ad62 | 15024 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 15025 | _("immediate out of range")); |
5287ad62 JB |
15026 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
15027 | } | |
15028 | ||
15029 | static void | |
15030 | do_neon_rshift_sat_narrow_u (void) | |
15031 | { | |
15032 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
15033 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
15034 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15035 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
15036 | int imm = inst.operands[2].imm; | |
15037 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15038 | right. */ | |
15039 | et.size /= 2; | |
15040 | ||
15041 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
15042 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
15043 | if (imm == 0) | |
15044 | { | |
15045 | inst.operands[2].present = 0; | |
15046 | inst.instruction = N_MNEM_vqmovun; | |
15047 | do_neon_qmovun (); | |
15048 | return; | |
15049 | } | |
15050 | ||
15051 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 15052 | _("immediate out of range")); |
5287ad62 JB |
15053 | /* FIXME: The manual is kind of unclear about what value U should have in |
15054 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
15055 | must be 1. */ | |
15056 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
15057 | } | |
15058 | ||
15059 | static void | |
15060 | do_neon_movn (void) | |
15061 | { | |
15062 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
15063 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 15064 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15065 | neon_two_same (0, 1, et.size / 2); |
15066 | } | |
15067 | ||
15068 | static void | |
15069 | do_neon_rshift_narrow (void) | |
15070 | { | |
15071 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15072 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
15073 | int imm = inst.operands[2].imm; | |
15074 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15075 | right. */ | |
15076 | et.size /= 2; | |
5f4273c7 | 15077 | |
5287ad62 JB |
15078 | /* If immediate is zero then we are a pseudo-instruction for |
15079 | VMOVN.I<size> <Dd>, <Qm> */ | |
15080 | if (imm == 0) | |
15081 | { | |
15082 | inst.operands[2].present = 0; | |
15083 | inst.instruction = N_MNEM_vmovn; | |
15084 | do_neon_movn (); | |
15085 | return; | |
15086 | } | |
5f4273c7 | 15087 | |
5287ad62 | 15088 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 15089 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
15090 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
15091 | } | |
15092 | ||
15093 | static void | |
15094 | do_neon_shll (void) | |
15095 | { | |
15096 | /* FIXME: Type checking when lengthening. */ | |
15097 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
15098 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
15099 | unsigned imm = inst.operands[2].imm; | |
15100 | ||
15101 | if (imm == et.size) | |
15102 | { | |
15103 | /* Maximum shift variant. */ | |
88714cb8 | 15104 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15105 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15106 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15107 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15108 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15109 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 15110 | |
88714cb8 | 15111 | neon_dp_fixup (&inst); |
5287ad62 JB |
15112 | } |
15113 | else | |
15114 | { | |
15115 | /* A more-specific type check for non-max versions. */ | |
15116 | et = neon_check_type (2, NS_QDI, | |
477330fc | 15117 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 15118 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15119 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
15120 | } | |
15121 | } | |
15122 | ||
037e8744 | 15123 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
15124 | the current instruction is. */ |
15125 | ||
6b9a8b67 MGD |
15126 | #define CVT_FLAVOUR_VAR \ |
15127 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
15128 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
15129 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
15130 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
15131 | /* Half-precision conversions. */ \ | |
15132 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ | |
15133 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
15134 | /* VFP instructions. */ \ | |
15135 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
15136 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
15137 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
15138 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
15139 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
15140 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
15141 | /* VFP instructions with bitshift. */ \ | |
15142 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
15143 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
15144 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
15145 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
15146 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
15147 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
15148 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
15149 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
15150 | ||
15151 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
15152 | neon_cvt_flavour_##C, | |
15153 | ||
15154 | /* The different types of conversions we can do. */ | |
15155 | enum neon_cvt_flavour | |
15156 | { | |
15157 | CVT_FLAVOUR_VAR | |
15158 | neon_cvt_flavour_invalid, | |
15159 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
15160 | }; | |
15161 | ||
15162 | #undef CVT_VAR | |
15163 | ||
15164 | static enum neon_cvt_flavour | |
15165 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 15166 | { |
6b9a8b67 MGD |
15167 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
15168 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
15169 | if (et.type != NT_invtype) \ | |
15170 | { \ | |
15171 | inst.error = NULL; \ | |
15172 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 15173 | } |
6b9a8b67 | 15174 | |
5287ad62 | 15175 | struct neon_type_el et; |
037e8744 | 15176 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 15177 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
15178 | /* The instruction versions which take an immediate take one register |
15179 | argument, which is extended to the width of the full register. Thus the | |
15180 | "source" and "destination" registers must have the same width. Hack that | |
15181 | here by making the size equal to the key (wider, in this case) operand. */ | |
15182 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 15183 | |
6b9a8b67 MGD |
15184 | CVT_FLAVOUR_VAR; |
15185 | ||
15186 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
15187 | #undef CVT_VAR |
15188 | } | |
15189 | ||
7e8e6784 MGD |
15190 | enum neon_cvt_mode |
15191 | { | |
15192 | neon_cvt_mode_a, | |
15193 | neon_cvt_mode_n, | |
15194 | neon_cvt_mode_p, | |
15195 | neon_cvt_mode_m, | |
15196 | neon_cvt_mode_z, | |
30bdf752 MGD |
15197 | neon_cvt_mode_x, |
15198 | neon_cvt_mode_r | |
7e8e6784 MGD |
15199 | }; |
15200 | ||
037e8744 JB |
15201 | /* Neon-syntax VFP conversions. */ |
15202 | ||
5287ad62 | 15203 | static void |
6b9a8b67 | 15204 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 15205 | { |
037e8744 | 15206 | const char *opname = 0; |
5f4273c7 | 15207 | |
037e8744 | 15208 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 15209 | { |
037e8744 JB |
15210 | /* Conversions with immediate bitshift. */ |
15211 | const char *enc[] = | |
477330fc | 15212 | { |
6b9a8b67 MGD |
15213 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
15214 | CVT_FLAVOUR_VAR | |
15215 | NULL | |
15216 | #undef CVT_VAR | |
477330fc | 15217 | }; |
037e8744 | 15218 | |
6b9a8b67 | 15219 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
15220 | { |
15221 | opname = enc[flavour]; | |
15222 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
15223 | _("operands 0 and 1 must be the same register")); | |
15224 | inst.operands[1] = inst.operands[2]; | |
15225 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
15226 | } | |
5287ad62 JB |
15227 | } |
15228 | else | |
15229 | { | |
037e8744 JB |
15230 | /* Conversions without bitshift. */ |
15231 | const char *enc[] = | |
477330fc | 15232 | { |
6b9a8b67 MGD |
15233 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
15234 | CVT_FLAVOUR_VAR | |
15235 | NULL | |
15236 | #undef CVT_VAR | |
477330fc | 15237 | }; |
037e8744 | 15238 | |
6b9a8b67 | 15239 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 15240 | opname = enc[flavour]; |
037e8744 JB |
15241 | } |
15242 | ||
15243 | if (opname) | |
15244 | do_vfp_nsyn_opcode (opname); | |
15245 | } | |
15246 | ||
15247 | static void | |
15248 | do_vfp_nsyn_cvtz (void) | |
15249 | { | |
15250 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
6b9a8b67 | 15251 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
15252 | const char *enc[] = |
15253 | { | |
6b9a8b67 MGD |
15254 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
15255 | CVT_FLAVOUR_VAR | |
15256 | NULL | |
15257 | #undef CVT_VAR | |
037e8744 JB |
15258 | }; |
15259 | ||
6b9a8b67 | 15260 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
15261 | do_vfp_nsyn_opcode (enc[flavour]); |
15262 | } | |
f31fef98 | 15263 | |
037e8744 | 15264 | static void |
bacebabc | 15265 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
15266 | enum neon_cvt_mode mode) |
15267 | { | |
15268 | int sz, op; | |
15269 | int rm; | |
15270 | ||
a715796b TG |
15271 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
15272 | D register operands. */ | |
15273 | if (flavour == neon_cvt_flavour_s32_f64 | |
15274 | || flavour == neon_cvt_flavour_u32_f64) | |
15275 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15276 | _(BAD_FPU)); | |
15277 | ||
7e8e6784 MGD |
15278 | set_it_insn_type (OUTSIDE_IT_INSN); |
15279 | ||
15280 | switch (flavour) | |
15281 | { | |
15282 | case neon_cvt_flavour_s32_f64: | |
15283 | sz = 1; | |
827f64ff | 15284 | op = 1; |
7e8e6784 MGD |
15285 | break; |
15286 | case neon_cvt_flavour_s32_f32: | |
15287 | sz = 0; | |
15288 | op = 1; | |
15289 | break; | |
15290 | case neon_cvt_flavour_u32_f64: | |
15291 | sz = 1; | |
15292 | op = 0; | |
15293 | break; | |
15294 | case neon_cvt_flavour_u32_f32: | |
15295 | sz = 0; | |
15296 | op = 0; | |
15297 | break; | |
15298 | default: | |
15299 | first_error (_("invalid instruction shape")); | |
15300 | return; | |
15301 | } | |
15302 | ||
15303 | switch (mode) | |
15304 | { | |
15305 | case neon_cvt_mode_a: rm = 0; break; | |
15306 | case neon_cvt_mode_n: rm = 1; break; | |
15307 | case neon_cvt_mode_p: rm = 2; break; | |
15308 | case neon_cvt_mode_m: rm = 3; break; | |
15309 | default: first_error (_("invalid rounding mode")); return; | |
15310 | } | |
15311 | ||
15312 | NEON_ENCODE (FPV8, inst); | |
15313 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
15314 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
15315 | inst.instruction |= sz << 8; | |
15316 | inst.instruction |= op << 7; | |
15317 | inst.instruction |= rm << 16; | |
15318 | inst.instruction |= 0xf0000000; | |
15319 | inst.is_neon = TRUE; | |
15320 | } | |
15321 | ||
15322 | static void | |
15323 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
15324 | { |
15325 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 15326 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
6b9a8b67 | 15327 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 15328 | |
e3e535bc | 15329 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 15330 | if (mode == neon_cvt_mode_z |
e3e535bc | 15331 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
bacebabc RM |
15332 | && (flavour == neon_cvt_flavour_s32_f32 |
15333 | || flavour == neon_cvt_flavour_u32_f32 | |
15334 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 15335 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
15336 | && (rs == NS_FD || rs == NS_FF)) |
15337 | { | |
15338 | do_vfp_nsyn_cvtz (); | |
15339 | return; | |
15340 | } | |
15341 | ||
037e8744 | 15342 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 15343 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 15344 | { |
7e8e6784 MGD |
15345 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15346 | do_vfp_nsyn_cvt (rs, flavour); | |
15347 | else | |
15348 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
15349 | ||
037e8744 JB |
15350 | return; |
15351 | } | |
15352 | ||
15353 | switch (rs) | |
15354 | { | |
15355 | case NS_DDI: | |
15356 | case NS_QQI: | |
15357 | { | |
477330fc RM |
15358 | unsigned immbits; |
15359 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
35997600 | 15360 | |
477330fc RM |
15361 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15362 | return; | |
037e8744 | 15363 | |
477330fc RM |
15364 | /* Fixed-point conversion with #0 immediate is encoded as an |
15365 | integer conversion. */ | |
15366 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
15367 | goto int_encode; | |
35997600 | 15368 | immbits = 32 - inst.operands[2].imm; |
477330fc RM |
15369 | NEON_ENCODE (IMMED, inst); |
15370 | if (flavour != neon_cvt_flavour_invalid) | |
15371 | inst.instruction |= enctab[flavour]; | |
15372 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15373 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15374 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15375 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15376 | inst.instruction |= neon_quad (rs) << 6; | |
15377 | inst.instruction |= 1 << 21; | |
15378 | inst.instruction |= immbits << 16; | |
15379 | ||
15380 | neon_dp_fixup (&inst); | |
037e8744 JB |
15381 | } |
15382 | break; | |
15383 | ||
15384 | case NS_DD: | |
15385 | case NS_QQ: | |
7e8e6784 MGD |
15386 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
15387 | { | |
15388 | NEON_ENCODE (FLOAT, inst); | |
15389 | set_it_insn_type (OUTSIDE_IT_INSN); | |
15390 | ||
15391 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
15392 | return; | |
15393 | ||
15394 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15395 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15396 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15397 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15398 | inst.instruction |= neon_quad (rs) << 6; | |
15399 | inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7; | |
15400 | inst.instruction |= mode << 8; | |
15401 | if (thumb_mode) | |
15402 | inst.instruction |= 0xfc000000; | |
15403 | else | |
15404 | inst.instruction |= 0xf0000000; | |
15405 | } | |
15406 | else | |
15407 | { | |
037e8744 | 15408 | int_encode: |
7e8e6784 MGD |
15409 | { |
15410 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
037e8744 | 15411 | |
7e8e6784 | 15412 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15413 | |
7e8e6784 MGD |
15414 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15415 | return; | |
037e8744 | 15416 | |
7e8e6784 MGD |
15417 | if (flavour != neon_cvt_flavour_invalid) |
15418 | inst.instruction |= enctab[flavour]; | |
037e8744 | 15419 | |
7e8e6784 MGD |
15420 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15421 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15422 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15423 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15424 | inst.instruction |= neon_quad (rs) << 6; | |
15425 | inst.instruction |= 2 << 18; | |
037e8744 | 15426 | |
7e8e6784 MGD |
15427 | neon_dp_fixup (&inst); |
15428 | } | |
15429 | } | |
15430 | break; | |
037e8744 | 15431 | |
8e79c3df CM |
15432 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
15433 | case NS_QD: | |
15434 | case NS_DQ: | |
15435 | ||
15436 | if ((rs == NS_DQ) | |
15437 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
15438 | { | |
15439 | as_bad (_("operand size must match register width")); | |
15440 | break; | |
15441 | } | |
15442 | ||
15443 | if ((rs == NS_QD) | |
15444 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
15445 | { | |
15446 | as_bad (_("operand size must match register width")); | |
15447 | break; | |
15448 | } | |
15449 | ||
15450 | if (rs == NS_DQ) | |
477330fc | 15451 | inst.instruction = 0x3b60600; |
8e79c3df CM |
15452 | else |
15453 | inst.instruction = 0x3b60700; | |
15454 | ||
15455 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15456 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15457 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15458 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 15459 | neon_dp_fixup (&inst); |
8e79c3df CM |
15460 | break; |
15461 | ||
037e8744 JB |
15462 | default: |
15463 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
15464 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15465 | do_vfp_nsyn_cvt (rs, flavour); | |
15466 | else | |
15467 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 15468 | } |
5287ad62 JB |
15469 | } |
15470 | ||
e3e535bc NC |
15471 | static void |
15472 | do_neon_cvtr (void) | |
15473 | { | |
7e8e6784 | 15474 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
15475 | } |
15476 | ||
15477 | static void | |
15478 | do_neon_cvt (void) | |
15479 | { | |
7e8e6784 MGD |
15480 | do_neon_cvt_1 (neon_cvt_mode_z); |
15481 | } | |
15482 | ||
15483 | static void | |
15484 | do_neon_cvta (void) | |
15485 | { | |
15486 | do_neon_cvt_1 (neon_cvt_mode_a); | |
15487 | } | |
15488 | ||
15489 | static void | |
15490 | do_neon_cvtn (void) | |
15491 | { | |
15492 | do_neon_cvt_1 (neon_cvt_mode_n); | |
15493 | } | |
15494 | ||
15495 | static void | |
15496 | do_neon_cvtp (void) | |
15497 | { | |
15498 | do_neon_cvt_1 (neon_cvt_mode_p); | |
15499 | } | |
15500 | ||
15501 | static void | |
15502 | do_neon_cvtm (void) | |
15503 | { | |
15504 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
15505 | } |
15506 | ||
8e79c3df | 15507 | static void |
c70a8987 | 15508 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 15509 | { |
c70a8987 MGD |
15510 | if (is_double) |
15511 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 15512 | |
c70a8987 MGD |
15513 | encode_arm_vfp_reg (inst.operands[0].reg, |
15514 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
15515 | encode_arm_vfp_reg (inst.operands[1].reg, | |
15516 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
15517 | inst.instruction |= to ? 0x10000 : 0; | |
15518 | inst.instruction |= t ? 0x80 : 0; | |
15519 | inst.instruction |= is_double ? 0x100 : 0; | |
15520 | do_vfp_cond_or_thumb (); | |
15521 | } | |
8e79c3df | 15522 | |
c70a8987 MGD |
15523 | static void |
15524 | do_neon_cvttb_1 (bfd_boolean t) | |
15525 | { | |
15526 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL); | |
8e79c3df | 15527 | |
c70a8987 MGD |
15528 | if (rs == NS_NULL) |
15529 | return; | |
15530 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) | |
15531 | { | |
15532 | inst.error = NULL; | |
15533 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
15534 | } | |
15535 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
15536 | { | |
15537 | inst.error = NULL; | |
15538 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
15539 | } | |
15540 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
15541 | { | |
a715796b TG |
15542 | /* The VCVTB and VCVTT instructions with D-register operands |
15543 | don't work for SP only targets. */ | |
15544 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15545 | _(BAD_FPU)); | |
15546 | ||
c70a8987 MGD |
15547 | inst.error = NULL; |
15548 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
15549 | } | |
15550 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
15551 | { | |
a715796b TG |
15552 | /* The VCVTB and VCVTT instructions with D-register operands |
15553 | don't work for SP only targets. */ | |
15554 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15555 | _(BAD_FPU)); | |
15556 | ||
c70a8987 MGD |
15557 | inst.error = NULL; |
15558 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
15559 | } | |
15560 | else | |
15561 | return; | |
15562 | } | |
15563 | ||
15564 | static void | |
15565 | do_neon_cvtb (void) | |
15566 | { | |
15567 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
15568 | } |
15569 | ||
15570 | ||
15571 | static void | |
15572 | do_neon_cvtt (void) | |
15573 | { | |
c70a8987 | 15574 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
15575 | } |
15576 | ||
5287ad62 JB |
15577 | static void |
15578 | neon_move_immediate (void) | |
15579 | { | |
037e8744 JB |
15580 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
15581 | struct neon_type_el et = neon_check_type (2, rs, | |
15582 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 15583 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 15584 | int op, cmode, float_p; |
5287ad62 | 15585 | |
037e8744 | 15586 | constraint (et.type == NT_invtype, |
477330fc | 15587 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 15588 | |
5287ad62 JB |
15589 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
15590 | op = (inst.instruction & (1 << 5)) != 0; | |
15591 | ||
15592 | immlo = inst.operands[1].imm; | |
15593 | if (inst.operands[1].regisimm) | |
15594 | immhi = inst.operands[1].reg; | |
15595 | ||
15596 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 15597 | _("immediate has bits set outside the operand size")); |
5287ad62 | 15598 | |
c96612cc JB |
15599 | float_p = inst.operands[1].immisfloat; |
15600 | ||
15601 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 15602 | et.size, et.type)) == FAIL) |
5287ad62 JB |
15603 | { |
15604 | /* Invert relevant bits only. */ | |
15605 | neon_invert_size (&immlo, &immhi, et.size); | |
15606 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
15607 | with one or the other; those cases are caught by |
15608 | neon_cmode_for_move_imm. */ | |
5287ad62 | 15609 | op = !op; |
c96612cc JB |
15610 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
15611 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
15612 | { |
15613 | first_error (_("immediate out of range")); | |
15614 | return; | |
15615 | } | |
5287ad62 JB |
15616 | } |
15617 | ||
15618 | inst.instruction &= ~(1 << 5); | |
15619 | inst.instruction |= op << 5; | |
15620 | ||
15621 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15622 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 15623 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15624 | inst.instruction |= cmode << 8; |
15625 | ||
15626 | neon_write_immbits (immbits); | |
15627 | } | |
15628 | ||
15629 | static void | |
15630 | do_neon_mvn (void) | |
15631 | { | |
15632 | if (inst.operands[1].isreg) | |
15633 | { | |
037e8744 | 15634 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 15635 | |
88714cb8 | 15636 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15637 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15638 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15639 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15640 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 15641 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15642 | } |
15643 | else | |
15644 | { | |
88714cb8 | 15645 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15646 | neon_move_immediate (); |
15647 | } | |
15648 | ||
88714cb8 | 15649 | neon_dp_fixup (&inst); |
5287ad62 JB |
15650 | } |
15651 | ||
15652 | /* Encode instructions of form: | |
15653 | ||
15654 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 15655 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
15656 | |
15657 | static void | |
15658 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
15659 | { | |
15660 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15661 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15662 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15663 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15664 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15665 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15666 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
15667 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 15668 | |
88714cb8 | 15669 | neon_dp_fixup (&inst); |
5287ad62 JB |
15670 | } |
15671 | ||
15672 | static void | |
15673 | do_neon_dyadic_long (void) | |
15674 | { | |
15675 | /* FIXME: Type checking for lengthening op. */ | |
15676 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15677 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15678 | neon_mixed_length (et, et.size); | |
15679 | } | |
15680 | ||
15681 | static void | |
15682 | do_neon_abal (void) | |
15683 | { | |
15684 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15685 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15686 | neon_mixed_length (et, et.size); | |
15687 | } | |
15688 | ||
15689 | static void | |
15690 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
15691 | { | |
15692 | if (inst.operands[2].isscalar) | |
15693 | { | |
dcbf9037 | 15694 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 15695 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 15696 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15697 | neon_mul_mac (et, et.type == NT_unsigned); |
15698 | } | |
15699 | else | |
15700 | { | |
15701 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15702 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 15703 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15704 | neon_mixed_length (et, et.size); |
15705 | } | |
15706 | } | |
15707 | ||
15708 | static void | |
15709 | do_neon_mac_maybe_scalar_long (void) | |
15710 | { | |
15711 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
15712 | } | |
15713 | ||
15714 | static void | |
15715 | do_neon_dyadic_wide (void) | |
15716 | { | |
15717 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
15718 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15719 | neon_mixed_length (et, et.size); | |
15720 | } | |
15721 | ||
15722 | static void | |
15723 | do_neon_dyadic_narrow (void) | |
15724 | { | |
15725 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15726 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
15727 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
15728 | so force the operand type to integer. */ | |
15729 | et.type = NT_integer; | |
5287ad62 JB |
15730 | neon_mixed_length (et, et.size / 2); |
15731 | } | |
15732 | ||
15733 | static void | |
15734 | do_neon_mul_sat_scalar_long (void) | |
15735 | { | |
15736 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
15737 | } | |
15738 | ||
15739 | static void | |
15740 | do_neon_vmull (void) | |
15741 | { | |
15742 | if (inst.operands[2].isscalar) | |
15743 | do_neon_mac_maybe_scalar_long (); | |
15744 | else | |
15745 | { | |
15746 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15747 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 15748 | |
5287ad62 | 15749 | if (et.type == NT_poly) |
477330fc | 15750 | NEON_ENCODE (POLY, inst); |
5287ad62 | 15751 | else |
477330fc | 15752 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
15753 | |
15754 | /* For polynomial encoding the U bit must be zero, and the size must | |
15755 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
15756 | obviously, as 0b10). */ | |
15757 | if (et.size == 64) | |
15758 | { | |
15759 | /* Check we're on the correct architecture. */ | |
15760 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
15761 | inst.error = | |
15762 | _("Instruction form not available on this architecture."); | |
15763 | ||
15764 | et.size = 32; | |
15765 | } | |
15766 | ||
5287ad62 JB |
15767 | neon_mixed_length (et, et.size); |
15768 | } | |
15769 | } | |
15770 | ||
15771 | static void | |
15772 | do_neon_ext (void) | |
15773 | { | |
037e8744 | 15774 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
15775 | struct neon_type_el et = neon_check_type (3, rs, |
15776 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
15777 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
15778 | |
15779 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
15780 | _("shift out of range")); | |
5287ad62 JB |
15781 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15782 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15783 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15784 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15785 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15786 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 15787 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 15788 | inst.instruction |= imm << 8; |
5f4273c7 | 15789 | |
88714cb8 | 15790 | neon_dp_fixup (&inst); |
5287ad62 JB |
15791 | } |
15792 | ||
15793 | static void | |
15794 | do_neon_rev (void) | |
15795 | { | |
037e8744 | 15796 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15797 | struct neon_type_el et = neon_check_type (2, rs, |
15798 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15799 | unsigned op = (inst.instruction >> 7) & 3; | |
15800 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
15801 | extract it here to check the elements to be reversed are smaller. | |
15802 | Otherwise we'd get a reserved instruction. */ | |
15803 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 15804 | gas_assert (elsize != 0); |
5287ad62 | 15805 | constraint (et.size >= elsize, |
477330fc | 15806 | _("elements must be smaller than reversal region")); |
037e8744 | 15807 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15808 | } |
15809 | ||
15810 | static void | |
15811 | do_neon_dup (void) | |
15812 | { | |
15813 | if (inst.operands[1].isscalar) | |
15814 | { | |
037e8744 | 15815 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 15816 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 15817 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 15818 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 15819 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 15820 | int logsize = neon_logbits (et.size); |
dcbf9037 | 15821 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
15822 | |
15823 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 15824 | return; |
037e8744 | 15825 | |
88714cb8 | 15826 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15827 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15828 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15829 | inst.instruction |= LOW4 (dm); | |
15830 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 15831 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15832 | inst.instruction |= x << 17; |
15833 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 15834 | |
88714cb8 | 15835 | neon_dp_fixup (&inst); |
5287ad62 JB |
15836 | } |
15837 | else | |
15838 | { | |
037e8744 JB |
15839 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
15840 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 15841 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
5287ad62 | 15842 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 15843 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 15844 | switch (et.size) |
477330fc RM |
15845 | { |
15846 | case 8: inst.instruction |= 0x400000; break; | |
15847 | case 16: inst.instruction |= 0x000020; break; | |
15848 | case 32: inst.instruction |= 0x000000; break; | |
15849 | default: break; | |
15850 | } | |
5287ad62 JB |
15851 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
15852 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
15853 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 15854 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 15855 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 15856 | variants, except for the condition field. */ |
037e8744 | 15857 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15858 | } |
15859 | } | |
15860 | ||
15861 | /* VMOV has particularly many variations. It can be one of: | |
15862 | 0. VMOV<c><q> <Qd>, <Qm> | |
15863 | 1. VMOV<c><q> <Dd>, <Dm> | |
15864 | (Register operations, which are VORR with Rm = Rn.) | |
15865 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
15866 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
15867 | (Immediate loads.) | |
15868 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
15869 | (ARM register to scalar.) | |
15870 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
15871 | (Two ARM registers to vector.) | |
15872 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
15873 | (Scalar to ARM register.) | |
15874 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
15875 | (Vector to two ARM registers.) | |
037e8744 JB |
15876 | 8. VMOV.F32 <Sd>, <Sm> |
15877 | 9. VMOV.F64 <Dd>, <Dm> | |
15878 | (VFP register moves.) | |
15879 | 10. VMOV.F32 <Sd>, #imm | |
15880 | 11. VMOV.F64 <Dd>, #imm | |
15881 | (VFP float immediate load.) | |
15882 | 12. VMOV <Rd>, <Sm> | |
15883 | (VFP single to ARM reg.) | |
15884 | 13. VMOV <Sd>, <Rm> | |
15885 | (ARM reg to VFP single.) | |
15886 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
15887 | (Two ARM regs to two VFP singles.) | |
15888 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
15889 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 15890 | |
037e8744 JB |
15891 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
15892 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 15893 | |
5287ad62 | 15894 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 15895 | |
b7fc2769 JB |
15896 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
15897 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 15898 | |
5287ad62 | 15899 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 15900 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
15901 | |
15902 | static void | |
15903 | do_neon_mov (void) | |
15904 | { | |
037e8744 JB |
15905 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
15906 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
15907 | NS_NULL); | |
15908 | struct neon_type_el et; | |
15909 | const char *ldconst = 0; | |
5287ad62 | 15910 | |
037e8744 | 15911 | switch (rs) |
5287ad62 | 15912 | { |
037e8744 JB |
15913 | case NS_DD: /* case 1/9. */ |
15914 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15915 | /* It is not an error here if no type is given. */ | |
15916 | inst.error = NULL; | |
15917 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15918 | { |
15919 | do_vfp_nsyn_opcode ("fcpyd"); | |
15920 | break; | |
15921 | } | |
037e8744 | 15922 | /* fall through. */ |
5287ad62 | 15923 | |
037e8744 JB |
15924 | case NS_QQ: /* case 0/1. */ |
15925 | { | |
477330fc RM |
15926 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15927 | return; | |
15928 | /* The architecture manual I have doesn't explicitly state which | |
15929 | value the U bit should have for register->register moves, but | |
15930 | the equivalent VORR instruction has U = 0, so do that. */ | |
15931 | inst.instruction = 0x0200110; | |
15932 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15933 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15934 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15935 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15936 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15937 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15938 | inst.instruction |= neon_quad (rs) << 6; | |
15939 | ||
15940 | neon_dp_fixup (&inst); | |
037e8744 JB |
15941 | } |
15942 | break; | |
5f4273c7 | 15943 | |
037e8744 JB |
15944 | case NS_DI: /* case 3/11. */ |
15945 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15946 | inst.error = NULL; | |
15947 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15948 | { |
15949 | /* case 11 (fconstd). */ | |
15950 | ldconst = "fconstd"; | |
15951 | goto encode_fconstd; | |
15952 | } | |
037e8744 JB |
15953 | /* fall through. */ |
15954 | ||
15955 | case NS_QI: /* case 2/3. */ | |
15956 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
477330fc | 15957 | return; |
037e8744 JB |
15958 | inst.instruction = 0x0800010; |
15959 | neon_move_immediate (); | |
88714cb8 | 15960 | neon_dp_fixup (&inst); |
5287ad62 | 15961 | break; |
5f4273c7 | 15962 | |
037e8744 JB |
15963 | case NS_SR: /* case 4. */ |
15964 | { | |
477330fc RM |
15965 | unsigned bcdebits = 0; |
15966 | int logsize; | |
15967 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
15968 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 15969 | |
05ac0ffb JB |
15970 | /* .<size> is optional here, defaulting to .32. */ |
15971 | if (inst.vectype.elems == 0 | |
15972 | && inst.operands[0].vectype.type == NT_invtype | |
15973 | && inst.operands[1].vectype.type == NT_invtype) | |
15974 | { | |
15975 | inst.vectype.el[0].type = NT_untyped; | |
15976 | inst.vectype.el[0].size = 32; | |
15977 | inst.vectype.elems = 1; | |
15978 | } | |
15979 | ||
477330fc RM |
15980 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
15981 | logsize = neon_logbits (et.size); | |
15982 | ||
15983 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15984 | _(BAD_FPU)); | |
15985 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15986 | && et.size != 32, _(BAD_FPU)); | |
15987 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15988 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15989 | ||
15990 | switch (et.size) | |
15991 | { | |
15992 | case 8: bcdebits = 0x8; break; | |
15993 | case 16: bcdebits = 0x1; break; | |
15994 | case 32: bcdebits = 0x0; break; | |
15995 | default: ; | |
15996 | } | |
15997 | ||
15998 | bcdebits |= x << logsize; | |
15999 | ||
16000 | inst.instruction = 0xe000b10; | |
16001 | do_vfp_cond_or_thumb (); | |
16002 | inst.instruction |= LOW4 (dn) << 16; | |
16003 | inst.instruction |= HI1 (dn) << 7; | |
16004 | inst.instruction |= inst.operands[1].reg << 12; | |
16005 | inst.instruction |= (bcdebits & 3) << 5; | |
16006 | inst.instruction |= (bcdebits >> 2) << 21; | |
037e8744 JB |
16007 | } |
16008 | break; | |
5f4273c7 | 16009 | |
037e8744 | 16010 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 16011 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
477330fc | 16012 | _(BAD_FPU)); |
b7fc2769 | 16013 | |
037e8744 JB |
16014 | inst.instruction = 0xc400b10; |
16015 | do_vfp_cond_or_thumb (); | |
16016 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
16017 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
16018 | inst.instruction |= inst.operands[1].reg << 12; | |
16019 | inst.instruction |= inst.operands[2].reg << 16; | |
16020 | break; | |
5f4273c7 | 16021 | |
037e8744 JB |
16022 | case NS_RS: /* case 6. */ |
16023 | { | |
477330fc RM |
16024 | unsigned logsize; |
16025 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
16026 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
16027 | unsigned abcdebits = 0; | |
037e8744 | 16028 | |
05ac0ffb JB |
16029 | /* .<dt> is optional here, defaulting to .32. */ |
16030 | if (inst.vectype.elems == 0 | |
16031 | && inst.operands[0].vectype.type == NT_invtype | |
16032 | && inst.operands[1].vectype.type == NT_invtype) | |
16033 | { | |
16034 | inst.vectype.el[0].type = NT_untyped; | |
16035 | inst.vectype.el[0].size = 32; | |
16036 | inst.vectype.elems = 1; | |
16037 | } | |
16038 | ||
91d6fa6a NC |
16039 | et = neon_check_type (2, NS_NULL, |
16040 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
16041 | logsize = neon_logbits (et.size); |
16042 | ||
16043 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
16044 | _(BAD_FPU)); | |
16045 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
16046 | && et.size != 32, _(BAD_FPU)); | |
16047 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
16048 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
16049 | ||
16050 | switch (et.size) | |
16051 | { | |
16052 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
16053 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
16054 | case 32: abcdebits = 0x00; break; | |
16055 | default: ; | |
16056 | } | |
16057 | ||
16058 | abcdebits |= x << logsize; | |
16059 | inst.instruction = 0xe100b10; | |
16060 | do_vfp_cond_or_thumb (); | |
16061 | inst.instruction |= LOW4 (dn) << 16; | |
16062 | inst.instruction |= HI1 (dn) << 7; | |
16063 | inst.instruction |= inst.operands[0].reg << 12; | |
16064 | inst.instruction |= (abcdebits & 3) << 5; | |
16065 | inst.instruction |= (abcdebits >> 2) << 21; | |
037e8744 JB |
16066 | } |
16067 | break; | |
5f4273c7 | 16068 | |
037e8744 JB |
16069 | case NS_RRD: /* case 7 (fmrrd). */ |
16070 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
477330fc | 16071 | _(BAD_FPU)); |
037e8744 JB |
16072 | |
16073 | inst.instruction = 0xc500b10; | |
16074 | do_vfp_cond_or_thumb (); | |
16075 | inst.instruction |= inst.operands[0].reg << 12; | |
16076 | inst.instruction |= inst.operands[1].reg << 16; | |
16077 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16078 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16079 | break; | |
5f4273c7 | 16080 | |
037e8744 JB |
16081 | case NS_FF: /* case 8 (fcpys). */ |
16082 | do_vfp_nsyn_opcode ("fcpys"); | |
16083 | break; | |
5f4273c7 | 16084 | |
037e8744 JB |
16085 | case NS_FI: /* case 10 (fconsts). */ |
16086 | ldconst = "fconsts"; | |
16087 | encode_fconstd: | |
16088 | if (is_quarter_float (inst.operands[1].imm)) | |
477330fc RM |
16089 | { |
16090 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
16091 | do_vfp_nsyn_opcode (ldconst); | |
16092 | } | |
5287ad62 | 16093 | else |
477330fc | 16094 | first_error (_("immediate out of range")); |
037e8744 | 16095 | break; |
5f4273c7 | 16096 | |
037e8744 JB |
16097 | case NS_RF: /* case 12 (fmrs). */ |
16098 | do_vfp_nsyn_opcode ("fmrs"); | |
16099 | break; | |
5f4273c7 | 16100 | |
037e8744 JB |
16101 | case NS_FR: /* case 13 (fmsr). */ |
16102 | do_vfp_nsyn_opcode ("fmsr"); | |
16103 | break; | |
5f4273c7 | 16104 | |
037e8744 JB |
16105 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
16106 | (one of which is a list), but we have parsed four. Do some fiddling to | |
16107 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
16108 | expect. */ | |
16109 | case NS_RRFF: /* case 14 (fmrrs). */ | |
16110 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
477330fc | 16111 | _("VFP registers must be adjacent")); |
037e8744 JB |
16112 | inst.operands[2].imm = 2; |
16113 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
16114 | do_vfp_nsyn_opcode ("fmrrs"); | |
16115 | break; | |
5f4273c7 | 16116 | |
037e8744 JB |
16117 | case NS_FFRR: /* case 15 (fmsrr). */ |
16118 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
477330fc | 16119 | _("VFP registers must be adjacent")); |
037e8744 JB |
16120 | inst.operands[1] = inst.operands[2]; |
16121 | inst.operands[2] = inst.operands[3]; | |
16122 | inst.operands[0].imm = 2; | |
16123 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
16124 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 16125 | break; |
5f4273c7 | 16126 | |
4c261dff NC |
16127 | case NS_NULL: |
16128 | /* neon_select_shape has determined that the instruction | |
16129 | shape is wrong and has already set the error message. */ | |
16130 | break; | |
16131 | ||
5287ad62 JB |
16132 | default: |
16133 | abort (); | |
16134 | } | |
16135 | } | |
16136 | ||
16137 | static void | |
16138 | do_neon_rshift_round_imm (void) | |
16139 | { | |
037e8744 | 16140 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
16141 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
16142 | int imm = inst.operands[2].imm; | |
16143 | ||
16144 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
16145 | if (imm == 0) | |
16146 | { | |
16147 | inst.operands[2].present = 0; | |
16148 | do_neon_mov (); | |
16149 | return; | |
16150 | } | |
16151 | ||
16152 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 16153 | _("immediate out of range for shift")); |
037e8744 | 16154 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 16155 | et.size - imm); |
5287ad62 JB |
16156 | } |
16157 | ||
16158 | static void | |
16159 | do_neon_movl (void) | |
16160 | { | |
16161 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
16162 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
16163 | unsigned sizebits = et.size >> 3; | |
16164 | inst.instruction |= sizebits << 19; | |
16165 | neon_two_same (0, et.type == NT_unsigned, -1); | |
16166 | } | |
16167 | ||
16168 | static void | |
16169 | do_neon_trn (void) | |
16170 | { | |
037e8744 | 16171 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16172 | struct neon_type_el et = neon_check_type (2, rs, |
16173 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 16174 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 16175 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16176 | } |
16177 | ||
16178 | static void | |
16179 | do_neon_zip_uzp (void) | |
16180 | { | |
037e8744 | 16181 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16182 | struct neon_type_el et = neon_check_type (2, rs, |
16183 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
16184 | if (rs == NS_DD && et.size == 32) | |
16185 | { | |
16186 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
16187 | inst.instruction = N_MNEM_vtrn; | |
16188 | do_neon_trn (); | |
16189 | return; | |
16190 | } | |
037e8744 | 16191 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16192 | } |
16193 | ||
16194 | static void | |
16195 | do_neon_sat_abs_neg (void) | |
16196 | { | |
037e8744 | 16197 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16198 | struct neon_type_el et = neon_check_type (2, rs, |
16199 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16200 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16201 | } |
16202 | ||
16203 | static void | |
16204 | do_neon_pair_long (void) | |
16205 | { | |
037e8744 | 16206 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16207 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
16208 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
16209 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 16210 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16211 | } |
16212 | ||
16213 | static void | |
16214 | do_neon_recip_est (void) | |
16215 | { | |
037e8744 | 16216 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16217 | struct neon_type_el et = neon_check_type (2, rs, |
16218 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
16219 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 16220 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16221 | } |
16222 | ||
16223 | static void | |
16224 | do_neon_cls (void) | |
16225 | { | |
037e8744 | 16226 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16227 | struct neon_type_el et = neon_check_type (2, rs, |
16228 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16229 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16230 | } |
16231 | ||
16232 | static void | |
16233 | do_neon_clz (void) | |
16234 | { | |
037e8744 | 16235 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16236 | struct neon_type_el et = neon_check_type (2, rs, |
16237 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 16238 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16239 | } |
16240 | ||
16241 | static void | |
16242 | do_neon_cnt (void) | |
16243 | { | |
037e8744 | 16244 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16245 | struct neon_type_el et = neon_check_type (2, rs, |
16246 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 16247 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16248 | } |
16249 | ||
16250 | static void | |
16251 | do_neon_swp (void) | |
16252 | { | |
037e8744 JB |
16253 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
16254 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
16255 | } |
16256 | ||
16257 | static void | |
16258 | do_neon_tbl_tbx (void) | |
16259 | { | |
16260 | unsigned listlenbits; | |
dcbf9037 | 16261 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 16262 | |
5287ad62 JB |
16263 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
16264 | { | |
dcbf9037 | 16265 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
16266 | return; |
16267 | } | |
5f4273c7 | 16268 | |
5287ad62 JB |
16269 | listlenbits = inst.operands[1].imm - 1; |
16270 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16271 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16272 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16273 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16274 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16275 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16276 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 16277 | |
88714cb8 | 16278 | neon_dp_fixup (&inst); |
5287ad62 JB |
16279 | } |
16280 | ||
16281 | static void | |
16282 | do_neon_ldm_stm (void) | |
16283 | { | |
16284 | /* P, U and L bits are part of bitmask. */ | |
16285 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
16286 | unsigned offsetbits = inst.operands[1].imm * 2; | |
16287 | ||
037e8744 JB |
16288 | if (inst.operands[1].issingle) |
16289 | { | |
16290 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
16291 | return; | |
16292 | } | |
16293 | ||
5287ad62 | 16294 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 16295 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
16296 | |
16297 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
16298 | _("register list must contain at least 1 and at most 16 " |
16299 | "registers")); | |
5287ad62 JB |
16300 | |
16301 | inst.instruction |= inst.operands[0].reg << 16; | |
16302 | inst.instruction |= inst.operands[0].writeback << 21; | |
16303 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
16304 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
16305 | ||
16306 | inst.instruction |= offsetbits; | |
5f4273c7 | 16307 | |
037e8744 | 16308 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
16309 | } |
16310 | ||
16311 | static void | |
16312 | do_neon_ldr_str (void) | |
16313 | { | |
5287ad62 | 16314 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 16315 | |
6844b2c2 MGD |
16316 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
16317 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 16318 | if (!is_ldr |
6844b2c2 | 16319 | && inst.operands[1].reg == REG_PC |
ba86b375 | 16320 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 16321 | { |
94dcf8bf | 16322 | if (thumb_mode) |
6844b2c2 | 16323 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf | 16324 | else if (warn_on_deprecated) |
5c3696f8 | 16325 | as_tsktsk (_("Use of PC here is deprecated")); |
6844b2c2 MGD |
16326 | } |
16327 | ||
037e8744 JB |
16328 | if (inst.operands[0].issingle) |
16329 | { | |
cd2f129f | 16330 | if (is_ldr) |
477330fc | 16331 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 16332 | else |
477330fc | 16333 | do_vfp_nsyn_opcode ("fsts"); |
5287ad62 JB |
16334 | } |
16335 | else | |
5287ad62 | 16336 | { |
cd2f129f | 16337 | if (is_ldr) |
477330fc | 16338 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 16339 | else |
477330fc | 16340 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 16341 | } |
5287ad62 JB |
16342 | } |
16343 | ||
16344 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
16345 | instructions. */ | |
16346 | ||
16347 | static void | |
16348 | do_neon_ld_st_interleave (void) | |
16349 | { | |
037e8744 | 16350 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 16351 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
16352 | unsigned alignbits = 0; |
16353 | unsigned idx; | |
16354 | /* The bits in this table go: | |
16355 | 0: register stride of one (0) or two (1) | |
16356 | 1,2: register list length, minus one (1, 2, 3, 4). | |
16357 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
16358 | We use -1 for invalid entries. */ | |
16359 | const int typetable[] = | |
16360 | { | |
16361 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
16362 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
16363 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
16364 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
16365 | }; | |
16366 | int typebits; | |
16367 | ||
dcbf9037 JB |
16368 | if (et.type == NT_invtype) |
16369 | return; | |
16370 | ||
5287ad62 JB |
16371 | if (inst.operands[1].immisalign) |
16372 | switch (inst.operands[1].imm >> 8) | |
16373 | { | |
16374 | case 64: alignbits = 1; break; | |
16375 | case 128: | |
477330fc | 16376 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 16377 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
16378 | goto bad_alignment; |
16379 | alignbits = 2; | |
16380 | break; | |
5287ad62 | 16381 | case 256: |
477330fc RM |
16382 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
16383 | goto bad_alignment; | |
16384 | alignbits = 3; | |
16385 | break; | |
5287ad62 JB |
16386 | default: |
16387 | bad_alignment: | |
477330fc RM |
16388 | first_error (_("bad alignment")); |
16389 | return; | |
5287ad62 JB |
16390 | } |
16391 | ||
16392 | inst.instruction |= alignbits << 4; | |
16393 | inst.instruction |= neon_logbits (et.size) << 6; | |
16394 | ||
16395 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
16396 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
16397 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
16398 | up the right value for "type" in a table based on this value and the given | |
16399 | list style, then stick it back. */ | |
16400 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 16401 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
16402 | |
16403 | typebits = typetable[idx]; | |
5f4273c7 | 16404 | |
5287ad62 | 16405 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c WN |
16406 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
16407 | _("bad element type for instruction")); | |
5287ad62 JB |
16408 | |
16409 | inst.instruction &= ~0xf00; | |
16410 | inst.instruction |= typebits << 8; | |
16411 | } | |
16412 | ||
16413 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
16414 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
16415 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
16416 | values, terminated with -1. */ | |
16417 | ||
16418 | static int | |
16419 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
16420 | { | |
16421 | va_list ap; | |
16422 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 16423 | |
5287ad62 JB |
16424 | if (!inst.operands[1].immisalign) |
16425 | { | |
16426 | *do_align = 0; | |
16427 | return SUCCESS; | |
16428 | } | |
5f4273c7 | 16429 | |
5287ad62 JB |
16430 | va_start (ap, do_align); |
16431 | ||
16432 | do | |
16433 | { | |
16434 | thissize = va_arg (ap, int); | |
16435 | if (thissize == -1) | |
477330fc | 16436 | break; |
5287ad62 JB |
16437 | thisalign = va_arg (ap, int); |
16438 | ||
16439 | if (size == thissize && align == thisalign) | |
477330fc | 16440 | result = SUCCESS; |
5287ad62 JB |
16441 | } |
16442 | while (result != SUCCESS); | |
16443 | ||
16444 | va_end (ap); | |
16445 | ||
16446 | if (result == SUCCESS) | |
16447 | *do_align = 1; | |
16448 | else | |
dcbf9037 | 16449 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 16450 | |
5287ad62 JB |
16451 | return result; |
16452 | } | |
16453 | ||
16454 | static void | |
16455 | do_neon_ld_st_lane (void) | |
16456 | { | |
037e8744 | 16457 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16458 | int align_good, do_align = 0; |
16459 | int logsize = neon_logbits (et.size); | |
16460 | int align = inst.operands[1].imm >> 8; | |
16461 | int n = (inst.instruction >> 8) & 3; | |
16462 | int max_el = 64 / et.size; | |
5f4273c7 | 16463 | |
dcbf9037 JB |
16464 | if (et.type == NT_invtype) |
16465 | return; | |
5f4273c7 | 16466 | |
5287ad62 | 16467 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 16468 | _("bad list length")); |
5287ad62 | 16469 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 16470 | _("scalar index out of range")); |
5287ad62 | 16471 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
16472 | && et.size == 8, |
16473 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 16474 | |
5287ad62 JB |
16475 | switch (n) |
16476 | { | |
16477 | case 0: /* VLD1 / VST1. */ | |
16478 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
477330fc | 16479 | 32, 32, -1); |
5287ad62 | 16480 | if (align_good == FAIL) |
477330fc | 16481 | return; |
5287ad62 | 16482 | if (do_align) |
477330fc RM |
16483 | { |
16484 | unsigned alignbits = 0; | |
16485 | switch (et.size) | |
16486 | { | |
16487 | case 16: alignbits = 0x1; break; | |
16488 | case 32: alignbits = 0x3; break; | |
16489 | default: ; | |
16490 | } | |
16491 | inst.instruction |= alignbits << 4; | |
16492 | } | |
5287ad62 JB |
16493 | break; |
16494 | ||
16495 | case 1: /* VLD2 / VST2. */ | |
16496 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
477330fc | 16497 | 32, 64, -1); |
5287ad62 | 16498 | if (align_good == FAIL) |
477330fc | 16499 | return; |
5287ad62 | 16500 | if (do_align) |
477330fc | 16501 | inst.instruction |= 1 << 4; |
5287ad62 JB |
16502 | break; |
16503 | ||
16504 | case 2: /* VLD3 / VST3. */ | |
16505 | constraint (inst.operands[1].immisalign, | |
477330fc | 16506 | _("can't use alignment with this instruction")); |
5287ad62 JB |
16507 | break; |
16508 | ||
16509 | case 3: /* VLD4 / VST4. */ | |
16510 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
477330fc | 16511 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 16512 | if (align_good == FAIL) |
477330fc | 16513 | return; |
5287ad62 | 16514 | if (do_align) |
477330fc RM |
16515 | { |
16516 | unsigned alignbits = 0; | |
16517 | switch (et.size) | |
16518 | { | |
16519 | case 8: alignbits = 0x1; break; | |
16520 | case 16: alignbits = 0x1; break; | |
16521 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
16522 | default: ; | |
16523 | } | |
16524 | inst.instruction |= alignbits << 4; | |
16525 | } | |
5287ad62 JB |
16526 | break; |
16527 | ||
16528 | default: ; | |
16529 | } | |
16530 | ||
16531 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
16532 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16533 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 16534 | |
5287ad62 JB |
16535 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
16536 | inst.instruction |= logsize << 10; | |
16537 | } | |
16538 | ||
16539 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
16540 | ||
16541 | static void | |
16542 | do_neon_ld_dup (void) | |
16543 | { | |
037e8744 | 16544 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16545 | int align_good, do_align = 0; |
16546 | ||
dcbf9037 JB |
16547 | if (et.type == NT_invtype) |
16548 | return; | |
16549 | ||
5287ad62 JB |
16550 | switch ((inst.instruction >> 8) & 3) |
16551 | { | |
16552 | case 0: /* VLD1. */ | |
9c2799c2 | 16553 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 16554 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
477330fc | 16555 | &do_align, 16, 16, 32, 32, -1); |
5287ad62 | 16556 | if (align_good == FAIL) |
477330fc | 16557 | return; |
5287ad62 | 16558 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
16559 | { |
16560 | case 1: break; | |
16561 | case 2: inst.instruction |= 1 << 5; break; | |
16562 | default: first_error (_("bad list length")); return; | |
16563 | } | |
5287ad62 JB |
16564 | inst.instruction |= neon_logbits (et.size) << 6; |
16565 | break; | |
16566 | ||
16567 | case 1: /* VLD2. */ | |
16568 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
477330fc | 16569 | &do_align, 8, 16, 16, 32, 32, 64, -1); |
5287ad62 | 16570 | if (align_good == FAIL) |
477330fc | 16571 | return; |
5287ad62 | 16572 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 16573 | _("bad list length")); |
5287ad62 | 16574 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16575 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16576 | inst.instruction |= neon_logbits (et.size) << 6; |
16577 | break; | |
16578 | ||
16579 | case 2: /* VLD3. */ | |
16580 | constraint (inst.operands[1].immisalign, | |
477330fc | 16581 | _("can't use alignment with this instruction")); |
5287ad62 | 16582 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 16583 | _("bad list length")); |
5287ad62 | 16584 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16585 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16586 | inst.instruction |= neon_logbits (et.size) << 6; |
16587 | break; | |
16588 | ||
16589 | case 3: /* VLD4. */ | |
16590 | { | |
477330fc RM |
16591 | int align = inst.operands[1].imm >> 8; |
16592 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
16593 | 16, 64, 32, 64, 32, 128, -1); | |
16594 | if (align_good == FAIL) | |
16595 | return; | |
16596 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
16597 | _("bad list length")); | |
16598 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16599 | inst.instruction |= 1 << 5; | |
16600 | if (et.size == 32 && align == 128) | |
16601 | inst.instruction |= 0x3 << 6; | |
16602 | else | |
16603 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
16604 | } |
16605 | break; | |
16606 | ||
16607 | default: ; | |
16608 | } | |
16609 | ||
16610 | inst.instruction |= do_align << 4; | |
16611 | } | |
16612 | ||
16613 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
16614 | apart from bits [11:4]. */ | |
16615 | ||
16616 | static void | |
16617 | do_neon_ldx_stx (void) | |
16618 | { | |
b1a769ed DG |
16619 | if (inst.operands[1].isreg) |
16620 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
16621 | ||
5287ad62 JB |
16622 | switch (NEON_LANE (inst.operands[0].imm)) |
16623 | { | |
16624 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 16625 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
16626 | do_neon_ld_st_interleave (); |
16627 | break; | |
5f4273c7 | 16628 | |
5287ad62 | 16629 | case NEON_ALL_LANES: |
88714cb8 | 16630 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
16631 | if (inst.instruction == N_INV) |
16632 | { | |
16633 | first_error ("only loads support such operands"); | |
16634 | break; | |
16635 | } | |
5287ad62 JB |
16636 | do_neon_ld_dup (); |
16637 | break; | |
5f4273c7 | 16638 | |
5287ad62 | 16639 | default: |
88714cb8 | 16640 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
16641 | do_neon_ld_st_lane (); |
16642 | } | |
16643 | ||
16644 | /* L bit comes from bit mask. */ | |
16645 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16646 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16647 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 16648 | |
5287ad62 JB |
16649 | if (inst.operands[1].postind) |
16650 | { | |
16651 | int postreg = inst.operands[1].imm & 0xf; | |
16652 | constraint (!inst.operands[1].immisreg, | |
477330fc | 16653 | _("post-index must be a register")); |
5287ad62 | 16654 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 16655 | _("bad register for post-index")); |
5287ad62 JB |
16656 | inst.instruction |= postreg; |
16657 | } | |
4f2374c7 | 16658 | else |
5287ad62 | 16659 | { |
4f2374c7 WN |
16660 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
16661 | constraint (inst.reloc.exp.X_op != O_constant | |
16662 | || inst.reloc.exp.X_add_number != 0, | |
16663 | BAD_ADDR_MODE); | |
16664 | ||
16665 | if (inst.operands[1].writeback) | |
16666 | { | |
16667 | inst.instruction |= 0xd; | |
16668 | } | |
16669 | else | |
16670 | inst.instruction |= 0xf; | |
5287ad62 | 16671 | } |
5f4273c7 | 16672 | |
5287ad62 JB |
16673 | if (thumb_mode) |
16674 | inst.instruction |= 0xf9000000; | |
16675 | else | |
16676 | inst.instruction |= 0xf4000000; | |
16677 | } | |
33399f07 MGD |
16678 | |
16679 | /* FP v8. */ | |
16680 | static void | |
16681 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
16682 | { | |
a715796b TG |
16683 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
16684 | D register operands. */ | |
16685 | if (neon_shape_class[rs] == SC_DOUBLE) | |
16686 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16687 | _(BAD_FPU)); | |
16688 | ||
33399f07 MGD |
16689 | NEON_ENCODE (FPV8, inst); |
16690 | ||
16691 | if (rs == NS_FFF) | |
16692 | do_vfp_sp_dyadic (); | |
16693 | else | |
16694 | do_vfp_dp_rd_rn_rm (); | |
16695 | ||
16696 | if (rs == NS_DDD) | |
16697 | inst.instruction |= 0x100; | |
16698 | ||
16699 | inst.instruction |= 0xf0000000; | |
16700 | } | |
16701 | ||
16702 | static void | |
16703 | do_vsel (void) | |
16704 | { | |
16705 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16706 | ||
16707 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
16708 | first_error (_("invalid instruction shape")); | |
16709 | } | |
16710 | ||
73924fbc MGD |
16711 | static void |
16712 | do_vmaxnm (void) | |
16713 | { | |
16714 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16715 | ||
16716 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
16717 | return; | |
16718 | ||
16719 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16720 | return; | |
16721 | ||
16722 | neon_dyadic_misc (NT_untyped, N_F32, 0); | |
16723 | } | |
16724 | ||
30bdf752 MGD |
16725 | static void |
16726 | do_vrint_1 (enum neon_cvt_mode mode) | |
16727 | { | |
16728 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL); | |
16729 | struct neon_type_el et; | |
16730 | ||
16731 | if (rs == NS_NULL) | |
16732 | return; | |
16733 | ||
a715796b TG |
16734 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
16735 | D register operands. */ | |
16736 | if (neon_shape_class[rs] == SC_DOUBLE) | |
16737 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16738 | _(BAD_FPU)); | |
16739 | ||
30bdf752 MGD |
16740 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
16741 | if (et.type != NT_invtype) | |
16742 | { | |
16743 | /* VFP encodings. */ | |
16744 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
16745 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
16746 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16747 | ||
16748 | NEON_ENCODE (FPV8, inst); | |
16749 | if (rs == NS_FF) | |
16750 | do_vfp_sp_monadic (); | |
16751 | else | |
16752 | do_vfp_dp_rd_rm (); | |
16753 | ||
16754 | switch (mode) | |
16755 | { | |
16756 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
16757 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
16758 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
16759 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
16760 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
16761 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
16762 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
16763 | default: abort (); | |
16764 | } | |
16765 | ||
16766 | inst.instruction |= (rs == NS_DD) << 8; | |
16767 | do_vfp_cond_or_thumb (); | |
16768 | } | |
16769 | else | |
16770 | { | |
16771 | /* Neon encodings (or something broken...). */ | |
16772 | inst.error = NULL; | |
16773 | et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY); | |
16774 | ||
16775 | if (et.type == NT_invtype) | |
16776 | return; | |
16777 | ||
16778 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16779 | NEON_ENCODE (FLOAT, inst); | |
16780 | ||
16781 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16782 | return; | |
16783 | ||
16784 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16785 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16786 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16787 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16788 | inst.instruction |= neon_quad (rs) << 6; | |
16789 | switch (mode) | |
16790 | { | |
16791 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
16792 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
16793 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
16794 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
16795 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
16796 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
16797 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
16798 | default: abort (); | |
16799 | } | |
16800 | ||
16801 | if (thumb_mode) | |
16802 | inst.instruction |= 0xfc000000; | |
16803 | else | |
16804 | inst.instruction |= 0xf0000000; | |
16805 | } | |
16806 | } | |
16807 | ||
16808 | static void | |
16809 | do_vrintx (void) | |
16810 | { | |
16811 | do_vrint_1 (neon_cvt_mode_x); | |
16812 | } | |
16813 | ||
16814 | static void | |
16815 | do_vrintz (void) | |
16816 | { | |
16817 | do_vrint_1 (neon_cvt_mode_z); | |
16818 | } | |
16819 | ||
16820 | static void | |
16821 | do_vrintr (void) | |
16822 | { | |
16823 | do_vrint_1 (neon_cvt_mode_r); | |
16824 | } | |
16825 | ||
16826 | static void | |
16827 | do_vrinta (void) | |
16828 | { | |
16829 | do_vrint_1 (neon_cvt_mode_a); | |
16830 | } | |
16831 | ||
16832 | static void | |
16833 | do_vrintn (void) | |
16834 | { | |
16835 | do_vrint_1 (neon_cvt_mode_n); | |
16836 | } | |
16837 | ||
16838 | static void | |
16839 | do_vrintp (void) | |
16840 | { | |
16841 | do_vrint_1 (neon_cvt_mode_p); | |
16842 | } | |
16843 | ||
16844 | static void | |
16845 | do_vrintm (void) | |
16846 | { | |
16847 | do_vrint_1 (neon_cvt_mode_m); | |
16848 | } | |
16849 | ||
91ff7894 MGD |
16850 | /* Crypto v1 instructions. */ |
16851 | static void | |
16852 | do_crypto_2op_1 (unsigned elttype, int op) | |
16853 | { | |
16854 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16855 | ||
16856 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
16857 | == NT_invtype) | |
16858 | return; | |
16859 | ||
16860 | inst.error = NULL; | |
16861 | ||
16862 | NEON_ENCODE (INTEGER, inst); | |
16863 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16864 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16865 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16866 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16867 | if (op != -1) | |
16868 | inst.instruction |= op << 6; | |
16869 | ||
16870 | if (thumb_mode) | |
16871 | inst.instruction |= 0xfc000000; | |
16872 | else | |
16873 | inst.instruction |= 0xf0000000; | |
16874 | } | |
16875 | ||
48adcd8e MGD |
16876 | static void |
16877 | do_crypto_3op_1 (int u, int op) | |
16878 | { | |
16879 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16880 | ||
16881 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
16882 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
16883 | return; | |
16884 | ||
16885 | inst.error = NULL; | |
16886 | ||
16887 | NEON_ENCODE (INTEGER, inst); | |
16888 | neon_three_same (1, u, 8 << op); | |
16889 | } | |
16890 | ||
91ff7894 MGD |
16891 | static void |
16892 | do_aese (void) | |
16893 | { | |
16894 | do_crypto_2op_1 (N_8, 0); | |
16895 | } | |
16896 | ||
16897 | static void | |
16898 | do_aesd (void) | |
16899 | { | |
16900 | do_crypto_2op_1 (N_8, 1); | |
16901 | } | |
16902 | ||
16903 | static void | |
16904 | do_aesmc (void) | |
16905 | { | |
16906 | do_crypto_2op_1 (N_8, 2); | |
16907 | } | |
16908 | ||
16909 | static void | |
16910 | do_aesimc (void) | |
16911 | { | |
16912 | do_crypto_2op_1 (N_8, 3); | |
16913 | } | |
16914 | ||
48adcd8e MGD |
16915 | static void |
16916 | do_sha1c (void) | |
16917 | { | |
16918 | do_crypto_3op_1 (0, 0); | |
16919 | } | |
16920 | ||
16921 | static void | |
16922 | do_sha1p (void) | |
16923 | { | |
16924 | do_crypto_3op_1 (0, 1); | |
16925 | } | |
16926 | ||
16927 | static void | |
16928 | do_sha1m (void) | |
16929 | { | |
16930 | do_crypto_3op_1 (0, 2); | |
16931 | } | |
16932 | ||
16933 | static void | |
16934 | do_sha1su0 (void) | |
16935 | { | |
16936 | do_crypto_3op_1 (0, 3); | |
16937 | } | |
91ff7894 | 16938 | |
48adcd8e MGD |
16939 | static void |
16940 | do_sha256h (void) | |
16941 | { | |
16942 | do_crypto_3op_1 (1, 0); | |
16943 | } | |
16944 | ||
16945 | static void | |
16946 | do_sha256h2 (void) | |
16947 | { | |
16948 | do_crypto_3op_1 (1, 1); | |
16949 | } | |
16950 | ||
16951 | static void | |
16952 | do_sha256su1 (void) | |
16953 | { | |
16954 | do_crypto_3op_1 (1, 2); | |
16955 | } | |
3c9017d2 MGD |
16956 | |
16957 | static void | |
16958 | do_sha1h (void) | |
16959 | { | |
16960 | do_crypto_2op_1 (N_32, -1); | |
16961 | } | |
16962 | ||
16963 | static void | |
16964 | do_sha1su1 (void) | |
16965 | { | |
16966 | do_crypto_2op_1 (N_32, 0); | |
16967 | } | |
16968 | ||
16969 | static void | |
16970 | do_sha256su0 (void) | |
16971 | { | |
16972 | do_crypto_2op_1 (N_32, 1); | |
16973 | } | |
dd5181d5 KT |
16974 | |
16975 | static void | |
16976 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
16977 | { | |
16978 | unsigned int Rd = inst.operands[0].reg; | |
16979 | unsigned int Rn = inst.operands[1].reg; | |
16980 | unsigned int Rm = inst.operands[2].reg; | |
16981 | ||
16982 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16983 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); | |
16984 | inst.instruction |= LOW4 (Rn) << 16; | |
16985 | inst.instruction |= LOW4 (Rm); | |
16986 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
16987 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
16988 | ||
16989 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
16990 | as_warn (UNPRED_REG ("r15")); | |
16991 | if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP)) | |
16992 | as_warn (UNPRED_REG ("r13")); | |
16993 | } | |
16994 | ||
16995 | static void | |
16996 | do_crc32b (void) | |
16997 | { | |
16998 | do_crc32_1 (0, 0); | |
16999 | } | |
17000 | ||
17001 | static void | |
17002 | do_crc32h (void) | |
17003 | { | |
17004 | do_crc32_1 (0, 1); | |
17005 | } | |
17006 | ||
17007 | static void | |
17008 | do_crc32w (void) | |
17009 | { | |
17010 | do_crc32_1 (0, 2); | |
17011 | } | |
17012 | ||
17013 | static void | |
17014 | do_crc32cb (void) | |
17015 | { | |
17016 | do_crc32_1 (1, 0); | |
17017 | } | |
17018 | ||
17019 | static void | |
17020 | do_crc32ch (void) | |
17021 | { | |
17022 | do_crc32_1 (1, 1); | |
17023 | } | |
17024 | ||
17025 | static void | |
17026 | do_crc32cw (void) | |
17027 | { | |
17028 | do_crc32_1 (1, 2); | |
17029 | } | |
17030 | ||
5287ad62 JB |
17031 | \f |
17032 | /* Overall per-instruction processing. */ | |
17033 | ||
17034 | /* We need to be able to fix up arbitrary expressions in some statements. | |
17035 | This is so that we can handle symbols that are an arbitrary distance from | |
17036 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
17037 | which returns part of an address in a form which will be valid for | |
17038 | a data instruction. We do this by pushing the expression into a symbol | |
17039 | in the expr_section, and creating a fix for that. */ | |
17040 | ||
17041 | static void | |
17042 | fix_new_arm (fragS * frag, | |
17043 | int where, | |
17044 | short int size, | |
17045 | expressionS * exp, | |
17046 | int pc_rel, | |
17047 | int reloc) | |
17048 | { | |
17049 | fixS * new_fix; | |
17050 | ||
17051 | switch (exp->X_op) | |
17052 | { | |
17053 | case O_constant: | |
6e7ce2cd PB |
17054 | if (pc_rel) |
17055 | { | |
17056 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
17057 | refer to in the object file. Unfortunately for us, gas's |
17058 | generic expression parsing will already have folded out | |
17059 | any use of .set foo/.type foo %function that may have | |
17060 | been used to set type information of the target location, | |
17061 | that's being specified symbolically. We have to presume | |
17062 | the user knows what they are doing. */ | |
6e7ce2cd PB |
17063 | char name[16 + 8]; |
17064 | symbolS *symbol; | |
17065 | ||
17066 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
17067 | ||
17068 | symbol = symbol_find_or_make (name); | |
17069 | S_SET_SEGMENT (symbol, absolute_section); | |
17070 | symbol_set_frag (symbol, &zero_address_frag); | |
17071 | S_SET_VALUE (symbol, exp->X_add_number); | |
17072 | exp->X_op = O_symbol; | |
17073 | exp->X_add_symbol = symbol; | |
17074 | exp->X_add_number = 0; | |
17075 | } | |
17076 | /* FALLTHROUGH */ | |
5287ad62 JB |
17077 | case O_symbol: |
17078 | case O_add: | |
17079 | case O_subtract: | |
21d799b5 | 17080 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 17081 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
17082 | break; |
17083 | ||
17084 | default: | |
21d799b5 | 17085 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 17086 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
17087 | break; |
17088 | } | |
17089 | ||
17090 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
17091 | instruction. */ | |
17092 | new_fix->tc_fix_data = thumb_mode; | |
17093 | } | |
17094 | ||
17095 | /* Create a frg for an instruction requiring relaxation. */ | |
17096 | static void | |
17097 | output_relax_insn (void) | |
17098 | { | |
17099 | char * to; | |
17100 | symbolS *sym; | |
0110f2b8 PB |
17101 | int offset; |
17102 | ||
6e1cb1a6 PB |
17103 | /* The size of the instruction is unknown, so tie the debug info to the |
17104 | start of the instruction. */ | |
17105 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 17106 | |
0110f2b8 PB |
17107 | switch (inst.reloc.exp.X_op) |
17108 | { | |
17109 | case O_symbol: | |
17110 | sym = inst.reloc.exp.X_add_symbol; | |
17111 | offset = inst.reloc.exp.X_add_number; | |
17112 | break; | |
17113 | case O_constant: | |
17114 | sym = NULL; | |
17115 | offset = inst.reloc.exp.X_add_number; | |
17116 | break; | |
17117 | default: | |
17118 | sym = make_expr_symbol (&inst.reloc.exp); | |
17119 | offset = 0; | |
17120 | break; | |
17121 | } | |
17122 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
17123 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
17124 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
17125 | } |
17126 | ||
17127 | /* Write a 32-bit thumb instruction to buf. */ | |
17128 | static void | |
17129 | put_thumb32_insn (char * buf, unsigned long insn) | |
17130 | { | |
17131 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
17132 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
17133 | } | |
17134 | ||
b99bd4ef | 17135 | static void |
c19d1205 | 17136 | output_inst (const char * str) |
b99bd4ef | 17137 | { |
c19d1205 | 17138 | char * to = NULL; |
b99bd4ef | 17139 | |
c19d1205 | 17140 | if (inst.error) |
b99bd4ef | 17141 | { |
c19d1205 | 17142 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
17143 | return; |
17144 | } | |
5f4273c7 NC |
17145 | if (inst.relax) |
17146 | { | |
17147 | output_relax_insn (); | |
0110f2b8 | 17148 | return; |
5f4273c7 | 17149 | } |
c19d1205 ZW |
17150 | if (inst.size == 0) |
17151 | return; | |
b99bd4ef | 17152 | |
c19d1205 | 17153 | to = frag_more (inst.size); |
8dc2430f NC |
17154 | /* PR 9814: Record the thumb mode into the current frag so that we know |
17155 | what type of NOP padding to use, if necessary. We override any previous | |
17156 | setting so that if the mode has changed then the NOPS that we use will | |
17157 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 17158 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
17159 | |
17160 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 17161 | { |
9c2799c2 | 17162 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 17163 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 17164 | } |
c19d1205 | 17165 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 17166 | { |
9c2799c2 | 17167 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
17168 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
17169 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 17170 | } |
c19d1205 ZW |
17171 | else |
17172 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 17173 | |
c19d1205 ZW |
17174 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
17175 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
17176 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
17177 | inst.reloc.type); | |
b99bd4ef | 17178 | |
c19d1205 | 17179 | dwarf2_emit_insn (inst.size); |
c19d1205 | 17180 | } |
b99bd4ef | 17181 | |
e07e6e58 NC |
17182 | static char * |
17183 | output_it_inst (int cond, int mask, char * to) | |
17184 | { | |
17185 | unsigned long instruction = 0xbf00; | |
17186 | ||
17187 | mask &= 0xf; | |
17188 | instruction |= mask; | |
17189 | instruction |= cond << 4; | |
17190 | ||
17191 | if (to == NULL) | |
17192 | { | |
17193 | to = frag_more (2); | |
17194 | #ifdef OBJ_ELF | |
17195 | dwarf2_emit_insn (2); | |
17196 | #endif | |
17197 | } | |
17198 | ||
17199 | md_number_to_chars (to, instruction, 2); | |
17200 | ||
17201 | return to; | |
17202 | } | |
17203 | ||
c19d1205 ZW |
17204 | /* Tag values used in struct asm_opcode's tag field. */ |
17205 | enum opcode_tag | |
17206 | { | |
17207 | OT_unconditional, /* Instruction cannot be conditionalized. | |
17208 | The ARM condition field is still 0xE. */ | |
17209 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
17210 | and carries 0xF in its ARM condition field. */ | |
17211 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 | 17212 | OT_csuffixF, /* Some forms of the instruction take a conditional |
477330fc RM |
17213 | suffix, others place 0xF where the condition field |
17214 | would be. */ | |
c19d1205 ZW |
17215 | OT_cinfix3, /* Instruction takes a conditional infix, |
17216 | beginning at character index 3. (In | |
17217 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
17218 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
17219 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
17220 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
17221 | character index 3, even in unified mode. Used for | |
17222 | legacy instructions where suffix and infix forms | |
17223 | may be ambiguous. */ | |
c19d1205 | 17224 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 17225 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
17226 | OT_odd_infix_unc, /* This is the unconditional variant of an |
17227 | instruction that takes a conditional infix | |
17228 | at an unusual position. In unified mode, | |
17229 | this variant will accept a suffix. */ | |
17230 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
17231 | are the conditional variants of instructions that | |
17232 | take conditional infixes in unusual positions. | |
17233 | The infix appears at character index | |
17234 | (tag - OT_odd_infix_0). These are not accepted | |
17235 | in unified mode. */ | |
17236 | }; | |
b99bd4ef | 17237 | |
c19d1205 ZW |
17238 | /* Subroutine of md_assemble, responsible for looking up the primary |
17239 | opcode from the mnemonic the user wrote. STR points to the | |
17240 | beginning of the mnemonic. | |
17241 | ||
17242 | This is not simply a hash table lookup, because of conditional | |
17243 | variants. Most instructions have conditional variants, which are | |
17244 | expressed with a _conditional affix_ to the mnemonic. If we were | |
17245 | to encode each conditional variant as a literal string in the opcode | |
17246 | table, it would have approximately 20,000 entries. | |
17247 | ||
17248 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
17249 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
17250 | instructions take the affix as an infix, notably the s-variants of | |
17251 | the arithmetic instructions. Of those instructions, all but six | |
17252 | have the infix appear after the third character of the mnemonic. | |
17253 | ||
17254 | Accordingly, the algorithm for looking up primary opcodes given | |
17255 | an identifier is: | |
17256 | ||
17257 | 1. Look up the identifier in the opcode table. | |
17258 | If we find a match, go to step U. | |
17259 | ||
17260 | 2. Look up the last two characters of the identifier in the | |
17261 | conditions table. If we find a match, look up the first N-2 | |
17262 | characters of the identifier in the opcode table. If we | |
17263 | find a match, go to step CE. | |
17264 | ||
17265 | 3. Look up the fourth and fifth characters of the identifier in | |
17266 | the conditions table. If we find a match, extract those | |
17267 | characters from the identifier, and look up the remaining | |
17268 | characters in the opcode table. If we find a match, go | |
17269 | to step CM. | |
17270 | ||
17271 | 4. Fail. | |
17272 | ||
17273 | U. Examine the tag field of the opcode structure, in case this is | |
17274 | one of the six instructions with its conditional infix in an | |
17275 | unusual place. If it is, the tag tells us where to find the | |
17276 | infix; look it up in the conditions table and set inst.cond | |
17277 | accordingly. Otherwise, this is an unconditional instruction. | |
17278 | Again set inst.cond accordingly. Return the opcode structure. | |
17279 | ||
17280 | CE. Examine the tag field to make sure this is an instruction that | |
17281 | should receive a conditional suffix. If it is not, fail. | |
17282 | Otherwise, set inst.cond from the suffix we already looked up, | |
17283 | and return the opcode structure. | |
17284 | ||
17285 | CM. Examine the tag field to make sure this is an instruction that | |
17286 | should receive a conditional infix after the third character. | |
17287 | If it is not, fail. Otherwise, undo the edits to the current | |
17288 | line of input and proceed as for case CE. */ | |
17289 | ||
17290 | static const struct asm_opcode * | |
17291 | opcode_lookup (char **str) | |
17292 | { | |
17293 | char *end, *base; | |
17294 | char *affix; | |
17295 | const struct asm_opcode *opcode; | |
17296 | const struct asm_cond *cond; | |
e3cb604e | 17297 | char save[2]; |
c19d1205 ZW |
17298 | |
17299 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 17300 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 17301 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 17302 | if (*end == ' ' || *end == '.') |
c19d1205 | 17303 | break; |
b99bd4ef | 17304 | |
c19d1205 | 17305 | if (end == base) |
c921be7d | 17306 | return NULL; |
b99bd4ef | 17307 | |
5287ad62 | 17308 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 17309 | if (end[0] == '.') |
b99bd4ef | 17310 | { |
5287ad62 | 17311 | int offset = 2; |
5f4273c7 | 17312 | |
267d2029 | 17313 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 17314 | use. */ |
267d2029 | 17315 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 17316 | inst.size_req = 4; |
267d2029 | 17317 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
17318 | inst.size_req = 2; |
17319 | else | |
477330fc | 17320 | offset = 0; |
5287ad62 JB |
17321 | |
17322 | inst.vectype.elems = 0; | |
17323 | ||
17324 | *str = end + offset; | |
b99bd4ef | 17325 | |
5f4273c7 | 17326 | if (end[offset] == '.') |
5287ad62 | 17327 | { |
267d2029 | 17328 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
17329 | non-unified ARM syntax mode). */ |
17330 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 17331 | return NULL; |
477330fc | 17332 | } |
5287ad62 | 17333 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 17334 | return NULL; |
b99bd4ef | 17335 | } |
c19d1205 ZW |
17336 | else |
17337 | *str = end; | |
b99bd4ef | 17338 | |
c19d1205 | 17339 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 17340 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17341 | end - base); |
c19d1205 | 17342 | if (opcode) |
b99bd4ef | 17343 | { |
c19d1205 ZW |
17344 | /* step U */ |
17345 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 17346 | { |
c19d1205 ZW |
17347 | inst.cond = COND_ALWAYS; |
17348 | return opcode; | |
b99bd4ef | 17349 | } |
b99bd4ef | 17350 | |
278df34e | 17351 | if (warn_on_deprecated && unified_syntax) |
5c3696f8 | 17352 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 | 17353 | affix = base + (opcode->tag - OT_odd_infix_0); |
21d799b5 | 17354 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 17355 | gas_assert (cond); |
b99bd4ef | 17356 | |
c19d1205 ZW |
17357 | inst.cond = cond->value; |
17358 | return opcode; | |
17359 | } | |
b99bd4ef | 17360 | |
c19d1205 ZW |
17361 | /* Cannot have a conditional suffix on a mnemonic of less than two |
17362 | characters. */ | |
17363 | if (end - base < 3) | |
c921be7d | 17364 | return NULL; |
b99bd4ef | 17365 | |
c19d1205 ZW |
17366 | /* Look for suffixed mnemonic. */ |
17367 | affix = end - 2; | |
21d799b5 NC |
17368 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
17369 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
477330fc | 17370 | affix - base); |
c19d1205 ZW |
17371 | if (opcode && cond) |
17372 | { | |
17373 | /* step CE */ | |
17374 | switch (opcode->tag) | |
17375 | { | |
e3cb604e PB |
17376 | case OT_cinfix3_legacy: |
17377 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
17378 | break; | |
17379 | ||
c19d1205 | 17380 | case OT_cinfix3: |
088fa78e | 17381 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
17382 | case OT_odd_infix_unc: |
17383 | if (!unified_syntax) | |
e3cb604e | 17384 | return 0; |
c19d1205 ZW |
17385 | /* else fall through */ |
17386 | ||
17387 | case OT_csuffix: | |
477330fc | 17388 | case OT_csuffixF: |
c19d1205 ZW |
17389 | case OT_csuf_or_in3: |
17390 | inst.cond = cond->value; | |
17391 | return opcode; | |
17392 | ||
17393 | case OT_unconditional: | |
17394 | case OT_unconditionalF: | |
dfa9f0d5 | 17395 | if (thumb_mode) |
c921be7d | 17396 | inst.cond = cond->value; |
dfa9f0d5 PB |
17397 | else |
17398 | { | |
c921be7d | 17399 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
17400 | inst.error = BAD_COND; |
17401 | inst.cond = COND_ALWAYS; | |
17402 | } | |
c19d1205 | 17403 | return opcode; |
b99bd4ef | 17404 | |
c19d1205 | 17405 | default: |
c921be7d | 17406 | return NULL; |
c19d1205 ZW |
17407 | } |
17408 | } | |
b99bd4ef | 17409 | |
c19d1205 ZW |
17410 | /* Cannot have a usual-position infix on a mnemonic of less than |
17411 | six characters (five would be a suffix). */ | |
17412 | if (end - base < 6) | |
c921be7d | 17413 | return NULL; |
b99bd4ef | 17414 | |
c19d1205 ZW |
17415 | /* Look for infixed mnemonic in the usual position. */ |
17416 | affix = base + 3; | |
21d799b5 | 17417 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 17418 | if (!cond) |
c921be7d | 17419 | return NULL; |
e3cb604e PB |
17420 | |
17421 | memcpy (save, affix, 2); | |
17422 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 17423 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17424 | (end - base) - 2); |
e3cb604e PB |
17425 | memmove (affix + 2, affix, (end - affix) - 2); |
17426 | memcpy (affix, save, 2); | |
17427 | ||
088fa78e KH |
17428 | if (opcode |
17429 | && (opcode->tag == OT_cinfix3 | |
17430 | || opcode->tag == OT_cinfix3_deprecated | |
17431 | || opcode->tag == OT_csuf_or_in3 | |
17432 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 17433 | { |
c921be7d | 17434 | /* Step CM. */ |
278df34e | 17435 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
17436 | && (opcode->tag == OT_cinfix3 |
17437 | || opcode->tag == OT_cinfix3_deprecated)) | |
5c3696f8 | 17438 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 ZW |
17439 | |
17440 | inst.cond = cond->value; | |
17441 | return opcode; | |
b99bd4ef NC |
17442 | } |
17443 | ||
c921be7d | 17444 | return NULL; |
b99bd4ef NC |
17445 | } |
17446 | ||
e07e6e58 NC |
17447 | /* This function generates an initial IT instruction, leaving its block |
17448 | virtually open for the new instructions. Eventually, | |
17449 | the mask will be updated by now_it_add_mask () each time | |
17450 | a new instruction needs to be included in the IT block. | |
17451 | Finally, the block is closed with close_automatic_it_block (). | |
17452 | The block closure can be requested either from md_assemble (), | |
17453 | a tencode (), or due to a label hook. */ | |
17454 | ||
17455 | static void | |
17456 | new_automatic_it_block (int cond) | |
17457 | { | |
17458 | now_it.state = AUTOMATIC_IT_BLOCK; | |
17459 | now_it.mask = 0x18; | |
17460 | now_it.cc = cond; | |
17461 | now_it.block_length = 1; | |
cd000bff | 17462 | mapping_state (MAP_THUMB); |
e07e6e58 | 17463 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
17464 | now_it.warn_deprecated = FALSE; |
17465 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
17466 | } |
17467 | ||
17468 | /* Close an automatic IT block. | |
17469 | See comments in new_automatic_it_block (). */ | |
17470 | ||
17471 | static void | |
17472 | close_automatic_it_block (void) | |
17473 | { | |
17474 | now_it.mask = 0x10; | |
17475 | now_it.block_length = 0; | |
17476 | } | |
17477 | ||
17478 | /* Update the mask of the current automatically-generated IT | |
17479 | instruction. See comments in new_automatic_it_block (). */ | |
17480 | ||
17481 | static void | |
17482 | now_it_add_mask (int cond) | |
17483 | { | |
17484 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
17485 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 17486 | | ((bitvalue) << (nbit))) |
e07e6e58 | 17487 | const int resulting_bit = (cond & 1); |
c921be7d | 17488 | |
e07e6e58 NC |
17489 | now_it.mask &= 0xf; |
17490 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
477330fc RM |
17491 | resulting_bit, |
17492 | (5 - now_it.block_length)); | |
e07e6e58 | 17493 | now_it.mask = SET_BIT_VALUE (now_it.mask, |
477330fc RM |
17494 | 1, |
17495 | ((5 - now_it.block_length) - 1) ); | |
e07e6e58 NC |
17496 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); |
17497 | ||
17498 | #undef CLEAR_BIT | |
17499 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
17500 | } |
17501 | ||
17502 | /* The IT blocks handling machinery is accessed through the these functions: | |
17503 | it_fsm_pre_encode () from md_assemble () | |
17504 | set_it_insn_type () optional, from the tencode functions | |
17505 | set_it_insn_type_last () ditto | |
17506 | in_it_block () ditto | |
17507 | it_fsm_post_encode () from md_assemble () | |
17508 | force_automatic_it_block_close () from label habdling functions | |
17509 | ||
17510 | Rationale: | |
17511 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
17512 | initializing the IT insn type with a generic initial value depending |
17513 | on the inst.condition. | |
e07e6e58 | 17514 | 2) During the tencode function, two things may happen: |
477330fc RM |
17515 | a) The tencode function overrides the IT insn type by |
17516 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
17517 | b) The tencode function queries the IT block state by | |
17518 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
17519 | ||
17520 | Both set_it_insn_type and in_it_block run the internal FSM state | |
17521 | handling function (handle_it_state), because: a) setting the IT insn | |
17522 | type may incur in an invalid state (exiting the function), | |
17523 | and b) querying the state requires the FSM to be updated. | |
17524 | Specifically we want to avoid creating an IT block for conditional | |
17525 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
17526 | determine whether an IT block is required until the tencode () routine | |
17527 | has decided what type of instruction this actually it. | |
17528 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
17529 | set_it_insn_type has to be called first. | |
17530 | ||
17531 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
17532 | determines the insn IT type depending on the inst.cond code. | |
17533 | When a tencode () routine encodes an instruction that can be | |
17534 | either outside an IT block, or, in the case of being inside, has to be | |
17535 | the last one, set_it_insn_type_last () will determine the proper | |
17536 | IT instruction type based on the inst.cond code. Otherwise, | |
17537 | set_it_insn_type can be called for overriding that logic or | |
17538 | for covering other cases. | |
17539 | ||
17540 | Calling handle_it_state () may not transition the IT block state to | |
17541 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
17542 | still queried. Instead, if the FSM determines that the state should | |
17543 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
17544 | after the tencode () function: that's what it_fsm_post_encode () does. | |
17545 | ||
17546 | Since in_it_block () calls the state handling function to get an | |
17547 | updated state, an error may occur (due to invalid insns combination). | |
17548 | In that case, inst.error is set. | |
17549 | Therefore, inst.error has to be checked after the execution of | |
17550 | the tencode () routine. | |
e07e6e58 NC |
17551 | |
17552 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc RM |
17553 | any pending state change (if any) that didn't take place in |
17554 | handle_it_state () as explained above. */ | |
e07e6e58 NC |
17555 | |
17556 | static void | |
17557 | it_fsm_pre_encode (void) | |
17558 | { | |
17559 | if (inst.cond != COND_ALWAYS) | |
17560 | inst.it_insn_type = INSIDE_IT_INSN; | |
17561 | else | |
17562 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
17563 | ||
17564 | now_it.state_handled = 0; | |
17565 | } | |
17566 | ||
17567 | /* IT state FSM handling function. */ | |
17568 | ||
17569 | static int | |
17570 | handle_it_state (void) | |
17571 | { | |
17572 | now_it.state_handled = 1; | |
5a01bb1d | 17573 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
17574 | |
17575 | switch (now_it.state) | |
17576 | { | |
17577 | case OUTSIDE_IT_BLOCK: | |
17578 | switch (inst.it_insn_type) | |
17579 | { | |
17580 | case OUTSIDE_IT_INSN: | |
17581 | break; | |
17582 | ||
17583 | case INSIDE_IT_INSN: | |
17584 | case INSIDE_IT_LAST_INSN: | |
17585 | if (thumb_mode == 0) | |
17586 | { | |
c921be7d | 17587 | if (unified_syntax |
e07e6e58 NC |
17588 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
17589 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
17590 | " for Thumb.")); | |
17591 | } | |
17592 | else | |
17593 | { | |
17594 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
17595 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
17596 | { | |
17597 | /* Automatically generate the IT instruction. */ | |
17598 | new_automatic_it_block (inst.cond); | |
17599 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
17600 | close_automatic_it_block (); | |
17601 | } | |
17602 | else | |
17603 | { | |
17604 | inst.error = BAD_OUT_IT; | |
17605 | return FAIL; | |
17606 | } | |
17607 | } | |
17608 | break; | |
17609 | ||
17610 | case IF_INSIDE_IT_LAST_INSN: | |
17611 | case NEUTRAL_IT_INSN: | |
17612 | break; | |
17613 | ||
17614 | case IT_INSN: | |
17615 | now_it.state = MANUAL_IT_BLOCK; | |
17616 | now_it.block_length = 0; | |
17617 | break; | |
17618 | } | |
17619 | break; | |
17620 | ||
17621 | case AUTOMATIC_IT_BLOCK: | |
17622 | /* Three things may happen now: | |
17623 | a) We should increment current it block size; | |
17624 | b) We should close current it block (closing insn or 4 insns); | |
17625 | c) We should close current it block and start a new one (due | |
17626 | to incompatible conditions or | |
17627 | 4 insns-length block reached). */ | |
17628 | ||
17629 | switch (inst.it_insn_type) | |
17630 | { | |
17631 | case OUTSIDE_IT_INSN: | |
17632 | /* The closure of the block shall happen immediatelly, | |
17633 | so any in_it_block () call reports the block as closed. */ | |
17634 | force_automatic_it_block_close (); | |
17635 | break; | |
17636 | ||
17637 | case INSIDE_IT_INSN: | |
17638 | case INSIDE_IT_LAST_INSN: | |
17639 | case IF_INSIDE_IT_LAST_INSN: | |
17640 | now_it.block_length++; | |
17641 | ||
17642 | if (now_it.block_length > 4 | |
17643 | || !now_it_compatible (inst.cond)) | |
17644 | { | |
17645 | force_automatic_it_block_close (); | |
17646 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
17647 | new_automatic_it_block (inst.cond); | |
17648 | } | |
17649 | else | |
17650 | { | |
5a01bb1d | 17651 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17652 | now_it_add_mask (inst.cond); |
17653 | } | |
17654 | ||
17655 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
17656 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
17657 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
17658 | close_automatic_it_block (); | |
17659 | break; | |
17660 | ||
17661 | case NEUTRAL_IT_INSN: | |
17662 | now_it.block_length++; | |
5a01bb1d | 17663 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17664 | |
17665 | if (now_it.block_length > 4) | |
17666 | force_automatic_it_block_close (); | |
17667 | else | |
17668 | now_it_add_mask (now_it.cc & 1); | |
17669 | break; | |
17670 | ||
17671 | case IT_INSN: | |
17672 | close_automatic_it_block (); | |
17673 | now_it.state = MANUAL_IT_BLOCK; | |
17674 | break; | |
17675 | } | |
17676 | break; | |
17677 | ||
17678 | case MANUAL_IT_BLOCK: | |
17679 | { | |
17680 | /* Check conditional suffixes. */ | |
17681 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
17682 | int is_last; | |
17683 | now_it.mask <<= 1; | |
17684 | now_it.mask &= 0x1f; | |
17685 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 17686 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17687 | |
17688 | switch (inst.it_insn_type) | |
17689 | { | |
17690 | case OUTSIDE_IT_INSN: | |
17691 | inst.error = BAD_NOT_IT; | |
17692 | return FAIL; | |
17693 | ||
17694 | case INSIDE_IT_INSN: | |
17695 | if (cond != inst.cond) | |
17696 | { | |
17697 | inst.error = BAD_IT_COND; | |
17698 | return FAIL; | |
17699 | } | |
17700 | break; | |
17701 | ||
17702 | case INSIDE_IT_LAST_INSN: | |
17703 | case IF_INSIDE_IT_LAST_INSN: | |
17704 | if (cond != inst.cond) | |
17705 | { | |
17706 | inst.error = BAD_IT_COND; | |
17707 | return FAIL; | |
17708 | } | |
17709 | if (!is_last) | |
17710 | { | |
17711 | inst.error = BAD_BRANCH; | |
17712 | return FAIL; | |
17713 | } | |
17714 | break; | |
17715 | ||
17716 | case NEUTRAL_IT_INSN: | |
17717 | /* The BKPT instruction is unconditional even in an IT block. */ | |
17718 | break; | |
17719 | ||
17720 | case IT_INSN: | |
17721 | inst.error = BAD_IT_IT; | |
17722 | return FAIL; | |
17723 | } | |
17724 | } | |
17725 | break; | |
17726 | } | |
17727 | ||
17728 | return SUCCESS; | |
17729 | } | |
17730 | ||
5a01bb1d MGD |
17731 | struct depr_insn_mask |
17732 | { | |
17733 | unsigned long pattern; | |
17734 | unsigned long mask; | |
17735 | const char* description; | |
17736 | }; | |
17737 | ||
17738 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
17739 | ARMv8. */ | |
17740 | static const struct depr_insn_mask depr_it_insns[] = { | |
17741 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
17742 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
17743 | { 0xa000, 0xb800, N_("ADR") }, | |
17744 | { 0x4800, 0xf800, N_("Literal loads") }, | |
17745 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
17746 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
17747 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
17748 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
17749 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
17750 | { 0, 0, NULL } |
17751 | }; | |
17752 | ||
e07e6e58 NC |
17753 | static void |
17754 | it_fsm_post_encode (void) | |
17755 | { | |
17756 | int is_last; | |
17757 | ||
17758 | if (!now_it.state_handled) | |
17759 | handle_it_state (); | |
17760 | ||
5a01bb1d MGD |
17761 | if (now_it.insn_cond |
17762 | && !now_it.warn_deprecated | |
17763 | && warn_on_deprecated | |
17764 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
17765 | { | |
17766 | if (inst.instruction >= 0x10000) | |
17767 | { | |
5c3696f8 | 17768 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
5a01bb1d MGD |
17769 | "deprecated in ARMv8")); |
17770 | now_it.warn_deprecated = TRUE; | |
17771 | } | |
17772 | else | |
17773 | { | |
17774 | const struct depr_insn_mask *p = depr_it_insns; | |
17775 | ||
17776 | while (p->mask != 0) | |
17777 | { | |
17778 | if ((inst.instruction & p->mask) == p->pattern) | |
17779 | { | |
5c3696f8 | 17780 | as_tsktsk (_("IT blocks containing 16-bit Thumb instructions " |
5a01bb1d MGD |
17781 | "of the following class are deprecated in ARMv8: " |
17782 | "%s"), p->description); | |
17783 | now_it.warn_deprecated = TRUE; | |
17784 | break; | |
17785 | } | |
17786 | ||
17787 | ++p; | |
17788 | } | |
17789 | } | |
17790 | ||
17791 | if (now_it.block_length > 1) | |
17792 | { | |
5c3696f8 | 17793 | as_tsktsk (_("IT blocks containing more than one conditional " |
0a8897c7 | 17794 | "instruction are deprecated in ARMv8")); |
5a01bb1d MGD |
17795 | now_it.warn_deprecated = TRUE; |
17796 | } | |
17797 | } | |
17798 | ||
e07e6e58 NC |
17799 | is_last = (now_it.mask == 0x10); |
17800 | if (is_last) | |
17801 | { | |
17802 | now_it.state = OUTSIDE_IT_BLOCK; | |
17803 | now_it.mask = 0; | |
17804 | } | |
17805 | } | |
17806 | ||
17807 | static void | |
17808 | force_automatic_it_block_close (void) | |
17809 | { | |
17810 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
17811 | { | |
17812 | close_automatic_it_block (); | |
17813 | now_it.state = OUTSIDE_IT_BLOCK; | |
17814 | now_it.mask = 0; | |
17815 | } | |
17816 | } | |
17817 | ||
17818 | static int | |
17819 | in_it_block (void) | |
17820 | { | |
17821 | if (!now_it.state_handled) | |
17822 | handle_it_state (); | |
17823 | ||
17824 | return now_it.state != OUTSIDE_IT_BLOCK; | |
17825 | } | |
17826 | ||
c19d1205 ZW |
17827 | void |
17828 | md_assemble (char *str) | |
b99bd4ef | 17829 | { |
c19d1205 ZW |
17830 | char *p = str; |
17831 | const struct asm_opcode * opcode; | |
b99bd4ef | 17832 | |
c19d1205 ZW |
17833 | /* Align the previous label if needed. */ |
17834 | if (last_label_seen != NULL) | |
b99bd4ef | 17835 | { |
c19d1205 ZW |
17836 | symbol_set_frag (last_label_seen, frag_now); |
17837 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
17838 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
17839 | } |
17840 | ||
c19d1205 ZW |
17841 | memset (&inst, '\0', sizeof (inst)); |
17842 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 17843 | |
c19d1205 ZW |
17844 | opcode = opcode_lookup (&p); |
17845 | if (!opcode) | |
b99bd4ef | 17846 | { |
c19d1205 | 17847 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 17848 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 17849 | if (! create_register_alias (str, p) |
477330fc | 17850 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 17851 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 17852 | |
b99bd4ef NC |
17853 | return; |
17854 | } | |
17855 | ||
278df34e | 17856 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
5c3696f8 | 17857 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
088fa78e | 17858 | |
037e8744 JB |
17859 | /* The value which unconditional instructions should have in place of the |
17860 | condition field. */ | |
17861 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
17862 | ||
c19d1205 | 17863 | if (thumb_mode) |
b99bd4ef | 17864 | { |
e74cfd16 | 17865 | arm_feature_set variant; |
8f06b2d8 PB |
17866 | |
17867 | variant = cpu_variant; | |
17868 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
17869 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
17870 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 17871 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
17872 | if (!opcode->tvariant |
17873 | || (thumb_mode == 1 | |
17874 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 17875 | { |
bf3eeda7 | 17876 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
17877 | return; |
17878 | } | |
c19d1205 ZW |
17879 | if (inst.cond != COND_ALWAYS && !unified_syntax |
17880 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 17881 | { |
c19d1205 | 17882 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
17883 | return; |
17884 | } | |
17885 | ||
752d5da4 | 17886 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 17887 | { |
7e806470 | 17888 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
17889 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
17890 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
17891 | { | |
17892 | /* Two things are addressed here. | |
17893 | 1) Implicit require narrow instructions on Thumb-1. | |
17894 | This avoids relaxation accidentally introducing Thumb-2 | |
17895 | instructions. | |
17896 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
17897 | if (inst.size_req == 0) | |
17898 | inst.size_req = 2; | |
17899 | else if (inst.size_req == 4) | |
17900 | { | |
bf3eeda7 | 17901 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
17902 | return; |
17903 | } | |
17904 | } | |
076d447c PB |
17905 | } |
17906 | ||
c19d1205 ZW |
17907 | inst.instruction = opcode->tvalue; |
17908 | ||
5be8be5d | 17909 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc RM |
17910 | { |
17911 | /* Prepare the it_insn_type for those encodings that don't set | |
17912 | it. */ | |
17913 | it_fsm_pre_encode (); | |
c19d1205 | 17914 | |
477330fc | 17915 | opcode->tencode (); |
e07e6e58 | 17916 | |
477330fc RM |
17917 | it_fsm_post_encode (); |
17918 | } | |
e27ec89e | 17919 | |
0110f2b8 | 17920 | if (!(inst.error || inst.relax)) |
b99bd4ef | 17921 | { |
9c2799c2 | 17922 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
17923 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
17924 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 17925 | { |
c19d1205 | 17926 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
17927 | return; |
17928 | } | |
17929 | } | |
076d447c PB |
17930 | |
17931 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 17932 | instruction. */ |
9c2799c2 | 17933 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 17934 | |
e74cfd16 PB |
17935 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17936 | *opcode->tvariant); | |
ee065d83 | 17937 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 17938 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 17939 | anything other than bl/blx and v6-M instructions. |
3cfdb781 TG |
17940 | The impact of relaxable instructions will be considered later after we |
17941 | finish all relaxation. */ | |
17942 | if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) | |
e07e6e58 NC |
17943 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
17944 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
17945 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17946 | arm_ext_v6t2); | |
cd000bff | 17947 | |
88714cb8 DG |
17948 | check_neon_suffixes; |
17949 | ||
cd000bff | 17950 | if (!inst.error) |
c877a2f2 NC |
17951 | { |
17952 | mapping_state (MAP_THUMB); | |
17953 | } | |
c19d1205 | 17954 | } |
3e9e4fcf | 17955 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 17956 | { |
845b51d6 PB |
17957 | bfd_boolean is_bx; |
17958 | ||
17959 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
17960 | is_bx = (opcode->aencode == do_bx); | |
17961 | ||
c19d1205 | 17962 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
17963 | if (!(is_bx && fix_v4bx) |
17964 | && !(opcode->avariant && | |
17965 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 17966 | { |
bf3eeda7 | 17967 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 17968 | return; |
b99bd4ef | 17969 | } |
c19d1205 | 17970 | if (inst.size_req) |
b99bd4ef | 17971 | { |
c19d1205 ZW |
17972 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
17973 | return; | |
b99bd4ef NC |
17974 | } |
17975 | ||
c19d1205 ZW |
17976 | inst.instruction = opcode->avalue; |
17977 | if (opcode->tag == OT_unconditionalF) | |
17978 | inst.instruction |= 0xF << 28; | |
17979 | else | |
17980 | inst.instruction |= inst.cond << 28; | |
17981 | inst.size = INSN_SIZE; | |
5be8be5d | 17982 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
17983 | { |
17984 | it_fsm_pre_encode (); | |
17985 | opcode->aencode (); | |
17986 | it_fsm_post_encode (); | |
17987 | } | |
ee065d83 | 17988 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 17989 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 17990 | if (is_bx) |
e74cfd16 | 17991 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 17992 | else |
e74cfd16 PB |
17993 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
17994 | *opcode->avariant); | |
88714cb8 DG |
17995 | |
17996 | check_neon_suffixes; | |
17997 | ||
cd000bff | 17998 | if (!inst.error) |
c877a2f2 NC |
17999 | { |
18000 | mapping_state (MAP_ARM); | |
18001 | } | |
b99bd4ef | 18002 | } |
3e9e4fcf JB |
18003 | else |
18004 | { | |
18005 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
18006 | "-- `%s'"), str); | |
18007 | return; | |
18008 | } | |
c19d1205 ZW |
18009 | output_inst (str); |
18010 | } | |
b99bd4ef | 18011 | |
e07e6e58 NC |
18012 | static void |
18013 | check_it_blocks_finished (void) | |
18014 | { | |
18015 | #ifdef OBJ_ELF | |
18016 | asection *sect; | |
18017 | ||
18018 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
18019 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
18020 | == MANUAL_IT_BLOCK) | |
18021 | { | |
18022 | as_warn (_("section '%s' finished with an open IT block."), | |
18023 | sect->name); | |
18024 | } | |
18025 | #else | |
18026 | if (now_it.state == MANUAL_IT_BLOCK) | |
18027 | as_warn (_("file finished with an open IT block.")); | |
18028 | #endif | |
18029 | } | |
18030 | ||
c19d1205 ZW |
18031 | /* Various frobbings of labels and their addresses. */ |
18032 | ||
18033 | void | |
18034 | arm_start_line_hook (void) | |
18035 | { | |
18036 | last_label_seen = NULL; | |
b99bd4ef NC |
18037 | } |
18038 | ||
c19d1205 ZW |
18039 | void |
18040 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 18041 | { |
c19d1205 | 18042 | last_label_seen = sym; |
b99bd4ef | 18043 | |
c19d1205 | 18044 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 18045 | |
c19d1205 ZW |
18046 | #if defined OBJ_COFF || defined OBJ_ELF |
18047 | ARM_SET_INTERWORK (sym, support_interwork); | |
18048 | #endif | |
b99bd4ef | 18049 | |
e07e6e58 NC |
18050 | force_automatic_it_block_close (); |
18051 | ||
5f4273c7 | 18052 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
18053 | as Thumb functions. This is because these labels, whilst |
18054 | they exist inside Thumb code, are not the entry points for | |
18055 | possible ARM->Thumb calls. Also, these labels can be used | |
18056 | as part of a computed goto or switch statement. eg gcc | |
18057 | can generate code that looks like this: | |
b99bd4ef | 18058 | |
c19d1205 ZW |
18059 | ldr r2, [pc, .Laaa] |
18060 | lsl r3, r3, #2 | |
18061 | ldr r2, [r3, r2] | |
18062 | mov pc, r2 | |
b99bd4ef | 18063 | |
c19d1205 ZW |
18064 | .Lbbb: .word .Lxxx |
18065 | .Lccc: .word .Lyyy | |
18066 | ..etc... | |
18067 | .Laaa: .word Lbbb | |
b99bd4ef | 18068 | |
c19d1205 ZW |
18069 | The first instruction loads the address of the jump table. |
18070 | The second instruction converts a table index into a byte offset. | |
18071 | The third instruction gets the jump address out of the table. | |
18072 | The fourth instruction performs the jump. | |
b99bd4ef | 18073 | |
c19d1205 ZW |
18074 | If the address stored at .Laaa is that of a symbol which has the |
18075 | Thumb_Func bit set, then the linker will arrange for this address | |
18076 | to have the bottom bit set, which in turn would mean that the | |
18077 | address computation performed by the third instruction would end | |
18078 | up with the bottom bit set. Since the ARM is capable of unaligned | |
18079 | word loads, the instruction would then load the incorrect address | |
18080 | out of the jump table, and chaos would ensue. */ | |
18081 | if (label_is_thumb_function_name | |
18082 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
18083 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 18084 | { |
c19d1205 ZW |
18085 | /* When the address of a Thumb function is taken the bottom |
18086 | bit of that address should be set. This will allow | |
18087 | interworking between Arm and Thumb functions to work | |
18088 | correctly. */ | |
b99bd4ef | 18089 | |
c19d1205 | 18090 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 18091 | |
c19d1205 | 18092 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 18093 | } |
07a53e5c | 18094 | |
07a53e5c | 18095 | dwarf2_emit_label (sym); |
b99bd4ef NC |
18096 | } |
18097 | ||
c921be7d | 18098 | bfd_boolean |
c19d1205 | 18099 | arm_data_in_code (void) |
b99bd4ef | 18100 | { |
c19d1205 | 18101 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 18102 | { |
c19d1205 ZW |
18103 | *input_line_pointer = '/'; |
18104 | input_line_pointer += 5; | |
18105 | *input_line_pointer = 0; | |
c921be7d | 18106 | return TRUE; |
b99bd4ef NC |
18107 | } |
18108 | ||
c921be7d | 18109 | return FALSE; |
b99bd4ef NC |
18110 | } |
18111 | ||
c19d1205 ZW |
18112 | char * |
18113 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 18114 | { |
c19d1205 | 18115 | int len; |
b99bd4ef | 18116 | |
c19d1205 ZW |
18117 | if (thumb_mode && (len = strlen (name)) > 5 |
18118 | && streq (name + len - 5, "/data")) | |
18119 | *(name + len - 5) = 0; | |
b99bd4ef | 18120 | |
c19d1205 | 18121 | return name; |
b99bd4ef | 18122 | } |
c19d1205 ZW |
18123 | \f |
18124 | /* Table of all register names defined by default. The user can | |
18125 | define additional names with .req. Note that all register names | |
18126 | should appear in both upper and lowercase variants. Some registers | |
18127 | also have mixed-case names. */ | |
b99bd4ef | 18128 | |
dcbf9037 | 18129 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 18130 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 18131 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
18132 | #define REGSET(p,t) \ |
18133 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
18134 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
18135 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
18136 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
18137 | #define REGSETH(p,t) \ |
18138 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
18139 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
18140 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
18141 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
18142 | #define REGSET2(p,t) \ | |
18143 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
18144 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
18145 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
18146 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
18147 | #define SPLRBANK(base,bank,t) \ |
18148 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
18149 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
18150 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
18151 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
18152 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
18153 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 18154 | |
c19d1205 | 18155 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 18156 | { |
c19d1205 ZW |
18157 | /* ARM integer registers. */ |
18158 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 18159 | |
c19d1205 ZW |
18160 | /* ATPCS synonyms. */ |
18161 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
18162 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
18163 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 18164 | |
c19d1205 ZW |
18165 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
18166 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
18167 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 18168 | |
c19d1205 ZW |
18169 | /* Well-known aliases. */ |
18170 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
18171 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
18172 | ||
18173 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
18174 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
18175 | ||
18176 | /* Coprocessor numbers. */ | |
18177 | REGSET(p, CP), REGSET(P, CP), | |
18178 | ||
18179 | /* Coprocessor register numbers. The "cr" variants are for backward | |
18180 | compatibility. */ | |
18181 | REGSET(c, CN), REGSET(C, CN), | |
18182 | REGSET(cr, CN), REGSET(CR, CN), | |
18183 | ||
90ec0d68 MGD |
18184 | /* ARM banked registers. */ |
18185 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
18186 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
18187 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
18188 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
18189 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
18190 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
18191 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
18192 | ||
18193 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
18194 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
18195 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
18196 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
18197 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 18198 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
18199 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
18200 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
18201 | ||
18202 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
18203 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
18204 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
18205 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
18206 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
18207 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
18208 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 18209 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
18210 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
18211 | ||
c19d1205 ZW |
18212 | /* FPA registers. */ |
18213 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
18214 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
18215 | ||
18216 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
18217 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
18218 | ||
18219 | /* VFP SP registers. */ | |
5287ad62 JB |
18220 | REGSET(s,VFS), REGSET(S,VFS), |
18221 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
18222 | |
18223 | /* VFP DP Registers. */ | |
5287ad62 JB |
18224 | REGSET(d,VFD), REGSET(D,VFD), |
18225 | /* Extra Neon DP registers. */ | |
18226 | REGSETH(d,VFD), REGSETH(D,VFD), | |
18227 | ||
18228 | /* Neon QP registers. */ | |
18229 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
18230 | |
18231 | /* VFP control registers. */ | |
18232 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
18233 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
18234 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
18235 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
18236 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
18237 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
18238 | |
18239 | /* Maverick DSP coprocessor registers. */ | |
18240 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
18241 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
18242 | ||
18243 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
18244 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
18245 | REGDEF(dspsc,0,DSPSC), | |
18246 | ||
18247 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
18248 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
18249 | REGDEF(DSPSC,0,DSPSC), | |
18250 | ||
18251 | /* iWMMXt data registers - p0, c0-15. */ | |
18252 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
18253 | ||
18254 | /* iWMMXt control registers - p1, c0-3. */ | |
18255 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
18256 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
18257 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
18258 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
18259 | ||
18260 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
18261 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
18262 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
18263 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
18264 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
18265 | ||
18266 | /* XScale accumulator registers. */ | |
18267 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
18268 | }; | |
18269 | #undef REGDEF | |
18270 | #undef REGNUM | |
18271 | #undef REGSET | |
7ed4c4c5 | 18272 | |
c19d1205 ZW |
18273 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
18274 | within psr_required_here. */ | |
18275 | static const struct asm_psr psrs[] = | |
18276 | { | |
18277 | /* Backward compatibility notation. Note that "all" is no longer | |
18278 | truly all possible PSR bits. */ | |
18279 | {"all", PSR_c | PSR_f}, | |
18280 | {"flg", PSR_f}, | |
18281 | {"ctl", PSR_c}, | |
18282 | ||
18283 | /* Individual flags. */ | |
18284 | {"f", PSR_f}, | |
18285 | {"c", PSR_c}, | |
18286 | {"x", PSR_x}, | |
18287 | {"s", PSR_s}, | |
59b42a0d | 18288 | |
c19d1205 ZW |
18289 | /* Combinations of flags. */ |
18290 | {"fs", PSR_f | PSR_s}, | |
18291 | {"fx", PSR_f | PSR_x}, | |
18292 | {"fc", PSR_f | PSR_c}, | |
18293 | {"sf", PSR_s | PSR_f}, | |
18294 | {"sx", PSR_s | PSR_x}, | |
18295 | {"sc", PSR_s | PSR_c}, | |
18296 | {"xf", PSR_x | PSR_f}, | |
18297 | {"xs", PSR_x | PSR_s}, | |
18298 | {"xc", PSR_x | PSR_c}, | |
18299 | {"cf", PSR_c | PSR_f}, | |
18300 | {"cs", PSR_c | PSR_s}, | |
18301 | {"cx", PSR_c | PSR_x}, | |
18302 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
18303 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
18304 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
18305 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
18306 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
18307 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
18308 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
18309 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
18310 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
18311 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
18312 | {"scf", PSR_s | PSR_c | PSR_f}, | |
18313 | {"scx", PSR_s | PSR_c | PSR_x}, | |
18314 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
18315 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
18316 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
18317 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
18318 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
18319 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
18320 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
18321 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
18322 | {"csf", PSR_c | PSR_s | PSR_f}, | |
18323 | {"csx", PSR_c | PSR_s | PSR_x}, | |
18324 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
18325 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
18326 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
18327 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
18328 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
18329 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
18330 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
18331 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
18332 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
18333 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
18334 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
18335 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
18336 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
18337 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
18338 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
18339 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
18340 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
18341 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
18342 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
18343 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
18344 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
18345 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
18346 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
18347 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
18348 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
18349 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
18350 | }; | |
18351 | ||
62b3e311 PB |
18352 | /* Table of V7M psr names. */ |
18353 | static const struct asm_psr v7m_psrs[] = | |
18354 | { | |
2b744c99 PB |
18355 | {"apsr", 0 }, {"APSR", 0 }, |
18356 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
18357 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
18358 | {"psr", 3 }, {"PSR", 3 }, | |
18359 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
18360 | {"ipsr", 5 }, {"IPSR", 5 }, | |
18361 | {"epsr", 6 }, {"EPSR", 6 }, | |
18362 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
18363 | {"msp", 8 }, {"MSP", 8 }, | |
18364 | {"psp", 9 }, {"PSP", 9 }, | |
18365 | {"primask", 16}, {"PRIMASK", 16}, | |
18366 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
18367 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
18368 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
18369 | {"faultmask", 19}, {"FAULTMASK", 19}, |
18370 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
18371 | }; |
18372 | ||
c19d1205 ZW |
18373 | /* Table of all shift-in-operand names. */ |
18374 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 18375 | { |
c19d1205 ZW |
18376 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
18377 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
18378 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
18379 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
18380 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
18381 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
18382 | }; | |
b99bd4ef | 18383 | |
c19d1205 ZW |
18384 | /* Table of all explicit relocation names. */ |
18385 | #ifdef OBJ_ELF | |
18386 | static struct reloc_entry reloc_names[] = | |
18387 | { | |
18388 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
18389 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
18390 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
18391 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
18392 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
18393 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
18394 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
18395 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
18396 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
18397 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 18398 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
18399 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
18400 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 18401 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 18402 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 18403 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 18404 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
477330fc | 18405 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} |
c19d1205 ZW |
18406 | }; |
18407 | #endif | |
b99bd4ef | 18408 | |
c19d1205 ZW |
18409 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
18410 | static const struct asm_cond conds[] = | |
18411 | { | |
18412 | {"eq", 0x0}, | |
18413 | {"ne", 0x1}, | |
18414 | {"cs", 0x2}, {"hs", 0x2}, | |
18415 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
18416 | {"mi", 0x4}, | |
18417 | {"pl", 0x5}, | |
18418 | {"vs", 0x6}, | |
18419 | {"vc", 0x7}, | |
18420 | {"hi", 0x8}, | |
18421 | {"ls", 0x9}, | |
18422 | {"ge", 0xa}, | |
18423 | {"lt", 0xb}, | |
18424 | {"gt", 0xc}, | |
18425 | {"le", 0xd}, | |
18426 | {"al", 0xe} | |
18427 | }; | |
bfae80f2 | 18428 | |
e797f7e0 | 18429 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
823d2571 TG |
18430 | { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ |
18431 | { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } | |
e797f7e0 | 18432 | |
62b3e311 PB |
18433 | static struct asm_barrier_opt barrier_opt_names[] = |
18434 | { | |
e797f7e0 MGD |
18435 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
18436 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
18437 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
18438 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
18439 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
18440 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
18441 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
18442 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
18443 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
18444 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
18445 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
18446 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
18447 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
18448 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
18449 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
18450 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
18451 | }; |
18452 | ||
e797f7e0 MGD |
18453 | #undef UL_BARRIER |
18454 | ||
c19d1205 ZW |
18455 | /* Table of ARM-format instructions. */ |
18456 | ||
18457 | /* Macros for gluing together operand strings. N.B. In all cases | |
18458 | other than OPS0, the trailing OP_stop comes from default | |
18459 | zero-initialization of the unspecified elements of the array. */ | |
18460 | #define OPS0() { OP_stop, } | |
18461 | #define OPS1(a) { OP_##a, } | |
18462 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
18463 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
18464 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
18465 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
18466 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
18467 | ||
5be8be5d DG |
18468 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
18469 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
18470 | MIX_ARM_THUMB_OPERANDS macro. | |
18471 | In order to use these macros, prefix the number of operands with _ | |
18472 | e.g. _3. */ | |
18473 | #define OPS_1(a) { a, } | |
18474 | #define OPS_2(a,b) { a,b, } | |
18475 | #define OPS_3(a,b,c) { a,b,c, } | |
18476 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
18477 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
18478 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
18479 | ||
c19d1205 ZW |
18480 | /* These macros abstract out the exact format of the mnemonic table and |
18481 | save some repeated characters. */ | |
18482 | ||
18483 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
18484 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18485 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18486 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18487 | |
18488 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
18489 | a T_MNEM_xyz enumerator. */ | |
18490 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 18491 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18492 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18493 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
18494 | |
18495 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
18496 | infix after the third character. */ | |
18497 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18498 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18499 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 18500 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18501 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 18502 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18503 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18504 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 18505 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18506 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18507 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18508 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 18509 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18510 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 18511 | |
c19d1205 | 18512 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
18513 | field is still 0xE. Many of the Thumb variants can be executed |
18514 | conditionally, so this is checked separately. */ | |
c19d1205 | 18515 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18516 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18517 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18518 | |
dd5181d5 KT |
18519 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
18520 | Used by mnemonics that have very minimal differences in the encoding for | |
18521 | ARM and Thumb variants and can be handled in a common function. */ | |
18522 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
18523 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
18524 | THUMB_VARIANT, do_##en, do_##en } | |
18525 | ||
c19d1205 ZW |
18526 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
18527 | condition code field. */ | |
18528 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18529 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18530 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18531 | |
18532 | /* ARM-only variants of all the above. */ | |
6a86118a | 18533 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 18534 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
18535 | |
18536 | #define C3(mnem, op, nops, ops, ae) \ | |
18537 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
18538 | ||
e3cb604e PB |
18539 | /* Legacy mnemonics that always have conditional infix after the third |
18540 | character. */ | |
18541 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18542 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18543 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18544 | ||
8f06b2d8 PB |
18545 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
18546 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18547 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18548 | |
e3cb604e PB |
18549 | /* Legacy coprocessor instructions where conditional infix and conditional |
18550 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
18551 | not just the potentially ambiguous ones. */ | |
18552 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18553 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18554 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
18555 | ||
18556 | /* Coprocessor, takes either a suffix or a position-3 infix | |
18557 | (for an FPA corner case). */ | |
18558 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18559 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 18560 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18561 | |
6a86118a | 18562 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
18563 | { m1 #m2 m3, OPS##nops ops, \ |
18564 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
18565 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18566 | ||
18567 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
18568 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
18569 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
18570 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
18571 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
18572 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
18573 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
18574 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
18575 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
18576 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
18577 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
18578 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
18579 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
18580 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
18581 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
18582 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
18583 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
18584 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
18585 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
18586 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
18587 | |
18588 | #define UE(mnem, op, nops, ops, ae) \ | |
18589 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18590 | ||
18591 | #define UF(mnem, op, nops, ops, ae) \ | |
18592 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18593 | ||
5287ad62 JB |
18594 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
18595 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
18596 | use the same encoding function for each. */ | |
18597 | #define NUF(mnem, op, nops, ops, enc) \ | |
18598 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
18599 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
18600 | ||
18601 | /* Neon data processing, version which indirects through neon_enc_tab for | |
18602 | the various overloaded versions of opcodes. */ | |
18603 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 18604 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18605 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18606 | ||
18607 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
18608 | version. */ | |
037e8744 JB |
18609 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
18610 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
18611 | THUMB_VARIANT, do_##enc, do_##enc } |
18612 | ||
037e8744 | 18613 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18614 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18615 | |
18616 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18617 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18618 | |
5287ad62 | 18619 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 18620 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 18621 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18622 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18623 | ||
037e8744 | 18624 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18625 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18626 | |
18627 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18628 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18629 | |
c19d1205 ZW |
18630 | #define do_0 0 |
18631 | ||
c19d1205 | 18632 | static const struct asm_opcode insns[] = |
bfae80f2 | 18633 | { |
74db7efb NC |
18634 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
18635 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
18636 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
18637 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
18638 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
18639 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
18640 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
18641 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
18642 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18643 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18644 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
18645 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18646 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
18647 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
18648 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
18649 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18650 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
18651 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
18652 | |
18653 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
18654 | for setting PSR flag bits. They are obsolete in V6 and do not | |
18655 | have Thumb equivalents. */ | |
21d799b5 NC |
18656 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
18657 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
18658 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
18659 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18660 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18661 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
18662 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18663 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18664 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
18665 | ||
18666 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
18667 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
18668 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
18669 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
18670 | ||
18671 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
18672 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
18673 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
18674 | OP_RRnpc), | |
18675 | OP_ADDRGLDR),ldst, t_ldst), | |
18676 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
18677 | |
18678 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18679 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18680 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18681 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18682 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18683 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18684 | ||
18685 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
18686 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
18687 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
18688 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 18689 | |
c19d1205 | 18690 | /* Pseudo ops. */ |
21d799b5 | 18691 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 18692 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 18693 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 18694 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
18695 | |
18696 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
18697 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
18698 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
18699 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
18700 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
18701 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
18702 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
18703 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
18704 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
18705 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
18706 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
18707 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
18708 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 18709 | |
16a4cf17 | 18710 | /* These may simplify to neg. */ |
21d799b5 NC |
18711 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
18712 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 18713 | |
c921be7d NC |
18714 | #undef THUMB_VARIANT |
18715 | #define THUMB_VARIANT & arm_ext_v6 | |
18716 | ||
21d799b5 | 18717 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
18718 | |
18719 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
18720 | #undef THUMB_VARIANT |
18721 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18722 | ||
21d799b5 NC |
18723 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
18724 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
18725 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 18726 | |
5be8be5d DG |
18727 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
18728 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
18729 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
18730 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 18731 | |
21d799b5 NC |
18732 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18733 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 18734 | |
21d799b5 NC |
18735 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18736 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
18737 | |
18738 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 18739 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
18740 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
18741 | ||
18742 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
18743 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
18744 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
18745 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
18746 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
18747 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
18748 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
18749 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
18750 | ||
c921be7d NC |
18751 | #undef ARM_VARIANT |
18752 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
18753 | #undef THUMB_VARIANT | |
18754 | #define THUMB_VARIANT & arm_ext_v4t | |
18755 | ||
21d799b5 NC |
18756 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
18757 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 18758 | |
c921be7d NC |
18759 | #undef THUMB_VARIANT |
18760 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18761 | ||
21d799b5 | 18762 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
18763 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
18764 | ||
18765 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
18766 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
18767 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18768 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18769 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18770 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18771 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 18772 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 18773 | |
c921be7d NC |
18774 | #undef ARM_VARIANT |
18775 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
18776 | ||
21d799b5 | 18777 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
18778 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
18779 | ||
c921be7d NC |
18780 | #undef ARM_VARIANT |
18781 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
18782 | #undef THUMB_VARIANT | |
18783 | #define THUMB_VARIANT & arm_ext_msr | |
18784 | ||
d2cd1205 JB |
18785 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
18786 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 18787 | |
c921be7d NC |
18788 | #undef ARM_VARIANT |
18789 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
18790 | #undef THUMB_VARIANT | |
18791 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18792 | ||
21d799b5 NC |
18793 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
18794 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18795 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18796 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18797 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18798 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18799 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18800 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 18801 | |
c921be7d NC |
18802 | #undef ARM_VARIANT |
18803 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
18804 | #undef THUMB_VARIANT | |
18805 | #define THUMB_VARIANT & arm_ext_v4t | |
18806 | ||
5be8be5d DG |
18807 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18808 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18809 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18810 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
18811 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18812 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 18813 | |
c921be7d NC |
18814 | #undef ARM_VARIANT |
18815 | #define ARM_VARIANT & arm_ext_v4t_5 | |
18816 | ||
c19d1205 ZW |
18817 | /* ARM Architecture 4T. */ |
18818 | /* Note: bx (and blx) are required on V5, even if the processor does | |
18819 | not support Thumb. */ | |
21d799b5 | 18820 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 18821 | |
c921be7d NC |
18822 | #undef ARM_VARIANT |
18823 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
18824 | #undef THUMB_VARIANT | |
18825 | #define THUMB_VARIANT & arm_ext_v5t | |
18826 | ||
c19d1205 ZW |
18827 | /* Note: blx has 2 variants; the .value coded here is for |
18828 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
18829 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
18830 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 18831 | |
c921be7d NC |
18832 | #undef THUMB_VARIANT |
18833 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18834 | ||
21d799b5 NC |
18835 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
18836 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18837 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18838 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18839 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18840 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
18841 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
18842 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 18843 | |
c921be7d | 18844 | #undef ARM_VARIANT |
74db7efb NC |
18845 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
18846 | #undef THUMB_VARIANT | |
18847 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 18848 | |
21d799b5 NC |
18849 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18850 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18851 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18852 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18853 | |
21d799b5 NC |
18854 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18855 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18856 | |
21d799b5 NC |
18857 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
18858 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18859 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18860 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 18861 | |
21d799b5 NC |
18862 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18863 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18864 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18865 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18866 | |
21d799b5 NC |
18867 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18868 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18869 | |
03ee1b7f NC |
18870 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
18871 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18872 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18873 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 18874 | |
c921be7d | 18875 | #undef ARM_VARIANT |
74db7efb NC |
18876 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
18877 | #undef THUMB_VARIANT | |
18878 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 18879 | |
21d799b5 | 18880 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
18881 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
18882 | ldrd, t_ldstd), | |
18883 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
18884 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 18885 | |
21d799b5 NC |
18886 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18887 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 18888 | |
c921be7d NC |
18889 | #undef ARM_VARIANT |
18890 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
18891 | ||
21d799b5 | 18892 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 18893 | |
c921be7d NC |
18894 | #undef ARM_VARIANT |
18895 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
18896 | #undef THUMB_VARIANT | |
18897 | #define THUMB_VARIANT & arm_ext_v6 | |
18898 | ||
21d799b5 NC |
18899 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
18900 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
18901 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18902 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18903 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18904 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18905 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18906 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18907 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18908 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 18909 | |
c921be7d NC |
18910 | #undef THUMB_VARIANT |
18911 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18912 | ||
5be8be5d DG |
18913 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
18914 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
18915 | strex, t_strex), | |
21d799b5 NC |
18916 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18917 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 18918 | |
21d799b5 NC |
18919 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
18920 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 18921 | |
9e3c6df6 | 18922 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
18923 | #undef THUMB_VARIANT |
18924 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 18925 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 18926 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
18927 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
18928 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
18929 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18930 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
18931 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
18932 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18933 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 18934 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
18935 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
18936 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 18937 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18938 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18939 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18940 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18941 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 18942 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
c921be7d | 18943 | |
9e3c6df6 PB |
18944 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
18945 | #undef THUMB_VARIANT | |
18946 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
18947 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
18948 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
18949 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
18950 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18951 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18952 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18953 | /* Old name for QASX. */ |
74db7efb | 18954 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18955 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18956 | /* Old name for QSAX. */ |
74db7efb | 18957 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18958 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18959 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18960 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18961 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18962 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18963 | /* Old name for SASX. */ |
74db7efb | 18964 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18965 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18966 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18967 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18968 | /* Old name for SHASX. */ |
21d799b5 | 18969 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 18970 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18971 | /* Old name for SHSAX. */ |
21d799b5 NC |
18972 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18973 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18974 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18975 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18976 | /* Old name for SSAX. */ |
74db7efb | 18977 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18978 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18979 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18980 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18981 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18982 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18983 | /* Old name for UASX. */ |
74db7efb | 18984 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18985 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18986 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18987 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18988 | /* Old name for UHASX. */ |
21d799b5 NC |
18989 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18990 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18991 | /* Old name for UHSAX. */ |
21d799b5 NC |
18992 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18993 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18994 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18995 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18996 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18997 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18998 | /* Old name for UQASX. */ |
21d799b5 NC |
18999 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19000 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19001 | /* Old name for UQSAX. */ |
21d799b5 NC |
19002 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
19003 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19004 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19005 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19006 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 19007 | /* Old name for USAX. */ |
74db7efb | 19008 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 19009 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
19010 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
19011 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19012 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19013 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19014 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19015 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19016 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
19017 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
19018 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
19019 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19020 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19021 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19022 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19023 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19024 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19025 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19026 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
19027 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19028 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19029 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19030 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19031 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19032 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19033 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19034 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19035 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19036 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
19037 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
19038 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
19039 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
19040 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
19041 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 19042 | |
c921be7d NC |
19043 | #undef ARM_VARIANT |
19044 | #define ARM_VARIANT & arm_ext_v6k | |
19045 | #undef THUMB_VARIANT | |
19046 | #define THUMB_VARIANT & arm_ext_v6k | |
19047 | ||
21d799b5 NC |
19048 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
19049 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
19050 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
19051 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 19052 | |
c921be7d NC |
19053 | #undef THUMB_VARIANT |
19054 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
19055 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
19056 | ldrexd, t_ldrexd), | |
19057 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
19058 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 19059 | |
c921be7d NC |
19060 | #undef THUMB_VARIANT |
19061 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
19062 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
19063 | rd_rn, rd_rn), | |
19064 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
19065 | rd_rn, rd_rn), | |
19066 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 19067 | strex, t_strexbh), |
5be8be5d | 19068 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 19069 | strex, t_strexbh), |
21d799b5 | 19070 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 19071 | |
c921be7d | 19072 | #undef ARM_VARIANT |
f4c65163 | 19073 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 19074 | #undef THUMB_VARIANT |
f4c65163 | 19075 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 19076 | |
21d799b5 | 19077 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 19078 | |
90ec0d68 MGD |
19079 | #undef ARM_VARIANT |
19080 | #define ARM_VARIANT & arm_ext_virt | |
19081 | #undef THUMB_VARIANT | |
19082 | #define THUMB_VARIANT & arm_ext_virt | |
19083 | ||
19084 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
19085 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
19086 | ||
ddfded2f MW |
19087 | #undef ARM_VARIANT |
19088 | #define ARM_VARIANT & arm_ext_pan | |
19089 | #undef THUMB_VARIANT | |
19090 | #define THUMB_VARIANT & arm_ext_pan | |
19091 | ||
19092 | TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan), | |
19093 | ||
c921be7d | 19094 | #undef ARM_VARIANT |
74db7efb | 19095 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
19096 | #undef THUMB_VARIANT |
19097 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 19098 | |
21d799b5 NC |
19099 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
19100 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
19101 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
19102 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 19103 | |
21d799b5 NC |
19104 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
19105 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
19106 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
19107 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 19108 | |
5be8be5d DG |
19109 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
19110 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
19111 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
19112 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 19113 | |
bf3eeda7 | 19114 | /* Thumb-only instructions. */ |
74db7efb | 19115 | #undef ARM_VARIANT |
bf3eeda7 NS |
19116 | #define ARM_VARIANT NULL |
19117 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
19118 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
19119 | |
19120 | /* ARM does not really have an IT instruction, so always allow it. | |
19121 | The opcode is copied from Thumb in order to allow warnings in | |
19122 | -mimplicit-it=[never | arm] modes. */ | |
19123 | #undef ARM_VARIANT | |
19124 | #define ARM_VARIANT & arm_ext_v1 | |
19125 | ||
21d799b5 NC |
19126 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
19127 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
19128 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
19129 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
19130 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
19131 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
19132 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
19133 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
19134 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
19135 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
19136 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
19137 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
19138 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
19139 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
19140 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 19141 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
19142 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
19143 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 19144 | |
92e90b6e | 19145 | /* Thumb2 only instructions. */ |
c921be7d NC |
19146 | #undef ARM_VARIANT |
19147 | #define ARM_VARIANT NULL | |
92e90b6e | 19148 | |
21d799b5 NC |
19149 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
19150 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
19151 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
19152 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
19153 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
19154 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 19155 | |
eea54501 MGD |
19156 | /* Hardware division instructions. */ |
19157 | #undef ARM_VARIANT | |
19158 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
19159 | #undef THUMB_VARIANT |
19160 | #define THUMB_VARIANT & arm_ext_div | |
19161 | ||
eea54501 MGD |
19162 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
19163 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 19164 | |
7e806470 | 19165 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
19166 | #undef ARM_VARIANT |
19167 | #define ARM_VARIANT & arm_ext_barrier | |
19168 | #undef THUMB_VARIANT | |
19169 | #define THUMB_VARIANT & arm_ext_barrier | |
19170 | ||
ccb84d65 JB |
19171 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
19172 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
19173 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 19174 | |
62b3e311 | 19175 | /* ARM V7 instructions. */ |
c921be7d NC |
19176 | #undef ARM_VARIANT |
19177 | #define ARM_VARIANT & arm_ext_v7 | |
19178 | #undef THUMB_VARIANT | |
19179 | #define THUMB_VARIANT & arm_ext_v7 | |
19180 | ||
21d799b5 NC |
19181 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
19182 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 19183 | |
74db7efb | 19184 | #undef ARM_VARIANT |
60e5ef9f | 19185 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 19186 | #undef THUMB_VARIANT |
60e5ef9f MGD |
19187 | #define THUMB_VARIANT & arm_ext_mp |
19188 | ||
19189 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
19190 | ||
53c4b28b MGD |
19191 | /* AArchv8 instructions. */ |
19192 | #undef ARM_VARIANT | |
19193 | #define ARM_VARIANT & arm_ext_v8 | |
19194 | #undef THUMB_VARIANT | |
19195 | #define THUMB_VARIANT & arm_ext_v8 | |
19196 | ||
19197 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), | |
8884b720 | 19198 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), |
4b8c8c02 RE |
19199 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
19200 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 19201 | ldrexd, t_ldrexd), |
4b8c8c02 RE |
19202 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
19203 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19204 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
19205 | stlex, t_stlex), | |
19206 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 19207 | strexd, t_strexd), |
4b8c8c02 RE |
19208 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
19209 | stlex, t_stlex), | |
19210 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
19211 | stlex, t_stlex), | |
19212 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19213 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19214 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19215 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
19216 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
19217 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
53c4b28b | 19218 | |
8884b720 | 19219 | /* ARMv8 T32 only. */ |
74db7efb | 19220 | #undef ARM_VARIANT |
b79f7053 MGD |
19221 | #define ARM_VARIANT NULL |
19222 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
19223 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
19224 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
19225 | ||
33399f07 MGD |
19226 | /* FP for ARMv8. */ |
19227 | #undef ARM_VARIANT | |
a715796b | 19228 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 | 19229 | #undef THUMB_VARIANT |
a715796b | 19230 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 MGD |
19231 | |
19232 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
19233 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
19234 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
19235 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
73924fbc MGD |
19236 | nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), |
19237 | nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), | |
7e8e6784 MGD |
19238 | nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta), |
19239 | nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn), | |
19240 | nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp), | |
19241 | nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm), | |
30bdf752 MGD |
19242 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
19243 | nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), | |
19244 | nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), | |
19245 | nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), | |
19246 | nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), | |
19247 | nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), | |
19248 | nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), | |
33399f07 | 19249 | |
91ff7894 MGD |
19250 | /* Crypto v1 extensions. */ |
19251 | #undef ARM_VARIANT | |
19252 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
19253 | #undef THUMB_VARIANT | |
19254 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
19255 | ||
19256 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
19257 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
19258 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
19259 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
19260 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
19261 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
19262 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
19263 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
19264 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
19265 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
19266 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
19267 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
19268 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
19269 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 19270 | |
dd5181d5 | 19271 | #undef ARM_VARIANT |
74db7efb | 19272 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
19273 | #undef THUMB_VARIANT |
19274 | #define THUMB_VARIANT & crc_ext_armv8 | |
19275 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
19276 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
19277 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
19278 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
19279 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
19280 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
19281 | ||
c921be7d NC |
19282 | #undef ARM_VARIANT |
19283 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
19284 | #undef THUMB_VARIANT |
19285 | #define THUMB_VARIANT NULL | |
c921be7d | 19286 | |
21d799b5 NC |
19287 | cCE("wfs", e200110, 1, (RR), rd), |
19288 | cCE("rfs", e300110, 1, (RR), rd), | |
19289 | cCE("wfc", e400110, 1, (RR), rd), | |
19290 | cCE("rfc", e500110, 1, (RR), rd), | |
19291 | ||
19292 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19293 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19294 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19295 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19296 | ||
19297 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19298 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19299 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19300 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19301 | ||
19302 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
19303 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
19304 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
19305 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
19306 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
19307 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
19308 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
19309 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
19310 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
19311 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
19312 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
19313 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
19314 | ||
19315 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
19316 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
19317 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
19318 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
19319 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
19320 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
19321 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
19322 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
19323 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
19324 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
19325 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
19326 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
19327 | ||
19328 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
19329 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
19330 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
19331 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
19332 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
19333 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
19334 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
19335 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
19336 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
19337 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
19338 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
19339 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
19340 | ||
19341 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
19342 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
19343 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
19344 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
19345 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
19346 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
19347 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
19348 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
19349 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
19350 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
19351 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
19352 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
19353 | ||
19354 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
19355 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
19356 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
19357 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
19358 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
19359 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
19360 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
19361 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
19362 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
19363 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
19364 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
19365 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
19366 | ||
19367 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
19368 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
19369 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
19370 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
19371 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
19372 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
19373 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
19374 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
19375 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
19376 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
19377 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
19378 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
19379 | ||
19380 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
19381 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
19382 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
19383 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
19384 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
19385 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
19386 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
19387 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
19388 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
19389 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
19390 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
19391 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
19392 | ||
19393 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
19394 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
19395 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
19396 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
19397 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
19398 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
19399 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
19400 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
19401 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
19402 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
19403 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
19404 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
19405 | ||
19406 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
19407 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
19408 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
19409 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
19410 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
19411 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
19412 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
19413 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
19414 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
19415 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
19416 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
19417 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
19418 | ||
19419 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
19420 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
19421 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
19422 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
19423 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
19424 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
19425 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
19426 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
19427 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
19428 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
19429 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
19430 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
19431 | ||
19432 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
19433 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
19434 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
19435 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
19436 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
19437 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
19438 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
19439 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
19440 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
19441 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
19442 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
19443 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
19444 | ||
19445 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
19446 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
19447 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
19448 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
19449 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
19450 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
19451 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
19452 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
19453 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
19454 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
19455 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
19456 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
19457 | ||
19458 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
19459 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
19460 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
19461 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
19462 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
19463 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
19464 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
19465 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
19466 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
19467 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
19468 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
19469 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
19470 | ||
19471 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
19472 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
19473 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
19474 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
19475 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
19476 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
19477 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
19478 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
19479 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
19480 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
19481 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
19482 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
19483 | ||
19484 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
19485 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
19486 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
19487 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
19488 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
19489 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
19490 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
19491 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
19492 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
19493 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
19494 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
19495 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
19496 | ||
19497 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
19498 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
19499 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
19500 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
19501 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
19502 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
19503 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
19504 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
19505 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
19506 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
19507 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
19508 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
19509 | ||
19510 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19511 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19512 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19513 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19514 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19515 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19516 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19517 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19518 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19519 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19520 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19521 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19522 | ||
19523 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19524 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19525 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19526 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19527 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19528 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19529 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19530 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19531 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19532 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19533 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19534 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19535 | ||
19536 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19537 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19538 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19539 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19540 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19541 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19542 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19543 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19544 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19545 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19546 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19547 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19548 | ||
19549 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19550 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19551 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19552 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19553 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19554 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19555 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19556 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19557 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19558 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19559 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19560 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19561 | ||
19562 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19563 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19564 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19565 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19566 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19567 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19568 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19569 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19570 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19571 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19572 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19573 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19574 | ||
19575 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19576 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19577 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19578 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19579 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19580 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19581 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19582 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19583 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19584 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19585 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19586 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19587 | ||
19588 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19589 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19590 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19591 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19592 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19593 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19594 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19595 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19596 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19597 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19598 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19599 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19600 | ||
19601 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19602 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19603 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19604 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19605 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19606 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19607 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19608 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19609 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19610 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19611 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19612 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19613 | ||
19614 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19615 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19616 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19617 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19618 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19619 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19620 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19621 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19622 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19623 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19624 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19625 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19626 | ||
19627 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19628 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19629 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19630 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19631 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19632 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19633 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19634 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19635 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19636 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19637 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19638 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19639 | ||
19640 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19641 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19642 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19643 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19644 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19645 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19646 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19647 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19648 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19649 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19650 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19651 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19652 | ||
19653 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19654 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19655 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19656 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19657 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19658 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19659 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19660 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19661 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19662 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19663 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19664 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19665 | ||
19666 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19667 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19668 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19669 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19670 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19671 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19672 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19673 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19674 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19675 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19676 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19677 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19678 | ||
19679 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
19680 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
19681 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
19682 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
19683 | ||
19684 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
19685 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
19686 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
19687 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
19688 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
19689 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
19690 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
19691 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
19692 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
19693 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
19694 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
19695 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 19696 | |
c19d1205 ZW |
19697 | /* The implementation of the FIX instruction is broken on some |
19698 | assemblers, in that it accepts a precision specifier as well as a | |
19699 | rounding specifier, despite the fact that this is meaningless. | |
19700 | To be more compatible, we accept it as well, though of course it | |
19701 | does not set any bits. */ | |
21d799b5 NC |
19702 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
19703 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
19704 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
19705 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
19706 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
19707 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
19708 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
19709 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
19710 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
19711 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
19712 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
19713 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
19714 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 19715 | |
c19d1205 | 19716 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
19717 | #undef ARM_VARIANT |
19718 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
19719 | ||
21d799b5 NC |
19720 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
19721 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19722 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19723 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19724 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19725 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 19726 | |
c921be7d NC |
19727 | #undef ARM_VARIANT |
19728 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
19729 | ||
c19d1205 | 19730 | /* Moves and type conversions. */ |
21d799b5 NC |
19731 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
19732 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
19733 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
19734 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
19735 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
19736 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
19737 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19738 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19739 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19740 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19741 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19742 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19743 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
19744 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
19745 | |
19746 | /* Memory operations. */ | |
21d799b5 NC |
19747 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
19748 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
19749 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
19750 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19751 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19752 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19753 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19754 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19755 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19756 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19757 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19758 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19759 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19760 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19761 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19762 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19763 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19764 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 19765 | |
c19d1205 | 19766 | /* Monadic operations. */ |
21d799b5 NC |
19767 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19768 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19769 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
19770 | |
19771 | /* Dyadic operations. */ | |
21d799b5 NC |
19772 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
19773 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19774 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19775 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19776 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19777 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19778 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19779 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19780 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 19781 | |
c19d1205 | 19782 | /* Comparisons. */ |
21d799b5 NC |
19783 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
19784 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
19785 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19786 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 19787 | |
62f3b8c8 PB |
19788 | /* Double precision load/store are still present on single precision |
19789 | implementations. */ | |
19790 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
19791 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
19792 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
19793 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19794 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19795 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19796 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19797 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19798 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19799 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 19800 | |
c921be7d NC |
19801 | #undef ARM_VARIANT |
19802 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
19803 | ||
c19d1205 | 19804 | /* Moves and type conversions. */ |
21d799b5 NC |
19805 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19806 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19807 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19808 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19809 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19810 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19811 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19812 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19813 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19814 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19815 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19816 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19817 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 19818 | |
c19d1205 | 19819 | /* Monadic operations. */ |
21d799b5 NC |
19820 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
19821 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19822 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
19823 | |
19824 | /* Dyadic operations. */ | |
21d799b5 NC |
19825 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
19826 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19827 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19828 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19829 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19830 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19831 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19832 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19833 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 19834 | |
c19d1205 | 19835 | /* Comparisons. */ |
21d799b5 NC |
19836 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19837 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
19838 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19839 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 19840 | |
c921be7d NC |
19841 | #undef ARM_VARIANT |
19842 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
19843 | ||
21d799b5 NC |
19844 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
19845 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
19846 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
19847 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 19848 | |
037e8744 JB |
19849 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
19850 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
19851 | #undef ARM_VARIANT |
19852 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
19853 | #undef THUMB_VARIANT | |
19854 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
19855 | ||
037e8744 JB |
19856 | /* These mnemonics are unique to VFP. */ |
19857 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
19858 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
19859 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
19860 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19861 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
aacf0b33 KT |
19862 | nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), |
19863 | nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), | |
037e8744 JB |
19864 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
19865 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
19866 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
19867 | ||
19868 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
19869 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
19870 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
19871 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 19872 | |
21d799b5 NC |
19873 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
19874 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
19875 | |
19876 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19877 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19878 | ||
55881a11 MGD |
19879 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
19880 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19881 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19882 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19883 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19884 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
19885 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
19886 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 19887 | |
5f1af56b | 19888 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 19889 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
c70a8987 MGD |
19890 | NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb), |
19891 | NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt), | |
f31fef98 | 19892 | |
037e8744 JB |
19893 | |
19894 | /* NOTE: All VMOV encoding is special-cased! */ | |
19895 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
19896 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
19897 | ||
c921be7d NC |
19898 | #undef THUMB_VARIANT |
19899 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
19900 | #undef ARM_VARIANT | |
19901 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
19902 | ||
5287ad62 JB |
19903 | /* Data processing with three registers of the same length. */ |
19904 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
19905 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
19906 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
19907 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19908 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19909 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19910 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19911 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19912 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19913 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19914 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19915 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
19916 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19917 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
19918 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
19919 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
19920 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
19921 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
19922 | /* If not immediate, fall back to neon_dyadic_i64_su. |
19923 | shl_imm should accept I8 I16 I32 I64, | |
19924 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
19925 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
19926 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
19927 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
19928 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 19929 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
19930 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
19931 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19932 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19933 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19934 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19935 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19936 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19937 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19938 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
19939 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
19940 | /* Bitfield ops, untyped. */ |
19941 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19942 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19943 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19944 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19945 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19946 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19947 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
19948 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
19949 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19950 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19951 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19952 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19953 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
19954 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
19955 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
19956 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
19957 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19958 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
19959 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19960 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19961 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
19962 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19963 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 19964 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
19965 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
19966 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 19967 | /* As above, D registers only. */ |
21d799b5 NC |
19968 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
19969 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 19970 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
19971 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
19972 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
19973 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 19974 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
19975 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
19976 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
19977 | /* vtst takes sizes 8, 16, 32. */ |
19978 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
19979 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
19980 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 19981 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 19982 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
19983 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
19984 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
19985 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
19986 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
19987 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
19988 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
19989 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
19990 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
19991 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
19992 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
19993 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
19994 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
19995 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
19996 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
19997 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
19998 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
d6b4b13e MW |
19999 | /* ARM v8.1 extension. */ |
20000 | nUF(vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
20001 | nUF(vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
20002 | nUF(vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
20003 | nUF(vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
20004 | |
20005 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 20006 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
20007 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
20008 | ||
20009 | /* Data processing with two registers and a shift amount. */ | |
20010 | /* Right shifts, and variants with rounding. | |
20011 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
20012 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
20013 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
20014 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
20015 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
20016 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
20017 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
20018 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
20019 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
20020 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
20021 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
20022 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
20023 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
20024 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
20025 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
20026 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
20027 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
20028 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
20029 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
20030 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
20031 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
20032 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
20033 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
20034 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
20035 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
20036 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
20037 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
20038 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 20039 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 20040 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 20041 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 20042 | |
4316f0d2 DG |
20043 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
20044 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
20045 | |
20046 | /* Data processing, three registers of different lengths. */ | |
20047 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
20048 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
20049 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
20050 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
20051 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
20052 | /* If not scalar, fall back to neon_dyadic_long. | |
20053 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
20054 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
20055 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
20056 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
20057 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
20058 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
20059 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
20060 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20061 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20062 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20063 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20064 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
20065 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
20066 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
20067 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
20068 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
20069 | S16 S32 U16 U32. */ | |
21d799b5 | 20070 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
20071 | |
20072 | /* Extract. Size 8. */ | |
3b8d421e PB |
20073 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
20074 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
20075 | |
20076 | /* Two registers, miscellaneous. */ | |
20077 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
20078 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
20079 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
20080 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
20081 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
20082 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
20083 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
20084 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
20085 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
20086 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
20087 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
20088 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
20089 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 20090 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 20091 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 20092 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 20093 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 20094 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
20095 | /* VZIP / VUZP. Sizes 8 16 32. */ |
20096 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
20097 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
20098 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
20099 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
20100 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
20101 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
20102 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
20103 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
20104 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
20105 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
20106 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
20107 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
20108 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
20109 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
20110 | /* Reciprocal estimates. Types U32 F32. */ | |
20111 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
20112 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
20113 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
20114 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
20115 | /* VCLS. Types S8 S16 S32. */ | |
20116 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
20117 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
20118 | /* VCLZ. Types I8 I16 I32. */ | |
20119 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
20120 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
20121 | /* VCNT. Size 8. */ | |
20122 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
20123 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
20124 | /* Two address, untyped. */ | |
20125 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
20126 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
20127 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
20128 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
20129 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
20130 | |
20131 | /* Table lookup. Size 8. */ | |
20132 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
20133 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
20134 | ||
c921be7d NC |
20135 | #undef THUMB_VARIANT |
20136 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
20137 | #undef ARM_VARIANT | |
20138 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
20139 | ||
5287ad62 | 20140 | /* Neon element/structure load/store. */ |
21d799b5 NC |
20141 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
20142 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20143 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20144 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20145 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20146 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20147 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20148 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 20149 | |
c921be7d | 20150 | #undef THUMB_VARIANT |
74db7efb NC |
20151 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
20152 | #undef ARM_VARIANT | |
20153 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
20154 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
20155 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20156 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20157 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20158 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20159 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20160 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20161 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20162 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20163 | ||
74db7efb | 20164 | #undef THUMB_VARIANT |
c921be7d NC |
20165 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
20166 | #undef ARM_VARIANT | |
20167 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
20168 | ||
21d799b5 | 20169 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 20170 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20171 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 20172 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20173 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 20174 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20175 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 20176 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20177 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 20178 | |
74db7efb NC |
20179 | #undef ARM_VARIANT |
20180 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
20181 | #undef THUMB_VARIANT | |
20182 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
62f3b8c8 PB |
20183 | /* Mnemonics shared by Neon and VFP. These are included in the |
20184 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
20185 | FMA instructions. */ | |
20186 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
20187 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
20188 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
20189 | the v form should always be used. */ | |
20190 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20191 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20192 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20193 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20194 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
20195 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
20196 | ||
5287ad62 | 20197 | #undef THUMB_VARIANT |
c921be7d NC |
20198 | #undef ARM_VARIANT |
20199 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
20200 | ||
21d799b5 NC |
20201 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
20202 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20203 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20204 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20205 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20206 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20207 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
20208 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 20209 | |
c921be7d NC |
20210 | #undef ARM_VARIANT |
20211 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
20212 | ||
21d799b5 NC |
20213 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
20214 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
20215 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
20216 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
20217 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
20218 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
20219 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
20220 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
20221 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
20222 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
20223 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20224 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20225 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20226 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20227 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
20228 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
20229 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
20230 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
20231 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
20232 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
20233 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20234 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20235 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20236 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20237 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20238 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
20239 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
20240 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
20241 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
20242 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
20243 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
20244 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
20245 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
20246 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
20247 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
20248 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
20249 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
20250 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20251 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20252 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20253 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20254 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20255 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20256 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20257 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20258 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20259 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
20260 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20261 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20262 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20263 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20264 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20265 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20266 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20267 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20268 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20269 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20270 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20271 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20272 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20273 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20274 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20275 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20276 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20277 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20278 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20279 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
20280 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20281 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20282 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20283 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20284 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20285 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20286 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20287 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20288 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20289 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20290 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20291 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20292 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20293 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20294 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20295 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20296 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20297 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20298 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20299 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20300 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20301 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
20302 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20303 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20304 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20305 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20306 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20307 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20308 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20309 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20310 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20311 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20312 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20313 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
20314 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20315 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20316 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20317 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20318 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20319 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20320 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20321 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20322 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20323 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
20324 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20325 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20326 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20327 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20328 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20329 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20330 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20331 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20332 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20333 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20334 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20335 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20336 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20337 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20338 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20339 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20340 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20341 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20342 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20343 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20344 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20345 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20346 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20347 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20348 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20349 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20350 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20351 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20352 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20353 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20354 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20355 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
20356 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
20357 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
20358 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
20359 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
20360 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
20361 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20362 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20363 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20364 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
20365 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
20366 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
20367 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
20368 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
20369 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
20370 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20371 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20372 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20373 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20374 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 20375 | |
c921be7d NC |
20376 | #undef ARM_VARIANT |
20377 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
20378 | ||
21d799b5 NC |
20379 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
20380 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
20381 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
20382 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
20383 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
20384 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
20385 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20386 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20387 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20388 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20389 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20390 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20391 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20392 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20393 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20394 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20395 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20396 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20397 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20398 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20399 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
20400 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20401 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20402 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20403 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20404 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20405 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20406 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20407 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20408 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20409 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20410 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20411 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20412 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20413 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20414 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20415 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20416 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20417 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20418 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20419 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20420 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20421 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20422 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20423 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20424 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20425 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20426 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20427 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20428 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20429 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20430 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20431 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20432 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20433 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20434 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20435 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 20436 | |
c921be7d NC |
20437 | #undef ARM_VARIANT |
20438 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
20439 | ||
21d799b5 NC |
20440 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
20441 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20442 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20443 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20444 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
20445 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20446 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20447 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20448 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
20449 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
20450 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
20451 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
20452 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
20453 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
20454 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
20455 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
20456 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
20457 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
20458 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
20459 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
20460 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
20461 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
20462 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
20463 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
20464 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
20465 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
20466 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
20467 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
20468 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
20469 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
20470 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
20471 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
20472 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
20473 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
20474 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
20475 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
20476 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
20477 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
20478 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
20479 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
20480 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
20481 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
20482 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
20483 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
20484 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
20485 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
20486 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
20487 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
20488 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
20489 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
20490 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
20491 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
20492 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
20493 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
20494 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20495 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20496 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20497 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20498 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20499 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20500 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
20501 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
20502 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
20503 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
20504 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20505 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20506 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20507 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20508 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20509 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20510 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20511 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
20512 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
20513 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
20514 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
20515 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
20516 | }; |
20517 | #undef ARM_VARIANT | |
20518 | #undef THUMB_VARIANT | |
20519 | #undef TCE | |
c19d1205 ZW |
20520 | #undef TUE |
20521 | #undef TUF | |
20522 | #undef TCC | |
8f06b2d8 | 20523 | #undef cCE |
e3cb604e PB |
20524 | #undef cCL |
20525 | #undef C3E | |
c19d1205 ZW |
20526 | #undef CE |
20527 | #undef CM | |
20528 | #undef UE | |
20529 | #undef UF | |
20530 | #undef UT | |
5287ad62 JB |
20531 | #undef NUF |
20532 | #undef nUF | |
20533 | #undef NCE | |
20534 | #undef nCE | |
c19d1205 ZW |
20535 | #undef OPS0 |
20536 | #undef OPS1 | |
20537 | #undef OPS2 | |
20538 | #undef OPS3 | |
20539 | #undef OPS4 | |
20540 | #undef OPS5 | |
20541 | #undef OPS6 | |
20542 | #undef do_0 | |
20543 | \f | |
20544 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 20545 | |
c19d1205 ZW |
20546 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
20547 | for use in the a.out file, and stores them in the array pointed to by buf. | |
20548 | This knows about the endian-ness of the target machine and does | |
20549 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
20550 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
20551 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 20552 | |
c19d1205 ZW |
20553 | void |
20554 | md_number_to_chars (char * buf, valueT val, int n) | |
20555 | { | |
20556 | if (target_big_endian) | |
20557 | number_to_chars_bigendian (buf, val, n); | |
20558 | else | |
20559 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
20560 | } |
20561 | ||
c19d1205 ZW |
20562 | static valueT |
20563 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 20564 | { |
c19d1205 ZW |
20565 | valueT result = 0; |
20566 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 20567 | |
c19d1205 | 20568 | if (target_big_endian) |
b99bd4ef | 20569 | { |
c19d1205 ZW |
20570 | while (n--) |
20571 | { | |
20572 | result <<= 8; | |
20573 | result |= (*where++ & 255); | |
20574 | } | |
b99bd4ef | 20575 | } |
c19d1205 | 20576 | else |
b99bd4ef | 20577 | { |
c19d1205 ZW |
20578 | while (n--) |
20579 | { | |
20580 | result <<= 8; | |
20581 | result |= (where[n] & 255); | |
20582 | } | |
bfae80f2 | 20583 | } |
b99bd4ef | 20584 | |
c19d1205 | 20585 | return result; |
bfae80f2 | 20586 | } |
b99bd4ef | 20587 | |
c19d1205 | 20588 | /* MD interface: Sections. */ |
b99bd4ef | 20589 | |
fa94de6b RM |
20590 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
20591 | that an rs_machine_dependent frag may reach. */ | |
20592 | ||
20593 | unsigned int | |
20594 | arm_frag_max_var (fragS *fragp) | |
20595 | { | |
20596 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
20597 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
20598 | ||
20599 | Note that we generate relaxable instructions even for cases that don't | |
20600 | really need it, like an immediate that's a trivial constant. So we're | |
20601 | overestimating the instruction size for some of those cases. Rather | |
20602 | than putting more intelligence here, it would probably be better to | |
20603 | avoid generating a relaxation frag in the first place when it can be | |
20604 | determined up front that a short instruction will suffice. */ | |
20605 | ||
20606 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
20607 | return INSN_SIZE; | |
20608 | } | |
20609 | ||
0110f2b8 PB |
20610 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
20611 | 2 bytes. */ | |
20612 | ||
c19d1205 | 20613 | int |
0110f2b8 | 20614 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
20615 | segT segtype ATTRIBUTE_UNUSED) |
20616 | { | |
0110f2b8 PB |
20617 | fragp->fr_var = 2; |
20618 | return 2; | |
20619 | } | |
20620 | ||
20621 | /* Convert a machine dependent frag. */ | |
20622 | ||
20623 | void | |
20624 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
20625 | { | |
20626 | unsigned long insn; | |
20627 | unsigned long old_op; | |
20628 | char *buf; | |
20629 | expressionS exp; | |
20630 | fixS *fixp; | |
20631 | int reloc_type; | |
20632 | int pc_rel; | |
20633 | int opcode; | |
20634 | ||
20635 | buf = fragp->fr_literal + fragp->fr_fix; | |
20636 | ||
20637 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
20638 | if (fragp->fr_symbol) |
20639 | { | |
0110f2b8 PB |
20640 | exp.X_op = O_symbol; |
20641 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
20642 | } |
20643 | else | |
20644 | { | |
0110f2b8 | 20645 | exp.X_op = O_constant; |
5f4273c7 | 20646 | } |
0110f2b8 PB |
20647 | exp.X_add_number = fragp->fr_offset; |
20648 | opcode = fragp->fr_subtype; | |
20649 | switch (opcode) | |
20650 | { | |
20651 | case T_MNEM_ldr_pc: | |
20652 | case T_MNEM_ldr_pc2: | |
20653 | case T_MNEM_ldr_sp: | |
20654 | case T_MNEM_str_sp: | |
20655 | case T_MNEM_ldr: | |
20656 | case T_MNEM_ldrb: | |
20657 | case T_MNEM_ldrh: | |
20658 | case T_MNEM_str: | |
20659 | case T_MNEM_strb: | |
20660 | case T_MNEM_strh: | |
20661 | if (fragp->fr_var == 4) | |
20662 | { | |
5f4273c7 | 20663 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
20664 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
20665 | { | |
20666 | insn |= (old_op & 0x700) << 4; | |
20667 | } | |
20668 | else | |
20669 | { | |
20670 | insn |= (old_op & 7) << 12; | |
20671 | insn |= (old_op & 0x38) << 13; | |
20672 | } | |
20673 | insn |= 0x00000c00; | |
20674 | put_thumb32_insn (buf, insn); | |
20675 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
20676 | } | |
20677 | else | |
20678 | { | |
20679 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
20680 | } | |
20681 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
20682 | break; | |
20683 | case T_MNEM_adr: | |
20684 | if (fragp->fr_var == 4) | |
20685 | { | |
20686 | insn = THUMB_OP32 (opcode); | |
20687 | insn |= (old_op & 0xf0) << 4; | |
20688 | put_thumb32_insn (buf, insn); | |
20689 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
20690 | } | |
20691 | else | |
20692 | { | |
20693 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20694 | exp.X_add_number -= 4; | |
20695 | } | |
20696 | pc_rel = 1; | |
20697 | break; | |
20698 | case T_MNEM_mov: | |
20699 | case T_MNEM_movs: | |
20700 | case T_MNEM_cmp: | |
20701 | case T_MNEM_cmn: | |
20702 | if (fragp->fr_var == 4) | |
20703 | { | |
20704 | int r0off = (opcode == T_MNEM_mov | |
20705 | || opcode == T_MNEM_movs) ? 0 : 8; | |
20706 | insn = THUMB_OP32 (opcode); | |
20707 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
20708 | insn |= (old_op & 0x700) << r0off; | |
20709 | put_thumb32_insn (buf, insn); | |
20710 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
20711 | } | |
20712 | else | |
20713 | { | |
20714 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
20715 | } | |
20716 | pc_rel = 0; | |
20717 | break; | |
20718 | case T_MNEM_b: | |
20719 | if (fragp->fr_var == 4) | |
20720 | { | |
20721 | insn = THUMB_OP32(opcode); | |
20722 | put_thumb32_insn (buf, insn); | |
20723 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
20724 | } | |
20725 | else | |
20726 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
20727 | pc_rel = 1; | |
20728 | break; | |
20729 | case T_MNEM_bcond: | |
20730 | if (fragp->fr_var == 4) | |
20731 | { | |
20732 | insn = THUMB_OP32(opcode); | |
20733 | insn |= (old_op & 0xf00) << 14; | |
20734 | put_thumb32_insn (buf, insn); | |
20735 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
20736 | } | |
20737 | else | |
20738 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
20739 | pc_rel = 1; | |
20740 | break; | |
20741 | case T_MNEM_add_sp: | |
20742 | case T_MNEM_add_pc: | |
20743 | case T_MNEM_inc_sp: | |
20744 | case T_MNEM_dec_sp: | |
20745 | if (fragp->fr_var == 4) | |
20746 | { | |
20747 | /* ??? Choose between add and addw. */ | |
20748 | insn = THUMB_OP32 (opcode); | |
20749 | insn |= (old_op & 0xf0) << 4; | |
20750 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20751 | if (opcode == T_MNEM_add_pc) |
20752 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
20753 | else | |
20754 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
20755 | } |
20756 | else | |
20757 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20758 | pc_rel = 0; | |
20759 | break; | |
20760 | ||
20761 | case T_MNEM_addi: | |
20762 | case T_MNEM_addis: | |
20763 | case T_MNEM_subi: | |
20764 | case T_MNEM_subis: | |
20765 | if (fragp->fr_var == 4) | |
20766 | { | |
20767 | insn = THUMB_OP32 (opcode); | |
20768 | insn |= (old_op & 0xf0) << 4; | |
20769 | insn |= (old_op & 0xf) << 16; | |
20770 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20771 | if (insn & (1 << 20)) |
20772 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
20773 | else | |
20774 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
20775 | } |
20776 | else | |
20777 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20778 | pc_rel = 0; | |
20779 | break; | |
20780 | default: | |
5f4273c7 | 20781 | abort (); |
0110f2b8 PB |
20782 | } |
20783 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 20784 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
20785 | fixp->fx_file = fragp->fr_file; |
20786 | fixp->fx_line = fragp->fr_line; | |
20787 | fragp->fr_fix += fragp->fr_var; | |
3cfdb781 TG |
20788 | |
20789 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ | |
20790 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () | |
20791 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) | |
20792 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); | |
0110f2b8 PB |
20793 | } |
20794 | ||
20795 | /* Return the size of a relaxable immediate operand instruction. | |
20796 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
20797 | static int | |
20798 | relax_immediate (fragS *fragp, int size, int shift) | |
20799 | { | |
20800 | offsetT offset; | |
20801 | offsetT mask; | |
20802 | offsetT low; | |
20803 | ||
20804 | /* ??? Should be able to do better than this. */ | |
20805 | if (fragp->fr_symbol) | |
20806 | return 4; | |
20807 | ||
20808 | low = (1 << shift) - 1; | |
20809 | mask = (1 << (shift + size)) - (1 << shift); | |
20810 | offset = fragp->fr_offset; | |
20811 | /* Force misaligned offsets to 32-bit variant. */ | |
20812 | if (offset & low) | |
5e77afaa | 20813 | return 4; |
0110f2b8 PB |
20814 | if (offset & ~mask) |
20815 | return 4; | |
20816 | return 2; | |
20817 | } | |
20818 | ||
5e77afaa PB |
20819 | /* Get the address of a symbol during relaxation. */ |
20820 | static addressT | |
5f4273c7 | 20821 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
20822 | { |
20823 | fragS *sym_frag; | |
20824 | addressT addr; | |
20825 | symbolS *sym; | |
20826 | ||
20827 | sym = fragp->fr_symbol; | |
20828 | sym_frag = symbol_get_frag (sym); | |
20829 | know (S_GET_SEGMENT (sym) != absolute_section | |
20830 | || sym_frag == &zero_address_frag); | |
20831 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
20832 | ||
20833 | /* If frag has yet to be reached on this pass, assume it will | |
20834 | move by STRETCH just as we did. If this is not so, it will | |
20835 | be because some frag between grows, and that will force | |
20836 | another pass. */ | |
20837 | ||
20838 | if (stretch != 0 | |
20839 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
20840 | { |
20841 | fragS *f; | |
20842 | ||
20843 | /* Adjust stretch for any alignment frag. Note that if have | |
20844 | been expanding the earlier code, the symbol may be | |
20845 | defined in what appears to be an earlier frag. FIXME: | |
20846 | This doesn't handle the fr_subtype field, which specifies | |
20847 | a maximum number of bytes to skip when doing an | |
20848 | alignment. */ | |
20849 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
20850 | { | |
20851 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
20852 | { | |
20853 | if (stretch < 0) | |
20854 | stretch = - ((- stretch) | |
20855 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
20856 | else | |
20857 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
20858 | if (stretch == 0) | |
20859 | break; | |
20860 | } | |
20861 | } | |
20862 | if (f != NULL) | |
20863 | addr += stretch; | |
20864 | } | |
5e77afaa PB |
20865 | |
20866 | return addr; | |
20867 | } | |
20868 | ||
0110f2b8 PB |
20869 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
20870 | load. */ | |
20871 | static int | |
5e77afaa | 20872 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
20873 | { |
20874 | addressT addr; | |
20875 | offsetT val; | |
20876 | ||
20877 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
20878 | if (fragp->fr_symbol == NULL |
20879 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
20880 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20881 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20882 | return 4; |
20883 | ||
5f4273c7 | 20884 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20885 | addr = fragp->fr_address + fragp->fr_fix; |
20886 | addr = (addr + 4) & ~3; | |
5e77afaa | 20887 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 20888 | if (val & 3) |
5e77afaa | 20889 | return 4; |
0110f2b8 PB |
20890 | val -= addr; |
20891 | if (val < 0 || val > 1020) | |
20892 | return 4; | |
20893 | return 2; | |
20894 | } | |
20895 | ||
20896 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
20897 | static int | |
20898 | relax_addsub (fragS *fragp, asection *sec) | |
20899 | { | |
20900 | char *buf; | |
20901 | int op; | |
20902 | ||
20903 | buf = fragp->fr_literal + fragp->fr_fix; | |
20904 | op = bfd_get_16(sec->owner, buf); | |
20905 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
20906 | return relax_immediate (fragp, 8, 0); | |
20907 | else | |
20908 | return relax_immediate (fragp, 3, 0); | |
20909 | } | |
20910 | ||
e83a675f RE |
20911 | /* Return TRUE iff the definition of symbol S could be pre-empted |
20912 | (overridden) at link or load time. */ | |
20913 | static bfd_boolean | |
20914 | symbol_preemptible (symbolS *s) | |
20915 | { | |
20916 | /* Weak symbols can always be pre-empted. */ | |
20917 | if (S_IS_WEAK (s)) | |
20918 | return TRUE; | |
20919 | ||
20920 | /* Non-global symbols cannot be pre-empted. */ | |
20921 | if (! S_IS_EXTERNAL (s)) | |
20922 | return FALSE; | |
20923 | ||
20924 | #ifdef OBJ_ELF | |
20925 | /* In ELF, a global symbol can be marked protected, or private. In that | |
20926 | case it can't be pre-empted (other definitions in the same link unit | |
20927 | would violate the ODR). */ | |
20928 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
20929 | return FALSE; | |
20930 | #endif | |
20931 | ||
20932 | /* Other global symbols might be pre-empted. */ | |
20933 | return TRUE; | |
20934 | } | |
0110f2b8 PB |
20935 | |
20936 | /* Return the size of a relaxable branch instruction. BITS is the | |
20937 | size of the offset field in the narrow instruction. */ | |
20938 | ||
20939 | static int | |
5e77afaa | 20940 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
20941 | { |
20942 | addressT addr; | |
20943 | offsetT val; | |
20944 | offsetT limit; | |
20945 | ||
20946 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 20947 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
20948 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20949 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20950 | return 4; |
20951 | ||
267bf995 | 20952 | #ifdef OBJ_ELF |
e83a675f | 20953 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
20954 | if (S_IS_DEFINED (fragp->fr_symbol) |
20955 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
20956 | return 4; | |
e83a675f | 20957 | #endif |
0d9b4b55 | 20958 | |
e83a675f | 20959 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 20960 | return 4; |
267bf995 | 20961 | |
5f4273c7 | 20962 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20963 | addr = fragp->fr_address + fragp->fr_fix + 4; |
20964 | val -= addr; | |
20965 | ||
20966 | /* Offset is a signed value *2 */ | |
20967 | limit = 1 << bits; | |
20968 | if (val >= limit || val < -limit) | |
20969 | return 4; | |
20970 | return 2; | |
20971 | } | |
20972 | ||
20973 | ||
20974 | /* Relax a machine dependent frag. This returns the amount by which | |
20975 | the current size of the frag should change. */ | |
20976 | ||
20977 | int | |
5e77afaa | 20978 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
20979 | { |
20980 | int oldsize; | |
20981 | int newsize; | |
20982 | ||
20983 | oldsize = fragp->fr_var; | |
20984 | switch (fragp->fr_subtype) | |
20985 | { | |
20986 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 20987 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20988 | break; |
20989 | case T_MNEM_ldr_pc: | |
20990 | case T_MNEM_ldr_sp: | |
20991 | case T_MNEM_str_sp: | |
5f4273c7 | 20992 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
20993 | break; |
20994 | case T_MNEM_ldr: | |
20995 | case T_MNEM_str: | |
5f4273c7 | 20996 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
20997 | break; |
20998 | case T_MNEM_ldrh: | |
20999 | case T_MNEM_strh: | |
5f4273c7 | 21000 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
21001 | break; |
21002 | case T_MNEM_ldrb: | |
21003 | case T_MNEM_strb: | |
5f4273c7 | 21004 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
21005 | break; |
21006 | case T_MNEM_adr: | |
5f4273c7 | 21007 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
21008 | break; |
21009 | case T_MNEM_mov: | |
21010 | case T_MNEM_movs: | |
21011 | case T_MNEM_cmp: | |
21012 | case T_MNEM_cmn: | |
5f4273c7 | 21013 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
21014 | break; |
21015 | case T_MNEM_b: | |
5f4273c7 | 21016 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
21017 | break; |
21018 | case T_MNEM_bcond: | |
5f4273c7 | 21019 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
21020 | break; |
21021 | case T_MNEM_add_sp: | |
21022 | case T_MNEM_add_pc: | |
21023 | newsize = relax_immediate (fragp, 8, 2); | |
21024 | break; | |
21025 | case T_MNEM_inc_sp: | |
21026 | case T_MNEM_dec_sp: | |
21027 | newsize = relax_immediate (fragp, 7, 2); | |
21028 | break; | |
21029 | case T_MNEM_addi: | |
21030 | case T_MNEM_addis: | |
21031 | case T_MNEM_subi: | |
21032 | case T_MNEM_subis: | |
21033 | newsize = relax_addsub (fragp, sec); | |
21034 | break; | |
21035 | default: | |
5f4273c7 | 21036 | abort (); |
0110f2b8 | 21037 | } |
5e77afaa PB |
21038 | |
21039 | fragp->fr_var = newsize; | |
21040 | /* Freeze wide instructions that are at or before the same location as | |
21041 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
21042 | Don't freeze them unconditionally because targets may be artificially |
21043 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 21044 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 21045 | { |
0110f2b8 | 21046 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 21047 | frag_wane (fragp); |
0110f2b8 | 21048 | } |
5e77afaa | 21049 | |
0110f2b8 | 21050 | return newsize - oldsize; |
c19d1205 | 21051 | } |
b99bd4ef | 21052 | |
c19d1205 | 21053 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 21054 | |
c19d1205 ZW |
21055 | valueT |
21056 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
21057 | valueT size) | |
21058 | { | |
f0927246 NC |
21059 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
21060 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
21061 | { | |
21062 | /* For a.out, force the section size to be aligned. If we don't do | |
21063 | this, BFD will align it for us, but it will not write out the | |
21064 | final bytes of the section. This may be a bug in BFD, but it is | |
21065 | easier to fix it here since that is how the other a.out targets | |
21066 | work. */ | |
21067 | int align; | |
21068 | ||
21069 | align = bfd_get_section_alignment (stdoutput, segment); | |
21070 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
21071 | } | |
c19d1205 | 21072 | #endif |
f0927246 NC |
21073 | |
21074 | return size; | |
bfae80f2 | 21075 | } |
b99bd4ef | 21076 | |
c19d1205 ZW |
21077 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
21078 | of an rs_align_code fragment. */ | |
21079 | ||
21080 | void | |
21081 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 21082 | { |
e7495e45 NS |
21083 | static char const arm_noop[2][2][4] = |
21084 | { | |
21085 | { /* ARMv1 */ | |
21086 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
21087 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
21088 | }, | |
21089 | { /* ARMv6k */ | |
21090 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
21091 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
21092 | }, | |
21093 | }; | |
21094 | static char const thumb_noop[2][2][2] = | |
21095 | { | |
21096 | { /* Thumb-1 */ | |
21097 | {0xc0, 0x46}, /* LE */ | |
21098 | {0x46, 0xc0}, /* BE */ | |
21099 | }, | |
21100 | { /* Thumb-2 */ | |
21101 | {0x00, 0xbf}, /* LE */ | |
21102 | {0xbf, 0x00} /* BE */ | |
21103 | } | |
21104 | }; | |
21105 | static char const wide_thumb_noop[2][4] = | |
21106 | { /* Wide Thumb-2 */ | |
21107 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
21108 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
21109 | }; | |
c921be7d | 21110 | |
e7495e45 | 21111 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
21112 | char * p; |
21113 | const char * noop; | |
e7495e45 | 21114 | const char *narrow_noop = NULL; |
cd000bff DJ |
21115 | #ifdef OBJ_ELF |
21116 | enum mstate state; | |
21117 | #endif | |
bfae80f2 | 21118 | |
c19d1205 | 21119 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
21120 | return; |
21121 | ||
c19d1205 ZW |
21122 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
21123 | p = fragP->fr_literal + fragP->fr_fix; | |
21124 | fix = 0; | |
bfae80f2 | 21125 | |
c19d1205 ZW |
21126 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
21127 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 21128 | |
cd000bff | 21129 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 21130 | |
cd000bff | 21131 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 21132 | { |
7f78eb34 JW |
21133 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
21134 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
21135 | { |
21136 | narrow_noop = thumb_noop[1][target_big_endian]; | |
21137 | noop = wide_thumb_noop[target_big_endian]; | |
21138 | } | |
c19d1205 | 21139 | else |
e7495e45 NS |
21140 | noop = thumb_noop[0][target_big_endian]; |
21141 | noop_size = 2; | |
cd000bff DJ |
21142 | #ifdef OBJ_ELF |
21143 | state = MAP_THUMB; | |
21144 | #endif | |
7ed4c4c5 NC |
21145 | } |
21146 | else | |
21147 | { | |
7f78eb34 JW |
21148 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
21149 | ? selected_cpu : arm_arch_none, | |
21150 | arm_ext_v6k) != 0] | |
e7495e45 NS |
21151 | [target_big_endian]; |
21152 | noop_size = 4; | |
cd000bff DJ |
21153 | #ifdef OBJ_ELF |
21154 | state = MAP_ARM; | |
21155 | #endif | |
7ed4c4c5 | 21156 | } |
c921be7d | 21157 | |
e7495e45 | 21158 | fragP->fr_var = noop_size; |
c921be7d | 21159 | |
c19d1205 | 21160 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 21161 | { |
c19d1205 | 21162 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
21163 | #ifdef OBJ_ELF |
21164 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
21165 | #endif | |
c19d1205 ZW |
21166 | memset (p, 0, fix); |
21167 | p += fix; | |
21168 | bytes -= fix; | |
a737bd4d | 21169 | } |
a737bd4d | 21170 | |
e7495e45 NS |
21171 | if (narrow_noop) |
21172 | { | |
21173 | if (bytes & noop_size) | |
21174 | { | |
21175 | /* Insert a narrow noop. */ | |
21176 | memcpy (p, narrow_noop, noop_size); | |
21177 | p += noop_size; | |
21178 | bytes -= noop_size; | |
21179 | fix += noop_size; | |
21180 | } | |
21181 | ||
21182 | /* Use wide noops for the remainder */ | |
21183 | noop_size = 4; | |
21184 | } | |
21185 | ||
c19d1205 | 21186 | while (bytes >= noop_size) |
a737bd4d | 21187 | { |
c19d1205 ZW |
21188 | memcpy (p, noop, noop_size); |
21189 | p += noop_size; | |
21190 | bytes -= noop_size; | |
21191 | fix += noop_size; | |
a737bd4d NC |
21192 | } |
21193 | ||
c19d1205 | 21194 | fragP->fr_fix += fix; |
a737bd4d NC |
21195 | } |
21196 | ||
c19d1205 ZW |
21197 | /* Called from md_do_align. Used to create an alignment |
21198 | frag in a code section. */ | |
21199 | ||
21200 | void | |
21201 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 21202 | { |
c19d1205 | 21203 | char * p; |
7ed4c4c5 | 21204 | |
c19d1205 | 21205 | /* We assume that there will never be a requirement |
6ec8e702 | 21206 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 21207 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
21208 | { |
21209 | char err_msg[128]; | |
21210 | ||
fa94de6b | 21211 | sprintf (err_msg, |
477330fc RM |
21212 | _("alignments greater than %d bytes not supported in .text sections."), |
21213 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 21214 | as_fatal ("%s", err_msg); |
6ec8e702 | 21215 | } |
bfae80f2 | 21216 | |
c19d1205 ZW |
21217 | p = frag_var (rs_align_code, |
21218 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
21219 | 1, | |
21220 | (relax_substateT) max, | |
21221 | (symbolS *) NULL, | |
21222 | (offsetT) n, | |
21223 | (char *) NULL); | |
21224 | *p = 0; | |
21225 | } | |
bfae80f2 | 21226 | |
8dc2430f NC |
21227 | /* Perform target specific initialisation of a frag. |
21228 | Note - despite the name this initialisation is not done when the frag | |
21229 | is created, but only when its type is assigned. A frag can be created | |
21230 | and used a long time before its type is set, so beware of assuming that | |
21231 | this initialisationis performed first. */ | |
bfae80f2 | 21232 | |
cd000bff DJ |
21233 | #ifndef OBJ_ELF |
21234 | void | |
21235 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
21236 | { | |
21237 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 21238 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
21239 | } |
21240 | ||
21241 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 21242 | void |
cd000bff | 21243 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 21244 | { |
b968d18a JW |
21245 | int frag_thumb_mode; |
21246 | ||
8dc2430f NC |
21247 | /* If the current ARM vs THUMB mode has not already |
21248 | been recorded into this frag then do so now. */ | |
cd000bff | 21249 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
b968d18a JW |
21250 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
21251 | ||
21252 | frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED; | |
cd000bff | 21253 | |
f9c1b181 RL |
21254 | /* Record a mapping symbol for alignment frags. We will delete this |
21255 | later if the alignment ends up empty. */ | |
21256 | switch (fragP->fr_type) | |
21257 | { | |
21258 | case rs_align: | |
21259 | case rs_align_test: | |
21260 | case rs_fill: | |
21261 | mapping_state_2 (MAP_DATA, max_chars); | |
21262 | break; | |
21263 | case rs_align_code: | |
b968d18a | 21264 | mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); |
f9c1b181 RL |
21265 | break; |
21266 | default: | |
21267 | break; | |
cd000bff | 21268 | } |
bfae80f2 RE |
21269 | } |
21270 | ||
c19d1205 ZW |
21271 | /* When we change sections we need to issue a new mapping symbol. */ |
21272 | ||
21273 | void | |
21274 | arm_elf_change_section (void) | |
bfae80f2 | 21275 | { |
c19d1205 ZW |
21276 | /* Link an unlinked unwind index table section to the .text section. */ |
21277 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
21278 | && elf_linked_to_section (now_seg) == NULL) | |
21279 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
21280 | } |
21281 | ||
c19d1205 ZW |
21282 | int |
21283 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 21284 | { |
c19d1205 ZW |
21285 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
21286 | return SHT_ARM_EXIDX; | |
e45d0630 | 21287 | |
c19d1205 ZW |
21288 | return -1; |
21289 | } | |
21290 | \f | |
21291 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 21292 | |
c19d1205 | 21293 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 21294 | |
5f4273c7 | 21295 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 21296 | |
bfae80f2 | 21297 | static void |
c19d1205 | 21298 | flush_pending_unwind (void) |
bfae80f2 | 21299 | { |
c19d1205 | 21300 | offsetT offset; |
bfae80f2 | 21301 | |
c19d1205 ZW |
21302 | offset = unwind.pending_offset; |
21303 | unwind.pending_offset = 0; | |
21304 | if (offset != 0) | |
21305 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
21306 | } |
21307 | ||
c19d1205 ZW |
21308 | /* Add an opcode to this list for this function. Two-byte opcodes should |
21309 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
21310 | order. */ | |
21311 | ||
bfae80f2 | 21312 | static void |
c19d1205 | 21313 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 21314 | { |
c19d1205 ZW |
21315 | /* Add any deferred stack adjustment. */ |
21316 | if (unwind.pending_offset) | |
21317 | flush_pending_unwind (); | |
bfae80f2 | 21318 | |
c19d1205 | 21319 | unwind.sp_restored = 0; |
bfae80f2 | 21320 | |
c19d1205 | 21321 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 21322 | { |
c19d1205 ZW |
21323 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
21324 | if (unwind.opcodes) | |
21d799b5 | 21325 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
477330fc | 21326 | unwind.opcode_alloc); |
c19d1205 | 21327 | else |
21d799b5 | 21328 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 21329 | } |
c19d1205 | 21330 | while (length > 0) |
bfae80f2 | 21331 | { |
c19d1205 ZW |
21332 | length--; |
21333 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
21334 | op >>= 8; | |
21335 | unwind.opcode_count++; | |
bfae80f2 | 21336 | } |
bfae80f2 RE |
21337 | } |
21338 | ||
c19d1205 ZW |
21339 | /* Add unwind opcodes to adjust the stack pointer. */ |
21340 | ||
bfae80f2 | 21341 | static void |
c19d1205 | 21342 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 21343 | { |
c19d1205 | 21344 | valueT op; |
bfae80f2 | 21345 | |
c19d1205 | 21346 | if (offset > 0x200) |
bfae80f2 | 21347 | { |
c19d1205 ZW |
21348 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
21349 | char bytes[5]; | |
21350 | int n; | |
21351 | valueT o; | |
bfae80f2 | 21352 | |
c19d1205 ZW |
21353 | /* Long form: 0xb2, uleb128. */ |
21354 | /* This might not fit in a word so add the individual bytes, | |
21355 | remembering the list is built in reverse order. */ | |
21356 | o = (valueT) ((offset - 0x204) >> 2); | |
21357 | if (o == 0) | |
21358 | add_unwind_opcode (0, 1); | |
bfae80f2 | 21359 | |
c19d1205 ZW |
21360 | /* Calculate the uleb128 encoding of the offset. */ |
21361 | n = 0; | |
21362 | while (o) | |
21363 | { | |
21364 | bytes[n] = o & 0x7f; | |
21365 | o >>= 7; | |
21366 | if (o) | |
21367 | bytes[n] |= 0x80; | |
21368 | n++; | |
21369 | } | |
21370 | /* Add the insn. */ | |
21371 | for (; n; n--) | |
21372 | add_unwind_opcode (bytes[n - 1], 1); | |
21373 | add_unwind_opcode (0xb2, 1); | |
21374 | } | |
21375 | else if (offset > 0x100) | |
bfae80f2 | 21376 | { |
c19d1205 ZW |
21377 | /* Two short opcodes. */ |
21378 | add_unwind_opcode (0x3f, 1); | |
21379 | op = (offset - 0x104) >> 2; | |
21380 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21381 | } |
c19d1205 ZW |
21382 | else if (offset > 0) |
21383 | { | |
21384 | /* Short opcode. */ | |
21385 | op = (offset - 4) >> 2; | |
21386 | add_unwind_opcode (op, 1); | |
21387 | } | |
21388 | else if (offset < 0) | |
bfae80f2 | 21389 | { |
c19d1205 ZW |
21390 | offset = -offset; |
21391 | while (offset > 0x100) | |
bfae80f2 | 21392 | { |
c19d1205 ZW |
21393 | add_unwind_opcode (0x7f, 1); |
21394 | offset -= 0x100; | |
bfae80f2 | 21395 | } |
c19d1205 ZW |
21396 | op = ((offset - 4) >> 2) | 0x40; |
21397 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21398 | } |
bfae80f2 RE |
21399 | } |
21400 | ||
c19d1205 ZW |
21401 | /* Finish the list of unwind opcodes for this function. */ |
21402 | static void | |
21403 | finish_unwind_opcodes (void) | |
bfae80f2 | 21404 | { |
c19d1205 | 21405 | valueT op; |
bfae80f2 | 21406 | |
c19d1205 | 21407 | if (unwind.fp_used) |
bfae80f2 | 21408 | { |
708587a4 | 21409 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
21410 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
21411 | flush_pending_unwind (); | |
bfae80f2 | 21412 | |
c19d1205 ZW |
21413 | /* After restoring sp from the frame pointer. */ |
21414 | op = 0x90 | unwind.fp_reg; | |
21415 | add_unwind_opcode (op, 1); | |
21416 | } | |
21417 | else | |
21418 | flush_pending_unwind (); | |
bfae80f2 RE |
21419 | } |
21420 | ||
bfae80f2 | 21421 | |
c19d1205 ZW |
21422 | /* Start an exception table entry. If idx is nonzero this is an index table |
21423 | entry. */ | |
bfae80f2 RE |
21424 | |
21425 | static void | |
c19d1205 | 21426 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 21427 | { |
c19d1205 ZW |
21428 | const char * text_name; |
21429 | const char * prefix; | |
21430 | const char * prefix_once; | |
21431 | const char * group_name; | |
21432 | size_t prefix_len; | |
21433 | size_t text_len; | |
21434 | char * sec_name; | |
21435 | size_t sec_name_len; | |
21436 | int type; | |
21437 | int flags; | |
21438 | int linkonce; | |
bfae80f2 | 21439 | |
c19d1205 | 21440 | if (idx) |
bfae80f2 | 21441 | { |
c19d1205 ZW |
21442 | prefix = ELF_STRING_ARM_unwind; |
21443 | prefix_once = ELF_STRING_ARM_unwind_once; | |
21444 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 21445 | } |
c19d1205 | 21446 | else |
bfae80f2 | 21447 | { |
c19d1205 ZW |
21448 | prefix = ELF_STRING_ARM_unwind_info; |
21449 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
21450 | type = SHT_PROGBITS; | |
bfae80f2 RE |
21451 | } |
21452 | ||
c19d1205 ZW |
21453 | text_name = segment_name (text_seg); |
21454 | if (streq (text_name, ".text")) | |
21455 | text_name = ""; | |
21456 | ||
21457 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
21458 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 21459 | { |
c19d1205 ZW |
21460 | prefix = prefix_once; |
21461 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
21462 | } |
21463 | ||
c19d1205 ZW |
21464 | prefix_len = strlen (prefix); |
21465 | text_len = strlen (text_name); | |
21466 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 21467 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
21468 | memcpy (sec_name, prefix, prefix_len); |
21469 | memcpy (sec_name + prefix_len, text_name, text_len); | |
21470 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 21471 | |
c19d1205 ZW |
21472 | flags = SHF_ALLOC; |
21473 | linkonce = 0; | |
21474 | group_name = 0; | |
bfae80f2 | 21475 | |
c19d1205 ZW |
21476 | /* Handle COMDAT group. */ |
21477 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 21478 | { |
c19d1205 ZW |
21479 | group_name = elf_group_name (text_seg); |
21480 | if (group_name == NULL) | |
21481 | { | |
bd3ba5d1 | 21482 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
21483 | segment_name (text_seg)); |
21484 | ignore_rest_of_line (); | |
21485 | return; | |
21486 | } | |
21487 | flags |= SHF_GROUP; | |
21488 | linkonce = 1; | |
bfae80f2 RE |
21489 | } |
21490 | ||
c19d1205 | 21491 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 21492 | |
5f4273c7 | 21493 | /* Set the section link for index tables. */ |
c19d1205 ZW |
21494 | if (idx) |
21495 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
21496 | } |
21497 | ||
bfae80f2 | 21498 | |
c19d1205 ZW |
21499 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
21500 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 21501 | an inline entry. */ |
c19d1205 ZW |
21502 | |
21503 | static valueT | |
21504 | create_unwind_entry (int have_data) | |
bfae80f2 | 21505 | { |
c19d1205 ZW |
21506 | int size; |
21507 | addressT where; | |
21508 | char *ptr; | |
21509 | /* The current word of data. */ | |
21510 | valueT data; | |
21511 | /* The number of bytes left in this word. */ | |
21512 | int n; | |
bfae80f2 | 21513 | |
c19d1205 | 21514 | finish_unwind_opcodes (); |
bfae80f2 | 21515 | |
c19d1205 ZW |
21516 | /* Remember the current text section. */ |
21517 | unwind.saved_seg = now_seg; | |
21518 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 21519 | |
c19d1205 | 21520 | start_unwind_section (now_seg, 0); |
bfae80f2 | 21521 | |
c19d1205 | 21522 | if (unwind.personality_routine == NULL) |
bfae80f2 | 21523 | { |
c19d1205 ZW |
21524 | if (unwind.personality_index == -2) |
21525 | { | |
21526 | if (have_data) | |
5f4273c7 | 21527 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
21528 | return 1; /* EXIDX_CANTUNWIND. */ |
21529 | } | |
bfae80f2 | 21530 | |
c19d1205 ZW |
21531 | /* Use a default personality routine if none is specified. */ |
21532 | if (unwind.personality_index == -1) | |
21533 | { | |
21534 | if (unwind.opcode_count > 3) | |
21535 | unwind.personality_index = 1; | |
21536 | else | |
21537 | unwind.personality_index = 0; | |
21538 | } | |
bfae80f2 | 21539 | |
c19d1205 ZW |
21540 | /* Space for the personality routine entry. */ |
21541 | if (unwind.personality_index == 0) | |
21542 | { | |
21543 | if (unwind.opcode_count > 3) | |
21544 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 21545 | |
c19d1205 ZW |
21546 | if (!have_data) |
21547 | { | |
21548 | /* All the data is inline in the index table. */ | |
21549 | data = 0x80; | |
21550 | n = 3; | |
21551 | while (unwind.opcode_count > 0) | |
21552 | { | |
21553 | unwind.opcode_count--; | |
21554 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21555 | n--; | |
21556 | } | |
bfae80f2 | 21557 | |
c19d1205 ZW |
21558 | /* Pad with "finish" opcodes. */ |
21559 | while (n--) | |
21560 | data = (data << 8) | 0xb0; | |
bfae80f2 | 21561 | |
c19d1205 ZW |
21562 | return data; |
21563 | } | |
21564 | size = 0; | |
21565 | } | |
21566 | else | |
21567 | /* We get two opcodes "free" in the first word. */ | |
21568 | size = unwind.opcode_count - 2; | |
21569 | } | |
21570 | else | |
5011093d | 21571 | { |
cad0da33 NC |
21572 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
21573 | if (unwind.personality_index != -1) | |
21574 | { | |
21575 | as_bad (_("attempt to recreate an unwind entry")); | |
21576 | return 1; | |
21577 | } | |
5011093d NC |
21578 | |
21579 | /* An extra byte is required for the opcode count. */ | |
21580 | size = unwind.opcode_count + 1; | |
21581 | } | |
bfae80f2 | 21582 | |
c19d1205 ZW |
21583 | size = (size + 3) >> 2; |
21584 | if (size > 0xff) | |
21585 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 21586 | |
c19d1205 ZW |
21587 | frag_align (2, 0, 0); |
21588 | record_alignment (now_seg, 2); | |
21589 | unwind.table_entry = expr_build_dot (); | |
21590 | ||
21591 | /* Allocate the table entry. */ | |
21592 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
21593 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
21594 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 21595 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 21596 | |
c19d1205 | 21597 | switch (unwind.personality_index) |
bfae80f2 | 21598 | { |
c19d1205 ZW |
21599 | case -1: |
21600 | /* ??? Should this be a PLT generating relocation? */ | |
21601 | /* Custom personality routine. */ | |
21602 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
21603 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 21604 | |
c19d1205 ZW |
21605 | where += 4; |
21606 | ptr += 4; | |
bfae80f2 | 21607 | |
c19d1205 | 21608 | /* Set the first byte to the number of additional words. */ |
5011093d | 21609 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
21610 | n = 3; |
21611 | break; | |
bfae80f2 | 21612 | |
c19d1205 ZW |
21613 | /* ABI defined personality routines. */ |
21614 | case 0: | |
21615 | /* Three opcodes bytes are packed into the first word. */ | |
21616 | data = 0x80; | |
21617 | n = 3; | |
21618 | break; | |
bfae80f2 | 21619 | |
c19d1205 ZW |
21620 | case 1: |
21621 | case 2: | |
21622 | /* The size and first two opcode bytes go in the first word. */ | |
21623 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
21624 | n = 2; | |
21625 | break; | |
bfae80f2 | 21626 | |
c19d1205 ZW |
21627 | default: |
21628 | /* Should never happen. */ | |
21629 | abort (); | |
21630 | } | |
bfae80f2 | 21631 | |
c19d1205 ZW |
21632 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
21633 | time. */ | |
21634 | while (unwind.opcode_count > 0) | |
21635 | { | |
21636 | if (n == 0) | |
21637 | { | |
21638 | md_number_to_chars (ptr, data, 4); | |
21639 | ptr += 4; | |
21640 | n = 4; | |
21641 | data = 0; | |
21642 | } | |
21643 | unwind.opcode_count--; | |
21644 | n--; | |
21645 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21646 | } | |
21647 | ||
21648 | /* Finish off the last word. */ | |
21649 | if (n < 4) | |
21650 | { | |
21651 | /* Pad with "finish" opcodes. */ | |
21652 | while (n--) | |
21653 | data = (data << 8) | 0xb0; | |
21654 | ||
21655 | md_number_to_chars (ptr, data, 4); | |
21656 | } | |
21657 | ||
21658 | if (!have_data) | |
21659 | { | |
21660 | /* Add an empty descriptor if there is no user-specified data. */ | |
21661 | ptr = frag_more (4); | |
21662 | md_number_to_chars (ptr, 0, 4); | |
21663 | } | |
21664 | ||
21665 | return 0; | |
bfae80f2 RE |
21666 | } |
21667 | ||
f0927246 NC |
21668 | |
21669 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
21670 | ||
21671 | void | |
21672 | tc_arm_frame_initial_instructions (void) | |
21673 | { | |
21674 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
21675 | } | |
21676 | #endif /* OBJ_ELF */ | |
21677 | ||
c19d1205 ZW |
21678 | /* Convert REGNAME to a DWARF-2 register number. */ |
21679 | ||
21680 | int | |
1df69f4f | 21681 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 21682 | { |
1df69f4f | 21683 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
21684 | if (reg != FAIL) |
21685 | return reg; | |
c19d1205 | 21686 | |
1f5afe1c NC |
21687 | /* PR 16694: Allow VFP registers as well. */ |
21688 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
21689 | if (reg != FAIL) | |
21690 | return 64 + reg; | |
c19d1205 | 21691 | |
1f5afe1c NC |
21692 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
21693 | if (reg != FAIL) | |
21694 | return reg + 256; | |
21695 | ||
21696 | return -1; | |
bfae80f2 RE |
21697 | } |
21698 | ||
f0927246 | 21699 | #ifdef TE_PE |
c19d1205 | 21700 | void |
f0927246 | 21701 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 21702 | { |
91d6fa6a | 21703 | expressionS exp; |
bfae80f2 | 21704 | |
91d6fa6a NC |
21705 | exp.X_op = O_secrel; |
21706 | exp.X_add_symbol = symbol; | |
21707 | exp.X_add_number = 0; | |
21708 | emit_expr (&exp, size); | |
f0927246 NC |
21709 | } |
21710 | #endif | |
bfae80f2 | 21711 | |
c19d1205 | 21712 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 21713 | |
2fc8bdac ZW |
21714 | /* Return the address within the segment that a PC-relative fixup is |
21715 | relative to. For ARM, PC-relative fixups applied to instructions | |
21716 | are generally relative to the location of the fixup plus 8 bytes. | |
21717 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
21718 | require special handling. */ | |
bfae80f2 | 21719 | |
c19d1205 | 21720 | long |
2fc8bdac | 21721 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 21722 | { |
2fc8bdac ZW |
21723 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
21724 | ||
21725 | /* If this is pc-relative and we are going to emit a relocation | |
21726 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
21727 | will need. Otherwise we want to use the calculated base. |
21728 | For WinCE we skip the bias for externals as well, since this | |
21729 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 21730 | if (fixP->fx_pcrel |
2fc8bdac | 21731 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
21732 | || (arm_force_relocation (fixP) |
21733 | #ifdef TE_WINCE | |
21734 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
21735 | #endif | |
21736 | ))) | |
2fc8bdac | 21737 | base = 0; |
bfae80f2 | 21738 | |
267bf995 | 21739 | |
c19d1205 | 21740 | switch (fixP->fx_r_type) |
bfae80f2 | 21741 | { |
2fc8bdac ZW |
21742 | /* PC relative addressing on the Thumb is slightly odd as the |
21743 | bottom two bits of the PC are forced to zero for the | |
21744 | calculation. This happens *after* application of the | |
21745 | pipeline offset. However, Thumb adrl already adjusts for | |
21746 | this, so we need not do it again. */ | |
c19d1205 | 21747 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 21748 | return base & ~3; |
c19d1205 ZW |
21749 | |
21750 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
21751 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 21752 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 21753 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 21754 | return (base + 4) & ~3; |
c19d1205 | 21755 | |
2fc8bdac ZW |
21756 | /* Thumb branches are simply offset by +4. */ |
21757 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21758 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21759 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21760 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 21761 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 21762 | return base + 4; |
bfae80f2 | 21763 | |
267bf995 | 21764 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
21765 | if (fixP->fx_addsy |
21766 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21767 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 21768 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
21769 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
21770 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
21771 | return base + 4; |
21772 | ||
00adf2d4 JB |
21773 | /* BLX is like branches above, but forces the low two bits of PC to |
21774 | zero. */ | |
486499d0 CL |
21775 | case BFD_RELOC_THUMB_PCREL_BLX: |
21776 | if (fixP->fx_addsy | |
21777 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21778 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21779 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21780 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21781 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
21782 | return (base + 4) & ~3; |
21783 | ||
2fc8bdac ZW |
21784 | /* ARM mode branches are offset by +8. However, the Windows CE |
21785 | loader expects the relocation not to take this into account. */ | |
267bf995 | 21786 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
21787 | if (fixP->fx_addsy |
21788 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21789 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21790 | && ARM_IS_FUNC (fixP->fx_addsy) |
21791 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21792 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21793 | return base + 8; |
267bf995 | 21794 | |
486499d0 CL |
21795 | case BFD_RELOC_ARM_PCREL_CALL: |
21796 | if (fixP->fx_addsy | |
21797 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21798 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21799 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21800 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21801 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21802 | return base + 8; |
267bf995 | 21803 | |
2fc8bdac | 21804 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 21805 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 21806 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 21807 | #ifdef TE_WINCE |
5f4273c7 | 21808 | /* When handling fixups immediately, because we have already |
477330fc | 21809 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 21810 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
21811 | see fixup_segment() in write.c |
21812 | The S_IS_EXTERNAL test handles the case of global symbols. | |
21813 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
21814 | if (fixP->fx_pcrel |
21815 | && fixP->fx_addsy != NULL | |
21816 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
21817 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
21818 | return base + 8; | |
2fc8bdac | 21819 | return base; |
c19d1205 | 21820 | #else |
2fc8bdac | 21821 | return base + 8; |
c19d1205 | 21822 | #endif |
2fc8bdac | 21823 | |
267bf995 | 21824 | |
2fc8bdac ZW |
21825 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
21826 | branches, the Windows CE loader *does* expect the relocation | |
21827 | to take this into account. */ | |
21828 | case BFD_RELOC_ARM_OFFSET_IMM: | |
21829 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
21830 | case BFD_RELOC_ARM_HWLITERAL: | |
21831 | case BFD_RELOC_ARM_LITERAL: | |
21832 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
21833 | return base + 8; | |
21834 | ||
21835 | ||
21836 | /* Other PC-relative relocations are un-offset. */ | |
21837 | default: | |
21838 | return base; | |
21839 | } | |
bfae80f2 RE |
21840 | } |
21841 | ||
8b2d793c NC |
21842 | static bfd_boolean flag_warn_syms = TRUE; |
21843 | ||
ae8714c2 NC |
21844 | bfd_boolean |
21845 | arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name) | |
bfae80f2 | 21846 | { |
8b2d793c NC |
21847 | /* PR 18347 - Warn if the user attempts to create a symbol with the same |
21848 | name as an ARM instruction. Whilst strictly speaking it is allowed, it | |
21849 | does mean that the resulting code might be very confusing to the reader. | |
21850 | Also this warning can be triggered if the user omits an operand before | |
21851 | an immediate address, eg: | |
21852 | ||
21853 | LDR =foo | |
21854 | ||
21855 | GAS treats this as an assignment of the value of the symbol foo to a | |
21856 | symbol LDR, and so (without this code) it will not issue any kind of | |
21857 | warning or error message. | |
21858 | ||
21859 | Note - ARM instructions are case-insensitive but the strings in the hash | |
21860 | table are all stored in lower case, so we must first ensure that name is | |
ae8714c2 NC |
21861 | lower case too. */ |
21862 | if (flag_warn_syms && arm_ops_hsh) | |
8b2d793c NC |
21863 | { |
21864 | char * nbuf = strdup (name); | |
21865 | char * p; | |
21866 | ||
21867 | for (p = nbuf; *p; p++) | |
21868 | *p = TOLOWER (*p); | |
21869 | if (hash_find (arm_ops_hsh, nbuf) != NULL) | |
21870 | { | |
21871 | static struct hash_control * already_warned = NULL; | |
21872 | ||
21873 | if (already_warned == NULL) | |
21874 | already_warned = hash_new (); | |
21875 | /* Only warn about the symbol once. To keep the code | |
21876 | simple we let hash_insert do the lookup for us. */ | |
21877 | if (hash_insert (already_warned, name, NULL) == NULL) | |
ae8714c2 | 21878 | as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name); |
8b2d793c NC |
21879 | } |
21880 | else | |
21881 | free (nbuf); | |
21882 | } | |
21883 | ||
ae8714c2 NC |
21884 | return FALSE; |
21885 | } | |
21886 | ||
21887 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
21888 | Otherwise we have no need to default values of symbols. */ | |
21889 | ||
21890 | symbolS * | |
21891 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
21892 | { | |
21893 | #ifdef OBJ_ELF | |
21894 | if (name[0] == '_' && name[1] == 'G' | |
21895 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
21896 | { | |
21897 | if (!GOT_symbol) | |
21898 | { | |
21899 | if (symbol_find (name)) | |
21900 | as_bad (_("GOT already in the symbol table")); | |
21901 | ||
21902 | GOT_symbol = symbol_new (name, undefined_section, | |
21903 | (valueT) 0, & zero_address_frag); | |
21904 | } | |
21905 | ||
21906 | return GOT_symbol; | |
21907 | } | |
21908 | #endif | |
21909 | ||
c921be7d | 21910 | return NULL; |
bfae80f2 RE |
21911 | } |
21912 | ||
55cf6793 | 21913 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
21914 | computed as two separate immediate values, added together. We |
21915 | already know that this value cannot be computed by just one ARM | |
21916 | instruction. */ | |
21917 | ||
21918 | static unsigned int | |
21919 | validate_immediate_twopart (unsigned int val, | |
21920 | unsigned int * highpart) | |
bfae80f2 | 21921 | { |
c19d1205 ZW |
21922 | unsigned int a; |
21923 | unsigned int i; | |
bfae80f2 | 21924 | |
c19d1205 ZW |
21925 | for (i = 0; i < 32; i += 2) |
21926 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
21927 | { | |
21928 | if (a & 0xff00) | |
21929 | { | |
21930 | if (a & ~ 0xffff) | |
21931 | continue; | |
21932 | * highpart = (a >> 8) | ((i + 24) << 7); | |
21933 | } | |
21934 | else if (a & 0xff0000) | |
21935 | { | |
21936 | if (a & 0xff000000) | |
21937 | continue; | |
21938 | * highpart = (a >> 16) | ((i + 16) << 7); | |
21939 | } | |
21940 | else | |
21941 | { | |
9c2799c2 | 21942 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
21943 | * highpart = (a >> 24) | ((i + 8) << 7); |
21944 | } | |
bfae80f2 | 21945 | |
c19d1205 ZW |
21946 | return (a & 0xff) | (i << 7); |
21947 | } | |
bfae80f2 | 21948 | |
c19d1205 | 21949 | return FAIL; |
bfae80f2 RE |
21950 | } |
21951 | ||
c19d1205 ZW |
21952 | static int |
21953 | validate_offset_imm (unsigned int val, int hwse) | |
21954 | { | |
21955 | if ((hwse && val > 255) || val > 4095) | |
21956 | return FAIL; | |
21957 | return val; | |
21958 | } | |
bfae80f2 | 21959 | |
55cf6793 | 21960 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
21961 | negative immediate constant by altering the instruction. A bit of |
21962 | a hack really. | |
21963 | MOV <-> MVN | |
21964 | AND <-> BIC | |
21965 | ADC <-> SBC | |
21966 | by inverting the second operand, and | |
21967 | ADD <-> SUB | |
21968 | CMP <-> CMN | |
21969 | by negating the second operand. */ | |
bfae80f2 | 21970 | |
c19d1205 ZW |
21971 | static int |
21972 | negate_data_op (unsigned long * instruction, | |
21973 | unsigned long value) | |
bfae80f2 | 21974 | { |
c19d1205 ZW |
21975 | int op, new_inst; |
21976 | unsigned long negated, inverted; | |
bfae80f2 | 21977 | |
c19d1205 ZW |
21978 | negated = encode_arm_immediate (-value); |
21979 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 21980 | |
c19d1205 ZW |
21981 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
21982 | switch (op) | |
bfae80f2 | 21983 | { |
c19d1205 ZW |
21984 | /* First negates. */ |
21985 | case OPCODE_SUB: /* ADD <-> SUB */ | |
21986 | new_inst = OPCODE_ADD; | |
21987 | value = negated; | |
21988 | break; | |
bfae80f2 | 21989 | |
c19d1205 ZW |
21990 | case OPCODE_ADD: |
21991 | new_inst = OPCODE_SUB; | |
21992 | value = negated; | |
21993 | break; | |
bfae80f2 | 21994 | |
c19d1205 ZW |
21995 | case OPCODE_CMP: /* CMP <-> CMN */ |
21996 | new_inst = OPCODE_CMN; | |
21997 | value = negated; | |
21998 | break; | |
bfae80f2 | 21999 | |
c19d1205 ZW |
22000 | case OPCODE_CMN: |
22001 | new_inst = OPCODE_CMP; | |
22002 | value = negated; | |
22003 | break; | |
bfae80f2 | 22004 | |
c19d1205 ZW |
22005 | /* Now Inverted ops. */ |
22006 | case OPCODE_MOV: /* MOV <-> MVN */ | |
22007 | new_inst = OPCODE_MVN; | |
22008 | value = inverted; | |
22009 | break; | |
bfae80f2 | 22010 | |
c19d1205 ZW |
22011 | case OPCODE_MVN: |
22012 | new_inst = OPCODE_MOV; | |
22013 | value = inverted; | |
22014 | break; | |
bfae80f2 | 22015 | |
c19d1205 ZW |
22016 | case OPCODE_AND: /* AND <-> BIC */ |
22017 | new_inst = OPCODE_BIC; | |
22018 | value = inverted; | |
22019 | break; | |
bfae80f2 | 22020 | |
c19d1205 ZW |
22021 | case OPCODE_BIC: |
22022 | new_inst = OPCODE_AND; | |
22023 | value = inverted; | |
22024 | break; | |
bfae80f2 | 22025 | |
c19d1205 ZW |
22026 | case OPCODE_ADC: /* ADC <-> SBC */ |
22027 | new_inst = OPCODE_SBC; | |
22028 | value = inverted; | |
22029 | break; | |
bfae80f2 | 22030 | |
c19d1205 ZW |
22031 | case OPCODE_SBC: |
22032 | new_inst = OPCODE_ADC; | |
22033 | value = inverted; | |
22034 | break; | |
bfae80f2 | 22035 | |
c19d1205 ZW |
22036 | /* We cannot do anything. */ |
22037 | default: | |
22038 | return FAIL; | |
b99bd4ef NC |
22039 | } |
22040 | ||
c19d1205 ZW |
22041 | if (value == (unsigned) FAIL) |
22042 | return FAIL; | |
22043 | ||
22044 | *instruction &= OPCODE_MASK; | |
22045 | *instruction |= new_inst << DATA_OP_SHIFT; | |
22046 | return value; | |
b99bd4ef NC |
22047 | } |
22048 | ||
ef8d22e6 PB |
22049 | /* Like negate_data_op, but for Thumb-2. */ |
22050 | ||
22051 | static unsigned int | |
16dd5e42 | 22052 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
22053 | { |
22054 | int op, new_inst; | |
22055 | int rd; | |
16dd5e42 | 22056 | unsigned int negated, inverted; |
ef8d22e6 PB |
22057 | |
22058 | negated = encode_thumb32_immediate (-value); | |
22059 | inverted = encode_thumb32_immediate (~value); | |
22060 | ||
22061 | rd = (*instruction >> 8) & 0xf; | |
22062 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
22063 | switch (op) | |
22064 | { | |
22065 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
22066 | case T2_OPCODE_SUB: | |
22067 | new_inst = T2_OPCODE_ADD; | |
22068 | value = negated; | |
22069 | break; | |
22070 | ||
22071 | case T2_OPCODE_ADD: | |
22072 | new_inst = T2_OPCODE_SUB; | |
22073 | value = negated; | |
22074 | break; | |
22075 | ||
22076 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
22077 | case T2_OPCODE_ORR: | |
22078 | new_inst = T2_OPCODE_ORN; | |
22079 | value = inverted; | |
22080 | break; | |
22081 | ||
22082 | case T2_OPCODE_ORN: | |
22083 | new_inst = T2_OPCODE_ORR; | |
22084 | value = inverted; | |
22085 | break; | |
22086 | ||
22087 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
22088 | case T2_OPCODE_AND: | |
22089 | new_inst = T2_OPCODE_BIC; | |
22090 | if (rd == 15) | |
22091 | value = FAIL; | |
22092 | else | |
22093 | value = inverted; | |
22094 | break; | |
22095 | ||
22096 | case T2_OPCODE_BIC: | |
22097 | new_inst = T2_OPCODE_AND; | |
22098 | value = inverted; | |
22099 | break; | |
22100 | ||
22101 | /* ADC <-> SBC */ | |
22102 | case T2_OPCODE_ADC: | |
22103 | new_inst = T2_OPCODE_SBC; | |
22104 | value = inverted; | |
22105 | break; | |
22106 | ||
22107 | case T2_OPCODE_SBC: | |
22108 | new_inst = T2_OPCODE_ADC; | |
22109 | value = inverted; | |
22110 | break; | |
22111 | ||
22112 | /* We cannot do anything. */ | |
22113 | default: | |
22114 | return FAIL; | |
22115 | } | |
22116 | ||
16dd5e42 | 22117 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
22118 | return FAIL; |
22119 | ||
22120 | *instruction &= T2_OPCODE_MASK; | |
22121 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
22122 | return value; | |
22123 | } | |
22124 | ||
8f06b2d8 PB |
22125 | /* Read a 32-bit thumb instruction from buf. */ |
22126 | static unsigned long | |
22127 | get_thumb32_insn (char * buf) | |
22128 | { | |
22129 | unsigned long insn; | |
22130 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
22131 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22132 | ||
22133 | return insn; | |
22134 | } | |
22135 | ||
a8bc6c78 PB |
22136 | |
22137 | /* We usually want to set the low bit on the address of thumb function | |
22138 | symbols. In particular .word foo - . should have the low bit set. | |
22139 | Generic code tries to fold the difference of two symbols to | |
22140 | a constant. Prevent this and force a relocation when the first symbols | |
22141 | is a thumb function. */ | |
c921be7d NC |
22142 | |
22143 | bfd_boolean | |
a8bc6c78 PB |
22144 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
22145 | { | |
22146 | if (op == O_subtract | |
22147 | && l->X_op == O_symbol | |
22148 | && r->X_op == O_symbol | |
22149 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
22150 | { | |
22151 | l->X_op = O_subtract; | |
22152 | l->X_op_symbol = r->X_add_symbol; | |
22153 | l->X_add_number -= r->X_add_number; | |
c921be7d | 22154 | return TRUE; |
a8bc6c78 | 22155 | } |
c921be7d | 22156 | |
a8bc6c78 | 22157 | /* Process as normal. */ |
c921be7d | 22158 | return FALSE; |
a8bc6c78 PB |
22159 | } |
22160 | ||
4a42ebbc RR |
22161 | /* Encode Thumb2 unconditional branches and calls. The encoding |
22162 | for the 2 are identical for the immediate values. */ | |
22163 | ||
22164 | static void | |
22165 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
22166 | { | |
22167 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
22168 | offsetT newval; | |
22169 | offsetT newval2; | |
22170 | addressT S, I1, I2, lo, hi; | |
22171 | ||
22172 | S = (value >> 24) & 0x01; | |
22173 | I1 = (value >> 23) & 0x01; | |
22174 | I2 = (value >> 22) & 0x01; | |
22175 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 22176 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
22177 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22178 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22179 | newval |= (S << 10) | hi; | |
22180 | newval2 &= ~T2I1I2MASK; | |
22181 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
22182 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22183 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
22184 | } | |
22185 | ||
c19d1205 | 22186 | void |
55cf6793 | 22187 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
22188 | valueT * valP, |
22189 | segT seg) | |
22190 | { | |
22191 | offsetT value = * valP; | |
22192 | offsetT newval; | |
22193 | unsigned int newimm; | |
22194 | unsigned long temp; | |
22195 | int sign; | |
22196 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 22197 | |
9c2799c2 | 22198 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 22199 | |
c19d1205 | 22200 | /* Note whether this will delete the relocation. */ |
4962c51a | 22201 | |
c19d1205 ZW |
22202 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
22203 | fixP->fx_done = 1; | |
b99bd4ef | 22204 | |
adbaf948 | 22205 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 22206 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
22207 | for emit_reloc. */ |
22208 | value &= 0xffffffff; | |
22209 | value ^= 0x80000000; | |
5f4273c7 | 22210 | value -= 0x80000000; |
adbaf948 ZW |
22211 | |
22212 | *valP = value; | |
c19d1205 | 22213 | fixP->fx_addnumber = value; |
b99bd4ef | 22214 | |
adbaf948 ZW |
22215 | /* Same treatment for fixP->fx_offset. */ |
22216 | fixP->fx_offset &= 0xffffffff; | |
22217 | fixP->fx_offset ^= 0x80000000; | |
22218 | fixP->fx_offset -= 0x80000000; | |
22219 | ||
c19d1205 | 22220 | switch (fixP->fx_r_type) |
b99bd4ef | 22221 | { |
c19d1205 ZW |
22222 | case BFD_RELOC_NONE: |
22223 | /* This will need to go in the object file. */ | |
22224 | fixP->fx_done = 0; | |
22225 | break; | |
b99bd4ef | 22226 | |
c19d1205 ZW |
22227 | case BFD_RELOC_ARM_IMMEDIATE: |
22228 | /* We claim that this fixup has been processed here, | |
22229 | even if in fact we generate an error because we do | |
22230 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
22231 | fixP->fx_done = 1; | |
b99bd4ef | 22232 | |
77db8e2e | 22233 | if (fixP->fx_addsy) |
b99bd4ef | 22234 | { |
77db8e2e | 22235 | const char *msg = 0; |
b99bd4ef | 22236 | |
77db8e2e NC |
22237 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
22238 | msg = _("undefined symbol %s used as an immediate value"); | |
22239 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
22240 | msg = _("symbol %s is in a different section"); | |
22241 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
22242 | msg = _("symbol %s is weak and may be overridden later"); | |
22243 | ||
22244 | if (msg) | |
22245 | { | |
22246 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22247 | msg, S_GET_NAME (fixP->fx_addsy)); | |
22248 | break; | |
22249 | } | |
42e5fcbf AS |
22250 | } |
22251 | ||
c19d1205 ZW |
22252 | temp = md_chars_to_number (buf, INSN_SIZE); |
22253 | ||
5e73442d SL |
22254 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
22255 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
22256 | newimm = negate_data_op (&temp, value); | |
22257 | else | |
22258 | { | |
22259 | newimm = encode_arm_immediate (value); | |
22260 | ||
22261 | /* If the instruction will fail, see if we can fix things up by | |
22262 | changing the opcode. */ | |
22263 | if (newimm == (unsigned int) FAIL) | |
22264 | newimm = negate_data_op (&temp, value); | |
22265 | } | |
22266 | ||
22267 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 22268 | { |
c19d1205 ZW |
22269 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22270 | _("invalid constant (%lx) after fixup"), | |
22271 | (unsigned long) value); | |
22272 | break; | |
b99bd4ef | 22273 | } |
b99bd4ef | 22274 | |
c19d1205 ZW |
22275 | newimm |= (temp & 0xfffff000); |
22276 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
22277 | break; | |
b99bd4ef | 22278 | |
c19d1205 ZW |
22279 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
22280 | { | |
22281 | unsigned int highpart = 0; | |
22282 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 22283 | |
77db8e2e | 22284 | if (fixP->fx_addsy) |
42e5fcbf | 22285 | { |
77db8e2e | 22286 | const char *msg = 0; |
42e5fcbf | 22287 | |
77db8e2e NC |
22288 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
22289 | msg = _("undefined symbol %s used as an immediate value"); | |
22290 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
22291 | msg = _("symbol %s is in a different section"); | |
22292 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
22293 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 22294 | |
77db8e2e NC |
22295 | if (msg) |
22296 | { | |
22297 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22298 | msg, S_GET_NAME (fixP->fx_addsy)); | |
22299 | break; | |
22300 | } | |
22301 | } | |
fa94de6b | 22302 | |
c19d1205 ZW |
22303 | newimm = encode_arm_immediate (value); |
22304 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 22305 | |
c19d1205 ZW |
22306 | /* If the instruction will fail, see if we can fix things up by |
22307 | changing the opcode. */ | |
22308 | if (newimm == (unsigned int) FAIL | |
22309 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
22310 | { | |
22311 | /* No ? OK - try using two ADD instructions to generate | |
22312 | the value. */ | |
22313 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 22314 | |
c19d1205 ZW |
22315 | /* Yes - then make sure that the second instruction is |
22316 | also an add. */ | |
22317 | if (newimm != (unsigned int) FAIL) | |
22318 | newinsn = temp; | |
22319 | /* Still No ? Try using a negated value. */ | |
22320 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
22321 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
22322 | /* Otherwise - give up. */ | |
22323 | else | |
22324 | { | |
22325 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22326 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
22327 | (long) value); | |
22328 | break; | |
22329 | } | |
b99bd4ef | 22330 | |
c19d1205 ZW |
22331 | /* Replace the first operand in the 2nd instruction (which |
22332 | is the PC) with the destination register. We have | |
22333 | already added in the PC in the first instruction and we | |
22334 | do not want to do it again. */ | |
22335 | newinsn &= ~ 0xf0000; | |
22336 | newinsn |= ((newinsn & 0x0f000) << 4); | |
22337 | } | |
b99bd4ef | 22338 | |
c19d1205 ZW |
22339 | newimm |= (temp & 0xfffff000); |
22340 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 22341 | |
c19d1205 ZW |
22342 | highpart |= (newinsn & 0xfffff000); |
22343 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
22344 | } | |
22345 | break; | |
b99bd4ef | 22346 | |
c19d1205 | 22347 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
22348 | if (!fixP->fx_done && seg->use_rela_p) |
22349 | value = 0; | |
22350 | ||
c19d1205 | 22351 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 22352 | sign = value > 0; |
b99bd4ef | 22353 | |
c19d1205 ZW |
22354 | if (value < 0) |
22355 | value = - value; | |
b99bd4ef | 22356 | |
c19d1205 | 22357 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 22358 | { |
c19d1205 ZW |
22359 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
22360 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22361 | _("invalid literal constant: pool needs to be closer")); | |
22362 | else | |
22363 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22364 | _("bad immediate value for offset (%ld)"), | |
22365 | (long) value); | |
22366 | break; | |
f03698e6 RE |
22367 | } |
22368 | ||
c19d1205 | 22369 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22370 | if (value == 0) |
22371 | newval &= 0xfffff000; | |
22372 | else | |
22373 | { | |
22374 | newval &= 0xff7ff000; | |
22375 | newval |= value | (sign ? INDEX_UP : 0); | |
22376 | } | |
c19d1205 ZW |
22377 | md_number_to_chars (buf, newval, INSN_SIZE); |
22378 | break; | |
b99bd4ef | 22379 | |
c19d1205 ZW |
22380 | case BFD_RELOC_ARM_OFFSET_IMM8: |
22381 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 22382 | sign = value > 0; |
b99bd4ef | 22383 | |
c19d1205 ZW |
22384 | if (value < 0) |
22385 | value = - value; | |
b99bd4ef | 22386 | |
c19d1205 | 22387 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 22388 | { |
c19d1205 ZW |
22389 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
22390 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22391 | _("invalid literal constant: pool needs to be closer")); | |
22392 | else | |
427d0db6 RM |
22393 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22394 | _("bad immediate value for 8-bit offset (%ld)"), | |
22395 | (long) value); | |
c19d1205 | 22396 | break; |
b99bd4ef NC |
22397 | } |
22398 | ||
c19d1205 | 22399 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22400 | if (value == 0) |
22401 | newval &= 0xfffff0f0; | |
22402 | else | |
22403 | { | |
22404 | newval &= 0xff7ff0f0; | |
22405 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
22406 | } | |
c19d1205 ZW |
22407 | md_number_to_chars (buf, newval, INSN_SIZE); |
22408 | break; | |
b99bd4ef | 22409 | |
c19d1205 ZW |
22410 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
22411 | if (value < 0 || value > 1020 || value % 4 != 0) | |
22412 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22413 | _("bad immediate value for offset (%ld)"), (long) value); | |
22414 | value /= 4; | |
b99bd4ef | 22415 | |
c19d1205 | 22416 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
22417 | newval |= value; |
22418 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
22419 | break; | |
b99bd4ef | 22420 | |
c19d1205 ZW |
22421 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
22422 | /* This is a complicated relocation used for all varieties of Thumb32 | |
22423 | load/store instruction with immediate offset: | |
22424 | ||
22425 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 22426 | *4, optional writeback(W) |
c19d1205 ZW |
22427 | (doubleword load/store) |
22428 | ||
22429 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
22430 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
22431 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
22432 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
22433 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
22434 | ||
22435 | Uppercase letters indicate bits that are already encoded at | |
22436 | this point. Lowercase letters are our problem. For the | |
22437 | second block of instructions, the secondary opcode nybble | |
22438 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
22439 | a PC-relative operation. */ | |
22440 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22441 | newval <<= 16; | |
22442 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 22443 | |
c19d1205 | 22444 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 22445 | { |
c19d1205 ZW |
22446 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
22447 | if (value >= 0) | |
22448 | newval |= (1 << 23); | |
22449 | else | |
22450 | value = -value; | |
22451 | if (value % 4 != 0) | |
22452 | { | |
22453 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22454 | _("offset not a multiple of 4")); | |
22455 | break; | |
22456 | } | |
22457 | value /= 4; | |
216d22bc | 22458 | if (value > 0xff) |
c19d1205 ZW |
22459 | { |
22460 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22461 | _("offset out of range")); | |
22462 | break; | |
22463 | } | |
22464 | newval &= ~0xff; | |
b99bd4ef | 22465 | } |
c19d1205 | 22466 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 22467 | { |
c19d1205 ZW |
22468 | /* PC-relative, 12-bit offset. */ |
22469 | if (value >= 0) | |
22470 | newval |= (1 << 23); | |
22471 | else | |
22472 | value = -value; | |
216d22bc | 22473 | if (value > 0xfff) |
c19d1205 ZW |
22474 | { |
22475 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22476 | _("offset out of range")); | |
22477 | break; | |
22478 | } | |
22479 | newval &= ~0xfff; | |
b99bd4ef | 22480 | } |
c19d1205 | 22481 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 22482 | { |
c19d1205 ZW |
22483 | /* Writeback: 8-bit, +/- offset. */ |
22484 | if (value >= 0) | |
22485 | newval |= (1 << 9); | |
22486 | else | |
22487 | value = -value; | |
216d22bc | 22488 | if (value > 0xff) |
c19d1205 ZW |
22489 | { |
22490 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22491 | _("offset out of range")); | |
22492 | break; | |
22493 | } | |
22494 | newval &= ~0xff; | |
b99bd4ef | 22495 | } |
c19d1205 | 22496 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 22497 | { |
c19d1205 | 22498 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 22499 | if (value < 0 || value > 0xff) |
b99bd4ef | 22500 | { |
c19d1205 ZW |
22501 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22502 | _("offset out of range")); | |
22503 | break; | |
b99bd4ef | 22504 | } |
c19d1205 ZW |
22505 | newval &= ~0xff; |
22506 | newval |= value; | |
b99bd4ef NC |
22507 | } |
22508 | else | |
b99bd4ef | 22509 | { |
c19d1205 ZW |
22510 | /* Positive 12-bit or negative 8-bit offset. */ |
22511 | int limit; | |
22512 | if (value >= 0) | |
b99bd4ef | 22513 | { |
c19d1205 ZW |
22514 | newval |= (1 << 23); |
22515 | limit = 0xfff; | |
22516 | } | |
22517 | else | |
22518 | { | |
22519 | value = -value; | |
22520 | limit = 0xff; | |
22521 | } | |
22522 | if (value > limit) | |
22523 | { | |
22524 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22525 | _("offset out of range")); | |
22526 | break; | |
b99bd4ef | 22527 | } |
c19d1205 | 22528 | newval &= ~limit; |
b99bd4ef | 22529 | } |
b99bd4ef | 22530 | |
c19d1205 ZW |
22531 | newval |= value; |
22532 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
22533 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
22534 | break; | |
404ff6b5 | 22535 | |
c19d1205 ZW |
22536 | case BFD_RELOC_ARM_SHIFT_IMM: |
22537 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22538 | if (((unsigned long) value) > 32 | |
22539 | || (value == 32 | |
22540 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
22541 | { | |
22542 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22543 | _("shift expression is too large")); | |
22544 | break; | |
22545 | } | |
404ff6b5 | 22546 | |
c19d1205 ZW |
22547 | if (value == 0) |
22548 | /* Shifts of zero must be done as lsl. */ | |
22549 | newval &= ~0x60; | |
22550 | else if (value == 32) | |
22551 | value = 0; | |
22552 | newval &= 0xfffff07f; | |
22553 | newval |= (value & 0x1f) << 7; | |
22554 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22555 | break; | |
404ff6b5 | 22556 | |
c19d1205 | 22557 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 22558 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 22559 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 22560 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
22561 | /* We claim that this fixup has been processed here, |
22562 | even if in fact we generate an error because we do | |
22563 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
22564 | fixP->fx_done = 1; | |
404ff6b5 | 22565 | |
c19d1205 ZW |
22566 | if (fixP->fx_addsy |
22567 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
22568 | { | |
22569 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22570 | _("undefined symbol %s used as an immediate value"), | |
22571 | S_GET_NAME (fixP->fx_addsy)); | |
22572 | break; | |
22573 | } | |
404ff6b5 | 22574 | |
c19d1205 ZW |
22575 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22576 | newval <<= 16; | |
22577 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 22578 | |
16805f35 PB |
22579 | newimm = FAIL; |
22580 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
22581 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
22582 | { |
22583 | newimm = encode_thumb32_immediate (value); | |
22584 | if (newimm == (unsigned int) FAIL) | |
22585 | newimm = thumb32_negate_data_op (&newval, value); | |
22586 | } | |
16805f35 PB |
22587 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
22588 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 22589 | { |
16805f35 PB |
22590 | /* Turn add/sum into addw/subw. */ |
22591 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
22592 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
22593 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
22594 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 22595 | { |
40f246e3 NC |
22596 | /* 12 bit immediate for addw/subw. */ |
22597 | if (value < 0) | |
22598 | { | |
22599 | value = -value; | |
22600 | newval ^= 0x00a00000; | |
22601 | } | |
22602 | if (value > 0xfff) | |
22603 | newimm = (unsigned int) FAIL; | |
22604 | else | |
22605 | newimm = value; | |
e9f89963 | 22606 | } |
92e90b6e | 22607 | } |
cc8a6dd0 | 22608 | |
c19d1205 | 22609 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 22610 | { |
c19d1205 ZW |
22611 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22612 | _("invalid constant (%lx) after fixup"), | |
22613 | (unsigned long) value); | |
22614 | break; | |
3631a3c8 NC |
22615 | } |
22616 | ||
c19d1205 ZW |
22617 | newval |= (newimm & 0x800) << 15; |
22618 | newval |= (newimm & 0x700) << 4; | |
22619 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 22620 | |
c19d1205 ZW |
22621 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
22622 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
22623 | break; | |
a737bd4d | 22624 | |
3eb17e6b | 22625 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
22626 | if (((unsigned long) value) > 0xffff) |
22627 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 22628 | _("invalid smc expression")); |
2fc8bdac | 22629 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22630 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
22631 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22632 | break; | |
a737bd4d | 22633 | |
90ec0d68 MGD |
22634 | case BFD_RELOC_ARM_HVC: |
22635 | if (((unsigned long) value) > 0xffff) | |
22636 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22637 | _("invalid hvc expression")); | |
22638 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22639 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
22640 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22641 | break; | |
22642 | ||
c19d1205 | 22643 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 22644 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
22645 | { |
22646 | if (((unsigned long) value) > 0xff) | |
22647 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22648 | _("invalid swi expression")); | |
2fc8bdac | 22649 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
22650 | newval |= value; |
22651 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22652 | } | |
22653 | else | |
22654 | { | |
22655 | if (((unsigned long) value) > 0x00ffffff) | |
22656 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22657 | _("invalid swi expression")); | |
2fc8bdac | 22658 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22659 | newval |= value; |
22660 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22661 | } | |
22662 | break; | |
a737bd4d | 22663 | |
c19d1205 ZW |
22664 | case BFD_RELOC_ARM_MULTI: |
22665 | if (((unsigned long) value) > 0xffff) | |
22666 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22667 | _("invalid expression in load/store multiple")); | |
22668 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
22669 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22670 | break; | |
a737bd4d | 22671 | |
c19d1205 | 22672 | #ifdef OBJ_ELF |
39b41c9c | 22673 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
22674 | |
22675 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
22676 | && fixP->fx_addsy | |
34e77a92 | 22677 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22678 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22679 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22680 | /* Flip the bl to blx. This is a simple flip | |
22681 | bit here because we generate PCREL_CALL for | |
22682 | unconditional bls. */ | |
22683 | { | |
22684 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22685 | newval = newval | 0x10000000; | |
22686 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22687 | temp = 1; | |
22688 | fixP->fx_done = 1; | |
22689 | } | |
39b41c9c PB |
22690 | else |
22691 | temp = 3; | |
22692 | goto arm_branch_common; | |
22693 | ||
22694 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
22695 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22696 | && fixP->fx_addsy | |
34e77a92 | 22697 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22698 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22699 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22700 | { | |
22701 | /* This would map to a bl<cond>, b<cond>, | |
22702 | b<always> to a Thumb function. We | |
22703 | need to force a relocation for this particular | |
22704 | case. */ | |
22705 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22706 | fixP->fx_done = 0; | |
22707 | } | |
22708 | ||
2fc8bdac | 22709 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 22710 | #endif |
39b41c9c PB |
22711 | case BFD_RELOC_ARM_PCREL_BRANCH: |
22712 | temp = 3; | |
22713 | goto arm_branch_common; | |
a737bd4d | 22714 | |
39b41c9c | 22715 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 22716 | |
39b41c9c | 22717 | temp = 1; |
267bf995 RR |
22718 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22719 | && fixP->fx_addsy | |
34e77a92 | 22720 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22721 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22722 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
22723 | { | |
22724 | /* Flip the blx to a bl and warn. */ | |
22725 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22726 | newval = 0xeb000000; | |
22727 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22728 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
22729 | name); | |
22730 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22731 | temp = 3; | |
22732 | fixP->fx_done = 1; | |
22733 | } | |
22734 | ||
22735 | #ifdef OBJ_ELF | |
22736 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 22737 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
22738 | #endif |
22739 | ||
39b41c9c | 22740 | arm_branch_common: |
c19d1205 | 22741 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
22742 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
22743 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
22744 | also be be clear. */ | |
22745 | if (value & temp) | |
c19d1205 | 22746 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
22747 | _("misaligned branch destination")); |
22748 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
22749 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 22750 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22751 | |
2fc8bdac | 22752 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22753 | { |
2fc8bdac ZW |
22754 | newval = md_chars_to_number (buf, INSN_SIZE); |
22755 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
22756 | /* Set the H bit on BLX instructions. */ |
22757 | if (temp == 1) | |
22758 | { | |
22759 | if (value & 2) | |
22760 | newval |= 0x01000000; | |
22761 | else | |
22762 | newval &= ~0x01000000; | |
22763 | } | |
2fc8bdac | 22764 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 22765 | } |
c19d1205 | 22766 | break; |
a737bd4d | 22767 | |
25fe350b MS |
22768 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
22769 | /* CBZ can only branch forward. */ | |
a737bd4d | 22770 | |
738755b0 | 22771 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
22772 | (which, strictly speaking, are prohibited) will be turned into |
22773 | no-ops. | |
738755b0 MS |
22774 | |
22775 | FIXME: It may be better to remove the instruction completely and | |
22776 | perform relaxation. */ | |
22777 | if (value == -2) | |
2fc8bdac ZW |
22778 | { |
22779 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 22780 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
22781 | md_number_to_chars (buf, newval, THUMB_SIZE); |
22782 | } | |
738755b0 MS |
22783 | else |
22784 | { | |
22785 | if (value & ~0x7e) | |
08f10d51 | 22786 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 22787 | |
477330fc | 22788 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
22789 | { |
22790 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22791 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
22792 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22793 | } | |
22794 | } | |
c19d1205 | 22795 | break; |
a737bd4d | 22796 | |
c19d1205 | 22797 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 22798 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 22799 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22800 | |
2fc8bdac ZW |
22801 | if (fixP->fx_done || !seg->use_rela_p) |
22802 | { | |
22803 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22804 | newval |= (value & 0x1ff) >> 1; | |
22805 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22806 | } | |
c19d1205 | 22807 | break; |
a737bd4d | 22808 | |
c19d1205 | 22809 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 22810 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 22811 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22812 | |
2fc8bdac ZW |
22813 | if (fixP->fx_done || !seg->use_rela_p) |
22814 | { | |
22815 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22816 | newval |= (value & 0xfff) >> 1; | |
22817 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22818 | } | |
c19d1205 | 22819 | break; |
a737bd4d | 22820 | |
c19d1205 | 22821 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
22822 | if (fixP->fx_addsy |
22823 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22824 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22825 | && ARM_IS_FUNC (fixP->fx_addsy) |
22826 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22827 | { | |
22828 | /* Force a relocation for a branch 20 bits wide. */ | |
22829 | fixP->fx_done = 0; | |
22830 | } | |
08f10d51 | 22831 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
22832 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22833 | _("conditional branch out of range")); | |
404ff6b5 | 22834 | |
2fc8bdac ZW |
22835 | if (fixP->fx_done || !seg->use_rela_p) |
22836 | { | |
22837 | offsetT newval2; | |
22838 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 22839 | |
2fc8bdac ZW |
22840 | S = (value & 0x00100000) >> 20; |
22841 | J2 = (value & 0x00080000) >> 19; | |
22842 | J1 = (value & 0x00040000) >> 18; | |
22843 | hi = (value & 0x0003f000) >> 12; | |
22844 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 22845 | |
2fc8bdac ZW |
22846 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22847 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22848 | newval |= (S << 10) | hi; | |
22849 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
22850 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22851 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
22852 | } | |
c19d1205 | 22853 | break; |
6c43fab6 | 22854 | |
c19d1205 | 22855 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
22856 | /* If there is a blx from a thumb state function to |
22857 | another thumb function flip this to a bl and warn | |
22858 | about it. */ | |
22859 | ||
22860 | if (fixP->fx_addsy | |
34e77a92 | 22861 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22862 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22863 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22864 | { | |
22865 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22866 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22867 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
22868 | name); | |
22869 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22870 | newval = newval | 0x1000; | |
22871 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22872 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22873 | fixP->fx_done = 1; | |
22874 | } | |
22875 | ||
22876 | ||
22877 | goto thumb_bl_common; | |
22878 | ||
c19d1205 | 22879 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
22880 | /* A bl from Thumb state ISA to an internal ARM state function |
22881 | is converted to a blx. */ | |
22882 | if (fixP->fx_addsy | |
22883 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22884 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22885 | && ARM_IS_FUNC (fixP->fx_addsy) |
22886 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22887 | { | |
22888 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22889 | newval = newval & ~0x1000; | |
22890 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22891 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
22892 | fixP->fx_done = 1; | |
22893 | } | |
22894 | ||
22895 | thumb_bl_common: | |
22896 | ||
2fc8bdac ZW |
22897 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
22898 | /* For a BLX instruction, make sure that the relocation is rounded up | |
22899 | to a word boundary. This follows the semantics of the instruction | |
22900 | which specifies that bit 1 of the target address will come from bit | |
22901 | 1 of the base address. */ | |
d406f3e4 JB |
22902 | value = (value + 3) & ~ 3; |
22903 | ||
22904 | #ifdef OBJ_ELF | |
22905 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
22906 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
22907 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22908 | #endif | |
404ff6b5 | 22909 | |
2b2f5df9 NC |
22910 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
22911 | { | |
22912 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
22913 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
22914 | else if ((value & ~0x1ffffff) | |
22915 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
22916 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22917 | _("Thumb2 branch out of range")); | |
22918 | } | |
4a42ebbc RR |
22919 | |
22920 | if (fixP->fx_done || !seg->use_rela_p) | |
22921 | encode_thumb2_b_bl_offset (buf, value); | |
22922 | ||
c19d1205 | 22923 | break; |
404ff6b5 | 22924 | |
c19d1205 | 22925 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
22926 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
22927 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 22928 | |
2fc8bdac | 22929 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 22930 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 22931 | |
2fc8bdac | 22932 | break; |
a737bd4d | 22933 | |
2fc8bdac ZW |
22934 | case BFD_RELOC_8: |
22935 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 22936 | *buf = value; |
c19d1205 | 22937 | break; |
a737bd4d | 22938 | |
c19d1205 | 22939 | case BFD_RELOC_16: |
2fc8bdac | 22940 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22941 | md_number_to_chars (buf, value, 2); |
c19d1205 | 22942 | break; |
a737bd4d | 22943 | |
c19d1205 | 22944 | #ifdef OBJ_ELF |
0855e32b NS |
22945 | case BFD_RELOC_ARM_TLS_CALL: |
22946 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
22947 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
22948 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 22949 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
22950 | case BFD_RELOC_ARM_TLS_GD32: |
22951 | case BFD_RELOC_ARM_TLS_LE32: | |
22952 | case BFD_RELOC_ARM_TLS_IE32: | |
22953 | case BFD_RELOC_ARM_TLS_LDM32: | |
22954 | case BFD_RELOC_ARM_TLS_LDO32: | |
22955 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 22956 | break; |
6c43fab6 | 22957 | |
c19d1205 ZW |
22958 | case BFD_RELOC_ARM_GOT32: |
22959 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 22960 | break; |
b43420e6 NC |
22961 | |
22962 | case BFD_RELOC_ARM_GOT_PREL: | |
22963 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 22964 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
22965 | break; |
22966 | ||
9a6f4e97 NS |
22967 | case BFD_RELOC_ARM_TARGET2: |
22968 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
22969 | addend here for REL targets, because it won't be written out |
22970 | during reloc processing later. */ | |
9a6f4e97 NS |
22971 | if (fixP->fx_done || !seg->use_rela_p) |
22972 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
22973 | break; | |
c19d1205 | 22974 | #endif |
6c43fab6 | 22975 | |
c19d1205 ZW |
22976 | case BFD_RELOC_RVA: |
22977 | case BFD_RELOC_32: | |
22978 | case BFD_RELOC_ARM_TARGET1: | |
22979 | case BFD_RELOC_ARM_ROSEGREL32: | |
22980 | case BFD_RELOC_ARM_SBREL32: | |
22981 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
22982 | #ifdef TE_PE |
22983 | case BFD_RELOC_32_SECREL: | |
22984 | #endif | |
2fc8bdac | 22985 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
22986 | #ifdef TE_WINCE |
22987 | /* For WinCE we only do this for pcrel fixups. */ | |
22988 | if (fixP->fx_done || fixP->fx_pcrel) | |
22989 | #endif | |
22990 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 22991 | break; |
6c43fab6 | 22992 | |
c19d1205 ZW |
22993 | #ifdef OBJ_ELF |
22994 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 22995 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
22996 | { |
22997 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
22998 | if ((value ^ (value >> 1)) & 0x40000000) | |
22999 | { | |
23000 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23001 | _("rel31 relocation overflow")); | |
23002 | } | |
23003 | newval |= value & 0x7fffffff; | |
23004 | md_number_to_chars (buf, newval, 4); | |
23005 | } | |
23006 | break; | |
c19d1205 | 23007 | #endif |
a737bd4d | 23008 | |
c19d1205 | 23009 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 23010 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
23011 | if (value < -1023 || value > 1023 || (value & 3)) |
23012 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23013 | _("co-processor offset out of range")); | |
23014 | cp_off_common: | |
26d97720 | 23015 | sign = value > 0; |
c19d1205 ZW |
23016 | if (value < 0) |
23017 | value = -value; | |
8f06b2d8 PB |
23018 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
23019 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
23020 | newval = md_chars_to_number (buf, INSN_SIZE); | |
23021 | else | |
23022 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
23023 | if (value == 0) |
23024 | newval &= 0xffffff00; | |
23025 | else | |
23026 | { | |
23027 | newval &= 0xff7fff00; | |
23028 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
23029 | } | |
8f06b2d8 PB |
23030 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
23031 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
23032 | md_number_to_chars (buf, newval, INSN_SIZE); | |
23033 | else | |
23034 | put_thumb32_insn (buf, newval); | |
c19d1205 | 23035 | break; |
a737bd4d | 23036 | |
c19d1205 | 23037 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 23038 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
23039 | if (value < -255 || value > 255) |
23040 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23041 | _("co-processor offset out of range")); | |
df7849c5 | 23042 | value *= 4; |
c19d1205 | 23043 | goto cp_off_common; |
6c43fab6 | 23044 | |
c19d1205 ZW |
23045 | case BFD_RELOC_ARM_THUMB_OFFSET: |
23046 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23047 | /* Exactly what ranges, and where the offset is inserted depends | |
23048 | on the type of instruction, we can establish this from the | |
23049 | top 4 bits. */ | |
23050 | switch (newval >> 12) | |
23051 | { | |
23052 | case 4: /* PC load. */ | |
23053 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
23054 | forced to zero for these loads; md_pcrel_from has already | |
23055 | compensated for this. */ | |
23056 | if (value & 3) | |
23057 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23058 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
23059 | (((unsigned long) fixP->fx_frag->fr_address |
23060 | + (unsigned long) fixP->fx_where) & ~3) | |
23061 | + (unsigned long) value); | |
a737bd4d | 23062 | |
c19d1205 ZW |
23063 | if (value & ~0x3fc) |
23064 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23065 | _("invalid offset, value too big (0x%08lX)"), | |
23066 | (long) value); | |
a737bd4d | 23067 | |
c19d1205 ZW |
23068 | newval |= value >> 2; |
23069 | break; | |
a737bd4d | 23070 | |
c19d1205 ZW |
23071 | case 9: /* SP load/store. */ |
23072 | if (value & ~0x3fc) | |
23073 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23074 | _("invalid offset, value too big (0x%08lX)"), | |
23075 | (long) value); | |
23076 | newval |= value >> 2; | |
23077 | break; | |
6c43fab6 | 23078 | |
c19d1205 ZW |
23079 | case 6: /* Word load/store. */ |
23080 | if (value & ~0x7c) | |
23081 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23082 | _("invalid offset, value too big (0x%08lX)"), | |
23083 | (long) value); | |
23084 | newval |= value << 4; /* 6 - 2. */ | |
23085 | break; | |
a737bd4d | 23086 | |
c19d1205 ZW |
23087 | case 7: /* Byte load/store. */ |
23088 | if (value & ~0x1f) | |
23089 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23090 | _("invalid offset, value too big (0x%08lX)"), | |
23091 | (long) value); | |
23092 | newval |= value << 6; | |
23093 | break; | |
a737bd4d | 23094 | |
c19d1205 ZW |
23095 | case 8: /* Halfword load/store. */ |
23096 | if (value & ~0x3e) | |
23097 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23098 | _("invalid offset, value too big (0x%08lX)"), | |
23099 | (long) value); | |
23100 | newval |= value << 5; /* 6 - 1. */ | |
23101 | break; | |
a737bd4d | 23102 | |
c19d1205 ZW |
23103 | default: |
23104 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23105 | "Unable to process relocation for thumb opcode: %lx", | |
23106 | (unsigned long) newval); | |
23107 | break; | |
23108 | } | |
23109 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23110 | break; | |
a737bd4d | 23111 | |
c19d1205 ZW |
23112 | case BFD_RELOC_ARM_THUMB_ADD: |
23113 | /* This is a complicated relocation, since we use it for all of | |
23114 | the following immediate relocations: | |
a737bd4d | 23115 | |
c19d1205 ZW |
23116 | 3bit ADD/SUB |
23117 | 8bit ADD/SUB | |
23118 | 9bit ADD/SUB SP word-aligned | |
23119 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 23120 | |
c19d1205 ZW |
23121 | The type of instruction being processed is encoded in the |
23122 | instruction field: | |
a737bd4d | 23123 | |
c19d1205 ZW |
23124 | 0x8000 SUB |
23125 | 0x00F0 Rd | |
23126 | 0x000F Rs | |
23127 | */ | |
23128 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23129 | { | |
23130 | int rd = (newval >> 4) & 0xf; | |
23131 | int rs = newval & 0xf; | |
23132 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 23133 | |
c19d1205 ZW |
23134 | /* Check for HI regs, only very restricted cases allowed: |
23135 | Adjusting SP, and using PC or SP to get an address. */ | |
23136 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
23137 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
23138 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23139 | _("invalid Hi register with immediate")); | |
a737bd4d | 23140 | |
c19d1205 ZW |
23141 | /* If value is negative, choose the opposite instruction. */ |
23142 | if (value < 0) | |
23143 | { | |
23144 | value = -value; | |
23145 | subtract = !subtract; | |
23146 | if (value < 0) | |
23147 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23148 | _("immediate value out of range")); | |
23149 | } | |
a737bd4d | 23150 | |
c19d1205 ZW |
23151 | if (rd == REG_SP) |
23152 | { | |
75c11999 | 23153 | if (value & ~0x1fc) |
c19d1205 ZW |
23154 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23155 | _("invalid immediate for stack address calculation")); | |
23156 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
23157 | newval |= value >> 2; | |
23158 | } | |
23159 | else if (rs == REG_PC || rs == REG_SP) | |
23160 | { | |
c12d2c9d NC |
23161 | /* PR gas/18541. If the addition is for a defined symbol |
23162 | within range of an ADR instruction then accept it. */ | |
23163 | if (subtract | |
23164 | && value == 4 | |
23165 | && fixP->fx_addsy != NULL) | |
23166 | { | |
23167 | subtract = 0; | |
23168 | ||
23169 | if (! S_IS_DEFINED (fixP->fx_addsy) | |
23170 | || S_GET_SEGMENT (fixP->fx_addsy) != seg | |
23171 | || S_IS_WEAK (fixP->fx_addsy)) | |
23172 | { | |
23173 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23174 | _("address calculation needs a strongly defined nearby symbol")); | |
23175 | } | |
23176 | else | |
23177 | { | |
23178 | offsetT v = fixP->fx_where + fixP->fx_frag->fr_address; | |
23179 | ||
23180 | /* Round up to the next 4-byte boundary. */ | |
23181 | if (v & 3) | |
23182 | v = (v + 3) & ~ 3; | |
23183 | else | |
23184 | v += 4; | |
23185 | v = S_GET_VALUE (fixP->fx_addsy) - v; | |
23186 | ||
23187 | if (v & ~0x3fc) | |
23188 | { | |
23189 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23190 | _("symbol too far away")); | |
23191 | } | |
23192 | else | |
23193 | { | |
23194 | fixP->fx_done = 1; | |
23195 | value = v; | |
23196 | } | |
23197 | } | |
23198 | } | |
23199 | ||
c19d1205 ZW |
23200 | if (subtract || value & ~0x3fc) |
23201 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23202 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
5fc177c8 | 23203 | (unsigned long) (subtract ? - value : value)); |
c19d1205 ZW |
23204 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); |
23205 | newval |= rd << 8; | |
23206 | newval |= value >> 2; | |
23207 | } | |
23208 | else if (rs == rd) | |
23209 | { | |
23210 | if (value & ~0xff) | |
23211 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23212 | _("immediate value out of range")); | |
23213 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
23214 | newval |= (rd << 8) | value; | |
23215 | } | |
23216 | else | |
23217 | { | |
23218 | if (value & ~0x7) | |
23219 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23220 | _("immediate value out of range")); | |
23221 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
23222 | newval |= rd | (rs << 3) | (value << 6); | |
23223 | } | |
23224 | } | |
23225 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23226 | break; | |
a737bd4d | 23227 | |
c19d1205 ZW |
23228 | case BFD_RELOC_ARM_THUMB_IMM: |
23229 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23230 | if (value < 0 || value > 255) | |
23231 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 23232 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
23233 | (long) value); |
23234 | newval |= value; | |
23235 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23236 | break; | |
a737bd4d | 23237 | |
c19d1205 ZW |
23238 | case BFD_RELOC_ARM_THUMB_SHIFT: |
23239 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
23240 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
23241 | temp = newval & 0xf800; | |
23242 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
23243 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23244 | _("invalid shift value: %ld"), (long) value); | |
23245 | /* Shifts of zero must be encoded as LSL. */ | |
23246 | if (value == 0) | |
23247 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
23248 | /* Shifts of 32 are encoded as zero. */ | |
23249 | else if (value == 32) | |
23250 | value = 0; | |
23251 | newval |= value << 6; | |
23252 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23253 | break; | |
a737bd4d | 23254 | |
c19d1205 ZW |
23255 | case BFD_RELOC_VTABLE_INHERIT: |
23256 | case BFD_RELOC_VTABLE_ENTRY: | |
23257 | fixP->fx_done = 0; | |
23258 | return; | |
6c43fab6 | 23259 | |
b6895b4f PB |
23260 | case BFD_RELOC_ARM_MOVW: |
23261 | case BFD_RELOC_ARM_MOVT: | |
23262 | case BFD_RELOC_ARM_THUMB_MOVW: | |
23263 | case BFD_RELOC_ARM_THUMB_MOVT: | |
23264 | if (fixP->fx_done || !seg->use_rela_p) | |
23265 | { | |
23266 | /* REL format relocations are limited to a 16-bit addend. */ | |
23267 | if (!fixP->fx_done) | |
23268 | { | |
39623e12 | 23269 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 23270 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 23271 | _("offset out of range")); |
b6895b4f PB |
23272 | } |
23273 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
23274 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
23275 | { | |
23276 | value >>= 16; | |
23277 | } | |
23278 | ||
23279 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
23280 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
23281 | { | |
23282 | newval = get_thumb32_insn (buf); | |
23283 | newval &= 0xfbf08f00; | |
23284 | newval |= (value & 0xf000) << 4; | |
23285 | newval |= (value & 0x0800) << 15; | |
23286 | newval |= (value & 0x0700) << 4; | |
23287 | newval |= (value & 0x00ff); | |
23288 | put_thumb32_insn (buf, newval); | |
23289 | } | |
23290 | else | |
23291 | { | |
23292 | newval = md_chars_to_number (buf, 4); | |
23293 | newval &= 0xfff0f000; | |
23294 | newval |= value & 0x0fff; | |
23295 | newval |= (value & 0xf000) << 4; | |
23296 | md_number_to_chars (buf, newval, 4); | |
23297 | } | |
23298 | } | |
23299 | return; | |
23300 | ||
4962c51a MS |
23301 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
23302 | case BFD_RELOC_ARM_ALU_PC_G0: | |
23303 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
23304 | case BFD_RELOC_ARM_ALU_PC_G1: | |
23305 | case BFD_RELOC_ARM_ALU_PC_G2: | |
23306 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
23307 | case BFD_RELOC_ARM_ALU_SB_G0: | |
23308 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
23309 | case BFD_RELOC_ARM_ALU_SB_G1: | |
23310 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 23311 | gas_assert (!fixP->fx_done); |
4962c51a MS |
23312 | if (!seg->use_rela_p) |
23313 | { | |
477330fc RM |
23314 | bfd_vma insn; |
23315 | bfd_vma encoded_addend; | |
23316 | bfd_vma addend_abs = abs (value); | |
23317 | ||
23318 | /* Check that the absolute value of the addend can be | |
23319 | expressed as an 8-bit constant plus a rotation. */ | |
23320 | encoded_addend = encode_arm_immediate (addend_abs); | |
23321 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 23322 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23323 | _("the offset 0x%08lX is not representable"), |
23324 | (unsigned long) addend_abs); | |
23325 | ||
23326 | /* Extract the instruction. */ | |
23327 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23328 | ||
23329 | /* If the addend is positive, use an ADD instruction. | |
23330 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
23331 | insn &= 0xff1fffff; | |
23332 | if (value < 0) | |
23333 | insn |= 1 << 22; | |
23334 | else | |
23335 | insn |= 1 << 23; | |
23336 | ||
23337 | /* Place the encoded addend into the first 12 bits of the | |
23338 | instruction. */ | |
23339 | insn &= 0xfffff000; | |
23340 | insn |= encoded_addend; | |
23341 | ||
23342 | /* Update the instruction. */ | |
23343 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
23344 | } |
23345 | break; | |
23346 | ||
23347 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23348 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23349 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23350 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23351 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23352 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 23353 | gas_assert (!fixP->fx_done); |
4962c51a | 23354 | if (!seg->use_rela_p) |
477330fc RM |
23355 | { |
23356 | bfd_vma insn; | |
23357 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23358 | |
477330fc RM |
23359 | /* Check that the absolute value of the addend can be |
23360 | encoded in 12 bits. */ | |
23361 | if (addend_abs >= 0x1000) | |
4962c51a | 23362 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23363 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
23364 | (unsigned long) addend_abs); | |
23365 | ||
23366 | /* Extract the instruction. */ | |
23367 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23368 | ||
23369 | /* If the addend is negative, clear bit 23 of the instruction. | |
23370 | Otherwise set it. */ | |
23371 | if (value < 0) | |
23372 | insn &= ~(1 << 23); | |
23373 | else | |
23374 | insn |= 1 << 23; | |
23375 | ||
23376 | /* Place the absolute value of the addend into the first 12 bits | |
23377 | of the instruction. */ | |
23378 | insn &= 0xfffff000; | |
23379 | insn |= addend_abs; | |
23380 | ||
23381 | /* Update the instruction. */ | |
23382 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23383 | } | |
4962c51a MS |
23384 | break; |
23385 | ||
23386 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23387 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23388 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23389 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23390 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23391 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 23392 | gas_assert (!fixP->fx_done); |
4962c51a | 23393 | if (!seg->use_rela_p) |
477330fc RM |
23394 | { |
23395 | bfd_vma insn; | |
23396 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23397 | |
477330fc RM |
23398 | /* Check that the absolute value of the addend can be |
23399 | encoded in 8 bits. */ | |
23400 | if (addend_abs >= 0x100) | |
4962c51a | 23401 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23402 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
23403 | (unsigned long) addend_abs); | |
23404 | ||
23405 | /* Extract the instruction. */ | |
23406 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23407 | ||
23408 | /* If the addend is negative, clear bit 23 of the instruction. | |
23409 | Otherwise set it. */ | |
23410 | if (value < 0) | |
23411 | insn &= ~(1 << 23); | |
23412 | else | |
23413 | insn |= 1 << 23; | |
23414 | ||
23415 | /* Place the first four bits of the absolute value of the addend | |
23416 | into the first 4 bits of the instruction, and the remaining | |
23417 | four into bits 8 .. 11. */ | |
23418 | insn &= 0xfffff0f0; | |
23419 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
23420 | ||
23421 | /* Update the instruction. */ | |
23422 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23423 | } | |
4962c51a MS |
23424 | break; |
23425 | ||
23426 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23427 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23428 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23429 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23430 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23431 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 23432 | gas_assert (!fixP->fx_done); |
4962c51a | 23433 | if (!seg->use_rela_p) |
477330fc RM |
23434 | { |
23435 | bfd_vma insn; | |
23436 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23437 | |
477330fc RM |
23438 | /* Check that the absolute value of the addend is a multiple of |
23439 | four and, when divided by four, fits in 8 bits. */ | |
23440 | if (addend_abs & 0x3) | |
4962c51a | 23441 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23442 | _("bad offset 0x%08lX (must be word-aligned)"), |
23443 | (unsigned long) addend_abs); | |
4962c51a | 23444 | |
477330fc | 23445 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 23446 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23447 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
23448 | (unsigned long) addend_abs); | |
23449 | ||
23450 | /* Extract the instruction. */ | |
23451 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23452 | ||
23453 | /* If the addend is negative, clear bit 23 of the instruction. | |
23454 | Otherwise set it. */ | |
23455 | if (value < 0) | |
23456 | insn &= ~(1 << 23); | |
23457 | else | |
23458 | insn |= 1 << 23; | |
23459 | ||
23460 | /* Place the addend (divided by four) into the first eight | |
23461 | bits of the instruction. */ | |
23462 | insn &= 0xfffffff0; | |
23463 | insn |= addend_abs >> 2; | |
23464 | ||
23465 | /* Update the instruction. */ | |
23466 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23467 | } | |
4962c51a MS |
23468 | break; |
23469 | ||
845b51d6 PB |
23470 | case BFD_RELOC_ARM_V4BX: |
23471 | /* This will need to go in the object file. */ | |
23472 | fixP->fx_done = 0; | |
23473 | break; | |
23474 | ||
c19d1205 ZW |
23475 | case BFD_RELOC_UNUSED: |
23476 | default: | |
23477 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23478 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
23479 | } | |
6c43fab6 RE |
23480 | } |
23481 | ||
c19d1205 ZW |
23482 | /* Translate internal representation of relocation info to BFD target |
23483 | format. */ | |
a737bd4d | 23484 | |
c19d1205 | 23485 | arelent * |
00a97672 | 23486 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 23487 | { |
c19d1205 ZW |
23488 | arelent * reloc; |
23489 | bfd_reloc_code_real_type code; | |
a737bd4d | 23490 | |
21d799b5 | 23491 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 23492 | |
21d799b5 | 23493 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
23494 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
23495 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 23496 | |
2fc8bdac | 23497 | if (fixp->fx_pcrel) |
00a97672 RS |
23498 | { |
23499 | if (section->use_rela_p) | |
23500 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
23501 | else | |
23502 | fixp->fx_offset = reloc->address; | |
23503 | } | |
c19d1205 | 23504 | reloc->addend = fixp->fx_offset; |
a737bd4d | 23505 | |
c19d1205 | 23506 | switch (fixp->fx_r_type) |
a737bd4d | 23507 | { |
c19d1205 ZW |
23508 | case BFD_RELOC_8: |
23509 | if (fixp->fx_pcrel) | |
23510 | { | |
23511 | code = BFD_RELOC_8_PCREL; | |
23512 | break; | |
23513 | } | |
a737bd4d | 23514 | |
c19d1205 ZW |
23515 | case BFD_RELOC_16: |
23516 | if (fixp->fx_pcrel) | |
23517 | { | |
23518 | code = BFD_RELOC_16_PCREL; | |
23519 | break; | |
23520 | } | |
6c43fab6 | 23521 | |
c19d1205 ZW |
23522 | case BFD_RELOC_32: |
23523 | if (fixp->fx_pcrel) | |
23524 | { | |
23525 | code = BFD_RELOC_32_PCREL; | |
23526 | break; | |
23527 | } | |
a737bd4d | 23528 | |
b6895b4f PB |
23529 | case BFD_RELOC_ARM_MOVW: |
23530 | if (fixp->fx_pcrel) | |
23531 | { | |
23532 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
23533 | break; | |
23534 | } | |
23535 | ||
23536 | case BFD_RELOC_ARM_MOVT: | |
23537 | if (fixp->fx_pcrel) | |
23538 | { | |
23539 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
23540 | break; | |
23541 | } | |
23542 | ||
23543 | case BFD_RELOC_ARM_THUMB_MOVW: | |
23544 | if (fixp->fx_pcrel) | |
23545 | { | |
23546 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
23547 | break; | |
23548 | } | |
23549 | ||
23550 | case BFD_RELOC_ARM_THUMB_MOVT: | |
23551 | if (fixp->fx_pcrel) | |
23552 | { | |
23553 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
23554 | break; | |
23555 | } | |
23556 | ||
c19d1205 ZW |
23557 | case BFD_RELOC_NONE: |
23558 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
23559 | case BFD_RELOC_ARM_PCREL_BLX: | |
23560 | case BFD_RELOC_RVA: | |
23561 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
23562 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
23563 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
23564 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23565 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23566 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
23567 | case BFD_RELOC_VTABLE_ENTRY: |
23568 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
23569 | #ifdef TE_PE |
23570 | case BFD_RELOC_32_SECREL: | |
23571 | #endif | |
c19d1205 ZW |
23572 | code = fixp->fx_r_type; |
23573 | break; | |
a737bd4d | 23574 | |
00adf2d4 JB |
23575 | case BFD_RELOC_THUMB_PCREL_BLX: |
23576 | #ifdef OBJ_ELF | |
23577 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
23578 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
23579 | else | |
23580 | #endif | |
23581 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
23582 | break; | |
23583 | ||
c19d1205 ZW |
23584 | case BFD_RELOC_ARM_LITERAL: |
23585 | case BFD_RELOC_ARM_HWLITERAL: | |
23586 | /* If this is called then the a literal has | |
23587 | been referenced across a section boundary. */ | |
23588 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23589 | _("literal referenced across section boundary")); | |
23590 | return NULL; | |
a737bd4d | 23591 | |
c19d1205 | 23592 | #ifdef OBJ_ELF |
0855e32b NS |
23593 | case BFD_RELOC_ARM_TLS_CALL: |
23594 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
23595 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
23596 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
23597 | case BFD_RELOC_ARM_GOT32: |
23598 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 23599 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
23600 | case BFD_RELOC_ARM_PLT32: |
23601 | case BFD_RELOC_ARM_TARGET1: | |
23602 | case BFD_RELOC_ARM_ROSEGREL32: | |
23603 | case BFD_RELOC_ARM_SBREL32: | |
23604 | case BFD_RELOC_ARM_PREL31: | |
23605 | case BFD_RELOC_ARM_TARGET2: | |
c19d1205 | 23606 | case BFD_RELOC_ARM_TLS_LDO32: |
39b41c9c PB |
23607 | case BFD_RELOC_ARM_PCREL_CALL: |
23608 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
23609 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
23610 | case BFD_RELOC_ARM_ALU_PC_G0: | |
23611 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
23612 | case BFD_RELOC_ARM_ALU_PC_G1: | |
23613 | case BFD_RELOC_ARM_ALU_PC_G2: | |
23614 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23615 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23616 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23617 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23618 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23619 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23620 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23621 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23622 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23623 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
23624 | case BFD_RELOC_ARM_ALU_SB_G0: | |
23625 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
23626 | case BFD_RELOC_ARM_ALU_SB_G1: | |
23627 | case BFD_RELOC_ARM_ALU_SB_G2: | |
23628 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23629 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23630 | case BFD_RELOC_ARM_LDR_SB_G2: | |
23631 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23632 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23633 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
23634 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23635 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23636 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 23637 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
23638 | code = fixp->fx_r_type; |
23639 | break; | |
a737bd4d | 23640 | |
0855e32b | 23641 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 | 23642 | case BFD_RELOC_ARM_TLS_GD32: |
75c11999 | 23643 | case BFD_RELOC_ARM_TLS_LE32: |
c19d1205 ZW |
23644 | case BFD_RELOC_ARM_TLS_IE32: |
23645 | case BFD_RELOC_ARM_TLS_LDM32: | |
23646 | /* BFD will include the symbol's address in the addend. | |
23647 | But we don't want that, so subtract it out again here. */ | |
23648 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
23649 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
23650 | code = fixp->fx_r_type; | |
23651 | break; | |
23652 | #endif | |
a737bd4d | 23653 | |
c19d1205 ZW |
23654 | case BFD_RELOC_ARM_IMMEDIATE: |
23655 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23656 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
23657 | return NULL; | |
a737bd4d | 23658 | |
c19d1205 ZW |
23659 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
23660 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23661 | _("ADRL used for a symbol not defined in the same file")); | |
23662 | return NULL; | |
a737bd4d | 23663 | |
c19d1205 | 23664 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
23665 | if (section->use_rela_p) |
23666 | { | |
23667 | code = fixp->fx_r_type; | |
23668 | break; | |
23669 | } | |
23670 | ||
c19d1205 ZW |
23671 | if (fixp->fx_addsy != NULL |
23672 | && !S_IS_DEFINED (fixp->fx_addsy) | |
23673 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 23674 | { |
c19d1205 ZW |
23675 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23676 | _("undefined local label `%s'"), | |
23677 | S_GET_NAME (fixp->fx_addsy)); | |
23678 | return NULL; | |
a737bd4d NC |
23679 | } |
23680 | ||
c19d1205 ZW |
23681 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23682 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
23683 | return NULL; | |
a737bd4d | 23684 | |
c19d1205 ZW |
23685 | default: |
23686 | { | |
23687 | char * type; | |
6c43fab6 | 23688 | |
c19d1205 ZW |
23689 | switch (fixp->fx_r_type) |
23690 | { | |
23691 | case BFD_RELOC_NONE: type = "NONE"; break; | |
23692 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
23693 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 23694 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
23695 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
23696 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
23697 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 23698 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 23699 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
23700 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
23701 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
23702 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
23703 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
23704 | default: type = _("<unknown>"); break; | |
23705 | } | |
23706 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23707 | _("cannot represent %s relocation in this object file format"), | |
23708 | type); | |
23709 | return NULL; | |
23710 | } | |
a737bd4d | 23711 | } |
6c43fab6 | 23712 | |
c19d1205 ZW |
23713 | #ifdef OBJ_ELF |
23714 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
23715 | && GOT_symbol | |
23716 | && fixp->fx_addsy == GOT_symbol) | |
23717 | { | |
23718 | code = BFD_RELOC_ARM_GOTPC; | |
23719 | reloc->addend = fixp->fx_offset = reloc->address; | |
23720 | } | |
23721 | #endif | |
6c43fab6 | 23722 | |
c19d1205 | 23723 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 23724 | |
c19d1205 ZW |
23725 | if (reloc->howto == NULL) |
23726 | { | |
23727 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23728 | _("cannot represent %s relocation in this object file format"), | |
23729 | bfd_get_reloc_code_name (code)); | |
23730 | return NULL; | |
23731 | } | |
6c43fab6 | 23732 | |
c19d1205 ZW |
23733 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
23734 | vtable entry to be used in the relocation's section offset. */ | |
23735 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
23736 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 23737 | |
c19d1205 | 23738 | return reloc; |
6c43fab6 RE |
23739 | } |
23740 | ||
c19d1205 | 23741 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 23742 | |
c19d1205 ZW |
23743 | void |
23744 | cons_fix_new_arm (fragS * frag, | |
23745 | int where, | |
23746 | int size, | |
62ebcb5c AM |
23747 | expressionS * exp, |
23748 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 23749 | { |
c19d1205 | 23750 | int pcrel = 0; |
6c43fab6 | 23751 | |
c19d1205 ZW |
23752 | /* Pick a reloc. |
23753 | FIXME: @@ Should look at CPU word size. */ | |
23754 | switch (size) | |
23755 | { | |
23756 | case 1: | |
62ebcb5c | 23757 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
23758 | break; |
23759 | case 2: | |
62ebcb5c | 23760 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
23761 | break; |
23762 | case 4: | |
23763 | default: | |
62ebcb5c | 23764 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
23765 | break; |
23766 | case 8: | |
62ebcb5c | 23767 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
23768 | break; |
23769 | } | |
6c43fab6 | 23770 | |
f0927246 NC |
23771 | #ifdef TE_PE |
23772 | if (exp->X_op == O_secrel) | |
23773 | { | |
23774 | exp->X_op = O_symbol; | |
62ebcb5c | 23775 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
23776 | } |
23777 | #endif | |
23778 | ||
62ebcb5c | 23779 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 23780 | } |
6c43fab6 | 23781 | |
4343666d | 23782 | #if defined (OBJ_COFF) |
c19d1205 ZW |
23783 | void |
23784 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 23785 | { |
c19d1205 ZW |
23786 | /* If the destination of the branch is a defined symbol which does not have |
23787 | the THUMB_FUNC attribute, then we must be calling a function which has | |
23788 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
23789 | function and change the branch to refer to that function instead. */ | |
23790 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
23791 | && fixP->fx_addsy != NULL | |
23792 | && S_IS_DEFINED (fixP->fx_addsy) | |
23793 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 23794 | { |
c19d1205 | 23795 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 23796 | } |
c19d1205 ZW |
23797 | } |
23798 | #endif | |
6c43fab6 | 23799 | |
267bf995 | 23800 | |
c19d1205 ZW |
23801 | int |
23802 | arm_force_relocation (struct fix * fixp) | |
23803 | { | |
23804 | #if defined (OBJ_COFF) && defined (TE_PE) | |
23805 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
23806 | return 1; | |
23807 | #endif | |
6c43fab6 | 23808 | |
267bf995 RR |
23809 | /* In case we have a call or a branch to a function in ARM ISA mode from |
23810 | a thumb function or vice-versa force the relocation. These relocations | |
23811 | are cleared off for some cores that might have blx and simple transformations | |
23812 | are possible. */ | |
23813 | ||
23814 | #ifdef OBJ_ELF | |
23815 | switch (fixp->fx_r_type) | |
23816 | { | |
23817 | case BFD_RELOC_ARM_PCREL_JUMP: | |
23818 | case BFD_RELOC_ARM_PCREL_CALL: | |
23819 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23820 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
23821 | return 1; | |
23822 | break; | |
23823 | ||
23824 | case BFD_RELOC_ARM_PCREL_BLX: | |
23825 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
23826 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23827 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23828 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
23829 | return 1; | |
23830 | break; | |
23831 | ||
23832 | default: | |
23833 | break; | |
23834 | } | |
23835 | #endif | |
23836 | ||
b5884301 PB |
23837 | /* Resolve these relocations even if the symbol is extern or weak. |
23838 | Technically this is probably wrong due to symbol preemption. | |
23839 | In practice these relocations do not have enough range to be useful | |
23840 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
23841 | expects these references to be resolved. */ | |
c19d1205 ZW |
23842 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
23843 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 23844 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 23845 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
23846 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
23847 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
23848 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 23849 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
23850 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
23851 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
23852 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
23853 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
23854 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
23855 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 23856 | return 0; |
a737bd4d | 23857 | |
4962c51a MS |
23858 | /* Always leave these relocations for the linker. */ |
23859 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23860 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23861 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
23862 | return 1; | |
23863 | ||
f0291e4c PB |
23864 | /* Always generate relocations against function symbols. */ |
23865 | if (fixp->fx_r_type == BFD_RELOC_32 | |
23866 | && fixp->fx_addsy | |
23867 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
23868 | return 1; | |
23869 | ||
c19d1205 | 23870 | return generic_force_reloc (fixp); |
404ff6b5 AH |
23871 | } |
23872 | ||
0ffdc86c | 23873 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
23874 | /* Relocations against function names must be left unadjusted, |
23875 | so that the linker can use this information to generate interworking | |
23876 | stubs. The MIPS version of this function | |
c19d1205 ZW |
23877 | also prevents relocations that are mips-16 specific, but I do not |
23878 | know why it does this. | |
404ff6b5 | 23879 | |
c19d1205 ZW |
23880 | FIXME: |
23881 | There is one other problem that ought to be addressed here, but | |
23882 | which currently is not: Taking the address of a label (rather | |
23883 | than a function) and then later jumping to that address. Such | |
23884 | addresses also ought to have their bottom bit set (assuming that | |
23885 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 23886 | |
c19d1205 ZW |
23887 | bfd_boolean |
23888 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 23889 | { |
c19d1205 ZW |
23890 | if (fixP->fx_addsy == NULL) |
23891 | return 1; | |
404ff6b5 | 23892 | |
e28387c3 PB |
23893 | /* Preserve relocations against symbols with function type. */ |
23894 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 23895 | return FALSE; |
e28387c3 | 23896 | |
c19d1205 ZW |
23897 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
23898 | && fixP->fx_subsy == NULL) | |
c921be7d | 23899 | return FALSE; |
a737bd4d | 23900 | |
c19d1205 ZW |
23901 | /* We need the symbol name for the VTABLE entries. */ |
23902 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
23903 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 23904 | return FALSE; |
404ff6b5 | 23905 | |
c19d1205 ZW |
23906 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
23907 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
23908 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
23909 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
23910 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
23911 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
23912 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
23913 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
23914 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
23915 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
23916 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
23917 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
23918 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
23919 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 23920 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 23921 | return FALSE; |
a737bd4d | 23922 | |
4962c51a MS |
23923 | /* Similarly for group relocations. */ |
23924 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23925 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23926 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 23927 | return FALSE; |
4962c51a | 23928 | |
79947c54 CD |
23929 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
23930 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
23931 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
23932 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
23933 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
23934 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
23935 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
23936 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
23937 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 23938 | return FALSE; |
79947c54 | 23939 | |
c921be7d | 23940 | return TRUE; |
a737bd4d | 23941 | } |
0ffdc86c NC |
23942 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
23943 | ||
23944 | #ifdef OBJ_ELF | |
404ff6b5 | 23945 | |
c19d1205 ZW |
23946 | const char * |
23947 | elf32_arm_target_format (void) | |
404ff6b5 | 23948 | { |
c19d1205 ZW |
23949 | #ifdef TE_SYMBIAN |
23950 | return (target_big_endian | |
23951 | ? "elf32-bigarm-symbian" | |
23952 | : "elf32-littlearm-symbian"); | |
23953 | #elif defined (TE_VXWORKS) | |
23954 | return (target_big_endian | |
23955 | ? "elf32-bigarm-vxworks" | |
23956 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
23957 | #elif defined (TE_NACL) |
23958 | return (target_big_endian | |
23959 | ? "elf32-bigarm-nacl" | |
23960 | : "elf32-littlearm-nacl"); | |
c19d1205 ZW |
23961 | #else |
23962 | if (target_big_endian) | |
23963 | return "elf32-bigarm"; | |
23964 | else | |
23965 | return "elf32-littlearm"; | |
23966 | #endif | |
404ff6b5 AH |
23967 | } |
23968 | ||
c19d1205 ZW |
23969 | void |
23970 | armelf_frob_symbol (symbolS * symp, | |
23971 | int * puntp) | |
404ff6b5 | 23972 | { |
c19d1205 ZW |
23973 | elf_frob_symbol (symp, puntp); |
23974 | } | |
23975 | #endif | |
404ff6b5 | 23976 | |
c19d1205 | 23977 | /* MD interface: Finalization. */ |
a737bd4d | 23978 | |
c19d1205 ZW |
23979 | void |
23980 | arm_cleanup (void) | |
23981 | { | |
23982 | literal_pool * pool; | |
a737bd4d | 23983 | |
e07e6e58 NC |
23984 | /* Ensure that all the IT blocks are properly closed. */ |
23985 | check_it_blocks_finished (); | |
23986 | ||
c19d1205 ZW |
23987 | for (pool = list_of_pools; pool; pool = pool->next) |
23988 | { | |
5f4273c7 | 23989 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
23990 | subseg_set (pool->section, pool->sub_section); |
23991 | #ifdef OBJ_ELF | |
23992 | arm_elf_change_section (); | |
23993 | #endif | |
23994 | s_ltorg (0); | |
23995 | } | |
404ff6b5 AH |
23996 | } |
23997 | ||
cd000bff DJ |
23998 | #ifdef OBJ_ELF |
23999 | /* Remove any excess mapping symbols generated for alignment frags in | |
24000 | SEC. We may have created a mapping symbol before a zero byte | |
24001 | alignment; remove it if there's a mapping symbol after the | |
24002 | alignment. */ | |
24003 | static void | |
24004 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
24005 | void *dummy ATTRIBUTE_UNUSED) | |
24006 | { | |
24007 | segment_info_type *seginfo = seg_info (sec); | |
24008 | fragS *fragp; | |
24009 | ||
24010 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
24011 | return; | |
24012 | ||
24013 | for (fragp = seginfo->frchainP->frch_root; | |
24014 | fragp != NULL; | |
24015 | fragp = fragp->fr_next) | |
24016 | { | |
24017 | symbolS *sym = fragp->tc_frag_data.last_map; | |
24018 | fragS *next = fragp->fr_next; | |
24019 | ||
24020 | /* Variable-sized frags have been converted to fixed size by | |
24021 | this point. But if this was variable-sized to start with, | |
24022 | there will be a fixed-size frag after it. So don't handle | |
24023 | next == NULL. */ | |
24024 | if (sym == NULL || next == NULL) | |
24025 | continue; | |
24026 | ||
24027 | if (S_GET_VALUE (sym) < next->fr_address) | |
24028 | /* Not at the end of this frag. */ | |
24029 | continue; | |
24030 | know (S_GET_VALUE (sym) == next->fr_address); | |
24031 | ||
24032 | do | |
24033 | { | |
24034 | if (next->tc_frag_data.first_map != NULL) | |
24035 | { | |
24036 | /* Next frag starts with a mapping symbol. Discard this | |
24037 | one. */ | |
24038 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
24039 | break; | |
24040 | } | |
24041 | ||
24042 | if (next->fr_next == NULL) | |
24043 | { | |
24044 | /* This mapping symbol is at the end of the section. Discard | |
24045 | it. */ | |
24046 | know (next->fr_fix == 0 && next->fr_var == 0); | |
24047 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
24048 | break; | |
24049 | } | |
24050 | ||
24051 | /* As long as we have empty frags without any mapping symbols, | |
24052 | keep looking. */ | |
24053 | /* If the next frag is non-empty and does not start with a | |
24054 | mapping symbol, then this mapping symbol is required. */ | |
24055 | if (next->fr_address != next->fr_next->fr_address) | |
24056 | break; | |
24057 | ||
24058 | next = next->fr_next; | |
24059 | } | |
24060 | while (next != NULL); | |
24061 | } | |
24062 | } | |
24063 | #endif | |
24064 | ||
c19d1205 ZW |
24065 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
24066 | ARM ones. */ | |
404ff6b5 | 24067 | |
c19d1205 ZW |
24068 | void |
24069 | arm_adjust_symtab (void) | |
404ff6b5 | 24070 | { |
c19d1205 ZW |
24071 | #ifdef OBJ_COFF |
24072 | symbolS * sym; | |
404ff6b5 | 24073 | |
c19d1205 ZW |
24074 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
24075 | { | |
24076 | if (ARM_IS_THUMB (sym)) | |
24077 | { | |
24078 | if (THUMB_IS_FUNC (sym)) | |
24079 | { | |
24080 | /* Mark the symbol as a Thumb function. */ | |
24081 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
24082 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
24083 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 24084 | |
c19d1205 ZW |
24085 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
24086 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
24087 | else | |
24088 | as_bad (_("%s: unexpected function type: %d"), | |
24089 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
24090 | } | |
24091 | else switch (S_GET_STORAGE_CLASS (sym)) | |
24092 | { | |
24093 | case C_EXT: | |
24094 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
24095 | break; | |
24096 | case C_STAT: | |
24097 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
24098 | break; | |
24099 | case C_LABEL: | |
24100 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
24101 | break; | |
24102 | default: | |
24103 | /* Do nothing. */ | |
24104 | break; | |
24105 | } | |
24106 | } | |
a737bd4d | 24107 | |
c19d1205 ZW |
24108 | if (ARM_IS_INTERWORK (sym)) |
24109 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 24110 | } |
c19d1205 ZW |
24111 | #endif |
24112 | #ifdef OBJ_ELF | |
24113 | symbolS * sym; | |
24114 | char bind; | |
404ff6b5 | 24115 | |
c19d1205 | 24116 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 24117 | { |
c19d1205 ZW |
24118 | if (ARM_IS_THUMB (sym)) |
24119 | { | |
24120 | elf_symbol_type * elf_sym; | |
404ff6b5 | 24121 | |
c19d1205 ZW |
24122 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
24123 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 24124 | |
b0796911 PB |
24125 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
24126 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
24127 | { |
24128 | /* If it's a .thumb_func, declare it as so, | |
24129 | otherwise tag label as .code 16. */ | |
24130 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
24131 | elf_sym->internal_elf_sym.st_target_internal |
24132 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 24133 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
24134 | elf_sym->internal_elf_sym.st_info = |
24135 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
24136 | } | |
24137 | } | |
24138 | } | |
cd000bff DJ |
24139 | |
24140 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
24141 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
24142 | /* Now do generic ELF adjustments. */ |
24143 | elf_adjust_symtab (); | |
c19d1205 | 24144 | #endif |
404ff6b5 AH |
24145 | } |
24146 | ||
c19d1205 | 24147 | /* MD interface: Initialization. */ |
404ff6b5 | 24148 | |
a737bd4d | 24149 | static void |
c19d1205 | 24150 | set_constant_flonums (void) |
a737bd4d | 24151 | { |
c19d1205 | 24152 | int i; |
404ff6b5 | 24153 | |
c19d1205 ZW |
24154 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
24155 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
24156 | abort (); | |
a737bd4d | 24157 | } |
404ff6b5 | 24158 | |
3e9e4fcf JB |
24159 | /* Auto-select Thumb mode if it's the only available instruction set for the |
24160 | given architecture. */ | |
24161 | ||
24162 | static void | |
24163 | autoselect_thumb_from_cpu_variant (void) | |
24164 | { | |
24165 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
24166 | opcode_select (16); | |
24167 | } | |
24168 | ||
c19d1205 ZW |
24169 | void |
24170 | md_begin (void) | |
a737bd4d | 24171 | { |
c19d1205 ZW |
24172 | unsigned mach; |
24173 | unsigned int i; | |
404ff6b5 | 24174 | |
c19d1205 ZW |
24175 | if ( (arm_ops_hsh = hash_new ()) == NULL |
24176 | || (arm_cond_hsh = hash_new ()) == NULL | |
24177 | || (arm_shift_hsh = hash_new ()) == NULL | |
24178 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 24179 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 24180 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
24181 | || (arm_reloc_hsh = hash_new ()) == NULL |
24182 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
24183 | as_fatal (_("virtual memory exhausted")); |
24184 | ||
24185 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 24186 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 24187 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 24188 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 24189 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 24190 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 24191 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 24192 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 24193 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 24194 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 24195 | (void *) (v7m_psrs + i)); |
c19d1205 | 24196 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 24197 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
24198 | for (i = 0; |
24199 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
24200 | i++) | |
d3ce72d0 | 24201 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 24202 | (void *) (barrier_opt_names + i)); |
c19d1205 | 24203 | #ifdef OBJ_ELF |
3da1d841 NC |
24204 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
24205 | { | |
24206 | struct reloc_entry * entry = reloc_names + i; | |
24207 | ||
24208 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
24209 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
24210 | entry->reloc = BFD_RELOC_UNUSED; | |
24211 | ||
24212 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
24213 | } | |
c19d1205 ZW |
24214 | #endif |
24215 | ||
24216 | set_constant_flonums (); | |
404ff6b5 | 24217 | |
c19d1205 ZW |
24218 | /* Set the cpu variant based on the command-line options. We prefer |
24219 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
24220 | -mfpu= over any other way of setting the floating point unit. | |
24221 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 24222 | if (legacy_cpu) |
404ff6b5 | 24223 | { |
e74cfd16 | 24224 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
24225 | as_bad (_("use of old and new-style options to set CPU type")); |
24226 | ||
24227 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 24228 | } |
e74cfd16 | 24229 | else if (!mcpu_cpu_opt) |
c19d1205 | 24230 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 24231 | |
e74cfd16 | 24232 | if (legacy_fpu) |
c19d1205 | 24233 | { |
e74cfd16 | 24234 | if (mfpu_opt) |
c19d1205 | 24235 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
24236 | |
24237 | mfpu_opt = legacy_fpu; | |
24238 | } | |
e74cfd16 | 24239 | else if (!mfpu_opt) |
03b1477f | 24240 | { |
45eb4c1b NS |
24241 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
24242 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
24243 | /* Some environments specify a default FPU. If they don't, infer it |
24244 | from the processor. */ | |
e74cfd16 | 24245 | if (mcpu_fpu_opt) |
03b1477f RE |
24246 | mfpu_opt = mcpu_fpu_opt; |
24247 | else | |
24248 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 24249 | #else |
e74cfd16 | 24250 | mfpu_opt = &fpu_default; |
39c2da32 | 24251 | #endif |
03b1477f RE |
24252 | } |
24253 | ||
e74cfd16 | 24254 | if (!mfpu_opt) |
03b1477f | 24255 | { |
493cb6ef | 24256 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 24257 | mfpu_opt = &fpu_default; |
493cb6ef | 24258 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 24259 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 24260 | else |
e74cfd16 | 24261 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
24262 | } |
24263 | ||
ee065d83 | 24264 | #ifdef CPU_DEFAULT |
e74cfd16 | 24265 | if (!mcpu_cpu_opt) |
ee065d83 | 24266 | { |
e74cfd16 PB |
24267 | mcpu_cpu_opt = &cpu_default; |
24268 | selected_cpu = cpu_default; | |
ee065d83 | 24269 | } |
73f43896 NC |
24270 | else if (no_cpu_selected ()) |
24271 | selected_cpu = cpu_default; | |
e74cfd16 PB |
24272 | #else |
24273 | if (mcpu_cpu_opt) | |
24274 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 24275 | else |
e74cfd16 | 24276 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 24277 | #endif |
03b1477f | 24278 | |
e74cfd16 | 24279 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 24280 | |
3e9e4fcf JB |
24281 | autoselect_thumb_from_cpu_variant (); |
24282 | ||
e74cfd16 | 24283 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 24284 | |
f17c130b | 24285 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 24286 | { |
7cc69913 NC |
24287 | unsigned int flags = 0; |
24288 | ||
24289 | #if defined OBJ_ELF | |
24290 | flags = meabi_flags; | |
d507cf36 PB |
24291 | |
24292 | switch (meabi_flags) | |
33a392fb | 24293 | { |
d507cf36 | 24294 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 24295 | #endif |
d507cf36 PB |
24296 | /* Set the flags in the private structure. */ |
24297 | if (uses_apcs_26) flags |= F_APCS26; | |
24298 | if (support_interwork) flags |= F_INTERWORK; | |
24299 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 24300 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 24301 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
24302 | flags |= F_SOFT_FLOAT; |
24303 | ||
d507cf36 PB |
24304 | switch (mfloat_abi_opt) |
24305 | { | |
24306 | case ARM_FLOAT_ABI_SOFT: | |
24307 | case ARM_FLOAT_ABI_SOFTFP: | |
24308 | flags |= F_SOFT_FLOAT; | |
24309 | break; | |
33a392fb | 24310 | |
d507cf36 PB |
24311 | case ARM_FLOAT_ABI_HARD: |
24312 | if (flags & F_SOFT_FLOAT) | |
24313 | as_bad (_("hard-float conflicts with specified fpu")); | |
24314 | break; | |
24315 | } | |
03b1477f | 24316 | |
e74cfd16 PB |
24317 | /* Using pure-endian doubles (even if soft-float). */ |
24318 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 24319 | flags |= F_VFP_FLOAT; |
f17c130b | 24320 | |
fde78edd | 24321 | #if defined OBJ_ELF |
e74cfd16 | 24322 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 24323 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
24324 | break; |
24325 | ||
8cb51566 | 24326 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 24327 | case EF_ARM_EABI_VER5: |
c19d1205 | 24328 | /* No additional flags to set. */ |
d507cf36 PB |
24329 | break; |
24330 | ||
24331 | default: | |
24332 | abort (); | |
24333 | } | |
7cc69913 | 24334 | #endif |
b99bd4ef NC |
24335 | bfd_set_private_flags (stdoutput, flags); |
24336 | ||
24337 | /* We have run out flags in the COFF header to encode the | |
24338 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 24339 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
24340 | if (atpcs) |
24341 | { | |
24342 | asection * sec; | |
24343 | ||
24344 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
24345 | ||
24346 | if (sec != NULL) | |
24347 | { | |
24348 | bfd_set_section_flags | |
24349 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
24350 | bfd_set_section_size (stdoutput, sec, 0); | |
24351 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
24352 | } | |
24353 | } | |
7cc69913 | 24354 | } |
f17c130b | 24355 | #endif |
b99bd4ef NC |
24356 | |
24357 | /* Record the CPU type as well. */ | |
2d447fca JM |
24358 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
24359 | mach = bfd_mach_arm_iWMMXt2; | |
24360 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 24361 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 24362 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 24363 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 24364 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 24365 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 24366 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 24367 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 24368 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 24369 | { |
e74cfd16 | 24370 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24371 | mach = bfd_mach_arm_5T; |
24372 | else | |
24373 | mach = bfd_mach_arm_5; | |
24374 | } | |
e74cfd16 | 24375 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 24376 | { |
e74cfd16 | 24377 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24378 | mach = bfd_mach_arm_4T; |
24379 | else | |
24380 | mach = bfd_mach_arm_4; | |
24381 | } | |
e74cfd16 | 24382 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 24383 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
24384 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
24385 | mach = bfd_mach_arm_3; | |
24386 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
24387 | mach = bfd_mach_arm_2a; | |
24388 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
24389 | mach = bfd_mach_arm_2; | |
24390 | else | |
24391 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
24392 | |
24393 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
24394 | } | |
24395 | ||
c19d1205 | 24396 | /* Command line processing. */ |
b99bd4ef | 24397 | |
c19d1205 ZW |
24398 | /* md_parse_option |
24399 | Invocation line includes a switch not recognized by the base assembler. | |
24400 | See if it's a processor-specific option. | |
b99bd4ef | 24401 | |
c19d1205 ZW |
24402 | This routine is somewhat complicated by the need for backwards |
24403 | compatibility (since older releases of gcc can't be changed). | |
24404 | The new options try to make the interface as compatible as | |
24405 | possible with GCC. | |
b99bd4ef | 24406 | |
c19d1205 | 24407 | New options (supported) are: |
b99bd4ef | 24408 | |
c19d1205 ZW |
24409 | -mcpu=<cpu name> Assemble for selected processor |
24410 | -march=<architecture name> Assemble for selected architecture | |
24411 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
24412 | -EB/-mbig-endian Big-endian | |
24413 | -EL/-mlittle-endian Little-endian | |
24414 | -k Generate PIC code | |
24415 | -mthumb Start in Thumb mode | |
24416 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 24417 | |
278df34e | 24418 | -m[no-]warn-deprecated Warn about deprecated features |
8b2d793c | 24419 | -m[no-]warn-syms Warn when symbols match instructions |
267bf995 | 24420 | |
c19d1205 | 24421 | For now we will also provide support for: |
b99bd4ef | 24422 | |
c19d1205 ZW |
24423 | -mapcs-32 32-bit Program counter |
24424 | -mapcs-26 26-bit Program counter | |
24425 | -macps-float Floats passed in FP registers | |
24426 | -mapcs-reentrant Reentrant code | |
24427 | -matpcs | |
24428 | (sometime these will probably be replaced with -mapcs=<list of options> | |
24429 | and -matpcs=<list of options>) | |
b99bd4ef | 24430 | |
c19d1205 ZW |
24431 | The remaining options are only supported for back-wards compatibility. |
24432 | Cpu variants, the arm part is optional: | |
24433 | -m[arm]1 Currently not supported. | |
24434 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
24435 | -m[arm]3 Arm 3 processor | |
24436 | -m[arm]6[xx], Arm 6 processors | |
24437 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
24438 | -m[arm]8[10] Arm 8 processors | |
24439 | -m[arm]9[20][tdmi] Arm 9 processors | |
24440 | -mstrongarm[110[0]] StrongARM processors | |
24441 | -mxscale XScale processors | |
24442 | -m[arm]v[2345[t[e]]] Arm architectures | |
24443 | -mall All (except the ARM1) | |
24444 | FP variants: | |
24445 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
24446 | -mfpe-old (No float load/store multiples) | |
24447 | -mvfpxd VFP Single precision | |
24448 | -mvfp All VFP | |
24449 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 24450 | |
c19d1205 ZW |
24451 | The following CPU names are recognized: |
24452 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
24453 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
24454 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
24455 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
24456 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
24457 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
24458 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 24459 | |
c19d1205 | 24460 | */ |
b99bd4ef | 24461 | |
c19d1205 | 24462 | const char * md_shortopts = "m:k"; |
b99bd4ef | 24463 | |
c19d1205 ZW |
24464 | #ifdef ARM_BI_ENDIAN |
24465 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
24466 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 24467 | #else |
c19d1205 ZW |
24468 | #if TARGET_BYTES_BIG_ENDIAN |
24469 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 24470 | #else |
c19d1205 ZW |
24471 | #define OPTION_EL (OPTION_MD_BASE + 1) |
24472 | #endif | |
b99bd4ef | 24473 | #endif |
845b51d6 | 24474 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 24475 | |
c19d1205 | 24476 | struct option md_longopts[] = |
b99bd4ef | 24477 | { |
c19d1205 ZW |
24478 | #ifdef OPTION_EB |
24479 | {"EB", no_argument, NULL, OPTION_EB}, | |
24480 | #endif | |
24481 | #ifdef OPTION_EL | |
24482 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 24483 | #endif |
845b51d6 | 24484 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
24485 | {NULL, no_argument, NULL, 0} |
24486 | }; | |
b99bd4ef | 24487 | |
8b2d793c | 24488 | |
c19d1205 | 24489 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 24490 | |
c19d1205 | 24491 | struct arm_option_table |
b99bd4ef | 24492 | { |
c19d1205 ZW |
24493 | char *option; /* Option name to match. */ |
24494 | char *help; /* Help information. */ | |
24495 | int *var; /* Variable to change. */ | |
24496 | int value; /* What to change it to. */ | |
24497 | char *deprecated; /* If non-null, print this message. */ | |
24498 | }; | |
b99bd4ef | 24499 | |
c19d1205 ZW |
24500 | struct arm_option_table arm_opts[] = |
24501 | { | |
24502 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
24503 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
24504 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
24505 | &support_interwork, 1, NULL}, | |
24506 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
24507 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
24508 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
24509 | 1, NULL}, | |
24510 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
24511 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
24512 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
24513 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
24514 | NULL}, | |
b99bd4ef | 24515 | |
c19d1205 ZW |
24516 | /* These are recognized by the assembler, but have no affect on code. */ |
24517 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
24518 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
24519 | |
24520 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
24521 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
24522 | &warn_on_deprecated, 0, NULL}, | |
8b2d793c NC |
24523 | {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL}, |
24524 | {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL}, | |
e74cfd16 PB |
24525 | {NULL, NULL, NULL, 0, NULL} |
24526 | }; | |
24527 | ||
24528 | struct arm_legacy_option_table | |
24529 | { | |
24530 | char *option; /* Option name to match. */ | |
24531 | const arm_feature_set **var; /* Variable to change. */ | |
24532 | const arm_feature_set value; /* What to change it to. */ | |
24533 | char *deprecated; /* If non-null, print this message. */ | |
24534 | }; | |
b99bd4ef | 24535 | |
e74cfd16 PB |
24536 | const struct arm_legacy_option_table arm_legacy_opts[] = |
24537 | { | |
c19d1205 ZW |
24538 | /* DON'T add any new processors to this list -- we want the whole list |
24539 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
24540 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
24541 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
24542 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24543 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24544 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24545 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24546 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24547 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24548 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24549 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24550 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24551 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24552 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24553 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24554 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24555 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24556 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24557 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24558 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24559 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24560 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24561 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24562 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24563 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24564 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24565 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24566 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24567 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24568 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24569 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24570 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24571 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24572 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24573 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24574 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24575 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24576 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24577 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24578 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24579 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24580 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24581 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24582 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24583 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24584 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24585 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24586 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24587 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24588 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24589 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24590 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24591 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24592 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24593 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24594 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24595 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24596 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24597 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24598 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24599 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24600 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24601 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24602 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24603 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24604 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24605 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24606 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24607 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24608 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
24609 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 24610 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 24611 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24612 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 24613 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24614 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
24615 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
24616 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
24617 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 24618 | |
c19d1205 | 24619 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24620 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
24621 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
24622 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24623 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24624 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24625 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24626 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24627 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24628 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24629 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24630 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24631 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24632 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24633 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24634 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24635 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24636 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
24637 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 24638 | |
c19d1205 | 24639 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24640 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
24641 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
24642 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
24643 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 24644 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 24645 | |
e74cfd16 | 24646 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 24647 | }; |
7ed4c4c5 | 24648 | |
c19d1205 | 24649 | struct arm_cpu_option_table |
7ed4c4c5 | 24650 | { |
c19d1205 | 24651 | char *name; |
f3bad469 | 24652 | size_t name_len; |
e74cfd16 | 24653 | const arm_feature_set value; |
c19d1205 ZW |
24654 | /* For some CPUs we assume an FPU unless the user explicitly sets |
24655 | -mfpu=... */ | |
e74cfd16 | 24656 | const arm_feature_set default_fpu; |
ee065d83 PB |
24657 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
24658 | case. */ | |
24659 | const char *canonical_name; | |
c19d1205 | 24660 | }; |
7ed4c4c5 | 24661 | |
c19d1205 ZW |
24662 | /* This list should, at a minimum, contain all the cpu names |
24663 | recognized by GCC. */ | |
f3bad469 | 24664 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 24665 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 24666 | { |
f3bad469 MGD |
24667 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
24668 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
24669 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
24670 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24671 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24672 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24673 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24674 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24675 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24676 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24677 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24678 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24679 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24680 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24681 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24682 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24683 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24684 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24685 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24686 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24687 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24688 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24689 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24690 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24691 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24692 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24693 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24694 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24695 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24696 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24697 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24698 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24699 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24700 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24701 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24702 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24703 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24704 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24705 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24706 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
24707 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24708 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24709 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24710 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24711 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24712 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
24713 | /* For V5 or later processors we default to using VFP; but the user |
24714 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
24715 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
24716 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24717 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24718 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24719 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24720 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24721 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
24722 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24723 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24724 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
24725 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24726 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24727 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24728 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24729 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24730 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
24731 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24732 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24733 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24734 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
24735 | "ARM1026EJ-S"), | |
24736 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24737 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24738 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24739 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24740 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24741 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24742 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
24743 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
24744 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
24745 | "ARM1136JF-S"), | |
24746 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
24747 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
24748 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
24749 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
24750 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
24751 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL), | |
24752 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL), | |
24753 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, | |
24754 | FPU_NONE, "Cortex-A5"), | |
c9fb6e58 | 24755 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 MGD |
24756 | "Cortex-A7"), |
24757 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
823d2571 | 24758 | ARM_FEATURE_COPROC (FPU_VFP_V3 |
477330fc | 24759 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
24760 | "Cortex-A8"), |
24761 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
823d2571 | 24762 | ARM_FEATURE_COPROC (FPU_VFP_V3 |
477330fc | 24763 | | FPU_NEON_EXT_V1), |
f3bad469 | 24764 | "Cortex-A9"), |
c9fb6e58 | 24765 | ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
63a4bc21 | 24766 | "Cortex-A12"), |
c9fb6e58 | 24767 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 | 24768 | "Cortex-A15"), |
d7adf960 KT |
24769 | ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
24770 | "Cortex-A17"), | |
92eb40d9 | 24771 | ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24772 | "Cortex-A53"), |
92eb40d9 | 24773 | ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24774 | "Cortex-A57"), |
b19f47ad JW |
24775 | ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
24776 | "Cortex-A72"), | |
f3bad469 MGD |
24777 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), |
24778 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
24779 | "Cortex-R4F"), | |
24780 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
24781 | FPU_NONE, "Cortex-R5"), | |
70a8bc5b | 24782 | ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV, |
24783 | FPU_ARCH_VFP_V3D16, | |
24784 | "Cortex-R7"), | |
a715796b | 24785 | ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"), |
f3bad469 MGD |
24786 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), |
24787 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
24788 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
24789 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
ce32bd10 | 24790 | ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), |
246496bb EM |
24791 | ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
24792 | "Samsung " \ | |
24793 | "Exynos M1"), | |
c19d1205 | 24794 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 24795 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 24796 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
24797 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
24798 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
24799 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 24800 | /* Maverick */ |
823d2571 | 24801 | ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
da4339ed NC |
24802 | FPU_ARCH_MAVERICK, "ARM920T"), |
24803 | /* Marvell processors. */ | |
823d2571 TG |
24804 | ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP |
24805 | | ARM_EXT_SEC), | |
477330fc | 24806 | FPU_ARCH_VFP_V3D16, NULL), |
823d2571 TG |
24807 | ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP |
24808 | | ARM_EXT_SEC), | |
4347085a | 24809 | FPU_ARCH_NEON_VFP_V4, NULL), |
ea0d6bb9 PT |
24810 | /* APM X-Gene family. */ |
24811 | ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
24812 | "APM X-Gene 1"), | |
24813 | ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
24814 | "APM X-Gene 2"), | |
da4339ed | 24815 | |
f3bad469 | 24816 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
c19d1205 | 24817 | }; |
f3bad469 | 24818 | #undef ARM_CPU_OPT |
7ed4c4c5 | 24819 | |
c19d1205 | 24820 | struct arm_arch_option_table |
7ed4c4c5 | 24821 | { |
c19d1205 | 24822 | char *name; |
f3bad469 | 24823 | size_t name_len; |
e74cfd16 PB |
24824 | const arm_feature_set value; |
24825 | const arm_feature_set default_fpu; | |
c19d1205 | 24826 | }; |
7ed4c4c5 | 24827 | |
c19d1205 ZW |
24828 | /* This list should, at a minimum, contain all the architecture names |
24829 | recognized by GCC. */ | |
f3bad469 | 24830 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 24831 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 24832 | { |
f3bad469 MGD |
24833 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
24834 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
24835 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
24836 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24837 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24838 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
24839 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
24840 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
24841 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
24842 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
24843 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
24844 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
24845 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
24846 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
24847 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
24848 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
24849 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
24850 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24851 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24852 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
24853 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
24854 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP), | |
24855 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
24856 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
24857 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
24858 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP), | |
24859 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
24860 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
24861 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
24862 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
24863 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 | 24864 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
c9fb6e58 | 24865 | ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP), |
f3bad469 MGD |
24866 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), |
24867 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24868 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
24869 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
24870 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24871 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
bca38921 | 24872 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), |
a5932920 | 24873 | ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP), |
f3bad469 MGD |
24874 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
24875 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
24876 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
24877 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 24878 | }; |
f3bad469 | 24879 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 24880 | |
69133863 MGD |
24881 | /* ISA extensions in the co-processor and main instruction set space. */ |
24882 | struct arm_option_extension_value_table | |
c19d1205 ZW |
24883 | { |
24884 | char *name; | |
f3bad469 | 24885 | size_t name_len; |
5a70a223 JB |
24886 | const arm_feature_set merge_value; |
24887 | const arm_feature_set clear_value; | |
69133863 | 24888 | const arm_feature_set allowed_archs; |
c19d1205 | 24889 | }; |
7ed4c4c5 | 24890 | |
69133863 MGD |
24891 | /* The following table must be in alphabetical order with a NULL last entry. |
24892 | */ | |
5a70a223 | 24893 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA } |
69133863 | 24894 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 24895 | { |
823d2571 TG |
24896 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
24897 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
bca38921 | 24898 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
823d2571 TG |
24899 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), |
24900 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
24901 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), | |
24902 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
24903 | ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), | |
24904 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), | |
24905 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)), | |
24906 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), | |
24907 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ANY), | |
24908 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), | |
24909 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ANY), | |
24910 | ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), | |
24911 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ANY), | |
24912 | ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
24913 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
24914 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)), | |
bca38921 | 24915 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
823d2571 TG |
24916 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8), |
24917 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
24918 | ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
24919 | ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
24920 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), | |
ddfded2f MW |
24921 | ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), |
24922 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), | |
24923 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
24924 | ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
24925 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), | |
24926 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V7A)), | |
24927 | ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV | |
24928 | | ARM_EXT_DIV), | |
24929 | ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), | |
24930 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
d6b4b13e MW |
24931 | ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8, |
24932 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), | |
24933 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
24934 | ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
24935 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY), | |
5a70a223 | 24936 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE } |
69133863 | 24937 | }; |
f3bad469 | 24938 | #undef ARM_EXT_OPT |
69133863 MGD |
24939 | |
24940 | /* ISA floating-point and Advanced SIMD extensions. */ | |
24941 | struct arm_option_fpu_value_table | |
24942 | { | |
24943 | char *name; | |
24944 | const arm_feature_set value; | |
c19d1205 | 24945 | }; |
7ed4c4c5 | 24946 | |
c19d1205 ZW |
24947 | /* This list should, at a minimum, contain all the fpu names |
24948 | recognized by GCC. */ | |
69133863 | 24949 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
24950 | { |
24951 | {"softfpa", FPU_NONE}, | |
24952 | {"fpe", FPU_ARCH_FPE}, | |
24953 | {"fpe2", FPU_ARCH_FPE}, | |
24954 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
24955 | {"fpa", FPU_ARCH_FPA}, | |
24956 | {"fpa10", FPU_ARCH_FPA}, | |
24957 | {"fpa11", FPU_ARCH_FPA}, | |
24958 | {"arm7500fe", FPU_ARCH_FPA}, | |
24959 | {"softvfp", FPU_ARCH_VFP}, | |
24960 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
24961 | {"vfp", FPU_ARCH_VFP_V2}, | |
24962 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 24963 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
24964 | {"vfp10", FPU_ARCH_VFP_V2}, |
24965 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
24966 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
24967 | {"vfpv2", FPU_ARCH_VFP_V2}, |
24968 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 24969 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 24970 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
24971 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
24972 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
24973 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
24974 | {"arm1020t", FPU_ARCH_VFP_V1}, |
24975 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
24976 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
24977 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
24978 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 24979 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 24980 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
24981 | {"vfpv4", FPU_ARCH_VFP_V4}, |
24982 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 24983 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
a715796b TG |
24984 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
24985 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, | |
62f3b8c8 | 24986 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
24987 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
24988 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
24989 | {"crypto-neon-fp-armv8", | |
24990 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
d6b4b13e | 24991 | {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1}, |
e74cfd16 PB |
24992 | {NULL, ARM_ARCH_NONE} |
24993 | }; | |
24994 | ||
24995 | struct arm_option_value_table | |
24996 | { | |
24997 | char *name; | |
24998 | long value; | |
c19d1205 | 24999 | }; |
7ed4c4c5 | 25000 | |
e74cfd16 | 25001 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
25002 | { |
25003 | {"hard", ARM_FLOAT_ABI_HARD}, | |
25004 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
25005 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 25006 | {NULL, 0} |
c19d1205 | 25007 | }; |
7ed4c4c5 | 25008 | |
c19d1205 | 25009 | #ifdef OBJ_ELF |
3a4a14e9 | 25010 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 25011 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
25012 | { |
25013 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
25014 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 25015 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 25016 | {NULL, 0} |
c19d1205 ZW |
25017 | }; |
25018 | #endif | |
7ed4c4c5 | 25019 | |
c19d1205 ZW |
25020 | struct arm_long_option_table |
25021 | { | |
25022 | char * option; /* Substring to match. */ | |
25023 | char * help; /* Help information. */ | |
25024 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
25025 | char * deprecated; /* If non-null, print this message. */ | |
25026 | }; | |
7ed4c4c5 | 25027 | |
c921be7d | 25028 | static bfd_boolean |
f3bad469 | 25029 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 25030 | { |
21d799b5 NC |
25031 | arm_feature_set *ext_set = (arm_feature_set *) |
25032 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 25033 | |
69133863 | 25034 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
25035 | extensions being added before being removed. We achieve this by having |
25036 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 25037 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 25038 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
25039 | -1 -> 1 -> 0. */ |
25040 | const struct arm_option_extension_value_table * opt = NULL; | |
25041 | int adding_value = -1; | |
25042 | ||
e74cfd16 PB |
25043 | /* Copy the feature set, so that we can modify it. */ |
25044 | *ext_set = **opt_p; | |
25045 | *opt_p = ext_set; | |
25046 | ||
c19d1205 | 25047 | while (str != NULL && *str != 0) |
7ed4c4c5 | 25048 | { |
f3bad469 MGD |
25049 | char *ext; |
25050 | size_t len; | |
7ed4c4c5 | 25051 | |
c19d1205 ZW |
25052 | if (*str != '+') |
25053 | { | |
25054 | as_bad (_("invalid architectural extension")); | |
c921be7d | 25055 | return FALSE; |
c19d1205 | 25056 | } |
7ed4c4c5 | 25057 | |
c19d1205 ZW |
25058 | str++; |
25059 | ext = strchr (str, '+'); | |
7ed4c4c5 | 25060 | |
c19d1205 | 25061 | if (ext != NULL) |
f3bad469 | 25062 | len = ext - str; |
c19d1205 | 25063 | else |
f3bad469 | 25064 | len = strlen (str); |
7ed4c4c5 | 25065 | |
f3bad469 | 25066 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
25067 | { |
25068 | if (adding_value != 0) | |
25069 | { | |
25070 | adding_value = 0; | |
25071 | opt = arm_extensions; | |
25072 | } | |
25073 | ||
f3bad469 | 25074 | len -= 2; |
69133863 MGD |
25075 | str += 2; |
25076 | } | |
f3bad469 | 25077 | else if (len > 0) |
69133863 MGD |
25078 | { |
25079 | if (adding_value == -1) | |
25080 | { | |
25081 | adding_value = 1; | |
25082 | opt = arm_extensions; | |
25083 | } | |
25084 | else if (adding_value != 1) | |
25085 | { | |
25086 | as_bad (_("must specify extensions to add before specifying " | |
25087 | "those to remove")); | |
25088 | return FALSE; | |
25089 | } | |
25090 | } | |
25091 | ||
f3bad469 | 25092 | if (len == 0) |
c19d1205 ZW |
25093 | { |
25094 | as_bad (_("missing architectural extension")); | |
c921be7d | 25095 | return FALSE; |
c19d1205 | 25096 | } |
7ed4c4c5 | 25097 | |
69133863 MGD |
25098 | gas_assert (adding_value != -1); |
25099 | gas_assert (opt != NULL); | |
25100 | ||
25101 | /* Scan over the options table trying to find an exact match. */ | |
25102 | for (; opt->name != NULL; opt++) | |
f3bad469 | 25103 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 25104 | { |
69133863 MGD |
25105 | /* Check we can apply the extension to this architecture. */ |
25106 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
25107 | { | |
25108 | as_bad (_("extension does not apply to the base architecture")); | |
25109 | return FALSE; | |
25110 | } | |
25111 | ||
25112 | /* Add or remove the extension. */ | |
25113 | if (adding_value) | |
5a70a223 | 25114 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
69133863 | 25115 | else |
5a70a223 | 25116 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
69133863 | 25117 | |
c19d1205 ZW |
25118 | break; |
25119 | } | |
7ed4c4c5 | 25120 | |
c19d1205 ZW |
25121 | if (opt->name == NULL) |
25122 | { | |
69133863 MGD |
25123 | /* Did we fail to find an extension because it wasn't specified in |
25124 | alphabetical order, or because it does not exist? */ | |
25125 | ||
25126 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 25127 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
25128 | break; |
25129 | ||
25130 | if (opt->name == NULL) | |
25131 | as_bad (_("unknown architectural extension `%s'"), str); | |
25132 | else | |
25133 | as_bad (_("architectural extensions must be specified in " | |
25134 | "alphabetical order")); | |
25135 | ||
c921be7d | 25136 | return FALSE; |
c19d1205 | 25137 | } |
69133863 MGD |
25138 | else |
25139 | { | |
25140 | /* We should skip the extension we've just matched the next time | |
25141 | round. */ | |
25142 | opt++; | |
25143 | } | |
7ed4c4c5 | 25144 | |
c19d1205 ZW |
25145 | str = ext; |
25146 | }; | |
7ed4c4c5 | 25147 | |
c921be7d | 25148 | return TRUE; |
c19d1205 | 25149 | } |
7ed4c4c5 | 25150 | |
c921be7d | 25151 | static bfd_boolean |
f3bad469 | 25152 | arm_parse_cpu (char *str) |
7ed4c4c5 | 25153 | { |
f3bad469 MGD |
25154 | const struct arm_cpu_option_table *opt; |
25155 | char *ext = strchr (str, '+'); | |
25156 | size_t len; | |
7ed4c4c5 | 25157 | |
c19d1205 | 25158 | if (ext != NULL) |
f3bad469 | 25159 | len = ext - str; |
7ed4c4c5 | 25160 | else |
f3bad469 | 25161 | len = strlen (str); |
7ed4c4c5 | 25162 | |
f3bad469 | 25163 | if (len == 0) |
7ed4c4c5 | 25164 | { |
c19d1205 | 25165 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 25166 | return FALSE; |
7ed4c4c5 NC |
25167 | } |
25168 | ||
c19d1205 | 25169 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 25170 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 25171 | { |
e74cfd16 PB |
25172 | mcpu_cpu_opt = &opt->value; |
25173 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 25174 | if (opt->canonical_name) |
5f4273c7 | 25175 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
25176 | else |
25177 | { | |
f3bad469 | 25178 | size_t i; |
c921be7d | 25179 | |
f3bad469 | 25180 | for (i = 0; i < len; i++) |
ee065d83 PB |
25181 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
25182 | selected_cpu_name[i] = 0; | |
25183 | } | |
7ed4c4c5 | 25184 | |
c19d1205 ZW |
25185 | if (ext != NULL) |
25186 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 25187 | |
c921be7d | 25188 | return TRUE; |
c19d1205 | 25189 | } |
7ed4c4c5 | 25190 | |
c19d1205 | 25191 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 25192 | return FALSE; |
7ed4c4c5 NC |
25193 | } |
25194 | ||
c921be7d | 25195 | static bfd_boolean |
f3bad469 | 25196 | arm_parse_arch (char *str) |
7ed4c4c5 | 25197 | { |
e74cfd16 | 25198 | const struct arm_arch_option_table *opt; |
c19d1205 | 25199 | char *ext = strchr (str, '+'); |
f3bad469 | 25200 | size_t len; |
7ed4c4c5 | 25201 | |
c19d1205 | 25202 | if (ext != NULL) |
f3bad469 | 25203 | len = ext - str; |
7ed4c4c5 | 25204 | else |
f3bad469 | 25205 | len = strlen (str); |
7ed4c4c5 | 25206 | |
f3bad469 | 25207 | if (len == 0) |
7ed4c4c5 | 25208 | { |
c19d1205 | 25209 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 25210 | return FALSE; |
7ed4c4c5 NC |
25211 | } |
25212 | ||
c19d1205 | 25213 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 25214 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 25215 | { |
e74cfd16 PB |
25216 | march_cpu_opt = &opt->value; |
25217 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 25218 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 25219 | |
c19d1205 ZW |
25220 | if (ext != NULL) |
25221 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 25222 | |
c921be7d | 25223 | return TRUE; |
c19d1205 ZW |
25224 | } |
25225 | ||
25226 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 25227 | return FALSE; |
7ed4c4c5 | 25228 | } |
eb043451 | 25229 | |
c921be7d | 25230 | static bfd_boolean |
c19d1205 ZW |
25231 | arm_parse_fpu (char * str) |
25232 | { | |
69133863 | 25233 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 25234 | |
c19d1205 ZW |
25235 | for (opt = arm_fpus; opt->name != NULL; opt++) |
25236 | if (streq (opt->name, str)) | |
25237 | { | |
e74cfd16 | 25238 | mfpu_opt = &opt->value; |
c921be7d | 25239 | return TRUE; |
c19d1205 | 25240 | } |
b99bd4ef | 25241 | |
c19d1205 | 25242 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 25243 | return FALSE; |
c19d1205 ZW |
25244 | } |
25245 | ||
c921be7d | 25246 | static bfd_boolean |
c19d1205 | 25247 | arm_parse_float_abi (char * str) |
b99bd4ef | 25248 | { |
e74cfd16 | 25249 | const struct arm_option_value_table * opt; |
b99bd4ef | 25250 | |
c19d1205 ZW |
25251 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
25252 | if (streq (opt->name, str)) | |
25253 | { | |
25254 | mfloat_abi_opt = opt->value; | |
c921be7d | 25255 | return TRUE; |
c19d1205 | 25256 | } |
cc8a6dd0 | 25257 | |
c19d1205 | 25258 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 25259 | return FALSE; |
c19d1205 | 25260 | } |
b99bd4ef | 25261 | |
c19d1205 | 25262 | #ifdef OBJ_ELF |
c921be7d | 25263 | static bfd_boolean |
c19d1205 ZW |
25264 | arm_parse_eabi (char * str) |
25265 | { | |
e74cfd16 | 25266 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 25267 | |
c19d1205 ZW |
25268 | for (opt = arm_eabis; opt->name != NULL; opt++) |
25269 | if (streq (opt->name, str)) | |
25270 | { | |
25271 | meabi_flags = opt->value; | |
c921be7d | 25272 | return TRUE; |
c19d1205 ZW |
25273 | } |
25274 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 25275 | return FALSE; |
c19d1205 ZW |
25276 | } |
25277 | #endif | |
cc8a6dd0 | 25278 | |
c921be7d | 25279 | static bfd_boolean |
e07e6e58 NC |
25280 | arm_parse_it_mode (char * str) |
25281 | { | |
c921be7d | 25282 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
25283 | |
25284 | if (streq ("arm", str)) | |
25285 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
25286 | else if (streq ("thumb", str)) | |
25287 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
25288 | else if (streq ("always", str)) | |
25289 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
25290 | else if (streq ("never", str)) | |
25291 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
25292 | else | |
25293 | { | |
25294 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 25295 | "arm, thumb, always, or never."), str); |
c921be7d | 25296 | ret = FALSE; |
e07e6e58 NC |
25297 | } |
25298 | ||
25299 | return ret; | |
25300 | } | |
25301 | ||
2e6976a8 DG |
25302 | static bfd_boolean |
25303 | arm_ccs_mode (char * unused ATTRIBUTE_UNUSED) | |
25304 | { | |
25305 | codecomposer_syntax = TRUE; | |
25306 | arm_comment_chars[0] = ';'; | |
25307 | arm_line_separator_chars[0] = 0; | |
25308 | return TRUE; | |
25309 | } | |
25310 | ||
c19d1205 ZW |
25311 | struct arm_long_option_table arm_long_opts[] = |
25312 | { | |
25313 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
25314 | arm_parse_cpu, NULL}, | |
25315 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
25316 | arm_parse_arch, NULL}, | |
25317 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
25318 | arm_parse_fpu, NULL}, | |
25319 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
25320 | arm_parse_float_abi, NULL}, | |
25321 | #ifdef OBJ_ELF | |
7fac0536 | 25322 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
25323 | arm_parse_eabi, NULL}, |
25324 | #endif | |
e07e6e58 NC |
25325 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
25326 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
25327 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
25328 | arm_ccs_mode, NULL}, | |
c19d1205 ZW |
25329 | {NULL, NULL, 0, NULL} |
25330 | }; | |
cc8a6dd0 | 25331 | |
c19d1205 ZW |
25332 | int |
25333 | md_parse_option (int c, char * arg) | |
25334 | { | |
25335 | struct arm_option_table *opt; | |
e74cfd16 | 25336 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 25337 | struct arm_long_option_table *lopt; |
b99bd4ef | 25338 | |
c19d1205 | 25339 | switch (c) |
b99bd4ef | 25340 | { |
c19d1205 ZW |
25341 | #ifdef OPTION_EB |
25342 | case OPTION_EB: | |
25343 | target_big_endian = 1; | |
25344 | break; | |
25345 | #endif | |
cc8a6dd0 | 25346 | |
c19d1205 ZW |
25347 | #ifdef OPTION_EL |
25348 | case OPTION_EL: | |
25349 | target_big_endian = 0; | |
25350 | break; | |
25351 | #endif | |
b99bd4ef | 25352 | |
845b51d6 PB |
25353 | case OPTION_FIX_V4BX: |
25354 | fix_v4bx = TRUE; | |
25355 | break; | |
25356 | ||
c19d1205 ZW |
25357 | case 'a': |
25358 | /* Listing option. Just ignore these, we don't support additional | |
25359 | ones. */ | |
25360 | return 0; | |
b99bd4ef | 25361 | |
c19d1205 ZW |
25362 | default: |
25363 | for (opt = arm_opts; opt->option != NULL; opt++) | |
25364 | { | |
25365 | if (c == opt->option[0] | |
25366 | && ((arg == NULL && opt->option[1] == 0) | |
25367 | || streq (arg, opt->option + 1))) | |
25368 | { | |
c19d1205 | 25369 | /* If the option is deprecated, tell the user. */ |
278df34e | 25370 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
25371 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
25372 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 25373 | |
c19d1205 ZW |
25374 | if (opt->var != NULL) |
25375 | *opt->var = opt->value; | |
cc8a6dd0 | 25376 | |
c19d1205 ZW |
25377 | return 1; |
25378 | } | |
25379 | } | |
b99bd4ef | 25380 | |
e74cfd16 PB |
25381 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
25382 | { | |
25383 | if (c == fopt->option[0] | |
25384 | && ((arg == NULL && fopt->option[1] == 0) | |
25385 | || streq (arg, fopt->option + 1))) | |
25386 | { | |
e74cfd16 | 25387 | /* If the option is deprecated, tell the user. */ |
278df34e | 25388 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
25389 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
25390 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
25391 | |
25392 | if (fopt->var != NULL) | |
25393 | *fopt->var = &fopt->value; | |
25394 | ||
25395 | return 1; | |
25396 | } | |
25397 | } | |
25398 | ||
c19d1205 ZW |
25399 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25400 | { | |
25401 | /* These options are expected to have an argument. */ | |
25402 | if (c == lopt->option[0] | |
25403 | && arg != NULL | |
25404 | && strncmp (arg, lopt->option + 1, | |
25405 | strlen (lopt->option + 1)) == 0) | |
25406 | { | |
c19d1205 | 25407 | /* If the option is deprecated, tell the user. */ |
278df34e | 25408 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
25409 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
25410 | _(lopt->deprecated)); | |
b99bd4ef | 25411 | |
c19d1205 ZW |
25412 | /* Call the sup-option parser. */ |
25413 | return lopt->func (arg + strlen (lopt->option) - 1); | |
25414 | } | |
25415 | } | |
a737bd4d | 25416 | |
c19d1205 ZW |
25417 | return 0; |
25418 | } | |
a394c00f | 25419 | |
c19d1205 ZW |
25420 | return 1; |
25421 | } | |
a394c00f | 25422 | |
c19d1205 ZW |
25423 | void |
25424 | md_show_usage (FILE * fp) | |
a394c00f | 25425 | { |
c19d1205 ZW |
25426 | struct arm_option_table *opt; |
25427 | struct arm_long_option_table *lopt; | |
a394c00f | 25428 | |
c19d1205 | 25429 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 25430 | |
c19d1205 ZW |
25431 | for (opt = arm_opts; opt->option != NULL; opt++) |
25432 | if (opt->help != NULL) | |
25433 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 25434 | |
c19d1205 ZW |
25435 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25436 | if (lopt->help != NULL) | |
25437 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 25438 | |
c19d1205 ZW |
25439 | #ifdef OPTION_EB |
25440 | fprintf (fp, _("\ | |
25441 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
25442 | #endif |
25443 | ||
c19d1205 ZW |
25444 | #ifdef OPTION_EL |
25445 | fprintf (fp, _("\ | |
25446 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 25447 | #endif |
845b51d6 PB |
25448 | |
25449 | fprintf (fp, _("\ | |
25450 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 25451 | } |
ee065d83 PB |
25452 | |
25453 | ||
25454 | #ifdef OBJ_ELF | |
62b3e311 PB |
25455 | typedef struct |
25456 | { | |
25457 | int val; | |
25458 | arm_feature_set flags; | |
25459 | } cpu_arch_ver_table; | |
25460 | ||
25461 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
25462 | least features first. */ | |
25463 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
25464 | { | |
25465 | {1, ARM_ARCH_V4}, | |
25466 | {2, ARM_ARCH_V4T}, | |
25467 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 25468 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
25469 | {4, ARM_ARCH_V5TE}, |
25470 | {5, ARM_ARCH_V5TEJ}, | |
25471 | {6, ARM_ARCH_V6}, | |
7e806470 | 25472 | {9, ARM_ARCH_V6K}, |
f4c65163 | 25473 | {7, ARM_ARCH_V6Z}, |
91e22acd | 25474 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 25475 | {12, ARM_ARCH_V6SM}, |
7e806470 | 25476 | {8, ARM_ARCH_V6T2}, |
c9fb6e58 | 25477 | {10, ARM_ARCH_V7VE}, |
62b3e311 PB |
25478 | {10, ARM_ARCH_V7R}, |
25479 | {10, ARM_ARCH_V7M}, | |
bca38921 | 25480 | {14, ARM_ARCH_V8A}, |
62b3e311 PB |
25481 | {0, ARM_ARCH_NONE} |
25482 | }; | |
25483 | ||
ee3c0378 AS |
25484 | /* Set an attribute if it has not already been set by the user. */ |
25485 | static void | |
25486 | aeabi_set_attribute_int (int tag, int value) | |
25487 | { | |
25488 | if (tag < 1 | |
25489 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25490 | || !attributes_set_explicitly[tag]) | |
25491 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
25492 | } | |
25493 | ||
25494 | static void | |
25495 | aeabi_set_attribute_string (int tag, const char *value) | |
25496 | { | |
25497 | if (tag < 1 | |
25498 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25499 | || !attributes_set_explicitly[tag]) | |
25500 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
25501 | } | |
25502 | ||
ee065d83 | 25503 | /* Set the public EABI object attributes. */ |
3cfdb781 | 25504 | void |
ee065d83 PB |
25505 | aeabi_set_public_attributes (void) |
25506 | { | |
25507 | int arch; | |
69239280 | 25508 | char profile; |
90ec0d68 | 25509 | int virt_sec = 0; |
bca38921 | 25510 | int fp16_optional = 0; |
e74cfd16 | 25511 | arm_feature_set flags; |
62b3e311 PB |
25512 | arm_feature_set tmp; |
25513 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
25514 | |
25515 | /* Choose the architecture based on the capabilities of the requested cpu | |
25516 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
25517 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
25518 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
25519 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
25520 | |
25521 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
25522 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
25523 | ||
25524 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
25525 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
25526 | ||
7f78eb34 JW |
25527 | selected_cpu = flags; |
25528 | ||
ddd7f988 | 25529 | /* Allow the user to override the reported architecture. */ |
7a1d4c38 PB |
25530 | if (object_arch) |
25531 | { | |
25532 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
25533 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
25534 | } | |
25535 | ||
251665fc MGD |
25536 | /* We need to make sure that the attributes do not identify us as v6S-M |
25537 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
25538 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
25539 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
477330fc | 25540 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); |
251665fc | 25541 | |
62b3e311 PB |
25542 | tmp = flags; |
25543 | arch = 0; | |
25544 | for (p = cpu_arch_ver; p->val; p++) | |
25545 | { | |
25546 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
25547 | { | |
25548 | arch = p->val; | |
25549 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
25550 | } | |
25551 | } | |
ee065d83 | 25552 | |
9e3c6df6 PB |
25553 | /* The table lookup above finds the last architecture to contribute |
25554 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
25555 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
25556 | We can not search for the last entry which is entirely used, | |
25557 | because if no CPU is specified we build up only those flags | |
25558 | actually used. Perhaps we should separate out the specified | |
25559 | and implicit cases. Avoid taking this path for -march=all by | |
25560 | checking for contradictory v7-A / v7-M features. */ | |
25561 | if (arch == 10 | |
25562 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
25563 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
25564 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
25565 | arch = 13; | |
25566 | ||
ee065d83 PB |
25567 | /* Tag_CPU_name. */ |
25568 | if (selected_cpu_name[0]) | |
25569 | { | |
91d6fa6a | 25570 | char *q; |
ee065d83 | 25571 | |
91d6fa6a NC |
25572 | q = selected_cpu_name; |
25573 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
25574 | { |
25575 | int i; | |
5f4273c7 | 25576 | |
91d6fa6a NC |
25577 | q += 4; |
25578 | for (i = 0; q[i]; i++) | |
25579 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 25580 | } |
91d6fa6a | 25581 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 25582 | } |
62f3b8c8 | 25583 | |
ee065d83 | 25584 | /* Tag_CPU_arch. */ |
ee3c0378 | 25585 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 25586 | |
62b3e311 PB |
25587 | /* Tag_CPU_arch_profile. */ |
25588 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
69239280 | 25589 | profile = 'A'; |
62b3e311 | 25590 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
69239280 | 25591 | profile = 'R'; |
7e806470 | 25592 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
69239280 MGD |
25593 | profile = 'M'; |
25594 | else | |
25595 | profile = '\0'; | |
25596 | ||
25597 | if (profile != '\0') | |
25598 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 25599 | |
ee065d83 | 25600 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
25601 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
25602 | || arch == 0) | |
25603 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 25604 | |
ee065d83 | 25605 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
25606 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
25607 | || arch == 0) | |
25608 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
25609 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 25610 | |
ee065d83 | 25611 | /* Tag_VFP_arch. */ |
a715796b TG |
25612 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
25613 | aeabi_set_attribute_int (Tag_VFP_arch, | |
25614 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25615 | ? 7 : 8); | |
bca38921 | 25616 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
62f3b8c8 PB |
25617 | aeabi_set_attribute_int (Tag_VFP_arch, |
25618 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25619 | ? 5 : 6); | |
25620 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
25621 | { |
25622 | fp16_optional = 1; | |
25623 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
25624 | } | |
ada65aa3 | 25625 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
25626 | { |
25627 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
25628 | fp16_optional = 1; | |
25629 | } | |
ee3c0378 AS |
25630 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
25631 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
25632 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 25633 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 25634 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 25635 | |
4547cb56 NC |
25636 | /* Tag_ABI_HardFP_use. */ |
25637 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
25638 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
25639 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
25640 | ||
ee065d83 | 25641 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
25642 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
25643 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
25644 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
25645 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 25646 | |
ee3c0378 | 25647 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
bca38921 MGD |
25648 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
25649 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); | |
25650 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
25651 | { | |
25652 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
25653 | { | |
25654 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
25655 | } | |
25656 | else | |
25657 | { | |
25658 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
25659 | fp16_optional = 1; | |
25660 | } | |
25661 | } | |
fa94de6b | 25662 | |
ee3c0378 | 25663 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 25664 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 25665 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 25666 | |
69239280 MGD |
25667 | /* Tag_DIV_use. |
25668 | ||
25669 | We set Tag_DIV_use to two when integer divide instructions have been used | |
25670 | in ARM state, or when Thumb integer divide instructions have been used, | |
25671 | but we have no architecture profile set, nor have we any ARM instructions. | |
25672 | ||
bca38921 MGD |
25673 | For ARMv8 we set the tag to 0 as integer divide is implied by the base |
25674 | architecture. | |
25675 | ||
69239280 | 25676 | For new architectures we will have to check these tests. */ |
bca38921 MGD |
25677 | gas_assert (arch <= TAG_CPU_ARCH_V8); |
25678 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) | |
25679 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
25680 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
25681 | || (profile == '\0' | |
25682 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
25683 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 25684 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
25685 | |
25686 | /* Tag_MP_extension_use. */ | |
25687 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
25688 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
25689 | |
25690 | /* Tag Virtualization_use. */ | |
25691 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
25692 | virt_sec |= 1; |
25693 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
25694 | virt_sec |= 2; | |
25695 | if (virt_sec != 0) | |
25696 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
25697 | } |
25698 | ||
104d59d1 | 25699 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
25700 | void |
25701 | arm_md_end (void) | |
25702 | { | |
ee065d83 PB |
25703 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
25704 | return; | |
25705 | ||
25706 | aeabi_set_public_attributes (); | |
ee065d83 | 25707 | } |
8463be01 | 25708 | #endif /* OBJ_ELF */ |
ee065d83 PB |
25709 | |
25710 | ||
25711 | /* Parse a .cpu directive. */ | |
25712 | ||
25713 | static void | |
25714 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
25715 | { | |
e74cfd16 | 25716 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
25717 | char *name; |
25718 | char saved_char; | |
25719 | ||
25720 | name = input_line_pointer; | |
5f4273c7 | 25721 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25722 | input_line_pointer++; |
25723 | saved_char = *input_line_pointer; | |
25724 | *input_line_pointer = 0; | |
25725 | ||
25726 | /* Skip the first "all" entry. */ | |
25727 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
25728 | if (streq (opt->name, name)) | |
25729 | { | |
e74cfd16 PB |
25730 | mcpu_cpu_opt = &opt->value; |
25731 | selected_cpu = opt->value; | |
ee065d83 | 25732 | if (opt->canonical_name) |
5f4273c7 | 25733 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
25734 | else |
25735 | { | |
25736 | int i; | |
25737 | for (i = 0; opt->name[i]; i++) | |
25738 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 25739 | |
ee065d83 PB |
25740 | selected_cpu_name[i] = 0; |
25741 | } | |
e74cfd16 | 25742 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25743 | *input_line_pointer = saved_char; |
25744 | demand_empty_rest_of_line (); | |
25745 | return; | |
25746 | } | |
25747 | as_bad (_("unknown cpu `%s'"), name); | |
25748 | *input_line_pointer = saved_char; | |
25749 | ignore_rest_of_line (); | |
25750 | } | |
25751 | ||
25752 | ||
25753 | /* Parse a .arch directive. */ | |
25754 | ||
25755 | static void | |
25756 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
25757 | { | |
e74cfd16 | 25758 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
25759 | char saved_char; |
25760 | char *name; | |
25761 | ||
25762 | name = input_line_pointer; | |
5f4273c7 | 25763 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25764 | input_line_pointer++; |
25765 | saved_char = *input_line_pointer; | |
25766 | *input_line_pointer = 0; | |
25767 | ||
25768 | /* Skip the first "all" entry. */ | |
25769 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25770 | if (streq (opt->name, name)) | |
25771 | { | |
e74cfd16 PB |
25772 | mcpu_cpu_opt = &opt->value; |
25773 | selected_cpu = opt->value; | |
5f4273c7 | 25774 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 25775 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25776 | *input_line_pointer = saved_char; |
25777 | demand_empty_rest_of_line (); | |
25778 | return; | |
25779 | } | |
25780 | ||
25781 | as_bad (_("unknown architecture `%s'\n"), name); | |
25782 | *input_line_pointer = saved_char; | |
25783 | ignore_rest_of_line (); | |
25784 | } | |
25785 | ||
25786 | ||
7a1d4c38 PB |
25787 | /* Parse a .object_arch directive. */ |
25788 | ||
25789 | static void | |
25790 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
25791 | { | |
25792 | const struct arm_arch_option_table *opt; | |
25793 | char saved_char; | |
25794 | char *name; | |
25795 | ||
25796 | name = input_line_pointer; | |
5f4273c7 | 25797 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
25798 | input_line_pointer++; |
25799 | saved_char = *input_line_pointer; | |
25800 | *input_line_pointer = 0; | |
25801 | ||
25802 | /* Skip the first "all" entry. */ | |
25803 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25804 | if (streq (opt->name, name)) | |
25805 | { | |
25806 | object_arch = &opt->value; | |
25807 | *input_line_pointer = saved_char; | |
25808 | demand_empty_rest_of_line (); | |
25809 | return; | |
25810 | } | |
25811 | ||
25812 | as_bad (_("unknown architecture `%s'\n"), name); | |
25813 | *input_line_pointer = saved_char; | |
25814 | ignore_rest_of_line (); | |
25815 | } | |
25816 | ||
69133863 MGD |
25817 | /* Parse a .arch_extension directive. */ |
25818 | ||
25819 | static void | |
25820 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
25821 | { | |
25822 | const struct arm_option_extension_value_table *opt; | |
25823 | char saved_char; | |
25824 | char *name; | |
25825 | int adding_value = 1; | |
25826 | ||
25827 | name = input_line_pointer; | |
25828 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
25829 | input_line_pointer++; | |
25830 | saved_char = *input_line_pointer; | |
25831 | *input_line_pointer = 0; | |
25832 | ||
25833 | if (strlen (name) >= 2 | |
25834 | && strncmp (name, "no", 2) == 0) | |
25835 | { | |
25836 | adding_value = 0; | |
25837 | name += 2; | |
25838 | } | |
25839 | ||
25840 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
25841 | if (streq (opt->name, name)) | |
25842 | { | |
25843 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
25844 | { | |
25845 | as_bad (_("architectural extension `%s' is not allowed for the " | |
25846 | "current base architecture"), name); | |
25847 | break; | |
25848 | } | |
25849 | ||
25850 | if (adding_value) | |
5a70a223 JB |
25851 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, |
25852 | opt->merge_value); | |
69133863 | 25853 | else |
5a70a223 | 25854 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value); |
69133863 MGD |
25855 | |
25856 | mcpu_cpu_opt = &selected_cpu; | |
25857 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
25858 | *input_line_pointer = saved_char; | |
25859 | demand_empty_rest_of_line (); | |
25860 | return; | |
25861 | } | |
25862 | ||
25863 | if (opt->name == NULL) | |
e673710a | 25864 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
25865 | |
25866 | *input_line_pointer = saved_char; | |
25867 | ignore_rest_of_line (); | |
25868 | } | |
25869 | ||
ee065d83 PB |
25870 | /* Parse a .fpu directive. */ |
25871 | ||
25872 | static void | |
25873 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
25874 | { | |
69133863 | 25875 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
25876 | char saved_char; |
25877 | char *name; | |
25878 | ||
25879 | name = input_line_pointer; | |
5f4273c7 | 25880 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25881 | input_line_pointer++; |
25882 | saved_char = *input_line_pointer; | |
25883 | *input_line_pointer = 0; | |
5f4273c7 | 25884 | |
ee065d83 PB |
25885 | for (opt = arm_fpus; opt->name != NULL; opt++) |
25886 | if (streq (opt->name, name)) | |
25887 | { | |
e74cfd16 PB |
25888 | mfpu_opt = &opt->value; |
25889 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
25890 | *input_line_pointer = saved_char; |
25891 | demand_empty_rest_of_line (); | |
25892 | return; | |
25893 | } | |
25894 | ||
25895 | as_bad (_("unknown floating point format `%s'\n"), name); | |
25896 | *input_line_pointer = saved_char; | |
25897 | ignore_rest_of_line (); | |
25898 | } | |
ee065d83 | 25899 | |
794ba86a | 25900 | /* Copy symbol information. */ |
f31fef98 | 25901 | |
794ba86a DJ |
25902 | void |
25903 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
25904 | { | |
25905 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
25906 | } | |
e04befd0 | 25907 | |
f31fef98 | 25908 | #ifdef OBJ_ELF |
e04befd0 AS |
25909 | /* Given a symbolic attribute NAME, return the proper integer value. |
25910 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 25911 | |
e04befd0 AS |
25912 | int |
25913 | arm_convert_symbolic_attribute (const char *name) | |
25914 | { | |
f31fef98 NC |
25915 | static const struct |
25916 | { | |
25917 | const char * name; | |
25918 | const int tag; | |
25919 | } | |
25920 | attribute_table[] = | |
25921 | { | |
25922 | /* When you modify this table you should | |
25923 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 25924 | #define T(tag) {#tag, tag} |
f31fef98 NC |
25925 | T (Tag_CPU_raw_name), |
25926 | T (Tag_CPU_name), | |
25927 | T (Tag_CPU_arch), | |
25928 | T (Tag_CPU_arch_profile), | |
25929 | T (Tag_ARM_ISA_use), | |
25930 | T (Tag_THUMB_ISA_use), | |
75375b3e | 25931 | T (Tag_FP_arch), |
f31fef98 NC |
25932 | T (Tag_VFP_arch), |
25933 | T (Tag_WMMX_arch), | |
25934 | T (Tag_Advanced_SIMD_arch), | |
25935 | T (Tag_PCS_config), | |
25936 | T (Tag_ABI_PCS_R9_use), | |
25937 | T (Tag_ABI_PCS_RW_data), | |
25938 | T (Tag_ABI_PCS_RO_data), | |
25939 | T (Tag_ABI_PCS_GOT_use), | |
25940 | T (Tag_ABI_PCS_wchar_t), | |
25941 | T (Tag_ABI_FP_rounding), | |
25942 | T (Tag_ABI_FP_denormal), | |
25943 | T (Tag_ABI_FP_exceptions), | |
25944 | T (Tag_ABI_FP_user_exceptions), | |
25945 | T (Tag_ABI_FP_number_model), | |
75375b3e | 25946 | T (Tag_ABI_align_needed), |
f31fef98 | 25947 | T (Tag_ABI_align8_needed), |
75375b3e | 25948 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
25949 | T (Tag_ABI_align8_preserved), |
25950 | T (Tag_ABI_enum_size), | |
25951 | T (Tag_ABI_HardFP_use), | |
25952 | T (Tag_ABI_VFP_args), | |
25953 | T (Tag_ABI_WMMX_args), | |
25954 | T (Tag_ABI_optimization_goals), | |
25955 | T (Tag_ABI_FP_optimization_goals), | |
25956 | T (Tag_compatibility), | |
25957 | T (Tag_CPU_unaligned_access), | |
75375b3e | 25958 | T (Tag_FP_HP_extension), |
f31fef98 NC |
25959 | T (Tag_VFP_HP_extension), |
25960 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
25961 | T (Tag_MPextension_use), |
25962 | T (Tag_DIV_use), | |
f31fef98 NC |
25963 | T (Tag_nodefaults), |
25964 | T (Tag_also_compatible_with), | |
25965 | T (Tag_conformance), | |
25966 | T (Tag_T2EE_use), | |
25967 | T (Tag_Virtualization_use), | |
cd21e546 | 25968 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 25969 | #undef T |
f31fef98 | 25970 | }; |
e04befd0 AS |
25971 | unsigned int i; |
25972 | ||
25973 | if (name == NULL) | |
25974 | return -1; | |
25975 | ||
f31fef98 | 25976 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 25977 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
25978 | return attribute_table[i].tag; |
25979 | ||
25980 | return -1; | |
25981 | } | |
267bf995 RR |
25982 | |
25983 | ||
93ef582d NC |
25984 | /* Apply sym value for relocations only in the case that they are for |
25985 | local symbols in the same segment as the fixup and you have the | |
25986 | respective architectural feature for blx and simple switches. */ | |
267bf995 | 25987 | int |
93ef582d | 25988 | arm_apply_sym_value (struct fix * fixP, segT this_seg) |
267bf995 RR |
25989 | { |
25990 | if (fixP->fx_addsy | |
25991 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
93ef582d NC |
25992 | /* PR 17444: If the local symbol is in a different section then a reloc |
25993 | will always be generated for it, so applying the symbol value now | |
25994 | will result in a double offset being stored in the relocation. */ | |
25995 | && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg) | |
34e77a92 | 25996 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
25997 | { |
25998 | switch (fixP->fx_r_type) | |
25999 | { | |
26000 | case BFD_RELOC_ARM_PCREL_BLX: | |
26001 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
26002 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
26003 | return 1; | |
26004 | break; | |
26005 | ||
26006 | case BFD_RELOC_ARM_PCREL_CALL: | |
26007 | case BFD_RELOC_THUMB_PCREL_BLX: | |
26008 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
93ef582d | 26009 | return 1; |
267bf995 RR |
26010 | break; |
26011 | ||
26012 | default: | |
26013 | break; | |
26014 | } | |
26015 | ||
26016 | } | |
26017 | return 0; | |
26018 | } | |
f31fef98 | 26019 | #endif /* OBJ_ELF */ |