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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
82704155 | 2 | Copyright (C) 1994-2019 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b | 34 | #include "opcode/arm.h" |
f37164d7 | 35 | #include "cpu-arm.h" |
f263249b | 36 | |
b99bd4ef NC |
37 | #ifdef OBJ_ELF |
38 | #include "elf/arm.h" | |
a394c00f | 39 | #include "dw2gencfi.h" |
b99bd4ef NC |
40 | #endif |
41 | ||
f0927246 NC |
42 | #include "dwarf2dbg.h" |
43 | ||
7ed4c4c5 NC |
44 | #ifdef OBJ_ELF |
45 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
46 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
47 | ||
48 | /* This structure holds the unwinding state. */ | |
49 | ||
50 | static struct | |
51 | { | |
c19d1205 ZW |
52 | symbolS * proc_start; |
53 | symbolS * table_entry; | |
54 | symbolS * personality_routine; | |
55 | int personality_index; | |
7ed4c4c5 | 56 | /* The segment containing the function. */ |
c19d1205 ZW |
57 | segT saved_seg; |
58 | subsegT saved_subseg; | |
7ed4c4c5 NC |
59 | /* Opcodes generated from this function. */ |
60 | unsigned char * opcodes; | |
c19d1205 ZW |
61 | int opcode_count; |
62 | int opcode_alloc; | |
7ed4c4c5 | 63 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 64 | offsetT frame_size; |
7ed4c4c5 NC |
65 | /* We don't add stack adjustment opcodes immediately so that we can merge |
66 | multiple adjustments. We can also omit the final adjustment | |
67 | when using a frame pointer. */ | |
c19d1205 | 68 | offsetT pending_offset; |
7ed4c4c5 | 69 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
70 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
71 | offsetT fp_offset; | |
72 | int fp_reg; | |
7ed4c4c5 | 73 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 74 | unsigned fp_used:1; |
7ed4c4c5 | 75 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 76 | unsigned sp_restored:1; |
7ed4c4c5 NC |
77 | } unwind; |
78 | ||
18a20338 CL |
79 | /* Whether --fdpic was given. */ |
80 | static int arm_fdpic; | |
81 | ||
8b1ad454 NC |
82 | #endif /* OBJ_ELF */ |
83 | ||
4962c51a MS |
84 | /* Results from operand parsing worker functions. */ |
85 | ||
86 | typedef enum | |
87 | { | |
88 | PARSE_OPERAND_SUCCESS, | |
89 | PARSE_OPERAND_FAIL, | |
90 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
91 | } parse_operand_result; | |
92 | ||
33a392fb PB |
93 | enum arm_float_abi |
94 | { | |
95 | ARM_FLOAT_ABI_HARD, | |
96 | ARM_FLOAT_ABI_SOFTFP, | |
97 | ARM_FLOAT_ABI_SOFT | |
98 | }; | |
99 | ||
c19d1205 | 100 | /* Types of processor to assemble for. */ |
b99bd4ef | 101 | #ifndef CPU_DEFAULT |
8a59fff3 | 102 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 103 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
104 | changing gas' default behaviour depending upon the build host. |
105 | ||
106 | If you have a target that requires a default CPU option then the you | |
107 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
108 | #endif |
109 | ||
e8f8842d TC |
110 | /* Perform range checks on positive and negative overflows by checking if the |
111 | VALUE given fits within the range of an BITS sized immediate. */ | |
112 | static bfd_boolean out_of_range_p (offsetT value, offsetT bits) | |
113 | { | |
114 | gas_assert (bits < (offsetT)(sizeof (value) * 8)); | |
115 | return (value & ~((1 << bits)-1)) | |
116 | && ((value & ~((1 << bits)-1)) != ~((1 << bits)-1)); | |
117 | } | |
118 | ||
b99bd4ef | 119 | #ifndef FPU_DEFAULT |
c820d418 MM |
120 | # ifdef TE_LINUX |
121 | # define FPU_DEFAULT FPU_ARCH_FPA | |
122 | # elif defined (TE_NetBSD) | |
123 | # ifdef OBJ_ELF | |
124 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
125 | # else | |
126 | /* Legacy a.out format. */ | |
127 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
128 | # endif | |
4e7fd91e PB |
129 | # elif defined (TE_VXWORKS) |
130 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
131 | # else |
132 | /* For backwards compatibility, default to FPA. */ | |
133 | # define FPU_DEFAULT FPU_ARCH_FPA | |
134 | # endif | |
135 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 136 | |
c19d1205 | 137 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 138 | |
4d354d8b TP |
139 | /* Current set of feature bits available (CPU+FPU). Different from |
140 | selected_cpu + selected_fpu in case of autodetection since the CPU | |
141 | feature bits are then all set. */ | |
e74cfd16 | 142 | static arm_feature_set cpu_variant; |
4d354d8b TP |
143 | /* Feature bits used in each execution state. Used to set build attribute |
144 | (in particular Tag_*_ISA_use) in CPU autodetection mode. */ | |
e74cfd16 PB |
145 | static arm_feature_set arm_arch_used; |
146 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 147 | |
b99bd4ef | 148 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
149 | static int uses_apcs_26 = FALSE; |
150 | static int atpcs = FALSE; | |
b34976b6 AM |
151 | static int support_interwork = FALSE; |
152 | static int uses_apcs_float = FALSE; | |
c19d1205 | 153 | static int pic_code = FALSE; |
845b51d6 | 154 | static int fix_v4bx = FALSE; |
278df34e NS |
155 | /* Warn on using deprecated features. */ |
156 | static int warn_on_deprecated = TRUE; | |
157 | ||
2e6976a8 DG |
158 | /* Understand CodeComposer Studio assembly syntax. */ |
159 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
160 | |
161 | /* Variables that we set while parsing command-line options. Once all | |
162 | options have been read we re-process these values to set the real | |
163 | assembly flags. */ | |
4d354d8b TP |
164 | |
165 | /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1 | |
166 | instead of -mcpu=arm1). */ | |
167 | static const arm_feature_set *legacy_cpu = NULL; | |
168 | static const arm_feature_set *legacy_fpu = NULL; | |
169 | ||
170 | /* CPU, extension and FPU feature bits selected by -mcpu. */ | |
171 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
172 | static arm_feature_set *mcpu_ext_opt = NULL; | |
173 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
174 | ||
175 | /* CPU, extension and FPU feature bits selected by -march. */ | |
176 | static const arm_feature_set *march_cpu_opt = NULL; | |
177 | static arm_feature_set *march_ext_opt = NULL; | |
178 | static const arm_feature_set *march_fpu_opt = NULL; | |
179 | ||
180 | /* Feature bits selected by -mfpu. */ | |
181 | static const arm_feature_set *mfpu_opt = NULL; | |
e74cfd16 PB |
182 | |
183 | /* Constants for known architecture features. */ | |
184 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
f85d59c3 | 185 | static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1; |
e74cfd16 | 186 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; |
f85d59c3 KT |
187 | static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3; |
188 | static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
189 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
190 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
69c9e028 | 191 | #ifdef OBJ_ELF |
e74cfd16 | 192 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; |
69c9e028 | 193 | #endif |
e74cfd16 PB |
194 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; |
195 | ||
196 | #ifdef CPU_DEFAULT | |
197 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
198 | #endif | |
199 | ||
823d2571 | 200 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); |
4070243b | 201 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2); |
823d2571 TG |
202 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); |
203 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); | |
204 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); | |
205 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); | |
206 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); | |
207 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); | |
e74cfd16 | 208 | static const arm_feature_set arm_ext_v4t_5 = |
823d2571 TG |
209 | ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); |
210 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); | |
211 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); | |
212 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); | |
213 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); | |
214 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); | |
215 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); | |
216 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); | |
55e8aae7 SP |
217 | /* Only for compatability of hint instructions. */ |
218 | static const arm_feature_set arm_ext_v6k_v6t2 = | |
219 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2); | |
823d2571 TG |
220 | static const arm_feature_set arm_ext_v6_notm = |
221 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); | |
222 | static const arm_feature_set arm_ext_v6_dsp = | |
223 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); | |
224 | static const arm_feature_set arm_ext_barrier = | |
225 | ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); | |
226 | static const arm_feature_set arm_ext_msr = | |
227 | ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); | |
228 | static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); | |
229 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); | |
230 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); | |
231 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); | |
69c9e028 | 232 | #ifdef OBJ_ELF |
e7d39ed3 | 233 | static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); |
69c9e028 | 234 | #endif |
823d2571 | 235 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); |
7e806470 | 236 | static const arm_feature_set arm_ext_m = |
173205ca | 237 | ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M, |
16a1fa25 | 238 | ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); |
823d2571 TG |
239 | static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); |
240 | static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); | |
241 | static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); | |
242 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); | |
243 | static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); | |
ddfded2f | 244 | static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); |
4ed7ed8d | 245 | static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M); |
16a1fa25 TP |
246 | static const arm_feature_set arm_ext_v8m_main = |
247 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN); | |
e12437dc AV |
248 | static const arm_feature_set arm_ext_v8_1m_main = |
249 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); | |
16a1fa25 TP |
250 | /* Instructions in ARMv8-M only found in M profile architectures. */ |
251 | static const arm_feature_set arm_ext_v8m_m_only = | |
252 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN); | |
ff8646ee TP |
253 | static const arm_feature_set arm_ext_v6t2_v8m = |
254 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M); | |
4ed7ed8d TP |
255 | /* Instructions shared between ARMv8-A and ARMv8-M. */ |
256 | static const arm_feature_set arm_ext_atomics = | |
257 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS); | |
69c9e028 | 258 | #ifdef OBJ_ELF |
15afaa63 TP |
259 | /* DSP instructions Tag_DSP_extension refers to. */ |
260 | static const arm_feature_set arm_ext_dsp = | |
261 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP); | |
69c9e028 | 262 | #endif |
4d1464f2 MW |
263 | static const arm_feature_set arm_ext_ras = |
264 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS); | |
b8ec4e87 JW |
265 | /* FP16 instructions. */ |
266 | static const arm_feature_set arm_ext_fp16 = | |
267 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); | |
01f48020 TC |
268 | static const arm_feature_set arm_ext_fp16_fml = |
269 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML); | |
dec41383 JW |
270 | static const arm_feature_set arm_ext_v8_2 = |
271 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A); | |
49e8a725 SN |
272 | static const arm_feature_set arm_ext_v8_3 = |
273 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A); | |
7fadb25d SD |
274 | static const arm_feature_set arm_ext_sb = |
275 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB); | |
dad0c3bf SD |
276 | static const arm_feature_set arm_ext_predres = |
277 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES); | |
e74cfd16 PB |
278 | |
279 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
49fa50ef | 280 | #ifdef OBJ_ELF |
2c6b98ea | 281 | static const arm_feature_set fpu_any = FPU_ANY; |
49fa50ef | 282 | #endif |
f85d59c3 | 283 | static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1); |
e74cfd16 PB |
284 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; |
285 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
286 | ||
2d447fca | 287 | static const arm_feature_set arm_cext_iwmmxt2 = |
823d2571 | 288 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); |
e74cfd16 | 289 | static const arm_feature_set arm_cext_iwmmxt = |
823d2571 | 290 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); |
e74cfd16 | 291 | static const arm_feature_set arm_cext_xscale = |
823d2571 | 292 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); |
e74cfd16 | 293 | static const arm_feature_set arm_cext_maverick = |
823d2571 TG |
294 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); |
295 | static const arm_feature_set fpu_fpa_ext_v1 = | |
296 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); | |
297 | static const arm_feature_set fpu_fpa_ext_v2 = | |
298 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); | |
e74cfd16 | 299 | static const arm_feature_set fpu_vfp_ext_v1xd = |
823d2571 TG |
300 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); |
301 | static const arm_feature_set fpu_vfp_ext_v1 = | |
302 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); | |
303 | static const arm_feature_set fpu_vfp_ext_v2 = | |
304 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); | |
305 | static const arm_feature_set fpu_vfp_ext_v3xd = | |
306 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); | |
307 | static const arm_feature_set fpu_vfp_ext_v3 = | |
308 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); | |
b1cc4aeb | 309 | static const arm_feature_set fpu_vfp_ext_d32 = |
823d2571 TG |
310 | ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); |
311 | static const arm_feature_set fpu_neon_ext_v1 = | |
312 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); | |
5287ad62 | 313 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
823d2571 | 314 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
a7ad558c AV |
315 | static const arm_feature_set mve_ext = |
316 | ARM_FEATURE_COPROC (FPU_MVE); | |
317 | static const arm_feature_set mve_fp_ext = | |
318 | ARM_FEATURE_COPROC (FPU_MVE_FP); | |
69c9e028 | 319 | #ifdef OBJ_ELF |
823d2571 TG |
320 | static const arm_feature_set fpu_vfp_fp16 = |
321 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); | |
322 | static const arm_feature_set fpu_neon_ext_fma = | |
323 | ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); | |
69c9e028 | 324 | #endif |
823d2571 TG |
325 | static const arm_feature_set fpu_vfp_ext_fma = |
326 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); | |
bca38921 | 327 | static const arm_feature_set fpu_vfp_ext_armv8 = |
823d2571 | 328 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); |
a715796b | 329 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
823d2571 | 330 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); |
bca38921 | 331 | static const arm_feature_set fpu_neon_ext_armv8 = |
823d2571 | 332 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); |
bca38921 | 333 | static const arm_feature_set fpu_crypto_ext_armv8 = |
823d2571 | 334 | ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); |
dd5181d5 | 335 | static const arm_feature_set crc_ext_armv8 = |
823d2571 | 336 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8); |
d6b4b13e | 337 | static const arm_feature_set fpu_neon_ext_v8_1 = |
643afb90 | 338 | ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA); |
c604a79a JW |
339 | static const arm_feature_set fpu_neon_ext_dotprod = |
340 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD); | |
e74cfd16 | 341 | |
33a392fb | 342 | static int mfloat_abi_opt = -1; |
4d354d8b TP |
343 | /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch |
344 | directive. */ | |
345 | static arm_feature_set selected_arch = ARM_ARCH_NONE; | |
346 | /* Extension feature bits selected by the last -mcpu/-march or .arch_extension | |
347 | directive. */ | |
348 | static arm_feature_set selected_ext = ARM_ARCH_NONE; | |
349 | /* Feature bits selected by the last -mcpu/-march or by the combination of the | |
350 | last .cpu/.arch directive .arch_extension directives since that | |
351 | directive. */ | |
e74cfd16 | 352 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; |
4d354d8b TP |
353 | /* FPU feature bits selected by the last -mfpu or .fpu directive. */ |
354 | static arm_feature_set selected_fpu = FPU_NONE; | |
355 | /* Feature bits selected by the last .object_arch directive. */ | |
356 | static arm_feature_set selected_object_arch = ARM_ARCH_NONE; | |
ee065d83 | 357 | /* Must be long enough to hold any of the names in arm_cpus. */ |
ef8e6722 | 358 | static char selected_cpu_name[20]; |
8d67f500 | 359 | |
aacf0b33 KT |
360 | extern FLONUM_TYPE generic_floating_point_number; |
361 | ||
8d67f500 NC |
362 | /* Return if no cpu was selected on command-line. */ |
363 | static bfd_boolean | |
364 | no_cpu_selected (void) | |
365 | { | |
823d2571 | 366 | return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); |
8d67f500 NC |
367 | } |
368 | ||
7cc69913 | 369 | #ifdef OBJ_ELF |
deeaaff8 DJ |
370 | # ifdef EABI_DEFAULT |
371 | static int meabi_flags = EABI_DEFAULT; | |
372 | # else | |
d507cf36 | 373 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 374 | # endif |
e1da3f5b | 375 | |
ee3c0378 AS |
376 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
377 | ||
e1da3f5b | 378 | bfd_boolean |
5f4273c7 | 379 | arm_is_eabi (void) |
e1da3f5b PB |
380 | { |
381 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
382 | } | |
7cc69913 | 383 | #endif |
b99bd4ef | 384 | |
b99bd4ef | 385 | #ifdef OBJ_ELF |
c19d1205 | 386 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
387 | symbolS * GOT_symbol; |
388 | #endif | |
389 | ||
b99bd4ef NC |
390 | /* 0: assemble for ARM, |
391 | 1: assemble for Thumb, | |
392 | 2: assemble for Thumb even though target CPU does not support thumb | |
393 | instructions. */ | |
394 | static int thumb_mode = 0; | |
8dc2430f NC |
395 | /* A value distinct from the possible values for thumb_mode that we |
396 | can use to record whether thumb_mode has been copied into the | |
397 | tc_frag_data field of a frag. */ | |
398 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 399 | |
e07e6e58 NC |
400 | /* Specifies the intrinsic IT insn behavior mode. */ |
401 | enum implicit_it_mode | |
402 | { | |
403 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
404 | IMPLICIT_IT_MODE_ARM = 0x01, | |
405 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
406 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
407 | }; | |
408 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
409 | ||
c19d1205 ZW |
410 | /* If unified_syntax is true, we are processing the new unified |
411 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
412 | ||
413 | - Immediate operands do not require a # prefix. | |
414 | - Conditional affixes always appear at the end of the | |
415 | instruction. (For backward compatibility, those instructions | |
416 | that formerly had them in the middle, continue to accept them | |
417 | there.) | |
418 | - The IT instruction may appear, and if it does is validated | |
419 | against subsequent conditional affixes. It does not generate | |
420 | machine code. | |
421 | ||
422 | Important differences from the old Thumb mode: | |
423 | ||
424 | - Immediate operands do not require a # prefix. | |
425 | - Most of the V6T2 instructions are only available in unified mode. | |
426 | - The .N and .W suffixes are recognized and honored (it is an error | |
427 | if they cannot be honored). | |
428 | - All instructions set the flags if and only if they have an 's' affix. | |
429 | - Conditional affixes may be used. They are validated against | |
430 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
431 | conditional affix except in the scope of an IT instruction. */ | |
432 | ||
433 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 434 | |
bacebabc RM |
435 | /* An immediate operand can start with #, and ld*, st*, pld operands |
436 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
437 | before a [, which can appear as the first operand for pld. |
438 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
439 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 440 | |
5287ad62 JB |
441 | enum neon_el_type |
442 | { | |
dcbf9037 | 443 | NT_invtype, |
5287ad62 JB |
444 | NT_untyped, |
445 | NT_integer, | |
446 | NT_float, | |
447 | NT_poly, | |
448 | NT_signed, | |
dcbf9037 | 449 | NT_unsigned |
5287ad62 JB |
450 | }; |
451 | ||
452 | struct neon_type_el | |
453 | { | |
454 | enum neon_el_type type; | |
455 | unsigned size; | |
456 | }; | |
457 | ||
458 | #define NEON_MAX_TYPE_ELS 4 | |
459 | ||
460 | struct neon_type | |
461 | { | |
462 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
463 | unsigned elems; | |
464 | }; | |
465 | ||
5ee91343 | 466 | enum pred_instruction_type |
e07e6e58 | 467 | { |
5ee91343 AV |
468 | OUTSIDE_PRED_INSN, |
469 | INSIDE_VPT_INSN, | |
e07e6e58 NC |
470 | INSIDE_IT_INSN, |
471 | INSIDE_IT_LAST_INSN, | |
472 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 473 | if inside, should be the last one. */ |
e07e6e58 | 474 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 475 | i.e. BKPT and NOP. */ |
5ee91343 AV |
476 | IT_INSN, /* The IT insn has been parsed. */ |
477 | VPT_INSN, /* The VPT/VPST insn has been parsed. */ | |
35c228db | 478 | MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without |
5ee91343 | 479 | a predication code. */ |
35c228db | 480 | MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */ |
e07e6e58 NC |
481 | }; |
482 | ||
ad6cec43 MGD |
483 | /* The maximum number of operands we need. */ |
484 | #define ARM_IT_MAX_OPERANDS 6 | |
e2b0ab59 | 485 | #define ARM_IT_MAX_RELOCS 3 |
ad6cec43 | 486 | |
b99bd4ef NC |
487 | struct arm_it |
488 | { | |
c19d1205 | 489 | const char * error; |
b99bd4ef | 490 | unsigned long instruction; |
c19d1205 ZW |
491 | int size; |
492 | int size_req; | |
493 | int cond; | |
037e8744 JB |
494 | /* "uncond_value" is set to the value in place of the conditional field in |
495 | unconditional versions of the instruction, or -1 if nothing is | |
496 | appropriate. */ | |
497 | int uncond_value; | |
5287ad62 | 498 | struct neon_type vectype; |
88714cb8 DG |
499 | /* This does not indicate an actual NEON instruction, only that |
500 | the mnemonic accepts neon-style type suffixes. */ | |
501 | int is_neon; | |
0110f2b8 PB |
502 | /* Set to the opcode if the instruction needs relaxation. |
503 | Zero if the instruction is not relaxed. */ | |
504 | unsigned long relax; | |
b99bd4ef NC |
505 | struct |
506 | { | |
507 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
508 | expressionS exp; |
509 | int pc_rel; | |
e2b0ab59 | 510 | } relocs[ARM_IT_MAX_RELOCS]; |
b99bd4ef | 511 | |
5ee91343 | 512 | enum pred_instruction_type pred_insn_type; |
e07e6e58 | 513 | |
c19d1205 ZW |
514 | struct |
515 | { | |
516 | unsigned reg; | |
ca3f61f7 | 517 | signed int imm; |
dcbf9037 | 518 | struct neon_type_el vectype; |
ca3f61f7 NC |
519 | unsigned present : 1; /* Operand present. */ |
520 | unsigned isreg : 1; /* Operand was a register. */ | |
f5f10c66 AV |
521 | unsigned immisreg : 2; /* .imm field is a second register. |
522 | 0: imm, 1: gpr, 2: MVE Q-register. */ | |
57785aa2 AV |
523 | unsigned isscalar : 2; /* Operand is a (SIMD) scalar: |
524 | 0) not scalar, | |
525 | 1) Neon scalar, | |
526 | 2) MVE scalar. */ | |
5287ad62 | 527 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ |
c96612cc | 528 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
529 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
530 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
531 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 532 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5ee91343 | 533 | unsigned isquad : 1; /* Operand is SIMD quad register. */ |
037e8744 | 534 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
1b883319 | 535 | unsigned iszr : 1; /* Operand is ZR register. */ |
ca3f61f7 NC |
536 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
537 | unsigned writeback : 1; /* Operand has trailing ! */ | |
538 | unsigned preind : 1; /* Preindexed address. */ | |
539 | unsigned postind : 1; /* Postindexed address. */ | |
540 | unsigned negative : 1; /* Index register was negated. */ | |
541 | unsigned shifted : 1; /* Shift applied to operation. */ | |
542 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 543 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
544 | }; |
545 | ||
c19d1205 | 546 | static struct arm_it inst; |
b99bd4ef NC |
547 | |
548 | #define NUM_FLOAT_VALS 8 | |
549 | ||
05d2d07e | 550 | const char * fp_const[] = |
b99bd4ef NC |
551 | { |
552 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
553 | }; | |
554 | ||
b99bd4ef NC |
555 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; |
556 | ||
557 | #define FAIL (-1) | |
558 | #define SUCCESS (0) | |
559 | ||
560 | #define SUFF_S 1 | |
561 | #define SUFF_D 2 | |
562 | #define SUFF_E 3 | |
563 | #define SUFF_P 4 | |
564 | ||
c19d1205 ZW |
565 | #define CP_T_X 0x00008000 |
566 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 567 | |
c19d1205 ZW |
568 | #define CONDS_BIT 0x00100000 |
569 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
570 | |
571 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
572 | ||
573 | struct asm_cond | |
574 | { | |
d3ce72d0 | 575 | const char * template_name; |
c921be7d | 576 | unsigned long value; |
b99bd4ef NC |
577 | }; |
578 | ||
c19d1205 | 579 | #define COND_ALWAYS 0xE |
b99bd4ef | 580 | |
b99bd4ef NC |
581 | struct asm_psr |
582 | { | |
d3ce72d0 | 583 | const char * template_name; |
c921be7d | 584 | unsigned long field; |
b99bd4ef NC |
585 | }; |
586 | ||
62b3e311 PB |
587 | struct asm_barrier_opt |
588 | { | |
e797f7e0 MGD |
589 | const char * template_name; |
590 | unsigned long value; | |
591 | const arm_feature_set arch; | |
62b3e311 PB |
592 | }; |
593 | ||
2d2255b5 | 594 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
595 | #define SPSR_BIT (1 << 22) |
596 | ||
c19d1205 ZW |
597 | /* The individual PSR flag bits. */ |
598 | #define PSR_c (1 << 16) | |
599 | #define PSR_x (1 << 17) | |
600 | #define PSR_s (1 << 18) | |
601 | #define PSR_f (1 << 19) | |
b99bd4ef | 602 | |
c19d1205 | 603 | struct reloc_entry |
bfae80f2 | 604 | { |
0198d5e6 | 605 | const char * name; |
c921be7d | 606 | bfd_reloc_code_real_type reloc; |
bfae80f2 RE |
607 | }; |
608 | ||
5287ad62 | 609 | enum vfp_reg_pos |
bfae80f2 | 610 | { |
5287ad62 JB |
611 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
612 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
613 | }; |
614 | ||
615 | enum vfp_ldstm_type | |
616 | { | |
617 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
618 | }; | |
619 | ||
dcbf9037 JB |
620 | /* Bits for DEFINED field in neon_typed_alias. */ |
621 | #define NTA_HASTYPE 1 | |
622 | #define NTA_HASINDEX 2 | |
623 | ||
624 | struct neon_typed_alias | |
625 | { | |
c921be7d NC |
626 | unsigned char defined; |
627 | unsigned char index; | |
628 | struct neon_type_el eltype; | |
dcbf9037 JB |
629 | }; |
630 | ||
c19d1205 | 631 | /* ARM register categories. This includes coprocessor numbers and various |
5aa75429 TP |
632 | architecture extensions' registers. Each entry should have an error message |
633 | in reg_expected_msgs below. */ | |
c19d1205 | 634 | enum arm_reg_type |
bfae80f2 | 635 | { |
c19d1205 ZW |
636 | REG_TYPE_RN, |
637 | REG_TYPE_CP, | |
638 | REG_TYPE_CN, | |
639 | REG_TYPE_FN, | |
640 | REG_TYPE_VFS, | |
641 | REG_TYPE_VFD, | |
5287ad62 | 642 | REG_TYPE_NQ, |
037e8744 | 643 | REG_TYPE_VFSD, |
5287ad62 | 644 | REG_TYPE_NDQ, |
dec41383 | 645 | REG_TYPE_NSD, |
037e8744 | 646 | REG_TYPE_NSDQ, |
c19d1205 ZW |
647 | REG_TYPE_VFC, |
648 | REG_TYPE_MVF, | |
649 | REG_TYPE_MVD, | |
650 | REG_TYPE_MVFX, | |
651 | REG_TYPE_MVDX, | |
652 | REG_TYPE_MVAX, | |
5ee91343 | 653 | REG_TYPE_MQ, |
c19d1205 ZW |
654 | REG_TYPE_DSPSC, |
655 | REG_TYPE_MMXWR, | |
656 | REG_TYPE_MMXWC, | |
657 | REG_TYPE_MMXWCG, | |
658 | REG_TYPE_XSCALE, | |
5ee91343 | 659 | REG_TYPE_RNB, |
1b883319 | 660 | REG_TYPE_ZR |
bfae80f2 RE |
661 | }; |
662 | ||
dcbf9037 JB |
663 | /* Structure for a hash table entry for a register. |
664 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
665 | information which states whether a vector type or index is specified (for a | |
666 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
667 | struct reg_entry |
668 | { | |
c921be7d | 669 | const char * name; |
90ec0d68 | 670 | unsigned int number; |
c921be7d NC |
671 | unsigned char type; |
672 | unsigned char builtin; | |
673 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
674 | }; |
675 | ||
c19d1205 | 676 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 677 | const char * const reg_expected_msgs[] = |
c19d1205 | 678 | { |
5aa75429 TP |
679 | [REG_TYPE_RN] = N_("ARM register expected"), |
680 | [REG_TYPE_CP] = N_("bad or missing co-processor number"), | |
681 | [REG_TYPE_CN] = N_("co-processor register expected"), | |
682 | [REG_TYPE_FN] = N_("FPA register expected"), | |
683 | [REG_TYPE_VFS] = N_("VFP single precision register expected"), | |
684 | [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"), | |
685 | [REG_TYPE_NQ] = N_("Neon quad precision register expected"), | |
686 | [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"), | |
687 | [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"), | |
688 | [REG_TYPE_NSD] = N_("Neon single or double precision register expected"), | |
689 | [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register" | |
690 | " expected"), | |
691 | [REG_TYPE_VFC] = N_("VFP system register expected"), | |
692 | [REG_TYPE_MVF] = N_("Maverick MVF register expected"), | |
693 | [REG_TYPE_MVD] = N_("Maverick MVD register expected"), | |
694 | [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"), | |
695 | [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"), | |
696 | [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"), | |
697 | [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"), | |
698 | [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"), | |
699 | [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"), | |
700 | [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"), | |
701 | [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"), | |
5ee91343 | 702 | [REG_TYPE_MQ] = N_("MVE vector register expected"), |
5aa75429 | 703 | [REG_TYPE_RNB] = N_("") |
6c43fab6 RE |
704 | }; |
705 | ||
c19d1205 | 706 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 707 | #define REG_R12 12 |
c19d1205 ZW |
708 | #define REG_SP 13 |
709 | #define REG_LR 14 | |
710 | #define REG_PC 15 | |
404ff6b5 | 711 | |
b99bd4ef NC |
712 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
713 | take 2: */ | |
c19d1205 | 714 | #define INSN_SIZE 4 |
b99bd4ef NC |
715 | |
716 | struct asm_opcode | |
717 | { | |
718 | /* Basic string to match. */ | |
d3ce72d0 | 719 | const char * template_name; |
c19d1205 ZW |
720 | |
721 | /* Parameters to instruction. */ | |
5be8be5d | 722 | unsigned int operands[8]; |
c19d1205 ZW |
723 | |
724 | /* Conditional tag - see opcode_lookup. */ | |
725 | unsigned int tag : 4; | |
b99bd4ef NC |
726 | |
727 | /* Basic instruction code. */ | |
a302e574 | 728 | unsigned int avalue; |
b99bd4ef | 729 | |
c19d1205 ZW |
730 | /* Thumb-format instruction code. */ |
731 | unsigned int tvalue; | |
b99bd4ef | 732 | |
90e4755a | 733 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
734 | const arm_feature_set * avariant; |
735 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
736 | |
737 | /* Function to call to encode instruction in ARM format. */ | |
738 | void (* aencode) (void); | |
b99bd4ef | 739 | |
c19d1205 ZW |
740 | /* Function to call to encode instruction in Thumb format. */ |
741 | void (* tencode) (void); | |
5ee91343 AV |
742 | |
743 | /* Indicates whether this instruction may be vector predicated. */ | |
744 | unsigned int mayBeVecPred : 1; | |
b99bd4ef NC |
745 | }; |
746 | ||
a737bd4d NC |
747 | /* Defines for various bits that we will want to toggle. */ |
748 | #define INST_IMMEDIATE 0x02000000 | |
749 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 750 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
751 | #define SHIFT_BY_REG 0x00000010 |
752 | #define PRE_INDEX 0x01000000 | |
753 | #define INDEX_UP 0x00800000 | |
754 | #define WRITE_BACK 0x00200000 | |
755 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 756 | #define CPSI_MMOD 0x00020000 |
90e4755a | 757 | |
a737bd4d NC |
758 | #define LITERAL_MASK 0xf000f000 |
759 | #define OPCODE_MASK 0xfe1fffff | |
760 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 761 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 762 | |
efd81785 PB |
763 | #define T2_SUBS_PC_LR 0xf3de8f00 |
764 | ||
a737bd4d | 765 | #define DATA_OP_SHIFT 21 |
bada4342 | 766 | #define SBIT_SHIFT 20 |
90e4755a | 767 | |
ef8d22e6 PB |
768 | #define T2_OPCODE_MASK 0xfe1fffff |
769 | #define T2_DATA_OP_SHIFT 21 | |
bada4342 | 770 | #define T2_SBIT_SHIFT 20 |
ef8d22e6 | 771 | |
6530b175 NC |
772 | #define A_COND_MASK 0xf0000000 |
773 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
774 | ||
775 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
776 | #define A1_OPCODE_PUSH 0x092d0000 | |
777 | #define A2_OPCODE_PUSH 0x052d0004 | |
778 | #define A2_OPCODE_POP 0x049d0004 | |
779 | ||
a737bd4d NC |
780 | /* Codes to distinguish the arithmetic instructions. */ |
781 | #define OPCODE_AND 0 | |
782 | #define OPCODE_EOR 1 | |
783 | #define OPCODE_SUB 2 | |
784 | #define OPCODE_RSB 3 | |
785 | #define OPCODE_ADD 4 | |
786 | #define OPCODE_ADC 5 | |
787 | #define OPCODE_SBC 6 | |
788 | #define OPCODE_RSC 7 | |
789 | #define OPCODE_TST 8 | |
790 | #define OPCODE_TEQ 9 | |
791 | #define OPCODE_CMP 10 | |
792 | #define OPCODE_CMN 11 | |
793 | #define OPCODE_ORR 12 | |
794 | #define OPCODE_MOV 13 | |
795 | #define OPCODE_BIC 14 | |
796 | #define OPCODE_MVN 15 | |
90e4755a | 797 | |
ef8d22e6 PB |
798 | #define T2_OPCODE_AND 0 |
799 | #define T2_OPCODE_BIC 1 | |
800 | #define T2_OPCODE_ORR 2 | |
801 | #define T2_OPCODE_ORN 3 | |
802 | #define T2_OPCODE_EOR 4 | |
803 | #define T2_OPCODE_ADD 8 | |
804 | #define T2_OPCODE_ADC 10 | |
805 | #define T2_OPCODE_SBC 11 | |
806 | #define T2_OPCODE_SUB 13 | |
807 | #define T2_OPCODE_RSB 14 | |
808 | ||
a737bd4d NC |
809 | #define T_OPCODE_MUL 0x4340 |
810 | #define T_OPCODE_TST 0x4200 | |
811 | #define T_OPCODE_CMN 0x42c0 | |
812 | #define T_OPCODE_NEG 0x4240 | |
813 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 814 | |
a737bd4d NC |
815 | #define T_OPCODE_ADD_R3 0x1800 |
816 | #define T_OPCODE_SUB_R3 0x1a00 | |
817 | #define T_OPCODE_ADD_HI 0x4400 | |
818 | #define T_OPCODE_ADD_ST 0xb000 | |
819 | #define T_OPCODE_SUB_ST 0xb080 | |
820 | #define T_OPCODE_ADD_SP 0xa800 | |
821 | #define T_OPCODE_ADD_PC 0xa000 | |
822 | #define T_OPCODE_ADD_I8 0x3000 | |
823 | #define T_OPCODE_SUB_I8 0x3800 | |
824 | #define T_OPCODE_ADD_I3 0x1c00 | |
825 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 826 | |
a737bd4d NC |
827 | #define T_OPCODE_ASR_R 0x4100 |
828 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
829 | #define T_OPCODE_LSR_R 0x40c0 |
830 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
831 | #define T_OPCODE_ASR_I 0x1000 |
832 | #define T_OPCODE_LSL_I 0x0000 | |
833 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 834 | |
a737bd4d NC |
835 | #define T_OPCODE_MOV_I8 0x2000 |
836 | #define T_OPCODE_CMP_I8 0x2800 | |
837 | #define T_OPCODE_CMP_LR 0x4280 | |
838 | #define T_OPCODE_MOV_HR 0x4600 | |
839 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 840 | |
a737bd4d NC |
841 | #define T_OPCODE_LDR_PC 0x4800 |
842 | #define T_OPCODE_LDR_SP 0x9800 | |
843 | #define T_OPCODE_STR_SP 0x9000 | |
844 | #define T_OPCODE_LDR_IW 0x6800 | |
845 | #define T_OPCODE_STR_IW 0x6000 | |
846 | #define T_OPCODE_LDR_IH 0x8800 | |
847 | #define T_OPCODE_STR_IH 0x8000 | |
848 | #define T_OPCODE_LDR_IB 0x7800 | |
849 | #define T_OPCODE_STR_IB 0x7000 | |
850 | #define T_OPCODE_LDR_RW 0x5800 | |
851 | #define T_OPCODE_STR_RW 0x5000 | |
852 | #define T_OPCODE_LDR_RH 0x5a00 | |
853 | #define T_OPCODE_STR_RH 0x5200 | |
854 | #define T_OPCODE_LDR_RB 0x5c00 | |
855 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 856 | |
a737bd4d NC |
857 | #define T_OPCODE_PUSH 0xb400 |
858 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 859 | |
2fc8bdac | 860 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 861 | |
a737bd4d | 862 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 863 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 864 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 865 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 | 866 | |
5ee91343 | 867 | #define BAD_SYNTAX _("syntax error") |
c19d1205 | 868 | #define BAD_ARGS _("bad arguments to instruction") |
fdfde340 | 869 | #define BAD_SP _("r13 not allowed here") |
c19d1205 | 870 | #define BAD_PC _("r15 not allowed here") |
a302e574 AV |
871 | #define BAD_ODD _("Odd register not allowed here") |
872 | #define BAD_EVEN _("Even register not allowed here") | |
c19d1205 ZW |
873 | #define BAD_COND _("instruction cannot be conditional") |
874 | #define BAD_OVERLAP _("registers may not be the same") | |
875 | #define BAD_HIREG _("lo register required") | |
876 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
35c228db | 877 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode") |
dfa9f0d5 | 878 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
e12437dc | 879 | #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2") |
dfa9f0d5 | 880 | #define BAD_NOT_IT _("instruction not allowed in IT block") |
5ee91343 | 881 | #define BAD_NOT_VPT _("instruction missing MVE vector predication code") |
037e8744 | 882 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 | 883 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
5ee91343 AV |
884 | #define BAD_OUT_VPT \ |
885 | _("vector predicated instruction should be in VPT/VPST block") | |
e07e6e58 | 886 | #define BAD_IT_COND _("incorrect condition in IT block") |
5ee91343 | 887 | #define BAD_VPT_COND _("incorrect condition in VPT/VPST block") |
e07e6e58 | 888 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") |
921e5f0a | 889 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
890 | #define BAD_PC_ADDRESSING \ |
891 | _("cannot use register index with PC-relative addressing") | |
892 | #define BAD_PC_WRITEBACK \ | |
893 | _("cannot use writeback with PC-relative addressing") | |
9db2f6b4 RL |
894 | #define BAD_RANGE _("branch out of range") |
895 | #define BAD_FP16 _("selected processor does not support fp16 instruction") | |
dd5181d5 | 896 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
a9f02af8 | 897 | #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only") |
5ee91343 AV |
898 | #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \ |
899 | "block") | |
900 | #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \ | |
901 | "block") | |
902 | #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \ | |
903 | " operand") | |
904 | #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \ | |
905 | " operand") | |
a302e574 | 906 | #define BAD_SIMD_TYPE _("bad type in SIMD instruction") |
886e1c73 AV |
907 | #define BAD_MVE_AUTO \ |
908 | _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \ | |
909 | " use a valid -march or -mcpu option.") | |
910 | #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\ | |
911 | "and source operands makes instruction UNPREDICTABLE") | |
35c228db | 912 | #define BAD_EL_TYPE _("bad element type for instruction") |
1b883319 | 913 | #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected") |
c19d1205 | 914 | |
c921be7d NC |
915 | static struct hash_control * arm_ops_hsh; |
916 | static struct hash_control * arm_cond_hsh; | |
5ee91343 | 917 | static struct hash_control * arm_vcond_hsh; |
c921be7d NC |
918 | static struct hash_control * arm_shift_hsh; |
919 | static struct hash_control * arm_psr_hsh; | |
920 | static struct hash_control * arm_v7m_psr_hsh; | |
921 | static struct hash_control * arm_reg_hsh; | |
922 | static struct hash_control * arm_reloc_hsh; | |
923 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 924 | |
b99bd4ef NC |
925 | /* Stuff needed to resolve the label ambiguity |
926 | As: | |
927 | ... | |
928 | label: <insn> | |
929 | may differ from: | |
930 | ... | |
931 | label: | |
5f4273c7 | 932 | <insn> */ |
b99bd4ef NC |
933 | |
934 | symbolS * last_label_seen; | |
b34976b6 | 935 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 936 | |
3d0c9500 NC |
937 | /* Literal pool structure. Held on a per-section |
938 | and per-sub-section basis. */ | |
a737bd4d | 939 | |
c19d1205 | 940 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 941 | typedef struct literal_pool |
b99bd4ef | 942 | { |
c921be7d NC |
943 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
944 | unsigned int next_free_entry; | |
945 | unsigned int id; | |
946 | symbolS * symbol; | |
947 | segT section; | |
948 | subsegT sub_section; | |
a8040cf2 NC |
949 | #ifdef OBJ_ELF |
950 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
951 | #endif | |
c921be7d | 952 | struct literal_pool * next; |
8335d6aa | 953 | unsigned int alignment; |
3d0c9500 | 954 | } literal_pool; |
b99bd4ef | 955 | |
3d0c9500 NC |
956 | /* Pointer to a linked list of literal pools. */ |
957 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 958 | |
2e6976a8 DG |
959 | typedef enum asmfunc_states |
960 | { | |
961 | OUTSIDE_ASMFUNC, | |
962 | WAITING_ASMFUNC_NAME, | |
963 | WAITING_ENDASMFUNC | |
964 | } asmfunc_states; | |
965 | ||
966 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
967 | ||
e07e6e58 | 968 | #ifdef OBJ_ELF |
5ee91343 | 969 | # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred |
e07e6e58 | 970 | #else |
5ee91343 | 971 | static struct current_pred now_pred; |
e07e6e58 NC |
972 | #endif |
973 | ||
974 | static inline int | |
5ee91343 | 975 | now_pred_compatible (int cond) |
e07e6e58 | 976 | { |
5ee91343 | 977 | return (cond & ~1) == (now_pred.cc & ~1); |
e07e6e58 NC |
978 | } |
979 | ||
980 | static inline int | |
981 | conditional_insn (void) | |
982 | { | |
983 | return inst.cond != COND_ALWAYS; | |
984 | } | |
985 | ||
5ee91343 | 986 | static int in_pred_block (void); |
e07e6e58 | 987 | |
5ee91343 | 988 | static int handle_pred_state (void); |
e07e6e58 NC |
989 | |
990 | static void force_automatic_it_block_close (void); | |
991 | ||
c921be7d NC |
992 | static void it_fsm_post_encode (void); |
993 | ||
5ee91343 | 994 | #define set_pred_insn_type(type) \ |
e07e6e58 NC |
995 | do \ |
996 | { \ | |
5ee91343 AV |
997 | inst.pred_insn_type = type; \ |
998 | if (handle_pred_state () == FAIL) \ | |
477330fc | 999 | return; \ |
e07e6e58 NC |
1000 | } \ |
1001 | while (0) | |
1002 | ||
5ee91343 | 1003 | #define set_pred_insn_type_nonvoid(type, failret) \ |
c921be7d NC |
1004 | do \ |
1005 | { \ | |
5ee91343 AV |
1006 | inst.pred_insn_type = type; \ |
1007 | if (handle_pred_state () == FAIL) \ | |
477330fc | 1008 | return failret; \ |
c921be7d NC |
1009 | } \ |
1010 | while(0) | |
1011 | ||
5ee91343 | 1012 | #define set_pred_insn_type_last() \ |
e07e6e58 NC |
1013 | do \ |
1014 | { \ | |
1015 | if (inst.cond == COND_ALWAYS) \ | |
5ee91343 | 1016 | set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 1017 | else \ |
5ee91343 | 1018 | set_pred_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
1019 | } \ |
1020 | while (0) | |
1021 | ||
e39c1607 SD |
1022 | /* Toggle value[pos]. */ |
1023 | #define TOGGLE_BIT(value, pos) (value ^ (1 << pos)) | |
1024 | ||
c19d1205 | 1025 | /* Pure syntax. */ |
b99bd4ef | 1026 | |
c19d1205 ZW |
1027 | /* This array holds the chars that always start a comment. If the |
1028 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 1029 | char arm_comment_chars[] = "@"; |
3d0c9500 | 1030 | |
c19d1205 ZW |
1031 | /* This array holds the chars that only start a comment at the beginning of |
1032 | a line. If the line seems to have the form '# 123 filename' | |
1033 | .line and .file directives will appear in the pre-processed output. */ | |
1034 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
1035 | first line of the input file. This is because the compiler outputs | |
1036 | #NO_APP at the beginning of its output. */ | |
1037 | /* Also note that comments like this one will always work. */ | |
1038 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 1039 | |
2e6976a8 | 1040 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 1041 | |
c19d1205 ZW |
1042 | /* Chars that can be used to separate mant |
1043 | from exp in floating point numbers. */ | |
1044 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 1045 | |
c19d1205 ZW |
1046 | /* Chars that mean this number is a floating point constant. */ |
1047 | /* As in 0f12.456 */ | |
1048 | /* or 0d1.2345e12 */ | |
b99bd4ef | 1049 | |
5312fe52 | 1050 | const char FLT_CHARS[] = "rRsSfFdDxXeEpPHh"; |
3d0c9500 | 1051 | |
c19d1205 ZW |
1052 | /* Prefix characters that indicate the start of an immediate |
1053 | value. */ | |
1054 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 1055 | |
c19d1205 ZW |
1056 | /* Separator character handling. */ |
1057 | ||
1058 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
1059 | ||
5312fe52 BW |
1060 | enum fp_16bit_format |
1061 | { | |
1062 | ARM_FP16_FORMAT_IEEE = 0x1, | |
1063 | ARM_FP16_FORMAT_ALTERNATIVE = 0x2, | |
1064 | ARM_FP16_FORMAT_DEFAULT = 0x3 | |
1065 | }; | |
1066 | ||
1067 | static enum fp_16bit_format fp16_format = ARM_FP16_FORMAT_DEFAULT; | |
1068 | ||
1069 | ||
c19d1205 ZW |
1070 | static inline int |
1071 | skip_past_char (char ** str, char c) | |
1072 | { | |
8ab8155f NC |
1073 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
1074 | skip_whitespace (*str); | |
427d0db6 | 1075 | |
c19d1205 ZW |
1076 | if (**str == c) |
1077 | { | |
1078 | (*str)++; | |
1079 | return SUCCESS; | |
3d0c9500 | 1080 | } |
c19d1205 ZW |
1081 | else |
1082 | return FAIL; | |
1083 | } | |
c921be7d | 1084 | |
c19d1205 | 1085 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 1086 | |
c19d1205 ZW |
1087 | /* Arithmetic expressions (possibly involving symbols). */ |
1088 | ||
1089 | /* Return TRUE if anything in the expression is a bignum. */ | |
1090 | ||
0198d5e6 | 1091 | static bfd_boolean |
c19d1205 ZW |
1092 | walk_no_bignums (symbolS * sp) |
1093 | { | |
1094 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
0198d5e6 | 1095 | return TRUE; |
c19d1205 ZW |
1096 | |
1097 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 1098 | { |
c19d1205 ZW |
1099 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
1100 | || (symbol_get_value_expression (sp)->X_op_symbol | |
1101 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
1102 | } |
1103 | ||
0198d5e6 | 1104 | return FALSE; |
3d0c9500 NC |
1105 | } |
1106 | ||
0198d5e6 | 1107 | static bfd_boolean in_my_get_expression = FALSE; |
c19d1205 ZW |
1108 | |
1109 | /* Third argument to my_get_expression. */ | |
1110 | #define GE_NO_PREFIX 0 | |
1111 | #define GE_IMM_PREFIX 1 | |
1112 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
1113 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
1114 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
1115 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 1116 | |
b99bd4ef | 1117 | static int |
c19d1205 | 1118 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 1119 | { |
c19d1205 | 1120 | char * save_in; |
b99bd4ef | 1121 | |
c19d1205 ZW |
1122 | /* In unified syntax, all prefixes are optional. */ |
1123 | if (unified_syntax) | |
5287ad62 | 1124 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 1125 | : GE_OPT_PREFIX; |
b99bd4ef | 1126 | |
c19d1205 | 1127 | switch (prefix_mode) |
b99bd4ef | 1128 | { |
c19d1205 ZW |
1129 | case GE_NO_PREFIX: break; |
1130 | case GE_IMM_PREFIX: | |
1131 | if (!is_immediate_prefix (**str)) | |
1132 | { | |
1133 | inst.error = _("immediate expression requires a # prefix"); | |
1134 | return FAIL; | |
1135 | } | |
1136 | (*str)++; | |
1137 | break; | |
1138 | case GE_OPT_PREFIX: | |
5287ad62 | 1139 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
1140 | if (is_immediate_prefix (**str)) |
1141 | (*str)++; | |
1142 | break; | |
0198d5e6 TC |
1143 | default: |
1144 | abort (); | |
c19d1205 | 1145 | } |
b99bd4ef | 1146 | |
c19d1205 | 1147 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 1148 | |
c19d1205 ZW |
1149 | save_in = input_line_pointer; |
1150 | input_line_pointer = *str; | |
0198d5e6 | 1151 | in_my_get_expression = TRUE; |
2ac93be7 | 1152 | expression (ep); |
0198d5e6 | 1153 | in_my_get_expression = FALSE; |
c19d1205 | 1154 | |
f86adc07 | 1155 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 1156 | { |
f86adc07 | 1157 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
1158 | *str = input_line_pointer; |
1159 | input_line_pointer = save_in; | |
1160 | if (inst.error == NULL) | |
f86adc07 NS |
1161 | inst.error = (ep->X_op == O_absent |
1162 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
1163 | return 1; |
1164 | } | |
b99bd4ef | 1165 | |
c19d1205 ZW |
1166 | /* Get rid of any bignums now, so that we don't generate an error for which |
1167 | we can't establish a line number later on. Big numbers are never valid | |
1168 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1169 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1170 | && (ep->X_op == O_big | |
477330fc | 1171 | || (ep->X_add_symbol |
5287ad62 | 1172 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1173 | || (ep->X_op_symbol |
5287ad62 | 1174 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1175 | { |
1176 | inst.error = _("invalid constant"); | |
1177 | *str = input_line_pointer; | |
1178 | input_line_pointer = save_in; | |
1179 | return 1; | |
1180 | } | |
b99bd4ef | 1181 | |
c19d1205 ZW |
1182 | *str = input_line_pointer; |
1183 | input_line_pointer = save_in; | |
0198d5e6 | 1184 | return SUCCESS; |
b99bd4ef NC |
1185 | } |
1186 | ||
c19d1205 ZW |
1187 | /* Turn a string in input_line_pointer into a floating point constant |
1188 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1189 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1190 | returned, or NULL on OK. | |
b99bd4ef | 1191 | |
c19d1205 ZW |
1192 | Note that fp constants aren't represent in the normal way on the ARM. |
1193 | In big endian mode, things are as expected. However, in little endian | |
1194 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1195 | within the words. For example, (double) 1.1 in big endian mode is | |
1196 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1197 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1198 | |
c19d1205 | 1199 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1200 | |
6d4af3c2 | 1201 | const char * |
c19d1205 ZW |
1202 | md_atof (int type, char * litP, int * sizeP) |
1203 | { | |
1204 | int prec; | |
1205 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1206 | char *t; | |
1207 | int i; | |
b99bd4ef | 1208 | |
c19d1205 ZW |
1209 | switch (type) |
1210 | { | |
5312fe52 BW |
1211 | case 'H': |
1212 | case 'h': | |
1213 | prec = 1; | |
1214 | break; | |
1215 | ||
c19d1205 ZW |
1216 | case 'f': |
1217 | case 'F': | |
1218 | case 's': | |
1219 | case 'S': | |
1220 | prec = 2; | |
1221 | break; | |
b99bd4ef | 1222 | |
c19d1205 ZW |
1223 | case 'd': |
1224 | case 'D': | |
1225 | case 'r': | |
1226 | case 'R': | |
1227 | prec = 4; | |
1228 | break; | |
b99bd4ef | 1229 | |
c19d1205 ZW |
1230 | case 'x': |
1231 | case 'X': | |
499ac353 | 1232 | prec = 5; |
c19d1205 | 1233 | break; |
b99bd4ef | 1234 | |
c19d1205 ZW |
1235 | case 'p': |
1236 | case 'P': | |
499ac353 | 1237 | prec = 5; |
c19d1205 | 1238 | break; |
a737bd4d | 1239 | |
c19d1205 ZW |
1240 | default: |
1241 | *sizeP = 0; | |
499ac353 | 1242 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1243 | } |
b99bd4ef | 1244 | |
c19d1205 ZW |
1245 | t = atof_ieee (input_line_pointer, type, words); |
1246 | if (t) | |
1247 | input_line_pointer = t; | |
499ac353 | 1248 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1249 | |
72c03e30 BW |
1250 | if (target_big_endian || prec == 1) |
1251 | for (i = 0; i < prec; i++) | |
1252 | { | |
1253 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1254 | litP += sizeof (LITTLENUM_TYPE); | |
1255 | } | |
1256 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
1257 | for (i = prec - 1; i >= 0; i--) | |
1258 | { | |
1259 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1260 | litP += sizeof (LITTLENUM_TYPE); | |
1261 | } | |
c19d1205 | 1262 | else |
72c03e30 BW |
1263 | /* For a 4 byte float the order of elements in `words' is 1 0. |
1264 | For an 8 byte float the order is 1 0 3 2. */ | |
1265 | for (i = 0; i < prec; i += 2) | |
1266 | { | |
1267 | md_number_to_chars (litP, (valueT) words[i + 1], | |
1268 | sizeof (LITTLENUM_TYPE)); | |
1269 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1270 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1271 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
1272 | } | |
b99bd4ef | 1273 | |
499ac353 | 1274 | return NULL; |
c19d1205 | 1275 | } |
b99bd4ef | 1276 | |
c19d1205 ZW |
1277 | /* We handle all bad expressions here, so that we can report the faulty |
1278 | instruction in the error message. */ | |
0198d5e6 | 1279 | |
c19d1205 | 1280 | void |
91d6fa6a | 1281 | md_operand (expressionS * exp) |
c19d1205 ZW |
1282 | { |
1283 | if (in_my_get_expression) | |
91d6fa6a | 1284 | exp->X_op = O_illegal; |
b99bd4ef NC |
1285 | } |
1286 | ||
c19d1205 | 1287 | /* Immediate values. */ |
b99bd4ef | 1288 | |
0198d5e6 | 1289 | #ifdef OBJ_ELF |
c19d1205 ZW |
1290 | /* Generic immediate-value read function for use in directives. |
1291 | Accepts anything that 'expression' can fold to a constant. | |
1292 | *val receives the number. */ | |
0198d5e6 | 1293 | |
c19d1205 ZW |
1294 | static int |
1295 | immediate_for_directive (int *val) | |
b99bd4ef | 1296 | { |
c19d1205 ZW |
1297 | expressionS exp; |
1298 | exp.X_op = O_illegal; | |
b99bd4ef | 1299 | |
c19d1205 ZW |
1300 | if (is_immediate_prefix (*input_line_pointer)) |
1301 | { | |
1302 | input_line_pointer++; | |
1303 | expression (&exp); | |
1304 | } | |
b99bd4ef | 1305 | |
c19d1205 ZW |
1306 | if (exp.X_op != O_constant) |
1307 | { | |
1308 | as_bad (_("expected #constant")); | |
1309 | ignore_rest_of_line (); | |
1310 | return FAIL; | |
1311 | } | |
1312 | *val = exp.X_add_number; | |
1313 | return SUCCESS; | |
b99bd4ef | 1314 | } |
c19d1205 | 1315 | #endif |
b99bd4ef | 1316 | |
c19d1205 | 1317 | /* Register parsing. */ |
b99bd4ef | 1318 | |
c19d1205 ZW |
1319 | /* Generic register parser. CCP points to what should be the |
1320 | beginning of a register name. If it is indeed a valid register | |
1321 | name, advance CCP over it and return the reg_entry structure; | |
1322 | otherwise return NULL. Does not issue diagnostics. */ | |
1323 | ||
1324 | static struct reg_entry * | |
1325 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1326 | { |
c19d1205 ZW |
1327 | char *start = *ccp; |
1328 | char *p; | |
1329 | struct reg_entry *reg; | |
b99bd4ef | 1330 | |
477330fc RM |
1331 | skip_whitespace (start); |
1332 | ||
c19d1205 ZW |
1333 | #ifdef REGISTER_PREFIX |
1334 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1335 | return NULL; |
c19d1205 ZW |
1336 | start++; |
1337 | #endif | |
1338 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1339 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1340 | start++; | |
1341 | #endif | |
b99bd4ef | 1342 | |
c19d1205 ZW |
1343 | p = start; |
1344 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1345 | return NULL; | |
b99bd4ef | 1346 | |
c19d1205 ZW |
1347 | do |
1348 | p++; | |
1349 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1350 | ||
1351 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1352 | ||
1353 | if (!reg) | |
1354 | return NULL; | |
1355 | ||
1356 | *ccp = p; | |
1357 | return reg; | |
b99bd4ef NC |
1358 | } |
1359 | ||
1360 | static int | |
dcbf9037 | 1361 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1362 | enum arm_reg_type type) |
b99bd4ef | 1363 | { |
c19d1205 ZW |
1364 | /* Alternative syntaxes are accepted for a few register classes. */ |
1365 | switch (type) | |
1366 | { | |
1367 | case REG_TYPE_MVF: | |
1368 | case REG_TYPE_MVD: | |
1369 | case REG_TYPE_MVFX: | |
1370 | case REG_TYPE_MVDX: | |
1371 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1372 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1373 | return reg->number; |
1374 | break; | |
69b97547 | 1375 | |
c19d1205 ZW |
1376 | case REG_TYPE_CP: |
1377 | /* For backward compatibility, a bare number is valid here. */ | |
1378 | { | |
1379 | unsigned long processor = strtoul (start, ccp, 10); | |
1380 | if (*ccp != start && processor <= 15) | |
1381 | return processor; | |
1382 | } | |
1a0670f3 | 1383 | /* Fall through. */ |
6057a28f | 1384 | |
c19d1205 ZW |
1385 | case REG_TYPE_MMXWC: |
1386 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1387 | instructions that take WC registers. */ | |
79134647 | 1388 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1389 | return reg->number; |
6057a28f | 1390 | break; |
c19d1205 | 1391 | |
6057a28f | 1392 | default: |
c19d1205 | 1393 | break; |
6057a28f NC |
1394 | } |
1395 | ||
dcbf9037 JB |
1396 | return FAIL; |
1397 | } | |
1398 | ||
1399 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1400 | return value is the register number or FAIL. */ | |
1401 | ||
1402 | static int | |
1403 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1404 | { | |
1405 | char *start = *ccp; | |
1406 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1407 | int ret; | |
1408 | ||
1409 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1410 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1411 | return FAIL; | |
1412 | ||
1413 | if (reg && reg->type == type) | |
1414 | return reg->number; | |
1415 | ||
1416 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1417 | return ret; | |
1418 | ||
c19d1205 ZW |
1419 | *ccp = start; |
1420 | return FAIL; | |
1421 | } | |
69b97547 | 1422 | |
dcbf9037 JB |
1423 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1424 | character. Does no verification at this stage that the type fits the opcode | |
1425 | properly. E.g., | |
1426 | ||
1427 | .i32.i32.s16 | |
1428 | .s32.f32 | |
1429 | .u16 | |
1430 | ||
1431 | Can all be legally parsed by this function. | |
1432 | ||
1433 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1434 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1435 | type, FAIL if not. */ | |
1436 | ||
1437 | static int | |
1438 | parse_neon_type (struct neon_type *type, char **str) | |
1439 | { | |
1440 | char *ptr = *str; | |
1441 | ||
1442 | if (type) | |
1443 | type->elems = 0; | |
1444 | ||
1445 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1446 | { | |
1447 | enum neon_el_type thistype = NT_untyped; | |
1448 | unsigned thissize = -1u; | |
1449 | ||
1450 | if (*ptr != '.') | |
1451 | break; | |
1452 | ||
1453 | ptr++; | |
1454 | ||
1455 | /* Just a size without an explicit type. */ | |
1456 | if (ISDIGIT (*ptr)) | |
1457 | goto parsesize; | |
1458 | ||
1459 | switch (TOLOWER (*ptr)) | |
1460 | { | |
1461 | case 'i': thistype = NT_integer; break; | |
1462 | case 'f': thistype = NT_float; break; | |
1463 | case 'p': thistype = NT_poly; break; | |
1464 | case 's': thistype = NT_signed; break; | |
1465 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1466 | case 'd': |
1467 | thistype = NT_float; | |
1468 | thissize = 64; | |
1469 | ptr++; | |
1470 | goto done; | |
dcbf9037 JB |
1471 | default: |
1472 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1473 | return FAIL; | |
1474 | } | |
1475 | ||
1476 | ptr++; | |
1477 | ||
1478 | /* .f is an abbreviation for .f32. */ | |
1479 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1480 | thissize = 32; | |
1481 | else | |
1482 | { | |
1483 | parsesize: | |
1484 | thissize = strtoul (ptr, &ptr, 10); | |
1485 | ||
1486 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1487 | && thissize != 64) |
1488 | { | |
1489 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1490 | return FAIL; |
1491 | } | |
1492 | } | |
1493 | ||
037e8744 | 1494 | done: |
dcbf9037 | 1495 | if (type) |
477330fc RM |
1496 | { |
1497 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1498 | type->el[type->elems].size = thissize; |
1499 | type->elems++; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | /* Empty/missing type is not a successful parse. */ | |
1504 | if (type->elems == 0) | |
1505 | return FAIL; | |
1506 | ||
1507 | *str = ptr; | |
1508 | ||
1509 | return SUCCESS; | |
1510 | } | |
1511 | ||
1512 | /* Errors may be set multiple times during parsing or bit encoding | |
1513 | (particularly in the Neon bits), but usually the earliest error which is set | |
1514 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1515 | errors by calling this function. */ | |
1516 | ||
1517 | static void | |
1518 | first_error (const char *err) | |
1519 | { | |
1520 | if (!inst.error) | |
1521 | inst.error = err; | |
1522 | } | |
1523 | ||
1524 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1525 | static int | |
1526 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1527 | { | |
1528 | char *str = *ccp; | |
1529 | struct neon_type optype; | |
1530 | ||
1531 | if (*str == '.') | |
1532 | { | |
1533 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1534 | { |
1535 | if (optype.elems == 1) | |
1536 | *vectype = optype.el[0]; | |
1537 | else | |
1538 | { | |
1539 | first_error (_("only one type should be specified for operand")); | |
1540 | return FAIL; | |
1541 | } | |
1542 | } | |
dcbf9037 | 1543 | else |
477330fc RM |
1544 | { |
1545 | first_error (_("vector type expected")); | |
1546 | return FAIL; | |
1547 | } | |
dcbf9037 JB |
1548 | } |
1549 | else | |
1550 | return FAIL; | |
5f4273c7 | 1551 | |
dcbf9037 | 1552 | *ccp = str; |
5f4273c7 | 1553 | |
dcbf9037 JB |
1554 | return SUCCESS; |
1555 | } | |
1556 | ||
1557 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1558 | a 4-bit integer. */ | |
1559 | ||
1560 | #define NEON_ALL_LANES 15 | |
1561 | #define NEON_INTERLEAVE_LANES 14 | |
1562 | ||
5ee91343 AV |
1563 | /* Record a use of the given feature. */ |
1564 | static void | |
1565 | record_feature_use (const arm_feature_set *feature) | |
1566 | { | |
1567 | if (thumb_mode) | |
1568 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
1569 | else | |
1570 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
1571 | } | |
1572 | ||
1573 | /* If the given feature available in the selected CPU, mark it as used. | |
1574 | Returns TRUE iff feature is available. */ | |
1575 | static bfd_boolean | |
1576 | mark_feature_used (const arm_feature_set *feature) | |
1577 | { | |
886e1c73 AV |
1578 | |
1579 | /* Do not support the use of MVE only instructions when in auto-detection or | |
1580 | -march=all. */ | |
1581 | if (((feature == &mve_ext) || (feature == &mve_fp_ext)) | |
1582 | && ARM_CPU_IS_ANY (cpu_variant)) | |
1583 | { | |
1584 | first_error (BAD_MVE_AUTO); | |
1585 | return FALSE; | |
1586 | } | |
5ee91343 AV |
1587 | /* Ensure the option is valid on the current architecture. */ |
1588 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
1589 | return FALSE; | |
1590 | ||
1591 | /* Add the appropriate architecture feature for the barrier option used. | |
1592 | */ | |
1593 | record_feature_use (feature); | |
1594 | ||
1595 | return TRUE; | |
1596 | } | |
1597 | ||
dcbf9037 JB |
1598 | /* Parse either a register or a scalar, with an optional type. Return the |
1599 | register number, and optionally fill in the actual type of the register | |
1600 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1601 | type/index information in *TYPEINFO. */ | |
1602 | ||
1603 | static int | |
1604 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1605 | enum arm_reg_type *rtype, |
1606 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1607 | { |
1608 | char *str = *ccp; | |
1609 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1610 | struct neon_typed_alias atype; | |
1611 | struct neon_type_el parsetype; | |
1612 | ||
1613 | atype.defined = 0; | |
1614 | atype.index = -1; | |
1615 | atype.eltype.type = NT_invtype; | |
1616 | atype.eltype.size = -1; | |
1617 | ||
1618 | /* Try alternate syntax for some types of register. Note these are mutually | |
1619 | exclusive with the Neon syntax extensions. */ | |
1620 | if (reg == NULL) | |
1621 | { | |
1622 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1623 | if (altreg != FAIL) | |
477330fc | 1624 | *ccp = str; |
dcbf9037 | 1625 | if (typeinfo) |
477330fc | 1626 | *typeinfo = atype; |
dcbf9037 JB |
1627 | return altreg; |
1628 | } | |
1629 | ||
037e8744 JB |
1630 | /* Undo polymorphism when a set of register types may be accepted. */ |
1631 | if ((type == REG_TYPE_NDQ | |
1632 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1633 | || (type == REG_TYPE_VFSD | |
477330fc | 1634 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1635 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1636 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1637 | || reg->type == REG_TYPE_NQ)) | |
dec41383 JW |
1638 | || (type == REG_TYPE_NSD |
1639 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
f512f76f NC |
1640 | || (type == REG_TYPE_MMXWC |
1641 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1642 | type = (enum arm_reg_type) reg->type; |
dcbf9037 | 1643 | |
5ee91343 AV |
1644 | if (type == REG_TYPE_MQ) |
1645 | { | |
1646 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
1647 | return FAIL; | |
1648 | ||
1649 | if (!reg || reg->type != REG_TYPE_NQ) | |
1650 | return FAIL; | |
1651 | ||
1652 | if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32)) | |
1653 | { | |
1654 | first_error (_("expected MVE register [q0..q7]")); | |
1655 | return FAIL; | |
1656 | } | |
1657 | type = REG_TYPE_NQ; | |
1658 | } | |
1659 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
1660 | && (type == REG_TYPE_NQ)) | |
1661 | return FAIL; | |
1662 | ||
1663 | ||
dcbf9037 JB |
1664 | if (type != reg->type) |
1665 | return FAIL; | |
1666 | ||
1667 | if (reg->neon) | |
1668 | atype = *reg->neon; | |
5f4273c7 | 1669 | |
dcbf9037 JB |
1670 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1671 | { | |
1672 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1673 | { |
1674 | first_error (_("can't redefine type for operand")); | |
1675 | return FAIL; | |
1676 | } | |
dcbf9037 JB |
1677 | atype.defined |= NTA_HASTYPE; |
1678 | atype.eltype = parsetype; | |
1679 | } | |
5f4273c7 | 1680 | |
dcbf9037 JB |
1681 | if (skip_past_char (&str, '[') == SUCCESS) |
1682 | { | |
dec41383 JW |
1683 | if (type != REG_TYPE_VFD |
1684 | && !(type == REG_TYPE_VFS | |
57785aa2 AV |
1685 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2)) |
1686 | && !(type == REG_TYPE_NQ | |
1687 | && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))) | |
477330fc | 1688 | { |
57785aa2 AV |
1689 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
1690 | first_error (_("only D and Q registers may be indexed")); | |
1691 | else | |
1692 | first_error (_("only D registers may be indexed")); | |
477330fc RM |
1693 | return FAIL; |
1694 | } | |
5f4273c7 | 1695 | |
dcbf9037 | 1696 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1697 | { |
1698 | first_error (_("can't change index for operand")); | |
1699 | return FAIL; | |
1700 | } | |
dcbf9037 JB |
1701 | |
1702 | atype.defined |= NTA_HASINDEX; | |
1703 | ||
1704 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1705 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1706 | else |
477330fc RM |
1707 | { |
1708 | expressionS exp; | |
dcbf9037 | 1709 | |
477330fc | 1710 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1711 | |
477330fc RM |
1712 | if (exp.X_op != O_constant) |
1713 | { | |
1714 | first_error (_("constant expression required")); | |
1715 | return FAIL; | |
1716 | } | |
dcbf9037 | 1717 | |
477330fc RM |
1718 | if (skip_past_char (&str, ']') == FAIL) |
1719 | return FAIL; | |
dcbf9037 | 1720 | |
477330fc RM |
1721 | atype.index = exp.X_add_number; |
1722 | } | |
dcbf9037 | 1723 | } |
5f4273c7 | 1724 | |
dcbf9037 JB |
1725 | if (typeinfo) |
1726 | *typeinfo = atype; | |
5f4273c7 | 1727 | |
dcbf9037 JB |
1728 | if (rtype) |
1729 | *rtype = type; | |
5f4273c7 | 1730 | |
dcbf9037 | 1731 | *ccp = str; |
5f4273c7 | 1732 | |
dcbf9037 JB |
1733 | return reg->number; |
1734 | } | |
1735 | ||
efd6b359 | 1736 | /* Like arm_reg_parse, but also allow the following extra features: |
dcbf9037 JB |
1737 | - If RTYPE is non-zero, return the (possibly restricted) type of the |
1738 | register (e.g. Neon double or quad reg when either has been requested). | |
1739 | - If this is a Neon vector type with additional type information, fill | |
1740 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1741 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1742 | |
1743 | static int | |
1744 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1745 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1746 | { |
1747 | struct neon_typed_alias atype; | |
1748 | char *str = *ccp; | |
1749 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1750 | ||
1751 | if (reg == FAIL) | |
1752 | return FAIL; | |
1753 | ||
0855e32b NS |
1754 | /* Do not allow regname(... to parse as a register. */ |
1755 | if (*str == '(') | |
1756 | return FAIL; | |
1757 | ||
dcbf9037 JB |
1758 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1759 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1760 | { | |
1761 | first_error (_("register operand expected, but got scalar")); | |
1762 | return FAIL; | |
1763 | } | |
1764 | ||
1765 | if (vectype) | |
1766 | *vectype = atype.eltype; | |
1767 | ||
1768 | *ccp = str; | |
1769 | ||
1770 | return reg; | |
1771 | } | |
1772 | ||
1773 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1774 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1775 | ||
5287ad62 JB |
1776 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1777 | have enough information to be able to do a good job bounds-checking. So, we | |
1778 | just do easy checks here, and do further checks later. */ | |
1779 | ||
1780 | static int | |
57785aa2 AV |
1781 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum |
1782 | arm_reg_type reg_type) | |
5287ad62 | 1783 | { |
dcbf9037 | 1784 | int reg; |
5287ad62 | 1785 | char *str = *ccp; |
dcbf9037 | 1786 | struct neon_typed_alias atype; |
57785aa2 | 1787 | unsigned reg_size; |
5f4273c7 | 1788 | |
dec41383 | 1789 | reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype); |
5f4273c7 | 1790 | |
57785aa2 AV |
1791 | switch (reg_type) |
1792 | { | |
1793 | case REG_TYPE_VFS: | |
1794 | reg_size = 32; | |
1795 | break; | |
1796 | case REG_TYPE_VFD: | |
1797 | reg_size = 64; | |
1798 | break; | |
1799 | case REG_TYPE_MQ: | |
1800 | reg_size = 128; | |
1801 | break; | |
1802 | default: | |
1803 | gas_assert (0); | |
1804 | return FAIL; | |
1805 | } | |
1806 | ||
dcbf9037 | 1807 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1808 | return FAIL; |
5f4273c7 | 1809 | |
57785aa2 | 1810 | if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES) |
5287ad62 | 1811 | { |
dcbf9037 | 1812 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1813 | return FAIL; |
1814 | } | |
57785aa2 | 1815 | else if (atype.index >= reg_size / elsize) |
5287ad62 | 1816 | { |
dcbf9037 | 1817 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1818 | return FAIL; |
1819 | } | |
5f4273c7 | 1820 | |
dcbf9037 JB |
1821 | if (type) |
1822 | *type = atype.eltype; | |
5f4273c7 | 1823 | |
5287ad62 | 1824 | *ccp = str; |
5f4273c7 | 1825 | |
dcbf9037 | 1826 | return reg * 16 + atype.index; |
5287ad62 JB |
1827 | } |
1828 | ||
4b5a202f AV |
1829 | /* Types of registers in a list. */ |
1830 | ||
1831 | enum reg_list_els | |
1832 | { | |
1833 | REGLIST_RN, | |
1834 | REGLIST_CLRM, | |
1835 | REGLIST_VFP_S, | |
efd6b359 | 1836 | REGLIST_VFP_S_VPR, |
4b5a202f | 1837 | REGLIST_VFP_D, |
efd6b359 | 1838 | REGLIST_VFP_D_VPR, |
4b5a202f AV |
1839 | REGLIST_NEON_D |
1840 | }; | |
1841 | ||
c19d1205 | 1842 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1843 | |
c19d1205 | 1844 | static long |
4b5a202f | 1845 | parse_reg_list (char ** strp, enum reg_list_els etype) |
c19d1205 | 1846 | { |
4b5a202f AV |
1847 | char *str = *strp; |
1848 | long range = 0; | |
1849 | int another_range; | |
1850 | ||
1851 | gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM); | |
a737bd4d | 1852 | |
c19d1205 ZW |
1853 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1854 | do | |
6057a28f | 1855 | { |
477330fc RM |
1856 | skip_whitespace (str); |
1857 | ||
c19d1205 | 1858 | another_range = 0; |
a737bd4d | 1859 | |
c19d1205 ZW |
1860 | if (*str == '{') |
1861 | { | |
1862 | int in_range = 0; | |
1863 | int cur_reg = -1; | |
a737bd4d | 1864 | |
c19d1205 ZW |
1865 | str++; |
1866 | do | |
1867 | { | |
1868 | int reg; | |
4b5a202f AV |
1869 | const char apsr_str[] = "apsr"; |
1870 | int apsr_str_len = strlen (apsr_str); | |
6057a28f | 1871 | |
4b5a202f AV |
1872 | reg = arm_reg_parse (&str, REGLIST_RN); |
1873 | if (etype == REGLIST_CLRM) | |
c19d1205 | 1874 | { |
4b5a202f AV |
1875 | if (reg == REG_SP || reg == REG_PC) |
1876 | reg = FAIL; | |
1877 | else if (reg == FAIL | |
1878 | && !strncasecmp (str, apsr_str, apsr_str_len) | |
1879 | && !ISALPHA (*(str + apsr_str_len))) | |
1880 | { | |
1881 | reg = 15; | |
1882 | str += apsr_str_len; | |
1883 | } | |
1884 | ||
1885 | if (reg == FAIL) | |
1886 | { | |
1887 | first_error (_("r0-r12, lr or APSR expected")); | |
1888 | return FAIL; | |
1889 | } | |
1890 | } | |
1891 | else /* etype == REGLIST_RN. */ | |
1892 | { | |
1893 | if (reg == FAIL) | |
1894 | { | |
1895 | first_error (_(reg_expected_msgs[REGLIST_RN])); | |
1896 | return FAIL; | |
1897 | } | |
c19d1205 | 1898 | } |
a737bd4d | 1899 | |
c19d1205 ZW |
1900 | if (in_range) |
1901 | { | |
1902 | int i; | |
a737bd4d | 1903 | |
c19d1205 ZW |
1904 | if (reg <= cur_reg) |
1905 | { | |
dcbf9037 | 1906 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1907 | return FAIL; |
1908 | } | |
40a18ebd | 1909 | |
c19d1205 ZW |
1910 | for (i = cur_reg + 1; i < reg; i++) |
1911 | { | |
1912 | if (range & (1 << i)) | |
1913 | as_tsktsk | |
1914 | (_("Warning: duplicated register (r%d) in register list"), | |
1915 | i); | |
1916 | else | |
1917 | range |= 1 << i; | |
1918 | } | |
1919 | in_range = 0; | |
1920 | } | |
a737bd4d | 1921 | |
c19d1205 ZW |
1922 | if (range & (1 << reg)) |
1923 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1924 | reg); | |
1925 | else if (reg <= cur_reg) | |
1926 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1927 | |
c19d1205 ZW |
1928 | range |= 1 << reg; |
1929 | cur_reg = reg; | |
1930 | } | |
1931 | while (skip_past_comma (&str) != FAIL | |
1932 | || (in_range = 1, *str++ == '-')); | |
1933 | str--; | |
a737bd4d | 1934 | |
d996d970 | 1935 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1936 | { |
dcbf9037 | 1937 | first_error (_("missing `}'")); |
c19d1205 ZW |
1938 | return FAIL; |
1939 | } | |
1940 | } | |
4b5a202f | 1941 | else if (etype == REGLIST_RN) |
c19d1205 | 1942 | { |
91d6fa6a | 1943 | expressionS exp; |
40a18ebd | 1944 | |
91d6fa6a | 1945 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1946 | return FAIL; |
40a18ebd | 1947 | |
91d6fa6a | 1948 | if (exp.X_op == O_constant) |
c19d1205 | 1949 | { |
91d6fa6a NC |
1950 | if (exp.X_add_number |
1951 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1952 | { |
1953 | inst.error = _("invalid register mask"); | |
1954 | return FAIL; | |
1955 | } | |
a737bd4d | 1956 | |
91d6fa6a | 1957 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1958 | { |
91d6fa6a | 1959 | int regno = range & exp.X_add_number; |
a737bd4d | 1960 | |
c19d1205 ZW |
1961 | regno &= -regno; |
1962 | regno = (1 << regno) - 1; | |
1963 | as_tsktsk | |
1964 | (_("Warning: duplicated register (r%d) in register list"), | |
1965 | regno); | |
1966 | } | |
a737bd4d | 1967 | |
91d6fa6a | 1968 | range |= exp.X_add_number; |
c19d1205 ZW |
1969 | } |
1970 | else | |
1971 | { | |
e2b0ab59 | 1972 | if (inst.relocs[0].type != 0) |
c19d1205 ZW |
1973 | { |
1974 | inst.error = _("expression too complex"); | |
1975 | return FAIL; | |
1976 | } | |
a737bd4d | 1977 | |
e2b0ab59 AV |
1978 | memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS)); |
1979 | inst.relocs[0].type = BFD_RELOC_ARM_MULTI; | |
1980 | inst.relocs[0].pc_rel = 0; | |
c19d1205 ZW |
1981 | } |
1982 | } | |
a737bd4d | 1983 | |
c19d1205 ZW |
1984 | if (*str == '|' || *str == '+') |
1985 | { | |
1986 | str++; | |
1987 | another_range = 1; | |
1988 | } | |
a737bd4d | 1989 | } |
c19d1205 | 1990 | while (another_range); |
a737bd4d | 1991 | |
c19d1205 ZW |
1992 | *strp = str; |
1993 | return range; | |
a737bd4d NC |
1994 | } |
1995 | ||
c19d1205 ZW |
1996 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1997 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1998 | register. Parses registers of type ETYPE. |
1999 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
2000 | - Q registers can be used to specify pairs of D registers | |
2001 | - { } can be omitted from around a singleton register list | |
477330fc RM |
2002 | FIXME: This is not implemented, as it would require backtracking in |
2003 | some cases, e.g.: | |
2004 | vtbl.8 d3,d4,d5 | |
2005 | This could be done (the meaning isn't really ambiguous), but doesn't | |
2006 | fit in well with the current parsing framework. | |
dcbf9037 JB |
2007 | - 32 D registers may be used (also true for VFPv3). |
2008 | FIXME: Types are ignored in these register lists, which is probably a | |
2009 | bug. */ | |
6057a28f | 2010 | |
c19d1205 | 2011 | static int |
efd6b359 AV |
2012 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype, |
2013 | bfd_boolean *partial_match) | |
6057a28f | 2014 | { |
037e8744 | 2015 | char *str = *ccp; |
c19d1205 ZW |
2016 | int base_reg; |
2017 | int new_base; | |
21d799b5 | 2018 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 2019 | int max_regs = 0; |
c19d1205 ZW |
2020 | int count = 0; |
2021 | int warned = 0; | |
2022 | unsigned long mask = 0; | |
a737bd4d | 2023 | int i; |
efd6b359 AV |
2024 | bfd_boolean vpr_seen = FALSE; |
2025 | bfd_boolean expect_vpr = | |
2026 | (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR); | |
6057a28f | 2027 | |
477330fc | 2028 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
2029 | { |
2030 | inst.error = _("expecting {"); | |
2031 | return FAIL; | |
2032 | } | |
6057a28f | 2033 | |
5287ad62 | 2034 | switch (etype) |
c19d1205 | 2035 | { |
5287ad62 | 2036 | case REGLIST_VFP_S: |
efd6b359 | 2037 | case REGLIST_VFP_S_VPR: |
c19d1205 ZW |
2038 | regtype = REG_TYPE_VFS; |
2039 | max_regs = 32; | |
5287ad62 | 2040 | break; |
5f4273c7 | 2041 | |
5287ad62 | 2042 | case REGLIST_VFP_D: |
efd6b359 | 2043 | case REGLIST_VFP_D_VPR: |
5287ad62 | 2044 | regtype = REG_TYPE_VFD; |
b7fc2769 | 2045 | break; |
5f4273c7 | 2046 | |
b7fc2769 JB |
2047 | case REGLIST_NEON_D: |
2048 | regtype = REG_TYPE_NDQ; | |
2049 | break; | |
4b5a202f AV |
2050 | |
2051 | default: | |
2052 | gas_assert (0); | |
b7fc2769 JB |
2053 | } |
2054 | ||
efd6b359 | 2055 | if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR) |
b7fc2769 | 2056 | { |
b1cc4aeb PB |
2057 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
2058 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
2059 | { |
2060 | max_regs = 32; | |
2061 | if (thumb_mode) | |
2062 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
2063 | fpu_vfp_ext_d32); | |
2064 | else | |
2065 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
2066 | fpu_vfp_ext_d32); | |
2067 | } | |
5287ad62 | 2068 | else |
477330fc | 2069 | max_regs = 16; |
c19d1205 | 2070 | } |
6057a28f | 2071 | |
c19d1205 | 2072 | base_reg = max_regs; |
efd6b359 | 2073 | *partial_match = FALSE; |
a737bd4d | 2074 | |
c19d1205 ZW |
2075 | do |
2076 | { | |
5287ad62 | 2077 | int setmask = 1, addregs = 1; |
efd6b359 AV |
2078 | const char vpr_str[] = "vpr"; |
2079 | int vpr_str_len = strlen (vpr_str); | |
dcbf9037 | 2080 | |
037e8744 | 2081 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 2082 | |
efd6b359 AV |
2083 | if (expect_vpr) |
2084 | { | |
2085 | if (new_base == FAIL | |
2086 | && !strncasecmp (str, vpr_str, vpr_str_len) | |
2087 | && !ISALPHA (*(str + vpr_str_len)) | |
2088 | && !vpr_seen) | |
2089 | { | |
2090 | vpr_seen = TRUE; | |
2091 | str += vpr_str_len; | |
2092 | if (count == 0) | |
2093 | base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */ | |
2094 | } | |
2095 | else if (vpr_seen) | |
2096 | { | |
2097 | first_error (_("VPR expected last")); | |
2098 | return FAIL; | |
2099 | } | |
2100 | else if (new_base == FAIL) | |
2101 | { | |
2102 | if (regtype == REG_TYPE_VFS) | |
2103 | first_error (_("VFP single precision register or VPR " | |
2104 | "expected")); | |
2105 | else /* regtype == REG_TYPE_VFD. */ | |
2106 | first_error (_("VFP/Neon double precision register or VPR " | |
2107 | "expected")); | |
2108 | return FAIL; | |
2109 | } | |
2110 | } | |
2111 | else if (new_base == FAIL) | |
a737bd4d | 2112 | { |
dcbf9037 | 2113 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
2114 | return FAIL; |
2115 | } | |
5f4273c7 | 2116 | |
efd6b359 AV |
2117 | *partial_match = TRUE; |
2118 | if (vpr_seen) | |
2119 | continue; | |
2120 | ||
b7fc2769 | 2121 | if (new_base >= max_regs) |
477330fc RM |
2122 | { |
2123 | first_error (_("register out of range in list")); | |
2124 | return FAIL; | |
2125 | } | |
5f4273c7 | 2126 | |
5287ad62 JB |
2127 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
2128 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
2129 | { |
2130 | setmask = 3; | |
2131 | addregs = 2; | |
2132 | } | |
5287ad62 | 2133 | |
c19d1205 ZW |
2134 | if (new_base < base_reg) |
2135 | base_reg = new_base; | |
a737bd4d | 2136 | |
5287ad62 | 2137 | if (mask & (setmask << new_base)) |
c19d1205 | 2138 | { |
dcbf9037 | 2139 | first_error (_("invalid register list")); |
c19d1205 | 2140 | return FAIL; |
a737bd4d | 2141 | } |
a737bd4d | 2142 | |
efd6b359 | 2143 | if ((mask >> new_base) != 0 && ! warned && !vpr_seen) |
c19d1205 ZW |
2144 | { |
2145 | as_tsktsk (_("register list not in ascending order")); | |
2146 | warned = 1; | |
2147 | } | |
0bbf2aa4 | 2148 | |
5287ad62 JB |
2149 | mask |= setmask << new_base; |
2150 | count += addregs; | |
0bbf2aa4 | 2151 | |
037e8744 | 2152 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
2153 | { |
2154 | int high_range; | |
0bbf2aa4 | 2155 | |
037e8744 | 2156 | str++; |
0bbf2aa4 | 2157 | |
037e8744 | 2158 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 2159 | == FAIL) |
c19d1205 ZW |
2160 | { |
2161 | inst.error = gettext (reg_expected_msgs[regtype]); | |
2162 | return FAIL; | |
2163 | } | |
0bbf2aa4 | 2164 | |
477330fc RM |
2165 | if (high_range >= max_regs) |
2166 | { | |
2167 | first_error (_("register out of range in list")); | |
2168 | return FAIL; | |
2169 | } | |
b7fc2769 | 2170 | |
477330fc RM |
2171 | if (regtype == REG_TYPE_NQ) |
2172 | high_range = high_range + 1; | |
5287ad62 | 2173 | |
c19d1205 ZW |
2174 | if (high_range <= new_base) |
2175 | { | |
2176 | inst.error = _("register range not in ascending order"); | |
2177 | return FAIL; | |
2178 | } | |
0bbf2aa4 | 2179 | |
5287ad62 | 2180 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 2181 | { |
5287ad62 | 2182 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 2183 | { |
c19d1205 ZW |
2184 | inst.error = _("invalid register list"); |
2185 | return FAIL; | |
0bbf2aa4 | 2186 | } |
c19d1205 | 2187 | |
5287ad62 JB |
2188 | mask |= setmask << new_base; |
2189 | count += addregs; | |
0bbf2aa4 | 2190 | } |
0bbf2aa4 | 2191 | } |
0bbf2aa4 | 2192 | } |
037e8744 | 2193 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 2194 | |
037e8744 | 2195 | str++; |
0bbf2aa4 | 2196 | |
c19d1205 | 2197 | /* Sanity check -- should have raised a parse error above. */ |
efd6b359 | 2198 | if ((!vpr_seen && count == 0) || count > max_regs) |
c19d1205 ZW |
2199 | abort (); |
2200 | ||
2201 | *pbase = base_reg; | |
2202 | ||
efd6b359 AV |
2203 | if (expect_vpr && !vpr_seen) |
2204 | { | |
2205 | first_error (_("VPR expected last")); | |
2206 | return FAIL; | |
2207 | } | |
2208 | ||
c19d1205 ZW |
2209 | /* Final test -- the registers must be consecutive. */ |
2210 | mask >>= base_reg; | |
2211 | for (i = 0; i < count; i++) | |
2212 | { | |
2213 | if ((mask & (1u << i)) == 0) | |
2214 | { | |
2215 | inst.error = _("non-contiguous register range"); | |
2216 | return FAIL; | |
2217 | } | |
2218 | } | |
2219 | ||
037e8744 JB |
2220 | *ccp = str; |
2221 | ||
c19d1205 | 2222 | return count; |
b99bd4ef NC |
2223 | } |
2224 | ||
dcbf9037 JB |
2225 | /* True if two alias types are the same. */ |
2226 | ||
c921be7d | 2227 | static bfd_boolean |
dcbf9037 JB |
2228 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
2229 | { | |
2230 | if (!a && !b) | |
c921be7d | 2231 | return TRUE; |
5f4273c7 | 2232 | |
dcbf9037 | 2233 | if (!a || !b) |
c921be7d | 2234 | return FALSE; |
dcbf9037 JB |
2235 | |
2236 | if (a->defined != b->defined) | |
c921be7d | 2237 | return FALSE; |
5f4273c7 | 2238 | |
dcbf9037 JB |
2239 | if ((a->defined & NTA_HASTYPE) != 0 |
2240 | && (a->eltype.type != b->eltype.type | |
477330fc | 2241 | || a->eltype.size != b->eltype.size)) |
c921be7d | 2242 | return FALSE; |
dcbf9037 JB |
2243 | |
2244 | if ((a->defined & NTA_HASINDEX) != 0 | |
2245 | && (a->index != b->index)) | |
c921be7d | 2246 | return FALSE; |
5f4273c7 | 2247 | |
c921be7d | 2248 | return TRUE; |
dcbf9037 JB |
2249 | } |
2250 | ||
5287ad62 JB |
2251 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
2252 | The base register is put in *PBASE. | |
dcbf9037 | 2253 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
2254 | the return value. |
2255 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
2256 | Bits [6:5] encode the list length (minus one). |
2257 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 2258 | |
5287ad62 | 2259 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 2260 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
2261 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
2262 | ||
2263 | static int | |
dcbf9037 | 2264 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
35c228db | 2265 | int mve, |
477330fc | 2266 | struct neon_type_el *eltype) |
5287ad62 JB |
2267 | { |
2268 | char *ptr = *str; | |
2269 | int base_reg = -1; | |
2270 | int reg_incr = -1; | |
2271 | int count = 0; | |
2272 | int lane = -1; | |
2273 | int leading_brace = 0; | |
2274 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
35c228db AV |
2275 | const char *const incr_error = mve ? _("register stride must be 1") : |
2276 | _("register stride must be 1 or 2"); | |
20203fb9 | 2277 | const char *const type_error = _("mismatched element/structure types in list"); |
dcbf9037 | 2278 | struct neon_typed_alias firsttype; |
f85d59c3 KT |
2279 | firsttype.defined = 0; |
2280 | firsttype.eltype.type = NT_invtype; | |
2281 | firsttype.eltype.size = -1; | |
2282 | firsttype.index = -1; | |
5f4273c7 | 2283 | |
5287ad62 JB |
2284 | if (skip_past_char (&ptr, '{') == SUCCESS) |
2285 | leading_brace = 1; | |
5f4273c7 | 2286 | |
5287ad62 JB |
2287 | do |
2288 | { | |
dcbf9037 | 2289 | struct neon_typed_alias atype; |
35c228db AV |
2290 | if (mve) |
2291 | rtype = REG_TYPE_MQ; | |
dcbf9037 JB |
2292 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); |
2293 | ||
5287ad62 | 2294 | if (getreg == FAIL) |
477330fc RM |
2295 | { |
2296 | first_error (_(reg_expected_msgs[rtype])); | |
2297 | return FAIL; | |
2298 | } | |
5f4273c7 | 2299 | |
5287ad62 | 2300 | if (base_reg == -1) |
477330fc RM |
2301 | { |
2302 | base_reg = getreg; | |
2303 | if (rtype == REG_TYPE_NQ) | |
2304 | { | |
2305 | reg_incr = 1; | |
2306 | } | |
2307 | firsttype = atype; | |
2308 | } | |
5287ad62 | 2309 | else if (reg_incr == -1) |
477330fc RM |
2310 | { |
2311 | reg_incr = getreg - base_reg; | |
2312 | if (reg_incr < 1 || reg_incr > 2) | |
2313 | { | |
2314 | first_error (_(incr_error)); | |
2315 | return FAIL; | |
2316 | } | |
2317 | } | |
5287ad62 | 2318 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
2319 | { |
2320 | first_error (_(incr_error)); | |
2321 | return FAIL; | |
2322 | } | |
dcbf9037 | 2323 | |
c921be7d | 2324 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2325 | { |
2326 | first_error (_(type_error)); | |
2327 | return FAIL; | |
2328 | } | |
5f4273c7 | 2329 | |
5287ad62 | 2330 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2331 | modes. */ |
5287ad62 | 2332 | if (ptr[0] == '-') |
477330fc RM |
2333 | { |
2334 | struct neon_typed_alias htype; | |
2335 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2336 | if (lane == -1) | |
2337 | lane = NEON_INTERLEAVE_LANES; | |
2338 | else if (lane != NEON_INTERLEAVE_LANES) | |
2339 | { | |
2340 | first_error (_(type_error)); | |
2341 | return FAIL; | |
2342 | } | |
2343 | if (reg_incr == -1) | |
2344 | reg_incr = 1; | |
2345 | else if (reg_incr != 1) | |
2346 | { | |
2347 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2348 | return FAIL; | |
2349 | } | |
2350 | ptr++; | |
2351 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2352 | if (hireg == FAIL) | |
2353 | { | |
2354 | first_error (_(reg_expected_msgs[rtype])); | |
2355 | return FAIL; | |
2356 | } | |
2357 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2358 | { | |
2359 | first_error (_(type_error)); | |
2360 | return FAIL; | |
2361 | } | |
2362 | count += hireg + dregs - getreg; | |
2363 | continue; | |
2364 | } | |
5f4273c7 | 2365 | |
5287ad62 JB |
2366 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2367 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2368 | { |
2369 | count += 2; | |
2370 | continue; | |
2371 | } | |
5f4273c7 | 2372 | |
dcbf9037 | 2373 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2374 | { |
2375 | if (lane == -1) | |
2376 | lane = atype.index; | |
2377 | else if (lane != atype.index) | |
2378 | { | |
2379 | first_error (_(type_error)); | |
2380 | return FAIL; | |
2381 | } | |
2382 | } | |
5287ad62 | 2383 | else if (lane == -1) |
477330fc | 2384 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2385 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2386 | { |
2387 | first_error (_(type_error)); | |
2388 | return FAIL; | |
2389 | } | |
5287ad62 JB |
2390 | count++; |
2391 | } | |
2392 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2393 | |
5287ad62 JB |
2394 | /* No lane set by [x]. We must be interleaving structures. */ |
2395 | if (lane == -1) | |
2396 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2397 | |
5287ad62 | 2398 | /* Sanity check. */ |
35c228db | 2399 | if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4) |
5287ad62 JB |
2400 | || (count > 1 && reg_incr == -1)) |
2401 | { | |
dcbf9037 | 2402 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2403 | return FAIL; |
2404 | } | |
2405 | ||
2406 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2407 | { | |
dcbf9037 | 2408 | first_error (_("expected }")); |
5287ad62 JB |
2409 | return FAIL; |
2410 | } | |
5f4273c7 | 2411 | |
5287ad62 JB |
2412 | if (reg_incr == -1) |
2413 | reg_incr = 1; | |
2414 | ||
dcbf9037 JB |
2415 | if (eltype) |
2416 | *eltype = firsttype.eltype; | |
2417 | ||
5287ad62 JB |
2418 | *pbase = base_reg; |
2419 | *str = ptr; | |
5f4273c7 | 2420 | |
5287ad62 JB |
2421 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2422 | } | |
2423 | ||
c19d1205 ZW |
2424 | /* Parse an explicit relocation suffix on an expression. This is |
2425 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2426 | arm_reloc_hsh contains no entries, so this function can only | |
2427 | succeed if there is no () after the word. Returns -1 on error, | |
2428 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2429 | |
c19d1205 ZW |
2430 | static int |
2431 | parse_reloc (char **str) | |
b99bd4ef | 2432 | { |
c19d1205 ZW |
2433 | struct reloc_entry *r; |
2434 | char *p, *q; | |
b99bd4ef | 2435 | |
c19d1205 ZW |
2436 | if (**str != '(') |
2437 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2438 | |
c19d1205 ZW |
2439 | p = *str + 1; |
2440 | q = p; | |
2441 | ||
2442 | while (*q && *q != ')' && *q != ',') | |
2443 | q++; | |
2444 | if (*q != ')') | |
2445 | return -1; | |
2446 | ||
21d799b5 NC |
2447 | if ((r = (struct reloc_entry *) |
2448 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2449 | return -1; |
2450 | ||
2451 | *str = q + 1; | |
2452 | return r->reloc; | |
b99bd4ef NC |
2453 | } |
2454 | ||
c19d1205 ZW |
2455 | /* Directives: register aliases. */ |
2456 | ||
dcbf9037 | 2457 | static struct reg_entry * |
90ec0d68 | 2458 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2459 | { |
d3ce72d0 | 2460 | struct reg_entry *new_reg; |
c19d1205 | 2461 | const char *name; |
b99bd4ef | 2462 | |
d3ce72d0 | 2463 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2464 | { |
d3ce72d0 | 2465 | if (new_reg->builtin) |
c19d1205 | 2466 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2467 | |
c19d1205 ZW |
2468 | /* Only warn about a redefinition if it's not defined as the |
2469 | same register. */ | |
d3ce72d0 | 2470 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2471 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2472 | |
d929913e | 2473 | return NULL; |
c19d1205 | 2474 | } |
b99bd4ef | 2475 | |
c19d1205 | 2476 | name = xstrdup (str); |
325801bd | 2477 | new_reg = XNEW (struct reg_entry); |
b99bd4ef | 2478 | |
d3ce72d0 NC |
2479 | new_reg->name = name; |
2480 | new_reg->number = number; | |
2481 | new_reg->type = type; | |
2482 | new_reg->builtin = FALSE; | |
2483 | new_reg->neon = NULL; | |
b99bd4ef | 2484 | |
d3ce72d0 | 2485 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2486 | abort (); |
5f4273c7 | 2487 | |
d3ce72d0 | 2488 | return new_reg; |
dcbf9037 JB |
2489 | } |
2490 | ||
2491 | static void | |
2492 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2493 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2494 | { |
2495 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2496 | |
dcbf9037 JB |
2497 | if (!reg) |
2498 | { | |
2499 | first_error (_("attempt to redefine typed alias")); | |
2500 | return; | |
2501 | } | |
5f4273c7 | 2502 | |
dcbf9037 JB |
2503 | if (atype) |
2504 | { | |
325801bd | 2505 | reg->neon = XNEW (struct neon_typed_alias); |
dcbf9037 JB |
2506 | *reg->neon = *atype; |
2507 | } | |
c19d1205 | 2508 | } |
b99bd4ef | 2509 | |
c19d1205 | 2510 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2511 | |
c19d1205 | 2512 | new_register_name .req existing_register_name |
b99bd4ef | 2513 | |
c19d1205 | 2514 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2515 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2516 | |
d929913e | 2517 | static bfd_boolean |
c19d1205 ZW |
2518 | create_register_alias (char * newname, char *p) |
2519 | { | |
2520 | struct reg_entry *old; | |
2521 | char *oldname, *nbuf; | |
2522 | size_t nlen; | |
b99bd4ef | 2523 | |
c19d1205 ZW |
2524 | /* The input scrubber ensures that whitespace after the mnemonic is |
2525 | collapsed to single spaces. */ | |
2526 | oldname = p; | |
2527 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2528 | return FALSE; |
b99bd4ef | 2529 | |
c19d1205 ZW |
2530 | oldname += 6; |
2531 | if (*oldname == '\0') | |
d929913e | 2532 | return FALSE; |
b99bd4ef | 2533 | |
21d799b5 | 2534 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2535 | if (!old) |
b99bd4ef | 2536 | { |
c19d1205 | 2537 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2538 | return TRUE; |
b99bd4ef NC |
2539 | } |
2540 | ||
c19d1205 ZW |
2541 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2542 | the desired alias name, and p points to its end. If not, then | |
2543 | the desired alias name is in the global original_case_string. */ | |
2544 | #ifdef TC_CASE_SENSITIVE | |
2545 | nlen = p - newname; | |
2546 | #else | |
2547 | newname = original_case_string; | |
2548 | nlen = strlen (newname); | |
2549 | #endif | |
b99bd4ef | 2550 | |
29a2809e | 2551 | nbuf = xmemdup0 (newname, nlen); |
b99bd4ef | 2552 | |
c19d1205 ZW |
2553 | /* Create aliases under the new name as stated; an all-lowercase |
2554 | version of the new name; and an all-uppercase version of the new | |
2555 | name. */ | |
d929913e NC |
2556 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2557 | { | |
2558 | for (p = nbuf; *p; p++) | |
2559 | *p = TOUPPER (*p); | |
c19d1205 | 2560 | |
d929913e NC |
2561 | if (strncmp (nbuf, newname, nlen)) |
2562 | { | |
2563 | /* If this attempt to create an additional alias fails, do not bother | |
2564 | trying to create the all-lower case alias. We will fail and issue | |
2565 | a second, duplicate error message. This situation arises when the | |
2566 | programmer does something like: | |
2567 | foo .req r0 | |
2568 | Foo .req r1 | |
2569 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2570 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2571 | first .req. */ |
2572 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
e1fa0163 NC |
2573 | { |
2574 | free (nbuf); | |
2575 | return TRUE; | |
2576 | } | |
d929913e | 2577 | } |
c19d1205 | 2578 | |
d929913e NC |
2579 | for (p = nbuf; *p; p++) |
2580 | *p = TOLOWER (*p); | |
c19d1205 | 2581 | |
d929913e NC |
2582 | if (strncmp (nbuf, newname, nlen)) |
2583 | insert_reg_alias (nbuf, old->number, old->type); | |
2584 | } | |
c19d1205 | 2585 | |
e1fa0163 | 2586 | free (nbuf); |
d929913e | 2587 | return TRUE; |
b99bd4ef NC |
2588 | } |
2589 | ||
dcbf9037 JB |
2590 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2591 | X .dn d5.s32[1] | |
2592 | Y .qn 6.s16 | |
2593 | Z .dn d7 | |
2594 | T .dn Z[0] | |
2595 | These typed registers can be used instead of the types specified after the | |
2596 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2597 | specified directly, e.g.: | |
5f4273c7 | 2598 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2599 | |
c921be7d | 2600 | static bfd_boolean |
dcbf9037 JB |
2601 | create_neon_reg_alias (char *newname, char *p) |
2602 | { | |
2603 | enum arm_reg_type basetype; | |
2604 | struct reg_entry *basereg; | |
2605 | struct reg_entry mybasereg; | |
2606 | struct neon_type ntype; | |
2607 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2608 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2609 | int namelen; |
5f4273c7 | 2610 | |
dcbf9037 JB |
2611 | typeinfo.defined = 0; |
2612 | typeinfo.eltype.type = NT_invtype; | |
2613 | typeinfo.eltype.size = -1; | |
2614 | typeinfo.index = -1; | |
5f4273c7 | 2615 | |
dcbf9037 | 2616 | nameend = p; |
5f4273c7 | 2617 | |
dcbf9037 JB |
2618 | if (strncmp (p, " .dn ", 5) == 0) |
2619 | basetype = REG_TYPE_VFD; | |
2620 | else if (strncmp (p, " .qn ", 5) == 0) | |
2621 | basetype = REG_TYPE_NQ; | |
2622 | else | |
c921be7d | 2623 | return FALSE; |
5f4273c7 | 2624 | |
dcbf9037 | 2625 | p += 5; |
5f4273c7 | 2626 | |
dcbf9037 | 2627 | if (*p == '\0') |
c921be7d | 2628 | return FALSE; |
5f4273c7 | 2629 | |
dcbf9037 JB |
2630 | basereg = arm_reg_parse_multi (&p); |
2631 | ||
2632 | if (basereg && basereg->type != basetype) | |
2633 | { | |
2634 | as_bad (_("bad type for register")); | |
c921be7d | 2635 | return FALSE; |
dcbf9037 JB |
2636 | } |
2637 | ||
2638 | if (basereg == NULL) | |
2639 | { | |
2640 | expressionS exp; | |
2641 | /* Try parsing as an integer. */ | |
2642 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2643 | if (exp.X_op != O_constant) | |
477330fc RM |
2644 | { |
2645 | as_bad (_("expression must be constant")); | |
2646 | return FALSE; | |
2647 | } | |
dcbf9037 JB |
2648 | basereg = &mybasereg; |
2649 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2650 | : exp.X_add_number; |
dcbf9037 JB |
2651 | basereg->neon = 0; |
2652 | } | |
2653 | ||
2654 | if (basereg->neon) | |
2655 | typeinfo = *basereg->neon; | |
2656 | ||
2657 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2658 | { | |
2659 | /* We got a type. */ | |
2660 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2661 | { |
2662 | as_bad (_("can't redefine the type of a register alias")); | |
2663 | return FALSE; | |
2664 | } | |
5f4273c7 | 2665 | |
dcbf9037 JB |
2666 | typeinfo.defined |= NTA_HASTYPE; |
2667 | if (ntype.elems != 1) | |
477330fc RM |
2668 | { |
2669 | as_bad (_("you must specify a single type only")); | |
2670 | return FALSE; | |
2671 | } | |
dcbf9037 JB |
2672 | typeinfo.eltype = ntype.el[0]; |
2673 | } | |
5f4273c7 | 2674 | |
dcbf9037 JB |
2675 | if (skip_past_char (&p, '[') == SUCCESS) |
2676 | { | |
2677 | expressionS exp; | |
2678 | /* We got a scalar index. */ | |
5f4273c7 | 2679 | |
dcbf9037 | 2680 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2681 | { |
2682 | as_bad (_("can't redefine the index of a scalar alias")); | |
2683 | return FALSE; | |
2684 | } | |
5f4273c7 | 2685 | |
dcbf9037 | 2686 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2687 | |
dcbf9037 | 2688 | if (exp.X_op != O_constant) |
477330fc RM |
2689 | { |
2690 | as_bad (_("scalar index must be constant")); | |
2691 | return FALSE; | |
2692 | } | |
5f4273c7 | 2693 | |
dcbf9037 JB |
2694 | typeinfo.defined |= NTA_HASINDEX; |
2695 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2696 | |
dcbf9037 | 2697 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2698 | { |
2699 | as_bad (_("expecting ]")); | |
2700 | return FALSE; | |
2701 | } | |
dcbf9037 JB |
2702 | } |
2703 | ||
15735687 NS |
2704 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2705 | the desired alias name, and p points to its end. If not, then | |
2706 | the desired alias name is in the global original_case_string. */ | |
2707 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2708 | namelen = nameend - newname; |
15735687 NS |
2709 | #else |
2710 | newname = original_case_string; | |
2711 | namelen = strlen (newname); | |
2712 | #endif | |
2713 | ||
29a2809e | 2714 | namebuf = xmemdup0 (newname, namelen); |
5f4273c7 | 2715 | |
dcbf9037 | 2716 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2717 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2718 | |
dcbf9037 JB |
2719 | /* Insert name in all uppercase. */ |
2720 | for (p = namebuf; *p; p++) | |
2721 | *p = TOUPPER (*p); | |
5f4273c7 | 2722 | |
dcbf9037 JB |
2723 | if (strncmp (namebuf, newname, namelen)) |
2724 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2725 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2726 | |
dcbf9037 JB |
2727 | /* Insert name in all lowercase. */ |
2728 | for (p = namebuf; *p; p++) | |
2729 | *p = TOLOWER (*p); | |
5f4273c7 | 2730 | |
dcbf9037 JB |
2731 | if (strncmp (namebuf, newname, namelen)) |
2732 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2733 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2734 | |
e1fa0163 | 2735 | free (namebuf); |
c921be7d | 2736 | return TRUE; |
dcbf9037 JB |
2737 | } |
2738 | ||
c19d1205 ZW |
2739 | /* Should never be called, as .req goes between the alias and the |
2740 | register name, not at the beginning of the line. */ | |
c921be7d | 2741 | |
b99bd4ef | 2742 | static void |
c19d1205 | 2743 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2744 | { |
c19d1205 ZW |
2745 | as_bad (_("invalid syntax for .req directive")); |
2746 | } | |
b99bd4ef | 2747 | |
dcbf9037 JB |
2748 | static void |
2749 | s_dn (int a ATTRIBUTE_UNUSED) | |
2750 | { | |
2751 | as_bad (_("invalid syntax for .dn directive")); | |
2752 | } | |
2753 | ||
2754 | static void | |
2755 | s_qn (int a ATTRIBUTE_UNUSED) | |
2756 | { | |
2757 | as_bad (_("invalid syntax for .qn directive")); | |
2758 | } | |
2759 | ||
c19d1205 ZW |
2760 | /* The .unreq directive deletes an alias which was previously defined |
2761 | by .req. For example: | |
b99bd4ef | 2762 | |
c19d1205 ZW |
2763 | my_alias .req r11 |
2764 | .unreq my_alias */ | |
b99bd4ef NC |
2765 | |
2766 | static void | |
c19d1205 | 2767 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2768 | { |
c19d1205 ZW |
2769 | char * name; |
2770 | char saved_char; | |
b99bd4ef | 2771 | |
c19d1205 ZW |
2772 | name = input_line_pointer; |
2773 | ||
2774 | while (*input_line_pointer != 0 | |
2775 | && *input_line_pointer != ' ' | |
2776 | && *input_line_pointer != '\n') | |
2777 | ++input_line_pointer; | |
2778 | ||
2779 | saved_char = *input_line_pointer; | |
2780 | *input_line_pointer = 0; | |
2781 | ||
2782 | if (!*name) | |
2783 | as_bad (_("invalid syntax for .unreq directive")); | |
2784 | else | |
2785 | { | |
21d799b5 | 2786 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2787 | name); |
c19d1205 ZW |
2788 | |
2789 | if (!reg) | |
2790 | as_bad (_("unknown register alias '%s'"), name); | |
2791 | else if (reg->builtin) | |
a1727c1a | 2792 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2793 | name); |
2794 | else | |
2795 | { | |
d929913e NC |
2796 | char * p; |
2797 | char * nbuf; | |
2798 | ||
db0bc284 | 2799 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2800 | free ((char *) reg->name); |
477330fc RM |
2801 | if (reg->neon) |
2802 | free (reg->neon); | |
c19d1205 | 2803 | free (reg); |
d929913e NC |
2804 | |
2805 | /* Also locate the all upper case and all lower case versions. | |
2806 | Do not complain if we cannot find one or the other as it | |
2807 | was probably deleted above. */ | |
5f4273c7 | 2808 | |
d929913e NC |
2809 | nbuf = strdup (name); |
2810 | for (p = nbuf; *p; p++) | |
2811 | *p = TOUPPER (*p); | |
21d799b5 | 2812 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2813 | if (reg) |
2814 | { | |
db0bc284 | 2815 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2816 | free ((char *) reg->name); |
2817 | if (reg->neon) | |
2818 | free (reg->neon); | |
2819 | free (reg); | |
2820 | } | |
2821 | ||
2822 | for (p = nbuf; *p; p++) | |
2823 | *p = TOLOWER (*p); | |
21d799b5 | 2824 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2825 | if (reg) |
2826 | { | |
db0bc284 | 2827 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2828 | free ((char *) reg->name); |
2829 | if (reg->neon) | |
2830 | free (reg->neon); | |
2831 | free (reg); | |
2832 | } | |
2833 | ||
2834 | free (nbuf); | |
c19d1205 ZW |
2835 | } |
2836 | } | |
b99bd4ef | 2837 | |
c19d1205 | 2838 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2839 | demand_empty_rest_of_line (); |
2840 | } | |
2841 | ||
c19d1205 ZW |
2842 | /* Directives: Instruction set selection. */ |
2843 | ||
2844 | #ifdef OBJ_ELF | |
2845 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2846 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2847 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2848 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2849 | ||
cd000bff DJ |
2850 | /* Create a new mapping symbol for the transition to STATE. */ |
2851 | ||
2852 | static void | |
2853 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2854 | { |
a737bd4d | 2855 | symbolS * symbolP; |
c19d1205 ZW |
2856 | const char * symname; |
2857 | int type; | |
b99bd4ef | 2858 | |
c19d1205 | 2859 | switch (state) |
b99bd4ef | 2860 | { |
c19d1205 ZW |
2861 | case MAP_DATA: |
2862 | symname = "$d"; | |
2863 | type = BSF_NO_FLAGS; | |
2864 | break; | |
2865 | case MAP_ARM: | |
2866 | symname = "$a"; | |
2867 | type = BSF_NO_FLAGS; | |
2868 | break; | |
2869 | case MAP_THUMB: | |
2870 | symname = "$t"; | |
2871 | type = BSF_NO_FLAGS; | |
2872 | break; | |
c19d1205 ZW |
2873 | default: |
2874 | abort (); | |
2875 | } | |
2876 | ||
cd000bff | 2877 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2878 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2879 | ||
2880 | switch (state) | |
2881 | { | |
2882 | case MAP_ARM: | |
2883 | THUMB_SET_FUNC (symbolP, 0); | |
2884 | ARM_SET_THUMB (symbolP, 0); | |
2885 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2886 | break; | |
2887 | ||
2888 | case MAP_THUMB: | |
2889 | THUMB_SET_FUNC (symbolP, 1); | |
2890 | ARM_SET_THUMB (symbolP, 1); | |
2891 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2892 | break; | |
2893 | ||
2894 | case MAP_DATA: | |
2895 | default: | |
cd000bff DJ |
2896 | break; |
2897 | } | |
2898 | ||
2899 | /* Save the mapping symbols for future reference. Also check that | |
2900 | we do not place two mapping symbols at the same offset within a | |
2901 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2902 | check_mapping_symbols. |
2903 | ||
2904 | If .fill or other data filling directive generates zero sized data, | |
2905 | the mapping symbol for the following code will have the same value | |
2906 | as the one generated for the data filling directive. In this case, | |
2907 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2908 | if (value == 0) |
2909 | { | |
2de7820f JZ |
2910 | if (frag->tc_frag_data.first_map != NULL) |
2911 | { | |
2912 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2913 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2914 | } | |
cd000bff DJ |
2915 | frag->tc_frag_data.first_map = symbolP; |
2916 | } | |
2917 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2918 | { |
2919 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2920 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2921 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2922 | } | |
cd000bff DJ |
2923 | frag->tc_frag_data.last_map = symbolP; |
2924 | } | |
2925 | ||
2926 | /* We must sometimes convert a region marked as code to data during | |
2927 | code alignment, if an odd number of bytes have to be padded. The | |
2928 | code mapping symbol is pushed to an aligned address. */ | |
2929 | ||
2930 | static void | |
2931 | insert_data_mapping_symbol (enum mstate state, | |
2932 | valueT value, fragS *frag, offsetT bytes) | |
2933 | { | |
2934 | /* If there was already a mapping symbol, remove it. */ | |
2935 | if (frag->tc_frag_data.last_map != NULL | |
2936 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2937 | { | |
2938 | symbolS *symp = frag->tc_frag_data.last_map; | |
2939 | ||
2940 | if (value == 0) | |
2941 | { | |
2942 | know (frag->tc_frag_data.first_map == symp); | |
2943 | frag->tc_frag_data.first_map = NULL; | |
2944 | } | |
2945 | frag->tc_frag_data.last_map = NULL; | |
2946 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2947 | } |
cd000bff DJ |
2948 | |
2949 | make_mapping_symbol (MAP_DATA, value, frag); | |
2950 | make_mapping_symbol (state, value + bytes, frag); | |
2951 | } | |
2952 | ||
2953 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2954 | ||
2955 | /* Set the mapping state to STATE. Only call this when about to | |
2956 | emit some STATE bytes to the file. */ | |
2957 | ||
4e9aaefb | 2958 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
cd000bff DJ |
2959 | void |
2960 | mapping_state (enum mstate state) | |
2961 | { | |
940b5ce0 DJ |
2962 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2963 | ||
cd000bff DJ |
2964 | if (mapstate == state) |
2965 | /* The mapping symbol has already been emitted. | |
2966 | There is nothing else to do. */ | |
2967 | return; | |
49c62a33 NC |
2968 | |
2969 | if (state == MAP_ARM || state == MAP_THUMB) | |
2970 | /* PR gas/12931 | |
2971 | All ARM instructions require 4-byte alignment. | |
2972 | (Almost) all Thumb instructions require 2-byte alignment. | |
2973 | ||
2974 | When emitting instructions into any section, mark the section | |
2975 | appropriately. | |
2976 | ||
2977 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2978 | but themselves require 2-byte alignment; this applies to some | |
33eaf5de | 2979 | PC- relative forms. However, these cases will involve implicit |
49c62a33 NC |
2980 | literal pool generation or an explicit .align >=2, both of |
2981 | which will cause the section to me marked with sufficient | |
2982 | alignment. Thus, we don't handle those cases here. */ | |
2983 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2984 | ||
2985 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
4e9aaefb | 2986 | /* This case will be evaluated later. */ |
cd000bff | 2987 | return; |
cd000bff DJ |
2988 | |
2989 | mapping_state_2 (state, 0); | |
cd000bff DJ |
2990 | } |
2991 | ||
2992 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2993 | allocated. Put the mapping symbol that far back. */ | |
2994 | ||
2995 | static void | |
2996 | mapping_state_2 (enum mstate state, int max_chars) | |
2997 | { | |
940b5ce0 DJ |
2998 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2999 | ||
3000 | if (!SEG_NORMAL (now_seg)) | |
3001 | return; | |
3002 | ||
cd000bff DJ |
3003 | if (mapstate == state) |
3004 | /* The mapping symbol has already been emitted. | |
3005 | There is nothing else to do. */ | |
3006 | return; | |
3007 | ||
4e9aaefb SA |
3008 | if (TRANSITION (MAP_UNDEFINED, MAP_ARM) |
3009 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
3010 | { | |
3011 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
3012 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
3013 | ||
3014 | if (add_symbol) | |
3015 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
3016 | } | |
3017 | ||
cd000bff DJ |
3018 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
3019 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 | 3020 | } |
4e9aaefb | 3021 | #undef TRANSITION |
c19d1205 | 3022 | #else |
d3106081 NS |
3023 | #define mapping_state(x) ((void)0) |
3024 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
3025 | #endif |
3026 | ||
3027 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
3028 | ||
4343666d | 3029 | #ifdef OBJ_COFF |
c19d1205 ZW |
3030 | static symbolS * |
3031 | find_real_start (symbolS * symbolP) | |
3032 | { | |
3033 | char * real_start; | |
3034 | const char * name = S_GET_NAME (symbolP); | |
3035 | symbolS * new_target; | |
3036 | ||
3037 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
3038 | #define STUB_NAME ".real_start_of" | |
3039 | ||
3040 | if (name == NULL) | |
3041 | abort (); | |
3042 | ||
37f6032b ZW |
3043 | /* The compiler may generate BL instructions to local labels because |
3044 | it needs to perform a branch to a far away location. These labels | |
3045 | do not have a corresponding ".real_start_of" label. We check | |
3046 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
3047 | the ".real_start_of" convention for nonlocal branches. */ | |
3048 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
3049 | return symbolP; |
3050 | ||
e1fa0163 | 3051 | real_start = concat (STUB_NAME, name, NULL); |
c19d1205 | 3052 | new_target = symbol_find (real_start); |
e1fa0163 | 3053 | free (real_start); |
c19d1205 ZW |
3054 | |
3055 | if (new_target == NULL) | |
3056 | { | |
bd3ba5d1 | 3057 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
3058 | new_target = symbolP; |
3059 | } | |
3060 | ||
c19d1205 ZW |
3061 | return new_target; |
3062 | } | |
4343666d | 3063 | #endif |
c19d1205 ZW |
3064 | |
3065 | static void | |
3066 | opcode_select (int width) | |
3067 | { | |
3068 | switch (width) | |
3069 | { | |
3070 | case 16: | |
3071 | if (! thumb_mode) | |
3072 | { | |
e74cfd16 | 3073 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
3074 | as_bad (_("selected processor does not support THUMB opcodes")); |
3075 | ||
3076 | thumb_mode = 1; | |
3077 | /* No need to force the alignment, since we will have been | |
3078 | coming from ARM mode, which is word-aligned. */ | |
3079 | record_alignment (now_seg, 1); | |
3080 | } | |
c19d1205 ZW |
3081 | break; |
3082 | ||
3083 | case 32: | |
3084 | if (thumb_mode) | |
3085 | { | |
e74cfd16 | 3086 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
3087 | as_bad (_("selected processor does not support ARM opcodes")); |
3088 | ||
3089 | thumb_mode = 0; | |
3090 | ||
3091 | if (!need_pass_2) | |
3092 | frag_align (2, 0, 0); | |
3093 | ||
3094 | record_alignment (now_seg, 1); | |
3095 | } | |
c19d1205 ZW |
3096 | break; |
3097 | ||
3098 | default: | |
3099 | as_bad (_("invalid instruction size selected (%d)"), width); | |
3100 | } | |
3101 | } | |
3102 | ||
3103 | static void | |
3104 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
3105 | { | |
3106 | opcode_select (32); | |
3107 | demand_empty_rest_of_line (); | |
3108 | } | |
3109 | ||
3110 | static void | |
3111 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
3112 | { | |
3113 | opcode_select (16); | |
3114 | demand_empty_rest_of_line (); | |
3115 | } | |
3116 | ||
3117 | static void | |
3118 | s_code (int unused ATTRIBUTE_UNUSED) | |
3119 | { | |
3120 | int temp; | |
3121 | ||
3122 | temp = get_absolute_expression (); | |
3123 | switch (temp) | |
3124 | { | |
3125 | case 16: | |
3126 | case 32: | |
3127 | opcode_select (temp); | |
3128 | break; | |
3129 | ||
3130 | default: | |
3131 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
3132 | } | |
3133 | } | |
3134 | ||
3135 | static void | |
3136 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
3137 | { | |
3138 | /* If we are not already in thumb mode go into it, EVEN if | |
3139 | the target processor does not support thumb instructions. | |
3140 | This is used by gcc/config/arm/lib1funcs.asm for example | |
3141 | to compile interworking support functions even if the | |
3142 | target processor should not support interworking. */ | |
3143 | if (! thumb_mode) | |
3144 | { | |
3145 | thumb_mode = 2; | |
3146 | record_alignment (now_seg, 1); | |
3147 | } | |
3148 | ||
3149 | demand_empty_rest_of_line (); | |
3150 | } | |
3151 | ||
3152 | static void | |
3153 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
3154 | { | |
3155 | s_thumb (0); | |
3156 | ||
3157 | /* The following label is the name/address of the start of a Thumb function. | |
3158 | We need to know this for the interworking support. */ | |
3159 | label_is_thumb_function_name = TRUE; | |
3160 | } | |
3161 | ||
3162 | /* Perform a .set directive, but also mark the alias as | |
3163 | being a thumb function. */ | |
3164 | ||
3165 | static void | |
3166 | s_thumb_set (int equiv) | |
3167 | { | |
3168 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
3169 | We cannot just call that code as we need to get at the symbol that | |
3170 | is created. */ | |
3171 | char * name; | |
3172 | char delim; | |
3173 | char * end_name; | |
3174 | symbolS * symbolP; | |
3175 | ||
3176 | /* Especial apologies for the random logic: | |
3177 | This just grew, and could be parsed much more simply! | |
3178 | Dean - in haste. */ | |
d02603dc | 3179 | delim = get_symbol_name (& name); |
c19d1205 | 3180 | end_name = input_line_pointer; |
d02603dc | 3181 | (void) restore_line_pointer (delim); |
c19d1205 ZW |
3182 | |
3183 | if (*input_line_pointer != ',') | |
3184 | { | |
3185 | *end_name = 0; | |
3186 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
3187 | *end_name = delim; |
3188 | ignore_rest_of_line (); | |
3189 | return; | |
3190 | } | |
3191 | ||
3192 | input_line_pointer++; | |
3193 | *end_name = 0; | |
3194 | ||
3195 | if (name[0] == '.' && name[1] == '\0') | |
3196 | { | |
3197 | /* XXX - this should not happen to .thumb_set. */ | |
3198 | abort (); | |
3199 | } | |
3200 | ||
3201 | if ((symbolP = symbol_find (name)) == NULL | |
3202 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
3203 | { | |
3204 | #ifndef NO_LISTING | |
3205 | /* When doing symbol listings, play games with dummy fragments living | |
3206 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 3207 | for this symbol. */ |
b99bd4ef NC |
3208 | if (listing & LISTING_SYMBOLS) |
3209 | { | |
3210 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 3211 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
3212 | |
3213 | memset (dummy_frag, 0, sizeof (fragS)); | |
3214 | dummy_frag->fr_type = rs_fill; | |
3215 | dummy_frag->line = listing_tail; | |
3216 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
3217 | dummy_frag->fr_symbol = symbolP; | |
3218 | } | |
3219 | else | |
3220 | #endif | |
3221 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
3222 | ||
3223 | #ifdef OBJ_COFF | |
3224 | /* "set" symbols are local unless otherwise specified. */ | |
3225 | SF_SET_LOCAL (symbolP); | |
3226 | #endif /* OBJ_COFF */ | |
3227 | } /* Make a new symbol. */ | |
3228 | ||
3229 | symbol_table_insert (symbolP); | |
3230 | ||
3231 | * end_name = delim; | |
3232 | ||
3233 | if (equiv | |
3234 | && S_IS_DEFINED (symbolP) | |
3235 | && S_GET_SEGMENT (symbolP) != reg_section) | |
3236 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
3237 | ||
3238 | pseudo_set (symbolP); | |
3239 | ||
3240 | demand_empty_rest_of_line (); | |
3241 | ||
c19d1205 | 3242 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
3243 | |
3244 | THUMB_SET_FUNC (symbolP, 1); | |
3245 | ARM_SET_THUMB (symbolP, 1); | |
3246 | #if defined OBJ_ELF || defined OBJ_COFF | |
3247 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
3248 | #endif | |
3249 | } | |
3250 | ||
c19d1205 | 3251 | /* Directives: Mode selection. */ |
b99bd4ef | 3252 | |
c19d1205 ZW |
3253 | /* .syntax [unified|divided] - choose the new unified syntax |
3254 | (same for Arm and Thumb encoding, modulo slight differences in what | |
3255 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 3256 | static void |
c19d1205 | 3257 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 3258 | { |
c19d1205 ZW |
3259 | char *name, delim; |
3260 | ||
d02603dc | 3261 | delim = get_symbol_name (& name); |
c19d1205 ZW |
3262 | |
3263 | if (!strcasecmp (name, "unified")) | |
3264 | unified_syntax = TRUE; | |
3265 | else if (!strcasecmp (name, "divided")) | |
3266 | unified_syntax = FALSE; | |
3267 | else | |
3268 | { | |
3269 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
3270 | return; | |
3271 | } | |
d02603dc | 3272 | (void) restore_line_pointer (delim); |
b99bd4ef NC |
3273 | demand_empty_rest_of_line (); |
3274 | } | |
3275 | ||
c19d1205 ZW |
3276 | /* Directives: sectioning and alignment. */ |
3277 | ||
c19d1205 ZW |
3278 | static void |
3279 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 3280 | { |
c19d1205 ZW |
3281 | /* We don't support putting frags in the BSS segment, we fake it by |
3282 | marking in_bss, then looking at s_skip for clues. */ | |
3283 | subseg_set (bss_section, 0); | |
3284 | demand_empty_rest_of_line (); | |
cd000bff DJ |
3285 | |
3286 | #ifdef md_elf_section_change_hook | |
3287 | md_elf_section_change_hook (); | |
3288 | #endif | |
c19d1205 | 3289 | } |
b99bd4ef | 3290 | |
c19d1205 ZW |
3291 | static void |
3292 | s_even (int ignore ATTRIBUTE_UNUSED) | |
3293 | { | |
3294 | /* Never make frag if expect extra pass. */ | |
3295 | if (!need_pass_2) | |
3296 | frag_align (1, 0, 0); | |
b99bd4ef | 3297 | |
c19d1205 | 3298 | record_alignment (now_seg, 1); |
b99bd4ef | 3299 | |
c19d1205 | 3300 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3301 | } |
3302 | ||
2e6976a8 DG |
3303 | /* Directives: CodeComposer Studio. */ |
3304 | ||
3305 | /* .ref (for CodeComposer Studio syntax only). */ | |
3306 | static void | |
3307 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3308 | { | |
3309 | if (codecomposer_syntax) | |
3310 | ignore_rest_of_line (); | |
3311 | else | |
3312 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3313 | } | |
3314 | ||
3315 | /* If name is not NULL, then it is used for marking the beginning of a | |
2b0f3761 | 3316 | function, whereas if it is NULL then it means the function end. */ |
2e6976a8 DG |
3317 | static void |
3318 | asmfunc_debug (const char * name) | |
3319 | { | |
3320 | static const char * last_name = NULL; | |
3321 | ||
3322 | if (name != NULL) | |
3323 | { | |
3324 | gas_assert (last_name == NULL); | |
3325 | last_name = name; | |
3326 | ||
3327 | if (debug_type == DEBUG_STABS) | |
3328 | stabs_generate_asm_func (name, name); | |
3329 | } | |
3330 | else | |
3331 | { | |
3332 | gas_assert (last_name != NULL); | |
3333 | ||
3334 | if (debug_type == DEBUG_STABS) | |
3335 | stabs_generate_asm_endfunc (last_name, last_name); | |
3336 | ||
3337 | last_name = NULL; | |
3338 | } | |
3339 | } | |
3340 | ||
3341 | static void | |
3342 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3343 | { | |
3344 | if (codecomposer_syntax) | |
3345 | { | |
3346 | switch (asmfunc_state) | |
3347 | { | |
3348 | case OUTSIDE_ASMFUNC: | |
3349 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3350 | break; | |
3351 | ||
3352 | case WAITING_ASMFUNC_NAME: | |
3353 | as_bad (_(".asmfunc repeated.")); | |
3354 | break; | |
3355 | ||
3356 | case WAITING_ENDASMFUNC: | |
3357 | as_bad (_(".asmfunc without function.")); | |
3358 | break; | |
3359 | } | |
3360 | demand_empty_rest_of_line (); | |
3361 | } | |
3362 | else | |
3363 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3364 | } | |
3365 | ||
3366 | static void | |
3367 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3368 | { | |
3369 | if (codecomposer_syntax) | |
3370 | { | |
3371 | switch (asmfunc_state) | |
3372 | { | |
3373 | case OUTSIDE_ASMFUNC: | |
3374 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3375 | break; | |
3376 | ||
3377 | case WAITING_ASMFUNC_NAME: | |
3378 | as_bad (_(".endasmfunc without function.")); | |
3379 | break; | |
3380 | ||
3381 | case WAITING_ENDASMFUNC: | |
3382 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3383 | asmfunc_debug (NULL); | |
3384 | break; | |
3385 | } | |
3386 | demand_empty_rest_of_line (); | |
3387 | } | |
3388 | else | |
3389 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3390 | } | |
3391 | ||
3392 | static void | |
3393 | s_ccs_def (int name) | |
3394 | { | |
3395 | if (codecomposer_syntax) | |
3396 | s_globl (name); | |
3397 | else | |
3398 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3399 | } | |
3400 | ||
c19d1205 | 3401 | /* Directives: Literal pools. */ |
a737bd4d | 3402 | |
c19d1205 ZW |
3403 | static literal_pool * |
3404 | find_literal_pool (void) | |
a737bd4d | 3405 | { |
c19d1205 | 3406 | literal_pool * pool; |
a737bd4d | 3407 | |
c19d1205 | 3408 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3409 | { |
c19d1205 ZW |
3410 | if (pool->section == now_seg |
3411 | && pool->sub_section == now_subseg) | |
3412 | break; | |
a737bd4d NC |
3413 | } |
3414 | ||
c19d1205 | 3415 | return pool; |
a737bd4d NC |
3416 | } |
3417 | ||
c19d1205 ZW |
3418 | static literal_pool * |
3419 | find_or_make_literal_pool (void) | |
a737bd4d | 3420 | { |
c19d1205 ZW |
3421 | /* Next literal pool ID number. */ |
3422 | static unsigned int latest_pool_num = 1; | |
3423 | literal_pool * pool; | |
a737bd4d | 3424 | |
c19d1205 | 3425 | pool = find_literal_pool (); |
a737bd4d | 3426 | |
c19d1205 | 3427 | if (pool == NULL) |
a737bd4d | 3428 | { |
c19d1205 | 3429 | /* Create a new pool. */ |
325801bd | 3430 | pool = XNEW (literal_pool); |
c19d1205 ZW |
3431 | if (! pool) |
3432 | return NULL; | |
a737bd4d | 3433 | |
c19d1205 ZW |
3434 | pool->next_free_entry = 0; |
3435 | pool->section = now_seg; | |
3436 | pool->sub_section = now_subseg; | |
3437 | pool->next = list_of_pools; | |
3438 | pool->symbol = NULL; | |
8335d6aa | 3439 | pool->alignment = 2; |
c19d1205 ZW |
3440 | |
3441 | /* Add it to the list. */ | |
3442 | list_of_pools = pool; | |
a737bd4d | 3443 | } |
a737bd4d | 3444 | |
c19d1205 ZW |
3445 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3446 | if (pool->symbol == NULL) | |
a737bd4d | 3447 | { |
c19d1205 ZW |
3448 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3449 | (valueT) 0, &zero_address_frag); | |
3450 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3451 | } |
3452 | ||
c19d1205 ZW |
3453 | /* Done. */ |
3454 | return pool; | |
a737bd4d NC |
3455 | } |
3456 | ||
c19d1205 | 3457 | /* Add the literal in the global 'inst' |
5f4273c7 | 3458 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3459 | |
3460 | static int | |
8335d6aa | 3461 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3462 | { |
8335d6aa JW |
3463 | #define PADDING_SLOT 0x1 |
3464 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3465 | literal_pool * pool; |
8335d6aa JW |
3466 | unsigned int entry, pool_size = 0; |
3467 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3468 | unsigned imm1 = 0; |
8335d6aa JW |
3469 | unsigned imm2 = 0; |
3470 | ||
3471 | if (nbytes == 8) | |
3472 | { | |
3473 | imm1 = inst.operands[1].imm; | |
3474 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
e2b0ab59 | 3475 | : inst.relocs[0].exp.X_unsigned ? 0 |
2569ceb0 | 3476 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3477 | if (target_big_endian) |
3478 | { | |
3479 | imm1 = imm2; | |
3480 | imm2 = inst.operands[1].imm; | |
3481 | } | |
3482 | } | |
b99bd4ef | 3483 | |
c19d1205 ZW |
3484 | pool = find_or_make_literal_pool (); |
3485 | ||
3486 | /* Check if this literal value is already in the pool. */ | |
3487 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3488 | { |
8335d6aa JW |
3489 | if (nbytes == 4) |
3490 | { | |
e2b0ab59 AV |
3491 | if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op) |
3492 | && (inst.relocs[0].exp.X_op == O_constant) | |
8335d6aa | 3493 | && (pool->literals[entry].X_add_number |
e2b0ab59 | 3494 | == inst.relocs[0].exp.X_add_number) |
8335d6aa JW |
3495 | && (pool->literals[entry].X_md == nbytes) |
3496 | && (pool->literals[entry].X_unsigned | |
e2b0ab59 | 3497 | == inst.relocs[0].exp.X_unsigned)) |
8335d6aa JW |
3498 | break; |
3499 | ||
e2b0ab59 AV |
3500 | if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op) |
3501 | && (inst.relocs[0].exp.X_op == O_symbol) | |
8335d6aa | 3502 | && (pool->literals[entry].X_add_number |
e2b0ab59 | 3503 | == inst.relocs[0].exp.X_add_number) |
8335d6aa | 3504 | && (pool->literals[entry].X_add_symbol |
e2b0ab59 | 3505 | == inst.relocs[0].exp.X_add_symbol) |
8335d6aa | 3506 | && (pool->literals[entry].X_op_symbol |
e2b0ab59 | 3507 | == inst.relocs[0].exp.X_op_symbol) |
8335d6aa JW |
3508 | && (pool->literals[entry].X_md == nbytes)) |
3509 | break; | |
3510 | } | |
3511 | else if ((nbytes == 8) | |
3512 | && !(pool_size & 0x7) | |
3513 | && ((entry + 1) != pool->next_free_entry) | |
3514 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3515 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa | 3516 | && (pool->literals[entry].X_unsigned |
e2b0ab59 | 3517 | == inst.relocs[0].exp.X_unsigned) |
8335d6aa | 3518 | && (pool->literals[entry + 1].X_op == O_constant) |
19f2f6a9 | 3519 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa | 3520 | && (pool->literals[entry + 1].X_unsigned |
e2b0ab59 | 3521 | == inst.relocs[0].exp.X_unsigned)) |
c19d1205 ZW |
3522 | break; |
3523 | ||
8335d6aa JW |
3524 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3525 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3526 | break; |
8335d6aa JW |
3527 | |
3528 | pool_size += 4; | |
b99bd4ef NC |
3529 | } |
3530 | ||
c19d1205 ZW |
3531 | /* Do we need to create a new entry? */ |
3532 | if (entry == pool->next_free_entry) | |
3533 | { | |
3534 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3535 | { | |
3536 | inst.error = _("literal pool overflow"); | |
3537 | return FAIL; | |
3538 | } | |
3539 | ||
8335d6aa JW |
3540 | if (nbytes == 8) |
3541 | { | |
3542 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3543 | and split it into two 4-byte entries, because on 32-bit | |
3544 | host, 8-byte constants are treated as big num, thus | |
3545 | saved in "generic_bignum" which will be overwritten | |
3546 | by later assignments. | |
3547 | ||
3548 | We also need to make sure there is enough space for | |
3549 | the split. | |
3550 | ||
3551 | We also check to make sure the literal operand is a | |
3552 | constant number. */ | |
e2b0ab59 AV |
3553 | if (!(inst.relocs[0].exp.X_op == O_constant |
3554 | || inst.relocs[0].exp.X_op == O_big)) | |
8335d6aa JW |
3555 | { |
3556 | inst.error = _("invalid type for literal pool"); | |
3557 | return FAIL; | |
3558 | } | |
3559 | else if (pool_size & 0x7) | |
3560 | { | |
3561 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3562 | { | |
3563 | inst.error = _("literal pool overflow"); | |
3564 | return FAIL; | |
3565 | } | |
3566 | ||
e2b0ab59 | 3567 | pool->literals[entry] = inst.relocs[0].exp; |
a6684f0d | 3568 | pool->literals[entry].X_op = O_constant; |
8335d6aa JW |
3569 | pool->literals[entry].X_add_number = 0; |
3570 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3571 | pool->next_free_entry += 1; | |
3572 | pool_size += 4; | |
3573 | } | |
3574 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3575 | { | |
3576 | inst.error = _("literal pool overflow"); | |
3577 | return FAIL; | |
3578 | } | |
3579 | ||
e2b0ab59 | 3580 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3581 | pool->literals[entry].X_op = O_constant; |
3582 | pool->literals[entry].X_add_number = imm1; | |
e2b0ab59 | 3583 | pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned; |
8335d6aa | 3584 | pool->literals[entry++].X_md = 4; |
e2b0ab59 | 3585 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3586 | pool->literals[entry].X_op = O_constant; |
3587 | pool->literals[entry].X_add_number = imm2; | |
e2b0ab59 | 3588 | pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned; |
8335d6aa JW |
3589 | pool->literals[entry].X_md = 4; |
3590 | pool->alignment = 3; | |
3591 | pool->next_free_entry += 1; | |
3592 | } | |
3593 | else | |
3594 | { | |
e2b0ab59 | 3595 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3596 | pool->literals[entry].X_md = 4; |
3597 | } | |
3598 | ||
a8040cf2 NC |
3599 | #ifdef OBJ_ELF |
3600 | /* PR ld/12974: Record the location of the first source line to reference | |
3601 | this entry in the literal pool. If it turns out during linking that the | |
3602 | symbol does not exist we will be able to give an accurate line number for | |
3603 | the (first use of the) missing reference. */ | |
3604 | if (debug_type == DEBUG_DWARF2) | |
3605 | dwarf2_where (pool->locs + entry); | |
3606 | #endif | |
c19d1205 ZW |
3607 | pool->next_free_entry += 1; |
3608 | } | |
8335d6aa JW |
3609 | else if (padding_slot_p) |
3610 | { | |
e2b0ab59 | 3611 | pool->literals[entry] = inst.relocs[0].exp; |
8335d6aa JW |
3612 | pool->literals[entry].X_md = nbytes; |
3613 | } | |
b99bd4ef | 3614 | |
e2b0ab59 AV |
3615 | inst.relocs[0].exp.X_op = O_symbol; |
3616 | inst.relocs[0].exp.X_add_number = pool_size; | |
3617 | inst.relocs[0].exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3618 | |
c19d1205 | 3619 | return SUCCESS; |
b99bd4ef NC |
3620 | } |
3621 | ||
2e6976a8 | 3622 | bfd_boolean |
2e57ce7b | 3623 | tc_start_label_without_colon (void) |
2e6976a8 DG |
3624 | { |
3625 | bfd_boolean ret = TRUE; | |
3626 | ||
3627 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3628 | { | |
2e57ce7b | 3629 | const char *label = input_line_pointer; |
2e6976a8 DG |
3630 | |
3631 | while (!is_end_of_line[(int) label[-1]]) | |
3632 | --label; | |
3633 | ||
3634 | if (*label == '.') | |
3635 | { | |
3636 | as_bad (_("Invalid label '%s'"), label); | |
3637 | ret = FALSE; | |
3638 | } | |
3639 | ||
3640 | asmfunc_debug (label); | |
3641 | ||
3642 | asmfunc_state = WAITING_ENDASMFUNC; | |
3643 | } | |
3644 | ||
3645 | return ret; | |
3646 | } | |
3647 | ||
c19d1205 | 3648 | /* Can't use symbol_new here, so have to create a symbol and then at |
33eaf5de | 3649 | a later date assign it a value. That's what these functions do. */ |
e16bb312 | 3650 | |
c19d1205 ZW |
3651 | static void |
3652 | symbol_locate (symbolS * symbolP, | |
3653 | const char * name, /* It is copied, the caller can modify. */ | |
3654 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3655 | valueT valu, /* Symbol value. */ | |
3656 | fragS * frag) /* Associated fragment. */ | |
3657 | { | |
e57e6ddc | 3658 | size_t name_length; |
c19d1205 | 3659 | char * preserved_copy_of_name; |
e16bb312 | 3660 | |
c19d1205 ZW |
3661 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3662 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3663 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3664 | |
c19d1205 ZW |
3665 | #ifdef tc_canonicalize_symbol_name |
3666 | preserved_copy_of_name = | |
3667 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3668 | #endif | |
b99bd4ef | 3669 | |
c19d1205 | 3670 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3671 | |
c19d1205 ZW |
3672 | S_SET_SEGMENT (symbolP, segment); |
3673 | S_SET_VALUE (symbolP, valu); | |
3674 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3675 | |
c19d1205 | 3676 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3677 | |
c19d1205 ZW |
3678 | /* Link to end of symbol chain. */ |
3679 | { | |
3680 | extern int symbol_table_frozen; | |
b99bd4ef | 3681 | |
c19d1205 ZW |
3682 | if (symbol_table_frozen) |
3683 | abort (); | |
3684 | } | |
b99bd4ef | 3685 | |
c19d1205 | 3686 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3687 | |
c19d1205 | 3688 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3689 | |
c19d1205 ZW |
3690 | #ifdef tc_symbol_new_hook |
3691 | tc_symbol_new_hook (symbolP); | |
3692 | #endif | |
3693 | ||
3694 | #ifdef DEBUG_SYMS | |
3695 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3696 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3697 | } |
3698 | ||
c19d1205 ZW |
3699 | static void |
3700 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3701 | { |
c19d1205 ZW |
3702 | unsigned int entry; |
3703 | literal_pool * pool; | |
3704 | char sym_name[20]; | |
b99bd4ef | 3705 | |
c19d1205 ZW |
3706 | pool = find_literal_pool (); |
3707 | if (pool == NULL | |
3708 | || pool->symbol == NULL | |
3709 | || pool->next_free_entry == 0) | |
3710 | return; | |
b99bd4ef | 3711 | |
c19d1205 ZW |
3712 | /* Align pool as you have word accesses. |
3713 | Only make a frag if we have to. */ | |
3714 | if (!need_pass_2) | |
8335d6aa | 3715 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3716 | |
c19d1205 | 3717 | record_alignment (now_seg, 2); |
b99bd4ef | 3718 | |
aaca88ef | 3719 | #ifdef OBJ_ELF |
47fc6e36 WN |
3720 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3721 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3722 | #endif |
c19d1205 | 3723 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3724 | |
c19d1205 ZW |
3725 | symbol_locate (pool->symbol, sym_name, now_seg, |
3726 | (valueT) frag_now_fix (), frag_now); | |
3727 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3728 | |
c19d1205 | 3729 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3730 | |
c19d1205 ZW |
3731 | #if defined OBJ_COFF || defined OBJ_ELF |
3732 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3733 | #endif | |
6c43fab6 | 3734 | |
c19d1205 | 3735 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3736 | { |
3737 | #ifdef OBJ_ELF | |
3738 | if (debug_type == DEBUG_DWARF2) | |
3739 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3740 | #endif | |
3741 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3742 | emit_expr (&(pool->literals[entry]), |
3743 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3744 | } |
b99bd4ef | 3745 | |
c19d1205 ZW |
3746 | /* Mark the pool as empty. */ |
3747 | pool->next_free_entry = 0; | |
3748 | pool->symbol = NULL; | |
b99bd4ef NC |
3749 | } |
3750 | ||
c19d1205 ZW |
3751 | #ifdef OBJ_ELF |
3752 | /* Forward declarations for functions below, in the MD interface | |
3753 | section. */ | |
3754 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3755 | static valueT create_unwind_entry (int); | |
3756 | static void start_unwind_section (const segT, int); | |
3757 | static void add_unwind_opcode (valueT, int); | |
3758 | static void flush_pending_unwind (void); | |
b99bd4ef | 3759 | |
c19d1205 | 3760 | /* Directives: Data. */ |
b99bd4ef | 3761 | |
c19d1205 ZW |
3762 | static void |
3763 | s_arm_elf_cons (int nbytes) | |
3764 | { | |
3765 | expressionS exp; | |
b99bd4ef | 3766 | |
c19d1205 ZW |
3767 | #ifdef md_flush_pending_output |
3768 | md_flush_pending_output (); | |
3769 | #endif | |
b99bd4ef | 3770 | |
c19d1205 | 3771 | if (is_it_end_of_statement ()) |
b99bd4ef | 3772 | { |
c19d1205 ZW |
3773 | demand_empty_rest_of_line (); |
3774 | return; | |
b99bd4ef NC |
3775 | } |
3776 | ||
c19d1205 ZW |
3777 | #ifdef md_cons_align |
3778 | md_cons_align (nbytes); | |
3779 | #endif | |
b99bd4ef | 3780 | |
c19d1205 ZW |
3781 | mapping_state (MAP_DATA); |
3782 | do | |
b99bd4ef | 3783 | { |
c19d1205 ZW |
3784 | int reloc; |
3785 | char *base = input_line_pointer; | |
b99bd4ef | 3786 | |
c19d1205 | 3787 | expression (& exp); |
b99bd4ef | 3788 | |
c19d1205 ZW |
3789 | if (exp.X_op != O_symbol) |
3790 | emit_expr (&exp, (unsigned int) nbytes); | |
3791 | else | |
3792 | { | |
3793 | char *before_reloc = input_line_pointer; | |
3794 | reloc = parse_reloc (&input_line_pointer); | |
3795 | if (reloc == -1) | |
3796 | { | |
3797 | as_bad (_("unrecognized relocation suffix")); | |
3798 | ignore_rest_of_line (); | |
3799 | return; | |
3800 | } | |
3801 | else if (reloc == BFD_RELOC_UNUSED) | |
3802 | emit_expr (&exp, (unsigned int) nbytes); | |
3803 | else | |
3804 | { | |
21d799b5 | 3805 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3806 | bfd_reloc_type_lookup (stdoutput, |
3807 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3808 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3809 | |
2fc8bdac ZW |
3810 | if (reloc == BFD_RELOC_ARM_PLT32) |
3811 | { | |
3812 | as_bad (_("(plt) is only valid on branch targets")); | |
3813 | reloc = BFD_RELOC_UNUSED; | |
3814 | size = 0; | |
3815 | } | |
3816 | ||
c19d1205 | 3817 | if (size > nbytes) |
992a06ee AM |
3818 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
3819 | "%s relocations do not fit in %d bytes", | |
3820 | nbytes), | |
c19d1205 ZW |
3821 | howto->name, nbytes); |
3822 | else | |
3823 | { | |
3824 | /* We've parsed an expression stopping at O_symbol. | |
3825 | But there may be more expression left now that we | |
3826 | have parsed the relocation marker. Parse it again. | |
3827 | XXX Surely there is a cleaner way to do this. */ | |
3828 | char *p = input_line_pointer; | |
3829 | int offset; | |
325801bd | 3830 | char *save_buf = XNEWVEC (char, input_line_pointer - base); |
e1fa0163 | 3831 | |
c19d1205 ZW |
3832 | memcpy (save_buf, base, input_line_pointer - base); |
3833 | memmove (base + (input_line_pointer - before_reloc), | |
3834 | base, before_reloc - base); | |
3835 | ||
3836 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3837 | expression (&exp); | |
3838 | memcpy (base, save_buf, p - base); | |
3839 | ||
3840 | offset = nbytes - size; | |
4b1a927e AM |
3841 | p = frag_more (nbytes); |
3842 | memset (p, 0, nbytes); | |
c19d1205 | 3843 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3844 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
e1fa0163 | 3845 | free (save_buf); |
c19d1205 ZW |
3846 | } |
3847 | } | |
3848 | } | |
b99bd4ef | 3849 | } |
c19d1205 | 3850 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3851 | |
c19d1205 ZW |
3852 | /* Put terminator back into stream. */ |
3853 | input_line_pointer --; | |
3854 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3855 | } |
3856 | ||
c921be7d NC |
3857 | /* Emit an expression containing a 32-bit thumb instruction. |
3858 | Implementation based on put_thumb32_insn. */ | |
3859 | ||
3860 | static void | |
3861 | emit_thumb32_expr (expressionS * exp) | |
3862 | { | |
3863 | expressionS exp_high = *exp; | |
3864 | ||
3865 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3866 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3867 | exp->X_add_number &= 0xffff; | |
3868 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3869 | } | |
3870 | ||
3871 | /* Guess the instruction size based on the opcode. */ | |
3872 | ||
3873 | static int | |
3874 | thumb_insn_size (int opcode) | |
3875 | { | |
3876 | if ((unsigned int) opcode < 0xe800u) | |
3877 | return 2; | |
3878 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3879 | return 4; | |
3880 | else | |
3881 | return 0; | |
3882 | } | |
3883 | ||
3884 | static bfd_boolean | |
3885 | emit_insn (expressionS *exp, int nbytes) | |
3886 | { | |
3887 | int size = 0; | |
3888 | ||
3889 | if (exp->X_op == O_constant) | |
3890 | { | |
3891 | size = nbytes; | |
3892 | ||
3893 | if (size == 0) | |
3894 | size = thumb_insn_size (exp->X_add_number); | |
3895 | ||
3896 | if (size != 0) | |
3897 | { | |
3898 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3899 | { | |
3900 | as_bad (_(".inst.n operand too big. "\ | |
3901 | "Use .inst.w instead")); | |
3902 | size = 0; | |
3903 | } | |
3904 | else | |
3905 | { | |
5ee91343 AV |
3906 | if (now_pred.state == AUTOMATIC_PRED_BLOCK) |
3907 | set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0); | |
c921be7d | 3908 | else |
5ee91343 | 3909 | set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); |
c921be7d NC |
3910 | |
3911 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3912 | emit_thumb32_expr (exp); | |
3913 | else | |
3914 | emit_expr (exp, (unsigned int) size); | |
3915 | ||
3916 | it_fsm_post_encode (); | |
3917 | } | |
3918 | } | |
3919 | else | |
3920 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3921 | "Use .inst.n/.inst.w instead")); | |
3922 | } | |
3923 | else | |
3924 | as_bad (_("constant expression required")); | |
3925 | ||
3926 | return (size != 0); | |
3927 | } | |
3928 | ||
3929 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3930 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3931 | ||
3932 | static void | |
3933 | s_arm_elf_inst (int nbytes) | |
3934 | { | |
3935 | if (is_it_end_of_statement ()) | |
3936 | { | |
3937 | demand_empty_rest_of_line (); | |
3938 | return; | |
3939 | } | |
3940 | ||
3941 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3942 | but will ensure not to be in DATA state. */ | |
3943 | ||
3944 | if (thumb_mode) | |
3945 | mapping_state (MAP_THUMB); | |
3946 | else | |
3947 | { | |
3948 | if (nbytes != 0) | |
3949 | { | |
3950 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3951 | ignore_rest_of_line (); | |
3952 | return; | |
3953 | } | |
3954 | ||
3955 | nbytes = 4; | |
3956 | ||
3957 | mapping_state (MAP_ARM); | |
3958 | } | |
3959 | ||
3960 | do | |
3961 | { | |
3962 | expressionS exp; | |
3963 | ||
3964 | expression (& exp); | |
3965 | ||
3966 | if (! emit_insn (& exp, nbytes)) | |
3967 | { | |
3968 | ignore_rest_of_line (); | |
3969 | return; | |
3970 | } | |
3971 | } | |
3972 | while (*input_line_pointer++ == ','); | |
3973 | ||
3974 | /* Put terminator back into stream. */ | |
3975 | input_line_pointer --; | |
3976 | demand_empty_rest_of_line (); | |
3977 | } | |
b99bd4ef | 3978 | |
c19d1205 | 3979 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3980 | |
c19d1205 ZW |
3981 | static void |
3982 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3983 | { | |
3984 | expressionS exp; | |
3985 | char *p; | |
3986 | valueT highbit; | |
b99bd4ef | 3987 | |
c19d1205 ZW |
3988 | highbit = 0; |
3989 | if (*input_line_pointer == '1') | |
3990 | highbit = 0x80000000; | |
3991 | else if (*input_line_pointer != '0') | |
3992 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3993 | |
c19d1205 ZW |
3994 | input_line_pointer++; |
3995 | if (*input_line_pointer != ',') | |
3996 | as_bad (_("missing comma")); | |
3997 | input_line_pointer++; | |
b99bd4ef | 3998 | |
c19d1205 ZW |
3999 | #ifdef md_flush_pending_output |
4000 | md_flush_pending_output (); | |
4001 | #endif | |
b99bd4ef | 4002 | |
c19d1205 ZW |
4003 | #ifdef md_cons_align |
4004 | md_cons_align (4); | |
4005 | #endif | |
b99bd4ef | 4006 | |
c19d1205 | 4007 | mapping_state (MAP_DATA); |
b99bd4ef | 4008 | |
c19d1205 | 4009 | expression (&exp); |
b99bd4ef | 4010 | |
c19d1205 ZW |
4011 | p = frag_more (4); |
4012 | md_number_to_chars (p, highbit, 4); | |
4013 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
4014 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 4015 | |
c19d1205 | 4016 | demand_empty_rest_of_line (); |
b99bd4ef NC |
4017 | } |
4018 | ||
c19d1205 | 4019 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 4020 | |
c19d1205 | 4021 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 4022 | |
c19d1205 ZW |
4023 | static void |
4024 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
4025 | { | |
4026 | demand_empty_rest_of_line (); | |
921e5f0a PB |
4027 | if (unwind.proc_start) |
4028 | { | |
c921be7d | 4029 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
4030 | return; |
4031 | } | |
4032 | ||
c19d1205 ZW |
4033 | /* Mark the start of the function. */ |
4034 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 4035 | |
c19d1205 ZW |
4036 | /* Reset the rest of the unwind info. */ |
4037 | unwind.opcode_count = 0; | |
4038 | unwind.table_entry = NULL; | |
4039 | unwind.personality_routine = NULL; | |
4040 | unwind.personality_index = -1; | |
4041 | unwind.frame_size = 0; | |
4042 | unwind.fp_offset = 0; | |
fdfde340 | 4043 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
4044 | unwind.fp_used = 0; |
4045 | unwind.sp_restored = 0; | |
4046 | } | |
b99bd4ef | 4047 | |
b99bd4ef | 4048 | |
c19d1205 ZW |
4049 | /* Parse a handlerdata directive. Creates the exception handling table entry |
4050 | for the function. */ | |
b99bd4ef | 4051 | |
c19d1205 ZW |
4052 | static void |
4053 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
4054 | { | |
4055 | demand_empty_rest_of_line (); | |
921e5f0a | 4056 | if (!unwind.proc_start) |
c921be7d | 4057 | as_bad (MISSING_FNSTART); |
921e5f0a | 4058 | |
c19d1205 | 4059 | if (unwind.table_entry) |
6decc662 | 4060 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 4061 | |
c19d1205 ZW |
4062 | create_unwind_entry (1); |
4063 | } | |
a737bd4d | 4064 | |
c19d1205 | 4065 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 4066 | |
c19d1205 ZW |
4067 | static void |
4068 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
4069 | { | |
4070 | long where; | |
4071 | char *ptr; | |
4072 | valueT val; | |
940b5ce0 | 4073 | unsigned int marked_pr_dependency; |
f02232aa | 4074 | |
c19d1205 | 4075 | demand_empty_rest_of_line (); |
f02232aa | 4076 | |
921e5f0a PB |
4077 | if (!unwind.proc_start) |
4078 | { | |
c921be7d | 4079 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
4080 | return; |
4081 | } | |
4082 | ||
c19d1205 ZW |
4083 | /* Add eh table entry. */ |
4084 | if (unwind.table_entry == NULL) | |
4085 | val = create_unwind_entry (0); | |
4086 | else | |
4087 | val = 0; | |
f02232aa | 4088 | |
c19d1205 ZW |
4089 | /* Add index table entry. This is two words. */ |
4090 | start_unwind_section (unwind.saved_seg, 1); | |
4091 | frag_align (2, 0, 0); | |
4092 | record_alignment (now_seg, 2); | |
b99bd4ef | 4093 | |
c19d1205 | 4094 | ptr = frag_more (8); |
5011093d | 4095 | memset (ptr, 0, 8); |
c19d1205 | 4096 | where = frag_now_fix () - 8; |
f02232aa | 4097 | |
c19d1205 ZW |
4098 | /* Self relative offset of the function start. */ |
4099 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
4100 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 4101 | |
c19d1205 ZW |
4102 | /* Indicate dependency on EHABI-defined personality routines to the |
4103 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
4104 | marked_pr_dependency |
4105 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
4106 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
4107 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
4108 | { | |
5f4273c7 NC |
4109 | static const char *const name[] = |
4110 | { | |
4111 | "__aeabi_unwind_cpp_pr0", | |
4112 | "__aeabi_unwind_cpp_pr1", | |
4113 | "__aeabi_unwind_cpp_pr2" | |
4114 | }; | |
c19d1205 ZW |
4115 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
4116 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 4117 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 4118 | |= 1 << unwind.personality_index; |
c19d1205 | 4119 | } |
f02232aa | 4120 | |
c19d1205 ZW |
4121 | if (val) |
4122 | /* Inline exception table entry. */ | |
4123 | md_number_to_chars (ptr + 4, val, 4); | |
4124 | else | |
4125 | /* Self relative offset of the table entry. */ | |
4126 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
4127 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 4128 | |
c19d1205 ZW |
4129 | /* Restore the original section. */ |
4130 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
4131 | |
4132 | unwind.proc_start = NULL; | |
c19d1205 | 4133 | } |
f02232aa | 4134 | |
f02232aa | 4135 | |
c19d1205 | 4136 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 4137 | |
c19d1205 ZW |
4138 | static void |
4139 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
4140 | { | |
4141 | demand_empty_rest_of_line (); | |
921e5f0a | 4142 | if (!unwind.proc_start) |
c921be7d | 4143 | as_bad (MISSING_FNSTART); |
921e5f0a | 4144 | |
c19d1205 ZW |
4145 | if (unwind.personality_routine || unwind.personality_index != -1) |
4146 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 4147 | |
c19d1205 ZW |
4148 | unwind.personality_index = -2; |
4149 | } | |
b99bd4ef | 4150 | |
b99bd4ef | 4151 | |
c19d1205 | 4152 | /* Parse a personalityindex directive. */ |
b99bd4ef | 4153 | |
c19d1205 ZW |
4154 | static void |
4155 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
4156 | { | |
4157 | expressionS exp; | |
b99bd4ef | 4158 | |
921e5f0a | 4159 | if (!unwind.proc_start) |
c921be7d | 4160 | as_bad (MISSING_FNSTART); |
921e5f0a | 4161 | |
c19d1205 ZW |
4162 | if (unwind.personality_routine || unwind.personality_index != -1) |
4163 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 4164 | |
c19d1205 | 4165 | expression (&exp); |
b99bd4ef | 4166 | |
c19d1205 ZW |
4167 | if (exp.X_op != O_constant |
4168 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 4169 | { |
c19d1205 ZW |
4170 | as_bad (_("bad personality routine number")); |
4171 | ignore_rest_of_line (); | |
4172 | return; | |
b99bd4ef NC |
4173 | } |
4174 | ||
c19d1205 | 4175 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 4176 | |
c19d1205 ZW |
4177 | demand_empty_rest_of_line (); |
4178 | } | |
e16bb312 | 4179 | |
e16bb312 | 4180 | |
c19d1205 | 4181 | /* Parse a personality directive. */ |
e16bb312 | 4182 | |
c19d1205 ZW |
4183 | static void |
4184 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
4185 | { | |
4186 | char *name, *p, c; | |
a737bd4d | 4187 | |
921e5f0a | 4188 | if (!unwind.proc_start) |
c921be7d | 4189 | as_bad (MISSING_FNSTART); |
921e5f0a | 4190 | |
c19d1205 ZW |
4191 | if (unwind.personality_routine || unwind.personality_index != -1) |
4192 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 4193 | |
d02603dc | 4194 | c = get_symbol_name (& name); |
c19d1205 | 4195 | p = input_line_pointer; |
d02603dc NC |
4196 | if (c == '"') |
4197 | ++ input_line_pointer; | |
c19d1205 ZW |
4198 | unwind.personality_routine = symbol_find_or_make (name); |
4199 | *p = c; | |
4200 | demand_empty_rest_of_line (); | |
4201 | } | |
e16bb312 | 4202 | |
e16bb312 | 4203 | |
c19d1205 | 4204 | /* Parse a directive saving core registers. */ |
e16bb312 | 4205 | |
c19d1205 ZW |
4206 | static void |
4207 | s_arm_unwind_save_core (void) | |
e16bb312 | 4208 | { |
c19d1205 ZW |
4209 | valueT op; |
4210 | long range; | |
4211 | int n; | |
e16bb312 | 4212 | |
4b5a202f | 4213 | range = parse_reg_list (&input_line_pointer, REGLIST_RN); |
c19d1205 | 4214 | if (range == FAIL) |
e16bb312 | 4215 | { |
c19d1205 ZW |
4216 | as_bad (_("expected register list")); |
4217 | ignore_rest_of_line (); | |
4218 | return; | |
4219 | } | |
e16bb312 | 4220 | |
c19d1205 | 4221 | demand_empty_rest_of_line (); |
e16bb312 | 4222 | |
c19d1205 ZW |
4223 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
4224 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
4225 | ip because it is clobbered by calls. */ | |
4226 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
4227 | && (range & 0x3000) == 0x1000) | |
4228 | { | |
4229 | unwind.opcode_count--; | |
4230 | unwind.sp_restored = 0; | |
4231 | range = (range | 0x2000) & ~0x1000; | |
4232 | unwind.pending_offset = 0; | |
4233 | } | |
e16bb312 | 4234 | |
01ae4198 DJ |
4235 | /* Pop r4-r15. */ |
4236 | if (range & 0xfff0) | |
c19d1205 | 4237 | { |
01ae4198 DJ |
4238 | /* See if we can use the short opcodes. These pop a block of up to 8 |
4239 | registers starting with r4, plus maybe r14. */ | |
4240 | for (n = 0; n < 8; n++) | |
4241 | { | |
4242 | /* Break at the first non-saved register. */ | |
4243 | if ((range & (1 << (n + 4))) == 0) | |
4244 | break; | |
4245 | } | |
4246 | /* See if there are any other bits set. */ | |
4247 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
4248 | { | |
4249 | /* Use the long form. */ | |
4250 | op = 0x8000 | ((range >> 4) & 0xfff); | |
4251 | add_unwind_opcode (op, 2); | |
4252 | } | |
0dd132b6 | 4253 | else |
01ae4198 DJ |
4254 | { |
4255 | /* Use the short form. */ | |
4256 | if (range & 0x4000) | |
4257 | op = 0xa8; /* Pop r14. */ | |
4258 | else | |
4259 | op = 0xa0; /* Do not pop r14. */ | |
4260 | op |= (n - 1); | |
4261 | add_unwind_opcode (op, 1); | |
4262 | } | |
c19d1205 | 4263 | } |
0dd132b6 | 4264 | |
c19d1205 ZW |
4265 | /* Pop r0-r3. */ |
4266 | if (range & 0xf) | |
4267 | { | |
4268 | op = 0xb100 | (range & 0xf); | |
4269 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
4270 | } |
4271 | ||
c19d1205 ZW |
4272 | /* Record the number of bytes pushed. */ |
4273 | for (n = 0; n < 16; n++) | |
4274 | { | |
4275 | if (range & (1 << n)) | |
4276 | unwind.frame_size += 4; | |
4277 | } | |
0dd132b6 NC |
4278 | } |
4279 | ||
c19d1205 ZW |
4280 | |
4281 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
4282 | |
4283 | static void | |
c19d1205 | 4284 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 4285 | { |
c19d1205 ZW |
4286 | expressionS exp; |
4287 | int num_regs; | |
4288 | valueT op; | |
b99bd4ef | 4289 | |
c19d1205 ZW |
4290 | /* Get Number of registers to transfer. */ |
4291 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4292 | expression (&exp); | |
4293 | else | |
4294 | exp.X_op = O_illegal; | |
b99bd4ef | 4295 | |
c19d1205 | 4296 | if (exp.X_op != O_constant) |
b99bd4ef | 4297 | { |
c19d1205 ZW |
4298 | as_bad (_("expected , <constant>")); |
4299 | ignore_rest_of_line (); | |
b99bd4ef NC |
4300 | return; |
4301 | } | |
4302 | ||
c19d1205 ZW |
4303 | num_regs = exp.X_add_number; |
4304 | ||
4305 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 4306 | { |
c19d1205 ZW |
4307 | as_bad (_("number of registers must be in the range [1:4]")); |
4308 | ignore_rest_of_line (); | |
b99bd4ef NC |
4309 | return; |
4310 | } | |
4311 | ||
c19d1205 | 4312 | demand_empty_rest_of_line (); |
b99bd4ef | 4313 | |
c19d1205 ZW |
4314 | if (reg == 4) |
4315 | { | |
4316 | /* Short form. */ | |
4317 | op = 0xb4 | (num_regs - 1); | |
4318 | add_unwind_opcode (op, 1); | |
4319 | } | |
b99bd4ef NC |
4320 | else |
4321 | { | |
c19d1205 ZW |
4322 | /* Long form. */ |
4323 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4324 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4325 | } |
c19d1205 | 4326 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4327 | } |
4328 | ||
c19d1205 | 4329 | |
fa073d69 MS |
4330 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4331 | ||
4332 | static void | |
4333 | s_arm_unwind_save_vfp_armv6 (void) | |
4334 | { | |
4335 | int count; | |
4336 | unsigned int start; | |
4337 | valueT op; | |
4338 | int num_vfpv3_regs = 0; | |
4339 | int num_regs_below_16; | |
efd6b359 | 4340 | bfd_boolean partial_match; |
fa073d69 | 4341 | |
efd6b359 AV |
4342 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D, |
4343 | &partial_match); | |
fa073d69 MS |
4344 | if (count == FAIL) |
4345 | { | |
4346 | as_bad (_("expected register list")); | |
4347 | ignore_rest_of_line (); | |
4348 | return; | |
4349 | } | |
4350 | ||
4351 | demand_empty_rest_of_line (); | |
4352 | ||
4353 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4354 | than FSTMX/FLDMX-style ones). */ | |
4355 | ||
4356 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4357 | if (start >= 16) | |
4358 | num_vfpv3_regs = count; | |
4359 | else if (start + count > 16) | |
4360 | num_vfpv3_regs = start + count - 16; | |
4361 | ||
4362 | if (num_vfpv3_regs > 0) | |
4363 | { | |
4364 | int start_offset = start > 16 ? start - 16 : 0; | |
4365 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4366 | add_unwind_opcode (op, 2); | |
4367 | } | |
4368 | ||
4369 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4370 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4371 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4372 | if (num_regs_below_16 > 0) |
4373 | { | |
4374 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4375 | add_unwind_opcode (op, 2); | |
4376 | } | |
4377 | ||
4378 | unwind.frame_size += count * 8; | |
4379 | } | |
4380 | ||
4381 | ||
4382 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4383 | |
4384 | static void | |
c19d1205 | 4385 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4386 | { |
c19d1205 | 4387 | int count; |
ca3f61f7 | 4388 | unsigned int reg; |
c19d1205 | 4389 | valueT op; |
efd6b359 | 4390 | bfd_boolean partial_match; |
b99bd4ef | 4391 | |
efd6b359 AV |
4392 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D, |
4393 | &partial_match); | |
c19d1205 | 4394 | if (count == FAIL) |
b99bd4ef | 4395 | { |
c19d1205 ZW |
4396 | as_bad (_("expected register list")); |
4397 | ignore_rest_of_line (); | |
b99bd4ef NC |
4398 | return; |
4399 | } | |
4400 | ||
c19d1205 | 4401 | demand_empty_rest_of_line (); |
b99bd4ef | 4402 | |
c19d1205 | 4403 | if (reg == 8) |
b99bd4ef | 4404 | { |
c19d1205 ZW |
4405 | /* Short form. */ |
4406 | op = 0xb8 | (count - 1); | |
4407 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4408 | } |
c19d1205 | 4409 | else |
b99bd4ef | 4410 | { |
c19d1205 ZW |
4411 | /* Long form. */ |
4412 | op = 0xb300 | (reg << 4) | (count - 1); | |
4413 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4414 | } |
c19d1205 ZW |
4415 | unwind.frame_size += count * 8 + 4; |
4416 | } | |
b99bd4ef | 4417 | |
b99bd4ef | 4418 | |
c19d1205 ZW |
4419 | /* Parse a directive saving iWMMXt data registers. */ |
4420 | ||
4421 | static void | |
4422 | s_arm_unwind_save_mmxwr (void) | |
4423 | { | |
4424 | int reg; | |
4425 | int hi_reg; | |
4426 | int i; | |
4427 | unsigned mask = 0; | |
4428 | valueT op; | |
b99bd4ef | 4429 | |
c19d1205 ZW |
4430 | if (*input_line_pointer == '{') |
4431 | input_line_pointer++; | |
b99bd4ef | 4432 | |
c19d1205 | 4433 | do |
b99bd4ef | 4434 | { |
dcbf9037 | 4435 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4436 | |
c19d1205 | 4437 | if (reg == FAIL) |
b99bd4ef | 4438 | { |
9b7132d3 | 4439 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4440 | goto error; |
b99bd4ef NC |
4441 | } |
4442 | ||
c19d1205 ZW |
4443 | if (mask >> reg) |
4444 | as_tsktsk (_("register list not in ascending order")); | |
4445 | mask |= 1 << reg; | |
b99bd4ef | 4446 | |
c19d1205 ZW |
4447 | if (*input_line_pointer == '-') |
4448 | { | |
4449 | input_line_pointer++; | |
dcbf9037 | 4450 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4451 | if (hi_reg == FAIL) |
4452 | { | |
9b7132d3 | 4453 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4454 | goto error; |
4455 | } | |
4456 | else if (reg >= hi_reg) | |
4457 | { | |
4458 | as_bad (_("bad register range")); | |
4459 | goto error; | |
4460 | } | |
4461 | for (; reg < hi_reg; reg++) | |
4462 | mask |= 1 << reg; | |
4463 | } | |
4464 | } | |
4465 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4466 | |
d996d970 | 4467 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4468 | |
c19d1205 | 4469 | demand_empty_rest_of_line (); |
b99bd4ef | 4470 | |
708587a4 | 4471 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4472 | the list. */ |
4473 | flush_pending_unwind (); | |
b99bd4ef | 4474 | |
c19d1205 | 4475 | for (i = 0; i < 16; i++) |
b99bd4ef | 4476 | { |
c19d1205 ZW |
4477 | if (mask & (1 << i)) |
4478 | unwind.frame_size += 8; | |
b99bd4ef NC |
4479 | } |
4480 | ||
c19d1205 ZW |
4481 | /* Attempt to combine with a previous opcode. We do this because gcc |
4482 | likes to output separate unwind directives for a single block of | |
4483 | registers. */ | |
4484 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4485 | { |
c19d1205 ZW |
4486 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4487 | if ((i & 0xf8) == 0xc0) | |
4488 | { | |
4489 | i &= 7; | |
4490 | /* Only merge if the blocks are contiguous. */ | |
4491 | if (i < 6) | |
4492 | { | |
4493 | if ((mask & 0xfe00) == (1 << 9)) | |
4494 | { | |
4495 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4496 | unwind.opcode_count--; | |
4497 | } | |
4498 | } | |
4499 | else if (i == 6 && unwind.opcode_count >= 2) | |
4500 | { | |
4501 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4502 | reg = i >> 4; | |
4503 | i &= 0xf; | |
b99bd4ef | 4504 | |
c19d1205 ZW |
4505 | op = 0xffff << (reg - 1); |
4506 | if (reg > 0 | |
87a1fd79 | 4507 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4508 | { |
4509 | op = (1 << (reg + i + 1)) - 1; | |
4510 | op &= ~((1 << reg) - 1); | |
4511 | mask |= op; | |
4512 | unwind.opcode_count -= 2; | |
4513 | } | |
4514 | } | |
4515 | } | |
b99bd4ef NC |
4516 | } |
4517 | ||
c19d1205 ZW |
4518 | hi_reg = 15; |
4519 | /* We want to generate opcodes in the order the registers have been | |
4520 | saved, ie. descending order. */ | |
4521 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4522 | { |
c19d1205 ZW |
4523 | /* Save registers in blocks. */ |
4524 | if (reg < 0 | |
4525 | || !(mask & (1 << reg))) | |
4526 | { | |
4527 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4528 | preceding block. */ |
c19d1205 ZW |
4529 | if (reg != hi_reg) |
4530 | { | |
4531 | if (reg == 9) | |
4532 | { | |
4533 | /* Short form. */ | |
4534 | op = 0xc0 | (hi_reg - 10); | |
4535 | add_unwind_opcode (op, 1); | |
4536 | } | |
4537 | else | |
4538 | { | |
4539 | /* Long form. */ | |
4540 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4541 | add_unwind_opcode (op, 2); | |
4542 | } | |
4543 | } | |
4544 | hi_reg = reg - 1; | |
4545 | } | |
b99bd4ef NC |
4546 | } |
4547 | ||
c19d1205 ZW |
4548 | return; |
4549 | error: | |
4550 | ignore_rest_of_line (); | |
b99bd4ef NC |
4551 | } |
4552 | ||
4553 | static void | |
c19d1205 | 4554 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4555 | { |
c19d1205 ZW |
4556 | int reg; |
4557 | int hi_reg; | |
4558 | unsigned mask = 0; | |
4559 | valueT op; | |
b99bd4ef | 4560 | |
c19d1205 ZW |
4561 | if (*input_line_pointer == '{') |
4562 | input_line_pointer++; | |
b99bd4ef | 4563 | |
477330fc RM |
4564 | skip_whitespace (input_line_pointer); |
4565 | ||
c19d1205 | 4566 | do |
b99bd4ef | 4567 | { |
dcbf9037 | 4568 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4569 | |
c19d1205 ZW |
4570 | if (reg == FAIL) |
4571 | { | |
9b7132d3 | 4572 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4573 | goto error; |
4574 | } | |
b99bd4ef | 4575 | |
c19d1205 ZW |
4576 | reg -= 8; |
4577 | if (mask >> reg) | |
4578 | as_tsktsk (_("register list not in ascending order")); | |
4579 | mask |= 1 << reg; | |
b99bd4ef | 4580 | |
c19d1205 ZW |
4581 | if (*input_line_pointer == '-') |
4582 | { | |
4583 | input_line_pointer++; | |
dcbf9037 | 4584 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4585 | if (hi_reg == FAIL) |
4586 | { | |
9b7132d3 | 4587 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4588 | goto error; |
4589 | } | |
4590 | else if (reg >= hi_reg) | |
4591 | { | |
4592 | as_bad (_("bad register range")); | |
4593 | goto error; | |
4594 | } | |
4595 | for (; reg < hi_reg; reg++) | |
4596 | mask |= 1 << reg; | |
4597 | } | |
b99bd4ef | 4598 | } |
c19d1205 | 4599 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4600 | |
d996d970 | 4601 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4602 | |
c19d1205 ZW |
4603 | demand_empty_rest_of_line (); |
4604 | ||
708587a4 | 4605 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4606 | the list. */ |
4607 | flush_pending_unwind (); | |
b99bd4ef | 4608 | |
c19d1205 | 4609 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4610 | { |
c19d1205 ZW |
4611 | if (mask & (1 << reg)) |
4612 | unwind.frame_size += 4; | |
b99bd4ef | 4613 | } |
c19d1205 ZW |
4614 | op = 0xc700 | mask; |
4615 | add_unwind_opcode (op, 2); | |
4616 | return; | |
4617 | error: | |
4618 | ignore_rest_of_line (); | |
b99bd4ef NC |
4619 | } |
4620 | ||
c19d1205 | 4621 | |
fa073d69 MS |
4622 | /* Parse an unwind_save directive. |
4623 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4624 | |
b99bd4ef | 4625 | static void |
fa073d69 | 4626 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4627 | { |
c19d1205 ZW |
4628 | char *peek; |
4629 | struct reg_entry *reg; | |
4630 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4631 | |
921e5f0a | 4632 | if (!unwind.proc_start) |
c921be7d | 4633 | as_bad (MISSING_FNSTART); |
921e5f0a | 4634 | |
c19d1205 ZW |
4635 | /* Figure out what sort of save we have. */ |
4636 | peek = input_line_pointer; | |
b99bd4ef | 4637 | |
c19d1205 | 4638 | if (*peek == '{') |
b99bd4ef | 4639 | { |
c19d1205 ZW |
4640 | had_brace = TRUE; |
4641 | peek++; | |
b99bd4ef NC |
4642 | } |
4643 | ||
c19d1205 | 4644 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4645 | |
c19d1205 | 4646 | if (!reg) |
b99bd4ef | 4647 | { |
c19d1205 ZW |
4648 | as_bad (_("register expected")); |
4649 | ignore_rest_of_line (); | |
b99bd4ef NC |
4650 | return; |
4651 | } | |
4652 | ||
c19d1205 | 4653 | switch (reg->type) |
b99bd4ef | 4654 | { |
c19d1205 ZW |
4655 | case REG_TYPE_FN: |
4656 | if (had_brace) | |
4657 | { | |
4658 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4659 | ignore_rest_of_line (); | |
4660 | return; | |
4661 | } | |
93ac2687 | 4662 | input_line_pointer = peek; |
c19d1205 | 4663 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4664 | return; |
c19d1205 | 4665 | |
1f5afe1c NC |
4666 | case REG_TYPE_RN: |
4667 | s_arm_unwind_save_core (); | |
4668 | return; | |
4669 | ||
fa073d69 MS |
4670 | case REG_TYPE_VFD: |
4671 | if (arch_v6) | |
477330fc | 4672 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4673 | else |
477330fc | 4674 | s_arm_unwind_save_vfp (); |
fa073d69 | 4675 | return; |
1f5afe1c NC |
4676 | |
4677 | case REG_TYPE_MMXWR: | |
4678 | s_arm_unwind_save_mmxwr (); | |
4679 | return; | |
4680 | ||
4681 | case REG_TYPE_MMXWCG: | |
4682 | s_arm_unwind_save_mmxwcg (); | |
4683 | return; | |
c19d1205 ZW |
4684 | |
4685 | default: | |
4686 | as_bad (_(".unwind_save does not support this kind of register")); | |
4687 | ignore_rest_of_line (); | |
b99bd4ef | 4688 | } |
c19d1205 | 4689 | } |
b99bd4ef | 4690 | |
b99bd4ef | 4691 | |
c19d1205 ZW |
4692 | /* Parse an unwind_movsp directive. */ |
4693 | ||
4694 | static void | |
4695 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4696 | { | |
4697 | int reg; | |
4698 | valueT op; | |
4fa3602b | 4699 | int offset; |
c19d1205 | 4700 | |
921e5f0a | 4701 | if (!unwind.proc_start) |
c921be7d | 4702 | as_bad (MISSING_FNSTART); |
921e5f0a | 4703 | |
dcbf9037 | 4704 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4705 | if (reg == FAIL) |
b99bd4ef | 4706 | { |
9b7132d3 | 4707 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4708 | ignore_rest_of_line (); |
b99bd4ef NC |
4709 | return; |
4710 | } | |
4fa3602b PB |
4711 | |
4712 | /* Optional constant. */ | |
4713 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4714 | { | |
4715 | if (immediate_for_directive (&offset) == FAIL) | |
4716 | return; | |
4717 | } | |
4718 | else | |
4719 | offset = 0; | |
4720 | ||
c19d1205 | 4721 | demand_empty_rest_of_line (); |
b99bd4ef | 4722 | |
c19d1205 | 4723 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4724 | { |
c19d1205 | 4725 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4726 | return; |
4727 | } | |
4728 | ||
c19d1205 ZW |
4729 | if (unwind.fp_reg != REG_SP) |
4730 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4731 | |
c19d1205 ZW |
4732 | /* Generate opcode to restore the value. */ |
4733 | op = 0x90 | reg; | |
4734 | add_unwind_opcode (op, 1); | |
4735 | ||
4736 | /* Record the information for later. */ | |
4737 | unwind.fp_reg = reg; | |
4fa3602b | 4738 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4739 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4740 | } |
4741 | ||
c19d1205 ZW |
4742 | /* Parse an unwind_pad directive. */ |
4743 | ||
b05fe5cf | 4744 | static void |
c19d1205 | 4745 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4746 | { |
c19d1205 | 4747 | int offset; |
b05fe5cf | 4748 | |
921e5f0a | 4749 | if (!unwind.proc_start) |
c921be7d | 4750 | as_bad (MISSING_FNSTART); |
921e5f0a | 4751 | |
c19d1205 ZW |
4752 | if (immediate_for_directive (&offset) == FAIL) |
4753 | return; | |
b99bd4ef | 4754 | |
c19d1205 ZW |
4755 | if (offset & 3) |
4756 | { | |
4757 | as_bad (_("stack increment must be multiple of 4")); | |
4758 | ignore_rest_of_line (); | |
4759 | return; | |
4760 | } | |
b99bd4ef | 4761 | |
c19d1205 ZW |
4762 | /* Don't generate any opcodes, just record the details for later. */ |
4763 | unwind.frame_size += offset; | |
4764 | unwind.pending_offset += offset; | |
4765 | ||
4766 | demand_empty_rest_of_line (); | |
4767 | } | |
4768 | ||
4769 | /* Parse an unwind_setfp directive. */ | |
4770 | ||
4771 | static void | |
4772 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4773 | { |
c19d1205 ZW |
4774 | int sp_reg; |
4775 | int fp_reg; | |
4776 | int offset; | |
4777 | ||
921e5f0a | 4778 | if (!unwind.proc_start) |
c921be7d | 4779 | as_bad (MISSING_FNSTART); |
921e5f0a | 4780 | |
dcbf9037 | 4781 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4782 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4783 | sp_reg = FAIL; | |
4784 | else | |
dcbf9037 | 4785 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4786 | |
c19d1205 ZW |
4787 | if (fp_reg == FAIL || sp_reg == FAIL) |
4788 | { | |
4789 | as_bad (_("expected <reg>, <reg>")); | |
4790 | ignore_rest_of_line (); | |
4791 | return; | |
4792 | } | |
b99bd4ef | 4793 | |
c19d1205 ZW |
4794 | /* Optional constant. */ |
4795 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4796 | { | |
4797 | if (immediate_for_directive (&offset) == FAIL) | |
4798 | return; | |
4799 | } | |
4800 | else | |
4801 | offset = 0; | |
a737bd4d | 4802 | |
c19d1205 | 4803 | demand_empty_rest_of_line (); |
a737bd4d | 4804 | |
fdfde340 | 4805 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4806 | { |
c19d1205 ZW |
4807 | as_bad (_("register must be either sp or set by a previous" |
4808 | "unwind_movsp directive")); | |
4809 | return; | |
a737bd4d NC |
4810 | } |
4811 | ||
c19d1205 ZW |
4812 | /* Don't generate any opcodes, just record the information for later. */ |
4813 | unwind.fp_reg = fp_reg; | |
4814 | unwind.fp_used = 1; | |
fdfde340 | 4815 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4816 | unwind.fp_offset = unwind.frame_size - offset; |
4817 | else | |
4818 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4819 | } |
4820 | ||
c19d1205 ZW |
4821 | /* Parse an unwind_raw directive. */ |
4822 | ||
4823 | static void | |
4824 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4825 | { |
c19d1205 | 4826 | expressionS exp; |
708587a4 | 4827 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4828 | unsigned char op[16]; |
4829 | int count; | |
a737bd4d | 4830 | |
921e5f0a | 4831 | if (!unwind.proc_start) |
c921be7d | 4832 | as_bad (MISSING_FNSTART); |
921e5f0a | 4833 | |
c19d1205 ZW |
4834 | expression (&exp); |
4835 | if (exp.X_op == O_constant | |
4836 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4837 | { |
c19d1205 ZW |
4838 | unwind.frame_size += exp.X_add_number; |
4839 | expression (&exp); | |
4840 | } | |
4841 | else | |
4842 | exp.X_op = O_illegal; | |
a737bd4d | 4843 | |
c19d1205 ZW |
4844 | if (exp.X_op != O_constant) |
4845 | { | |
4846 | as_bad (_("expected <offset>, <opcode>")); | |
4847 | ignore_rest_of_line (); | |
4848 | return; | |
4849 | } | |
a737bd4d | 4850 | |
c19d1205 | 4851 | count = 0; |
a737bd4d | 4852 | |
c19d1205 ZW |
4853 | /* Parse the opcode. */ |
4854 | for (;;) | |
4855 | { | |
4856 | if (count >= 16) | |
4857 | { | |
4858 | as_bad (_("unwind opcode too long")); | |
4859 | ignore_rest_of_line (); | |
a737bd4d | 4860 | } |
c19d1205 | 4861 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4862 | { |
c19d1205 ZW |
4863 | as_bad (_("invalid unwind opcode")); |
4864 | ignore_rest_of_line (); | |
4865 | return; | |
a737bd4d | 4866 | } |
c19d1205 | 4867 | op[count++] = exp.X_add_number; |
a737bd4d | 4868 | |
c19d1205 ZW |
4869 | /* Parse the next byte. */ |
4870 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4871 | break; | |
a737bd4d | 4872 | |
c19d1205 ZW |
4873 | expression (&exp); |
4874 | } | |
b99bd4ef | 4875 | |
c19d1205 ZW |
4876 | /* Add the opcode bytes in reverse order. */ |
4877 | while (count--) | |
4878 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4879 | |
c19d1205 | 4880 | demand_empty_rest_of_line (); |
b99bd4ef | 4881 | } |
ee065d83 PB |
4882 | |
4883 | ||
4884 | /* Parse a .eabi_attribute directive. */ | |
4885 | ||
4886 | static void | |
4887 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4888 | { | |
0420f52b | 4889 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 | 4890 | |
3076e594 | 4891 | if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES) |
ee3c0378 | 4892 | attributes_set_explicitly[tag] = 1; |
ee065d83 PB |
4893 | } |
4894 | ||
0855e32b NS |
4895 | /* Emit a tls fix for the symbol. */ |
4896 | ||
4897 | static void | |
4898 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4899 | { | |
4900 | char *p; | |
4901 | expressionS exp; | |
4902 | #ifdef md_flush_pending_output | |
4903 | md_flush_pending_output (); | |
4904 | #endif | |
4905 | ||
4906 | #ifdef md_cons_align | |
4907 | md_cons_align (4); | |
4908 | #endif | |
4909 | ||
4910 | /* Since we're just labelling the code, there's no need to define a | |
4911 | mapping symbol. */ | |
4912 | expression (&exp); | |
4913 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4914 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4915 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4916 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4917 | } | |
cdf9ccec | 4918 | #endif /* OBJ_ELF */ |
0855e32b | 4919 | |
ee065d83 | 4920 | static void s_arm_arch (int); |
7a1d4c38 | 4921 | static void s_arm_object_arch (int); |
ee065d83 PB |
4922 | static void s_arm_cpu (int); |
4923 | static void s_arm_fpu (int); | |
69133863 | 4924 | static void s_arm_arch_extension (int); |
b99bd4ef | 4925 | |
f0927246 NC |
4926 | #ifdef TE_PE |
4927 | ||
4928 | static void | |
5f4273c7 | 4929 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4930 | { |
4931 | expressionS exp; | |
4932 | ||
4933 | do | |
4934 | { | |
4935 | expression (&exp); | |
4936 | if (exp.X_op == O_symbol) | |
4937 | exp.X_op = O_secrel; | |
4938 | ||
4939 | emit_expr (&exp, 4); | |
4940 | } | |
4941 | while (*input_line_pointer++ == ','); | |
4942 | ||
4943 | input_line_pointer--; | |
4944 | demand_empty_rest_of_line (); | |
4945 | } | |
4946 | #endif /* TE_PE */ | |
4947 | ||
5312fe52 BW |
4948 | int |
4949 | arm_is_largest_exponent_ok (int precision) | |
4950 | { | |
4951 | /* precision == 1 ensures that this will only return | |
4952 | true for 16 bit floats. */ | |
4953 | return (precision == 1) && (fp16_format == ARM_FP16_FORMAT_ALTERNATIVE); | |
4954 | } | |
4955 | ||
4956 | static void | |
4957 | set_fp16_format (int dummy ATTRIBUTE_UNUSED) | |
4958 | { | |
4959 | char saved_char; | |
4960 | char* name; | |
4961 | enum fp_16bit_format new_format; | |
4962 | ||
4963 | new_format = ARM_FP16_FORMAT_DEFAULT; | |
4964 | ||
4965 | name = input_line_pointer; | |
4966 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
4967 | input_line_pointer++; | |
4968 | ||
4969 | saved_char = *input_line_pointer; | |
4970 | *input_line_pointer = 0; | |
4971 | ||
4972 | if (strcasecmp (name, "ieee") == 0) | |
4973 | new_format = ARM_FP16_FORMAT_IEEE; | |
4974 | else if (strcasecmp (name, "alternative") == 0) | |
4975 | new_format = ARM_FP16_FORMAT_ALTERNATIVE; | |
4976 | else | |
4977 | { | |
4978 | as_bad (_("unrecognised float16 format \"%s\""), name); | |
4979 | goto cleanup; | |
4980 | } | |
4981 | ||
4982 | /* Only set fp16_format if it is still the default (aka not already | |
4983 | been set yet). */ | |
4984 | if (fp16_format == ARM_FP16_FORMAT_DEFAULT) | |
4985 | fp16_format = new_format; | |
4986 | else | |
4987 | { | |
4988 | if (new_format != fp16_format) | |
4989 | as_warn (_("float16 format cannot be set more than once, ignoring.")); | |
4990 | } | |
4991 | ||
4992 | cleanup: | |
4993 | *input_line_pointer = saved_char; | |
4994 | ignore_rest_of_line (); | |
4995 | } | |
4996 | ||
c19d1205 ZW |
4997 | /* This table describes all the machine specific pseudo-ops the assembler |
4998 | has to support. The fields are: | |
4999 | pseudo-op name without dot | |
5000 | function to call to execute this pseudo-op | |
5001 | Integer arg to pass to the function. */ | |
b99bd4ef | 5002 | |
c19d1205 | 5003 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 5004 | { |
c19d1205 ZW |
5005 | /* Never called because '.req' does not start a line. */ |
5006 | { "req", s_req, 0 }, | |
dcbf9037 JB |
5007 | /* Following two are likewise never called. */ |
5008 | { "dn", s_dn, 0 }, | |
5009 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
5010 | { "unreq", s_unreq, 0 }, |
5011 | { "bss", s_bss, 0 }, | |
db2ed2e0 | 5012 | { "align", s_align_ptwo, 2 }, |
c19d1205 ZW |
5013 | { "arm", s_arm, 0 }, |
5014 | { "thumb", s_thumb, 0 }, | |
5015 | { "code", s_code, 0 }, | |
5016 | { "force_thumb", s_force_thumb, 0 }, | |
5017 | { "thumb_func", s_thumb_func, 0 }, | |
5018 | { "thumb_set", s_thumb_set, 0 }, | |
5019 | { "even", s_even, 0 }, | |
5020 | { "ltorg", s_ltorg, 0 }, | |
5021 | { "pool", s_ltorg, 0 }, | |
5022 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
5023 | { "cpu", s_arm_cpu, 0 }, |
5024 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 5025 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 5026 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 5027 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 5028 | #ifdef OBJ_ELF |
c921be7d NC |
5029 | { "word", s_arm_elf_cons, 4 }, |
5030 | { "long", s_arm_elf_cons, 4 }, | |
5031 | { "inst.n", s_arm_elf_inst, 2 }, | |
5032 | { "inst.w", s_arm_elf_inst, 4 }, | |
5033 | { "inst", s_arm_elf_inst, 0 }, | |
5034 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
5035 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
5036 | { "fnend", s_arm_unwind_fnend, 0 }, | |
5037 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
5038 | { "personality", s_arm_unwind_personality, 0 }, | |
5039 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
5040 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
5041 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 5042 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
5043 | { "movsp", s_arm_unwind_movsp, 0 }, |
5044 | { "pad", s_arm_unwind_pad, 0 }, | |
5045 | { "setfp", s_arm_unwind_setfp, 0 }, | |
5046 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 5047 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 5048 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
5049 | #else |
5050 | { "word", cons, 4}, | |
f0927246 NC |
5051 | |
5052 | /* These are used for dwarf. */ | |
5053 | {"2byte", cons, 2}, | |
5054 | {"4byte", cons, 4}, | |
5055 | {"8byte", cons, 8}, | |
5056 | /* These are used for dwarf2. */ | |
68d20676 | 5057 | { "file", dwarf2_directive_file, 0 }, |
f0927246 NC |
5058 | { "loc", dwarf2_directive_loc, 0 }, |
5059 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
5060 | #endif |
5061 | { "extend", float_cons, 'x' }, | |
5062 | { "ldouble", float_cons, 'x' }, | |
5063 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
5064 | #ifdef TE_PE |
5065 | {"secrel32", pe_directive_secrel, 0}, | |
5066 | #endif | |
2e6976a8 DG |
5067 | |
5068 | /* These are for compatibility with CodeComposer Studio. */ | |
5069 | {"ref", s_ccs_ref, 0}, | |
5070 | {"def", s_ccs_def, 0}, | |
5071 | {"asmfunc", s_ccs_asmfunc, 0}, | |
5072 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
5073 | ||
5312fe52 BW |
5074 | {"float16", float_cons, 'h' }, |
5075 | {"float16_format", set_fp16_format, 0 }, | |
5076 | ||
c19d1205 ZW |
5077 | { 0, 0, 0 } |
5078 | }; | |
5312fe52 | 5079 | |
c19d1205 | 5080 | /* Parser functions used exclusively in instruction operands. */ |
b99bd4ef | 5081 | |
c19d1205 ZW |
5082 | /* Generic immediate-value read function for use in insn parsing. |
5083 | STR points to the beginning of the immediate (the leading #); | |
5084 | VAL receives the value; if the value is outside [MIN, MAX] | |
5085 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
5086 | optional. */ | |
b99bd4ef | 5087 | |
c19d1205 ZW |
5088 | static int |
5089 | parse_immediate (char **str, int *val, int min, int max, | |
5090 | bfd_boolean prefix_opt) | |
5091 | { | |
5092 | expressionS exp; | |
0198d5e6 | 5093 | |
c19d1205 ZW |
5094 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); |
5095 | if (exp.X_op != O_constant) | |
b99bd4ef | 5096 | { |
c19d1205 ZW |
5097 | inst.error = _("constant expression required"); |
5098 | return FAIL; | |
5099 | } | |
b99bd4ef | 5100 | |
c19d1205 ZW |
5101 | if (exp.X_add_number < min || exp.X_add_number > max) |
5102 | { | |
5103 | inst.error = _("immediate value out of range"); | |
5104 | return FAIL; | |
5105 | } | |
b99bd4ef | 5106 | |
c19d1205 ZW |
5107 | *val = exp.X_add_number; |
5108 | return SUCCESS; | |
5109 | } | |
b99bd4ef | 5110 | |
5287ad62 | 5111 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 5112 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
5113 | instructions. Puts the result directly in inst.operands[i]. */ |
5114 | ||
5115 | static int | |
8335d6aa JW |
5116 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
5117 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
5118 | { |
5119 | expressionS exp; | |
8335d6aa | 5120 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
5121 | char *ptr = *str; |
5122 | ||
8335d6aa | 5123 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 5124 | |
8335d6aa | 5125 | if (exp_p->X_op == O_constant) |
036dc3f7 | 5126 | { |
8335d6aa | 5127 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
5128 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
5129 | O_constant. We have to be careful not to break compilation for | |
5130 | 32-bit X_add_number, though. */ | |
8335d6aa | 5131 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 5132 | { |
8335d6aa JW |
5133 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
5134 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
5135 | & 0xffffffff); | |
036dc3f7 PB |
5136 | inst.operands[i].regisimm = 1; |
5137 | } | |
5138 | } | |
8335d6aa JW |
5139 | else if (exp_p->X_op == O_big |
5140 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
5141 | { |
5142 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 5143 | |
5287ad62 | 5144 | /* Bignums have their least significant bits in |
477330fc RM |
5145 | generic_bignum[0]. Make sure we put 32 bits in imm and |
5146 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 5147 | gas_assert (parts != 0); |
95b75c01 NC |
5148 | |
5149 | /* Make sure that the number is not too big. | |
5150 | PR 11972: Bignums can now be sign-extended to the | |
5151 | size of a .octa so check that the out of range bits | |
5152 | are all zero or all one. */ | |
8335d6aa | 5153 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
5154 | { |
5155 | LITTLENUM_TYPE m = -1; | |
5156 | ||
5157 | if (generic_bignum[parts * 2] != 0 | |
5158 | && generic_bignum[parts * 2] != m) | |
5159 | return FAIL; | |
5160 | ||
8335d6aa | 5161 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
5162 | if (generic_bignum[j] != generic_bignum[j-1]) |
5163 | return FAIL; | |
5164 | } | |
5165 | ||
5287ad62 JB |
5166 | inst.operands[i].imm = 0; |
5167 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
5168 | inst.operands[i].imm |= generic_bignum[idx] |
5169 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
5170 | inst.operands[i].reg = 0; |
5171 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
5172 | inst.operands[i].reg |= generic_bignum[idx] |
5173 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
5174 | inst.operands[i].regisimm = 1; |
5175 | } | |
8335d6aa | 5176 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 5177 | return FAIL; |
5f4273c7 | 5178 | |
5287ad62 JB |
5179 | *str = ptr; |
5180 | ||
5181 | return SUCCESS; | |
5182 | } | |
5183 | ||
c19d1205 ZW |
5184 | /* Returns the pseudo-register number of an FPA immediate constant, |
5185 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 5186 | |
c19d1205 ZW |
5187 | static int |
5188 | parse_fpa_immediate (char ** str) | |
5189 | { | |
5190 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
5191 | char * save_in; | |
5192 | expressionS exp; | |
5193 | int i; | |
5194 | int j; | |
b99bd4ef | 5195 | |
c19d1205 ZW |
5196 | /* First try and match exact strings, this is to guarantee |
5197 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 5198 | |
c19d1205 ZW |
5199 | for (i = 0; fp_const[i]; i++) |
5200 | { | |
5201 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 5202 | { |
c19d1205 | 5203 | char *start = *str; |
b99bd4ef | 5204 | |
c19d1205 ZW |
5205 | *str += strlen (fp_const[i]); |
5206 | if (is_end_of_line[(unsigned char) **str]) | |
5207 | return i + 8; | |
5208 | *str = start; | |
5209 | } | |
5210 | } | |
b99bd4ef | 5211 | |
c19d1205 ZW |
5212 | /* Just because we didn't get a match doesn't mean that the constant |
5213 | isn't valid, just that it is in a format that we don't | |
5214 | automatically recognize. Try parsing it with the standard | |
5215 | expression routines. */ | |
b99bd4ef | 5216 | |
c19d1205 | 5217 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 5218 | |
c19d1205 ZW |
5219 | /* Look for a raw floating point number. */ |
5220 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
5221 | && is_end_of_line[(unsigned char) *save_in]) | |
5222 | { | |
5223 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
5224 | { | |
5225 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 5226 | { |
c19d1205 ZW |
5227 | if (words[j] != fp_values[i][j]) |
5228 | break; | |
b99bd4ef NC |
5229 | } |
5230 | ||
c19d1205 | 5231 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 5232 | { |
c19d1205 ZW |
5233 | *str = save_in; |
5234 | return i + 8; | |
b99bd4ef NC |
5235 | } |
5236 | } | |
5237 | } | |
b99bd4ef | 5238 | |
c19d1205 ZW |
5239 | /* Try and parse a more complex expression, this will probably fail |
5240 | unless the code uses a floating point prefix (eg "0f"). */ | |
5241 | save_in = input_line_pointer; | |
5242 | input_line_pointer = *str; | |
5243 | if (expression (&exp) == absolute_section | |
5244 | && exp.X_op == O_big | |
5245 | && exp.X_add_number < 0) | |
5246 | { | |
5247 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
5248 | Ditto for 15. */ | |
ba592044 AM |
5249 | #define X_PRECISION 5 |
5250 | #define E_PRECISION 15L | |
5251 | if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0) | |
c19d1205 ZW |
5252 | { |
5253 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
5254 | { | |
5255 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
5256 | { | |
5257 | if (words[j] != fp_values[i][j]) | |
5258 | break; | |
5259 | } | |
b99bd4ef | 5260 | |
c19d1205 ZW |
5261 | if (j == MAX_LITTLENUMS) |
5262 | { | |
5263 | *str = input_line_pointer; | |
5264 | input_line_pointer = save_in; | |
5265 | return i + 8; | |
5266 | } | |
5267 | } | |
5268 | } | |
b99bd4ef NC |
5269 | } |
5270 | ||
c19d1205 ZW |
5271 | *str = input_line_pointer; |
5272 | input_line_pointer = save_in; | |
5273 | inst.error = _("invalid FPA immediate expression"); | |
5274 | return FAIL; | |
b99bd4ef NC |
5275 | } |
5276 | ||
136da414 JB |
5277 | /* Returns 1 if a number has "quarter-precision" float format |
5278 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
5279 | ||
5280 | static int | |
5281 | is_quarter_float (unsigned imm) | |
5282 | { | |
5283 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
5284 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
5285 | } | |
5286 | ||
aacf0b33 KT |
5287 | |
5288 | /* Detect the presence of a floating point or integer zero constant, | |
5289 | i.e. #0.0 or #0. */ | |
5290 | ||
5291 | static bfd_boolean | |
5292 | parse_ifimm_zero (char **in) | |
5293 | { | |
5294 | int error_code; | |
5295 | ||
5296 | if (!is_immediate_prefix (**in)) | |
3c6452ae TP |
5297 | { |
5298 | /* In unified syntax, all prefixes are optional. */ | |
5299 | if (!unified_syntax) | |
5300 | return FALSE; | |
5301 | } | |
5302 | else | |
5303 | ++*in; | |
0900a05b JW |
5304 | |
5305 | /* Accept #0x0 as a synonym for #0. */ | |
5306 | if (strncmp (*in, "0x", 2) == 0) | |
5307 | { | |
5308 | int val; | |
5309 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) | |
5310 | return FALSE; | |
5311 | return TRUE; | |
5312 | } | |
5313 | ||
aacf0b33 KT |
5314 | error_code = atof_generic (in, ".", EXP_CHARS, |
5315 | &generic_floating_point_number); | |
5316 | ||
5317 | if (!error_code | |
5318 | && generic_floating_point_number.sign == '+' | |
5319 | && (generic_floating_point_number.low | |
5320 | > generic_floating_point_number.leader)) | |
5321 | return TRUE; | |
5322 | ||
5323 | return FALSE; | |
5324 | } | |
5325 | ||
136da414 JB |
5326 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
5327 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
5328 | The zero and minus-zero cases need special handling, since they can't be |
5329 | encoded in the "quarter-precision" float format, but can nonetheless be | |
5330 | loaded as integer constants. */ | |
136da414 JB |
5331 | |
5332 | static unsigned | |
5333 | parse_qfloat_immediate (char **ccp, int *immed) | |
5334 | { | |
5335 | char *str = *ccp; | |
c96612cc | 5336 | char *fpnum; |
136da414 | 5337 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 5338 | int found_fpchar = 0; |
5f4273c7 | 5339 | |
136da414 | 5340 | skip_past_char (&str, '#'); |
5f4273c7 | 5341 | |
c96612cc JB |
5342 | /* We must not accidentally parse an integer as a floating-point number. Make |
5343 | sure that the value we parse is not an integer by checking for special | |
5344 | characters '.' or 'e'. | |
5345 | FIXME: This is a horrible hack, but doing better is tricky because type | |
5346 | information isn't in a very usable state at parse time. */ | |
5347 | fpnum = str; | |
5348 | skip_whitespace (fpnum); | |
5349 | ||
5350 | if (strncmp (fpnum, "0x", 2) == 0) | |
5351 | return FAIL; | |
5352 | else | |
5353 | { | |
5354 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
5355 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
5356 | { | |
5357 | found_fpchar = 1; | |
5358 | break; | |
5359 | } | |
c96612cc JB |
5360 | |
5361 | if (!found_fpchar) | |
477330fc | 5362 | return FAIL; |
c96612cc | 5363 | } |
5f4273c7 | 5364 | |
136da414 JB |
5365 | if ((str = atof_ieee (str, 's', words)) != NULL) |
5366 | { | |
5367 | unsigned fpword = 0; | |
5368 | int i; | |
5f4273c7 | 5369 | |
136da414 JB |
5370 | /* Our FP word must be 32 bits (single-precision FP). */ |
5371 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
5372 | { |
5373 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5374 | fpword |= words[i]; | |
5375 | } | |
5f4273c7 | 5376 | |
c96612cc | 5377 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5378 | *immed = fpword; |
136da414 | 5379 | else |
477330fc | 5380 | return FAIL; |
136da414 JB |
5381 | |
5382 | *ccp = str; | |
5f4273c7 | 5383 | |
136da414 JB |
5384 | return SUCCESS; |
5385 | } | |
5f4273c7 | 5386 | |
136da414 JB |
5387 | return FAIL; |
5388 | } | |
5389 | ||
c19d1205 ZW |
5390 | /* Shift operands. */ |
5391 | enum shift_kind | |
b99bd4ef | 5392 | { |
f5f10c66 | 5393 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW |
c19d1205 | 5394 | }; |
b99bd4ef | 5395 | |
c19d1205 ZW |
5396 | struct asm_shift_name |
5397 | { | |
5398 | const char *name; | |
5399 | enum shift_kind kind; | |
5400 | }; | |
b99bd4ef | 5401 | |
c19d1205 ZW |
5402 | /* Third argument to parse_shift. */ |
5403 | enum parse_shift_mode | |
5404 | { | |
5405 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5406 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5407 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5408 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5409 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
f5f10c66 | 5410 | SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */ |
c19d1205 | 5411 | }; |
b99bd4ef | 5412 | |
c19d1205 ZW |
5413 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5414 | This has three forms: | |
b99bd4ef | 5415 | |
c19d1205 ZW |
5416 | (LSL|LSR|ASL|ASR|ROR) Rs |
5417 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5418 | RRX | |
b99bd4ef | 5419 | |
c19d1205 ZW |
5420 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5421 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5422 | |
c19d1205 ZW |
5423 | static int |
5424 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5425 | { |
c19d1205 ZW |
5426 | const struct asm_shift_name *shift_name; |
5427 | enum shift_kind shift; | |
5428 | char *s = *str; | |
5429 | char *p = s; | |
5430 | int reg; | |
b99bd4ef | 5431 | |
c19d1205 ZW |
5432 | for (p = *str; ISALPHA (*p); p++) |
5433 | ; | |
b99bd4ef | 5434 | |
c19d1205 | 5435 | if (p == *str) |
b99bd4ef | 5436 | { |
c19d1205 ZW |
5437 | inst.error = _("shift expression expected"); |
5438 | return FAIL; | |
b99bd4ef NC |
5439 | } |
5440 | ||
21d799b5 | 5441 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5442 | p - *str); |
c19d1205 ZW |
5443 | |
5444 | if (shift_name == NULL) | |
b99bd4ef | 5445 | { |
c19d1205 ZW |
5446 | inst.error = _("shift expression expected"); |
5447 | return FAIL; | |
b99bd4ef NC |
5448 | } |
5449 | ||
c19d1205 | 5450 | shift = shift_name->kind; |
b99bd4ef | 5451 | |
c19d1205 ZW |
5452 | switch (mode) |
5453 | { | |
5454 | case NO_SHIFT_RESTRICT: | |
f5f10c66 AV |
5455 | case SHIFT_IMMEDIATE: |
5456 | if (shift == SHIFT_UXTW) | |
5457 | { | |
5458 | inst.error = _("'UXTW' not allowed here"); | |
5459 | return FAIL; | |
5460 | } | |
5461 | break; | |
b99bd4ef | 5462 | |
c19d1205 ZW |
5463 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5464 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5465 | { | |
5466 | inst.error = _("'LSL' or 'ASR' required"); | |
5467 | return FAIL; | |
5468 | } | |
5469 | break; | |
b99bd4ef | 5470 | |
c19d1205 ZW |
5471 | case SHIFT_LSL_IMMEDIATE: |
5472 | if (shift != SHIFT_LSL) | |
5473 | { | |
5474 | inst.error = _("'LSL' required"); | |
5475 | return FAIL; | |
5476 | } | |
5477 | break; | |
b99bd4ef | 5478 | |
c19d1205 ZW |
5479 | case SHIFT_ASR_IMMEDIATE: |
5480 | if (shift != SHIFT_ASR) | |
5481 | { | |
5482 | inst.error = _("'ASR' required"); | |
5483 | return FAIL; | |
5484 | } | |
5485 | break; | |
f5f10c66 AV |
5486 | case SHIFT_UXTW_IMMEDIATE: |
5487 | if (shift != SHIFT_UXTW) | |
5488 | { | |
5489 | inst.error = _("'UXTW' required"); | |
5490 | return FAIL; | |
5491 | } | |
5492 | break; | |
b99bd4ef | 5493 | |
c19d1205 ZW |
5494 | default: abort (); |
5495 | } | |
b99bd4ef | 5496 | |
c19d1205 ZW |
5497 | if (shift != SHIFT_RRX) |
5498 | { | |
5499 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5500 | skip_whitespace (p); | |
b99bd4ef | 5501 | |
c19d1205 | 5502 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5503 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5504 | { |
5505 | inst.operands[i].imm = reg; | |
5506 | inst.operands[i].immisreg = 1; | |
5507 | } | |
e2b0ab59 | 5508 | else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
c19d1205 ZW |
5509 | return FAIL; |
5510 | } | |
5511 | inst.operands[i].shift_kind = shift; | |
5512 | inst.operands[i].shifted = 1; | |
5513 | *str = p; | |
5514 | return SUCCESS; | |
b99bd4ef NC |
5515 | } |
5516 | ||
c19d1205 | 5517 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5518 | |
c19d1205 ZW |
5519 | #<immediate> |
5520 | #<immediate>, <rotate> | |
5521 | <Rm> | |
5522 | <Rm>, <shift> | |
b99bd4ef | 5523 | |
c19d1205 ZW |
5524 | where <shift> is defined by parse_shift above, and <rotate> is a |
5525 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5526 | is deferred to md_apply_fix. */ |
b99bd4ef | 5527 | |
c19d1205 ZW |
5528 | static int |
5529 | parse_shifter_operand (char **str, int i) | |
5530 | { | |
5531 | int value; | |
91d6fa6a | 5532 | expressionS exp; |
b99bd4ef | 5533 | |
dcbf9037 | 5534 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5535 | { |
5536 | inst.operands[i].reg = value; | |
5537 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5538 | |
c19d1205 | 5539 | /* parse_shift will override this if appropriate */ |
e2b0ab59 AV |
5540 | inst.relocs[0].exp.X_op = O_constant; |
5541 | inst.relocs[0].exp.X_add_number = 0; | |
b99bd4ef | 5542 | |
c19d1205 ZW |
5543 | if (skip_past_comma (str) == FAIL) |
5544 | return SUCCESS; | |
b99bd4ef | 5545 | |
c19d1205 ZW |
5546 | /* Shift operation on register. */ |
5547 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5548 | } |
5549 | ||
e2b0ab59 | 5550 | if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX)) |
c19d1205 | 5551 | return FAIL; |
b99bd4ef | 5552 | |
c19d1205 | 5553 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5554 | { |
c19d1205 | 5555 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5556 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5557 | return FAIL; |
b99bd4ef | 5558 | |
e2b0ab59 | 5559 | if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant) |
c19d1205 ZW |
5560 | { |
5561 | inst.error = _("constant expression expected"); | |
5562 | return FAIL; | |
5563 | } | |
b99bd4ef | 5564 | |
91d6fa6a | 5565 | value = exp.X_add_number; |
c19d1205 ZW |
5566 | if (value < 0 || value > 30 || value % 2 != 0) |
5567 | { | |
5568 | inst.error = _("invalid rotation"); | |
5569 | return FAIL; | |
5570 | } | |
e2b0ab59 AV |
5571 | if (inst.relocs[0].exp.X_add_number < 0 |
5572 | || inst.relocs[0].exp.X_add_number > 255) | |
c19d1205 ZW |
5573 | { |
5574 | inst.error = _("invalid constant"); | |
5575 | return FAIL; | |
5576 | } | |
09d92015 | 5577 | |
a415b1cd | 5578 | /* Encode as specified. */ |
e2b0ab59 | 5579 | inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7; |
a415b1cd | 5580 | return SUCCESS; |
09d92015 MM |
5581 | } |
5582 | ||
e2b0ab59 AV |
5583 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
5584 | inst.relocs[0].pc_rel = 0; | |
c19d1205 | 5585 | return SUCCESS; |
09d92015 MM |
5586 | } |
5587 | ||
4962c51a MS |
5588 | /* Group relocation information. Each entry in the table contains the |
5589 | textual name of the relocation as may appear in assembler source | |
5590 | and must end with a colon. | |
5591 | Along with this textual name are the relocation codes to be used if | |
5592 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5593 | an LDR, an LDRS, or an LDC. */ | |
5594 | ||
5595 | struct group_reloc_table_entry | |
5596 | { | |
5597 | const char *name; | |
5598 | int alu_code; | |
5599 | int ldr_code; | |
5600 | int ldrs_code; | |
5601 | int ldc_code; | |
5602 | }; | |
5603 | ||
5604 | typedef enum | |
5605 | { | |
5606 | /* Varieties of non-ALU group relocation. */ | |
5607 | ||
5608 | GROUP_LDR, | |
5609 | GROUP_LDRS, | |
35c228db AV |
5610 | GROUP_LDC, |
5611 | GROUP_MVE | |
4962c51a MS |
5612 | } group_reloc_type; |
5613 | ||
5614 | static struct group_reloc_table_entry group_reloc_table[] = | |
5615 | { /* Program counter relative: */ | |
5616 | { "pc_g0_nc", | |
5617 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5618 | 0, /* LDR */ | |
5619 | 0, /* LDRS */ | |
5620 | 0 }, /* LDC */ | |
5621 | { "pc_g0", | |
5622 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5623 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5624 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5625 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5626 | { "pc_g1_nc", | |
5627 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5628 | 0, /* LDR */ | |
5629 | 0, /* LDRS */ | |
5630 | 0 }, /* LDC */ | |
5631 | { "pc_g1", | |
5632 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5633 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5634 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5635 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5636 | { "pc_g2", | |
5637 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5638 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5639 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5640 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5641 | /* Section base relative */ | |
5642 | { "sb_g0_nc", | |
5643 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5644 | 0, /* LDR */ | |
5645 | 0, /* LDRS */ | |
5646 | 0 }, /* LDC */ | |
5647 | { "sb_g0", | |
5648 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5649 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5650 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5651 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5652 | { "sb_g1_nc", | |
5653 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5654 | 0, /* LDR */ | |
5655 | 0, /* LDRS */ | |
5656 | 0 }, /* LDC */ | |
5657 | { "sb_g1", | |
5658 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5659 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5660 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5661 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5662 | { "sb_g2", | |
5663 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5664 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5665 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
72d98d16 MG |
5666 | BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */ |
5667 | /* Absolute thumb alu relocations. */ | |
5668 | { "lower0_7", | |
5669 | BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */ | |
5670 | 0, /* LDR. */ | |
5671 | 0, /* LDRS. */ | |
5672 | 0 }, /* LDC. */ | |
5673 | { "lower8_15", | |
5674 | BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */ | |
5675 | 0, /* LDR. */ | |
5676 | 0, /* LDRS. */ | |
5677 | 0 }, /* LDC. */ | |
5678 | { "upper0_7", | |
5679 | BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */ | |
5680 | 0, /* LDR. */ | |
5681 | 0, /* LDRS. */ | |
5682 | 0 }, /* LDC. */ | |
5683 | { "upper8_15", | |
5684 | BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */ | |
5685 | 0, /* LDR. */ | |
5686 | 0, /* LDRS. */ | |
5687 | 0 } }; /* LDC. */ | |
4962c51a MS |
5688 | |
5689 | /* Given the address of a pointer pointing to the textual name of a group | |
5690 | relocation as may appear in assembler source, attempt to find its details | |
5691 | in group_reloc_table. The pointer will be updated to the character after | |
5692 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5693 | otherwise. On success, *entry will be updated to point at the relevant | |
5694 | group_reloc_table entry. */ | |
5695 | ||
5696 | static int | |
5697 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5698 | { | |
5699 | unsigned int i; | |
5700 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5701 | { | |
5702 | int length = strlen (group_reloc_table[i].name); | |
5703 | ||
5f4273c7 NC |
5704 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5705 | && (*str)[length] == ':') | |
477330fc RM |
5706 | { |
5707 | *out = &group_reloc_table[i]; | |
5708 | *str += (length + 1); | |
5709 | return SUCCESS; | |
5710 | } | |
4962c51a MS |
5711 | } |
5712 | ||
5713 | return FAIL; | |
5714 | } | |
5715 | ||
5716 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5717 | (as for parse_shifter_operand) where group relocations are allowed: | |
5718 | ||
5719 | #<immediate> | |
5720 | #<immediate>, <rotate> | |
5721 | #:<group_reloc>:<expression> | |
5722 | <Rm> | |
5723 | <Rm>, <shift> | |
5724 | ||
5725 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5726 | The hashes are optional. | |
5727 | ||
5728 | Everything else is as for parse_shifter_operand. */ | |
5729 | ||
5730 | static parse_operand_result | |
5731 | parse_shifter_operand_group_reloc (char **str, int i) | |
5732 | { | |
5733 | /* Determine if we have the sequence of characters #: or just : | |
5734 | coming next. If we do, then we check for a group relocation. | |
5735 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5736 | ||
5737 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5738 | || (*str)[0] == ':') | |
5739 | { | |
5740 | struct group_reloc_table_entry *entry; | |
5741 | ||
5742 | if ((*str)[0] == '#') | |
477330fc | 5743 | (*str) += 2; |
4962c51a | 5744 | else |
477330fc | 5745 | (*str)++; |
4962c51a MS |
5746 | |
5747 | /* Try to parse a group relocation. Anything else is an error. */ | |
5748 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5749 | { |
5750 | inst.error = _("unknown group relocation"); | |
5751 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5752 | } | |
4962c51a MS |
5753 | |
5754 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5755 | the name in the assembler source. Next, we parse the expression. */ |
e2b0ab59 | 5756 | if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX)) |
477330fc | 5757 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5758 | |
5759 | /* Record the relocation type (always the ALU variant here). */ | |
e2b0ab59 AV |
5760 | inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code; |
5761 | gas_assert (inst.relocs[0].type != 0); | |
4962c51a MS |
5762 | |
5763 | return PARSE_OPERAND_SUCCESS; | |
5764 | } | |
5765 | else | |
5766 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5767 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5768 | |
5769 | /* Never reached. */ | |
5770 | } | |
5771 | ||
8e560766 MGD |
5772 | /* Parse a Neon alignment expression. Information is written to |
5773 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5774 | |
8e560766 MGD |
5775 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5776 | static parse_operand_result | |
5777 | parse_neon_alignment (char **str, int i) | |
5778 | { | |
5779 | char *p = *str; | |
5780 | expressionS exp; | |
5781 | ||
5782 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5783 | ||
5784 | if (exp.X_op != O_constant) | |
5785 | { | |
5786 | inst.error = _("alignment must be constant"); | |
5787 | return PARSE_OPERAND_FAIL; | |
5788 | } | |
5789 | ||
5790 | inst.operands[i].imm = exp.X_add_number << 8; | |
5791 | inst.operands[i].immisalign = 1; | |
5792 | /* Alignments are not pre-indexes. */ | |
5793 | inst.operands[i].preind = 0; | |
5794 | ||
5795 | *str = p; | |
5796 | return PARSE_OPERAND_SUCCESS; | |
5797 | } | |
5798 | ||
c19d1205 | 5799 | /* Parse all forms of an ARM address expression. Information is written |
e2b0ab59 | 5800 | to inst.operands[i] and/or inst.relocs[0]. |
09d92015 | 5801 | |
c19d1205 | 5802 | Preindexed addressing (.preind=1): |
09d92015 | 5803 | |
e2b0ab59 | 5804 | [Rn, #offset] .reg=Rn .relocs[0].exp=offset |
c19d1205 ZW |
5805 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
5806 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
e2b0ab59 | 5807 | .shift_kind=shift .relocs[0].exp=shift_imm |
09d92015 | 5808 | |
c19d1205 | 5809 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5810 | |
c19d1205 | 5811 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5812 | |
e2b0ab59 | 5813 | [Rn], #offset .reg=Rn .relocs[0].exp=offset |
c19d1205 ZW |
5814 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 |
5815 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
e2b0ab59 | 5816 | .shift_kind=shift .relocs[0].exp=shift_imm |
09d92015 | 5817 | |
c19d1205 | 5818 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5819 | |
c19d1205 | 5820 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5821 | |
c19d1205 | 5822 | Other: |
09d92015 | 5823 | |
c19d1205 | 5824 | [Rn]{!} shorthand for [Rn,#0]{!} |
e2b0ab59 AV |
5825 | =immediate .isreg=0 .relocs[0].exp=immediate |
5826 | label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label | |
09d92015 | 5827 | |
c19d1205 | 5828 | It is the caller's responsibility to check for addressing modes not |
e2b0ab59 | 5829 | supported by the instruction, and to set inst.relocs[0].type. */ |
c19d1205 | 5830 | |
4962c51a MS |
5831 | static parse_operand_result |
5832 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5833 | group_reloc_type group_type) |
09d92015 | 5834 | { |
c19d1205 ZW |
5835 | char *p = *str; |
5836 | int reg; | |
09d92015 | 5837 | |
c19d1205 | 5838 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5839 | { |
c19d1205 ZW |
5840 | if (skip_past_char (&p, '=') == FAIL) |
5841 | { | |
974da60d | 5842 | /* Bare address - translate to PC-relative offset. */ |
e2b0ab59 | 5843 | inst.relocs[0].pc_rel = 1; |
c19d1205 ZW |
5844 | inst.operands[i].reg = REG_PC; |
5845 | inst.operands[i].isreg = 1; | |
5846 | inst.operands[i].preind = 1; | |
09d92015 | 5847 | |
e2b0ab59 | 5848 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG)) |
8335d6aa JW |
5849 | return PARSE_OPERAND_FAIL; |
5850 | } | |
e2b0ab59 | 5851 | else if (parse_big_immediate (&p, i, &inst.relocs[0].exp, |
8335d6aa | 5852 | /*allow_symbol_p=*/TRUE)) |
4962c51a | 5853 | return PARSE_OPERAND_FAIL; |
09d92015 | 5854 | |
c19d1205 | 5855 | *str = p; |
4962c51a | 5856 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5857 | } |
5858 | ||
8ab8155f NC |
5859 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5860 | skip_whitespace (p); | |
5861 | ||
f5f10c66 AV |
5862 | if (group_type == GROUP_MVE) |
5863 | { | |
5864 | enum arm_reg_type rtype = REG_TYPE_MQ; | |
5865 | struct neon_type_el et; | |
5866 | if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) | |
5867 | { | |
5868 | inst.operands[i].isquad = 1; | |
5869 | } | |
5870 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
5871 | { | |
5872 | inst.error = BAD_ADDR_MODE; | |
5873 | return PARSE_OPERAND_FAIL; | |
5874 | } | |
5875 | } | |
5876 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
09d92015 | 5877 | { |
35c228db AV |
5878 | if (group_type == GROUP_MVE) |
5879 | inst.error = BAD_ADDR_MODE; | |
5880 | else | |
5881 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
4962c51a | 5882 | return PARSE_OPERAND_FAIL; |
09d92015 | 5883 | } |
c19d1205 ZW |
5884 | inst.operands[i].reg = reg; |
5885 | inst.operands[i].isreg = 1; | |
09d92015 | 5886 | |
c19d1205 | 5887 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5888 | { |
c19d1205 | 5889 | inst.operands[i].preind = 1; |
09d92015 | 5890 | |
c19d1205 ZW |
5891 | if (*p == '+') p++; |
5892 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5893 | ||
f5f10c66 AV |
5894 | enum arm_reg_type rtype = REG_TYPE_MQ; |
5895 | struct neon_type_el et; | |
5896 | if (group_type == GROUP_MVE | |
5897 | && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) | |
5898 | { | |
5899 | inst.operands[i].immisreg = 2; | |
5900 | inst.operands[i].imm = reg; | |
5901 | ||
5902 | if (skip_past_comma (&p) == SUCCESS) | |
5903 | { | |
5904 | if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS) | |
5905 | { | |
5906 | inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5; | |
5907 | inst.relocs[0].exp.X_add_number = 0; | |
5908 | } | |
5909 | else | |
5910 | return PARSE_OPERAND_FAIL; | |
5911 | } | |
5912 | } | |
5913 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
09d92015 | 5914 | { |
c19d1205 ZW |
5915 | inst.operands[i].imm = reg; |
5916 | inst.operands[i].immisreg = 1; | |
5917 | ||
5918 | if (skip_past_comma (&p) == SUCCESS) | |
5919 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5920 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5921 | } |
5287ad62 | 5922 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5923 | { |
5924 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5925 | code before we get to see it here. This may be subject to | |
5926 | change. */ | |
5927 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5928 | |
8e560766 MGD |
5929 | if (result != PARSE_OPERAND_SUCCESS) |
5930 | return result; | |
5931 | } | |
c19d1205 ZW |
5932 | else |
5933 | { | |
5934 | if (inst.operands[i].negative) | |
5935 | { | |
5936 | inst.operands[i].negative = 0; | |
5937 | p--; | |
5938 | } | |
4962c51a | 5939 | |
5f4273c7 NC |
5940 | if (group_relocations |
5941 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5942 | { |
5943 | struct group_reloc_table_entry *entry; | |
5944 | ||
477330fc RM |
5945 | /* Skip over the #: or : sequence. */ |
5946 | if (*p == '#') | |
5947 | p += 2; | |
5948 | else | |
5949 | p++; | |
4962c51a MS |
5950 | |
5951 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5952 | error. */ |
4962c51a MS |
5953 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5954 | { | |
5955 | inst.error = _("unknown group relocation"); | |
5956 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5957 | } | |
5958 | ||
5959 | /* We now have the group relocation table entry corresponding to | |
5960 | the name in the assembler source. Next, we parse the | |
477330fc | 5961 | expression. */ |
e2b0ab59 | 5962 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX)) |
4962c51a MS |
5963 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
5964 | ||
5965 | /* Record the relocation type. */ | |
477330fc RM |
5966 | switch (group_type) |
5967 | { | |
5968 | case GROUP_LDR: | |
e2b0ab59 AV |
5969 | inst.relocs[0].type |
5970 | = (bfd_reloc_code_real_type) entry->ldr_code; | |
477330fc | 5971 | break; |
4962c51a | 5972 | |
477330fc | 5973 | case GROUP_LDRS: |
e2b0ab59 AV |
5974 | inst.relocs[0].type |
5975 | = (bfd_reloc_code_real_type) entry->ldrs_code; | |
477330fc | 5976 | break; |
4962c51a | 5977 | |
477330fc | 5978 | case GROUP_LDC: |
e2b0ab59 AV |
5979 | inst.relocs[0].type |
5980 | = (bfd_reloc_code_real_type) entry->ldc_code; | |
477330fc | 5981 | break; |
4962c51a | 5982 | |
477330fc RM |
5983 | default: |
5984 | gas_assert (0); | |
5985 | } | |
4962c51a | 5986 | |
e2b0ab59 | 5987 | if (inst.relocs[0].type == 0) |
4962c51a MS |
5988 | { |
5989 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5990 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5991 | } | |
477330fc RM |
5992 | } |
5993 | else | |
26d97720 NS |
5994 | { |
5995 | char *q = p; | |
0198d5e6 | 5996 | |
e2b0ab59 | 5997 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
26d97720 NS |
5998 | return PARSE_OPERAND_FAIL; |
5999 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
e2b0ab59 AV |
6000 | if (inst.relocs[0].exp.X_op == O_constant |
6001 | && inst.relocs[0].exp.X_add_number == 0) | |
26d97720 NS |
6002 | { |
6003 | skip_whitespace (q); | |
6004 | if (*q == '#') | |
6005 | { | |
6006 | q++; | |
6007 | skip_whitespace (q); | |
6008 | } | |
6009 | if (*q == '-') | |
6010 | inst.operands[i].negative = 1; | |
6011 | } | |
6012 | } | |
09d92015 MM |
6013 | } |
6014 | } | |
8e560766 MGD |
6015 | else if (skip_past_char (&p, ':') == SUCCESS) |
6016 | { | |
6017 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
6018 | before we get to see it here. This may be subject to change. */ | |
6019 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 6020 | |
8e560766 MGD |
6021 | if (result != PARSE_OPERAND_SUCCESS) |
6022 | return result; | |
6023 | } | |
09d92015 | 6024 | |
c19d1205 | 6025 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 6026 | { |
c19d1205 | 6027 | inst.error = _("']' expected"); |
4962c51a | 6028 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
6029 | } |
6030 | ||
c19d1205 ZW |
6031 | if (skip_past_char (&p, '!') == SUCCESS) |
6032 | inst.operands[i].writeback = 1; | |
09d92015 | 6033 | |
c19d1205 | 6034 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 6035 | { |
c19d1205 ZW |
6036 | if (skip_past_char (&p, '{') == SUCCESS) |
6037 | { | |
6038 | /* [Rn], {expr} - unindexed, with option */ | |
6039 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 6040 | 0, 255, TRUE) == FAIL) |
4962c51a | 6041 | return PARSE_OPERAND_FAIL; |
09d92015 | 6042 | |
c19d1205 ZW |
6043 | if (skip_past_char (&p, '}') == FAIL) |
6044 | { | |
6045 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 6046 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
6047 | } |
6048 | if (inst.operands[i].preind) | |
6049 | { | |
6050 | inst.error = _("cannot combine index with option"); | |
4962c51a | 6051 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
6052 | } |
6053 | *str = p; | |
4962c51a | 6054 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 6055 | } |
c19d1205 ZW |
6056 | else |
6057 | { | |
6058 | inst.operands[i].postind = 1; | |
6059 | inst.operands[i].writeback = 1; | |
09d92015 | 6060 | |
c19d1205 ZW |
6061 | if (inst.operands[i].preind) |
6062 | { | |
6063 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 6064 | return PARSE_OPERAND_FAIL; |
c19d1205 | 6065 | } |
09d92015 | 6066 | |
c19d1205 ZW |
6067 | if (*p == '+') p++; |
6068 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 6069 | |
f5f10c66 AV |
6070 | enum arm_reg_type rtype = REG_TYPE_MQ; |
6071 | struct neon_type_el et; | |
6072 | if (group_type == GROUP_MVE | |
6073 | && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL) | |
6074 | { | |
6075 | inst.operands[i].immisreg = 2; | |
6076 | inst.operands[i].imm = reg; | |
6077 | } | |
6078 | else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
c19d1205 | 6079 | { |
477330fc RM |
6080 | /* We might be using the immediate for alignment already. If we |
6081 | are, OR the register number into the low-order bits. */ | |
6082 | if (inst.operands[i].immisalign) | |
6083 | inst.operands[i].imm |= reg; | |
6084 | else | |
6085 | inst.operands[i].imm = reg; | |
c19d1205 | 6086 | inst.operands[i].immisreg = 1; |
a737bd4d | 6087 | |
c19d1205 ZW |
6088 | if (skip_past_comma (&p) == SUCCESS) |
6089 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 6090 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
6091 | } |
6092 | else | |
6093 | { | |
26d97720 | 6094 | char *q = p; |
0198d5e6 | 6095 | |
c19d1205 ZW |
6096 | if (inst.operands[i].negative) |
6097 | { | |
6098 | inst.operands[i].negative = 0; | |
6099 | p--; | |
6100 | } | |
e2b0ab59 | 6101 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX)) |
4962c51a | 6102 | return PARSE_OPERAND_FAIL; |
26d97720 | 6103 | /* If the offset is 0, find out if it's a +0 or -0. */ |
e2b0ab59 AV |
6104 | if (inst.relocs[0].exp.X_op == O_constant |
6105 | && inst.relocs[0].exp.X_add_number == 0) | |
26d97720 NS |
6106 | { |
6107 | skip_whitespace (q); | |
6108 | if (*q == '#') | |
6109 | { | |
6110 | q++; | |
6111 | skip_whitespace (q); | |
6112 | } | |
6113 | if (*q == '-') | |
6114 | inst.operands[i].negative = 1; | |
6115 | } | |
c19d1205 ZW |
6116 | } |
6117 | } | |
a737bd4d NC |
6118 | } |
6119 | ||
c19d1205 ZW |
6120 | /* If at this point neither .preind nor .postind is set, we have a |
6121 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
6122 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
6123 | { | |
6124 | inst.operands[i].preind = 1; | |
e2b0ab59 AV |
6125 | inst.relocs[0].exp.X_op = O_constant; |
6126 | inst.relocs[0].exp.X_add_number = 0; | |
c19d1205 ZW |
6127 | } |
6128 | *str = p; | |
4962c51a MS |
6129 | return PARSE_OPERAND_SUCCESS; |
6130 | } | |
6131 | ||
6132 | static int | |
6133 | parse_address (char **str, int i) | |
6134 | { | |
21d799b5 | 6135 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 6136 | ? SUCCESS : FAIL; |
4962c51a MS |
6137 | } |
6138 | ||
6139 | static parse_operand_result | |
6140 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
6141 | { | |
6142 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
6143 | } |
6144 | ||
b6895b4f PB |
6145 | /* Parse an operand for a MOVW or MOVT instruction. */ |
6146 | static int | |
6147 | parse_half (char **str) | |
6148 | { | |
6149 | char * p; | |
5f4273c7 | 6150 | |
b6895b4f PB |
6151 | p = *str; |
6152 | skip_past_char (&p, '#'); | |
5f4273c7 | 6153 | if (strncasecmp (p, ":lower16:", 9) == 0) |
e2b0ab59 | 6154 | inst.relocs[0].type = BFD_RELOC_ARM_MOVW; |
b6895b4f | 6155 | else if (strncasecmp (p, ":upper16:", 9) == 0) |
e2b0ab59 | 6156 | inst.relocs[0].type = BFD_RELOC_ARM_MOVT; |
b6895b4f | 6157 | |
e2b0ab59 | 6158 | if (inst.relocs[0].type != BFD_RELOC_UNUSED) |
b6895b4f PB |
6159 | { |
6160 | p += 9; | |
5f4273c7 | 6161 | skip_whitespace (p); |
b6895b4f PB |
6162 | } |
6163 | ||
e2b0ab59 | 6164 | if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX)) |
b6895b4f PB |
6165 | return FAIL; |
6166 | ||
e2b0ab59 | 6167 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
b6895b4f | 6168 | { |
e2b0ab59 | 6169 | if (inst.relocs[0].exp.X_op != O_constant) |
b6895b4f PB |
6170 | { |
6171 | inst.error = _("constant expression expected"); | |
6172 | return FAIL; | |
6173 | } | |
e2b0ab59 AV |
6174 | if (inst.relocs[0].exp.X_add_number < 0 |
6175 | || inst.relocs[0].exp.X_add_number > 0xffff) | |
b6895b4f PB |
6176 | { |
6177 | inst.error = _("immediate value out of range"); | |
6178 | return FAIL; | |
6179 | } | |
6180 | } | |
6181 | *str = p; | |
6182 | return SUCCESS; | |
6183 | } | |
6184 | ||
c19d1205 | 6185 | /* Miscellaneous. */ |
a737bd4d | 6186 | |
c19d1205 ZW |
6187 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
6188 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
6189 | static int | |
d2cd1205 | 6190 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 6191 | { |
c19d1205 ZW |
6192 | char *p; |
6193 | unsigned long psr_field; | |
62b3e311 PB |
6194 | const struct asm_psr *psr; |
6195 | char *start; | |
d2cd1205 | 6196 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 6197 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 6198 | |
a4482bb6 NC |
6199 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
6200 | be TRUE, but we want to ignore it in this case as we are building for any | |
6201 | CPU type, including non-m variants. */ | |
823d2571 | 6202 | if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) |
a4482bb6 NC |
6203 | m_profile = FALSE; |
6204 | ||
c19d1205 ZW |
6205 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
6206 | feature for ease of use and backwards compatibility. */ | |
6207 | p = *str; | |
62b3e311 | 6208 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
6209 | { |
6210 | if (m_profile) | |
6211 | goto unsupported_psr; | |
fa94de6b | 6212 | |
d2cd1205 JB |
6213 | psr_field = SPSR_BIT; |
6214 | } | |
6215 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
6216 | { | |
6217 | if (m_profile) | |
6218 | goto unsupported_psr; | |
6219 | ||
6220 | psr_field = 0; | |
6221 | } | |
6222 | else if (strncasecmp (p, "APSR", 4) == 0) | |
6223 | { | |
6224 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
6225 | and ARMv7-R architecture CPUs. */ | |
6226 | is_apsr = TRUE; | |
6227 | psr_field = 0; | |
6228 | } | |
6229 | else if (m_profile) | |
62b3e311 PB |
6230 | { |
6231 | start = p; | |
6232 | do | |
6233 | p++; | |
6234 | while (ISALNUM (*p) || *p == '_'); | |
6235 | ||
d2cd1205 JB |
6236 | if (strncasecmp (start, "iapsr", 5) == 0 |
6237 | || strncasecmp (start, "eapsr", 5) == 0 | |
6238 | || strncasecmp (start, "xpsr", 4) == 0 | |
6239 | || strncasecmp (start, "psr", 3) == 0) | |
6240 | p = start + strcspn (start, "rR") + 1; | |
6241 | ||
21d799b5 | 6242 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 6243 | p - start); |
d2cd1205 | 6244 | |
62b3e311 PB |
6245 | if (!psr) |
6246 | return FAIL; | |
09d92015 | 6247 | |
d2cd1205 JB |
6248 | /* If APSR is being written, a bitfield may be specified. Note that |
6249 | APSR itself is handled above. */ | |
6250 | if (psr->field <= 3) | |
6251 | { | |
6252 | psr_field = psr->field; | |
6253 | is_apsr = TRUE; | |
6254 | goto check_suffix; | |
6255 | } | |
6256 | ||
62b3e311 | 6257 | *str = p; |
d2cd1205 JB |
6258 | /* M-profile MSR instructions have the mask field set to "10", except |
6259 | *PSR variants which modify APSR, which may use a different mask (and | |
6260 | have been handled already). Do that by setting the PSR_f field | |
6261 | here. */ | |
6262 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 6263 | } |
d2cd1205 JB |
6264 | else |
6265 | goto unsupported_psr; | |
09d92015 | 6266 | |
62b3e311 | 6267 | p += 4; |
d2cd1205 | 6268 | check_suffix: |
c19d1205 ZW |
6269 | if (*p == '_') |
6270 | { | |
6271 | /* A suffix follows. */ | |
c19d1205 ZW |
6272 | p++; |
6273 | start = p; | |
a737bd4d | 6274 | |
c19d1205 ZW |
6275 | do |
6276 | p++; | |
6277 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 6278 | |
d2cd1205 JB |
6279 | if (is_apsr) |
6280 | { | |
6281 | /* APSR uses a notation for bits, rather than fields. */ | |
6282 | unsigned int nzcvq_bits = 0; | |
6283 | unsigned int g_bit = 0; | |
6284 | char *bit; | |
fa94de6b | 6285 | |
d2cd1205 JB |
6286 | for (bit = start; bit != p; bit++) |
6287 | { | |
6288 | switch (TOLOWER (*bit)) | |
477330fc | 6289 | { |
d2cd1205 JB |
6290 | case 'n': |
6291 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
6292 | break; | |
6293 | ||
6294 | case 'z': | |
6295 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
6296 | break; | |
6297 | ||
6298 | case 'c': | |
6299 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
6300 | break; | |
6301 | ||
6302 | case 'v': | |
6303 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
6304 | break; | |
fa94de6b | 6305 | |
d2cd1205 JB |
6306 | case 'q': |
6307 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
6308 | break; | |
fa94de6b | 6309 | |
d2cd1205 JB |
6310 | case 'g': |
6311 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
6312 | break; | |
fa94de6b | 6313 | |
d2cd1205 JB |
6314 | default: |
6315 | inst.error = _("unexpected bit specified after APSR"); | |
6316 | return FAIL; | |
6317 | } | |
6318 | } | |
fa94de6b | 6319 | |
d2cd1205 JB |
6320 | if (nzcvq_bits == 0x1f) |
6321 | psr_field |= PSR_f; | |
fa94de6b | 6322 | |
d2cd1205 JB |
6323 | if (g_bit == 0x1) |
6324 | { | |
6325 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 6326 | { |
d2cd1205 JB |
6327 | inst.error = _("selected processor does not " |
6328 | "support DSP extension"); | |
6329 | return FAIL; | |
6330 | } | |
6331 | ||
6332 | psr_field |= PSR_s; | |
6333 | } | |
fa94de6b | 6334 | |
d2cd1205 JB |
6335 | if ((nzcvq_bits & 0x20) != 0 |
6336 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
6337 | || (g_bit & 0x2) != 0) | |
6338 | { | |
6339 | inst.error = _("bad bitmask specified after APSR"); | |
6340 | return FAIL; | |
6341 | } | |
6342 | } | |
6343 | else | |
477330fc | 6344 | { |
d2cd1205 | 6345 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 6346 | p - start); |
d2cd1205 | 6347 | if (!psr) |
477330fc | 6348 | goto error; |
a737bd4d | 6349 | |
d2cd1205 JB |
6350 | psr_field |= psr->field; |
6351 | } | |
a737bd4d | 6352 | } |
c19d1205 | 6353 | else |
a737bd4d | 6354 | { |
c19d1205 ZW |
6355 | if (ISALNUM (*p)) |
6356 | goto error; /* Garbage after "[CS]PSR". */ | |
6357 | ||
d2cd1205 | 6358 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 6359 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
6360 | if (is_apsr && lhs) |
6361 | { | |
6362 | psr_field |= PSR_f; | |
6363 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
6364 | "deprecated")); | |
6365 | } | |
6366 | else if (!m_profile) | |
6367 | /* These bits are never right for M-profile devices: don't set them | |
6368 | (only code paths which read/write APSR reach here). */ | |
6369 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 6370 | } |
c19d1205 ZW |
6371 | *str = p; |
6372 | return psr_field; | |
a737bd4d | 6373 | |
d2cd1205 JB |
6374 | unsupported_psr: |
6375 | inst.error = _("selected processor does not support requested special " | |
6376 | "purpose register"); | |
6377 | return FAIL; | |
6378 | ||
c19d1205 ZW |
6379 | error: |
6380 | inst.error = _("flag for {c}psr instruction expected"); | |
6381 | return FAIL; | |
a737bd4d NC |
6382 | } |
6383 | ||
32c36c3c AV |
6384 | static int |
6385 | parse_sys_vldr_vstr (char **str) | |
6386 | { | |
6387 | unsigned i; | |
6388 | int val = FAIL; | |
6389 | struct { | |
6390 | const char *name; | |
6391 | int regl; | |
6392 | int regh; | |
6393 | } sysregs[] = { | |
6394 | {"FPSCR", 0x1, 0x0}, | |
6395 | {"FPSCR_nzcvqc", 0x2, 0x0}, | |
6396 | {"VPR", 0x4, 0x1}, | |
6397 | {"P0", 0x5, 0x1}, | |
6398 | {"FPCXTNS", 0x6, 0x1}, | |
6399 | {"FPCXTS", 0x7, 0x1} | |
6400 | }; | |
6401 | char *op_end = strchr (*str, ','); | |
6402 | size_t op_strlen = op_end - *str; | |
6403 | ||
6404 | for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++) | |
6405 | { | |
6406 | if (!strncmp (*str, sysregs[i].name, op_strlen)) | |
6407 | { | |
6408 | val = sysregs[i].regl | (sysregs[i].regh << 3); | |
6409 | *str = op_end; | |
6410 | break; | |
6411 | } | |
6412 | } | |
6413 | ||
6414 | return val; | |
6415 | } | |
6416 | ||
c19d1205 ZW |
6417 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
6418 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 6419 | |
c19d1205 ZW |
6420 | static int |
6421 | parse_cps_flags (char **str) | |
a737bd4d | 6422 | { |
c19d1205 ZW |
6423 | int val = 0; |
6424 | int saw_a_flag = 0; | |
6425 | char *s = *str; | |
a737bd4d | 6426 | |
c19d1205 ZW |
6427 | for (;;) |
6428 | switch (*s++) | |
6429 | { | |
6430 | case '\0': case ',': | |
6431 | goto done; | |
a737bd4d | 6432 | |
c19d1205 ZW |
6433 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
6434 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
6435 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 6436 | |
c19d1205 ZW |
6437 | default: |
6438 | inst.error = _("unrecognized CPS flag"); | |
6439 | return FAIL; | |
6440 | } | |
a737bd4d | 6441 | |
c19d1205 ZW |
6442 | done: |
6443 | if (saw_a_flag == 0) | |
a737bd4d | 6444 | { |
c19d1205 ZW |
6445 | inst.error = _("missing CPS flags"); |
6446 | return FAIL; | |
a737bd4d | 6447 | } |
a737bd4d | 6448 | |
c19d1205 ZW |
6449 | *str = s - 1; |
6450 | return val; | |
a737bd4d NC |
6451 | } |
6452 | ||
c19d1205 ZW |
6453 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
6454 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
6455 | |
6456 | static int | |
c19d1205 | 6457 | parse_endian_specifier (char **str) |
a737bd4d | 6458 | { |
c19d1205 ZW |
6459 | int little_endian; |
6460 | char *s = *str; | |
a737bd4d | 6461 | |
c19d1205 ZW |
6462 | if (strncasecmp (s, "BE", 2)) |
6463 | little_endian = 0; | |
6464 | else if (strncasecmp (s, "LE", 2)) | |
6465 | little_endian = 1; | |
6466 | else | |
a737bd4d | 6467 | { |
c19d1205 | 6468 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6469 | return FAIL; |
6470 | } | |
6471 | ||
c19d1205 | 6472 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 6473 | { |
c19d1205 | 6474 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
6475 | return FAIL; |
6476 | } | |
6477 | ||
c19d1205 ZW |
6478 | *str = s + 2; |
6479 | return little_endian; | |
6480 | } | |
a737bd4d | 6481 | |
c19d1205 ZW |
6482 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
6483 | value suitable for poking into the rotate field of an sxt or sxta | |
6484 | instruction, or FAIL on error. */ | |
6485 | ||
6486 | static int | |
6487 | parse_ror (char **str) | |
6488 | { | |
6489 | int rot; | |
6490 | char *s = *str; | |
6491 | ||
6492 | if (strncasecmp (s, "ROR", 3) == 0) | |
6493 | s += 3; | |
6494 | else | |
a737bd4d | 6495 | { |
c19d1205 | 6496 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6497 | return FAIL; |
6498 | } | |
c19d1205 ZW |
6499 | |
6500 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6501 | return FAIL; | |
6502 | ||
6503 | switch (rot) | |
a737bd4d | 6504 | { |
c19d1205 ZW |
6505 | case 0: *str = s; return 0x0; |
6506 | case 8: *str = s; return 0x1; | |
6507 | case 16: *str = s; return 0x2; | |
6508 | case 24: *str = s; return 0x3; | |
6509 | ||
6510 | default: | |
6511 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6512 | return FAIL; |
6513 | } | |
c19d1205 | 6514 | } |
a737bd4d | 6515 | |
c19d1205 ZW |
6516 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6517 | range 0 .. 14, or FAIL. */ | |
6518 | static int | |
6519 | parse_cond (char **str) | |
6520 | { | |
c462b453 | 6521 | char *q; |
c19d1205 | 6522 | const struct asm_cond *c; |
c462b453 PB |
6523 | int n; |
6524 | /* Condition codes are always 2 characters, so matching up to | |
6525 | 3 characters is sufficient. */ | |
6526 | char cond[3]; | |
a737bd4d | 6527 | |
c462b453 PB |
6528 | q = *str; |
6529 | n = 0; | |
6530 | while (ISALPHA (*q) && n < 3) | |
6531 | { | |
e07e6e58 | 6532 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6533 | q++; |
6534 | n++; | |
6535 | } | |
a737bd4d | 6536 | |
21d799b5 | 6537 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6538 | if (!c) |
a737bd4d | 6539 | { |
c19d1205 | 6540 | inst.error = _("condition required"); |
a737bd4d NC |
6541 | return FAIL; |
6542 | } | |
6543 | ||
c19d1205 ZW |
6544 | *str = q; |
6545 | return c->value; | |
6546 | } | |
6547 | ||
62b3e311 PB |
6548 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6549 | option, or FAIL. */ | |
6550 | static int | |
6551 | parse_barrier (char **str) | |
6552 | { | |
6553 | char *p, *q; | |
6554 | const struct asm_barrier_opt *o; | |
6555 | ||
6556 | p = q = *str; | |
6557 | while (ISALPHA (*q)) | |
6558 | q++; | |
6559 | ||
21d799b5 | 6560 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6561 | q - p); |
62b3e311 PB |
6562 | if (!o) |
6563 | return FAIL; | |
6564 | ||
e797f7e0 MGD |
6565 | if (!mark_feature_used (&o->arch)) |
6566 | return FAIL; | |
6567 | ||
62b3e311 PB |
6568 | *str = q; |
6569 | return o->value; | |
6570 | } | |
6571 | ||
92e90b6e PB |
6572 | /* Parse the operands of a table branch instruction. Similar to a memory |
6573 | operand. */ | |
6574 | static int | |
6575 | parse_tb (char **str) | |
6576 | { | |
6577 | char * p = *str; | |
6578 | int reg; | |
6579 | ||
6580 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6581 | { |
6582 | inst.error = _("'[' expected"); | |
6583 | return FAIL; | |
6584 | } | |
92e90b6e | 6585 | |
dcbf9037 | 6586 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6587 | { |
6588 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6589 | return FAIL; | |
6590 | } | |
6591 | inst.operands[0].reg = reg; | |
6592 | ||
6593 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6594 | { |
6595 | inst.error = _("',' expected"); | |
6596 | return FAIL; | |
6597 | } | |
5f4273c7 | 6598 | |
dcbf9037 | 6599 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6600 | { |
6601 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6602 | return FAIL; | |
6603 | } | |
6604 | inst.operands[0].imm = reg; | |
6605 | ||
6606 | if (skip_past_comma (&p) == SUCCESS) | |
6607 | { | |
6608 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6609 | return FAIL; | |
e2b0ab59 | 6610 | if (inst.relocs[0].exp.X_add_number != 1) |
92e90b6e PB |
6611 | { |
6612 | inst.error = _("invalid shift"); | |
6613 | return FAIL; | |
6614 | } | |
6615 | inst.operands[0].shifted = 1; | |
6616 | } | |
6617 | ||
6618 | if (skip_past_char (&p, ']') == FAIL) | |
6619 | { | |
6620 | inst.error = _("']' expected"); | |
6621 | return FAIL; | |
6622 | } | |
6623 | *str = p; | |
6624 | return SUCCESS; | |
6625 | } | |
6626 | ||
5287ad62 JB |
6627 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6628 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6629 | Up to four operands may be read; this function handles setting the |
6630 | ".present" field for each read operand itself. | |
5287ad62 JB |
6631 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6632 | else returns FAIL. */ | |
6633 | ||
6634 | static int | |
6635 | parse_neon_mov (char **str, int *which_operand) | |
6636 | { | |
6637 | int i = *which_operand, val; | |
6638 | enum arm_reg_type rtype; | |
6639 | char *ptr = *str; | |
dcbf9037 | 6640 | struct neon_type_el optype; |
5f4273c7 | 6641 | |
57785aa2 AV |
6642 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
6643 | { | |
6644 | /* Cases 17 or 19. */ | |
6645 | inst.operands[i].reg = val; | |
6646 | inst.operands[i].isvec = 1; | |
6647 | inst.operands[i].isscalar = 2; | |
6648 | inst.operands[i].vectype = optype; | |
6649 | inst.operands[i++].present = 1; | |
6650 | ||
6651 | if (skip_past_comma (&ptr) == FAIL) | |
6652 | goto wanted_comma; | |
6653 | ||
6654 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) | |
6655 | { | |
6656 | /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */ | |
6657 | inst.operands[i].reg = val; | |
6658 | inst.operands[i].isreg = 1; | |
6659 | inst.operands[i].present = 1; | |
6660 | } | |
6661 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) | |
6662 | { | |
6663 | /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */ | |
6664 | inst.operands[i].reg = val; | |
6665 | inst.operands[i].isvec = 1; | |
6666 | inst.operands[i].isscalar = 2; | |
6667 | inst.operands[i].vectype = optype; | |
6668 | inst.operands[i++].present = 1; | |
6669 | ||
6670 | if (skip_past_comma (&ptr) == FAIL) | |
6671 | goto wanted_comma; | |
6672 | ||
6673 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6674 | goto wanted_arm; | |
6675 | ||
6676 | inst.operands[i].reg = val; | |
6677 | inst.operands[i].isreg = 1; | |
6678 | inst.operands[i++].present = 1; | |
6679 | ||
6680 | if (skip_past_comma (&ptr) == FAIL) | |
6681 | goto wanted_comma; | |
6682 | ||
6683 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6684 | goto wanted_arm; | |
6685 | ||
6686 | inst.operands[i].reg = val; | |
6687 | inst.operands[i].isreg = 1; | |
6688 | inst.operands[i].present = 1; | |
6689 | } | |
6690 | else | |
6691 | { | |
6692 | first_error (_("expected ARM or MVE vector register")); | |
6693 | return FAIL; | |
6694 | } | |
6695 | } | |
6696 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL) | |
5287ad62 JB |
6697 | { |
6698 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6699 | inst.operands[i].reg = val; | |
6700 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6701 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6702 | inst.operands[i++].present = 1; |
6703 | ||
6704 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6705 | goto wanted_comma; |
5f4273c7 | 6706 | |
dcbf9037 | 6707 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6708 | goto wanted_arm; |
5f4273c7 | 6709 | |
5287ad62 JB |
6710 | inst.operands[i].reg = val; |
6711 | inst.operands[i].isreg = 1; | |
6712 | inst.operands[i].present = 1; | |
6713 | } | |
57785aa2 AV |
6714 | else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
6715 | != FAIL) | |
6716 | || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype)) | |
6717 | != FAIL)) | |
5287ad62 JB |
6718 | { |
6719 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6720 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6721 | goto wanted_comma; |
5f4273c7 | 6722 | |
5287ad62 JB |
6723 | inst.operands[i].reg = val; |
6724 | inst.operands[i].isreg = 1; | |
6725 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6726 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6727 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6728 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6729 | inst.operands[i++].present = 1; |
6730 | ||
dcbf9037 | 6731 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6732 | { |
6733 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6734 | Case 13: VMOV <Sd>, <Rm> */ | |
6735 | inst.operands[i].reg = val; | |
6736 | inst.operands[i].isreg = 1; | |
6737 | inst.operands[i].present = 1; | |
6738 | ||
6739 | if (rtype == REG_TYPE_NQ) | |
6740 | { | |
6741 | first_error (_("can't use Neon quad register here")); | |
6742 | return FAIL; | |
6743 | } | |
6744 | else if (rtype != REG_TYPE_VFS) | |
6745 | { | |
6746 | i++; | |
6747 | if (skip_past_comma (&ptr) == FAIL) | |
6748 | goto wanted_comma; | |
6749 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6750 | goto wanted_arm; | |
6751 | inst.operands[i].reg = val; | |
6752 | inst.operands[i].isreg = 1; | |
6753 | inst.operands[i].present = 1; | |
6754 | } | |
6755 | } | |
c4a23bf8 SP |
6756 | else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
6757 | &optype)) != FAIL) | |
6758 | || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, | |
6759 | &optype)) != FAIL)) | |
477330fc RM |
6760 | { |
6761 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6762 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6763 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6764 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6765 | ||
6766 | inst.operands[i].reg = val; | |
6767 | inst.operands[i].isreg = 1; | |
6768 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6769 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6770 | inst.operands[i].isvec = 1; | |
6771 | inst.operands[i].vectype = optype; | |
6772 | inst.operands[i].present = 1; | |
6773 | ||
6774 | if (skip_past_comma (&ptr) == SUCCESS) | |
6775 | { | |
6776 | /* Case 15. */ | |
6777 | i++; | |
6778 | ||
6779 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6780 | goto wanted_arm; | |
6781 | ||
6782 | inst.operands[i].reg = val; | |
6783 | inst.operands[i].isreg = 1; | |
6784 | inst.operands[i++].present = 1; | |
6785 | ||
6786 | if (skip_past_comma (&ptr) == FAIL) | |
6787 | goto wanted_comma; | |
6788 | ||
6789 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6790 | goto wanted_arm; | |
6791 | ||
6792 | inst.operands[i].reg = val; | |
6793 | inst.operands[i].isreg = 1; | |
6794 | inst.operands[i].present = 1; | |
6795 | } | |
6796 | } | |
4641781c | 6797 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6798 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6799 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6800 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6801 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6802 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6803 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6804 | == SUCCESS) | |
477330fc RM |
6805 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6806 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6807 | ; | |
5287ad62 | 6808 | else |
477330fc RM |
6809 | { |
6810 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6811 | return FAIL; | |
6812 | } | |
5287ad62 | 6813 | } |
dcbf9037 | 6814 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 6815 | { |
57785aa2 | 6816 | /* Cases 6, 7, 16, 18. */ |
5287ad62 JB |
6817 | inst.operands[i].reg = val; |
6818 | inst.operands[i].isreg = 1; | |
6819 | inst.operands[i++].present = 1; | |
5f4273c7 | 6820 | |
5287ad62 | 6821 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6822 | goto wanted_comma; |
5f4273c7 | 6823 | |
57785aa2 AV |
6824 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL) |
6825 | { | |
6826 | /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */ | |
6827 | inst.operands[i].reg = val; | |
6828 | inst.operands[i].isscalar = 2; | |
6829 | inst.operands[i].present = 1; | |
6830 | inst.operands[i].vectype = optype; | |
6831 | } | |
6832 | else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL) | |
477330fc RM |
6833 | { |
6834 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6835 | inst.operands[i].reg = val; | |
6836 | inst.operands[i].isscalar = 1; | |
6837 | inst.operands[i].present = 1; | |
6838 | inst.operands[i].vectype = optype; | |
6839 | } | |
dcbf9037 | 6840 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc | 6841 | { |
477330fc RM |
6842 | inst.operands[i].reg = val; |
6843 | inst.operands[i].isreg = 1; | |
6844 | inst.operands[i++].present = 1; | |
6845 | ||
6846 | if (skip_past_comma (&ptr) == FAIL) | |
6847 | goto wanted_comma; | |
6848 | ||
6849 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
57785aa2 | 6850 | != FAIL) |
477330fc | 6851 | { |
57785aa2 | 6852 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ |
477330fc | 6853 | |
477330fc RM |
6854 | inst.operands[i].reg = val; |
6855 | inst.operands[i].isreg = 1; | |
6856 | inst.operands[i].isvec = 1; | |
57785aa2 | 6857 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
477330fc RM |
6858 | inst.operands[i].vectype = optype; |
6859 | inst.operands[i].present = 1; | |
57785aa2 AV |
6860 | |
6861 | if (rtype == REG_TYPE_VFS) | |
6862 | { | |
6863 | /* Case 14. */ | |
6864 | i++; | |
6865 | if (skip_past_comma (&ptr) == FAIL) | |
6866 | goto wanted_comma; | |
6867 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6868 | &optype)) == FAIL) | |
6869 | { | |
6870 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6871 | return FAIL; | |
6872 | } | |
6873 | inst.operands[i].reg = val; | |
6874 | inst.operands[i].isreg = 1; | |
6875 | inst.operands[i].isvec = 1; | |
6876 | inst.operands[i].issingle = 1; | |
6877 | inst.operands[i].vectype = optype; | |
6878 | inst.operands[i].present = 1; | |
6879 | } | |
6880 | } | |
6881 | else | |
6882 | { | |
6883 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) | |
6884 | != FAIL) | |
6885 | { | |
6886 | /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */ | |
6887 | inst.operands[i].reg = val; | |
6888 | inst.operands[i].isvec = 1; | |
6889 | inst.operands[i].isscalar = 2; | |
6890 | inst.operands[i].vectype = optype; | |
6891 | inst.operands[i++].present = 1; | |
6892 | ||
6893 | if (skip_past_comma (&ptr) == FAIL) | |
6894 | goto wanted_comma; | |
6895 | ||
6896 | if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) | |
6897 | == FAIL) | |
6898 | { | |
6899 | first_error (_(reg_expected_msgs[REG_TYPE_MQ])); | |
6900 | return FAIL; | |
6901 | } | |
6902 | inst.operands[i].reg = val; | |
6903 | inst.operands[i].isvec = 1; | |
6904 | inst.operands[i].isscalar = 2; | |
6905 | inst.operands[i].vectype = optype; | |
6906 | inst.operands[i].present = 1; | |
6907 | } | |
6908 | else | |
6909 | { | |
6910 | first_error (_("VFP single, double or MVE vector register" | |
6911 | " expected")); | |
6912 | return FAIL; | |
6913 | } | |
477330fc RM |
6914 | } |
6915 | } | |
037e8744 | 6916 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6917 | != FAIL) |
6918 | { | |
6919 | /* Case 13. */ | |
6920 | inst.operands[i].reg = val; | |
6921 | inst.operands[i].isreg = 1; | |
6922 | inst.operands[i].isvec = 1; | |
6923 | inst.operands[i].issingle = 1; | |
6924 | inst.operands[i].vectype = optype; | |
6925 | inst.operands[i].present = 1; | |
6926 | } | |
5287ad62 JB |
6927 | } |
6928 | else | |
6929 | { | |
dcbf9037 | 6930 | first_error (_("parse error")); |
5287ad62 JB |
6931 | return FAIL; |
6932 | } | |
6933 | ||
6934 | /* Successfully parsed the operands. Update args. */ | |
6935 | *which_operand = i; | |
6936 | *str = ptr; | |
6937 | return SUCCESS; | |
6938 | ||
5f4273c7 | 6939 | wanted_comma: |
dcbf9037 | 6940 | first_error (_("expected comma")); |
5287ad62 | 6941 | return FAIL; |
5f4273c7 NC |
6942 | |
6943 | wanted_arm: | |
dcbf9037 | 6944 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6945 | return FAIL; |
5287ad62 JB |
6946 | } |
6947 | ||
5be8be5d DG |
6948 | /* Use this macro when the operand constraints are different |
6949 | for ARM and THUMB (e.g. ldrd). */ | |
6950 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6951 | ((arm_operand) | ((thumb_operand) << 16)) | |
6952 | ||
c19d1205 ZW |
6953 | /* Matcher codes for parse_operands. */ |
6954 | enum operand_parse_code | |
6955 | { | |
6956 | OP_stop, /* end of line */ | |
6957 | ||
6958 | OP_RR, /* ARM register */ | |
6959 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6960 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6961 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6962 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6963 | optional trailing ! */ |
c19d1205 ZW |
6964 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6965 | OP_RCP, /* Coprocessor number */ | |
6966 | OP_RCN, /* Coprocessor register */ | |
6967 | OP_RF, /* FPA register */ | |
6968 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6969 | OP_RVD, /* VFP double precision register (0..15) */ |
6970 | OP_RND, /* Neon double precision register (0..31) */ | |
5ee91343 AV |
6971 | OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */ |
6972 | OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register. | |
6973 | */ | |
5287ad62 | 6974 | OP_RNQ, /* Neon quad precision register */ |
5ee91343 | 6975 | OP_RNQMQ, /* Neon quad or MVE vector register. */ |
037e8744 | 6976 | OP_RVSD, /* VFP single or double precision register */ |
1b883319 | 6977 | OP_RVSD_COND, /* VFP single, double precision register or condition code. */ |
dd9634d9 | 6978 | OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */ |
dec41383 | 6979 | OP_RNSD, /* Neon single or double precision register */ |
5287ad62 | 6980 | OP_RNDQ, /* Neon double or quad precision register */ |
5ee91343 | 6981 | OP_RNDQMQ, /* Neon double, quad or MVE vector register. */ |
7df54120 | 6982 | OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */ |
037e8744 | 6983 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6984 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6985 | OP_RVC, /* VFP control register */ |
6986 | OP_RMF, /* Maverick F register */ | |
6987 | OP_RMD, /* Maverick D register */ | |
6988 | OP_RMFX, /* Maverick FX register */ | |
6989 | OP_RMDX, /* Maverick DX register */ | |
6990 | OP_RMAX, /* Maverick AX register */ | |
6991 | OP_RMDS, /* Maverick DSPSC register */ | |
6992 | OP_RIWR, /* iWMMXt wR register */ | |
6993 | OP_RIWC, /* iWMMXt wC register */ | |
6994 | OP_RIWG, /* iWMMXt wCG register */ | |
6995 | OP_RXA, /* XScale accumulator register */ | |
6996 | ||
5ee91343 AV |
6997 | OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register |
6998 | */ | |
6999 | OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or | |
7000 | GPR (no SP/SP) */ | |
a302e574 | 7001 | OP_RMQ, /* MVE vector register. */ |
1b883319 | 7002 | OP_RMQRZ, /* MVE vector or ARM register including ZR. */ |
35d1cfc2 | 7003 | OP_RMQRR, /* MVE vector or ARM register. */ |
a302e574 | 7004 | |
60f993ce AV |
7005 | /* New operands for Armv8.1-M Mainline. */ |
7006 | OP_LR, /* ARM LR register */ | |
a302e574 AV |
7007 | OP_RRe, /* ARM register, only even numbered. */ |
7008 | OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */ | |
60f993ce | 7009 | OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */ |
e39c1607 | 7010 | OP_RR_ZR, /* ARM register or ZR but no PC */ |
60f993ce | 7011 | |
c19d1205 | 7012 | OP_REGLST, /* ARM register list */ |
4b5a202f | 7013 | OP_CLRMLST, /* CLRM register list */ |
c19d1205 ZW |
7014 | OP_VRSLST, /* VFP single-precision register list */ |
7015 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 7016 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
7017 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
7018 | OP_NSTRLST, /* Neon element/structure list */ | |
efd6b359 | 7019 | OP_VRSDVLST, /* VFP single or double-precision register list and VPR */ |
35c228db AV |
7020 | OP_MSTRLST2, /* MVE vector list with two elements. */ |
7021 | OP_MSTRLST4, /* MVE vector list with four elements. */ | |
5287ad62 | 7022 | |
5287ad62 | 7023 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 7024 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 7025 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
1b883319 AV |
7026 | OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate |
7027 | zero. */ | |
5287ad62 | 7028 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
dec41383 | 7029 | OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */ |
037e8744 | 7030 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
886e1c73 AV |
7031 | OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register. |
7032 | */ | |
a8465a06 AV |
7033 | OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon |
7034 | scalar, or ARM register. */ | |
5287ad62 | 7035 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
42b16635 AV |
7036 | OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */ |
7037 | OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM | |
7038 | register. */ | |
5d281bf0 | 7039 | OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */ |
5287ad62 JB |
7040 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ |
7041 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 7042 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
f601a00c AV |
7043 | /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */ |
7044 | OP_RNDQMQ_Ibig, | |
5287ad62 | 7045 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
5150f0d8 AV |
7046 | OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or |
7047 | ARM register. */ | |
2d447fca | 7048 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
32c36c3c | 7049 | OP_VLDR, /* VLDR operand. */ |
5287ad62 JB |
7050 | |
7051 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
7052 | OP_I7, /* immediate value 0 .. 7 */ |
7053 | OP_I15, /* 0 .. 15 */ | |
7054 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 7055 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
7056 | OP_I31, /* 0 .. 31 */ |
7057 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
7058 | OP_I32, /* 1 .. 32 */ | |
5287ad62 | 7059 | OP_I32z, /* 0 .. 32 */ |
08132bdd | 7060 | OP_I48_I64, /* 48 or 64 */ |
5287ad62 | 7061 | OP_I63, /* 0 .. 63 */ |
c19d1205 | 7062 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
7063 | OP_I64, /* 1 .. 64 */ |
7064 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 7065 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
7066 | |
7067 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
7068 | OP_I7b, /* 0 .. 7 */ | |
7069 | OP_I15b, /* 0 .. 15 */ | |
7070 | OP_I31b, /* 0 .. 31 */ | |
7071 | ||
7072 | OP_SH, /* shifter operand */ | |
4962c51a | 7073 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 7074 | OP_ADDR, /* Memory address expression (any mode) */ |
35c228db | 7075 | OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */ |
4962c51a MS |
7076 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
7077 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
7078 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
7079 | OP_EXP, /* arbitrary expression */ |
7080 | OP_EXPi, /* same, with optional immediate prefix */ | |
7081 | OP_EXPr, /* same, with optional relocation suffix */ | |
e2b0ab59 | 7082 | OP_EXPs, /* same, with optional non-first operand relocation suffix */ |
b6895b4f | 7083 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c28eeff2 SN |
7084 | OP_IROT1, /* VCADD rotate immediate: 90, 270. */ |
7085 | OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */ | |
c19d1205 ZW |
7086 | |
7087 | OP_CPSF, /* CPS flags */ | |
7088 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
7089 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
7090 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 7091 | OP_COND, /* conditional code */ |
92e90b6e | 7092 | OP_TB, /* Table branch. */ |
c19d1205 | 7093 | |
037e8744 JB |
7094 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
7095 | ||
c19d1205 | 7096 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
33eaf5de | 7097 | OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */ |
c19d1205 ZW |
7098 | OP_RR_EXi, /* ARM register or expression with imm prefix */ |
7099 | OP_RF_IF, /* FPA register or immediate */ | |
7100 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 7101 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
7102 | |
7103 | /* Optional operands. */ | |
7104 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
7105 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 7106 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 7107 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
7108 | OP_oIffffb, /* 0 .. 65535 */ |
7109 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
7110 | ||
7111 | OP_oRR, /* ARM register */ | |
60f993ce | 7112 | OP_oLR, /* ARM LR register */ |
c19d1205 | 7113 | OP_oRRnpc, /* ARM register, not the PC */ |
5be8be5d | 7114 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 7115 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
7116 | OP_oRND, /* Optional Neon double precision register */ |
7117 | OP_oRNQ, /* Optional Neon quad precision register */ | |
5ee91343 | 7118 | OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */ |
5287ad62 | 7119 | OP_oRNDQ, /* Optional Neon double or quad precision register */ |
037e8744 | 7120 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
5ee91343 AV |
7121 | OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector |
7122 | register. */ | |
c19d1205 ZW |
7123 | OP_oSHll, /* LSL immediate */ |
7124 | OP_oSHar, /* ASR immediate */ | |
7125 | OP_oSHllar, /* LSL or ASR immediate */ | |
7126 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 7127 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 7128 | |
1b883319 AV |
7129 | OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */ |
7130 | ||
5be8be5d DG |
7131 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
7132 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
7133 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
7134 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
7135 | ||
c19d1205 ZW |
7136 | OP_FIRST_OPTIONAL = OP_oI7b |
7137 | }; | |
a737bd4d | 7138 | |
c19d1205 ZW |
7139 | /* Generic instruction operand parser. This does no encoding and no |
7140 | semantic validation; it merely squirrels values away in the inst | |
7141 | structure. Returns SUCCESS or FAIL depending on whether the | |
7142 | specified grammar matched. */ | |
7143 | static int | |
5be8be5d | 7144 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 7145 | { |
5be8be5d | 7146 | unsigned const int *upat = pattern; |
c19d1205 ZW |
7147 | char *backtrack_pos = 0; |
7148 | const char *backtrack_error = 0; | |
99aad254 | 7149 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 7150 | enum arm_reg_type rtype; |
4962c51a | 7151 | parse_operand_result result; |
5be8be5d | 7152 | unsigned int op_parse_code; |
efd6b359 | 7153 | bfd_boolean partial_match; |
c19d1205 | 7154 | |
e07e6e58 NC |
7155 | #define po_char_or_fail(chr) \ |
7156 | do \ | |
7157 | { \ | |
7158 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 7159 | goto bad_args; \ |
e07e6e58 NC |
7160 | } \ |
7161 | while (0) | |
c19d1205 | 7162 | |
e07e6e58 NC |
7163 | #define po_reg_or_fail(regtype) \ |
7164 | do \ | |
dcbf9037 | 7165 | { \ |
e07e6e58 | 7166 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 7167 | & inst.operands[i].vectype); \ |
e07e6e58 | 7168 | if (val == FAIL) \ |
477330fc RM |
7169 | { \ |
7170 | first_error (_(reg_expected_msgs[regtype])); \ | |
7171 | goto failure; \ | |
7172 | } \ | |
e07e6e58 NC |
7173 | inst.operands[i].reg = val; \ |
7174 | inst.operands[i].isreg = 1; \ | |
7175 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
7176 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
7177 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
7178 | || rtype == REG_TYPE_VFD \ |
7179 | || rtype == REG_TYPE_NQ); \ | |
1b883319 | 7180 | inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \ |
dcbf9037 | 7181 | } \ |
e07e6e58 NC |
7182 | while (0) |
7183 | ||
7184 | #define po_reg_or_goto(regtype, label) \ | |
7185 | do \ | |
7186 | { \ | |
7187 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
7188 | & inst.operands[i].vectype); \ | |
7189 | if (val == FAIL) \ | |
7190 | goto label; \ | |
dcbf9037 | 7191 | \ |
e07e6e58 NC |
7192 | inst.operands[i].reg = val; \ |
7193 | inst.operands[i].isreg = 1; \ | |
7194 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
7195 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
7196 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 7197 | || rtype == REG_TYPE_VFD \ |
e07e6e58 | 7198 | || rtype == REG_TYPE_NQ); \ |
1b883319 | 7199 | inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \ |
e07e6e58 NC |
7200 | } \ |
7201 | while (0) | |
7202 | ||
7203 | #define po_imm_or_fail(min, max, popt) \ | |
7204 | do \ | |
7205 | { \ | |
7206 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
7207 | goto failure; \ | |
7208 | inst.operands[i].imm = val; \ | |
7209 | } \ | |
7210 | while (0) | |
7211 | ||
08132bdd SP |
7212 | #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \ |
7213 | do \ | |
7214 | { \ | |
7215 | expressionS exp; \ | |
7216 | my_get_expression (&exp, &str, popt); \ | |
7217 | if (exp.X_op != O_constant) \ | |
7218 | { \ | |
7219 | inst.error = _("constant expression required"); \ | |
7220 | goto failure; \ | |
7221 | } \ | |
7222 | if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \ | |
7223 | { \ | |
7224 | inst.error = _("immediate value 48 or 64 expected"); \ | |
7225 | goto failure; \ | |
7226 | } \ | |
7227 | inst.operands[i].imm = exp.X_add_number; \ | |
7228 | } \ | |
7229 | while (0) | |
7230 | ||
57785aa2 | 7231 | #define po_scalar_or_goto(elsz, label, reg_type) \ |
e07e6e58 NC |
7232 | do \ |
7233 | { \ | |
57785aa2 AV |
7234 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \ |
7235 | reg_type); \ | |
e07e6e58 NC |
7236 | if (val == FAIL) \ |
7237 | goto label; \ | |
7238 | inst.operands[i].reg = val; \ | |
7239 | inst.operands[i].isscalar = 1; \ | |
7240 | } \ | |
7241 | while (0) | |
7242 | ||
7243 | #define po_misc_or_fail(expr) \ | |
7244 | do \ | |
7245 | { \ | |
7246 | if (expr) \ | |
7247 | goto failure; \ | |
7248 | } \ | |
7249 | while (0) | |
7250 | ||
7251 | #define po_misc_or_fail_no_backtrack(expr) \ | |
7252 | do \ | |
7253 | { \ | |
7254 | result = expr; \ | |
7255 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
7256 | backtrack_pos = 0; \ | |
7257 | if (result != PARSE_OPERAND_SUCCESS) \ | |
7258 | goto failure; \ | |
7259 | } \ | |
7260 | while (0) | |
4962c51a | 7261 | |
52e7f43d RE |
7262 | #define po_barrier_or_imm(str) \ |
7263 | do \ | |
7264 | { \ | |
7265 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
7266 | if (val == FAIL && ! ISALPHA (*str)) \ |
7267 | goto immediate; \ | |
7268 | if (val == FAIL \ | |
7269 | /* ISB can only take SY as an option. */ \ | |
7270 | || ((inst.instruction & 0xf0) == 0x60 \ | |
7271 | && val != 0xf)) \ | |
52e7f43d | 7272 | { \ |
ccb84d65 JB |
7273 | inst.error = _("invalid barrier type"); \ |
7274 | backtrack_pos = 0; \ | |
7275 | goto failure; \ | |
52e7f43d RE |
7276 | } \ |
7277 | } \ | |
7278 | while (0) | |
7279 | ||
c19d1205 ZW |
7280 | skip_whitespace (str); |
7281 | ||
7282 | for (i = 0; upat[i] != OP_stop; i++) | |
7283 | { | |
5be8be5d DG |
7284 | op_parse_code = upat[i]; |
7285 | if (op_parse_code >= 1<<16) | |
7286 | op_parse_code = thumb ? (op_parse_code >> 16) | |
7287 | : (op_parse_code & ((1<<16)-1)); | |
7288 | ||
7289 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
7290 | { |
7291 | /* Remember where we are in case we need to backtrack. */ | |
c19d1205 ZW |
7292 | backtrack_pos = str; |
7293 | backtrack_error = inst.error; | |
7294 | backtrack_index = i; | |
7295 | } | |
7296 | ||
b6702015 | 7297 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
7298 | po_char_or_fail (','); |
7299 | ||
5be8be5d | 7300 | switch (op_parse_code) |
c19d1205 ZW |
7301 | { |
7302 | /* Registers */ | |
7303 | case OP_oRRnpc: | |
5be8be5d | 7304 | case OP_oRRnpcsp: |
c19d1205 | 7305 | case OP_RRnpc: |
5be8be5d | 7306 | case OP_RRnpcsp: |
c19d1205 | 7307 | case OP_oRR: |
a302e574 AV |
7308 | case OP_RRe: |
7309 | case OP_RRo: | |
60f993ce AV |
7310 | case OP_LR: |
7311 | case OP_oLR: | |
c19d1205 ZW |
7312 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; |
7313 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
7314 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
7315 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
7316 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
7317 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 7318 | case OP_oRND: |
5ee91343 AV |
7319 | case OP_RNDMQR: |
7320 | po_reg_or_goto (REG_TYPE_RN, try_rndmq); | |
7321 | break; | |
7322 | try_rndmq: | |
7323 | case OP_RNDMQ: | |
7324 | po_reg_or_goto (REG_TYPE_MQ, try_rnd); | |
7325 | break; | |
7326 | try_rnd: | |
5287ad62 | 7327 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
7328 | case OP_RVC: |
7329 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
7330 | break; | |
7331 | /* Also accept generic coprocessor regs for unknown registers. */ | |
7332 | coproc_reg: | |
ba6cd17f SD |
7333 | po_reg_or_goto (REG_TYPE_CN, vpr_po); |
7334 | break; | |
7335 | /* Also accept P0 or p0 for VPR.P0. Since P0 is already an | |
7336 | existing register with a value of 0, this seems like the | |
7337 | best way to parse P0. */ | |
7338 | vpr_po: | |
7339 | if (strncasecmp (str, "P0", 2) == 0) | |
7340 | { | |
7341 | str += 2; | |
7342 | inst.operands[i].isreg = 1; | |
7343 | inst.operands[i].reg = 13; | |
7344 | } | |
7345 | else | |
7346 | goto failure; | |
cd2cf30b | 7347 | break; |
c19d1205 ZW |
7348 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
7349 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
7350 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
7351 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
7352 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
7353 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
7354 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
7355 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
7356 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
7357 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 7358 | case OP_oRNQ: |
5ee91343 AV |
7359 | case OP_RNQMQ: |
7360 | po_reg_or_goto (REG_TYPE_MQ, try_nq); | |
7361 | break; | |
7362 | try_nq: | |
5287ad62 | 7363 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
dec41383 | 7364 | case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break; |
7df54120 AV |
7365 | case OP_RNDQMQR: |
7366 | po_reg_or_goto (REG_TYPE_RN, try_rndqmq); | |
7367 | break; | |
7368 | try_rndqmq: | |
5ee91343 AV |
7369 | case OP_oRNDQMQ: |
7370 | case OP_RNDQMQ: | |
7371 | po_reg_or_goto (REG_TYPE_MQ, try_rndq); | |
7372 | break; | |
7373 | try_rndq: | |
477330fc | 7374 | case OP_oRNDQ: |
5287ad62 | 7375 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
dd9634d9 AV |
7376 | case OP_RVSDMQ: |
7377 | po_reg_or_goto (REG_TYPE_MQ, try_rvsd); | |
7378 | break; | |
7379 | try_rvsd: | |
477330fc | 7380 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
1b883319 AV |
7381 | case OP_RVSD_COND: |
7382 | po_reg_or_goto (REG_TYPE_VFSD, try_cond); | |
7383 | break; | |
477330fc RM |
7384 | case OP_oRNSDQ: |
7385 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5ee91343 AV |
7386 | case OP_RNSDQMQR: |
7387 | po_reg_or_goto (REG_TYPE_RN, try_mq); | |
7388 | break; | |
7389 | try_mq: | |
7390 | case OP_oRNSDQMQ: | |
7391 | case OP_RNSDQMQ: | |
7392 | po_reg_or_goto (REG_TYPE_MQ, try_nsdq2); | |
7393 | break; | |
7394 | try_nsdq2: | |
7395 | po_reg_or_fail (REG_TYPE_NSDQ); | |
7396 | inst.error = 0; | |
7397 | break; | |
35d1cfc2 AV |
7398 | case OP_RMQRR: |
7399 | po_reg_or_goto (REG_TYPE_RN, try_rmq); | |
7400 | break; | |
7401 | try_rmq: | |
a302e574 AV |
7402 | case OP_RMQ: |
7403 | po_reg_or_fail (REG_TYPE_MQ); | |
7404 | break; | |
477330fc RM |
7405 | /* Neon scalar. Using an element size of 8 means that some invalid |
7406 | scalars are accepted here, so deal with those in later code. */ | |
57785aa2 | 7407 | case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break; |
477330fc RM |
7408 | |
7409 | case OP_RNDQ_I0: | |
7410 | { | |
7411 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
7412 | break; | |
7413 | try_imm0: | |
7414 | po_imm_or_fail (0, 0, TRUE); | |
7415 | } | |
7416 | break; | |
7417 | ||
7418 | case OP_RVSD_I0: | |
7419 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
7420 | break; | |
7421 | ||
1b883319 AV |
7422 | case OP_RSVDMQ_FI0: |
7423 | po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0); | |
7424 | break; | |
7425 | try_rsvd_fi0: | |
aacf0b33 KT |
7426 | case OP_RSVD_FI0: |
7427 | { | |
7428 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
7429 | break; | |
7430 | try_ifimm0: | |
7431 | if (parse_ifimm_zero (&str)) | |
7432 | inst.operands[i].imm = 0; | |
7433 | else | |
7434 | { | |
7435 | inst.error | |
7436 | = _("only floating point zero is allowed as immediate value"); | |
7437 | goto failure; | |
7438 | } | |
7439 | } | |
7440 | break; | |
7441 | ||
477330fc RM |
7442 | case OP_RR_RNSC: |
7443 | { | |
57785aa2 | 7444 | po_scalar_or_goto (8, try_rr, REG_TYPE_VFD); |
477330fc RM |
7445 | break; |
7446 | try_rr: | |
7447 | po_reg_or_fail (REG_TYPE_RN); | |
7448 | } | |
7449 | break; | |
7450 | ||
a8465a06 AV |
7451 | case OP_RNSDQ_RNSC_MQ_RR: |
7452 | po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq); | |
7453 | break; | |
7454 | try_rnsdq_rnsc_mq: | |
886e1c73 AV |
7455 | case OP_RNSDQ_RNSC_MQ: |
7456 | po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc); | |
7457 | break; | |
7458 | try_rnsdq_rnsc: | |
477330fc RM |
7459 | case OP_RNSDQ_RNSC: |
7460 | { | |
57785aa2 AV |
7461 | po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD); |
7462 | inst.error = 0; | |
477330fc RM |
7463 | break; |
7464 | try_nsdq: | |
7465 | po_reg_or_fail (REG_TYPE_NSDQ); | |
57785aa2 | 7466 | inst.error = 0; |
477330fc RM |
7467 | } |
7468 | break; | |
7469 | ||
dec41383 JW |
7470 | case OP_RNSD_RNSC: |
7471 | { | |
57785aa2 | 7472 | po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD); |
dec41383 JW |
7473 | break; |
7474 | try_s_scalar: | |
57785aa2 | 7475 | po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS); |
dec41383 JW |
7476 | break; |
7477 | try_nsd: | |
7478 | po_reg_or_fail (REG_TYPE_NSD); | |
7479 | } | |
7480 | break; | |
7481 | ||
42b16635 AV |
7482 | case OP_RNDQMQ_RNSC_RR: |
7483 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr); | |
7484 | break; | |
7485 | try_rndq_rnsc_rr: | |
7486 | case OP_RNDQ_RNSC_RR: | |
7487 | po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc); | |
7488 | break; | |
5d281bf0 AV |
7489 | case OP_RNDQMQ_RNSC: |
7490 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc); | |
7491 | break; | |
7492 | try_rndq_rnsc: | |
477330fc RM |
7493 | case OP_RNDQ_RNSC: |
7494 | { | |
57785aa2 | 7495 | po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD); |
477330fc RM |
7496 | break; |
7497 | try_ndq: | |
7498 | po_reg_or_fail (REG_TYPE_NDQ); | |
7499 | } | |
7500 | break; | |
7501 | ||
7502 | case OP_RND_RNSC: | |
7503 | { | |
57785aa2 | 7504 | po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD); |
477330fc RM |
7505 | break; |
7506 | try_vfd: | |
7507 | po_reg_or_fail (REG_TYPE_VFD); | |
7508 | } | |
7509 | break; | |
7510 | ||
7511 | case OP_VMOV: | |
7512 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
7513 | not careful then bad things might happen. */ | |
7514 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
7515 | break; | |
7516 | ||
f601a00c AV |
7517 | case OP_RNDQMQ_Ibig: |
7518 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig); | |
7519 | break; | |
7520 | try_rndq_ibig: | |
477330fc RM |
7521 | case OP_RNDQ_Ibig: |
7522 | { | |
7523 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
7524 | break; | |
7525 | try_immbig: | |
7526 | /* There's a possibility of getting a 64-bit immediate here, so | |
7527 | we need special handling. */ | |
8335d6aa JW |
7528 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
7529 | == FAIL) | |
477330fc RM |
7530 | { |
7531 | inst.error = _("immediate value is out of range"); | |
7532 | goto failure; | |
7533 | } | |
7534 | } | |
7535 | break; | |
7536 | ||
5150f0d8 AV |
7537 | case OP_RNDQMQ_I63b_RR: |
7538 | po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr); | |
7539 | break; | |
7540 | try_rndq_i63b_rr: | |
7541 | po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b); | |
7542 | break; | |
7543 | try_rndq_i63b: | |
477330fc RM |
7544 | case OP_RNDQ_I63b: |
7545 | { | |
7546 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
7547 | break; | |
7548 | try_shimm: | |
7549 | po_imm_or_fail (0, 63, TRUE); | |
7550 | } | |
7551 | break; | |
c19d1205 ZW |
7552 | |
7553 | case OP_RRnpcb: | |
7554 | po_char_or_fail ('['); | |
7555 | po_reg_or_fail (REG_TYPE_RN); | |
7556 | po_char_or_fail (']'); | |
7557 | break; | |
a737bd4d | 7558 | |
55881a11 | 7559 | case OP_RRnpctw: |
c19d1205 | 7560 | case OP_RRw: |
b6702015 | 7561 | case OP_oRRw: |
c19d1205 ZW |
7562 | po_reg_or_fail (REG_TYPE_RN); |
7563 | if (skip_past_char (&str, '!') == SUCCESS) | |
7564 | inst.operands[i].writeback = 1; | |
7565 | break; | |
7566 | ||
7567 | /* Immediates */ | |
7568 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
7569 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
7570 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 7571 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
7572 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
7573 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 7574 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
08132bdd | 7575 | case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, FALSE); break; |
c19d1205 | 7576 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
7577 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
7578 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
7579 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 7580 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
7581 | |
7582 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
7583 | case OP_oI7b: | |
7584 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
7585 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
7586 | case OP_oI31b: | |
7587 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
7588 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
7589 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
7590 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
7591 | ||
7592 | /* Immediate variants */ | |
7593 | case OP_oI255c: | |
7594 | po_char_or_fail ('{'); | |
7595 | po_imm_or_fail (0, 255, TRUE); | |
7596 | po_char_or_fail ('}'); | |
7597 | break; | |
7598 | ||
7599 | case OP_I31w: | |
7600 | /* The expression parser chokes on a trailing !, so we have | |
7601 | to find it first and zap it. */ | |
7602 | { | |
7603 | char *s = str; | |
7604 | while (*s && *s != ',') | |
7605 | s++; | |
7606 | if (s[-1] == '!') | |
7607 | { | |
7608 | s[-1] = '\0'; | |
7609 | inst.operands[i].writeback = 1; | |
7610 | } | |
7611 | po_imm_or_fail (0, 31, TRUE); | |
7612 | if (str == s - 1) | |
7613 | str = s; | |
7614 | } | |
7615 | break; | |
7616 | ||
7617 | /* Expressions */ | |
7618 | case OP_EXPi: EXPi: | |
e2b0ab59 | 7619 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
c19d1205 ZW |
7620 | GE_OPT_PREFIX)); |
7621 | break; | |
7622 | ||
7623 | case OP_EXP: | |
e2b0ab59 | 7624 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
c19d1205 ZW |
7625 | GE_NO_PREFIX)); |
7626 | break; | |
7627 | ||
7628 | case OP_EXPr: EXPr: | |
e2b0ab59 | 7629 | po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str, |
c19d1205 | 7630 | GE_NO_PREFIX)); |
e2b0ab59 | 7631 | if (inst.relocs[0].exp.X_op == O_symbol) |
a737bd4d | 7632 | { |
c19d1205 ZW |
7633 | val = parse_reloc (&str); |
7634 | if (val == -1) | |
7635 | { | |
7636 | inst.error = _("unrecognized relocation suffix"); | |
7637 | goto failure; | |
7638 | } | |
7639 | else if (val != BFD_RELOC_UNUSED) | |
7640 | { | |
7641 | inst.operands[i].imm = val; | |
7642 | inst.operands[i].hasreloc = 1; | |
7643 | } | |
a737bd4d | 7644 | } |
c19d1205 | 7645 | break; |
a737bd4d | 7646 | |
e2b0ab59 AV |
7647 | case OP_EXPs: |
7648 | po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str, | |
7649 | GE_NO_PREFIX)); | |
7650 | if (inst.relocs[i].exp.X_op == O_symbol) | |
7651 | { | |
7652 | inst.operands[i].hasreloc = 1; | |
7653 | } | |
7654 | else if (inst.relocs[i].exp.X_op == O_constant) | |
7655 | { | |
7656 | inst.operands[i].imm = inst.relocs[i].exp.X_add_number; | |
7657 | inst.operands[i].hasreloc = 0; | |
7658 | } | |
7659 | break; | |
7660 | ||
b6895b4f PB |
7661 | /* Operand for MOVW or MOVT. */ |
7662 | case OP_HALF: | |
7663 | po_misc_or_fail (parse_half (&str)); | |
7664 | break; | |
7665 | ||
e07e6e58 | 7666 | /* Register or expression. */ |
c19d1205 ZW |
7667 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
7668 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 7669 | |
e07e6e58 | 7670 | /* Register or immediate. */ |
c19d1205 ZW |
7671 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
7672 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 7673 | |
23d00a41 SD |
7674 | case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break; |
7675 | I32: po_imm_or_fail (1, 32, FALSE); break; | |
7676 | ||
c19d1205 ZW |
7677 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
7678 | IF: | |
7679 | if (!is_immediate_prefix (*str)) | |
7680 | goto bad_args; | |
7681 | str++; | |
7682 | val = parse_fpa_immediate (&str); | |
7683 | if (val == FAIL) | |
7684 | goto failure; | |
7685 | /* FPA immediates are encoded as registers 8-15. | |
7686 | parse_fpa_immediate has already applied the offset. */ | |
7687 | inst.operands[i].reg = val; | |
7688 | inst.operands[i].isreg = 1; | |
7689 | break; | |
09d92015 | 7690 | |
2d447fca JM |
7691 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
7692 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
7693 | ||
e07e6e58 | 7694 | /* Two kinds of register. */ |
c19d1205 ZW |
7695 | case OP_RIWR_RIWC: |
7696 | { | |
7697 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
7698 | if (!rege |
7699 | || (rege->type != REG_TYPE_MMXWR | |
7700 | && rege->type != REG_TYPE_MMXWC | |
7701 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
7702 | { |
7703 | inst.error = _("iWMMXt data or control register expected"); | |
7704 | goto failure; | |
7705 | } | |
7706 | inst.operands[i].reg = rege->number; | |
7707 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
7708 | } | |
7709 | break; | |
09d92015 | 7710 | |
41adaa5c JM |
7711 | case OP_RIWC_RIWG: |
7712 | { | |
7713 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
7714 | if (!rege | |
7715 | || (rege->type != REG_TYPE_MMXWC | |
7716 | && rege->type != REG_TYPE_MMXWCG)) | |
7717 | { | |
7718 | inst.error = _("iWMMXt control register expected"); | |
7719 | goto failure; | |
7720 | } | |
7721 | inst.operands[i].reg = rege->number; | |
7722 | inst.operands[i].isreg = 1; | |
7723 | } | |
7724 | break; | |
7725 | ||
c19d1205 ZW |
7726 | /* Misc */ |
7727 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
7728 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
7729 | case OP_oROR: val = parse_ror (&str); break; | |
1b883319 | 7730 | try_cond: |
c19d1205 | 7731 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
7732 | case OP_oBARRIER_I15: |
7733 | po_barrier_or_imm (str); break; | |
7734 | immediate: | |
7735 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 7736 | goto failure; |
52e7f43d | 7737 | break; |
c19d1205 | 7738 | |
fa94de6b | 7739 | case OP_wPSR: |
d2cd1205 | 7740 | case OP_rPSR: |
90ec0d68 MGD |
7741 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
7742 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
7743 | { | |
7744 | inst.error = _("Banked registers are not available with this " | |
7745 | "architecture."); | |
7746 | goto failure; | |
7747 | } | |
7748 | break; | |
d2cd1205 JB |
7749 | try_psr: |
7750 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
7751 | break; | |
037e8744 | 7752 | |
32c36c3c AV |
7753 | case OP_VLDR: |
7754 | po_reg_or_goto (REG_TYPE_VFSD, try_sysreg); | |
7755 | break; | |
7756 | try_sysreg: | |
7757 | val = parse_sys_vldr_vstr (&str); | |
7758 | break; | |
7759 | ||
477330fc RM |
7760 | case OP_APSR_RR: |
7761 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
7762 | break; | |
7763 | try_apsr: | |
7764 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
7765 | instruction). */ | |
7766 | if (strncasecmp (str, "APSR_", 5) == 0) | |
7767 | { | |
7768 | unsigned found = 0; | |
7769 | str += 5; | |
7770 | while (found < 15) | |
7771 | switch (*str++) | |
7772 | { | |
7773 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
7774 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
7775 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
7776 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
7777 | default: found = 16; | |
7778 | } | |
7779 | if (found != 15) | |
7780 | goto failure; | |
7781 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
7782 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
7783 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
7784 | } |
7785 | else | |
7786 | goto failure; | |
7787 | break; | |
037e8744 | 7788 | |
92e90b6e PB |
7789 | case OP_TB: |
7790 | po_misc_or_fail (parse_tb (&str)); | |
7791 | break; | |
7792 | ||
e07e6e58 | 7793 | /* Register lists. */ |
c19d1205 | 7794 | case OP_REGLST: |
4b5a202f | 7795 | val = parse_reg_list (&str, REGLIST_RN); |
c19d1205 ZW |
7796 | if (*str == '^') |
7797 | { | |
5e0d7f77 | 7798 | inst.operands[i].writeback = 1; |
c19d1205 ZW |
7799 | str++; |
7800 | } | |
7801 | break; | |
09d92015 | 7802 | |
4b5a202f AV |
7803 | case OP_CLRMLST: |
7804 | val = parse_reg_list (&str, REGLIST_CLRM); | |
7805 | break; | |
7806 | ||
c19d1205 | 7807 | case OP_VRSLST: |
efd6b359 AV |
7808 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S, |
7809 | &partial_match); | |
c19d1205 | 7810 | break; |
09d92015 | 7811 | |
c19d1205 | 7812 | case OP_VRDLST: |
efd6b359 AV |
7813 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D, |
7814 | &partial_match); | |
c19d1205 | 7815 | break; |
a737bd4d | 7816 | |
477330fc RM |
7817 | case OP_VRSDLST: |
7818 | /* Allow Q registers too. */ | |
7819 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
efd6b359 | 7820 | REGLIST_NEON_D, &partial_match); |
477330fc RM |
7821 | if (val == FAIL) |
7822 | { | |
7823 | inst.error = NULL; | |
7824 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
efd6b359 AV |
7825 | REGLIST_VFP_S, &partial_match); |
7826 | inst.operands[i].issingle = 1; | |
7827 | } | |
7828 | break; | |
7829 | ||
7830 | case OP_VRSDVLST: | |
7831 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7832 | REGLIST_VFP_D_VPR, &partial_match); | |
7833 | if (val == FAIL && !partial_match) | |
7834 | { | |
7835 | inst.error = NULL; | |
7836 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7837 | REGLIST_VFP_S_VPR, &partial_match); | |
477330fc RM |
7838 | inst.operands[i].issingle = 1; |
7839 | } | |
7840 | break; | |
7841 | ||
7842 | case OP_NRDLST: | |
7843 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
efd6b359 | 7844 | REGLIST_NEON_D, &partial_match); |
477330fc | 7845 | break; |
5287ad62 | 7846 | |
35c228db AV |
7847 | case OP_MSTRLST4: |
7848 | case OP_MSTRLST2: | |
7849 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, | |
7850 | 1, &inst.operands[i].vectype); | |
7851 | if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe)) | |
7852 | goto failure; | |
7853 | break; | |
5287ad62 | 7854 | case OP_NSTRLST: |
477330fc | 7855 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
35c228db | 7856 | 0, &inst.operands[i].vectype); |
477330fc | 7857 | break; |
5287ad62 | 7858 | |
c19d1205 | 7859 | /* Addressing modes */ |
35c228db AV |
7860 | case OP_ADDRMVE: |
7861 | po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE)); | |
7862 | break; | |
7863 | ||
c19d1205 ZW |
7864 | case OP_ADDR: |
7865 | po_misc_or_fail (parse_address (&str, i)); | |
7866 | break; | |
09d92015 | 7867 | |
4962c51a MS |
7868 | case OP_ADDRGLDR: |
7869 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7870 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7871 | break; |
7872 | ||
7873 | case OP_ADDRGLDRS: | |
7874 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7875 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7876 | break; |
7877 | ||
7878 | case OP_ADDRGLDC: | |
7879 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7880 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7881 | break; |
7882 | ||
c19d1205 ZW |
7883 | case OP_SH: |
7884 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7885 | break; | |
09d92015 | 7886 | |
4962c51a MS |
7887 | case OP_SHG: |
7888 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7889 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7890 | break; |
7891 | ||
c19d1205 ZW |
7892 | case OP_oSHll: |
7893 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7894 | break; | |
09d92015 | 7895 | |
c19d1205 ZW |
7896 | case OP_oSHar: |
7897 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7898 | break; | |
09d92015 | 7899 | |
c19d1205 ZW |
7900 | case OP_oSHllar: |
7901 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7902 | break; | |
09d92015 | 7903 | |
1b883319 AV |
7904 | case OP_RMQRZ: |
7905 | case OP_oRMQRZ: | |
7906 | po_reg_or_goto (REG_TYPE_MQ, try_rr_zr); | |
7907 | break; | |
e39c1607 SD |
7908 | |
7909 | case OP_RR_ZR: | |
1b883319 AV |
7910 | try_rr_zr: |
7911 | po_reg_or_goto (REG_TYPE_RN, ZR); | |
7912 | break; | |
7913 | ZR: | |
7914 | po_reg_or_fail (REG_TYPE_ZR); | |
7915 | break; | |
7916 | ||
c19d1205 | 7917 | default: |
5be8be5d | 7918 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7919 | } |
09d92015 | 7920 | |
c19d1205 ZW |
7921 | /* Various value-based sanity checks and shared operations. We |
7922 | do not signal immediate failures for the register constraints; | |
7923 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7924 | switch (op_parse_code) |
c19d1205 ZW |
7925 | { |
7926 | case OP_oRRnpc: | |
7927 | case OP_RRnpc: | |
7928 | case OP_RRnpcb: | |
7929 | case OP_RRw: | |
b6702015 | 7930 | case OP_oRRw: |
c19d1205 ZW |
7931 | case OP_RRnpc_I0: |
7932 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7933 | inst.error = BAD_PC; | |
7934 | break; | |
09d92015 | 7935 | |
5be8be5d DG |
7936 | case OP_oRRnpcsp: |
7937 | case OP_RRnpcsp: | |
23d00a41 | 7938 | case OP_RRnpcsp_I32: |
5be8be5d DG |
7939 | if (inst.operands[i].isreg) |
7940 | { | |
7941 | if (inst.operands[i].reg == REG_PC) | |
7942 | inst.error = BAD_PC; | |
5c8ed6a4 JW |
7943 | else if (inst.operands[i].reg == REG_SP |
7944 | /* The restriction on Rd/Rt/Rt2 on Thumb mode has been | |
7945 | relaxed since ARMv8-A. */ | |
7946 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
7947 | { | |
7948 | gas_assert (thumb); | |
7949 | inst.error = BAD_SP; | |
7950 | } | |
5be8be5d DG |
7951 | } |
7952 | break; | |
7953 | ||
55881a11 | 7954 | case OP_RRnpctw: |
fa94de6b RM |
7955 | if (inst.operands[i].isreg |
7956 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7957 | && (inst.operands[i].writeback || thumb)) |
7958 | inst.error = BAD_PC; | |
7959 | break; | |
7960 | ||
1b883319 | 7961 | case OP_RVSD_COND: |
32c36c3c AV |
7962 | case OP_VLDR: |
7963 | if (inst.operands[i].isreg) | |
7964 | break; | |
7965 | /* fall through. */ | |
1b883319 | 7966 | |
c19d1205 ZW |
7967 | case OP_CPSF: |
7968 | case OP_ENDI: | |
7969 | case OP_oROR: | |
d2cd1205 JB |
7970 | case OP_wPSR: |
7971 | case OP_rPSR: | |
c19d1205 | 7972 | case OP_COND: |
52e7f43d | 7973 | case OP_oBARRIER_I15: |
c19d1205 | 7974 | case OP_REGLST: |
4b5a202f | 7975 | case OP_CLRMLST: |
c19d1205 ZW |
7976 | case OP_VRSLST: |
7977 | case OP_VRDLST: | |
477330fc | 7978 | case OP_VRSDLST: |
efd6b359 | 7979 | case OP_VRSDVLST: |
477330fc RM |
7980 | case OP_NRDLST: |
7981 | case OP_NSTRLST: | |
35c228db AV |
7982 | case OP_MSTRLST2: |
7983 | case OP_MSTRLST4: | |
c19d1205 ZW |
7984 | if (val == FAIL) |
7985 | goto failure; | |
7986 | inst.operands[i].imm = val; | |
7987 | break; | |
a737bd4d | 7988 | |
60f993ce AV |
7989 | case OP_LR: |
7990 | case OP_oLR: | |
7991 | if (inst.operands[i].reg != REG_LR) | |
7992 | inst.error = _("operand must be LR register"); | |
7993 | break; | |
7994 | ||
1b883319 AV |
7995 | case OP_RMQRZ: |
7996 | case OP_oRMQRZ: | |
e39c1607 | 7997 | case OP_RR_ZR: |
1b883319 AV |
7998 | if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC) |
7999 | inst.error = BAD_PC; | |
8000 | break; | |
8001 | ||
a302e574 AV |
8002 | case OP_RRe: |
8003 | if (inst.operands[i].isreg | |
8004 | && (inst.operands[i].reg & 0x00000001) != 0) | |
8005 | inst.error = BAD_ODD; | |
8006 | break; | |
8007 | ||
8008 | case OP_RRo: | |
8009 | if (inst.operands[i].isreg) | |
8010 | { | |
8011 | if ((inst.operands[i].reg & 0x00000001) != 1) | |
8012 | inst.error = BAD_EVEN; | |
8013 | else if (inst.operands[i].reg == REG_SP) | |
8014 | as_tsktsk (MVE_BAD_SP); | |
8015 | else if (inst.operands[i].reg == REG_PC) | |
8016 | inst.error = BAD_PC; | |
8017 | } | |
8018 | break; | |
8019 | ||
c19d1205 ZW |
8020 | default: |
8021 | break; | |
8022 | } | |
09d92015 | 8023 | |
c19d1205 ZW |
8024 | /* If we get here, this operand was successfully parsed. */ |
8025 | inst.operands[i].present = 1; | |
8026 | continue; | |
09d92015 | 8027 | |
c19d1205 | 8028 | bad_args: |
09d92015 | 8029 | inst.error = BAD_ARGS; |
c19d1205 ZW |
8030 | |
8031 | failure: | |
8032 | if (!backtrack_pos) | |
d252fdde PB |
8033 | { |
8034 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 8035 | default here just in case. */ |
d252fdde | 8036 | if (!inst.error) |
5ee91343 | 8037 | inst.error = BAD_SYNTAX; |
d252fdde PB |
8038 | return FAIL; |
8039 | } | |
c19d1205 ZW |
8040 | |
8041 | /* Do not backtrack over a trailing optional argument that | |
8042 | absorbed some text. We will only fail again, with the | |
8043 | 'garbage following instruction' error message, which is | |
8044 | probably less helpful than the current one. */ | |
8045 | if (backtrack_index == i && backtrack_pos != str | |
8046 | && upat[i+1] == OP_stop) | |
d252fdde PB |
8047 | { |
8048 | if (!inst.error) | |
5ee91343 | 8049 | inst.error = BAD_SYNTAX; |
d252fdde PB |
8050 | return FAIL; |
8051 | } | |
c19d1205 ZW |
8052 | |
8053 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
8054 | str = backtrack_pos; | |
8055 | inst.error = backtrack_error; | |
8056 | inst.operands[backtrack_index].present = 0; | |
8057 | i = backtrack_index; | |
8058 | backtrack_pos = 0; | |
09d92015 | 8059 | } |
09d92015 | 8060 | |
c19d1205 ZW |
8061 | /* Check that we have parsed all the arguments. */ |
8062 | if (*str != '\0' && !inst.error) | |
8063 | inst.error = _("garbage following instruction"); | |
09d92015 | 8064 | |
c19d1205 | 8065 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
8066 | } |
8067 | ||
c19d1205 ZW |
8068 | #undef po_char_or_fail |
8069 | #undef po_reg_or_fail | |
8070 | #undef po_reg_or_goto | |
8071 | #undef po_imm_or_fail | |
5287ad62 | 8072 | #undef po_scalar_or_fail |
52e7f43d | 8073 | #undef po_barrier_or_imm |
e07e6e58 | 8074 | |
c19d1205 | 8075 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
8076 | #define constraint(expr, err) \ |
8077 | do \ | |
c19d1205 | 8078 | { \ |
e07e6e58 NC |
8079 | if (expr) \ |
8080 | { \ | |
8081 | inst.error = err; \ | |
8082 | return; \ | |
8083 | } \ | |
c19d1205 | 8084 | } \ |
e07e6e58 | 8085 | while (0) |
c19d1205 | 8086 | |
fdfde340 JM |
8087 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
8088 | instructions are unpredictable if these registers are used. This | |
5c8ed6a4 JW |
8089 | is the BadReg predicate in ARM's Thumb-2 documentation. |
8090 | ||
8091 | Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few | |
8092 | places, while the restriction on REG_SP was relaxed since ARMv8-A. */ | |
8093 | #define reject_bad_reg(reg) \ | |
8094 | do \ | |
8095 | if (reg == REG_PC) \ | |
8096 | { \ | |
8097 | inst.error = BAD_PC; \ | |
8098 | return; \ | |
8099 | } \ | |
8100 | else if (reg == REG_SP \ | |
8101 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \ | |
8102 | { \ | |
8103 | inst.error = BAD_SP; \ | |
8104 | return; \ | |
8105 | } \ | |
fdfde340 JM |
8106 | while (0) |
8107 | ||
94206790 MM |
8108 | /* If REG is R13 (the stack pointer), warn that its use is |
8109 | deprecated. */ | |
8110 | #define warn_deprecated_sp(reg) \ | |
8111 | do \ | |
8112 | if (warn_on_deprecated && reg == REG_SP) \ | |
5c3696f8 | 8113 | as_tsktsk (_("use of r13 is deprecated")); \ |
94206790 MM |
8114 | while (0) |
8115 | ||
c19d1205 ZW |
8116 | /* Functions for operand encoding. ARM, then Thumb. */ |
8117 | ||
d840c081 | 8118 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 | 8119 | |
9db2f6b4 RL |
8120 | /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding. |
8121 | ||
8122 | The only binary encoding difference is the Coprocessor number. Coprocessor | |
8123 | 9 is used for half-precision calculations or conversions. The format of the | |
2b0f3761 | 8124 | instruction is the same as the equivalent Coprocessor 10 instruction that |
9db2f6b4 RL |
8125 | exists for Single-Precision operation. */ |
8126 | ||
8127 | static void | |
8128 | do_scalar_fp16_v82_encode (void) | |
8129 | { | |
5ee91343 | 8130 | if (inst.cond < COND_ALWAYS) |
9db2f6b4 RL |
8131 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," |
8132 | " the behaviour is UNPREDICTABLE")); | |
8133 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), | |
8134 | _(BAD_FP16)); | |
8135 | ||
8136 | inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900; | |
8137 | mark_feature_used (&arm_ext_fp16); | |
8138 | } | |
8139 | ||
c19d1205 ZW |
8140 | /* If VAL can be encoded in the immediate field of an ARM instruction, |
8141 | return the encoded form. Otherwise, return FAIL. */ | |
8142 | ||
8143 | static unsigned int | |
8144 | encode_arm_immediate (unsigned int val) | |
09d92015 | 8145 | { |
c19d1205 ZW |
8146 | unsigned int a, i; |
8147 | ||
4f1d6205 L |
8148 | if (val <= 0xff) |
8149 | return val; | |
8150 | ||
8151 | for (i = 2; i < 32; i += 2) | |
c19d1205 ZW |
8152 | if ((a = rotate_left (val, i)) <= 0xff) |
8153 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
8154 | ||
8155 | return FAIL; | |
09d92015 MM |
8156 | } |
8157 | ||
c19d1205 ZW |
8158 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
8159 | return the encoded form. Otherwise, return FAIL. */ | |
8160 | static unsigned int | |
8161 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 8162 | { |
c19d1205 | 8163 | unsigned int a, i; |
09d92015 | 8164 | |
9c3c69f2 | 8165 | if (val <= 0xff) |
c19d1205 | 8166 | return val; |
a737bd4d | 8167 | |
9c3c69f2 | 8168 | for (i = 1; i <= 24; i++) |
09d92015 | 8169 | { |
9c3c69f2 PB |
8170 | a = val >> i; |
8171 | if ((val & ~(0xff << i)) == 0) | |
8172 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 8173 | } |
a737bd4d | 8174 | |
c19d1205 ZW |
8175 | a = val & 0xff; |
8176 | if (val == ((a << 16) | a)) | |
8177 | return 0x100 | a; | |
8178 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
8179 | return 0x300 | a; | |
09d92015 | 8180 | |
c19d1205 ZW |
8181 | a = val & 0xff00; |
8182 | if (val == ((a << 16) | a)) | |
8183 | return 0x200 | (a >> 8); | |
a737bd4d | 8184 | |
c19d1205 | 8185 | return FAIL; |
09d92015 | 8186 | } |
5287ad62 | 8187 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
8188 | |
8189 | static void | |
5287ad62 JB |
8190 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
8191 | { | |
8192 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
8193 | && reg > 15) | |
8194 | { | |
b1cc4aeb | 8195 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
8196 | { |
8197 | if (thumb_mode) | |
8198 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
8199 | fpu_vfp_ext_d32); | |
8200 | else | |
8201 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
8202 | fpu_vfp_ext_d32); | |
8203 | } | |
5287ad62 | 8204 | else |
477330fc RM |
8205 | { |
8206 | first_error (_("D register out of range for selected VFP version")); | |
8207 | return; | |
8208 | } | |
5287ad62 JB |
8209 | } |
8210 | ||
c19d1205 | 8211 | switch (pos) |
09d92015 | 8212 | { |
c19d1205 ZW |
8213 | case VFP_REG_Sd: |
8214 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
8215 | break; | |
8216 | ||
8217 | case VFP_REG_Sn: | |
8218 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
8219 | break; | |
8220 | ||
8221 | case VFP_REG_Sm: | |
8222 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
8223 | break; | |
8224 | ||
5287ad62 JB |
8225 | case VFP_REG_Dd: |
8226 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
8227 | break; | |
5f4273c7 | 8228 | |
5287ad62 JB |
8229 | case VFP_REG_Dn: |
8230 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
8231 | break; | |
5f4273c7 | 8232 | |
5287ad62 JB |
8233 | case VFP_REG_Dm: |
8234 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
8235 | break; | |
8236 | ||
c19d1205 ZW |
8237 | default: |
8238 | abort (); | |
09d92015 | 8239 | } |
09d92015 MM |
8240 | } |
8241 | ||
c19d1205 | 8242 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 8243 | if any, is handled by md_apply_fix. */ |
09d92015 | 8244 | static void |
c19d1205 | 8245 | encode_arm_shift (int i) |
09d92015 | 8246 | { |
008a97ef RL |
8247 | /* register-shifted register. */ |
8248 | if (inst.operands[i].immisreg) | |
8249 | { | |
bf355b69 MR |
8250 | int op_index; |
8251 | for (op_index = 0; op_index <= i; ++op_index) | |
008a97ef | 8252 | { |
5689c942 RL |
8253 | /* Check the operand only when it's presented. In pre-UAL syntax, |
8254 | if the destination register is the same as the first operand, two | |
8255 | register form of the instruction can be used. */ | |
bf355b69 MR |
8256 | if (inst.operands[op_index].present && inst.operands[op_index].isreg |
8257 | && inst.operands[op_index].reg == REG_PC) | |
008a97ef RL |
8258 | as_warn (UNPRED_REG ("r15")); |
8259 | } | |
8260 | ||
8261 | if (inst.operands[i].imm == REG_PC) | |
8262 | as_warn (UNPRED_REG ("r15")); | |
8263 | } | |
8264 | ||
c19d1205 ZW |
8265 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
8266 | inst.instruction |= SHIFT_ROR << 5; | |
8267 | else | |
09d92015 | 8268 | { |
c19d1205 ZW |
8269 | inst.instruction |= inst.operands[i].shift_kind << 5; |
8270 | if (inst.operands[i].immisreg) | |
8271 | { | |
8272 | inst.instruction |= SHIFT_BY_REG; | |
8273 | inst.instruction |= inst.operands[i].imm << 8; | |
8274 | } | |
8275 | else | |
e2b0ab59 | 8276 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
09d92015 | 8277 | } |
c19d1205 | 8278 | } |
09d92015 | 8279 | |
c19d1205 ZW |
8280 | static void |
8281 | encode_arm_shifter_operand (int i) | |
8282 | { | |
8283 | if (inst.operands[i].isreg) | |
09d92015 | 8284 | { |
c19d1205 ZW |
8285 | inst.instruction |= inst.operands[i].reg; |
8286 | encode_arm_shift (i); | |
09d92015 | 8287 | } |
c19d1205 | 8288 | else |
a415b1cd JB |
8289 | { |
8290 | inst.instruction |= INST_IMMEDIATE; | |
e2b0ab59 | 8291 | if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE) |
a415b1cd JB |
8292 | inst.instruction |= inst.operands[i].imm; |
8293 | } | |
09d92015 MM |
8294 | } |
8295 | ||
c19d1205 | 8296 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 8297 | static void |
c19d1205 | 8298 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 8299 | { |
2b2f5df9 NC |
8300 | /* PR 14260: |
8301 | Generate an error if the operand is not a register. */ | |
8302 | constraint (!inst.operands[i].isreg, | |
8303 | _("Instruction does not support =N addresses")); | |
8304 | ||
c19d1205 | 8305 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 8306 | |
c19d1205 | 8307 | if (inst.operands[i].preind) |
09d92015 | 8308 | { |
c19d1205 ZW |
8309 | if (is_t) |
8310 | { | |
8311 | inst.error = _("instruction does not accept preindexed addressing"); | |
8312 | return; | |
8313 | } | |
8314 | inst.instruction |= PRE_INDEX; | |
8315 | if (inst.operands[i].writeback) | |
8316 | inst.instruction |= WRITE_BACK; | |
09d92015 | 8317 | |
c19d1205 ZW |
8318 | } |
8319 | else if (inst.operands[i].postind) | |
8320 | { | |
9c2799c2 | 8321 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
8322 | if (is_t) |
8323 | inst.instruction |= WRITE_BACK; | |
8324 | } | |
8325 | else /* unindexed - only for coprocessor */ | |
09d92015 | 8326 | { |
c19d1205 | 8327 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
8328 | return; |
8329 | } | |
8330 | ||
c19d1205 ZW |
8331 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
8332 | && (((inst.instruction & 0x000f0000) >> 16) | |
8333 | == ((inst.instruction & 0x0000f000) >> 12))) | |
8334 | as_warn ((inst.instruction & LOAD_BIT) | |
8335 | ? _("destination register same as write-back base") | |
8336 | : _("source register same as write-back base")); | |
09d92015 MM |
8337 | } |
8338 | ||
c19d1205 ZW |
8339 | /* inst.operands[i] was set up by parse_address. Encode it into an |
8340 | ARM-format mode 2 load or store instruction. If is_t is true, | |
8341 | reject forms that cannot be used with a T instruction (i.e. not | |
8342 | post-indexed). */ | |
a737bd4d | 8343 | static void |
c19d1205 | 8344 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 8345 | { |
5be8be5d DG |
8346 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
8347 | ||
c19d1205 | 8348 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 8349 | |
c19d1205 | 8350 | if (inst.operands[i].immisreg) |
09d92015 | 8351 | { |
5be8be5d DG |
8352 | constraint ((inst.operands[i].imm == REG_PC |
8353 | || (is_pc && inst.operands[i].writeback)), | |
8354 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
8355 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
8356 | inst.instruction |= inst.operands[i].imm; | |
8357 | if (!inst.operands[i].negative) | |
8358 | inst.instruction |= INDEX_UP; | |
8359 | if (inst.operands[i].shifted) | |
8360 | { | |
8361 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
8362 | inst.instruction |= SHIFT_ROR << 5; | |
8363 | else | |
8364 | { | |
8365 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
e2b0ab59 | 8366 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
c19d1205 ZW |
8367 | } |
8368 | } | |
09d92015 | 8369 | } |
e2b0ab59 | 8370 | else /* immediate offset in inst.relocs[0] */ |
09d92015 | 8371 | { |
e2b0ab59 | 8372 | if (is_pc && !inst.relocs[0].pc_rel) |
5be8be5d DG |
8373 | { |
8374 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
8375 | |
8376 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
8377 | cannot use PC in addressing. | |
8378 | PC cannot be used in writeback addressing, either. */ | |
8379 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 8380 | BAD_PC_ADDRESSING); |
23a10334 | 8381 | |
dc5ec521 | 8382 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
8383 | if (warn_on_deprecated |
8384 | && !is_load | |
8385 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
5c3696f8 | 8386 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
5be8be5d DG |
8387 | } |
8388 | ||
e2b0ab59 | 8389 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
26d97720 NS |
8390 | { |
8391 | /* Prefer + for zero encoded value. */ | |
8392 | if (!inst.operands[i].negative) | |
8393 | inst.instruction |= INDEX_UP; | |
e2b0ab59 | 8394 | inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM; |
26d97720 | 8395 | } |
09d92015 | 8396 | } |
09d92015 MM |
8397 | } |
8398 | ||
c19d1205 ZW |
8399 | /* inst.operands[i] was set up by parse_address. Encode it into an |
8400 | ARM-format mode 3 load or store instruction. Reject forms that | |
8401 | cannot be used with such instructions. If is_t is true, reject | |
8402 | forms that cannot be used with a T instruction (i.e. not | |
8403 | post-indexed). */ | |
8404 | static void | |
8405 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 8406 | { |
c19d1205 | 8407 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 8408 | { |
c19d1205 ZW |
8409 | inst.error = _("instruction does not accept scaled register index"); |
8410 | return; | |
09d92015 | 8411 | } |
a737bd4d | 8412 | |
c19d1205 | 8413 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 8414 | |
c19d1205 ZW |
8415 | if (inst.operands[i].immisreg) |
8416 | { | |
5be8be5d | 8417 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 8418 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 8419 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
8420 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
8421 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
8422 | inst.instruction |= inst.operands[i].imm; |
8423 | if (!inst.operands[i].negative) | |
8424 | inst.instruction |= INDEX_UP; | |
8425 | } | |
e2b0ab59 | 8426 | else /* immediate offset in inst.relocs[0] */ |
c19d1205 | 8427 | { |
e2b0ab59 | 8428 | constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel |
5be8be5d DG |
8429 | && inst.operands[i].writeback), |
8430 | BAD_PC_WRITEBACK); | |
c19d1205 | 8431 | inst.instruction |= HWOFFSET_IMM; |
e2b0ab59 | 8432 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
26d97720 NS |
8433 | { |
8434 | /* Prefer + for zero encoded value. */ | |
8435 | if (!inst.operands[i].negative) | |
8436 | inst.instruction |= INDEX_UP; | |
8437 | ||
e2b0ab59 | 8438 | inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8; |
26d97720 | 8439 | } |
c19d1205 | 8440 | } |
a737bd4d NC |
8441 | } |
8442 | ||
8335d6aa JW |
8443 | /* Write immediate bits [7:0] to the following locations: |
8444 | ||
8445 | |28/24|23 19|18 16|15 4|3 0| | |
8446 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
8447 | ||
8448 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
8449 | ||
8450 | static void | |
8451 | neon_write_immbits (unsigned immbits) | |
8452 | { | |
8453 | inst.instruction |= immbits & 0xf; | |
8454 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
8455 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
8456 | } | |
8457 | ||
8458 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
8459 | ||
8460 | static void | |
8461 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
8462 | { | |
8463 | unsigned immlo = xlo ? *xlo : 0; | |
8464 | unsigned immhi = xhi ? *xhi : 0; | |
8465 | ||
8466 | switch (size) | |
8467 | { | |
8468 | case 8: | |
8469 | immlo = (~immlo) & 0xff; | |
8470 | break; | |
8471 | ||
8472 | case 16: | |
8473 | immlo = (~immlo) & 0xffff; | |
8474 | break; | |
8475 | ||
8476 | case 64: | |
8477 | immhi = (~immhi) & 0xffffffff; | |
8478 | /* fall through. */ | |
8479 | ||
8480 | case 32: | |
8481 | immlo = (~immlo) & 0xffffffff; | |
8482 | break; | |
8483 | ||
8484 | default: | |
8485 | abort (); | |
8486 | } | |
8487 | ||
8488 | if (xlo) | |
8489 | *xlo = immlo; | |
8490 | ||
8491 | if (xhi) | |
8492 | *xhi = immhi; | |
8493 | } | |
8494 | ||
8495 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
8496 | A, B, C, D. */ | |
09d92015 | 8497 | |
c19d1205 | 8498 | static int |
8335d6aa | 8499 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 8500 | { |
8335d6aa JW |
8501 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
8502 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
8503 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
8504 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
8505 | } | |
a737bd4d | 8506 | |
8335d6aa | 8507 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 8508 | |
8335d6aa JW |
8509 | static unsigned |
8510 | neon_squash_bits (unsigned imm) | |
8511 | { | |
8512 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
8513 | | ((imm & 0x01000000) >> 21); | |
8514 | } | |
8515 | ||
8516 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
8517 | ||
8518 | static unsigned | |
8519 | neon_qfloat_bits (unsigned imm) | |
8520 | { | |
8521 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
8522 | } | |
8523 | ||
8524 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
8525 | the instruction. *OP is passed as the initial value of the op field, and | |
8526 | may be set to a different value depending on the constant (i.e. | |
8527 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
8528 | MVN). If the immediate looks like a repeated pattern then also | |
8529 | try smaller element sizes. */ | |
8530 | ||
8531 | static int | |
8532 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
8533 | unsigned *immbits, int *op, int size, | |
8534 | enum neon_el_type type) | |
8535 | { | |
8536 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
8537 | float. */ | |
8538 | if (type == NT_float && !float_p) | |
8539 | return FAIL; | |
8540 | ||
8541 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 8542 | { |
8335d6aa JW |
8543 | if (size != 32 || *op == 1) |
8544 | return FAIL; | |
8545 | *immbits = neon_qfloat_bits (immlo); | |
8546 | return 0xf; | |
8547 | } | |
8548 | ||
8549 | if (size == 64) | |
8550 | { | |
8551 | if (neon_bits_same_in_bytes (immhi) | |
8552 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 8553 | { |
8335d6aa JW |
8554 | if (*op == 1) |
8555 | return FAIL; | |
8556 | *immbits = (neon_squash_bits (immhi) << 4) | |
8557 | | neon_squash_bits (immlo); | |
8558 | *op = 1; | |
8559 | return 0xe; | |
c19d1205 | 8560 | } |
a737bd4d | 8561 | |
8335d6aa JW |
8562 | if (immhi != immlo) |
8563 | return FAIL; | |
8564 | } | |
a737bd4d | 8565 | |
8335d6aa | 8566 | if (size >= 32) |
09d92015 | 8567 | { |
8335d6aa | 8568 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 8569 | { |
8335d6aa JW |
8570 | *immbits = immlo; |
8571 | return 0x0; | |
c19d1205 | 8572 | } |
8335d6aa | 8573 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 8574 | { |
8335d6aa JW |
8575 | *immbits = immlo >> 8; |
8576 | return 0x2; | |
c19d1205 | 8577 | } |
8335d6aa JW |
8578 | else if (immlo == (immlo & 0x00ff0000)) |
8579 | { | |
8580 | *immbits = immlo >> 16; | |
8581 | return 0x4; | |
8582 | } | |
8583 | else if (immlo == (immlo & 0xff000000)) | |
8584 | { | |
8585 | *immbits = immlo >> 24; | |
8586 | return 0x6; | |
8587 | } | |
8588 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
8589 | { | |
8590 | *immbits = (immlo >> 8) & 0xff; | |
8591 | return 0xc; | |
8592 | } | |
8593 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
8594 | { | |
8595 | *immbits = (immlo >> 16) & 0xff; | |
8596 | return 0xd; | |
8597 | } | |
8598 | ||
8599 | if ((immlo & 0xffff) != (immlo >> 16)) | |
8600 | return FAIL; | |
8601 | immlo &= 0xffff; | |
09d92015 | 8602 | } |
a737bd4d | 8603 | |
8335d6aa | 8604 | if (size >= 16) |
4962c51a | 8605 | { |
8335d6aa JW |
8606 | if (immlo == (immlo & 0x000000ff)) |
8607 | { | |
8608 | *immbits = immlo; | |
8609 | return 0x8; | |
8610 | } | |
8611 | else if (immlo == (immlo & 0x0000ff00)) | |
8612 | { | |
8613 | *immbits = immlo >> 8; | |
8614 | return 0xa; | |
8615 | } | |
8616 | ||
8617 | if ((immlo & 0xff) != (immlo >> 8)) | |
8618 | return FAIL; | |
8619 | immlo &= 0xff; | |
4962c51a MS |
8620 | } |
8621 | ||
8335d6aa JW |
8622 | if (immlo == (immlo & 0x000000ff)) |
8623 | { | |
8624 | /* Don't allow MVN with 8-bit immediate. */ | |
8625 | if (*op == 1) | |
8626 | return FAIL; | |
8627 | *immbits = immlo; | |
8628 | return 0xe; | |
8629 | } | |
26d97720 | 8630 | |
8335d6aa | 8631 | return FAIL; |
c19d1205 | 8632 | } |
a737bd4d | 8633 | |
5fc177c8 | 8634 | #if defined BFD_HOST_64_BIT |
ba592044 AM |
8635 | /* Returns TRUE if double precision value V may be cast |
8636 | to single precision without loss of accuracy. */ | |
8637 | ||
8638 | static bfd_boolean | |
5fc177c8 | 8639 | is_double_a_single (bfd_int64_t v) |
ba592044 | 8640 | { |
5fc177c8 | 8641 | int exp = (int)((v >> 52) & 0x7FF); |
8fe3f3d6 | 8642 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
8643 | |
8644 | return (exp == 0 || exp == 0x7FF | |
8645 | || (exp >= 1023 - 126 && exp <= 1023 + 127)) | |
8646 | && (mantissa & 0x1FFFFFFFl) == 0; | |
8647 | } | |
8648 | ||
3739860c | 8649 | /* Returns a double precision value casted to single precision |
ba592044 AM |
8650 | (ignoring the least significant bits in exponent and mantissa). */ |
8651 | ||
8652 | static int | |
5fc177c8 | 8653 | double_to_single (bfd_int64_t v) |
ba592044 AM |
8654 | { |
8655 | int sign = (int) ((v >> 63) & 1l); | |
5fc177c8 | 8656 | int exp = (int) ((v >> 52) & 0x7FF); |
8fe3f3d6 | 8657 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
8658 | |
8659 | if (exp == 0x7FF) | |
8660 | exp = 0xFF; | |
8661 | else | |
8662 | { | |
8663 | exp = exp - 1023 + 127; | |
8664 | if (exp >= 0xFF) | |
8665 | { | |
8666 | /* Infinity. */ | |
8667 | exp = 0x7F; | |
8668 | mantissa = 0; | |
8669 | } | |
8670 | else if (exp < 0) | |
8671 | { | |
8672 | /* No denormalized numbers. */ | |
8673 | exp = 0; | |
8674 | mantissa = 0; | |
8675 | } | |
8676 | } | |
8677 | mantissa >>= 29; | |
8678 | return (sign << 31) | (exp << 23) | mantissa; | |
8679 | } | |
5fc177c8 | 8680 | #endif /* BFD_HOST_64_BIT */ |
ba592044 | 8681 | |
8335d6aa JW |
8682 | enum lit_type |
8683 | { | |
8684 | CONST_THUMB, | |
8685 | CONST_ARM, | |
8686 | CONST_VEC | |
8687 | }; | |
8688 | ||
ba592044 AM |
8689 | static void do_vfp_nsyn_opcode (const char *); |
8690 | ||
e2b0ab59 | 8691 | /* inst.relocs[0].exp describes an "=expr" load pseudo-operation. |
c19d1205 ZW |
8692 | Determine whether it can be performed with a move instruction; if |
8693 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
8694 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
8695 | load and return FALSE. If this is not a valid thing to do in the | |
8696 | current context, set inst.error and return TRUE. | |
a737bd4d | 8697 | |
c19d1205 ZW |
8698 | inst.operands[i] describes the destination register. */ |
8699 | ||
c921be7d | 8700 | static bfd_boolean |
8335d6aa | 8701 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 8702 | { |
53365c0d | 8703 | unsigned long tbit; |
8335d6aa JW |
8704 | bfd_boolean thumb_p = (t == CONST_THUMB); |
8705 | bfd_boolean arm_p = (t == CONST_ARM); | |
53365c0d PB |
8706 | |
8707 | if (thumb_p) | |
8708 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
8709 | else | |
8710 | tbit = LOAD_BIT; | |
8711 | ||
8712 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 8713 | { |
c19d1205 | 8714 | inst.error = _("invalid pseudo operation"); |
c921be7d | 8715 | return TRUE; |
09d92015 | 8716 | } |
ba592044 | 8717 | |
e2b0ab59 AV |
8718 | if (inst.relocs[0].exp.X_op != O_constant |
8719 | && inst.relocs[0].exp.X_op != O_symbol | |
8720 | && inst.relocs[0].exp.X_op != O_big) | |
09d92015 MM |
8721 | { |
8722 | inst.error = _("constant expression expected"); | |
c921be7d | 8723 | return TRUE; |
09d92015 | 8724 | } |
ba592044 | 8725 | |
e2b0ab59 AV |
8726 | if (inst.relocs[0].exp.X_op == O_constant |
8727 | || inst.relocs[0].exp.X_op == O_big) | |
8335d6aa | 8728 | { |
5fc177c8 NC |
8729 | #if defined BFD_HOST_64_BIT |
8730 | bfd_int64_t v; | |
8731 | #else | |
ba592044 | 8732 | offsetT v; |
5fc177c8 | 8733 | #endif |
e2b0ab59 | 8734 | if (inst.relocs[0].exp.X_op == O_big) |
8335d6aa | 8735 | { |
ba592044 AM |
8736 | LITTLENUM_TYPE w[X_PRECISION]; |
8737 | LITTLENUM_TYPE * l; | |
8738 | ||
e2b0ab59 | 8739 | if (inst.relocs[0].exp.X_add_number == -1) |
8335d6aa | 8740 | { |
ba592044 AM |
8741 | gen_to_words (w, X_PRECISION, E_PRECISION); |
8742 | l = w; | |
8743 | /* FIXME: Should we check words w[2..5] ? */ | |
8335d6aa | 8744 | } |
ba592044 AM |
8745 | else |
8746 | l = generic_bignum; | |
3739860c | 8747 | |
5fc177c8 NC |
8748 | #if defined BFD_HOST_64_BIT |
8749 | v = | |
8750 | ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK) | |
8751 | << LITTLENUM_NUMBER_OF_BITS) | |
8752 | | ((bfd_int64_t) l[2] & LITTLENUM_MASK)) | |
8753 | << LITTLENUM_NUMBER_OF_BITS) | |
8754 | | ((bfd_int64_t) l[1] & LITTLENUM_MASK)) | |
8755 | << LITTLENUM_NUMBER_OF_BITS) | |
8756 | | ((bfd_int64_t) l[0] & LITTLENUM_MASK)); | |
8757 | #else | |
ba592044 AM |
8758 | v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS) |
8759 | | (l[0] & LITTLENUM_MASK); | |
5fc177c8 | 8760 | #endif |
8335d6aa | 8761 | } |
ba592044 | 8762 | else |
e2b0ab59 | 8763 | v = inst.relocs[0].exp.X_add_number; |
ba592044 AM |
8764 | |
8765 | if (!inst.operands[i].issingle) | |
8335d6aa | 8766 | { |
12569877 | 8767 | if (thumb_p) |
8335d6aa | 8768 | { |
53445554 TP |
8769 | /* LDR should not use lead in a flag-setting instruction being |
8770 | chosen so we do not check whether movs can be used. */ | |
12569877 | 8771 | |
53445554 | 8772 | if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) |
ff8646ee | 8773 | || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) |
53445554 TP |
8774 | && inst.operands[i].reg != 13 |
8775 | && inst.operands[i].reg != 15) | |
12569877 | 8776 | { |
fc289b0a TP |
8777 | /* Check if on thumb2 it can be done with a mov.w, mvn or |
8778 | movw instruction. */ | |
12569877 AM |
8779 | unsigned int newimm; |
8780 | bfd_boolean isNegated; | |
8781 | ||
8782 | newimm = encode_thumb32_immediate (v); | |
8783 | if (newimm != (unsigned int) FAIL) | |
8784 | isNegated = FALSE; | |
8785 | else | |
8786 | { | |
582cfe03 | 8787 | newimm = encode_thumb32_immediate (~v); |
12569877 AM |
8788 | if (newimm != (unsigned int) FAIL) |
8789 | isNegated = TRUE; | |
8790 | } | |
8791 | ||
fc289b0a TP |
8792 | /* The number can be loaded with a mov.w or mvn |
8793 | instruction. */ | |
ff8646ee TP |
8794 | if (newimm != (unsigned int) FAIL |
8795 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
12569877 | 8796 | { |
fc289b0a | 8797 | inst.instruction = (0xf04f0000 /* MOV.W. */ |
582cfe03 | 8798 | | (inst.operands[i].reg << 8)); |
fc289b0a | 8799 | /* Change to MOVN. */ |
582cfe03 | 8800 | inst.instruction |= (isNegated ? 0x200000 : 0); |
12569877 AM |
8801 | inst.instruction |= (newimm & 0x800) << 15; |
8802 | inst.instruction |= (newimm & 0x700) << 4; | |
8803 | inst.instruction |= (newimm & 0x0ff); | |
8804 | return TRUE; | |
8805 | } | |
fc289b0a | 8806 | /* The number can be loaded with a movw instruction. */ |
ff8646ee TP |
8807 | else if ((v & ~0xFFFF) == 0 |
8808 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) | |
3739860c | 8809 | { |
582cfe03 | 8810 | int imm = v & 0xFFFF; |
12569877 | 8811 | |
582cfe03 | 8812 | inst.instruction = 0xf2400000; /* MOVW. */ |
12569877 AM |
8813 | inst.instruction |= (inst.operands[i].reg << 8); |
8814 | inst.instruction |= (imm & 0xf000) << 4; | |
8815 | inst.instruction |= (imm & 0x0800) << 15; | |
8816 | inst.instruction |= (imm & 0x0700) << 4; | |
8817 | inst.instruction |= (imm & 0x00ff); | |
8fe9a076 AV |
8818 | /* In case this replacement is being done on Armv8-M |
8819 | Baseline we need to make sure to disable the | |
8820 | instruction size check, as otherwise GAS will reject | |
8821 | the use of this T32 instruction. */ | |
8822 | inst.size_req = 0; | |
12569877 AM |
8823 | return TRUE; |
8824 | } | |
8825 | } | |
8335d6aa | 8826 | } |
12569877 | 8827 | else if (arm_p) |
ba592044 AM |
8828 | { |
8829 | int value = encode_arm_immediate (v); | |
12569877 | 8830 | |
ba592044 AM |
8831 | if (value != FAIL) |
8832 | { | |
8833 | /* This can be done with a mov instruction. */ | |
8834 | inst.instruction &= LITERAL_MASK; | |
8835 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
8836 | inst.instruction |= value & 0xfff; | |
8837 | return TRUE; | |
8838 | } | |
8335d6aa | 8839 | |
ba592044 AM |
8840 | value = encode_arm_immediate (~ v); |
8841 | if (value != FAIL) | |
8842 | { | |
8843 | /* This can be done with a mvn instruction. */ | |
8844 | inst.instruction &= LITERAL_MASK; | |
8845 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
8846 | inst.instruction |= value & 0xfff; | |
8847 | return TRUE; | |
8848 | } | |
8849 | } | |
934c2632 | 8850 | else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) |
8335d6aa | 8851 | { |
ba592044 AM |
8852 | int op = 0; |
8853 | unsigned immbits = 0; | |
8854 | unsigned immlo = inst.operands[1].imm; | |
8855 | unsigned immhi = inst.operands[1].regisimm | |
8856 | ? inst.operands[1].reg | |
e2b0ab59 | 8857 | : inst.relocs[0].exp.X_unsigned |
ba592044 AM |
8858 | ? 0 |
8859 | : ((bfd_int64_t)((int) immlo)) >> 32; | |
8860 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
8861 | &op, 64, NT_invtype); | |
8862 | ||
8863 | if (cmode == FAIL) | |
8864 | { | |
8865 | neon_invert_size (&immlo, &immhi, 64); | |
8866 | op = !op; | |
8867 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
8868 | &op, 64, NT_invtype); | |
8869 | } | |
8870 | ||
8871 | if (cmode != FAIL) | |
8872 | { | |
8873 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
8874 | | (1 << 23) | |
8875 | | (cmode << 8) | |
8876 | | (op << 5) | |
8877 | | (1 << 4); | |
8878 | ||
8879 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
8880 | if (thumb_mode) | |
eff0bc54 | 8881 | inst.instruction |= (0x7U << 29) | (0xF << 24); |
ba592044 | 8882 | else |
eff0bc54 | 8883 | inst.instruction |= (0xFU << 28) | (0x1 << 25); |
ba592044 AM |
8884 | neon_write_immbits (immbits); |
8885 | return TRUE; | |
8886 | } | |
8335d6aa JW |
8887 | } |
8888 | } | |
8335d6aa | 8889 | |
ba592044 AM |
8890 | if (t == CONST_VEC) |
8891 | { | |
8892 | /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */ | |
8893 | if (inst.operands[i].issingle | |
8894 | && is_quarter_float (inst.operands[1].imm) | |
8895 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd)) | |
8335d6aa | 8896 | { |
ba592044 AM |
8897 | inst.operands[1].imm = |
8898 | neon_qfloat_bits (v); | |
8899 | do_vfp_nsyn_opcode ("fconsts"); | |
8900 | return TRUE; | |
8335d6aa | 8901 | } |
5fc177c8 NC |
8902 | |
8903 | /* If our host does not support a 64-bit type then we cannot perform | |
8904 | the following optimization. This mean that there will be a | |
8905 | discrepancy between the output produced by an assembler built for | |
8906 | a 32-bit-only host and the output produced from a 64-bit host, but | |
8907 | this cannot be helped. */ | |
8908 | #if defined BFD_HOST_64_BIT | |
ba592044 AM |
8909 | else if (!inst.operands[1].issingle |
8910 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
8335d6aa | 8911 | { |
ba592044 AM |
8912 | if (is_double_a_single (v) |
8913 | && is_quarter_float (double_to_single (v))) | |
8914 | { | |
8915 | inst.operands[1].imm = | |
8916 | neon_qfloat_bits (double_to_single (v)); | |
8917 | do_vfp_nsyn_opcode ("fconstd"); | |
8918 | return TRUE; | |
8919 | } | |
8335d6aa | 8920 | } |
5fc177c8 | 8921 | #endif |
8335d6aa JW |
8922 | } |
8923 | } | |
8924 | ||
8925 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
8926 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
8927 | return TRUE; | |
8928 | ||
8929 | inst.operands[1].reg = REG_PC; | |
8930 | inst.operands[1].isreg = 1; | |
8931 | inst.operands[1].preind = 1; | |
e2b0ab59 AV |
8932 | inst.relocs[0].pc_rel = 1; |
8933 | inst.relocs[0].type = (thumb_p | |
8335d6aa JW |
8934 | ? BFD_RELOC_ARM_THUMB_OFFSET |
8935 | : (mode_3 | |
8936 | ? BFD_RELOC_ARM_HWLITERAL | |
8937 | : BFD_RELOC_ARM_LITERAL)); | |
8938 | return FALSE; | |
8939 | } | |
8940 | ||
8941 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
8942 | ARM-format instruction. Reject all forms which cannot be encoded | |
8943 | into a coprocessor load/store instruction. If wb_ok is false, | |
8944 | reject use of writeback; if unind_ok is false, reject use of | |
8945 | unindexed addressing. If reloc_override is not 0, use it instead | |
8946 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
8947 | (in which case it is preserved). */ | |
8948 | ||
8949 | static int | |
8950 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
8951 | { | |
8952 | if (!inst.operands[i].isreg) | |
8953 | { | |
99b2a2dd NC |
8954 | /* PR 18256 */ |
8955 | if (! inst.operands[0].isvec) | |
8956 | { | |
8957 | inst.error = _("invalid co-processor operand"); | |
8958 | return FAIL; | |
8959 | } | |
8335d6aa JW |
8960 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) |
8961 | return SUCCESS; | |
8962 | } | |
8963 | ||
8964 | inst.instruction |= inst.operands[i].reg << 16; | |
8965 | ||
8966 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
8967 | ||
8968 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
8969 | { | |
8970 | gas_assert (!inst.operands[i].writeback); | |
8971 | if (!unind_ok) | |
8972 | { | |
8973 | inst.error = _("instruction does not support unindexed addressing"); | |
8974 | return FAIL; | |
8975 | } | |
8976 | inst.instruction |= inst.operands[i].imm; | |
8977 | inst.instruction |= INDEX_UP; | |
8978 | return SUCCESS; | |
8979 | } | |
8980 | ||
8981 | if (inst.operands[i].preind) | |
8982 | inst.instruction |= PRE_INDEX; | |
8983 | ||
8984 | if (inst.operands[i].writeback) | |
09d92015 | 8985 | { |
8335d6aa | 8986 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 8987 | { |
8335d6aa JW |
8988 | inst.error = _("pc may not be used with write-back"); |
8989 | return FAIL; | |
c19d1205 | 8990 | } |
8335d6aa | 8991 | if (!wb_ok) |
c19d1205 | 8992 | { |
8335d6aa JW |
8993 | inst.error = _("instruction does not support writeback"); |
8994 | return FAIL; | |
c19d1205 | 8995 | } |
8335d6aa | 8996 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
8997 | } |
8998 | ||
8335d6aa | 8999 | if (reloc_override) |
e2b0ab59 AV |
9000 | inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override; |
9001 | else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
9002 | || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2) | |
9003 | && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 9004 | { |
8335d6aa | 9005 | if (thumb_mode) |
e2b0ab59 | 9006 | inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM; |
8335d6aa | 9007 | else |
e2b0ab59 | 9008 | inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM; |
c19d1205 | 9009 | } |
8335d6aa JW |
9010 | |
9011 | /* Prefer + for zero encoded value. */ | |
9012 | if (!inst.operands[i].negative) | |
9013 | inst.instruction |= INDEX_UP; | |
9014 | ||
9015 | return SUCCESS; | |
09d92015 MM |
9016 | } |
9017 | ||
5f4273c7 | 9018 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
9019 | First some generics; their names are taken from the conventional |
9020 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 9021 | |
a737bd4d | 9022 | static void |
c19d1205 | 9023 | do_noargs (void) |
09d92015 | 9024 | { |
c19d1205 | 9025 | } |
a737bd4d | 9026 | |
c19d1205 ZW |
9027 | static void |
9028 | do_rd (void) | |
9029 | { | |
9030 | inst.instruction |= inst.operands[0].reg << 12; | |
9031 | } | |
a737bd4d | 9032 | |
16a1fa25 TP |
9033 | static void |
9034 | do_rn (void) | |
9035 | { | |
9036 | inst.instruction |= inst.operands[0].reg << 16; | |
9037 | } | |
9038 | ||
c19d1205 ZW |
9039 | static void |
9040 | do_rd_rm (void) | |
9041 | { | |
9042 | inst.instruction |= inst.operands[0].reg << 12; | |
9043 | inst.instruction |= inst.operands[1].reg; | |
9044 | } | |
09d92015 | 9045 | |
9eb6c0f1 MGD |
9046 | static void |
9047 | do_rm_rn (void) | |
9048 | { | |
9049 | inst.instruction |= inst.operands[0].reg; | |
9050 | inst.instruction |= inst.operands[1].reg << 16; | |
9051 | } | |
9052 | ||
c19d1205 ZW |
9053 | static void |
9054 | do_rd_rn (void) | |
9055 | { | |
9056 | inst.instruction |= inst.operands[0].reg << 12; | |
9057 | inst.instruction |= inst.operands[1].reg << 16; | |
9058 | } | |
a737bd4d | 9059 | |
c19d1205 ZW |
9060 | static void |
9061 | do_rn_rd (void) | |
9062 | { | |
9063 | inst.instruction |= inst.operands[0].reg << 16; | |
9064 | inst.instruction |= inst.operands[1].reg << 12; | |
9065 | } | |
09d92015 | 9066 | |
4ed7ed8d TP |
9067 | static void |
9068 | do_tt (void) | |
9069 | { | |
9070 | inst.instruction |= inst.operands[0].reg << 8; | |
9071 | inst.instruction |= inst.operands[1].reg << 16; | |
9072 | } | |
9073 | ||
59d09be6 MGD |
9074 | static bfd_boolean |
9075 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
9076 | { | |
9077 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
9078 | { | |
5c3696f8 | 9079 | as_tsktsk ("%s", msg); |
59d09be6 MGD |
9080 | return TRUE; |
9081 | } | |
9082 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
9083 | { | |
9084 | as_bad ("%s", msg); | |
9085 | return TRUE; | |
9086 | } | |
9087 | ||
9088 | return FALSE; | |
9089 | } | |
9090 | ||
c19d1205 ZW |
9091 | static void |
9092 | do_rd_rm_rn (void) | |
9093 | { | |
9a64e435 | 9094 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 9095 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 9096 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
9097 | { |
9098 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
9099 | _("Rn must not overlap other operands")); | |
9100 | ||
59d09be6 MGD |
9101 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
9102 | */ | |
9103 | if (!check_obsolete (&arm_ext_v8, | |
9104 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
9105 | && warn_on_deprecated | |
9106 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
5c3696f8 | 9107 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
56adecf4 | 9108 | } |
59d09be6 | 9109 | |
c19d1205 ZW |
9110 | inst.instruction |= inst.operands[0].reg << 12; |
9111 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 9112 | inst.instruction |= Rn << 16; |
c19d1205 | 9113 | } |
09d92015 | 9114 | |
c19d1205 ZW |
9115 | static void |
9116 | do_rd_rn_rm (void) | |
9117 | { | |
9118 | inst.instruction |= inst.operands[0].reg << 12; | |
9119 | inst.instruction |= inst.operands[1].reg << 16; | |
9120 | inst.instruction |= inst.operands[2].reg; | |
9121 | } | |
a737bd4d | 9122 | |
c19d1205 ZW |
9123 | static void |
9124 | do_rm_rd_rn (void) | |
9125 | { | |
5be8be5d | 9126 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
e2b0ab59 AV |
9127 | constraint (((inst.relocs[0].exp.X_op != O_constant |
9128 | && inst.relocs[0].exp.X_op != O_illegal) | |
9129 | || inst.relocs[0].exp.X_add_number != 0), | |
5be8be5d | 9130 | BAD_ADDR_MODE); |
c19d1205 ZW |
9131 | inst.instruction |= inst.operands[0].reg; |
9132 | inst.instruction |= inst.operands[1].reg << 12; | |
9133 | inst.instruction |= inst.operands[2].reg << 16; | |
9134 | } | |
09d92015 | 9135 | |
c19d1205 ZW |
9136 | static void |
9137 | do_imm0 (void) | |
9138 | { | |
9139 | inst.instruction |= inst.operands[0].imm; | |
9140 | } | |
09d92015 | 9141 | |
c19d1205 ZW |
9142 | static void |
9143 | do_rd_cpaddr (void) | |
9144 | { | |
9145 | inst.instruction |= inst.operands[0].reg << 12; | |
9146 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 9147 | } |
a737bd4d | 9148 | |
c19d1205 ZW |
9149 | /* ARM instructions, in alphabetical order by function name (except |
9150 | that wrapper functions appear immediately after the function they | |
9151 | wrap). */ | |
09d92015 | 9152 | |
c19d1205 ZW |
9153 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
9154 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
9155 | |
9156 | static void | |
c19d1205 | 9157 | do_adr (void) |
09d92015 | 9158 | { |
c19d1205 | 9159 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 9160 | |
c19d1205 ZW |
9161 | /* Frag hacking will turn this into a sub instruction if the offset turns |
9162 | out to be negative. */ | |
e2b0ab59 AV |
9163 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
9164 | inst.relocs[0].pc_rel = 1; | |
9165 | inst.relocs[0].exp.X_add_number -= 8; | |
52a86f84 | 9166 | |
fc6141f0 | 9167 | if (support_interwork |
e2b0ab59 AV |
9168 | && inst.relocs[0].exp.X_op == O_symbol |
9169 | && inst.relocs[0].exp.X_add_symbol != NULL | |
9170 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
9171 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
9172 | inst.relocs[0].exp.X_add_number |= 1; | |
c19d1205 | 9173 | } |
b99bd4ef | 9174 | |
c19d1205 ZW |
9175 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
9176 | into a relative address of the form: | |
9177 | add rd, pc, #low(label-.-8)" | |
9178 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 9179 | |
c19d1205 ZW |
9180 | static void |
9181 | do_adrl (void) | |
9182 | { | |
9183 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 9184 | |
c19d1205 ZW |
9185 | /* Frag hacking will turn this into a sub instruction if the offset turns |
9186 | out to be negative. */ | |
e2b0ab59 AV |
9187 | inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE; |
9188 | inst.relocs[0].pc_rel = 1; | |
c19d1205 | 9189 | inst.size = INSN_SIZE * 2; |
e2b0ab59 | 9190 | inst.relocs[0].exp.X_add_number -= 8; |
52a86f84 | 9191 | |
fc6141f0 | 9192 | if (support_interwork |
e2b0ab59 AV |
9193 | && inst.relocs[0].exp.X_op == O_symbol |
9194 | && inst.relocs[0].exp.X_add_symbol != NULL | |
9195 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
9196 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
9197 | inst.relocs[0].exp.X_add_number |= 1; | |
b99bd4ef NC |
9198 | } |
9199 | ||
b99bd4ef | 9200 | static void |
c19d1205 | 9201 | do_arit (void) |
b99bd4ef | 9202 | { |
e2b0ab59 AV |
9203 | constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
9204 | && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
a9f02af8 | 9205 | THUMB1_RELOC_ONLY); |
c19d1205 ZW |
9206 | if (!inst.operands[1].present) |
9207 | inst.operands[1].reg = inst.operands[0].reg; | |
9208 | inst.instruction |= inst.operands[0].reg << 12; | |
9209 | inst.instruction |= inst.operands[1].reg << 16; | |
9210 | encode_arm_shifter_operand (2); | |
9211 | } | |
b99bd4ef | 9212 | |
62b3e311 PB |
9213 | static void |
9214 | do_barrier (void) | |
9215 | { | |
9216 | if (inst.operands[0].present) | |
ccb84d65 | 9217 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
9218 | else |
9219 | inst.instruction |= 0xf; | |
9220 | } | |
9221 | ||
c19d1205 ZW |
9222 | static void |
9223 | do_bfc (void) | |
9224 | { | |
9225 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
9226 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9227 | /* The instruction encoding stores the LSB and MSB, | |
9228 | not the LSB and width. */ | |
9229 | inst.instruction |= inst.operands[0].reg << 12; | |
9230 | inst.instruction |= inst.operands[1].imm << 7; | |
9231 | inst.instruction |= (msb - 1) << 16; | |
9232 | } | |
b99bd4ef | 9233 | |
c19d1205 ZW |
9234 | static void |
9235 | do_bfi (void) | |
9236 | { | |
9237 | unsigned int msb; | |
b99bd4ef | 9238 | |
c19d1205 ZW |
9239 | /* #0 in second position is alternative syntax for bfc, which is |
9240 | the same instruction but with REG_PC in the Rm field. */ | |
9241 | if (!inst.operands[1].isreg) | |
9242 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 9243 | |
c19d1205 ZW |
9244 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9245 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9246 | /* The instruction encoding stores the LSB and MSB, | |
9247 | not the LSB and width. */ | |
9248 | inst.instruction |= inst.operands[0].reg << 12; | |
9249 | inst.instruction |= inst.operands[1].reg; | |
9250 | inst.instruction |= inst.operands[2].imm << 7; | |
9251 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
9252 | } |
9253 | ||
b99bd4ef | 9254 | static void |
c19d1205 | 9255 | do_bfx (void) |
b99bd4ef | 9256 | { |
c19d1205 ZW |
9257 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9258 | _("bit-field extends past end of register")); | |
9259 | inst.instruction |= inst.operands[0].reg << 12; | |
9260 | inst.instruction |= inst.operands[1].reg; | |
9261 | inst.instruction |= inst.operands[2].imm << 7; | |
9262 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
9263 | } | |
09d92015 | 9264 | |
c19d1205 ZW |
9265 | /* ARM V5 breakpoint instruction (argument parse) |
9266 | BKPT <16 bit unsigned immediate> | |
9267 | Instruction is not conditional. | |
9268 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
9269 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 9270 | |
c19d1205 ZW |
9271 | static void |
9272 | do_bkpt (void) | |
9273 | { | |
9274 | /* Top 12 of 16 bits to bits 19:8. */ | |
9275 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 9276 | |
c19d1205 ZW |
9277 | /* Bottom 4 of 16 bits to bits 3:0. */ |
9278 | inst.instruction |= inst.operands[0].imm & 0xf; | |
9279 | } | |
09d92015 | 9280 | |
c19d1205 ZW |
9281 | static void |
9282 | encode_branch (int default_reloc) | |
9283 | { | |
9284 | if (inst.operands[0].hasreloc) | |
9285 | { | |
0855e32b NS |
9286 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
9287 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
9288 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
e2b0ab59 | 9289 | inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 |
0855e32b NS |
9290 | ? BFD_RELOC_ARM_PLT32 |
9291 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 9292 | } |
b99bd4ef | 9293 | else |
e2b0ab59 AV |
9294 | inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc; |
9295 | inst.relocs[0].pc_rel = 1; | |
b99bd4ef NC |
9296 | } |
9297 | ||
b99bd4ef | 9298 | static void |
c19d1205 | 9299 | do_branch (void) |
b99bd4ef | 9300 | { |
39b41c9c PB |
9301 | #ifdef OBJ_ELF |
9302 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
9303 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
9304 | else | |
9305 | #endif | |
9306 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
9307 | } | |
9308 | ||
9309 | static void | |
9310 | do_bl (void) | |
9311 | { | |
9312 | #ifdef OBJ_ELF | |
9313 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
9314 | { | |
9315 | if (inst.cond == COND_ALWAYS) | |
9316 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
9317 | else | |
9318 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
9319 | } | |
9320 | else | |
9321 | #endif | |
9322 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 9323 | } |
b99bd4ef | 9324 | |
c19d1205 ZW |
9325 | /* ARM V5 branch-link-exchange instruction (argument parse) |
9326 | BLX <target_addr> ie BLX(1) | |
9327 | BLX{<condition>} <Rm> ie BLX(2) | |
9328 | Unfortunately, there are two different opcodes for this mnemonic. | |
9329 | So, the insns[].value is not used, and the code here zaps values | |
9330 | into inst.instruction. | |
9331 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 9332 | |
c19d1205 ZW |
9333 | static void |
9334 | do_blx (void) | |
9335 | { | |
9336 | if (inst.operands[0].isreg) | |
b99bd4ef | 9337 | { |
c19d1205 ZW |
9338 | /* Arg is a register; the opcode provided by insns[] is correct. |
9339 | It is not illegal to do "blx pc", just useless. */ | |
9340 | if (inst.operands[0].reg == REG_PC) | |
9341 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 9342 | |
c19d1205 ZW |
9343 | inst.instruction |= inst.operands[0].reg; |
9344 | } | |
9345 | else | |
b99bd4ef | 9346 | { |
c19d1205 | 9347 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
9348 | conditionally, and the opcode must be adjusted. |
9349 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
9350 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 9351 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 9352 | inst.instruction = 0xfa000000; |
267bf995 | 9353 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 9354 | } |
c19d1205 ZW |
9355 | } |
9356 | ||
9357 | static void | |
9358 | do_bx (void) | |
9359 | { | |
845b51d6 PB |
9360 | bfd_boolean want_reloc; |
9361 | ||
c19d1205 ZW |
9362 | if (inst.operands[0].reg == REG_PC) |
9363 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 9364 | |
c19d1205 | 9365 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
9366 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
9367 | it is for ARMv4t or earlier. */ | |
9368 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
4d354d8b TP |
9369 | if (!ARM_FEATURE_ZERO (selected_object_arch) |
9370 | && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5)) | |
845b51d6 PB |
9371 | want_reloc = TRUE; |
9372 | ||
5ad34203 | 9373 | #ifdef OBJ_ELF |
845b51d6 | 9374 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 9375 | #endif |
584206db | 9376 | want_reloc = FALSE; |
845b51d6 PB |
9377 | |
9378 | if (want_reloc) | |
e2b0ab59 | 9379 | inst.relocs[0].type = BFD_RELOC_ARM_V4BX; |
09d92015 MM |
9380 | } |
9381 | ||
c19d1205 ZW |
9382 | |
9383 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
9384 | |
9385 | static void | |
c19d1205 | 9386 | do_bxj (void) |
a737bd4d | 9387 | { |
c19d1205 ZW |
9388 | if (inst.operands[0].reg == REG_PC) |
9389 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
9390 | ||
9391 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
9392 | } |
9393 | ||
c19d1205 ZW |
9394 | /* Co-processor data operation: |
9395 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
9396 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
9397 | static void | |
9398 | do_cdp (void) | |
9399 | { | |
9400 | inst.instruction |= inst.operands[0].reg << 8; | |
9401 | inst.instruction |= inst.operands[1].imm << 20; | |
9402 | inst.instruction |= inst.operands[2].reg << 12; | |
9403 | inst.instruction |= inst.operands[3].reg << 16; | |
9404 | inst.instruction |= inst.operands[4].reg; | |
9405 | inst.instruction |= inst.operands[5].imm << 5; | |
9406 | } | |
a737bd4d NC |
9407 | |
9408 | static void | |
c19d1205 | 9409 | do_cmp (void) |
a737bd4d | 9410 | { |
c19d1205 ZW |
9411 | inst.instruction |= inst.operands[0].reg << 16; |
9412 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
9413 | } |
9414 | ||
c19d1205 ZW |
9415 | /* Transfer between coprocessor and ARM registers. |
9416 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
9417 | MRC2 | |
9418 | MCR{cond} | |
9419 | MCR2 | |
9420 | ||
9421 | No special properties. */ | |
09d92015 | 9422 | |
dcbd0d71 MGD |
9423 | struct deprecated_coproc_regs_s |
9424 | { | |
9425 | unsigned cp; | |
9426 | int opc1; | |
9427 | unsigned crn; | |
9428 | unsigned crm; | |
9429 | int opc2; | |
9430 | arm_feature_set deprecated; | |
9431 | arm_feature_set obsoleted; | |
9432 | const char *dep_msg; | |
9433 | const char *obs_msg; | |
9434 | }; | |
9435 | ||
9436 | #define DEPR_ACCESS_V8 \ | |
9437 | N_("This coprocessor register access is deprecated in ARMv8") | |
9438 | ||
9439 | /* Table of all deprecated coprocessor registers. */ | |
9440 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
9441 | { | |
9442 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
823d2571 | 9443 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9444 | DEPR_ACCESS_V8, NULL}, |
9445 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
823d2571 | 9446 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9447 | DEPR_ACCESS_V8, NULL}, |
9448 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
823d2571 | 9449 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9450 | DEPR_ACCESS_V8, NULL}, |
9451 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
823d2571 | 9452 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9453 | DEPR_ACCESS_V8, NULL}, |
9454 | {14, 6, 0, 0, 0, /* TEECR. */ | |
823d2571 | 9455 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
9456 | DEPR_ACCESS_V8, NULL}, |
9457 | }; | |
9458 | ||
9459 | #undef DEPR_ACCESS_V8 | |
9460 | ||
9461 | static const size_t deprecated_coproc_reg_count = | |
9462 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
9463 | ||
09d92015 | 9464 | static void |
c19d1205 | 9465 | do_co_reg (void) |
09d92015 | 9466 | { |
fdfde340 | 9467 | unsigned Rd; |
dcbd0d71 | 9468 | size_t i; |
fdfde340 JM |
9469 | |
9470 | Rd = inst.operands[2].reg; | |
9471 | if (thumb_mode) | |
9472 | { | |
9473 | if (inst.instruction == 0xee000010 | |
9474 | || inst.instruction == 0xfe000010) | |
9475 | /* MCR, MCR2 */ | |
9476 | reject_bad_reg (Rd); | |
5c8ed6a4 | 9477 | else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
fdfde340 JM |
9478 | /* MRC, MRC2 */ |
9479 | constraint (Rd == REG_SP, BAD_SP); | |
9480 | } | |
9481 | else | |
9482 | { | |
9483 | /* MCR */ | |
9484 | if (inst.instruction == 0xe000010) | |
9485 | constraint (Rd == REG_PC, BAD_PC); | |
9486 | } | |
9487 | ||
dcbd0d71 MGD |
9488 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
9489 | { | |
9490 | const struct deprecated_coproc_regs_s *r = | |
9491 | deprecated_coproc_regs + i; | |
9492 | ||
9493 | if (inst.operands[0].reg == r->cp | |
9494 | && inst.operands[1].imm == r->opc1 | |
9495 | && inst.operands[3].reg == r->crn | |
9496 | && inst.operands[4].reg == r->crm | |
9497 | && inst.operands[5].imm == r->opc2) | |
9498 | { | |
b10bf8c5 | 9499 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 9500 | && warn_on_deprecated |
dcbd0d71 | 9501 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
5c3696f8 | 9502 | as_tsktsk ("%s", r->dep_msg); |
dcbd0d71 MGD |
9503 | } |
9504 | } | |
fdfde340 | 9505 | |
c19d1205 ZW |
9506 | inst.instruction |= inst.operands[0].reg << 8; |
9507 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 9508 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
9509 | inst.instruction |= inst.operands[3].reg << 16; |
9510 | inst.instruction |= inst.operands[4].reg; | |
9511 | inst.instruction |= inst.operands[5].imm << 5; | |
9512 | } | |
09d92015 | 9513 | |
c19d1205 ZW |
9514 | /* Transfer between coprocessor register and pair of ARM registers. |
9515 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
9516 | MCRR2 | |
9517 | MRRC{cond} | |
9518 | MRRC2 | |
b99bd4ef | 9519 | |
c19d1205 | 9520 | Two XScale instructions are special cases of these: |
09d92015 | 9521 | |
c19d1205 ZW |
9522 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
9523 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 9524 | |
5f4273c7 | 9525 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 9526 | |
c19d1205 ZW |
9527 | static void |
9528 | do_co_reg2c (void) | |
9529 | { | |
fdfde340 JM |
9530 | unsigned Rd, Rn; |
9531 | ||
9532 | Rd = inst.operands[2].reg; | |
9533 | Rn = inst.operands[3].reg; | |
9534 | ||
9535 | if (thumb_mode) | |
9536 | { | |
9537 | reject_bad_reg (Rd); | |
9538 | reject_bad_reg (Rn); | |
9539 | } | |
9540 | else | |
9541 | { | |
9542 | constraint (Rd == REG_PC, BAD_PC); | |
9543 | constraint (Rn == REG_PC, BAD_PC); | |
9544 | } | |
9545 | ||
873f10f0 TC |
9546 | /* Only check the MRRC{2} variants. */ |
9547 | if ((inst.instruction & 0x0FF00000) == 0x0C500000) | |
9548 | { | |
9549 | /* If Rd == Rn, error that the operation is | |
9550 | unpredictable (example MRRC p3,#1,r1,r1,c4). */ | |
9551 | constraint (Rd == Rn, BAD_OVERLAP); | |
9552 | } | |
9553 | ||
c19d1205 ZW |
9554 | inst.instruction |= inst.operands[0].reg << 8; |
9555 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
9556 | inst.instruction |= Rd << 12; |
9557 | inst.instruction |= Rn << 16; | |
c19d1205 | 9558 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
9559 | } |
9560 | ||
c19d1205 ZW |
9561 | static void |
9562 | do_cpsi (void) | |
9563 | { | |
9564 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
9565 | if (inst.operands[1].present) |
9566 | { | |
9567 | inst.instruction |= CPSI_MMOD; | |
9568 | inst.instruction |= inst.operands[1].imm; | |
9569 | } | |
c19d1205 | 9570 | } |
b99bd4ef | 9571 | |
62b3e311 PB |
9572 | static void |
9573 | do_dbg (void) | |
9574 | { | |
9575 | inst.instruction |= inst.operands[0].imm; | |
9576 | } | |
9577 | ||
eea54501 MGD |
9578 | static void |
9579 | do_div (void) | |
9580 | { | |
9581 | unsigned Rd, Rn, Rm; | |
9582 | ||
9583 | Rd = inst.operands[0].reg; | |
9584 | Rn = (inst.operands[1].present | |
9585 | ? inst.operands[1].reg : Rd); | |
9586 | Rm = inst.operands[2].reg; | |
9587 | ||
9588 | constraint ((Rd == REG_PC), BAD_PC); | |
9589 | constraint ((Rn == REG_PC), BAD_PC); | |
9590 | constraint ((Rm == REG_PC), BAD_PC); | |
9591 | ||
9592 | inst.instruction |= Rd << 16; | |
9593 | inst.instruction |= Rn << 0; | |
9594 | inst.instruction |= Rm << 8; | |
9595 | } | |
9596 | ||
b99bd4ef | 9597 | static void |
c19d1205 | 9598 | do_it (void) |
b99bd4ef | 9599 | { |
c19d1205 | 9600 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
9601 | process it to do the validation as if in |
9602 | thumb mode, just in case the code gets | |
9603 | assembled for thumb using the unified syntax. */ | |
9604 | ||
c19d1205 | 9605 | inst.size = 0; |
e07e6e58 NC |
9606 | if (unified_syntax) |
9607 | { | |
5ee91343 AV |
9608 | set_pred_insn_type (IT_INSN); |
9609 | now_pred.mask = (inst.instruction & 0xf) | 0x10; | |
9610 | now_pred.cc = inst.operands[0].imm; | |
e07e6e58 | 9611 | } |
09d92015 | 9612 | } |
b99bd4ef | 9613 | |
6530b175 NC |
9614 | /* If there is only one register in the register list, |
9615 | then return its register number. Otherwise return -1. */ | |
9616 | static int | |
9617 | only_one_reg_in_list (int range) | |
9618 | { | |
9619 | int i = ffs (range) - 1; | |
9620 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
9621 | } | |
9622 | ||
09d92015 | 9623 | static void |
6530b175 | 9624 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 9625 | { |
c19d1205 ZW |
9626 | int base_reg = inst.operands[0].reg; |
9627 | int range = inst.operands[1].imm; | |
6530b175 | 9628 | int one_reg; |
ea6ef066 | 9629 | |
c19d1205 ZW |
9630 | inst.instruction |= base_reg << 16; |
9631 | inst.instruction |= range; | |
ea6ef066 | 9632 | |
c19d1205 ZW |
9633 | if (inst.operands[1].writeback) |
9634 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 9635 | |
c19d1205 | 9636 | if (inst.operands[0].writeback) |
ea6ef066 | 9637 | { |
c19d1205 ZW |
9638 | inst.instruction |= WRITE_BACK; |
9639 | /* Check for unpredictable uses of writeback. */ | |
9640 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 9641 | { |
c19d1205 ZW |
9642 | /* Not allowed in LDM type 2. */ |
9643 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
9644 | && ((range & (1 << REG_PC)) == 0)) | |
9645 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
9646 | /* Only allowed if base reg not in list for other types. */ | |
9647 | else if (range & (1 << base_reg)) | |
9648 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
9649 | } | |
9650 | else /* STM. */ | |
9651 | { | |
9652 | /* Not allowed for type 2. */ | |
9653 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
9654 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
9655 | /* Only allowed if base reg not in list, or first in list. */ | |
9656 | else if ((range & (1 << base_reg)) | |
9657 | && (range & ((1 << base_reg) - 1))) | |
9658 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 9659 | } |
ea6ef066 | 9660 | } |
6530b175 NC |
9661 | |
9662 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
9663 | one_reg = only_one_reg_in_list (range); | |
9664 | if (from_push_pop_mnem && one_reg >= 0) | |
9665 | { | |
9666 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
9667 | ||
4f588891 NC |
9668 | if (is_push && one_reg == 13 /* SP */) |
9669 | /* PR 22483: The A2 encoding cannot be used when | |
9670 | pushing the stack pointer as this is UNPREDICTABLE. */ | |
9671 | return; | |
9672 | ||
6530b175 NC |
9673 | inst.instruction &= A_COND_MASK; |
9674 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
9675 | inst.instruction |= one_reg << 12; | |
9676 | } | |
9677 | } | |
9678 | ||
9679 | static void | |
9680 | do_ldmstm (void) | |
9681 | { | |
9682 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
9683 | } |
9684 | ||
c19d1205 ZW |
9685 | /* ARMv5TE load-consecutive (argument parse) |
9686 | Mode is like LDRH. | |
9687 | ||
9688 | LDRccD R, mode | |
9689 | STRccD R, mode. */ | |
9690 | ||
a737bd4d | 9691 | static void |
c19d1205 | 9692 | do_ldrd (void) |
a737bd4d | 9693 | { |
c19d1205 | 9694 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 9695 | _("first transfer register must be even")); |
c19d1205 ZW |
9696 | constraint (inst.operands[1].present |
9697 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 9698 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
9699 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
9700 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 9701 | |
c19d1205 ZW |
9702 | if (!inst.operands[1].present) |
9703 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 9704 | |
c56791bb RE |
9705 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
9706 | register and the first register written; we have to diagnose | |
9707 | overlap between the base and the second register written here. */ | |
ea6ef066 | 9708 | |
c56791bb RE |
9709 | if (inst.operands[2].reg == inst.operands[1].reg |
9710 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
9711 | as_warn (_("base register written back, and overlaps " | |
9712 | "second transfer register")); | |
b05fe5cf | 9713 | |
c56791bb RE |
9714 | if (!(inst.instruction & V4_STR_BIT)) |
9715 | { | |
c19d1205 | 9716 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
9717 | destination (even if not write-back). */ |
9718 | if (inst.operands[2].immisreg | |
9719 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
9720 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
9721 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 9722 | } |
c19d1205 ZW |
9723 | inst.instruction |= inst.operands[0].reg << 12; |
9724 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
9725 | } |
9726 | ||
9727 | static void | |
c19d1205 | 9728 | do_ldrex (void) |
b05fe5cf | 9729 | { |
c19d1205 ZW |
9730 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
9731 | || inst.operands[1].postind || inst.operands[1].writeback | |
9732 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
9733 | || inst.operands[1].negative |
9734 | /* This can arise if the programmer has written | |
9735 | strex rN, rM, foo | |
9736 | or if they have mistakenly used a register name as the last | |
9737 | operand, eg: | |
9738 | strex rN, rM, rX | |
9739 | It is very difficult to distinguish between these two cases | |
9740 | because "rX" might actually be a label. ie the register | |
9741 | name has been occluded by a symbol of the same name. So we | |
9742 | just generate a general 'bad addressing mode' type error | |
9743 | message and leave it up to the programmer to discover the | |
9744 | true cause and fix their mistake. */ | |
9745 | || (inst.operands[1].reg == REG_PC), | |
9746 | BAD_ADDR_MODE); | |
b05fe5cf | 9747 | |
e2b0ab59 AV |
9748 | constraint (inst.relocs[0].exp.X_op != O_constant |
9749 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 9750 | _("offset must be zero in ARM encoding")); |
b05fe5cf | 9751 | |
5be8be5d DG |
9752 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
9753 | ||
c19d1205 ZW |
9754 | inst.instruction |= inst.operands[0].reg << 12; |
9755 | inst.instruction |= inst.operands[1].reg << 16; | |
e2b0ab59 | 9756 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
b05fe5cf ZW |
9757 | } |
9758 | ||
9759 | static void | |
c19d1205 | 9760 | do_ldrexd (void) |
b05fe5cf | 9761 | { |
c19d1205 ZW |
9762 | constraint (inst.operands[0].reg % 2 != 0, |
9763 | _("even register required")); | |
9764 | constraint (inst.operands[1].present | |
9765 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
9766 | _("can only load two consecutive registers")); | |
9767 | /* If op 1 were present and equal to PC, this function wouldn't | |
9768 | have been called in the first place. */ | |
9769 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 9770 | |
c19d1205 ZW |
9771 | inst.instruction |= inst.operands[0].reg << 12; |
9772 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
9773 | } |
9774 | ||
1be5fd2e NC |
9775 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
9776 | which is not a multiple of four is UNPREDICTABLE. */ | |
9777 | static void | |
9778 | check_ldr_r15_aligned (void) | |
9779 | { | |
9780 | constraint (!(inst.operands[1].immisreg) | |
9781 | && (inst.operands[0].reg == REG_PC | |
9782 | && inst.operands[1].reg == REG_PC | |
e2b0ab59 | 9783 | && (inst.relocs[0].exp.X_add_number & 0x3)), |
de194d85 | 9784 | _("ldr to register 15 must be 4-byte aligned")); |
1be5fd2e NC |
9785 | } |
9786 | ||
b05fe5cf | 9787 | static void |
c19d1205 | 9788 | do_ldst (void) |
b05fe5cf | 9789 | { |
c19d1205 ZW |
9790 | inst.instruction |= inst.operands[0].reg << 12; |
9791 | if (!inst.operands[1].isreg) | |
8335d6aa | 9792 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 9793 | return; |
c19d1205 | 9794 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 9795 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
9796 | } |
9797 | ||
9798 | static void | |
c19d1205 | 9799 | do_ldstt (void) |
b05fe5cf | 9800 | { |
c19d1205 ZW |
9801 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
9802 | reject [Rn,...]. */ | |
9803 | if (inst.operands[1].preind) | |
b05fe5cf | 9804 | { |
e2b0ab59 AV |
9805 | constraint (inst.relocs[0].exp.X_op != O_constant |
9806 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 9807 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 9808 | |
c19d1205 ZW |
9809 | inst.operands[1].preind = 0; |
9810 | inst.operands[1].postind = 1; | |
9811 | inst.operands[1].writeback = 1; | |
b05fe5cf | 9812 | } |
c19d1205 ZW |
9813 | inst.instruction |= inst.operands[0].reg << 12; |
9814 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
9815 | } | |
b05fe5cf | 9816 | |
c19d1205 | 9817 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 9818 | |
c19d1205 ZW |
9819 | static void |
9820 | do_ldstv4 (void) | |
9821 | { | |
ff4a8d2b | 9822 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
9823 | inst.instruction |= inst.operands[0].reg << 12; |
9824 | if (!inst.operands[1].isreg) | |
8335d6aa | 9825 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 9826 | return; |
c19d1205 | 9827 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
9828 | } |
9829 | ||
9830 | static void | |
c19d1205 | 9831 | do_ldsttv4 (void) |
b05fe5cf | 9832 | { |
c19d1205 ZW |
9833 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
9834 | reject [Rn,...]. */ | |
9835 | if (inst.operands[1].preind) | |
b05fe5cf | 9836 | { |
e2b0ab59 AV |
9837 | constraint (inst.relocs[0].exp.X_op != O_constant |
9838 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 9839 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 9840 | |
c19d1205 ZW |
9841 | inst.operands[1].preind = 0; |
9842 | inst.operands[1].postind = 1; | |
9843 | inst.operands[1].writeback = 1; | |
b05fe5cf | 9844 | } |
c19d1205 ZW |
9845 | inst.instruction |= inst.operands[0].reg << 12; |
9846 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
9847 | } | |
b05fe5cf | 9848 | |
c19d1205 ZW |
9849 | /* Co-processor register load/store. |
9850 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
9851 | static void | |
9852 | do_lstc (void) | |
9853 | { | |
9854 | inst.instruction |= inst.operands[0].reg << 8; | |
9855 | inst.instruction |= inst.operands[1].reg << 12; | |
9856 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
9857 | } |
9858 | ||
b05fe5cf | 9859 | static void |
c19d1205 | 9860 | do_mlas (void) |
b05fe5cf | 9861 | { |
8fb9d7b9 | 9862 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 9863 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 9864 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 9865 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 9866 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 9867 | |
c19d1205 ZW |
9868 | inst.instruction |= inst.operands[0].reg << 16; |
9869 | inst.instruction |= inst.operands[1].reg; | |
9870 | inst.instruction |= inst.operands[2].reg << 8; | |
9871 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 9872 | } |
b05fe5cf | 9873 | |
c19d1205 ZW |
9874 | static void |
9875 | do_mov (void) | |
9876 | { | |
e2b0ab59 AV |
9877 | constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
9878 | && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC , | |
a9f02af8 | 9879 | THUMB1_RELOC_ONLY); |
c19d1205 ZW |
9880 | inst.instruction |= inst.operands[0].reg << 12; |
9881 | encode_arm_shifter_operand (1); | |
9882 | } | |
b05fe5cf | 9883 | |
c19d1205 ZW |
9884 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
9885 | static void | |
9886 | do_mov16 (void) | |
9887 | { | |
b6895b4f PB |
9888 | bfd_vma imm; |
9889 | bfd_boolean top; | |
9890 | ||
9891 | top = (inst.instruction & 0x00400000) != 0; | |
e2b0ab59 | 9892 | constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW, |
33eaf5de | 9893 | _(":lower16: not allowed in this instruction")); |
e2b0ab59 | 9894 | constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT, |
33eaf5de | 9895 | _(":upper16: not allowed in this instruction")); |
c19d1205 | 9896 | inst.instruction |= inst.operands[0].reg << 12; |
e2b0ab59 | 9897 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
b6895b4f | 9898 | { |
e2b0ab59 | 9899 | imm = inst.relocs[0].exp.X_add_number; |
b6895b4f PB |
9900 | /* The value is in two pieces: 0:11, 16:19. */ |
9901 | inst.instruction |= (imm & 0x00000fff); | |
9902 | inst.instruction |= (imm & 0x0000f000) << 4; | |
9903 | } | |
b05fe5cf | 9904 | } |
b99bd4ef | 9905 | |
037e8744 JB |
9906 | static int |
9907 | do_vfp_nsyn_mrs (void) | |
9908 | { | |
9909 | if (inst.operands[0].isvec) | |
9910 | { | |
9911 | if (inst.operands[1].reg != 1) | |
477330fc | 9912 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
9913 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
9914 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
9915 | do_vfp_nsyn_opcode ("fmstat"); | |
9916 | } | |
9917 | else if (inst.operands[1].isvec) | |
9918 | do_vfp_nsyn_opcode ("fmrx"); | |
9919 | else | |
9920 | return FAIL; | |
5f4273c7 | 9921 | |
037e8744 JB |
9922 | return SUCCESS; |
9923 | } | |
9924 | ||
9925 | static int | |
9926 | do_vfp_nsyn_msr (void) | |
9927 | { | |
9928 | if (inst.operands[0].isvec) | |
9929 | do_vfp_nsyn_opcode ("fmxr"); | |
9930 | else | |
9931 | return FAIL; | |
9932 | ||
9933 | return SUCCESS; | |
9934 | } | |
9935 | ||
f7c21dc7 NC |
9936 | static void |
9937 | do_vmrs (void) | |
9938 | { | |
9939 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 9940 | |
16d02dc9 | 9941 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
9942 | { |
9943 | inst.error = BAD_SP; | |
9944 | return; | |
9945 | } | |
9946 | ||
ba6cd17f SD |
9947 | switch (inst.operands[1].reg) |
9948 | { | |
9949 | /* MVFR2 is only valid for Armv8-A. */ | |
9950 | case 5: | |
9951 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
9952 | _(BAD_FPU)); | |
9953 | break; | |
9954 | ||
9955 | /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */ | |
9956 | case 1: /* fpscr. */ | |
9957 | constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
9958 | || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
9959 | _(BAD_FPU)); | |
9960 | break; | |
9961 | ||
9962 | case 14: /* fpcxt_ns. */ | |
9963 | case 15: /* fpcxt_s. */ | |
9964 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), | |
9965 | _("selected processor does not support instruction")); | |
9966 | break; | |
9967 | ||
9968 | case 2: /* fpscr_nzcvqc. */ | |
9969 | case 12: /* vpr. */ | |
9970 | case 13: /* p0. */ | |
9971 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main) | |
9972 | || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
9973 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
9974 | _("selected processor does not support instruction")); | |
9975 | if (inst.operands[0].reg != 2 | |
9976 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
9977 | as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE")); | |
9978 | break; | |
9979 | ||
9980 | default: | |
9981 | break; | |
9982 | } | |
40c7d507 | 9983 | |
f7c21dc7 | 9984 | /* APSR_ sets isvec. All other refs to PC are illegal. */ |
16d02dc9 | 9985 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
9986 | { |
9987 | inst.error = BAD_PC; | |
9988 | return; | |
9989 | } | |
9990 | ||
16d02dc9 JB |
9991 | /* If we get through parsing the register name, we just insert the number |
9992 | generated into the instruction without further validation. */ | |
9993 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
9994 | inst.instruction |= (Rt << 12); |
9995 | } | |
9996 | ||
9997 | static void | |
9998 | do_vmsr (void) | |
9999 | { | |
10000 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 10001 | |
f7c21dc7 NC |
10002 | if (thumb_mode) |
10003 | reject_bad_reg (Rt); | |
10004 | else if (Rt == REG_PC) | |
10005 | { | |
10006 | inst.error = BAD_PC; | |
10007 | return; | |
10008 | } | |
10009 | ||
ba6cd17f SD |
10010 | switch (inst.operands[0].reg) |
10011 | { | |
10012 | /* MVFR2 is only valid for Armv8-A. */ | |
10013 | case 5: | |
10014 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
10015 | _(BAD_FPU)); | |
10016 | break; | |
10017 | ||
10018 | /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */ | |
10019 | case 1: /* fpcr. */ | |
10020 | constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
10021 | || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
10022 | _(BAD_FPU)); | |
10023 | break; | |
10024 | ||
10025 | case 14: /* fpcxt_ns. */ | |
10026 | case 15: /* fpcxt_s. */ | |
10027 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), | |
10028 | _("selected processor does not support instruction")); | |
10029 | break; | |
10030 | ||
10031 | case 2: /* fpscr_nzcvqc. */ | |
10032 | case 12: /* vpr. */ | |
10033 | case 13: /* p0. */ | |
10034 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main) | |
10035 | || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
10036 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)), | |
10037 | _("selected processor does not support instruction")); | |
10038 | if (inst.operands[0].reg != 2 | |
10039 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
10040 | as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE")); | |
10041 | break; | |
10042 | ||
10043 | default: | |
10044 | break; | |
10045 | } | |
40c7d507 | 10046 | |
16d02dc9 JB |
10047 | /* If we get through parsing the register name, we just insert the number |
10048 | generated into the instruction without further validation. */ | |
10049 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
10050 | inst.instruction |= (Rt << 12); |
10051 | } | |
10052 | ||
b99bd4ef | 10053 | static void |
c19d1205 | 10054 | do_mrs (void) |
b99bd4ef | 10055 | { |
90ec0d68 MGD |
10056 | unsigned br; |
10057 | ||
037e8744 JB |
10058 | if (do_vfp_nsyn_mrs () == SUCCESS) |
10059 | return; | |
10060 | ||
ff4a8d2b | 10061 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 10062 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
10063 | |
10064 | if (inst.operands[1].isreg) | |
10065 | { | |
10066 | br = inst.operands[1].reg; | |
806ab1c0 | 10067 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000)) |
90ec0d68 MGD |
10068 | as_bad (_("bad register for mrs")); |
10069 | } | |
10070 | else | |
10071 | { | |
10072 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
10073 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
10074 | != (PSR_c|PSR_f), | |
d2cd1205 | 10075 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
10076 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
10077 | } | |
10078 | ||
10079 | inst.instruction |= br; | |
c19d1205 | 10080 | } |
b99bd4ef | 10081 | |
c19d1205 ZW |
10082 | /* Two possible forms: |
10083 | "{C|S}PSR_<field>, Rm", | |
10084 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 10085 | |
c19d1205 ZW |
10086 | static void |
10087 | do_msr (void) | |
10088 | { | |
037e8744 JB |
10089 | if (do_vfp_nsyn_msr () == SUCCESS) |
10090 | return; | |
10091 | ||
c19d1205 ZW |
10092 | inst.instruction |= inst.operands[0].imm; |
10093 | if (inst.operands[1].isreg) | |
10094 | inst.instruction |= inst.operands[1].reg; | |
10095 | else | |
b99bd4ef | 10096 | { |
c19d1205 | 10097 | inst.instruction |= INST_IMMEDIATE; |
e2b0ab59 AV |
10098 | inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE; |
10099 | inst.relocs[0].pc_rel = 0; | |
b99bd4ef | 10100 | } |
b99bd4ef NC |
10101 | } |
10102 | ||
c19d1205 ZW |
10103 | static void |
10104 | do_mul (void) | |
a737bd4d | 10105 | { |
ff4a8d2b NC |
10106 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
10107 | ||
c19d1205 ZW |
10108 | if (!inst.operands[2].present) |
10109 | inst.operands[2].reg = inst.operands[0].reg; | |
10110 | inst.instruction |= inst.operands[0].reg << 16; | |
10111 | inst.instruction |= inst.operands[1].reg; | |
10112 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 10113 | |
8fb9d7b9 MS |
10114 | if (inst.operands[0].reg == inst.operands[1].reg |
10115 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
10116 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
10117 | } |
10118 | ||
c19d1205 ZW |
10119 | /* Long Multiply Parser |
10120 | UMULL RdLo, RdHi, Rm, Rs | |
10121 | SMULL RdLo, RdHi, Rm, Rs | |
10122 | UMLAL RdLo, RdHi, Rm, Rs | |
10123 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
10124 | |
10125 | static void | |
c19d1205 | 10126 | do_mull (void) |
b99bd4ef | 10127 | { |
c19d1205 ZW |
10128 | inst.instruction |= inst.operands[0].reg << 12; |
10129 | inst.instruction |= inst.operands[1].reg << 16; | |
10130 | inst.instruction |= inst.operands[2].reg; | |
10131 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 10132 | |
682b27ad PB |
10133 | /* rdhi and rdlo must be different. */ |
10134 | if (inst.operands[0].reg == inst.operands[1].reg) | |
10135 | as_tsktsk (_("rdhi and rdlo must be different")); | |
10136 | ||
10137 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
10138 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 10139 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 10140 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
10141 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
10142 | } | |
b99bd4ef | 10143 | |
c19d1205 ZW |
10144 | static void |
10145 | do_nop (void) | |
10146 | { | |
e7495e45 NS |
10147 | if (inst.operands[0].present |
10148 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
10149 | { |
10150 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
10151 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
10152 | inst.instruction |= 0x0320f000; |
10153 | if (inst.operands[0].present) | |
10154 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 10155 | } |
b99bd4ef NC |
10156 | } |
10157 | ||
c19d1205 ZW |
10158 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
10159 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
10160 | Condition defaults to COND_ALWAYS. | |
10161 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
10162 | |
10163 | static void | |
c19d1205 | 10164 | do_pkhbt (void) |
b99bd4ef | 10165 | { |
c19d1205 ZW |
10166 | inst.instruction |= inst.operands[0].reg << 12; |
10167 | inst.instruction |= inst.operands[1].reg << 16; | |
10168 | inst.instruction |= inst.operands[2].reg; | |
10169 | if (inst.operands[3].present) | |
10170 | encode_arm_shift (3); | |
10171 | } | |
b99bd4ef | 10172 | |
c19d1205 | 10173 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 10174 | |
c19d1205 ZW |
10175 | static void |
10176 | do_pkhtb (void) | |
10177 | { | |
10178 | if (!inst.operands[3].present) | |
b99bd4ef | 10179 | { |
c19d1205 ZW |
10180 | /* If the shift specifier is omitted, turn the instruction |
10181 | into pkhbt rd, rm, rn. */ | |
10182 | inst.instruction &= 0xfff00010; | |
10183 | inst.instruction |= inst.operands[0].reg << 12; | |
10184 | inst.instruction |= inst.operands[1].reg; | |
10185 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10186 | } |
10187 | else | |
10188 | { | |
c19d1205 ZW |
10189 | inst.instruction |= inst.operands[0].reg << 12; |
10190 | inst.instruction |= inst.operands[1].reg << 16; | |
10191 | inst.instruction |= inst.operands[2].reg; | |
10192 | encode_arm_shift (3); | |
b99bd4ef NC |
10193 | } |
10194 | } | |
10195 | ||
c19d1205 | 10196 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 10197 | MP Extensions: Preload for write |
c19d1205 | 10198 | |
60e5ef9f | 10199 | PLD(W) <addr_mode> |
c19d1205 ZW |
10200 | |
10201 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
10202 | |
10203 | static void | |
c19d1205 | 10204 | do_pld (void) |
b99bd4ef | 10205 | { |
c19d1205 ZW |
10206 | constraint (!inst.operands[0].isreg, |
10207 | _("'[' expected after PLD mnemonic")); | |
10208 | constraint (inst.operands[0].postind, | |
10209 | _("post-indexed expression used in preload instruction")); | |
10210 | constraint (inst.operands[0].writeback, | |
10211 | _("writeback used in preload instruction")); | |
10212 | constraint (!inst.operands[0].preind, | |
10213 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
10214 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
10215 | } | |
b99bd4ef | 10216 | |
62b3e311 PB |
10217 | /* ARMv7: PLI <addr_mode> */ |
10218 | static void | |
10219 | do_pli (void) | |
10220 | { | |
10221 | constraint (!inst.operands[0].isreg, | |
10222 | _("'[' expected after PLI mnemonic")); | |
10223 | constraint (inst.operands[0].postind, | |
10224 | _("post-indexed expression used in preload instruction")); | |
10225 | constraint (inst.operands[0].writeback, | |
10226 | _("writeback used in preload instruction")); | |
10227 | constraint (!inst.operands[0].preind, | |
10228 | _("unindexed addressing used in preload instruction")); | |
10229 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
10230 | inst.instruction &= ~PRE_INDEX; | |
10231 | } | |
10232 | ||
c19d1205 ZW |
10233 | static void |
10234 | do_push_pop (void) | |
10235 | { | |
5e0d7f77 MP |
10236 | constraint (inst.operands[0].writeback, |
10237 | _("push/pop do not support {reglist}^")); | |
c19d1205 ZW |
10238 | inst.operands[1] = inst.operands[0]; |
10239 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
10240 | inst.operands[0].isreg = 1; | |
10241 | inst.operands[0].writeback = 1; | |
10242 | inst.operands[0].reg = REG_SP; | |
6530b175 | 10243 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 10244 | } |
b99bd4ef | 10245 | |
c19d1205 ZW |
10246 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
10247 | word at the specified address and the following word | |
10248 | respectively. | |
10249 | Unconditionally executed. | |
10250 | Error if Rn is R15. */ | |
b99bd4ef | 10251 | |
c19d1205 ZW |
10252 | static void |
10253 | do_rfe (void) | |
10254 | { | |
10255 | inst.instruction |= inst.operands[0].reg << 16; | |
10256 | if (inst.operands[0].writeback) | |
10257 | inst.instruction |= WRITE_BACK; | |
10258 | } | |
b99bd4ef | 10259 | |
c19d1205 | 10260 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 10261 | |
c19d1205 ZW |
10262 | static void |
10263 | do_ssat (void) | |
10264 | { | |
10265 | inst.instruction |= inst.operands[0].reg << 12; | |
10266 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
10267 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 10268 | |
c19d1205 ZW |
10269 | if (inst.operands[3].present) |
10270 | encode_arm_shift (3); | |
b99bd4ef NC |
10271 | } |
10272 | ||
c19d1205 | 10273 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
10274 | |
10275 | static void | |
c19d1205 | 10276 | do_usat (void) |
b99bd4ef | 10277 | { |
c19d1205 ZW |
10278 | inst.instruction |= inst.operands[0].reg << 12; |
10279 | inst.instruction |= inst.operands[1].imm << 16; | |
10280 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 10281 | |
c19d1205 ZW |
10282 | if (inst.operands[3].present) |
10283 | encode_arm_shift (3); | |
b99bd4ef NC |
10284 | } |
10285 | ||
c19d1205 | 10286 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
10287 | |
10288 | static void | |
c19d1205 | 10289 | do_ssat16 (void) |
09d92015 | 10290 | { |
c19d1205 ZW |
10291 | inst.instruction |= inst.operands[0].reg << 12; |
10292 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
10293 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
10294 | } |
10295 | ||
c19d1205 ZW |
10296 | static void |
10297 | do_usat16 (void) | |
a737bd4d | 10298 | { |
c19d1205 ZW |
10299 | inst.instruction |= inst.operands[0].reg << 12; |
10300 | inst.instruction |= inst.operands[1].imm << 16; | |
10301 | inst.instruction |= inst.operands[2].reg; | |
10302 | } | |
a737bd4d | 10303 | |
c19d1205 ZW |
10304 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
10305 | preserving the other bits. | |
a737bd4d | 10306 | |
c19d1205 ZW |
10307 | setend <endian_specifier>, where <endian_specifier> is either |
10308 | BE or LE. */ | |
a737bd4d | 10309 | |
c19d1205 ZW |
10310 | static void |
10311 | do_setend (void) | |
10312 | { | |
12e37cbc MGD |
10313 | if (warn_on_deprecated |
10314 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 10315 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 10316 | |
c19d1205 ZW |
10317 | if (inst.operands[0].imm) |
10318 | inst.instruction |= 0x200; | |
a737bd4d NC |
10319 | } |
10320 | ||
10321 | static void | |
c19d1205 | 10322 | do_shift (void) |
a737bd4d | 10323 | { |
c19d1205 ZW |
10324 | unsigned int Rm = (inst.operands[1].present |
10325 | ? inst.operands[1].reg | |
10326 | : inst.operands[0].reg); | |
a737bd4d | 10327 | |
c19d1205 ZW |
10328 | inst.instruction |= inst.operands[0].reg << 12; |
10329 | inst.instruction |= Rm; | |
10330 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 10331 | { |
c19d1205 ZW |
10332 | inst.instruction |= inst.operands[2].reg << 8; |
10333 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
10334 | /* PR 12854: Error on extraneous shifts. */ |
10335 | constraint (inst.operands[2].shifted, | |
10336 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
10337 | } |
10338 | else | |
e2b0ab59 | 10339 | inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
10340 | } |
10341 | ||
09d92015 | 10342 | static void |
3eb17e6b | 10343 | do_smc (void) |
09d92015 | 10344 | { |
ba85f98c BW |
10345 | unsigned int value = inst.relocs[0].exp.X_add_number; |
10346 | constraint (value > 0xf, _("immediate too large (bigger than 0xF)")); | |
10347 | ||
e2b0ab59 AV |
10348 | inst.relocs[0].type = BFD_RELOC_ARM_SMC; |
10349 | inst.relocs[0].pc_rel = 0; | |
09d92015 MM |
10350 | } |
10351 | ||
90ec0d68 MGD |
10352 | static void |
10353 | do_hvc (void) | |
10354 | { | |
e2b0ab59 AV |
10355 | inst.relocs[0].type = BFD_RELOC_ARM_HVC; |
10356 | inst.relocs[0].pc_rel = 0; | |
90ec0d68 MGD |
10357 | } |
10358 | ||
09d92015 | 10359 | static void |
c19d1205 | 10360 | do_swi (void) |
09d92015 | 10361 | { |
e2b0ab59 AV |
10362 | inst.relocs[0].type = BFD_RELOC_ARM_SWI; |
10363 | inst.relocs[0].pc_rel = 0; | |
09d92015 MM |
10364 | } |
10365 | ||
ddfded2f MW |
10366 | static void |
10367 | do_setpan (void) | |
10368 | { | |
10369 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
10370 | _("selected processor does not support SETPAN instruction")); | |
10371 | ||
10372 | inst.instruction |= ((inst.operands[0].imm & 1) << 9); | |
10373 | } | |
10374 | ||
10375 | static void | |
10376 | do_t_setpan (void) | |
10377 | { | |
10378 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
10379 | _("selected processor does not support SETPAN instruction")); | |
10380 | ||
10381 | inst.instruction |= (inst.operands[0].imm << 3); | |
10382 | } | |
10383 | ||
c19d1205 ZW |
10384 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
10385 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
10386 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
10387 | Error if any register is R15. */ | |
e16bb312 | 10388 | |
c19d1205 ZW |
10389 | static void |
10390 | do_smla (void) | |
e16bb312 | 10391 | { |
c19d1205 ZW |
10392 | inst.instruction |= inst.operands[0].reg << 16; |
10393 | inst.instruction |= inst.operands[1].reg; | |
10394 | inst.instruction |= inst.operands[2].reg << 8; | |
10395 | inst.instruction |= inst.operands[3].reg << 12; | |
10396 | } | |
a737bd4d | 10397 | |
c19d1205 ZW |
10398 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
10399 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
10400 | Error if any register is R15. | |
10401 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 10402 | |
c19d1205 ZW |
10403 | static void |
10404 | do_smlal (void) | |
10405 | { | |
10406 | inst.instruction |= inst.operands[0].reg << 12; | |
10407 | inst.instruction |= inst.operands[1].reg << 16; | |
10408 | inst.instruction |= inst.operands[2].reg; | |
10409 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 10410 | |
c19d1205 ZW |
10411 | if (inst.operands[0].reg == inst.operands[1].reg) |
10412 | as_tsktsk (_("rdhi and rdlo must be different")); | |
10413 | } | |
a737bd4d | 10414 | |
c19d1205 ZW |
10415 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
10416 | SMULxy{cond} Rd,Rm,Rs | |
10417 | Error if any register is R15. */ | |
a737bd4d | 10418 | |
c19d1205 ZW |
10419 | static void |
10420 | do_smul (void) | |
10421 | { | |
10422 | inst.instruction |= inst.operands[0].reg << 16; | |
10423 | inst.instruction |= inst.operands[1].reg; | |
10424 | inst.instruction |= inst.operands[2].reg << 8; | |
10425 | } | |
a737bd4d | 10426 | |
b6702015 PB |
10427 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
10428 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 10429 | |
c19d1205 ZW |
10430 | static void |
10431 | do_srs (void) | |
10432 | { | |
b6702015 PB |
10433 | int reg; |
10434 | ||
10435 | if (inst.operands[0].present) | |
10436 | { | |
10437 | reg = inst.operands[0].reg; | |
fdfde340 | 10438 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
10439 | } |
10440 | else | |
fdfde340 | 10441 | reg = REG_SP; |
b6702015 PB |
10442 | |
10443 | inst.instruction |= reg << 16; | |
10444 | inst.instruction |= inst.operands[1].imm; | |
10445 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
10446 | inst.instruction |= WRITE_BACK; |
10447 | } | |
a737bd4d | 10448 | |
c19d1205 | 10449 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 10450 | |
c19d1205 ZW |
10451 | static void |
10452 | do_strex (void) | |
10453 | { | |
10454 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
10455 | || inst.operands[2].postind || inst.operands[2].writeback | |
10456 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
10457 | || inst.operands[2].negative |
10458 | /* See comment in do_ldrex(). */ | |
10459 | || (inst.operands[2].reg == REG_PC), | |
10460 | BAD_ADDR_MODE); | |
a737bd4d | 10461 | |
c19d1205 ZW |
10462 | constraint (inst.operands[0].reg == inst.operands[1].reg |
10463 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 10464 | |
e2b0ab59 AV |
10465 | constraint (inst.relocs[0].exp.X_op != O_constant |
10466 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 10467 | _("offset must be zero in ARM encoding")); |
a737bd4d | 10468 | |
c19d1205 ZW |
10469 | inst.instruction |= inst.operands[0].reg << 12; |
10470 | inst.instruction |= inst.operands[1].reg; | |
10471 | inst.instruction |= inst.operands[2].reg << 16; | |
e2b0ab59 | 10472 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
e16bb312 NC |
10473 | } |
10474 | ||
877807f8 NC |
10475 | static void |
10476 | do_t_strexbh (void) | |
10477 | { | |
10478 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
10479 | || inst.operands[2].postind || inst.operands[2].writeback | |
10480 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
10481 | || inst.operands[2].negative, | |
10482 | BAD_ADDR_MODE); | |
10483 | ||
10484 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
10485 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
10486 | ||
10487 | do_rm_rd_rn (); | |
10488 | } | |
10489 | ||
e16bb312 | 10490 | static void |
c19d1205 | 10491 | do_strexd (void) |
e16bb312 | 10492 | { |
c19d1205 ZW |
10493 | constraint (inst.operands[1].reg % 2 != 0, |
10494 | _("even register required")); | |
10495 | constraint (inst.operands[2].present | |
10496 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
10497 | _("can only store two consecutive registers")); | |
10498 | /* If op 2 were present and equal to PC, this function wouldn't | |
10499 | have been called in the first place. */ | |
10500 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 10501 | |
c19d1205 ZW |
10502 | constraint (inst.operands[0].reg == inst.operands[1].reg |
10503 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
10504 | || inst.operands[0].reg == inst.operands[3].reg, | |
10505 | BAD_OVERLAP); | |
e16bb312 | 10506 | |
c19d1205 ZW |
10507 | inst.instruction |= inst.operands[0].reg << 12; |
10508 | inst.instruction |= inst.operands[1].reg; | |
10509 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
10510 | } |
10511 | ||
9eb6c0f1 MGD |
10512 | /* ARM V8 STRL. */ |
10513 | static void | |
4b8c8c02 | 10514 | do_stlex (void) |
9eb6c0f1 MGD |
10515 | { |
10516 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
10517 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
10518 | ||
10519 | do_rd_rm_rn (); | |
10520 | } | |
10521 | ||
10522 | static void | |
4b8c8c02 | 10523 | do_t_stlex (void) |
9eb6c0f1 MGD |
10524 | { |
10525 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
10526 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
10527 | ||
10528 | do_rm_rd_rn (); | |
10529 | } | |
10530 | ||
c19d1205 ZW |
10531 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
10532 | extends it to 32-bits, and adds the result to a value in another | |
10533 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
10534 | before extracting the 16-bit value. | |
10535 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
10536 | Condition defaults to COND_ALWAYS. | |
10537 | Error if any register uses R15. */ | |
10538 | ||
e16bb312 | 10539 | static void |
c19d1205 | 10540 | do_sxtah (void) |
e16bb312 | 10541 | { |
c19d1205 ZW |
10542 | inst.instruction |= inst.operands[0].reg << 12; |
10543 | inst.instruction |= inst.operands[1].reg << 16; | |
10544 | inst.instruction |= inst.operands[2].reg; | |
10545 | inst.instruction |= inst.operands[3].imm << 10; | |
10546 | } | |
e16bb312 | 10547 | |
c19d1205 | 10548 | /* ARM V6 SXTH. |
e16bb312 | 10549 | |
c19d1205 ZW |
10550 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
10551 | Condition defaults to COND_ALWAYS. | |
10552 | Error if any register uses R15. */ | |
e16bb312 NC |
10553 | |
10554 | static void | |
c19d1205 | 10555 | do_sxth (void) |
e16bb312 | 10556 | { |
c19d1205 ZW |
10557 | inst.instruction |= inst.operands[0].reg << 12; |
10558 | inst.instruction |= inst.operands[1].reg; | |
10559 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 10560 | } |
c19d1205 ZW |
10561 | \f |
10562 | /* VFP instructions. In a logical order: SP variant first, monad | |
10563 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
10564 | |
10565 | static void | |
c19d1205 | 10566 | do_vfp_sp_monadic (void) |
e16bb312 | 10567 | { |
57785aa2 AV |
10568 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
10569 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10570 | _(BAD_FPU)); | |
10571 | ||
5287ad62 JB |
10572 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
10573 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
10574 | } |
10575 | ||
10576 | static void | |
c19d1205 | 10577 | do_vfp_sp_dyadic (void) |
e16bb312 | 10578 | { |
5287ad62 JB |
10579 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
10580 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
10581 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
10582 | } |
10583 | ||
10584 | static void | |
c19d1205 | 10585 | do_vfp_sp_compare_z (void) |
e16bb312 | 10586 | { |
5287ad62 | 10587 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
10588 | } |
10589 | ||
10590 | static void | |
c19d1205 | 10591 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 10592 | { |
5287ad62 JB |
10593 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
10594 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
10595 | } |
10596 | ||
10597 | static void | |
c19d1205 | 10598 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 10599 | { |
5287ad62 JB |
10600 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
10601 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
10602 | } |
10603 | ||
10604 | static void | |
c19d1205 | 10605 | do_vfp_reg_from_sp (void) |
e16bb312 | 10606 | { |
57785aa2 AV |
10607 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
10608 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10609 | _(BAD_FPU)); | |
10610 | ||
c19d1205 | 10611 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 10612 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
10613 | } |
10614 | ||
10615 | static void | |
c19d1205 | 10616 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 10617 | { |
c19d1205 ZW |
10618 | constraint (inst.operands[2].imm != 2, |
10619 | _("only two consecutive VFP SP registers allowed here")); | |
10620 | inst.instruction |= inst.operands[0].reg << 12; | |
10621 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 10622 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
10623 | } |
10624 | ||
10625 | static void | |
c19d1205 | 10626 | do_vfp_sp_from_reg (void) |
e16bb312 | 10627 | { |
57785aa2 AV |
10628 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) |
10629 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10630 | _(BAD_FPU)); | |
10631 | ||
5287ad62 | 10632 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 10633 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
10634 | } |
10635 | ||
10636 | static void | |
c19d1205 | 10637 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 10638 | { |
c19d1205 ZW |
10639 | constraint (inst.operands[0].imm != 2, |
10640 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 10641 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
10642 | inst.instruction |= inst.operands[1].reg << 12; |
10643 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
10644 | } |
10645 | ||
10646 | static void | |
c19d1205 | 10647 | do_vfp_sp_ldst (void) |
e16bb312 | 10648 | { |
5287ad62 | 10649 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 10650 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
10651 | } |
10652 | ||
10653 | static void | |
c19d1205 | 10654 | do_vfp_dp_ldst (void) |
e16bb312 | 10655 | { |
5287ad62 | 10656 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 10657 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
10658 | } |
10659 | ||
c19d1205 | 10660 | |
e16bb312 | 10661 | static void |
c19d1205 | 10662 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 10663 | { |
c19d1205 ZW |
10664 | if (inst.operands[0].writeback) |
10665 | inst.instruction |= WRITE_BACK; | |
10666 | else | |
10667 | constraint (ldstm_type != VFP_LDSTMIA, | |
10668 | _("this addressing mode requires base-register writeback")); | |
10669 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 10670 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 10671 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
10672 | } |
10673 | ||
10674 | static void | |
c19d1205 | 10675 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 10676 | { |
c19d1205 | 10677 | int count; |
e16bb312 | 10678 | |
c19d1205 ZW |
10679 | if (inst.operands[0].writeback) |
10680 | inst.instruction |= WRITE_BACK; | |
10681 | else | |
10682 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
10683 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 10684 | |
c19d1205 | 10685 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 10686 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 10687 | |
c19d1205 ZW |
10688 | count = inst.operands[1].imm << 1; |
10689 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
10690 | count += 1; | |
e16bb312 | 10691 | |
c19d1205 | 10692 | inst.instruction |= count; |
e16bb312 NC |
10693 | } |
10694 | ||
10695 | static void | |
c19d1205 | 10696 | do_vfp_sp_ldstmia (void) |
e16bb312 | 10697 | { |
c19d1205 | 10698 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
10699 | } |
10700 | ||
10701 | static void | |
c19d1205 | 10702 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 10703 | { |
c19d1205 | 10704 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
10705 | } |
10706 | ||
10707 | static void | |
c19d1205 | 10708 | do_vfp_dp_ldstmia (void) |
e16bb312 | 10709 | { |
c19d1205 | 10710 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
10711 | } |
10712 | ||
10713 | static void | |
c19d1205 | 10714 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 10715 | { |
c19d1205 | 10716 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
10717 | } |
10718 | ||
10719 | static void | |
c19d1205 | 10720 | do_vfp_xp_ldstmia (void) |
e16bb312 | 10721 | { |
c19d1205 ZW |
10722 | vfp_dp_ldstm (VFP_LDSTMIAX); |
10723 | } | |
e16bb312 | 10724 | |
c19d1205 ZW |
10725 | static void |
10726 | do_vfp_xp_ldstmdb (void) | |
10727 | { | |
10728 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 10729 | } |
5287ad62 JB |
10730 | |
10731 | static void | |
10732 | do_vfp_dp_rd_rm (void) | |
10733 | { | |
57785aa2 AV |
10734 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) |
10735 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10736 | _(BAD_FPU)); | |
10737 | ||
5287ad62 JB |
10738 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
10739 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
10740 | } | |
10741 | ||
10742 | static void | |
10743 | do_vfp_dp_rn_rd (void) | |
10744 | { | |
10745 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
10746 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
10747 | } | |
10748 | ||
10749 | static void | |
10750 | do_vfp_dp_rd_rn (void) | |
10751 | { | |
10752 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10753 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
10754 | } | |
10755 | ||
10756 | static void | |
10757 | do_vfp_dp_rd_rn_rm (void) | |
10758 | { | |
57785aa2 AV |
10759 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
10760 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10761 | _(BAD_FPU)); | |
10762 | ||
5287ad62 JB |
10763 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
10764 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
10765 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
10766 | } | |
10767 | ||
10768 | static void | |
10769 | do_vfp_dp_rd (void) | |
10770 | { | |
10771 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10772 | } | |
10773 | ||
10774 | static void | |
10775 | do_vfp_dp_rm_rd_rn (void) | |
10776 | { | |
57785aa2 AV |
10777 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
10778 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
10779 | _(BAD_FPU)); | |
10780 | ||
5287ad62 JB |
10781 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); |
10782 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
10783 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
10784 | } | |
10785 | ||
10786 | /* VFPv3 instructions. */ | |
10787 | static void | |
10788 | do_vfp_sp_const (void) | |
10789 | { | |
10790 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
10791 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
10792 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
10793 | } |
10794 | ||
10795 | static void | |
10796 | do_vfp_dp_const (void) | |
10797 | { | |
10798 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
10799 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
10800 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
10801 | } |
10802 | ||
10803 | static void | |
10804 | vfp_conv (int srcsize) | |
10805 | { | |
5f1af56b MGD |
10806 | int immbits = srcsize - inst.operands[1].imm; |
10807 | ||
fa94de6b RM |
10808 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
10809 | { | |
5f1af56b | 10810 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 10811 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
10812 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
10813 | return; | |
10814 | } | |
fa94de6b | 10815 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
10816 | { |
10817 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 10818 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
10819 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
10820 | return; | |
10821 | } | |
10822 | ||
5287ad62 JB |
10823 | inst.instruction |= (immbits & 1) << 5; |
10824 | inst.instruction |= (immbits >> 1); | |
10825 | } | |
10826 | ||
10827 | static void | |
10828 | do_vfp_sp_conv_16 (void) | |
10829 | { | |
10830 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
10831 | vfp_conv (16); | |
10832 | } | |
10833 | ||
10834 | static void | |
10835 | do_vfp_dp_conv_16 (void) | |
10836 | { | |
10837 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10838 | vfp_conv (16); | |
10839 | } | |
10840 | ||
10841 | static void | |
10842 | do_vfp_sp_conv_32 (void) | |
10843 | { | |
10844 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
10845 | vfp_conv (32); | |
10846 | } | |
10847 | ||
10848 | static void | |
10849 | do_vfp_dp_conv_32 (void) | |
10850 | { | |
10851 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
10852 | vfp_conv (32); | |
10853 | } | |
c19d1205 ZW |
10854 | \f |
10855 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 10856 | |
c19d1205 ZW |
10857 | static void |
10858 | do_fpa_cmp (void) | |
10859 | { | |
10860 | inst.instruction |= inst.operands[0].reg << 16; | |
10861 | inst.instruction |= inst.operands[1].reg; | |
10862 | } | |
b99bd4ef NC |
10863 | |
10864 | static void | |
c19d1205 | 10865 | do_fpa_ldmstm (void) |
b99bd4ef | 10866 | { |
c19d1205 ZW |
10867 | inst.instruction |= inst.operands[0].reg << 12; |
10868 | switch (inst.operands[1].imm) | |
10869 | { | |
10870 | case 1: inst.instruction |= CP_T_X; break; | |
10871 | case 2: inst.instruction |= CP_T_Y; break; | |
10872 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
10873 | case 4: break; | |
10874 | default: abort (); | |
10875 | } | |
b99bd4ef | 10876 | |
c19d1205 ZW |
10877 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
10878 | { | |
10879 | /* The instruction specified "ea" or "fd", so we can only accept | |
10880 | [Rn]{!}. The instruction does not really support stacking or | |
10881 | unstacking, so we have to emulate these by setting appropriate | |
10882 | bits and offsets. */ | |
e2b0ab59 AV |
10883 | constraint (inst.relocs[0].exp.X_op != O_constant |
10884 | || inst.relocs[0].exp.X_add_number != 0, | |
c19d1205 | 10885 | _("this instruction does not support indexing")); |
b99bd4ef | 10886 | |
c19d1205 | 10887 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
e2b0ab59 | 10888 | inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm; |
b99bd4ef | 10889 | |
c19d1205 | 10890 | if (!(inst.instruction & INDEX_UP)) |
e2b0ab59 | 10891 | inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number; |
b99bd4ef | 10892 | |
c19d1205 ZW |
10893 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
10894 | { | |
10895 | inst.operands[2].preind = 0; | |
10896 | inst.operands[2].postind = 1; | |
10897 | } | |
10898 | } | |
b99bd4ef | 10899 | |
c19d1205 | 10900 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 10901 | } |
c19d1205 ZW |
10902 | \f |
10903 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 10904 | |
c19d1205 ZW |
10905 | static void |
10906 | do_iwmmxt_tandorc (void) | |
10907 | { | |
10908 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
10909 | } | |
b99bd4ef | 10910 | |
c19d1205 ZW |
10911 | static void |
10912 | do_iwmmxt_textrc (void) | |
10913 | { | |
10914 | inst.instruction |= inst.operands[0].reg << 12; | |
10915 | inst.instruction |= inst.operands[1].imm; | |
10916 | } | |
b99bd4ef NC |
10917 | |
10918 | static void | |
c19d1205 | 10919 | do_iwmmxt_textrm (void) |
b99bd4ef | 10920 | { |
c19d1205 ZW |
10921 | inst.instruction |= inst.operands[0].reg << 12; |
10922 | inst.instruction |= inst.operands[1].reg << 16; | |
10923 | inst.instruction |= inst.operands[2].imm; | |
10924 | } | |
b99bd4ef | 10925 | |
c19d1205 ZW |
10926 | static void |
10927 | do_iwmmxt_tinsr (void) | |
10928 | { | |
10929 | inst.instruction |= inst.operands[0].reg << 16; | |
10930 | inst.instruction |= inst.operands[1].reg << 12; | |
10931 | inst.instruction |= inst.operands[2].imm; | |
10932 | } | |
b99bd4ef | 10933 | |
c19d1205 ZW |
10934 | static void |
10935 | do_iwmmxt_tmia (void) | |
10936 | { | |
10937 | inst.instruction |= inst.operands[0].reg << 5; | |
10938 | inst.instruction |= inst.operands[1].reg; | |
10939 | inst.instruction |= inst.operands[2].reg << 12; | |
10940 | } | |
b99bd4ef | 10941 | |
c19d1205 ZW |
10942 | static void |
10943 | do_iwmmxt_waligni (void) | |
10944 | { | |
10945 | inst.instruction |= inst.operands[0].reg << 12; | |
10946 | inst.instruction |= inst.operands[1].reg << 16; | |
10947 | inst.instruction |= inst.operands[2].reg; | |
10948 | inst.instruction |= inst.operands[3].imm << 20; | |
10949 | } | |
b99bd4ef | 10950 | |
2d447fca JM |
10951 | static void |
10952 | do_iwmmxt_wmerge (void) | |
10953 | { | |
10954 | inst.instruction |= inst.operands[0].reg << 12; | |
10955 | inst.instruction |= inst.operands[1].reg << 16; | |
10956 | inst.instruction |= inst.operands[2].reg; | |
10957 | inst.instruction |= inst.operands[3].imm << 21; | |
10958 | } | |
10959 | ||
c19d1205 ZW |
10960 | static void |
10961 | do_iwmmxt_wmov (void) | |
10962 | { | |
10963 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
10964 | inst.instruction |= inst.operands[0].reg << 12; | |
10965 | inst.instruction |= inst.operands[1].reg << 16; | |
10966 | inst.instruction |= inst.operands[1].reg; | |
10967 | } | |
b99bd4ef | 10968 | |
c19d1205 ZW |
10969 | static void |
10970 | do_iwmmxt_wldstbh (void) | |
10971 | { | |
8f06b2d8 | 10972 | int reloc; |
c19d1205 | 10973 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
10974 | if (thumb_mode) |
10975 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
10976 | else | |
10977 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
10978 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
10979 | } |
10980 | ||
c19d1205 ZW |
10981 | static void |
10982 | do_iwmmxt_wldstw (void) | |
10983 | { | |
10984 | /* RIWR_RIWC clears .isreg for a control register. */ | |
10985 | if (!inst.operands[0].isreg) | |
10986 | { | |
10987 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
10988 | inst.instruction |= 0xf0000000; | |
10989 | } | |
b99bd4ef | 10990 | |
c19d1205 ZW |
10991 | inst.instruction |= inst.operands[0].reg << 12; |
10992 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
10993 | } | |
b99bd4ef NC |
10994 | |
10995 | static void | |
c19d1205 | 10996 | do_iwmmxt_wldstd (void) |
b99bd4ef | 10997 | { |
c19d1205 | 10998 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
10999 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
11000 | && inst.operands[1].immisreg) | |
11001 | { | |
11002 | inst.instruction &= ~0x1a000ff; | |
eff0bc54 | 11003 | inst.instruction |= (0xfU << 28); |
2d447fca JM |
11004 | if (inst.operands[1].preind) |
11005 | inst.instruction |= PRE_INDEX; | |
11006 | if (!inst.operands[1].negative) | |
11007 | inst.instruction |= INDEX_UP; | |
11008 | if (inst.operands[1].writeback) | |
11009 | inst.instruction |= WRITE_BACK; | |
11010 | inst.instruction |= inst.operands[1].reg << 16; | |
e2b0ab59 | 11011 | inst.instruction |= inst.relocs[0].exp.X_add_number << 4; |
2d447fca JM |
11012 | inst.instruction |= inst.operands[1].imm; |
11013 | } | |
11014 | else | |
11015 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 11016 | } |
b99bd4ef | 11017 | |
c19d1205 ZW |
11018 | static void |
11019 | do_iwmmxt_wshufh (void) | |
11020 | { | |
11021 | inst.instruction |= inst.operands[0].reg << 12; | |
11022 | inst.instruction |= inst.operands[1].reg << 16; | |
11023 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
11024 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
11025 | } | |
b99bd4ef | 11026 | |
c19d1205 ZW |
11027 | static void |
11028 | do_iwmmxt_wzero (void) | |
11029 | { | |
11030 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
11031 | inst.instruction |= inst.operands[0].reg; | |
11032 | inst.instruction |= inst.operands[0].reg << 12; | |
11033 | inst.instruction |= inst.operands[0].reg << 16; | |
11034 | } | |
2d447fca JM |
11035 | |
11036 | static void | |
11037 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
11038 | { | |
11039 | if (inst.operands[2].isreg) | |
11040 | do_rd_rn_rm (); | |
11041 | else { | |
11042 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
11043 | _("immediate operand requires iWMMXt2")); | |
11044 | do_rd_rn (); | |
11045 | if (inst.operands[2].imm == 0) | |
11046 | { | |
11047 | switch ((inst.instruction >> 20) & 0xf) | |
11048 | { | |
11049 | case 4: | |
11050 | case 5: | |
11051 | case 6: | |
5f4273c7 | 11052 | case 7: |
2d447fca JM |
11053 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
11054 | inst.operands[2].imm = 16; | |
11055 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
11056 | break; | |
11057 | case 8: | |
11058 | case 9: | |
11059 | case 10: | |
11060 | case 11: | |
11061 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
11062 | inst.operands[2].imm = 32; | |
11063 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
11064 | break; | |
11065 | case 12: | |
11066 | case 13: | |
11067 | case 14: | |
11068 | case 15: | |
11069 | { | |
11070 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
11071 | unsigned long wrn; | |
11072 | wrn = (inst.instruction >> 16) & 0xf; | |
11073 | inst.instruction &= 0xff0fff0f; | |
11074 | inst.instruction |= wrn; | |
11075 | /* Bail out here; the instruction is now assembled. */ | |
11076 | return; | |
11077 | } | |
11078 | } | |
11079 | } | |
11080 | /* Map 32 -> 0, etc. */ | |
11081 | inst.operands[2].imm &= 0x1f; | |
eff0bc54 | 11082 | inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); |
2d447fca JM |
11083 | } |
11084 | } | |
c19d1205 ZW |
11085 | \f |
11086 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
11087 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 11088 | |
c19d1205 | 11089 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 11090 | |
c19d1205 ZW |
11091 | static void |
11092 | do_mav_triple (void) | |
11093 | { | |
11094 | inst.instruction |= inst.operands[0].reg << 16; | |
11095 | inst.instruction |= inst.operands[1].reg; | |
11096 | inst.instruction |= inst.operands[2].reg << 12; | |
11097 | } | |
b99bd4ef | 11098 | |
c19d1205 ZW |
11099 | /* Insns like "foo W,X,Y,Z". |
11100 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 11101 | |
c19d1205 ZW |
11102 | static void |
11103 | do_mav_quad (void) | |
11104 | { | |
11105 | inst.instruction |= inst.operands[0].reg << 5; | |
11106 | inst.instruction |= inst.operands[1].reg << 12; | |
11107 | inst.instruction |= inst.operands[2].reg << 16; | |
11108 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
11109 | } |
11110 | ||
c19d1205 ZW |
11111 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
11112 | static void | |
11113 | do_mav_dspsc (void) | |
a737bd4d | 11114 | { |
c19d1205 ZW |
11115 | inst.instruction |= inst.operands[1].reg << 12; |
11116 | } | |
a737bd4d | 11117 | |
c19d1205 ZW |
11118 | /* Maverick shift immediate instructions. |
11119 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
11120 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 11121 | |
c19d1205 ZW |
11122 | static void |
11123 | do_mav_shift (void) | |
11124 | { | |
11125 | int imm = inst.operands[2].imm; | |
a737bd4d | 11126 | |
c19d1205 ZW |
11127 | inst.instruction |= inst.operands[0].reg << 12; |
11128 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 11129 | |
c19d1205 ZW |
11130 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
11131 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
11132 | Bit 4 should be 0. */ | |
11133 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 11134 | |
c19d1205 ZW |
11135 | inst.instruction |= imm; |
11136 | } | |
11137 | \f | |
11138 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 11139 | |
c19d1205 ZW |
11140 | /* Xscale multiply-accumulate (argument parse) |
11141 | MIAcc acc0,Rm,Rs | |
11142 | MIAPHcc acc0,Rm,Rs | |
11143 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 11144 | |
c19d1205 ZW |
11145 | static void |
11146 | do_xsc_mia (void) | |
11147 | { | |
11148 | inst.instruction |= inst.operands[1].reg; | |
11149 | inst.instruction |= inst.operands[2].reg << 12; | |
11150 | } | |
a737bd4d | 11151 | |
c19d1205 | 11152 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 11153 | |
c19d1205 | 11154 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 11155 | |
c19d1205 ZW |
11156 | static void |
11157 | do_xsc_mar (void) | |
11158 | { | |
11159 | inst.instruction |= inst.operands[1].reg << 12; | |
11160 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11161 | } |
11162 | ||
c19d1205 | 11163 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 11164 | |
c19d1205 | 11165 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
11166 | |
11167 | static void | |
c19d1205 | 11168 | do_xsc_mra (void) |
b99bd4ef | 11169 | { |
c19d1205 ZW |
11170 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
11171 | inst.instruction |= inst.operands[0].reg << 12; | |
11172 | inst.instruction |= inst.operands[1].reg << 16; | |
11173 | } | |
11174 | \f | |
11175 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 11176 | |
c19d1205 ZW |
11177 | /* inst.operands[i] is a shifted-register operand; encode |
11178 | it into inst.instruction in the format used by Thumb32. */ | |
11179 | ||
11180 | static void | |
11181 | encode_thumb32_shifted_operand (int i) | |
11182 | { | |
e2b0ab59 | 11183 | unsigned int value = inst.relocs[0].exp.X_add_number; |
c19d1205 | 11184 | unsigned int shift = inst.operands[i].shift_kind; |
b99bd4ef | 11185 | |
9c3c69f2 PB |
11186 | constraint (inst.operands[i].immisreg, |
11187 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
11188 | inst.instruction |= inst.operands[i].reg; |
11189 | if (shift == SHIFT_RRX) | |
11190 | inst.instruction |= SHIFT_ROR << 4; | |
11191 | else | |
b99bd4ef | 11192 | { |
e2b0ab59 | 11193 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 ZW |
11194 | _("expression too complex")); |
11195 | ||
11196 | constraint (value > 32 | |
11197 | || (value == 32 && (shift == SHIFT_LSL | |
11198 | || shift == SHIFT_ROR)), | |
11199 | _("shift expression is too large")); | |
11200 | ||
11201 | if (value == 0) | |
11202 | shift = SHIFT_LSL; | |
11203 | else if (value == 32) | |
11204 | value = 0; | |
11205 | ||
11206 | inst.instruction |= shift << 4; | |
11207 | inst.instruction |= (value & 0x1c) << 10; | |
11208 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 11209 | } |
c19d1205 | 11210 | } |
b99bd4ef | 11211 | |
b99bd4ef | 11212 | |
c19d1205 ZW |
11213 | /* inst.operands[i] was set up by parse_address. Encode it into a |
11214 | Thumb32 format load or store instruction. Reject forms that cannot | |
11215 | be used with such instructions. If is_t is true, reject forms that | |
11216 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
11217 | that cannot be used with a D instruction. If it is a store insn, |
11218 | reject PC in Rn. */ | |
b99bd4ef | 11219 | |
c19d1205 ZW |
11220 | static void |
11221 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
11222 | { | |
5be8be5d | 11223 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
11224 | |
11225 | constraint (!inst.operands[i].isreg, | |
53365c0d | 11226 | _("Instruction does not support =N addresses")); |
b99bd4ef | 11227 | |
c19d1205 ZW |
11228 | inst.instruction |= inst.operands[i].reg << 16; |
11229 | if (inst.operands[i].immisreg) | |
b99bd4ef | 11230 | { |
5be8be5d | 11231 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
11232 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
11233 | constraint (inst.operands[i].negative, | |
11234 | _("Thumb does not support negative register indexing")); | |
11235 | constraint (inst.operands[i].postind, | |
11236 | _("Thumb does not support register post-indexing")); | |
11237 | constraint (inst.operands[i].writeback, | |
11238 | _("Thumb does not support register indexing with writeback")); | |
11239 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
11240 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 11241 | |
f40d1643 | 11242 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 11243 | if (inst.operands[i].shifted) |
b99bd4ef | 11244 | { |
e2b0ab59 | 11245 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 | 11246 | _("expression too complex")); |
e2b0ab59 AV |
11247 | constraint (inst.relocs[0].exp.X_add_number < 0 |
11248 | || inst.relocs[0].exp.X_add_number > 3, | |
c19d1205 | 11249 | _("shift out of range")); |
e2b0ab59 | 11250 | inst.instruction |= inst.relocs[0].exp.X_add_number << 4; |
c19d1205 | 11251 | } |
e2b0ab59 | 11252 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
c19d1205 ZW |
11253 | } |
11254 | else if (inst.operands[i].preind) | |
11255 | { | |
5be8be5d | 11256 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 11257 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 11258 | _("cannot use writeback with this instruction")); |
4755303e WN |
11259 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
11260 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
11261 | |
11262 | if (is_d) | |
11263 | { | |
11264 | inst.instruction |= 0x01000000; | |
11265 | if (inst.operands[i].writeback) | |
11266 | inst.instruction |= 0x00200000; | |
b99bd4ef | 11267 | } |
c19d1205 | 11268 | else |
b99bd4ef | 11269 | { |
c19d1205 ZW |
11270 | inst.instruction |= 0x00000c00; |
11271 | if (inst.operands[i].writeback) | |
11272 | inst.instruction |= 0x00000100; | |
b99bd4ef | 11273 | } |
e2b0ab59 | 11274 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 11275 | } |
c19d1205 | 11276 | else if (inst.operands[i].postind) |
b99bd4ef | 11277 | { |
9c2799c2 | 11278 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
11279 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
11280 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
11281 | ||
11282 | if (is_d) | |
11283 | inst.instruction |= 0x00200000; | |
11284 | else | |
11285 | inst.instruction |= 0x00000900; | |
e2b0ab59 | 11286 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
c19d1205 ZW |
11287 | } |
11288 | else /* unindexed - only for coprocessor */ | |
11289 | inst.error = _("instruction does not accept unindexed addressing"); | |
11290 | } | |
11291 | ||
e39c1607 | 11292 | /* Table of Thumb instructions which exist in 16- and/or 32-bit |
c19d1205 ZW |
11293 | encodings (the latter only in post-V6T2 cores). The index is the |
11294 | value used in the insns table below. When there is more than one | |
11295 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
11296 | holds variant (1). |
11297 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 11298 | #define T16_32_TAB \ |
21d799b5 NC |
11299 | X(_adc, 4140, eb400000), \ |
11300 | X(_adcs, 4140, eb500000), \ | |
11301 | X(_add, 1c00, eb000000), \ | |
11302 | X(_adds, 1c00, eb100000), \ | |
11303 | X(_addi, 0000, f1000000), \ | |
11304 | X(_addis, 0000, f1100000), \ | |
11305 | X(_add_pc,000f, f20f0000), \ | |
11306 | X(_add_sp,000d, f10d0000), \ | |
11307 | X(_adr, 000f, f20f0000), \ | |
11308 | X(_and, 4000, ea000000), \ | |
11309 | X(_ands, 4000, ea100000), \ | |
11310 | X(_asr, 1000, fa40f000), \ | |
11311 | X(_asrs, 1000, fa50f000), \ | |
11312 | X(_b, e000, f000b000), \ | |
11313 | X(_bcond, d000, f0008000), \ | |
4389b29a | 11314 | X(_bf, 0000, f040e001), \ |
f6b2b12d | 11315 | X(_bfcsel,0000, f000e001), \ |
f1c7f421 | 11316 | X(_bfx, 0000, f060e001), \ |
65d1bc05 | 11317 | X(_bfl, 0000, f000c001), \ |
f1c7f421 | 11318 | X(_bflx, 0000, f070e001), \ |
21d799b5 NC |
11319 | X(_bic, 4380, ea200000), \ |
11320 | X(_bics, 4380, ea300000), \ | |
e39c1607 SD |
11321 | X(_cinc, 0000, ea509000), \ |
11322 | X(_cinv, 0000, ea50a000), \ | |
21d799b5 NC |
11323 | X(_cmn, 42c0, eb100f00), \ |
11324 | X(_cmp, 2800, ebb00f00), \ | |
e39c1607 | 11325 | X(_cneg, 0000, ea50b000), \ |
21d799b5 NC |
11326 | X(_cpsie, b660, f3af8400), \ |
11327 | X(_cpsid, b670, f3af8600), \ | |
11328 | X(_cpy, 4600, ea4f0000), \ | |
e39c1607 SD |
11329 | X(_csel, 0000, ea508000), \ |
11330 | X(_cset, 0000, ea5f900f), \ | |
11331 | X(_csetm, 0000, ea5fa00f), \ | |
11332 | X(_csinc, 0000, ea509000), \ | |
11333 | X(_csinv, 0000, ea50a000), \ | |
11334 | X(_csneg, 0000, ea50b000), \ | |
21d799b5 | 11335 | X(_dec_sp,80dd, f1ad0d00), \ |
60f993ce | 11336 | X(_dls, 0000, f040e001), \ |
1f6234a3 | 11337 | X(_dlstp, 0000, f000e001), \ |
21d799b5 NC |
11338 | X(_eor, 4040, ea800000), \ |
11339 | X(_eors, 4040, ea900000), \ | |
11340 | X(_inc_sp,00dd, f10d0d00), \ | |
1f6234a3 | 11341 | X(_lctp, 0000, f00fe001), \ |
21d799b5 NC |
11342 | X(_ldmia, c800, e8900000), \ |
11343 | X(_ldr, 6800, f8500000), \ | |
11344 | X(_ldrb, 7800, f8100000), \ | |
11345 | X(_ldrh, 8800, f8300000), \ | |
11346 | X(_ldrsb, 5600, f9100000), \ | |
11347 | X(_ldrsh, 5e00, f9300000), \ | |
11348 | X(_ldr_pc,4800, f85f0000), \ | |
11349 | X(_ldr_pc2,4800, f85f0000), \ | |
11350 | X(_ldr_sp,9800, f85d0000), \ | |
60f993ce | 11351 | X(_le, 0000, f00fc001), \ |
1f6234a3 | 11352 | X(_letp, 0000, f01fc001), \ |
21d799b5 NC |
11353 | X(_lsl, 0000, fa00f000), \ |
11354 | X(_lsls, 0000, fa10f000), \ | |
11355 | X(_lsr, 0800, fa20f000), \ | |
11356 | X(_lsrs, 0800, fa30f000), \ | |
11357 | X(_mov, 2000, ea4f0000), \ | |
11358 | X(_movs, 2000, ea5f0000), \ | |
11359 | X(_mul, 4340, fb00f000), \ | |
11360 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
11361 | X(_mvn, 43c0, ea6f0000), \ | |
11362 | X(_mvns, 43c0, ea7f0000), \ | |
11363 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
11364 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
11365 | X(_orr, 4300, ea400000), \ | |
11366 | X(_orrs, 4300, ea500000), \ | |
11367 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
11368 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
11369 | X(_rev, ba00, fa90f080), \ | |
11370 | X(_rev16, ba40, fa90f090), \ | |
11371 | X(_revsh, bac0, fa90f0b0), \ | |
11372 | X(_ror, 41c0, fa60f000), \ | |
11373 | X(_rors, 41c0, fa70f000), \ | |
11374 | X(_sbc, 4180, eb600000), \ | |
11375 | X(_sbcs, 4180, eb700000), \ | |
11376 | X(_stmia, c000, e8800000), \ | |
11377 | X(_str, 6000, f8400000), \ | |
11378 | X(_strb, 7000, f8000000), \ | |
11379 | X(_strh, 8000, f8200000), \ | |
11380 | X(_str_sp,9000, f84d0000), \ | |
11381 | X(_sub, 1e00, eba00000), \ | |
11382 | X(_subs, 1e00, ebb00000), \ | |
11383 | X(_subi, 8000, f1a00000), \ | |
11384 | X(_subis, 8000, f1b00000), \ | |
11385 | X(_sxtb, b240, fa4ff080), \ | |
11386 | X(_sxth, b200, fa0ff080), \ | |
11387 | X(_tst, 4200, ea100f00), \ | |
11388 | X(_uxtb, b2c0, fa5ff080), \ | |
11389 | X(_uxth, b280, fa1ff080), \ | |
11390 | X(_nop, bf00, f3af8000), \ | |
11391 | X(_yield, bf10, f3af8001), \ | |
11392 | X(_wfe, bf20, f3af8002), \ | |
11393 | X(_wfi, bf30, f3af8003), \ | |
60f993ce | 11394 | X(_wls, 0000, f040c001), \ |
1f6234a3 | 11395 | X(_wlstp, 0000, f000c001), \ |
53c4b28b | 11396 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
11397 | X(_sevl, bf50, f3af8005), \ |
11398 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
11399 | |
11400 | /* To catch errors in encoding functions, the codes are all offset by | |
11401 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
11402 | as 16-bit instructions. */ | |
21d799b5 | 11403 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
11404 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
11405 | #undef X | |
11406 | ||
11407 | #define X(a,b,c) 0x##b | |
11408 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
11409 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
11410 | #undef X | |
11411 | ||
11412 | #define X(a,b,c) 0x##c | |
11413 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
11414 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
11415 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
11416 | #undef X |
11417 | #undef T16_32_TAB | |
11418 | ||
11419 | /* Thumb instruction encoders, in alphabetical order. */ | |
11420 | ||
92e90b6e | 11421 | /* ADDW or SUBW. */ |
c921be7d | 11422 | |
92e90b6e PB |
11423 | static void |
11424 | do_t_add_sub_w (void) | |
11425 | { | |
11426 | int Rd, Rn; | |
11427 | ||
11428 | Rd = inst.operands[0].reg; | |
11429 | Rn = inst.operands[1].reg; | |
11430 | ||
539d4391 NC |
11431 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
11432 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
11433 | if (Rn == REG_SP) | |
11434 | constraint (Rd == REG_PC, BAD_PC); | |
11435 | else | |
11436 | reject_bad_reg (Rd); | |
fdfde340 | 11437 | |
92e90b6e | 11438 | inst.instruction |= (Rn << 16) | (Rd << 8); |
e2b0ab59 | 11439 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12; |
92e90b6e PB |
11440 | } |
11441 | ||
c19d1205 | 11442 | /* Parse an add or subtract instruction. We get here with inst.instruction |
33eaf5de | 11443 | equaling any of THUMB_OPCODE_add, adds, sub, or subs. */ |
c19d1205 ZW |
11444 | |
11445 | static void | |
11446 | do_t_add_sub (void) | |
11447 | { | |
11448 | int Rd, Rs, Rn; | |
11449 | ||
11450 | Rd = inst.operands[0].reg; | |
11451 | Rs = (inst.operands[1].present | |
11452 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11453 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
11454 | ||
e07e6e58 | 11455 | if (Rd == REG_PC) |
5ee91343 | 11456 | set_pred_insn_type_last (); |
e07e6e58 | 11457 | |
c19d1205 ZW |
11458 | if (unified_syntax) |
11459 | { | |
0110f2b8 PB |
11460 | bfd_boolean flags; |
11461 | bfd_boolean narrow; | |
11462 | int opcode; | |
11463 | ||
11464 | flags = (inst.instruction == T_MNEM_adds | |
11465 | || inst.instruction == T_MNEM_subs); | |
11466 | if (flags) | |
5ee91343 | 11467 | narrow = !in_pred_block (); |
0110f2b8 | 11468 | else |
5ee91343 | 11469 | narrow = in_pred_block (); |
c19d1205 | 11470 | if (!inst.operands[2].isreg) |
b99bd4ef | 11471 | { |
16805f35 PB |
11472 | int add; |
11473 | ||
5c8ed6a4 JW |
11474 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
11475 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
fdfde340 | 11476 | |
16805f35 PB |
11477 | add = (inst.instruction == T_MNEM_add |
11478 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
11479 | opcode = 0; |
11480 | if (inst.size_req != 4) | |
11481 | { | |
0110f2b8 | 11482 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 11483 | appropriate. */ |
0110f2b8 PB |
11484 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
11485 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
11486 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
11487 | opcode = T_MNEM_add_sp; | |
11488 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
11489 | opcode = T_MNEM_add_pc; | |
11490 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
11491 | { | |
11492 | if (flags) | |
11493 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
11494 | else | |
11495 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
11496 | } | |
11497 | if (opcode) | |
11498 | { | |
11499 | inst.instruction = THUMB_OP16(opcode); | |
11500 | inst.instruction |= (Rd << 4) | Rs; | |
e2b0ab59 AV |
11501 | if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
11502 | || (inst.relocs[0].type | |
11503 | > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)) | |
a9f02af8 MG |
11504 | { |
11505 | if (inst.size_req == 2) | |
e2b0ab59 | 11506 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
a9f02af8 MG |
11507 | else |
11508 | inst.relax = opcode; | |
11509 | } | |
0110f2b8 PB |
11510 | } |
11511 | else | |
11512 | constraint (inst.size_req == 2, BAD_HIREG); | |
11513 | } | |
11514 | if (inst.size_req == 4 | |
11515 | || (inst.size_req != 2 && !opcode)) | |
11516 | { | |
e2b0ab59 AV |
11517 | constraint ((inst.relocs[0].type |
11518 | >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC) | |
11519 | && (inst.relocs[0].type | |
11520 | <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) , | |
a9f02af8 | 11521 | THUMB1_RELOC_ONLY); |
efd81785 PB |
11522 | if (Rd == REG_PC) |
11523 | { | |
fdfde340 | 11524 | constraint (add, BAD_PC); |
efd81785 PB |
11525 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
11526 | _("only SUBS PC, LR, #const allowed")); | |
e2b0ab59 | 11527 | constraint (inst.relocs[0].exp.X_op != O_constant, |
efd81785 | 11528 | _("expression too complex")); |
e2b0ab59 AV |
11529 | constraint (inst.relocs[0].exp.X_add_number < 0 |
11530 | || inst.relocs[0].exp.X_add_number > 0xff, | |
efd81785 PB |
11531 | _("immediate value out of range")); |
11532 | inst.instruction = T2_SUBS_PC_LR | |
e2b0ab59 AV |
11533 | | inst.relocs[0].exp.X_add_number; |
11534 | inst.relocs[0].type = BFD_RELOC_UNUSED; | |
efd81785 PB |
11535 | return; |
11536 | } | |
11537 | else if (Rs == REG_PC) | |
16805f35 PB |
11538 | { |
11539 | /* Always use addw/subw. */ | |
11540 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
e2b0ab59 | 11541 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12; |
16805f35 PB |
11542 | } |
11543 | else | |
11544 | { | |
11545 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11546 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
11547 | | 0x10000000; | |
11548 | if (flags) | |
e2b0ab59 | 11549 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
16805f35 | 11550 | else |
e2b0ab59 | 11551 | inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM; |
16805f35 | 11552 | } |
dc4503c6 PB |
11553 | inst.instruction |= Rd << 8; |
11554 | inst.instruction |= Rs << 16; | |
0110f2b8 | 11555 | } |
b99bd4ef | 11556 | } |
c19d1205 ZW |
11557 | else |
11558 | { | |
e2b0ab59 | 11559 | unsigned int value = inst.relocs[0].exp.X_add_number; |
5f4cb198 NC |
11560 | unsigned int shift = inst.operands[2].shift_kind; |
11561 | ||
c19d1205 ZW |
11562 | Rn = inst.operands[2].reg; |
11563 | /* See if we can do this with a 16-bit instruction. */ | |
11564 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
11565 | { | |
e27ec89e PB |
11566 | if (Rd > 7 || Rs > 7 || Rn > 7) |
11567 | narrow = FALSE; | |
11568 | ||
11569 | if (narrow) | |
c19d1205 | 11570 | { |
e27ec89e PB |
11571 | inst.instruction = ((inst.instruction == T_MNEM_adds |
11572 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
11573 | ? T_OPCODE_ADD_R3 |
11574 | : T_OPCODE_SUB_R3); | |
11575 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
11576 | return; | |
11577 | } | |
b99bd4ef | 11578 | |
7e806470 | 11579 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 11580 | { |
7e806470 PB |
11581 | /* Thumb-1 cores (except v6-M) require at least one high |
11582 | register in a narrow non flag setting add. */ | |
11583 | if (Rd > 7 || Rn > 7 | |
11584 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
11585 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 11586 | { |
7e806470 PB |
11587 | if (Rd == Rn) |
11588 | { | |
11589 | Rn = Rs; | |
11590 | Rs = Rd; | |
11591 | } | |
c19d1205 ZW |
11592 | inst.instruction = T_OPCODE_ADD_HI; |
11593 | inst.instruction |= (Rd & 8) << 4; | |
11594 | inst.instruction |= (Rd & 7); | |
11595 | inst.instruction |= Rn << 3; | |
11596 | return; | |
11597 | } | |
c19d1205 ZW |
11598 | } |
11599 | } | |
c921be7d | 11600 | |
fdfde340 | 11601 | constraint (Rd == REG_PC, BAD_PC); |
5c8ed6a4 JW |
11602 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
11603 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
fdfde340 JM |
11604 | constraint (Rs == REG_PC, BAD_PC); |
11605 | reject_bad_reg (Rn); | |
11606 | ||
c19d1205 ZW |
11607 | /* If we get here, it can't be done in 16 bits. */ |
11608 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
11609 | _("shift must be constant")); | |
11610 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11611 | inst.instruction |= Rd << 8; | |
11612 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
11613 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
11614 | _("shift value over 3 not allowed in thumb mode")); | |
11615 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
11616 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
11617 | encode_thumb32_shifted_operand (2); |
11618 | } | |
11619 | } | |
11620 | else | |
11621 | { | |
11622 | constraint (inst.instruction == T_MNEM_adds | |
11623 | || inst.instruction == T_MNEM_subs, | |
11624 | BAD_THUMB32); | |
b99bd4ef | 11625 | |
c19d1205 | 11626 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 11627 | { |
c19d1205 ZW |
11628 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
11629 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
11630 | BAD_HIREG); | |
11631 | ||
11632 | inst.instruction = (inst.instruction == T_MNEM_add | |
11633 | ? 0x0000 : 0x8000); | |
11634 | inst.instruction |= (Rd << 4) | Rs; | |
e2b0ab59 | 11635 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
b99bd4ef NC |
11636 | return; |
11637 | } | |
11638 | ||
c19d1205 ZW |
11639 | Rn = inst.operands[2].reg; |
11640 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 11641 | |
c19d1205 ZW |
11642 | /* We now have Rd, Rs, and Rn set to registers. */ |
11643 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 11644 | { |
c19d1205 ZW |
11645 | /* Can't do this for SUB. */ |
11646 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
11647 | inst.instruction = T_OPCODE_ADD_HI; | |
11648 | inst.instruction |= (Rd & 8) << 4; | |
11649 | inst.instruction |= (Rd & 7); | |
11650 | if (Rs == Rd) | |
11651 | inst.instruction |= Rn << 3; | |
11652 | else if (Rn == Rd) | |
11653 | inst.instruction |= Rs << 3; | |
11654 | else | |
11655 | constraint (1, _("dest must overlap one source register")); | |
11656 | } | |
11657 | else | |
11658 | { | |
11659 | inst.instruction = (inst.instruction == T_MNEM_add | |
11660 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
11661 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 11662 | } |
b99bd4ef | 11663 | } |
b99bd4ef NC |
11664 | } |
11665 | ||
c19d1205 ZW |
11666 | static void |
11667 | do_t_adr (void) | |
11668 | { | |
fdfde340 JM |
11669 | unsigned Rd; |
11670 | ||
11671 | Rd = inst.operands[0].reg; | |
11672 | reject_bad_reg (Rd); | |
11673 | ||
11674 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
11675 | { |
11676 | /* Defer to section relaxation. */ | |
11677 | inst.relax = inst.instruction; | |
11678 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 11679 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
11680 | } |
11681 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 11682 | { |
0110f2b8 | 11683 | /* Generate a 32-bit opcode. */ |
e9f89963 | 11684 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 11685 | inst.instruction |= Rd << 8; |
e2b0ab59 AV |
11686 | inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12; |
11687 | inst.relocs[0].pc_rel = 1; | |
e9f89963 PB |
11688 | } |
11689 | else | |
11690 | { | |
0110f2b8 | 11691 | /* Generate a 16-bit opcode. */ |
e9f89963 | 11692 | inst.instruction = THUMB_OP16 (inst.instruction); |
e2b0ab59 AV |
11693 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD; |
11694 | inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */ | |
11695 | inst.relocs[0].pc_rel = 1; | |
fdfde340 | 11696 | inst.instruction |= Rd << 4; |
e9f89963 | 11697 | } |
52a86f84 | 11698 | |
e2b0ab59 AV |
11699 | if (inst.relocs[0].exp.X_op == O_symbol |
11700 | && inst.relocs[0].exp.X_add_symbol != NULL | |
11701 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
11702 | && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
11703 | inst.relocs[0].exp.X_add_number += 1; | |
c19d1205 | 11704 | } |
b99bd4ef | 11705 | |
c19d1205 ZW |
11706 | /* Arithmetic instructions for which there is just one 16-bit |
11707 | instruction encoding, and it allows only two low registers. | |
11708 | For maximal compatibility with ARM syntax, we allow three register | |
11709 | operands even when Thumb-32 instructions are not available, as long | |
11710 | as the first two are identical. For instance, both "sbc r0,r1" and | |
11711 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 11712 | static void |
c19d1205 | 11713 | do_t_arit3 (void) |
b99bd4ef | 11714 | { |
c19d1205 | 11715 | int Rd, Rs, Rn; |
b99bd4ef | 11716 | |
c19d1205 ZW |
11717 | Rd = inst.operands[0].reg; |
11718 | Rs = (inst.operands[1].present | |
11719 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11720 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
11721 | Rn = inst.operands[2].reg; | |
b99bd4ef | 11722 | |
fdfde340 JM |
11723 | reject_bad_reg (Rd); |
11724 | reject_bad_reg (Rs); | |
11725 | if (inst.operands[2].isreg) | |
11726 | reject_bad_reg (Rn); | |
11727 | ||
c19d1205 | 11728 | if (unified_syntax) |
b99bd4ef | 11729 | { |
c19d1205 ZW |
11730 | if (!inst.operands[2].isreg) |
11731 | { | |
11732 | /* For an immediate, we always generate a 32-bit opcode; | |
11733 | section relaxation will shrink it later if possible. */ | |
11734 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11735 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11736 | inst.instruction |= Rd << 8; | |
11737 | inst.instruction |= Rs << 16; | |
e2b0ab59 | 11738 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
c19d1205 ZW |
11739 | } |
11740 | else | |
11741 | { | |
e27ec89e PB |
11742 | bfd_boolean narrow; |
11743 | ||
c19d1205 | 11744 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 11745 | if (THUMB_SETS_FLAGS (inst.instruction)) |
5ee91343 | 11746 | narrow = !in_pred_block (); |
e27ec89e | 11747 | else |
5ee91343 | 11748 | narrow = in_pred_block (); |
e27ec89e PB |
11749 | |
11750 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
11751 | narrow = FALSE; | |
11752 | if (inst.operands[2].shifted) | |
11753 | narrow = FALSE; | |
11754 | if (inst.size_req == 4) | |
11755 | narrow = FALSE; | |
11756 | ||
11757 | if (narrow | |
c19d1205 ZW |
11758 | && Rd == Rs) |
11759 | { | |
11760 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11761 | inst.instruction |= Rd; | |
11762 | inst.instruction |= Rn << 3; | |
11763 | return; | |
11764 | } | |
b99bd4ef | 11765 | |
c19d1205 ZW |
11766 | /* If we get here, it can't be done in 16 bits. */ |
11767 | constraint (inst.operands[2].shifted | |
11768 | && inst.operands[2].immisreg, | |
11769 | _("shift must be constant")); | |
11770 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11771 | inst.instruction |= Rd << 8; | |
11772 | inst.instruction |= Rs << 16; | |
11773 | encode_thumb32_shifted_operand (2); | |
11774 | } | |
a737bd4d | 11775 | } |
c19d1205 | 11776 | else |
b99bd4ef | 11777 | { |
c19d1205 ZW |
11778 | /* On its face this is a lie - the instruction does set the |
11779 | flags. However, the only supported mnemonic in this mode | |
11780 | says it doesn't. */ | |
11781 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 11782 | |
c19d1205 ZW |
11783 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
11784 | _("unshifted register required")); | |
11785 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
11786 | constraint (Rd != Rs, | |
11787 | _("dest and source1 must be the same register")); | |
a737bd4d | 11788 | |
c19d1205 ZW |
11789 | inst.instruction = THUMB_OP16 (inst.instruction); |
11790 | inst.instruction |= Rd; | |
11791 | inst.instruction |= Rn << 3; | |
b99bd4ef | 11792 | } |
a737bd4d | 11793 | } |
b99bd4ef | 11794 | |
c19d1205 ZW |
11795 | /* Similarly, but for instructions where the arithmetic operation is |
11796 | commutative, so we can allow either of them to be different from | |
11797 | the destination operand in a 16-bit instruction. For instance, all | |
11798 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
11799 | accepted. */ | |
11800 | static void | |
11801 | do_t_arit3c (void) | |
a737bd4d | 11802 | { |
c19d1205 | 11803 | int Rd, Rs, Rn; |
b99bd4ef | 11804 | |
c19d1205 ZW |
11805 | Rd = inst.operands[0].reg; |
11806 | Rs = (inst.operands[1].present | |
11807 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11808 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
11809 | Rn = inst.operands[2].reg; | |
c921be7d | 11810 | |
fdfde340 JM |
11811 | reject_bad_reg (Rd); |
11812 | reject_bad_reg (Rs); | |
11813 | if (inst.operands[2].isreg) | |
11814 | reject_bad_reg (Rn); | |
a737bd4d | 11815 | |
c19d1205 | 11816 | if (unified_syntax) |
a737bd4d | 11817 | { |
c19d1205 | 11818 | if (!inst.operands[2].isreg) |
b99bd4ef | 11819 | { |
c19d1205 ZW |
11820 | /* For an immediate, we always generate a 32-bit opcode; |
11821 | section relaxation will shrink it later if possible. */ | |
11822 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11823 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11824 | inst.instruction |= Rd << 8; | |
11825 | inst.instruction |= Rs << 16; | |
e2b0ab59 | 11826 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11827 | } |
c19d1205 | 11828 | else |
a737bd4d | 11829 | { |
e27ec89e PB |
11830 | bfd_boolean narrow; |
11831 | ||
c19d1205 | 11832 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 11833 | if (THUMB_SETS_FLAGS (inst.instruction)) |
5ee91343 | 11834 | narrow = !in_pred_block (); |
e27ec89e | 11835 | else |
5ee91343 | 11836 | narrow = in_pred_block (); |
e27ec89e PB |
11837 | |
11838 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
11839 | narrow = FALSE; | |
11840 | if (inst.operands[2].shifted) | |
11841 | narrow = FALSE; | |
11842 | if (inst.size_req == 4) | |
11843 | narrow = FALSE; | |
11844 | ||
11845 | if (narrow) | |
a737bd4d | 11846 | { |
c19d1205 | 11847 | if (Rd == Rs) |
a737bd4d | 11848 | { |
c19d1205 ZW |
11849 | inst.instruction = THUMB_OP16 (inst.instruction); |
11850 | inst.instruction |= Rd; | |
11851 | inst.instruction |= Rn << 3; | |
11852 | return; | |
a737bd4d | 11853 | } |
c19d1205 | 11854 | if (Rd == Rn) |
a737bd4d | 11855 | { |
c19d1205 ZW |
11856 | inst.instruction = THUMB_OP16 (inst.instruction); |
11857 | inst.instruction |= Rd; | |
11858 | inst.instruction |= Rs << 3; | |
11859 | return; | |
a737bd4d NC |
11860 | } |
11861 | } | |
c19d1205 ZW |
11862 | |
11863 | /* If we get here, it can't be done in 16 bits. */ | |
11864 | constraint (inst.operands[2].shifted | |
11865 | && inst.operands[2].immisreg, | |
11866 | _("shift must be constant")); | |
11867 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11868 | inst.instruction |= Rd << 8; | |
11869 | inst.instruction |= Rs << 16; | |
11870 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 11871 | } |
b99bd4ef | 11872 | } |
c19d1205 ZW |
11873 | else |
11874 | { | |
11875 | /* On its face this is a lie - the instruction does set the | |
11876 | flags. However, the only supported mnemonic in this mode | |
11877 | says it doesn't. */ | |
11878 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 11879 | |
c19d1205 ZW |
11880 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
11881 | _("unshifted register required")); | |
11882 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
11883 | ||
11884 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11885 | inst.instruction |= Rd; | |
11886 | ||
11887 | if (Rd == Rs) | |
11888 | inst.instruction |= Rn << 3; | |
11889 | else if (Rd == Rn) | |
11890 | inst.instruction |= Rs << 3; | |
11891 | else | |
11892 | constraint (1, _("dest must overlap one source register")); | |
11893 | } | |
a737bd4d NC |
11894 | } |
11895 | ||
c19d1205 ZW |
11896 | static void |
11897 | do_t_bfc (void) | |
a737bd4d | 11898 | { |
fdfde340 | 11899 | unsigned Rd; |
c19d1205 ZW |
11900 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
11901 | constraint (msb > 32, _("bit-field extends past end of register")); | |
11902 | /* The instruction encoding stores the LSB and MSB, | |
11903 | not the LSB and width. */ | |
fdfde340 JM |
11904 | Rd = inst.operands[0].reg; |
11905 | reject_bad_reg (Rd); | |
11906 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
11907 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
11908 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
11909 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
11910 | } |
11911 | ||
c19d1205 ZW |
11912 | static void |
11913 | do_t_bfi (void) | |
b99bd4ef | 11914 | { |
fdfde340 | 11915 | int Rd, Rn; |
c19d1205 | 11916 | unsigned int msb; |
b99bd4ef | 11917 | |
fdfde340 JM |
11918 | Rd = inst.operands[0].reg; |
11919 | reject_bad_reg (Rd); | |
11920 | ||
c19d1205 ZW |
11921 | /* #0 in second position is alternative syntax for bfc, which is |
11922 | the same instruction but with REG_PC in the Rm field. */ | |
11923 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
11924 | Rn = REG_PC; |
11925 | else | |
11926 | { | |
11927 | Rn = inst.operands[1].reg; | |
11928 | reject_bad_reg (Rn); | |
11929 | } | |
b99bd4ef | 11930 | |
c19d1205 ZW |
11931 | msb = inst.operands[2].imm + inst.operands[3].imm; |
11932 | constraint (msb > 32, _("bit-field extends past end of register")); | |
11933 | /* The instruction encoding stores the LSB and MSB, | |
11934 | not the LSB and width. */ | |
fdfde340 JM |
11935 | inst.instruction |= Rd << 8; |
11936 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
11937 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
11938 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
11939 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
11940 | } |
11941 | ||
c19d1205 ZW |
11942 | static void |
11943 | do_t_bfx (void) | |
b99bd4ef | 11944 | { |
fdfde340 JM |
11945 | unsigned Rd, Rn; |
11946 | ||
11947 | Rd = inst.operands[0].reg; | |
11948 | Rn = inst.operands[1].reg; | |
11949 | ||
11950 | reject_bad_reg (Rd); | |
11951 | reject_bad_reg (Rn); | |
11952 | ||
c19d1205 ZW |
11953 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
11954 | _("bit-field extends past end of register")); | |
fdfde340 JM |
11955 | inst.instruction |= Rd << 8; |
11956 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
11957 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
11958 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
11959 | inst.instruction |= inst.operands[3].imm - 1; | |
11960 | } | |
b99bd4ef | 11961 | |
c19d1205 ZW |
11962 | /* ARM V5 Thumb BLX (argument parse) |
11963 | BLX <target_addr> which is BLX(1) | |
11964 | BLX <Rm> which is BLX(2) | |
11965 | Unfortunately, there are two different opcodes for this mnemonic. | |
11966 | So, the insns[].value is not used, and the code here zaps values | |
11967 | into inst.instruction. | |
b99bd4ef | 11968 | |
c19d1205 ZW |
11969 | ??? How to take advantage of the additional two bits of displacement |
11970 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 11971 | |
c19d1205 ZW |
11972 | static void |
11973 | do_t_blx (void) | |
11974 | { | |
5ee91343 | 11975 | set_pred_insn_type_last (); |
e07e6e58 | 11976 | |
c19d1205 | 11977 | if (inst.operands[0].isreg) |
fdfde340 JM |
11978 | { |
11979 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
11980 | /* We have a register, so this is BLX(2). */ | |
11981 | inst.instruction |= inst.operands[0].reg << 3; | |
11982 | } | |
b99bd4ef NC |
11983 | else |
11984 | { | |
c19d1205 | 11985 | /* No register. This must be BLX(1). */ |
2fc8bdac | 11986 | inst.instruction = 0xf000e800; |
0855e32b | 11987 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
11988 | } |
11989 | } | |
11990 | ||
c19d1205 ZW |
11991 | static void |
11992 | do_t_branch (void) | |
b99bd4ef | 11993 | { |
0110f2b8 | 11994 | int opcode; |
dfa9f0d5 | 11995 | int cond; |
2fe88214 | 11996 | bfd_reloc_code_real_type reloc; |
dfa9f0d5 | 11997 | |
e07e6e58 | 11998 | cond = inst.cond; |
5ee91343 | 11999 | set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); |
e07e6e58 | 12000 | |
5ee91343 | 12001 | if (in_pred_block ()) |
dfa9f0d5 PB |
12002 | { |
12003 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 12004 | branches. */ |
dfa9f0d5 | 12005 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
12006 | } |
12007 | else | |
12008 | cond = inst.cond; | |
12009 | ||
12010 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
12011 | opcode = T_MNEM_bcond; |
12012 | else | |
12013 | opcode = inst.instruction; | |
12014 | ||
12d6b0b7 RS |
12015 | if (unified_syntax |
12016 | && (inst.size_req == 4 | |
10960bfb PB |
12017 | || (inst.size_req != 2 |
12018 | && (inst.operands[0].hasreloc | |
e2b0ab59 | 12019 | || inst.relocs[0].exp.X_op == O_constant)))) |
c19d1205 | 12020 | { |
0110f2b8 | 12021 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 12022 | if (cond == COND_ALWAYS) |
9ae92b05 | 12023 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
12024 | else |
12025 | { | |
ff8646ee TP |
12026 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2), |
12027 | _("selected architecture does not support " | |
12028 | "wide conditional branch instruction")); | |
12029 | ||
9c2799c2 | 12030 | gas_assert (cond != 0xF); |
dfa9f0d5 | 12031 | inst.instruction |= cond << 22; |
9ae92b05 | 12032 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
12033 | } |
12034 | } | |
b99bd4ef NC |
12035 | else |
12036 | { | |
0110f2b8 | 12037 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 12038 | if (cond == COND_ALWAYS) |
9ae92b05 | 12039 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 12040 | else |
b99bd4ef | 12041 | { |
dfa9f0d5 | 12042 | inst.instruction |= cond << 8; |
9ae92b05 | 12043 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 12044 | } |
0110f2b8 PB |
12045 | /* Allow section relaxation. */ |
12046 | if (unified_syntax && inst.size_req != 2) | |
12047 | inst.relax = opcode; | |
b99bd4ef | 12048 | } |
e2b0ab59 AV |
12049 | inst.relocs[0].type = reloc; |
12050 | inst.relocs[0].pc_rel = 1; | |
b99bd4ef NC |
12051 | } |
12052 | ||
8884b720 | 12053 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 12054 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 12055 | RANGE. */ |
b99bd4ef | 12056 | static void |
8884b720 | 12057 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 12058 | { |
dfa9f0d5 PB |
12059 | constraint (inst.cond != COND_ALWAYS, |
12060 | _("instruction is always unconditional")); | |
c19d1205 | 12061 | if (inst.operands[0].present) |
b99bd4ef | 12062 | { |
8884b720 | 12063 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
12064 | _("immediate value out of range")); |
12065 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 12066 | } |
8884b720 | 12067 | |
5ee91343 | 12068 | set_pred_insn_type (NEUTRAL_IT_INSN); |
8884b720 MGD |
12069 | } |
12070 | ||
12071 | static void | |
12072 | do_t_hlt (void) | |
12073 | { | |
12074 | do_t_bkpt_hlt1 (63); | |
12075 | } | |
12076 | ||
12077 | static void | |
12078 | do_t_bkpt (void) | |
12079 | { | |
12080 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
12081 | } |
12082 | ||
12083 | static void | |
c19d1205 | 12084 | do_t_branch23 (void) |
b99bd4ef | 12085 | { |
5ee91343 | 12086 | set_pred_insn_type_last (); |
0855e32b | 12087 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 12088 | |
0855e32b NS |
12089 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
12090 | this file. We used to simply ignore the PLT reloc type here -- | |
12091 | the branch encoding is now needed to deal with TLSCALL relocs. | |
12092 | So if we see a PLT reloc now, put it back to how it used to be to | |
12093 | keep the preexisting behaviour. */ | |
e2b0ab59 AV |
12094 | if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32) |
12095 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 12096 | |
4343666d | 12097 | #if defined(OBJ_COFF) |
c19d1205 ZW |
12098 | /* If the destination of the branch is a defined symbol which does not have |
12099 | the THUMB_FUNC attribute, then we must be calling a function which has | |
12100 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
12101 | function and change the branch to refer to that function instead. */ | |
e2b0ab59 AV |
12102 | if ( inst.relocs[0].exp.X_op == O_symbol |
12103 | && inst.relocs[0].exp.X_add_symbol != NULL | |
12104 | && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol) | |
12105 | && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol)) | |
12106 | inst.relocs[0].exp.X_add_symbol | |
12107 | = find_real_start (inst.relocs[0].exp.X_add_symbol); | |
4343666d | 12108 | #endif |
90e4755a RE |
12109 | } |
12110 | ||
12111 | static void | |
c19d1205 | 12112 | do_t_bx (void) |
90e4755a | 12113 | { |
5ee91343 | 12114 | set_pred_insn_type_last (); |
c19d1205 ZW |
12115 | inst.instruction |= inst.operands[0].reg << 3; |
12116 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
12117 | should cause the alignment to be checked once it is known. This is | |
12118 | because BX PC only works if the instruction is word aligned. */ | |
12119 | } | |
90e4755a | 12120 | |
c19d1205 ZW |
12121 | static void |
12122 | do_t_bxj (void) | |
12123 | { | |
fdfde340 | 12124 | int Rm; |
90e4755a | 12125 | |
5ee91343 | 12126 | set_pred_insn_type_last (); |
fdfde340 JM |
12127 | Rm = inst.operands[0].reg; |
12128 | reject_bad_reg (Rm); | |
12129 | inst.instruction |= Rm << 16; | |
90e4755a RE |
12130 | } |
12131 | ||
12132 | static void | |
c19d1205 | 12133 | do_t_clz (void) |
90e4755a | 12134 | { |
fdfde340 JM |
12135 | unsigned Rd; |
12136 | unsigned Rm; | |
12137 | ||
12138 | Rd = inst.operands[0].reg; | |
12139 | Rm = inst.operands[1].reg; | |
12140 | ||
12141 | reject_bad_reg (Rd); | |
12142 | reject_bad_reg (Rm); | |
12143 | ||
12144 | inst.instruction |= Rd << 8; | |
12145 | inst.instruction |= Rm << 16; | |
12146 | inst.instruction |= Rm; | |
c19d1205 | 12147 | } |
90e4755a | 12148 | |
e39c1607 SD |
12149 | /* For the Armv8.1-M conditional instructions. */ |
12150 | static void | |
12151 | do_t_cond (void) | |
12152 | { | |
12153 | unsigned Rd, Rn, Rm; | |
12154 | signed int cond; | |
12155 | ||
12156 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
12157 | ||
12158 | Rd = inst.operands[0].reg; | |
12159 | switch (inst.instruction) | |
12160 | { | |
12161 | case T_MNEM_csinc: | |
12162 | case T_MNEM_csinv: | |
12163 | case T_MNEM_csneg: | |
12164 | case T_MNEM_csel: | |
12165 | Rn = inst.operands[1].reg; | |
12166 | Rm = inst.operands[2].reg; | |
12167 | cond = inst.operands[3].imm; | |
12168 | constraint (Rn == REG_SP, BAD_SP); | |
12169 | constraint (Rm == REG_SP, BAD_SP); | |
12170 | break; | |
12171 | ||
12172 | case T_MNEM_cinc: | |
12173 | case T_MNEM_cinv: | |
12174 | case T_MNEM_cneg: | |
12175 | Rn = inst.operands[1].reg; | |
12176 | cond = inst.operands[2].imm; | |
12177 | /* Invert the last bit to invert the cond. */ | |
12178 | cond = TOGGLE_BIT (cond, 0); | |
12179 | constraint (Rn == REG_SP, BAD_SP); | |
12180 | Rm = Rn; | |
12181 | break; | |
12182 | ||
12183 | case T_MNEM_csetm: | |
12184 | case T_MNEM_cset: | |
12185 | cond = inst.operands[1].imm; | |
12186 | /* Invert the last bit to invert the cond. */ | |
12187 | cond = TOGGLE_BIT (cond, 0); | |
12188 | Rn = REG_PC; | |
12189 | Rm = REG_PC; | |
12190 | break; | |
12191 | ||
12192 | default: abort (); | |
12193 | } | |
12194 | ||
12195 | set_pred_insn_type (OUTSIDE_PRED_INSN); | |
12196 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12197 | inst.instruction |= Rd << 8; | |
12198 | inst.instruction |= Rn << 16; | |
12199 | inst.instruction |= Rm; | |
12200 | inst.instruction |= cond << 4; | |
12201 | } | |
12202 | ||
91d8b670 JG |
12203 | static void |
12204 | do_t_csdb (void) | |
12205 | { | |
5ee91343 | 12206 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
91d8b670 JG |
12207 | } |
12208 | ||
dfa9f0d5 PB |
12209 | static void |
12210 | do_t_cps (void) | |
12211 | { | |
5ee91343 | 12212 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
dfa9f0d5 PB |
12213 | inst.instruction |= inst.operands[0].imm; |
12214 | } | |
12215 | ||
c19d1205 ZW |
12216 | static void |
12217 | do_t_cpsi (void) | |
12218 | { | |
5ee91343 | 12219 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
c19d1205 | 12220 | if (unified_syntax |
62b3e311 PB |
12221 | && (inst.operands[1].present || inst.size_req == 4) |
12222 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 12223 | { |
c19d1205 ZW |
12224 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
12225 | inst.instruction = 0xf3af8000; | |
12226 | inst.instruction |= imod << 9; | |
12227 | inst.instruction |= inst.operands[0].imm << 5; | |
12228 | if (inst.operands[1].present) | |
12229 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 12230 | } |
c19d1205 | 12231 | else |
90e4755a | 12232 | { |
62b3e311 PB |
12233 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
12234 | && (inst.operands[0].imm & 4), | |
12235 | _("selected processor does not support 'A' form " | |
12236 | "of this instruction")); | |
12237 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
12238 | _("Thumb does not support the 2-argument " |
12239 | "form of this instruction")); | |
12240 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 12241 | } |
90e4755a RE |
12242 | } |
12243 | ||
c19d1205 ZW |
12244 | /* THUMB CPY instruction (argument parse). */ |
12245 | ||
90e4755a | 12246 | static void |
c19d1205 | 12247 | do_t_cpy (void) |
90e4755a | 12248 | { |
c19d1205 | 12249 | if (inst.size_req == 4) |
90e4755a | 12250 | { |
c19d1205 ZW |
12251 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
12252 | inst.instruction |= inst.operands[0].reg << 8; | |
12253 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 12254 | } |
c19d1205 | 12255 | else |
90e4755a | 12256 | { |
c19d1205 ZW |
12257 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
12258 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
12259 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 12260 | } |
90e4755a RE |
12261 | } |
12262 | ||
90e4755a | 12263 | static void |
25fe350b | 12264 | do_t_cbz (void) |
90e4755a | 12265 | { |
5ee91343 | 12266 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
c19d1205 ZW |
12267 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
12268 | inst.instruction |= inst.operands[0].reg; | |
e2b0ab59 AV |
12269 | inst.relocs[0].pc_rel = 1; |
12270 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
c19d1205 | 12271 | } |
90e4755a | 12272 | |
62b3e311 PB |
12273 | static void |
12274 | do_t_dbg (void) | |
12275 | { | |
12276 | inst.instruction |= inst.operands[0].imm; | |
12277 | } | |
12278 | ||
12279 | static void | |
12280 | do_t_div (void) | |
12281 | { | |
fdfde340 JM |
12282 | unsigned Rd, Rn, Rm; |
12283 | ||
12284 | Rd = inst.operands[0].reg; | |
12285 | Rn = (inst.operands[1].present | |
12286 | ? inst.operands[1].reg : Rd); | |
12287 | Rm = inst.operands[2].reg; | |
12288 | ||
12289 | reject_bad_reg (Rd); | |
12290 | reject_bad_reg (Rn); | |
12291 | reject_bad_reg (Rm); | |
12292 | ||
12293 | inst.instruction |= Rd << 8; | |
12294 | inst.instruction |= Rn << 16; | |
12295 | inst.instruction |= Rm; | |
62b3e311 PB |
12296 | } |
12297 | ||
c19d1205 ZW |
12298 | static void |
12299 | do_t_hint (void) | |
12300 | { | |
12301 | if (unified_syntax && inst.size_req == 4) | |
12302 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12303 | else | |
12304 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12305 | } | |
90e4755a | 12306 | |
c19d1205 ZW |
12307 | static void |
12308 | do_t_it (void) | |
12309 | { | |
12310 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 12311 | |
5ee91343 AV |
12312 | set_pred_insn_type (IT_INSN); |
12313 | now_pred.mask = (inst.instruction & 0xf) | 0x10; | |
12314 | now_pred.cc = cond; | |
12315 | now_pred.warn_deprecated = FALSE; | |
12316 | now_pred.type = SCALAR_PRED; | |
e27ec89e PB |
12317 | |
12318 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 12319 | if ((cond & 0x1) == 0x0) |
90e4755a | 12320 | { |
c19d1205 | 12321 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 12322 | |
c19d1205 | 12323 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
12324 | { |
12325 | /* No conversion needed. */ | |
5ee91343 | 12326 | now_pred.block_length = 1; |
5a01bb1d | 12327 | } |
c19d1205 | 12328 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
12329 | { |
12330 | mask ^= 0x8; | |
5ee91343 | 12331 | now_pred.block_length = 2; |
5a01bb1d | 12332 | } |
e27ec89e | 12333 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
12334 | { |
12335 | mask ^= 0xC; | |
5ee91343 | 12336 | now_pred.block_length = 3; |
5a01bb1d | 12337 | } |
c19d1205 | 12338 | else |
5a01bb1d MGD |
12339 | { |
12340 | mask ^= 0xE; | |
5ee91343 | 12341 | now_pred.block_length = 4; |
5a01bb1d | 12342 | } |
90e4755a | 12343 | |
e27ec89e PB |
12344 | inst.instruction &= 0xfff0; |
12345 | inst.instruction |= mask; | |
c19d1205 | 12346 | } |
90e4755a | 12347 | |
c19d1205 ZW |
12348 | inst.instruction |= cond << 4; |
12349 | } | |
90e4755a | 12350 | |
3c707909 PB |
12351 | /* Helper function used for both push/pop and ldm/stm. */ |
12352 | static void | |
4b5a202f AV |
12353 | encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask, |
12354 | bfd_boolean writeback) | |
3c707909 | 12355 | { |
4b5a202f | 12356 | bfd_boolean load, store; |
3c707909 | 12357 | |
4b5a202f AV |
12358 | gas_assert (base != -1 || !do_io); |
12359 | load = do_io && ((inst.instruction & (1 << 20)) != 0); | |
12360 | store = do_io && !load; | |
3c707909 PB |
12361 | |
12362 | if (mask & (1 << 13)) | |
12363 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 | 12364 | |
4b5a202f | 12365 | if (do_io && (mask & (1 << base)) != 0 |
1e5b0379 NC |
12366 | && writeback) |
12367 | inst.error = _("having the base register in the register list when " | |
12368 | "using write back is UNPREDICTABLE"); | |
12369 | ||
3c707909 PB |
12370 | if (load) |
12371 | { | |
e07e6e58 | 12372 | if (mask & (1 << 15)) |
477330fc RM |
12373 | { |
12374 | if (mask & (1 << 14)) | |
12375 | inst.error = _("LR and PC should not both be in register list"); | |
12376 | else | |
5ee91343 | 12377 | set_pred_insn_type_last (); |
477330fc | 12378 | } |
3c707909 | 12379 | } |
4b5a202f | 12380 | else if (store) |
3c707909 PB |
12381 | { |
12382 | if (mask & (1 << 15)) | |
12383 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
12384 | } |
12385 | ||
4b5a202f | 12386 | if (do_io && ((mask & (mask - 1)) == 0)) |
3c707909 PB |
12387 | { |
12388 | /* Single register transfers implemented as str/ldr. */ | |
12389 | if (writeback) | |
12390 | { | |
12391 | if (inst.instruction & (1 << 23)) | |
12392 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
12393 | else | |
12394 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
12395 | } | |
12396 | else | |
12397 | { | |
12398 | if (inst.instruction & (1 << 23)) | |
12399 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
12400 | else | |
12401 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
12402 | } | |
12403 | ||
12404 | inst.instruction |= 0xf8400000; | |
12405 | if (load) | |
12406 | inst.instruction |= 0x00100000; | |
12407 | ||
5f4273c7 | 12408 | mask = ffs (mask) - 1; |
3c707909 PB |
12409 | mask <<= 12; |
12410 | } | |
12411 | else if (writeback) | |
12412 | inst.instruction |= WRITE_BACK; | |
12413 | ||
12414 | inst.instruction |= mask; | |
4b5a202f AV |
12415 | if (do_io) |
12416 | inst.instruction |= base << 16; | |
3c707909 PB |
12417 | } |
12418 | ||
c19d1205 ZW |
12419 | static void |
12420 | do_t_ldmstm (void) | |
12421 | { | |
12422 | /* This really doesn't seem worth it. */ | |
e2b0ab59 | 12423 | constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, |
c19d1205 ZW |
12424 | _("expression too complex")); |
12425 | constraint (inst.operands[1].writeback, | |
12426 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 12427 | |
c19d1205 ZW |
12428 | if (unified_syntax) |
12429 | { | |
3c707909 PB |
12430 | bfd_boolean narrow; |
12431 | unsigned mask; | |
12432 | ||
12433 | narrow = FALSE; | |
c19d1205 ZW |
12434 | /* See if we can use a 16-bit instruction. */ |
12435 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
12436 | && inst.size_req != 4 | |
3c707909 | 12437 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 12438 | { |
3c707909 | 12439 | mask = 1 << inst.operands[0].reg; |
90e4755a | 12440 | |
eab4f823 | 12441 | if (inst.operands[0].reg <= 7) |
90e4755a | 12442 | { |
3c707909 | 12443 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
12444 | ? inst.operands[0].writeback |
12445 | : (inst.operands[0].writeback | |
12446 | == !(inst.operands[1].imm & mask))) | |
477330fc | 12447 | { |
eab4f823 MGD |
12448 | if (inst.instruction == T_MNEM_stmia |
12449 | && (inst.operands[1].imm & mask) | |
12450 | && (inst.operands[1].imm & (mask - 1))) | |
12451 | as_warn (_("value stored for r%d is UNKNOWN"), | |
12452 | inst.operands[0].reg); | |
3c707909 | 12453 | |
eab4f823 MGD |
12454 | inst.instruction = THUMB_OP16 (inst.instruction); |
12455 | inst.instruction |= inst.operands[0].reg << 8; | |
12456 | inst.instruction |= inst.operands[1].imm; | |
12457 | narrow = TRUE; | |
12458 | } | |
12459 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
12460 | { | |
12461 | /* This means 1 register in reg list one of 3 situations: | |
12462 | 1. Instruction is stmia, but without writeback. | |
12463 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 12464 | reglist. |
eab4f823 MGD |
12465 | 3. ldmia with writeback, but with Rn in reglist. |
12466 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
12467 | case 1 and 2 which can be converted into a 16-bit | |
12468 | str or ldr. The SP cases are handled below. */ | |
12469 | unsigned long opcode; | |
12470 | /* First, record an error for Case 3. */ | |
12471 | if (inst.operands[1].imm & mask | |
12472 | && inst.operands[0].writeback) | |
fa94de6b | 12473 | inst.error = |
eab4f823 MGD |
12474 | _("having the base register in the register list when " |
12475 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
12476 | |
12477 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
12478 | : T_MNEM_ldr); |
12479 | inst.instruction = THUMB_OP16 (opcode); | |
12480 | inst.instruction |= inst.operands[0].reg << 3; | |
12481 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
12482 | narrow = TRUE; | |
12483 | } | |
90e4755a | 12484 | } |
eab4f823 | 12485 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 12486 | { |
eab4f823 MGD |
12487 | if (inst.operands[0].writeback) |
12488 | { | |
fa94de6b | 12489 | inst.instruction = |
eab4f823 | 12490 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 12491 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 12492 | inst.instruction |= inst.operands[1].imm; |
477330fc | 12493 | narrow = TRUE; |
eab4f823 MGD |
12494 | } |
12495 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
12496 | { | |
fa94de6b | 12497 | inst.instruction = |
eab4f823 | 12498 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 12499 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 12500 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 12501 | narrow = TRUE; |
eab4f823 | 12502 | } |
90e4755a | 12503 | } |
3c707909 PB |
12504 | } |
12505 | ||
12506 | if (!narrow) | |
12507 | { | |
c19d1205 ZW |
12508 | if (inst.instruction < 0xffff) |
12509 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 12510 | |
4b5a202f AV |
12511 | encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg, |
12512 | inst.operands[1].imm, | |
12513 | inst.operands[0].writeback); | |
90e4755a RE |
12514 | } |
12515 | } | |
c19d1205 | 12516 | else |
90e4755a | 12517 | { |
c19d1205 ZW |
12518 | constraint (inst.operands[0].reg > 7 |
12519 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
12520 | constraint (inst.instruction != T_MNEM_ldmia |
12521 | && inst.instruction != T_MNEM_stmia, | |
12522 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 12523 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 12524 | { |
c19d1205 ZW |
12525 | if (!inst.operands[0].writeback) |
12526 | as_warn (_("this instruction will write back the base register")); | |
12527 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
12528 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 12529 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 12530 | inst.operands[0].reg); |
f03698e6 | 12531 | } |
c19d1205 | 12532 | else |
90e4755a | 12533 | { |
c19d1205 ZW |
12534 | if (!inst.operands[0].writeback |
12535 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
12536 | as_warn (_("this instruction will write back the base register")); | |
12537 | else if (inst.operands[0].writeback | |
12538 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
12539 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
12540 | } |
12541 | ||
c19d1205 ZW |
12542 | inst.instruction = THUMB_OP16 (inst.instruction); |
12543 | inst.instruction |= inst.operands[0].reg << 8; | |
12544 | inst.instruction |= inst.operands[1].imm; | |
12545 | } | |
12546 | } | |
e28cd48c | 12547 | |
c19d1205 ZW |
12548 | static void |
12549 | do_t_ldrex (void) | |
12550 | { | |
12551 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
12552 | || inst.operands[1].postind || inst.operands[1].writeback | |
12553 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
12554 | || inst.operands[1].negative, | |
01cfc07f | 12555 | BAD_ADDR_MODE); |
e28cd48c | 12556 | |
5be8be5d DG |
12557 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
12558 | ||
c19d1205 ZW |
12559 | inst.instruction |= inst.operands[0].reg << 12; |
12560 | inst.instruction |= inst.operands[1].reg << 16; | |
e2b0ab59 | 12561 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8; |
c19d1205 | 12562 | } |
e28cd48c | 12563 | |
c19d1205 ZW |
12564 | static void |
12565 | do_t_ldrexd (void) | |
12566 | { | |
12567 | if (!inst.operands[1].present) | |
1cac9012 | 12568 | { |
c19d1205 ZW |
12569 | constraint (inst.operands[0].reg == REG_LR, |
12570 | _("r14 not allowed as first register " | |
12571 | "when second register is omitted")); | |
12572 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 12573 | } |
c19d1205 ZW |
12574 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
12575 | BAD_OVERLAP); | |
b99bd4ef | 12576 | |
c19d1205 ZW |
12577 | inst.instruction |= inst.operands[0].reg << 12; |
12578 | inst.instruction |= inst.operands[1].reg << 8; | |
12579 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
12580 | } |
12581 | ||
12582 | static void | |
c19d1205 | 12583 | do_t_ldst (void) |
b99bd4ef | 12584 | { |
0110f2b8 PB |
12585 | unsigned long opcode; |
12586 | int Rn; | |
12587 | ||
e07e6e58 NC |
12588 | if (inst.operands[0].isreg |
12589 | && !inst.operands[0].preind | |
12590 | && inst.operands[0].reg == REG_PC) | |
5ee91343 | 12591 | set_pred_insn_type_last (); |
e07e6e58 | 12592 | |
0110f2b8 | 12593 | opcode = inst.instruction; |
c19d1205 | 12594 | if (unified_syntax) |
b99bd4ef | 12595 | { |
53365c0d PB |
12596 | if (!inst.operands[1].isreg) |
12597 | { | |
12598 | if (opcode <= 0xffff) | |
12599 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 12600 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
12601 | return; |
12602 | } | |
0110f2b8 PB |
12603 | if (inst.operands[1].isreg |
12604 | && !inst.operands[1].writeback | |
c19d1205 ZW |
12605 | && !inst.operands[1].shifted && !inst.operands[1].postind |
12606 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
12607 | && opcode <= 0xffff |
12608 | && inst.size_req != 4) | |
c19d1205 | 12609 | { |
0110f2b8 PB |
12610 | /* Insn may have a 16-bit form. */ |
12611 | Rn = inst.operands[1].reg; | |
12612 | if (inst.operands[1].immisreg) | |
12613 | { | |
12614 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 12615 | /* [Rn, Rik] */ |
0110f2b8 PB |
12616 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
12617 | goto op16; | |
5be8be5d DG |
12618 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
12619 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
12620 | } |
12621 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
12622 | && opcode != T_MNEM_ldrsb) | |
12623 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
12624 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
12625 | { | |
12626 | /* [Rn, #const] */ | |
12627 | if (Rn > 7) | |
12628 | { | |
12629 | if (Rn == REG_PC) | |
12630 | { | |
e2b0ab59 | 12631 | if (inst.relocs[0].pc_rel) |
0110f2b8 PB |
12632 | opcode = T_MNEM_ldr_pc2; |
12633 | else | |
12634 | opcode = T_MNEM_ldr_pc; | |
12635 | } | |
12636 | else | |
12637 | { | |
12638 | if (opcode == T_MNEM_ldr) | |
12639 | opcode = T_MNEM_ldr_sp; | |
12640 | else | |
12641 | opcode = T_MNEM_str_sp; | |
12642 | } | |
12643 | inst.instruction = inst.operands[0].reg << 8; | |
12644 | } | |
12645 | else | |
12646 | { | |
12647 | inst.instruction = inst.operands[0].reg; | |
12648 | inst.instruction |= inst.operands[1].reg << 3; | |
12649 | } | |
12650 | inst.instruction |= THUMB_OP16 (opcode); | |
12651 | if (inst.size_req == 2) | |
e2b0ab59 | 12652 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
0110f2b8 PB |
12653 | else |
12654 | inst.relax = opcode; | |
12655 | return; | |
12656 | } | |
c19d1205 | 12657 | } |
0110f2b8 | 12658 | /* Definitely a 32-bit variant. */ |
5be8be5d | 12659 | |
8d67f500 NC |
12660 | /* Warning for Erratum 752419. */ |
12661 | if (opcode == T_MNEM_ldr | |
12662 | && inst.operands[0].reg == REG_SP | |
12663 | && inst.operands[1].writeback == 1 | |
12664 | && !inst.operands[1].immisreg) | |
12665 | { | |
12666 | if (no_cpu_selected () | |
12667 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
12668 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
12669 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
12670 | as_warn (_("This instruction may be unpredictable " |
12671 | "if executed on M-profile cores " | |
12672 | "with interrupts enabled.")); | |
12673 | } | |
12674 | ||
5be8be5d | 12675 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 12676 | if (inst.operands[1].immisreg) |
5be8be5d DG |
12677 | reject_bad_reg (inst.operands[1].imm); |
12678 | ||
1be5fd2e NC |
12679 | constraint (inst.operands[1].writeback == 1 |
12680 | && inst.operands[0].reg == inst.operands[1].reg, | |
12681 | BAD_OVERLAP); | |
12682 | ||
0110f2b8 | 12683 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
12684 | inst.instruction |= inst.operands[0].reg << 12; |
12685 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 12686 | check_ldr_r15_aligned (); |
b99bd4ef NC |
12687 | return; |
12688 | } | |
12689 | ||
c19d1205 ZW |
12690 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
12691 | ||
12692 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 12693 | { |
c19d1205 ZW |
12694 | /* Only [Rn,Rm] is acceptable. */ |
12695 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
12696 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
12697 | || inst.operands[1].postind || inst.operands[1].shifted | |
12698 | || inst.operands[1].negative, | |
12699 | _("Thumb does not support this addressing mode")); | |
12700 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12701 | goto op16; | |
b99bd4ef | 12702 | } |
5f4273c7 | 12703 | |
c19d1205 ZW |
12704 | inst.instruction = THUMB_OP16 (inst.instruction); |
12705 | if (!inst.operands[1].isreg) | |
8335d6aa | 12706 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 12707 | return; |
b99bd4ef | 12708 | |
c19d1205 ZW |
12709 | constraint (!inst.operands[1].preind |
12710 | || inst.operands[1].shifted | |
12711 | || inst.operands[1].writeback, | |
12712 | _("Thumb does not support this addressing mode")); | |
12713 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 12714 | { |
c19d1205 ZW |
12715 | constraint (inst.instruction & 0x0600, |
12716 | _("byte or halfword not valid for base register")); | |
12717 | constraint (inst.operands[1].reg == REG_PC | |
12718 | && !(inst.instruction & THUMB_LOAD_BIT), | |
12719 | _("r15 based store not allowed")); | |
12720 | constraint (inst.operands[1].immisreg, | |
12721 | _("invalid base register for register offset")); | |
b99bd4ef | 12722 | |
c19d1205 ZW |
12723 | if (inst.operands[1].reg == REG_PC) |
12724 | inst.instruction = T_OPCODE_LDR_PC; | |
12725 | else if (inst.instruction & THUMB_LOAD_BIT) | |
12726 | inst.instruction = T_OPCODE_LDR_SP; | |
12727 | else | |
12728 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 12729 | |
c19d1205 | 12730 | inst.instruction |= inst.operands[0].reg << 8; |
e2b0ab59 | 12731 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
c19d1205 ZW |
12732 | return; |
12733 | } | |
90e4755a | 12734 | |
c19d1205 ZW |
12735 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
12736 | if (!inst.operands[1].immisreg) | |
12737 | { | |
12738 | /* Immediate offset. */ | |
12739 | inst.instruction |= inst.operands[0].reg; | |
12740 | inst.instruction |= inst.operands[1].reg << 3; | |
e2b0ab59 | 12741 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET; |
c19d1205 ZW |
12742 | return; |
12743 | } | |
90e4755a | 12744 | |
c19d1205 ZW |
12745 | /* Register offset. */ |
12746 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
12747 | constraint (inst.operands[1].negative, | |
12748 | _("Thumb does not support this addressing mode")); | |
90e4755a | 12749 | |
c19d1205 ZW |
12750 | op16: |
12751 | switch (inst.instruction) | |
12752 | { | |
12753 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
12754 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
12755 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
12756 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
12757 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
12758 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
12759 | case 0x5600 /* ldrsb */: | |
12760 | case 0x5e00 /* ldrsh */: break; | |
12761 | default: abort (); | |
12762 | } | |
90e4755a | 12763 | |
c19d1205 ZW |
12764 | inst.instruction |= inst.operands[0].reg; |
12765 | inst.instruction |= inst.operands[1].reg << 3; | |
12766 | inst.instruction |= inst.operands[1].imm << 6; | |
12767 | } | |
90e4755a | 12768 | |
c19d1205 ZW |
12769 | static void |
12770 | do_t_ldstd (void) | |
12771 | { | |
12772 | if (!inst.operands[1].present) | |
b99bd4ef | 12773 | { |
c19d1205 ZW |
12774 | inst.operands[1].reg = inst.operands[0].reg + 1; |
12775 | constraint (inst.operands[0].reg == REG_LR, | |
12776 | _("r14 not allowed here")); | |
bd340a04 | 12777 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 12778 | _("r12 not allowed here")); |
b99bd4ef | 12779 | } |
bd340a04 MGD |
12780 | |
12781 | if (inst.operands[2].writeback | |
12782 | && (inst.operands[0].reg == inst.operands[2].reg | |
12783 | || inst.operands[1].reg == inst.operands[2].reg)) | |
12784 | as_warn (_("base register written back, and overlaps " | |
477330fc | 12785 | "one of transfer registers")); |
bd340a04 | 12786 | |
c19d1205 ZW |
12787 | inst.instruction |= inst.operands[0].reg << 12; |
12788 | inst.instruction |= inst.operands[1].reg << 8; | |
12789 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
12790 | } |
12791 | ||
c19d1205 ZW |
12792 | static void |
12793 | do_t_ldstt (void) | |
12794 | { | |
12795 | inst.instruction |= inst.operands[0].reg << 12; | |
12796 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
12797 | } | |
a737bd4d | 12798 | |
b99bd4ef | 12799 | static void |
c19d1205 | 12800 | do_t_mla (void) |
b99bd4ef | 12801 | { |
fdfde340 | 12802 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 12803 | |
fdfde340 JM |
12804 | Rd = inst.operands[0].reg; |
12805 | Rn = inst.operands[1].reg; | |
12806 | Rm = inst.operands[2].reg; | |
12807 | Ra = inst.operands[3].reg; | |
12808 | ||
12809 | reject_bad_reg (Rd); | |
12810 | reject_bad_reg (Rn); | |
12811 | reject_bad_reg (Rm); | |
12812 | reject_bad_reg (Ra); | |
12813 | ||
12814 | inst.instruction |= Rd << 8; | |
12815 | inst.instruction |= Rn << 16; | |
12816 | inst.instruction |= Rm; | |
12817 | inst.instruction |= Ra << 12; | |
c19d1205 | 12818 | } |
b99bd4ef | 12819 | |
c19d1205 ZW |
12820 | static void |
12821 | do_t_mlal (void) | |
12822 | { | |
fdfde340 JM |
12823 | unsigned RdLo, RdHi, Rn, Rm; |
12824 | ||
12825 | RdLo = inst.operands[0].reg; | |
12826 | RdHi = inst.operands[1].reg; | |
12827 | Rn = inst.operands[2].reg; | |
12828 | Rm = inst.operands[3].reg; | |
12829 | ||
12830 | reject_bad_reg (RdLo); | |
12831 | reject_bad_reg (RdHi); | |
12832 | reject_bad_reg (Rn); | |
12833 | reject_bad_reg (Rm); | |
12834 | ||
12835 | inst.instruction |= RdLo << 12; | |
12836 | inst.instruction |= RdHi << 8; | |
12837 | inst.instruction |= Rn << 16; | |
12838 | inst.instruction |= Rm; | |
c19d1205 | 12839 | } |
b99bd4ef | 12840 | |
c19d1205 ZW |
12841 | static void |
12842 | do_t_mov_cmp (void) | |
12843 | { | |
fdfde340 JM |
12844 | unsigned Rn, Rm; |
12845 | ||
12846 | Rn = inst.operands[0].reg; | |
12847 | Rm = inst.operands[1].reg; | |
12848 | ||
e07e6e58 | 12849 | if (Rn == REG_PC) |
5ee91343 | 12850 | set_pred_insn_type_last (); |
e07e6e58 | 12851 | |
c19d1205 | 12852 | if (unified_syntax) |
b99bd4ef | 12853 | { |
c19d1205 ZW |
12854 | int r0off = (inst.instruction == T_MNEM_mov |
12855 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 12856 | unsigned long opcode; |
3d388997 PB |
12857 | bfd_boolean narrow; |
12858 | bfd_boolean low_regs; | |
12859 | ||
fdfde340 | 12860 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 12861 | opcode = inst.instruction; |
5ee91343 | 12862 | if (in_pred_block ()) |
0110f2b8 | 12863 | narrow = opcode != T_MNEM_movs; |
3d388997 | 12864 | else |
0110f2b8 | 12865 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
12866 | if (inst.size_req == 4 |
12867 | || inst.operands[1].shifted) | |
12868 | narrow = FALSE; | |
12869 | ||
efd81785 PB |
12870 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
12871 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
12872 | && !inst.operands[1].shifted | |
fdfde340 JM |
12873 | && Rn == REG_PC |
12874 | && Rm == REG_LR) | |
efd81785 PB |
12875 | { |
12876 | inst.instruction = T2_SUBS_PC_LR; | |
12877 | return; | |
12878 | } | |
12879 | ||
fdfde340 JM |
12880 | if (opcode == T_MNEM_cmp) |
12881 | { | |
12882 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
12883 | if (narrow) |
12884 | { | |
12885 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
12886 | but valid. */ | |
12887 | warn_deprecated_sp (Rm); | |
12888 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
12889 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
12890 | tools reject R15, so we do too. */ | |
12891 | constraint (Rm == REG_PC, BAD_PC); | |
12892 | } | |
12893 | else | |
12894 | reject_bad_reg (Rm); | |
fdfde340 JM |
12895 | } |
12896 | else if (opcode == T_MNEM_mov | |
12897 | || opcode == T_MNEM_movs) | |
12898 | { | |
12899 | if (inst.operands[1].isreg) | |
12900 | { | |
12901 | if (opcode == T_MNEM_movs) | |
12902 | { | |
12903 | reject_bad_reg (Rn); | |
12904 | reject_bad_reg (Rm); | |
12905 | } | |
76fa04a4 MGD |
12906 | else if (narrow) |
12907 | { | |
12908 | /* This is mov.n. */ | |
12909 | if ((Rn == REG_SP || Rn == REG_PC) | |
12910 | && (Rm == REG_SP || Rm == REG_PC)) | |
12911 | { | |
5c3696f8 | 12912 | as_tsktsk (_("Use of r%u as a source register is " |
76fa04a4 MGD |
12913 | "deprecated when r%u is the destination " |
12914 | "register."), Rm, Rn); | |
12915 | } | |
12916 | } | |
12917 | else | |
12918 | { | |
12919 | /* This is mov.w. */ | |
12920 | constraint (Rn == REG_PC, BAD_PC); | |
12921 | constraint (Rm == REG_PC, BAD_PC); | |
5c8ed6a4 JW |
12922 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
12923 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
76fa04a4 | 12924 | } |
fdfde340 JM |
12925 | } |
12926 | else | |
12927 | reject_bad_reg (Rn); | |
12928 | } | |
12929 | ||
c19d1205 ZW |
12930 | if (!inst.operands[1].isreg) |
12931 | { | |
0110f2b8 | 12932 | /* Immediate operand. */ |
5ee91343 | 12933 | if (!in_pred_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
12934 | narrow = 0; |
12935 | if (low_regs && narrow) | |
12936 | { | |
12937 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 12938 | inst.instruction |= Rn << 8; |
e2b0ab59 AV |
12939 | if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC |
12940 | || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
72d98d16 | 12941 | { |
a9f02af8 | 12942 | if (inst.size_req == 2) |
e2b0ab59 | 12943 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM; |
a9f02af8 MG |
12944 | else |
12945 | inst.relax = opcode; | |
72d98d16 | 12946 | } |
0110f2b8 PB |
12947 | } |
12948 | else | |
12949 | { | |
e2b0ab59 AV |
12950 | constraint ((inst.relocs[0].type |
12951 | >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC) | |
12952 | && (inst.relocs[0].type | |
12953 | <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) , | |
a9f02af8 MG |
12954 | THUMB1_RELOC_ONLY); |
12955 | ||
0110f2b8 PB |
12956 | inst.instruction = THUMB_OP32 (inst.instruction); |
12957 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 12958 | inst.instruction |= Rn << r0off; |
e2b0ab59 | 12959 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
0110f2b8 | 12960 | } |
c19d1205 | 12961 | } |
728ca7c9 PB |
12962 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
12963 | && (inst.instruction == T_MNEM_mov | |
12964 | || inst.instruction == T_MNEM_movs)) | |
12965 | { | |
12966 | /* Register shifts are encoded as separate shift instructions. */ | |
12967 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
12968 | ||
5ee91343 | 12969 | if (in_pred_block ()) |
728ca7c9 PB |
12970 | narrow = !flags; |
12971 | else | |
12972 | narrow = flags; | |
12973 | ||
12974 | if (inst.size_req == 4) | |
12975 | narrow = FALSE; | |
12976 | ||
12977 | if (!low_regs || inst.operands[1].imm > 7) | |
12978 | narrow = FALSE; | |
12979 | ||
fdfde340 | 12980 | if (Rn != Rm) |
728ca7c9 PB |
12981 | narrow = FALSE; |
12982 | ||
12983 | switch (inst.operands[1].shift_kind) | |
12984 | { | |
12985 | case SHIFT_LSL: | |
12986 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
12987 | break; | |
12988 | case SHIFT_ASR: | |
12989 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
12990 | break; | |
12991 | case SHIFT_LSR: | |
12992 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
12993 | break; | |
12994 | case SHIFT_ROR: | |
12995 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
12996 | break; | |
12997 | default: | |
5f4273c7 | 12998 | abort (); |
728ca7c9 PB |
12999 | } |
13000 | ||
13001 | inst.instruction = opcode; | |
13002 | if (narrow) | |
13003 | { | |
fdfde340 | 13004 | inst.instruction |= Rn; |
728ca7c9 PB |
13005 | inst.instruction |= inst.operands[1].imm << 3; |
13006 | } | |
13007 | else | |
13008 | { | |
13009 | if (flags) | |
13010 | inst.instruction |= CONDS_BIT; | |
13011 | ||
fdfde340 JM |
13012 | inst.instruction |= Rn << 8; |
13013 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
13014 | inst.instruction |= inst.operands[1].imm; |
13015 | } | |
13016 | } | |
3d388997 | 13017 | else if (!narrow) |
c19d1205 | 13018 | { |
728ca7c9 PB |
13019 | /* Some mov with immediate shift have narrow variants. |
13020 | Register shifts are handled above. */ | |
13021 | if (low_regs && inst.operands[1].shifted | |
13022 | && (inst.instruction == T_MNEM_mov | |
13023 | || inst.instruction == T_MNEM_movs)) | |
13024 | { | |
5ee91343 | 13025 | if (in_pred_block ()) |
728ca7c9 PB |
13026 | narrow = (inst.instruction == T_MNEM_mov); |
13027 | else | |
13028 | narrow = (inst.instruction == T_MNEM_movs); | |
13029 | } | |
13030 | ||
13031 | if (narrow) | |
13032 | { | |
13033 | switch (inst.operands[1].shift_kind) | |
13034 | { | |
13035 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
13036 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
13037 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
13038 | default: narrow = FALSE; break; | |
13039 | } | |
13040 | } | |
13041 | ||
13042 | if (narrow) | |
13043 | { | |
fdfde340 JM |
13044 | inst.instruction |= Rn; |
13045 | inst.instruction |= Rm << 3; | |
e2b0ab59 | 13046 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
728ca7c9 PB |
13047 | } |
13048 | else | |
13049 | { | |
13050 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 13051 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
13052 | encode_thumb32_shifted_operand (1); |
13053 | } | |
c19d1205 ZW |
13054 | } |
13055 | else | |
13056 | switch (inst.instruction) | |
13057 | { | |
13058 | case T_MNEM_mov: | |
837b3435 | 13059 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
13060 | results. Don't allow this. */ |
13061 | if (low_regs) | |
13062 | { | |
13063 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
13064 | "MOV Rd, Rs with two low registers is not " | |
13065 | "permitted on this architecture"); | |
fa94de6b | 13066 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
13067 | arm_ext_v6); |
13068 | } | |
13069 | ||
c19d1205 | 13070 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
13071 | inst.instruction |= (Rn & 0x8) << 4; |
13072 | inst.instruction |= (Rn & 0x7); | |
13073 | inst.instruction |= Rm << 3; | |
c19d1205 | 13074 | break; |
b99bd4ef | 13075 | |
c19d1205 ZW |
13076 | case T_MNEM_movs: |
13077 | /* We know we have low registers at this point. | |
941a8a52 MGD |
13078 | Generate LSLS Rd, Rs, #0. */ |
13079 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
13080 | inst.instruction |= Rn; |
13081 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
13082 | break; |
13083 | ||
13084 | case T_MNEM_cmp: | |
3d388997 | 13085 | if (low_regs) |
c19d1205 ZW |
13086 | { |
13087 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
13088 | inst.instruction |= Rn; |
13089 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
13090 | } |
13091 | else | |
13092 | { | |
13093 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
13094 | inst.instruction |= (Rn & 0x8) << 4; |
13095 | inst.instruction |= (Rn & 0x7); | |
13096 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
13097 | } |
13098 | break; | |
13099 | } | |
b99bd4ef NC |
13100 | return; |
13101 | } | |
13102 | ||
c19d1205 | 13103 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
13104 | |
13105 | /* PR 10443: Do not silently ignore shifted operands. */ | |
13106 | constraint (inst.operands[1].shifted, | |
13107 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
13108 | ||
c19d1205 | 13109 | if (inst.operands[1].isreg) |
b99bd4ef | 13110 | { |
fdfde340 | 13111 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 13112 | { |
c19d1205 ZW |
13113 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
13114 | since a MOV instruction produces unpredictable results. */ | |
13115 | if (inst.instruction == T_OPCODE_MOV_I8) | |
13116 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 13117 | else |
c19d1205 | 13118 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 13119 | |
fdfde340 JM |
13120 | inst.instruction |= Rn; |
13121 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
13122 | } |
13123 | else | |
13124 | { | |
c19d1205 ZW |
13125 | if (inst.instruction == T_OPCODE_MOV_I8) |
13126 | inst.instruction = T_OPCODE_MOV_HR; | |
13127 | else | |
13128 | inst.instruction = T_OPCODE_CMP_HR; | |
13129 | do_t_cpy (); | |
b99bd4ef NC |
13130 | } |
13131 | } | |
c19d1205 | 13132 | else |
b99bd4ef | 13133 | { |
fdfde340 | 13134 | constraint (Rn > 7, |
c19d1205 | 13135 | _("only lo regs allowed with immediate")); |
fdfde340 | 13136 | inst.instruction |= Rn << 8; |
e2b0ab59 | 13137 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM; |
c19d1205 ZW |
13138 | } |
13139 | } | |
b99bd4ef | 13140 | |
c19d1205 ZW |
13141 | static void |
13142 | do_t_mov16 (void) | |
13143 | { | |
fdfde340 | 13144 | unsigned Rd; |
b6895b4f PB |
13145 | bfd_vma imm; |
13146 | bfd_boolean top; | |
13147 | ||
13148 | top = (inst.instruction & 0x00800000) != 0; | |
e2b0ab59 | 13149 | if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW) |
b6895b4f | 13150 | { |
33eaf5de | 13151 | constraint (top, _(":lower16: not allowed in this instruction")); |
e2b0ab59 | 13152 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW; |
b6895b4f | 13153 | } |
e2b0ab59 | 13154 | else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT) |
b6895b4f | 13155 | { |
33eaf5de | 13156 | constraint (!top, _(":upper16: not allowed in this instruction")); |
e2b0ab59 | 13157 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT; |
b6895b4f PB |
13158 | } |
13159 | ||
fdfde340 JM |
13160 | Rd = inst.operands[0].reg; |
13161 | reject_bad_reg (Rd); | |
13162 | ||
13163 | inst.instruction |= Rd << 8; | |
e2b0ab59 | 13164 | if (inst.relocs[0].type == BFD_RELOC_UNUSED) |
b6895b4f | 13165 | { |
e2b0ab59 | 13166 | imm = inst.relocs[0].exp.X_add_number; |
b6895b4f PB |
13167 | inst.instruction |= (imm & 0xf000) << 4; |
13168 | inst.instruction |= (imm & 0x0800) << 15; | |
13169 | inst.instruction |= (imm & 0x0700) << 4; | |
13170 | inst.instruction |= (imm & 0x00ff); | |
13171 | } | |
c19d1205 | 13172 | } |
b99bd4ef | 13173 | |
c19d1205 ZW |
13174 | static void |
13175 | do_t_mvn_tst (void) | |
13176 | { | |
fdfde340 | 13177 | unsigned Rn, Rm; |
c921be7d | 13178 | |
fdfde340 JM |
13179 | Rn = inst.operands[0].reg; |
13180 | Rm = inst.operands[1].reg; | |
13181 | ||
13182 | if (inst.instruction == T_MNEM_cmp | |
13183 | || inst.instruction == T_MNEM_cmn) | |
13184 | constraint (Rn == REG_PC, BAD_PC); | |
13185 | else | |
13186 | reject_bad_reg (Rn); | |
13187 | reject_bad_reg (Rm); | |
13188 | ||
c19d1205 ZW |
13189 | if (unified_syntax) |
13190 | { | |
13191 | int r0off = (inst.instruction == T_MNEM_mvn | |
13192 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
13193 | bfd_boolean narrow; |
13194 | ||
13195 | if (inst.size_req == 4 | |
13196 | || inst.instruction > 0xffff | |
13197 | || inst.operands[1].shifted | |
fdfde340 | 13198 | || Rn > 7 || Rm > 7) |
3d388997 | 13199 | narrow = FALSE; |
fe8b4cc3 KT |
13200 | else if (inst.instruction == T_MNEM_cmn |
13201 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
13202 | narrow = TRUE; |
13203 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
5ee91343 | 13204 | narrow = !in_pred_block (); |
3d388997 | 13205 | else |
5ee91343 | 13206 | narrow = in_pred_block (); |
3d388997 | 13207 | |
c19d1205 | 13208 | if (!inst.operands[1].isreg) |
b99bd4ef | 13209 | { |
c19d1205 ZW |
13210 | /* For an immediate, we always generate a 32-bit opcode; |
13211 | section relaxation will shrink it later if possible. */ | |
13212 | if (inst.instruction < 0xffff) | |
13213 | inst.instruction = THUMB_OP32 (inst.instruction); | |
13214 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 13215 | inst.instruction |= Rn << r0off; |
e2b0ab59 | 13216 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 13217 | } |
c19d1205 | 13218 | else |
b99bd4ef | 13219 | { |
c19d1205 | 13220 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 13221 | if (narrow) |
b99bd4ef | 13222 | { |
c19d1205 | 13223 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
13224 | inst.instruction |= Rn; |
13225 | inst.instruction |= Rm << 3; | |
b99bd4ef | 13226 | } |
c19d1205 | 13227 | else |
b99bd4ef | 13228 | { |
c19d1205 ZW |
13229 | constraint (inst.operands[1].shifted |
13230 | && inst.operands[1].immisreg, | |
13231 | _("shift must be constant")); | |
13232 | if (inst.instruction < 0xffff) | |
13233 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 13234 | inst.instruction |= Rn << r0off; |
c19d1205 | 13235 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 13236 | } |
b99bd4ef NC |
13237 | } |
13238 | } | |
13239 | else | |
13240 | { | |
c19d1205 ZW |
13241 | constraint (inst.instruction > 0xffff |
13242 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
13243 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
13244 | _("unshifted register required")); | |
fdfde340 | 13245 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 13246 | BAD_HIREG); |
b99bd4ef | 13247 | |
c19d1205 | 13248 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
13249 | inst.instruction |= Rn; |
13250 | inst.instruction |= Rm << 3; | |
b99bd4ef | 13251 | } |
b99bd4ef NC |
13252 | } |
13253 | ||
b05fe5cf | 13254 | static void |
c19d1205 | 13255 | do_t_mrs (void) |
b05fe5cf | 13256 | { |
fdfde340 | 13257 | unsigned Rd; |
037e8744 JB |
13258 | |
13259 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
13260 | return; | |
13261 | ||
90ec0d68 MGD |
13262 | Rd = inst.operands[0].reg; |
13263 | reject_bad_reg (Rd); | |
13264 | inst.instruction |= Rd << 8; | |
13265 | ||
13266 | if (inst.operands[1].isreg) | |
62b3e311 | 13267 | { |
90ec0d68 MGD |
13268 | unsigned br = inst.operands[1].reg; |
13269 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
13270 | as_bad (_("bad register for mrs")); | |
13271 | ||
13272 | inst.instruction |= br & (0xf << 16); | |
13273 | inst.instruction |= (br & 0x300) >> 4; | |
13274 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
13275 | } |
13276 | else | |
13277 | { | |
90ec0d68 | 13278 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 13279 | |
d2cd1205 | 13280 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
13281 | { |
13282 | /* PR gas/12698: The constraint is only applied for m_profile. | |
13283 | If the user has specified -march=all, we want to ignore it as | |
13284 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
13285 | bfd_boolean m_profile = |
13286 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf NC |
13287 | constraint ((flags != 0) && m_profile, _("selected processor does " |
13288 | "not support requested special purpose register")); | |
13289 | } | |
90ec0d68 | 13290 | else |
d2cd1205 JB |
13291 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
13292 | devices). */ | |
13293 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
13294 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 13295 | |
90ec0d68 MGD |
13296 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
13297 | inst.instruction |= inst.operands[1].imm & 0xff; | |
13298 | inst.instruction |= 0xf0000; | |
13299 | } | |
c19d1205 | 13300 | } |
b05fe5cf | 13301 | |
c19d1205 ZW |
13302 | static void |
13303 | do_t_msr (void) | |
13304 | { | |
62b3e311 | 13305 | int flags; |
fdfde340 | 13306 | unsigned Rn; |
62b3e311 | 13307 | |
037e8744 JB |
13308 | if (do_vfp_nsyn_msr () == SUCCESS) |
13309 | return; | |
13310 | ||
c19d1205 ZW |
13311 | constraint (!inst.operands[1].isreg, |
13312 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
13313 | |
13314 | if (inst.operands[0].isreg) | |
13315 | flags = (int)(inst.operands[0].reg); | |
13316 | else | |
13317 | flags = inst.operands[0].imm; | |
13318 | ||
d2cd1205 | 13319 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 13320 | { |
d2cd1205 JB |
13321 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
13322 | ||
1a43faaf | 13323 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
13324 | If the user has specified -march=all, we want to ignore it as |
13325 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
13326 | bfd_boolean m_profile = |
13327 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf | 13328 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
477330fc RM |
13329 | && (bits & ~(PSR_s | PSR_f)) != 0) |
13330 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
13331 | && bits != PSR_f)) && m_profile, | |
13332 | _("selected processor does not support requested special " | |
13333 | "purpose register")); | |
62b3e311 PB |
13334 | } |
13335 | else | |
d2cd1205 JB |
13336 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
13337 | "requested special purpose register")); | |
c921be7d | 13338 | |
fdfde340 JM |
13339 | Rn = inst.operands[1].reg; |
13340 | reject_bad_reg (Rn); | |
13341 | ||
62b3e311 | 13342 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
13343 | inst.instruction |= (flags & 0xf0000) >> 8; |
13344 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 13345 | inst.instruction |= (flags & 0xff); |
fdfde340 | 13346 | inst.instruction |= Rn << 16; |
c19d1205 | 13347 | } |
b05fe5cf | 13348 | |
c19d1205 ZW |
13349 | static void |
13350 | do_t_mul (void) | |
13351 | { | |
17828f45 | 13352 | bfd_boolean narrow; |
fdfde340 | 13353 | unsigned Rd, Rn, Rm; |
17828f45 | 13354 | |
c19d1205 ZW |
13355 | if (!inst.operands[2].present) |
13356 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 13357 | |
fdfde340 JM |
13358 | Rd = inst.operands[0].reg; |
13359 | Rn = inst.operands[1].reg; | |
13360 | Rm = inst.operands[2].reg; | |
13361 | ||
17828f45 | 13362 | if (unified_syntax) |
b05fe5cf | 13363 | { |
17828f45 | 13364 | if (inst.size_req == 4 |
fdfde340 JM |
13365 | || (Rd != Rn |
13366 | && Rd != Rm) | |
13367 | || Rn > 7 | |
13368 | || Rm > 7) | |
17828f45 JM |
13369 | narrow = FALSE; |
13370 | else if (inst.instruction == T_MNEM_muls) | |
5ee91343 | 13371 | narrow = !in_pred_block (); |
17828f45 | 13372 | else |
5ee91343 | 13373 | narrow = in_pred_block (); |
b05fe5cf | 13374 | } |
c19d1205 | 13375 | else |
b05fe5cf | 13376 | { |
17828f45 | 13377 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 13378 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 13379 | BAD_HIREG); |
17828f45 JM |
13380 | narrow = TRUE; |
13381 | } | |
b05fe5cf | 13382 | |
17828f45 JM |
13383 | if (narrow) |
13384 | { | |
13385 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 13386 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 13387 | inst.instruction |= Rd; |
b05fe5cf | 13388 | |
fdfde340 JM |
13389 | if (Rd == Rn) |
13390 | inst.instruction |= Rm << 3; | |
13391 | else if (Rd == Rm) | |
13392 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
13393 | else |
13394 | constraint (1, _("dest must overlap one source register")); | |
13395 | } | |
17828f45 JM |
13396 | else |
13397 | { | |
e07e6e58 NC |
13398 | constraint (inst.instruction != T_MNEM_mul, |
13399 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
13400 | /* 32-bit MUL. */ |
13401 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
13402 | inst.instruction |= Rd << 8; |
13403 | inst.instruction |= Rn << 16; | |
13404 | inst.instruction |= Rm << 0; | |
13405 | ||
13406 | reject_bad_reg (Rd); | |
13407 | reject_bad_reg (Rn); | |
13408 | reject_bad_reg (Rm); | |
17828f45 | 13409 | } |
c19d1205 | 13410 | } |
b05fe5cf | 13411 | |
c19d1205 ZW |
13412 | static void |
13413 | do_t_mull (void) | |
13414 | { | |
fdfde340 | 13415 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 13416 | |
fdfde340 JM |
13417 | RdLo = inst.operands[0].reg; |
13418 | RdHi = inst.operands[1].reg; | |
13419 | Rn = inst.operands[2].reg; | |
13420 | Rm = inst.operands[3].reg; | |
13421 | ||
13422 | reject_bad_reg (RdLo); | |
13423 | reject_bad_reg (RdHi); | |
13424 | reject_bad_reg (Rn); | |
13425 | reject_bad_reg (Rm); | |
13426 | ||
13427 | inst.instruction |= RdLo << 12; | |
13428 | inst.instruction |= RdHi << 8; | |
13429 | inst.instruction |= Rn << 16; | |
13430 | inst.instruction |= Rm; | |
13431 | ||
13432 | if (RdLo == RdHi) | |
c19d1205 ZW |
13433 | as_tsktsk (_("rdhi and rdlo must be different")); |
13434 | } | |
b05fe5cf | 13435 | |
c19d1205 ZW |
13436 | static void |
13437 | do_t_nop (void) | |
13438 | { | |
5ee91343 | 13439 | set_pred_insn_type (NEUTRAL_IT_INSN); |
e07e6e58 | 13440 | |
c19d1205 ZW |
13441 | if (unified_syntax) |
13442 | { | |
13443 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 13444 | { |
c19d1205 ZW |
13445 | inst.instruction = THUMB_OP32 (inst.instruction); |
13446 | inst.instruction |= inst.operands[0].imm; | |
13447 | } | |
13448 | else | |
13449 | { | |
bc2d1808 NC |
13450 | /* PR9722: Check for Thumb2 availability before |
13451 | generating a thumb2 nop instruction. */ | |
afa62d5e | 13452 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
13453 | { |
13454 | inst.instruction = THUMB_OP16 (inst.instruction); | |
13455 | inst.instruction |= inst.operands[0].imm << 4; | |
13456 | } | |
13457 | else | |
13458 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
13459 | } |
13460 | } | |
13461 | else | |
13462 | { | |
13463 | constraint (inst.operands[0].present, | |
13464 | _("Thumb does not support NOP with hints")); | |
13465 | inst.instruction = 0x46c0; | |
13466 | } | |
13467 | } | |
b05fe5cf | 13468 | |
c19d1205 ZW |
13469 | static void |
13470 | do_t_neg (void) | |
13471 | { | |
13472 | if (unified_syntax) | |
13473 | { | |
3d388997 PB |
13474 | bfd_boolean narrow; |
13475 | ||
13476 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
5ee91343 | 13477 | narrow = !in_pred_block (); |
3d388997 | 13478 | else |
5ee91343 | 13479 | narrow = in_pred_block (); |
3d388997 PB |
13480 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
13481 | narrow = FALSE; | |
13482 | if (inst.size_req == 4) | |
13483 | narrow = FALSE; | |
13484 | ||
13485 | if (!narrow) | |
c19d1205 ZW |
13486 | { |
13487 | inst.instruction = THUMB_OP32 (inst.instruction); | |
13488 | inst.instruction |= inst.operands[0].reg << 8; | |
13489 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
13490 | } |
13491 | else | |
13492 | { | |
c19d1205 ZW |
13493 | inst.instruction = THUMB_OP16 (inst.instruction); |
13494 | inst.instruction |= inst.operands[0].reg; | |
13495 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
13496 | } |
13497 | } | |
13498 | else | |
13499 | { | |
c19d1205 ZW |
13500 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
13501 | BAD_HIREG); | |
13502 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
13503 | ||
13504 | inst.instruction = THUMB_OP16 (inst.instruction); | |
13505 | inst.instruction |= inst.operands[0].reg; | |
13506 | inst.instruction |= inst.operands[1].reg << 3; | |
13507 | } | |
13508 | } | |
13509 | ||
1c444d06 JM |
13510 | static void |
13511 | do_t_orn (void) | |
13512 | { | |
13513 | unsigned Rd, Rn; | |
13514 | ||
13515 | Rd = inst.operands[0].reg; | |
13516 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
13517 | ||
fdfde340 JM |
13518 | reject_bad_reg (Rd); |
13519 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
13520 | reject_bad_reg (Rn); | |
13521 | ||
1c444d06 JM |
13522 | inst.instruction |= Rd << 8; |
13523 | inst.instruction |= Rn << 16; | |
13524 | ||
13525 | if (!inst.operands[2].isreg) | |
13526 | { | |
13527 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
e2b0ab59 | 13528 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
1c444d06 JM |
13529 | } |
13530 | else | |
13531 | { | |
13532 | unsigned Rm; | |
13533 | ||
13534 | Rm = inst.operands[2].reg; | |
fdfde340 | 13535 | reject_bad_reg (Rm); |
1c444d06 JM |
13536 | |
13537 | constraint (inst.operands[2].shifted | |
13538 | && inst.operands[2].immisreg, | |
13539 | _("shift must be constant")); | |
13540 | encode_thumb32_shifted_operand (2); | |
13541 | } | |
13542 | } | |
13543 | ||
c19d1205 ZW |
13544 | static void |
13545 | do_t_pkhbt (void) | |
13546 | { | |
fdfde340 JM |
13547 | unsigned Rd, Rn, Rm; |
13548 | ||
13549 | Rd = inst.operands[0].reg; | |
13550 | Rn = inst.operands[1].reg; | |
13551 | Rm = inst.operands[2].reg; | |
13552 | ||
13553 | reject_bad_reg (Rd); | |
13554 | reject_bad_reg (Rn); | |
13555 | reject_bad_reg (Rm); | |
13556 | ||
13557 | inst.instruction |= Rd << 8; | |
13558 | inst.instruction |= Rn << 16; | |
13559 | inst.instruction |= Rm; | |
c19d1205 ZW |
13560 | if (inst.operands[3].present) |
13561 | { | |
e2b0ab59 AV |
13562 | unsigned int val = inst.relocs[0].exp.X_add_number; |
13563 | constraint (inst.relocs[0].exp.X_op != O_constant, | |
c19d1205 ZW |
13564 | _("expression too complex")); |
13565 | inst.instruction |= (val & 0x1c) << 10; | |
13566 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 13567 | } |
c19d1205 | 13568 | } |
b05fe5cf | 13569 | |
c19d1205 ZW |
13570 | static void |
13571 | do_t_pkhtb (void) | |
13572 | { | |
13573 | if (!inst.operands[3].present) | |
1ef52f49 NC |
13574 | { |
13575 | unsigned Rtmp; | |
13576 | ||
13577 | inst.instruction &= ~0x00000020; | |
13578 | ||
13579 | /* PR 10168. Swap the Rm and Rn registers. */ | |
13580 | Rtmp = inst.operands[1].reg; | |
13581 | inst.operands[1].reg = inst.operands[2].reg; | |
13582 | inst.operands[2].reg = Rtmp; | |
13583 | } | |
c19d1205 | 13584 | do_t_pkhbt (); |
b05fe5cf ZW |
13585 | } |
13586 | ||
c19d1205 ZW |
13587 | static void |
13588 | do_t_pld (void) | |
13589 | { | |
fdfde340 JM |
13590 | if (inst.operands[0].immisreg) |
13591 | reject_bad_reg (inst.operands[0].imm); | |
13592 | ||
c19d1205 ZW |
13593 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
13594 | } | |
b05fe5cf | 13595 | |
c19d1205 ZW |
13596 | static void |
13597 | do_t_push_pop (void) | |
b99bd4ef | 13598 | { |
e9f89963 | 13599 | unsigned mask; |
5f4273c7 | 13600 | |
c19d1205 ZW |
13601 | constraint (inst.operands[0].writeback, |
13602 | _("push/pop do not support {reglist}^")); | |
e2b0ab59 | 13603 | constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, |
c19d1205 | 13604 | _("expression too complex")); |
b99bd4ef | 13605 | |
e9f89963 | 13606 | mask = inst.operands[0].imm; |
d3bfe16e | 13607 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 13608 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e | 13609 | else if (inst.size_req != 4 |
c6025a80 | 13610 | && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push |
d3bfe16e | 13611 | ? REG_LR : REG_PC))) |
b99bd4ef | 13612 | { |
c19d1205 ZW |
13613 | inst.instruction = THUMB_OP16 (inst.instruction); |
13614 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 13615 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
13616 | } |
13617 | else if (unified_syntax) | |
13618 | { | |
3c707909 | 13619 | inst.instruction = THUMB_OP32 (inst.instruction); |
4b5a202f AV |
13620 | encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE); |
13621 | } | |
13622 | else | |
13623 | { | |
13624 | inst.error = _("invalid register list to push/pop instruction"); | |
13625 | return; | |
c19d1205 | 13626 | } |
4b5a202f AV |
13627 | } |
13628 | ||
13629 | static void | |
13630 | do_t_clrm (void) | |
13631 | { | |
13632 | if (unified_syntax) | |
13633 | encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE); | |
c19d1205 ZW |
13634 | else |
13635 | { | |
13636 | inst.error = _("invalid register list to push/pop instruction"); | |
13637 | return; | |
13638 | } | |
c19d1205 | 13639 | } |
b99bd4ef | 13640 | |
efd6b359 AV |
13641 | static void |
13642 | do_t_vscclrm (void) | |
13643 | { | |
13644 | if (inst.operands[0].issingle) | |
13645 | { | |
13646 | inst.instruction |= (inst.operands[0].reg & 0x1) << 22; | |
13647 | inst.instruction |= (inst.operands[0].reg & 0x1e) << 11; | |
13648 | inst.instruction |= inst.operands[0].imm; | |
13649 | } | |
13650 | else | |
13651 | { | |
13652 | inst.instruction |= (inst.operands[0].reg & 0x10) << 18; | |
13653 | inst.instruction |= (inst.operands[0].reg & 0xf) << 12; | |
13654 | inst.instruction |= 1 << 8; | |
13655 | inst.instruction |= inst.operands[0].imm << 1; | |
13656 | } | |
13657 | } | |
13658 | ||
c19d1205 ZW |
13659 | static void |
13660 | do_t_rbit (void) | |
13661 | { | |
fdfde340 JM |
13662 | unsigned Rd, Rm; |
13663 | ||
13664 | Rd = inst.operands[0].reg; | |
13665 | Rm = inst.operands[1].reg; | |
13666 | ||
13667 | reject_bad_reg (Rd); | |
13668 | reject_bad_reg (Rm); | |
13669 | ||
13670 | inst.instruction |= Rd << 8; | |
13671 | inst.instruction |= Rm << 16; | |
13672 | inst.instruction |= Rm; | |
c19d1205 | 13673 | } |
b99bd4ef | 13674 | |
c19d1205 ZW |
13675 | static void |
13676 | do_t_rev (void) | |
13677 | { | |
fdfde340 JM |
13678 | unsigned Rd, Rm; |
13679 | ||
13680 | Rd = inst.operands[0].reg; | |
13681 | Rm = inst.operands[1].reg; | |
13682 | ||
13683 | reject_bad_reg (Rd); | |
13684 | reject_bad_reg (Rm); | |
13685 | ||
13686 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
13687 | && inst.size_req != 4) |
13688 | { | |
13689 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
13690 | inst.instruction |= Rd; |
13691 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
13692 | } |
13693 | else if (unified_syntax) | |
13694 | { | |
13695 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
13696 | inst.instruction |= Rd << 8; |
13697 | inst.instruction |= Rm << 16; | |
13698 | inst.instruction |= Rm; | |
c19d1205 ZW |
13699 | } |
13700 | else | |
13701 | inst.error = BAD_HIREG; | |
13702 | } | |
b99bd4ef | 13703 | |
1c444d06 JM |
13704 | static void |
13705 | do_t_rrx (void) | |
13706 | { | |
13707 | unsigned Rd, Rm; | |
13708 | ||
13709 | Rd = inst.operands[0].reg; | |
13710 | Rm = inst.operands[1].reg; | |
13711 | ||
fdfde340 JM |
13712 | reject_bad_reg (Rd); |
13713 | reject_bad_reg (Rm); | |
c921be7d | 13714 | |
1c444d06 JM |
13715 | inst.instruction |= Rd << 8; |
13716 | inst.instruction |= Rm; | |
13717 | } | |
13718 | ||
c19d1205 ZW |
13719 | static void |
13720 | do_t_rsb (void) | |
13721 | { | |
fdfde340 | 13722 | unsigned Rd, Rs; |
b99bd4ef | 13723 | |
c19d1205 ZW |
13724 | Rd = inst.operands[0].reg; |
13725 | Rs = (inst.operands[1].present | |
13726 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
13727 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 13728 | |
fdfde340 JM |
13729 | reject_bad_reg (Rd); |
13730 | reject_bad_reg (Rs); | |
13731 | if (inst.operands[2].isreg) | |
13732 | reject_bad_reg (inst.operands[2].reg); | |
13733 | ||
c19d1205 ZW |
13734 | inst.instruction |= Rd << 8; |
13735 | inst.instruction |= Rs << 16; | |
13736 | if (!inst.operands[2].isreg) | |
13737 | { | |
026d3abb PB |
13738 | bfd_boolean narrow; |
13739 | ||
13740 | if ((inst.instruction & 0x00100000) != 0) | |
5ee91343 | 13741 | narrow = !in_pred_block (); |
026d3abb | 13742 | else |
5ee91343 | 13743 | narrow = in_pred_block (); |
026d3abb PB |
13744 | |
13745 | if (Rd > 7 || Rs > 7) | |
13746 | narrow = FALSE; | |
13747 | ||
13748 | if (inst.size_req == 4 || !unified_syntax) | |
13749 | narrow = FALSE; | |
13750 | ||
e2b0ab59 AV |
13751 | if (inst.relocs[0].exp.X_op != O_constant |
13752 | || inst.relocs[0].exp.X_add_number != 0) | |
026d3abb PB |
13753 | narrow = FALSE; |
13754 | ||
13755 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 13756 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
13757 | if (narrow) |
13758 | { | |
e2b0ab59 | 13759 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
026d3abb PB |
13760 | inst.instruction = THUMB_OP16 (T_MNEM_negs); |
13761 | inst.instruction |= Rs << 3; | |
13762 | inst.instruction |= Rd; | |
13763 | } | |
13764 | else | |
13765 | { | |
13766 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
e2b0ab59 | 13767 | inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE; |
026d3abb | 13768 | } |
c19d1205 ZW |
13769 | } |
13770 | else | |
13771 | encode_thumb32_shifted_operand (2); | |
13772 | } | |
b99bd4ef | 13773 | |
c19d1205 ZW |
13774 | static void |
13775 | do_t_setend (void) | |
13776 | { | |
12e37cbc MGD |
13777 | if (warn_on_deprecated |
13778 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 13779 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 13780 | |
5ee91343 | 13781 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
c19d1205 ZW |
13782 | if (inst.operands[0].imm) |
13783 | inst.instruction |= 0x8; | |
13784 | } | |
b99bd4ef | 13785 | |
c19d1205 ZW |
13786 | static void |
13787 | do_t_shift (void) | |
13788 | { | |
13789 | if (!inst.operands[1].present) | |
13790 | inst.operands[1].reg = inst.operands[0].reg; | |
13791 | ||
13792 | if (unified_syntax) | |
13793 | { | |
3d388997 PB |
13794 | bfd_boolean narrow; |
13795 | int shift_kind; | |
13796 | ||
13797 | switch (inst.instruction) | |
13798 | { | |
13799 | case T_MNEM_asr: | |
13800 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
13801 | case T_MNEM_lsl: | |
13802 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
13803 | case T_MNEM_lsr: | |
13804 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
13805 | case T_MNEM_ror: | |
13806 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
13807 | default: abort (); | |
13808 | } | |
13809 | ||
13810 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
5ee91343 | 13811 | narrow = !in_pred_block (); |
3d388997 | 13812 | else |
5ee91343 | 13813 | narrow = in_pred_block (); |
3d388997 PB |
13814 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
13815 | narrow = FALSE; | |
13816 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
13817 | narrow = FALSE; | |
13818 | if (inst.operands[2].isreg | |
13819 | && (inst.operands[1].reg != inst.operands[0].reg | |
13820 | || inst.operands[2].reg > 7)) | |
13821 | narrow = FALSE; | |
13822 | if (inst.size_req == 4) | |
13823 | narrow = FALSE; | |
13824 | ||
fdfde340 JM |
13825 | reject_bad_reg (inst.operands[0].reg); |
13826 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 13827 | |
3d388997 | 13828 | if (!narrow) |
c19d1205 ZW |
13829 | { |
13830 | if (inst.operands[2].isreg) | |
b99bd4ef | 13831 | { |
fdfde340 | 13832 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
13833 | inst.instruction = THUMB_OP32 (inst.instruction); |
13834 | inst.instruction |= inst.operands[0].reg << 8; | |
13835 | inst.instruction |= inst.operands[1].reg << 16; | |
13836 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
13837 | |
13838 | /* PR 12854: Error on extraneous shifts. */ | |
13839 | constraint (inst.operands[2].shifted, | |
13840 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
13841 | } |
13842 | else | |
13843 | { | |
13844 | inst.operands[1].shifted = 1; | |
3d388997 | 13845 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
13846 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
13847 | ? T_MNEM_movs : T_MNEM_mov); | |
13848 | inst.instruction |= inst.operands[0].reg << 8; | |
13849 | encode_thumb32_shifted_operand (1); | |
13850 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
e2b0ab59 | 13851 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
b99bd4ef NC |
13852 | } |
13853 | } | |
13854 | else | |
13855 | { | |
c19d1205 | 13856 | if (inst.operands[2].isreg) |
b99bd4ef | 13857 | { |
3d388997 | 13858 | switch (shift_kind) |
b99bd4ef | 13859 | { |
3d388997 PB |
13860 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
13861 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
13862 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
13863 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 13864 | default: abort (); |
b99bd4ef | 13865 | } |
5f4273c7 | 13866 | |
c19d1205 ZW |
13867 | inst.instruction |= inst.operands[0].reg; |
13868 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
13869 | |
13870 | /* PR 12854: Error on extraneous shifts. */ | |
13871 | constraint (inst.operands[2].shifted, | |
13872 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
13873 | } |
13874 | else | |
13875 | { | |
3d388997 | 13876 | switch (shift_kind) |
b99bd4ef | 13877 | { |
3d388997 PB |
13878 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
13879 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
13880 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 13881 | default: abort (); |
b99bd4ef | 13882 | } |
e2b0ab59 | 13883 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
c19d1205 ZW |
13884 | inst.instruction |= inst.operands[0].reg; |
13885 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
13886 | } |
13887 | } | |
c19d1205 ZW |
13888 | } |
13889 | else | |
13890 | { | |
13891 | constraint (inst.operands[0].reg > 7 | |
13892 | || inst.operands[1].reg > 7, BAD_HIREG); | |
13893 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 13894 | |
c19d1205 ZW |
13895 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
13896 | { | |
13897 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
13898 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13899 | _("source1 and dest must be same register")); | |
b99bd4ef | 13900 | |
c19d1205 ZW |
13901 | switch (inst.instruction) |
13902 | { | |
13903 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
13904 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
13905 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
13906 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
13907 | default: abort (); | |
13908 | } | |
5f4273c7 | 13909 | |
c19d1205 ZW |
13910 | inst.instruction |= inst.operands[0].reg; |
13911 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
13912 | |
13913 | /* PR 12854: Error on extraneous shifts. */ | |
13914 | constraint (inst.operands[2].shifted, | |
13915 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
13916 | } |
13917 | else | |
b99bd4ef | 13918 | { |
c19d1205 ZW |
13919 | switch (inst.instruction) |
13920 | { | |
13921 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
13922 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
13923 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
13924 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
13925 | default: abort (); | |
13926 | } | |
e2b0ab59 | 13927 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT; |
c19d1205 ZW |
13928 | inst.instruction |= inst.operands[0].reg; |
13929 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
13930 | } |
13931 | } | |
b99bd4ef NC |
13932 | } |
13933 | ||
13934 | static void | |
c19d1205 | 13935 | do_t_simd (void) |
b99bd4ef | 13936 | { |
fdfde340 JM |
13937 | unsigned Rd, Rn, Rm; |
13938 | ||
13939 | Rd = inst.operands[0].reg; | |
13940 | Rn = inst.operands[1].reg; | |
13941 | Rm = inst.operands[2].reg; | |
13942 | ||
13943 | reject_bad_reg (Rd); | |
13944 | reject_bad_reg (Rn); | |
13945 | reject_bad_reg (Rm); | |
13946 | ||
13947 | inst.instruction |= Rd << 8; | |
13948 | inst.instruction |= Rn << 16; | |
13949 | inst.instruction |= Rm; | |
c19d1205 | 13950 | } |
b99bd4ef | 13951 | |
03ee1b7f NC |
13952 | static void |
13953 | do_t_simd2 (void) | |
13954 | { | |
13955 | unsigned Rd, Rn, Rm; | |
13956 | ||
13957 | Rd = inst.operands[0].reg; | |
13958 | Rm = inst.operands[1].reg; | |
13959 | Rn = inst.operands[2].reg; | |
13960 | ||
13961 | reject_bad_reg (Rd); | |
13962 | reject_bad_reg (Rn); | |
13963 | reject_bad_reg (Rm); | |
13964 | ||
13965 | inst.instruction |= Rd << 8; | |
13966 | inst.instruction |= Rn << 16; | |
13967 | inst.instruction |= Rm; | |
13968 | } | |
13969 | ||
c19d1205 | 13970 | static void |
3eb17e6b | 13971 | do_t_smc (void) |
c19d1205 | 13972 | { |
e2b0ab59 | 13973 | unsigned int value = inst.relocs[0].exp.X_add_number; |
f4c65163 MGD |
13974 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
13975 | _("SMC is not permitted on this architecture")); | |
e2b0ab59 | 13976 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 | 13977 | _("expression too complex")); |
ba85f98c BW |
13978 | constraint (value > 0xf, _("immediate too large (bigger than 0xF)")); |
13979 | ||
e2b0ab59 | 13980 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
c19d1205 | 13981 | inst.instruction |= (value & 0x000f) << 16; |
ba85f98c | 13982 | |
24382199 | 13983 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
5ee91343 | 13984 | set_pred_insn_type_last (); |
c19d1205 | 13985 | } |
b99bd4ef | 13986 | |
90ec0d68 MGD |
13987 | static void |
13988 | do_t_hvc (void) | |
13989 | { | |
e2b0ab59 | 13990 | unsigned int value = inst.relocs[0].exp.X_add_number; |
90ec0d68 | 13991 | |
e2b0ab59 | 13992 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
90ec0d68 MGD |
13993 | inst.instruction |= (value & 0x0fff); |
13994 | inst.instruction |= (value & 0xf000) << 4; | |
13995 | } | |
13996 | ||
c19d1205 | 13997 | static void |
3a21c15a | 13998 | do_t_ssat_usat (int bias) |
c19d1205 | 13999 | { |
fdfde340 JM |
14000 | unsigned Rd, Rn; |
14001 | ||
14002 | Rd = inst.operands[0].reg; | |
14003 | Rn = inst.operands[2].reg; | |
14004 | ||
14005 | reject_bad_reg (Rd); | |
14006 | reject_bad_reg (Rn); | |
14007 | ||
14008 | inst.instruction |= Rd << 8; | |
3a21c15a | 14009 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 14010 | inst.instruction |= Rn << 16; |
b99bd4ef | 14011 | |
c19d1205 | 14012 | if (inst.operands[3].present) |
b99bd4ef | 14013 | { |
e2b0ab59 | 14014 | offsetT shift_amount = inst.relocs[0].exp.X_add_number; |
3a21c15a | 14015 | |
e2b0ab59 | 14016 | inst.relocs[0].type = BFD_RELOC_UNUSED; |
3a21c15a | 14017 | |
e2b0ab59 | 14018 | constraint (inst.relocs[0].exp.X_op != O_constant, |
c19d1205 | 14019 | _("expression too complex")); |
b99bd4ef | 14020 | |
3a21c15a | 14021 | if (shift_amount != 0) |
6189168b | 14022 | { |
3a21c15a NC |
14023 | constraint (shift_amount > 31, |
14024 | _("shift expression is too large")); | |
14025 | ||
c19d1205 | 14026 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
14027 | inst.instruction |= 0x00200000; /* sh bit. */ |
14028 | ||
14029 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
14030 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
14031 | } |
14032 | } | |
b99bd4ef | 14033 | } |
c921be7d | 14034 | |
3a21c15a NC |
14035 | static void |
14036 | do_t_ssat (void) | |
14037 | { | |
14038 | do_t_ssat_usat (1); | |
14039 | } | |
b99bd4ef | 14040 | |
0dd132b6 | 14041 | static void |
c19d1205 | 14042 | do_t_ssat16 (void) |
0dd132b6 | 14043 | { |
fdfde340 JM |
14044 | unsigned Rd, Rn; |
14045 | ||
14046 | Rd = inst.operands[0].reg; | |
14047 | Rn = inst.operands[2].reg; | |
14048 | ||
14049 | reject_bad_reg (Rd); | |
14050 | reject_bad_reg (Rn); | |
14051 | ||
14052 | inst.instruction |= Rd << 8; | |
c19d1205 | 14053 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 14054 | inst.instruction |= Rn << 16; |
c19d1205 | 14055 | } |
0dd132b6 | 14056 | |
c19d1205 ZW |
14057 | static void |
14058 | do_t_strex (void) | |
14059 | { | |
14060 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
14061 | || inst.operands[2].postind || inst.operands[2].writeback | |
14062 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
14063 | || inst.operands[2].negative, | |
01cfc07f | 14064 | BAD_ADDR_MODE); |
0dd132b6 | 14065 | |
5be8be5d DG |
14066 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
14067 | ||
c19d1205 ZW |
14068 | inst.instruction |= inst.operands[0].reg << 8; |
14069 | inst.instruction |= inst.operands[1].reg << 12; | |
14070 | inst.instruction |= inst.operands[2].reg << 16; | |
e2b0ab59 | 14071 | inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8; |
0dd132b6 NC |
14072 | } |
14073 | ||
b99bd4ef | 14074 | static void |
c19d1205 | 14075 | do_t_strexd (void) |
b99bd4ef | 14076 | { |
c19d1205 ZW |
14077 | if (!inst.operands[2].present) |
14078 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 14079 | |
c19d1205 ZW |
14080 | constraint (inst.operands[0].reg == inst.operands[1].reg |
14081 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 14082 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 14083 | BAD_OVERLAP); |
b99bd4ef | 14084 | |
c19d1205 ZW |
14085 | inst.instruction |= inst.operands[0].reg; |
14086 | inst.instruction |= inst.operands[1].reg << 12; | |
14087 | inst.instruction |= inst.operands[2].reg << 8; | |
14088 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
14089 | } |
14090 | ||
14091 | static void | |
c19d1205 | 14092 | do_t_sxtah (void) |
b99bd4ef | 14093 | { |
fdfde340 JM |
14094 | unsigned Rd, Rn, Rm; |
14095 | ||
14096 | Rd = inst.operands[0].reg; | |
14097 | Rn = inst.operands[1].reg; | |
14098 | Rm = inst.operands[2].reg; | |
14099 | ||
14100 | reject_bad_reg (Rd); | |
14101 | reject_bad_reg (Rn); | |
14102 | reject_bad_reg (Rm); | |
14103 | ||
14104 | inst.instruction |= Rd << 8; | |
14105 | inst.instruction |= Rn << 16; | |
14106 | inst.instruction |= Rm; | |
c19d1205 ZW |
14107 | inst.instruction |= inst.operands[3].imm << 4; |
14108 | } | |
b99bd4ef | 14109 | |
c19d1205 ZW |
14110 | static void |
14111 | do_t_sxth (void) | |
14112 | { | |
fdfde340 JM |
14113 | unsigned Rd, Rm; |
14114 | ||
14115 | Rd = inst.operands[0].reg; | |
14116 | Rm = inst.operands[1].reg; | |
14117 | ||
14118 | reject_bad_reg (Rd); | |
14119 | reject_bad_reg (Rm); | |
c921be7d NC |
14120 | |
14121 | if (inst.instruction <= 0xffff | |
14122 | && inst.size_req != 4 | |
fdfde340 | 14123 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 14124 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 14125 | { |
c19d1205 | 14126 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
14127 | inst.instruction |= Rd; |
14128 | inst.instruction |= Rm << 3; | |
b99bd4ef | 14129 | } |
c19d1205 | 14130 | else if (unified_syntax) |
b99bd4ef | 14131 | { |
c19d1205 ZW |
14132 | if (inst.instruction <= 0xffff) |
14133 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
14134 | inst.instruction |= Rd << 8; |
14135 | inst.instruction |= Rm; | |
c19d1205 | 14136 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 14137 | } |
c19d1205 | 14138 | else |
b99bd4ef | 14139 | { |
c19d1205 ZW |
14140 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
14141 | _("Thumb encoding does not support rotation")); | |
14142 | constraint (1, BAD_HIREG); | |
b99bd4ef | 14143 | } |
c19d1205 | 14144 | } |
b99bd4ef | 14145 | |
c19d1205 ZW |
14146 | static void |
14147 | do_t_swi (void) | |
14148 | { | |
e2b0ab59 | 14149 | inst.relocs[0].type = BFD_RELOC_ARM_SWI; |
c19d1205 | 14150 | } |
b99bd4ef | 14151 | |
92e90b6e PB |
14152 | static void |
14153 | do_t_tb (void) | |
14154 | { | |
fdfde340 | 14155 | unsigned Rn, Rm; |
92e90b6e PB |
14156 | int half; |
14157 | ||
14158 | half = (inst.instruction & 0x10) != 0; | |
5ee91343 | 14159 | set_pred_insn_type_last (); |
dfa9f0d5 PB |
14160 | constraint (inst.operands[0].immisreg, |
14161 | _("instruction requires register index")); | |
fdfde340 JM |
14162 | |
14163 | Rn = inst.operands[0].reg; | |
14164 | Rm = inst.operands[0].imm; | |
c921be7d | 14165 | |
5c8ed6a4 JW |
14166 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) |
14167 | constraint (Rn == REG_SP, BAD_SP); | |
fdfde340 JM |
14168 | reject_bad_reg (Rm); |
14169 | ||
92e90b6e PB |
14170 | constraint (!half && inst.operands[0].shifted, |
14171 | _("instruction does not allow shifted index")); | |
fdfde340 | 14172 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
14173 | } |
14174 | ||
74db7efb NC |
14175 | static void |
14176 | do_t_udf (void) | |
14177 | { | |
14178 | if (!inst.operands[0].present) | |
14179 | inst.operands[0].imm = 0; | |
14180 | ||
14181 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
14182 | { | |
14183 | constraint (inst.size_req == 2, | |
14184 | _("immediate value out of range")); | |
14185 | inst.instruction = THUMB_OP32 (inst.instruction); | |
14186 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
14187 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
14188 | } | |
14189 | else | |
14190 | { | |
14191 | inst.instruction = THUMB_OP16 (inst.instruction); | |
14192 | inst.instruction |= inst.operands[0].imm; | |
14193 | } | |
14194 | ||
5ee91343 | 14195 | set_pred_insn_type (NEUTRAL_IT_INSN); |
74db7efb NC |
14196 | } |
14197 | ||
14198 | ||
c19d1205 ZW |
14199 | static void |
14200 | do_t_usat (void) | |
14201 | { | |
3a21c15a | 14202 | do_t_ssat_usat (0); |
b99bd4ef NC |
14203 | } |
14204 | ||
14205 | static void | |
c19d1205 | 14206 | do_t_usat16 (void) |
b99bd4ef | 14207 | { |
fdfde340 JM |
14208 | unsigned Rd, Rn; |
14209 | ||
14210 | Rd = inst.operands[0].reg; | |
14211 | Rn = inst.operands[2].reg; | |
14212 | ||
14213 | reject_bad_reg (Rd); | |
14214 | reject_bad_reg (Rn); | |
14215 | ||
14216 | inst.instruction |= Rd << 8; | |
c19d1205 | 14217 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 14218 | inst.instruction |= Rn << 16; |
b99bd4ef | 14219 | } |
c19d1205 | 14220 | |
e12437dc AV |
14221 | /* Checking the range of the branch offset (VAL) with NBITS bits |
14222 | and IS_SIGNED signedness. Also checks the LSB to be 0. */ | |
14223 | static int | |
14224 | v8_1_branch_value_check (int val, int nbits, int is_signed) | |
14225 | { | |
14226 | gas_assert (nbits > 0 && nbits <= 32); | |
14227 | if (is_signed) | |
14228 | { | |
14229 | int cmp = (1 << (nbits - 1)); | |
14230 | if ((val < -cmp) || (val >= cmp) || (val & 0x01)) | |
14231 | return FAIL; | |
14232 | } | |
14233 | else | |
14234 | { | |
14235 | if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1)) | |
14236 | return FAIL; | |
14237 | } | |
14238 | return SUCCESS; | |
14239 | } | |
14240 | ||
4389b29a AV |
14241 | /* For branches in Armv8.1-M Mainline. */ |
14242 | static void | |
14243 | do_t_branch_future (void) | |
14244 | { | |
14245 | unsigned long insn = inst.instruction; | |
14246 | ||
14247 | inst.instruction = THUMB_OP32 (inst.instruction); | |
14248 | if (inst.operands[0].hasreloc == 0) | |
14249 | { | |
14250 | if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL) | |
14251 | as_bad (BAD_BRANCH_OFF); | |
14252 | ||
14253 | inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23; | |
14254 | } | |
14255 | else | |
14256 | { | |
14257 | inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5; | |
14258 | inst.relocs[0].pc_rel = 1; | |
14259 | } | |
14260 | ||
14261 | switch (insn) | |
14262 | { | |
14263 | case T_MNEM_bf: | |
14264 | if (inst.operands[1].hasreloc == 0) | |
14265 | { | |
14266 | int val = inst.operands[1].imm; | |
14267 | if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL) | |
14268 | as_bad (BAD_BRANCH_OFF); | |
14269 | ||
14270 | int immA = (val & 0x0001f000) >> 12; | |
14271 | int immB = (val & 0x00000ffc) >> 2; | |
14272 | int immC = (val & 0x00000002) >> 1; | |
14273 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); | |
14274 | } | |
14275 | else | |
14276 | { | |
14277 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17; | |
14278 | inst.relocs[1].pc_rel = 1; | |
14279 | } | |
14280 | break; | |
14281 | ||
65d1bc05 AV |
14282 | case T_MNEM_bfl: |
14283 | if (inst.operands[1].hasreloc == 0) | |
14284 | { | |
14285 | int val = inst.operands[1].imm; | |
14286 | if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL) | |
14287 | as_bad (BAD_BRANCH_OFF); | |
14288 | ||
14289 | int immA = (val & 0x0007f000) >> 12; | |
14290 | int immB = (val & 0x00000ffc) >> 2; | |
14291 | int immC = (val & 0x00000002) >> 1; | |
14292 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); | |
14293 | } | |
14294 | else | |
14295 | { | |
14296 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19; | |
14297 | inst.relocs[1].pc_rel = 1; | |
14298 | } | |
14299 | break; | |
14300 | ||
f6b2b12d AV |
14301 | case T_MNEM_bfcsel: |
14302 | /* Operand 1. */ | |
14303 | if (inst.operands[1].hasreloc == 0) | |
14304 | { | |
14305 | int val = inst.operands[1].imm; | |
14306 | int immA = (val & 0x00001000) >> 12; | |
14307 | int immB = (val & 0x00000ffc) >> 2; | |
14308 | int immC = (val & 0x00000002) >> 1; | |
14309 | inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); | |
14310 | } | |
14311 | else | |
14312 | { | |
14313 | inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13; | |
14314 | inst.relocs[1].pc_rel = 1; | |
14315 | } | |
14316 | ||
14317 | /* Operand 2. */ | |
14318 | if (inst.operands[2].hasreloc == 0) | |
14319 | { | |
14320 | constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS); | |
14321 | int val2 = inst.operands[2].imm; | |
14322 | int val0 = inst.operands[0].imm & 0x1f; | |
14323 | int diff = val2 - val0; | |
14324 | if (diff == 4) | |
14325 | inst.instruction |= 1 << 17; /* T bit. */ | |
14326 | else if (diff != 2) | |
14327 | as_bad (_("out of range label-relative fixup value")); | |
14328 | } | |
14329 | else | |
14330 | { | |
14331 | constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS); | |
14332 | inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL; | |
14333 | inst.relocs[2].pc_rel = 1; | |
14334 | } | |
14335 | ||
14336 | /* Operand 3. */ | |
14337 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
14338 | inst.instruction |= (inst.operands[3].imm & 0xf) << 18; | |
14339 | break; | |
14340 | ||
f1c7f421 AV |
14341 | case T_MNEM_bfx: |
14342 | case T_MNEM_bflx: | |
14343 | inst.instruction |= inst.operands[1].reg << 16; | |
14344 | break; | |
14345 | ||
4389b29a AV |
14346 | default: abort (); |
14347 | } | |
14348 | } | |
14349 | ||
60f993ce AV |
14350 | /* Helper function for do_t_loloop to handle relocations. */ |
14351 | static void | |
14352 | v8_1_loop_reloc (int is_le) | |
14353 | { | |
14354 | if (inst.relocs[0].exp.X_op == O_constant) | |
14355 | { | |
14356 | int value = inst.relocs[0].exp.X_add_number; | |
14357 | value = (is_le) ? -value : value; | |
14358 | ||
14359 | if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) | |
14360 | as_bad (BAD_BRANCH_OFF); | |
14361 | ||
14362 | int imml, immh; | |
14363 | ||
14364 | immh = (value & 0x00000ffc) >> 2; | |
14365 | imml = (value & 0x00000002) >> 1; | |
14366 | ||
14367 | inst.instruction |= (imml << 11) | (immh << 1); | |
14368 | } | |
14369 | else | |
14370 | { | |
14371 | inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12; | |
14372 | inst.relocs[0].pc_rel = 1; | |
14373 | } | |
14374 | } | |
14375 | ||
08132bdd SP |
14376 | /* For shifts with four operands in MVE. */ |
14377 | static void | |
14378 | do_mve_scalar_shift1 (void) | |
14379 | { | |
14380 | unsigned int value = inst.operands[2].imm; | |
14381 | ||
14382 | inst.instruction |= inst.operands[0].reg << 16; | |
14383 | inst.instruction |= inst.operands[1].reg << 8; | |
14384 | ||
14385 | /* Setting the bit for saturation. */ | |
14386 | inst.instruction |= ((value == 64) ? 0: 1) << 7; | |
14387 | ||
14388 | /* Assuming Rm is already checked not to be 11x1. */ | |
14389 | constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP); | |
14390 | constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP); | |
14391 | inst.instruction |= inst.operands[3].reg << 12; | |
14392 | } | |
14393 | ||
23d00a41 SD |
14394 | /* For shifts in MVE. */ |
14395 | static void | |
14396 | do_mve_scalar_shift (void) | |
14397 | { | |
14398 | if (!inst.operands[2].present) | |
14399 | { | |
14400 | inst.operands[2] = inst.operands[1]; | |
14401 | inst.operands[1].reg = 0xf; | |
14402 | } | |
14403 | ||
14404 | inst.instruction |= inst.operands[0].reg << 16; | |
14405 | inst.instruction |= inst.operands[1].reg << 8; | |
14406 | ||
14407 | if (inst.operands[2].isreg) | |
14408 | { | |
14409 | /* Assuming Rm is already checked not to be 11x1. */ | |
14410 | constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP); | |
14411 | constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP); | |
14412 | inst.instruction |= inst.operands[2].reg << 12; | |
14413 | } | |
14414 | else | |
14415 | { | |
14416 | /* Assuming imm is already checked as [1,32]. */ | |
14417 | unsigned int value = inst.operands[2].imm; | |
14418 | inst.instruction |= (value & 0x1c) << 10; | |
14419 | inst.instruction |= (value & 0x03) << 6; | |
14420 | /* Change last 4 bits from 0xd to 0xf. */ | |
14421 | inst.instruction |= 0x2; | |
14422 | } | |
14423 | } | |
14424 | ||
a302e574 AV |
14425 | /* MVE instruction encoder helpers. */ |
14426 | #define M_MNEM_vabav 0xee800f01 | |
14427 | #define M_MNEM_vmladav 0xeef00e00 | |
14428 | #define M_MNEM_vmladava 0xeef00e20 | |
14429 | #define M_MNEM_vmladavx 0xeef01e00 | |
14430 | #define M_MNEM_vmladavax 0xeef01e20 | |
14431 | #define M_MNEM_vmlsdav 0xeef00e01 | |
14432 | #define M_MNEM_vmlsdava 0xeef00e21 | |
14433 | #define M_MNEM_vmlsdavx 0xeef01e01 | |
14434 | #define M_MNEM_vmlsdavax 0xeef01e21 | |
886e1c73 AV |
14435 | #define M_MNEM_vmullt 0xee011e00 |
14436 | #define M_MNEM_vmullb 0xee010e00 | |
efd0b310 | 14437 | #define M_MNEM_vctp 0xf000e801 |
35c228db AV |
14438 | #define M_MNEM_vst20 0xfc801e00 |
14439 | #define M_MNEM_vst21 0xfc801e20 | |
14440 | #define M_MNEM_vst40 0xfc801e01 | |
14441 | #define M_MNEM_vst41 0xfc801e21 | |
14442 | #define M_MNEM_vst42 0xfc801e41 | |
14443 | #define M_MNEM_vst43 0xfc801e61 | |
14444 | #define M_MNEM_vld20 0xfc901e00 | |
14445 | #define M_MNEM_vld21 0xfc901e20 | |
14446 | #define M_MNEM_vld40 0xfc901e01 | |
14447 | #define M_MNEM_vld41 0xfc901e21 | |
14448 | #define M_MNEM_vld42 0xfc901e41 | |
14449 | #define M_MNEM_vld43 0xfc901e61 | |
f5f10c66 AV |
14450 | #define M_MNEM_vstrb 0xec000e00 |
14451 | #define M_MNEM_vstrh 0xec000e10 | |
14452 | #define M_MNEM_vstrw 0xec000e40 | |
14453 | #define M_MNEM_vstrd 0xec000e50 | |
14454 | #define M_MNEM_vldrb 0xec100e00 | |
14455 | #define M_MNEM_vldrh 0xec100e10 | |
14456 | #define M_MNEM_vldrw 0xec100e40 | |
14457 | #define M_MNEM_vldrd 0xec100e50 | |
57785aa2 AV |
14458 | #define M_MNEM_vmovlt 0xeea01f40 |
14459 | #define M_MNEM_vmovlb 0xeea00f40 | |
14460 | #define M_MNEM_vmovnt 0xfe311e81 | |
14461 | #define M_MNEM_vmovnb 0xfe310e81 | |
c2dafc2a AV |
14462 | #define M_MNEM_vadc 0xee300f00 |
14463 | #define M_MNEM_vadci 0xee301f00 | |
14464 | #define M_MNEM_vbrsr 0xfe011e60 | |
26c1e780 AV |
14465 | #define M_MNEM_vaddlv 0xee890f00 |
14466 | #define M_MNEM_vaddlva 0xee890f20 | |
14467 | #define M_MNEM_vaddv 0xeef10f00 | |
14468 | #define M_MNEM_vaddva 0xeef10f20 | |
b409bdb6 AV |
14469 | #define M_MNEM_vddup 0xee011f6e |
14470 | #define M_MNEM_vdwdup 0xee011f60 | |
14471 | #define M_MNEM_vidup 0xee010f6e | |
14472 | #define M_MNEM_viwdup 0xee010f60 | |
13ccd4c0 AV |
14473 | #define M_MNEM_vmaxv 0xeee20f00 |
14474 | #define M_MNEM_vmaxav 0xeee00f00 | |
14475 | #define M_MNEM_vminv 0xeee20f80 | |
14476 | #define M_MNEM_vminav 0xeee00f80 | |
93925576 AV |
14477 | #define M_MNEM_vmlaldav 0xee800e00 |
14478 | #define M_MNEM_vmlaldava 0xee800e20 | |
14479 | #define M_MNEM_vmlaldavx 0xee801e00 | |
14480 | #define M_MNEM_vmlaldavax 0xee801e20 | |
14481 | #define M_MNEM_vmlsldav 0xee800e01 | |
14482 | #define M_MNEM_vmlsldava 0xee800e21 | |
14483 | #define M_MNEM_vmlsldavx 0xee801e01 | |
14484 | #define M_MNEM_vmlsldavax 0xee801e21 | |
14485 | #define M_MNEM_vrmlaldavhx 0xee801f00 | |
14486 | #define M_MNEM_vrmlaldavhax 0xee801f20 | |
14487 | #define M_MNEM_vrmlsldavh 0xfe800e01 | |
14488 | #define M_MNEM_vrmlsldavha 0xfe800e21 | |
14489 | #define M_MNEM_vrmlsldavhx 0xfe801e01 | |
14490 | #define M_MNEM_vrmlsldavhax 0xfe801e21 | |
1be7aba3 AV |
14491 | #define M_MNEM_vqmovnt 0xee331e01 |
14492 | #define M_MNEM_vqmovnb 0xee330e01 | |
14493 | #define M_MNEM_vqmovunt 0xee311e81 | |
14494 | #define M_MNEM_vqmovunb 0xee310e81 | |
4aa88b50 AV |
14495 | #define M_MNEM_vshrnt 0xee801fc1 |
14496 | #define M_MNEM_vshrnb 0xee800fc1 | |
14497 | #define M_MNEM_vrshrnt 0xfe801fc1 | |
14498 | #define M_MNEM_vqshrnt 0xee801f40 | |
14499 | #define M_MNEM_vqshrnb 0xee800f40 | |
14500 | #define M_MNEM_vqshrunt 0xee801fc0 | |
14501 | #define M_MNEM_vqshrunb 0xee800fc0 | |
14502 | #define M_MNEM_vrshrnb 0xfe800fc1 | |
14503 | #define M_MNEM_vqrshrnt 0xee801f41 | |
14504 | #define M_MNEM_vqrshrnb 0xee800f41 | |
14505 | #define M_MNEM_vqrshrunt 0xfe801fc0 | |
14506 | #define M_MNEM_vqrshrunb 0xfe800fc0 | |
a302e574 | 14507 | |
5287ad62 | 14508 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 14509 | |
5287ad62 | 14510 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 14511 | |
5287ad62 JB |
14512 | /* An "invalid" code for the following tables. */ |
14513 | #define N_INV -1u | |
14514 | ||
14515 | struct neon_tab_entry | |
b99bd4ef | 14516 | { |
5287ad62 JB |
14517 | unsigned integer; |
14518 | unsigned float_or_poly; | |
14519 | unsigned scalar_or_imm; | |
14520 | }; | |
5f4273c7 | 14521 | |
5287ad62 JB |
14522 | /* Map overloaded Neon opcodes to their respective encodings. */ |
14523 | #define NEON_ENC_TAB \ | |
14524 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
5ee91343 | 14525 | X(vabdl, 0x0800700, N_INV, N_INV), \ |
5287ad62 JB |
14526 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ |
14527 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
14528 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
14529 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
14530 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
14531 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
5ee91343 | 14532 | X(vaddl, 0x0800000, N_INV, N_INV), \ |
5287ad62 | 14533 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ |
5ee91343 | 14534 | X(vsubl, 0x0800200, N_INV, N_INV), \ |
5287ad62 JB |
14535 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ |
14536 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
14537 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
14538 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 14539 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
14540 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
14541 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
14542 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
14543 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
14544 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
14545 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
14546 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
14547 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
14548 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
14549 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
14550 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
14551 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
14552 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
14553 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
14554 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
d6b4b13e MW |
14555 | X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \ |
14556 | X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \ | |
5287ad62 JB |
14557 | X(vshl, 0x0000400, N_INV, 0x0800510), \ |
14558 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
14559 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
14560 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
14561 | X(veor, 0x1000110, N_INV, N_INV), \ | |
14562 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
14563 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
14564 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
14565 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
14566 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
14567 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
14568 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
14569 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
14570 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
14571 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
14572 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
14573 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
14574 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
14575 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
14576 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
14577 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
14578 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
14579 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
14580 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
14581 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
14582 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
14583 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
14584 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
14585 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
14586 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
14587 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
14588 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
14589 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
14590 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
14591 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
14592 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
14593 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 14594 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
14595 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
14596 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 14597 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 14598 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
14599 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
14600 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
14601 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
14602 | |
14603 | enum neon_opc | |
14604 | { | |
14605 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
14606 | NEON_ENC_TAB | |
14607 | #undef X | |
14608 | }; | |
b99bd4ef | 14609 | |
5287ad62 JB |
14610 | static const struct neon_tab_entry neon_enc_tab[] = |
14611 | { | |
14612 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
14613 | NEON_ENC_TAB | |
14614 | #undef X | |
14615 | }; | |
b99bd4ef | 14616 | |
88714cb8 DG |
14617 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
14618 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
14619 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
14620 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
14621 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
14622 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
14623 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
14624 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
14625 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
14626 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
14627 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 14628 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 14629 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 14630 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
14631 | #define NEON_ENC_FPV8_(X) \ |
14632 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 14633 | |
88714cb8 DG |
14634 | #define NEON_ENCODE(type, inst) \ |
14635 | do \ | |
14636 | { \ | |
14637 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
14638 | inst.is_neon = 1; \ | |
14639 | } \ | |
14640 | while (0) | |
14641 | ||
14642 | #define check_neon_suffixes \ | |
14643 | do \ | |
14644 | { \ | |
14645 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
14646 | { \ | |
14647 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
14648 | return; \ | |
14649 | } \ | |
14650 | } \ | |
14651 | while (0) | |
14652 | ||
037e8744 JB |
14653 | /* Define shapes for instruction operands. The following mnemonic characters |
14654 | are used in this table: | |
5287ad62 | 14655 | |
037e8744 | 14656 | F - VFP S<n> register |
5287ad62 JB |
14657 | D - Neon D<n> register |
14658 | Q - Neon Q<n> register | |
14659 | I - Immediate | |
14660 | S - Scalar | |
14661 | R - ARM register | |
14662 | L - D<n> register list | |
5f4273c7 | 14663 | |
037e8744 JB |
14664 | This table is used to generate various data: |
14665 | - enumerations of the form NS_DDR to be used as arguments to | |
14666 | neon_select_shape. | |
14667 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 14668 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 14669 | |
037e8744 | 14670 | #define NEON_SHAPE_DEF \ |
93925576 | 14671 | X(4, (R, R, Q, Q), QUAD), \ |
b409bdb6 | 14672 | X(4, (Q, R, R, I), QUAD), \ |
57785aa2 AV |
14673 | X(4, (R, R, S, S), QUAD), \ |
14674 | X(4, (S, S, R, R), QUAD), \ | |
b409bdb6 | 14675 | X(3, (Q, R, I), QUAD), \ |
1b883319 AV |
14676 | X(3, (I, Q, Q), QUAD), \ |
14677 | X(3, (I, Q, R), QUAD), \ | |
a302e574 | 14678 | X(3, (R, Q, Q), QUAD), \ |
037e8744 JB |
14679 | X(3, (D, D, D), DOUBLE), \ |
14680 | X(3, (Q, Q, Q), QUAD), \ | |
14681 | X(3, (D, D, I), DOUBLE), \ | |
14682 | X(3, (Q, Q, I), QUAD), \ | |
14683 | X(3, (D, D, S), DOUBLE), \ | |
14684 | X(3, (Q, Q, S), QUAD), \ | |
5ee91343 | 14685 | X(3, (Q, Q, R), QUAD), \ |
26c1e780 AV |
14686 | X(3, (R, R, Q), QUAD), \ |
14687 | X(2, (R, Q), QUAD), \ | |
037e8744 JB |
14688 | X(2, (D, D), DOUBLE), \ |
14689 | X(2, (Q, Q), QUAD), \ | |
14690 | X(2, (D, S), DOUBLE), \ | |
14691 | X(2, (Q, S), QUAD), \ | |
14692 | X(2, (D, R), DOUBLE), \ | |
14693 | X(2, (Q, R), QUAD), \ | |
14694 | X(2, (D, I), DOUBLE), \ | |
14695 | X(2, (Q, I), QUAD), \ | |
14696 | X(3, (D, L, D), DOUBLE), \ | |
14697 | X(2, (D, Q), MIXED), \ | |
14698 | X(2, (Q, D), MIXED), \ | |
14699 | X(3, (D, Q, I), MIXED), \ | |
14700 | X(3, (Q, D, I), MIXED), \ | |
14701 | X(3, (Q, D, D), MIXED), \ | |
14702 | X(3, (D, Q, Q), MIXED), \ | |
14703 | X(3, (Q, Q, D), MIXED), \ | |
14704 | X(3, (Q, D, S), MIXED), \ | |
14705 | X(3, (D, Q, S), MIXED), \ | |
14706 | X(4, (D, D, D, I), DOUBLE), \ | |
14707 | X(4, (Q, Q, Q, I), QUAD), \ | |
c28eeff2 SN |
14708 | X(4, (D, D, S, I), DOUBLE), \ |
14709 | X(4, (Q, Q, S, I), QUAD), \ | |
037e8744 JB |
14710 | X(2, (F, F), SINGLE), \ |
14711 | X(3, (F, F, F), SINGLE), \ | |
14712 | X(2, (F, I), SINGLE), \ | |
14713 | X(2, (F, D), MIXED), \ | |
14714 | X(2, (D, F), MIXED), \ | |
14715 | X(3, (F, F, I), MIXED), \ | |
14716 | X(4, (R, R, F, F), SINGLE), \ | |
14717 | X(4, (F, F, R, R), SINGLE), \ | |
14718 | X(3, (D, R, R), DOUBLE), \ | |
14719 | X(3, (R, R, D), DOUBLE), \ | |
14720 | X(2, (S, R), SINGLE), \ | |
14721 | X(2, (R, S), SINGLE), \ | |
14722 | X(2, (F, R), SINGLE), \ | |
d54af2d0 | 14723 | X(2, (R, F), SINGLE), \ |
1f6234a3 AV |
14724 | /* Used for MVE tail predicated loop instructions. */\ |
14725 | X(2, (R, R), QUAD), \ | |
d54af2d0 RL |
14726 | /* Half float shape supported so far. */\ |
14727 | X (2, (H, D), MIXED), \ | |
14728 | X (2, (D, H), MIXED), \ | |
14729 | X (2, (H, F), MIXED), \ | |
14730 | X (2, (F, H), MIXED), \ | |
14731 | X (2, (H, H), HALF), \ | |
14732 | X (2, (H, R), HALF), \ | |
14733 | X (2, (R, H), HALF), \ | |
14734 | X (2, (H, I), HALF), \ | |
14735 | X (3, (H, H, H), HALF), \ | |
14736 | X (3, (H, F, I), MIXED), \ | |
dec41383 JW |
14737 | X (3, (F, H, I), MIXED), \ |
14738 | X (3, (D, H, H), MIXED), \ | |
14739 | X (3, (D, H, S), MIXED) | |
037e8744 JB |
14740 | |
14741 | #define S2(A,B) NS_##A##B | |
14742 | #define S3(A,B,C) NS_##A##B##C | |
14743 | #define S4(A,B,C,D) NS_##A##B##C##D | |
14744 | ||
14745 | #define X(N, L, C) S##N L | |
14746 | ||
5287ad62 JB |
14747 | enum neon_shape |
14748 | { | |
037e8744 JB |
14749 | NEON_SHAPE_DEF, |
14750 | NS_NULL | |
5287ad62 | 14751 | }; |
b99bd4ef | 14752 | |
037e8744 JB |
14753 | #undef X |
14754 | #undef S2 | |
14755 | #undef S3 | |
14756 | #undef S4 | |
14757 | ||
14758 | enum neon_shape_class | |
14759 | { | |
d54af2d0 | 14760 | SC_HALF, |
037e8744 JB |
14761 | SC_SINGLE, |
14762 | SC_DOUBLE, | |
14763 | SC_QUAD, | |
14764 | SC_MIXED | |
14765 | }; | |
14766 | ||
14767 | #define X(N, L, C) SC_##C | |
14768 | ||
14769 | static enum neon_shape_class neon_shape_class[] = | |
14770 | { | |
14771 | NEON_SHAPE_DEF | |
14772 | }; | |
14773 | ||
14774 | #undef X | |
14775 | ||
14776 | enum neon_shape_el | |
14777 | { | |
d54af2d0 | 14778 | SE_H, |
037e8744 JB |
14779 | SE_F, |
14780 | SE_D, | |
14781 | SE_Q, | |
14782 | SE_I, | |
14783 | SE_S, | |
14784 | SE_R, | |
14785 | SE_L | |
14786 | }; | |
14787 | ||
14788 | /* Register widths of above. */ | |
14789 | static unsigned neon_shape_el_size[] = | |
14790 | { | |
d54af2d0 | 14791 | 16, |
037e8744 JB |
14792 | 32, |
14793 | 64, | |
14794 | 128, | |
14795 | 0, | |
14796 | 32, | |
14797 | 32, | |
14798 | 0 | |
14799 | }; | |
14800 | ||
14801 | struct neon_shape_info | |
14802 | { | |
14803 | unsigned els; | |
14804 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
14805 | }; | |
14806 | ||
14807 | #define S2(A,B) { SE_##A, SE_##B } | |
14808 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
14809 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
14810 | ||
14811 | #define X(N, L, C) { N, S##N L } | |
14812 | ||
14813 | static struct neon_shape_info neon_shape_tab[] = | |
14814 | { | |
14815 | NEON_SHAPE_DEF | |
14816 | }; | |
14817 | ||
14818 | #undef X | |
14819 | #undef S2 | |
14820 | #undef S3 | |
14821 | #undef S4 | |
14822 | ||
5287ad62 JB |
14823 | /* Bit masks used in type checking given instructions. |
14824 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
14825 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
14826 | set, various other bits can be set as well in order to modify the meaning of | |
14827 | the type constraint. */ | |
14828 | ||
14829 | enum neon_type_mask | |
14830 | { | |
8e79c3df CM |
14831 | N_S8 = 0x0000001, |
14832 | N_S16 = 0x0000002, | |
14833 | N_S32 = 0x0000004, | |
14834 | N_S64 = 0x0000008, | |
14835 | N_U8 = 0x0000010, | |
14836 | N_U16 = 0x0000020, | |
14837 | N_U32 = 0x0000040, | |
14838 | N_U64 = 0x0000080, | |
14839 | N_I8 = 0x0000100, | |
14840 | N_I16 = 0x0000200, | |
14841 | N_I32 = 0x0000400, | |
14842 | N_I64 = 0x0000800, | |
14843 | N_8 = 0x0001000, | |
14844 | N_16 = 0x0002000, | |
14845 | N_32 = 0x0004000, | |
14846 | N_64 = 0x0008000, | |
14847 | N_P8 = 0x0010000, | |
14848 | N_P16 = 0x0020000, | |
14849 | N_F16 = 0x0040000, | |
14850 | N_F32 = 0x0080000, | |
14851 | N_F64 = 0x0100000, | |
4f51b4bd | 14852 | N_P64 = 0x0200000, |
c921be7d NC |
14853 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
14854 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 14855 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 14856 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
14857 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
14858 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
14859 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
14860 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
14861 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
14862 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
14863 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 14864 | N_UTYP = 0, |
4f51b4bd | 14865 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
14866 | }; |
14867 | ||
dcbf9037 JB |
14868 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
14869 | ||
5287ad62 JB |
14870 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
14871 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
14872 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
cc933301 JW |
14873 | #define N_S_32 (N_S8 | N_S16 | N_S32) |
14874 | #define N_F_16_32 (N_F16 | N_F32) | |
14875 | #define N_SUF_32 (N_SU_32 | N_F_16_32) | |
5287ad62 | 14876 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) |
cc933301 | 14877 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32) |
d54af2d0 | 14878 | #define N_F_ALL (N_F16 | N_F32 | N_F64) |
5ee91343 AV |
14879 | #define N_I_MVE (N_I8 | N_I16 | N_I32) |
14880 | #define N_F_MVE (N_F16 | N_F32) | |
14881 | #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
5287ad62 JB |
14882 | |
14883 | /* Pass this as the first type argument to neon_check_type to ignore types | |
14884 | altogether. */ | |
14885 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
14886 | ||
037e8744 JB |
14887 | /* Select a "shape" for the current instruction (describing register types or |
14888 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
14889 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
14890 | function of operand parsing, so this function doesn't need to be called. | |
14891 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
14892 | |
14893 | static enum neon_shape | |
037e8744 | 14894 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 14895 | { |
037e8744 JB |
14896 | va_list ap; |
14897 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
14898 | |
14899 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
14900 | many arguments we should have, so this makes the assumption that we have | |
14901 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
14902 | true in the future. */ | |
14903 | if (!inst.operands[1].present) | |
14904 | inst.operands[1] = inst.operands[0]; | |
14905 | ||
037e8744 | 14906 | va_start (ap, shape); |
5f4273c7 | 14907 | |
21d799b5 | 14908 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
14909 | { |
14910 | unsigned j; | |
14911 | int matches = 1; | |
14912 | ||
14913 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
14914 | { |
14915 | if (!inst.operands[j].present) | |
14916 | { | |
14917 | matches = 0; | |
14918 | break; | |
14919 | } | |
14920 | ||
14921 | switch (neon_shape_tab[shape].el[j]) | |
14922 | { | |
d54af2d0 RL |
14923 | /* If a .f16, .16, .u16, .s16 type specifier is given over |
14924 | a VFP single precision register operand, it's essentially | |
14925 | means only half of the register is used. | |
14926 | ||
14927 | If the type specifier is given after the mnemonics, the | |
14928 | information is stored in inst.vectype. If the type specifier | |
14929 | is given after register operand, the information is stored | |
14930 | in inst.operands[].vectype. | |
14931 | ||
14932 | When there is only one type specifier, and all the register | |
14933 | operands are the same type of hardware register, the type | |
14934 | specifier applies to all register operands. | |
14935 | ||
14936 | If no type specifier is given, the shape is inferred from | |
14937 | operand information. | |
14938 | ||
14939 | for example: | |
14940 | vadd.f16 s0, s1, s2: NS_HHH | |
14941 | vabs.f16 s0, s1: NS_HH | |
14942 | vmov.f16 s0, r1: NS_HR | |
14943 | vmov.f16 r0, s1: NS_RH | |
14944 | vcvt.f16 r0, s1: NS_RH | |
14945 | vcvt.f16.s32 s2, s2, #29: NS_HFI | |
14946 | vcvt.f16.s32 s2, s2: NS_HF | |
14947 | */ | |
14948 | case SE_H: | |
14949 | if (!(inst.operands[j].isreg | |
14950 | && inst.operands[j].isvec | |
14951 | && inst.operands[j].issingle | |
14952 | && !inst.operands[j].isquad | |
14953 | && ((inst.vectype.elems == 1 | |
14954 | && inst.vectype.el[0].size == 16) | |
14955 | || (inst.vectype.elems > 1 | |
14956 | && inst.vectype.el[j].size == 16) | |
14957 | || (inst.vectype.elems == 0 | |
14958 | && inst.operands[j].vectype.type != NT_invtype | |
14959 | && inst.operands[j].vectype.size == 16)))) | |
14960 | matches = 0; | |
14961 | break; | |
14962 | ||
477330fc RM |
14963 | case SE_F: |
14964 | if (!(inst.operands[j].isreg | |
14965 | && inst.operands[j].isvec | |
14966 | && inst.operands[j].issingle | |
d54af2d0 RL |
14967 | && !inst.operands[j].isquad |
14968 | && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32) | |
14969 | || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32) | |
14970 | || (inst.vectype.elems == 0 | |
14971 | && (inst.operands[j].vectype.size == 32 | |
14972 | || inst.operands[j].vectype.type == NT_invtype))))) | |
477330fc RM |
14973 | matches = 0; |
14974 | break; | |
14975 | ||
14976 | case SE_D: | |
14977 | if (!(inst.operands[j].isreg | |
14978 | && inst.operands[j].isvec | |
14979 | && !inst.operands[j].isquad | |
14980 | && !inst.operands[j].issingle)) | |
14981 | matches = 0; | |
14982 | break; | |
14983 | ||
14984 | case SE_R: | |
14985 | if (!(inst.operands[j].isreg | |
14986 | && !inst.operands[j].isvec)) | |
14987 | matches = 0; | |
14988 | break; | |
14989 | ||
14990 | case SE_Q: | |
14991 | if (!(inst.operands[j].isreg | |
14992 | && inst.operands[j].isvec | |
14993 | && inst.operands[j].isquad | |
14994 | && !inst.operands[j].issingle)) | |
14995 | matches = 0; | |
14996 | break; | |
14997 | ||
14998 | case SE_I: | |
14999 | if (!(!inst.operands[j].isreg | |
15000 | && !inst.operands[j].isscalar)) | |
15001 | matches = 0; | |
15002 | break; | |
15003 | ||
15004 | case SE_S: | |
15005 | if (!(!inst.operands[j].isreg | |
15006 | && inst.operands[j].isscalar)) | |
15007 | matches = 0; | |
15008 | break; | |
15009 | ||
15010 | case SE_L: | |
15011 | break; | |
15012 | } | |
3fde54a2 JZ |
15013 | if (!matches) |
15014 | break; | |
477330fc | 15015 | } |
ad6cec43 MGD |
15016 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
15017 | /* We've matched all the entries in the shape table, and we don't | |
15018 | have any left over operands which have not been matched. */ | |
477330fc | 15019 | break; |
037e8744 | 15020 | } |
5f4273c7 | 15021 | |
037e8744 | 15022 | va_end (ap); |
5287ad62 | 15023 | |
037e8744 JB |
15024 | if (shape == NS_NULL && first_shape != NS_NULL) |
15025 | first_error (_("invalid instruction shape")); | |
5287ad62 | 15026 | |
037e8744 JB |
15027 | return shape; |
15028 | } | |
5287ad62 | 15029 | |
037e8744 JB |
15030 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
15031 | means the Q bit should be set). */ | |
15032 | ||
15033 | static int | |
15034 | neon_quad (enum neon_shape shape) | |
15035 | { | |
15036 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 15037 | } |
037e8744 | 15038 | |
5287ad62 JB |
15039 | static void |
15040 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 15041 | unsigned *g_size) |
5287ad62 JB |
15042 | { |
15043 | /* Allow modification to be made to types which are constrained to be | |
15044 | based on the key element, based on bits set alongside N_EQK. */ | |
15045 | if ((typebits & N_EQK) != 0) | |
15046 | { | |
15047 | if ((typebits & N_HLF) != 0) | |
15048 | *g_size /= 2; | |
15049 | else if ((typebits & N_DBL) != 0) | |
15050 | *g_size *= 2; | |
15051 | if ((typebits & N_SGN) != 0) | |
15052 | *g_type = NT_signed; | |
15053 | else if ((typebits & N_UNS) != 0) | |
477330fc | 15054 | *g_type = NT_unsigned; |
5287ad62 | 15055 | else if ((typebits & N_INT) != 0) |
477330fc | 15056 | *g_type = NT_integer; |
5287ad62 | 15057 | else if ((typebits & N_FLT) != 0) |
477330fc | 15058 | *g_type = NT_float; |
dcbf9037 | 15059 | else if ((typebits & N_SIZ) != 0) |
477330fc | 15060 | *g_type = NT_untyped; |
5287ad62 JB |
15061 | } |
15062 | } | |
5f4273c7 | 15063 | |
5287ad62 JB |
15064 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
15065 | operand type, i.e. the single type specified in a Neon instruction when it | |
15066 | is the only one given. */ | |
15067 | ||
15068 | static struct neon_type_el | |
15069 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
15070 | { | |
15071 | struct neon_type_el dest = *key; | |
5f4273c7 | 15072 | |
9c2799c2 | 15073 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 15074 | |
5287ad62 JB |
15075 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
15076 | ||
15077 | return dest; | |
15078 | } | |
15079 | ||
15080 | /* Convert Neon type and size into compact bitmask representation. */ | |
15081 | ||
15082 | static enum neon_type_mask | |
15083 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
15084 | { | |
15085 | switch (type) | |
15086 | { | |
15087 | case NT_untyped: | |
15088 | switch (size) | |
477330fc RM |
15089 | { |
15090 | case 8: return N_8; | |
15091 | case 16: return N_16; | |
15092 | case 32: return N_32; | |
15093 | case 64: return N_64; | |
15094 | default: ; | |
15095 | } | |
5287ad62 JB |
15096 | break; |
15097 | ||
15098 | case NT_integer: | |
15099 | switch (size) | |
477330fc RM |
15100 | { |
15101 | case 8: return N_I8; | |
15102 | case 16: return N_I16; | |
15103 | case 32: return N_I32; | |
15104 | case 64: return N_I64; | |
15105 | default: ; | |
15106 | } | |
5287ad62 JB |
15107 | break; |
15108 | ||
15109 | case NT_float: | |
037e8744 | 15110 | switch (size) |
477330fc | 15111 | { |
8e79c3df | 15112 | case 16: return N_F16; |
477330fc RM |
15113 | case 32: return N_F32; |
15114 | case 64: return N_F64; | |
15115 | default: ; | |
15116 | } | |
5287ad62 JB |
15117 | break; |
15118 | ||
15119 | case NT_poly: | |
15120 | switch (size) | |
477330fc RM |
15121 | { |
15122 | case 8: return N_P8; | |
15123 | case 16: return N_P16; | |
4f51b4bd | 15124 | case 64: return N_P64; |
477330fc RM |
15125 | default: ; |
15126 | } | |
5287ad62 JB |
15127 | break; |
15128 | ||
15129 | case NT_signed: | |
15130 | switch (size) | |
477330fc RM |
15131 | { |
15132 | case 8: return N_S8; | |
15133 | case 16: return N_S16; | |
15134 | case 32: return N_S32; | |
15135 | case 64: return N_S64; | |
15136 | default: ; | |
15137 | } | |
5287ad62 JB |
15138 | break; |
15139 | ||
15140 | case NT_unsigned: | |
15141 | switch (size) | |
477330fc RM |
15142 | { |
15143 | case 8: return N_U8; | |
15144 | case 16: return N_U16; | |
15145 | case 32: return N_U32; | |
15146 | case 64: return N_U64; | |
15147 | default: ; | |
15148 | } | |
5287ad62 JB |
15149 | break; |
15150 | ||
15151 | default: ; | |
15152 | } | |
5f4273c7 | 15153 | |
5287ad62 JB |
15154 | return N_UTYP; |
15155 | } | |
15156 | ||
15157 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
15158 | handles the case where a single bit is set in the mask. */ | |
15159 | ||
dcbf9037 | 15160 | static int |
5287ad62 | 15161 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 15162 | enum neon_type_mask mask) |
5287ad62 | 15163 | { |
dcbf9037 JB |
15164 | if ((mask & N_EQK) != 0) |
15165 | return FAIL; | |
15166 | ||
5287ad62 JB |
15167 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
15168 | *size = 8; | |
c70a8987 | 15169 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 15170 | *size = 16; |
dcbf9037 | 15171 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 15172 | *size = 32; |
4f51b4bd | 15173 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 15174 | *size = 64; |
dcbf9037 JB |
15175 | else |
15176 | return FAIL; | |
15177 | ||
5287ad62 JB |
15178 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
15179 | *type = NT_signed; | |
dcbf9037 | 15180 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 15181 | *type = NT_unsigned; |
dcbf9037 | 15182 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 15183 | *type = NT_integer; |
dcbf9037 | 15184 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 15185 | *type = NT_untyped; |
4f51b4bd | 15186 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 15187 | *type = NT_poly; |
d54af2d0 | 15188 | else if ((mask & (N_F_ALL)) != 0) |
5287ad62 | 15189 | *type = NT_float; |
dcbf9037 JB |
15190 | else |
15191 | return FAIL; | |
5f4273c7 | 15192 | |
dcbf9037 | 15193 | return SUCCESS; |
5287ad62 JB |
15194 | } |
15195 | ||
15196 | /* Modify a bitmask of allowed types. This is only needed for type | |
15197 | relaxation. */ | |
15198 | ||
15199 | static unsigned | |
15200 | modify_types_allowed (unsigned allowed, unsigned mods) | |
15201 | { | |
15202 | unsigned size; | |
15203 | enum neon_el_type type; | |
15204 | unsigned destmask; | |
15205 | int i; | |
5f4273c7 | 15206 | |
5287ad62 | 15207 | destmask = 0; |
5f4273c7 | 15208 | |
5287ad62 JB |
15209 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
15210 | { | |
21d799b5 | 15211 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
15212 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
15213 | { | |
15214 | neon_modify_type_size (mods, &type, &size); | |
15215 | destmask |= type_chk_of_el_type (type, size); | |
15216 | } | |
5287ad62 | 15217 | } |
5f4273c7 | 15218 | |
5287ad62 JB |
15219 | return destmask; |
15220 | } | |
15221 | ||
15222 | /* Check type and return type classification. | |
15223 | The manual states (paraphrase): If one datatype is given, it indicates the | |
15224 | type given in: | |
15225 | - the second operand, if there is one | |
15226 | - the operand, if there is no second operand | |
15227 | - the result, if there are no operands. | |
15228 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
15229 | which is set on a per-instruction basis, which is the one which matters when | |
15230 | only one data type is written. | |
15231 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 15232 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
15233 | |
15234 | static struct neon_type_el | |
15235 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
15236 | { | |
15237 | va_list ap; | |
15238 | unsigned i, pass, key_el = 0; | |
15239 | unsigned types[NEON_MAX_TYPE_ELS]; | |
15240 | enum neon_el_type k_type = NT_invtype; | |
15241 | unsigned k_size = -1u; | |
15242 | struct neon_type_el badtype = {NT_invtype, -1}; | |
15243 | unsigned key_allowed = 0; | |
15244 | ||
15245 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
15246 | Fill in the missing operand here, if it was omitted. */ | |
15247 | if (els > 1 && !inst.operands[1].present) | |
15248 | inst.operands[1] = inst.operands[0]; | |
15249 | ||
15250 | /* Suck up all the varargs. */ | |
15251 | va_start (ap, ns); | |
15252 | for (i = 0; i < els; i++) | |
15253 | { | |
15254 | unsigned thisarg = va_arg (ap, unsigned); | |
15255 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
15256 | { |
15257 | va_end (ap); | |
15258 | return badtype; | |
15259 | } | |
5287ad62 JB |
15260 | types[i] = thisarg; |
15261 | if ((thisarg & N_KEY) != 0) | |
477330fc | 15262 | key_el = i; |
5287ad62 JB |
15263 | } |
15264 | va_end (ap); | |
15265 | ||
dcbf9037 JB |
15266 | if (inst.vectype.elems > 0) |
15267 | for (i = 0; i < els; i++) | |
15268 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
15269 | { |
15270 | first_error (_("types specified in both the mnemonic and operands")); | |
15271 | return badtype; | |
15272 | } | |
dcbf9037 | 15273 | |
5287ad62 JB |
15274 | /* Duplicate inst.vectype elements here as necessary. |
15275 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
15276 | particularly when an insn takes one register and one non-register | |
15277 | operand. */ | |
15278 | if (inst.vectype.elems == 1 && els > 1) | |
15279 | { | |
15280 | unsigned j; | |
15281 | inst.vectype.elems = els; | |
15282 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
15283 | for (j = 0; j < els; j++) | |
477330fc RM |
15284 | if (j != key_el) |
15285 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
15286 | types[j]); | |
dcbf9037 JB |
15287 | } |
15288 | else if (inst.vectype.elems == 0 && els > 0) | |
15289 | { | |
15290 | unsigned j; | |
15291 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
15292 | after each operand. We allow some flexibility here; as long as the |
15293 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 15294 | for (j = 0; j < els; j++) |
477330fc RM |
15295 | if (inst.operands[j].vectype.type != NT_invtype) |
15296 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
15297 | |
15298 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
15299 | { |
15300 | for (j = 0; j < els; j++) | |
15301 | if (inst.operands[j].vectype.type == NT_invtype) | |
15302 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
15303 | types[j]); | |
15304 | } | |
dcbf9037 | 15305 | else |
477330fc RM |
15306 | { |
15307 | first_error (_("operand types can't be inferred")); | |
15308 | return badtype; | |
15309 | } | |
5287ad62 JB |
15310 | } |
15311 | else if (inst.vectype.elems != els) | |
15312 | { | |
dcbf9037 | 15313 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
15314 | return badtype; |
15315 | } | |
15316 | ||
15317 | for (pass = 0; pass < 2; pass++) | |
15318 | { | |
15319 | for (i = 0; i < els; i++) | |
477330fc RM |
15320 | { |
15321 | unsigned thisarg = types[i]; | |
15322 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
15323 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
15324 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
15325 | unsigned g_size = inst.vectype.el[i].size; | |
15326 | ||
15327 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 15328 | integer types if sign-specific variants are unavailable. */ |
477330fc | 15329 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
15330 | && (types_allowed & N_SU_ALL) == 0) |
15331 | g_type = NT_integer; | |
15332 | ||
477330fc | 15333 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
15334 | them. Some instructions only care about signs for some element |
15335 | sizes, so handle that properly. */ | |
477330fc | 15336 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
15337 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
15338 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
15339 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
15340 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
15341 | g_type = NT_untyped; |
15342 | ||
477330fc RM |
15343 | if (pass == 0) |
15344 | { | |
15345 | if ((thisarg & N_KEY) != 0) | |
15346 | { | |
15347 | k_type = g_type; | |
15348 | k_size = g_size; | |
15349 | key_allowed = thisarg & ~N_KEY; | |
cc933301 JW |
15350 | |
15351 | /* Check architecture constraint on FP16 extension. */ | |
15352 | if (k_size == 16 | |
15353 | && k_type == NT_float | |
15354 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) | |
15355 | { | |
15356 | inst.error = _(BAD_FP16); | |
15357 | return badtype; | |
15358 | } | |
477330fc RM |
15359 | } |
15360 | } | |
15361 | else | |
15362 | { | |
15363 | if ((thisarg & N_VFP) != 0) | |
15364 | { | |
15365 | enum neon_shape_el regshape; | |
15366 | unsigned regwidth, match; | |
99b253c5 NC |
15367 | |
15368 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
15369 | if (ns == NS_NULL) | |
15370 | { | |
15371 | first_error (_("invalid instruction shape")); | |
15372 | return badtype; | |
15373 | } | |
477330fc RM |
15374 | regshape = neon_shape_tab[ns].el[i]; |
15375 | regwidth = neon_shape_el_size[regshape]; | |
15376 | ||
15377 | /* In VFP mode, operands must match register widths. If we | |
15378 | have a key operand, use its width, else use the width of | |
15379 | the current operand. */ | |
15380 | if (k_size != -1u) | |
15381 | match = k_size; | |
15382 | else | |
15383 | match = g_size; | |
15384 | ||
9db2f6b4 RL |
15385 | /* FP16 will use a single precision register. */ |
15386 | if (regwidth == 32 && match == 16) | |
15387 | { | |
15388 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)) | |
15389 | match = regwidth; | |
15390 | else | |
15391 | { | |
15392 | inst.error = _(BAD_FP16); | |
15393 | return badtype; | |
15394 | } | |
15395 | } | |
15396 | ||
477330fc RM |
15397 | if (regwidth != match) |
15398 | { | |
15399 | first_error (_("operand size must match register width")); | |
15400 | return badtype; | |
15401 | } | |
15402 | } | |
15403 | ||
15404 | if ((thisarg & N_EQK) == 0) | |
15405 | { | |
15406 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
15407 | ||
15408 | if ((given_type & types_allowed) == 0) | |
15409 | { | |
a302e574 | 15410 | first_error (BAD_SIMD_TYPE); |
477330fc RM |
15411 | return badtype; |
15412 | } | |
15413 | } | |
15414 | else | |
15415 | { | |
15416 | enum neon_el_type mod_k_type = k_type; | |
15417 | unsigned mod_k_size = k_size; | |
15418 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
15419 | if (g_type != mod_k_type || g_size != mod_k_size) | |
15420 | { | |
15421 | first_error (_("inconsistent types in Neon instruction")); | |
15422 | return badtype; | |
15423 | } | |
15424 | } | |
15425 | } | |
15426 | } | |
5287ad62 JB |
15427 | } |
15428 | ||
15429 | return inst.vectype.el[key_el]; | |
15430 | } | |
15431 | ||
037e8744 | 15432 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 15433 | |
037e8744 JB |
15434 | /* Thumb VFP instructions have 0xE in the condition field. */ |
15435 | ||
15436 | static void | |
15437 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 15438 | { |
88714cb8 DG |
15439 | inst.is_neon = 1; |
15440 | ||
5287ad62 | 15441 | if (thumb_mode) |
037e8744 | 15442 | inst.instruction |= 0xe0000000; |
5287ad62 | 15443 | else |
037e8744 | 15444 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
15445 | } |
15446 | ||
037e8744 JB |
15447 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
15448 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
15449 | etc. It is assumed that operand parsing has already been done, and that the | |
15450 | operands are in the form expected by the given opcode (this isn't necessarily | |
15451 | the same as the form in which they were parsed, hence some massaging must | |
15452 | take place before this function is called). | |
15453 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 15454 | |
037e8744 JB |
15455 | static void |
15456 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 15457 | { |
037e8744 | 15458 | const struct asm_opcode *opcode; |
5f4273c7 | 15459 | |
21d799b5 | 15460 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 15461 | |
037e8744 JB |
15462 | if (!opcode) |
15463 | abort (); | |
5287ad62 | 15464 | |
037e8744 | 15465 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
15466 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
15467 | _(BAD_FPU)); | |
5287ad62 | 15468 | |
88714cb8 DG |
15469 | inst.is_neon = 1; |
15470 | ||
037e8744 JB |
15471 | if (thumb_mode) |
15472 | { | |
15473 | inst.instruction = opcode->tvalue; | |
15474 | opcode->tencode (); | |
15475 | } | |
15476 | else | |
15477 | { | |
15478 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
15479 | opcode->aencode (); | |
15480 | } | |
15481 | } | |
5287ad62 JB |
15482 | |
15483 | static void | |
037e8744 | 15484 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 15485 | { |
037e8744 JB |
15486 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
15487 | ||
9db2f6b4 | 15488 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 JB |
15489 | { |
15490 | if (is_add) | |
477330fc | 15491 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 15492 | else |
477330fc | 15493 | do_vfp_nsyn_opcode ("fsubs"); |
9db2f6b4 RL |
15494 | |
15495 | /* ARMv8.2 fp16 instruction. */ | |
15496 | if (rs == NS_HHH) | |
15497 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15498 | } |
15499 | else | |
15500 | { | |
15501 | if (is_add) | |
477330fc | 15502 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 15503 | else |
477330fc | 15504 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
15505 | } |
15506 | } | |
15507 | ||
15508 | /* Check operand types to see if this is a VFP instruction, and if so call | |
15509 | PFN (). */ | |
15510 | ||
15511 | static int | |
15512 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
15513 | { | |
15514 | enum neon_shape rs; | |
15515 | struct neon_type_el et; | |
15516 | ||
15517 | switch (args) | |
15518 | { | |
15519 | case 2: | |
9db2f6b4 RL |
15520 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
15521 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
037e8744 | 15522 | break; |
5f4273c7 | 15523 | |
037e8744 | 15524 | case 3: |
9db2f6b4 RL |
15525 | rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
15526 | et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
15527 | N_F_ALL | N_KEY | N_VFP); | |
037e8744 JB |
15528 | break; |
15529 | ||
15530 | default: | |
15531 | abort (); | |
15532 | } | |
15533 | ||
15534 | if (et.type != NT_invtype) | |
15535 | { | |
15536 | pfn (rs); | |
15537 | return SUCCESS; | |
15538 | } | |
037e8744 | 15539 | |
99b253c5 | 15540 | inst.error = NULL; |
037e8744 JB |
15541 | return FAIL; |
15542 | } | |
15543 | ||
15544 | static void | |
15545 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
15546 | { | |
15547 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 15548 | |
9db2f6b4 | 15549 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 JB |
15550 | { |
15551 | if (is_mla) | |
477330fc | 15552 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 15553 | else |
477330fc | 15554 | do_vfp_nsyn_opcode ("fnmacs"); |
9db2f6b4 RL |
15555 | |
15556 | /* ARMv8.2 fp16 instruction. */ | |
15557 | if (rs == NS_HHH) | |
15558 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15559 | } |
15560 | else | |
15561 | { | |
15562 | if (is_mla) | |
477330fc | 15563 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 15564 | else |
477330fc | 15565 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
15566 | } |
15567 | } | |
15568 | ||
62f3b8c8 PB |
15569 | static void |
15570 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
15571 | { | |
15572 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
15573 | ||
9db2f6b4 | 15574 | if (rs == NS_FFF || rs == NS_HHH) |
62f3b8c8 PB |
15575 | { |
15576 | if (is_fma) | |
477330fc | 15577 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 15578 | else |
477330fc | 15579 | do_vfp_nsyn_opcode ("ffnmas"); |
9db2f6b4 RL |
15580 | |
15581 | /* ARMv8.2 fp16 instruction. */ | |
15582 | if (rs == NS_HHH) | |
15583 | do_scalar_fp16_v82_encode (); | |
62f3b8c8 PB |
15584 | } |
15585 | else | |
15586 | { | |
15587 | if (is_fma) | |
477330fc | 15588 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 15589 | else |
477330fc | 15590 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
15591 | } |
15592 | } | |
15593 | ||
037e8744 JB |
15594 | static void |
15595 | do_vfp_nsyn_mul (enum neon_shape rs) | |
15596 | { | |
9db2f6b4 RL |
15597 | if (rs == NS_FFF || rs == NS_HHH) |
15598 | { | |
15599 | do_vfp_nsyn_opcode ("fmuls"); | |
15600 | ||
15601 | /* ARMv8.2 fp16 instruction. */ | |
15602 | if (rs == NS_HHH) | |
15603 | do_scalar_fp16_v82_encode (); | |
15604 | } | |
037e8744 JB |
15605 | else |
15606 | do_vfp_nsyn_opcode ("fmuld"); | |
15607 | } | |
15608 | ||
15609 | static void | |
15610 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
15611 | { | |
15612 | int is_neg = (inst.instruction & 0x80) != 0; | |
9db2f6b4 | 15613 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY); |
037e8744 | 15614 | |
9db2f6b4 | 15615 | if (rs == NS_FF || rs == NS_HH) |
037e8744 JB |
15616 | { |
15617 | if (is_neg) | |
477330fc | 15618 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 15619 | else |
477330fc | 15620 | do_vfp_nsyn_opcode ("fabss"); |
9db2f6b4 RL |
15621 | |
15622 | /* ARMv8.2 fp16 instruction. */ | |
15623 | if (rs == NS_HH) | |
15624 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15625 | } |
15626 | else | |
15627 | { | |
15628 | if (is_neg) | |
477330fc | 15629 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 15630 | else |
477330fc | 15631 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
15632 | } |
15633 | } | |
15634 | ||
15635 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
15636 | insns belong to Neon, and are handled elsewhere. */ | |
15637 | ||
15638 | static void | |
15639 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
15640 | { | |
15641 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
15642 | if (is_ldm) | |
15643 | { | |
15644 | if (is_dbmode) | |
477330fc | 15645 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 15646 | else |
477330fc | 15647 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
15648 | } |
15649 | else | |
15650 | { | |
15651 | if (is_dbmode) | |
477330fc | 15652 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 15653 | else |
477330fc | 15654 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
15655 | } |
15656 | } | |
15657 | ||
037e8744 JB |
15658 | static void |
15659 | do_vfp_nsyn_sqrt (void) | |
15660 | { | |
9db2f6b4 RL |
15661 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
15662 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
5f4273c7 | 15663 | |
9db2f6b4 RL |
15664 | if (rs == NS_FF || rs == NS_HH) |
15665 | { | |
15666 | do_vfp_nsyn_opcode ("fsqrts"); | |
15667 | ||
15668 | /* ARMv8.2 fp16 instruction. */ | |
15669 | if (rs == NS_HH) | |
15670 | do_scalar_fp16_v82_encode (); | |
15671 | } | |
037e8744 JB |
15672 | else |
15673 | do_vfp_nsyn_opcode ("fsqrtd"); | |
15674 | } | |
15675 | ||
15676 | static void | |
15677 | do_vfp_nsyn_div (void) | |
15678 | { | |
9db2f6b4 | 15679 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
037e8744 | 15680 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
9db2f6b4 | 15681 | N_F_ALL | N_KEY | N_VFP); |
5f4273c7 | 15682 | |
9db2f6b4 RL |
15683 | if (rs == NS_FFF || rs == NS_HHH) |
15684 | { | |
15685 | do_vfp_nsyn_opcode ("fdivs"); | |
15686 | ||
15687 | /* ARMv8.2 fp16 instruction. */ | |
15688 | if (rs == NS_HHH) | |
15689 | do_scalar_fp16_v82_encode (); | |
15690 | } | |
037e8744 JB |
15691 | else |
15692 | do_vfp_nsyn_opcode ("fdivd"); | |
15693 | } | |
15694 | ||
15695 | static void | |
15696 | do_vfp_nsyn_nmul (void) | |
15697 | { | |
9db2f6b4 | 15698 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); |
037e8744 | 15699 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, |
9db2f6b4 | 15700 | N_F_ALL | N_KEY | N_VFP); |
5f4273c7 | 15701 | |
9db2f6b4 | 15702 | if (rs == NS_FFF || rs == NS_HHH) |
037e8744 | 15703 | { |
88714cb8 | 15704 | NEON_ENCODE (SINGLE, inst); |
037e8744 | 15705 | do_vfp_sp_dyadic (); |
9db2f6b4 RL |
15706 | |
15707 | /* ARMv8.2 fp16 instruction. */ | |
15708 | if (rs == NS_HHH) | |
15709 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
15710 | } |
15711 | else | |
15712 | { | |
88714cb8 | 15713 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
15714 | do_vfp_dp_rd_rn_rm (); |
15715 | } | |
15716 | do_vfp_cond_or_thumb (); | |
9db2f6b4 | 15717 | |
037e8744 JB |
15718 | } |
15719 | ||
1b883319 AV |
15720 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 |
15721 | (0, 1, 2, 3). */ | |
15722 | ||
15723 | static unsigned | |
15724 | neon_logbits (unsigned x) | |
15725 | { | |
15726 | return ffs (x) - 4; | |
15727 | } | |
15728 | ||
15729 | #define LOW4(R) ((R) & 0xf) | |
15730 | #define HI1(R) (((R) >> 4) & 1) | |
15731 | ||
15732 | static unsigned | |
15733 | mve_get_vcmp_vpt_cond (struct neon_type_el et) | |
15734 | { | |
15735 | switch (et.type) | |
15736 | { | |
15737 | default: | |
15738 | first_error (BAD_EL_TYPE); | |
15739 | return 0; | |
15740 | case NT_float: | |
15741 | switch (inst.operands[0].imm) | |
15742 | { | |
15743 | default: | |
15744 | first_error (_("invalid condition")); | |
15745 | return 0; | |
15746 | case 0x0: | |
15747 | /* eq. */ | |
15748 | return 0; | |
15749 | case 0x1: | |
15750 | /* ne. */ | |
15751 | return 1; | |
15752 | case 0xa: | |
15753 | /* ge/ */ | |
15754 | return 4; | |
15755 | case 0xb: | |
15756 | /* lt. */ | |
15757 | return 5; | |
15758 | case 0xc: | |
15759 | /* gt. */ | |
15760 | return 6; | |
15761 | case 0xd: | |
15762 | /* le. */ | |
15763 | return 7; | |
15764 | } | |
15765 | case NT_integer: | |
15766 | /* only accept eq and ne. */ | |
15767 | if (inst.operands[0].imm > 1) | |
15768 | { | |
15769 | first_error (_("invalid condition")); | |
15770 | return 0; | |
15771 | } | |
15772 | return inst.operands[0].imm; | |
15773 | case NT_unsigned: | |
15774 | if (inst.operands[0].imm == 0x2) | |
15775 | return 2; | |
15776 | else if (inst.operands[0].imm == 0x8) | |
15777 | return 3; | |
15778 | else | |
15779 | { | |
15780 | first_error (_("invalid condition")); | |
15781 | return 0; | |
15782 | } | |
15783 | case NT_signed: | |
15784 | switch (inst.operands[0].imm) | |
15785 | { | |
15786 | default: | |
15787 | first_error (_("invalid condition")); | |
15788 | return 0; | |
15789 | case 0xa: | |
15790 | /* ge. */ | |
15791 | return 4; | |
15792 | case 0xb: | |
15793 | /* lt. */ | |
15794 | return 5; | |
15795 | case 0xc: | |
15796 | /* gt. */ | |
15797 | return 6; | |
15798 | case 0xd: | |
15799 | /* le. */ | |
15800 | return 7; | |
15801 | } | |
15802 | } | |
15803 | /* Should be unreachable. */ | |
15804 | abort (); | |
15805 | } | |
15806 | ||
efd0b310 SP |
15807 | /* For VCTP (create vector tail predicate) in MVE. */ |
15808 | static void | |
15809 | do_mve_vctp (void) | |
15810 | { | |
15811 | int dt = 0; | |
15812 | unsigned size = 0x0; | |
15813 | ||
15814 | if (inst.cond > COND_ALWAYS) | |
15815 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15816 | else | |
15817 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15818 | ||
15819 | /* This is a typical MVE instruction which has no type but have size 8, 16, | |
15820 | 32 and 64. For instructions with no type, inst.vectype.el[j].type is set | |
15821 | to NT_untyped and size is updated in inst.vectype.el[j].size. */ | |
15822 | if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped)) | |
15823 | dt = inst.vectype.el[0].size; | |
15824 | ||
15825 | /* Setting this does not indicate an actual NEON instruction, but only | |
15826 | indicates that the mnemonic accepts neon-style type suffixes. */ | |
15827 | inst.is_neon = 1; | |
15828 | ||
15829 | switch (dt) | |
15830 | { | |
15831 | case 8: | |
15832 | break; | |
15833 | case 16: | |
15834 | size = 0x1; break; | |
15835 | case 32: | |
15836 | size = 0x2; break; | |
15837 | case 64: | |
15838 | size = 0x3; break; | |
15839 | default: | |
15840 | first_error (_("Type is not allowed for this instruction")); | |
15841 | } | |
15842 | inst.instruction |= size << 20; | |
15843 | inst.instruction |= inst.operands[0].reg << 16; | |
15844 | } | |
15845 | ||
1b883319 AV |
15846 | static void |
15847 | do_mve_vpt (void) | |
15848 | { | |
15849 | /* We are dealing with a vector predicated block. */ | |
15850 | if (inst.operands[0].present) | |
15851 | { | |
15852 | enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); | |
15853 | struct neon_type_el et | |
15854 | = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32, | |
15855 | N_EQK); | |
15856 | ||
15857 | unsigned fcond = mve_get_vcmp_vpt_cond (et); | |
15858 | ||
15859 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
15860 | ||
15861 | if (et.type == NT_invtype) | |
15862 | return; | |
15863 | ||
15864 | if (et.type == NT_float) | |
15865 | { | |
15866 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), | |
15867 | BAD_FPU); | |
15868 | constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE); | |
15869 | inst.instruction |= (et.size == 16) << 28; | |
15870 | inst.instruction |= 0x3 << 20; | |
15871 | } | |
15872 | else | |
15873 | { | |
15874 | constraint (et.size != 8 && et.size != 16 && et.size != 32, | |
15875 | BAD_EL_TYPE); | |
15876 | inst.instruction |= 1 << 28; | |
15877 | inst.instruction |= neon_logbits (et.size) << 20; | |
15878 | } | |
15879 | ||
15880 | if (inst.operands[2].isquad) | |
15881 | { | |
15882 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15883 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15884 | inst.instruction |= (fcond & 0x2) >> 1; | |
15885 | } | |
15886 | else | |
15887 | { | |
15888 | if (inst.operands[2].reg == REG_SP) | |
15889 | as_tsktsk (MVE_BAD_SP); | |
15890 | inst.instruction |= 1 << 6; | |
15891 | inst.instruction |= (fcond & 0x2) << 4; | |
15892 | inst.instruction |= inst.operands[2].reg; | |
15893 | } | |
15894 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15895 | inst.instruction |= (fcond & 0x4) << 10; | |
15896 | inst.instruction |= (fcond & 0x1) << 7; | |
15897 | ||
15898 | } | |
15899 | set_pred_insn_type (VPT_INSN); | |
15900 | now_pred.cc = 0; | |
15901 | now_pred.mask = ((inst.instruction & 0x00400000) >> 19) | |
15902 | | ((inst.instruction & 0xe000) >> 13); | |
15903 | now_pred.warn_deprecated = FALSE; | |
15904 | now_pred.type = VECTOR_PRED; | |
15905 | inst.is_neon = 1; | |
15906 | } | |
15907 | ||
15908 | static void | |
15909 | do_mve_vcmp (void) | |
15910 | { | |
15911 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
15912 | if (!inst.operands[1].isreg || !inst.operands[1].isquad) | |
15913 | first_error (_(reg_expected_msgs[REG_TYPE_MQ])); | |
15914 | if (!inst.operands[2].present) | |
15915 | first_error (_("MVE vector or ARM register expected")); | |
15916 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
15917 | ||
15918 | /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */ | |
15919 | if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe | |
15920 | && inst.operands[1].isquad) | |
15921 | { | |
15922 | inst.instruction = N_MNEM_vcmp; | |
15923 | inst.cond = 0x10; | |
15924 | } | |
15925 | ||
15926 | if (inst.cond > COND_ALWAYS) | |
15927 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15928 | else | |
15929 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15930 | ||
15931 | enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); | |
15932 | struct neon_type_el et | |
15933 | = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32, | |
15934 | N_EQK); | |
15935 | ||
15936 | constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC | |
15937 | && !inst.operands[2].iszr, BAD_PC); | |
15938 | ||
15939 | unsigned fcond = mve_get_vcmp_vpt_cond (et); | |
15940 | ||
15941 | inst.instruction = 0xee010f00; | |
15942 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15943 | inst.instruction |= (fcond & 0x4) << 10; | |
15944 | inst.instruction |= (fcond & 0x1) << 7; | |
15945 | if (et.type == NT_float) | |
15946 | { | |
15947 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), | |
15948 | BAD_FPU); | |
15949 | inst.instruction |= (et.size == 16) << 28; | |
15950 | inst.instruction |= 0x3 << 20; | |
15951 | } | |
15952 | else | |
15953 | { | |
15954 | inst.instruction |= 1 << 28; | |
15955 | inst.instruction |= neon_logbits (et.size) << 20; | |
15956 | } | |
15957 | if (inst.operands[2].isquad) | |
15958 | { | |
15959 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15960 | inst.instruction |= (fcond & 0x2) >> 1; | |
15961 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15962 | } | |
15963 | else | |
15964 | { | |
15965 | if (inst.operands[2].reg == REG_SP) | |
15966 | as_tsktsk (MVE_BAD_SP); | |
15967 | inst.instruction |= 1 << 6; | |
15968 | inst.instruction |= (fcond & 0x2) << 4; | |
15969 | inst.instruction |= inst.operands[2].reg; | |
15970 | } | |
15971 | ||
15972 | inst.is_neon = 1; | |
15973 | return; | |
15974 | } | |
15975 | ||
935295b5 AV |
15976 | static void |
15977 | do_mve_vmaxa_vmina (void) | |
15978 | { | |
15979 | if (inst.cond > COND_ALWAYS) | |
15980 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
15981 | else | |
15982 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
15983 | ||
15984 | enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); | |
15985 | struct neon_type_el et | |
15986 | = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32); | |
15987 | ||
15988 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15989 | inst.instruction |= neon_logbits (et.size) << 18; | |
15990 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15991 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15992 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15993 | inst.is_neon = 1; | |
15994 | } | |
15995 | ||
f30ee27c AV |
15996 | static void |
15997 | do_mve_vfmas (void) | |
15998 | { | |
15999 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
16000 | struct neon_type_el et | |
16001 | = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK); | |
16002 | ||
16003 | if (inst.cond > COND_ALWAYS) | |
16004 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16005 | else | |
16006 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16007 | ||
16008 | if (inst.operands[2].reg == REG_SP) | |
16009 | as_tsktsk (MVE_BAD_SP); | |
16010 | else if (inst.operands[2].reg == REG_PC) | |
16011 | as_tsktsk (MVE_BAD_PC); | |
16012 | ||
16013 | inst.instruction |= (et.size == 16) << 28; | |
16014 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16015 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16016 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16017 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16018 | inst.instruction |= inst.operands[2].reg; | |
16019 | inst.is_neon = 1; | |
16020 | } | |
16021 | ||
b409bdb6 AV |
16022 | static void |
16023 | do_mve_viddup (void) | |
16024 | { | |
16025 | if (inst.cond > COND_ALWAYS) | |
16026 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16027 | else | |
16028 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16029 | ||
16030 | unsigned imm = inst.relocs[0].exp.X_add_number; | |
16031 | constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8, | |
16032 | _("immediate must be either 1, 2, 4 or 8")); | |
16033 | ||
16034 | enum neon_shape rs; | |
16035 | struct neon_type_el et; | |
16036 | unsigned Rm; | |
16037 | if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup) | |
16038 | { | |
16039 | rs = neon_select_shape (NS_QRI, NS_NULL); | |
16040 | et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK); | |
16041 | Rm = 7; | |
16042 | } | |
16043 | else | |
16044 | { | |
16045 | constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN); | |
16046 | if (inst.operands[2].reg == REG_SP) | |
16047 | as_tsktsk (MVE_BAD_SP); | |
16048 | else if (inst.operands[2].reg == REG_PC) | |
16049 | first_error (BAD_PC); | |
16050 | ||
16051 | rs = neon_select_shape (NS_QRRI, NS_NULL); | |
16052 | et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK); | |
16053 | Rm = inst.operands[2].reg >> 1; | |
16054 | } | |
16055 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16056 | inst.instruction |= neon_logbits (et.size) << 20; | |
16057 | inst.instruction |= inst.operands[1].reg << 16; | |
16058 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16059 | inst.instruction |= (imm > 2) << 7; | |
16060 | inst.instruction |= Rm << 1; | |
16061 | inst.instruction |= (imm == 2 || imm == 8); | |
16062 | inst.is_neon = 1; | |
16063 | } | |
16064 | ||
2d78f95b AV |
16065 | static void |
16066 | do_mve_vmlas (void) | |
16067 | { | |
16068 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
16069 | struct neon_type_el et | |
16070 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
16071 | ||
16072 | if (inst.operands[2].reg == REG_PC) | |
16073 | as_tsktsk (MVE_BAD_PC); | |
16074 | else if (inst.operands[2].reg == REG_SP) | |
16075 | as_tsktsk (MVE_BAD_SP); | |
16076 | ||
16077 | if (inst.cond > COND_ALWAYS) | |
16078 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16079 | else | |
16080 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16081 | ||
16082 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16083 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16084 | inst.instruction |= neon_logbits (et.size) << 20; | |
16085 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16086 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16087 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16088 | inst.instruction |= inst.operands[2].reg; | |
16089 | inst.is_neon = 1; | |
16090 | } | |
16091 | ||
acca5630 AV |
16092 | static void |
16093 | do_mve_vshll (void) | |
16094 | { | |
16095 | struct neon_type_el et | |
16096 | = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY); | |
16097 | ||
16098 | if (inst.cond > COND_ALWAYS) | |
16099 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16100 | else | |
16101 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16102 | ||
16103 | int imm = inst.operands[2].imm; | |
16104 | constraint (imm < 1 || (unsigned)imm > et.size, | |
16105 | _("immediate value out of range")); | |
16106 | ||
16107 | if ((unsigned)imm == et.size) | |
16108 | { | |
16109 | inst.instruction |= neon_logbits (et.size) << 18; | |
16110 | inst.instruction |= 0x110001; | |
16111 | } | |
16112 | else | |
16113 | { | |
16114 | inst.instruction |= (et.size + imm) << 16; | |
16115 | inst.instruction |= 0x800140; | |
16116 | } | |
16117 | ||
16118 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16119 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16120 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16121 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16122 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16123 | inst.is_neon = 1; | |
16124 | } | |
16125 | ||
16126 | static void | |
16127 | do_mve_vshlc (void) | |
16128 | { | |
16129 | if (inst.cond > COND_ALWAYS) | |
16130 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16131 | else | |
16132 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16133 | ||
16134 | if (inst.operands[1].reg == REG_PC) | |
16135 | as_tsktsk (MVE_BAD_PC); | |
16136 | else if (inst.operands[1].reg == REG_SP) | |
16137 | as_tsktsk (MVE_BAD_SP); | |
16138 | ||
16139 | int imm = inst.operands[2].imm; | |
16140 | constraint (imm < 1 || imm > 32, _("immediate value out of range")); | |
16141 | ||
16142 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16143 | inst.instruction |= (imm & 0x1f) << 16; | |
16144 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16145 | inst.instruction |= inst.operands[1].reg; | |
16146 | inst.is_neon = 1; | |
16147 | } | |
16148 | ||
4aa88b50 AV |
16149 | static void |
16150 | do_mve_vshrn (void) | |
16151 | { | |
16152 | unsigned types; | |
16153 | switch (inst.instruction) | |
16154 | { | |
16155 | case M_MNEM_vshrnt: | |
16156 | case M_MNEM_vshrnb: | |
16157 | case M_MNEM_vrshrnt: | |
16158 | case M_MNEM_vrshrnb: | |
16159 | types = N_I16 | N_I32; | |
16160 | break; | |
16161 | case M_MNEM_vqshrnt: | |
16162 | case M_MNEM_vqshrnb: | |
16163 | case M_MNEM_vqrshrnt: | |
16164 | case M_MNEM_vqrshrnb: | |
16165 | types = N_U16 | N_U32 | N_S16 | N_S32; | |
16166 | break; | |
16167 | case M_MNEM_vqshrunt: | |
16168 | case M_MNEM_vqshrunb: | |
16169 | case M_MNEM_vqrshrunt: | |
16170 | case M_MNEM_vqrshrunb: | |
16171 | types = N_S16 | N_S32; | |
16172 | break; | |
16173 | default: | |
16174 | abort (); | |
16175 | } | |
16176 | ||
16177 | struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY); | |
16178 | ||
16179 | if (inst.cond > COND_ALWAYS) | |
16180 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16181 | else | |
16182 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16183 | ||
16184 | unsigned Qd = inst.operands[0].reg; | |
16185 | unsigned Qm = inst.operands[1].reg; | |
16186 | unsigned imm = inst.operands[2].imm; | |
16187 | constraint (imm < 1 || ((unsigned) imm) > (et.size / 2), | |
16188 | et.size == 16 | |
16189 | ? _("immediate operand expected in the range [1,8]") | |
16190 | : _("immediate operand expected in the range [1,16]")); | |
16191 | ||
16192 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16193 | inst.instruction |= HI1 (Qd) << 22; | |
16194 | inst.instruction |= (et.size - imm) << 16; | |
16195 | inst.instruction |= LOW4 (Qd) << 12; | |
16196 | inst.instruction |= HI1 (Qm) << 5; | |
16197 | inst.instruction |= LOW4 (Qm); | |
16198 | inst.is_neon = 1; | |
16199 | } | |
16200 | ||
1be7aba3 AV |
16201 | static void |
16202 | do_mve_vqmovn (void) | |
16203 | { | |
16204 | struct neon_type_el et; | |
16205 | if (inst.instruction == M_MNEM_vqmovnt | |
16206 | || inst.instruction == M_MNEM_vqmovnb) | |
16207 | et = neon_check_type (2, NS_QQ, N_EQK, | |
16208 | N_U16 | N_U32 | N_S16 | N_S32 | N_KEY); | |
16209 | else | |
16210 | et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY); | |
16211 | ||
16212 | if (inst.cond > COND_ALWAYS) | |
16213 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16214 | else | |
16215 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16216 | ||
16217 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16218 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16219 | inst.instruction |= (et.size == 32) << 18; | |
16220 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16221 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16222 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16223 | inst.is_neon = 1; | |
16224 | } | |
16225 | ||
3063888e AV |
16226 | static void |
16227 | do_mve_vpsel (void) | |
16228 | { | |
16229 | neon_select_shape (NS_QQQ, NS_NULL); | |
16230 | ||
16231 | if (inst.cond > COND_ALWAYS) | |
16232 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16233 | else | |
16234 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16235 | ||
16236 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16237 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16238 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16239 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16240 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16241 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16242 | inst.is_neon = 1; | |
16243 | } | |
16244 | ||
16245 | static void | |
16246 | do_mve_vpnot (void) | |
16247 | { | |
16248 | if (inst.cond > COND_ALWAYS) | |
16249 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16250 | else | |
16251 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16252 | } | |
16253 | ||
935295b5 AV |
16254 | static void |
16255 | do_mve_vmaxnma_vminnma (void) | |
16256 | { | |
16257 | enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); | |
16258 | struct neon_type_el et | |
16259 | = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); | |
16260 | ||
16261 | if (inst.cond > COND_ALWAYS) | |
16262 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16263 | else | |
16264 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16265 | ||
16266 | inst.instruction |= (et.size == 16) << 28; | |
16267 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16268 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16269 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16270 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16271 | inst.is_neon = 1; | |
16272 | } | |
16273 | ||
5d281bf0 AV |
16274 | static void |
16275 | do_mve_vcmul (void) | |
16276 | { | |
16277 | enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); | |
16278 | struct neon_type_el et | |
16279 | = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY); | |
16280 | ||
16281 | if (inst.cond > COND_ALWAYS) | |
16282 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16283 | else | |
16284 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16285 | ||
16286 | unsigned rot = inst.relocs[0].exp.X_add_number; | |
16287 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, | |
16288 | _("immediate out of range")); | |
16289 | ||
16290 | if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg | |
16291 | || inst.operands[0].reg == inst.operands[2].reg)) | |
16292 | as_tsktsk (BAD_MVE_SRCDEST); | |
16293 | ||
16294 | inst.instruction |= (et.size == 32) << 28; | |
16295 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16296 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16297 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16298 | inst.instruction |= (rot > 90) << 12; | |
16299 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16300 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16301 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16302 | inst.instruction |= (rot == 90 || rot == 270); | |
16303 | inst.is_neon = 1; | |
16304 | } | |
16305 | ||
1f6234a3 AV |
16306 | /* To handle the Low Overhead Loop instructions |
16307 | in Armv8.1-M Mainline and MVE. */ | |
16308 | static void | |
16309 | do_t_loloop (void) | |
16310 | { | |
16311 | unsigned long insn = inst.instruction; | |
16312 | ||
16313 | inst.instruction = THUMB_OP32 (inst.instruction); | |
16314 | ||
16315 | if (insn == T_MNEM_lctp) | |
16316 | return; | |
16317 | ||
16318 | set_pred_insn_type (MVE_OUTSIDE_PRED_INSN); | |
16319 | ||
16320 | if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp) | |
16321 | { | |
16322 | struct neon_type_el et | |
16323 | = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
16324 | inst.instruction |= neon_logbits (et.size) << 20; | |
16325 | inst.is_neon = 1; | |
16326 | } | |
16327 | ||
16328 | switch (insn) | |
16329 | { | |
16330 | case T_MNEM_letp: | |
16331 | constraint (!inst.operands[0].present, | |
16332 | _("expected LR")); | |
16333 | /* fall through. */ | |
16334 | case T_MNEM_le: | |
16335 | /* le <label>. */ | |
16336 | if (!inst.operands[0].present) | |
16337 | inst.instruction |= 1 << 21; | |
16338 | ||
16339 | v8_1_loop_reloc (TRUE); | |
16340 | break; | |
16341 | ||
16342 | case T_MNEM_wls: | |
16343 | case T_MNEM_wlstp: | |
16344 | v8_1_loop_reloc (FALSE); | |
16345 | /* fall through. */ | |
16346 | case T_MNEM_dlstp: | |
16347 | case T_MNEM_dls: | |
16348 | constraint (inst.operands[1].isreg != 1, BAD_ARGS); | |
16349 | ||
16350 | if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp) | |
16351 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
16352 | else if (inst.operands[1].reg == REG_PC) | |
16353 | as_tsktsk (MVE_BAD_PC); | |
16354 | if (inst.operands[1].reg == REG_SP) | |
16355 | as_tsktsk (MVE_BAD_SP); | |
16356 | ||
16357 | inst.instruction |= (inst.operands[1].reg << 16); | |
16358 | break; | |
16359 | ||
16360 | default: | |
16361 | abort (); | |
16362 | } | |
16363 | } | |
16364 | ||
16365 | ||
037e8744 JB |
16366 | static void |
16367 | do_vfp_nsyn_cmp (void) | |
16368 | { | |
9db2f6b4 | 16369 | enum neon_shape rs; |
1b883319 AV |
16370 | if (!inst.operands[0].isreg) |
16371 | { | |
16372 | do_mve_vcmp (); | |
16373 | return; | |
16374 | } | |
16375 | else | |
16376 | { | |
16377 | constraint (inst.operands[2].present, BAD_SYNTAX); | |
16378 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), | |
16379 | BAD_FPU); | |
16380 | } | |
16381 | ||
037e8744 JB |
16382 | if (inst.operands[1].isreg) |
16383 | { | |
9db2f6b4 RL |
16384 | rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); |
16385 | neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP); | |
5f4273c7 | 16386 | |
9db2f6b4 | 16387 | if (rs == NS_FF || rs == NS_HH) |
477330fc RM |
16388 | { |
16389 | NEON_ENCODE (SINGLE, inst); | |
16390 | do_vfp_sp_monadic (); | |
16391 | } | |
037e8744 | 16392 | else |
477330fc RM |
16393 | { |
16394 | NEON_ENCODE (DOUBLE, inst); | |
16395 | do_vfp_dp_rd_rm (); | |
16396 | } | |
037e8744 JB |
16397 | } |
16398 | else | |
16399 | { | |
9db2f6b4 RL |
16400 | rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL); |
16401 | neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK); | |
037e8744 JB |
16402 | |
16403 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
16404 | { |
16405 | case N_MNEM_vcmp: | |
16406 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
16407 | break; | |
16408 | case N_MNEM_vcmpe: | |
16409 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
16410 | break; | |
16411 | default: | |
16412 | abort (); | |
16413 | } | |
5f4273c7 | 16414 | |
9db2f6b4 | 16415 | if (rs == NS_FI || rs == NS_HI) |
477330fc RM |
16416 | { |
16417 | NEON_ENCODE (SINGLE, inst); | |
16418 | do_vfp_sp_compare_z (); | |
16419 | } | |
037e8744 | 16420 | else |
477330fc RM |
16421 | { |
16422 | NEON_ENCODE (DOUBLE, inst); | |
16423 | do_vfp_dp_rd (); | |
16424 | } | |
037e8744 JB |
16425 | } |
16426 | do_vfp_cond_or_thumb (); | |
9db2f6b4 RL |
16427 | |
16428 | /* ARMv8.2 fp16 instruction. */ | |
16429 | if (rs == NS_HI || rs == NS_HH) | |
16430 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
16431 | } |
16432 | ||
16433 | static void | |
16434 | nsyn_insert_sp (void) | |
16435 | { | |
16436 | inst.operands[1] = inst.operands[0]; | |
16437 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 16438 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
16439 | inst.operands[0].isreg = 1; |
16440 | inst.operands[0].writeback = 1; | |
16441 | inst.operands[0].present = 1; | |
16442 | } | |
16443 | ||
16444 | static void | |
16445 | do_vfp_nsyn_push (void) | |
16446 | { | |
16447 | nsyn_insert_sp (); | |
b126985e NC |
16448 | |
16449 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
16450 | _("register list must contain at least 1 and at most 16 " | |
16451 | "registers")); | |
16452 | ||
037e8744 JB |
16453 | if (inst.operands[1].issingle) |
16454 | do_vfp_nsyn_opcode ("fstmdbs"); | |
16455 | else | |
16456 | do_vfp_nsyn_opcode ("fstmdbd"); | |
16457 | } | |
16458 | ||
16459 | static void | |
16460 | do_vfp_nsyn_pop (void) | |
16461 | { | |
16462 | nsyn_insert_sp (); | |
b126985e NC |
16463 | |
16464 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
16465 | _("register list must contain at least 1 and at most 16 " | |
16466 | "registers")); | |
16467 | ||
037e8744 | 16468 | if (inst.operands[1].issingle) |
22b5b651 | 16469 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 16470 | else |
22b5b651 | 16471 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
16472 | } |
16473 | ||
16474 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
16475 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
16476 | ||
88714cb8 DG |
16477 | static void |
16478 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 16479 | { |
88714cb8 DG |
16480 | unsigned int i = insn->instruction; |
16481 | insn->is_neon = 1; | |
16482 | ||
037e8744 JB |
16483 | if (thumb_mode) |
16484 | { | |
16485 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
16486 | if (i & (1 << 24)) | |
477330fc | 16487 | i |= 1 << 28; |
5f4273c7 | 16488 | |
037e8744 | 16489 | i &= ~(1 << 24); |
5f4273c7 | 16490 | |
037e8744 JB |
16491 | i |= 0xef000000; |
16492 | } | |
16493 | else | |
16494 | i |= 0xf2000000; | |
5f4273c7 | 16495 | |
88714cb8 | 16496 | insn->instruction = i; |
037e8744 JB |
16497 | } |
16498 | ||
5ee91343 | 16499 | static void |
7df54120 | 16500 | mve_encode_qqr (int size, int U, int fp) |
5ee91343 AV |
16501 | { |
16502 | if (inst.operands[2].reg == REG_SP) | |
16503 | as_tsktsk (MVE_BAD_SP); | |
16504 | else if (inst.operands[2].reg == REG_PC) | |
16505 | as_tsktsk (MVE_BAD_PC); | |
16506 | ||
16507 | if (fp) | |
16508 | { | |
16509 | /* vadd. */ | |
16510 | if (((unsigned)inst.instruction) == 0xd00) | |
16511 | inst.instruction = 0xee300f40; | |
16512 | /* vsub. */ | |
16513 | else if (((unsigned)inst.instruction) == 0x200d00) | |
16514 | inst.instruction = 0xee301f40; | |
a8465a06 AV |
16515 | /* vmul. */ |
16516 | else if (((unsigned)inst.instruction) == 0x1000d10) | |
16517 | inst.instruction = 0xee310e60; | |
5ee91343 AV |
16518 | |
16519 | /* Setting size which is 1 for F16 and 0 for F32. */ | |
16520 | inst.instruction |= (size == 16) << 28; | |
16521 | } | |
16522 | else | |
16523 | { | |
16524 | /* vadd. */ | |
16525 | if (((unsigned)inst.instruction) == 0x800) | |
16526 | inst.instruction = 0xee010f40; | |
16527 | /* vsub. */ | |
16528 | else if (((unsigned)inst.instruction) == 0x1000800) | |
16529 | inst.instruction = 0xee011f40; | |
7df54120 AV |
16530 | /* vhadd. */ |
16531 | else if (((unsigned)inst.instruction) == 0) | |
16532 | inst.instruction = 0xee000f40; | |
16533 | /* vhsub. */ | |
16534 | else if (((unsigned)inst.instruction) == 0x200) | |
16535 | inst.instruction = 0xee001f40; | |
a8465a06 AV |
16536 | /* vmla. */ |
16537 | else if (((unsigned)inst.instruction) == 0x900) | |
16538 | inst.instruction = 0xee010e40; | |
16539 | /* vmul. */ | |
16540 | else if (((unsigned)inst.instruction) == 0x910) | |
16541 | inst.instruction = 0xee011e60; | |
16542 | /* vqadd. */ | |
16543 | else if (((unsigned)inst.instruction) == 0x10) | |
16544 | inst.instruction = 0xee000f60; | |
16545 | /* vqsub. */ | |
16546 | else if (((unsigned)inst.instruction) == 0x210) | |
16547 | inst.instruction = 0xee001f60; | |
42b16635 AV |
16548 | /* vqrdmlah. */ |
16549 | else if (((unsigned)inst.instruction) == 0x3000b10) | |
16550 | inst.instruction = 0xee000e40; | |
16551 | /* vqdmulh. */ | |
16552 | else if (((unsigned)inst.instruction) == 0x0000b00) | |
16553 | inst.instruction = 0xee010e60; | |
16554 | /* vqrdmulh. */ | |
16555 | else if (((unsigned)inst.instruction) == 0x1000b00) | |
16556 | inst.instruction = 0xfe010e60; | |
7df54120 AV |
16557 | |
16558 | /* Set U-bit. */ | |
16559 | inst.instruction |= U << 28; | |
16560 | ||
5ee91343 AV |
16561 | /* Setting bits for size. */ |
16562 | inst.instruction |= neon_logbits (size) << 20; | |
16563 | } | |
16564 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16565 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16566 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16567 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16568 | inst.instruction |= inst.operands[2].reg; | |
16569 | inst.is_neon = 1; | |
16570 | } | |
16571 | ||
a302e574 AV |
16572 | static void |
16573 | mve_encode_rqq (unsigned bit28, unsigned size) | |
16574 | { | |
16575 | inst.instruction |= bit28 << 28; | |
16576 | inst.instruction |= neon_logbits (size) << 20; | |
16577 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16578 | inst.instruction |= inst.operands[0].reg << 12; | |
16579 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16580 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16581 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16582 | inst.is_neon = 1; | |
16583 | } | |
16584 | ||
886e1c73 AV |
16585 | static void |
16586 | mve_encode_qqq (int ubit, int size) | |
16587 | { | |
16588 | ||
16589 | inst.instruction |= (ubit != 0) << 28; | |
16590 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16591 | inst.instruction |= neon_logbits (size) << 20; | |
16592 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16593 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16594 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16595 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16596 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16597 | ||
16598 | inst.is_neon = 1; | |
16599 | } | |
16600 | ||
26c1e780 AV |
16601 | static void |
16602 | mve_encode_rq (unsigned bit28, unsigned size) | |
16603 | { | |
16604 | inst.instruction |= bit28 << 28; | |
16605 | inst.instruction |= neon_logbits (size) << 18; | |
16606 | inst.instruction |= inst.operands[0].reg << 12; | |
16607 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16608 | inst.is_neon = 1; | |
16609 | } | |
886e1c73 | 16610 | |
93925576 AV |
16611 | static void |
16612 | mve_encode_rrqq (unsigned U, unsigned size) | |
16613 | { | |
16614 | constraint (inst.operands[3].reg > 14, MVE_BAD_QREG); | |
16615 | ||
16616 | inst.instruction |= U << 28; | |
16617 | inst.instruction |= (inst.operands[1].reg >> 1) << 20; | |
16618 | inst.instruction |= LOW4 (inst.operands[2].reg) << 16; | |
16619 | inst.instruction |= (size == 32) << 16; | |
16620 | inst.instruction |= inst.operands[0].reg << 12; | |
16621 | inst.instruction |= HI1 (inst.operands[2].reg) << 7; | |
16622 | inst.instruction |= inst.operands[3].reg; | |
16623 | inst.is_neon = 1; | |
16624 | } | |
16625 | ||
037e8744 JB |
16626 | /* Encode insns with bit pattern: |
16627 | ||
16628 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
16629 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 16630 | |
037e8744 JB |
16631 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
16632 | different meaning for some instruction. */ | |
16633 | ||
16634 | static void | |
16635 | neon_three_same (int isquad, int ubit, int size) | |
16636 | { | |
16637 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16638 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16639 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16640 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16641 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16642 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16643 | inst.instruction |= (isquad != 0) << 6; | |
16644 | inst.instruction |= (ubit != 0) << 24; | |
16645 | if (size != -1) | |
16646 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 16647 | |
88714cb8 | 16648 | neon_dp_fixup (&inst); |
037e8744 JB |
16649 | } |
16650 | ||
16651 | /* Encode instructions of the form: | |
16652 | ||
16653 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
16654 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
16655 | |
16656 | Don't write size if SIZE == -1. */ | |
16657 | ||
16658 | static void | |
16659 | neon_two_same (int qbit, int ubit, int size) | |
16660 | { | |
16661 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16662 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16663 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16664 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16665 | inst.instruction |= (qbit != 0) << 6; | |
16666 | inst.instruction |= (ubit != 0) << 24; | |
16667 | ||
16668 | if (size != -1) | |
16669 | inst.instruction |= neon_logbits (size) << 18; | |
16670 | ||
88714cb8 | 16671 | neon_dp_fixup (&inst); |
5287ad62 JB |
16672 | } |
16673 | ||
7df54120 AV |
16674 | enum vfp_or_neon_is_neon_bits |
16675 | { | |
16676 | NEON_CHECK_CC = 1, | |
16677 | NEON_CHECK_ARCH = 2, | |
16678 | NEON_CHECK_ARCH8 = 4 | |
16679 | }; | |
16680 | ||
16681 | /* Call this function if an instruction which may have belonged to the VFP or | |
16682 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
16683 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
16684 | things: | |
16685 | ||
16686 | - Make sure the user hasn't attempted to make a Neon instruction | |
16687 | conditional. | |
16688 | - Alter the value in the condition code field if necessary. | |
16689 | - Make sure that the arch supports Neon instructions. | |
16690 | ||
16691 | Which of these operations take place depends on bits from enum | |
16692 | vfp_or_neon_is_neon_bits. | |
16693 | ||
16694 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
16695 | current instruction's condition is COND_ALWAYS, the condition field is | |
16696 | changed to inst.uncond_value. This is necessary because instructions shared | |
16697 | between VFP and Neon may be conditional for the VFP variants only, and the | |
16698 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
16699 | ||
16700 | static int | |
16701 | vfp_or_neon_is_neon (unsigned check) | |
16702 | { | |
16703 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
16704 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
16705 | { | |
16706 | if (inst.cond != COND_ALWAYS) | |
16707 | { | |
16708 | first_error (_(BAD_COND)); | |
16709 | return FAIL; | |
16710 | } | |
16711 | if (inst.uncond_value != -1) | |
16712 | inst.instruction |= inst.uncond_value << 28; | |
16713 | } | |
16714 | ||
16715 | ||
16716 | if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1)) | |
16717 | || ((check & NEON_CHECK_ARCH8) | |
16718 | && !mark_feature_used (&fpu_neon_ext_armv8))) | |
16719 | { | |
16720 | first_error (_(BAD_FPU)); | |
16721 | return FAIL; | |
16722 | } | |
16723 | ||
16724 | return SUCCESS; | |
16725 | } | |
16726 | ||
64c350f2 AV |
16727 | |
16728 | /* Return TRUE if the SIMD instruction is available for the current | |
16729 | cpu_variant. FP is set to TRUE if this is a SIMD floating-point | |
16730 | instruction. CHECK contains th. CHECK contains the set of bits to pass to | |
16731 | vfp_or_neon_is_neon for the NEON specific checks. */ | |
16732 | ||
16733 | static bfd_boolean | |
7df54120 AV |
16734 | check_simd_pred_availability (int fp, unsigned check) |
16735 | { | |
16736 | if (inst.cond > COND_ALWAYS) | |
16737 | { | |
16738 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16739 | { | |
16740 | inst.error = BAD_FPU; | |
64c350f2 | 16741 | return FALSE; |
7df54120 AV |
16742 | } |
16743 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
16744 | } | |
16745 | else if (inst.cond < COND_ALWAYS) | |
16746 | { | |
16747 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16748 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16749 | else if (vfp_or_neon_is_neon (check) == FAIL) | |
64c350f2 | 16750 | return FALSE; |
7df54120 AV |
16751 | } |
16752 | else | |
16753 | { | |
16754 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext) | |
16755 | && vfp_or_neon_is_neon (check) == FAIL) | |
64c350f2 | 16756 | return FALSE; |
7df54120 AV |
16757 | |
16758 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16759 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
16760 | } | |
64c350f2 | 16761 | return TRUE; |
7df54120 AV |
16762 | } |
16763 | ||
5287ad62 JB |
16764 | /* Neon instruction encoders, in approximate order of appearance. */ |
16765 | ||
16766 | static void | |
16767 | do_neon_dyadic_i_su (void) | |
16768 | { | |
64c350f2 | 16769 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
7df54120 AV |
16770 | return; |
16771 | ||
16772 | enum neon_shape rs; | |
16773 | struct neon_type_el et; | |
16774 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16775 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
16776 | else | |
16777 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16778 | ||
16779 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY); | |
16780 | ||
16781 | ||
16782 | if (rs != NS_QQR) | |
16783 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16784 | else | |
16785 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); | |
5287ad62 JB |
16786 | } |
16787 | ||
16788 | static void | |
16789 | do_neon_dyadic_i64_su (void) | |
16790 | { | |
64c350f2 | 16791 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
a8465a06 AV |
16792 | return; |
16793 | enum neon_shape rs; | |
16794 | struct neon_type_el et; | |
16795 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16796 | { | |
16797 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
16798 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
16799 | } | |
16800 | else | |
16801 | { | |
16802 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16803 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
16804 | } | |
16805 | if (rs == NS_QQR) | |
16806 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); | |
16807 | else | |
16808 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
5287ad62 JB |
16809 | } |
16810 | ||
16811 | static void | |
16812 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 16813 | unsigned immbits) |
5287ad62 JB |
16814 | { |
16815 | unsigned size = et.size >> 3; | |
16816 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16817 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16818 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16819 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16820 | inst.instruction |= (isquad != 0) << 6; | |
16821 | inst.instruction |= immbits << 16; | |
16822 | inst.instruction |= (size >> 3) << 7; | |
16823 | inst.instruction |= (size & 0x7) << 19; | |
16824 | if (write_ubit) | |
16825 | inst.instruction |= (uval != 0) << 24; | |
16826 | ||
88714cb8 | 16827 | neon_dp_fixup (&inst); |
5287ad62 JB |
16828 | } |
16829 | ||
16830 | static void | |
5150f0d8 | 16831 | do_neon_shl (void) |
5287ad62 | 16832 | { |
64c350f2 | 16833 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
5150f0d8 AV |
16834 | return; |
16835 | ||
5287ad62 JB |
16836 | if (!inst.operands[2].isreg) |
16837 | { | |
5150f0d8 AV |
16838 | enum neon_shape rs; |
16839 | struct neon_type_el et; | |
16840 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16841 | { | |
16842 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
16843 | et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE); | |
16844 | } | |
16845 | else | |
16846 | { | |
16847 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
16848 | et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); | |
16849 | } | |
cb3b1e65 JB |
16850 | int imm = inst.operands[2].imm; |
16851 | ||
16852 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
16853 | _("immediate out of range for shift")); | |
88714cb8 | 16854 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 16855 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
16856 | } |
16857 | else | |
16858 | { | |
5150f0d8 AV |
16859 | enum neon_shape rs; |
16860 | struct neon_type_el et; | |
16861 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16862 | { | |
16863 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
16864 | et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK); | |
16865 | } | |
16866 | else | |
16867 | { | |
16868 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16869 | et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
16870 | } | |
16871 | ||
16872 | ||
16873 | if (rs == NS_QQR) | |
16874 | { | |
16875 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
16876 | _("invalid instruction shape")); | |
16877 | if (inst.operands[2].reg == REG_SP) | |
16878 | as_tsktsk (MVE_BAD_SP); | |
16879 | else if (inst.operands[2].reg == REG_PC) | |
16880 | as_tsktsk (MVE_BAD_PC); | |
16881 | ||
16882 | inst.instruction = 0xee311e60; | |
16883 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16884 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16885 | inst.instruction |= neon_logbits (et.size) << 18; | |
16886 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16887 | inst.instruction |= inst.operands[2].reg; | |
16888 | inst.is_neon = 1; | |
16889 | } | |
16890 | else | |
16891 | { | |
16892 | unsigned int tmp; | |
16893 | ||
16894 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
16895 | vshl.xx Dd, Dm, Dn | |
16896 | whereas other 3-register operations encoded by neon_three_same have | |
16897 | syntax like: | |
16898 | vadd.xx Dd, Dn, Dm | |
16899 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and | |
16900 | operands[2].reg here. */ | |
16901 | tmp = inst.operands[2].reg; | |
16902 | inst.operands[2].reg = inst.operands[1].reg; | |
16903 | inst.operands[1].reg = tmp; | |
16904 | NEON_ENCODE (INTEGER, inst); | |
16905 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16906 | } | |
5287ad62 JB |
16907 | } |
16908 | } | |
16909 | ||
16910 | static void | |
5150f0d8 | 16911 | do_neon_qshl (void) |
5287ad62 | 16912 | { |
64c350f2 | 16913 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
5150f0d8 AV |
16914 | return; |
16915 | ||
5287ad62 JB |
16916 | if (!inst.operands[2].isreg) |
16917 | { | |
5150f0d8 AV |
16918 | enum neon_shape rs; |
16919 | struct neon_type_el et; | |
16920 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16921 | { | |
16922 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
16923 | et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE); | |
16924 | } | |
16925 | else | |
16926 | { | |
16927 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
16928 | et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); | |
16929 | } | |
cb3b1e65 | 16930 | int imm = inst.operands[2].imm; |
627907b7 | 16931 | |
cb3b1e65 JB |
16932 | constraint (imm < 0 || (unsigned)imm >= et.size, |
16933 | _("immediate out of range for shift")); | |
88714cb8 | 16934 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 16935 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
5287ad62 JB |
16936 | } |
16937 | else | |
16938 | { | |
5150f0d8 AV |
16939 | enum neon_shape rs; |
16940 | struct neon_type_el et; | |
627907b7 | 16941 | |
5150f0d8 AV |
16942 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
16943 | { | |
16944 | rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
16945 | et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK); | |
16946 | } | |
16947 | else | |
16948 | { | |
16949 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
16950 | et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
16951 | } | |
16952 | ||
16953 | if (rs == NS_QQR) | |
16954 | { | |
16955 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
16956 | _("invalid instruction shape")); | |
16957 | if (inst.operands[2].reg == REG_SP) | |
16958 | as_tsktsk (MVE_BAD_SP); | |
16959 | else if (inst.operands[2].reg == REG_PC) | |
16960 | as_tsktsk (MVE_BAD_PC); | |
16961 | ||
16962 | inst.instruction = 0xee311ee0; | |
16963 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
16964 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16965 | inst.instruction |= neon_logbits (et.size) << 18; | |
16966 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16967 | inst.instruction |= inst.operands[2].reg; | |
16968 | inst.is_neon = 1; | |
16969 | } | |
16970 | else | |
16971 | { | |
16972 | unsigned int tmp; | |
16973 | ||
16974 | /* See note in do_neon_shl. */ | |
16975 | tmp = inst.operands[2].reg; | |
16976 | inst.operands[2].reg = inst.operands[1].reg; | |
16977 | inst.operands[1].reg = tmp; | |
16978 | NEON_ENCODE (INTEGER, inst); | |
16979 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
16980 | } | |
5287ad62 JB |
16981 | } |
16982 | } | |
16983 | ||
627907b7 JB |
16984 | static void |
16985 | do_neon_rshl (void) | |
16986 | { | |
64c350f2 | 16987 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
1be7aba3 AV |
16988 | return; |
16989 | ||
16990 | enum neon_shape rs; | |
16991 | struct neon_type_el et; | |
16992 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
16993 | { | |
16994 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
16995 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
16996 | } | |
16997 | else | |
16998 | { | |
16999 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
17000 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
17001 | } | |
17002 | ||
627907b7 JB |
17003 | unsigned int tmp; |
17004 | ||
1be7aba3 AV |
17005 | if (rs == NS_QQR) |
17006 | { | |
17007 | if (inst.operands[2].reg == REG_PC) | |
17008 | as_tsktsk (MVE_BAD_PC); | |
17009 | else if (inst.operands[2].reg == REG_SP) | |
17010 | as_tsktsk (MVE_BAD_SP); | |
17011 | ||
17012 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
17013 | _("invalid instruction shape")); | |
17014 | ||
17015 | if (inst.instruction == 0x0000510) | |
17016 | /* We are dealing with vqrshl. */ | |
17017 | inst.instruction = 0xee331ee0; | |
17018 | else | |
17019 | /* We are dealing with vrshl. */ | |
17020 | inst.instruction = 0xee331e60; | |
17021 | ||
17022 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
17023 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17024 | inst.instruction |= neon_logbits (et.size) << 18; | |
17025 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17026 | inst.instruction |= inst.operands[2].reg; | |
17027 | inst.is_neon = 1; | |
17028 | } | |
17029 | else | |
17030 | { | |
17031 | tmp = inst.operands[2].reg; | |
17032 | inst.operands[2].reg = inst.operands[1].reg; | |
17033 | inst.operands[1].reg = tmp; | |
17034 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
17035 | } | |
627907b7 JB |
17036 | } |
17037 | ||
5287ad62 JB |
17038 | static int |
17039 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
17040 | { | |
036dc3f7 PB |
17041 | /* Handle .I8 pseudo-instructions. */ |
17042 | if (size == 8) | |
5287ad62 | 17043 | { |
5287ad62 | 17044 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
17045 | FIXME is this the intended semantics? There doesn't seem much point in |
17046 | accepting .I8 if so. */ | |
5287ad62 JB |
17047 | immediate |= immediate << 8; |
17048 | size = 16; | |
036dc3f7 PB |
17049 | } |
17050 | ||
17051 | if (size >= 32) | |
17052 | { | |
17053 | if (immediate == (immediate & 0x000000ff)) | |
17054 | { | |
17055 | *immbits = immediate; | |
17056 | return 0x1; | |
17057 | } | |
17058 | else if (immediate == (immediate & 0x0000ff00)) | |
17059 | { | |
17060 | *immbits = immediate >> 8; | |
17061 | return 0x3; | |
17062 | } | |
17063 | else if (immediate == (immediate & 0x00ff0000)) | |
17064 | { | |
17065 | *immbits = immediate >> 16; | |
17066 | return 0x5; | |
17067 | } | |
17068 | else if (immediate == (immediate & 0xff000000)) | |
17069 | { | |
17070 | *immbits = immediate >> 24; | |
17071 | return 0x7; | |
17072 | } | |
17073 | if ((immediate & 0xffff) != (immediate >> 16)) | |
17074 | goto bad_immediate; | |
17075 | immediate &= 0xffff; | |
5287ad62 JB |
17076 | } |
17077 | ||
17078 | if (immediate == (immediate & 0x000000ff)) | |
17079 | { | |
17080 | *immbits = immediate; | |
036dc3f7 | 17081 | return 0x9; |
5287ad62 JB |
17082 | } |
17083 | else if (immediate == (immediate & 0x0000ff00)) | |
17084 | { | |
17085 | *immbits = immediate >> 8; | |
036dc3f7 | 17086 | return 0xb; |
5287ad62 JB |
17087 | } |
17088 | ||
17089 | bad_immediate: | |
dcbf9037 | 17090 | first_error (_("immediate value out of range")); |
5287ad62 JB |
17091 | return FAIL; |
17092 | } | |
17093 | ||
5287ad62 JB |
17094 | static void |
17095 | do_neon_logic (void) | |
17096 | { | |
17097 | if (inst.operands[2].present && inst.operands[2].isreg) | |
17098 | { | |
037e8744 | 17099 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
f601a00c | 17100 | if (rs == NS_QQQ |
64c350f2 AV |
17101 | && !check_simd_pred_availability (FALSE, |
17102 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
f601a00c AV |
17103 | return; |
17104 | else if (rs != NS_QQQ | |
17105 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
17106 | first_error (BAD_FPU); | |
17107 | ||
5287ad62 JB |
17108 | neon_check_type (3, rs, N_IGNORE_TYPE); |
17109 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 17110 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 17111 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
17112 | } |
17113 | else | |
17114 | { | |
4316f0d2 DG |
17115 | const int three_ops_form = (inst.operands[2].present |
17116 | && !inst.operands[2].isreg); | |
17117 | const int immoperand = (three_ops_form ? 2 : 1); | |
17118 | enum neon_shape rs = (three_ops_form | |
17119 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
17120 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
f601a00c AV |
17121 | /* Because neon_select_shape makes the second operand a copy of the first |
17122 | if the second operand is not present. */ | |
17123 | if (rs == NS_QQI | |
64c350f2 AV |
17124 | && !check_simd_pred_availability (FALSE, |
17125 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
f601a00c AV |
17126 | return; |
17127 | else if (rs != NS_QQI | |
17128 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
17129 | first_error (BAD_FPU); | |
17130 | ||
17131 | struct neon_type_el et; | |
17132 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17133 | et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK); | |
17134 | else | |
17135 | et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | |
17136 | | N_KEY, N_EQK); | |
17137 | ||
17138 | if (et.type == NT_invtype) | |
17139 | return; | |
21d799b5 | 17140 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
17141 | unsigned immbits; |
17142 | int cmode; | |
5f4273c7 | 17143 | |
5f4273c7 | 17144 | |
4316f0d2 DG |
17145 | if (three_ops_form) |
17146 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
17147 | _("first and second operands shall be the same register")); | |
17148 | ||
88714cb8 | 17149 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 17150 | |
4316f0d2 | 17151 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
17152 | if (et.size == 64) |
17153 | { | |
17154 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
17155 | pattern. */ | |
4316f0d2 DG |
17156 | if (immbits != (inst.operands[immoperand].regisimm ? |
17157 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
17158 | { |
17159 | /* Set immbits to an invalid constant. */ | |
17160 | immbits = 0xdeadbeef; | |
17161 | } | |
17162 | } | |
17163 | ||
5287ad62 | 17164 | switch (opcode) |
477330fc RM |
17165 | { |
17166 | case N_MNEM_vbic: | |
17167 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17168 | break; | |
17169 | ||
17170 | case N_MNEM_vorr: | |
17171 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17172 | break; | |
17173 | ||
17174 | case N_MNEM_vand: | |
17175 | /* Pseudo-instruction for VBIC. */ | |
17176 | neon_invert_size (&immbits, 0, et.size); | |
17177 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17178 | break; | |
17179 | ||
17180 | case N_MNEM_vorn: | |
17181 | /* Pseudo-instruction for VORR. */ | |
17182 | neon_invert_size (&immbits, 0, et.size); | |
17183 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
17184 | break; | |
17185 | ||
17186 | default: | |
17187 | abort (); | |
17188 | } | |
5287ad62 JB |
17189 | |
17190 | if (cmode == FAIL) | |
477330fc | 17191 | return; |
5287ad62 | 17192 | |
037e8744 | 17193 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
17194 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
17195 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17196 | inst.instruction |= cmode << 8; | |
17197 | neon_write_immbits (immbits); | |
5f4273c7 | 17198 | |
88714cb8 | 17199 | neon_dp_fixup (&inst); |
5287ad62 JB |
17200 | } |
17201 | } | |
17202 | ||
17203 | static void | |
17204 | do_neon_bitfield (void) | |
17205 | { | |
037e8744 | 17206 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 17207 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 17208 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
17209 | } |
17210 | ||
17211 | static void | |
dcbf9037 | 17212 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 17213 | unsigned destbits) |
5287ad62 | 17214 | { |
5ee91343 | 17215 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
dcbf9037 | 17216 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 17217 | types | N_KEY); |
5287ad62 JB |
17218 | if (et.type == NT_float) |
17219 | { | |
88714cb8 | 17220 | NEON_ENCODE (FLOAT, inst); |
5ee91343 | 17221 | if (rs == NS_QQR) |
7df54120 | 17222 | mve_encode_qqr (et.size, 0, 1); |
5ee91343 AV |
17223 | else |
17224 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); | |
5287ad62 JB |
17225 | } |
17226 | else | |
17227 | { | |
88714cb8 | 17228 | NEON_ENCODE (INTEGER, inst); |
5ee91343 | 17229 | if (rs == NS_QQR) |
a8465a06 | 17230 | mve_encode_qqr (et.size, et.type == ubit_meaning, 0); |
5ee91343 AV |
17231 | else |
17232 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); | |
5287ad62 JB |
17233 | } |
17234 | } | |
17235 | ||
5287ad62 JB |
17236 | |
17237 | static void | |
17238 | do_neon_dyadic_if_su_d (void) | |
17239 | { | |
17240 | /* This version only allow D registers, but that constraint is enforced during | |
17241 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 17242 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
17243 | } |
17244 | ||
5287ad62 JB |
17245 | static void |
17246 | do_neon_dyadic_if_i_d (void) | |
17247 | { | |
428e3f1f PB |
17248 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
17249 | affected if we specify unsigned args. */ | |
17250 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
17251 | } |
17252 | ||
f5f10c66 AV |
17253 | static void |
17254 | do_mve_vstr_vldr_QI (int size, int elsize, int load) | |
17255 | { | |
17256 | constraint (size < 32, BAD_ADDR_MODE); | |
17257 | constraint (size != elsize, BAD_EL_TYPE); | |
17258 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); | |
17259 | constraint (!inst.operands[1].preind, BAD_ADDR_MODE); | |
17260 | constraint (load && inst.operands[0].reg == inst.operands[1].reg, | |
17261 | _("destination register and offset register may not be the" | |
17262 | " same")); | |
17263 | ||
17264 | int imm = inst.relocs[0].exp.X_add_number; | |
17265 | int add = 1; | |
17266 | if (imm < 0) | |
17267 | { | |
17268 | add = 0; | |
17269 | imm = -imm; | |
17270 | } | |
17271 | constraint ((imm % (size / 8) != 0) | |
17272 | || imm > (0x7f << neon_logbits (size)), | |
17273 | (size == 32) ? _("immediate must be a multiple of 4 in the" | |
17274 | " range of +/-[0,508]") | |
17275 | : _("immediate must be a multiple of 8 in the" | |
17276 | " range of +/-[0,1016]")); | |
17277 | inst.instruction |= 0x11 << 24; | |
17278 | inst.instruction |= add << 23; | |
17279 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17280 | inst.instruction |= inst.operands[1].writeback << 21; | |
17281 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17282 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17283 | inst.instruction |= 1 << 12; | |
17284 | inst.instruction |= (size == 64) << 8; | |
17285 | inst.instruction &= 0xffffff00; | |
17286 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
17287 | inst.instruction |= imm >> neon_logbits (size); | |
17288 | } | |
17289 | ||
17290 | static void | |
17291 | do_mve_vstr_vldr_RQ (int size, int elsize, int load) | |
17292 | { | |
17293 | unsigned os = inst.operands[1].imm >> 5; | |
e449ea97 | 17294 | unsigned type = inst.vectype.el[0].type; |
f5f10c66 AV |
17295 | constraint (os != 0 && size == 8, |
17296 | _("can not shift offsets when accessing less than half-word")); | |
17297 | constraint (os && os != neon_logbits (size), | |
17298 | _("shift immediate must be 1, 2 or 3 for half-word, word" | |
17299 | " or double-word accesses respectively")); | |
17300 | if (inst.operands[1].reg == REG_PC) | |
17301 | as_tsktsk (MVE_BAD_PC); | |
17302 | ||
17303 | switch (size) | |
17304 | { | |
17305 | case 8: | |
17306 | constraint (elsize >= 64, BAD_EL_TYPE); | |
17307 | break; | |
17308 | case 16: | |
17309 | constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); | |
17310 | break; | |
17311 | case 32: | |
17312 | case 64: | |
17313 | constraint (elsize != size, BAD_EL_TYPE); | |
17314 | break; | |
17315 | default: | |
17316 | break; | |
17317 | } | |
17318 | constraint (inst.operands[1].writeback || !inst.operands[1].preind, | |
17319 | BAD_ADDR_MODE); | |
17320 | if (load) | |
17321 | { | |
17322 | constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f), | |
17323 | _("destination register and offset register may not be" | |
17324 | " the same")); | |
e449ea97 SP |
17325 | constraint (size == elsize && type == NT_signed, BAD_EL_TYPE); |
17326 | constraint (size != elsize && type != NT_unsigned && type != NT_signed, | |
f5f10c66 | 17327 | BAD_EL_TYPE); |
e449ea97 | 17328 | inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28; |
f5f10c66 AV |
17329 | } |
17330 | else | |
17331 | { | |
e449ea97 | 17332 | constraint (type != NT_untyped, BAD_EL_TYPE); |
f5f10c66 AV |
17333 | } |
17334 | ||
17335 | inst.instruction |= 1 << 23; | |
17336 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17337 | inst.instruction |= inst.operands[1].reg << 16; | |
17338 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17339 | inst.instruction |= neon_logbits (elsize) << 7; | |
17340 | inst.instruction |= HI1 (inst.operands[1].imm) << 5; | |
17341 | inst.instruction |= LOW4 (inst.operands[1].imm); | |
17342 | inst.instruction |= !!os; | |
17343 | } | |
17344 | ||
17345 | static void | |
17346 | do_mve_vstr_vldr_RI (int size, int elsize, int load) | |
17347 | { | |
17348 | enum neon_el_type type = inst.vectype.el[0].type; | |
17349 | ||
17350 | constraint (size >= 64, BAD_ADDR_MODE); | |
17351 | switch (size) | |
17352 | { | |
17353 | case 16: | |
17354 | constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); | |
17355 | break; | |
17356 | case 32: | |
17357 | constraint (elsize != size, BAD_EL_TYPE); | |
17358 | break; | |
17359 | default: | |
17360 | break; | |
17361 | } | |
17362 | if (load) | |
17363 | { | |
17364 | constraint (elsize != size && type != NT_unsigned | |
17365 | && type != NT_signed, BAD_EL_TYPE); | |
17366 | } | |
17367 | else | |
17368 | { | |
17369 | constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE); | |
17370 | } | |
17371 | ||
17372 | int imm = inst.relocs[0].exp.X_add_number; | |
17373 | int add = 1; | |
17374 | if (imm < 0) | |
17375 | { | |
17376 | add = 0; | |
17377 | imm = -imm; | |
17378 | } | |
17379 | ||
17380 | if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size))) | |
17381 | { | |
17382 | switch (size) | |
17383 | { | |
17384 | case 8: | |
17385 | constraint (1, _("immediate must be in the range of +/-[0,127]")); | |
17386 | break; | |
17387 | case 16: | |
17388 | constraint (1, _("immediate must be a multiple of 2 in the" | |
17389 | " range of +/-[0,254]")); | |
17390 | break; | |
17391 | case 32: | |
17392 | constraint (1, _("immediate must be a multiple of 4 in the" | |
17393 | " range of +/-[0,508]")); | |
17394 | break; | |
17395 | } | |
17396 | } | |
17397 | ||
17398 | if (size != elsize) | |
17399 | { | |
17400 | constraint (inst.operands[1].reg > 7, BAD_HIREG); | |
17401 | constraint (inst.operands[0].reg > 14, | |
17402 | _("MVE vector register in the range [Q0..Q7] expected")); | |
17403 | inst.instruction |= (load && type == NT_unsigned) << 28; | |
17404 | inst.instruction |= (size == 16) << 19; | |
17405 | inst.instruction |= neon_logbits (elsize) << 7; | |
17406 | } | |
17407 | else | |
17408 | { | |
17409 | if (inst.operands[1].reg == REG_PC) | |
17410 | as_tsktsk (MVE_BAD_PC); | |
17411 | else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback) | |
17412 | as_tsktsk (MVE_BAD_SP); | |
17413 | inst.instruction |= 1 << 12; | |
17414 | inst.instruction |= neon_logbits (size) << 7; | |
17415 | } | |
17416 | inst.instruction |= inst.operands[1].preind << 24; | |
17417 | inst.instruction |= add << 23; | |
17418 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17419 | inst.instruction |= inst.operands[1].writeback << 21; | |
17420 | inst.instruction |= inst.operands[1].reg << 16; | |
17421 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17422 | inst.instruction &= 0xffffff80; | |
17423 | inst.instruction |= imm >> neon_logbits (size); | |
17424 | ||
17425 | } | |
17426 | ||
17427 | static void | |
17428 | do_mve_vstr_vldr (void) | |
17429 | { | |
17430 | unsigned size; | |
17431 | int load = 0; | |
17432 | ||
17433 | if (inst.cond > COND_ALWAYS) | |
17434 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17435 | else | |
17436 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17437 | ||
17438 | switch (inst.instruction) | |
17439 | { | |
17440 | default: | |
17441 | gas_assert (0); | |
17442 | break; | |
17443 | case M_MNEM_vldrb: | |
17444 | load = 1; | |
17445 | /* fall through. */ | |
17446 | case M_MNEM_vstrb: | |
17447 | size = 8; | |
17448 | break; | |
17449 | case M_MNEM_vldrh: | |
17450 | load = 1; | |
17451 | /* fall through. */ | |
17452 | case M_MNEM_vstrh: | |
17453 | size = 16; | |
17454 | break; | |
17455 | case M_MNEM_vldrw: | |
17456 | load = 1; | |
17457 | /* fall through. */ | |
17458 | case M_MNEM_vstrw: | |
17459 | size = 32; | |
17460 | break; | |
17461 | case M_MNEM_vldrd: | |
17462 | load = 1; | |
17463 | /* fall through. */ | |
17464 | case M_MNEM_vstrd: | |
17465 | size = 64; | |
17466 | break; | |
17467 | } | |
17468 | unsigned elsize = inst.vectype.el[0].size; | |
17469 | ||
17470 | if (inst.operands[1].isquad) | |
17471 | { | |
17472 | /* We are dealing with [Q, imm]{!} cases. */ | |
17473 | do_mve_vstr_vldr_QI (size, elsize, load); | |
17474 | } | |
17475 | else | |
17476 | { | |
17477 | if (inst.operands[1].immisreg == 2) | |
17478 | { | |
17479 | /* We are dealing with [R, Q, {UXTW #os}] cases. */ | |
17480 | do_mve_vstr_vldr_RQ (size, elsize, load); | |
17481 | } | |
17482 | else if (!inst.operands[1].immisreg) | |
17483 | { | |
17484 | /* We are dealing with [R, Imm]{!}/[R], Imm cases. */ | |
17485 | do_mve_vstr_vldr_RI (size, elsize, load); | |
17486 | } | |
17487 | else | |
17488 | constraint (1, BAD_ADDR_MODE); | |
17489 | } | |
17490 | ||
17491 | inst.is_neon = 1; | |
17492 | } | |
17493 | ||
35c228db AV |
17494 | static void |
17495 | do_mve_vst_vld (void) | |
17496 | { | |
17497 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17498 | return; | |
17499 | ||
17500 | constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0 | |
17501 | || inst.relocs[0].exp.X_add_number != 0 | |
17502 | || inst.operands[1].immisreg != 0, | |
17503 | BAD_ADDR_MODE); | |
17504 | constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE); | |
17505 | if (inst.operands[1].reg == REG_PC) | |
17506 | as_tsktsk (MVE_BAD_PC); | |
17507 | else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback) | |
17508 | as_tsktsk (MVE_BAD_SP); | |
17509 | ||
17510 | ||
17511 | /* These instructions are one of the "exceptions" mentioned in | |
17512 | handle_pred_state. They are MVE instructions that are not VPT compatible | |
17513 | and do not accept a VPT code, thus appending such a code is a syntax | |
17514 | error. */ | |
17515 | if (inst.cond > COND_ALWAYS) | |
17516 | first_error (BAD_SYNTAX); | |
17517 | /* If we append a scalar condition code we can set this to | |
17518 | MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */ | |
17519 | else if (inst.cond < COND_ALWAYS) | |
17520 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17521 | else | |
17522 | inst.pred_insn_type = MVE_UNPREDICABLE_INSN; | |
17523 | ||
17524 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17525 | inst.instruction |= inst.operands[1].writeback << 21; | |
17526 | inst.instruction |= inst.operands[1].reg << 16; | |
17527 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17528 | inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7; | |
17529 | inst.is_neon = 1; | |
17530 | } | |
17531 | ||
26c1e780 AV |
17532 | static void |
17533 | do_mve_vaddlv (void) | |
17534 | { | |
17535 | enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL); | |
17536 | struct neon_type_el et | |
17537 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY); | |
17538 | ||
17539 | if (et.type == NT_invtype) | |
17540 | first_error (BAD_EL_TYPE); | |
17541 | ||
17542 | if (inst.cond > COND_ALWAYS) | |
17543 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17544 | else | |
17545 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17546 | ||
17547 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
17548 | ||
17549 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
17550 | inst.instruction |= inst.operands[1].reg << 19; | |
17551 | inst.instruction |= inst.operands[0].reg << 12; | |
17552 | inst.instruction |= inst.operands[2].reg; | |
17553 | inst.is_neon = 1; | |
17554 | } | |
17555 | ||
5287ad62 | 17556 | static void |
5ee91343 | 17557 | do_neon_dyadic_if_su (void) |
5287ad62 | 17558 | { |
5ee91343 AV |
17559 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
17560 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, | |
17561 | N_SUF_32 | N_KEY); | |
17562 | ||
935295b5 AV |
17563 | constraint ((inst.instruction == ((unsigned) N_MNEM_vmax) |
17564 | || inst.instruction == ((unsigned) N_MNEM_vmin)) | |
17565 | && et.type == NT_float | |
17566 | && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU); | |
17567 | ||
64c350f2 AV |
17568 | if (!check_simd_pred_availability (et.type == NT_float, |
17569 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
037e8744 JB |
17570 | return; |
17571 | ||
5ee91343 AV |
17572 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
17573 | } | |
17574 | ||
17575 | static void | |
17576 | do_neon_addsub_if_i (void) | |
17577 | { | |
17578 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) | |
17579 | && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) | |
037e8744 JB |
17580 | return; |
17581 | ||
5ee91343 AV |
17582 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); |
17583 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, | |
17584 | N_EQK, N_IF_32 | N_I64 | N_KEY); | |
17585 | ||
17586 | constraint (rs == NS_QQR && et.size == 64, BAD_FPU); | |
17587 | /* If we are parsing Q registers and the element types match MVE, which NEON | |
17588 | also supports, then we must check whether this is an instruction that can | |
17589 | be used by both MVE/NEON. This distinction can be made based on whether | |
17590 | they are predicated or not. */ | |
17591 | if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64) | |
17592 | { | |
64c350f2 AV |
17593 | if (!check_simd_pred_availability (et.type == NT_float, |
17594 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
5ee91343 AV |
17595 | return; |
17596 | } | |
17597 | else | |
17598 | { | |
17599 | /* If they are either in a D register or are using an unsupported. */ | |
17600 | if (rs != NS_QQR | |
17601 | && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
17602 | return; | |
17603 | } | |
17604 | ||
5287ad62 JB |
17605 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
17606 | affected if we specify unsigned args. */ | |
dcbf9037 | 17607 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
17608 | } |
17609 | ||
17610 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
17611 | result to be: | |
17612 | V<op> A,B (A is operand 0, B is operand 2) | |
17613 | to mean: | |
17614 | V<op> A,B,A | |
17615 | not: | |
17616 | V<op> A,B,B | |
17617 | so handle that case specially. */ | |
17618 | ||
17619 | static void | |
17620 | neon_exchange_operands (void) | |
17621 | { | |
5287ad62 JB |
17622 | if (inst.operands[1].present) |
17623 | { | |
e1fa0163 NC |
17624 | void *scratch = xmalloc (sizeof (inst.operands[0])); |
17625 | ||
5287ad62 JB |
17626 | /* Swap operands[1] and operands[2]. */ |
17627 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
17628 | inst.operands[1] = inst.operands[2]; | |
17629 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
e1fa0163 | 17630 | free (scratch); |
5287ad62 JB |
17631 | } |
17632 | else | |
17633 | { | |
17634 | inst.operands[1] = inst.operands[2]; | |
17635 | inst.operands[2] = inst.operands[0]; | |
17636 | } | |
17637 | } | |
17638 | ||
17639 | static void | |
17640 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
17641 | { | |
17642 | if (inst.operands[2].isreg) | |
17643 | { | |
17644 | if (invert) | |
477330fc | 17645 | neon_exchange_operands (); |
dcbf9037 | 17646 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
17647 | } |
17648 | else | |
17649 | { | |
037e8744 | 17650 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 17651 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 17652 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 17653 | |
88714cb8 | 17654 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
17655 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
17656 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17657 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
17658 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 17659 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
17660 | inst.instruction |= (et.type == NT_float) << 10; |
17661 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 17662 | |
88714cb8 | 17663 | neon_dp_fixup (&inst); |
5287ad62 JB |
17664 | } |
17665 | } | |
17666 | ||
17667 | static void | |
17668 | do_neon_cmp (void) | |
17669 | { | |
cc933301 | 17670 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE); |
5287ad62 JB |
17671 | } |
17672 | ||
17673 | static void | |
17674 | do_neon_cmp_inv (void) | |
17675 | { | |
cc933301 | 17676 | neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE); |
5287ad62 JB |
17677 | } |
17678 | ||
17679 | static void | |
17680 | do_neon_ceq (void) | |
17681 | { | |
17682 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
17683 | } | |
17684 | ||
17685 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
17686 | scalars, which are encoded in 5 bits, M : Rm. | |
17687 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
17688 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
c604a79a JW |
17689 | index in M. |
17690 | ||
17691 | Dot Product instructions are similar to multiply instructions except elsize | |
17692 | should always be 32. | |
17693 | ||
17694 | This function translates SCALAR, which is GAS's internal encoding of indexed | |
17695 | scalar register, to raw encoding. There is also register and index range | |
17696 | check based on ELSIZE. */ | |
5287ad62 JB |
17697 | |
17698 | static unsigned | |
17699 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
17700 | { | |
dcbf9037 JB |
17701 | unsigned regno = NEON_SCALAR_REG (scalar); |
17702 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
17703 | |
17704 | switch (elsize) | |
17705 | { | |
17706 | case 16: | |
17707 | if (regno > 7 || elno > 3) | |
477330fc | 17708 | goto bad_scalar; |
5287ad62 | 17709 | return regno | (elno << 3); |
5f4273c7 | 17710 | |
5287ad62 JB |
17711 | case 32: |
17712 | if (regno > 15 || elno > 1) | |
477330fc | 17713 | goto bad_scalar; |
5287ad62 JB |
17714 | return regno | (elno << 4); |
17715 | ||
17716 | default: | |
17717 | bad_scalar: | |
dcbf9037 | 17718 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
17719 | } |
17720 | ||
17721 | return 0; | |
17722 | } | |
17723 | ||
17724 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
17725 | ||
17726 | static void | |
17727 | neon_mul_mac (struct neon_type_el et, int ubit) | |
17728 | { | |
dcbf9037 JB |
17729 | unsigned scalar; |
17730 | ||
17731 | /* Give a more helpful error message if we have an invalid type. */ | |
17732 | if (et.type == NT_invtype) | |
17733 | return; | |
5f4273c7 | 17734 | |
dcbf9037 | 17735 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
17736 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
17737 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17738 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17739 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
17740 | inst.instruction |= LOW4 (scalar); | |
17741 | inst.instruction |= HI1 (scalar) << 5; | |
17742 | inst.instruction |= (et.type == NT_float) << 8; | |
17743 | inst.instruction |= neon_logbits (et.size) << 20; | |
17744 | inst.instruction |= (ubit != 0) << 24; | |
17745 | ||
88714cb8 | 17746 | neon_dp_fixup (&inst); |
5287ad62 JB |
17747 | } |
17748 | ||
17749 | static void | |
17750 | do_neon_mac_maybe_scalar (void) | |
17751 | { | |
037e8744 JB |
17752 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
17753 | return; | |
17754 | ||
64c350f2 | 17755 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
037e8744 JB |
17756 | return; |
17757 | ||
5287ad62 JB |
17758 | if (inst.operands[2].isscalar) |
17759 | { | |
a8465a06 | 17760 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
037e8744 | 17761 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 17762 | struct neon_type_el et = neon_check_type (3, rs, |
589a7d88 | 17763 | N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY); |
88714cb8 | 17764 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 17765 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 | 17766 | } |
a8465a06 AV |
17767 | else if (!inst.operands[2].isvec) |
17768 | { | |
17769 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
17770 | ||
17771 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
17772 | neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
17773 | ||
17774 | neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0); | |
17775 | } | |
5287ad62 | 17776 | else |
428e3f1f | 17777 | { |
a8465a06 | 17778 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
428e3f1f PB |
17779 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
17780 | affected if we specify unsigned args. */ | |
17781 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
17782 | } | |
5287ad62 JB |
17783 | } |
17784 | ||
62f3b8c8 PB |
17785 | static void |
17786 | do_neon_fmac (void) | |
17787 | { | |
d58196e0 AV |
17788 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma) |
17789 | && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
62f3b8c8 PB |
17790 | return; |
17791 | ||
64c350f2 | 17792 | if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
62f3b8c8 PB |
17793 | return; |
17794 | ||
d58196e0 AV |
17795 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
17796 | { | |
17797 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
17798 | struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, | |
17799 | N_EQK); | |
17800 | ||
17801 | if (rs == NS_QQR) | |
17802 | { | |
17803 | if (inst.operands[2].reg == REG_SP) | |
17804 | as_tsktsk (MVE_BAD_SP); | |
17805 | else if (inst.operands[2].reg == REG_PC) | |
17806 | as_tsktsk (MVE_BAD_PC); | |
17807 | ||
17808 | inst.instruction = 0xee310e40; | |
17809 | inst.instruction |= (et.size == 16) << 28; | |
17810 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
17811 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
17812 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
17813 | inst.instruction |= HI1 (inst.operands[1].reg) << 6; | |
17814 | inst.instruction |= inst.operands[2].reg; | |
17815 | inst.is_neon = 1; | |
17816 | return; | |
17817 | } | |
17818 | } | |
17819 | else | |
17820 | { | |
17821 | constraint (!inst.operands[2].isvec, BAD_FPU); | |
17822 | } | |
17823 | ||
62f3b8c8 PB |
17824 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); |
17825 | } | |
17826 | ||
5287ad62 JB |
17827 | static void |
17828 | do_neon_tst (void) | |
17829 | { | |
037e8744 | 17830 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
17831 | struct neon_type_el et = neon_check_type (3, rs, |
17832 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 17833 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
17834 | } |
17835 | ||
17836 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
17837 | same types as the MAC equivalents. The polynomial type for this instruction | |
17838 | is encoded the same as the integer type. */ | |
17839 | ||
17840 | static void | |
17841 | do_neon_mul (void) | |
17842 | { | |
037e8744 JB |
17843 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
17844 | return; | |
17845 | ||
64c350f2 | 17846 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
037e8744 JB |
17847 | return; |
17848 | ||
5287ad62 | 17849 | if (inst.operands[2].isscalar) |
a8465a06 AV |
17850 | { |
17851 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
17852 | do_neon_mac_maybe_scalar (); | |
17853 | } | |
5287ad62 | 17854 | else |
a8465a06 AV |
17855 | { |
17856 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17857 | { | |
17858 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
17859 | struct neon_type_el et | |
17860 | = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY); | |
17861 | if (et.type == NT_float) | |
17862 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), | |
17863 | BAD_FPU); | |
17864 | ||
17865 | neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0); | |
17866 | } | |
17867 | else | |
17868 | { | |
17869 | constraint (!inst.operands[2].isvec, BAD_FPU); | |
17870 | neon_dyadic_misc (NT_poly, | |
17871 | N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0); | |
17872 | } | |
17873 | } | |
5287ad62 JB |
17874 | } |
17875 | ||
17876 | static void | |
17877 | do_neon_qdmulh (void) | |
17878 | { | |
64c350f2 | 17879 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
42b16635 AV |
17880 | return; |
17881 | ||
5287ad62 JB |
17882 | if (inst.operands[2].isscalar) |
17883 | { | |
42b16635 | 17884 | constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); |
037e8744 | 17885 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 17886 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 17887 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 17888 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 17889 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
17890 | } |
17891 | else | |
17892 | { | |
42b16635 AV |
17893 | enum neon_shape rs; |
17894 | struct neon_type_el et; | |
17895 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
17896 | { | |
17897 | rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); | |
17898 | et = neon_check_type (3, rs, | |
17899 | N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
17900 | } | |
17901 | else | |
17902 | { | |
17903 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
17904 | et = neon_check_type (3, rs, | |
17905 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
17906 | } | |
17907 | ||
88714cb8 | 17908 | NEON_ENCODE (INTEGER, inst); |
42b16635 AV |
17909 | if (rs == NS_QQR) |
17910 | mve_encode_qqr (et.size, 0, 0); | |
17911 | else | |
17912 | /* The U bit (rounding) comes from bit mask. */ | |
17913 | neon_three_same (neon_quad (rs), 0, et.size); | |
5287ad62 JB |
17914 | } |
17915 | } | |
17916 | ||
26c1e780 AV |
17917 | static void |
17918 | do_mve_vaddv (void) | |
17919 | { | |
17920 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); | |
17921 | struct neon_type_el et | |
17922 | = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); | |
17923 | ||
17924 | if (et.type == NT_invtype) | |
17925 | first_error (BAD_EL_TYPE); | |
17926 | ||
17927 | if (inst.cond > COND_ALWAYS) | |
17928 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17929 | else | |
17930 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17931 | ||
17932 | constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); | |
17933 | ||
17934 | mve_encode_rq (et.type == NT_unsigned, et.size); | |
17935 | } | |
17936 | ||
7df54120 AV |
17937 | static void |
17938 | do_mve_vhcadd (void) | |
17939 | { | |
17940 | enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); | |
17941 | struct neon_type_el et | |
17942 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
17943 | ||
17944 | if (inst.cond > COND_ALWAYS) | |
17945 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17946 | else | |
17947 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17948 | ||
17949 | unsigned rot = inst.relocs[0].exp.X_add_number; | |
17950 | constraint (rot != 90 && rot != 270, _("immediate out of range")); | |
17951 | ||
17952 | if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) | |
17953 | as_tsktsk (_("Warning: 32-bit element size and same first and third " | |
17954 | "operand makes instruction UNPREDICTABLE")); | |
17955 | ||
17956 | mve_encode_qqq (0, et.size); | |
17957 | inst.instruction |= (rot == 270) << 12; | |
17958 | inst.is_neon = 1; | |
17959 | } | |
17960 | ||
35d1cfc2 AV |
17961 | static void |
17962 | do_mve_vqdmull (void) | |
17963 | { | |
17964 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); | |
17965 | struct neon_type_el et | |
17966 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
17967 | ||
17968 | if (et.size == 32 | |
17969 | && (inst.operands[0].reg == inst.operands[1].reg | |
17970 | || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg))) | |
17971 | as_tsktsk (BAD_MVE_SRCDEST); | |
17972 | ||
17973 | if (inst.cond > COND_ALWAYS) | |
17974 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
17975 | else | |
17976 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
17977 | ||
17978 | if (rs == NS_QQQ) | |
17979 | { | |
17980 | mve_encode_qqq (et.size == 32, 64); | |
17981 | inst.instruction |= 1; | |
17982 | } | |
17983 | else | |
17984 | { | |
17985 | mve_encode_qqr (64, et.size == 32, 0); | |
17986 | inst.instruction |= 0x3 << 5; | |
17987 | } | |
17988 | } | |
17989 | ||
c2dafc2a AV |
17990 | static void |
17991 | do_mve_vadc (void) | |
17992 | { | |
17993 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); | |
17994 | struct neon_type_el et | |
17995 | = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK); | |
17996 | ||
17997 | if (et.type == NT_invtype) | |
17998 | first_error (BAD_EL_TYPE); | |
17999 | ||
18000 | if (inst.cond > COND_ALWAYS) | |
18001 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18002 | else | |
18003 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18004 | ||
18005 | mve_encode_qqq (0, 64); | |
18006 | } | |
18007 | ||
18008 | static void | |
18009 | do_mve_vbrsr (void) | |
18010 | { | |
18011 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
18012 | struct neon_type_el et | |
18013 | = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
18014 | ||
18015 | if (inst.cond > COND_ALWAYS) | |
18016 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18017 | else | |
18018 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18019 | ||
7df54120 | 18020 | mve_encode_qqr (et.size, 0, 0); |
c2dafc2a AV |
18021 | } |
18022 | ||
18023 | static void | |
18024 | do_mve_vsbc (void) | |
18025 | { | |
18026 | neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY); | |
18027 | ||
18028 | if (inst.cond > COND_ALWAYS) | |
18029 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18030 | else | |
18031 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18032 | ||
18033 | mve_encode_qqq (1, 64); | |
18034 | } | |
18035 | ||
2d78f95b AV |
18036 | static void |
18037 | do_mve_vmulh (void) | |
18038 | { | |
18039 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); | |
18040 | struct neon_type_el et | |
18041 | = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
18042 | ||
18043 | if (inst.cond > COND_ALWAYS) | |
18044 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18045 | else | |
18046 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18047 | ||
18048 | mve_encode_qqq (et.type == NT_unsigned, et.size); | |
18049 | } | |
18050 | ||
42b16635 AV |
18051 | static void |
18052 | do_mve_vqdmlah (void) | |
18053 | { | |
18054 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); | |
18055 | struct neon_type_el et | |
23d188c7 | 18056 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY); |
42b16635 AV |
18057 | |
18058 | if (inst.cond > COND_ALWAYS) | |
18059 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18060 | else | |
18061 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18062 | ||
18063 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); | |
18064 | } | |
8b8b22a4 AV |
18065 | |
18066 | static void | |
18067 | do_mve_vqdmladh (void) | |
18068 | { | |
18069 | enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); | |
18070 | struct neon_type_el et | |
18071 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
18072 | ||
18073 | if (inst.cond > COND_ALWAYS) | |
18074 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18075 | else | |
18076 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18077 | ||
8b8b22a4 AV |
18078 | mve_encode_qqq (0, et.size); |
18079 | } | |
18080 | ||
18081 | ||
886e1c73 AV |
18082 | static void |
18083 | do_mve_vmull (void) | |
18084 | { | |
18085 | ||
18086 | enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS, | |
18087 | NS_QQS, NS_QQQ, NS_QQR, NS_NULL); | |
18088 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
18089 | && inst.cond == COND_ALWAYS | |
18090 | && ((unsigned)inst.instruction) == M_MNEM_vmullt) | |
18091 | { | |
18092 | if (rs == NS_QQQ) | |
18093 | { | |
18094 | ||
18095 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, | |
18096 | N_SUF_32 | N_F64 | N_P8 | |
18097 | | N_P16 | N_I_MVE | N_KEY); | |
18098 | if (((et.type == NT_poly) && et.size == 8 | |
18099 | && ARM_CPU_IS_ANY (cpu_variant)) | |
18100 | || (et.type == NT_integer) || (et.type == NT_float)) | |
18101 | goto neon_vmul; | |
18102 | } | |
18103 | else | |
18104 | goto neon_vmul; | |
18105 | } | |
18106 | ||
18107 | constraint (rs != NS_QQQ, BAD_FPU); | |
18108 | struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, | |
18109 | N_SU_32 | N_P8 | N_P16 | N_KEY); | |
18110 | ||
18111 | /* We are dealing with MVE's vmullt. */ | |
18112 | if (et.size == 32 | |
18113 | && (inst.operands[0].reg == inst.operands[1].reg | |
18114 | || inst.operands[0].reg == inst.operands[2].reg)) | |
18115 | as_tsktsk (BAD_MVE_SRCDEST); | |
18116 | ||
18117 | if (inst.cond > COND_ALWAYS) | |
18118 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18119 | else | |
18120 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18121 | ||
18122 | if (et.type == NT_poly) | |
18123 | mve_encode_qqq (neon_logbits (et.size), 64); | |
18124 | else | |
18125 | mve_encode_qqq (et.type == NT_unsigned, et.size); | |
18126 | ||
18127 | return; | |
18128 | ||
18129 | neon_vmul: | |
18130 | inst.instruction = N_MNEM_vmul; | |
18131 | inst.cond = 0xb; | |
18132 | if (thumb_mode) | |
18133 | inst.pred_insn_type = INSIDE_IT_INSN; | |
18134 | do_neon_mul (); | |
18135 | } | |
18136 | ||
a302e574 AV |
18137 | static void |
18138 | do_mve_vabav (void) | |
18139 | { | |
18140 | enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); | |
18141 | ||
18142 | if (rs == NS_NULL) | |
18143 | return; | |
18144 | ||
18145 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18146 | return; | |
18147 | ||
18148 | struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8 | |
18149 | | N_S16 | N_S32 | N_U8 | N_U16 | |
18150 | | N_U32); | |
18151 | ||
18152 | if (inst.cond > COND_ALWAYS) | |
18153 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18154 | else | |
18155 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18156 | ||
18157 | mve_encode_rqq (et.type == NT_unsigned, et.size); | |
18158 | } | |
18159 | ||
18160 | static void | |
18161 | do_mve_vmladav (void) | |
18162 | { | |
18163 | enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); | |
18164 | struct neon_type_el et = neon_check_type (3, rs, | |
18165 | N_EQK, N_EQK, N_SU_MVE | N_KEY); | |
18166 | ||
18167 | if (et.type == NT_unsigned | |
18168 | && (inst.instruction == M_MNEM_vmladavx | |
18169 | || inst.instruction == M_MNEM_vmladavax | |
18170 | || inst.instruction == M_MNEM_vmlsdav | |
18171 | || inst.instruction == M_MNEM_vmlsdava | |
18172 | || inst.instruction == M_MNEM_vmlsdavx | |
18173 | || inst.instruction == M_MNEM_vmlsdavax)) | |
18174 | first_error (BAD_SIMD_TYPE); | |
18175 | ||
18176 | constraint (inst.operands[2].reg > 14, | |
18177 | _("MVE vector register in the range [Q0..Q7] expected")); | |
18178 | ||
18179 | if (inst.cond > COND_ALWAYS) | |
18180 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18181 | else | |
18182 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18183 | ||
18184 | if (inst.instruction == M_MNEM_vmlsdav | |
18185 | || inst.instruction == M_MNEM_vmlsdava | |
18186 | || inst.instruction == M_MNEM_vmlsdavx | |
18187 | || inst.instruction == M_MNEM_vmlsdavax) | |
18188 | inst.instruction |= (et.size == 8) << 28; | |
18189 | else | |
18190 | inst.instruction |= (et.size == 8) << 8; | |
18191 | ||
18192 | mve_encode_rqq (et.type == NT_unsigned, 64); | |
18193 | inst.instruction |= (et.size == 32) << 16; | |
18194 | } | |
18195 | ||
93925576 AV |
18196 | static void |
18197 | do_mve_vmlaldav (void) | |
18198 | { | |
18199 | enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL); | |
18200 | struct neon_type_el et | |
18201 | = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK, | |
18202 | N_S16 | N_S32 | N_U16 | N_U32 | N_KEY); | |
18203 | ||
18204 | if (et.type == NT_unsigned | |
18205 | && (inst.instruction == M_MNEM_vmlsldav | |
18206 | || inst.instruction == M_MNEM_vmlsldava | |
18207 | || inst.instruction == M_MNEM_vmlsldavx | |
18208 | || inst.instruction == M_MNEM_vmlsldavax)) | |
18209 | first_error (BAD_SIMD_TYPE); | |
18210 | ||
18211 | if (inst.cond > COND_ALWAYS) | |
18212 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18213 | else | |
18214 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18215 | ||
18216 | mve_encode_rrqq (et.type == NT_unsigned, et.size); | |
18217 | } | |
18218 | ||
18219 | static void | |
18220 | do_mve_vrmlaldavh (void) | |
18221 | { | |
18222 | struct neon_type_el et; | |
18223 | if (inst.instruction == M_MNEM_vrmlsldavh | |
18224 | || inst.instruction == M_MNEM_vrmlsldavha | |
18225 | || inst.instruction == M_MNEM_vrmlsldavhx | |
18226 | || inst.instruction == M_MNEM_vrmlsldavhax) | |
18227 | { | |
18228 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY); | |
18229 | if (inst.operands[1].reg == REG_SP) | |
18230 | as_tsktsk (MVE_BAD_SP); | |
18231 | } | |
18232 | else | |
18233 | { | |
18234 | if (inst.instruction == M_MNEM_vrmlaldavhx | |
18235 | || inst.instruction == M_MNEM_vrmlaldavhax) | |
18236 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY); | |
18237 | else | |
18238 | et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, | |
18239 | N_U32 | N_S32 | N_KEY); | |
18240 | /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias | |
18241 | with vmax/min instructions, making the use of SP in assembly really | |
18242 | nonsensical, so instead of issuing a warning like we do for other uses | |
18243 | of SP for the odd register operand we error out. */ | |
18244 | constraint (inst.operands[1].reg == REG_SP, BAD_SP); | |
18245 | } | |
18246 | ||
18247 | /* Make sure we still check the second operand is an odd one and that PC is | |
18248 | disallowed. This because we are parsing for any GPR operand, to be able | |
18249 | to distinguish between giving a warning or an error for SP as described | |
18250 | above. */ | |
18251 | constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN); | |
18252 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
18253 | ||
18254 | if (inst.cond > COND_ALWAYS) | |
18255 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18256 | else | |
18257 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18258 | ||
18259 | mve_encode_rrqq (et.type == NT_unsigned, 0); | |
18260 | } | |
18261 | ||
18262 | ||
8cd78170 AV |
18263 | static void |
18264 | do_mve_vmaxnmv (void) | |
18265 | { | |
18266 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); | |
18267 | struct neon_type_el et | |
18268 | = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); | |
18269 | ||
18270 | if (inst.cond > COND_ALWAYS) | |
18271 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18272 | else | |
18273 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18274 | ||
18275 | if (inst.operands[0].reg == REG_SP) | |
18276 | as_tsktsk (MVE_BAD_SP); | |
18277 | else if (inst.operands[0].reg == REG_PC) | |
18278 | as_tsktsk (MVE_BAD_PC); | |
18279 | ||
18280 | mve_encode_rq (et.size == 16, 64); | |
18281 | } | |
18282 | ||
13ccd4c0 AV |
18283 | static void |
18284 | do_mve_vmaxv (void) | |
18285 | { | |
18286 | enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); | |
18287 | struct neon_type_el et; | |
18288 | ||
18289 | if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv) | |
18290 | et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY); | |
18291 | else | |
18292 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
18293 | ||
18294 | if (inst.cond > COND_ALWAYS) | |
18295 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
18296 | else | |
18297 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
18298 | ||
18299 | if (inst.operands[0].reg == REG_SP) | |
18300 | as_tsktsk (MVE_BAD_SP); | |
18301 | else if (inst.operands[0].reg == REG_PC) | |
18302 | as_tsktsk (MVE_BAD_PC); | |
18303 | ||
18304 | mve_encode_rq (et.type == NT_unsigned, et.size); | |
18305 | } | |
18306 | ||
18307 | ||
643afb90 MW |
18308 | static void |
18309 | do_neon_qrdmlah (void) | |
18310 | { | |
64c350f2 | 18311 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
42b16635 AV |
18312 | return; |
18313 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
643afb90 | 18314 | { |
42b16635 AV |
18315 | /* Check we're on the correct architecture. */ |
18316 | if (!mark_feature_used (&fpu_neon_ext_armv8)) | |
18317 | inst.error | |
18318 | = _("instruction form not available on this architecture."); | |
18319 | else if (!mark_feature_used (&fpu_neon_ext_v8_1)) | |
18320 | { | |
18321 | as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD.")); | |
18322 | record_feature_use (&fpu_neon_ext_v8_1); | |
18323 | } | |
18324 | if (inst.operands[2].isscalar) | |
18325 | { | |
18326 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); | |
18327 | struct neon_type_el et = neon_check_type (3, rs, | |
18328 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
18329 | NEON_ENCODE (SCALAR, inst); | |
18330 | neon_mul_mac (et, neon_quad (rs)); | |
18331 | } | |
18332 | else | |
18333 | { | |
18334 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
18335 | struct neon_type_el et = neon_check_type (3, rs, | |
18336 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
18337 | NEON_ENCODE (INTEGER, inst); | |
18338 | /* The U bit (rounding) comes from bit mask. */ | |
18339 | neon_three_same (neon_quad (rs), 0, et.size); | |
18340 | } | |
643afb90 MW |
18341 | } |
18342 | else | |
18343 | { | |
42b16635 AV |
18344 | enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); |
18345 | struct neon_type_el et | |
23d188c7 | 18346 | = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY); |
42b16635 | 18347 | |
643afb90 | 18348 | NEON_ENCODE (INTEGER, inst); |
42b16635 | 18349 | mve_encode_qqr (et.size, et.type == NT_unsigned, 0); |
643afb90 MW |
18350 | } |
18351 | } | |
18352 | ||
5287ad62 JB |
18353 | static void |
18354 | do_neon_fcmp_absolute (void) | |
18355 | { | |
037e8744 | 18356 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
cc933301 JW |
18357 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
18358 | N_F_16_32 | N_KEY); | |
5287ad62 | 18359 | /* Size field comes from bit mask. */ |
cc933301 | 18360 | neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1); |
5287ad62 JB |
18361 | } |
18362 | ||
18363 | static void | |
18364 | do_neon_fcmp_absolute_inv (void) | |
18365 | { | |
18366 | neon_exchange_operands (); | |
18367 | do_neon_fcmp_absolute (); | |
18368 | } | |
18369 | ||
18370 | static void | |
18371 | do_neon_step (void) | |
18372 | { | |
037e8744 | 18373 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
cc933301 JW |
18374 | struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK, |
18375 | N_F_16_32 | N_KEY); | |
18376 | neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1); | |
5287ad62 JB |
18377 | } |
18378 | ||
18379 | static void | |
18380 | do_neon_abs_neg (void) | |
18381 | { | |
037e8744 JB |
18382 | enum neon_shape rs; |
18383 | struct neon_type_el et; | |
5f4273c7 | 18384 | |
037e8744 JB |
18385 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
18386 | return; | |
18387 | ||
037e8744 | 18388 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
cc933301 | 18389 | et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); |
5f4273c7 | 18390 | |
64c350f2 AV |
18391 | if (!check_simd_pred_availability (et.type == NT_float, |
18392 | NEON_CHECK_ARCH | NEON_CHECK_CC)) | |
485dee97 AV |
18393 | return; |
18394 | ||
5287ad62 JB |
18395 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
18396 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18397 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18398 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 18399 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
18400 | inst.instruction |= (et.type == NT_float) << 10; |
18401 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 18402 | |
88714cb8 | 18403 | neon_dp_fixup (&inst); |
5287ad62 JB |
18404 | } |
18405 | ||
18406 | static void | |
18407 | do_neon_sli (void) | |
18408 | { | |
64c350f2 | 18409 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
18410 | return; |
18411 | ||
18412 | enum neon_shape rs; | |
18413 | struct neon_type_el et; | |
18414 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18415 | { | |
18416 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
18417 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
18418 | } | |
18419 | else | |
18420 | { | |
18421 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
18422 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
18423 | } | |
18424 | ||
18425 | ||
5287ad62 JB |
18426 | int imm = inst.operands[2].imm; |
18427 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 18428 | _("immediate out of range for insert")); |
037e8744 | 18429 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
18430 | } |
18431 | ||
18432 | static void | |
18433 | do_neon_sri (void) | |
18434 | { | |
64c350f2 | 18435 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
18436 | return; |
18437 | ||
18438 | enum neon_shape rs; | |
18439 | struct neon_type_el et; | |
18440 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18441 | { | |
18442 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
18443 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
18444 | } | |
18445 | else | |
18446 | { | |
18447 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
18448 | et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
18449 | } | |
18450 | ||
5287ad62 JB |
18451 | int imm = inst.operands[2].imm; |
18452 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 18453 | _("immediate out of range for insert")); |
037e8744 | 18454 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
18455 | } |
18456 | ||
18457 | static void | |
18458 | do_neon_qshlu_imm (void) | |
18459 | { | |
64c350f2 | 18460 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
5150f0d8 AV |
18461 | return; |
18462 | ||
18463 | enum neon_shape rs; | |
18464 | struct neon_type_el et; | |
18465 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
18466 | { | |
18467 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
18468 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
18469 | } | |
18470 | else | |
18471 | { | |
18472 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
18473 | et = neon_check_type (2, rs, N_EQK | N_UNS, | |
18474 | N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
18475 | } | |
18476 | ||
5287ad62 JB |
18477 | int imm = inst.operands[2].imm; |
18478 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 18479 | _("immediate out of range for shift")); |
5287ad62 JB |
18480 | /* Only encodes the 'U present' variant of the instruction. |
18481 | In this case, signed types have OP (bit 8) set to 0. | |
18482 | Unsigned types have OP set to 1. */ | |
18483 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
18484 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 18485 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
18486 | } |
18487 | ||
18488 | static void | |
18489 | do_neon_qmovn (void) | |
18490 | { | |
18491 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
18492 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
18493 | /* Saturating move where operands can be signed or unsigned, and the | |
18494 | destination has the same signedness. */ | |
88714cb8 | 18495 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18496 | if (et.type == NT_unsigned) |
18497 | inst.instruction |= 0xc0; | |
18498 | else | |
18499 | inst.instruction |= 0x80; | |
18500 | neon_two_same (0, 1, et.size / 2); | |
18501 | } | |
18502 | ||
18503 | static void | |
18504 | do_neon_qmovun (void) | |
18505 | { | |
18506 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
18507 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
18508 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 18509 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18510 | neon_two_same (0, 1, et.size / 2); |
18511 | } | |
18512 | ||
18513 | static void | |
18514 | do_neon_rshift_sat_narrow (void) | |
18515 | { | |
18516 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
18517 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
18518 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
18519 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
18520 | int imm = inst.operands[2].imm; | |
18521 | /* This gets the bounds check, size encoding and immediate bits calculation | |
18522 | right. */ | |
18523 | et.size /= 2; | |
5f4273c7 | 18524 | |
5287ad62 JB |
18525 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
18526 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
18527 | if (imm == 0) | |
18528 | { | |
18529 | inst.operands[2].present = 0; | |
18530 | inst.instruction = N_MNEM_vqmovn; | |
18531 | do_neon_qmovn (); | |
18532 | return; | |
18533 | } | |
5f4273c7 | 18534 | |
5287ad62 | 18535 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 18536 | _("immediate out of range")); |
5287ad62 JB |
18537 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
18538 | } | |
18539 | ||
18540 | static void | |
18541 | do_neon_rshift_sat_narrow_u (void) | |
18542 | { | |
18543 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
18544 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
18545 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
18546 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
18547 | int imm = inst.operands[2].imm; | |
18548 | /* This gets the bounds check, size encoding and immediate bits calculation | |
18549 | right. */ | |
18550 | et.size /= 2; | |
18551 | ||
18552 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
18553 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
18554 | if (imm == 0) | |
18555 | { | |
18556 | inst.operands[2].present = 0; | |
18557 | inst.instruction = N_MNEM_vqmovun; | |
18558 | do_neon_qmovun (); | |
18559 | return; | |
18560 | } | |
18561 | ||
18562 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 18563 | _("immediate out of range")); |
5287ad62 JB |
18564 | /* FIXME: The manual is kind of unclear about what value U should have in |
18565 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
18566 | must be 1. */ | |
18567 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
18568 | } | |
18569 | ||
18570 | static void | |
18571 | do_neon_movn (void) | |
18572 | { | |
18573 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
18574 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 18575 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18576 | neon_two_same (0, 1, et.size / 2); |
18577 | } | |
18578 | ||
18579 | static void | |
18580 | do_neon_rshift_narrow (void) | |
18581 | { | |
18582 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
18583 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
18584 | int imm = inst.operands[2].imm; | |
18585 | /* This gets the bounds check, size encoding and immediate bits calculation | |
18586 | right. */ | |
18587 | et.size /= 2; | |
5f4273c7 | 18588 | |
5287ad62 JB |
18589 | /* If immediate is zero then we are a pseudo-instruction for |
18590 | VMOVN.I<size> <Dd>, <Qm> */ | |
18591 | if (imm == 0) | |
18592 | { | |
18593 | inst.operands[2].present = 0; | |
18594 | inst.instruction = N_MNEM_vmovn; | |
18595 | do_neon_movn (); | |
18596 | return; | |
18597 | } | |
5f4273c7 | 18598 | |
5287ad62 | 18599 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 18600 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
18601 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
18602 | } | |
18603 | ||
18604 | static void | |
18605 | do_neon_shll (void) | |
18606 | { | |
18607 | /* FIXME: Type checking when lengthening. */ | |
18608 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
18609 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
18610 | unsigned imm = inst.operands[2].imm; | |
18611 | ||
18612 | if (imm == et.size) | |
18613 | { | |
18614 | /* Maximum shift variant. */ | |
88714cb8 | 18615 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
18616 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
18617 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18618 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18619 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
18620 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 18621 | |
88714cb8 | 18622 | neon_dp_fixup (&inst); |
5287ad62 JB |
18623 | } |
18624 | else | |
18625 | { | |
18626 | /* A more-specific type check for non-max versions. */ | |
18627 | et = neon_check_type (2, NS_QDI, | |
477330fc | 18628 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 18629 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
18630 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
18631 | } | |
18632 | } | |
18633 | ||
037e8744 | 18634 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
18635 | the current instruction is. */ |
18636 | ||
6b9a8b67 MGD |
18637 | #define CVT_FLAVOUR_VAR \ |
18638 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
18639 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
18640 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
18641 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
18642 | /* Half-precision conversions. */ \ | |
cc933301 JW |
18643 | CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ |
18644 | CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \ | |
18645 | CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \ | |
18646 | CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \ | |
6b9a8b67 MGD |
18647 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ |
18648 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
9db2f6b4 RL |
18649 | /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \ |
18650 | Compared with single/double precision variants, only the co-processor \ | |
18651 | field is different, so the encoding flow is reused here. */ \ | |
18652 | CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \ | |
18653 | CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \ | |
18654 | CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\ | |
18655 | CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\ | |
6b9a8b67 MGD |
18656 | /* VFP instructions. */ \ |
18657 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
18658 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
18659 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
18660 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
18661 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
18662 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
18663 | /* VFP instructions with bitshift. */ \ | |
18664 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
18665 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
18666 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
18667 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
18668 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
18669 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
18670 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
18671 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
18672 | ||
18673 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
18674 | neon_cvt_flavour_##C, | |
18675 | ||
18676 | /* The different types of conversions we can do. */ | |
18677 | enum neon_cvt_flavour | |
18678 | { | |
18679 | CVT_FLAVOUR_VAR | |
18680 | neon_cvt_flavour_invalid, | |
18681 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
18682 | }; | |
18683 | ||
18684 | #undef CVT_VAR | |
18685 | ||
18686 | static enum neon_cvt_flavour | |
18687 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 18688 | { |
6b9a8b67 MGD |
18689 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
18690 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
18691 | if (et.type != NT_invtype) \ | |
18692 | { \ | |
18693 | inst.error = NULL; \ | |
18694 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 18695 | } |
6b9a8b67 | 18696 | |
5287ad62 | 18697 | struct neon_type_el et; |
037e8744 | 18698 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 18699 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
18700 | /* The instruction versions which take an immediate take one register |
18701 | argument, which is extended to the width of the full register. Thus the | |
18702 | "source" and "destination" registers must have the same width. Hack that | |
18703 | here by making the size equal to the key (wider, in this case) operand. */ | |
18704 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 18705 | |
6b9a8b67 MGD |
18706 | CVT_FLAVOUR_VAR; |
18707 | ||
18708 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
18709 | #undef CVT_VAR |
18710 | } | |
18711 | ||
7e8e6784 MGD |
18712 | enum neon_cvt_mode |
18713 | { | |
18714 | neon_cvt_mode_a, | |
18715 | neon_cvt_mode_n, | |
18716 | neon_cvt_mode_p, | |
18717 | neon_cvt_mode_m, | |
18718 | neon_cvt_mode_z, | |
30bdf752 MGD |
18719 | neon_cvt_mode_x, |
18720 | neon_cvt_mode_r | |
7e8e6784 MGD |
18721 | }; |
18722 | ||
037e8744 JB |
18723 | /* Neon-syntax VFP conversions. */ |
18724 | ||
5287ad62 | 18725 | static void |
6b9a8b67 | 18726 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 18727 | { |
037e8744 | 18728 | const char *opname = 0; |
5f4273c7 | 18729 | |
d54af2d0 RL |
18730 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI |
18731 | || rs == NS_FHI || rs == NS_HFI) | |
5287ad62 | 18732 | { |
037e8744 JB |
18733 | /* Conversions with immediate bitshift. */ |
18734 | const char *enc[] = | |
477330fc | 18735 | { |
6b9a8b67 MGD |
18736 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
18737 | CVT_FLAVOUR_VAR | |
18738 | NULL | |
18739 | #undef CVT_VAR | |
477330fc | 18740 | }; |
037e8744 | 18741 | |
6b9a8b67 | 18742 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
18743 | { |
18744 | opname = enc[flavour]; | |
18745 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
18746 | _("operands 0 and 1 must be the same register")); | |
18747 | inst.operands[1] = inst.operands[2]; | |
18748 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
18749 | } | |
5287ad62 JB |
18750 | } |
18751 | else | |
18752 | { | |
037e8744 JB |
18753 | /* Conversions without bitshift. */ |
18754 | const char *enc[] = | |
477330fc | 18755 | { |
6b9a8b67 MGD |
18756 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
18757 | CVT_FLAVOUR_VAR | |
18758 | NULL | |
18759 | #undef CVT_VAR | |
477330fc | 18760 | }; |
037e8744 | 18761 | |
6b9a8b67 | 18762 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 18763 | opname = enc[flavour]; |
037e8744 JB |
18764 | } |
18765 | ||
18766 | if (opname) | |
18767 | do_vfp_nsyn_opcode (opname); | |
9db2f6b4 RL |
18768 | |
18769 | /* ARMv8.2 fp16 VCVT instruction. */ | |
18770 | if (flavour == neon_cvt_flavour_s32_f16 | |
18771 | || flavour == neon_cvt_flavour_u32_f16 | |
18772 | || flavour == neon_cvt_flavour_f16_u32 | |
18773 | || flavour == neon_cvt_flavour_f16_s32) | |
18774 | do_scalar_fp16_v82_encode (); | |
037e8744 JB |
18775 | } |
18776 | ||
18777 | static void | |
18778 | do_vfp_nsyn_cvtz (void) | |
18779 | { | |
d54af2d0 | 18780 | enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL); |
6b9a8b67 | 18781 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
18782 | const char *enc[] = |
18783 | { | |
6b9a8b67 MGD |
18784 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
18785 | CVT_FLAVOUR_VAR | |
18786 | NULL | |
18787 | #undef CVT_VAR | |
037e8744 JB |
18788 | }; |
18789 | ||
6b9a8b67 | 18790 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
18791 | do_vfp_nsyn_opcode (enc[flavour]); |
18792 | } | |
f31fef98 | 18793 | |
037e8744 | 18794 | static void |
bacebabc | 18795 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
18796 | enum neon_cvt_mode mode) |
18797 | { | |
18798 | int sz, op; | |
18799 | int rm; | |
18800 | ||
a715796b TG |
18801 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
18802 | D register operands. */ | |
18803 | if (flavour == neon_cvt_flavour_s32_f64 | |
18804 | || flavour == neon_cvt_flavour_u32_f64) | |
18805 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
18806 | _(BAD_FPU)); | |
18807 | ||
9db2f6b4 RL |
18808 | if (flavour == neon_cvt_flavour_s32_f16 |
18809 | || flavour == neon_cvt_flavour_u32_f16) | |
18810 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), | |
18811 | _(BAD_FP16)); | |
18812 | ||
5ee91343 | 18813 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
7e8e6784 MGD |
18814 | |
18815 | switch (flavour) | |
18816 | { | |
18817 | case neon_cvt_flavour_s32_f64: | |
18818 | sz = 1; | |
827f64ff | 18819 | op = 1; |
7e8e6784 MGD |
18820 | break; |
18821 | case neon_cvt_flavour_s32_f32: | |
18822 | sz = 0; | |
18823 | op = 1; | |
18824 | break; | |
9db2f6b4 RL |
18825 | case neon_cvt_flavour_s32_f16: |
18826 | sz = 0; | |
18827 | op = 1; | |
18828 | break; | |
7e8e6784 MGD |
18829 | case neon_cvt_flavour_u32_f64: |
18830 | sz = 1; | |
18831 | op = 0; | |
18832 | break; | |
18833 | case neon_cvt_flavour_u32_f32: | |
18834 | sz = 0; | |
18835 | op = 0; | |
18836 | break; | |
9db2f6b4 RL |
18837 | case neon_cvt_flavour_u32_f16: |
18838 | sz = 0; | |
18839 | op = 0; | |
18840 | break; | |
7e8e6784 MGD |
18841 | default: |
18842 | first_error (_("invalid instruction shape")); | |
18843 | return; | |
18844 | } | |
18845 | ||
18846 | switch (mode) | |
18847 | { | |
18848 | case neon_cvt_mode_a: rm = 0; break; | |
18849 | case neon_cvt_mode_n: rm = 1; break; | |
18850 | case neon_cvt_mode_p: rm = 2; break; | |
18851 | case neon_cvt_mode_m: rm = 3; break; | |
18852 | default: first_error (_("invalid rounding mode")); return; | |
18853 | } | |
18854 | ||
18855 | NEON_ENCODE (FPV8, inst); | |
18856 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
18857 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
18858 | inst.instruction |= sz << 8; | |
9db2f6b4 RL |
18859 | |
18860 | /* ARMv8.2 fp16 VCVT instruction. */ | |
18861 | if (flavour == neon_cvt_flavour_s32_f16 | |
18862 | ||flavour == neon_cvt_flavour_u32_f16) | |
18863 | do_scalar_fp16_v82_encode (); | |
7e8e6784 MGD |
18864 | inst.instruction |= op << 7; |
18865 | inst.instruction |= rm << 16; | |
18866 | inst.instruction |= 0xf0000000; | |
18867 | inst.is_neon = TRUE; | |
18868 | } | |
18869 | ||
18870 | static void | |
18871 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
18872 | { |
18873 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
d54af2d0 RL |
18874 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, |
18875 | NS_FH, NS_HF, NS_FHI, NS_HFI, | |
18876 | NS_NULL); | |
6b9a8b67 | 18877 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 18878 | |
cc933301 JW |
18879 | if (flavour == neon_cvt_flavour_invalid) |
18880 | return; | |
18881 | ||
e3e535bc | 18882 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 18883 | if (mode == neon_cvt_mode_z |
e3e535bc | 18884 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
cc933301 JW |
18885 | && (flavour == neon_cvt_flavour_s16_f16 |
18886 | || flavour == neon_cvt_flavour_u16_f16 | |
18887 | || flavour == neon_cvt_flavour_s32_f32 | |
bacebabc RM |
18888 | || flavour == neon_cvt_flavour_u32_f32 |
18889 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 18890 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
18891 | && (rs == NS_FD || rs == NS_FF)) |
18892 | { | |
18893 | do_vfp_nsyn_cvtz (); | |
18894 | return; | |
18895 | } | |
18896 | ||
9db2f6b4 RL |
18897 | /* ARMv8.2 fp16 VCVT conversions. */ |
18898 | if (mode == neon_cvt_mode_z | |
18899 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16) | |
18900 | && (flavour == neon_cvt_flavour_s32_f16 | |
18901 | || flavour == neon_cvt_flavour_u32_f16) | |
18902 | && (rs == NS_FH)) | |
18903 | { | |
18904 | do_vfp_nsyn_cvtz (); | |
18905 | do_scalar_fp16_v82_encode (); | |
18906 | return; | |
18907 | } | |
18908 | ||
037e8744 | 18909 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 18910 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 18911 | { |
7e8e6784 MGD |
18912 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
18913 | do_vfp_nsyn_cvt (rs, flavour); | |
18914 | else | |
18915 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
18916 | ||
037e8744 JB |
18917 | return; |
18918 | } | |
18919 | ||
18920 | switch (rs) | |
18921 | { | |
037e8744 | 18922 | case NS_QQI: |
dd9634d9 AV |
18923 | if (mode == neon_cvt_mode_z |
18924 | && (flavour == neon_cvt_flavour_f16_s16 | |
18925 | || flavour == neon_cvt_flavour_f16_u16 | |
18926 | || flavour == neon_cvt_flavour_s16_f16 | |
18927 | || flavour == neon_cvt_flavour_u16_f16 | |
18928 | || flavour == neon_cvt_flavour_f32_u32 | |
18929 | || flavour == neon_cvt_flavour_f32_s32 | |
18930 | || flavour == neon_cvt_flavour_s32_f32 | |
18931 | || flavour == neon_cvt_flavour_u32_f32)) | |
18932 | { | |
64c350f2 AV |
18933 | if (!check_simd_pred_availability (TRUE, |
18934 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
dd9634d9 AV |
18935 | return; |
18936 | } | |
18937 | else if (mode == neon_cvt_mode_n) | |
18938 | { | |
18939 | /* We are dealing with vcvt with the 'ne' condition. */ | |
18940 | inst.cond = 0x1; | |
18941 | inst.instruction = N_MNEM_vcvt; | |
18942 | do_neon_cvt_1 (neon_cvt_mode_z); | |
18943 | return; | |
18944 | } | |
18945 | /* fall through. */ | |
18946 | case NS_DDI: | |
037e8744 | 18947 | { |
477330fc | 18948 | unsigned immbits; |
cc933301 JW |
18949 | unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000, |
18950 | 0x0000100, 0x1000100, 0x0, 0x1000000}; | |
35997600 | 18951 | |
dd9634d9 AV |
18952 | if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
18953 | && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
18954 | return; | |
18955 | ||
18956 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) | |
18957 | { | |
18958 | constraint (inst.operands[2].present && inst.operands[2].imm == 0, | |
18959 | _("immediate value out of range")); | |
18960 | switch (flavour) | |
18961 | { | |
18962 | case neon_cvt_flavour_f16_s16: | |
18963 | case neon_cvt_flavour_f16_u16: | |
18964 | case neon_cvt_flavour_s16_f16: | |
18965 | case neon_cvt_flavour_u16_f16: | |
18966 | constraint (inst.operands[2].imm > 16, | |
18967 | _("immediate value out of range")); | |
18968 | break; | |
18969 | case neon_cvt_flavour_f32_u32: | |
18970 | case neon_cvt_flavour_f32_s32: | |
18971 | case neon_cvt_flavour_s32_f32: | |
18972 | case neon_cvt_flavour_u32_f32: | |
18973 | constraint (inst.operands[2].imm > 32, | |
18974 | _("immediate value out of range")); | |
18975 | break; | |
18976 | default: | |
18977 | inst.error = BAD_FPU; | |
18978 | return; | |
18979 | } | |
18980 | } | |
037e8744 | 18981 | |
477330fc RM |
18982 | /* Fixed-point conversion with #0 immediate is encoded as an |
18983 | integer conversion. */ | |
18984 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
18985 | goto int_encode; | |
477330fc RM |
18986 | NEON_ENCODE (IMMED, inst); |
18987 | if (flavour != neon_cvt_flavour_invalid) | |
18988 | inst.instruction |= enctab[flavour]; | |
18989 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
18990 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
18991 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
18992 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
18993 | inst.instruction |= neon_quad (rs) << 6; | |
18994 | inst.instruction |= 1 << 21; | |
cc933301 JW |
18995 | if (flavour < neon_cvt_flavour_s16_f16) |
18996 | { | |
18997 | inst.instruction |= 1 << 21; | |
18998 | immbits = 32 - inst.operands[2].imm; | |
18999 | inst.instruction |= immbits << 16; | |
19000 | } | |
19001 | else | |
19002 | { | |
19003 | inst.instruction |= 3 << 20; | |
19004 | immbits = 16 - inst.operands[2].imm; | |
19005 | inst.instruction |= immbits << 16; | |
19006 | inst.instruction &= ~(1 << 9); | |
19007 | } | |
477330fc RM |
19008 | |
19009 | neon_dp_fixup (&inst); | |
037e8744 JB |
19010 | } |
19011 | break; | |
19012 | ||
037e8744 | 19013 | case NS_QQ: |
dd9634d9 AV |
19014 | if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n |
19015 | || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p) | |
19016 | && (flavour == neon_cvt_flavour_s16_f16 | |
19017 | || flavour == neon_cvt_flavour_u16_f16 | |
19018 | || flavour == neon_cvt_flavour_s32_f32 | |
19019 | || flavour == neon_cvt_flavour_u32_f32)) | |
19020 | { | |
64c350f2 AV |
19021 | if (!check_simd_pred_availability (TRUE, |
19022 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) | |
dd9634d9 AV |
19023 | return; |
19024 | } | |
19025 | else if (mode == neon_cvt_mode_z | |
19026 | && (flavour == neon_cvt_flavour_f16_s16 | |
19027 | || flavour == neon_cvt_flavour_f16_u16 | |
19028 | || flavour == neon_cvt_flavour_s16_f16 | |
19029 | || flavour == neon_cvt_flavour_u16_f16 | |
19030 | || flavour == neon_cvt_flavour_f32_u32 | |
19031 | || flavour == neon_cvt_flavour_f32_s32 | |
19032 | || flavour == neon_cvt_flavour_s32_f32 | |
19033 | || flavour == neon_cvt_flavour_u32_f32)) | |
19034 | { | |
64c350f2 AV |
19035 | if (!check_simd_pred_availability (TRUE, |
19036 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
dd9634d9 AV |
19037 | return; |
19038 | } | |
19039 | /* fall through. */ | |
19040 | case NS_DD: | |
7e8e6784 MGD |
19041 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
19042 | { | |
7e8e6784 | 19043 | |
dd9634d9 | 19044 | NEON_ENCODE (FLOAT, inst); |
64c350f2 AV |
19045 | if (!check_simd_pred_availability (TRUE, |
19046 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) | |
7e8e6784 MGD |
19047 | return; |
19048 | ||
19049 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19050 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19051 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19052 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19053 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
19054 | inst.instruction |= (flavour == neon_cvt_flavour_u16_f16 |
19055 | || flavour == neon_cvt_flavour_u32_f32) << 7; | |
7e8e6784 | 19056 | inst.instruction |= mode << 8; |
cc933301 JW |
19057 | if (flavour == neon_cvt_flavour_u16_f16 |
19058 | || flavour == neon_cvt_flavour_s16_f16) | |
19059 | /* Mask off the original size bits and reencode them. */ | |
19060 | inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18)); | |
19061 | ||
7e8e6784 MGD |
19062 | if (thumb_mode) |
19063 | inst.instruction |= 0xfc000000; | |
19064 | else | |
19065 | inst.instruction |= 0xf0000000; | |
19066 | } | |
19067 | else | |
19068 | { | |
037e8744 | 19069 | int_encode: |
7e8e6784 | 19070 | { |
cc933301 JW |
19071 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080, |
19072 | 0x100, 0x180, 0x0, 0x080}; | |
037e8744 | 19073 | |
7e8e6784 | 19074 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 19075 | |
dd9634d9 AV |
19076 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
19077 | { | |
19078 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
19079 | return; | |
19080 | } | |
037e8744 | 19081 | |
7e8e6784 MGD |
19082 | if (flavour != neon_cvt_flavour_invalid) |
19083 | inst.instruction |= enctab[flavour]; | |
037e8744 | 19084 | |
7e8e6784 MGD |
19085 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19086 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19087 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19088 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19089 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
19090 | if (flavour >= neon_cvt_flavour_s16_f16 |
19091 | && flavour <= neon_cvt_flavour_f16_u16) | |
19092 | /* Half precision. */ | |
19093 | inst.instruction |= 1 << 18; | |
19094 | else | |
19095 | inst.instruction |= 2 << 18; | |
037e8744 | 19096 | |
7e8e6784 MGD |
19097 | neon_dp_fixup (&inst); |
19098 | } | |
19099 | } | |
19100 | break; | |
037e8744 | 19101 | |
8e79c3df CM |
19102 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
19103 | case NS_QD: | |
19104 | case NS_DQ: | |
bc52d49c MM |
19105 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
19106 | return; | |
8e79c3df CM |
19107 | |
19108 | if ((rs == NS_DQ) | |
19109 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
19110 | { | |
19111 | as_bad (_("operand size must match register width")); | |
19112 | break; | |
19113 | } | |
19114 | ||
19115 | if ((rs == NS_QD) | |
19116 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
19117 | { | |
19118 | as_bad (_("operand size must match register width")); | |
19119 | break; | |
19120 | } | |
19121 | ||
19122 | if (rs == NS_DQ) | |
477330fc | 19123 | inst.instruction = 0x3b60600; |
8e79c3df CM |
19124 | else |
19125 | inst.instruction = 0x3b60700; | |
19126 | ||
19127 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19128 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19129 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19130 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 19131 | neon_dp_fixup (&inst); |
8e79c3df CM |
19132 | break; |
19133 | ||
037e8744 JB |
19134 | default: |
19135 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
19136 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
19137 | do_vfp_nsyn_cvt (rs, flavour); | |
19138 | else | |
19139 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 19140 | } |
5287ad62 JB |
19141 | } |
19142 | ||
e3e535bc NC |
19143 | static void |
19144 | do_neon_cvtr (void) | |
19145 | { | |
7e8e6784 | 19146 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
19147 | } |
19148 | ||
19149 | static void | |
19150 | do_neon_cvt (void) | |
19151 | { | |
7e8e6784 MGD |
19152 | do_neon_cvt_1 (neon_cvt_mode_z); |
19153 | } | |
19154 | ||
19155 | static void | |
19156 | do_neon_cvta (void) | |
19157 | { | |
19158 | do_neon_cvt_1 (neon_cvt_mode_a); | |
19159 | } | |
19160 | ||
19161 | static void | |
19162 | do_neon_cvtn (void) | |
19163 | { | |
19164 | do_neon_cvt_1 (neon_cvt_mode_n); | |
19165 | } | |
19166 | ||
19167 | static void | |
19168 | do_neon_cvtp (void) | |
19169 | { | |
19170 | do_neon_cvt_1 (neon_cvt_mode_p); | |
19171 | } | |
19172 | ||
19173 | static void | |
19174 | do_neon_cvtm (void) | |
19175 | { | |
19176 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
19177 | } |
19178 | ||
8e79c3df | 19179 | static void |
c70a8987 | 19180 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 19181 | { |
c70a8987 MGD |
19182 | if (is_double) |
19183 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 19184 | |
c70a8987 MGD |
19185 | encode_arm_vfp_reg (inst.operands[0].reg, |
19186 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
19187 | encode_arm_vfp_reg (inst.operands[1].reg, | |
19188 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
19189 | inst.instruction |= to ? 0x10000 : 0; | |
19190 | inst.instruction |= t ? 0x80 : 0; | |
19191 | inst.instruction |= is_double ? 0x100 : 0; | |
19192 | do_vfp_cond_or_thumb (); | |
19193 | } | |
8e79c3df | 19194 | |
c70a8987 MGD |
19195 | static void |
19196 | do_neon_cvttb_1 (bfd_boolean t) | |
19197 | { | |
d54af2d0 | 19198 | enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD, |
dd9634d9 | 19199 | NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL); |
8e79c3df | 19200 | |
c70a8987 MGD |
19201 | if (rs == NS_NULL) |
19202 | return; | |
dd9634d9 AV |
19203 | else if (rs == NS_QQ || rs == NS_QQI) |
19204 | { | |
19205 | int single_to_half = 0; | |
64c350f2 | 19206 | if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH)) |
dd9634d9 AV |
19207 | return; |
19208 | ||
19209 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); | |
19210 | ||
19211 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19212 | && (flavour == neon_cvt_flavour_u16_f16 | |
19213 | || flavour == neon_cvt_flavour_s16_f16 | |
19214 | || flavour == neon_cvt_flavour_f16_s16 | |
19215 | || flavour == neon_cvt_flavour_f16_u16 | |
19216 | || flavour == neon_cvt_flavour_u32_f32 | |
19217 | || flavour == neon_cvt_flavour_s32_f32 | |
19218 | || flavour == neon_cvt_flavour_f32_s32 | |
19219 | || flavour == neon_cvt_flavour_f32_u32)) | |
19220 | { | |
19221 | inst.cond = 0xf; | |
19222 | inst.instruction = N_MNEM_vcvt; | |
19223 | set_pred_insn_type (INSIDE_VPT_INSN); | |
19224 | do_neon_cvt_1 (neon_cvt_mode_z); | |
19225 | return; | |
19226 | } | |
19227 | else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16) | |
19228 | single_to_half = 1; | |
19229 | else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32) | |
19230 | { | |
19231 | first_error (BAD_FPU); | |
19232 | return; | |
19233 | } | |
19234 | ||
19235 | inst.instruction = 0xee3f0e01; | |
19236 | inst.instruction |= single_to_half << 28; | |
19237 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19238 | inst.instruction |= LOW4 (inst.operands[0].reg) << 13; | |
19239 | inst.instruction |= t << 12; | |
19240 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19241 | inst.instruction |= LOW4 (inst.operands[1].reg) << 1; | |
19242 | inst.is_neon = 1; | |
19243 | } | |
c70a8987 MGD |
19244 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) |
19245 | { | |
19246 | inst.error = NULL; | |
19247 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
19248 | } | |
19249 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
19250 | { | |
19251 | inst.error = NULL; | |
19252 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
19253 | } | |
19254 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
19255 | { | |
a715796b TG |
19256 | /* The VCVTB and VCVTT instructions with D-register operands |
19257 | don't work for SP only targets. */ | |
19258 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
19259 | _(BAD_FPU)); | |
19260 | ||
c70a8987 MGD |
19261 | inst.error = NULL; |
19262 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
19263 | } | |
19264 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
19265 | { | |
a715796b TG |
19266 | /* The VCVTB and VCVTT instructions with D-register operands |
19267 | don't work for SP only targets. */ | |
19268 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
19269 | _(BAD_FPU)); | |
19270 | ||
c70a8987 MGD |
19271 | inst.error = NULL; |
19272 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
19273 | } | |
19274 | else | |
19275 | return; | |
19276 | } | |
19277 | ||
19278 | static void | |
19279 | do_neon_cvtb (void) | |
19280 | { | |
19281 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
19282 | } |
19283 | ||
19284 | ||
19285 | static void | |
19286 | do_neon_cvtt (void) | |
19287 | { | |
c70a8987 | 19288 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
19289 | } |
19290 | ||
5287ad62 JB |
19291 | static void |
19292 | neon_move_immediate (void) | |
19293 | { | |
037e8744 JB |
19294 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
19295 | struct neon_type_el et = neon_check_type (2, rs, | |
19296 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 19297 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 19298 | int op, cmode, float_p; |
5287ad62 | 19299 | |
037e8744 | 19300 | constraint (et.type == NT_invtype, |
477330fc | 19301 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 19302 | |
5287ad62 JB |
19303 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
19304 | op = (inst.instruction & (1 << 5)) != 0; | |
19305 | ||
19306 | immlo = inst.operands[1].imm; | |
19307 | if (inst.operands[1].regisimm) | |
19308 | immhi = inst.operands[1].reg; | |
19309 | ||
19310 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 19311 | _("immediate has bits set outside the operand size")); |
5287ad62 | 19312 | |
c96612cc JB |
19313 | float_p = inst.operands[1].immisfloat; |
19314 | ||
19315 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 19316 | et.size, et.type)) == FAIL) |
5287ad62 JB |
19317 | { |
19318 | /* Invert relevant bits only. */ | |
19319 | neon_invert_size (&immlo, &immhi, et.size); | |
19320 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
19321 | with one or the other; those cases are caught by |
19322 | neon_cmode_for_move_imm. */ | |
5287ad62 | 19323 | op = !op; |
c96612cc JB |
19324 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
19325 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
19326 | { |
19327 | first_error (_("immediate out of range")); | |
19328 | return; | |
19329 | } | |
5287ad62 JB |
19330 | } |
19331 | ||
19332 | inst.instruction &= ~(1 << 5); | |
19333 | inst.instruction |= op << 5; | |
19334 | ||
19335 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19336 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 19337 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
19338 | inst.instruction |= cmode << 8; |
19339 | ||
19340 | neon_write_immbits (immbits); | |
19341 | } | |
19342 | ||
19343 | static void | |
19344 | do_neon_mvn (void) | |
19345 | { | |
64c350f2 | 19346 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
1a186d29 AV |
19347 | return; |
19348 | ||
5287ad62 JB |
19349 | if (inst.operands[1].isreg) |
19350 | { | |
1a186d29 AV |
19351 | enum neon_shape rs; |
19352 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19353 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
19354 | else | |
19355 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
5f4273c7 | 19356 | |
88714cb8 | 19357 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
19358 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19359 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19360 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19361 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 19362 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
19363 | } |
19364 | else | |
19365 | { | |
88714cb8 | 19366 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
19367 | neon_move_immediate (); |
19368 | } | |
19369 | ||
88714cb8 | 19370 | neon_dp_fixup (&inst); |
1a186d29 AV |
19371 | |
19372 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19373 | { | |
19374 | constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU); | |
19375 | constraint ((inst.instruction & 0xd00) == 0xd00, | |
19376 | _("immediate value out of range")); | |
19377 | } | |
5287ad62 JB |
19378 | } |
19379 | ||
19380 | /* Encode instructions of form: | |
19381 | ||
19382 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 19383 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
19384 | |
19385 | static void | |
19386 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
19387 | { | |
19388 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19389 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19390 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
19391 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
19392 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
19393 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
19394 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
19395 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 19396 | |
88714cb8 | 19397 | neon_dp_fixup (&inst); |
5287ad62 JB |
19398 | } |
19399 | ||
19400 | static void | |
19401 | do_neon_dyadic_long (void) | |
19402 | { | |
5ee91343 AV |
19403 | enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL); |
19404 | if (rs == NS_QDD) | |
19405 | { | |
19406 | if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL) | |
19407 | return; | |
19408 | ||
19409 | NEON_ENCODE (INTEGER, inst); | |
19410 | /* FIXME: Type checking for lengthening op. */ | |
19411 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
19412 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
19413 | neon_mixed_length (et, et.size); | |
19414 | } | |
19415 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19416 | && (inst.cond == 0xf || inst.cond == 0x10)) | |
19417 | { | |
19418 | /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd | |
19419 | in an IT block with le/lt conditions. */ | |
19420 | ||
19421 | if (inst.cond == 0xf) | |
19422 | inst.cond = 0xb; | |
19423 | else if (inst.cond == 0x10) | |
19424 | inst.cond = 0xd; | |
19425 | ||
19426 | inst.pred_insn_type = INSIDE_IT_INSN; | |
19427 | ||
19428 | if (inst.instruction == N_MNEM_vaddl) | |
19429 | { | |
19430 | inst.instruction = N_MNEM_vadd; | |
19431 | do_neon_addsub_if_i (); | |
19432 | } | |
19433 | else if (inst.instruction == N_MNEM_vsubl) | |
19434 | { | |
19435 | inst.instruction = N_MNEM_vsub; | |
19436 | do_neon_addsub_if_i (); | |
19437 | } | |
19438 | else if (inst.instruction == N_MNEM_vabdl) | |
19439 | { | |
19440 | inst.instruction = N_MNEM_vabd; | |
19441 | do_neon_dyadic_if_su (); | |
19442 | } | |
19443 | } | |
19444 | else | |
19445 | first_error (BAD_FPU); | |
5287ad62 JB |
19446 | } |
19447 | ||
19448 | static void | |
19449 | do_neon_abal (void) | |
19450 | { | |
19451 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
19452 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
19453 | neon_mixed_length (et, et.size); | |
19454 | } | |
19455 | ||
19456 | static void | |
19457 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
19458 | { | |
19459 | if (inst.operands[2].isscalar) | |
19460 | { | |
dcbf9037 | 19461 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 19462 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 19463 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
19464 | neon_mul_mac (et, et.type == NT_unsigned); |
19465 | } | |
19466 | else | |
19467 | { | |
19468 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 19469 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 19470 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
19471 | neon_mixed_length (et, et.size); |
19472 | } | |
19473 | } | |
19474 | ||
19475 | static void | |
19476 | do_neon_mac_maybe_scalar_long (void) | |
19477 | { | |
19478 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
19479 | } | |
19480 | ||
dec41383 JW |
19481 | /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's |
19482 | internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */ | |
19483 | ||
19484 | static unsigned | |
19485 | neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p) | |
19486 | { | |
19487 | unsigned regno = NEON_SCALAR_REG (scalar); | |
19488 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
19489 | ||
19490 | if (quad_p) | |
19491 | { | |
19492 | if (regno > 7 || elno > 3) | |
19493 | goto bad_scalar; | |
19494 | ||
19495 | return ((regno & 0x7) | |
19496 | | ((elno & 0x1) << 3) | |
19497 | | (((elno >> 1) & 0x1) << 5)); | |
19498 | } | |
19499 | else | |
19500 | { | |
19501 | if (regno > 15 || elno > 1) | |
19502 | goto bad_scalar; | |
19503 | ||
19504 | return (((regno & 0x1) << 5) | |
19505 | | ((regno >> 1) & 0x7) | |
19506 | | ((elno & 0x1) << 3)); | |
19507 | } | |
19508 | ||
19509 | bad_scalar: | |
19510 | first_error (_("scalar out of range for multiply instruction")); | |
19511 | return 0; | |
19512 | } | |
19513 | ||
19514 | static void | |
19515 | do_neon_fmac_maybe_scalar_long (int subtype) | |
19516 | { | |
19517 | enum neon_shape rs; | |
19518 | int high8; | |
19519 | /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size" | |
19520 | field (bits[21:20]) has different meaning. For scalar index variant, it's | |
19521 | used to differentiate add and subtract, otherwise it's with fixed value | |
19522 | 0x2. */ | |
19523 | int size = -1; | |
19524 | ||
19525 | if (inst.cond != COND_ALWAYS) | |
19526 | as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the " | |
19527 | "behaviour is UNPREDICTABLE")); | |
19528 | ||
01f48020 | 19529 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml), |
dec41383 JW |
19530 | _(BAD_FP16)); |
19531 | ||
19532 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
19533 | _(BAD_FPU)); | |
19534 | ||
19535 | /* vfmal/vfmsl are in three-same D/Q register format or the third operand can | |
19536 | be a scalar index register. */ | |
19537 | if (inst.operands[2].isscalar) | |
19538 | { | |
19539 | high8 = 0xfe000000; | |
19540 | if (subtype) | |
19541 | size = 16; | |
19542 | rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL); | |
19543 | } | |
19544 | else | |
19545 | { | |
19546 | high8 = 0xfc000000; | |
19547 | size = 32; | |
19548 | if (subtype) | |
19549 | inst.instruction |= (0x1 << 23); | |
19550 | rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL); | |
19551 | } | |
19552 | ||
19553 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16); | |
19554 | ||
19555 | /* "opcode" from template has included "ubit", so simply pass 0 here. Also, | |
19556 | the "S" bit in size field has been reused to differentiate vfmal and vfmsl, | |
19557 | so we simply pass -1 as size. */ | |
19558 | unsigned quad_p = (rs == NS_QDD || rs == NS_QDS); | |
19559 | neon_three_same (quad_p, 0, size); | |
19560 | ||
19561 | /* Undo neon_dp_fixup. Redo the high eight bits. */ | |
19562 | inst.instruction &= 0x00ffffff; | |
19563 | inst.instruction |= high8; | |
19564 | ||
19565 | #define LOW1(R) ((R) & 0x1) | |
19566 | #define HI4(R) (((R) >> 1) & 0xf) | |
19567 | /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on | |
19568 | whether the instruction is in Q form and whether Vm is a scalar indexed | |
19569 | operand. */ | |
19570 | if (inst.operands[2].isscalar) | |
19571 | { | |
19572 | unsigned rm | |
19573 | = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p); | |
19574 | inst.instruction &= 0xffffffd0; | |
19575 | inst.instruction |= rm; | |
19576 | ||
19577 | if (!quad_p) | |
19578 | { | |
19579 | /* Redo Rn as well. */ | |
19580 | inst.instruction &= 0xfff0ff7f; | |
19581 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; | |
19582 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; | |
19583 | } | |
19584 | } | |
19585 | else if (!quad_p) | |
19586 | { | |
19587 | /* Redo Rn and Rm. */ | |
19588 | inst.instruction &= 0xfff0ff50; | |
19589 | inst.instruction |= HI4 (inst.operands[1].reg) << 16; | |
19590 | inst.instruction |= LOW1 (inst.operands[1].reg) << 7; | |
19591 | inst.instruction |= HI4 (inst.operands[2].reg); | |
19592 | inst.instruction |= LOW1 (inst.operands[2].reg) << 5; | |
19593 | } | |
19594 | } | |
19595 | ||
19596 | static void | |
19597 | do_neon_vfmal (void) | |
19598 | { | |
19599 | return do_neon_fmac_maybe_scalar_long (0); | |
19600 | } | |
19601 | ||
19602 | static void | |
19603 | do_neon_vfmsl (void) | |
19604 | { | |
19605 | return do_neon_fmac_maybe_scalar_long (1); | |
19606 | } | |
19607 | ||
5287ad62 JB |
19608 | static void |
19609 | do_neon_dyadic_wide (void) | |
19610 | { | |
19611 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
19612 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
19613 | neon_mixed_length (et, et.size); | |
19614 | } | |
19615 | ||
19616 | static void | |
19617 | do_neon_dyadic_narrow (void) | |
19618 | { | |
19619 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
19620 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
19621 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
19622 | so force the operand type to integer. */ | |
19623 | et.type = NT_integer; | |
5287ad62 JB |
19624 | neon_mixed_length (et, et.size / 2); |
19625 | } | |
19626 | ||
19627 | static void | |
19628 | do_neon_mul_sat_scalar_long (void) | |
19629 | { | |
19630 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
19631 | } | |
19632 | ||
19633 | static void | |
19634 | do_neon_vmull (void) | |
19635 | { | |
19636 | if (inst.operands[2].isscalar) | |
19637 | do_neon_mac_maybe_scalar_long (); | |
19638 | else | |
19639 | { | |
19640 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 19641 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 19642 | |
5287ad62 | 19643 | if (et.type == NT_poly) |
477330fc | 19644 | NEON_ENCODE (POLY, inst); |
5287ad62 | 19645 | else |
477330fc | 19646 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
19647 | |
19648 | /* For polynomial encoding the U bit must be zero, and the size must | |
19649 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
19650 | obviously, as 0b10). */ | |
19651 | if (et.size == 64) | |
19652 | { | |
19653 | /* Check we're on the correct architecture. */ | |
19654 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
19655 | inst.error = | |
19656 | _("Instruction form not available on this architecture."); | |
19657 | ||
19658 | et.size = 32; | |
19659 | } | |
19660 | ||
5287ad62 JB |
19661 | neon_mixed_length (et, et.size); |
19662 | } | |
19663 | } | |
19664 | ||
19665 | static void | |
19666 | do_neon_ext (void) | |
19667 | { | |
037e8744 | 19668 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
19669 | struct neon_type_el et = neon_check_type (3, rs, |
19670 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
19671 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
19672 | |
19673 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
19674 | _("shift out of range")); | |
5287ad62 JB |
19675 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19676 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19677 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
19678 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
19679 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
19680 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 19681 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 19682 | inst.instruction |= imm << 8; |
5f4273c7 | 19683 | |
88714cb8 | 19684 | neon_dp_fixup (&inst); |
5287ad62 JB |
19685 | } |
19686 | ||
19687 | static void | |
19688 | do_neon_rev (void) | |
19689 | { | |
64c350f2 | 19690 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
19691 | return; |
19692 | ||
19693 | enum neon_shape rs; | |
19694 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19695 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
19696 | else | |
19697 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
19698 | ||
5287ad62 JB |
19699 | struct neon_type_el et = neon_check_type (2, rs, |
19700 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
4401c241 | 19701 | |
5287ad62 JB |
19702 | unsigned op = (inst.instruction >> 7) & 3; |
19703 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
19704 | extract it here to check the elements to be reversed are smaller. | |
19705 | Otherwise we'd get a reserved instruction. */ | |
19706 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
4401c241 AV |
19707 | |
19708 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64 | |
19709 | && inst.operands[0].reg == inst.operands[1].reg) | |
19710 | as_tsktsk (_("Warning: 64-bit element size and same destination and source" | |
19711 | " operands makes instruction UNPREDICTABLE")); | |
19712 | ||
9c2799c2 | 19713 | gas_assert (elsize != 0); |
5287ad62 | 19714 | constraint (et.size >= elsize, |
477330fc | 19715 | _("elements must be smaller than reversal region")); |
037e8744 | 19716 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
19717 | } |
19718 | ||
19719 | static void | |
19720 | do_neon_dup (void) | |
19721 | { | |
19722 | if (inst.operands[1].isscalar) | |
19723 | { | |
b409bdb6 AV |
19724 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), |
19725 | BAD_FPU); | |
037e8744 | 19726 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 19727 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 19728 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 19729 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 19730 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 19731 | int logsize = neon_logbits (et.size); |
dcbf9037 | 19732 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
19733 | |
19734 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 19735 | return; |
037e8744 | 19736 | |
88714cb8 | 19737 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
19738 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
19739 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19740 | inst.instruction |= LOW4 (dm); | |
19741 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 19742 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
19743 | inst.instruction |= x << 17; |
19744 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 19745 | |
88714cb8 | 19746 | neon_dp_fixup (&inst); |
5287ad62 JB |
19747 | } |
19748 | else | |
19749 | { | |
037e8744 JB |
19750 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
19751 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 19752 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
b409bdb6 AV |
19753 | if (rs == NS_QR) |
19754 | { | |
64c350f2 | 19755 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH)) |
b409bdb6 AV |
19756 | return; |
19757 | } | |
19758 | else | |
19759 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), | |
19760 | BAD_FPU); | |
19761 | ||
19762 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19763 | { | |
19764 | if (inst.operands[1].reg == REG_SP) | |
19765 | as_tsktsk (MVE_BAD_SP); | |
19766 | else if (inst.operands[1].reg == REG_PC) | |
19767 | as_tsktsk (MVE_BAD_PC); | |
19768 | } | |
19769 | ||
5287ad62 | 19770 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 19771 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 19772 | switch (et.size) |
477330fc RM |
19773 | { |
19774 | case 8: inst.instruction |= 0x400000; break; | |
19775 | case 16: inst.instruction |= 0x000020; break; | |
19776 | case 32: inst.instruction |= 0x000000; break; | |
19777 | default: break; | |
19778 | } | |
5287ad62 JB |
19779 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
19780 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
19781 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 19782 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 19783 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 19784 | variants, except for the condition field. */ |
037e8744 | 19785 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
19786 | } |
19787 | } | |
19788 | ||
57785aa2 AV |
19789 | static void |
19790 | do_mve_mov (int toQ) | |
19791 | { | |
19792 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19793 | return; | |
19794 | if (inst.cond > COND_ALWAYS) | |
19795 | inst.pred_insn_type = MVE_UNPREDICABLE_INSN; | |
19796 | ||
19797 | unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; | |
19798 | if (toQ) | |
19799 | { | |
19800 | Q0 = 0; | |
19801 | Q1 = 1; | |
19802 | Rt = 2; | |
19803 | Rt2 = 3; | |
19804 | } | |
19805 | ||
19806 | constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2, | |
19807 | _("Index one must be [2,3] and index two must be two less than" | |
19808 | " index one.")); | |
19809 | constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg, | |
19810 | _("General purpose registers may not be the same")); | |
19811 | constraint (inst.operands[Rt].reg == REG_SP | |
19812 | || inst.operands[Rt2].reg == REG_SP, | |
19813 | BAD_SP); | |
19814 | constraint (inst.operands[Rt].reg == REG_PC | |
19815 | || inst.operands[Rt2].reg == REG_PC, | |
19816 | BAD_PC); | |
19817 | ||
19818 | inst.instruction = 0xec000f00; | |
19819 | inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23; | |
19820 | inst.instruction |= !!toQ << 20; | |
19821 | inst.instruction |= inst.operands[Rt2].reg << 16; | |
19822 | inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13; | |
19823 | inst.instruction |= (inst.operands[Q1].reg % 4) << 4; | |
19824 | inst.instruction |= inst.operands[Rt].reg; | |
19825 | } | |
19826 | ||
19827 | static void | |
19828 | do_mve_movn (void) | |
19829 | { | |
19830 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
19831 | return; | |
19832 | ||
19833 | if (inst.cond > COND_ALWAYS) | |
19834 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
19835 | else | |
19836 | inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; | |
19837 | ||
19838 | struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32 | |
19839 | | N_KEY); | |
19840 | ||
19841 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19842 | inst.instruction |= (neon_logbits (et.size) - 1) << 18; | |
19843 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19844 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19845 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19846 | inst.is_neon = 1; | |
19847 | ||
19848 | } | |
19849 | ||
5287ad62 JB |
19850 | /* VMOV has particularly many variations. It can be one of: |
19851 | 0. VMOV<c><q> <Qd>, <Qm> | |
19852 | 1. VMOV<c><q> <Dd>, <Dm> | |
19853 | (Register operations, which are VORR with Rm = Rn.) | |
19854 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
19855 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
19856 | (Immediate loads.) | |
19857 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
19858 | (ARM register to scalar.) | |
19859 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
19860 | (Two ARM registers to vector.) | |
19861 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
19862 | (Scalar to ARM register.) | |
19863 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
19864 | (Vector to two ARM registers.) | |
037e8744 JB |
19865 | 8. VMOV.F32 <Sd>, <Sm> |
19866 | 9. VMOV.F64 <Dd>, <Dm> | |
19867 | (VFP register moves.) | |
19868 | 10. VMOV.F32 <Sd>, #imm | |
19869 | 11. VMOV.F64 <Dd>, #imm | |
19870 | (VFP float immediate load.) | |
19871 | 12. VMOV <Rd>, <Sm> | |
19872 | (VFP single to ARM reg.) | |
19873 | 13. VMOV <Sd>, <Rm> | |
19874 | (ARM reg to VFP single.) | |
19875 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
19876 | (Two ARM regs to two VFP singles.) | |
19877 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
19878 | (Two VFP singles to two ARM regs.) | |
57785aa2 AV |
19879 | 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> |
19880 | 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> | |
19881 | 18. VMOV<c>.<dt> <Rt>, <Qn[idx]> | |
19882 | 19. VMOV<c>.<dt> <Qd[idx]>, <Rt> | |
5f4273c7 | 19883 | |
037e8744 JB |
19884 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
19885 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 19886 | |
5287ad62 | 19887 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 19888 | |
b7fc2769 JB |
19889 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
19890 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 19891 | |
5287ad62 | 19892 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 19893 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
19894 | |
19895 | static void | |
19896 | do_neon_mov (void) | |
19897 | { | |
57785aa2 AV |
19898 | enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR, |
19899 | NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI, | |
19900 | NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, | |
19901 | NS_RF, NS_FR, NS_HR, NS_RH, NS_HI, | |
19902 | NS_NULL); | |
037e8744 JB |
19903 | struct neon_type_el et; |
19904 | const char *ldconst = 0; | |
5287ad62 | 19905 | |
037e8744 | 19906 | switch (rs) |
5287ad62 | 19907 | { |
037e8744 JB |
19908 | case NS_DD: /* case 1/9. */ |
19909 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
19910 | /* It is not an error here if no type is given. */ | |
19911 | inst.error = NULL; | |
1c1e0fe5 SP |
19912 | |
19913 | /* In MVE we interpret the following instructions as same, so ignoring | |
19914 | the following type (float) and size (64) checks. | |
19915 | a: VMOV<c><q> <Dd>, <Dm> | |
19916 | b: VMOV<c><q>.F64 <Dd>, <Dm>. */ | |
19917 | if ((et.type == NT_float && et.size == 64) | |
19918 | || (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))) | |
477330fc RM |
19919 | { |
19920 | do_vfp_nsyn_opcode ("fcpyd"); | |
19921 | break; | |
19922 | } | |
037e8744 | 19923 | /* fall through. */ |
5287ad62 | 19924 | |
037e8744 JB |
19925 | case NS_QQ: /* case 0/1. */ |
19926 | { | |
64c350f2 AV |
19927 | if (!check_simd_pred_availability (FALSE, |
19928 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
477330fc RM |
19929 | return; |
19930 | /* The architecture manual I have doesn't explicitly state which | |
19931 | value the U bit should have for register->register moves, but | |
19932 | the equivalent VORR instruction has U = 0, so do that. */ | |
19933 | inst.instruction = 0x0200110; | |
19934 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
19935 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
19936 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
19937 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
19938 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
19939 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
19940 | inst.instruction |= neon_quad (rs) << 6; | |
19941 | ||
19942 | neon_dp_fixup (&inst); | |
037e8744 JB |
19943 | } |
19944 | break; | |
5f4273c7 | 19945 | |
037e8744 JB |
19946 | case NS_DI: /* case 3/11. */ |
19947 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
19948 | inst.error = NULL; | |
19949 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
19950 | { |
19951 | /* case 11 (fconstd). */ | |
19952 | ldconst = "fconstd"; | |
19953 | goto encode_fconstd; | |
19954 | } | |
037e8744 JB |
19955 | /* fall through. */ |
19956 | ||
19957 | case NS_QI: /* case 2/3. */ | |
64c350f2 AV |
19958 | if (!check_simd_pred_availability (FALSE, |
19959 | NEON_CHECK_CC | NEON_CHECK_ARCH)) | |
477330fc | 19960 | return; |
037e8744 JB |
19961 | inst.instruction = 0x0800010; |
19962 | neon_move_immediate (); | |
88714cb8 | 19963 | neon_dp_fixup (&inst); |
5287ad62 | 19964 | break; |
5f4273c7 | 19965 | |
037e8744 JB |
19966 | case NS_SR: /* case 4. */ |
19967 | { | |
477330fc RM |
19968 | unsigned bcdebits = 0; |
19969 | int logsize; | |
19970 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
19971 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 19972 | |
05ac0ffb JB |
19973 | /* .<size> is optional here, defaulting to .32. */ |
19974 | if (inst.vectype.elems == 0 | |
19975 | && inst.operands[0].vectype.type == NT_invtype | |
19976 | && inst.operands[1].vectype.type == NT_invtype) | |
19977 | { | |
19978 | inst.vectype.el[0].type = NT_untyped; | |
19979 | inst.vectype.el[0].size = 32; | |
19980 | inst.vectype.elems = 1; | |
19981 | } | |
19982 | ||
477330fc RM |
19983 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
19984 | logsize = neon_logbits (et.size); | |
19985 | ||
57785aa2 AV |
19986 | if (et.size != 32) |
19987 | { | |
19988 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
19989 | && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL) | |
19990 | return; | |
19991 | } | |
19992 | else | |
19993 | { | |
19994 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) | |
19995 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
19996 | _(BAD_FPU)); | |
19997 | } | |
19998 | ||
19999 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20000 | { | |
20001 | if (inst.operands[1].reg == REG_SP) | |
20002 | as_tsktsk (MVE_BAD_SP); | |
20003 | else if (inst.operands[1].reg == REG_PC) | |
20004 | as_tsktsk (MVE_BAD_PC); | |
20005 | } | |
20006 | unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128; | |
20007 | ||
477330fc | 20008 | constraint (et.type == NT_invtype, _("bad type for scalar")); |
57785aa2 AV |
20009 | constraint (x >= size / et.size, _("scalar index out of range")); |
20010 | ||
477330fc RM |
20011 | |
20012 | switch (et.size) | |
20013 | { | |
20014 | case 8: bcdebits = 0x8; break; | |
20015 | case 16: bcdebits = 0x1; break; | |
20016 | case 32: bcdebits = 0x0; break; | |
20017 | default: ; | |
20018 | } | |
20019 | ||
57785aa2 | 20020 | bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize; |
477330fc RM |
20021 | |
20022 | inst.instruction = 0xe000b10; | |
20023 | do_vfp_cond_or_thumb (); | |
20024 | inst.instruction |= LOW4 (dn) << 16; | |
20025 | inst.instruction |= HI1 (dn) << 7; | |
20026 | inst.instruction |= inst.operands[1].reg << 12; | |
20027 | inst.instruction |= (bcdebits & 3) << 5; | |
57785aa2 AV |
20028 | inst.instruction |= ((bcdebits >> 2) & 3) << 21; |
20029 | inst.instruction |= (x >> (3-logsize)) << 16; | |
037e8744 JB |
20030 | } |
20031 | break; | |
5f4273c7 | 20032 | |
037e8744 | 20033 | case NS_DRR: /* case 5 (fmdrr). */ |
57785aa2 AV |
20034 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
20035 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
477330fc | 20036 | _(BAD_FPU)); |
b7fc2769 | 20037 | |
037e8744 JB |
20038 | inst.instruction = 0xc400b10; |
20039 | do_vfp_cond_or_thumb (); | |
20040 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
20041 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
20042 | inst.instruction |= inst.operands[1].reg << 12; | |
20043 | inst.instruction |= inst.operands[2].reg << 16; | |
20044 | break; | |
5f4273c7 | 20045 | |
037e8744 JB |
20046 | case NS_RS: /* case 6. */ |
20047 | { | |
477330fc RM |
20048 | unsigned logsize; |
20049 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
20050 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
20051 | unsigned abcdebits = 0; | |
037e8744 | 20052 | |
05ac0ffb JB |
20053 | /* .<dt> is optional here, defaulting to .32. */ |
20054 | if (inst.vectype.elems == 0 | |
20055 | && inst.operands[0].vectype.type == NT_invtype | |
20056 | && inst.operands[1].vectype.type == NT_invtype) | |
20057 | { | |
20058 | inst.vectype.el[0].type = NT_untyped; | |
20059 | inst.vectype.el[0].size = 32; | |
20060 | inst.vectype.elems = 1; | |
20061 | } | |
20062 | ||
91d6fa6a NC |
20063 | et = neon_check_type (2, NS_NULL, |
20064 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
20065 | logsize = neon_logbits (et.size); |
20066 | ||
57785aa2 AV |
20067 | if (et.size != 32) |
20068 | { | |
20069 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) | |
20070 | && vfp_or_neon_is_neon (NEON_CHECK_CC | |
20071 | | NEON_CHECK_ARCH) == FAIL) | |
20072 | return; | |
20073 | } | |
20074 | else | |
20075 | { | |
20076 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) | |
20077 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
20078 | _(BAD_FPU)); | |
20079 | } | |
20080 | ||
20081 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20082 | { | |
20083 | if (inst.operands[0].reg == REG_SP) | |
20084 | as_tsktsk (MVE_BAD_SP); | |
20085 | else if (inst.operands[0].reg == REG_PC) | |
20086 | as_tsktsk (MVE_BAD_PC); | |
20087 | } | |
20088 | ||
20089 | unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128; | |
20090 | ||
477330fc | 20091 | constraint (et.type == NT_invtype, _("bad type for scalar")); |
57785aa2 | 20092 | constraint (x >= size / et.size, _("scalar index out of range")); |
477330fc RM |
20093 | |
20094 | switch (et.size) | |
20095 | { | |
20096 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
20097 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
20098 | case 32: abcdebits = 0x00; break; | |
20099 | default: ; | |
20100 | } | |
20101 | ||
57785aa2 | 20102 | abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize; |
477330fc RM |
20103 | inst.instruction = 0xe100b10; |
20104 | do_vfp_cond_or_thumb (); | |
20105 | inst.instruction |= LOW4 (dn) << 16; | |
20106 | inst.instruction |= HI1 (dn) << 7; | |
20107 | inst.instruction |= inst.operands[0].reg << 12; | |
20108 | inst.instruction |= (abcdebits & 3) << 5; | |
20109 | inst.instruction |= (abcdebits >> 2) << 21; | |
57785aa2 | 20110 | inst.instruction |= (x >> (3-logsize)) << 16; |
037e8744 JB |
20111 | } |
20112 | break; | |
5f4273c7 | 20113 | |
037e8744 | 20114 | case NS_RRD: /* case 7 (fmrrd). */ |
57785aa2 AV |
20115 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
20116 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
477330fc | 20117 | _(BAD_FPU)); |
037e8744 JB |
20118 | |
20119 | inst.instruction = 0xc500b10; | |
20120 | do_vfp_cond_or_thumb (); | |
20121 | inst.instruction |= inst.operands[0].reg << 12; | |
20122 | inst.instruction |= inst.operands[1].reg << 16; | |
20123 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
20124 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
20125 | break; | |
5f4273c7 | 20126 | |
037e8744 JB |
20127 | case NS_FF: /* case 8 (fcpys). */ |
20128 | do_vfp_nsyn_opcode ("fcpys"); | |
20129 | break; | |
5f4273c7 | 20130 | |
9db2f6b4 | 20131 | case NS_HI: |
037e8744 JB |
20132 | case NS_FI: /* case 10 (fconsts). */ |
20133 | ldconst = "fconsts"; | |
4ef4710f | 20134 | encode_fconstd: |
58ed5c38 TC |
20135 | if (!inst.operands[1].immisfloat) |
20136 | { | |
4ef4710f | 20137 | unsigned new_imm; |
58ed5c38 | 20138 | /* Immediate has to fit in 8 bits so float is enough. */ |
4ef4710f NC |
20139 | float imm = (float) inst.operands[1].imm; |
20140 | memcpy (&new_imm, &imm, sizeof (float)); | |
20141 | /* But the assembly may have been written to provide an integer | |
20142 | bit pattern that equates to a float, so check that the | |
20143 | conversion has worked. */ | |
20144 | if (is_quarter_float (new_imm)) | |
20145 | { | |
20146 | if (is_quarter_float (inst.operands[1].imm)) | |
20147 | as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)")); | |
20148 | ||
20149 | inst.operands[1].imm = new_imm; | |
20150 | inst.operands[1].immisfloat = 1; | |
20151 | } | |
58ed5c38 TC |
20152 | } |
20153 | ||
037e8744 | 20154 | if (is_quarter_float (inst.operands[1].imm)) |
477330fc RM |
20155 | { |
20156 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
20157 | do_vfp_nsyn_opcode (ldconst); | |
9db2f6b4 RL |
20158 | |
20159 | /* ARMv8.2 fp16 vmov.f16 instruction. */ | |
20160 | if (rs == NS_HI) | |
20161 | do_scalar_fp16_v82_encode (); | |
477330fc | 20162 | } |
5287ad62 | 20163 | else |
477330fc | 20164 | first_error (_("immediate out of range")); |
037e8744 | 20165 | break; |
5f4273c7 | 20166 | |
9db2f6b4 | 20167 | case NS_RH: |
037e8744 JB |
20168 | case NS_RF: /* case 12 (fmrs). */ |
20169 | do_vfp_nsyn_opcode ("fmrs"); | |
9db2f6b4 RL |
20170 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
20171 | if (rs == NS_RH) | |
20172 | do_scalar_fp16_v82_encode (); | |
037e8744 | 20173 | break; |
5f4273c7 | 20174 | |
9db2f6b4 | 20175 | case NS_HR: |
037e8744 JB |
20176 | case NS_FR: /* case 13 (fmsr). */ |
20177 | do_vfp_nsyn_opcode ("fmsr"); | |
9db2f6b4 RL |
20178 | /* ARMv8.2 fp16 vmov.f16 instruction. */ |
20179 | if (rs == NS_HR) | |
20180 | do_scalar_fp16_v82_encode (); | |
037e8744 | 20181 | break; |
5f4273c7 | 20182 | |
57785aa2 AV |
20183 | case NS_RRSS: |
20184 | do_mve_mov (0); | |
20185 | break; | |
20186 | case NS_SSRR: | |
20187 | do_mve_mov (1); | |
20188 | break; | |
20189 | ||
037e8744 JB |
20190 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
20191 | (one of which is a list), but we have parsed four. Do some fiddling to | |
20192 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
20193 | expect. */ | |
20194 | case NS_RRFF: /* case 14 (fmrrs). */ | |
57785aa2 AV |
20195 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
20196 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
20197 | _(BAD_FPU)); | |
037e8744 | 20198 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, |
477330fc | 20199 | _("VFP registers must be adjacent")); |
037e8744 JB |
20200 | inst.operands[2].imm = 2; |
20201 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
20202 | do_vfp_nsyn_opcode ("fmrrs"); | |
20203 | break; | |
5f4273c7 | 20204 | |
037e8744 | 20205 | case NS_FFRR: /* case 15 (fmsrr). */ |
57785aa2 AV |
20206 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) |
20207 | && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), | |
20208 | _(BAD_FPU)); | |
037e8744 | 20209 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, |
477330fc | 20210 | _("VFP registers must be adjacent")); |
037e8744 JB |
20211 | inst.operands[1] = inst.operands[2]; |
20212 | inst.operands[2] = inst.operands[3]; | |
20213 | inst.operands[0].imm = 2; | |
20214 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
20215 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 20216 | break; |
5f4273c7 | 20217 | |
4c261dff NC |
20218 | case NS_NULL: |
20219 | /* neon_select_shape has determined that the instruction | |
20220 | shape is wrong and has already set the error message. */ | |
20221 | break; | |
20222 | ||
5287ad62 JB |
20223 | default: |
20224 | abort (); | |
20225 | } | |
20226 | } | |
20227 | ||
57785aa2 AV |
20228 | static void |
20229 | do_mve_movl (void) | |
20230 | { | |
20231 | if (!(inst.operands[0].present && inst.operands[0].isquad | |
20232 | && inst.operands[1].present && inst.operands[1].isquad | |
20233 | && !inst.operands[2].present)) | |
20234 | { | |
20235 | inst.instruction = 0; | |
20236 | inst.cond = 0xb; | |
20237 | if (thumb_mode) | |
20238 | set_pred_insn_type (INSIDE_IT_INSN); | |
20239 | do_neon_mov (); | |
20240 | return; | |
20241 | } | |
20242 | ||
20243 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20244 | return; | |
20245 | ||
20246 | if (inst.cond != COND_ALWAYS) | |
20247 | inst.pred_insn_type = INSIDE_VPT_INSN; | |
20248 | ||
20249 | struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8 | |
20250 | | N_S16 | N_U16 | N_KEY); | |
20251 | ||
20252 | inst.instruction |= (et.type == NT_unsigned) << 28; | |
20253 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20254 | inst.instruction |= (neon_logbits (et.size) + 1) << 19; | |
20255 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20256 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
20257 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
20258 | inst.is_neon = 1; | |
20259 | } | |
20260 | ||
5287ad62 JB |
20261 | static void |
20262 | do_neon_rshift_round_imm (void) | |
20263 | { | |
64c350f2 | 20264 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
4401c241 AV |
20265 | return; |
20266 | ||
20267 | enum neon_shape rs; | |
20268 | struct neon_type_el et; | |
20269 | ||
20270 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20271 | { | |
20272 | rs = neon_select_shape (NS_QQI, NS_NULL); | |
20273 | et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY); | |
20274 | } | |
20275 | else | |
20276 | { | |
20277 | rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); | |
20278 | et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); | |
20279 | } | |
5287ad62 JB |
20280 | int imm = inst.operands[2].imm; |
20281 | ||
20282 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
20283 | if (imm == 0) | |
20284 | { | |
20285 | inst.operands[2].present = 0; | |
20286 | do_neon_mov (); | |
20287 | return; | |
20288 | } | |
20289 | ||
20290 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 20291 | _("immediate out of range for shift")); |
037e8744 | 20292 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 20293 | et.size - imm); |
5287ad62 JB |
20294 | } |
20295 | ||
9db2f6b4 RL |
20296 | static void |
20297 | do_neon_movhf (void) | |
20298 | { | |
20299 | enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL); | |
20300 | constraint (rs != NS_HH, _("invalid suffix")); | |
20301 | ||
7bdf778b ASDV |
20302 | if (inst.cond != COND_ALWAYS) |
20303 | { | |
20304 | if (thumb_mode) | |
20305 | { | |
20306 | as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional," | |
20307 | " the behaviour is UNPREDICTABLE")); | |
20308 | } | |
20309 | else | |
20310 | { | |
20311 | inst.error = BAD_COND; | |
20312 | return; | |
20313 | } | |
20314 | } | |
20315 | ||
9db2f6b4 RL |
20316 | do_vfp_sp_monadic (); |
20317 | ||
20318 | inst.is_neon = 1; | |
20319 | inst.instruction |= 0xf0000000; | |
20320 | } | |
20321 | ||
5287ad62 JB |
20322 | static void |
20323 | do_neon_movl (void) | |
20324 | { | |
20325 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
20326 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
20327 | unsigned sizebits = et.size >> 3; | |
20328 | inst.instruction |= sizebits << 19; | |
20329 | neon_two_same (0, et.type == NT_unsigned, -1); | |
20330 | } | |
20331 | ||
20332 | static void | |
20333 | do_neon_trn (void) | |
20334 | { | |
037e8744 | 20335 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20336 | struct neon_type_el et = neon_check_type (2, rs, |
20337 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 20338 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 20339 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20340 | } |
20341 | ||
20342 | static void | |
20343 | do_neon_zip_uzp (void) | |
20344 | { | |
037e8744 | 20345 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20346 | struct neon_type_el et = neon_check_type (2, rs, |
20347 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
20348 | if (rs == NS_DD && et.size == 32) | |
20349 | { | |
20350 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
20351 | inst.instruction = N_MNEM_vtrn; | |
20352 | do_neon_trn (); | |
20353 | return; | |
20354 | } | |
037e8744 | 20355 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20356 | } |
20357 | ||
20358 | static void | |
20359 | do_neon_sat_abs_neg (void) | |
20360 | { | |
64c350f2 | 20361 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH)) |
1a186d29 AV |
20362 | return; |
20363 | ||
20364 | enum neon_shape rs; | |
20365 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20366 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
20367 | else | |
20368 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
5287ad62 JB |
20369 | struct neon_type_el et = neon_check_type (2, rs, |
20370 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 20371 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20372 | } |
20373 | ||
20374 | static void | |
20375 | do_neon_pair_long (void) | |
20376 | { | |
037e8744 | 20377 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20378 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
20379 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
20380 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 20381 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20382 | } |
20383 | ||
20384 | static void | |
20385 | do_neon_recip_est (void) | |
20386 | { | |
037e8744 | 20387 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 | 20388 | struct neon_type_el et = neon_check_type (2, rs, |
cc933301 | 20389 | N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY); |
5287ad62 | 20390 | inst.instruction |= (et.type == NT_float) << 8; |
037e8744 | 20391 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20392 | } |
20393 | ||
20394 | static void | |
20395 | do_neon_cls (void) | |
20396 | { | |
64c350f2 | 20397 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
f30ee27c AV |
20398 | return; |
20399 | ||
20400 | enum neon_shape rs; | |
20401 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20402 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
20403 | else | |
20404 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
20405 | ||
5287ad62 JB |
20406 | struct neon_type_el et = neon_check_type (2, rs, |
20407 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 20408 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20409 | } |
20410 | ||
20411 | static void | |
20412 | do_neon_clz (void) | |
20413 | { | |
64c350f2 | 20414 | if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC)) |
f30ee27c AV |
20415 | return; |
20416 | ||
20417 | enum neon_shape rs; | |
20418 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
20419 | rs = neon_select_shape (NS_QQ, NS_NULL); | |
20420 | else | |
20421 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
20422 | ||
5287ad62 JB |
20423 | struct neon_type_el et = neon_check_type (2, rs, |
20424 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 20425 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20426 | } |
20427 | ||
20428 | static void | |
20429 | do_neon_cnt (void) | |
20430 | { | |
037e8744 | 20431 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
20432 | struct neon_type_el et = neon_check_type (2, rs, |
20433 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 20434 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
20435 | } |
20436 | ||
20437 | static void | |
20438 | do_neon_swp (void) | |
20439 | { | |
037e8744 JB |
20440 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
20441 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
20442 | } |
20443 | ||
20444 | static void | |
20445 | do_neon_tbl_tbx (void) | |
20446 | { | |
20447 | unsigned listlenbits; | |
dcbf9037 | 20448 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 20449 | |
5287ad62 JB |
20450 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
20451 | { | |
dcbf9037 | 20452 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
20453 | return; |
20454 | } | |
5f4273c7 | 20455 | |
5287ad62 JB |
20456 | listlenbits = inst.operands[1].imm - 1; |
20457 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20458 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20459 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
20460 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
20461 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
20462 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
20463 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 20464 | |
88714cb8 | 20465 | neon_dp_fixup (&inst); |
5287ad62 JB |
20466 | } |
20467 | ||
20468 | static void | |
20469 | do_neon_ldm_stm (void) | |
20470 | { | |
20471 | /* P, U and L bits are part of bitmask. */ | |
20472 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
20473 | unsigned offsetbits = inst.operands[1].imm * 2; | |
20474 | ||
037e8744 JB |
20475 | if (inst.operands[1].issingle) |
20476 | { | |
20477 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
20478 | return; | |
20479 | } | |
20480 | ||
5287ad62 | 20481 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 20482 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
20483 | |
20484 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
20485 | _("register list must contain at least 1 and at most 16 " |
20486 | "registers")); | |
5287ad62 JB |
20487 | |
20488 | inst.instruction |= inst.operands[0].reg << 16; | |
20489 | inst.instruction |= inst.operands[0].writeback << 21; | |
20490 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
20491 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
20492 | ||
20493 | inst.instruction |= offsetbits; | |
5f4273c7 | 20494 | |
037e8744 | 20495 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
20496 | } |
20497 | ||
20498 | static void | |
20499 | do_neon_ldr_str (void) | |
20500 | { | |
5287ad62 | 20501 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 20502 | |
6844b2c2 MGD |
20503 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
20504 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 20505 | if (!is_ldr |
6844b2c2 | 20506 | && inst.operands[1].reg == REG_PC |
ba86b375 | 20507 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 20508 | { |
94dcf8bf | 20509 | if (thumb_mode) |
6844b2c2 | 20510 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf | 20511 | else if (warn_on_deprecated) |
5c3696f8 | 20512 | as_tsktsk (_("Use of PC here is deprecated")); |
6844b2c2 MGD |
20513 | } |
20514 | ||
037e8744 JB |
20515 | if (inst.operands[0].issingle) |
20516 | { | |
cd2f129f | 20517 | if (is_ldr) |
477330fc | 20518 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 20519 | else |
477330fc | 20520 | do_vfp_nsyn_opcode ("fsts"); |
9db2f6b4 RL |
20521 | |
20522 | /* ARMv8.2 vldr.16/vstr.16 instruction. */ | |
20523 | if (inst.vectype.el[0].size == 16) | |
20524 | do_scalar_fp16_v82_encode (); | |
5287ad62 JB |
20525 | } |
20526 | else | |
5287ad62 | 20527 | { |
cd2f129f | 20528 | if (is_ldr) |
477330fc | 20529 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 20530 | else |
477330fc | 20531 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 20532 | } |
5287ad62 JB |
20533 | } |
20534 | ||
32c36c3c AV |
20535 | static void |
20536 | do_t_vldr_vstr_sysreg (void) | |
20537 | { | |
20538 | int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20; | |
20539 | bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0); | |
20540 | ||
20541 | /* Use of PC is UNPREDICTABLE. */ | |
20542 | if (inst.operands[1].reg == REG_PC) | |
20543 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
20544 | ||
20545 | if (inst.operands[1].immisreg) | |
20546 | inst.error = _("instruction does not accept register index"); | |
20547 | ||
20548 | if (!inst.operands[1].isreg) | |
20549 | inst.error = _("instruction does not accept PC-relative addressing"); | |
20550 | ||
20551 | if (abs (inst.operands[1].imm) >= (1 << 7)) | |
20552 | inst.error = _("immediate value out of range"); | |
20553 | ||
20554 | inst.instruction = 0xec000f80; | |
20555 | if (is_vldr) | |
20556 | inst.instruction |= 1 << sysreg_vldr_bitno; | |
20557 | encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM); | |
20558 | inst.instruction |= (inst.operands[0].imm & 0x7) << 13; | |
20559 | inst.instruction |= (inst.operands[0].imm & 0x8) << 19; | |
20560 | } | |
20561 | ||
20562 | static void | |
20563 | do_vldr_vstr (void) | |
20564 | { | |
20565 | bfd_boolean sysreg_op = !inst.operands[0].isreg; | |
20566 | ||
20567 | /* VLDR/VSTR (System Register). */ | |
20568 | if (sysreg_op) | |
20569 | { | |
20570 | if (!mark_feature_used (&arm_ext_v8_1m_main)) | |
20571 | as_bad (_("Instruction not permitted on this architecture")); | |
20572 | ||
20573 | do_t_vldr_vstr_sysreg (); | |
20574 | } | |
20575 | /* VLDR/VSTR. */ | |
20576 | else | |
20577 | { | |
20578 | if (!mark_feature_used (&fpu_vfp_ext_v1xd)) | |
20579 | as_bad (_("Instruction not permitted on this architecture")); | |
20580 | do_neon_ldr_str (); | |
20581 | } | |
20582 | } | |
20583 | ||
5287ad62 JB |
20584 | /* "interleave" version also handles non-interleaving register VLD1/VST1 |
20585 | instructions. */ | |
20586 | ||
20587 | static void | |
20588 | do_neon_ld_st_interleave (void) | |
20589 | { | |
037e8744 | 20590 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 20591 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
20592 | unsigned alignbits = 0; |
20593 | unsigned idx; | |
20594 | /* The bits in this table go: | |
20595 | 0: register stride of one (0) or two (1) | |
20596 | 1,2: register list length, minus one (1, 2, 3, 4). | |
20597 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
20598 | We use -1 for invalid entries. */ | |
20599 | const int typetable[] = | |
20600 | { | |
20601 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
20602 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
20603 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
20604 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
20605 | }; | |
20606 | int typebits; | |
20607 | ||
dcbf9037 JB |
20608 | if (et.type == NT_invtype) |
20609 | return; | |
20610 | ||
5287ad62 JB |
20611 | if (inst.operands[1].immisalign) |
20612 | switch (inst.operands[1].imm >> 8) | |
20613 | { | |
20614 | case 64: alignbits = 1; break; | |
20615 | case 128: | |
477330fc | 20616 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 20617 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
20618 | goto bad_alignment; |
20619 | alignbits = 2; | |
20620 | break; | |
5287ad62 | 20621 | case 256: |
477330fc RM |
20622 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
20623 | goto bad_alignment; | |
20624 | alignbits = 3; | |
20625 | break; | |
5287ad62 JB |
20626 | default: |
20627 | bad_alignment: | |
477330fc RM |
20628 | first_error (_("bad alignment")); |
20629 | return; | |
5287ad62 JB |
20630 | } |
20631 | ||
20632 | inst.instruction |= alignbits << 4; | |
20633 | inst.instruction |= neon_logbits (et.size) << 6; | |
20634 | ||
20635 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
20636 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
20637 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
20638 | up the right value for "type" in a table based on this value and the given | |
20639 | list style, then stick it back. */ | |
20640 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 20641 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
20642 | |
20643 | typebits = typetable[idx]; | |
5f4273c7 | 20644 | |
5287ad62 | 20645 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c | 20646 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
35c228db | 20647 | BAD_EL_TYPE); |
5287ad62 JB |
20648 | |
20649 | inst.instruction &= ~0xf00; | |
20650 | inst.instruction |= typebits << 8; | |
20651 | } | |
20652 | ||
20653 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
20654 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
20655 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
20656 | values, terminated with -1. */ | |
20657 | ||
20658 | static int | |
aa8a0863 | 20659 | neon_alignment_bit (int size, int align, int *do_alignment, ...) |
5287ad62 JB |
20660 | { |
20661 | va_list ap; | |
20662 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 20663 | |
5287ad62 JB |
20664 | if (!inst.operands[1].immisalign) |
20665 | { | |
aa8a0863 | 20666 | *do_alignment = 0; |
5287ad62 JB |
20667 | return SUCCESS; |
20668 | } | |
5f4273c7 | 20669 | |
aa8a0863 | 20670 | va_start (ap, do_alignment); |
5287ad62 JB |
20671 | |
20672 | do | |
20673 | { | |
20674 | thissize = va_arg (ap, int); | |
20675 | if (thissize == -1) | |
477330fc | 20676 | break; |
5287ad62 JB |
20677 | thisalign = va_arg (ap, int); |
20678 | ||
20679 | if (size == thissize && align == thisalign) | |
477330fc | 20680 | result = SUCCESS; |
5287ad62 JB |
20681 | } |
20682 | while (result != SUCCESS); | |
20683 | ||
20684 | va_end (ap); | |
20685 | ||
20686 | if (result == SUCCESS) | |
aa8a0863 | 20687 | *do_alignment = 1; |
5287ad62 | 20688 | else |
dcbf9037 | 20689 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 20690 | |
5287ad62 JB |
20691 | return result; |
20692 | } | |
20693 | ||
20694 | static void | |
20695 | do_neon_ld_st_lane (void) | |
20696 | { | |
037e8744 | 20697 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
aa8a0863 | 20698 | int align_good, do_alignment = 0; |
5287ad62 JB |
20699 | int logsize = neon_logbits (et.size); |
20700 | int align = inst.operands[1].imm >> 8; | |
20701 | int n = (inst.instruction >> 8) & 3; | |
20702 | int max_el = 64 / et.size; | |
5f4273c7 | 20703 | |
dcbf9037 JB |
20704 | if (et.type == NT_invtype) |
20705 | return; | |
5f4273c7 | 20706 | |
5287ad62 | 20707 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 20708 | _("bad list length")); |
5287ad62 | 20709 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 20710 | _("scalar index out of range")); |
5287ad62 | 20711 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
20712 | && et.size == 8, |
20713 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 20714 | |
5287ad62 JB |
20715 | switch (n) |
20716 | { | |
20717 | case 0: /* VLD1 / VST1. */ | |
aa8a0863 | 20718 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16, |
477330fc | 20719 | 32, 32, -1); |
5287ad62 | 20720 | if (align_good == FAIL) |
477330fc | 20721 | return; |
aa8a0863 | 20722 | if (do_alignment) |
477330fc RM |
20723 | { |
20724 | unsigned alignbits = 0; | |
20725 | switch (et.size) | |
20726 | { | |
20727 | case 16: alignbits = 0x1; break; | |
20728 | case 32: alignbits = 0x3; break; | |
20729 | default: ; | |
20730 | } | |
20731 | inst.instruction |= alignbits << 4; | |
20732 | } | |
5287ad62 JB |
20733 | break; |
20734 | ||
20735 | case 1: /* VLD2 / VST2. */ | |
aa8a0863 TS |
20736 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16, |
20737 | 16, 32, 32, 64, -1); | |
5287ad62 | 20738 | if (align_good == FAIL) |
477330fc | 20739 | return; |
aa8a0863 | 20740 | if (do_alignment) |
477330fc | 20741 | inst.instruction |= 1 << 4; |
5287ad62 JB |
20742 | break; |
20743 | ||
20744 | case 2: /* VLD3 / VST3. */ | |
20745 | constraint (inst.operands[1].immisalign, | |
477330fc | 20746 | _("can't use alignment with this instruction")); |
5287ad62 JB |
20747 | break; |
20748 | ||
20749 | case 3: /* VLD4 / VST4. */ | |
aa8a0863 | 20750 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
477330fc | 20751 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 20752 | if (align_good == FAIL) |
477330fc | 20753 | return; |
aa8a0863 | 20754 | if (do_alignment) |
477330fc RM |
20755 | { |
20756 | unsigned alignbits = 0; | |
20757 | switch (et.size) | |
20758 | { | |
20759 | case 8: alignbits = 0x1; break; | |
20760 | case 16: alignbits = 0x1; break; | |
20761 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
20762 | default: ; | |
20763 | } | |
20764 | inst.instruction |= alignbits << 4; | |
20765 | } | |
5287ad62 JB |
20766 | break; |
20767 | ||
20768 | default: ; | |
20769 | } | |
20770 | ||
20771 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
20772 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
20773 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 20774 | |
5287ad62 JB |
20775 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
20776 | inst.instruction |= logsize << 10; | |
20777 | } | |
20778 | ||
20779 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
20780 | ||
20781 | static void | |
20782 | do_neon_ld_dup (void) | |
20783 | { | |
037e8744 | 20784 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
aa8a0863 | 20785 | int align_good, do_alignment = 0; |
5287ad62 | 20786 | |
dcbf9037 JB |
20787 | if (et.type == NT_invtype) |
20788 | return; | |
20789 | ||
5287ad62 JB |
20790 | switch ((inst.instruction >> 8) & 3) |
20791 | { | |
20792 | case 0: /* VLD1. */ | |
9c2799c2 | 20793 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 20794 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
aa8a0863 | 20795 | &do_alignment, 16, 16, 32, 32, -1); |
5287ad62 | 20796 | if (align_good == FAIL) |
477330fc | 20797 | return; |
5287ad62 | 20798 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
20799 | { |
20800 | case 1: break; | |
20801 | case 2: inst.instruction |= 1 << 5; break; | |
20802 | default: first_error (_("bad list length")); return; | |
20803 | } | |
5287ad62 JB |
20804 | inst.instruction |= neon_logbits (et.size) << 6; |
20805 | break; | |
20806 | ||
20807 | case 1: /* VLD2. */ | |
20808 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
aa8a0863 TS |
20809 | &do_alignment, 8, 16, 16, 32, 32, 64, |
20810 | -1); | |
5287ad62 | 20811 | if (align_good == FAIL) |
477330fc | 20812 | return; |
5287ad62 | 20813 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 20814 | _("bad list length")); |
5287ad62 | 20815 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 20816 | inst.instruction |= 1 << 5; |
5287ad62 JB |
20817 | inst.instruction |= neon_logbits (et.size) << 6; |
20818 | break; | |
20819 | ||
20820 | case 2: /* VLD3. */ | |
20821 | constraint (inst.operands[1].immisalign, | |
477330fc | 20822 | _("can't use alignment with this instruction")); |
5287ad62 | 20823 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 20824 | _("bad list length")); |
5287ad62 | 20825 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 20826 | inst.instruction |= 1 << 5; |
5287ad62 JB |
20827 | inst.instruction |= neon_logbits (et.size) << 6; |
20828 | break; | |
20829 | ||
20830 | case 3: /* VLD4. */ | |
20831 | { | |
477330fc | 20832 | int align = inst.operands[1].imm >> 8; |
aa8a0863 | 20833 | align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32, |
477330fc RM |
20834 | 16, 64, 32, 64, 32, 128, -1); |
20835 | if (align_good == FAIL) | |
20836 | return; | |
20837 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
20838 | _("bad list length")); | |
20839 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
20840 | inst.instruction |= 1 << 5; | |
20841 | if (et.size == 32 && align == 128) | |
20842 | inst.instruction |= 0x3 << 6; | |
20843 | else | |
20844 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
20845 | } |
20846 | break; | |
20847 | ||
20848 | default: ; | |
20849 | } | |
20850 | ||
aa8a0863 | 20851 | inst.instruction |= do_alignment << 4; |
5287ad62 JB |
20852 | } |
20853 | ||
20854 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
20855 | apart from bits [11:4]. */ | |
20856 | ||
20857 | static void | |
20858 | do_neon_ldx_stx (void) | |
20859 | { | |
b1a769ed DG |
20860 | if (inst.operands[1].isreg) |
20861 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
20862 | ||
5287ad62 JB |
20863 | switch (NEON_LANE (inst.operands[0].imm)) |
20864 | { | |
20865 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 20866 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
20867 | do_neon_ld_st_interleave (); |
20868 | break; | |
5f4273c7 | 20869 | |
5287ad62 | 20870 | case NEON_ALL_LANES: |
88714cb8 | 20871 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
20872 | if (inst.instruction == N_INV) |
20873 | { | |
20874 | first_error ("only loads support such operands"); | |
20875 | break; | |
20876 | } | |
5287ad62 JB |
20877 | do_neon_ld_dup (); |
20878 | break; | |
5f4273c7 | 20879 | |
5287ad62 | 20880 | default: |
88714cb8 | 20881 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
20882 | do_neon_ld_st_lane (); |
20883 | } | |
20884 | ||
20885 | /* L bit comes from bit mask. */ | |
20886 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
20887 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
20888 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 20889 | |
5287ad62 JB |
20890 | if (inst.operands[1].postind) |
20891 | { | |
20892 | int postreg = inst.operands[1].imm & 0xf; | |
20893 | constraint (!inst.operands[1].immisreg, | |
477330fc | 20894 | _("post-index must be a register")); |
5287ad62 | 20895 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 20896 | _("bad register for post-index")); |
5287ad62 JB |
20897 | inst.instruction |= postreg; |
20898 | } | |
4f2374c7 | 20899 | else |
5287ad62 | 20900 | { |
4f2374c7 | 20901 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
e2b0ab59 AV |
20902 | constraint (inst.relocs[0].exp.X_op != O_constant |
20903 | || inst.relocs[0].exp.X_add_number != 0, | |
4f2374c7 WN |
20904 | BAD_ADDR_MODE); |
20905 | ||
20906 | if (inst.operands[1].writeback) | |
20907 | { | |
20908 | inst.instruction |= 0xd; | |
20909 | } | |
20910 | else | |
20911 | inst.instruction |= 0xf; | |
5287ad62 | 20912 | } |
5f4273c7 | 20913 | |
5287ad62 JB |
20914 | if (thumb_mode) |
20915 | inst.instruction |= 0xf9000000; | |
20916 | else | |
20917 | inst.instruction |= 0xf4000000; | |
20918 | } | |
33399f07 MGD |
20919 | |
20920 | /* FP v8. */ | |
20921 | static void | |
20922 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
20923 | { | |
a715796b TG |
20924 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
20925 | D register operands. */ | |
20926 | if (neon_shape_class[rs] == SC_DOUBLE) | |
20927 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
20928 | _(BAD_FPU)); | |
20929 | ||
33399f07 MGD |
20930 | NEON_ENCODE (FPV8, inst); |
20931 | ||
9db2f6b4 RL |
20932 | if (rs == NS_FFF || rs == NS_HHH) |
20933 | { | |
20934 | do_vfp_sp_dyadic (); | |
20935 | ||
20936 | /* ARMv8.2 fp16 instruction. */ | |
20937 | if (rs == NS_HHH) | |
20938 | do_scalar_fp16_v82_encode (); | |
20939 | } | |
33399f07 MGD |
20940 | else |
20941 | do_vfp_dp_rd_rn_rm (); | |
20942 | ||
20943 | if (rs == NS_DDD) | |
20944 | inst.instruction |= 0x100; | |
20945 | ||
20946 | inst.instruction |= 0xf0000000; | |
20947 | } | |
20948 | ||
20949 | static void | |
20950 | do_vsel (void) | |
20951 | { | |
5ee91343 | 20952 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
33399f07 MGD |
20953 | |
20954 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
20955 | first_error (_("invalid instruction shape")); | |
20956 | } | |
20957 | ||
73924fbc MGD |
20958 | static void |
20959 | do_vmaxnm (void) | |
20960 | { | |
935295b5 AV |
20961 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
20962 | set_pred_insn_type (OUTSIDE_PRED_INSN); | |
73924fbc MGD |
20963 | |
20964 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
20965 | return; | |
20966 | ||
64c350f2 | 20967 | if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8)) |
73924fbc MGD |
20968 | return; |
20969 | ||
cc933301 | 20970 | neon_dyadic_misc (NT_untyped, N_F_16_32, 0); |
73924fbc MGD |
20971 | } |
20972 | ||
30bdf752 MGD |
20973 | static void |
20974 | do_vrint_1 (enum neon_cvt_mode mode) | |
20975 | { | |
9db2f6b4 | 20976 | enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL); |
30bdf752 MGD |
20977 | struct neon_type_el et; |
20978 | ||
20979 | if (rs == NS_NULL) | |
20980 | return; | |
20981 | ||
a715796b TG |
20982 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
20983 | D register operands. */ | |
20984 | if (neon_shape_class[rs] == SC_DOUBLE) | |
20985 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
20986 | _(BAD_FPU)); | |
20987 | ||
9db2f6b4 RL |
20988 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY |
20989 | | N_VFP); | |
30bdf752 MGD |
20990 | if (et.type != NT_invtype) |
20991 | { | |
20992 | /* VFP encodings. */ | |
20993 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
20994 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
5ee91343 | 20995 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
30bdf752 MGD |
20996 | |
20997 | NEON_ENCODE (FPV8, inst); | |
9db2f6b4 | 20998 | if (rs == NS_FF || rs == NS_HH) |
30bdf752 MGD |
20999 | do_vfp_sp_monadic (); |
21000 | else | |
21001 | do_vfp_dp_rd_rm (); | |
21002 | ||
21003 | switch (mode) | |
21004 | { | |
21005 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
21006 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
21007 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
21008 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
21009 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
21010 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
21011 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
21012 | default: abort (); | |
21013 | } | |
21014 | ||
21015 | inst.instruction |= (rs == NS_DD) << 8; | |
21016 | do_vfp_cond_or_thumb (); | |
9db2f6b4 RL |
21017 | |
21018 | /* ARMv8.2 fp16 vrint instruction. */ | |
21019 | if (rs == NS_HH) | |
21020 | do_scalar_fp16_v82_encode (); | |
30bdf752 MGD |
21021 | } |
21022 | else | |
21023 | { | |
21024 | /* Neon encodings (or something broken...). */ | |
21025 | inst.error = NULL; | |
cc933301 | 21026 | et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY); |
30bdf752 MGD |
21027 | |
21028 | if (et.type == NT_invtype) | |
21029 | return; | |
21030 | ||
64c350f2 AV |
21031 | if (!check_simd_pred_availability (TRUE, |
21032 | NEON_CHECK_CC | NEON_CHECK_ARCH8)) | |
30bdf752 MGD |
21033 | return; |
21034 | ||
a710b305 AV |
21035 | NEON_ENCODE (FLOAT, inst); |
21036 | ||
30bdf752 MGD |
21037 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
21038 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
21039 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
21040 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
21041 | inst.instruction |= neon_quad (rs) << 6; | |
cc933301 JW |
21042 | /* Mask off the original size bits and reencode them. */ |
21043 | inst.instruction = ((inst.instruction & 0xfff3ffff) | |
21044 | | neon_logbits (et.size) << 18); | |
21045 | ||
30bdf752 MGD |
21046 | switch (mode) |
21047 | { | |
21048 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
21049 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
21050 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
21051 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
21052 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
21053 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
21054 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
21055 | default: abort (); | |
21056 | } | |
21057 | ||
21058 | if (thumb_mode) | |
21059 | inst.instruction |= 0xfc000000; | |
21060 | else | |
21061 | inst.instruction |= 0xf0000000; | |
21062 | } | |
21063 | } | |
21064 | ||
21065 | static void | |
21066 | do_vrintx (void) | |
21067 | { | |
21068 | do_vrint_1 (neon_cvt_mode_x); | |
21069 | } | |
21070 | ||
21071 | static void | |
21072 | do_vrintz (void) | |
21073 | { | |
21074 | do_vrint_1 (neon_cvt_mode_z); | |
21075 | } | |
21076 | ||
21077 | static void | |
21078 | do_vrintr (void) | |
21079 | { | |
21080 | do_vrint_1 (neon_cvt_mode_r); | |
21081 | } | |
21082 | ||
21083 | static void | |
21084 | do_vrinta (void) | |
21085 | { | |
21086 | do_vrint_1 (neon_cvt_mode_a); | |
21087 | } | |
21088 | ||
21089 | static void | |
21090 | do_vrintn (void) | |
21091 | { | |
21092 | do_vrint_1 (neon_cvt_mode_n); | |
21093 | } | |
21094 | ||
21095 | static void | |
21096 | do_vrintp (void) | |
21097 | { | |
21098 | do_vrint_1 (neon_cvt_mode_p); | |
21099 | } | |
21100 | ||
21101 | static void | |
21102 | do_vrintm (void) | |
21103 | { | |
21104 | do_vrint_1 (neon_cvt_mode_m); | |
21105 | } | |
21106 | ||
c28eeff2 SN |
21107 | static unsigned |
21108 | neon_scalar_for_vcmla (unsigned opnd, unsigned elsize) | |
21109 | { | |
21110 | unsigned regno = NEON_SCALAR_REG (opnd); | |
21111 | unsigned elno = NEON_SCALAR_INDEX (opnd); | |
21112 | ||
21113 | if (elsize == 16 && elno < 2 && regno < 16) | |
21114 | return regno | (elno << 4); | |
21115 | else if (elsize == 32 && elno == 0) | |
21116 | return regno; | |
21117 | ||
21118 | first_error (_("scalar out of range")); | |
21119 | return 0; | |
21120 | } | |
21121 | ||
21122 | static void | |
21123 | do_vcmla (void) | |
21124 | { | |
5d281bf0 AV |
21125 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) |
21126 | && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) | |
21127 | || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); | |
e2b0ab59 AV |
21128 | constraint (inst.relocs[0].exp.X_op != O_constant, |
21129 | _("expression too complex")); | |
21130 | unsigned rot = inst.relocs[0].exp.X_add_number; | |
c28eeff2 SN |
21131 | constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, |
21132 | _("immediate out of range")); | |
21133 | rot /= 90; | |
5d281bf0 | 21134 | |
64c350f2 AV |
21135 | if (!check_simd_pred_availability (TRUE, |
21136 | NEON_CHECK_ARCH8 | NEON_CHECK_CC)) | |
5d281bf0 AV |
21137 | return; |
21138 | ||
c28eeff2 SN |
21139 | if (inst.operands[2].isscalar) |
21140 | { | |
5d281bf0 AV |
21141 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) |
21142 | first_error (_("invalid instruction shape")); | |
c28eeff2 SN |
21143 | enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); |
21144 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, | |
21145 | N_KEY | N_F16 | N_F32).size; | |
21146 | unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size); | |
21147 | inst.is_neon = 1; | |
21148 | inst.instruction = 0xfe000800; | |
21149 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
21150 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
21151 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
21152 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
21153 | inst.instruction |= LOW4 (m); | |
21154 | inst.instruction |= HI1 (m) << 5; | |
21155 | inst.instruction |= neon_quad (rs) << 6; | |
21156 | inst.instruction |= rot << 20; | |
21157 | inst.instruction |= (size == 32) << 23; | |
21158 | } | |
21159 | else | |
21160 | { | |
5d281bf0 AV |
21161 | enum neon_shape rs; |
21162 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)) | |
21163 | rs = neon_select_shape (NS_QQQI, NS_NULL); | |
21164 | else | |
21165 | rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); | |
21166 | ||
c28eeff2 SN |
21167 | unsigned size = neon_check_type (3, rs, N_EQK, N_EQK, |
21168 | N_KEY | N_F16 | N_F32).size; | |
5d281bf0 AV |
21169 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32 |
21170 | && (inst.operands[0].reg == inst.operands[1].reg | |
21171 | || inst.operands[0].reg == inst.operands[2].reg)) | |
21172 | as_tsktsk (BAD_MVE_SRCDEST); | |
21173 | ||
c28eeff2 SN |
21174 | neon_three_same (neon_quad (rs), 0, -1); |
21175 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ | |
21176 | inst.instruction |= 0xfc200800; | |
21177 | inst.instruction |= rot << 23; | |
21178 | inst.instruction |= (size == 32) << 20; | |
21179 | } | |
21180 | } | |
21181 | ||
21182 | static void | |
21183 | do_vcadd (void) | |
21184 | { | |
5d281bf0 AV |
21185 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) |
21186 | && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8) | |
21187 | || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU)); | |
e2b0ab59 AV |
21188 | constraint (inst.relocs[0].exp.X_op != O_constant, |
21189 | _("expression too complex")); | |
5d281bf0 | 21190 | |
e2b0ab59 | 21191 | unsigned rot = inst.relocs[0].exp.X_add_number; |
c28eeff2 | 21192 | constraint (rot != 90 && rot != 270, _("immediate out of range")); |
5d281bf0 AV |
21193 | enum neon_shape rs; |
21194 | struct neon_type_el et; | |
21195 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) | |
21196 | { | |
21197 | rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); | |
21198 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32); | |
21199 | } | |
21200 | else | |
21201 | { | |
21202 | rs = neon_select_shape (NS_QQQI, NS_NULL); | |
21203 | et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8 | |
21204 | | N_I16 | N_I32); | |
21205 | if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg) | |
21206 | as_tsktsk (_("Warning: 32-bit element size and same first and third " | |
21207 | "operand makes instruction UNPREDICTABLE")); | |
21208 | } | |
21209 | ||
21210 | if (et.type == NT_invtype) | |
21211 | return; | |
21212 | ||
64c350f2 AV |
21213 | if (!check_simd_pred_availability (et.type == NT_float, |
21214 | NEON_CHECK_ARCH8 | NEON_CHECK_CC)) | |
5d281bf0 AV |
21215 | return; |
21216 | ||
21217 | if (et.type == NT_float) | |
21218 | { | |
21219 | neon_three_same (neon_quad (rs), 0, -1); | |
21220 | inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */ | |
21221 | inst.instruction |= 0xfc800800; | |
21222 | inst.instruction |= (rot == 270) << 24; | |
21223 | inst.instruction |= (et.size == 32) << 20; | |
21224 | } | |
21225 | else | |
21226 | { | |
21227 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); | |
21228 | inst.instruction = 0xfe000f00; | |
21229 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
21230 | inst.instruction |= neon_logbits (et.size) << 20; | |
21231 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
21232 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
21233 | inst.instruction |= (rot == 270) << 12; | |
21234 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
21235 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
21236 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
21237 | inst.is_neon = 1; | |
21238 | } | |
c28eeff2 SN |
21239 | } |
21240 | ||
c604a79a JW |
21241 | /* Dot Product instructions encoding support. */ |
21242 | ||
21243 | static void | |
21244 | do_neon_dotproduct (int unsigned_p) | |
21245 | { | |
21246 | enum neon_shape rs; | |
21247 | unsigned scalar_oprd2 = 0; | |
21248 | int high8; | |
21249 | ||
21250 | if (inst.cond != COND_ALWAYS) | |
21251 | as_warn (_("Dot Product instructions cannot be conditional, the behaviour " | |
21252 | "is UNPREDICTABLE")); | |
21253 | ||
21254 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), | |
21255 | _(BAD_FPU)); | |
21256 | ||
21257 | /* Dot Product instructions are in three-same D/Q register format or the third | |
21258 | operand can be a scalar index register. */ | |
21259 | if (inst.operands[2].isscalar) | |
21260 | { | |
21261 | scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32); | |
21262 | high8 = 0xfe000000; | |
21263 | rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); | |
21264 | } | |
21265 | else | |
21266 | { | |
21267 | high8 = 0xfc000000; | |
21268 | rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
21269 | } | |
21270 | ||
21271 | if (unsigned_p) | |
21272 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8); | |
21273 | else | |
21274 | neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8); | |
21275 | ||
21276 | /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot | |
21277 | Product instruction, so we pass 0 as the "ubit" parameter. And the | |
21278 | "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */ | |
21279 | neon_three_same (neon_quad (rs), 0, 32); | |
21280 | ||
21281 | /* Undo neon_dp_fixup. Dot Product instructions are using a slightly | |
21282 | different NEON three-same encoding. */ | |
21283 | inst.instruction &= 0x00ffffff; | |
21284 | inst.instruction |= high8; | |
21285 | /* Encode 'U' bit which indicates signedness. */ | |
21286 | inst.instruction |= (unsigned_p ? 1 : 0) << 4; | |
21287 | /* Re-encode operand2 if it's indexed scalar operand. What has been encoded | |
21288 | from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not | |
21289 | the instruction encoding. */ | |
21290 | if (inst.operands[2].isscalar) | |
21291 | { | |
21292 | inst.instruction &= 0xffffffd0; | |
21293 | inst.instruction |= LOW4 (scalar_oprd2); | |
21294 | inst.instruction |= HI1 (scalar_oprd2) << 5; | |
21295 | } | |
21296 | } | |
21297 | ||
21298 | /* Dot Product instructions for signed integer. */ | |
21299 | ||
21300 | static void | |
21301 | do_neon_dotproduct_s (void) | |
21302 | { | |
21303 | return do_neon_dotproduct (0); | |
21304 | } | |
21305 | ||
21306 | /* Dot Product instructions for unsigned integer. */ | |
21307 | ||
21308 | static void | |
21309 | do_neon_dotproduct_u (void) | |
21310 | { | |
21311 | return do_neon_dotproduct (1); | |
21312 | } | |
21313 | ||
91ff7894 MGD |
21314 | /* Crypto v1 instructions. */ |
21315 | static void | |
21316 | do_crypto_2op_1 (unsigned elttype, int op) | |
21317 | { | |
5ee91343 | 21318 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
91ff7894 MGD |
21319 | |
21320 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
21321 | == NT_invtype) | |
21322 | return; | |
21323 | ||
21324 | inst.error = NULL; | |
21325 | ||
21326 | NEON_ENCODE (INTEGER, inst); | |
21327 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
21328 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
21329 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
21330 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
21331 | if (op != -1) | |
21332 | inst.instruction |= op << 6; | |
21333 | ||
21334 | if (thumb_mode) | |
21335 | inst.instruction |= 0xfc000000; | |
21336 | else | |
21337 | inst.instruction |= 0xf0000000; | |
21338 | } | |
21339 | ||
48adcd8e MGD |
21340 | static void |
21341 | do_crypto_3op_1 (int u, int op) | |
21342 | { | |
5ee91343 | 21343 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
48adcd8e MGD |
21344 | |
21345 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
21346 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
21347 | return; | |
21348 | ||
21349 | inst.error = NULL; | |
21350 | ||
21351 | NEON_ENCODE (INTEGER, inst); | |
21352 | neon_three_same (1, u, 8 << op); | |
21353 | } | |
21354 | ||
91ff7894 MGD |
21355 | static void |
21356 | do_aese (void) | |
21357 | { | |
21358 | do_crypto_2op_1 (N_8, 0); | |
21359 | } | |
21360 | ||
21361 | static void | |
21362 | do_aesd (void) | |
21363 | { | |
21364 | do_crypto_2op_1 (N_8, 1); | |
21365 | } | |
21366 | ||
21367 | static void | |
21368 | do_aesmc (void) | |
21369 | { | |
21370 | do_crypto_2op_1 (N_8, 2); | |
21371 | } | |
21372 | ||
21373 | static void | |
21374 | do_aesimc (void) | |
21375 | { | |
21376 | do_crypto_2op_1 (N_8, 3); | |
21377 | } | |
21378 | ||
48adcd8e MGD |
21379 | static void |
21380 | do_sha1c (void) | |
21381 | { | |
21382 | do_crypto_3op_1 (0, 0); | |
21383 | } | |
21384 | ||
21385 | static void | |
21386 | do_sha1p (void) | |
21387 | { | |
21388 | do_crypto_3op_1 (0, 1); | |
21389 | } | |
21390 | ||
21391 | static void | |
21392 | do_sha1m (void) | |
21393 | { | |
21394 | do_crypto_3op_1 (0, 2); | |
21395 | } | |
21396 | ||
21397 | static void | |
21398 | do_sha1su0 (void) | |
21399 | { | |
21400 | do_crypto_3op_1 (0, 3); | |
21401 | } | |
91ff7894 | 21402 | |
48adcd8e MGD |
21403 | static void |
21404 | do_sha256h (void) | |
21405 | { | |
21406 | do_crypto_3op_1 (1, 0); | |
21407 | } | |
21408 | ||
21409 | static void | |
21410 | do_sha256h2 (void) | |
21411 | { | |
21412 | do_crypto_3op_1 (1, 1); | |
21413 | } | |
21414 | ||
21415 | static void | |
21416 | do_sha256su1 (void) | |
21417 | { | |
21418 | do_crypto_3op_1 (1, 2); | |
21419 | } | |
3c9017d2 MGD |
21420 | |
21421 | static void | |
21422 | do_sha1h (void) | |
21423 | { | |
21424 | do_crypto_2op_1 (N_32, -1); | |
21425 | } | |
21426 | ||
21427 | static void | |
21428 | do_sha1su1 (void) | |
21429 | { | |
21430 | do_crypto_2op_1 (N_32, 0); | |
21431 | } | |
21432 | ||
21433 | static void | |
21434 | do_sha256su0 (void) | |
21435 | { | |
21436 | do_crypto_2op_1 (N_32, 1); | |
21437 | } | |
dd5181d5 KT |
21438 | |
21439 | static void | |
21440 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
21441 | { | |
21442 | unsigned int Rd = inst.operands[0].reg; | |
21443 | unsigned int Rn = inst.operands[1].reg; | |
21444 | unsigned int Rm = inst.operands[2].reg; | |
21445 | ||
5ee91343 | 21446 | set_pred_insn_type (OUTSIDE_PRED_INSN); |
dd5181d5 KT |
21447 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); |
21448 | inst.instruction |= LOW4 (Rn) << 16; | |
21449 | inst.instruction |= LOW4 (Rm); | |
21450 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
21451 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
21452 | ||
21453 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
21454 | as_warn (UNPRED_REG ("r15")); | |
dd5181d5 KT |
21455 | } |
21456 | ||
21457 | static void | |
21458 | do_crc32b (void) | |
21459 | { | |
21460 | do_crc32_1 (0, 0); | |
21461 | } | |
21462 | ||
21463 | static void | |
21464 | do_crc32h (void) | |
21465 | { | |
21466 | do_crc32_1 (0, 1); | |
21467 | } | |
21468 | ||
21469 | static void | |
21470 | do_crc32w (void) | |
21471 | { | |
21472 | do_crc32_1 (0, 2); | |
21473 | } | |
21474 | ||
21475 | static void | |
21476 | do_crc32cb (void) | |
21477 | { | |
21478 | do_crc32_1 (1, 0); | |
21479 | } | |
21480 | ||
21481 | static void | |
21482 | do_crc32ch (void) | |
21483 | { | |
21484 | do_crc32_1 (1, 1); | |
21485 | } | |
21486 | ||
21487 | static void | |
21488 | do_crc32cw (void) | |
21489 | { | |
21490 | do_crc32_1 (1, 2); | |
21491 | } | |
21492 | ||
49e8a725 SN |
21493 | static void |
21494 | do_vjcvt (void) | |
21495 | { | |
21496 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
21497 | _(BAD_FPU)); | |
21498 | neon_check_type (2, NS_FD, N_S32, N_F64); | |
21499 | do_vfp_sp_dp_cvt (); | |
21500 | do_vfp_cond_or_thumb (); | |
21501 | } | |
21502 | ||
5287ad62 JB |
21503 | \f |
21504 | /* Overall per-instruction processing. */ | |
21505 | ||
21506 | /* We need to be able to fix up arbitrary expressions in some statements. | |
21507 | This is so that we can handle symbols that are an arbitrary distance from | |
21508 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
21509 | which returns part of an address in a form which will be valid for | |
21510 | a data instruction. We do this by pushing the expression into a symbol | |
21511 | in the expr_section, and creating a fix for that. */ | |
21512 | ||
21513 | static void | |
21514 | fix_new_arm (fragS * frag, | |
21515 | int where, | |
21516 | short int size, | |
21517 | expressionS * exp, | |
21518 | int pc_rel, | |
21519 | int reloc) | |
21520 | { | |
21521 | fixS * new_fix; | |
21522 | ||
21523 | switch (exp->X_op) | |
21524 | { | |
21525 | case O_constant: | |
6e7ce2cd PB |
21526 | if (pc_rel) |
21527 | { | |
21528 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
21529 | refer to in the object file. Unfortunately for us, gas's |
21530 | generic expression parsing will already have folded out | |
21531 | any use of .set foo/.type foo %function that may have | |
21532 | been used to set type information of the target location, | |
21533 | that's being specified symbolically. We have to presume | |
21534 | the user knows what they are doing. */ | |
6e7ce2cd PB |
21535 | char name[16 + 8]; |
21536 | symbolS *symbol; | |
21537 | ||
21538 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
21539 | ||
21540 | symbol = symbol_find_or_make (name); | |
21541 | S_SET_SEGMENT (symbol, absolute_section); | |
21542 | symbol_set_frag (symbol, &zero_address_frag); | |
21543 | S_SET_VALUE (symbol, exp->X_add_number); | |
21544 | exp->X_op = O_symbol; | |
21545 | exp->X_add_symbol = symbol; | |
21546 | exp->X_add_number = 0; | |
21547 | } | |
21548 | /* FALLTHROUGH */ | |
5287ad62 JB |
21549 | case O_symbol: |
21550 | case O_add: | |
21551 | case O_subtract: | |
21d799b5 | 21552 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 21553 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
21554 | break; |
21555 | ||
21556 | default: | |
21d799b5 | 21557 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 21558 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
21559 | break; |
21560 | } | |
21561 | ||
21562 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
21563 | instruction. */ | |
21564 | new_fix->tc_fix_data = thumb_mode; | |
21565 | } | |
21566 | ||
21567 | /* Create a frg for an instruction requiring relaxation. */ | |
21568 | static void | |
21569 | output_relax_insn (void) | |
21570 | { | |
21571 | char * to; | |
21572 | symbolS *sym; | |
0110f2b8 PB |
21573 | int offset; |
21574 | ||
6e1cb1a6 PB |
21575 | /* The size of the instruction is unknown, so tie the debug info to the |
21576 | start of the instruction. */ | |
21577 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 21578 | |
e2b0ab59 | 21579 | switch (inst.relocs[0].exp.X_op) |
0110f2b8 PB |
21580 | { |
21581 | case O_symbol: | |
e2b0ab59 AV |
21582 | sym = inst.relocs[0].exp.X_add_symbol; |
21583 | offset = inst.relocs[0].exp.X_add_number; | |
0110f2b8 PB |
21584 | break; |
21585 | case O_constant: | |
21586 | sym = NULL; | |
e2b0ab59 | 21587 | offset = inst.relocs[0].exp.X_add_number; |
0110f2b8 PB |
21588 | break; |
21589 | default: | |
e2b0ab59 | 21590 | sym = make_expr_symbol (&inst.relocs[0].exp); |
0110f2b8 PB |
21591 | offset = 0; |
21592 | break; | |
21593 | } | |
21594 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
21595 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
21596 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
21597 | } |
21598 | ||
21599 | /* Write a 32-bit thumb instruction to buf. */ | |
21600 | static void | |
21601 | put_thumb32_insn (char * buf, unsigned long insn) | |
21602 | { | |
21603 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
21604 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
21605 | } | |
21606 | ||
b99bd4ef | 21607 | static void |
c19d1205 | 21608 | output_inst (const char * str) |
b99bd4ef | 21609 | { |
c19d1205 | 21610 | char * to = NULL; |
b99bd4ef | 21611 | |
c19d1205 | 21612 | if (inst.error) |
b99bd4ef | 21613 | { |
c19d1205 | 21614 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
21615 | return; |
21616 | } | |
5f4273c7 NC |
21617 | if (inst.relax) |
21618 | { | |
21619 | output_relax_insn (); | |
0110f2b8 | 21620 | return; |
5f4273c7 | 21621 | } |
c19d1205 ZW |
21622 | if (inst.size == 0) |
21623 | return; | |
b99bd4ef | 21624 | |
c19d1205 | 21625 | to = frag_more (inst.size); |
8dc2430f NC |
21626 | /* PR 9814: Record the thumb mode into the current frag so that we know |
21627 | what type of NOP padding to use, if necessary. We override any previous | |
21628 | setting so that if the mode has changed then the NOPS that we use will | |
21629 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 21630 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
21631 | |
21632 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 21633 | { |
9c2799c2 | 21634 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 21635 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 21636 | } |
c19d1205 | 21637 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 21638 | { |
9c2799c2 | 21639 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
21640 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
21641 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 21642 | } |
c19d1205 ZW |
21643 | else |
21644 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 21645 | |
e2b0ab59 AV |
21646 | int r; |
21647 | for (r = 0; r < ARM_IT_MAX_RELOCS; r++) | |
21648 | { | |
21649 | if (inst.relocs[r].type != BFD_RELOC_UNUSED) | |
21650 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
21651 | inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel, | |
21652 | inst.relocs[r].type); | |
21653 | } | |
b99bd4ef | 21654 | |
c19d1205 | 21655 | dwarf2_emit_insn (inst.size); |
c19d1205 | 21656 | } |
b99bd4ef | 21657 | |
e07e6e58 NC |
21658 | static char * |
21659 | output_it_inst (int cond, int mask, char * to) | |
21660 | { | |
21661 | unsigned long instruction = 0xbf00; | |
21662 | ||
21663 | mask &= 0xf; | |
21664 | instruction |= mask; | |
21665 | instruction |= cond << 4; | |
21666 | ||
21667 | if (to == NULL) | |
21668 | { | |
21669 | to = frag_more (2); | |
21670 | #ifdef OBJ_ELF | |
21671 | dwarf2_emit_insn (2); | |
21672 | #endif | |
21673 | } | |
21674 | ||
21675 | md_number_to_chars (to, instruction, 2); | |
21676 | ||
21677 | return to; | |
21678 | } | |
21679 | ||
c19d1205 ZW |
21680 | /* Tag values used in struct asm_opcode's tag field. */ |
21681 | enum opcode_tag | |
21682 | { | |
21683 | OT_unconditional, /* Instruction cannot be conditionalized. | |
21684 | The ARM condition field is still 0xE. */ | |
21685 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
21686 | and carries 0xF in its ARM condition field. */ | |
21687 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
5ee91343 AV |
21688 | OT_csuffixF, /* Some forms of the instruction take a scalar |
21689 | conditional suffix, others place 0xF where the | |
21690 | condition field would be, others take a vector | |
21691 | conditional suffix. */ | |
c19d1205 ZW |
21692 | OT_cinfix3, /* Instruction takes a conditional infix, |
21693 | beginning at character index 3. (In | |
21694 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
21695 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
21696 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
21697 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
21698 | character index 3, even in unified mode. Used for | |
21699 | legacy instructions where suffix and infix forms | |
21700 | may be ambiguous. */ | |
c19d1205 | 21701 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 21702 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
21703 | OT_odd_infix_unc, /* This is the unconditional variant of an |
21704 | instruction that takes a conditional infix | |
21705 | at an unusual position. In unified mode, | |
21706 | this variant will accept a suffix. */ | |
21707 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
21708 | are the conditional variants of instructions that | |
21709 | take conditional infixes in unusual positions. | |
21710 | The infix appears at character index | |
21711 | (tag - OT_odd_infix_0). These are not accepted | |
21712 | in unified mode. */ | |
21713 | }; | |
b99bd4ef | 21714 | |
c19d1205 ZW |
21715 | /* Subroutine of md_assemble, responsible for looking up the primary |
21716 | opcode from the mnemonic the user wrote. STR points to the | |
21717 | beginning of the mnemonic. | |
21718 | ||
21719 | This is not simply a hash table lookup, because of conditional | |
21720 | variants. Most instructions have conditional variants, which are | |
21721 | expressed with a _conditional affix_ to the mnemonic. If we were | |
21722 | to encode each conditional variant as a literal string in the opcode | |
21723 | table, it would have approximately 20,000 entries. | |
21724 | ||
21725 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
21726 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
21727 | instructions take the affix as an infix, notably the s-variants of | |
21728 | the arithmetic instructions. Of those instructions, all but six | |
21729 | have the infix appear after the third character of the mnemonic. | |
21730 | ||
21731 | Accordingly, the algorithm for looking up primary opcodes given | |
21732 | an identifier is: | |
21733 | ||
21734 | 1. Look up the identifier in the opcode table. | |
21735 | If we find a match, go to step U. | |
21736 | ||
21737 | 2. Look up the last two characters of the identifier in the | |
21738 | conditions table. If we find a match, look up the first N-2 | |
21739 | characters of the identifier in the opcode table. If we | |
21740 | find a match, go to step CE. | |
21741 | ||
21742 | 3. Look up the fourth and fifth characters of the identifier in | |
21743 | the conditions table. If we find a match, extract those | |
21744 | characters from the identifier, and look up the remaining | |
21745 | characters in the opcode table. If we find a match, go | |
21746 | to step CM. | |
21747 | ||
21748 | 4. Fail. | |
21749 | ||
21750 | U. Examine the tag field of the opcode structure, in case this is | |
21751 | one of the six instructions with its conditional infix in an | |
21752 | unusual place. If it is, the tag tells us where to find the | |
21753 | infix; look it up in the conditions table and set inst.cond | |
21754 | accordingly. Otherwise, this is an unconditional instruction. | |
21755 | Again set inst.cond accordingly. Return the opcode structure. | |
21756 | ||
21757 | CE. Examine the tag field to make sure this is an instruction that | |
21758 | should receive a conditional suffix. If it is not, fail. | |
21759 | Otherwise, set inst.cond from the suffix we already looked up, | |
21760 | and return the opcode structure. | |
21761 | ||
21762 | CM. Examine the tag field to make sure this is an instruction that | |
21763 | should receive a conditional infix after the third character. | |
21764 | If it is not, fail. Otherwise, undo the edits to the current | |
21765 | line of input and proceed as for case CE. */ | |
21766 | ||
21767 | static const struct asm_opcode * | |
21768 | opcode_lookup (char **str) | |
21769 | { | |
21770 | char *end, *base; | |
21771 | char *affix; | |
21772 | const struct asm_opcode *opcode; | |
21773 | const struct asm_cond *cond; | |
e3cb604e | 21774 | char save[2]; |
c19d1205 ZW |
21775 | |
21776 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 21777 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 21778 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 21779 | if (*end == ' ' || *end == '.') |
c19d1205 | 21780 | break; |
b99bd4ef | 21781 | |
c19d1205 | 21782 | if (end == base) |
c921be7d | 21783 | return NULL; |
b99bd4ef | 21784 | |
5287ad62 | 21785 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 21786 | if (end[0] == '.') |
b99bd4ef | 21787 | { |
5287ad62 | 21788 | int offset = 2; |
5f4273c7 | 21789 | |
267d2029 | 21790 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 21791 | use. */ |
267d2029 | 21792 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 21793 | inst.size_req = 4; |
267d2029 | 21794 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
21795 | inst.size_req = 2; |
21796 | else | |
477330fc | 21797 | offset = 0; |
5287ad62 JB |
21798 | |
21799 | inst.vectype.elems = 0; | |
21800 | ||
21801 | *str = end + offset; | |
b99bd4ef | 21802 | |
5f4273c7 | 21803 | if (end[offset] == '.') |
5287ad62 | 21804 | { |
267d2029 | 21805 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
21806 | non-unified ARM syntax mode). */ |
21807 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 21808 | return NULL; |
477330fc | 21809 | } |
5287ad62 | 21810 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 21811 | return NULL; |
b99bd4ef | 21812 | } |
c19d1205 ZW |
21813 | else |
21814 | *str = end; | |
b99bd4ef | 21815 | |
c19d1205 | 21816 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 21817 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 21818 | end - base); |
c19d1205 | 21819 | if (opcode) |
b99bd4ef | 21820 | { |
c19d1205 ZW |
21821 | /* step U */ |
21822 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 21823 | { |
c19d1205 ZW |
21824 | inst.cond = COND_ALWAYS; |
21825 | return opcode; | |
b99bd4ef | 21826 | } |
b99bd4ef | 21827 | |
278df34e | 21828 | if (warn_on_deprecated && unified_syntax) |
5c3696f8 | 21829 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 | 21830 | affix = base + (opcode->tag - OT_odd_infix_0); |
21d799b5 | 21831 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 21832 | gas_assert (cond); |
b99bd4ef | 21833 | |
c19d1205 ZW |
21834 | inst.cond = cond->value; |
21835 | return opcode; | |
21836 | } | |
5ee91343 AV |
21837 | if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) |
21838 | { | |
21839 | /* Cannot have a conditional suffix on a mnemonic of less than a character. | |
21840 | */ | |
21841 | if (end - base < 2) | |
21842 | return NULL; | |
21843 | affix = end - 1; | |
21844 | cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1); | |
21845 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
21846 | affix - base); | |
21847 | /* If this opcode can not be vector predicated then don't accept it with a | |
21848 | vector predication code. */ | |
21849 | if (opcode && !opcode->mayBeVecPred) | |
21850 | opcode = NULL; | |
21851 | } | |
21852 | if (!opcode || !cond) | |
21853 | { | |
21854 | /* Cannot have a conditional suffix on a mnemonic of less than two | |
21855 | characters. */ | |
21856 | if (end - base < 3) | |
21857 | return NULL; | |
b99bd4ef | 21858 | |
5ee91343 AV |
21859 | /* Look for suffixed mnemonic. */ |
21860 | affix = end - 2; | |
21861 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); | |
21862 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
21863 | affix - base); | |
21864 | } | |
b99bd4ef | 21865 | |
c19d1205 ZW |
21866 | if (opcode && cond) |
21867 | { | |
21868 | /* step CE */ | |
21869 | switch (opcode->tag) | |
21870 | { | |
e3cb604e PB |
21871 | case OT_cinfix3_legacy: |
21872 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
21873 | break; | |
21874 | ||
c19d1205 | 21875 | case OT_cinfix3: |
088fa78e | 21876 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
21877 | case OT_odd_infix_unc: |
21878 | if (!unified_syntax) | |
0198d5e6 | 21879 | return NULL; |
1a0670f3 | 21880 | /* Fall through. */ |
c19d1205 ZW |
21881 | |
21882 | case OT_csuffix: | |
477330fc | 21883 | case OT_csuffixF: |
c19d1205 ZW |
21884 | case OT_csuf_or_in3: |
21885 | inst.cond = cond->value; | |
21886 | return opcode; | |
21887 | ||
21888 | case OT_unconditional: | |
21889 | case OT_unconditionalF: | |
dfa9f0d5 | 21890 | if (thumb_mode) |
c921be7d | 21891 | inst.cond = cond->value; |
dfa9f0d5 PB |
21892 | else |
21893 | { | |
c921be7d | 21894 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
21895 | inst.error = BAD_COND; |
21896 | inst.cond = COND_ALWAYS; | |
21897 | } | |
c19d1205 | 21898 | return opcode; |
b99bd4ef | 21899 | |
c19d1205 | 21900 | default: |
c921be7d | 21901 | return NULL; |
c19d1205 ZW |
21902 | } |
21903 | } | |
b99bd4ef | 21904 | |
c19d1205 ZW |
21905 | /* Cannot have a usual-position infix on a mnemonic of less than |
21906 | six characters (five would be a suffix). */ | |
21907 | if (end - base < 6) | |
c921be7d | 21908 | return NULL; |
b99bd4ef | 21909 | |
c19d1205 ZW |
21910 | /* Look for infixed mnemonic in the usual position. */ |
21911 | affix = base + 3; | |
21d799b5 | 21912 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 21913 | if (!cond) |
c921be7d | 21914 | return NULL; |
e3cb604e PB |
21915 | |
21916 | memcpy (save, affix, 2); | |
21917 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 21918 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 21919 | (end - base) - 2); |
e3cb604e PB |
21920 | memmove (affix + 2, affix, (end - affix) - 2); |
21921 | memcpy (affix, save, 2); | |
21922 | ||
088fa78e KH |
21923 | if (opcode |
21924 | && (opcode->tag == OT_cinfix3 | |
21925 | || opcode->tag == OT_cinfix3_deprecated | |
21926 | || opcode->tag == OT_csuf_or_in3 | |
21927 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 21928 | { |
c921be7d | 21929 | /* Step CM. */ |
278df34e | 21930 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
21931 | && (opcode->tag == OT_cinfix3 |
21932 | || opcode->tag == OT_cinfix3_deprecated)) | |
5c3696f8 | 21933 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 ZW |
21934 | |
21935 | inst.cond = cond->value; | |
21936 | return opcode; | |
b99bd4ef NC |
21937 | } |
21938 | ||
c921be7d | 21939 | return NULL; |
b99bd4ef NC |
21940 | } |
21941 | ||
e07e6e58 NC |
21942 | /* This function generates an initial IT instruction, leaving its block |
21943 | virtually open for the new instructions. Eventually, | |
5ee91343 | 21944 | the mask will be updated by now_pred_add_mask () each time |
e07e6e58 NC |
21945 | a new instruction needs to be included in the IT block. |
21946 | Finally, the block is closed with close_automatic_it_block (). | |
21947 | The block closure can be requested either from md_assemble (), | |
21948 | a tencode (), or due to a label hook. */ | |
21949 | ||
21950 | static void | |
21951 | new_automatic_it_block (int cond) | |
21952 | { | |
5ee91343 AV |
21953 | now_pred.state = AUTOMATIC_PRED_BLOCK; |
21954 | now_pred.mask = 0x18; | |
21955 | now_pred.cc = cond; | |
21956 | now_pred.block_length = 1; | |
cd000bff | 21957 | mapping_state (MAP_THUMB); |
5ee91343 AV |
21958 | now_pred.insn = output_it_inst (cond, now_pred.mask, NULL); |
21959 | now_pred.warn_deprecated = FALSE; | |
21960 | now_pred.insn_cond = TRUE; | |
e07e6e58 NC |
21961 | } |
21962 | ||
21963 | /* Close an automatic IT block. | |
21964 | See comments in new_automatic_it_block (). */ | |
21965 | ||
21966 | static void | |
21967 | close_automatic_it_block (void) | |
21968 | { | |
5ee91343 AV |
21969 | now_pred.mask = 0x10; |
21970 | now_pred.block_length = 0; | |
e07e6e58 NC |
21971 | } |
21972 | ||
21973 | /* Update the mask of the current automatically-generated IT | |
21974 | instruction. See comments in new_automatic_it_block (). */ | |
21975 | ||
21976 | static void | |
5ee91343 | 21977 | now_pred_add_mask (int cond) |
e07e6e58 NC |
21978 | { |
21979 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
21980 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 21981 | | ((bitvalue) << (nbit))) |
e07e6e58 | 21982 | const int resulting_bit = (cond & 1); |
c921be7d | 21983 | |
5ee91343 AV |
21984 | now_pred.mask &= 0xf; |
21985 | now_pred.mask = SET_BIT_VALUE (now_pred.mask, | |
477330fc | 21986 | resulting_bit, |
5ee91343 AV |
21987 | (5 - now_pred.block_length)); |
21988 | now_pred.mask = SET_BIT_VALUE (now_pred.mask, | |
477330fc | 21989 | 1, |
5ee91343 AV |
21990 | ((5 - now_pred.block_length) - 1)); |
21991 | output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn); | |
e07e6e58 NC |
21992 | |
21993 | #undef CLEAR_BIT | |
21994 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
21995 | } |
21996 | ||
21997 | /* The IT blocks handling machinery is accessed through the these functions: | |
21998 | it_fsm_pre_encode () from md_assemble () | |
5ee91343 AV |
21999 | set_pred_insn_type () optional, from the tencode functions |
22000 | set_pred_insn_type_last () ditto | |
22001 | in_pred_block () ditto | |
e07e6e58 | 22002 | it_fsm_post_encode () from md_assemble () |
33eaf5de | 22003 | force_automatic_it_block_close () from label handling functions |
e07e6e58 NC |
22004 | |
22005 | Rationale: | |
22006 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
22007 | initializing the IT insn type with a generic initial value depending |
22008 | on the inst.condition. | |
e07e6e58 | 22009 | 2) During the tencode function, two things may happen: |
477330fc | 22010 | a) The tencode function overrides the IT insn type by |
5ee91343 AV |
22011 | calling either set_pred_insn_type (type) or |
22012 | set_pred_insn_type_last (). | |
477330fc | 22013 | b) The tencode function queries the IT block state by |
5ee91343 | 22014 | calling in_pred_block () (i.e. to determine narrow/not narrow mode). |
477330fc | 22015 | |
5ee91343 AV |
22016 | Both set_pred_insn_type and in_pred_block run the internal FSM state |
22017 | handling function (handle_pred_state), because: a) setting the IT insn | |
477330fc RM |
22018 | type may incur in an invalid state (exiting the function), |
22019 | and b) querying the state requires the FSM to be updated. | |
22020 | Specifically we want to avoid creating an IT block for conditional | |
22021 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
22022 | determine whether an IT block is required until the tencode () routine | |
22023 | has decided what type of instruction this actually it. | |
5ee91343 AV |
22024 | Because of this, if set_pred_insn_type and in_pred_block have to be |
22025 | used, set_pred_insn_type has to be called first. | |
477330fc | 22026 | |
5ee91343 AV |
22027 | set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type), |
22028 | that determines the insn IT type depending on the inst.cond code. | |
477330fc RM |
22029 | When a tencode () routine encodes an instruction that can be |
22030 | either outside an IT block, or, in the case of being inside, has to be | |
5ee91343 | 22031 | the last one, set_pred_insn_type_last () will determine the proper |
477330fc | 22032 | IT instruction type based on the inst.cond code. Otherwise, |
5ee91343 | 22033 | set_pred_insn_type can be called for overriding that logic or |
477330fc RM |
22034 | for covering other cases. |
22035 | ||
5ee91343 AV |
22036 | Calling handle_pred_state () may not transition the IT block state to |
22037 | OUTSIDE_PRED_BLOCK immediately, since the (current) state could be | |
477330fc | 22038 | still queried. Instead, if the FSM determines that the state should |
5ee91343 | 22039 | be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed |
477330fc RM |
22040 | after the tencode () function: that's what it_fsm_post_encode () does. |
22041 | ||
5ee91343 | 22042 | Since in_pred_block () calls the state handling function to get an |
477330fc RM |
22043 | updated state, an error may occur (due to invalid insns combination). |
22044 | In that case, inst.error is set. | |
22045 | Therefore, inst.error has to be checked after the execution of | |
22046 | the tencode () routine. | |
e07e6e58 NC |
22047 | |
22048 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc | 22049 | any pending state change (if any) that didn't take place in |
5ee91343 | 22050 | handle_pred_state () as explained above. */ |
e07e6e58 NC |
22051 | |
22052 | static void | |
22053 | it_fsm_pre_encode (void) | |
22054 | { | |
22055 | if (inst.cond != COND_ALWAYS) | |
5ee91343 | 22056 | inst.pred_insn_type = INSIDE_IT_INSN; |
e07e6e58 | 22057 | else |
5ee91343 | 22058 | inst.pred_insn_type = OUTSIDE_PRED_INSN; |
e07e6e58 | 22059 | |
5ee91343 | 22060 | now_pred.state_handled = 0; |
e07e6e58 NC |
22061 | } |
22062 | ||
22063 | /* IT state FSM handling function. */ | |
5ee91343 AV |
22064 | /* MVE instructions and non-MVE instructions are handled differently because of |
22065 | the introduction of VPT blocks. | |
22066 | Specifications say that any non-MVE instruction inside a VPT block is | |
22067 | UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE | |
22068 | instructions are deemed to be UNPREDICTABLE if inside an IT block. For the | |
35c228db | 22069 | few exceptions we have MVE_UNPREDICABLE_INSN. |
5ee91343 AV |
22070 | The error messages provided depending on the different combinations possible |
22071 | are described in the cases below: | |
22072 | For 'most' MVE instructions: | |
22073 | 1) In an IT block, with an IT code: syntax error | |
22074 | 2) In an IT block, with a VPT code: error: must be in a VPT block | |
22075 | 3) In an IT block, with no code: warning: UNPREDICTABLE | |
22076 | 4) In a VPT block, with an IT code: syntax error | |
22077 | 5) In a VPT block, with a VPT code: OK! | |
22078 | 6) In a VPT block, with no code: error: missing code | |
22079 | 7) Outside a pred block, with an IT code: error: syntax error | |
22080 | 8) Outside a pred block, with a VPT code: error: should be in a VPT block | |
22081 | 9) Outside a pred block, with no code: OK! | |
22082 | For non-MVE instructions: | |
22083 | 10) In an IT block, with an IT code: OK! | |
22084 | 11) In an IT block, with a VPT code: syntax error | |
22085 | 12) In an IT block, with no code: error: missing code | |
22086 | 13) In a VPT block, with an IT code: error: should be in an IT block | |
22087 | 14) In a VPT block, with a VPT code: syntax error | |
22088 | 15) In a VPT block, with no code: UNPREDICTABLE | |
22089 | 16) Outside a pred block, with an IT code: error: should be in an IT block | |
22090 | 17) Outside a pred block, with a VPT code: syntax error | |
22091 | 18) Outside a pred block, with no code: OK! | |
22092 | */ | |
22093 | ||
e07e6e58 NC |
22094 | |
22095 | static int | |
5ee91343 | 22096 | handle_pred_state (void) |
e07e6e58 | 22097 | { |
5ee91343 AV |
22098 | now_pred.state_handled = 1; |
22099 | now_pred.insn_cond = FALSE; | |
e07e6e58 | 22100 | |
5ee91343 | 22101 | switch (now_pred.state) |
e07e6e58 | 22102 | { |
5ee91343 AV |
22103 | case OUTSIDE_PRED_BLOCK: |
22104 | switch (inst.pred_insn_type) | |
e07e6e58 | 22105 | { |
35c228db | 22106 | case MVE_UNPREDICABLE_INSN: |
5ee91343 AV |
22107 | case MVE_OUTSIDE_PRED_INSN: |
22108 | if (inst.cond < COND_ALWAYS) | |
22109 | { | |
22110 | /* Case 7: Outside a pred block, with an IT code: error: syntax | |
22111 | error. */ | |
22112 | inst.error = BAD_SYNTAX; | |
22113 | return FAIL; | |
22114 | } | |
22115 | /* Case 9: Outside a pred block, with no code: OK! */ | |
22116 | break; | |
22117 | case OUTSIDE_PRED_INSN: | |
22118 | if (inst.cond > COND_ALWAYS) | |
22119 | { | |
22120 | /* Case 17: Outside a pred block, with a VPT code: syntax error. | |
22121 | */ | |
22122 | inst.error = BAD_SYNTAX; | |
22123 | return FAIL; | |
22124 | } | |
22125 | /* Case 18: Outside a pred block, with no code: OK! */ | |
e07e6e58 NC |
22126 | break; |
22127 | ||
5ee91343 AV |
22128 | case INSIDE_VPT_INSN: |
22129 | /* Case 8: Outside a pred block, with a VPT code: error: should be in | |
22130 | a VPT block. */ | |
22131 | inst.error = BAD_OUT_VPT; | |
22132 | return FAIL; | |
22133 | ||
e07e6e58 NC |
22134 | case INSIDE_IT_INSN: |
22135 | case INSIDE_IT_LAST_INSN: | |
5ee91343 | 22136 | if (inst.cond < COND_ALWAYS) |
e07e6e58 | 22137 | { |
5ee91343 AV |
22138 | /* Case 16: Outside a pred block, with an IT code: error: should |
22139 | be in an IT block. */ | |
22140 | if (thumb_mode == 0) | |
e07e6e58 | 22141 | { |
5ee91343 AV |
22142 | if (unified_syntax |
22143 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) | |
22144 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
22145 | " for Thumb.")); | |
e07e6e58 NC |
22146 | } |
22147 | else | |
22148 | { | |
5ee91343 AV |
22149 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) |
22150 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
22151 | { | |
22152 | /* Automatically generate the IT instruction. */ | |
22153 | new_automatic_it_block (inst.cond); | |
22154 | if (inst.pred_insn_type == INSIDE_IT_LAST_INSN) | |
22155 | close_automatic_it_block (); | |
22156 | } | |
22157 | else | |
22158 | { | |
22159 | inst.error = BAD_OUT_IT; | |
22160 | return FAIL; | |
22161 | } | |
e07e6e58 | 22162 | } |
5ee91343 | 22163 | break; |
e07e6e58 | 22164 | } |
5ee91343 AV |
22165 | else if (inst.cond > COND_ALWAYS) |
22166 | { | |
22167 | /* Case 17: Outside a pred block, with a VPT code: syntax error. | |
22168 | */ | |
22169 | inst.error = BAD_SYNTAX; | |
22170 | return FAIL; | |
22171 | } | |
22172 | else | |
22173 | gas_assert (0); | |
e07e6e58 NC |
22174 | case IF_INSIDE_IT_LAST_INSN: |
22175 | case NEUTRAL_IT_INSN: | |
22176 | break; | |
22177 | ||
5ee91343 AV |
22178 | case VPT_INSN: |
22179 | if (inst.cond != COND_ALWAYS) | |
22180 | first_error (BAD_SYNTAX); | |
22181 | now_pred.state = MANUAL_PRED_BLOCK; | |
22182 | now_pred.block_length = 0; | |
22183 | now_pred.type = VECTOR_PRED; | |
22184 | now_pred.cc = 0; | |
22185 | break; | |
e07e6e58 | 22186 | case IT_INSN: |
5ee91343 AV |
22187 | now_pred.state = MANUAL_PRED_BLOCK; |
22188 | now_pred.block_length = 0; | |
22189 | now_pred.type = SCALAR_PRED; | |
e07e6e58 NC |
22190 | break; |
22191 | } | |
22192 | break; | |
22193 | ||
5ee91343 | 22194 | case AUTOMATIC_PRED_BLOCK: |
e07e6e58 NC |
22195 | /* Three things may happen now: |
22196 | a) We should increment current it block size; | |
22197 | b) We should close current it block (closing insn or 4 insns); | |
22198 | c) We should close current it block and start a new one (due | |
22199 | to incompatible conditions or | |
22200 | 4 insns-length block reached). */ | |
22201 | ||
5ee91343 | 22202 | switch (inst.pred_insn_type) |
e07e6e58 | 22203 | { |
5ee91343 AV |
22204 | case INSIDE_VPT_INSN: |
22205 | case VPT_INSN: | |
35c228db | 22206 | case MVE_UNPREDICABLE_INSN: |
5ee91343 AV |
22207 | case MVE_OUTSIDE_PRED_INSN: |
22208 | gas_assert (0); | |
22209 | case OUTSIDE_PRED_INSN: | |
2b0f3761 | 22210 | /* The closure of the block shall happen immediately, |
5ee91343 | 22211 | so any in_pred_block () call reports the block as closed. */ |
e07e6e58 NC |
22212 | force_automatic_it_block_close (); |
22213 | break; | |
22214 | ||
22215 | case INSIDE_IT_INSN: | |
22216 | case INSIDE_IT_LAST_INSN: | |
22217 | case IF_INSIDE_IT_LAST_INSN: | |
5ee91343 | 22218 | now_pred.block_length++; |
e07e6e58 | 22219 | |
5ee91343 AV |
22220 | if (now_pred.block_length > 4 |
22221 | || !now_pred_compatible (inst.cond)) | |
e07e6e58 NC |
22222 | { |
22223 | force_automatic_it_block_close (); | |
5ee91343 | 22224 | if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN) |
e07e6e58 NC |
22225 | new_automatic_it_block (inst.cond); |
22226 | } | |
22227 | else | |
22228 | { | |
5ee91343 AV |
22229 | now_pred.insn_cond = TRUE; |
22230 | now_pred_add_mask (inst.cond); | |
e07e6e58 NC |
22231 | } |
22232 | ||
5ee91343 AV |
22233 | if (now_pred.state == AUTOMATIC_PRED_BLOCK |
22234 | && (inst.pred_insn_type == INSIDE_IT_LAST_INSN | |
22235 | || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
e07e6e58 NC |
22236 | close_automatic_it_block (); |
22237 | break; | |
22238 | ||
22239 | case NEUTRAL_IT_INSN: | |
5ee91343 AV |
22240 | now_pred.block_length++; |
22241 | now_pred.insn_cond = TRUE; | |
e07e6e58 | 22242 | |
5ee91343 | 22243 | if (now_pred.block_length > 4) |
e07e6e58 NC |
22244 | force_automatic_it_block_close (); |
22245 | else | |
5ee91343 | 22246 | now_pred_add_mask (now_pred.cc & 1); |
e07e6e58 NC |
22247 | break; |
22248 | ||
22249 | case IT_INSN: | |
22250 | close_automatic_it_block (); | |
5ee91343 | 22251 | now_pred.state = MANUAL_PRED_BLOCK; |
e07e6e58 NC |
22252 | break; |
22253 | } | |
22254 | break; | |
22255 | ||
5ee91343 | 22256 | case MANUAL_PRED_BLOCK: |
e07e6e58 | 22257 | { |
5ee91343 AV |
22258 | int cond, is_last; |
22259 | if (now_pred.type == SCALAR_PRED) | |
e07e6e58 | 22260 | { |
5ee91343 AV |
22261 | /* Check conditional suffixes. */ |
22262 | cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1; | |
22263 | now_pred.mask <<= 1; | |
22264 | now_pred.mask &= 0x1f; | |
22265 | is_last = (now_pred.mask == 0x10); | |
22266 | } | |
22267 | else | |
22268 | { | |
22269 | now_pred.cc ^= (now_pred.mask >> 4); | |
22270 | cond = now_pred.cc + 0xf; | |
22271 | now_pred.mask <<= 1; | |
22272 | now_pred.mask &= 0x1f; | |
22273 | is_last = now_pred.mask == 0x10; | |
22274 | } | |
22275 | now_pred.insn_cond = TRUE; | |
e07e6e58 | 22276 | |
5ee91343 AV |
22277 | switch (inst.pred_insn_type) |
22278 | { | |
22279 | case OUTSIDE_PRED_INSN: | |
22280 | if (now_pred.type == SCALAR_PRED) | |
22281 | { | |
22282 | if (inst.cond == COND_ALWAYS) | |
22283 | { | |
22284 | /* Case 12: In an IT block, with no code: error: missing | |
22285 | code. */ | |
22286 | inst.error = BAD_NOT_IT; | |
22287 | return FAIL; | |
22288 | } | |
22289 | else if (inst.cond > COND_ALWAYS) | |
22290 | { | |
22291 | /* Case 11: In an IT block, with a VPT code: syntax error. | |
22292 | */ | |
22293 | inst.error = BAD_SYNTAX; | |
22294 | return FAIL; | |
22295 | } | |
22296 | else if (thumb_mode) | |
22297 | { | |
22298 | /* This is for some special cases where a non-MVE | |
22299 | instruction is not allowed in an IT block, such as cbz, | |
22300 | but are put into one with a condition code. | |
22301 | You could argue this should be a syntax error, but we | |
22302 | gave the 'not allowed in IT block' diagnostic in the | |
22303 | past so we will keep doing so. */ | |
22304 | inst.error = BAD_NOT_IT; | |
22305 | return FAIL; | |
22306 | } | |
22307 | break; | |
22308 | } | |
22309 | else | |
22310 | { | |
22311 | /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */ | |
22312 | as_tsktsk (MVE_NOT_VPT); | |
22313 | return SUCCESS; | |
22314 | } | |
22315 | case MVE_OUTSIDE_PRED_INSN: | |
22316 | if (now_pred.type == SCALAR_PRED) | |
22317 | { | |
22318 | if (inst.cond == COND_ALWAYS) | |
22319 | { | |
22320 | /* Case 3: In an IT block, with no code: warning: | |
22321 | UNPREDICTABLE. */ | |
22322 | as_tsktsk (MVE_NOT_IT); | |
22323 | return SUCCESS; | |
22324 | } | |
22325 | else if (inst.cond < COND_ALWAYS) | |
22326 | { | |
22327 | /* Case 1: In an IT block, with an IT code: syntax error. | |
22328 | */ | |
22329 | inst.error = BAD_SYNTAX; | |
22330 | return FAIL; | |
22331 | } | |
22332 | else | |
22333 | gas_assert (0); | |
22334 | } | |
22335 | else | |
22336 | { | |
22337 | if (inst.cond < COND_ALWAYS) | |
22338 | { | |
22339 | /* Case 4: In a VPT block, with an IT code: syntax error. | |
22340 | */ | |
22341 | inst.error = BAD_SYNTAX; | |
22342 | return FAIL; | |
22343 | } | |
22344 | else if (inst.cond == COND_ALWAYS) | |
22345 | { | |
22346 | /* Case 6: In a VPT block, with no code: error: missing | |
22347 | code. */ | |
22348 | inst.error = BAD_NOT_VPT; | |
22349 | return FAIL; | |
22350 | } | |
22351 | else | |
22352 | { | |
22353 | gas_assert (0); | |
22354 | } | |
22355 | } | |
35c228db AV |
22356 | case MVE_UNPREDICABLE_INSN: |
22357 | as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT); | |
22358 | return SUCCESS; | |
e07e6e58 | 22359 | case INSIDE_IT_INSN: |
5ee91343 | 22360 | if (inst.cond > COND_ALWAYS) |
e07e6e58 | 22361 | { |
5ee91343 AV |
22362 | /* Case 11: In an IT block, with a VPT code: syntax error. */ |
22363 | /* Case 14: In a VPT block, with a VPT code: syntax error. */ | |
22364 | inst.error = BAD_SYNTAX; | |
22365 | return FAIL; | |
22366 | } | |
22367 | else if (now_pred.type == SCALAR_PRED) | |
22368 | { | |
22369 | /* Case 10: In an IT block, with an IT code: OK! */ | |
22370 | if (cond != inst.cond) | |
22371 | { | |
22372 | inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND : | |
22373 | BAD_VPT_COND; | |
22374 | return FAIL; | |
22375 | } | |
22376 | } | |
22377 | else | |
22378 | { | |
22379 | /* Case 13: In a VPT block, with an IT code: error: should be | |
22380 | in an IT block. */ | |
22381 | inst.error = BAD_OUT_IT; | |
e07e6e58 NC |
22382 | return FAIL; |
22383 | } | |
22384 | break; | |
22385 | ||
5ee91343 AV |
22386 | case INSIDE_VPT_INSN: |
22387 | if (now_pred.type == SCALAR_PRED) | |
22388 | { | |
22389 | /* Case 2: In an IT block, with a VPT code: error: must be in a | |
22390 | VPT block. */ | |
22391 | inst.error = BAD_OUT_VPT; | |
22392 | return FAIL; | |
22393 | } | |
22394 | /* Case 5: In a VPT block, with a VPT code: OK! */ | |
22395 | else if (cond != inst.cond) | |
22396 | { | |
22397 | inst.error = BAD_VPT_COND; | |
22398 | return FAIL; | |
22399 | } | |
22400 | break; | |
e07e6e58 NC |
22401 | case INSIDE_IT_LAST_INSN: |
22402 | case IF_INSIDE_IT_LAST_INSN: | |
5ee91343 AV |
22403 | if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS) |
22404 | { | |
22405 | /* Case 4: In a VPT block, with an IT code: syntax error. */ | |
22406 | /* Case 11: In an IT block, with a VPT code: syntax error. */ | |
22407 | inst.error = BAD_SYNTAX; | |
22408 | return FAIL; | |
22409 | } | |
22410 | else if (cond != inst.cond) | |
e07e6e58 NC |
22411 | { |
22412 | inst.error = BAD_IT_COND; | |
22413 | return FAIL; | |
22414 | } | |
22415 | if (!is_last) | |
22416 | { | |
22417 | inst.error = BAD_BRANCH; | |
22418 | return FAIL; | |
22419 | } | |
22420 | break; | |
22421 | ||
22422 | case NEUTRAL_IT_INSN: | |
5ee91343 AV |
22423 | /* The BKPT instruction is unconditional even in a IT or VPT |
22424 | block. */ | |
e07e6e58 NC |
22425 | break; |
22426 | ||
22427 | case IT_INSN: | |
5ee91343 AV |
22428 | if (now_pred.type == SCALAR_PRED) |
22429 | { | |
22430 | inst.error = BAD_IT_IT; | |
22431 | return FAIL; | |
22432 | } | |
22433 | /* fall through. */ | |
22434 | case VPT_INSN: | |
22435 | if (inst.cond == COND_ALWAYS) | |
22436 | { | |
22437 | /* Executing a VPT/VPST instruction inside an IT block or a | |
22438 | VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE. | |
22439 | */ | |
22440 | if (now_pred.type == SCALAR_PRED) | |
22441 | as_tsktsk (MVE_NOT_IT); | |
22442 | else | |
22443 | as_tsktsk (MVE_NOT_VPT); | |
22444 | return SUCCESS; | |
22445 | } | |
22446 | else | |
22447 | { | |
22448 | /* VPT/VPST do not accept condition codes. */ | |
22449 | inst.error = BAD_SYNTAX; | |
22450 | return FAIL; | |
22451 | } | |
e07e6e58 | 22452 | } |
5ee91343 | 22453 | } |
e07e6e58 NC |
22454 | break; |
22455 | } | |
22456 | ||
22457 | return SUCCESS; | |
22458 | } | |
22459 | ||
5a01bb1d MGD |
22460 | struct depr_insn_mask |
22461 | { | |
22462 | unsigned long pattern; | |
22463 | unsigned long mask; | |
22464 | const char* description; | |
22465 | }; | |
22466 | ||
22467 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
22468 | ARMv8. */ | |
22469 | static const struct depr_insn_mask depr_it_insns[] = { | |
22470 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
22471 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
22472 | { 0xa000, 0xb800, N_("ADR") }, | |
22473 | { 0x4800, 0xf800, N_("Literal loads") }, | |
22474 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
22475 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
22476 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
22477 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
22478 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
22479 | { 0, 0, NULL } |
22480 | }; | |
22481 | ||
e07e6e58 NC |
22482 | static void |
22483 | it_fsm_post_encode (void) | |
22484 | { | |
22485 | int is_last; | |
22486 | ||
5ee91343 AV |
22487 | if (!now_pred.state_handled) |
22488 | handle_pred_state (); | |
e07e6e58 | 22489 | |
5ee91343 AV |
22490 | if (now_pred.insn_cond |
22491 | && !now_pred.warn_deprecated | |
5a01bb1d | 22492 | && warn_on_deprecated |
df9909b8 TP |
22493 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8) |
22494 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m)) | |
5a01bb1d MGD |
22495 | { |
22496 | if (inst.instruction >= 0x10000) | |
22497 | { | |
5c3696f8 | 22498 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
df9909b8 | 22499 | "performance deprecated in ARMv8-A and ARMv8-R")); |
5ee91343 | 22500 | now_pred.warn_deprecated = TRUE; |
5a01bb1d MGD |
22501 | } |
22502 | else | |
22503 | { | |
22504 | const struct depr_insn_mask *p = depr_it_insns; | |
22505 | ||
22506 | while (p->mask != 0) | |
22507 | { | |
22508 | if ((inst.instruction & p->mask) == p->pattern) | |
22509 | { | |
df9909b8 TP |
22510 | as_tsktsk (_("IT blocks containing 16-bit Thumb " |
22511 | "instructions of the following class are " | |
22512 | "performance deprecated in ARMv8-A and " | |
22513 | "ARMv8-R: %s"), p->description); | |
5ee91343 | 22514 | now_pred.warn_deprecated = TRUE; |
5a01bb1d MGD |
22515 | break; |
22516 | } | |
22517 | ||
22518 | ++p; | |
22519 | } | |
22520 | } | |
22521 | ||
5ee91343 | 22522 | if (now_pred.block_length > 1) |
5a01bb1d | 22523 | { |
5c3696f8 | 22524 | as_tsktsk (_("IT blocks containing more than one conditional " |
df9909b8 TP |
22525 | "instruction are performance deprecated in ARMv8-A and " |
22526 | "ARMv8-R")); | |
5ee91343 | 22527 | now_pred.warn_deprecated = TRUE; |
5a01bb1d MGD |
22528 | } |
22529 | } | |
22530 | ||
5ee91343 AV |
22531 | is_last = (now_pred.mask == 0x10); |
22532 | if (is_last) | |
22533 | { | |
22534 | now_pred.state = OUTSIDE_PRED_BLOCK; | |
22535 | now_pred.mask = 0; | |
22536 | } | |
e07e6e58 NC |
22537 | } |
22538 | ||
22539 | static void | |
22540 | force_automatic_it_block_close (void) | |
22541 | { | |
5ee91343 | 22542 | if (now_pred.state == AUTOMATIC_PRED_BLOCK) |
e07e6e58 NC |
22543 | { |
22544 | close_automatic_it_block (); | |
5ee91343 AV |
22545 | now_pred.state = OUTSIDE_PRED_BLOCK; |
22546 | now_pred.mask = 0; | |
e07e6e58 NC |
22547 | } |
22548 | } | |
22549 | ||
22550 | static int | |
5ee91343 | 22551 | in_pred_block (void) |
e07e6e58 | 22552 | { |
5ee91343 AV |
22553 | if (!now_pred.state_handled) |
22554 | handle_pred_state (); | |
e07e6e58 | 22555 | |
5ee91343 | 22556 | return now_pred.state != OUTSIDE_PRED_BLOCK; |
e07e6e58 NC |
22557 | } |
22558 | ||
ff8646ee TP |
22559 | /* Whether OPCODE only has T32 encoding. Since this function is only used by |
22560 | t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed | |
22561 | here, hence the "known" in the function name. */ | |
fc289b0a TP |
22562 | |
22563 | static bfd_boolean | |
ff8646ee | 22564 | known_t32_only_insn (const struct asm_opcode *opcode) |
fc289b0a TP |
22565 | { |
22566 | /* Original Thumb-1 wide instruction. */ | |
22567 | if (opcode->tencode == do_t_blx | |
22568 | || opcode->tencode == do_t_branch23 | |
22569 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) | |
22570 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)) | |
22571 | return TRUE; | |
22572 | ||
16a1fa25 TP |
22573 | /* Wide-only instruction added to ARMv8-M Baseline. */ |
22574 | if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only) | |
ff8646ee TP |
22575 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics) |
22576 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m) | |
22577 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div)) | |
22578 | return TRUE; | |
22579 | ||
22580 | return FALSE; | |
22581 | } | |
22582 | ||
22583 | /* Whether wide instruction variant can be used if available for a valid OPCODE | |
22584 | in ARCH. */ | |
22585 | ||
22586 | static bfd_boolean | |
22587 | t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode) | |
22588 | { | |
22589 | if (known_t32_only_insn (opcode)) | |
22590 | return TRUE; | |
22591 | ||
22592 | /* Instruction with narrow and wide encoding added to ARMv8-M. Availability | |
22593 | of variant T3 of B.W is checked in do_t_branch. */ | |
22594 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) | |
22595 | && opcode->tencode == do_t_branch) | |
22596 | return TRUE; | |
22597 | ||
bada4342 JW |
22598 | /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */ |
22599 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) | |
22600 | && opcode->tencode == do_t_mov_cmp | |
22601 | /* Make sure CMP instruction is not affected. */ | |
22602 | && opcode->aencode == do_mov) | |
22603 | return TRUE; | |
22604 | ||
ff8646ee TP |
22605 | /* Wide instruction variants of all instructions with narrow *and* wide |
22606 | variants become available with ARMv6t2. Other opcodes are either | |
22607 | narrow-only or wide-only and are thus available if OPCODE is valid. */ | |
22608 | if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2)) | |
22609 | return TRUE; | |
22610 | ||
22611 | /* OPCODE with narrow only instruction variant or wide variant not | |
22612 | available. */ | |
fc289b0a TP |
22613 | return FALSE; |
22614 | } | |
22615 | ||
c19d1205 ZW |
22616 | void |
22617 | md_assemble (char *str) | |
b99bd4ef | 22618 | { |
c19d1205 ZW |
22619 | char *p = str; |
22620 | const struct asm_opcode * opcode; | |
b99bd4ef | 22621 | |
c19d1205 ZW |
22622 | /* Align the previous label if needed. */ |
22623 | if (last_label_seen != NULL) | |
b99bd4ef | 22624 | { |
c19d1205 ZW |
22625 | symbol_set_frag (last_label_seen, frag_now); |
22626 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
22627 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
22628 | } |
22629 | ||
c19d1205 | 22630 | memset (&inst, '\0', sizeof (inst)); |
e2b0ab59 AV |
22631 | int r; |
22632 | for (r = 0; r < ARM_IT_MAX_RELOCS; r++) | |
22633 | inst.relocs[r].type = BFD_RELOC_UNUSED; | |
b99bd4ef | 22634 | |
c19d1205 ZW |
22635 | opcode = opcode_lookup (&p); |
22636 | if (!opcode) | |
b99bd4ef | 22637 | { |
c19d1205 | 22638 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 22639 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 22640 | if (! create_register_alias (str, p) |
477330fc | 22641 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 22642 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 22643 | |
b99bd4ef NC |
22644 | return; |
22645 | } | |
22646 | ||
278df34e | 22647 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
5c3696f8 | 22648 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
088fa78e | 22649 | |
037e8744 JB |
22650 | /* The value which unconditional instructions should have in place of the |
22651 | condition field. */ | |
22652 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
22653 | ||
c19d1205 | 22654 | if (thumb_mode) |
b99bd4ef | 22655 | { |
e74cfd16 | 22656 | arm_feature_set variant; |
8f06b2d8 PB |
22657 | |
22658 | variant = cpu_variant; | |
22659 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
22660 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
22661 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 22662 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
22663 | if (!opcode->tvariant |
22664 | || (thumb_mode == 1 | |
22665 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 22666 | { |
173205ca TP |
22667 | if (opcode->tencode == do_t_swi) |
22668 | as_bad (_("SVC is not permitted on this architecture")); | |
22669 | else | |
22670 | as_bad (_("selected processor does not support `%s' in Thumb mode"), str); | |
b99bd4ef NC |
22671 | return; |
22672 | } | |
c19d1205 ZW |
22673 | if (inst.cond != COND_ALWAYS && !unified_syntax |
22674 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 22675 | { |
c19d1205 | 22676 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
22677 | return; |
22678 | } | |
22679 | ||
fc289b0a TP |
22680 | /* Two things are addressed here: |
22681 | 1) Implicit require narrow instructions on Thumb-1. | |
22682 | This avoids relaxation accidentally introducing Thumb-2 | |
22683 | instructions. | |
22684 | 2) Reject wide instructions in non Thumb-2 cores. | |
22685 | ||
22686 | Only instructions with narrow and wide variants need to be handled | |
22687 | but selecting all non wide-only instructions is easier. */ | |
22688 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) | |
ff8646ee | 22689 | && !t32_insn_ok (variant, opcode)) |
076d447c | 22690 | { |
fc289b0a TP |
22691 | if (inst.size_req == 0) |
22692 | inst.size_req = 2; | |
22693 | else if (inst.size_req == 4) | |
752d5da4 | 22694 | { |
ff8646ee TP |
22695 | if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m)) |
22696 | as_bad (_("selected processor does not support 32bit wide " | |
22697 | "variant of instruction `%s'"), str); | |
22698 | else | |
22699 | as_bad (_("selected processor does not support `%s' in " | |
22700 | "Thumb-2 mode"), str); | |
fc289b0a | 22701 | return; |
752d5da4 | 22702 | } |
076d447c PB |
22703 | } |
22704 | ||
c19d1205 ZW |
22705 | inst.instruction = opcode->tvalue; |
22706 | ||
5be8be5d | 22707 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc | 22708 | { |
5ee91343 | 22709 | /* Prepare the pred_insn_type for those encodings that don't set |
477330fc RM |
22710 | it. */ |
22711 | it_fsm_pre_encode (); | |
c19d1205 | 22712 | |
477330fc | 22713 | opcode->tencode (); |
e07e6e58 | 22714 | |
477330fc RM |
22715 | it_fsm_post_encode (); |
22716 | } | |
e27ec89e | 22717 | |
0110f2b8 | 22718 | if (!(inst.error || inst.relax)) |
b99bd4ef | 22719 | { |
9c2799c2 | 22720 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
22721 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
22722 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 22723 | { |
c19d1205 | 22724 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
22725 | return; |
22726 | } | |
22727 | } | |
076d447c PB |
22728 | |
22729 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 22730 | instruction. */ |
9c2799c2 | 22731 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 22732 | |
e74cfd16 PB |
22733 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
22734 | *opcode->tvariant); | |
ee065d83 | 22735 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
fc289b0a TP |
22736 | set those bits when Thumb-2 32-bit instructions are seen. The impact |
22737 | of relaxable instructions will be considered later after we finish all | |
22738 | relaxation. */ | |
ff8646ee TP |
22739 | if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any)) |
22740 | variant = arm_arch_none; | |
22741 | else | |
22742 | variant = cpu_variant; | |
22743 | if (inst.size == 4 && !t32_insn_ok (variant, opcode)) | |
e74cfd16 PB |
22744 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
22745 | arm_ext_v6t2); | |
cd000bff | 22746 | |
88714cb8 DG |
22747 | check_neon_suffixes; |
22748 | ||
cd000bff | 22749 | if (!inst.error) |
c877a2f2 NC |
22750 | { |
22751 | mapping_state (MAP_THUMB); | |
22752 | } | |
c19d1205 | 22753 | } |
3e9e4fcf | 22754 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 22755 | { |
845b51d6 PB |
22756 | bfd_boolean is_bx; |
22757 | ||
22758 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
22759 | is_bx = (opcode->aencode == do_bx); | |
22760 | ||
c19d1205 | 22761 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
22762 | if (!(is_bx && fix_v4bx) |
22763 | && !(opcode->avariant && | |
22764 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 22765 | { |
84b52b66 | 22766 | as_bad (_("selected processor does not support `%s' in ARM mode"), str); |
c19d1205 | 22767 | return; |
b99bd4ef | 22768 | } |
c19d1205 | 22769 | if (inst.size_req) |
b99bd4ef | 22770 | { |
c19d1205 ZW |
22771 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
22772 | return; | |
b99bd4ef NC |
22773 | } |
22774 | ||
c19d1205 ZW |
22775 | inst.instruction = opcode->avalue; |
22776 | if (opcode->tag == OT_unconditionalF) | |
eff0bc54 | 22777 | inst.instruction |= 0xFU << 28; |
c19d1205 ZW |
22778 | else |
22779 | inst.instruction |= inst.cond << 28; | |
22780 | inst.size = INSN_SIZE; | |
5be8be5d | 22781 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
22782 | { |
22783 | it_fsm_pre_encode (); | |
22784 | opcode->aencode (); | |
22785 | it_fsm_post_encode (); | |
22786 | } | |
ee065d83 | 22787 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 22788 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 22789 | if (is_bx) |
e74cfd16 | 22790 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 22791 | else |
e74cfd16 PB |
22792 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
22793 | *opcode->avariant); | |
88714cb8 DG |
22794 | |
22795 | check_neon_suffixes; | |
22796 | ||
cd000bff | 22797 | if (!inst.error) |
c877a2f2 NC |
22798 | { |
22799 | mapping_state (MAP_ARM); | |
22800 | } | |
b99bd4ef | 22801 | } |
3e9e4fcf JB |
22802 | else |
22803 | { | |
22804 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
22805 | "-- `%s'"), str); | |
22806 | return; | |
22807 | } | |
c19d1205 ZW |
22808 | output_inst (str); |
22809 | } | |
b99bd4ef | 22810 | |
e07e6e58 | 22811 | static void |
5ee91343 | 22812 | check_pred_blocks_finished (void) |
e07e6e58 NC |
22813 | { |
22814 | #ifdef OBJ_ELF | |
22815 | asection *sect; | |
22816 | ||
22817 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
5ee91343 AV |
22818 | if (seg_info (sect)->tc_segment_info_data.current_pred.state |
22819 | == MANUAL_PRED_BLOCK) | |
e07e6e58 | 22820 | { |
5ee91343 AV |
22821 | if (now_pred.type == SCALAR_PRED) |
22822 | as_warn (_("section '%s' finished with an open IT block."), | |
22823 | sect->name); | |
22824 | else | |
22825 | as_warn (_("section '%s' finished with an open VPT/VPST block."), | |
22826 | sect->name); | |
e07e6e58 NC |
22827 | } |
22828 | #else | |
5ee91343 AV |
22829 | if (now_pred.state == MANUAL_PRED_BLOCK) |
22830 | { | |
22831 | if (now_pred.type == SCALAR_PRED) | |
22832 | as_warn (_("file finished with an open IT block.")); | |
22833 | else | |
22834 | as_warn (_("file finished with an open VPT/VPST block.")); | |
22835 | } | |
e07e6e58 NC |
22836 | #endif |
22837 | } | |
22838 | ||
c19d1205 ZW |
22839 | /* Various frobbings of labels and their addresses. */ |
22840 | ||
22841 | void | |
22842 | arm_start_line_hook (void) | |
22843 | { | |
22844 | last_label_seen = NULL; | |
b99bd4ef NC |
22845 | } |
22846 | ||
c19d1205 ZW |
22847 | void |
22848 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 22849 | { |
c19d1205 | 22850 | last_label_seen = sym; |
b99bd4ef | 22851 | |
c19d1205 | 22852 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 22853 | |
c19d1205 ZW |
22854 | #if defined OBJ_COFF || defined OBJ_ELF |
22855 | ARM_SET_INTERWORK (sym, support_interwork); | |
22856 | #endif | |
b99bd4ef | 22857 | |
e07e6e58 NC |
22858 | force_automatic_it_block_close (); |
22859 | ||
5f4273c7 | 22860 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
22861 | as Thumb functions. This is because these labels, whilst |
22862 | they exist inside Thumb code, are not the entry points for | |
22863 | possible ARM->Thumb calls. Also, these labels can be used | |
22864 | as part of a computed goto or switch statement. eg gcc | |
22865 | can generate code that looks like this: | |
b99bd4ef | 22866 | |
c19d1205 ZW |
22867 | ldr r2, [pc, .Laaa] |
22868 | lsl r3, r3, #2 | |
22869 | ldr r2, [r3, r2] | |
22870 | mov pc, r2 | |
b99bd4ef | 22871 | |
c19d1205 ZW |
22872 | .Lbbb: .word .Lxxx |
22873 | .Lccc: .word .Lyyy | |
22874 | ..etc... | |
22875 | .Laaa: .word Lbbb | |
b99bd4ef | 22876 | |
c19d1205 ZW |
22877 | The first instruction loads the address of the jump table. |
22878 | The second instruction converts a table index into a byte offset. | |
22879 | The third instruction gets the jump address out of the table. | |
22880 | The fourth instruction performs the jump. | |
b99bd4ef | 22881 | |
c19d1205 ZW |
22882 | If the address stored at .Laaa is that of a symbol which has the |
22883 | Thumb_Func bit set, then the linker will arrange for this address | |
22884 | to have the bottom bit set, which in turn would mean that the | |
22885 | address computation performed by the third instruction would end | |
22886 | up with the bottom bit set. Since the ARM is capable of unaligned | |
22887 | word loads, the instruction would then load the incorrect address | |
22888 | out of the jump table, and chaos would ensue. */ | |
22889 | if (label_is_thumb_function_name | |
22890 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
fd361982 | 22891 | && (bfd_section_flags (now_seg) & SEC_CODE) != 0) |
b99bd4ef | 22892 | { |
c19d1205 ZW |
22893 | /* When the address of a Thumb function is taken the bottom |
22894 | bit of that address should be set. This will allow | |
22895 | interworking between Arm and Thumb functions to work | |
22896 | correctly. */ | |
b99bd4ef | 22897 | |
c19d1205 | 22898 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 22899 | |
c19d1205 | 22900 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 22901 | } |
07a53e5c | 22902 | |
07a53e5c | 22903 | dwarf2_emit_label (sym); |
b99bd4ef NC |
22904 | } |
22905 | ||
c921be7d | 22906 | bfd_boolean |
c19d1205 | 22907 | arm_data_in_code (void) |
b99bd4ef | 22908 | { |
c19d1205 | 22909 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 22910 | { |
c19d1205 ZW |
22911 | *input_line_pointer = '/'; |
22912 | input_line_pointer += 5; | |
22913 | *input_line_pointer = 0; | |
c921be7d | 22914 | return TRUE; |
b99bd4ef NC |
22915 | } |
22916 | ||
c921be7d | 22917 | return FALSE; |
b99bd4ef NC |
22918 | } |
22919 | ||
c19d1205 ZW |
22920 | char * |
22921 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 22922 | { |
c19d1205 | 22923 | int len; |
b99bd4ef | 22924 | |
c19d1205 ZW |
22925 | if (thumb_mode && (len = strlen (name)) > 5 |
22926 | && streq (name + len - 5, "/data")) | |
22927 | *(name + len - 5) = 0; | |
b99bd4ef | 22928 | |
c19d1205 | 22929 | return name; |
b99bd4ef | 22930 | } |
c19d1205 ZW |
22931 | \f |
22932 | /* Table of all register names defined by default. The user can | |
22933 | define additional names with .req. Note that all register names | |
22934 | should appear in both upper and lowercase variants. Some registers | |
22935 | also have mixed-case names. */ | |
b99bd4ef | 22936 | |
dcbf9037 | 22937 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 22938 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 22939 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
22940 | #define REGSET(p,t) \ |
22941 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
22942 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
22943 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
22944 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
22945 | #define REGSETH(p,t) \ |
22946 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
22947 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
22948 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
22949 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
22950 | #define REGSET2(p,t) \ | |
22951 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
22952 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
22953 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
22954 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
22955 | #define SPLRBANK(base,bank,t) \ |
22956 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
22957 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
22958 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
22959 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
22960 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
22961 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 22962 | |
c19d1205 | 22963 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 22964 | { |
c19d1205 ZW |
22965 | /* ARM integer registers. */ |
22966 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 22967 | |
c19d1205 ZW |
22968 | /* ATPCS synonyms. */ |
22969 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
22970 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
22971 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 22972 | |
c19d1205 ZW |
22973 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
22974 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
22975 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 22976 | |
c19d1205 ZW |
22977 | /* Well-known aliases. */ |
22978 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
22979 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
22980 | ||
22981 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
22982 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
22983 | ||
1b883319 AV |
22984 | /* Defining the new Zero register from ARMv8.1-M. */ |
22985 | REGDEF(zr,15,ZR), | |
22986 | REGDEF(ZR,15,ZR), | |
22987 | ||
c19d1205 ZW |
22988 | /* Coprocessor numbers. */ |
22989 | REGSET(p, CP), REGSET(P, CP), | |
22990 | ||
22991 | /* Coprocessor register numbers. The "cr" variants are for backward | |
22992 | compatibility. */ | |
22993 | REGSET(c, CN), REGSET(C, CN), | |
22994 | REGSET(cr, CN), REGSET(CR, CN), | |
22995 | ||
90ec0d68 MGD |
22996 | /* ARM banked registers. */ |
22997 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
22998 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
22999 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
23000 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
23001 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
23002 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
23003 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
23004 | ||
23005 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
23006 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
23007 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
23008 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
23009 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 23010 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
23011 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
23012 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
23013 | ||
23014 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
23015 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
23016 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
23017 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
23018 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
23019 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
23020 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 23021 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
23022 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
23023 | ||
c19d1205 ZW |
23024 | /* FPA registers. */ |
23025 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
23026 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
23027 | ||
23028 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
23029 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
23030 | ||
23031 | /* VFP SP registers. */ | |
5287ad62 JB |
23032 | REGSET(s,VFS), REGSET(S,VFS), |
23033 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
23034 | |
23035 | /* VFP DP Registers. */ | |
5287ad62 JB |
23036 | REGSET(d,VFD), REGSET(D,VFD), |
23037 | /* Extra Neon DP registers. */ | |
23038 | REGSETH(d,VFD), REGSETH(D,VFD), | |
23039 | ||
23040 | /* Neon QP registers. */ | |
23041 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
23042 | |
23043 | /* VFP control registers. */ | |
23044 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
23045 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
23046 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
23047 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
23048 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
23049 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
40c7d507 | 23050 | REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC), |
ba6cd17f SD |
23051 | REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC), |
23052 | REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC), | |
23053 | REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC), | |
23054 | REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC), | |
c19d1205 ZW |
23055 | |
23056 | /* Maverick DSP coprocessor registers. */ | |
23057 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
23058 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
23059 | ||
23060 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
23061 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
23062 | REGDEF(dspsc,0,DSPSC), | |
23063 | ||
23064 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
23065 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
23066 | REGDEF(DSPSC,0,DSPSC), | |
23067 | ||
23068 | /* iWMMXt data registers - p0, c0-15. */ | |
23069 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
23070 | ||
23071 | /* iWMMXt control registers - p1, c0-3. */ | |
23072 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
23073 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
23074 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
23075 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
23076 | ||
23077 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
23078 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
23079 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
23080 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
23081 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
23082 | ||
23083 | /* XScale accumulator registers. */ | |
23084 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
23085 | }; | |
23086 | #undef REGDEF | |
23087 | #undef REGNUM | |
23088 | #undef REGSET | |
7ed4c4c5 | 23089 | |
c19d1205 ZW |
23090 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
23091 | within psr_required_here. */ | |
23092 | static const struct asm_psr psrs[] = | |
23093 | { | |
23094 | /* Backward compatibility notation. Note that "all" is no longer | |
23095 | truly all possible PSR bits. */ | |
23096 | {"all", PSR_c | PSR_f}, | |
23097 | {"flg", PSR_f}, | |
23098 | {"ctl", PSR_c}, | |
23099 | ||
23100 | /* Individual flags. */ | |
23101 | {"f", PSR_f}, | |
23102 | {"c", PSR_c}, | |
23103 | {"x", PSR_x}, | |
23104 | {"s", PSR_s}, | |
59b42a0d | 23105 | |
c19d1205 ZW |
23106 | /* Combinations of flags. */ |
23107 | {"fs", PSR_f | PSR_s}, | |
23108 | {"fx", PSR_f | PSR_x}, | |
23109 | {"fc", PSR_f | PSR_c}, | |
23110 | {"sf", PSR_s | PSR_f}, | |
23111 | {"sx", PSR_s | PSR_x}, | |
23112 | {"sc", PSR_s | PSR_c}, | |
23113 | {"xf", PSR_x | PSR_f}, | |
23114 | {"xs", PSR_x | PSR_s}, | |
23115 | {"xc", PSR_x | PSR_c}, | |
23116 | {"cf", PSR_c | PSR_f}, | |
23117 | {"cs", PSR_c | PSR_s}, | |
23118 | {"cx", PSR_c | PSR_x}, | |
23119 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
23120 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
23121 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
23122 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
23123 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
23124 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
23125 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
23126 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
23127 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
23128 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
23129 | {"scf", PSR_s | PSR_c | PSR_f}, | |
23130 | {"scx", PSR_s | PSR_c | PSR_x}, | |
23131 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
23132 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
23133 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
23134 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
23135 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
23136 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
23137 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
23138 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
23139 | {"csf", PSR_c | PSR_s | PSR_f}, | |
23140 | {"csx", PSR_c | PSR_s | PSR_x}, | |
23141 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
23142 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
23143 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
23144 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
23145 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
23146 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
23147 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
23148 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
23149 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
23150 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
23151 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
23152 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
23153 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
23154 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
23155 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
23156 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
23157 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
23158 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
23159 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
23160 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
23161 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
23162 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
23163 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
23164 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
23165 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
23166 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
23167 | }; | |
23168 | ||
62b3e311 PB |
23169 | /* Table of V7M psr names. */ |
23170 | static const struct asm_psr v7m_psrs[] = | |
23171 | { | |
1a336194 TP |
23172 | {"apsr", 0x0 }, {"APSR", 0x0 }, |
23173 | {"iapsr", 0x1 }, {"IAPSR", 0x1 }, | |
23174 | {"eapsr", 0x2 }, {"EAPSR", 0x2 }, | |
23175 | {"psr", 0x3 }, {"PSR", 0x3 }, | |
23176 | {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 }, | |
23177 | {"ipsr", 0x5 }, {"IPSR", 0x5 }, | |
23178 | {"epsr", 0x6 }, {"EPSR", 0x6 }, | |
23179 | {"iepsr", 0x7 }, {"IEPSR", 0x7 }, | |
23180 | {"msp", 0x8 }, {"MSP", 0x8 }, | |
23181 | {"psp", 0x9 }, {"PSP", 0x9 }, | |
23182 | {"msplim", 0xa }, {"MSPLIM", 0xa }, | |
23183 | {"psplim", 0xb }, {"PSPLIM", 0xb }, | |
23184 | {"primask", 0x10}, {"PRIMASK", 0x10}, | |
23185 | {"basepri", 0x11}, {"BASEPRI", 0x11}, | |
23186 | {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12}, | |
1a336194 TP |
23187 | {"faultmask", 0x13}, {"FAULTMASK", 0x13}, |
23188 | {"control", 0x14}, {"CONTROL", 0x14}, | |
23189 | {"msp_ns", 0x88}, {"MSP_NS", 0x88}, | |
23190 | {"psp_ns", 0x89}, {"PSP_NS", 0x89}, | |
23191 | {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a}, | |
23192 | {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b}, | |
23193 | {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90}, | |
23194 | {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91}, | |
23195 | {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93}, | |
23196 | {"control_ns", 0x94}, {"CONTROL_NS", 0x94}, | |
23197 | {"sp_ns", 0x98}, {"SP_NS", 0x98 } | |
62b3e311 PB |
23198 | }; |
23199 | ||
c19d1205 ZW |
23200 | /* Table of all shift-in-operand names. */ |
23201 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 23202 | { |
c19d1205 ZW |
23203 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
23204 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
23205 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
23206 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
23207 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
f5f10c66 AV |
23208 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }, |
23209 | { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW} | |
c19d1205 | 23210 | }; |
b99bd4ef | 23211 | |
c19d1205 ZW |
23212 | /* Table of all explicit relocation names. */ |
23213 | #ifdef OBJ_ELF | |
23214 | static struct reloc_entry reloc_names[] = | |
23215 | { | |
23216 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
23217 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
23218 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
23219 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
23220 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
23221 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
23222 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
23223 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
23224 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
23225 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 23226 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
23227 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
23228 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 23229 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 23230 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 23231 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 23232 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
188fd7ae CL |
23233 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}, |
23234 | { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC }, | |
23235 | { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC }, | |
23236 | { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC }, | |
23237 | { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC }, | |
23238 | { "funcdesc", BFD_RELOC_ARM_FUNCDESC }, | |
5c5a4843 CL |
23239 | { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC }, |
23240 | { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC }, | |
23241 | { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, | |
23242 | { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC }, | |
c19d1205 ZW |
23243 | }; |
23244 | #endif | |
b99bd4ef | 23245 | |
5ee91343 | 23246 | /* Table of all conditional affixes. */ |
c19d1205 ZW |
23247 | static const struct asm_cond conds[] = |
23248 | { | |
23249 | {"eq", 0x0}, | |
23250 | {"ne", 0x1}, | |
23251 | {"cs", 0x2}, {"hs", 0x2}, | |
23252 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
23253 | {"mi", 0x4}, | |
23254 | {"pl", 0x5}, | |
23255 | {"vs", 0x6}, | |
23256 | {"vc", 0x7}, | |
23257 | {"hi", 0x8}, | |
23258 | {"ls", 0x9}, | |
23259 | {"ge", 0xa}, | |
23260 | {"lt", 0xb}, | |
23261 | {"gt", 0xc}, | |
23262 | {"le", 0xd}, | |
23263 | {"al", 0xe} | |
23264 | }; | |
5ee91343 AV |
23265 | static const struct asm_cond vconds[] = |
23266 | { | |
23267 | {"t", 0xf}, | |
23268 | {"e", 0x10} | |
23269 | }; | |
bfae80f2 | 23270 | |
e797f7e0 | 23271 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
823d2571 TG |
23272 | { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ |
23273 | { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } | |
e797f7e0 | 23274 | |
62b3e311 PB |
23275 | static struct asm_barrier_opt barrier_opt_names[] = |
23276 | { | |
e797f7e0 MGD |
23277 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
23278 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
23279 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
23280 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
23281 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
23282 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
23283 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
23284 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
23285 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
23286 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
23287 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
23288 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
23289 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
23290 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
23291 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
23292 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
23293 | }; |
23294 | ||
e797f7e0 MGD |
23295 | #undef UL_BARRIER |
23296 | ||
c19d1205 ZW |
23297 | /* Table of ARM-format instructions. */ |
23298 | ||
23299 | /* Macros for gluing together operand strings. N.B. In all cases | |
23300 | other than OPS0, the trailing OP_stop comes from default | |
23301 | zero-initialization of the unspecified elements of the array. */ | |
23302 | #define OPS0() { OP_stop, } | |
23303 | #define OPS1(a) { OP_##a, } | |
23304 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
23305 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
23306 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
23307 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
23308 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
23309 | ||
5be8be5d DG |
23310 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
23311 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
23312 | MIX_ARM_THUMB_OPERANDS macro. | |
23313 | In order to use these macros, prefix the number of operands with _ | |
23314 | e.g. _3. */ | |
23315 | #define OPS_1(a) { a, } | |
23316 | #define OPS_2(a,b) { a,b, } | |
23317 | #define OPS_3(a,b,c) { a,b,c, } | |
23318 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
23319 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
23320 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
23321 | ||
c19d1205 ZW |
23322 | /* These macros abstract out the exact format of the mnemonic table and |
23323 | save some repeated characters. */ | |
23324 | ||
23325 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
23326 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 23327 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
5ee91343 | 23328 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 ZW |
23329 | |
23330 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
23331 | a T_MNEM_xyz enumerator. */ | |
23332 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 23333 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 23334 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 23335 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
23336 | |
23337 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
23338 | infix after the third character. */ | |
23339 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 23340 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
5ee91343 | 23341 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
088fa78e | 23342 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 23343 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
5ee91343 | 23344 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 | 23345 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 23346 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 23347 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 23348 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 23349 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 23350 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 23351 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 23352 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 23353 | |
c19d1205 | 23354 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
23355 | field is still 0xE. Many of the Thumb variants can be executed |
23356 | conditionally, so this is checked separately. */ | |
c19d1205 | 23357 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 23358 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
5ee91343 | 23359 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 | 23360 | |
dd5181d5 KT |
23361 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
23362 | Used by mnemonics that have very minimal differences in the encoding for | |
23363 | ARM and Thumb variants and can be handled in a common function. */ | |
23364 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
23365 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
5ee91343 | 23366 | THUMB_VARIANT, do_##en, do_##en, 0 } |
dd5181d5 | 23367 | |
c19d1205 ZW |
23368 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
23369 | condition code field. */ | |
23370 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 23371 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
5ee91343 | 23372 | THUMB_VARIANT, do_##ae, do_##te, 0 } |
c19d1205 ZW |
23373 | |
23374 | /* ARM-only variants of all the above. */ | |
6a86118a | 23375 | #define CE(mnem, op, nops, ops, ae) \ |
5ee91343 | 23376 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a NC |
23377 | |
23378 | #define C3(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23379 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a | 23380 | |
cf3cf39d TP |
23381 | /* Thumb-only variants of TCE and TUE. */ |
23382 | #define ToC(mnem, top, nops, ops, te) \ | |
23383 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ | |
5ee91343 | 23384 | do_##te, 0 } |
cf3cf39d TP |
23385 | |
23386 | #define ToU(mnem, top, nops, ops, te) \ | |
23387 | { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \ | |
5ee91343 | 23388 | NULL, do_##te, 0 } |
cf3cf39d | 23389 | |
4389b29a AV |
23390 | /* T_MNEM_xyz enumerator variants of ToC. */ |
23391 | #define toC(mnem, top, nops, ops, te) \ | |
23392 | { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \ | |
5ee91343 | 23393 | do_##te, 0 } |
4389b29a | 23394 | |
f6b2b12d AV |
23395 | /* T_MNEM_xyz enumerator variants of ToU. */ |
23396 | #define toU(mnem, top, nops, ops, te) \ | |
23397 | { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \ | |
5ee91343 | 23398 | NULL, do_##te, 0 } |
f6b2b12d | 23399 | |
e3cb604e PB |
23400 | /* Legacy mnemonics that always have conditional infix after the third |
23401 | character. */ | |
23402 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 23403 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
5ee91343 | 23404 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
e3cb604e | 23405 | |
8f06b2d8 PB |
23406 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
23407 | #define cCE(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23408 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
8f06b2d8 | 23409 | |
57785aa2 AV |
23410 | /* mov instructions that are shared between coprocessor and MVE. */ |
23411 | #define mcCE(mnem, op, nops, ops, ae) \ | |
23412 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 } | |
23413 | ||
e3cb604e PB |
23414 | /* Legacy coprocessor instructions where conditional infix and conditional |
23415 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
23416 | not just the potentially ambiguous ones. */ | |
23417 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 23418 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
5ee91343 | 23419 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
e3cb604e PB |
23420 | |
23421 | /* Coprocessor, takes either a suffix or a position-3 infix | |
23422 | (for an FPA corner case). */ | |
23423 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 23424 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
5ee91343 | 23425 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 } |
8f06b2d8 | 23426 | |
6a86118a | 23427 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
23428 | { m1 #m2 m3, OPS##nops ops, \ |
23429 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
5ee91343 | 23430 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a NC |
23431 | |
23432 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
23433 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
23434 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
23435 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
23436 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
23437 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
23438 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
23439 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
23440 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
23441 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
23442 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
23443 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
23444 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
23445 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
23446 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
23447 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
23448 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
23449 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
23450 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
23451 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
23452 | |
23453 | #define UE(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23454 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a NC |
23455 | |
23456 | #define UF(mnem, op, nops, ops, ae) \ | |
5ee91343 | 23457 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 } |
6a86118a | 23458 | |
5287ad62 JB |
23459 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
23460 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
23461 | use the same encoding function for each. */ | |
23462 | #define NUF(mnem, op, nops, ops, enc) \ | |
23463 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
5ee91343 | 23464 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 } |
5287ad62 JB |
23465 | |
23466 | /* Neon data processing, version which indirects through neon_enc_tab for | |
23467 | the various overloaded versions of opcodes. */ | |
23468 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 23469 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5ee91343 | 23470 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 } |
5287ad62 JB |
23471 | |
23472 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
23473 | version. */ | |
5ee91343 | 23474 | #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \ |
037e8744 | 23475 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ |
5ee91343 | 23476 | THUMB_VARIANT, do_##enc, do_##enc, mve_p } |
5287ad62 | 23477 | |
037e8744 | 23478 | #define NCE(mnem, op, nops, ops, enc) \ |
5ee91343 | 23479 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0) |
037e8744 JB |
23480 | |
23481 | #define NCEF(mnem, op, nops, ops, enc) \ | |
5ee91343 | 23482 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0) |
037e8744 | 23483 | |
5287ad62 | 23484 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
5ee91343 | 23485 | #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \ |
21d799b5 | 23486 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5ee91343 | 23487 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p } |
5287ad62 | 23488 | |
037e8744 | 23489 | #define nCE(mnem, op, nops, ops, enc) \ |
5ee91343 | 23490 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0) |
037e8744 JB |
23491 | |
23492 | #define nCEF(mnem, op, nops, ops, enc) \ | |
5ee91343 AV |
23493 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0) |
23494 | ||
23495 | /* */ | |
23496 | #define mCEF(mnem, op, nops, ops, enc) \ | |
a302e574 | 23497 | { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \ |
5ee91343 AV |
23498 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } |
23499 | ||
23500 | ||
23501 | /* nCEF but for MVE predicated instructions. */ | |
23502 | #define mnCEF(mnem, op, nops, ops, enc) \ | |
23503 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1) | |
23504 | ||
23505 | /* nCE but for MVE predicated instructions. */ | |
23506 | #define mnCE(mnem, op, nops, ops, enc) \ | |
23507 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1) | |
037e8744 | 23508 | |
5ee91343 AV |
23509 | /* NUF but for potentially MVE predicated instructions. */ |
23510 | #define MNUF(mnem, op, nops, ops, enc) \ | |
23511 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
23512 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } | |
23513 | ||
23514 | /* nUF but for potentially MVE predicated instructions. */ | |
23515 | #define mnUF(mnem, op, nops, ops, enc) \ | |
23516 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ | |
23517 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } | |
23518 | ||
23519 | /* ToC but for potentially MVE predicated instructions. */ | |
23520 | #define mToC(mnem, top, nops, ops, te) \ | |
23521 | { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \ | |
23522 | do_##te, 1 } | |
23523 | ||
23524 | /* NCE but for MVE predicated instructions. */ | |
23525 | #define MNCE(mnem, op, nops, ops, enc) \ | |
23526 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1) | |
23527 | ||
23528 | /* NCEF but for MVE predicated instructions. */ | |
23529 | #define MNCEF(mnem, op, nops, ops, enc) \ | |
23530 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1) | |
c19d1205 ZW |
23531 | #define do_0 0 |
23532 | ||
c19d1205 | 23533 | static const struct asm_opcode insns[] = |
bfae80f2 | 23534 | { |
74db7efb NC |
23535 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
23536 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
23537 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
23538 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
23539 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
23540 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
23541 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
23542 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
23543 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
23544 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
23545 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
23546 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
23547 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
23548 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
23549 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
23550 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
23551 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
23552 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
23553 | |
23554 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
23555 | for setting PSR flag bits. They are obsolete in V6 and do not | |
23556 | have Thumb equivalents. */ | |
21d799b5 NC |
23557 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
23558 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
23559 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
23560 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
23561 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
23562 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
23563 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
23564 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
23565 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
23566 | ||
23567 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
72d98d16 | 23568 | tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp), |
21d799b5 NC |
23569 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), |
23570 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
23571 | ||
23572 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
23573 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
23574 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
23575 | OP_RRnpc), | |
23576 | OP_ADDRGLDR),ldst, t_ldst), | |
23577 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
23578 | |
23579 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23580 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23581 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23582 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23583 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23584 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
23585 | ||
21d799b5 NC |
23586 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), |
23587 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 23588 | |
c19d1205 | 23589 | /* Pseudo ops. */ |
21d799b5 | 23590 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 23591 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 23592 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 23593 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
23594 | |
23595 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
23596 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
23597 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
23598 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
23599 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
23600 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
23601 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
23602 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
23603 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
23604 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
23605 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
23606 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
23607 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 23608 | |
16a4cf17 | 23609 | /* These may simplify to neg. */ |
21d799b5 NC |
23610 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
23611 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 23612 | |
173205ca TP |
23613 | #undef THUMB_VARIANT |
23614 | #define THUMB_VARIANT & arm_ext_os | |
23615 | ||
23616 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
23617 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
23618 | ||
c921be7d NC |
23619 | #undef THUMB_VARIANT |
23620 | #define THUMB_VARIANT & arm_ext_v6 | |
23621 | ||
21d799b5 | 23622 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
23623 | |
23624 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
23625 | #undef THUMB_VARIANT |
23626 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23627 | ||
21d799b5 NC |
23628 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
23629 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
23630 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 23631 | |
5be8be5d DG |
23632 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
23633 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
23634 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
23635 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 23636 | |
21d799b5 NC |
23637 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
23638 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 23639 | |
21d799b5 NC |
23640 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
23641 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
23642 | |
23643 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 23644 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
23645 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
23646 | ||
23647 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
23648 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
23649 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
23650 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
23651 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
23652 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
23653 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
23654 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
23655 | ||
c921be7d NC |
23656 | #undef ARM_VARIANT |
23657 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
23658 | #undef THUMB_VARIANT | |
23659 | #define THUMB_VARIANT & arm_ext_v4t | |
23660 | ||
21d799b5 NC |
23661 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
23662 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 23663 | |
c921be7d NC |
23664 | #undef THUMB_VARIANT |
23665 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23666 | ||
21d799b5 | 23667 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
23668 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
23669 | ||
23670 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
23671 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
23672 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23673 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23674 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23675 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23676 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 23677 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 23678 | |
c921be7d NC |
23679 | #undef ARM_VARIANT |
23680 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
23681 | ||
21d799b5 | 23682 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
23683 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
23684 | ||
c921be7d NC |
23685 | #undef ARM_VARIANT |
23686 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
23687 | #undef THUMB_VARIANT | |
23688 | #define THUMB_VARIANT & arm_ext_msr | |
23689 | ||
d2cd1205 JB |
23690 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
23691 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 23692 | |
c921be7d NC |
23693 | #undef ARM_VARIANT |
23694 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
23695 | #undef THUMB_VARIANT | |
23696 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23697 | ||
21d799b5 NC |
23698 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
23699 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
23700 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
23701 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
23702 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
23703 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
23704 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
23705 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 23706 | |
c921be7d NC |
23707 | #undef ARM_VARIANT |
23708 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
23709 | #undef THUMB_VARIANT | |
23710 | #define THUMB_VARIANT & arm_ext_v4t | |
23711 | ||
5be8be5d DG |
23712 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
23713 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
23714 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
23715 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
23716 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
23717 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 23718 | |
c921be7d NC |
23719 | #undef ARM_VARIANT |
23720 | #define ARM_VARIANT & arm_ext_v4t_5 | |
23721 | ||
c19d1205 ZW |
23722 | /* ARM Architecture 4T. */ |
23723 | /* Note: bx (and blx) are required on V5, even if the processor does | |
23724 | not support Thumb. */ | |
21d799b5 | 23725 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 23726 | |
c921be7d NC |
23727 | #undef ARM_VARIANT |
23728 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
23729 | #undef THUMB_VARIANT | |
23730 | #define THUMB_VARIANT & arm_ext_v5t | |
23731 | ||
c19d1205 ZW |
23732 | /* Note: blx has 2 variants; the .value coded here is for |
23733 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
23734 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
23735 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 23736 | |
c921be7d NC |
23737 | #undef THUMB_VARIANT |
23738 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23739 | ||
21d799b5 NC |
23740 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
23741 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23742 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23743 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23744 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
23745 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
23746 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
23747 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 23748 | |
c921be7d | 23749 | #undef ARM_VARIANT |
74db7efb NC |
23750 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
23751 | #undef THUMB_VARIANT | |
23752 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 23753 | |
21d799b5 NC |
23754 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
23755 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
23756 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
23757 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 23758 | |
21d799b5 NC |
23759 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
23760 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 23761 | |
21d799b5 NC |
23762 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
23763 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
23764 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
23765 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 23766 | |
21d799b5 NC |
23767 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
23768 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23769 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23770 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 23771 | |
21d799b5 NC |
23772 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
23773 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 23774 | |
03ee1b7f NC |
23775 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
23776 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
23777 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
23778 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 23779 | |
c921be7d | 23780 | #undef ARM_VARIANT |
74db7efb NC |
23781 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
23782 | #undef THUMB_VARIANT | |
23783 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 23784 | |
21d799b5 | 23785 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
23786 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
23787 | ldrd, t_ldstd), | |
23788 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
23789 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 23790 | |
21d799b5 NC |
23791 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
23792 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 23793 | |
c921be7d NC |
23794 | #undef ARM_VARIANT |
23795 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
23796 | ||
21d799b5 | 23797 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 23798 | |
c921be7d NC |
23799 | #undef ARM_VARIANT |
23800 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
23801 | #undef THUMB_VARIANT | |
23802 | #define THUMB_VARIANT & arm_ext_v6 | |
23803 | ||
21d799b5 NC |
23804 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
23805 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
23806 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
23807 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
23808 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
23809 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23810 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23811 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23812 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23813 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 23814 | |
c921be7d | 23815 | #undef THUMB_VARIANT |
ff8646ee | 23816 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
c921be7d | 23817 | |
5be8be5d DG |
23818 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
23819 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
23820 | strex, t_strex), | |
ff8646ee TP |
23821 | #undef THUMB_VARIANT |
23822 | #define THUMB_VARIANT & arm_ext_v6t2 | |
23823 | ||
21d799b5 NC |
23824 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
23825 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 23826 | |
21d799b5 NC |
23827 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
23828 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 23829 | |
9e3c6df6 | 23830 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
23831 | #undef THUMB_VARIANT |
23832 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 23833 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 23834 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
23835 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
23836 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
23837 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
23838 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
23839 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
23840 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
23841 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 23842 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
23843 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
23844 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 23845 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 23846 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 23847 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 23848 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 23849 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 23850 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
941c9cad | 23851 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
c921be7d | 23852 | |
9e3c6df6 PB |
23853 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
23854 | #undef THUMB_VARIANT | |
23855 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
23856 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
23857 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
23858 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23859 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23860 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23861 | /* Old name for QASX. */ |
74db7efb | 23862 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 23863 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23864 | /* Old name for QSAX. */ |
74db7efb | 23865 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23866 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23867 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23868 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23869 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23870 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23871 | /* Old name for SASX. */ |
74db7efb | 23872 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23873 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23874 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 23875 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23876 | /* Old name for SHASX. */ |
21d799b5 | 23877 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 23878 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23879 | /* Old name for SHSAX. */ |
21d799b5 NC |
23880 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23881 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23882 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23883 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23884 | /* Old name for SSAX. */ |
74db7efb | 23885 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23886 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23887 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23888 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23889 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23890 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23891 | /* Old name for UASX. */ |
74db7efb | 23892 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23893 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23894 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 23895 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23896 | /* Old name for UHASX. */ |
21d799b5 NC |
23897 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23898 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23899 | /* Old name for UHSAX. */ |
21d799b5 NC |
23900 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23901 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23902 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23903 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23904 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 23905 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 23906 | /* Old name for UQASX. */ |
21d799b5 NC |
23907 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23908 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23909 | /* Old name for UQSAX. */ |
21d799b5 NC |
23910 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
23911 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23912 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23913 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23914 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 23915 | /* Old name for USAX. */ |
74db7efb | 23916 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 23917 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
23918 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
23919 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23920 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23921 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23922 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23923 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23924 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
23925 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
23926 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
23927 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23928 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23929 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23930 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23931 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23932 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23933 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23934 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
23935 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23936 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23937 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23938 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23939 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23940 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23941 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23942 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23943 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23944 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
23945 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
23946 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
23947 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
23948 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
23949 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 23950 | |
c921be7d | 23951 | #undef ARM_VARIANT |
55e8aae7 | 23952 | #define ARM_VARIANT & arm_ext_v6k_v6t2 |
c921be7d | 23953 | #undef THUMB_VARIANT |
55e8aae7 | 23954 | #define THUMB_VARIANT & arm_ext_v6k_v6t2 |
c921be7d | 23955 | |
21d799b5 NC |
23956 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
23957 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
23958 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
23959 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 23960 | |
c921be7d NC |
23961 | #undef THUMB_VARIANT |
23962 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
23963 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
23964 | ldrexd, t_ldrexd), | |
23965 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
23966 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 23967 | |
c921be7d | 23968 | #undef THUMB_VARIANT |
ff8646ee | 23969 | #define THUMB_VARIANT & arm_ext_v6t2_v8m |
5be8be5d DG |
23970 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
23971 | rd_rn, rd_rn), | |
23972 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
23973 | rd_rn, rd_rn), | |
23974 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 23975 | strex, t_strexbh), |
5be8be5d | 23976 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 23977 | strex, t_strexbh), |
21d799b5 | 23978 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 23979 | |
c921be7d | 23980 | #undef ARM_VARIANT |
f4c65163 | 23981 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 23982 | #undef THUMB_VARIANT |
f4c65163 | 23983 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 23984 | |
21d799b5 | 23985 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 23986 | |
90ec0d68 MGD |
23987 | #undef ARM_VARIANT |
23988 | #define ARM_VARIANT & arm_ext_virt | |
23989 | #undef THUMB_VARIANT | |
23990 | #define THUMB_VARIANT & arm_ext_virt | |
23991 | ||
23992 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
23993 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
23994 | ||
ddfded2f MW |
23995 | #undef ARM_VARIANT |
23996 | #define ARM_VARIANT & arm_ext_pan | |
23997 | #undef THUMB_VARIANT | |
23998 | #define THUMB_VARIANT & arm_ext_pan | |
23999 | ||
24000 | TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan), | |
24001 | ||
c921be7d | 24002 | #undef ARM_VARIANT |
74db7efb | 24003 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
24004 | #undef THUMB_VARIANT |
24005 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 24006 | |
21d799b5 NC |
24007 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
24008 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
24009 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
24010 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 24011 | |
21d799b5 | 24012 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
21d799b5 | 24013 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), |
c19d1205 | 24014 | |
5be8be5d DG |
24015 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
24016 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
24017 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
24018 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 24019 | |
91d8b670 JG |
24020 | #undef ARM_VARIANT |
24021 | #define ARM_VARIANT & arm_ext_v3 | |
24022 | #undef THUMB_VARIANT | |
24023 | #define THUMB_VARIANT & arm_ext_v6t2 | |
24024 | ||
24025 | TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb), | |
c597cc3d SD |
24026 | TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb), |
24027 | TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb), | |
91d8b670 JG |
24028 | |
24029 | #undef ARM_VARIANT | |
24030 | #define ARM_VARIANT & arm_ext_v6t2 | |
ff8646ee TP |
24031 | #undef THUMB_VARIANT |
24032 | #define THUMB_VARIANT & arm_ext_v6t2_v8m | |
24033 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
24034 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
24035 | ||
bf3eeda7 | 24036 | /* Thumb-only instructions. */ |
74db7efb | 24037 | #undef ARM_VARIANT |
bf3eeda7 NS |
24038 | #define ARM_VARIANT NULL |
24039 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
24040 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
24041 | |
24042 | /* ARM does not really have an IT instruction, so always allow it. | |
24043 | The opcode is copied from Thumb in order to allow warnings in | |
24044 | -mimplicit-it=[never | arm] modes. */ | |
24045 | #undef ARM_VARIANT | |
24046 | #define ARM_VARIANT & arm_ext_v1 | |
ff8646ee TP |
24047 | #undef THUMB_VARIANT |
24048 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 24049 | |
21d799b5 NC |
24050 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
24051 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
24052 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
24053 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
24054 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
24055 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
24056 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
24057 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
24058 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
24059 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
24060 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
24061 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
24062 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
24063 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
24064 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 24065 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
24066 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
24067 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 24068 | |
92e90b6e | 24069 | /* Thumb2 only instructions. */ |
c921be7d NC |
24070 | #undef ARM_VARIANT |
24071 | #define ARM_VARIANT NULL | |
92e90b6e | 24072 | |
21d799b5 NC |
24073 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
24074 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
24075 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
24076 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
24077 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
24078 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 24079 | |
eea54501 MGD |
24080 | /* Hardware division instructions. */ |
24081 | #undef ARM_VARIANT | |
24082 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
24083 | #undef THUMB_VARIANT |
24084 | #define THUMB_VARIANT & arm_ext_div | |
24085 | ||
eea54501 MGD |
24086 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
24087 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 24088 | |
7e806470 | 24089 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
24090 | #undef ARM_VARIANT |
24091 | #define ARM_VARIANT & arm_ext_barrier | |
24092 | #undef THUMB_VARIANT | |
24093 | #define THUMB_VARIANT & arm_ext_barrier | |
24094 | ||
ccb84d65 JB |
24095 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
24096 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
24097 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 24098 | |
62b3e311 | 24099 | /* ARM V7 instructions. */ |
c921be7d NC |
24100 | #undef ARM_VARIANT |
24101 | #define ARM_VARIANT & arm_ext_v7 | |
24102 | #undef THUMB_VARIANT | |
24103 | #define THUMB_VARIANT & arm_ext_v7 | |
24104 | ||
21d799b5 NC |
24105 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
24106 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 24107 | |
74db7efb | 24108 | #undef ARM_VARIANT |
60e5ef9f | 24109 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 24110 | #undef THUMB_VARIANT |
60e5ef9f MGD |
24111 | #define THUMB_VARIANT & arm_ext_mp |
24112 | ||
24113 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
24114 | ||
53c4b28b MGD |
24115 | /* AArchv8 instructions. */ |
24116 | #undef ARM_VARIANT | |
24117 | #define ARM_VARIANT & arm_ext_v8 | |
4ed7ed8d TP |
24118 | |
24119 | /* Instructions shared between armv8-a and armv8-m. */ | |
53c4b28b | 24120 | #undef THUMB_VARIANT |
4ed7ed8d | 24121 | #define THUMB_VARIANT & arm_ext_atomics |
53c4b28b | 24122 | |
4ed7ed8d TP |
24123 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
24124 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
24125 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
24126 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
24127 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
24128 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
4b8c8c02 | 24129 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
4b8c8c02 RE |
24130 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
24131 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
24132 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
24133 | stlex, t_stlex), | |
4b8c8c02 RE |
24134 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
24135 | stlex, t_stlex), | |
24136 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
24137 | stlex, t_stlex), | |
4ed7ed8d TP |
24138 | #undef THUMB_VARIANT |
24139 | #define THUMB_VARIANT & arm_ext_v8 | |
53c4b28b | 24140 | |
4ed7ed8d | 24141 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), |
4ed7ed8d TP |
24142 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), |
24143 | ldrexd, t_ldrexd), | |
24144 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
24145 | strexd, t_strexd), | |
f7dd2fb2 TC |
24146 | |
24147 | /* Defined in V8 but is in undefined encoding space for earlier | |
24148 | architectures. However earlier architectures are required to treat | |
24149 | this instuction as a semihosting trap as well. Hence while not explicitly | |
24150 | defined as such, it is in fact correct to define the instruction for all | |
24151 | architectures. */ | |
24152 | #undef THUMB_VARIANT | |
24153 | #define THUMB_VARIANT & arm_ext_v1 | |
24154 | #undef ARM_VARIANT | |
24155 | #define ARM_VARIANT & arm_ext_v1 | |
24156 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), | |
24157 | ||
8884b720 | 24158 | /* ARMv8 T32 only. */ |
74db7efb | 24159 | #undef ARM_VARIANT |
b79f7053 MGD |
24160 | #define ARM_VARIANT NULL |
24161 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
24162 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
24163 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
24164 | ||
33399f07 MGD |
24165 | /* FP for ARMv8. */ |
24166 | #undef ARM_VARIANT | |
a715796b | 24167 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 | 24168 | #undef THUMB_VARIANT |
a715796b | 24169 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 MGD |
24170 | |
24171 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
24172 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
24173 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
24174 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
30bdf752 | 24175 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
a710b305 AV |
24176 | mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz), |
24177 | mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx), | |
24178 | mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta), | |
24179 | mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn), | |
24180 | mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp), | |
24181 | mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm), | |
33399f07 | 24182 | |
91ff7894 MGD |
24183 | /* Crypto v1 extensions. */ |
24184 | #undef ARM_VARIANT | |
24185 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
24186 | #undef THUMB_VARIANT | |
24187 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
24188 | ||
24189 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
24190 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
24191 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
24192 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
24193 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
24194 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
24195 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
24196 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
24197 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
24198 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
24199 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
24200 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
24201 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
24202 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 24203 | |
dd5181d5 | 24204 | #undef ARM_VARIANT |
74db7efb | 24205 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
24206 | #undef THUMB_VARIANT |
24207 | #define THUMB_VARIANT & crc_ext_armv8 | |
24208 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
24209 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
24210 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
24211 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
24212 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
24213 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
24214 | ||
105bde57 MW |
24215 | /* ARMv8.2 RAS extension. */ |
24216 | #undef ARM_VARIANT | |
4d1464f2 | 24217 | #define ARM_VARIANT & arm_ext_ras |
105bde57 | 24218 | #undef THUMB_VARIANT |
4d1464f2 | 24219 | #define THUMB_VARIANT & arm_ext_ras |
105bde57 MW |
24220 | TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), |
24221 | ||
49e8a725 SN |
24222 | #undef ARM_VARIANT |
24223 | #define ARM_VARIANT & arm_ext_v8_3 | |
24224 | #undef THUMB_VARIANT | |
24225 | #define THUMB_VARIANT & arm_ext_v8_3 | |
24226 | NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt), | |
24227 | ||
c604a79a JW |
24228 | #undef ARM_VARIANT |
24229 | #define ARM_VARIANT & fpu_neon_ext_dotprod | |
24230 | #undef THUMB_VARIANT | |
24231 | #define THUMB_VARIANT & fpu_neon_ext_dotprod | |
24232 | NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s), | |
24233 | NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u), | |
24234 | ||
c921be7d NC |
24235 | #undef ARM_VARIANT |
24236 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
24237 | #undef THUMB_VARIANT |
24238 | #define THUMB_VARIANT NULL | |
c921be7d | 24239 | |
21d799b5 NC |
24240 | cCE("wfs", e200110, 1, (RR), rd), |
24241 | cCE("rfs", e300110, 1, (RR), rd), | |
24242 | cCE("wfc", e400110, 1, (RR), rd), | |
24243 | cCE("rfc", e500110, 1, (RR), rd), | |
24244 | ||
24245 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24246 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24247 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24248 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24249 | ||
24250 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24251 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24252 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24253 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
24254 | ||
24255 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
24256 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
24257 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
24258 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
24259 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
24260 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
24261 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
24262 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
24263 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
24264 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
24265 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
24266 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
24267 | ||
24268 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
24269 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
24270 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
24271 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
24272 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
24273 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
24274 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
24275 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
24276 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
24277 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
24278 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
24279 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
24280 | ||
24281 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
24282 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
24283 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
24284 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
24285 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
24286 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
24287 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
24288 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
24289 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
24290 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
24291 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
24292 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
24293 | ||
24294 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
24295 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
24296 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
24297 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
24298 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
24299 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
24300 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
24301 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
24302 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
24303 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
24304 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
24305 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
24306 | ||
24307 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
24308 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
24309 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
24310 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
24311 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
24312 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
24313 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
24314 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
24315 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
24316 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
24317 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
24318 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
24319 | ||
24320 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
24321 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
24322 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
24323 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
24324 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
24325 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
24326 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
24327 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
24328 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
24329 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
24330 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
24331 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
24332 | ||
24333 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
24334 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
24335 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
24336 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
24337 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
24338 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
24339 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
24340 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
24341 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
24342 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
24343 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
24344 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
24345 | ||
24346 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
24347 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
24348 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
24349 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
24350 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
24351 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
24352 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
24353 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
24354 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
24355 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
24356 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
24357 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
24358 | ||
24359 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
24360 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
24361 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
24362 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
24363 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
24364 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
24365 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
24366 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
24367 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
24368 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
24369 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
24370 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
24371 | ||
24372 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
24373 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
24374 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
24375 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
24376 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
24377 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
24378 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
24379 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
24380 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
24381 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
24382 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
24383 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
24384 | ||
24385 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
24386 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
24387 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
24388 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
24389 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
24390 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
24391 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
24392 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
24393 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
24394 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
24395 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
24396 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
24397 | ||
24398 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
24399 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
24400 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
24401 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
24402 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
24403 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
24404 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
24405 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
24406 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
24407 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
24408 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
24409 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
24410 | ||
24411 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
24412 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
24413 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
24414 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
24415 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
24416 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
24417 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
24418 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
24419 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
24420 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
24421 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
24422 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
24423 | ||
24424 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
24425 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
24426 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
24427 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
24428 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
24429 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
24430 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
24431 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
24432 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
24433 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
24434 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
24435 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
24436 | ||
24437 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
24438 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
24439 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
24440 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
24441 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
24442 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
24443 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
24444 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
24445 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
24446 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
24447 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
24448 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
24449 | ||
24450 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
24451 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
24452 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
24453 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
24454 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
24455 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
24456 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
24457 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
24458 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
24459 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
24460 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
24461 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
24462 | ||
24463 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24464 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24465 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24466 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24467 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24468 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24469 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24470 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24471 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24472 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24473 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24474 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24475 | ||
24476 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24477 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24478 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24479 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24480 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24481 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24482 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24483 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24484 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24485 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24486 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24487 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24488 | ||
24489 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24490 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24491 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24492 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24493 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24494 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24495 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24496 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24497 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24498 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24499 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24500 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24501 | ||
24502 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24503 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24504 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24505 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24506 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24507 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24508 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24509 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24510 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24511 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24512 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24513 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24514 | ||
24515 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24516 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24517 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24518 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24519 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24520 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24521 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24522 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24523 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24524 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24525 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24526 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24527 | ||
24528 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24529 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24530 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24531 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24532 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24533 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24534 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24535 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24536 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24537 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24538 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24539 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24540 | ||
24541 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24542 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24543 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24544 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24545 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24546 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24547 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24548 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24549 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24550 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24551 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24552 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24553 | ||
24554 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24555 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24556 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24557 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24558 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24559 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24560 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24561 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24562 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24563 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24564 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24565 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24566 | ||
24567 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24568 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24569 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24570 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24571 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24572 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24573 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24574 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24575 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24576 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24577 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24578 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24579 | ||
24580 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24581 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24582 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24583 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24584 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24585 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24586 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24587 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24588 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24589 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24590 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24591 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24592 | ||
24593 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24594 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24595 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24596 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24597 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24598 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24599 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24600 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24601 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24602 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24603 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24604 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24605 | ||
24606 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24607 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24608 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24609 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24610 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24611 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24612 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24613 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24614 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24615 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24616 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24617 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24618 | ||
24619 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24620 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24621 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24622 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24623 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24624 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24625 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24626 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24627 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24628 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24629 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24630 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
24631 | ||
24632 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
24633 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
24634 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
24635 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
24636 | ||
24637 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
24638 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
24639 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
24640 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
24641 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
24642 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
24643 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
24644 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
24645 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
24646 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
24647 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
24648 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 24649 | |
c19d1205 ZW |
24650 | /* The implementation of the FIX instruction is broken on some |
24651 | assemblers, in that it accepts a precision specifier as well as a | |
24652 | rounding specifier, despite the fact that this is meaningless. | |
24653 | To be more compatible, we accept it as well, though of course it | |
24654 | does not set any bits. */ | |
21d799b5 NC |
24655 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
24656 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
24657 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
24658 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
24659 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
24660 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
24661 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
24662 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
24663 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
24664 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
24665 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
24666 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
24667 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 24668 | |
c19d1205 | 24669 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
24670 | #undef ARM_VARIANT |
24671 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
24672 | ||
21d799b5 NC |
24673 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
24674 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24675 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24676 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24677 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
24678 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 24679 | |
c921be7d NC |
24680 | #undef ARM_VARIANT |
24681 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
ba6cd17f SD |
24682 | #undef THUMB_VARIANT |
24683 | #define THUMB_VARIANT & arm_ext_v6t2 | |
24684 | mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs), | |
24685 | mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr), | |
24686 | #undef THUMB_VARIANT | |
c921be7d | 24687 | |
c19d1205 | 24688 | /* Moves and type conversions. */ |
21d799b5 NC |
24689 | cCE("fmstat", ef1fa10, 0, (), noargs), |
24690 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24691 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24692 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24693 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24694 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24695 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24696 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
24697 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
24698 | |
24699 | /* Memory operations. */ | |
21d799b5 NC |
24700 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
24701 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
24702 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
24703 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
24704 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24705 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24706 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24707 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24708 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
24709 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
24710 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
24711 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
24712 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24713 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
24714 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24715 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
24716 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
24717 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 24718 | |
c19d1205 | 24719 | /* Monadic operations. */ |
21d799b5 NC |
24720 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
24721 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
24722 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
24723 | |
24724 | /* Dyadic operations. */ | |
21d799b5 NC |
24725 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
24726 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24727 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24728 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24729 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24730 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24731 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24732 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
24733 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 24734 | |
c19d1205 | 24735 | /* Comparisons. */ |
21d799b5 NC |
24736 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
24737 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
24738 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
24739 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 24740 | |
62f3b8c8 PB |
24741 | /* Double precision load/store are still present on single precision |
24742 | implementations. */ | |
24743 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
24744 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
24745 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
24746 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
24747 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
24748 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
24749 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
24750 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
24751 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
24752 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 24753 | |
c921be7d NC |
24754 | #undef ARM_VARIANT |
24755 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
24756 | ||
c19d1205 | 24757 | /* Moves and type conversions. */ |
21d799b5 NC |
24758 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), |
24759 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24760 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
24761 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
24762 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
24763 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
24764 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
24765 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
24766 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24767 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24768 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
24769 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 24770 | |
c19d1205 | 24771 | /* Monadic operations. */ |
21d799b5 NC |
24772 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
24773 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
24774 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
24775 | |
24776 | /* Dyadic operations. */ | |
21d799b5 NC |
24777 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
24778 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24779 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24780 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24781 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24782 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24783 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24784 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
24785 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 24786 | |
c19d1205 | 24787 | /* Comparisons. */ |
21d799b5 NC |
24788 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
24789 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
24790 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
24791 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 24792 | |
037e8744 JB |
24793 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
24794 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
24795 | #undef ARM_VARIANT |
24796 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
24797 | #undef THUMB_VARIANT | |
24798 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
24799 | ||
037e8744 JB |
24800 | /* These mnemonics are unique to VFP. */ |
24801 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
24802 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
24803 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
24804 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
24805 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
037e8744 JB |
24806 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
24807 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
24808 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
24809 | ||
24810 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 | 24811 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), |
037e8744 | 24812 | |
55881a11 MGD |
24813 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
24814 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24815 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24816 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24817 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
24818 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
037e8744 | 24819 | |
dd9634d9 | 24820 | mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt), |
e3e535bc | 24821 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
dd9634d9 AV |
24822 | MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb), |
24823 | MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt), | |
f31fef98 | 24824 | |
037e8744 JB |
24825 | |
24826 | /* NOTE: All VMOV encoding is special-cased! */ | |
037e8744 JB |
24827 | NCE(vmovq, 0, 1, (VMOV), neon_mov), |
24828 | ||
32c36c3c AV |
24829 | #undef THUMB_VARIANT |
24830 | /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded | |
24831 | by different feature bits. Since we are setting the Thumb guard, we can | |
24832 | require Thumb-1 which makes it a nop guard and set the right feature bit in | |
24833 | do_vldr_vstr (). */ | |
24834 | #define THUMB_VARIANT & arm_ext_v4t | |
24835 | NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr), | |
24836 | NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr), | |
24837 | ||
9db2f6b4 RL |
24838 | #undef ARM_VARIANT |
24839 | #define ARM_VARIANT & arm_ext_fp16 | |
24840 | #undef THUMB_VARIANT | |
24841 | #define THUMB_VARIANT & arm_ext_fp16 | |
24842 | /* New instructions added from v8.2, allowing the extraction and insertion of | |
24843 | the upper 16 bits of a 32-bit vector register. */ | |
24844 | NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf), | |
24845 | NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf), | |
24846 | ||
dec41383 JW |
24847 | /* New backported fma/fms instructions optional in v8.2. */ |
24848 | NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal), | |
24849 | NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl), | |
24850 | ||
c921be7d NC |
24851 | #undef THUMB_VARIANT |
24852 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
24853 | #undef ARM_VARIANT | |
24854 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
24855 | ||
5287ad62 JB |
24856 | /* Data processing with three registers of the same length. */ |
24857 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
24858 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
24859 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
5287ad62 | 24860 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
5287ad62 | 24861 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
5287ad62 JB |
24862 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), |
24863 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
5287ad62 | 24864 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), |
5287ad62 | 24865 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), |
627907b7 | 24866 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), |
627907b7 | 24867 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), |
5287ad62 | 24868 | /* If not immediate, fall back to neon_dyadic_i64_su. |
5150f0d8 AV |
24869 | shl should accept I8 I16 I32 I64, |
24870 | qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
24871 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl), | |
24872 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl), | |
5287ad62 | 24873 | /* Logic ops, types optional & ignored. */ |
4316f0d2 | 24874 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24875 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24876 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24877 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), |
4316f0d2 | 24878 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), |
5287ad62 JB |
24879 | /* Bitfield ops, untyped. */ |
24880 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
24881 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
24882 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
24883 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
24884 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
24885 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
cc933301 | 24886 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */ |
21d799b5 | 24887 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
21d799b5 | 24888 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
21d799b5 | 24889 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), |
5287ad62 JB |
24890 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
24891 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
24892 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
24893 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
24894 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
24895 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
24896 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
24897 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
24898 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
24899 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 24900 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
24901 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
24902 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 24903 | /* As above, D registers only. */ |
21d799b5 NC |
24904 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
24905 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 24906 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
24907 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
24908 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
24909 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 24910 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
24911 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
24912 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
24913 | /* vtst takes sizes 8, 16, 32. */ |
24914 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
24915 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
24916 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 24917 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 24918 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 | 24919 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), |
21d799b5 | 24920 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), |
5287ad62 JB |
24921 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
24922 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
24923 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
24924 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
24925 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
24926 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
24927 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
24928 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
24929 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
24930 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
24931 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
24932 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
d6b4b13e | 24933 | /* ARM v8.1 extension. */ |
643afb90 MW |
24934 | nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), |
24935 | nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah), | |
24936 | nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah), | |
5287ad62 JB |
24937 | |
24938 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 24939 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
24940 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
24941 | ||
24942 | /* Data processing with two registers and a shift amount. */ | |
24943 | /* Right shifts, and variants with rounding. | |
24944 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
5287ad62 | 24945 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), |
5287ad62 JB |
24946 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), |
24947 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
24948 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
24949 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
24950 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
24951 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
5287ad62 | 24952 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), |
5287ad62 JB |
24953 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), |
24954 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
5287ad62 JB |
24955 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), |
24956 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
24957 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
24958 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
24959 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
24960 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
24961 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
24962 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
24963 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
24964 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
24965 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
24966 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 24967 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 24968 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 24969 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 24970 | |
4316f0d2 | 24971 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), |
5287ad62 JB |
24972 | |
24973 | /* Data processing, three registers of different lengths. */ | |
24974 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
24975 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
5287ad62 JB |
24976 | /* If not scalar, fall back to neon_dyadic_long. |
24977 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
24978 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
24979 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
24980 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
24981 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
24982 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
24983 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
24984 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24985 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24986 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24987 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
24988 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
24989 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
24990 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
24991 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
24992 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
24993 | S16 S32 U16 U32. */ | |
21d799b5 | 24994 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
24995 | |
24996 | /* Extract. Size 8. */ | |
3b8d421e PB |
24997 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
24998 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
24999 | |
25000 | /* Two registers, miscellaneous. */ | |
25001 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
5287ad62 | 25002 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), |
5287ad62 | 25003 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), |
5287ad62 JB |
25004 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), |
25005 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 | 25006 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), |
5287ad62 JB |
25007 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
25008 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
25009 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 25010 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 25011 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 25012 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 25013 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 25014 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
25015 | /* VZIP / VUZP. Sizes 8 16 32. */ |
25016 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
25017 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
25018 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
25019 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
25020 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
5287ad62 | 25021 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), |
5287ad62 JB |
25022 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), |
25023 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
25024 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
25025 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
25026 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
25027 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
cc933301 | 25028 | /* Reciprocal estimates. Types U32 F16 F32. */ |
5287ad62 JB |
25029 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), |
25030 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
25031 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
25032 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
25033 | /* VCLS. Types S8 S16 S32. */ | |
5287ad62 JB |
25034 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), |
25035 | /* VCLZ. Types I8 I16 I32. */ | |
5287ad62 JB |
25036 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), |
25037 | /* VCNT. Size 8. */ | |
25038 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
25039 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
25040 | /* Two address, untyped. */ | |
25041 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
25042 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
25043 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
25044 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
25045 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
25046 | |
25047 | /* Table lookup. Size 8. */ | |
25048 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
25049 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
25050 | ||
c921be7d NC |
25051 | #undef THUMB_VARIANT |
25052 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
25053 | #undef ARM_VARIANT | |
25054 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
25055 | ||
5287ad62 | 25056 | /* Neon element/structure load/store. */ |
21d799b5 NC |
25057 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
25058 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
25059 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
25060 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
25061 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
25062 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
25063 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
25064 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 25065 | |
c921be7d | 25066 | #undef THUMB_VARIANT |
74db7efb NC |
25067 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
25068 | #undef ARM_VARIANT | |
25069 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
25070 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
25071 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
25072 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
25073 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
25074 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
25075 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
25076 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
25077 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
25078 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
25079 | ||
74db7efb | 25080 | #undef THUMB_VARIANT |
c921be7d NC |
25081 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
25082 | #undef ARM_VARIANT | |
25083 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
25084 | ||
21d799b5 | 25085 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 25086 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 25087 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 25088 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 25089 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 25090 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 25091 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 25092 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 25093 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 25094 | |
74db7efb NC |
25095 | #undef ARM_VARIANT |
25096 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
25097 | #undef THUMB_VARIANT | |
25098 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
d58196e0 | 25099 | /* Mnemonics shared by Neon, VFP and MVE. These are included in the |
62f3b8c8 PB |
25100 | VFP FMA variant; NEON and VFP FMA always includes the NEON |
25101 | FMA instructions. */ | |
d58196e0 AV |
25102 | mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac), |
25103 | mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac), | |
25104 | ||
62f3b8c8 PB |
25105 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; |
25106 | the v form should always be used. */ | |
25107 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
25108 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
25109 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
25110 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
25111 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
25112 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
25113 | ||
5287ad62 | 25114 | #undef THUMB_VARIANT |
c921be7d NC |
25115 | #undef ARM_VARIANT |
25116 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
25117 | ||
21d799b5 NC |
25118 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
25119 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
25120 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
25121 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
25122 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
25123 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
25124 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
25125 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 25126 | |
c921be7d NC |
25127 | #undef ARM_VARIANT |
25128 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
25129 | ||
21d799b5 NC |
25130 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
25131 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
25132 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
25133 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
25134 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
25135 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
25136 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
25137 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
25138 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
25139 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
25140 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
25141 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
25142 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
25143 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
25144 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
25145 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
25146 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
25147 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
25148 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
25149 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
25150 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
25151 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
25152 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
25153 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
25154 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
25155 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
25156 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
25157 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
25158 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
25159 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
25160 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
25161 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
25162 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
25163 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
25164 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
25165 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
25166 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
25167 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25168 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25169 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25170 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25171 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25172 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25173 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25174 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25175 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25176 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
25177 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25178 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25179 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25180 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
25181 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25182 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25183 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25184 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25185 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25186 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25187 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25188 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25189 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
25190 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25191 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25192 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25193 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25194 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25195 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
25196 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
25197 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
25198 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
25199 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
25200 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25201 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25202 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25203 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25204 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25205 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25206 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25207 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25208 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25209 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25210 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25211 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25212 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25213 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25214 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25215 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25216 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25217 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25218 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
25219 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25220 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25221 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25222 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25223 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
25224 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
25225 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25226 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25227 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25228 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25229 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
25230 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
25231 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25232 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25233 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25234 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25235 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25236 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25237 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25238 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25239 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25240 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
25241 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25242 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25243 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25244 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25245 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25246 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25247 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25248 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25249 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25250 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25251 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25252 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25253 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25254 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25255 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25256 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25257 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
25258 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
25259 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
25260 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
25261 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
25262 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
25263 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25264 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25265 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25266 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25267 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25268 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25269 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25270 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25271 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25272 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
25273 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
25274 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
25275 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
25276 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
25277 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
25278 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25279 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25280 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25281 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
25282 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
25283 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
25284 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
25285 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
25286 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
25287 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25288 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25289 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25290 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25291 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 25292 | |
c921be7d NC |
25293 | #undef ARM_VARIANT |
25294 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
25295 | ||
21d799b5 NC |
25296 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
25297 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
25298 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
25299 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
25300 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
25301 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
25302 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25303 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25304 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25305 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25306 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25307 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25308 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25309 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25310 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25311 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25312 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25313 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25314 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25315 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25316 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
25317 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25318 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25319 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25320 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25321 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25322 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25323 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25324 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25325 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25326 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25327 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25328 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25329 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25330 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25331 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25332 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25333 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25334 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25335 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25336 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25337 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25338 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25339 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25340 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25341 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25342 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25343 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25344 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25345 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25346 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25347 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25348 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25349 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25350 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25351 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
25352 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 25353 | |
c921be7d NC |
25354 | #undef ARM_VARIANT |
25355 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
25356 | ||
21d799b5 NC |
25357 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
25358 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
25359 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
25360 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
25361 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
25362 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
25363 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
25364 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
25365 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
25366 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
25367 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
25368 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
25369 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
25370 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
25371 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
25372 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
25373 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
25374 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
25375 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
25376 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
25377 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
25378 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
25379 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
25380 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
25381 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
25382 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
25383 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
25384 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
25385 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
25386 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
25387 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
25388 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
25389 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
25390 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
25391 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
25392 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
25393 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
25394 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
25395 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
25396 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
25397 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
25398 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
25399 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
25400 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
25401 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
25402 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
25403 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
25404 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
25405 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
25406 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
25407 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
25408 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
25409 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
25410 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
25411 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
25412 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
25413 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
25414 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
25415 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
25416 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
25417 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
25418 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
25419 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
25420 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
25421 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25422 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
25423 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25424 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
25425 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25426 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
25427 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
25428 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
25429 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
25430 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
25431 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
25432 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
4ed7ed8d | 25433 | |
7fadb25d SD |
25434 | /* ARMv8.5-A instructions. */ |
25435 | #undef ARM_VARIANT | |
25436 | #define ARM_VARIANT & arm_ext_sb | |
25437 | #undef THUMB_VARIANT | |
25438 | #define THUMB_VARIANT & arm_ext_sb | |
25439 | TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs), | |
25440 | ||
dad0c3bf SD |
25441 | #undef ARM_VARIANT |
25442 | #define ARM_VARIANT & arm_ext_predres | |
25443 | #undef THUMB_VARIANT | |
25444 | #define THUMB_VARIANT & arm_ext_predres | |
25445 | CE("cfprctx", e070f93, 1, (RRnpc), rd), | |
25446 | CE("dvprctx", e070fb3, 1, (RRnpc), rd), | |
25447 | CE("cpprctx", e070ff3, 1, (RRnpc), rd), | |
25448 | ||
16a1fa25 | 25449 | /* ARMv8-M instructions. */ |
4ed7ed8d TP |
25450 | #undef ARM_VARIANT |
25451 | #define ARM_VARIANT NULL | |
25452 | #undef THUMB_VARIANT | |
25453 | #define THUMB_VARIANT & arm_ext_v8m | |
cf3cf39d TP |
25454 | ToU("sg", e97fe97f, 0, (), noargs), |
25455 | ToC("blxns", 4784, 1, (RRnpc), t_blx), | |
25456 | ToC("bxns", 4704, 1, (RRnpc), t_bx), | |
25457 | ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt), | |
25458 | ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt), | |
25459 | ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt), | |
25460 | ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt), | |
16a1fa25 TP |
25461 | |
25462 | /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the | |
25463 | instructions behave as nop if no VFP is present. */ | |
25464 | #undef THUMB_VARIANT | |
25465 | #define THUMB_VARIANT & arm_ext_v8m_main | |
cf3cf39d TP |
25466 | ToC("vlldm", ec300a00, 1, (RRnpc), rn), |
25467 | ToC("vlstm", ec200a00, 1, (RRnpc), rn), | |
4389b29a AV |
25468 | |
25469 | /* Armv8.1-M Mainline instructions. */ | |
25470 | #undef THUMB_VARIANT | |
25471 | #define THUMB_VARIANT & arm_ext_v8_1m_main | |
e39c1607 SD |
25472 | toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond), |
25473 | toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond), | |
25474 | toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond), | |
25475 | toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25476 | toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond), | |
25477 | toU("cset", _cset, 2, (RRnpcsp, COND), t_cond), | |
25478 | toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25479 | toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25480 | toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond), | |
25481 | ||
4389b29a | 25482 | toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future), |
f6b2b12d | 25483 | toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future), |
f1c7f421 | 25484 | toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future), |
65d1bc05 | 25485 | toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future), |
f1c7f421 | 25486 | toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future), |
60f993ce AV |
25487 | |
25488 | toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop), | |
25489 | toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop), | |
25490 | toU("le", _le, 2, (oLR, EXP), t_loloop), | |
4b5a202f | 25491 | |
efd6b359 | 25492 | ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm), |
5ee91343 AV |
25493 | ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm), |
25494 | ||
25495 | #undef THUMB_VARIANT | |
25496 | #define THUMB_VARIANT & mve_ext | |
23d00a41 SD |
25497 | ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift), |
25498 | ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25499 | ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift), | |
08132bdd SP |
25500 | ToC("uqrshll", ea51010d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1), |
25501 | ToC("sqrshrl", ea51012d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1), | |
23d00a41 SD |
25502 | ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift), |
25503 | ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25504 | ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25505 | ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift), | |
25506 | ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift), | |
25507 | ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift), | |
25508 | ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
25509 | ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
25510 | ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
25511 | ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift), | |
1b883319 AV |
25512 | |
25513 | ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25514 | ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25515 | ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25516 | ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25517 | ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25518 | ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25519 | ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25520 | ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25521 | ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25522 | ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25523 | ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25524 | ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25525 | ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25526 | ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25527 | ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt), | |
25528 | ||
5ee91343 AV |
25529 | ToC("vpst", fe710f4d, 0, (), mve_vpt), |
25530 | ToC("vpstt", fe318f4d, 0, (), mve_vpt), | |
25531 | ToC("vpste", fe718f4d, 0, (), mve_vpt), | |
25532 | ToC("vpsttt", fe314f4d, 0, (), mve_vpt), | |
25533 | ToC("vpstte", fe31cf4d, 0, (), mve_vpt), | |
25534 | ToC("vpstet", fe71cf4d, 0, (), mve_vpt), | |
25535 | ToC("vpstee", fe714f4d, 0, (), mve_vpt), | |
25536 | ToC("vpstttt", fe312f4d, 0, (), mve_vpt), | |
25537 | ToC("vpsttte", fe316f4d, 0, (), mve_vpt), | |
25538 | ToC("vpsttet", fe31ef4d, 0, (), mve_vpt), | |
25539 | ToC("vpsttee", fe31af4d, 0, (), mve_vpt), | |
25540 | ToC("vpstett", fe71af4d, 0, (), mve_vpt), | |
25541 | ToC("vpstete", fe71ef4d, 0, (), mve_vpt), | |
25542 | ToC("vpsteet", fe716f4d, 0, (), mve_vpt), | |
25543 | ToC("vpsteee", fe712f4d, 0, (), mve_vpt), | |
25544 | ||
a302e574 | 25545 | /* MVE and MVE FP only. */ |
7df54120 | 25546 | mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd), |
efd0b310 | 25547 | mCEF(vctp, _vctp, 1, (RRnpc), mve_vctp), |
c2dafc2a AV |
25548 | mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc), |
25549 | mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc), | |
25550 | mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), | |
25551 | mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), | |
886e1c73 | 25552 | mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull), |
a302e574 AV |
25553 | mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav), |
25554 | mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25555 | mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25556 | mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25557 | mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25558 | mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25559 | mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25560 | mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25561 | mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25562 | mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25563 | mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav), | |
25564 | ||
35c228db AV |
25565 | mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), |
25566 | mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), | |
25567 | mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25568 | mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25569 | mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25570 | mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25571 | mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), | |
25572 | mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld), | |
25573 | mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25574 | mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25575 | mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
25576 | mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld), | |
f5f10c66 AV |
25577 | mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr), |
25578 | mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25579 | mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25580 | mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25581 | mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25582 | mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25583 | mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
25584 | mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr), | |
35c228db | 25585 | |
57785aa2 AV |
25586 | mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn), |
25587 | mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn), | |
c2dafc2a | 25588 | mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr), |
26c1e780 AV |
25589 | mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv), |
25590 | mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv), | |
25591 | mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv), | |
25592 | mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv), | |
b409bdb6 AV |
25593 | mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup), |
25594 | mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), | |
25595 | mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup), | |
25596 | mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), | |
935295b5 AV |
25597 | mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), |
25598 | mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), | |
13ccd4c0 AV |
25599 | mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv), |
25600 | mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv), | |
25601 | mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv), | |
25602 | mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv), | |
57785aa2 | 25603 | |
93925576 AV |
25604 | mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), |
25605 | mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25606 | mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25607 | mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25608 | mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25609 | mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25610 | mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25611 | mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25612 | mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25613 | mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav), | |
25614 | mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25615 | mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25616 | mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25617 | mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25618 | mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25619 | mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25620 | mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25621 | mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25622 | mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25623 | mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), | |
25624 | ||
2d78f95b AV |
25625 | mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas), |
25626 | mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), | |
25627 | mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), | |
3063888e AV |
25628 | mToC("vpnot", fe310f4d, 0, (), mve_vpnot), |
25629 | mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel), | |
2d78f95b | 25630 | |
8b8b22a4 AV |
25631 | mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), |
25632 | mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25633 | mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25634 | mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25635 | mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25636 | mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25637 | mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
25638 | mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh), | |
42b16635 AV |
25639 | mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah), |
25640 | mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah), | |
25641 | mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah), | |
35d1cfc2 AV |
25642 | mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull), |
25643 | mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull), | |
1be7aba3 AV |
25644 | mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn), |
25645 | mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn), | |
25646 | mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn), | |
25647 | mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn), | |
8b8b22a4 | 25648 | |
4aa88b50 AV |
25649 | mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), |
25650 | mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25651 | mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25652 | mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25653 | mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25654 | mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25655 | mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25656 | mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25657 | mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25658 | mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25659 | mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25660 | mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), | |
25661 | ||
acca5630 AV |
25662 | mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc), |
25663 | mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll), | |
25664 | mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll), | |
25665 | ||
1f6234a3 AV |
25666 | toU("dlstp", _dlstp, 2, (LR, RR), t_loloop), |
25667 | toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop), | |
25668 | toU("letp", _letp, 2, (LR, EXP), t_loloop), | |
25669 | toU("lctp", _lctp, 0, (), t_loloop), | |
25670 | ||
5d281bf0 AV |
25671 | #undef THUMB_VARIANT |
25672 | #define THUMB_VARIANT & mve_fp_ext | |
25673 | mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), | |
f30ee27c | 25674 | mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas), |
935295b5 AV |
25675 | mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), |
25676 | mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), | |
8cd78170 AV |
25677 | mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv), |
25678 | mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv), | |
25679 | mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv), | |
25680 | mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv), | |
5d281bf0 | 25681 | |
5ee91343 | 25682 | #undef ARM_VARIANT |
57785aa2 | 25683 | #define ARM_VARIANT & fpu_vfp_ext_v1 |
5ee91343 AV |
25684 | #undef THUMB_VARIANT |
25685 | #define THUMB_VARIANT & arm_ext_v6t2 | |
a8465a06 AV |
25686 | mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar), |
25687 | mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul), | |
5ee91343 | 25688 | |
57785aa2 AV |
25689 | mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
25690 | ||
25691 | #undef ARM_VARIANT | |
25692 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
25693 | ||
25694 | MNCE(vmov, 0, 1, (VMOV), neon_mov), | |
25695 | mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
25696 | mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
25697 | mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), | |
25698 | ||
886e1c73 AV |
25699 | mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull), |
25700 | mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), | |
25701 | mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), | |
5ee91343 | 25702 | |
485dee97 AV |
25703 | MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), |
25704 | MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), | |
25705 | ||
57785aa2 AV |
25706 | mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl), |
25707 | mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl), | |
25708 | ||
1b883319 AV |
25709 | mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp), |
25710 | mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp), | |
25711 | ||
57785aa2 AV |
25712 | #undef ARM_VARIANT |
25713 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
25714 | ||
25715 | mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), | |
25716 | mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
25717 | mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
25718 | mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
25719 | ||
dd9634d9 AV |
25720 | #undef ARM_VARIANT |
25721 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd | |
25722 | mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta), | |
25723 | mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp), | |
25724 | mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn), | |
25725 | mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm), | |
935295b5 AV |
25726 | mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), |
25727 | mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), | |
dd9634d9 AV |
25728 | |
25729 | #undef ARM_VARIANT | |
5ee91343 | 25730 | #define ARM_VARIANT & fpu_neon_ext_v1 |
f601a00c | 25731 | mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
5ee91343 AV |
25732 | mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long), |
25733 | mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long), | |
25734 | mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long), | |
f601a00c AV |
25735 | mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), |
25736 | mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), | |
25737 | mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), | |
25738 | mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), | |
25739 | mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic), | |
f30ee27c AV |
25740 | MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls), |
25741 | MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz), | |
b409bdb6 | 25742 | mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup), |
7df54120 AV |
25743 | MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), |
25744 | MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su), | |
25745 | MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), | |
935295b5 AV |
25746 | mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |
25747 | mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), | |
a8465a06 AV |
25748 | MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), |
25749 | MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su), | |
1a186d29 AV |
25750 | mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn), |
25751 | MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg), | |
25752 | MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg), | |
42b16635 AV |
25753 | mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah), |
25754 | mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh), | |
25755 | mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh), | |
1be7aba3 AV |
25756 | MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl), |
25757 | MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl), | |
4401c241 AV |
25758 | MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm), |
25759 | MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm), | |
25760 | MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli), | |
25761 | MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri), | |
25762 | MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev), | |
25763 | MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev), | |
25764 | MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev), | |
5150f0d8 AV |
25765 | mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl), |
25766 | mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl), | |
25767 | MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm), | |
5d281bf0 AV |
25768 | |
25769 | #undef ARM_VARIANT | |
25770 | #define ARM_VARIANT & arm_ext_v8_3 | |
25771 | #undef THUMB_VARIANT | |
25772 | #define THUMB_VARIANT & arm_ext_v6t2_v8m | |
25773 | MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd), | |
25774 | MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla), | |
c19d1205 ZW |
25775 | }; |
25776 | #undef ARM_VARIANT | |
25777 | #undef THUMB_VARIANT | |
25778 | #undef TCE | |
c19d1205 ZW |
25779 | #undef TUE |
25780 | #undef TUF | |
25781 | #undef TCC | |
8f06b2d8 | 25782 | #undef cCE |
e3cb604e PB |
25783 | #undef cCL |
25784 | #undef C3E | |
4389b29a | 25785 | #undef C3 |
c19d1205 ZW |
25786 | #undef CE |
25787 | #undef CM | |
4389b29a | 25788 | #undef CL |
c19d1205 ZW |
25789 | #undef UE |
25790 | #undef UF | |
25791 | #undef UT | |
5287ad62 JB |
25792 | #undef NUF |
25793 | #undef nUF | |
25794 | #undef NCE | |
25795 | #undef nCE | |
c19d1205 ZW |
25796 | #undef OPS0 |
25797 | #undef OPS1 | |
25798 | #undef OPS2 | |
25799 | #undef OPS3 | |
25800 | #undef OPS4 | |
25801 | #undef OPS5 | |
25802 | #undef OPS6 | |
25803 | #undef do_0 | |
4389b29a AV |
25804 | #undef ToC |
25805 | #undef toC | |
25806 | #undef ToU | |
f6b2b12d | 25807 | #undef toU |
c19d1205 ZW |
25808 | \f |
25809 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 25810 | |
c19d1205 ZW |
25811 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
25812 | for use in the a.out file, and stores them in the array pointed to by buf. | |
25813 | This knows about the endian-ness of the target machine and does | |
25814 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
25815 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
25816 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 25817 | |
c19d1205 ZW |
25818 | void |
25819 | md_number_to_chars (char * buf, valueT val, int n) | |
25820 | { | |
25821 | if (target_big_endian) | |
25822 | number_to_chars_bigendian (buf, val, n); | |
25823 | else | |
25824 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
25825 | } |
25826 | ||
c19d1205 ZW |
25827 | static valueT |
25828 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 25829 | { |
c19d1205 ZW |
25830 | valueT result = 0; |
25831 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 25832 | |
c19d1205 | 25833 | if (target_big_endian) |
b99bd4ef | 25834 | { |
c19d1205 ZW |
25835 | while (n--) |
25836 | { | |
25837 | result <<= 8; | |
25838 | result |= (*where++ & 255); | |
25839 | } | |
b99bd4ef | 25840 | } |
c19d1205 | 25841 | else |
b99bd4ef | 25842 | { |
c19d1205 ZW |
25843 | while (n--) |
25844 | { | |
25845 | result <<= 8; | |
25846 | result |= (where[n] & 255); | |
25847 | } | |
bfae80f2 | 25848 | } |
b99bd4ef | 25849 | |
c19d1205 | 25850 | return result; |
bfae80f2 | 25851 | } |
b99bd4ef | 25852 | |
c19d1205 | 25853 | /* MD interface: Sections. */ |
b99bd4ef | 25854 | |
fa94de6b RM |
25855 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
25856 | that an rs_machine_dependent frag may reach. */ | |
25857 | ||
25858 | unsigned int | |
25859 | arm_frag_max_var (fragS *fragp) | |
25860 | { | |
25861 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
25862 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
25863 | ||
25864 | Note that we generate relaxable instructions even for cases that don't | |
25865 | really need it, like an immediate that's a trivial constant. So we're | |
25866 | overestimating the instruction size for some of those cases. Rather | |
25867 | than putting more intelligence here, it would probably be better to | |
25868 | avoid generating a relaxation frag in the first place when it can be | |
25869 | determined up front that a short instruction will suffice. */ | |
25870 | ||
25871 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
25872 | return INSN_SIZE; | |
25873 | } | |
25874 | ||
0110f2b8 PB |
25875 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
25876 | 2 bytes. */ | |
25877 | ||
c19d1205 | 25878 | int |
0110f2b8 | 25879 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
25880 | segT segtype ATTRIBUTE_UNUSED) |
25881 | { | |
0110f2b8 PB |
25882 | fragp->fr_var = 2; |
25883 | return 2; | |
25884 | } | |
25885 | ||
25886 | /* Convert a machine dependent frag. */ | |
25887 | ||
25888 | void | |
25889 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
25890 | { | |
25891 | unsigned long insn; | |
25892 | unsigned long old_op; | |
25893 | char *buf; | |
25894 | expressionS exp; | |
25895 | fixS *fixp; | |
25896 | int reloc_type; | |
25897 | int pc_rel; | |
25898 | int opcode; | |
25899 | ||
25900 | buf = fragp->fr_literal + fragp->fr_fix; | |
25901 | ||
25902 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
25903 | if (fragp->fr_symbol) |
25904 | { | |
0110f2b8 PB |
25905 | exp.X_op = O_symbol; |
25906 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
25907 | } |
25908 | else | |
25909 | { | |
0110f2b8 | 25910 | exp.X_op = O_constant; |
5f4273c7 | 25911 | } |
0110f2b8 PB |
25912 | exp.X_add_number = fragp->fr_offset; |
25913 | opcode = fragp->fr_subtype; | |
25914 | switch (opcode) | |
25915 | { | |
25916 | case T_MNEM_ldr_pc: | |
25917 | case T_MNEM_ldr_pc2: | |
25918 | case T_MNEM_ldr_sp: | |
25919 | case T_MNEM_str_sp: | |
25920 | case T_MNEM_ldr: | |
25921 | case T_MNEM_ldrb: | |
25922 | case T_MNEM_ldrh: | |
25923 | case T_MNEM_str: | |
25924 | case T_MNEM_strb: | |
25925 | case T_MNEM_strh: | |
25926 | if (fragp->fr_var == 4) | |
25927 | { | |
5f4273c7 | 25928 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
25929 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
25930 | { | |
25931 | insn |= (old_op & 0x700) << 4; | |
25932 | } | |
25933 | else | |
25934 | { | |
25935 | insn |= (old_op & 7) << 12; | |
25936 | insn |= (old_op & 0x38) << 13; | |
25937 | } | |
25938 | insn |= 0x00000c00; | |
25939 | put_thumb32_insn (buf, insn); | |
25940 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
25941 | } | |
25942 | else | |
25943 | { | |
25944 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
25945 | } | |
25946 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
25947 | break; | |
25948 | case T_MNEM_adr: | |
25949 | if (fragp->fr_var == 4) | |
25950 | { | |
25951 | insn = THUMB_OP32 (opcode); | |
25952 | insn |= (old_op & 0xf0) << 4; | |
25953 | put_thumb32_insn (buf, insn); | |
25954 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
25955 | } | |
25956 | else | |
25957 | { | |
25958 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
25959 | exp.X_add_number -= 4; | |
25960 | } | |
25961 | pc_rel = 1; | |
25962 | break; | |
25963 | case T_MNEM_mov: | |
25964 | case T_MNEM_movs: | |
25965 | case T_MNEM_cmp: | |
25966 | case T_MNEM_cmn: | |
25967 | if (fragp->fr_var == 4) | |
25968 | { | |
25969 | int r0off = (opcode == T_MNEM_mov | |
25970 | || opcode == T_MNEM_movs) ? 0 : 8; | |
25971 | insn = THUMB_OP32 (opcode); | |
25972 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
25973 | insn |= (old_op & 0x700) << r0off; | |
25974 | put_thumb32_insn (buf, insn); | |
25975 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
25976 | } | |
25977 | else | |
25978 | { | |
25979 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
25980 | } | |
25981 | pc_rel = 0; | |
25982 | break; | |
25983 | case T_MNEM_b: | |
25984 | if (fragp->fr_var == 4) | |
25985 | { | |
25986 | insn = THUMB_OP32(opcode); | |
25987 | put_thumb32_insn (buf, insn); | |
25988 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
25989 | } | |
25990 | else | |
25991 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
25992 | pc_rel = 1; | |
25993 | break; | |
25994 | case T_MNEM_bcond: | |
25995 | if (fragp->fr_var == 4) | |
25996 | { | |
25997 | insn = THUMB_OP32(opcode); | |
25998 | insn |= (old_op & 0xf00) << 14; | |
25999 | put_thumb32_insn (buf, insn); | |
26000 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
26001 | } | |
26002 | else | |
26003 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
26004 | pc_rel = 1; | |
26005 | break; | |
26006 | case T_MNEM_add_sp: | |
26007 | case T_MNEM_add_pc: | |
26008 | case T_MNEM_inc_sp: | |
26009 | case T_MNEM_dec_sp: | |
26010 | if (fragp->fr_var == 4) | |
26011 | { | |
26012 | /* ??? Choose between add and addw. */ | |
26013 | insn = THUMB_OP32 (opcode); | |
26014 | insn |= (old_op & 0xf0) << 4; | |
26015 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
26016 | if (opcode == T_MNEM_add_pc) |
26017 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
26018 | else | |
26019 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
26020 | } |
26021 | else | |
26022 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
26023 | pc_rel = 0; | |
26024 | break; | |
26025 | ||
26026 | case T_MNEM_addi: | |
26027 | case T_MNEM_addis: | |
26028 | case T_MNEM_subi: | |
26029 | case T_MNEM_subis: | |
26030 | if (fragp->fr_var == 4) | |
26031 | { | |
26032 | insn = THUMB_OP32 (opcode); | |
26033 | insn |= (old_op & 0xf0) << 4; | |
26034 | insn |= (old_op & 0xf) << 16; | |
26035 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
26036 | if (insn & (1 << 20)) |
26037 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
26038 | else | |
26039 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
26040 | } |
26041 | else | |
26042 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
26043 | pc_rel = 0; | |
26044 | break; | |
26045 | default: | |
5f4273c7 | 26046 | abort (); |
0110f2b8 PB |
26047 | } |
26048 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 26049 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
26050 | fixp->fx_file = fragp->fr_file; |
26051 | fixp->fx_line = fragp->fr_line; | |
26052 | fragp->fr_fix += fragp->fr_var; | |
3cfdb781 TG |
26053 | |
26054 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ | |
26055 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () | |
26056 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) | |
26057 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); | |
0110f2b8 PB |
26058 | } |
26059 | ||
26060 | /* Return the size of a relaxable immediate operand instruction. | |
26061 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
26062 | static int | |
26063 | relax_immediate (fragS *fragp, int size, int shift) | |
26064 | { | |
26065 | offsetT offset; | |
26066 | offsetT mask; | |
26067 | offsetT low; | |
26068 | ||
26069 | /* ??? Should be able to do better than this. */ | |
26070 | if (fragp->fr_symbol) | |
26071 | return 4; | |
26072 | ||
26073 | low = (1 << shift) - 1; | |
26074 | mask = (1 << (shift + size)) - (1 << shift); | |
26075 | offset = fragp->fr_offset; | |
26076 | /* Force misaligned offsets to 32-bit variant. */ | |
26077 | if (offset & low) | |
5e77afaa | 26078 | return 4; |
0110f2b8 PB |
26079 | if (offset & ~mask) |
26080 | return 4; | |
26081 | return 2; | |
26082 | } | |
26083 | ||
5e77afaa PB |
26084 | /* Get the address of a symbol during relaxation. */ |
26085 | static addressT | |
5f4273c7 | 26086 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
26087 | { |
26088 | fragS *sym_frag; | |
26089 | addressT addr; | |
26090 | symbolS *sym; | |
26091 | ||
26092 | sym = fragp->fr_symbol; | |
26093 | sym_frag = symbol_get_frag (sym); | |
26094 | know (S_GET_SEGMENT (sym) != absolute_section | |
26095 | || sym_frag == &zero_address_frag); | |
26096 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
26097 | ||
26098 | /* If frag has yet to be reached on this pass, assume it will | |
26099 | move by STRETCH just as we did. If this is not so, it will | |
26100 | be because some frag between grows, and that will force | |
26101 | another pass. */ | |
26102 | ||
26103 | if (stretch != 0 | |
26104 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
26105 | { |
26106 | fragS *f; | |
26107 | ||
26108 | /* Adjust stretch for any alignment frag. Note that if have | |
26109 | been expanding the earlier code, the symbol may be | |
26110 | defined in what appears to be an earlier frag. FIXME: | |
26111 | This doesn't handle the fr_subtype field, which specifies | |
26112 | a maximum number of bytes to skip when doing an | |
26113 | alignment. */ | |
26114 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
26115 | { | |
26116 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
26117 | { | |
26118 | if (stretch < 0) | |
26119 | stretch = - ((- stretch) | |
26120 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
26121 | else | |
26122 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
26123 | if (stretch == 0) | |
26124 | break; | |
26125 | } | |
26126 | } | |
26127 | if (f != NULL) | |
26128 | addr += stretch; | |
26129 | } | |
5e77afaa PB |
26130 | |
26131 | return addr; | |
26132 | } | |
26133 | ||
0110f2b8 PB |
26134 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
26135 | load. */ | |
26136 | static int | |
5e77afaa | 26137 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
26138 | { |
26139 | addressT addr; | |
26140 | offsetT val; | |
26141 | ||
26142 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
26143 | if (fragp->fr_symbol == NULL |
26144 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
26145 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
26146 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
26147 | return 4; |
26148 | ||
5f4273c7 | 26149 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
26150 | addr = fragp->fr_address + fragp->fr_fix; |
26151 | addr = (addr + 4) & ~3; | |
5e77afaa | 26152 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 26153 | if (val & 3) |
5e77afaa | 26154 | return 4; |
0110f2b8 PB |
26155 | val -= addr; |
26156 | if (val < 0 || val > 1020) | |
26157 | return 4; | |
26158 | return 2; | |
26159 | } | |
26160 | ||
26161 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
26162 | static int | |
26163 | relax_addsub (fragS *fragp, asection *sec) | |
26164 | { | |
26165 | char *buf; | |
26166 | int op; | |
26167 | ||
26168 | buf = fragp->fr_literal + fragp->fr_fix; | |
26169 | op = bfd_get_16(sec->owner, buf); | |
26170 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
26171 | return relax_immediate (fragp, 8, 0); | |
26172 | else | |
26173 | return relax_immediate (fragp, 3, 0); | |
26174 | } | |
26175 | ||
e83a675f RE |
26176 | /* Return TRUE iff the definition of symbol S could be pre-empted |
26177 | (overridden) at link or load time. */ | |
26178 | static bfd_boolean | |
26179 | symbol_preemptible (symbolS *s) | |
26180 | { | |
26181 | /* Weak symbols can always be pre-empted. */ | |
26182 | if (S_IS_WEAK (s)) | |
26183 | return TRUE; | |
26184 | ||
26185 | /* Non-global symbols cannot be pre-empted. */ | |
26186 | if (! S_IS_EXTERNAL (s)) | |
26187 | return FALSE; | |
26188 | ||
26189 | #ifdef OBJ_ELF | |
26190 | /* In ELF, a global symbol can be marked protected, or private. In that | |
26191 | case it can't be pre-empted (other definitions in the same link unit | |
26192 | would violate the ODR). */ | |
26193 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
26194 | return FALSE; | |
26195 | #endif | |
26196 | ||
26197 | /* Other global symbols might be pre-empted. */ | |
26198 | return TRUE; | |
26199 | } | |
0110f2b8 PB |
26200 | |
26201 | /* Return the size of a relaxable branch instruction. BITS is the | |
26202 | size of the offset field in the narrow instruction. */ | |
26203 | ||
26204 | static int | |
5e77afaa | 26205 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
26206 | { |
26207 | addressT addr; | |
26208 | offsetT val; | |
26209 | offsetT limit; | |
26210 | ||
26211 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 26212 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
26213 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
26214 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
26215 | return 4; |
26216 | ||
267bf995 | 26217 | #ifdef OBJ_ELF |
e83a675f | 26218 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
26219 | if (S_IS_DEFINED (fragp->fr_symbol) |
26220 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
26221 | return 4; | |
e83a675f | 26222 | #endif |
0d9b4b55 | 26223 | |
e83a675f | 26224 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 26225 | return 4; |
267bf995 | 26226 | |
5f4273c7 | 26227 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
26228 | addr = fragp->fr_address + fragp->fr_fix + 4; |
26229 | val -= addr; | |
26230 | ||
26231 | /* Offset is a signed value *2 */ | |
26232 | limit = 1 << bits; | |
26233 | if (val >= limit || val < -limit) | |
26234 | return 4; | |
26235 | return 2; | |
26236 | } | |
26237 | ||
26238 | ||
26239 | /* Relax a machine dependent frag. This returns the amount by which | |
26240 | the current size of the frag should change. */ | |
26241 | ||
26242 | int | |
5e77afaa | 26243 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
26244 | { |
26245 | int oldsize; | |
26246 | int newsize; | |
26247 | ||
26248 | oldsize = fragp->fr_var; | |
26249 | switch (fragp->fr_subtype) | |
26250 | { | |
26251 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 26252 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
26253 | break; |
26254 | case T_MNEM_ldr_pc: | |
26255 | case T_MNEM_ldr_sp: | |
26256 | case T_MNEM_str_sp: | |
5f4273c7 | 26257 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
26258 | break; |
26259 | case T_MNEM_ldr: | |
26260 | case T_MNEM_str: | |
5f4273c7 | 26261 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
26262 | break; |
26263 | case T_MNEM_ldrh: | |
26264 | case T_MNEM_strh: | |
5f4273c7 | 26265 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
26266 | break; |
26267 | case T_MNEM_ldrb: | |
26268 | case T_MNEM_strb: | |
5f4273c7 | 26269 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
26270 | break; |
26271 | case T_MNEM_adr: | |
5f4273c7 | 26272 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
26273 | break; |
26274 | case T_MNEM_mov: | |
26275 | case T_MNEM_movs: | |
26276 | case T_MNEM_cmp: | |
26277 | case T_MNEM_cmn: | |
5f4273c7 | 26278 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
26279 | break; |
26280 | case T_MNEM_b: | |
5f4273c7 | 26281 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
26282 | break; |
26283 | case T_MNEM_bcond: | |
5f4273c7 | 26284 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
26285 | break; |
26286 | case T_MNEM_add_sp: | |
26287 | case T_MNEM_add_pc: | |
26288 | newsize = relax_immediate (fragp, 8, 2); | |
26289 | break; | |
26290 | case T_MNEM_inc_sp: | |
26291 | case T_MNEM_dec_sp: | |
26292 | newsize = relax_immediate (fragp, 7, 2); | |
26293 | break; | |
26294 | case T_MNEM_addi: | |
26295 | case T_MNEM_addis: | |
26296 | case T_MNEM_subi: | |
26297 | case T_MNEM_subis: | |
26298 | newsize = relax_addsub (fragp, sec); | |
26299 | break; | |
26300 | default: | |
5f4273c7 | 26301 | abort (); |
0110f2b8 | 26302 | } |
5e77afaa PB |
26303 | |
26304 | fragp->fr_var = newsize; | |
26305 | /* Freeze wide instructions that are at or before the same location as | |
26306 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
26307 | Don't freeze them unconditionally because targets may be artificially |
26308 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 26309 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 26310 | { |
0110f2b8 | 26311 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 26312 | frag_wane (fragp); |
0110f2b8 | 26313 | } |
5e77afaa | 26314 | |
0110f2b8 | 26315 | return newsize - oldsize; |
c19d1205 | 26316 | } |
b99bd4ef | 26317 | |
c19d1205 | 26318 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 26319 | |
c19d1205 ZW |
26320 | valueT |
26321 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
26322 | valueT size) | |
26323 | { | |
6844c0cc | 26324 | return size; |
bfae80f2 | 26325 | } |
b99bd4ef | 26326 | |
c19d1205 ZW |
26327 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
26328 | of an rs_align_code fragment. */ | |
26329 | ||
26330 | void | |
26331 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 26332 | { |
d9235011 | 26333 | static unsigned char const arm_noop[2][2][4] = |
e7495e45 NS |
26334 | { |
26335 | { /* ARMv1 */ | |
26336 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
26337 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
26338 | }, | |
26339 | { /* ARMv6k */ | |
26340 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
26341 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
26342 | }, | |
26343 | }; | |
d9235011 | 26344 | static unsigned char const thumb_noop[2][2][2] = |
e7495e45 NS |
26345 | { |
26346 | { /* Thumb-1 */ | |
26347 | {0xc0, 0x46}, /* LE */ | |
26348 | {0x46, 0xc0}, /* BE */ | |
26349 | }, | |
26350 | { /* Thumb-2 */ | |
26351 | {0x00, 0xbf}, /* LE */ | |
26352 | {0xbf, 0x00} /* BE */ | |
26353 | } | |
26354 | }; | |
d9235011 | 26355 | static unsigned char const wide_thumb_noop[2][4] = |
e7495e45 NS |
26356 | { /* Wide Thumb-2 */ |
26357 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
26358 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
26359 | }; | |
c921be7d | 26360 | |
e7495e45 | 26361 | unsigned bytes, fix, noop_size; |
c19d1205 | 26362 | char * p; |
d9235011 TS |
26363 | const unsigned char * noop; |
26364 | const unsigned char *narrow_noop = NULL; | |
cd000bff DJ |
26365 | #ifdef OBJ_ELF |
26366 | enum mstate state; | |
26367 | #endif | |
bfae80f2 | 26368 | |
c19d1205 | 26369 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
26370 | return; |
26371 | ||
c19d1205 ZW |
26372 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
26373 | p = fragP->fr_literal + fragP->fr_fix; | |
26374 | fix = 0; | |
bfae80f2 | 26375 | |
c19d1205 ZW |
26376 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
26377 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 26378 | |
cd000bff | 26379 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 26380 | |
cd000bff | 26381 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 26382 | { |
7f78eb34 JW |
26383 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
26384 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
26385 | { |
26386 | narrow_noop = thumb_noop[1][target_big_endian]; | |
26387 | noop = wide_thumb_noop[target_big_endian]; | |
26388 | } | |
c19d1205 | 26389 | else |
e7495e45 NS |
26390 | noop = thumb_noop[0][target_big_endian]; |
26391 | noop_size = 2; | |
cd000bff DJ |
26392 | #ifdef OBJ_ELF |
26393 | state = MAP_THUMB; | |
26394 | #endif | |
7ed4c4c5 NC |
26395 | } |
26396 | else | |
26397 | { | |
7f78eb34 JW |
26398 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
26399 | ? selected_cpu : arm_arch_none, | |
26400 | arm_ext_v6k) != 0] | |
e7495e45 NS |
26401 | [target_big_endian]; |
26402 | noop_size = 4; | |
cd000bff DJ |
26403 | #ifdef OBJ_ELF |
26404 | state = MAP_ARM; | |
26405 | #endif | |
7ed4c4c5 | 26406 | } |
c921be7d | 26407 | |
e7495e45 | 26408 | fragP->fr_var = noop_size; |
c921be7d | 26409 | |
c19d1205 | 26410 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 26411 | { |
c19d1205 | 26412 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
26413 | #ifdef OBJ_ELF |
26414 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
26415 | #endif | |
c19d1205 ZW |
26416 | memset (p, 0, fix); |
26417 | p += fix; | |
26418 | bytes -= fix; | |
a737bd4d | 26419 | } |
a737bd4d | 26420 | |
e7495e45 NS |
26421 | if (narrow_noop) |
26422 | { | |
26423 | if (bytes & noop_size) | |
26424 | { | |
26425 | /* Insert a narrow noop. */ | |
26426 | memcpy (p, narrow_noop, noop_size); | |
26427 | p += noop_size; | |
26428 | bytes -= noop_size; | |
26429 | fix += noop_size; | |
26430 | } | |
26431 | ||
26432 | /* Use wide noops for the remainder */ | |
26433 | noop_size = 4; | |
26434 | } | |
26435 | ||
c19d1205 | 26436 | while (bytes >= noop_size) |
a737bd4d | 26437 | { |
c19d1205 ZW |
26438 | memcpy (p, noop, noop_size); |
26439 | p += noop_size; | |
26440 | bytes -= noop_size; | |
26441 | fix += noop_size; | |
a737bd4d NC |
26442 | } |
26443 | ||
c19d1205 | 26444 | fragP->fr_fix += fix; |
a737bd4d NC |
26445 | } |
26446 | ||
c19d1205 ZW |
26447 | /* Called from md_do_align. Used to create an alignment |
26448 | frag in a code section. */ | |
26449 | ||
26450 | void | |
26451 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 26452 | { |
c19d1205 | 26453 | char * p; |
7ed4c4c5 | 26454 | |
c19d1205 | 26455 | /* We assume that there will never be a requirement |
6ec8e702 | 26456 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 26457 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
26458 | { |
26459 | char err_msg[128]; | |
26460 | ||
fa94de6b | 26461 | sprintf (err_msg, |
477330fc RM |
26462 | _("alignments greater than %d bytes not supported in .text sections."), |
26463 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 26464 | as_fatal ("%s", err_msg); |
6ec8e702 | 26465 | } |
bfae80f2 | 26466 | |
c19d1205 ZW |
26467 | p = frag_var (rs_align_code, |
26468 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
26469 | 1, | |
26470 | (relax_substateT) max, | |
26471 | (symbolS *) NULL, | |
26472 | (offsetT) n, | |
26473 | (char *) NULL); | |
26474 | *p = 0; | |
26475 | } | |
bfae80f2 | 26476 | |
8dc2430f NC |
26477 | /* Perform target specific initialisation of a frag. |
26478 | Note - despite the name this initialisation is not done when the frag | |
26479 | is created, but only when its type is assigned. A frag can be created | |
26480 | and used a long time before its type is set, so beware of assuming that | |
33eaf5de | 26481 | this initialisation is performed first. */ |
bfae80f2 | 26482 | |
cd000bff DJ |
26483 | #ifndef OBJ_ELF |
26484 | void | |
26485 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
26486 | { | |
26487 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 26488 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
26489 | } |
26490 | ||
26491 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 26492 | void |
cd000bff | 26493 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 26494 | { |
e8d84ca1 | 26495 | bfd_boolean frag_thumb_mode; |
b968d18a | 26496 | |
8dc2430f NC |
26497 | /* If the current ARM vs THUMB mode has not already |
26498 | been recorded into this frag then do so now. */ | |
cd000bff | 26499 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
b968d18a JW |
26500 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
26501 | ||
e8d84ca1 NC |
26502 | /* PR 21809: Do not set a mapping state for debug sections |
26503 | - it just confuses other tools. */ | |
fd361982 | 26504 | if (bfd_section_flags (now_seg) & SEC_DEBUGGING) |
e8d84ca1 NC |
26505 | return; |
26506 | ||
b968d18a | 26507 | frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED; |
cd000bff | 26508 | |
f9c1b181 RL |
26509 | /* Record a mapping symbol for alignment frags. We will delete this |
26510 | later if the alignment ends up empty. */ | |
26511 | switch (fragP->fr_type) | |
26512 | { | |
26513 | case rs_align: | |
26514 | case rs_align_test: | |
26515 | case rs_fill: | |
26516 | mapping_state_2 (MAP_DATA, max_chars); | |
26517 | break; | |
26518 | case rs_align_code: | |
b968d18a | 26519 | mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); |
f9c1b181 RL |
26520 | break; |
26521 | default: | |
26522 | break; | |
cd000bff | 26523 | } |
bfae80f2 RE |
26524 | } |
26525 | ||
c19d1205 ZW |
26526 | /* When we change sections we need to issue a new mapping symbol. */ |
26527 | ||
26528 | void | |
26529 | arm_elf_change_section (void) | |
bfae80f2 | 26530 | { |
c19d1205 ZW |
26531 | /* Link an unlinked unwind index table section to the .text section. */ |
26532 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
26533 | && elf_linked_to_section (now_seg) == NULL) | |
26534 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
26535 | } |
26536 | ||
c19d1205 ZW |
26537 | int |
26538 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 26539 | { |
c19d1205 ZW |
26540 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
26541 | return SHT_ARM_EXIDX; | |
e45d0630 | 26542 | |
c19d1205 ZW |
26543 | return -1; |
26544 | } | |
26545 | \f | |
26546 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 26547 | |
c19d1205 | 26548 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 26549 | |
5f4273c7 | 26550 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 26551 | |
bfae80f2 | 26552 | static void |
c19d1205 | 26553 | flush_pending_unwind (void) |
bfae80f2 | 26554 | { |
c19d1205 | 26555 | offsetT offset; |
bfae80f2 | 26556 | |
c19d1205 ZW |
26557 | offset = unwind.pending_offset; |
26558 | unwind.pending_offset = 0; | |
26559 | if (offset != 0) | |
26560 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
26561 | } |
26562 | ||
c19d1205 ZW |
26563 | /* Add an opcode to this list for this function. Two-byte opcodes should |
26564 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
26565 | order. */ | |
26566 | ||
bfae80f2 | 26567 | static void |
c19d1205 | 26568 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 26569 | { |
c19d1205 ZW |
26570 | /* Add any deferred stack adjustment. */ |
26571 | if (unwind.pending_offset) | |
26572 | flush_pending_unwind (); | |
bfae80f2 | 26573 | |
c19d1205 | 26574 | unwind.sp_restored = 0; |
bfae80f2 | 26575 | |
c19d1205 | 26576 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 26577 | { |
c19d1205 ZW |
26578 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
26579 | if (unwind.opcodes) | |
325801bd TS |
26580 | unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes, |
26581 | unwind.opcode_alloc); | |
c19d1205 | 26582 | else |
325801bd | 26583 | unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc); |
bfae80f2 | 26584 | } |
c19d1205 | 26585 | while (length > 0) |
bfae80f2 | 26586 | { |
c19d1205 ZW |
26587 | length--; |
26588 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
26589 | op >>= 8; | |
26590 | unwind.opcode_count++; | |
bfae80f2 | 26591 | } |
bfae80f2 RE |
26592 | } |
26593 | ||
c19d1205 ZW |
26594 | /* Add unwind opcodes to adjust the stack pointer. */ |
26595 | ||
bfae80f2 | 26596 | static void |
c19d1205 | 26597 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 26598 | { |
c19d1205 | 26599 | valueT op; |
bfae80f2 | 26600 | |
c19d1205 | 26601 | if (offset > 0x200) |
bfae80f2 | 26602 | { |
c19d1205 ZW |
26603 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
26604 | char bytes[5]; | |
26605 | int n; | |
26606 | valueT o; | |
bfae80f2 | 26607 | |
c19d1205 ZW |
26608 | /* Long form: 0xb2, uleb128. */ |
26609 | /* This might not fit in a word so add the individual bytes, | |
26610 | remembering the list is built in reverse order. */ | |
26611 | o = (valueT) ((offset - 0x204) >> 2); | |
26612 | if (o == 0) | |
26613 | add_unwind_opcode (0, 1); | |
bfae80f2 | 26614 | |
c19d1205 ZW |
26615 | /* Calculate the uleb128 encoding of the offset. */ |
26616 | n = 0; | |
26617 | while (o) | |
26618 | { | |
26619 | bytes[n] = o & 0x7f; | |
26620 | o >>= 7; | |
26621 | if (o) | |
26622 | bytes[n] |= 0x80; | |
26623 | n++; | |
26624 | } | |
26625 | /* Add the insn. */ | |
26626 | for (; n; n--) | |
26627 | add_unwind_opcode (bytes[n - 1], 1); | |
26628 | add_unwind_opcode (0xb2, 1); | |
26629 | } | |
26630 | else if (offset > 0x100) | |
bfae80f2 | 26631 | { |
c19d1205 ZW |
26632 | /* Two short opcodes. */ |
26633 | add_unwind_opcode (0x3f, 1); | |
26634 | op = (offset - 0x104) >> 2; | |
26635 | add_unwind_opcode (op, 1); | |
bfae80f2 | 26636 | } |
c19d1205 ZW |
26637 | else if (offset > 0) |
26638 | { | |
26639 | /* Short opcode. */ | |
26640 | op = (offset - 4) >> 2; | |
26641 | add_unwind_opcode (op, 1); | |
26642 | } | |
26643 | else if (offset < 0) | |
bfae80f2 | 26644 | { |
c19d1205 ZW |
26645 | offset = -offset; |
26646 | while (offset > 0x100) | |
bfae80f2 | 26647 | { |
c19d1205 ZW |
26648 | add_unwind_opcode (0x7f, 1); |
26649 | offset -= 0x100; | |
bfae80f2 | 26650 | } |
c19d1205 ZW |
26651 | op = ((offset - 4) >> 2) | 0x40; |
26652 | add_unwind_opcode (op, 1); | |
bfae80f2 | 26653 | } |
bfae80f2 RE |
26654 | } |
26655 | ||
c19d1205 | 26656 | /* Finish the list of unwind opcodes for this function. */ |
0198d5e6 | 26657 | |
c19d1205 ZW |
26658 | static void |
26659 | finish_unwind_opcodes (void) | |
bfae80f2 | 26660 | { |
c19d1205 | 26661 | valueT op; |
bfae80f2 | 26662 | |
c19d1205 | 26663 | if (unwind.fp_used) |
bfae80f2 | 26664 | { |
708587a4 | 26665 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
26666 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
26667 | flush_pending_unwind (); | |
bfae80f2 | 26668 | |
c19d1205 ZW |
26669 | /* After restoring sp from the frame pointer. */ |
26670 | op = 0x90 | unwind.fp_reg; | |
26671 | add_unwind_opcode (op, 1); | |
26672 | } | |
26673 | else | |
26674 | flush_pending_unwind (); | |
bfae80f2 RE |
26675 | } |
26676 | ||
bfae80f2 | 26677 | |
c19d1205 ZW |
26678 | /* Start an exception table entry. If idx is nonzero this is an index table |
26679 | entry. */ | |
bfae80f2 RE |
26680 | |
26681 | static void | |
c19d1205 | 26682 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 26683 | { |
c19d1205 ZW |
26684 | const char * text_name; |
26685 | const char * prefix; | |
26686 | const char * prefix_once; | |
26687 | const char * group_name; | |
c19d1205 | 26688 | char * sec_name; |
c19d1205 ZW |
26689 | int type; |
26690 | int flags; | |
26691 | int linkonce; | |
bfae80f2 | 26692 | |
c19d1205 | 26693 | if (idx) |
bfae80f2 | 26694 | { |
c19d1205 ZW |
26695 | prefix = ELF_STRING_ARM_unwind; |
26696 | prefix_once = ELF_STRING_ARM_unwind_once; | |
26697 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 26698 | } |
c19d1205 | 26699 | else |
bfae80f2 | 26700 | { |
c19d1205 ZW |
26701 | prefix = ELF_STRING_ARM_unwind_info; |
26702 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
26703 | type = SHT_PROGBITS; | |
bfae80f2 RE |
26704 | } |
26705 | ||
c19d1205 ZW |
26706 | text_name = segment_name (text_seg); |
26707 | if (streq (text_name, ".text")) | |
26708 | text_name = ""; | |
26709 | ||
26710 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
26711 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 26712 | { |
c19d1205 ZW |
26713 | prefix = prefix_once; |
26714 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
26715 | } |
26716 | ||
29a2809e | 26717 | sec_name = concat (prefix, text_name, (char *) NULL); |
bfae80f2 | 26718 | |
c19d1205 ZW |
26719 | flags = SHF_ALLOC; |
26720 | linkonce = 0; | |
26721 | group_name = 0; | |
bfae80f2 | 26722 | |
c19d1205 ZW |
26723 | /* Handle COMDAT group. */ |
26724 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 26725 | { |
c19d1205 ZW |
26726 | group_name = elf_group_name (text_seg); |
26727 | if (group_name == NULL) | |
26728 | { | |
bd3ba5d1 | 26729 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
26730 | segment_name (text_seg)); |
26731 | ignore_rest_of_line (); | |
26732 | return; | |
26733 | } | |
26734 | flags |= SHF_GROUP; | |
26735 | linkonce = 1; | |
bfae80f2 RE |
26736 | } |
26737 | ||
a91e1603 L |
26738 | obj_elf_change_section (sec_name, type, 0, flags, 0, group_name, |
26739 | linkonce, 0); | |
bfae80f2 | 26740 | |
5f4273c7 | 26741 | /* Set the section link for index tables. */ |
c19d1205 ZW |
26742 | if (idx) |
26743 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
26744 | } |
26745 | ||
bfae80f2 | 26746 | |
c19d1205 ZW |
26747 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
26748 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 26749 | an inline entry. */ |
c19d1205 ZW |
26750 | |
26751 | static valueT | |
26752 | create_unwind_entry (int have_data) | |
bfae80f2 | 26753 | { |
c19d1205 ZW |
26754 | int size; |
26755 | addressT where; | |
26756 | char *ptr; | |
26757 | /* The current word of data. */ | |
26758 | valueT data; | |
26759 | /* The number of bytes left in this word. */ | |
26760 | int n; | |
bfae80f2 | 26761 | |
c19d1205 | 26762 | finish_unwind_opcodes (); |
bfae80f2 | 26763 | |
c19d1205 ZW |
26764 | /* Remember the current text section. */ |
26765 | unwind.saved_seg = now_seg; | |
26766 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 26767 | |
c19d1205 | 26768 | start_unwind_section (now_seg, 0); |
bfae80f2 | 26769 | |
c19d1205 | 26770 | if (unwind.personality_routine == NULL) |
bfae80f2 | 26771 | { |
c19d1205 ZW |
26772 | if (unwind.personality_index == -2) |
26773 | { | |
26774 | if (have_data) | |
5f4273c7 | 26775 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
26776 | return 1; /* EXIDX_CANTUNWIND. */ |
26777 | } | |
bfae80f2 | 26778 | |
c19d1205 ZW |
26779 | /* Use a default personality routine if none is specified. */ |
26780 | if (unwind.personality_index == -1) | |
26781 | { | |
26782 | if (unwind.opcode_count > 3) | |
26783 | unwind.personality_index = 1; | |
26784 | else | |
26785 | unwind.personality_index = 0; | |
26786 | } | |
bfae80f2 | 26787 | |
c19d1205 ZW |
26788 | /* Space for the personality routine entry. */ |
26789 | if (unwind.personality_index == 0) | |
26790 | { | |
26791 | if (unwind.opcode_count > 3) | |
26792 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 26793 | |
c19d1205 ZW |
26794 | if (!have_data) |
26795 | { | |
26796 | /* All the data is inline in the index table. */ | |
26797 | data = 0x80; | |
26798 | n = 3; | |
26799 | while (unwind.opcode_count > 0) | |
26800 | { | |
26801 | unwind.opcode_count--; | |
26802 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
26803 | n--; | |
26804 | } | |
bfae80f2 | 26805 | |
c19d1205 ZW |
26806 | /* Pad with "finish" opcodes. */ |
26807 | while (n--) | |
26808 | data = (data << 8) | 0xb0; | |
bfae80f2 | 26809 | |
c19d1205 ZW |
26810 | return data; |
26811 | } | |
26812 | size = 0; | |
26813 | } | |
26814 | else | |
26815 | /* We get two opcodes "free" in the first word. */ | |
26816 | size = unwind.opcode_count - 2; | |
26817 | } | |
26818 | else | |
5011093d | 26819 | { |
cad0da33 NC |
26820 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
26821 | if (unwind.personality_index != -1) | |
26822 | { | |
26823 | as_bad (_("attempt to recreate an unwind entry")); | |
26824 | return 1; | |
26825 | } | |
5011093d NC |
26826 | |
26827 | /* An extra byte is required for the opcode count. */ | |
26828 | size = unwind.opcode_count + 1; | |
26829 | } | |
bfae80f2 | 26830 | |
c19d1205 ZW |
26831 | size = (size + 3) >> 2; |
26832 | if (size > 0xff) | |
26833 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 26834 | |
c19d1205 ZW |
26835 | frag_align (2, 0, 0); |
26836 | record_alignment (now_seg, 2); | |
26837 | unwind.table_entry = expr_build_dot (); | |
26838 | ||
26839 | /* Allocate the table entry. */ | |
26840 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
26841 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
26842 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 26843 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 26844 | |
c19d1205 | 26845 | switch (unwind.personality_index) |
bfae80f2 | 26846 | { |
c19d1205 ZW |
26847 | case -1: |
26848 | /* ??? Should this be a PLT generating relocation? */ | |
26849 | /* Custom personality routine. */ | |
26850 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
26851 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 26852 | |
c19d1205 ZW |
26853 | where += 4; |
26854 | ptr += 4; | |
bfae80f2 | 26855 | |
c19d1205 | 26856 | /* Set the first byte to the number of additional words. */ |
5011093d | 26857 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
26858 | n = 3; |
26859 | break; | |
bfae80f2 | 26860 | |
c19d1205 ZW |
26861 | /* ABI defined personality routines. */ |
26862 | case 0: | |
26863 | /* Three opcodes bytes are packed into the first word. */ | |
26864 | data = 0x80; | |
26865 | n = 3; | |
26866 | break; | |
bfae80f2 | 26867 | |
c19d1205 ZW |
26868 | case 1: |
26869 | case 2: | |
26870 | /* The size and first two opcode bytes go in the first word. */ | |
26871 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
26872 | n = 2; | |
26873 | break; | |
bfae80f2 | 26874 | |
c19d1205 ZW |
26875 | default: |
26876 | /* Should never happen. */ | |
26877 | abort (); | |
26878 | } | |
bfae80f2 | 26879 | |
c19d1205 ZW |
26880 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
26881 | time. */ | |
26882 | while (unwind.opcode_count > 0) | |
26883 | { | |
26884 | if (n == 0) | |
26885 | { | |
26886 | md_number_to_chars (ptr, data, 4); | |
26887 | ptr += 4; | |
26888 | n = 4; | |
26889 | data = 0; | |
26890 | } | |
26891 | unwind.opcode_count--; | |
26892 | n--; | |
26893 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
26894 | } | |
26895 | ||
26896 | /* Finish off the last word. */ | |
26897 | if (n < 4) | |
26898 | { | |
26899 | /* Pad with "finish" opcodes. */ | |
26900 | while (n--) | |
26901 | data = (data << 8) | 0xb0; | |
26902 | ||
26903 | md_number_to_chars (ptr, data, 4); | |
26904 | } | |
26905 | ||
26906 | if (!have_data) | |
26907 | { | |
26908 | /* Add an empty descriptor if there is no user-specified data. */ | |
26909 | ptr = frag_more (4); | |
26910 | md_number_to_chars (ptr, 0, 4); | |
26911 | } | |
26912 | ||
26913 | return 0; | |
bfae80f2 RE |
26914 | } |
26915 | ||
f0927246 NC |
26916 | |
26917 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
26918 | ||
26919 | void | |
26920 | tc_arm_frame_initial_instructions (void) | |
26921 | { | |
26922 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
26923 | } | |
26924 | #endif /* OBJ_ELF */ | |
26925 | ||
c19d1205 ZW |
26926 | /* Convert REGNAME to a DWARF-2 register number. */ |
26927 | ||
26928 | int | |
1df69f4f | 26929 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 26930 | { |
1df69f4f | 26931 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
26932 | if (reg != FAIL) |
26933 | return reg; | |
c19d1205 | 26934 | |
1f5afe1c NC |
26935 | /* PR 16694: Allow VFP registers as well. */ |
26936 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
26937 | if (reg != FAIL) | |
26938 | return 64 + reg; | |
c19d1205 | 26939 | |
1f5afe1c NC |
26940 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
26941 | if (reg != FAIL) | |
26942 | return reg + 256; | |
26943 | ||
0198d5e6 | 26944 | return FAIL; |
bfae80f2 RE |
26945 | } |
26946 | ||
f0927246 | 26947 | #ifdef TE_PE |
c19d1205 | 26948 | void |
f0927246 | 26949 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 26950 | { |
91d6fa6a | 26951 | expressionS exp; |
bfae80f2 | 26952 | |
91d6fa6a NC |
26953 | exp.X_op = O_secrel; |
26954 | exp.X_add_symbol = symbol; | |
26955 | exp.X_add_number = 0; | |
26956 | emit_expr (&exp, size); | |
f0927246 NC |
26957 | } |
26958 | #endif | |
bfae80f2 | 26959 | |
c19d1205 | 26960 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 26961 | |
2fc8bdac ZW |
26962 | /* Return the address within the segment that a PC-relative fixup is |
26963 | relative to. For ARM, PC-relative fixups applied to instructions | |
26964 | are generally relative to the location of the fixup plus 8 bytes. | |
26965 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
26966 | require special handling. */ | |
bfae80f2 | 26967 | |
c19d1205 | 26968 | long |
2fc8bdac | 26969 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 26970 | { |
2fc8bdac ZW |
26971 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
26972 | ||
26973 | /* If this is pc-relative and we are going to emit a relocation | |
26974 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
26975 | will need. Otherwise we want to use the calculated base. |
26976 | For WinCE we skip the bias for externals as well, since this | |
26977 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 26978 | if (fixP->fx_pcrel |
2fc8bdac | 26979 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
26980 | || (arm_force_relocation (fixP) |
26981 | #ifdef TE_WINCE | |
26982 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
26983 | #endif | |
26984 | ))) | |
2fc8bdac | 26985 | base = 0; |
bfae80f2 | 26986 | |
267bf995 | 26987 | |
c19d1205 | 26988 | switch (fixP->fx_r_type) |
bfae80f2 | 26989 | { |
2fc8bdac ZW |
26990 | /* PC relative addressing on the Thumb is slightly odd as the |
26991 | bottom two bits of the PC are forced to zero for the | |
26992 | calculation. This happens *after* application of the | |
26993 | pipeline offset. However, Thumb adrl already adjusts for | |
26994 | this, so we need not do it again. */ | |
c19d1205 | 26995 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 26996 | return base & ~3; |
c19d1205 ZW |
26997 | |
26998 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
26999 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 27000 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 27001 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 27002 | return (base + 4) & ~3; |
c19d1205 | 27003 | |
2fc8bdac | 27004 | /* Thumb branches are simply offset by +4. */ |
e12437dc | 27005 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
2fc8bdac ZW |
27006 | case BFD_RELOC_THUMB_PCREL_BRANCH7: |
27007 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
27008 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
27009 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 27010 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
f6b2b12d | 27011 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
e5d6e09e | 27012 | case BFD_RELOC_ARM_THUMB_BF17: |
1caf72a5 | 27013 | case BFD_RELOC_ARM_THUMB_BF19: |
1889da70 | 27014 | case BFD_RELOC_ARM_THUMB_BF13: |
60f993ce | 27015 | case BFD_RELOC_ARM_THUMB_LOOP12: |
2fc8bdac | 27016 | return base + 4; |
bfae80f2 | 27017 | |
267bf995 | 27018 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
27019 | if (fixP->fx_addsy |
27020 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 27021 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 27022 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
27023 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
27024 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
27025 | return base + 4; |
27026 | ||
00adf2d4 JB |
27027 | /* BLX is like branches above, but forces the low two bits of PC to |
27028 | zero. */ | |
486499d0 CL |
27029 | case BFD_RELOC_THUMB_PCREL_BLX: |
27030 | if (fixP->fx_addsy | |
27031 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 27032 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
27033 | && THUMB_IS_FUNC (fixP->fx_addsy) |
27034 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
27035 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
27036 | return (base + 4) & ~3; |
27037 | ||
2fc8bdac ZW |
27038 | /* ARM mode branches are offset by +8. However, the Windows CE |
27039 | loader expects the relocation not to take this into account. */ | |
267bf995 | 27040 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
27041 | if (fixP->fx_addsy |
27042 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 27043 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
27044 | && ARM_IS_FUNC (fixP->fx_addsy) |
27045 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
27046 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 27047 | return base + 8; |
267bf995 | 27048 | |
486499d0 CL |
27049 | case BFD_RELOC_ARM_PCREL_CALL: |
27050 | if (fixP->fx_addsy | |
27051 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 27052 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
27053 | && THUMB_IS_FUNC (fixP->fx_addsy) |
27054 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
27055 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 27056 | return base + 8; |
267bf995 | 27057 | |
2fc8bdac | 27058 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 27059 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 27060 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 27061 | #ifdef TE_WINCE |
5f4273c7 | 27062 | /* When handling fixups immediately, because we have already |
477330fc | 27063 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 27064 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
27065 | see fixup_segment() in write.c |
27066 | The S_IS_EXTERNAL test handles the case of global symbols. | |
27067 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
27068 | if (fixP->fx_pcrel |
27069 | && fixP->fx_addsy != NULL | |
27070 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
27071 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
27072 | return base + 8; | |
2fc8bdac | 27073 | return base; |
c19d1205 | 27074 | #else |
2fc8bdac | 27075 | return base + 8; |
c19d1205 | 27076 | #endif |
2fc8bdac | 27077 | |
267bf995 | 27078 | |
2fc8bdac ZW |
27079 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
27080 | branches, the Windows CE loader *does* expect the relocation | |
27081 | to take this into account. */ | |
27082 | case BFD_RELOC_ARM_OFFSET_IMM: | |
27083 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
27084 | case BFD_RELOC_ARM_HWLITERAL: | |
27085 | case BFD_RELOC_ARM_LITERAL: | |
27086 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
27087 | return base + 8; | |
27088 | ||
27089 | ||
27090 | /* Other PC-relative relocations are un-offset. */ | |
27091 | default: | |
27092 | return base; | |
27093 | } | |
bfae80f2 RE |
27094 | } |
27095 | ||
8b2d793c NC |
27096 | static bfd_boolean flag_warn_syms = TRUE; |
27097 | ||
ae8714c2 NC |
27098 | bfd_boolean |
27099 | arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name) | |
bfae80f2 | 27100 | { |
8b2d793c NC |
27101 | /* PR 18347 - Warn if the user attempts to create a symbol with the same |
27102 | name as an ARM instruction. Whilst strictly speaking it is allowed, it | |
27103 | does mean that the resulting code might be very confusing to the reader. | |
27104 | Also this warning can be triggered if the user omits an operand before | |
27105 | an immediate address, eg: | |
27106 | ||
27107 | LDR =foo | |
27108 | ||
27109 | GAS treats this as an assignment of the value of the symbol foo to a | |
27110 | symbol LDR, and so (without this code) it will not issue any kind of | |
27111 | warning or error message. | |
27112 | ||
27113 | Note - ARM instructions are case-insensitive but the strings in the hash | |
27114 | table are all stored in lower case, so we must first ensure that name is | |
ae8714c2 NC |
27115 | lower case too. */ |
27116 | if (flag_warn_syms && arm_ops_hsh) | |
8b2d793c NC |
27117 | { |
27118 | char * nbuf = strdup (name); | |
27119 | char * p; | |
27120 | ||
27121 | for (p = nbuf; *p; p++) | |
27122 | *p = TOLOWER (*p); | |
27123 | if (hash_find (arm_ops_hsh, nbuf) != NULL) | |
27124 | { | |
27125 | static struct hash_control * already_warned = NULL; | |
27126 | ||
27127 | if (already_warned == NULL) | |
27128 | already_warned = hash_new (); | |
27129 | /* Only warn about the symbol once. To keep the code | |
27130 | simple we let hash_insert do the lookup for us. */ | |
3076e594 | 27131 | if (hash_insert (already_warned, nbuf, NULL) == NULL) |
ae8714c2 | 27132 | as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name); |
8b2d793c NC |
27133 | } |
27134 | else | |
27135 | free (nbuf); | |
27136 | } | |
3739860c | 27137 | |
ae8714c2 NC |
27138 | return FALSE; |
27139 | } | |
27140 | ||
27141 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
27142 | Otherwise we have no need to default values of symbols. */ | |
27143 | ||
27144 | symbolS * | |
27145 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
27146 | { | |
27147 | #ifdef OBJ_ELF | |
27148 | if (name[0] == '_' && name[1] == 'G' | |
27149 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
27150 | { | |
27151 | if (!GOT_symbol) | |
27152 | { | |
27153 | if (symbol_find (name)) | |
27154 | as_bad (_("GOT already in the symbol table")); | |
27155 | ||
27156 | GOT_symbol = symbol_new (name, undefined_section, | |
27157 | (valueT) 0, & zero_address_frag); | |
27158 | } | |
27159 | ||
27160 | return GOT_symbol; | |
27161 | } | |
27162 | #endif | |
27163 | ||
c921be7d | 27164 | return NULL; |
bfae80f2 RE |
27165 | } |
27166 | ||
55cf6793 | 27167 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
27168 | computed as two separate immediate values, added together. We |
27169 | already know that this value cannot be computed by just one ARM | |
27170 | instruction. */ | |
27171 | ||
27172 | static unsigned int | |
27173 | validate_immediate_twopart (unsigned int val, | |
27174 | unsigned int * highpart) | |
bfae80f2 | 27175 | { |
c19d1205 ZW |
27176 | unsigned int a; |
27177 | unsigned int i; | |
bfae80f2 | 27178 | |
c19d1205 ZW |
27179 | for (i = 0; i < 32; i += 2) |
27180 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
27181 | { | |
27182 | if (a & 0xff00) | |
27183 | { | |
27184 | if (a & ~ 0xffff) | |
27185 | continue; | |
27186 | * highpart = (a >> 8) | ((i + 24) << 7); | |
27187 | } | |
27188 | else if (a & 0xff0000) | |
27189 | { | |
27190 | if (a & 0xff000000) | |
27191 | continue; | |
27192 | * highpart = (a >> 16) | ((i + 16) << 7); | |
27193 | } | |
27194 | else | |
27195 | { | |
9c2799c2 | 27196 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
27197 | * highpart = (a >> 24) | ((i + 8) << 7); |
27198 | } | |
bfae80f2 | 27199 | |
c19d1205 ZW |
27200 | return (a & 0xff) | (i << 7); |
27201 | } | |
bfae80f2 | 27202 | |
c19d1205 | 27203 | return FAIL; |
bfae80f2 RE |
27204 | } |
27205 | ||
c19d1205 ZW |
27206 | static int |
27207 | validate_offset_imm (unsigned int val, int hwse) | |
27208 | { | |
27209 | if ((hwse && val > 255) || val > 4095) | |
27210 | return FAIL; | |
27211 | return val; | |
27212 | } | |
bfae80f2 | 27213 | |
55cf6793 | 27214 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
27215 | negative immediate constant by altering the instruction. A bit of |
27216 | a hack really. | |
27217 | MOV <-> MVN | |
27218 | AND <-> BIC | |
27219 | ADC <-> SBC | |
27220 | by inverting the second operand, and | |
27221 | ADD <-> SUB | |
27222 | CMP <-> CMN | |
27223 | by negating the second operand. */ | |
bfae80f2 | 27224 | |
c19d1205 ZW |
27225 | static int |
27226 | negate_data_op (unsigned long * instruction, | |
27227 | unsigned long value) | |
bfae80f2 | 27228 | { |
c19d1205 ZW |
27229 | int op, new_inst; |
27230 | unsigned long negated, inverted; | |
bfae80f2 | 27231 | |
c19d1205 ZW |
27232 | negated = encode_arm_immediate (-value); |
27233 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 27234 | |
c19d1205 ZW |
27235 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
27236 | switch (op) | |
bfae80f2 | 27237 | { |
c19d1205 ZW |
27238 | /* First negates. */ |
27239 | case OPCODE_SUB: /* ADD <-> SUB */ | |
27240 | new_inst = OPCODE_ADD; | |
27241 | value = negated; | |
27242 | break; | |
bfae80f2 | 27243 | |
c19d1205 ZW |
27244 | case OPCODE_ADD: |
27245 | new_inst = OPCODE_SUB; | |
27246 | value = negated; | |
27247 | break; | |
bfae80f2 | 27248 | |
c19d1205 ZW |
27249 | case OPCODE_CMP: /* CMP <-> CMN */ |
27250 | new_inst = OPCODE_CMN; | |
27251 | value = negated; | |
27252 | break; | |
bfae80f2 | 27253 | |
c19d1205 ZW |
27254 | case OPCODE_CMN: |
27255 | new_inst = OPCODE_CMP; | |
27256 | value = negated; | |
27257 | break; | |
bfae80f2 | 27258 | |
c19d1205 ZW |
27259 | /* Now Inverted ops. */ |
27260 | case OPCODE_MOV: /* MOV <-> MVN */ | |
27261 | new_inst = OPCODE_MVN; | |
27262 | value = inverted; | |
27263 | break; | |
bfae80f2 | 27264 | |
c19d1205 ZW |
27265 | case OPCODE_MVN: |
27266 | new_inst = OPCODE_MOV; | |
27267 | value = inverted; | |
27268 | break; | |
bfae80f2 | 27269 | |
c19d1205 ZW |
27270 | case OPCODE_AND: /* AND <-> BIC */ |
27271 | new_inst = OPCODE_BIC; | |
27272 | value = inverted; | |
27273 | break; | |
bfae80f2 | 27274 | |
c19d1205 ZW |
27275 | case OPCODE_BIC: |
27276 | new_inst = OPCODE_AND; | |
27277 | value = inverted; | |
27278 | break; | |
bfae80f2 | 27279 | |
c19d1205 ZW |
27280 | case OPCODE_ADC: /* ADC <-> SBC */ |
27281 | new_inst = OPCODE_SBC; | |
27282 | value = inverted; | |
27283 | break; | |
bfae80f2 | 27284 | |
c19d1205 ZW |
27285 | case OPCODE_SBC: |
27286 | new_inst = OPCODE_ADC; | |
27287 | value = inverted; | |
27288 | break; | |
bfae80f2 | 27289 | |
c19d1205 ZW |
27290 | /* We cannot do anything. */ |
27291 | default: | |
27292 | return FAIL; | |
b99bd4ef NC |
27293 | } |
27294 | ||
c19d1205 ZW |
27295 | if (value == (unsigned) FAIL) |
27296 | return FAIL; | |
27297 | ||
27298 | *instruction &= OPCODE_MASK; | |
27299 | *instruction |= new_inst << DATA_OP_SHIFT; | |
27300 | return value; | |
b99bd4ef NC |
27301 | } |
27302 | ||
ef8d22e6 PB |
27303 | /* Like negate_data_op, but for Thumb-2. */ |
27304 | ||
27305 | static unsigned int | |
16dd5e42 | 27306 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
27307 | { |
27308 | int op, new_inst; | |
27309 | int rd; | |
16dd5e42 | 27310 | unsigned int negated, inverted; |
ef8d22e6 PB |
27311 | |
27312 | negated = encode_thumb32_immediate (-value); | |
27313 | inverted = encode_thumb32_immediate (~value); | |
27314 | ||
27315 | rd = (*instruction >> 8) & 0xf; | |
27316 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
27317 | switch (op) | |
27318 | { | |
27319 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
27320 | case T2_OPCODE_SUB: | |
27321 | new_inst = T2_OPCODE_ADD; | |
27322 | value = negated; | |
27323 | break; | |
27324 | ||
27325 | case T2_OPCODE_ADD: | |
27326 | new_inst = T2_OPCODE_SUB; | |
27327 | value = negated; | |
27328 | break; | |
27329 | ||
27330 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
27331 | case T2_OPCODE_ORR: | |
27332 | new_inst = T2_OPCODE_ORN; | |
27333 | value = inverted; | |
27334 | break; | |
27335 | ||
27336 | case T2_OPCODE_ORN: | |
27337 | new_inst = T2_OPCODE_ORR; | |
27338 | value = inverted; | |
27339 | break; | |
27340 | ||
27341 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
27342 | case T2_OPCODE_AND: | |
27343 | new_inst = T2_OPCODE_BIC; | |
27344 | if (rd == 15) | |
27345 | value = FAIL; | |
27346 | else | |
27347 | value = inverted; | |
27348 | break; | |
27349 | ||
27350 | case T2_OPCODE_BIC: | |
27351 | new_inst = T2_OPCODE_AND; | |
27352 | value = inverted; | |
27353 | break; | |
27354 | ||
27355 | /* ADC <-> SBC */ | |
27356 | case T2_OPCODE_ADC: | |
27357 | new_inst = T2_OPCODE_SBC; | |
27358 | value = inverted; | |
27359 | break; | |
27360 | ||
27361 | case T2_OPCODE_SBC: | |
27362 | new_inst = T2_OPCODE_ADC; | |
27363 | value = inverted; | |
27364 | break; | |
27365 | ||
27366 | /* We cannot do anything. */ | |
27367 | default: | |
27368 | return FAIL; | |
27369 | } | |
27370 | ||
16dd5e42 | 27371 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
27372 | return FAIL; |
27373 | ||
27374 | *instruction &= T2_OPCODE_MASK; | |
27375 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
27376 | return value; | |
27377 | } | |
27378 | ||
8f06b2d8 | 27379 | /* Read a 32-bit thumb instruction from buf. */ |
0198d5e6 | 27380 | |
8f06b2d8 PB |
27381 | static unsigned long |
27382 | get_thumb32_insn (char * buf) | |
27383 | { | |
27384 | unsigned long insn; | |
27385 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
27386 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
27387 | ||
27388 | return insn; | |
27389 | } | |
27390 | ||
a8bc6c78 PB |
27391 | /* We usually want to set the low bit on the address of thumb function |
27392 | symbols. In particular .word foo - . should have the low bit set. | |
27393 | Generic code tries to fold the difference of two symbols to | |
27394 | a constant. Prevent this and force a relocation when the first symbols | |
27395 | is a thumb function. */ | |
c921be7d NC |
27396 | |
27397 | bfd_boolean | |
a8bc6c78 PB |
27398 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
27399 | { | |
27400 | if (op == O_subtract | |
27401 | && l->X_op == O_symbol | |
27402 | && r->X_op == O_symbol | |
27403 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
27404 | { | |
27405 | l->X_op = O_subtract; | |
27406 | l->X_op_symbol = r->X_add_symbol; | |
27407 | l->X_add_number -= r->X_add_number; | |
c921be7d | 27408 | return TRUE; |
a8bc6c78 | 27409 | } |
c921be7d | 27410 | |
a8bc6c78 | 27411 | /* Process as normal. */ |
c921be7d | 27412 | return FALSE; |
a8bc6c78 PB |
27413 | } |
27414 | ||
4a42ebbc RR |
27415 | /* Encode Thumb2 unconditional branches and calls. The encoding |
27416 | for the 2 are identical for the immediate values. */ | |
27417 | ||
27418 | static void | |
27419 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
27420 | { | |
27421 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
27422 | offsetT newval; | |
27423 | offsetT newval2; | |
27424 | addressT S, I1, I2, lo, hi; | |
27425 | ||
27426 | S = (value >> 24) & 0x01; | |
27427 | I1 = (value >> 23) & 0x01; | |
27428 | I2 = (value >> 22) & 0x01; | |
27429 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 27430 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
27431 | newval = md_chars_to_number (buf, THUMB_SIZE); |
27432 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
27433 | newval |= (S << 10) | hi; | |
27434 | newval2 &= ~T2I1I2MASK; | |
27435 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
27436 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27437 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
27438 | } | |
27439 | ||
c19d1205 | 27440 | void |
55cf6793 | 27441 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
27442 | valueT * valP, |
27443 | segT seg) | |
27444 | { | |
27445 | offsetT value = * valP; | |
27446 | offsetT newval; | |
27447 | unsigned int newimm; | |
27448 | unsigned long temp; | |
27449 | int sign; | |
27450 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 27451 | |
9c2799c2 | 27452 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 27453 | |
c19d1205 | 27454 | /* Note whether this will delete the relocation. */ |
4962c51a | 27455 | |
c19d1205 ZW |
27456 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
27457 | fixP->fx_done = 1; | |
b99bd4ef | 27458 | |
adbaf948 | 27459 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 27460 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
27461 | for emit_reloc. */ |
27462 | value &= 0xffffffff; | |
27463 | value ^= 0x80000000; | |
5f4273c7 | 27464 | value -= 0x80000000; |
adbaf948 ZW |
27465 | |
27466 | *valP = value; | |
c19d1205 | 27467 | fixP->fx_addnumber = value; |
b99bd4ef | 27468 | |
adbaf948 ZW |
27469 | /* Same treatment for fixP->fx_offset. */ |
27470 | fixP->fx_offset &= 0xffffffff; | |
27471 | fixP->fx_offset ^= 0x80000000; | |
27472 | fixP->fx_offset -= 0x80000000; | |
27473 | ||
c19d1205 | 27474 | switch (fixP->fx_r_type) |
b99bd4ef | 27475 | { |
c19d1205 ZW |
27476 | case BFD_RELOC_NONE: |
27477 | /* This will need to go in the object file. */ | |
27478 | fixP->fx_done = 0; | |
27479 | break; | |
b99bd4ef | 27480 | |
c19d1205 ZW |
27481 | case BFD_RELOC_ARM_IMMEDIATE: |
27482 | /* We claim that this fixup has been processed here, | |
27483 | even if in fact we generate an error because we do | |
27484 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
27485 | fixP->fx_done = 1; | |
b99bd4ef | 27486 | |
77db8e2e | 27487 | if (fixP->fx_addsy) |
b99bd4ef | 27488 | { |
77db8e2e | 27489 | const char *msg = 0; |
b99bd4ef | 27490 | |
77db8e2e NC |
27491 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
27492 | msg = _("undefined symbol %s used as an immediate value"); | |
27493 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
27494 | msg = _("symbol %s is in a different section"); | |
27495 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
27496 | msg = _("symbol %s is weak and may be overridden later"); | |
27497 | ||
27498 | if (msg) | |
27499 | { | |
27500 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27501 | msg, S_GET_NAME (fixP->fx_addsy)); | |
27502 | break; | |
27503 | } | |
42e5fcbf AS |
27504 | } |
27505 | ||
c19d1205 ZW |
27506 | temp = md_chars_to_number (buf, INSN_SIZE); |
27507 | ||
5e73442d SL |
27508 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
27509 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
27510 | newimm = negate_data_op (&temp, value); | |
27511 | else | |
27512 | { | |
27513 | newimm = encode_arm_immediate (value); | |
27514 | ||
27515 | /* If the instruction will fail, see if we can fix things up by | |
27516 | changing the opcode. */ | |
27517 | if (newimm == (unsigned int) FAIL) | |
27518 | newimm = negate_data_op (&temp, value); | |
bada4342 JW |
27519 | /* MOV accepts both ARM modified immediate (A1 encoding) and |
27520 | UINT16 (A2 encoding) when possible, MOVW only accepts UINT16. | |
27521 | When disassembling, MOV is preferred when there is no encoding | |
27522 | overlap. */ | |
27523 | if (newimm == (unsigned int) FAIL | |
27524 | && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV | |
27525 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) | |
27526 | && !((temp >> SBIT_SHIFT) & 0x1) | |
27527 | && value >= 0 && value <= 0xffff) | |
27528 | { | |
27529 | /* Clear bits[23:20] to change encoding from A1 to A2. */ | |
27530 | temp &= 0xff0fffff; | |
27531 | /* Encoding high 4bits imm. Code below will encode the remaining | |
27532 | low 12bits. */ | |
27533 | temp |= (value & 0x0000f000) << 4; | |
27534 | newimm = value & 0x00000fff; | |
27535 | } | |
5e73442d SL |
27536 | } |
27537 | ||
27538 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 27539 | { |
c19d1205 ZW |
27540 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27541 | _("invalid constant (%lx) after fixup"), | |
27542 | (unsigned long) value); | |
27543 | break; | |
b99bd4ef | 27544 | } |
b99bd4ef | 27545 | |
c19d1205 ZW |
27546 | newimm |= (temp & 0xfffff000); |
27547 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
27548 | break; | |
b99bd4ef | 27549 | |
c19d1205 ZW |
27550 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
27551 | { | |
27552 | unsigned int highpart = 0; | |
27553 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 27554 | |
77db8e2e | 27555 | if (fixP->fx_addsy) |
42e5fcbf | 27556 | { |
77db8e2e | 27557 | const char *msg = 0; |
42e5fcbf | 27558 | |
77db8e2e NC |
27559 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
27560 | msg = _("undefined symbol %s used as an immediate value"); | |
27561 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
27562 | msg = _("symbol %s is in a different section"); | |
27563 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
27564 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 27565 | |
77db8e2e NC |
27566 | if (msg) |
27567 | { | |
27568 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27569 | msg, S_GET_NAME (fixP->fx_addsy)); | |
27570 | break; | |
27571 | } | |
27572 | } | |
fa94de6b | 27573 | |
c19d1205 ZW |
27574 | newimm = encode_arm_immediate (value); |
27575 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 27576 | |
c19d1205 ZW |
27577 | /* If the instruction will fail, see if we can fix things up by |
27578 | changing the opcode. */ | |
27579 | if (newimm == (unsigned int) FAIL | |
27580 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
27581 | { | |
27582 | /* No ? OK - try using two ADD instructions to generate | |
27583 | the value. */ | |
27584 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 27585 | |
c19d1205 ZW |
27586 | /* Yes - then make sure that the second instruction is |
27587 | also an add. */ | |
27588 | if (newimm != (unsigned int) FAIL) | |
27589 | newinsn = temp; | |
27590 | /* Still No ? Try using a negated value. */ | |
27591 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
27592 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
27593 | /* Otherwise - give up. */ | |
27594 | else | |
27595 | { | |
27596 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27597 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
27598 | (long) value); | |
27599 | break; | |
27600 | } | |
b99bd4ef | 27601 | |
c19d1205 ZW |
27602 | /* Replace the first operand in the 2nd instruction (which |
27603 | is the PC) with the destination register. We have | |
27604 | already added in the PC in the first instruction and we | |
27605 | do not want to do it again. */ | |
27606 | newinsn &= ~ 0xf0000; | |
27607 | newinsn |= ((newinsn & 0x0f000) << 4); | |
27608 | } | |
b99bd4ef | 27609 | |
c19d1205 ZW |
27610 | newimm |= (temp & 0xfffff000); |
27611 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 27612 | |
c19d1205 ZW |
27613 | highpart |= (newinsn & 0xfffff000); |
27614 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
27615 | } | |
27616 | break; | |
b99bd4ef | 27617 | |
c19d1205 | 27618 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
27619 | if (!fixP->fx_done && seg->use_rela_p) |
27620 | value = 0; | |
1a0670f3 | 27621 | /* Fall through. */ |
00a97672 | 27622 | |
c19d1205 | 27623 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 27624 | sign = value > 0; |
b99bd4ef | 27625 | |
c19d1205 ZW |
27626 | if (value < 0) |
27627 | value = - value; | |
b99bd4ef | 27628 | |
c19d1205 | 27629 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 27630 | { |
c19d1205 ZW |
27631 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
27632 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27633 | _("invalid literal constant: pool needs to be closer")); | |
27634 | else | |
27635 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27636 | _("bad immediate value for offset (%ld)"), | |
27637 | (long) value); | |
27638 | break; | |
f03698e6 RE |
27639 | } |
27640 | ||
c19d1205 | 27641 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
27642 | if (value == 0) |
27643 | newval &= 0xfffff000; | |
27644 | else | |
27645 | { | |
27646 | newval &= 0xff7ff000; | |
27647 | newval |= value | (sign ? INDEX_UP : 0); | |
27648 | } | |
c19d1205 ZW |
27649 | md_number_to_chars (buf, newval, INSN_SIZE); |
27650 | break; | |
b99bd4ef | 27651 | |
c19d1205 ZW |
27652 | case BFD_RELOC_ARM_OFFSET_IMM8: |
27653 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 27654 | sign = value > 0; |
b99bd4ef | 27655 | |
c19d1205 ZW |
27656 | if (value < 0) |
27657 | value = - value; | |
b99bd4ef | 27658 | |
c19d1205 | 27659 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 27660 | { |
c19d1205 ZW |
27661 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
27662 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27663 | _("invalid literal constant: pool needs to be closer")); | |
27664 | else | |
427d0db6 RM |
27665 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27666 | _("bad immediate value for 8-bit offset (%ld)"), | |
27667 | (long) value); | |
c19d1205 | 27668 | break; |
b99bd4ef NC |
27669 | } |
27670 | ||
c19d1205 | 27671 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
27672 | if (value == 0) |
27673 | newval &= 0xfffff0f0; | |
27674 | else | |
27675 | { | |
27676 | newval &= 0xff7ff0f0; | |
27677 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
27678 | } | |
c19d1205 ZW |
27679 | md_number_to_chars (buf, newval, INSN_SIZE); |
27680 | break; | |
b99bd4ef | 27681 | |
c19d1205 ZW |
27682 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
27683 | if (value < 0 || value > 1020 || value % 4 != 0) | |
27684 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27685 | _("bad immediate value for offset (%ld)"), (long) value); | |
27686 | value /= 4; | |
b99bd4ef | 27687 | |
c19d1205 | 27688 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
27689 | newval |= value; |
27690 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
27691 | break; | |
b99bd4ef | 27692 | |
c19d1205 ZW |
27693 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
27694 | /* This is a complicated relocation used for all varieties of Thumb32 | |
27695 | load/store instruction with immediate offset: | |
27696 | ||
27697 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 27698 | *4, optional writeback(W) |
c19d1205 ZW |
27699 | (doubleword load/store) |
27700 | ||
27701 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
27702 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
27703 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
27704 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
27705 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
27706 | ||
27707 | Uppercase letters indicate bits that are already encoded at | |
27708 | this point. Lowercase letters are our problem. For the | |
27709 | second block of instructions, the secondary opcode nybble | |
27710 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
27711 | a PC-relative operation. */ | |
27712 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
27713 | newval <<= 16; | |
27714 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 27715 | |
c19d1205 | 27716 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 27717 | { |
c19d1205 ZW |
27718 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
27719 | if (value >= 0) | |
27720 | newval |= (1 << 23); | |
27721 | else | |
27722 | value = -value; | |
27723 | if (value % 4 != 0) | |
27724 | { | |
27725 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27726 | _("offset not a multiple of 4")); | |
27727 | break; | |
27728 | } | |
27729 | value /= 4; | |
216d22bc | 27730 | if (value > 0xff) |
c19d1205 ZW |
27731 | { |
27732 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27733 | _("offset out of range")); | |
27734 | break; | |
27735 | } | |
27736 | newval &= ~0xff; | |
b99bd4ef | 27737 | } |
c19d1205 | 27738 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 27739 | { |
c19d1205 ZW |
27740 | /* PC-relative, 12-bit offset. */ |
27741 | if (value >= 0) | |
27742 | newval |= (1 << 23); | |
27743 | else | |
27744 | value = -value; | |
216d22bc | 27745 | if (value > 0xfff) |
c19d1205 ZW |
27746 | { |
27747 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27748 | _("offset out of range")); | |
27749 | break; | |
27750 | } | |
27751 | newval &= ~0xfff; | |
b99bd4ef | 27752 | } |
c19d1205 | 27753 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 27754 | { |
c19d1205 ZW |
27755 | /* Writeback: 8-bit, +/- offset. */ |
27756 | if (value >= 0) | |
27757 | newval |= (1 << 9); | |
27758 | else | |
27759 | value = -value; | |
216d22bc | 27760 | if (value > 0xff) |
c19d1205 ZW |
27761 | { |
27762 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27763 | _("offset out of range")); | |
27764 | break; | |
27765 | } | |
27766 | newval &= ~0xff; | |
b99bd4ef | 27767 | } |
c19d1205 | 27768 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 27769 | { |
c19d1205 | 27770 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 27771 | if (value < 0 || value > 0xff) |
b99bd4ef | 27772 | { |
c19d1205 ZW |
27773 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27774 | _("offset out of range")); | |
27775 | break; | |
b99bd4ef | 27776 | } |
c19d1205 ZW |
27777 | newval &= ~0xff; |
27778 | newval |= value; | |
b99bd4ef NC |
27779 | } |
27780 | else | |
b99bd4ef | 27781 | { |
c19d1205 ZW |
27782 | /* Positive 12-bit or negative 8-bit offset. */ |
27783 | int limit; | |
27784 | if (value >= 0) | |
b99bd4ef | 27785 | { |
c19d1205 ZW |
27786 | newval |= (1 << 23); |
27787 | limit = 0xfff; | |
27788 | } | |
27789 | else | |
27790 | { | |
27791 | value = -value; | |
27792 | limit = 0xff; | |
27793 | } | |
27794 | if (value > limit) | |
27795 | { | |
27796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27797 | _("offset out of range")); | |
27798 | break; | |
b99bd4ef | 27799 | } |
c19d1205 | 27800 | newval &= ~limit; |
b99bd4ef | 27801 | } |
b99bd4ef | 27802 | |
c19d1205 ZW |
27803 | newval |= value; |
27804 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
27805 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
27806 | break; | |
404ff6b5 | 27807 | |
c19d1205 ZW |
27808 | case BFD_RELOC_ARM_SHIFT_IMM: |
27809 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27810 | if (((unsigned long) value) > 32 | |
27811 | || (value == 32 | |
27812 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
27813 | { | |
27814 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27815 | _("shift expression is too large")); | |
27816 | break; | |
27817 | } | |
404ff6b5 | 27818 | |
c19d1205 ZW |
27819 | if (value == 0) |
27820 | /* Shifts of zero must be done as lsl. */ | |
27821 | newval &= ~0x60; | |
27822 | else if (value == 32) | |
27823 | value = 0; | |
27824 | newval &= 0xfffff07f; | |
27825 | newval |= (value & 0x1f) << 7; | |
27826 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27827 | break; | |
404ff6b5 | 27828 | |
c19d1205 | 27829 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 27830 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 27831 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 27832 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
27833 | /* We claim that this fixup has been processed here, |
27834 | even if in fact we generate an error because we do | |
27835 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
27836 | fixP->fx_done = 1; | |
404ff6b5 | 27837 | |
c19d1205 ZW |
27838 | if (fixP->fx_addsy |
27839 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
27840 | { | |
27841 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27842 | _("undefined symbol %s used as an immediate value"), | |
27843 | S_GET_NAME (fixP->fx_addsy)); | |
27844 | break; | |
27845 | } | |
404ff6b5 | 27846 | |
c19d1205 ZW |
27847 | newval = md_chars_to_number (buf, THUMB_SIZE); |
27848 | newval <<= 16; | |
27849 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 27850 | |
16805f35 | 27851 | newimm = FAIL; |
bada4342 JW |
27852 | if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
27853 | /* ARMv8-M Baseline MOV will reach here, but it doesn't support | |
27854 | Thumb2 modified immediate encoding (T2). */ | |
27855 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
16805f35 | 27856 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) |
ef8d22e6 PB |
27857 | { |
27858 | newimm = encode_thumb32_immediate (value); | |
27859 | if (newimm == (unsigned int) FAIL) | |
27860 | newimm = thumb32_negate_data_op (&newval, value); | |
27861 | } | |
bada4342 | 27862 | if (newimm == (unsigned int) FAIL) |
92e90b6e | 27863 | { |
bada4342 | 27864 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE) |
e9f89963 | 27865 | { |
bada4342 JW |
27866 | /* Turn add/sum into addw/subw. */ |
27867 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
27868 | newval = (newval & 0xfeffffff) | 0x02000000; | |
27869 | /* No flat 12-bit imm encoding for addsw/subsw. */ | |
27870 | if ((newval & 0x00100000) == 0) | |
40f246e3 | 27871 | { |
bada4342 JW |
27872 | /* 12 bit immediate for addw/subw. */ |
27873 | if (value < 0) | |
27874 | { | |
27875 | value = -value; | |
27876 | newval ^= 0x00a00000; | |
27877 | } | |
27878 | if (value > 0xfff) | |
27879 | newimm = (unsigned int) FAIL; | |
27880 | else | |
27881 | newimm = value; | |
27882 | } | |
27883 | } | |
27884 | else | |
27885 | { | |
27886 | /* MOV accepts both Thumb2 modified immediate (T2 encoding) and | |
27887 | UINT16 (T3 encoding), MOVW only accepts UINT16. When | |
27888 | disassembling, MOV is preferred when there is no encoding | |
db7bf105 | 27889 | overlap. */ |
bada4342 | 27890 | if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR |
db7bf105 NC |
27891 | /* NOTE: MOV uses the ORR opcode in Thumb 2 mode |
27892 | but with the Rn field [19:16] set to 1111. */ | |
27893 | && (((newval >> 16) & 0xf) == 0xf) | |
bada4342 JW |
27894 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m) |
27895 | && !((newval >> T2_SBIT_SHIFT) & 0x1) | |
db7bf105 | 27896 | && value >= 0 && value <= 0xffff) |
bada4342 JW |
27897 | { |
27898 | /* Toggle bit[25] to change encoding from T2 to T3. */ | |
27899 | newval ^= 1 << 25; | |
27900 | /* Clear bits[19:16]. */ | |
27901 | newval &= 0xfff0ffff; | |
27902 | /* Encoding high 4bits imm. Code below will encode the | |
27903 | remaining low 12bits. */ | |
27904 | newval |= (value & 0x0000f000) << 4; | |
27905 | newimm = value & 0x00000fff; | |
40f246e3 | 27906 | } |
e9f89963 | 27907 | } |
92e90b6e | 27908 | } |
cc8a6dd0 | 27909 | |
c19d1205 | 27910 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 27911 | { |
c19d1205 ZW |
27912 | as_bad_where (fixP->fx_file, fixP->fx_line, |
27913 | _("invalid constant (%lx) after fixup"), | |
27914 | (unsigned long) value); | |
27915 | break; | |
3631a3c8 NC |
27916 | } |
27917 | ||
c19d1205 ZW |
27918 | newval |= (newimm & 0x800) << 15; |
27919 | newval |= (newimm & 0x700) << 4; | |
27920 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 27921 | |
c19d1205 ZW |
27922 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
27923 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
27924 | break; | |
a737bd4d | 27925 | |
3eb17e6b | 27926 | case BFD_RELOC_ARM_SMC: |
ba85f98c | 27927 | if (((unsigned long) value) > 0xf) |
c19d1205 | 27928 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3eb17e6b | 27929 | _("invalid smc expression")); |
ba85f98c | 27930 | |
2fc8bdac | 27931 | newval = md_chars_to_number (buf, INSN_SIZE); |
ba85f98c | 27932 | newval |= (value & 0xf); |
c19d1205 ZW |
27933 | md_number_to_chars (buf, newval, INSN_SIZE); |
27934 | break; | |
a737bd4d | 27935 | |
90ec0d68 MGD |
27936 | case BFD_RELOC_ARM_HVC: |
27937 | if (((unsigned long) value) > 0xffff) | |
27938 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27939 | _("invalid hvc expression")); | |
27940 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27941 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
27942 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27943 | break; | |
27944 | ||
c19d1205 | 27945 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 27946 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
27947 | { |
27948 | if (((unsigned long) value) > 0xff) | |
27949 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27950 | _("invalid swi expression")); | |
2fc8bdac | 27951 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
27952 | newval |= value; |
27953 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
27954 | } | |
27955 | else | |
27956 | { | |
27957 | if (((unsigned long) value) > 0x00ffffff) | |
27958 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27959 | _("invalid swi expression")); | |
2fc8bdac | 27960 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
27961 | newval |= value; |
27962 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27963 | } | |
27964 | break; | |
a737bd4d | 27965 | |
c19d1205 ZW |
27966 | case BFD_RELOC_ARM_MULTI: |
27967 | if (((unsigned long) value) > 0xffff) | |
27968 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
27969 | _("invalid expression in load/store multiple")); | |
27970 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
27971 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27972 | break; | |
a737bd4d | 27973 | |
c19d1205 | 27974 | #ifdef OBJ_ELF |
39b41c9c | 27975 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
27976 | |
27977 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
27978 | && fixP->fx_addsy | |
34e77a92 | 27979 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
27980 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
27981 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
27982 | /* Flip the bl to blx. This is a simple flip | |
27983 | bit here because we generate PCREL_CALL for | |
27984 | unconditional bls. */ | |
27985 | { | |
27986 | newval = md_chars_to_number (buf, INSN_SIZE); | |
27987 | newval = newval | 0x10000000; | |
27988 | md_number_to_chars (buf, newval, INSN_SIZE); | |
27989 | temp = 1; | |
27990 | fixP->fx_done = 1; | |
27991 | } | |
39b41c9c PB |
27992 | else |
27993 | temp = 3; | |
27994 | goto arm_branch_common; | |
27995 | ||
27996 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
27997 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
27998 | && fixP->fx_addsy | |
34e77a92 | 27999 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28000 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
28001 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
28002 | { | |
28003 | /* This would map to a bl<cond>, b<cond>, | |
28004 | b<always> to a Thumb function. We | |
28005 | need to force a relocation for this particular | |
28006 | case. */ | |
28007 | newval = md_chars_to_number (buf, INSN_SIZE); | |
28008 | fixP->fx_done = 0; | |
28009 | } | |
1a0670f3 | 28010 | /* Fall through. */ |
267bf995 | 28011 | |
2fc8bdac | 28012 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 28013 | #endif |
39b41c9c PB |
28014 | case BFD_RELOC_ARM_PCREL_BRANCH: |
28015 | temp = 3; | |
28016 | goto arm_branch_common; | |
a737bd4d | 28017 | |
39b41c9c | 28018 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 28019 | |
39b41c9c | 28020 | temp = 1; |
267bf995 RR |
28021 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
28022 | && fixP->fx_addsy | |
34e77a92 | 28023 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28024 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
28025 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
28026 | { | |
28027 | /* Flip the blx to a bl and warn. */ | |
28028 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
28029 | newval = 0xeb000000; | |
28030 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
28031 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
28032 | name); | |
28033 | md_number_to_chars (buf, newval, INSN_SIZE); | |
28034 | temp = 3; | |
28035 | fixP->fx_done = 1; | |
28036 | } | |
28037 | ||
28038 | #ifdef OBJ_ELF | |
28039 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 28040 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
28041 | #endif |
28042 | ||
39b41c9c | 28043 | arm_branch_common: |
c19d1205 | 28044 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
28045 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
28046 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
de194d85 | 28047 | also be clear. */ |
39b41c9c | 28048 | if (value & temp) |
c19d1205 | 28049 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
28050 | _("misaligned branch destination")); |
28051 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
28052 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 28053 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 28054 | |
2fc8bdac | 28055 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 28056 | { |
2fc8bdac ZW |
28057 | newval = md_chars_to_number (buf, INSN_SIZE); |
28058 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
28059 | /* Set the H bit on BLX instructions. */ |
28060 | if (temp == 1) | |
28061 | { | |
28062 | if (value & 2) | |
28063 | newval |= 0x01000000; | |
28064 | else | |
28065 | newval &= ~0x01000000; | |
28066 | } | |
2fc8bdac | 28067 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 28068 | } |
c19d1205 | 28069 | break; |
a737bd4d | 28070 | |
25fe350b MS |
28071 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
28072 | /* CBZ can only branch forward. */ | |
a737bd4d | 28073 | |
738755b0 | 28074 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
28075 | (which, strictly speaking, are prohibited) will be turned into |
28076 | no-ops. | |
738755b0 MS |
28077 | |
28078 | FIXME: It may be better to remove the instruction completely and | |
28079 | perform relaxation. */ | |
28080 | if (value == -2) | |
2fc8bdac ZW |
28081 | { |
28082 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 28083 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
28084 | md_number_to_chars (buf, newval, THUMB_SIZE); |
28085 | } | |
738755b0 MS |
28086 | else |
28087 | { | |
28088 | if (value & ~0x7e) | |
08f10d51 | 28089 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 28090 | |
477330fc | 28091 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
28092 | { |
28093 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28094 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
28095 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28096 | } | |
28097 | } | |
c19d1205 | 28098 | break; |
a737bd4d | 28099 | |
c19d1205 | 28100 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
e8f8842d | 28101 | if (out_of_range_p (value, 8)) |
08f10d51 | 28102 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 28103 | |
2fc8bdac ZW |
28104 | if (fixP->fx_done || !seg->use_rela_p) |
28105 | { | |
28106 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28107 | newval |= (value & 0x1ff) >> 1; | |
28108 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28109 | } | |
c19d1205 | 28110 | break; |
a737bd4d | 28111 | |
c19d1205 | 28112 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
e8f8842d | 28113 | if (out_of_range_p (value, 11)) |
08f10d51 | 28114 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 28115 | |
2fc8bdac ZW |
28116 | if (fixP->fx_done || !seg->use_rela_p) |
28117 | { | |
28118 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28119 | newval |= (value & 0xfff) >> 1; | |
28120 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28121 | } | |
c19d1205 | 28122 | break; |
a737bd4d | 28123 | |
e8f8842d | 28124 | /* This relocation is misnamed, it should be BRANCH21. */ |
c19d1205 | 28125 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
28126 | if (fixP->fx_addsy |
28127 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 28128 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28129 | && ARM_IS_FUNC (fixP->fx_addsy) |
28130 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
28131 | { | |
28132 | /* Force a relocation for a branch 20 bits wide. */ | |
28133 | fixP->fx_done = 0; | |
28134 | } | |
e8f8842d | 28135 | if (out_of_range_p (value, 20)) |
2fc8bdac ZW |
28136 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28137 | _("conditional branch out of range")); | |
404ff6b5 | 28138 | |
2fc8bdac ZW |
28139 | if (fixP->fx_done || !seg->use_rela_p) |
28140 | { | |
28141 | offsetT newval2; | |
28142 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 28143 | |
2fc8bdac ZW |
28144 | S = (value & 0x00100000) >> 20; |
28145 | J2 = (value & 0x00080000) >> 19; | |
28146 | J1 = (value & 0x00040000) >> 18; | |
28147 | hi = (value & 0x0003f000) >> 12; | |
28148 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 28149 | |
2fc8bdac ZW |
28150 | newval = md_chars_to_number (buf, THUMB_SIZE); |
28151 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28152 | newval |= (S << 10) | hi; | |
28153 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
28154 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28155 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
28156 | } | |
c19d1205 | 28157 | break; |
6c43fab6 | 28158 | |
c19d1205 | 28159 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
28160 | /* If there is a blx from a thumb state function to |
28161 | another thumb function flip this to a bl and warn | |
28162 | about it. */ | |
28163 | ||
28164 | if (fixP->fx_addsy | |
34e77a92 | 28165 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28166 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
28167 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
28168 | { | |
28169 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
28170 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
28171 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
28172 | name); | |
28173 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28174 | newval = newval | 0x1000; | |
28175 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
28176 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
28177 | fixP->fx_done = 1; | |
28178 | } | |
28179 | ||
28180 | ||
28181 | goto thumb_bl_common; | |
28182 | ||
c19d1205 | 28183 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
28184 | /* A bl from Thumb state ISA to an internal ARM state function |
28185 | is converted to a blx. */ | |
28186 | if (fixP->fx_addsy | |
28187 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 28188 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
28189 | && ARM_IS_FUNC (fixP->fx_addsy) |
28190 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
28191 | { | |
28192 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28193 | newval = newval & ~0x1000; | |
28194 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
28195 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
28196 | fixP->fx_done = 1; | |
28197 | } | |
28198 | ||
28199 | thumb_bl_common: | |
28200 | ||
2fc8bdac ZW |
28201 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
28202 | /* For a BLX instruction, make sure that the relocation is rounded up | |
28203 | to a word boundary. This follows the semantics of the instruction | |
28204 | which specifies that bit 1 of the target address will come from bit | |
28205 | 1 of the base address. */ | |
d406f3e4 JB |
28206 | value = (value + 3) & ~ 3; |
28207 | ||
28208 | #ifdef OBJ_ELF | |
28209 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
28210 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
28211 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
28212 | #endif | |
404ff6b5 | 28213 | |
e8f8842d | 28214 | if (out_of_range_p (value, 22)) |
2b2f5df9 | 28215 | { |
fc289b0a | 28216 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))) |
2b2f5df9 | 28217 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
e8f8842d | 28218 | else if (out_of_range_p (value, 24)) |
2b2f5df9 NC |
28219 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28220 | _("Thumb2 branch out of range")); | |
28221 | } | |
4a42ebbc RR |
28222 | |
28223 | if (fixP->fx_done || !seg->use_rela_p) | |
28224 | encode_thumb2_b_bl_offset (buf, value); | |
28225 | ||
c19d1205 | 28226 | break; |
404ff6b5 | 28227 | |
c19d1205 | 28228 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
e8f8842d | 28229 | if (out_of_range_p (value, 24)) |
08f10d51 | 28230 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
6c43fab6 | 28231 | |
2fc8bdac | 28232 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 28233 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 28234 | |
2fc8bdac | 28235 | break; |
a737bd4d | 28236 | |
2fc8bdac ZW |
28237 | case BFD_RELOC_8: |
28238 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 28239 | *buf = value; |
c19d1205 | 28240 | break; |
a737bd4d | 28241 | |
c19d1205 | 28242 | case BFD_RELOC_16: |
2fc8bdac | 28243 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 28244 | md_number_to_chars (buf, value, 2); |
c19d1205 | 28245 | break; |
a737bd4d | 28246 | |
c19d1205 | 28247 | #ifdef OBJ_ELF |
0855e32b NS |
28248 | case BFD_RELOC_ARM_TLS_CALL: |
28249 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
28250 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
28251 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 28252 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
28253 | case BFD_RELOC_ARM_TLS_GD32: |
28254 | case BFD_RELOC_ARM_TLS_LE32: | |
28255 | case BFD_RELOC_ARM_TLS_IE32: | |
28256 | case BFD_RELOC_ARM_TLS_LDM32: | |
28257 | case BFD_RELOC_ARM_TLS_LDO32: | |
28258 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 28259 | break; |
6c43fab6 | 28260 | |
5c5a4843 CL |
28261 | /* Same handling as above, but with the arm_fdpic guard. */ |
28262 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: | |
28263 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: | |
28264 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: | |
28265 | if (arm_fdpic) | |
28266 | { | |
28267 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
28268 | } | |
28269 | else | |
28270 | { | |
28271 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28272 | _("Relocation supported only in FDPIC mode")); | |
28273 | } | |
28274 | break; | |
28275 | ||
c19d1205 ZW |
28276 | case BFD_RELOC_ARM_GOT32: |
28277 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 28278 | break; |
b43420e6 NC |
28279 | |
28280 | case BFD_RELOC_ARM_GOT_PREL: | |
28281 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 28282 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
28283 | break; |
28284 | ||
9a6f4e97 NS |
28285 | case BFD_RELOC_ARM_TARGET2: |
28286 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
28287 | addend here for REL targets, because it won't be written out |
28288 | during reloc processing later. */ | |
9a6f4e97 NS |
28289 | if (fixP->fx_done || !seg->use_rela_p) |
28290 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
28291 | break; | |
188fd7ae CL |
28292 | |
28293 | /* Relocations for FDPIC. */ | |
28294 | case BFD_RELOC_ARM_GOTFUNCDESC: | |
28295 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: | |
28296 | case BFD_RELOC_ARM_FUNCDESC: | |
28297 | if (arm_fdpic) | |
28298 | { | |
28299 | if (fixP->fx_done || !seg->use_rela_p) | |
28300 | md_number_to_chars (buf, 0, 4); | |
28301 | } | |
28302 | else | |
28303 | { | |
28304 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28305 | _("Relocation supported only in FDPIC mode")); | |
28306 | } | |
28307 | break; | |
c19d1205 | 28308 | #endif |
6c43fab6 | 28309 | |
c19d1205 ZW |
28310 | case BFD_RELOC_RVA: |
28311 | case BFD_RELOC_32: | |
28312 | case BFD_RELOC_ARM_TARGET1: | |
28313 | case BFD_RELOC_ARM_ROSEGREL32: | |
28314 | case BFD_RELOC_ARM_SBREL32: | |
28315 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
28316 | #ifdef TE_PE |
28317 | case BFD_RELOC_32_SECREL: | |
28318 | #endif | |
2fc8bdac | 28319 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
28320 | #ifdef TE_WINCE |
28321 | /* For WinCE we only do this for pcrel fixups. */ | |
28322 | if (fixP->fx_done || fixP->fx_pcrel) | |
28323 | #endif | |
28324 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 28325 | break; |
6c43fab6 | 28326 | |
c19d1205 ZW |
28327 | #ifdef OBJ_ELF |
28328 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 28329 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
28330 | { |
28331 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
28332 | if ((value ^ (value >> 1)) & 0x40000000) | |
28333 | { | |
28334 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28335 | _("rel31 relocation overflow")); | |
28336 | } | |
28337 | newval |= value & 0x7fffffff; | |
28338 | md_number_to_chars (buf, newval, 4); | |
28339 | } | |
28340 | break; | |
c19d1205 | 28341 | #endif |
a737bd4d | 28342 | |
c19d1205 | 28343 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 28344 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
32c36c3c | 28345 | case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM: |
9db2f6b4 RL |
28346 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM) |
28347 | newval = md_chars_to_number (buf, INSN_SIZE); | |
28348 | else | |
28349 | newval = get_thumb32_insn (buf); | |
28350 | if ((newval & 0x0f200f00) == 0x0d000900) | |
28351 | { | |
28352 | /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic | |
28353 | has permitted values that are multiples of 2, in the range 0 | |
28354 | to 510. */ | |
28355 | if (value < -510 || value > 510 || (value & 1)) | |
28356 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28357 | _("co-processor offset out of range")); | |
28358 | } | |
32c36c3c AV |
28359 | else if ((newval & 0xfe001f80) == 0xec000f80) |
28360 | { | |
28361 | if (value < -511 || value > 512 || (value & 3)) | |
28362 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28363 | _("co-processor offset out of range")); | |
28364 | } | |
9db2f6b4 | 28365 | else if (value < -1023 || value > 1023 || (value & 3)) |
c19d1205 ZW |
28366 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28367 | _("co-processor offset out of range")); | |
28368 | cp_off_common: | |
26d97720 | 28369 | sign = value > 0; |
c19d1205 ZW |
28370 | if (value < 0) |
28371 | value = -value; | |
8f06b2d8 PB |
28372 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
28373 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
28374 | newval = md_chars_to_number (buf, INSN_SIZE); | |
28375 | else | |
28376 | newval = get_thumb32_insn (buf); | |
26d97720 | 28377 | if (value == 0) |
32c36c3c AV |
28378 | { |
28379 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM) | |
28380 | newval &= 0xffffff80; | |
28381 | else | |
28382 | newval &= 0xffffff00; | |
28383 | } | |
26d97720 NS |
28384 | else |
28385 | { | |
32c36c3c AV |
28386 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM) |
28387 | newval &= 0xff7fff80; | |
28388 | else | |
28389 | newval &= 0xff7fff00; | |
9db2f6b4 RL |
28390 | if ((newval & 0x0f200f00) == 0x0d000900) |
28391 | { | |
28392 | /* This is a fp16 vstr/vldr. | |
28393 | ||
28394 | It requires the immediate offset in the instruction is shifted | |
28395 | left by 1 to be a half-word offset. | |
28396 | ||
28397 | Here, left shift by 1 first, and later right shift by 2 | |
28398 | should get the right offset. */ | |
28399 | value <<= 1; | |
28400 | } | |
26d97720 NS |
28401 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
28402 | } | |
8f06b2d8 PB |
28403 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
28404 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
28405 | md_number_to_chars (buf, newval, INSN_SIZE); | |
28406 | else | |
28407 | put_thumb32_insn (buf, newval); | |
c19d1205 | 28408 | break; |
a737bd4d | 28409 | |
c19d1205 | 28410 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 28411 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
28412 | if (value < -255 || value > 255) |
28413 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28414 | _("co-processor offset out of range")); | |
df7849c5 | 28415 | value *= 4; |
c19d1205 | 28416 | goto cp_off_common; |
6c43fab6 | 28417 | |
c19d1205 ZW |
28418 | case BFD_RELOC_ARM_THUMB_OFFSET: |
28419 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28420 | /* Exactly what ranges, and where the offset is inserted depends | |
28421 | on the type of instruction, we can establish this from the | |
28422 | top 4 bits. */ | |
28423 | switch (newval >> 12) | |
28424 | { | |
28425 | case 4: /* PC load. */ | |
28426 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
28427 | forced to zero for these loads; md_pcrel_from has already | |
28428 | compensated for this. */ | |
28429 | if (value & 3) | |
28430 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28431 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
28432 | (((unsigned long) fixP->fx_frag->fr_address |
28433 | + (unsigned long) fixP->fx_where) & ~3) | |
28434 | + (unsigned long) value); | |
a737bd4d | 28435 | |
c19d1205 ZW |
28436 | if (value & ~0x3fc) |
28437 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28438 | _("invalid offset, value too big (0x%08lX)"), | |
28439 | (long) value); | |
a737bd4d | 28440 | |
c19d1205 ZW |
28441 | newval |= value >> 2; |
28442 | break; | |
a737bd4d | 28443 | |
c19d1205 ZW |
28444 | case 9: /* SP load/store. */ |
28445 | if (value & ~0x3fc) | |
28446 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28447 | _("invalid offset, value too big (0x%08lX)"), | |
28448 | (long) value); | |
28449 | newval |= value >> 2; | |
28450 | break; | |
6c43fab6 | 28451 | |
c19d1205 ZW |
28452 | case 6: /* Word load/store. */ |
28453 | if (value & ~0x7c) | |
28454 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28455 | _("invalid offset, value too big (0x%08lX)"), | |
28456 | (long) value); | |
28457 | newval |= value << 4; /* 6 - 2. */ | |
28458 | break; | |
a737bd4d | 28459 | |
c19d1205 ZW |
28460 | case 7: /* Byte load/store. */ |
28461 | if (value & ~0x1f) | |
28462 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28463 | _("invalid offset, value too big (0x%08lX)"), | |
28464 | (long) value); | |
28465 | newval |= value << 6; | |
28466 | break; | |
a737bd4d | 28467 | |
c19d1205 ZW |
28468 | case 8: /* Halfword load/store. */ |
28469 | if (value & ~0x3e) | |
28470 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28471 | _("invalid offset, value too big (0x%08lX)"), | |
28472 | (long) value); | |
28473 | newval |= value << 5; /* 6 - 1. */ | |
28474 | break; | |
a737bd4d | 28475 | |
c19d1205 ZW |
28476 | default: |
28477 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28478 | "Unable to process relocation for thumb opcode: %lx", | |
28479 | (unsigned long) newval); | |
28480 | break; | |
28481 | } | |
28482 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28483 | break; | |
a737bd4d | 28484 | |
c19d1205 ZW |
28485 | case BFD_RELOC_ARM_THUMB_ADD: |
28486 | /* This is a complicated relocation, since we use it for all of | |
28487 | the following immediate relocations: | |
a737bd4d | 28488 | |
c19d1205 ZW |
28489 | 3bit ADD/SUB |
28490 | 8bit ADD/SUB | |
28491 | 9bit ADD/SUB SP word-aligned | |
28492 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 28493 | |
c19d1205 ZW |
28494 | The type of instruction being processed is encoded in the |
28495 | instruction field: | |
a737bd4d | 28496 | |
c19d1205 ZW |
28497 | 0x8000 SUB |
28498 | 0x00F0 Rd | |
28499 | 0x000F Rs | |
28500 | */ | |
28501 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28502 | { | |
28503 | int rd = (newval >> 4) & 0xf; | |
28504 | int rs = newval & 0xf; | |
28505 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 28506 | |
c19d1205 ZW |
28507 | /* Check for HI regs, only very restricted cases allowed: |
28508 | Adjusting SP, and using PC or SP to get an address. */ | |
28509 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
28510 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
28511 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28512 | _("invalid Hi register with immediate")); | |
a737bd4d | 28513 | |
c19d1205 ZW |
28514 | /* If value is negative, choose the opposite instruction. */ |
28515 | if (value < 0) | |
28516 | { | |
28517 | value = -value; | |
28518 | subtract = !subtract; | |
28519 | if (value < 0) | |
28520 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28521 | _("immediate value out of range")); | |
28522 | } | |
a737bd4d | 28523 | |
c19d1205 ZW |
28524 | if (rd == REG_SP) |
28525 | { | |
75c11999 | 28526 | if (value & ~0x1fc) |
c19d1205 ZW |
28527 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28528 | _("invalid immediate for stack address calculation")); | |
28529 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
28530 | newval |= value >> 2; | |
28531 | } | |
28532 | else if (rs == REG_PC || rs == REG_SP) | |
28533 | { | |
c12d2c9d NC |
28534 | /* PR gas/18541. If the addition is for a defined symbol |
28535 | within range of an ADR instruction then accept it. */ | |
28536 | if (subtract | |
28537 | && value == 4 | |
28538 | && fixP->fx_addsy != NULL) | |
28539 | { | |
28540 | subtract = 0; | |
28541 | ||
28542 | if (! S_IS_DEFINED (fixP->fx_addsy) | |
28543 | || S_GET_SEGMENT (fixP->fx_addsy) != seg | |
28544 | || S_IS_WEAK (fixP->fx_addsy)) | |
28545 | { | |
28546 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28547 | _("address calculation needs a strongly defined nearby symbol")); | |
28548 | } | |
28549 | else | |
28550 | { | |
28551 | offsetT v = fixP->fx_where + fixP->fx_frag->fr_address; | |
28552 | ||
28553 | /* Round up to the next 4-byte boundary. */ | |
28554 | if (v & 3) | |
28555 | v = (v + 3) & ~ 3; | |
28556 | else | |
28557 | v += 4; | |
28558 | v = S_GET_VALUE (fixP->fx_addsy) - v; | |
28559 | ||
28560 | if (v & ~0x3fc) | |
28561 | { | |
28562 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28563 | _("symbol too far away")); | |
28564 | } | |
28565 | else | |
28566 | { | |
28567 | fixP->fx_done = 1; | |
28568 | value = v; | |
28569 | } | |
28570 | } | |
28571 | } | |
28572 | ||
c19d1205 ZW |
28573 | if (subtract || value & ~0x3fc) |
28574 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28575 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
5fc177c8 | 28576 | (unsigned long) (subtract ? - value : value)); |
c19d1205 ZW |
28577 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); |
28578 | newval |= rd << 8; | |
28579 | newval |= value >> 2; | |
28580 | } | |
28581 | else if (rs == rd) | |
28582 | { | |
28583 | if (value & ~0xff) | |
28584 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28585 | _("immediate value out of range")); | |
28586 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
28587 | newval |= (rd << 8) | value; | |
28588 | } | |
28589 | else | |
28590 | { | |
28591 | if (value & ~0x7) | |
28592 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28593 | _("immediate value out of range")); | |
28594 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
28595 | newval |= rd | (rs << 3) | (value << 6); | |
28596 | } | |
28597 | } | |
28598 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28599 | break; | |
a737bd4d | 28600 | |
c19d1205 ZW |
28601 | case BFD_RELOC_ARM_THUMB_IMM: |
28602 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28603 | if (value < 0 || value > 255) | |
28604 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 28605 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
28606 | (long) value); |
28607 | newval |= value; | |
28608 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28609 | break; | |
a737bd4d | 28610 | |
c19d1205 ZW |
28611 | case BFD_RELOC_ARM_THUMB_SHIFT: |
28612 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
28613 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
28614 | temp = newval & 0xf800; | |
28615 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
28616 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28617 | _("invalid shift value: %ld"), (long) value); | |
28618 | /* Shifts of zero must be encoded as LSL. */ | |
28619 | if (value == 0) | |
28620 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
28621 | /* Shifts of 32 are encoded as zero. */ | |
28622 | else if (value == 32) | |
28623 | value = 0; | |
28624 | newval |= value << 6; | |
28625 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28626 | break; | |
a737bd4d | 28627 | |
c19d1205 ZW |
28628 | case BFD_RELOC_VTABLE_INHERIT: |
28629 | case BFD_RELOC_VTABLE_ENTRY: | |
28630 | fixP->fx_done = 0; | |
28631 | return; | |
6c43fab6 | 28632 | |
b6895b4f PB |
28633 | case BFD_RELOC_ARM_MOVW: |
28634 | case BFD_RELOC_ARM_MOVT: | |
28635 | case BFD_RELOC_ARM_THUMB_MOVW: | |
28636 | case BFD_RELOC_ARM_THUMB_MOVT: | |
28637 | if (fixP->fx_done || !seg->use_rela_p) | |
28638 | { | |
28639 | /* REL format relocations are limited to a 16-bit addend. */ | |
28640 | if (!fixP->fx_done) | |
28641 | { | |
39623e12 | 28642 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 28643 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 28644 | _("offset out of range")); |
b6895b4f PB |
28645 | } |
28646 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
28647 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
28648 | { | |
28649 | value >>= 16; | |
28650 | } | |
28651 | ||
28652 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
28653 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
28654 | { | |
28655 | newval = get_thumb32_insn (buf); | |
28656 | newval &= 0xfbf08f00; | |
28657 | newval |= (value & 0xf000) << 4; | |
28658 | newval |= (value & 0x0800) << 15; | |
28659 | newval |= (value & 0x0700) << 4; | |
28660 | newval |= (value & 0x00ff); | |
28661 | put_thumb32_insn (buf, newval); | |
28662 | } | |
28663 | else | |
28664 | { | |
28665 | newval = md_chars_to_number (buf, 4); | |
28666 | newval &= 0xfff0f000; | |
28667 | newval |= value & 0x0fff; | |
28668 | newval |= (value & 0xf000) << 4; | |
28669 | md_number_to_chars (buf, newval, 4); | |
28670 | } | |
28671 | } | |
28672 | return; | |
28673 | ||
72d98d16 MG |
28674 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
28675 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: | |
28676 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: | |
28677 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: | |
28678 | gas_assert (!fixP->fx_done); | |
28679 | { | |
28680 | bfd_vma insn; | |
28681 | bfd_boolean is_mov; | |
28682 | bfd_vma encoded_addend = value; | |
28683 | ||
28684 | /* Check that addend can be encoded in instruction. */ | |
28685 | if (!seg->use_rela_p && (value < 0 || value > 255)) | |
28686 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28687 | _("the offset 0x%08lX is not representable"), | |
28688 | (unsigned long) encoded_addend); | |
28689 | ||
28690 | /* Extract the instruction. */ | |
28691 | insn = md_chars_to_number (buf, THUMB_SIZE); | |
28692 | is_mov = (insn & 0xf800) == 0x2000; | |
28693 | ||
28694 | /* Encode insn. */ | |
28695 | if (is_mov) | |
28696 | { | |
28697 | if (!seg->use_rela_p) | |
28698 | insn |= encoded_addend; | |
28699 | } | |
28700 | else | |
28701 | { | |
28702 | int rd, rs; | |
28703 | ||
28704 | /* Extract the instruction. */ | |
28705 | /* Encoding is the following | |
28706 | 0x8000 SUB | |
28707 | 0x00F0 Rd | |
28708 | 0x000F Rs | |
28709 | */ | |
28710 | /* The following conditions must be true : | |
28711 | - ADD | |
28712 | - Rd == Rs | |
28713 | - Rd <= 7 | |
28714 | */ | |
28715 | rd = (insn >> 4) & 0xf; | |
28716 | rs = insn & 0xf; | |
28717 | if ((insn & 0x8000) || (rd != rs) || rd > 7) | |
28718 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28719 | _("Unable to process relocation for thumb opcode: %lx"), | |
28720 | (unsigned long) insn); | |
28721 | ||
28722 | /* Encode as ADD immediate8 thumb 1 code. */ | |
28723 | insn = 0x3000 | (rd << 8); | |
28724 | ||
28725 | /* Place the encoded addend into the first 8 bits of the | |
28726 | instruction. */ | |
28727 | if (!seg->use_rela_p) | |
28728 | insn |= encoded_addend; | |
28729 | } | |
28730 | ||
28731 | /* Update the instruction. */ | |
28732 | md_number_to_chars (buf, insn, THUMB_SIZE); | |
28733 | } | |
28734 | break; | |
28735 | ||
4962c51a MS |
28736 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
28737 | case BFD_RELOC_ARM_ALU_PC_G0: | |
28738 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
28739 | case BFD_RELOC_ARM_ALU_PC_G1: | |
28740 | case BFD_RELOC_ARM_ALU_PC_G2: | |
28741 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
28742 | case BFD_RELOC_ARM_ALU_SB_G0: | |
28743 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
28744 | case BFD_RELOC_ARM_ALU_SB_G1: | |
28745 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 28746 | gas_assert (!fixP->fx_done); |
4962c51a MS |
28747 | if (!seg->use_rela_p) |
28748 | { | |
477330fc RM |
28749 | bfd_vma insn; |
28750 | bfd_vma encoded_addend; | |
3ca4a8ec | 28751 | bfd_vma addend_abs = llabs (value); |
477330fc RM |
28752 | |
28753 | /* Check that the absolute value of the addend can be | |
28754 | expressed as an 8-bit constant plus a rotation. */ | |
28755 | encoded_addend = encode_arm_immediate (addend_abs); | |
28756 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 28757 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28758 | _("the offset 0x%08lX is not representable"), |
28759 | (unsigned long) addend_abs); | |
28760 | ||
28761 | /* Extract the instruction. */ | |
28762 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28763 | ||
28764 | /* If the addend is positive, use an ADD instruction. | |
28765 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
28766 | insn &= 0xff1fffff; | |
28767 | if (value < 0) | |
28768 | insn |= 1 << 22; | |
28769 | else | |
28770 | insn |= 1 << 23; | |
28771 | ||
28772 | /* Place the encoded addend into the first 12 bits of the | |
28773 | instruction. */ | |
28774 | insn &= 0xfffff000; | |
28775 | insn |= encoded_addend; | |
28776 | ||
28777 | /* Update the instruction. */ | |
28778 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
28779 | } |
28780 | break; | |
28781 | ||
28782 | case BFD_RELOC_ARM_LDR_PC_G0: | |
28783 | case BFD_RELOC_ARM_LDR_PC_G1: | |
28784 | case BFD_RELOC_ARM_LDR_PC_G2: | |
28785 | case BFD_RELOC_ARM_LDR_SB_G0: | |
28786 | case BFD_RELOC_ARM_LDR_SB_G1: | |
28787 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 28788 | gas_assert (!fixP->fx_done); |
4962c51a | 28789 | if (!seg->use_rela_p) |
477330fc RM |
28790 | { |
28791 | bfd_vma insn; | |
3ca4a8ec | 28792 | bfd_vma addend_abs = llabs (value); |
4962c51a | 28793 | |
477330fc RM |
28794 | /* Check that the absolute value of the addend can be |
28795 | encoded in 12 bits. */ | |
28796 | if (addend_abs >= 0x1000) | |
4962c51a | 28797 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28798 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
28799 | (unsigned long) addend_abs); | |
28800 | ||
28801 | /* Extract the instruction. */ | |
28802 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28803 | ||
28804 | /* If the addend is negative, clear bit 23 of the instruction. | |
28805 | Otherwise set it. */ | |
28806 | if (value < 0) | |
28807 | insn &= ~(1 << 23); | |
28808 | else | |
28809 | insn |= 1 << 23; | |
28810 | ||
28811 | /* Place the absolute value of the addend into the first 12 bits | |
28812 | of the instruction. */ | |
28813 | insn &= 0xfffff000; | |
28814 | insn |= addend_abs; | |
28815 | ||
28816 | /* Update the instruction. */ | |
28817 | md_number_to_chars (buf, insn, INSN_SIZE); | |
28818 | } | |
4962c51a MS |
28819 | break; |
28820 | ||
28821 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
28822 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
28823 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
28824 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
28825 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
28826 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 28827 | gas_assert (!fixP->fx_done); |
4962c51a | 28828 | if (!seg->use_rela_p) |
477330fc RM |
28829 | { |
28830 | bfd_vma insn; | |
3ca4a8ec | 28831 | bfd_vma addend_abs = llabs (value); |
4962c51a | 28832 | |
477330fc RM |
28833 | /* Check that the absolute value of the addend can be |
28834 | encoded in 8 bits. */ | |
28835 | if (addend_abs >= 0x100) | |
4962c51a | 28836 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28837 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
28838 | (unsigned long) addend_abs); | |
28839 | ||
28840 | /* Extract the instruction. */ | |
28841 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28842 | ||
28843 | /* If the addend is negative, clear bit 23 of the instruction. | |
28844 | Otherwise set it. */ | |
28845 | if (value < 0) | |
28846 | insn &= ~(1 << 23); | |
28847 | else | |
28848 | insn |= 1 << 23; | |
28849 | ||
28850 | /* Place the first four bits of the absolute value of the addend | |
28851 | into the first 4 bits of the instruction, and the remaining | |
28852 | four into bits 8 .. 11. */ | |
28853 | insn &= 0xfffff0f0; | |
28854 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
28855 | ||
28856 | /* Update the instruction. */ | |
28857 | md_number_to_chars (buf, insn, INSN_SIZE); | |
28858 | } | |
4962c51a MS |
28859 | break; |
28860 | ||
28861 | case BFD_RELOC_ARM_LDC_PC_G0: | |
28862 | case BFD_RELOC_ARM_LDC_PC_G1: | |
28863 | case BFD_RELOC_ARM_LDC_PC_G2: | |
28864 | case BFD_RELOC_ARM_LDC_SB_G0: | |
28865 | case BFD_RELOC_ARM_LDC_SB_G1: | |
28866 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 28867 | gas_assert (!fixP->fx_done); |
4962c51a | 28868 | if (!seg->use_rela_p) |
477330fc RM |
28869 | { |
28870 | bfd_vma insn; | |
3ca4a8ec | 28871 | bfd_vma addend_abs = llabs (value); |
4962c51a | 28872 | |
477330fc RM |
28873 | /* Check that the absolute value of the addend is a multiple of |
28874 | four and, when divided by four, fits in 8 bits. */ | |
28875 | if (addend_abs & 0x3) | |
4962c51a | 28876 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28877 | _("bad offset 0x%08lX (must be word-aligned)"), |
28878 | (unsigned long) addend_abs); | |
4962c51a | 28879 | |
477330fc | 28880 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 28881 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
28882 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
28883 | (unsigned long) addend_abs); | |
28884 | ||
28885 | /* Extract the instruction. */ | |
28886 | insn = md_chars_to_number (buf, INSN_SIZE); | |
28887 | ||
28888 | /* If the addend is negative, clear bit 23 of the instruction. | |
28889 | Otherwise set it. */ | |
28890 | if (value < 0) | |
28891 | insn &= ~(1 << 23); | |
28892 | else | |
28893 | insn |= 1 << 23; | |
28894 | ||
28895 | /* Place the addend (divided by four) into the first eight | |
28896 | bits of the instruction. */ | |
28897 | insn &= 0xfffffff0; | |
28898 | insn |= addend_abs >> 2; | |
28899 | ||
28900 | /* Update the instruction. */ | |
28901 | md_number_to_chars (buf, insn, INSN_SIZE); | |
28902 | } | |
4962c51a MS |
28903 | break; |
28904 | ||
e12437dc AV |
28905 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
28906 | if (fixP->fx_addsy | |
28907 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28908 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28909 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28910 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28911 | { | |
28912 | /* Force a relocation for a branch 5 bits wide. */ | |
28913 | fixP->fx_done = 0; | |
28914 | } | |
28915 | if (v8_1_branch_value_check (value, 5, FALSE) == FAIL) | |
28916 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28917 | BAD_BRANCH_OFF); | |
28918 | ||
28919 | if (fixP->fx_done || !seg->use_rela_p) | |
28920 | { | |
28921 | addressT boff = value >> 1; | |
28922 | ||
28923 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28924 | newval |= (boff << 7); | |
28925 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28926 | } | |
28927 | break; | |
28928 | ||
f6b2b12d AV |
28929 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
28930 | if (fixP->fx_addsy | |
28931 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28932 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28933 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28934 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28935 | { | |
28936 | fixP->fx_done = 0; | |
28937 | } | |
28938 | if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f)) | |
28939 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28940 | _("branch out of range")); | |
28941 | ||
28942 | if (fixP->fx_done || !seg->use_rela_p) | |
28943 | { | |
28944 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28945 | ||
28946 | addressT boff = ((newval & 0x0780) >> 7) << 1; | |
28947 | addressT diff = value - boff; | |
28948 | ||
28949 | if (diff == 4) | |
28950 | { | |
28951 | newval |= 1 << 1; /* T bit. */ | |
28952 | } | |
28953 | else if (diff != 2) | |
28954 | { | |
28955 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28956 | _("out of range label-relative fixup value")); | |
28957 | } | |
28958 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28959 | } | |
28960 | break; | |
28961 | ||
e5d6e09e AV |
28962 | case BFD_RELOC_ARM_THUMB_BF17: |
28963 | if (fixP->fx_addsy | |
28964 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28965 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28966 | && ARM_IS_FUNC (fixP->fx_addsy) | |
28967 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
28968 | { | |
28969 | /* Force a relocation for a branch 17 bits wide. */ | |
28970 | fixP->fx_done = 0; | |
28971 | } | |
28972 | ||
28973 | if (v8_1_branch_value_check (value, 17, TRUE) == FAIL) | |
28974 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
28975 | BAD_BRANCH_OFF); | |
28976 | ||
28977 | if (fixP->fx_done || !seg->use_rela_p) | |
28978 | { | |
28979 | offsetT newval2; | |
28980 | addressT immA, immB, immC; | |
28981 | ||
28982 | immA = (value & 0x0001f000) >> 12; | |
28983 | immB = (value & 0x00000ffc) >> 2; | |
28984 | immC = (value & 0x00000002) >> 1; | |
28985 | ||
28986 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
28987 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
28988 | newval |= immA; | |
28989 | newval2 |= (immC << 11) | (immB << 1); | |
28990 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
28991 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
28992 | } | |
28993 | break; | |
28994 | ||
1caf72a5 AV |
28995 | case BFD_RELOC_ARM_THUMB_BF19: |
28996 | if (fixP->fx_addsy | |
28997 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
28998 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
28999 | && ARM_IS_FUNC (fixP->fx_addsy) | |
29000 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
29001 | { | |
29002 | /* Force a relocation for a branch 19 bits wide. */ | |
29003 | fixP->fx_done = 0; | |
29004 | } | |
29005 | ||
29006 | if (v8_1_branch_value_check (value, 19, TRUE) == FAIL) | |
29007 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
29008 | BAD_BRANCH_OFF); | |
29009 | ||
29010 | if (fixP->fx_done || !seg->use_rela_p) | |
29011 | { | |
29012 | offsetT newval2; | |
29013 | addressT immA, immB, immC; | |
29014 | ||
29015 | immA = (value & 0x0007f000) >> 12; | |
29016 | immB = (value & 0x00000ffc) >> 2; | |
29017 | immC = (value & 0x00000002) >> 1; | |
29018 | ||
29019 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
29020 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
29021 | newval |= immA; | |
29022 | newval2 |= (immC << 11) | (immB << 1); | |
29023 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
29024 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
29025 | } | |
29026 | break; | |
29027 | ||
1889da70 AV |
29028 | case BFD_RELOC_ARM_THUMB_BF13: |
29029 | if (fixP->fx_addsy | |
29030 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
29031 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
29032 | && ARM_IS_FUNC (fixP->fx_addsy) | |
29033 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
29034 | { | |
29035 | /* Force a relocation for a branch 13 bits wide. */ | |
29036 | fixP->fx_done = 0; | |
29037 | } | |
29038 | ||
29039 | if (v8_1_branch_value_check (value, 13, TRUE) == FAIL) | |
29040 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
29041 | BAD_BRANCH_OFF); | |
29042 | ||
29043 | if (fixP->fx_done || !seg->use_rela_p) | |
29044 | { | |
29045 | offsetT newval2; | |
29046 | addressT immA, immB, immC; | |
29047 | ||
29048 | immA = (value & 0x00001000) >> 12; | |
29049 | immB = (value & 0x00000ffc) >> 2; | |
29050 | immC = (value & 0x00000002) >> 1; | |
29051 | ||
29052 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
29053 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
29054 | newval |= immA; | |
29055 | newval2 |= (immC << 11) | (immB << 1); | |
29056 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
29057 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
29058 | } | |
29059 | break; | |
29060 | ||
60f993ce AV |
29061 | case BFD_RELOC_ARM_THUMB_LOOP12: |
29062 | if (fixP->fx_addsy | |
29063 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
29064 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
29065 | && ARM_IS_FUNC (fixP->fx_addsy) | |
29066 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) | |
29067 | { | |
29068 | /* Force a relocation for a branch 12 bits wide. */ | |
29069 | fixP->fx_done = 0; | |
29070 | } | |
29071 | ||
29072 | bfd_vma insn = get_thumb32_insn (buf); | |
1f6234a3 | 29073 | /* le lr, <label>, le <label> or letp lr, <label> */ |
60f993ce | 29074 | if (((insn & 0xffffffff) == 0xf00fc001) |
1f6234a3 AV |
29075 | || ((insn & 0xffffffff) == 0xf02fc001) |
29076 | || ((insn & 0xffffffff) == 0xf01fc001)) | |
60f993ce AV |
29077 | value = -value; |
29078 | ||
29079 | if (v8_1_branch_value_check (value, 12, FALSE) == FAIL) | |
29080 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
29081 | BAD_BRANCH_OFF); | |
29082 | if (fixP->fx_done || !seg->use_rela_p) | |
29083 | { | |
29084 | addressT imml, immh; | |
29085 | ||
29086 | immh = (value & 0x00000ffc) >> 2; | |
29087 | imml = (value & 0x00000002) >> 1; | |
29088 | ||
29089 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
29090 | newval |= (imml << 11) | (immh << 1); | |
29091 | md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE); | |
29092 | } | |
29093 | break; | |
29094 | ||
845b51d6 PB |
29095 | case BFD_RELOC_ARM_V4BX: |
29096 | /* This will need to go in the object file. */ | |
29097 | fixP->fx_done = 0; | |
29098 | break; | |
29099 | ||
c19d1205 ZW |
29100 | case BFD_RELOC_UNUSED: |
29101 | default: | |
29102 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
29103 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
29104 | } | |
6c43fab6 RE |
29105 | } |
29106 | ||
c19d1205 ZW |
29107 | /* Translate internal representation of relocation info to BFD target |
29108 | format. */ | |
a737bd4d | 29109 | |
c19d1205 | 29110 | arelent * |
00a97672 | 29111 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 29112 | { |
c19d1205 ZW |
29113 | arelent * reloc; |
29114 | bfd_reloc_code_real_type code; | |
a737bd4d | 29115 | |
325801bd | 29116 | reloc = XNEW (arelent); |
a737bd4d | 29117 | |
325801bd | 29118 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
c19d1205 ZW |
29119 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
29120 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 29121 | |
2fc8bdac | 29122 | if (fixp->fx_pcrel) |
00a97672 RS |
29123 | { |
29124 | if (section->use_rela_p) | |
29125 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
29126 | else | |
29127 | fixp->fx_offset = reloc->address; | |
29128 | } | |
c19d1205 | 29129 | reloc->addend = fixp->fx_offset; |
a737bd4d | 29130 | |
c19d1205 | 29131 | switch (fixp->fx_r_type) |
a737bd4d | 29132 | { |
c19d1205 ZW |
29133 | case BFD_RELOC_8: |
29134 | if (fixp->fx_pcrel) | |
29135 | { | |
29136 | code = BFD_RELOC_8_PCREL; | |
29137 | break; | |
29138 | } | |
1a0670f3 | 29139 | /* Fall through. */ |
a737bd4d | 29140 | |
c19d1205 ZW |
29141 | case BFD_RELOC_16: |
29142 | if (fixp->fx_pcrel) | |
29143 | { | |
29144 | code = BFD_RELOC_16_PCREL; | |
29145 | break; | |
29146 | } | |
1a0670f3 | 29147 | /* Fall through. */ |
6c43fab6 | 29148 | |
c19d1205 ZW |
29149 | case BFD_RELOC_32: |
29150 | if (fixp->fx_pcrel) | |
29151 | { | |
29152 | code = BFD_RELOC_32_PCREL; | |
29153 | break; | |
29154 | } | |
1a0670f3 | 29155 | /* Fall through. */ |
a737bd4d | 29156 | |
b6895b4f PB |
29157 | case BFD_RELOC_ARM_MOVW: |
29158 | if (fixp->fx_pcrel) | |
29159 | { | |
29160 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
29161 | break; | |
29162 | } | |
1a0670f3 | 29163 | /* Fall through. */ |
b6895b4f PB |
29164 | |
29165 | case BFD_RELOC_ARM_MOVT: | |
29166 | if (fixp->fx_pcrel) | |
29167 | { | |
29168 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
29169 | break; | |
29170 | } | |
1a0670f3 | 29171 | /* Fall through. */ |
b6895b4f PB |
29172 | |
29173 | case BFD_RELOC_ARM_THUMB_MOVW: | |
29174 | if (fixp->fx_pcrel) | |
29175 | { | |
29176 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
29177 | break; | |
29178 | } | |
1a0670f3 | 29179 | /* Fall through. */ |
b6895b4f PB |
29180 | |
29181 | case BFD_RELOC_ARM_THUMB_MOVT: | |
29182 | if (fixp->fx_pcrel) | |
29183 | { | |
29184 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
29185 | break; | |
29186 | } | |
1a0670f3 | 29187 | /* Fall through. */ |
b6895b4f | 29188 | |
c19d1205 ZW |
29189 | case BFD_RELOC_NONE: |
29190 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
29191 | case BFD_RELOC_ARM_PCREL_BLX: | |
29192 | case BFD_RELOC_RVA: | |
29193 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
29194 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
29195 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
29196 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
29197 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
29198 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
29199 | case BFD_RELOC_VTABLE_ENTRY: |
29200 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
29201 | #ifdef TE_PE |
29202 | case BFD_RELOC_32_SECREL: | |
29203 | #endif | |
c19d1205 ZW |
29204 | code = fixp->fx_r_type; |
29205 | break; | |
a737bd4d | 29206 | |
00adf2d4 JB |
29207 | case BFD_RELOC_THUMB_PCREL_BLX: |
29208 | #ifdef OBJ_ELF | |
29209 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
29210 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
29211 | else | |
29212 | #endif | |
29213 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
29214 | break; | |
29215 | ||
c19d1205 ZW |
29216 | case BFD_RELOC_ARM_LITERAL: |
29217 | case BFD_RELOC_ARM_HWLITERAL: | |
29218 | /* If this is called then the a literal has | |
29219 | been referenced across a section boundary. */ | |
29220 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29221 | _("literal referenced across section boundary")); | |
29222 | return NULL; | |
a737bd4d | 29223 | |
c19d1205 | 29224 | #ifdef OBJ_ELF |
0855e32b NS |
29225 | case BFD_RELOC_ARM_TLS_CALL: |
29226 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
29227 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
29228 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
29229 | case BFD_RELOC_ARM_GOT32: |
29230 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 29231 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
29232 | case BFD_RELOC_ARM_PLT32: |
29233 | case BFD_RELOC_ARM_TARGET1: | |
29234 | case BFD_RELOC_ARM_ROSEGREL32: | |
29235 | case BFD_RELOC_ARM_SBREL32: | |
29236 | case BFD_RELOC_ARM_PREL31: | |
29237 | case BFD_RELOC_ARM_TARGET2: | |
c19d1205 | 29238 | case BFD_RELOC_ARM_TLS_LDO32: |
39b41c9c PB |
29239 | case BFD_RELOC_ARM_PCREL_CALL: |
29240 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
29241 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
29242 | case BFD_RELOC_ARM_ALU_PC_G0: | |
29243 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
29244 | case BFD_RELOC_ARM_ALU_PC_G1: | |
29245 | case BFD_RELOC_ARM_ALU_PC_G2: | |
29246 | case BFD_RELOC_ARM_LDR_PC_G0: | |
29247 | case BFD_RELOC_ARM_LDR_PC_G1: | |
29248 | case BFD_RELOC_ARM_LDR_PC_G2: | |
29249 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
29250 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
29251 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
29252 | case BFD_RELOC_ARM_LDC_PC_G0: | |
29253 | case BFD_RELOC_ARM_LDC_PC_G1: | |
29254 | case BFD_RELOC_ARM_LDC_PC_G2: | |
29255 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
29256 | case BFD_RELOC_ARM_ALU_SB_G0: | |
29257 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
29258 | case BFD_RELOC_ARM_ALU_SB_G1: | |
29259 | case BFD_RELOC_ARM_ALU_SB_G2: | |
29260 | case BFD_RELOC_ARM_LDR_SB_G0: | |
29261 | case BFD_RELOC_ARM_LDR_SB_G1: | |
29262 | case BFD_RELOC_ARM_LDR_SB_G2: | |
29263 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
29264 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
29265 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
29266 | case BFD_RELOC_ARM_LDC_SB_G0: | |
29267 | case BFD_RELOC_ARM_LDC_SB_G1: | |
29268 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 29269 | case BFD_RELOC_ARM_V4BX: |
72d98d16 MG |
29270 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC: |
29271 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC: | |
29272 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC: | |
29273 | case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC: | |
188fd7ae CL |
29274 | case BFD_RELOC_ARM_GOTFUNCDESC: |
29275 | case BFD_RELOC_ARM_GOTOFFFUNCDESC: | |
29276 | case BFD_RELOC_ARM_FUNCDESC: | |
e5d6e09e | 29277 | case BFD_RELOC_ARM_THUMB_BF17: |
1caf72a5 | 29278 | case BFD_RELOC_ARM_THUMB_BF19: |
1889da70 | 29279 | case BFD_RELOC_ARM_THUMB_BF13: |
c19d1205 ZW |
29280 | code = fixp->fx_r_type; |
29281 | break; | |
a737bd4d | 29282 | |
0855e32b | 29283 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 | 29284 | case BFD_RELOC_ARM_TLS_GD32: |
5c5a4843 | 29285 | case BFD_RELOC_ARM_TLS_GD32_FDPIC: |
75c11999 | 29286 | case BFD_RELOC_ARM_TLS_LE32: |
c19d1205 | 29287 | case BFD_RELOC_ARM_TLS_IE32: |
5c5a4843 | 29288 | case BFD_RELOC_ARM_TLS_IE32_FDPIC: |
c19d1205 | 29289 | case BFD_RELOC_ARM_TLS_LDM32: |
5c5a4843 | 29290 | case BFD_RELOC_ARM_TLS_LDM32_FDPIC: |
c19d1205 ZW |
29291 | /* BFD will include the symbol's address in the addend. |
29292 | But we don't want that, so subtract it out again here. */ | |
29293 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
29294 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
29295 | code = fixp->fx_r_type; | |
29296 | break; | |
29297 | #endif | |
a737bd4d | 29298 | |
c19d1205 ZW |
29299 | case BFD_RELOC_ARM_IMMEDIATE: |
29300 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29301 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
29302 | return NULL; | |
a737bd4d | 29303 | |
c19d1205 ZW |
29304 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
29305 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29306 | _("ADRL used for a symbol not defined in the same file")); | |
29307 | return NULL; | |
a737bd4d | 29308 | |
e12437dc | 29309 | case BFD_RELOC_THUMB_PCREL_BRANCH5: |
f6b2b12d | 29310 | case BFD_RELOC_THUMB_PCREL_BFCSEL: |
60f993ce | 29311 | case BFD_RELOC_ARM_THUMB_LOOP12: |
e12437dc AV |
29312 | as_bad_where (fixp->fx_file, fixp->fx_line, |
29313 | _("%s used for a symbol not defined in the same file"), | |
29314 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
29315 | return NULL; | |
29316 | ||
c19d1205 | 29317 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
29318 | if (section->use_rela_p) |
29319 | { | |
29320 | code = fixp->fx_r_type; | |
29321 | break; | |
29322 | } | |
29323 | ||
c19d1205 ZW |
29324 | if (fixp->fx_addsy != NULL |
29325 | && !S_IS_DEFINED (fixp->fx_addsy) | |
29326 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 29327 | { |
c19d1205 ZW |
29328 | as_bad_where (fixp->fx_file, fixp->fx_line, |
29329 | _("undefined local label `%s'"), | |
29330 | S_GET_NAME (fixp->fx_addsy)); | |
29331 | return NULL; | |
a737bd4d NC |
29332 | } |
29333 | ||
c19d1205 ZW |
29334 | as_bad_where (fixp->fx_file, fixp->fx_line, |
29335 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
29336 | return NULL; | |
a737bd4d | 29337 | |
c19d1205 ZW |
29338 | default: |
29339 | { | |
e0471c16 | 29340 | const char * type; |
6c43fab6 | 29341 | |
c19d1205 ZW |
29342 | switch (fixp->fx_r_type) |
29343 | { | |
29344 | case BFD_RELOC_NONE: type = "NONE"; break; | |
29345 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
29346 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 29347 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
29348 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
29349 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
29350 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 29351 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 29352 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
29353 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
29354 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
29355 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
29356 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
29357 | default: type = _("<unknown>"); break; | |
29358 | } | |
29359 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29360 | _("cannot represent %s relocation in this object file format"), | |
29361 | type); | |
29362 | return NULL; | |
29363 | } | |
a737bd4d | 29364 | } |
6c43fab6 | 29365 | |
c19d1205 ZW |
29366 | #ifdef OBJ_ELF |
29367 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
29368 | && GOT_symbol | |
29369 | && fixp->fx_addsy == GOT_symbol) | |
29370 | { | |
29371 | code = BFD_RELOC_ARM_GOTPC; | |
29372 | reloc->addend = fixp->fx_offset = reloc->address; | |
29373 | } | |
29374 | #endif | |
6c43fab6 | 29375 | |
c19d1205 | 29376 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 29377 | |
c19d1205 ZW |
29378 | if (reloc->howto == NULL) |
29379 | { | |
29380 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
29381 | _("cannot represent %s relocation in this object file format"), | |
29382 | bfd_get_reloc_code_name (code)); | |
29383 | return NULL; | |
29384 | } | |
6c43fab6 | 29385 | |
c19d1205 ZW |
29386 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
29387 | vtable entry to be used in the relocation's section offset. */ | |
29388 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
29389 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 29390 | |
c19d1205 | 29391 | return reloc; |
6c43fab6 RE |
29392 | } |
29393 | ||
c19d1205 | 29394 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 29395 | |
c19d1205 ZW |
29396 | void |
29397 | cons_fix_new_arm (fragS * frag, | |
29398 | int where, | |
29399 | int size, | |
62ebcb5c AM |
29400 | expressionS * exp, |
29401 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 29402 | { |
c19d1205 | 29403 | int pcrel = 0; |
6c43fab6 | 29404 | |
c19d1205 ZW |
29405 | /* Pick a reloc. |
29406 | FIXME: @@ Should look at CPU word size. */ | |
29407 | switch (size) | |
29408 | { | |
29409 | case 1: | |
62ebcb5c | 29410 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
29411 | break; |
29412 | case 2: | |
62ebcb5c | 29413 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
29414 | break; |
29415 | case 4: | |
29416 | default: | |
62ebcb5c | 29417 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
29418 | break; |
29419 | case 8: | |
62ebcb5c | 29420 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
29421 | break; |
29422 | } | |
6c43fab6 | 29423 | |
f0927246 NC |
29424 | #ifdef TE_PE |
29425 | if (exp->X_op == O_secrel) | |
29426 | { | |
29427 | exp->X_op = O_symbol; | |
62ebcb5c | 29428 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
29429 | } |
29430 | #endif | |
29431 | ||
62ebcb5c | 29432 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 29433 | } |
6c43fab6 | 29434 | |
4343666d | 29435 | #if defined (OBJ_COFF) |
c19d1205 ZW |
29436 | void |
29437 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 29438 | { |
c19d1205 ZW |
29439 | /* If the destination of the branch is a defined symbol which does not have |
29440 | the THUMB_FUNC attribute, then we must be calling a function which has | |
29441 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
29442 | function and change the branch to refer to that function instead. */ | |
29443 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
29444 | && fixP->fx_addsy != NULL | |
29445 | && S_IS_DEFINED (fixP->fx_addsy) | |
29446 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 29447 | { |
c19d1205 | 29448 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 29449 | } |
c19d1205 ZW |
29450 | } |
29451 | #endif | |
6c43fab6 | 29452 | |
267bf995 | 29453 | |
c19d1205 ZW |
29454 | int |
29455 | arm_force_relocation (struct fix * fixp) | |
29456 | { | |
29457 | #if defined (OBJ_COFF) && defined (TE_PE) | |
29458 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
29459 | return 1; | |
29460 | #endif | |
6c43fab6 | 29461 | |
267bf995 RR |
29462 | /* In case we have a call or a branch to a function in ARM ISA mode from |
29463 | a thumb function or vice-versa force the relocation. These relocations | |
29464 | are cleared off for some cores that might have blx and simple transformations | |
29465 | are possible. */ | |
29466 | ||
29467 | #ifdef OBJ_ELF | |
29468 | switch (fixp->fx_r_type) | |
29469 | { | |
29470 | case BFD_RELOC_ARM_PCREL_JUMP: | |
29471 | case BFD_RELOC_ARM_PCREL_CALL: | |
29472 | case BFD_RELOC_THUMB_PCREL_BLX: | |
29473 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
29474 | return 1; | |
29475 | break; | |
29476 | ||
29477 | case BFD_RELOC_ARM_PCREL_BLX: | |
29478 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
29479 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
29480 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
29481 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
29482 | return 1; | |
29483 | break; | |
29484 | ||
29485 | default: | |
29486 | break; | |
29487 | } | |
29488 | #endif | |
29489 | ||
b5884301 PB |
29490 | /* Resolve these relocations even if the symbol is extern or weak. |
29491 | Technically this is probably wrong due to symbol preemption. | |
29492 | In practice these relocations do not have enough range to be useful | |
29493 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
29494 | expects these references to be resolved. */ | |
c19d1205 ZW |
29495 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
29496 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 29497 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 29498 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
29499 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
29500 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
29501 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 29502 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
29503 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
29504 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
29505 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
29506 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
29507 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
29508 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 29509 | return 0; |
a737bd4d | 29510 | |
4962c51a MS |
29511 | /* Always leave these relocations for the linker. */ |
29512 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
29513 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
29514 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
29515 | return 1; | |
29516 | ||
f0291e4c PB |
29517 | /* Always generate relocations against function symbols. */ |
29518 | if (fixp->fx_r_type == BFD_RELOC_32 | |
29519 | && fixp->fx_addsy | |
29520 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
29521 | return 1; | |
29522 | ||
c19d1205 | 29523 | return generic_force_reloc (fixp); |
404ff6b5 AH |
29524 | } |
29525 | ||
0ffdc86c | 29526 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
29527 | /* Relocations against function names must be left unadjusted, |
29528 | so that the linker can use this information to generate interworking | |
29529 | stubs. The MIPS version of this function | |
c19d1205 ZW |
29530 | also prevents relocations that are mips-16 specific, but I do not |
29531 | know why it does this. | |
404ff6b5 | 29532 | |
c19d1205 ZW |
29533 | FIXME: |
29534 | There is one other problem that ought to be addressed here, but | |
29535 | which currently is not: Taking the address of a label (rather | |
29536 | than a function) and then later jumping to that address. Such | |
29537 | addresses also ought to have their bottom bit set (assuming that | |
29538 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 29539 | |
c19d1205 ZW |
29540 | bfd_boolean |
29541 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 29542 | { |
c19d1205 ZW |
29543 | if (fixP->fx_addsy == NULL) |
29544 | return 1; | |
404ff6b5 | 29545 | |
e28387c3 PB |
29546 | /* Preserve relocations against symbols with function type. */ |
29547 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 29548 | return FALSE; |
e28387c3 | 29549 | |
c19d1205 ZW |
29550 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
29551 | && fixP->fx_subsy == NULL) | |
c921be7d | 29552 | return FALSE; |
a737bd4d | 29553 | |
c19d1205 ZW |
29554 | /* We need the symbol name for the VTABLE entries. */ |
29555 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
29556 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 29557 | return FALSE; |
404ff6b5 | 29558 | |
c19d1205 ZW |
29559 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
29560 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
29561 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
29562 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
29563 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
5c5a4843 | 29564 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC |
c19d1205 ZW |
29565 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 |
29566 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
5c5a4843 | 29567 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC |
c19d1205 | 29568 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 |
5c5a4843 | 29569 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC |
c19d1205 | 29570 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 |
0855e32b NS |
29571 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
29572 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
29573 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
29574 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
29575 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 29576 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 29577 | return FALSE; |
a737bd4d | 29578 | |
4962c51a MS |
29579 | /* Similarly for group relocations. */ |
29580 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
29581 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
29582 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 29583 | return FALSE; |
4962c51a | 29584 | |
79947c54 CD |
29585 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
29586 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
29587 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
29588 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
29589 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
29590 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
29591 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
29592 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
29593 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 29594 | return FALSE; |
79947c54 | 29595 | |
72d98d16 MG |
29596 | /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited |
29597 | offsets, so keep these symbols. */ | |
29598 | if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC | |
29599 | && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) | |
29600 | return FALSE; | |
29601 | ||
c921be7d | 29602 | return TRUE; |
a737bd4d | 29603 | } |
0ffdc86c NC |
29604 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
29605 | ||
29606 | #ifdef OBJ_ELF | |
c19d1205 ZW |
29607 | const char * |
29608 | elf32_arm_target_format (void) | |
404ff6b5 | 29609 | { |
c19d1205 ZW |
29610 | #ifdef TE_SYMBIAN |
29611 | return (target_big_endian | |
29612 | ? "elf32-bigarm-symbian" | |
29613 | : "elf32-littlearm-symbian"); | |
29614 | #elif defined (TE_VXWORKS) | |
29615 | return (target_big_endian | |
29616 | ? "elf32-bigarm-vxworks" | |
29617 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
29618 | #elif defined (TE_NACL) |
29619 | return (target_big_endian | |
29620 | ? "elf32-bigarm-nacl" | |
29621 | : "elf32-littlearm-nacl"); | |
c19d1205 | 29622 | #else |
18a20338 CL |
29623 | if (arm_fdpic) |
29624 | { | |
29625 | if (target_big_endian) | |
29626 | return "elf32-bigarm-fdpic"; | |
29627 | else | |
29628 | return "elf32-littlearm-fdpic"; | |
29629 | } | |
c19d1205 | 29630 | else |
18a20338 CL |
29631 | { |
29632 | if (target_big_endian) | |
29633 | return "elf32-bigarm"; | |
29634 | else | |
29635 | return "elf32-littlearm"; | |
29636 | } | |
c19d1205 | 29637 | #endif |
404ff6b5 AH |
29638 | } |
29639 | ||
c19d1205 ZW |
29640 | void |
29641 | armelf_frob_symbol (symbolS * symp, | |
29642 | int * puntp) | |
404ff6b5 | 29643 | { |
c19d1205 ZW |
29644 | elf_frob_symbol (symp, puntp); |
29645 | } | |
29646 | #endif | |
404ff6b5 | 29647 | |
c19d1205 | 29648 | /* MD interface: Finalization. */ |
a737bd4d | 29649 | |
c19d1205 ZW |
29650 | void |
29651 | arm_cleanup (void) | |
29652 | { | |
29653 | literal_pool * pool; | |
a737bd4d | 29654 | |
5ee91343 AV |
29655 | /* Ensure that all the predication blocks are properly closed. */ |
29656 | check_pred_blocks_finished (); | |
e07e6e58 | 29657 | |
c19d1205 ZW |
29658 | for (pool = list_of_pools; pool; pool = pool->next) |
29659 | { | |
5f4273c7 | 29660 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
29661 | subseg_set (pool->section, pool->sub_section); |
29662 | #ifdef OBJ_ELF | |
29663 | arm_elf_change_section (); | |
29664 | #endif | |
29665 | s_ltorg (0); | |
29666 | } | |
404ff6b5 AH |
29667 | } |
29668 | ||
cd000bff DJ |
29669 | #ifdef OBJ_ELF |
29670 | /* Remove any excess mapping symbols generated for alignment frags in | |
29671 | SEC. We may have created a mapping symbol before a zero byte | |
29672 | alignment; remove it if there's a mapping symbol after the | |
29673 | alignment. */ | |
29674 | static void | |
29675 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
29676 | void *dummy ATTRIBUTE_UNUSED) | |
29677 | { | |
29678 | segment_info_type *seginfo = seg_info (sec); | |
29679 | fragS *fragp; | |
29680 | ||
29681 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
29682 | return; | |
29683 | ||
29684 | for (fragp = seginfo->frchainP->frch_root; | |
29685 | fragp != NULL; | |
29686 | fragp = fragp->fr_next) | |
29687 | { | |
29688 | symbolS *sym = fragp->tc_frag_data.last_map; | |
29689 | fragS *next = fragp->fr_next; | |
29690 | ||
29691 | /* Variable-sized frags have been converted to fixed size by | |
29692 | this point. But if this was variable-sized to start with, | |
29693 | there will be a fixed-size frag after it. So don't handle | |
29694 | next == NULL. */ | |
29695 | if (sym == NULL || next == NULL) | |
29696 | continue; | |
29697 | ||
29698 | if (S_GET_VALUE (sym) < next->fr_address) | |
29699 | /* Not at the end of this frag. */ | |
29700 | continue; | |
29701 | know (S_GET_VALUE (sym) == next->fr_address); | |
29702 | ||
29703 | do | |
29704 | { | |
29705 | if (next->tc_frag_data.first_map != NULL) | |
29706 | { | |
29707 | /* Next frag starts with a mapping symbol. Discard this | |
29708 | one. */ | |
29709 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
29710 | break; | |
29711 | } | |
29712 | ||
29713 | if (next->fr_next == NULL) | |
29714 | { | |
29715 | /* This mapping symbol is at the end of the section. Discard | |
29716 | it. */ | |
29717 | know (next->fr_fix == 0 && next->fr_var == 0); | |
29718 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
29719 | break; | |
29720 | } | |
29721 | ||
29722 | /* As long as we have empty frags without any mapping symbols, | |
29723 | keep looking. */ | |
29724 | /* If the next frag is non-empty and does not start with a | |
29725 | mapping symbol, then this mapping symbol is required. */ | |
29726 | if (next->fr_address != next->fr_next->fr_address) | |
29727 | break; | |
29728 | ||
29729 | next = next->fr_next; | |
29730 | } | |
29731 | while (next != NULL); | |
29732 | } | |
29733 | } | |
29734 | #endif | |
29735 | ||
c19d1205 ZW |
29736 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
29737 | ARM ones. */ | |
404ff6b5 | 29738 | |
c19d1205 ZW |
29739 | void |
29740 | arm_adjust_symtab (void) | |
404ff6b5 | 29741 | { |
c19d1205 ZW |
29742 | #ifdef OBJ_COFF |
29743 | symbolS * sym; | |
404ff6b5 | 29744 | |
c19d1205 ZW |
29745 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
29746 | { | |
29747 | if (ARM_IS_THUMB (sym)) | |
29748 | { | |
29749 | if (THUMB_IS_FUNC (sym)) | |
29750 | { | |
29751 | /* Mark the symbol as a Thumb function. */ | |
29752 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
29753 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
29754 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 29755 | |
c19d1205 ZW |
29756 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
29757 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
29758 | else | |
29759 | as_bad (_("%s: unexpected function type: %d"), | |
29760 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
29761 | } | |
29762 | else switch (S_GET_STORAGE_CLASS (sym)) | |
29763 | { | |
29764 | case C_EXT: | |
29765 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
29766 | break; | |
29767 | case C_STAT: | |
29768 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
29769 | break; | |
29770 | case C_LABEL: | |
29771 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
29772 | break; | |
29773 | default: | |
29774 | /* Do nothing. */ | |
29775 | break; | |
29776 | } | |
29777 | } | |
a737bd4d | 29778 | |
c19d1205 ZW |
29779 | if (ARM_IS_INTERWORK (sym)) |
29780 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 29781 | } |
c19d1205 ZW |
29782 | #endif |
29783 | #ifdef OBJ_ELF | |
29784 | symbolS * sym; | |
29785 | char bind; | |
404ff6b5 | 29786 | |
c19d1205 | 29787 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 29788 | { |
c19d1205 ZW |
29789 | if (ARM_IS_THUMB (sym)) |
29790 | { | |
29791 | elf_symbol_type * elf_sym; | |
404ff6b5 | 29792 | |
c19d1205 ZW |
29793 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
29794 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 29795 | |
b0796911 PB |
29796 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
29797 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
29798 | { |
29799 | /* If it's a .thumb_func, declare it as so, | |
29800 | otherwise tag label as .code 16. */ | |
29801 | if (THUMB_IS_FUNC (sym)) | |
39d911fc TP |
29802 | ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal, |
29803 | ST_BRANCH_TO_THUMB); | |
3ba67470 | 29804 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
29805 | elf_sym->internal_elf_sym.st_info = |
29806 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
29807 | } | |
29808 | } | |
29809 | } | |
cd000bff DJ |
29810 | |
29811 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
29812 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
29813 | /* Now do generic ELF adjustments. */ |
29814 | elf_adjust_symtab (); | |
c19d1205 | 29815 | #endif |
404ff6b5 AH |
29816 | } |
29817 | ||
c19d1205 | 29818 | /* MD interface: Initialization. */ |
404ff6b5 | 29819 | |
a737bd4d | 29820 | static void |
c19d1205 | 29821 | set_constant_flonums (void) |
a737bd4d | 29822 | { |
c19d1205 | 29823 | int i; |
404ff6b5 | 29824 | |
c19d1205 ZW |
29825 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
29826 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
29827 | abort (); | |
a737bd4d | 29828 | } |
404ff6b5 | 29829 | |
3e9e4fcf JB |
29830 | /* Auto-select Thumb mode if it's the only available instruction set for the |
29831 | given architecture. */ | |
29832 | ||
29833 | static void | |
29834 | autoselect_thumb_from_cpu_variant (void) | |
29835 | { | |
29836 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
29837 | opcode_select (16); | |
29838 | } | |
29839 | ||
c19d1205 ZW |
29840 | void |
29841 | md_begin (void) | |
a737bd4d | 29842 | { |
c19d1205 ZW |
29843 | unsigned mach; |
29844 | unsigned int i; | |
404ff6b5 | 29845 | |
c19d1205 ZW |
29846 | if ( (arm_ops_hsh = hash_new ()) == NULL |
29847 | || (arm_cond_hsh = hash_new ()) == NULL | |
5ee91343 | 29848 | || (arm_vcond_hsh = hash_new ()) == NULL |
c19d1205 ZW |
29849 | || (arm_shift_hsh = hash_new ()) == NULL |
29850 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 29851 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 29852 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
29853 | || (arm_reloc_hsh = hash_new ()) == NULL |
29854 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
29855 | as_fatal (_("virtual memory exhausted")); |
29856 | ||
29857 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 29858 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 29859 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 29860 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
5ee91343 AV |
29861 | for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++) |
29862 | hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i)); | |
c19d1205 | 29863 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 29864 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 29865 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 29866 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 29867 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 29868 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 29869 | (void *) (v7m_psrs + i)); |
c19d1205 | 29870 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 29871 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
29872 | for (i = 0; |
29873 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
29874 | i++) | |
d3ce72d0 | 29875 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 29876 | (void *) (barrier_opt_names + i)); |
c19d1205 | 29877 | #ifdef OBJ_ELF |
3da1d841 NC |
29878 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
29879 | { | |
29880 | struct reloc_entry * entry = reloc_names + i; | |
29881 | ||
29882 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
29883 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
29884 | entry->reloc = BFD_RELOC_UNUSED; | |
29885 | ||
29886 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
29887 | } | |
c19d1205 ZW |
29888 | #endif |
29889 | ||
29890 | set_constant_flonums (); | |
404ff6b5 | 29891 | |
c19d1205 ZW |
29892 | /* Set the cpu variant based on the command-line options. We prefer |
29893 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
29894 | -mfpu= over any other way of setting the floating point unit. | |
29895 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 29896 | if (legacy_cpu) |
404ff6b5 | 29897 | { |
e74cfd16 | 29898 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
29899 | as_bad (_("use of old and new-style options to set CPU type")); |
29900 | ||
4d354d8b | 29901 | selected_arch = *legacy_cpu; |
404ff6b5 | 29902 | } |
4d354d8b TP |
29903 | else if (mcpu_cpu_opt) |
29904 | { | |
29905 | selected_arch = *mcpu_cpu_opt; | |
29906 | selected_ext = *mcpu_ext_opt; | |
29907 | } | |
29908 | else if (march_cpu_opt) | |
c168ce07 | 29909 | { |
4d354d8b TP |
29910 | selected_arch = *march_cpu_opt; |
29911 | selected_ext = *march_ext_opt; | |
c168ce07 | 29912 | } |
4d354d8b | 29913 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
404ff6b5 | 29914 | |
e74cfd16 | 29915 | if (legacy_fpu) |
c19d1205 | 29916 | { |
e74cfd16 | 29917 | if (mfpu_opt) |
c19d1205 | 29918 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f | 29919 | |
4d354d8b | 29920 | selected_fpu = *legacy_fpu; |
03b1477f | 29921 | } |
4d354d8b TP |
29922 | else if (mfpu_opt) |
29923 | selected_fpu = *mfpu_opt; | |
29924 | else | |
03b1477f | 29925 | { |
45eb4c1b NS |
29926 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
29927 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
29928 | /* Some environments specify a default FPU. If they don't, infer it |
29929 | from the processor. */ | |
e74cfd16 | 29930 | if (mcpu_fpu_opt) |
4d354d8b | 29931 | selected_fpu = *mcpu_fpu_opt; |
e7da50fa | 29932 | else if (march_fpu_opt) |
4d354d8b | 29933 | selected_fpu = *march_fpu_opt; |
39c2da32 | 29934 | #else |
4d354d8b | 29935 | selected_fpu = fpu_default; |
39c2da32 | 29936 | #endif |
03b1477f RE |
29937 | } |
29938 | ||
4d354d8b | 29939 | if (ARM_FEATURE_ZERO (selected_fpu)) |
03b1477f | 29940 | { |
4d354d8b TP |
29941 | if (!no_cpu_selected ()) |
29942 | selected_fpu = fpu_default; | |
03b1477f | 29943 | else |
4d354d8b | 29944 | selected_fpu = fpu_arch_fpa; |
03b1477f RE |
29945 | } |
29946 | ||
ee065d83 | 29947 | #ifdef CPU_DEFAULT |
4d354d8b | 29948 | if (ARM_FEATURE_ZERO (selected_arch)) |
ee065d83 | 29949 | { |
4d354d8b TP |
29950 | selected_arch = cpu_default; |
29951 | selected_cpu = selected_arch; | |
ee065d83 | 29952 | } |
4d354d8b | 29953 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
e74cfd16 | 29954 | #else |
4d354d8b TP |
29955 | /* Autodection of feature mode: allow all features in cpu_variant but leave |
29956 | selected_cpu unset. It will be set in aeabi_set_public_attributes () | |
29957 | after all instruction have been processed and we can decide what CPU | |
29958 | should be selected. */ | |
29959 | if (ARM_FEATURE_ZERO (selected_arch)) | |
29960 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); | |
ee065d83 | 29961 | else |
4d354d8b | 29962 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
ee065d83 | 29963 | #endif |
03b1477f | 29964 | |
3e9e4fcf JB |
29965 | autoselect_thumb_from_cpu_variant (); |
29966 | ||
e74cfd16 | 29967 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 29968 | |
f17c130b | 29969 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 29970 | { |
7cc69913 NC |
29971 | unsigned int flags = 0; |
29972 | ||
29973 | #if defined OBJ_ELF | |
29974 | flags = meabi_flags; | |
d507cf36 PB |
29975 | |
29976 | switch (meabi_flags) | |
33a392fb | 29977 | { |
d507cf36 | 29978 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 29979 | #endif |
d507cf36 PB |
29980 | /* Set the flags in the private structure. */ |
29981 | if (uses_apcs_26) flags |= F_APCS26; | |
29982 | if (support_interwork) flags |= F_INTERWORK; | |
29983 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 29984 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 29985 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
29986 | flags |= F_SOFT_FLOAT; |
29987 | ||
d507cf36 PB |
29988 | switch (mfloat_abi_opt) |
29989 | { | |
29990 | case ARM_FLOAT_ABI_SOFT: | |
29991 | case ARM_FLOAT_ABI_SOFTFP: | |
29992 | flags |= F_SOFT_FLOAT; | |
29993 | break; | |
33a392fb | 29994 | |
d507cf36 PB |
29995 | case ARM_FLOAT_ABI_HARD: |
29996 | if (flags & F_SOFT_FLOAT) | |
29997 | as_bad (_("hard-float conflicts with specified fpu")); | |
29998 | break; | |
29999 | } | |
03b1477f | 30000 | |
e74cfd16 PB |
30001 | /* Using pure-endian doubles (even if soft-float). */ |
30002 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 30003 | flags |= F_VFP_FLOAT; |
f17c130b | 30004 | |
fde78edd | 30005 | #if defined OBJ_ELF |
e74cfd16 | 30006 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 30007 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
30008 | break; |
30009 | ||
8cb51566 | 30010 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 30011 | case EF_ARM_EABI_VER5: |
c19d1205 | 30012 | /* No additional flags to set. */ |
d507cf36 PB |
30013 | break; |
30014 | ||
30015 | default: | |
30016 | abort (); | |
30017 | } | |
7cc69913 | 30018 | #endif |
b99bd4ef NC |
30019 | bfd_set_private_flags (stdoutput, flags); |
30020 | ||
30021 | /* We have run out flags in the COFF header to encode the | |
30022 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 30023 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
30024 | if (atpcs) |
30025 | { | |
30026 | asection * sec; | |
30027 | ||
30028 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
30029 | ||
30030 | if (sec != NULL) | |
30031 | { | |
fd361982 AM |
30032 | bfd_set_section_flags (sec, SEC_READONLY | SEC_DEBUGGING); |
30033 | bfd_set_section_size (sec, 0); | |
b99bd4ef NC |
30034 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); |
30035 | } | |
30036 | } | |
7cc69913 | 30037 | } |
f17c130b | 30038 | #endif |
b99bd4ef NC |
30039 | |
30040 | /* Record the CPU type as well. */ | |
2d447fca JM |
30041 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
30042 | mach = bfd_mach_arm_iWMMXt2; | |
30043 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 30044 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 30045 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 30046 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 30047 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 30048 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 30049 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 30050 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 30051 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 30052 | { |
e74cfd16 | 30053 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
30054 | mach = bfd_mach_arm_5T; |
30055 | else | |
30056 | mach = bfd_mach_arm_5; | |
30057 | } | |
e74cfd16 | 30058 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 30059 | { |
e74cfd16 | 30060 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
30061 | mach = bfd_mach_arm_4T; |
30062 | else | |
30063 | mach = bfd_mach_arm_4; | |
30064 | } | |
e74cfd16 | 30065 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 30066 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
30067 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
30068 | mach = bfd_mach_arm_3; | |
30069 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
30070 | mach = bfd_mach_arm_2a; | |
30071 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
30072 | mach = bfd_mach_arm_2; | |
30073 | else | |
30074 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
30075 | |
30076 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
30077 | } | |
30078 | ||
c19d1205 | 30079 | /* Command line processing. */ |
b99bd4ef | 30080 | |
c19d1205 ZW |
30081 | /* md_parse_option |
30082 | Invocation line includes a switch not recognized by the base assembler. | |
30083 | See if it's a processor-specific option. | |
b99bd4ef | 30084 | |
c19d1205 ZW |
30085 | This routine is somewhat complicated by the need for backwards |
30086 | compatibility (since older releases of gcc can't be changed). | |
30087 | The new options try to make the interface as compatible as | |
30088 | possible with GCC. | |
b99bd4ef | 30089 | |
c19d1205 | 30090 | New options (supported) are: |
b99bd4ef | 30091 | |
c19d1205 ZW |
30092 | -mcpu=<cpu name> Assemble for selected processor |
30093 | -march=<architecture name> Assemble for selected architecture | |
30094 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
30095 | -EB/-mbig-endian Big-endian | |
30096 | -EL/-mlittle-endian Little-endian | |
30097 | -k Generate PIC code | |
30098 | -mthumb Start in Thumb mode | |
30099 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 30100 | |
278df34e | 30101 | -m[no-]warn-deprecated Warn about deprecated features |
8b2d793c | 30102 | -m[no-]warn-syms Warn when symbols match instructions |
267bf995 | 30103 | |
c19d1205 | 30104 | For now we will also provide support for: |
b99bd4ef | 30105 | |
c19d1205 ZW |
30106 | -mapcs-32 32-bit Program counter |
30107 | -mapcs-26 26-bit Program counter | |
30108 | -macps-float Floats passed in FP registers | |
30109 | -mapcs-reentrant Reentrant code | |
30110 | -matpcs | |
30111 | (sometime these will probably be replaced with -mapcs=<list of options> | |
30112 | and -matpcs=<list of options>) | |
b99bd4ef | 30113 | |
c19d1205 ZW |
30114 | The remaining options are only supported for back-wards compatibility. |
30115 | Cpu variants, the arm part is optional: | |
30116 | -m[arm]1 Currently not supported. | |
30117 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
30118 | -m[arm]3 Arm 3 processor | |
30119 | -m[arm]6[xx], Arm 6 processors | |
30120 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
30121 | -m[arm]8[10] Arm 8 processors | |
30122 | -m[arm]9[20][tdmi] Arm 9 processors | |
30123 | -mstrongarm[110[0]] StrongARM processors | |
30124 | -mxscale XScale processors | |
30125 | -m[arm]v[2345[t[e]]] Arm architectures | |
30126 | -mall All (except the ARM1) | |
30127 | FP variants: | |
30128 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
30129 | -mfpe-old (No float load/store multiples) | |
30130 | -mvfpxd VFP Single precision | |
30131 | -mvfp All VFP | |
30132 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 30133 | |
c19d1205 ZW |
30134 | The following CPU names are recognized: |
30135 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
30136 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
30137 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
30138 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
30139 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
30140 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
30141 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 30142 | |
c19d1205 | 30143 | */ |
b99bd4ef | 30144 | |
c19d1205 | 30145 | const char * md_shortopts = "m:k"; |
b99bd4ef | 30146 | |
c19d1205 ZW |
30147 | #ifdef ARM_BI_ENDIAN |
30148 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
30149 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 30150 | #else |
c19d1205 ZW |
30151 | #if TARGET_BYTES_BIG_ENDIAN |
30152 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 30153 | #else |
c19d1205 ZW |
30154 | #define OPTION_EL (OPTION_MD_BASE + 1) |
30155 | #endif | |
b99bd4ef | 30156 | #endif |
845b51d6 | 30157 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
18a20338 | 30158 | #define OPTION_FDPIC (OPTION_MD_BASE + 3) |
b99bd4ef | 30159 | |
c19d1205 | 30160 | struct option md_longopts[] = |
b99bd4ef | 30161 | { |
c19d1205 ZW |
30162 | #ifdef OPTION_EB |
30163 | {"EB", no_argument, NULL, OPTION_EB}, | |
30164 | #endif | |
30165 | #ifdef OPTION_EL | |
30166 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 30167 | #endif |
845b51d6 | 30168 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
18a20338 CL |
30169 | #ifdef OBJ_ELF |
30170 | {"fdpic", no_argument, NULL, OPTION_FDPIC}, | |
30171 | #endif | |
c19d1205 ZW |
30172 | {NULL, no_argument, NULL, 0} |
30173 | }; | |
b99bd4ef | 30174 | |
c19d1205 | 30175 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 30176 | |
c19d1205 | 30177 | struct arm_option_table |
b99bd4ef | 30178 | { |
0198d5e6 TC |
30179 | const char * option; /* Option name to match. */ |
30180 | const char * help; /* Help information. */ | |
30181 | int * var; /* Variable to change. */ | |
30182 | int value; /* What to change it to. */ | |
30183 | const char * deprecated; /* If non-null, print this message. */ | |
c19d1205 | 30184 | }; |
b99bd4ef | 30185 | |
c19d1205 ZW |
30186 | struct arm_option_table arm_opts[] = |
30187 | { | |
30188 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
30189 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
30190 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
30191 | &support_interwork, 1, NULL}, | |
30192 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
30193 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
30194 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
30195 | 1, NULL}, | |
30196 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
30197 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
30198 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
30199 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
30200 | NULL}, | |
b99bd4ef | 30201 | |
c19d1205 ZW |
30202 | /* These are recognized by the assembler, but have no affect on code. */ |
30203 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
30204 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
30205 | |
30206 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
30207 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
30208 | &warn_on_deprecated, 0, NULL}, | |
8b2d793c NC |
30209 | {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL}, |
30210 | {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL}, | |
e74cfd16 PB |
30211 | {NULL, NULL, NULL, 0, NULL} |
30212 | }; | |
30213 | ||
30214 | struct arm_legacy_option_table | |
30215 | { | |
0198d5e6 TC |
30216 | const char * option; /* Option name to match. */ |
30217 | const arm_feature_set ** var; /* Variable to change. */ | |
30218 | const arm_feature_set value; /* What to change it to. */ | |
30219 | const char * deprecated; /* If non-null, print this message. */ | |
e74cfd16 | 30220 | }; |
b99bd4ef | 30221 | |
e74cfd16 PB |
30222 | const struct arm_legacy_option_table arm_legacy_opts[] = |
30223 | { | |
c19d1205 ZW |
30224 | /* DON'T add any new processors to this list -- we want the whole list |
30225 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
30226 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
30227 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
30228 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
30229 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
30230 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
30231 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
30232 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
30233 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
30234 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
30235 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
30236 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
30237 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
30238 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
30239 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
30240 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
30241 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
30242 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
30243 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
30244 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
30245 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
30246 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
30247 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
30248 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
30249 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
30250 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
30251 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
30252 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
30253 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
30254 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
30255 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
30256 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
30257 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
30258 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
30259 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
30260 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
30261 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
30262 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
30263 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
30264 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
30265 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
30266 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
30267 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
30268 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
30269 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
30270 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
30271 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
30272 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30273 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30274 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30275 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
30276 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
30277 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
30278 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
30279 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
30280 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
30281 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
30282 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
30283 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
30284 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
30285 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
30286 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
30287 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
30288 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
30289 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
30290 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
30291 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
30292 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
30293 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
30294 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
30295 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 30296 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 30297 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 30298 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 30299 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 30300 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
30301 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
30302 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
30303 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 30304 | |
c19d1205 | 30305 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
30306 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
30307 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
30308 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
30309 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
30310 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
30311 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
30312 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
30313 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
30314 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
30315 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
30316 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
30317 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
30318 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
30319 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
30320 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
30321 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
30322 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
30323 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 30324 | |
c19d1205 | 30325 | /* Floating point variants -- don't add any more to this list either. */ |
0198d5e6 TC |
30326 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
30327 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
30328 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
30329 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 30330 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 30331 | |
e74cfd16 | 30332 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 30333 | }; |
7ed4c4c5 | 30334 | |
c19d1205 | 30335 | struct arm_cpu_option_table |
7ed4c4c5 | 30336 | { |
0198d5e6 TC |
30337 | const char * name; |
30338 | size_t name_len; | |
30339 | const arm_feature_set value; | |
30340 | const arm_feature_set ext; | |
c19d1205 ZW |
30341 | /* For some CPUs we assume an FPU unless the user explicitly sets |
30342 | -mfpu=... */ | |
0198d5e6 | 30343 | const arm_feature_set default_fpu; |
ee065d83 PB |
30344 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
30345 | case. */ | |
0198d5e6 | 30346 | const char * canonical_name; |
c19d1205 | 30347 | }; |
7ed4c4c5 | 30348 | |
c19d1205 ZW |
30349 | /* This list should, at a minimum, contain all the cpu names |
30350 | recognized by GCC. */ | |
996b5569 | 30351 | #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN } |
0198d5e6 | 30352 | |
e74cfd16 | 30353 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 30354 | { |
996b5569 TP |
30355 | ARM_CPU_OPT ("all", NULL, ARM_ANY, |
30356 | ARM_ARCH_NONE, | |
30357 | FPU_ARCH_FPA), | |
30358 | ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1, | |
30359 | ARM_ARCH_NONE, | |
30360 | FPU_ARCH_FPA), | |
30361 | ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2, | |
30362 | ARM_ARCH_NONE, | |
30363 | FPU_ARCH_FPA), | |
30364 | ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S, | |
30365 | ARM_ARCH_NONE, | |
30366 | FPU_ARCH_FPA), | |
30367 | ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S, | |
30368 | ARM_ARCH_NONE, | |
30369 | FPU_ARCH_FPA), | |
30370 | ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3, | |
30371 | ARM_ARCH_NONE, | |
30372 | FPU_ARCH_FPA), | |
30373 | ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3, | |
30374 | ARM_ARCH_NONE, | |
30375 | FPU_ARCH_FPA), | |
30376 | ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3, | |
30377 | ARM_ARCH_NONE, | |
30378 | FPU_ARCH_FPA), | |
30379 | ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3, | |
30380 | ARM_ARCH_NONE, | |
30381 | FPU_ARCH_FPA), | |
30382 | ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3, | |
30383 | ARM_ARCH_NONE, | |
30384 | FPU_ARCH_FPA), | |
30385 | ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3, | |
30386 | ARM_ARCH_NONE, | |
30387 | FPU_ARCH_FPA), | |
30388 | ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M, | |
30389 | ARM_ARCH_NONE, | |
30390 | FPU_ARCH_FPA), | |
30391 | ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3, | |
30392 | ARM_ARCH_NONE, | |
30393 | FPU_ARCH_FPA), | |
30394 | ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M, | |
30395 | ARM_ARCH_NONE, | |
30396 | FPU_ARCH_FPA), | |
30397 | ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3, | |
30398 | ARM_ARCH_NONE, | |
30399 | FPU_ARCH_FPA), | |
30400 | ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M, | |
30401 | ARM_ARCH_NONE, | |
30402 | FPU_ARCH_FPA), | |
30403 | ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3, | |
30404 | ARM_ARCH_NONE, | |
30405 | FPU_ARCH_FPA), | |
30406 | ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3, | |
30407 | ARM_ARCH_NONE, | |
30408 | FPU_ARCH_FPA), | |
30409 | ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3, | |
30410 | ARM_ARCH_NONE, | |
30411 | FPU_ARCH_FPA), | |
30412 | ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3, | |
30413 | ARM_ARCH_NONE, | |
30414 | FPU_ARCH_FPA), | |
30415 | ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T, | |
30416 | ARM_ARCH_NONE, | |
30417 | FPU_ARCH_FPA), | |
30418 | ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3, | |
30419 | ARM_ARCH_NONE, | |
30420 | FPU_ARCH_FPA), | |
30421 | ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T, | |
30422 | ARM_ARCH_NONE, | |
30423 | FPU_ARCH_FPA), | |
30424 | ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T, | |
30425 | ARM_ARCH_NONE, | |
30426 | FPU_ARCH_FPA), | |
30427 | ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3, | |
30428 | ARM_ARCH_NONE, | |
30429 | FPU_ARCH_FPA), | |
30430 | ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3, | |
30431 | ARM_ARCH_NONE, | |
30432 | FPU_ARCH_FPA), | |
30433 | ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3, | |
30434 | ARM_ARCH_NONE, | |
30435 | FPU_ARCH_FPA), | |
30436 | ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3, | |
30437 | ARM_ARCH_NONE, | |
30438 | FPU_ARCH_FPA), | |
30439 | ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T, | |
30440 | ARM_ARCH_NONE, | |
30441 | FPU_ARCH_FPA), | |
30442 | ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T, | |
30443 | ARM_ARCH_NONE, | |
30444 | FPU_ARCH_FPA), | |
30445 | ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T, | |
30446 | ARM_ARCH_NONE, | |
30447 | FPU_ARCH_FPA), | |
30448 | ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4, | |
30449 | ARM_ARCH_NONE, | |
30450 | FPU_ARCH_FPA), | |
30451 | ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4, | |
30452 | ARM_ARCH_NONE, | |
30453 | FPU_ARCH_FPA), | |
30454 | ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4, | |
30455 | ARM_ARCH_NONE, | |
30456 | FPU_ARCH_FPA), | |
30457 | ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4, | |
30458 | ARM_ARCH_NONE, | |
30459 | FPU_ARCH_FPA), | |
30460 | ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4, | |
30461 | ARM_ARCH_NONE, | |
30462 | FPU_ARCH_FPA), | |
30463 | ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4, | |
30464 | ARM_ARCH_NONE, | |
30465 | FPU_ARCH_FPA), | |
30466 | ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4, | |
30467 | ARM_ARCH_NONE, | |
30468 | FPU_ARCH_FPA), | |
30469 | ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T, | |
30470 | ARM_ARCH_NONE, | |
30471 | FPU_ARCH_FPA), | |
30472 | ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T, | |
30473 | ARM_ARCH_NONE, | |
30474 | FPU_ARCH_FPA), | |
30475 | ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T, | |
30476 | ARM_ARCH_NONE, | |
30477 | FPU_ARCH_FPA), | |
30478 | ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T, | |
30479 | ARM_ARCH_NONE, | |
30480 | FPU_ARCH_FPA), | |
30481 | ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T, | |
30482 | ARM_ARCH_NONE, | |
30483 | FPU_ARCH_FPA), | |
30484 | ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T, | |
30485 | ARM_ARCH_NONE, | |
30486 | FPU_ARCH_FPA), | |
30487 | ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4, | |
30488 | ARM_ARCH_NONE, | |
30489 | FPU_ARCH_FPA), | |
30490 | ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4, | |
30491 | ARM_ARCH_NONE, | |
30492 | FPU_ARCH_FPA), | |
30493 | ||
c19d1205 ZW |
30494 | /* For V5 or later processors we default to using VFP; but the user |
30495 | should really set the FPU type explicitly. */ | |
996b5569 TP |
30496 | ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP, |
30497 | ARM_ARCH_NONE, | |
30498 | FPU_ARCH_VFP_V2), | |
30499 | ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE, | |
30500 | ARM_ARCH_NONE, | |
30501 | FPU_ARCH_VFP_V2), | |
30502 | ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ, | |
30503 | ARM_ARCH_NONE, | |
30504 | FPU_ARCH_VFP_V2), | |
30505 | ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ, | |
30506 | ARM_ARCH_NONE, | |
30507 | FPU_ARCH_VFP_V2), | |
30508 | ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ, | |
30509 | ARM_ARCH_NONE, | |
30510 | FPU_ARCH_VFP_V2), | |
30511 | ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP, | |
30512 | ARM_ARCH_NONE, | |
30513 | FPU_ARCH_VFP_V2), | |
30514 | ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE, | |
30515 | ARM_ARCH_NONE, | |
30516 | FPU_ARCH_VFP_V2), | |
30517 | ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE, | |
30518 | ARM_ARCH_NONE, | |
30519 | FPU_ARCH_VFP_V2), | |
30520 | ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP, | |
30521 | ARM_ARCH_NONE, | |
30522 | FPU_ARCH_VFP_V2), | |
30523 | ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE, | |
30524 | ARM_ARCH_NONE, | |
30525 | FPU_ARCH_VFP_V2), | |
30526 | ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE, | |
30527 | ARM_ARCH_NONE, | |
30528 | FPU_ARCH_VFP_V2), | |
30529 | ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE, | |
30530 | ARM_ARCH_NONE, | |
30531 | FPU_ARCH_VFP_V2), | |
30532 | ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T, | |
30533 | ARM_ARCH_NONE, | |
30534 | FPU_ARCH_VFP_V1), | |
30535 | ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T, | |
30536 | ARM_ARCH_NONE, | |
30537 | FPU_ARCH_VFP_V1), | |
30538 | ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE, | |
30539 | ARM_ARCH_NONE, | |
30540 | FPU_ARCH_VFP_V2), | |
30541 | ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE, | |
30542 | ARM_ARCH_NONE, | |
30543 | FPU_ARCH_VFP_V2), | |
30544 | ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T, | |
30545 | ARM_ARCH_NONE, | |
30546 | FPU_ARCH_VFP_V1), | |
30547 | ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE, | |
30548 | ARM_ARCH_NONE, | |
30549 | FPU_ARCH_VFP_V2), | |
30550 | ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE, | |
30551 | ARM_ARCH_NONE, | |
30552 | FPU_ARCH_VFP_V2), | |
30553 | ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ, | |
30554 | ARM_ARCH_NONE, | |
30555 | FPU_ARCH_VFP_V2), | |
30556 | ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ, | |
30557 | ARM_ARCH_NONE, | |
30558 | FPU_ARCH_VFP_V2), | |
30559 | ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE, | |
30560 | ARM_ARCH_NONE, | |
30561 | FPU_ARCH_VFP_V2), | |
30562 | ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE, | |
30563 | ARM_ARCH_NONE, | |
30564 | FPU_ARCH_VFP_V2), | |
30565 | ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE, | |
30566 | ARM_ARCH_NONE, | |
30567 | FPU_ARCH_VFP_V2), | |
30568 | ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE, | |
30569 | ARM_ARCH_NONE, | |
30570 | FPU_ARCH_VFP_V2), | |
30571 | ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE, | |
30572 | ARM_ARCH_NONE, | |
30573 | FPU_ARCH_VFP_V2), | |
30574 | ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6, | |
30575 | ARM_ARCH_NONE, | |
30576 | FPU_NONE), | |
30577 | ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6, | |
30578 | ARM_ARCH_NONE, | |
30579 | FPU_NONE), | |
30580 | ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6, | |
30581 | ARM_ARCH_NONE, | |
30582 | FPU_ARCH_VFP_V2), | |
30583 | ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6, | |
30584 | ARM_ARCH_NONE, | |
30585 | FPU_ARCH_VFP_V2), | |
30586 | ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K, | |
30587 | ARM_ARCH_NONE, | |
30588 | FPU_ARCH_VFP_V2), | |
30589 | ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K, | |
30590 | ARM_ARCH_NONE, | |
30591 | FPU_NONE), | |
30592 | ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2, | |
30593 | ARM_ARCH_NONE, | |
30594 | FPU_NONE), | |
30595 | ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2, | |
30596 | ARM_ARCH_NONE, | |
30597 | FPU_ARCH_VFP_V2), | |
30598 | ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ, | |
30599 | ARM_ARCH_NONE, | |
30600 | FPU_NONE), | |
30601 | ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ, | |
30602 | ARM_ARCH_NONE, | |
30603 | FPU_ARCH_VFP_V2), | |
30604 | ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A, | |
30605 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30606 | FPU_NONE), | |
30607 | ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE, | |
30608 | ARM_ARCH_NONE, | |
30609 | FPU_ARCH_NEON_VFP_V4), | |
30610 | ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A, | |
30611 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), | |
30612 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), | |
30613 | ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A, | |
30614 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30615 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)), | |
30616 | ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE, | |
30617 | ARM_ARCH_NONE, | |
30618 | FPU_ARCH_NEON_VFP_V4), | |
30619 | ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE, | |
30620 | ARM_ARCH_NONE, | |
30621 | FPU_ARCH_NEON_VFP_V4), | |
30622 | ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE, | |
30623 | ARM_ARCH_NONE, | |
30624 | FPU_ARCH_NEON_VFP_V4), | |
30625 | ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A, | |
30626 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30627 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30628 | ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A, | |
30629 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30630 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30631 | ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A, | |
30632 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30633 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
15a7695f JG |
30634 | ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A, |
30635 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
0198d5e6 | 30636 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
996b5569 TP |
30637 | ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A, |
30638 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30639 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30640 | ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A, | |
30641 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30642 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30643 | ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A, | |
30644 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30645 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
15a7695f JG |
30646 | ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A, |
30647 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
0198d5e6 | 30648 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), |
7ebd1359 | 30649 | ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A, |
30650 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30651 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
0535e5d7 DZ |
30652 | ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A, |
30653 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30654 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
30655 | ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A, | |
30656 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30657 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
ef8df4ca KT |
30658 | ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A, |
30659 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30660 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
996b5569 TP |
30661 | ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R, |
30662 | ARM_ARCH_NONE, | |
30663 | FPU_NONE), | |
30664 | ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R, | |
30665 | ARM_ARCH_NONE, | |
30666 | FPU_ARCH_VFP_V3D16), | |
30667 | ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R, | |
30668 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
30669 | FPU_NONE), | |
30670 | ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R, | |
30671 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
30672 | FPU_ARCH_VFP_V3D16), | |
30673 | ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R, | |
30674 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), | |
30675 | FPU_ARCH_VFP_V3D16), | |
0cda1e19 TP |
30676 | ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R, |
30677 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30678 | FPU_ARCH_NEON_VFP_ARMV8), | |
0535e5d7 DZ |
30679 | ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN, |
30680 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30681 | FPU_NONE), | |
996b5569 TP |
30682 | ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN, |
30683 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30684 | FPU_NONE), | |
30685 | ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE, | |
30686 | ARM_ARCH_NONE, | |
30687 | FPU_NONE), | |
30688 | ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM, | |
30689 | ARM_ARCH_NONE, | |
30690 | FPU_NONE), | |
30691 | ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM, | |
30692 | ARM_ARCH_NONE, | |
30693 | FPU_NONE), | |
30694 | ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M, | |
30695 | ARM_ARCH_NONE, | |
30696 | FPU_NONE), | |
30697 | ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM, | |
30698 | ARM_ARCH_NONE, | |
30699 | FPU_NONE), | |
30700 | ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM, | |
30701 | ARM_ARCH_NONE, | |
30702 | FPU_NONE), | |
30703 | ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM, | |
30704 | ARM_ARCH_NONE, | |
30705 | FPU_NONE), | |
30706 | ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A, | |
30707 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30708 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
83f43c83 KT |
30709 | ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A, |
30710 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
30711 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD), | |
c19d1205 | 30712 | /* ??? XSCALE is really an architecture. */ |
996b5569 TP |
30713 | ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE, |
30714 | ARM_ARCH_NONE, | |
30715 | FPU_ARCH_VFP_V2), | |
30716 | ||
c19d1205 | 30717 | /* ??? iwmmxt is not a processor. */ |
996b5569 TP |
30718 | ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT, |
30719 | ARM_ARCH_NONE, | |
30720 | FPU_ARCH_VFP_V2), | |
30721 | ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2, | |
30722 | ARM_ARCH_NONE, | |
30723 | FPU_ARCH_VFP_V2), | |
30724 | ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE, | |
30725 | ARM_ARCH_NONE, | |
30726 | FPU_ARCH_VFP_V2), | |
30727 | ||
0198d5e6 | 30728 | /* Maverick. */ |
996b5569 TP |
30729 | ARM_CPU_OPT ("ep9312", "ARM920T", |
30730 | ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), | |
30731 | ARM_ARCH_NONE, FPU_ARCH_MAVERICK), | |
30732 | ||
da4339ed | 30733 | /* Marvell processors. */ |
996b5569 TP |
30734 | ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A, |
30735 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30736 | FPU_ARCH_VFP_V3D16), | |
30737 | ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A, | |
30738 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC), | |
30739 | FPU_ARCH_NEON_VFP_V4), | |
da4339ed | 30740 | |
996b5569 TP |
30741 | /* APM X-Gene family. */ |
30742 | ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A, | |
30743 | ARM_ARCH_NONE, | |
30744 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30745 | ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A, | |
30746 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8), | |
30747 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8), | |
30748 | ||
30749 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } | |
c19d1205 | 30750 | }; |
f3bad469 | 30751 | #undef ARM_CPU_OPT |
7ed4c4c5 | 30752 | |
34ef62f4 AV |
30753 | struct arm_ext_table |
30754 | { | |
30755 | const char * name; | |
30756 | size_t name_len; | |
30757 | const arm_feature_set merge; | |
30758 | const arm_feature_set clear; | |
30759 | }; | |
30760 | ||
c19d1205 | 30761 | struct arm_arch_option_table |
7ed4c4c5 | 30762 | { |
34ef62f4 AV |
30763 | const char * name; |
30764 | size_t name_len; | |
30765 | const arm_feature_set value; | |
30766 | const arm_feature_set default_fpu; | |
30767 | const struct arm_ext_table * ext_table; | |
30768 | }; | |
30769 | ||
30770 | /* Used to add support for +E and +noE extension. */ | |
30771 | #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C } | |
30772 | /* Used to add support for a +E extension. */ | |
30773 | #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE } | |
30774 | /* Used to add support for a +noE extension. */ | |
30775 | #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C } | |
30776 | ||
30777 | #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \ | |
30778 | ~0 & ~FPU_ENDIAN_PURE) | |
30779 | ||
30780 | static const struct arm_ext_table armv5te_ext_table[] = | |
30781 | { | |
30782 | ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP), | |
30783 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30784 | }; | |
30785 | ||
30786 | static const struct arm_ext_table armv7_ext_table[] = | |
30787 | { | |
30788 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), | |
30789 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30790 | }; | |
30791 | ||
30792 | static const struct arm_ext_table armv7ve_ext_table[] = | |
30793 | { | |
30794 | ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP), | |
30795 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), | |
30796 | ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3), | |
30797 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), | |
30798 | ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16), | |
30799 | ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */ | |
30800 | ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4), | |
30801 | ||
30802 | ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4, | |
30803 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)), | |
30804 | ||
30805 | /* Aliases for +simd. */ | |
30806 | ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4), | |
30807 | ||
30808 | ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30809 | ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30810 | ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16), | |
30811 | ||
30812 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30813 | }; | |
30814 | ||
30815 | static const struct arm_ext_table armv7a_ext_table[] = | |
30816 | { | |
30817 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), | |
30818 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */ | |
30819 | ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3), | |
30820 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), | |
30821 | ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16), | |
30822 | ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), | |
30823 | ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4), | |
30824 | ||
30825 | ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1, | |
30826 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)), | |
30827 | ||
30828 | /* Aliases for +simd. */ | |
30829 | ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30830 | ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1), | |
30831 | ||
30832 | ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16), | |
30833 | ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4), | |
30834 | ||
30835 | ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)), | |
30836 | ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)), | |
30837 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30838 | }; | |
30839 | ||
30840 | static const struct arm_ext_table armv7r_ext_table[] = | |
30841 | { | |
30842 | ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD), | |
30843 | ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */ | |
30844 | ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP), | |
30845 | ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */ | |
30846 | ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16), | |
30847 | ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16), | |
30848 | ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), | |
30849 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)), | |
30850 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30851 | }; | |
30852 | ||
30853 | static const struct arm_ext_table armv7em_ext_table[] = | |
30854 | { | |
30855 | ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP), | |
30856 | /* Alias for +fp, used to be known as fpv4-sp-d16. */ | |
30857 | ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16), | |
30858 | ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16), | |
30859 | ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16), | |
30860 | ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16), | |
30861 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30862 | }; | |
30863 | ||
30864 | static const struct arm_ext_table armv8a_ext_table[] = | |
30865 | { | |
30866 | ARM_ADD ("crc", ARCH_CRC_ARMV8), | |
30867 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8), | |
30868 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
30869 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30870 | ||
30871 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30872 | should use the +simd option to turn on FP. */ | |
30873 | ARM_REMOVE ("fp", ALL_FP), | |
30874 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30875 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30876 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30877 | }; | |
30878 | ||
30879 | ||
30880 | static const struct arm_ext_table armv81a_ext_table[] = | |
30881 | { | |
30882 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1), | |
30883 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, | |
30884 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30885 | ||
30886 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30887 | should use the +simd option to turn on FP. */ | |
30888 | ARM_REMOVE ("fp", ALL_FP), | |
30889 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30890 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30891 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30892 | }; | |
30893 | ||
30894 | static const struct arm_ext_table armv82a_ext_table[] = | |
30895 | { | |
30896 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1), | |
30897 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16), | |
30898 | ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML), | |
30899 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, | |
30900 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30901 | ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), | |
30902 | ||
30903 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30904 | should use the +simd option to turn on FP. */ | |
30905 | ARM_REMOVE ("fp", ALL_FP), | |
30906 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30907 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30908 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30909 | }; | |
30910 | ||
30911 | static const struct arm_ext_table armv84a_ext_table[] = | |
30912 | { | |
30913 | ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), | |
30914 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML), | |
30915 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4, | |
30916 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30917 | ||
30918 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30919 | should use the +simd option to turn on FP. */ | |
30920 | ARM_REMOVE ("fp", ALL_FP), | |
30921 | ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)), | |
30922 | ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)), | |
30923 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30924 | }; | |
30925 | ||
30926 | static const struct arm_ext_table armv85a_ext_table[] = | |
30927 | { | |
30928 | ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8), | |
30929 | ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML), | |
30930 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4, | |
30931 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30932 | ||
30933 | /* Armv8-a does not allow an FP implementation without SIMD, so the user | |
30934 | should use the +simd option to turn on FP. */ | |
30935 | ARM_REMOVE ("fp", ALL_FP), | |
30936 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30937 | }; | |
30938 | ||
30939 | static const struct arm_ext_table armv8m_main_ext_table[] = | |
30940 | { | |
30941 | ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30942 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)), | |
30943 | ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP), | |
30944 | ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16), | |
30945 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
30946 | }; | |
30947 | ||
e0991585 AV |
30948 | static const struct arm_ext_table armv8_1m_main_ext_table[] = |
30949 | { | |
30950 | ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
30951 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)), | |
30952 | ARM_EXT ("fp", | |
30953 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, | |
30954 | FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA), | |
30955 | ALL_FP), | |
30956 | ARM_ADD ("fp.dp", | |
30957 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, | |
30958 | FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)), | |
a7ad558c AV |
30959 | ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE), |
30960 | ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)), | |
30961 | ARM_ADD ("mve.fp", | |
30962 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, | |
30963 | FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 | | |
30964 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)), | |
e0991585 AV |
30965 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } |
30966 | }; | |
30967 | ||
34ef62f4 AV |
30968 | static const struct arm_ext_table armv8r_ext_table[] = |
30969 | { | |
30970 | ARM_ADD ("crc", ARCH_CRC_ARMV8), | |
30971 | ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8), | |
30972 | ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
30973 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)), | |
30974 | ARM_REMOVE ("fp", ALL_FP), | |
30975 | ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16), | |
30976 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 30977 | }; |
7ed4c4c5 | 30978 | |
c19d1205 ZW |
30979 | /* This list should, at a minimum, contain all the architecture names |
30980 | recognized by GCC. */ | |
34ef62f4 AV |
30981 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL } |
30982 | #define ARM_ARCH_OPT2(N, V, DF, ext) \ | |
30983 | { N, sizeof (N) - 1, V, DF, ext##_ext_table } | |
0198d5e6 | 30984 | |
e74cfd16 | 30985 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 30986 | { |
497d849d TP |
30987 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
30988 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
30989 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
30990 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
30991 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
30992 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
30993 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
30994 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
30995 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
30996 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
30997 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
30998 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
30999 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
31000 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
34ef62f4 AV |
31001 | ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te), |
31002 | ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te), | |
31003 | ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te), | |
31004 | ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te), | |
31005 | ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te), | |
31006 | ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te), | |
31007 | ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te), | |
f33026a9 MW |
31008 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is |
31009 | kept to preserve existing behaviour. */ | |
34ef62f4 AV |
31010 | ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te), |
31011 | ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te), | |
31012 | ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te), | |
31013 | ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te), | |
31014 | ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te), | |
f33026a9 MW |
31015 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is |
31016 | kept to preserve existing behaviour. */ | |
34ef62f4 AV |
31017 | ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te), |
31018 | ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te), | |
497d849d TP |
31019 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), |
31020 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
34ef62f4 | 31021 | ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7), |
c450d570 PB |
31022 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
31023 | Accept the non-dashed form for compatibility with old toolchains. */ | |
34ef62f4 AV |
31024 | ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a), |
31025 | ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve), | |
31026 | ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r), | |
497d849d | 31027 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), |
34ef62f4 AV |
31028 | ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a), |
31029 | ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r), | |
497d849d | 31030 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), |
34ef62f4 | 31031 | ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em), |
497d849d | 31032 | ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP), |
34ef62f4 AV |
31033 | ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP, |
31034 | armv8m_main), | |
e0991585 AV |
31035 | ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP, |
31036 | armv8_1m_main), | |
34ef62f4 AV |
31037 | ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a), |
31038 | ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a), | |
31039 | ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a), | |
31040 | ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a), | |
31041 | ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r), | |
31042 | ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a), | |
31043 | ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a), | |
497d849d TP |
31044 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
31045 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
31046 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP), | |
34ef62f4 | 31047 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
c19d1205 | 31048 | }; |
f3bad469 | 31049 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 31050 | |
69133863 | 31051 | /* ISA extensions in the co-processor and main instruction set space. */ |
0198d5e6 | 31052 | |
69133863 | 31053 | struct arm_option_extension_value_table |
c19d1205 | 31054 | { |
0198d5e6 TC |
31055 | const char * name; |
31056 | size_t name_len; | |
31057 | const arm_feature_set merge_value; | |
31058 | const arm_feature_set clear_value; | |
d942732e TP |
31059 | /* List of architectures for which an extension is available. ARM_ARCH_NONE |
31060 | indicates that an extension is available for all architectures while | |
31061 | ARM_ANY marks an empty entry. */ | |
0198d5e6 | 31062 | const arm_feature_set allowed_archs[2]; |
c19d1205 | 31063 | }; |
7ed4c4c5 | 31064 | |
0198d5e6 TC |
31065 | /* The following table must be in alphabetical order with a NULL last entry. */ |
31066 | ||
d942732e TP |
31067 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } } |
31068 | #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} } | |
0198d5e6 | 31069 | |
34ef62f4 AV |
31070 | /* DEPRECATED: Refrain from using this table to add any new extensions, instead |
31071 | use the context sensitive approach using arm_ext_table's. */ | |
69133863 | 31072 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 31073 | { |
823d2571 TG |
31074 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
31075 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
bca38921 | 31076 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
823d2571 TG |
31077 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), |
31078 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
c604a79a JW |
31079 | ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, |
31080 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), | |
31081 | ARM_ARCH_V8_2A), | |
15afaa63 TP |
31082 | ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), |
31083 | ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP), | |
31084 | ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)), | |
823d2571 TG |
31085 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), |
31086 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
b8ec4e87 JW |
31087 | ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
31088 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), | |
31089 | ARM_ARCH_V8_2A), | |
01f48020 TC |
31090 | ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST |
31091 | | ARM_EXT2_FP16_FML), | |
31092 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | |
31093 | | ARM_EXT2_FP16_FML), | |
31094 | ARM_ARCH_V8_2A), | |
d942732e | 31095 | ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
823d2571 | 31096 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), |
d942732e TP |
31097 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
31098 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), | |
3d030cdb TP |
31099 | /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of |
31100 | Thumb divide instruction. Due to this having the same name as the | |
31101 | previous entry, this will be ignored when doing command-line parsing and | |
31102 | only considered by build attribute selection code. */ | |
31103 | ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), | |
31104 | ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), | |
31105 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7)), | |
823d2571 | 31106 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), |
d942732e | 31107 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE), |
823d2571 | 31108 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), |
d942732e | 31109 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE), |
823d2571 | 31110 | ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), |
d942732e TP |
31111 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE), |
31112 | ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
823d2571 | 31113 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP), |
d942732e TP |
31114 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A), |
31115 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)), | |
823d2571 TG |
31116 | ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), |
31117 | ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
31118 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), | |
ddfded2f MW |
31119 | ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), |
31120 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), | |
ced40572 | 31121 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
dad0c3bf SD |
31122 | ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), |
31123 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), | |
31124 | ARM_ARCH_V8A), | |
4d1464f2 MW |
31125 | ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), |
31126 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0), | |
ced40572 | 31127 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
643afb90 MW |
31128 | ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1, |
31129 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), | |
ced40572 | 31130 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), |
7fadb25d SD |
31131 | ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), |
31132 | ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), | |
31133 | ARM_ARCH_V8A), | |
d942732e | 31134 | ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
823d2571 | 31135 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
d942732e TP |
31136 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), |
31137 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
643afb90 MW |
31138 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
31139 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8), | |
31140 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
31141 | ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV |
31142 | | ARM_EXT_DIV), | |
31143 | ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), | |
31144 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
31145 | ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), | |
d942732e TP |
31146 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE), |
31147 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } } | |
69133863 | 31148 | }; |
f3bad469 | 31149 | #undef ARM_EXT_OPT |
69133863 MGD |
31150 | |
31151 | /* ISA floating-point and Advanced SIMD extensions. */ | |
31152 | struct arm_option_fpu_value_table | |
31153 | { | |
0198d5e6 TC |
31154 | const char * name; |
31155 | const arm_feature_set value; | |
c19d1205 | 31156 | }; |
7ed4c4c5 | 31157 | |
c19d1205 ZW |
31158 | /* This list should, at a minimum, contain all the fpu names |
31159 | recognized by GCC. */ | |
69133863 | 31160 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
31161 | { |
31162 | {"softfpa", FPU_NONE}, | |
31163 | {"fpe", FPU_ARCH_FPE}, | |
31164 | {"fpe2", FPU_ARCH_FPE}, | |
31165 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
31166 | {"fpa", FPU_ARCH_FPA}, | |
31167 | {"fpa10", FPU_ARCH_FPA}, | |
31168 | {"fpa11", FPU_ARCH_FPA}, | |
31169 | {"arm7500fe", FPU_ARCH_FPA}, | |
31170 | {"softvfp", FPU_ARCH_VFP}, | |
31171 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
31172 | {"vfp", FPU_ARCH_VFP_V2}, | |
31173 | {"vfp9", FPU_ARCH_VFP_V2}, | |
d5e0ba9c | 31174 | {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */ |
c19d1205 ZW |
31175 | {"vfp10", FPU_ARCH_VFP_V2}, |
31176 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
31177 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
31178 | {"vfpv2", FPU_ARCH_VFP_V2}, |
31179 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 31180 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 31181 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
31182 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
31183 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
31184 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
31185 | {"arm1020t", FPU_ARCH_VFP_V1}, |
31186 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
d5e0ba9c | 31187 | {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */ |
c19d1205 ZW |
31188 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, |
31189 | {"maverick", FPU_ARCH_MAVERICK}, | |
d5e0ba9c | 31190 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
d3375ddd | 31191 | {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 31192 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
31193 | {"vfpv4", FPU_ARCH_VFP_V4}, |
31194 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 31195 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
a715796b TG |
31196 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
31197 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, | |
62f3b8c8 | 31198 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
31199 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
31200 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
31201 | {"crypto-neon-fp-armv8", | |
31202 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
d6b4b13e | 31203 | {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1}, |
081e4c7d MW |
31204 | {"crypto-neon-fp-armv8.1", |
31205 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1}, | |
e74cfd16 PB |
31206 | {NULL, ARM_ARCH_NONE} |
31207 | }; | |
31208 | ||
31209 | struct arm_option_value_table | |
31210 | { | |
e0471c16 | 31211 | const char *name; |
e74cfd16 | 31212 | long value; |
c19d1205 | 31213 | }; |
7ed4c4c5 | 31214 | |
e74cfd16 | 31215 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
31216 | { |
31217 | {"hard", ARM_FLOAT_ABI_HARD}, | |
31218 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
31219 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 31220 | {NULL, 0} |
c19d1205 | 31221 | }; |
7ed4c4c5 | 31222 | |
c19d1205 | 31223 | #ifdef OBJ_ELF |
3a4a14e9 | 31224 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 31225 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
31226 | { |
31227 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
31228 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 31229 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 31230 | {NULL, 0} |
c19d1205 ZW |
31231 | }; |
31232 | #endif | |
7ed4c4c5 | 31233 | |
c19d1205 ZW |
31234 | struct arm_long_option_table |
31235 | { | |
0198d5e6 | 31236 | const char * option; /* Substring to match. */ |
e0471c16 | 31237 | const char * help; /* Help information. */ |
17b9d67d | 31238 | int (* func) (const char * subopt); /* Function to decode sub-option. */ |
e0471c16 | 31239 | const char * deprecated; /* If non-null, print this message. */ |
c19d1205 | 31240 | }; |
7ed4c4c5 | 31241 | |
c921be7d | 31242 | static bfd_boolean |
c168ce07 | 31243 | arm_parse_extension (const char *str, const arm_feature_set *opt_set, |
34ef62f4 AV |
31244 | arm_feature_set *ext_set, |
31245 | const struct arm_ext_table *ext_table) | |
7ed4c4c5 | 31246 | { |
69133863 | 31247 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
31248 | extensions being added before being removed. We achieve this by having |
31249 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 31250 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 31251 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
31252 | -1 -> 1 -> 0. */ |
31253 | const struct arm_option_extension_value_table * opt = NULL; | |
d942732e | 31254 | const arm_feature_set arm_any = ARM_ANY; |
69133863 MGD |
31255 | int adding_value = -1; |
31256 | ||
c19d1205 | 31257 | while (str != NULL && *str != 0) |
7ed4c4c5 | 31258 | { |
82b8a785 | 31259 | const char *ext; |
f3bad469 | 31260 | size_t len; |
7ed4c4c5 | 31261 | |
c19d1205 ZW |
31262 | if (*str != '+') |
31263 | { | |
31264 | as_bad (_("invalid architectural extension")); | |
c921be7d | 31265 | return FALSE; |
c19d1205 | 31266 | } |
7ed4c4c5 | 31267 | |
c19d1205 ZW |
31268 | str++; |
31269 | ext = strchr (str, '+'); | |
7ed4c4c5 | 31270 | |
c19d1205 | 31271 | if (ext != NULL) |
f3bad469 | 31272 | len = ext - str; |
c19d1205 | 31273 | else |
f3bad469 | 31274 | len = strlen (str); |
7ed4c4c5 | 31275 | |
f3bad469 | 31276 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
31277 | { |
31278 | if (adding_value != 0) | |
31279 | { | |
31280 | adding_value = 0; | |
31281 | opt = arm_extensions; | |
31282 | } | |
31283 | ||
f3bad469 | 31284 | len -= 2; |
69133863 MGD |
31285 | str += 2; |
31286 | } | |
f3bad469 | 31287 | else if (len > 0) |
69133863 MGD |
31288 | { |
31289 | if (adding_value == -1) | |
31290 | { | |
31291 | adding_value = 1; | |
31292 | opt = arm_extensions; | |
31293 | } | |
31294 | else if (adding_value != 1) | |
31295 | { | |
31296 | as_bad (_("must specify extensions to add before specifying " | |
31297 | "those to remove")); | |
31298 | return FALSE; | |
31299 | } | |
31300 | } | |
31301 | ||
f3bad469 | 31302 | if (len == 0) |
c19d1205 ZW |
31303 | { |
31304 | as_bad (_("missing architectural extension")); | |
c921be7d | 31305 | return FALSE; |
c19d1205 | 31306 | } |
7ed4c4c5 | 31307 | |
69133863 MGD |
31308 | gas_assert (adding_value != -1); |
31309 | gas_assert (opt != NULL); | |
31310 | ||
34ef62f4 AV |
31311 | if (ext_table != NULL) |
31312 | { | |
31313 | const struct arm_ext_table * ext_opt = ext_table; | |
31314 | bfd_boolean found = FALSE; | |
31315 | for (; ext_opt->name != NULL; ext_opt++) | |
31316 | if (ext_opt->name_len == len | |
31317 | && strncmp (ext_opt->name, str, len) == 0) | |
31318 | { | |
31319 | if (adding_value) | |
31320 | { | |
31321 | if (ARM_FEATURE_ZERO (ext_opt->merge)) | |
31322 | /* TODO: Option not supported. When we remove the | |
31323 | legacy table this case should error out. */ | |
31324 | continue; | |
31325 | ||
31326 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge); | |
31327 | } | |
31328 | else | |
31329 | { | |
31330 | if (ARM_FEATURE_ZERO (ext_opt->clear)) | |
31331 | /* TODO: Option not supported. When we remove the | |
31332 | legacy table this case should error out. */ | |
31333 | continue; | |
31334 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear); | |
31335 | } | |
31336 | found = TRUE; | |
31337 | break; | |
31338 | } | |
31339 | if (found) | |
31340 | { | |
31341 | str = ext; | |
31342 | continue; | |
31343 | } | |
31344 | } | |
31345 | ||
69133863 MGD |
31346 | /* Scan over the options table trying to find an exact match. */ |
31347 | for (; opt->name != NULL; opt++) | |
f3bad469 | 31348 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 31349 | { |
d942732e TP |
31350 | int i, nb_allowed_archs = |
31351 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); | |
69133863 | 31352 | /* Check we can apply the extension to this architecture. */ |
d942732e TP |
31353 | for (i = 0; i < nb_allowed_archs; i++) |
31354 | { | |
31355 | /* Empty entry. */ | |
31356 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any)) | |
31357 | continue; | |
c168ce07 | 31358 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set)) |
d942732e TP |
31359 | break; |
31360 | } | |
31361 | if (i == nb_allowed_archs) | |
69133863 MGD |
31362 | { |
31363 | as_bad (_("extension does not apply to the base architecture")); | |
31364 | return FALSE; | |
31365 | } | |
31366 | ||
31367 | /* Add or remove the extension. */ | |
31368 | if (adding_value) | |
4d354d8b | 31369 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
69133863 | 31370 | else |
4d354d8b | 31371 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
69133863 | 31372 | |
3d030cdb TP |
31373 | /* Allowing Thumb division instructions for ARMv7 in autodetection |
31374 | rely on this break so that duplicate extensions (extensions | |
31375 | with the same name as a previous extension in the list) are not | |
31376 | considered for command-line parsing. */ | |
c19d1205 ZW |
31377 | break; |
31378 | } | |
7ed4c4c5 | 31379 | |
c19d1205 ZW |
31380 | if (opt->name == NULL) |
31381 | { | |
69133863 MGD |
31382 | /* Did we fail to find an extension because it wasn't specified in |
31383 | alphabetical order, or because it does not exist? */ | |
31384 | ||
31385 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 31386 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
31387 | break; |
31388 | ||
31389 | if (opt->name == NULL) | |
31390 | as_bad (_("unknown architectural extension `%s'"), str); | |
31391 | else | |
31392 | as_bad (_("architectural extensions must be specified in " | |
31393 | "alphabetical order")); | |
31394 | ||
c921be7d | 31395 | return FALSE; |
c19d1205 | 31396 | } |
69133863 MGD |
31397 | else |
31398 | { | |
31399 | /* We should skip the extension we've just matched the next time | |
31400 | round. */ | |
31401 | opt++; | |
31402 | } | |
7ed4c4c5 | 31403 | |
c19d1205 ZW |
31404 | str = ext; |
31405 | }; | |
7ed4c4c5 | 31406 | |
c921be7d | 31407 | return TRUE; |
c19d1205 | 31408 | } |
7ed4c4c5 | 31409 | |
5312fe52 BW |
31410 | static bfd_boolean |
31411 | arm_parse_fp16_opt (const char *str) | |
31412 | { | |
31413 | if (strcasecmp (str, "ieee") == 0) | |
31414 | fp16_format = ARM_FP16_FORMAT_IEEE; | |
31415 | else if (strcasecmp (str, "alternative") == 0) | |
31416 | fp16_format = ARM_FP16_FORMAT_ALTERNATIVE; | |
31417 | else | |
31418 | { | |
31419 | as_bad (_("unrecognised float16 format \"%s\""), str); | |
31420 | return FALSE; | |
31421 | } | |
31422 | ||
31423 | return TRUE; | |
31424 | } | |
31425 | ||
c921be7d | 31426 | static bfd_boolean |
17b9d67d | 31427 | arm_parse_cpu (const char *str) |
7ed4c4c5 | 31428 | { |
f3bad469 | 31429 | const struct arm_cpu_option_table *opt; |
82b8a785 | 31430 | const char *ext = strchr (str, '+'); |
f3bad469 | 31431 | size_t len; |
7ed4c4c5 | 31432 | |
c19d1205 | 31433 | if (ext != NULL) |
f3bad469 | 31434 | len = ext - str; |
7ed4c4c5 | 31435 | else |
f3bad469 | 31436 | len = strlen (str); |
7ed4c4c5 | 31437 | |
f3bad469 | 31438 | if (len == 0) |
7ed4c4c5 | 31439 | { |
c19d1205 | 31440 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 31441 | return FALSE; |
7ed4c4c5 NC |
31442 | } |
31443 | ||
c19d1205 | 31444 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 31445 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 31446 | { |
c168ce07 | 31447 | mcpu_cpu_opt = &opt->value; |
4d354d8b TP |
31448 | if (mcpu_ext_opt == NULL) |
31449 | mcpu_ext_opt = XNEW (arm_feature_set); | |
31450 | *mcpu_ext_opt = opt->ext; | |
e74cfd16 | 31451 | mcpu_fpu_opt = &opt->default_fpu; |
ee065d83 | 31452 | if (opt->canonical_name) |
ef8e6722 JW |
31453 | { |
31454 | gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name)); | |
31455 | strcpy (selected_cpu_name, opt->canonical_name); | |
31456 | } | |
ee065d83 PB |
31457 | else |
31458 | { | |
f3bad469 | 31459 | size_t i; |
c921be7d | 31460 | |
ef8e6722 JW |
31461 | if (len >= sizeof selected_cpu_name) |
31462 | len = (sizeof selected_cpu_name) - 1; | |
31463 | ||
f3bad469 | 31464 | for (i = 0; i < len; i++) |
ee065d83 PB |
31465 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
31466 | selected_cpu_name[i] = 0; | |
31467 | } | |
7ed4c4c5 | 31468 | |
c19d1205 | 31469 | if (ext != NULL) |
34ef62f4 | 31470 | return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL); |
7ed4c4c5 | 31471 | |
c921be7d | 31472 | return TRUE; |
c19d1205 | 31473 | } |
7ed4c4c5 | 31474 | |
c19d1205 | 31475 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 31476 | return FALSE; |
7ed4c4c5 NC |
31477 | } |
31478 | ||
c921be7d | 31479 | static bfd_boolean |
17b9d67d | 31480 | arm_parse_arch (const char *str) |
7ed4c4c5 | 31481 | { |
e74cfd16 | 31482 | const struct arm_arch_option_table *opt; |
82b8a785 | 31483 | const char *ext = strchr (str, '+'); |
f3bad469 | 31484 | size_t len; |
7ed4c4c5 | 31485 | |
c19d1205 | 31486 | if (ext != NULL) |
f3bad469 | 31487 | len = ext - str; |
7ed4c4c5 | 31488 | else |
f3bad469 | 31489 | len = strlen (str); |
7ed4c4c5 | 31490 | |
f3bad469 | 31491 | if (len == 0) |
7ed4c4c5 | 31492 | { |
c19d1205 | 31493 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 31494 | return FALSE; |
7ed4c4c5 NC |
31495 | } |
31496 | ||
c19d1205 | 31497 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 31498 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 31499 | { |
e74cfd16 | 31500 | march_cpu_opt = &opt->value; |
4d354d8b TP |
31501 | if (march_ext_opt == NULL) |
31502 | march_ext_opt = XNEW (arm_feature_set); | |
31503 | *march_ext_opt = arm_arch_none; | |
e74cfd16 | 31504 | march_fpu_opt = &opt->default_fpu; |
5f4273c7 | 31505 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 31506 | |
c19d1205 | 31507 | if (ext != NULL) |
34ef62f4 AV |
31508 | return arm_parse_extension (ext, march_cpu_opt, march_ext_opt, |
31509 | opt->ext_table); | |
7ed4c4c5 | 31510 | |
c921be7d | 31511 | return TRUE; |
c19d1205 ZW |
31512 | } |
31513 | ||
31514 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 31515 | return FALSE; |
7ed4c4c5 | 31516 | } |
eb043451 | 31517 | |
c921be7d | 31518 | static bfd_boolean |
17b9d67d | 31519 | arm_parse_fpu (const char * str) |
c19d1205 | 31520 | { |
69133863 | 31521 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 31522 | |
c19d1205 ZW |
31523 | for (opt = arm_fpus; opt->name != NULL; opt++) |
31524 | if (streq (opt->name, str)) | |
31525 | { | |
e74cfd16 | 31526 | mfpu_opt = &opt->value; |
c921be7d | 31527 | return TRUE; |
c19d1205 | 31528 | } |
b99bd4ef | 31529 | |
c19d1205 | 31530 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 31531 | return FALSE; |
c19d1205 ZW |
31532 | } |
31533 | ||
c921be7d | 31534 | static bfd_boolean |
17b9d67d | 31535 | arm_parse_float_abi (const char * str) |
b99bd4ef | 31536 | { |
e74cfd16 | 31537 | const struct arm_option_value_table * opt; |
b99bd4ef | 31538 | |
c19d1205 ZW |
31539 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
31540 | if (streq (opt->name, str)) | |
31541 | { | |
31542 | mfloat_abi_opt = opt->value; | |
c921be7d | 31543 | return TRUE; |
c19d1205 | 31544 | } |
cc8a6dd0 | 31545 | |
c19d1205 | 31546 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 31547 | return FALSE; |
c19d1205 | 31548 | } |
b99bd4ef | 31549 | |
c19d1205 | 31550 | #ifdef OBJ_ELF |
c921be7d | 31551 | static bfd_boolean |
17b9d67d | 31552 | arm_parse_eabi (const char * str) |
c19d1205 | 31553 | { |
e74cfd16 | 31554 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 31555 | |
c19d1205 ZW |
31556 | for (opt = arm_eabis; opt->name != NULL; opt++) |
31557 | if (streq (opt->name, str)) | |
31558 | { | |
31559 | meabi_flags = opt->value; | |
c921be7d | 31560 | return TRUE; |
c19d1205 ZW |
31561 | } |
31562 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 31563 | return FALSE; |
c19d1205 ZW |
31564 | } |
31565 | #endif | |
cc8a6dd0 | 31566 | |
c921be7d | 31567 | static bfd_boolean |
17b9d67d | 31568 | arm_parse_it_mode (const char * str) |
e07e6e58 | 31569 | { |
c921be7d | 31570 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
31571 | |
31572 | if (streq ("arm", str)) | |
31573 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
31574 | else if (streq ("thumb", str)) | |
31575 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
31576 | else if (streq ("always", str)) | |
31577 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
31578 | else if (streq ("never", str)) | |
31579 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
31580 | else | |
31581 | { | |
31582 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 31583 | "arm, thumb, always, or never."), str); |
c921be7d | 31584 | ret = FALSE; |
e07e6e58 NC |
31585 | } |
31586 | ||
31587 | return ret; | |
31588 | } | |
31589 | ||
2e6976a8 | 31590 | static bfd_boolean |
17b9d67d | 31591 | arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED) |
2e6976a8 DG |
31592 | { |
31593 | codecomposer_syntax = TRUE; | |
31594 | arm_comment_chars[0] = ';'; | |
31595 | arm_line_separator_chars[0] = 0; | |
31596 | return TRUE; | |
31597 | } | |
31598 | ||
c19d1205 ZW |
31599 | struct arm_long_option_table arm_long_opts[] = |
31600 | { | |
31601 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
31602 | arm_parse_cpu, NULL}, | |
31603 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
31604 | arm_parse_arch, NULL}, | |
31605 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
31606 | arm_parse_fpu, NULL}, | |
31607 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
31608 | arm_parse_float_abi, NULL}, | |
31609 | #ifdef OBJ_ELF | |
7fac0536 | 31610 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
31611 | arm_parse_eabi, NULL}, |
31612 | #endif | |
e07e6e58 NC |
31613 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
31614 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
31615 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
31616 | arm_ccs_mode, NULL}, | |
5312fe52 BW |
31617 | {"mfp16-format=", |
31618 | N_("[ieee|alternative]\n\ | |
31619 | set the encoding for half precision floating point " | |
31620 | "numbers to IEEE\n\ | |
31621 | or Arm alternative format."), | |
31622 | arm_parse_fp16_opt, NULL }, | |
c19d1205 ZW |
31623 | {NULL, NULL, 0, NULL} |
31624 | }; | |
cc8a6dd0 | 31625 | |
c19d1205 | 31626 | int |
17b9d67d | 31627 | md_parse_option (int c, const char * arg) |
c19d1205 ZW |
31628 | { |
31629 | struct arm_option_table *opt; | |
e74cfd16 | 31630 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 31631 | struct arm_long_option_table *lopt; |
b99bd4ef | 31632 | |
c19d1205 | 31633 | switch (c) |
b99bd4ef | 31634 | { |
c19d1205 ZW |
31635 | #ifdef OPTION_EB |
31636 | case OPTION_EB: | |
31637 | target_big_endian = 1; | |
31638 | break; | |
31639 | #endif | |
cc8a6dd0 | 31640 | |
c19d1205 ZW |
31641 | #ifdef OPTION_EL |
31642 | case OPTION_EL: | |
31643 | target_big_endian = 0; | |
31644 | break; | |
31645 | #endif | |
b99bd4ef | 31646 | |
845b51d6 PB |
31647 | case OPTION_FIX_V4BX: |
31648 | fix_v4bx = TRUE; | |
31649 | break; | |
31650 | ||
18a20338 CL |
31651 | #ifdef OBJ_ELF |
31652 | case OPTION_FDPIC: | |
31653 | arm_fdpic = TRUE; | |
31654 | break; | |
31655 | #endif /* OBJ_ELF */ | |
31656 | ||
c19d1205 ZW |
31657 | case 'a': |
31658 | /* Listing option. Just ignore these, we don't support additional | |
31659 | ones. */ | |
31660 | return 0; | |
b99bd4ef | 31661 | |
c19d1205 ZW |
31662 | default: |
31663 | for (opt = arm_opts; opt->option != NULL; opt++) | |
31664 | { | |
31665 | if (c == opt->option[0] | |
31666 | && ((arg == NULL && opt->option[1] == 0) | |
31667 | || streq (arg, opt->option + 1))) | |
31668 | { | |
c19d1205 | 31669 | /* If the option is deprecated, tell the user. */ |
278df34e | 31670 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
31671 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
31672 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 31673 | |
c19d1205 ZW |
31674 | if (opt->var != NULL) |
31675 | *opt->var = opt->value; | |
cc8a6dd0 | 31676 | |
c19d1205 ZW |
31677 | return 1; |
31678 | } | |
31679 | } | |
b99bd4ef | 31680 | |
e74cfd16 PB |
31681 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
31682 | { | |
31683 | if (c == fopt->option[0] | |
31684 | && ((arg == NULL && fopt->option[1] == 0) | |
31685 | || streq (arg, fopt->option + 1))) | |
31686 | { | |
e74cfd16 | 31687 | /* If the option is deprecated, tell the user. */ |
278df34e | 31688 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
31689 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
31690 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
31691 | |
31692 | if (fopt->var != NULL) | |
31693 | *fopt->var = &fopt->value; | |
31694 | ||
31695 | return 1; | |
31696 | } | |
31697 | } | |
31698 | ||
c19d1205 ZW |
31699 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
31700 | { | |
31701 | /* These options are expected to have an argument. */ | |
31702 | if (c == lopt->option[0] | |
31703 | && arg != NULL | |
31704 | && strncmp (arg, lopt->option + 1, | |
31705 | strlen (lopt->option + 1)) == 0) | |
31706 | { | |
c19d1205 | 31707 | /* If the option is deprecated, tell the user. */ |
278df34e | 31708 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
31709 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
31710 | _(lopt->deprecated)); | |
b99bd4ef | 31711 | |
c19d1205 ZW |
31712 | /* Call the sup-option parser. */ |
31713 | return lopt->func (arg + strlen (lopt->option) - 1); | |
31714 | } | |
31715 | } | |
a737bd4d | 31716 | |
c19d1205 ZW |
31717 | return 0; |
31718 | } | |
a394c00f | 31719 | |
c19d1205 ZW |
31720 | return 1; |
31721 | } | |
a394c00f | 31722 | |
c19d1205 ZW |
31723 | void |
31724 | md_show_usage (FILE * fp) | |
a394c00f | 31725 | { |
c19d1205 ZW |
31726 | struct arm_option_table *opt; |
31727 | struct arm_long_option_table *lopt; | |
a394c00f | 31728 | |
c19d1205 | 31729 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 31730 | |
c19d1205 ZW |
31731 | for (opt = arm_opts; opt->option != NULL; opt++) |
31732 | if (opt->help != NULL) | |
31733 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 31734 | |
c19d1205 ZW |
31735 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
31736 | if (lopt->help != NULL) | |
31737 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 31738 | |
c19d1205 ZW |
31739 | #ifdef OPTION_EB |
31740 | fprintf (fp, _("\ | |
31741 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
31742 | #endif |
31743 | ||
c19d1205 ZW |
31744 | #ifdef OPTION_EL |
31745 | fprintf (fp, _("\ | |
31746 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 31747 | #endif |
845b51d6 PB |
31748 | |
31749 | fprintf (fp, _("\ | |
31750 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
18a20338 CL |
31751 | |
31752 | #ifdef OBJ_ELF | |
31753 | fprintf (fp, _("\ | |
31754 | --fdpic generate an FDPIC object file\n")); | |
31755 | #endif /* OBJ_ELF */ | |
c19d1205 | 31756 | } |
ee065d83 | 31757 | |
ee065d83 | 31758 | #ifdef OBJ_ELF |
0198d5e6 | 31759 | |
62b3e311 PB |
31760 | typedef struct |
31761 | { | |
31762 | int val; | |
31763 | arm_feature_set flags; | |
31764 | } cpu_arch_ver_table; | |
31765 | ||
2c6b98ea TP |
31766 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted |
31767 | chronologically for architectures, with an exception for ARMv6-M and | |
31768 | ARMv6S-M due to legacy reasons. No new architecture should have a | |
31769 | special case. This allows for build attribute selection results to be | |
31770 | stable when new architectures are added. */ | |
62b3e311 PB |
31771 | static const cpu_arch_ver_table cpu_arch_ver[] = |
31772 | { | |
031254f2 AV |
31773 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1}, |
31774 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2}, | |
31775 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S}, | |
31776 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3}, | |
31777 | {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M}, | |
31778 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM}, | |
31779 | {TAG_CPU_ARCH_V4, ARM_ARCH_V4}, | |
31780 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM}, | |
31781 | {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T}, | |
31782 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM}, | |
31783 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5}, | |
31784 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM}, | |
31785 | {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T}, | |
31786 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP}, | |
31787 | {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE}, | |
31788 | {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ}, | |
31789 | {TAG_CPU_ARCH_V6, ARM_ARCH_V6}, | |
31790 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z}, | |
31791 | {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ}, | |
31792 | {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K}, | |
31793 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2}, | |
31794 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2}, | |
31795 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2}, | |
31796 | {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2}, | |
2c6b98ea TP |
31797 | |
31798 | /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as | |
31799 | always selected build attributes to match those of ARMv6-M | |
31800 | (resp. ARMv6S-M). However, due to these architectures being a strict | |
31801 | subset of ARMv7-M in terms of instructions available, ARMv7-M attributes | |
31802 | would be selected when fully respecting chronology of architectures. | |
31803 | It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and | |
31804 | move them before ARMv7 architectures. */ | |
031254f2 AV |
31805 | {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M}, |
31806 | {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM}, | |
31807 | ||
31808 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7}, | |
31809 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7A}, | |
31810 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7R}, | |
31811 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7M}, | |
31812 | {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE}, | |
31813 | {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM}, | |
31814 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8A}, | |
31815 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A}, | |
31816 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A}, | |
31817 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A}, | |
31818 | {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE}, | |
31819 | {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN}, | |
31820 | {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R}, | |
31821 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A}, | |
31822 | {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A}, | |
31823 | {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN}, | |
31824 | {-1, ARM_ARCH_NONE} | |
62b3e311 PB |
31825 | }; |
31826 | ||
ee3c0378 | 31827 | /* Set an attribute if it has not already been set by the user. */ |
0198d5e6 | 31828 | |
ee3c0378 AS |
31829 | static void |
31830 | aeabi_set_attribute_int (int tag, int value) | |
31831 | { | |
31832 | if (tag < 1 | |
31833 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
31834 | || !attributes_set_explicitly[tag]) | |
31835 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
31836 | } | |
31837 | ||
31838 | static void | |
31839 | aeabi_set_attribute_string (int tag, const char *value) | |
31840 | { | |
31841 | if (tag < 1 | |
31842 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
31843 | || !attributes_set_explicitly[tag]) | |
31844 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
31845 | } | |
31846 | ||
2c6b98ea TP |
31847 | /* Return whether features in the *NEEDED feature set are available via |
31848 | extensions for the architecture whose feature set is *ARCH_FSET. */ | |
0198d5e6 | 31849 | |
2c6b98ea TP |
31850 | static bfd_boolean |
31851 | have_ext_for_needed_feat_p (const arm_feature_set *arch_fset, | |
31852 | const arm_feature_set *needed) | |
31853 | { | |
31854 | int i, nb_allowed_archs; | |
31855 | arm_feature_set ext_fset; | |
31856 | const struct arm_option_extension_value_table *opt; | |
31857 | ||
31858 | ext_fset = arm_arch_none; | |
31859 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
31860 | { | |
31861 | /* Extension does not provide any feature we need. */ | |
31862 | if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value)) | |
31863 | continue; | |
31864 | ||
31865 | nb_allowed_archs = | |
31866 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]); | |
31867 | for (i = 0; i < nb_allowed_archs; i++) | |
31868 | { | |
31869 | /* Empty entry. */ | |
31870 | if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any)) | |
31871 | break; | |
31872 | ||
31873 | /* Extension is available, add it. */ | |
31874 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset)) | |
31875 | ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value); | |
31876 | } | |
31877 | } | |
31878 | ||
31879 | /* Can we enable all features in *needed? */ | |
31880 | return ARM_FSET_CPU_SUBSET (*needed, ext_fset); | |
31881 | } | |
31882 | ||
31883 | /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for | |
31884 | a given architecture feature set *ARCH_EXT_FSET including extension feature | |
31885 | set *EXT_FSET. Selection logic used depend on EXACT_MATCH: | |
31886 | - if true, check for an exact match of the architecture modulo extensions; | |
31887 | - otherwise, select build attribute value of the first superset | |
31888 | architecture released so that results remains stable when new architectures | |
31889 | are added. | |
31890 | For -march/-mcpu=all the build attribute value of the most featureful | |
31891 | architecture is returned. Tag_CPU_arch_profile result is returned in | |
31892 | PROFILE. */ | |
0198d5e6 | 31893 | |
2c6b98ea TP |
31894 | static int |
31895 | get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset, | |
31896 | const arm_feature_set *ext_fset, | |
31897 | char *profile, int exact_match) | |
31898 | { | |
31899 | arm_feature_set arch_fset; | |
31900 | const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL; | |
31901 | ||
31902 | /* Select most featureful architecture with all its extensions if building | |
31903 | for -march=all as the feature sets used to set build attributes. */ | |
31904 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any)) | |
31905 | { | |
31906 | /* Force revisiting of decision for each new architecture. */ | |
031254f2 | 31907 | gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN); |
2c6b98ea TP |
31908 | *profile = 'A'; |
31909 | return TAG_CPU_ARCH_V8; | |
31910 | } | |
31911 | ||
31912 | ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset); | |
31913 | ||
31914 | for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++) | |
31915 | { | |
31916 | arm_feature_set known_arch_fset; | |
31917 | ||
31918 | ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any); | |
31919 | if (exact_match) | |
31920 | { | |
31921 | /* Base architecture match user-specified architecture and | |
31922 | extensions, eg. ARMv6S-M matching -march=armv6-m+os. */ | |
31923 | if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset)) | |
31924 | { | |
31925 | p_ver_ret = p_ver; | |
31926 | goto found; | |
31927 | } | |
31928 | /* Base architecture match user-specified architecture only | |
31929 | (eg. ARMv6-M in the same case as above). Record it in case we | |
31930 | find a match with above condition. */ | |
31931 | else if (p_ver_ret == NULL | |
31932 | && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset)) | |
31933 | p_ver_ret = p_ver; | |
31934 | } | |
31935 | else | |
31936 | { | |
31937 | ||
31938 | /* Architecture has all features wanted. */ | |
31939 | if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset)) | |
31940 | { | |
31941 | arm_feature_set added_fset; | |
31942 | ||
31943 | /* Compute features added by this architecture over the one | |
31944 | recorded in p_ver_ret. */ | |
31945 | if (p_ver_ret != NULL) | |
31946 | ARM_CLEAR_FEATURE (added_fset, known_arch_fset, | |
31947 | p_ver_ret->flags); | |
31948 | /* First architecture that match incl. with extensions, or the | |
31949 | only difference in features over the recorded match is | |
31950 | features that were optional and are now mandatory. */ | |
31951 | if (p_ver_ret == NULL | |
31952 | || ARM_FSET_CPU_SUBSET (added_fset, arch_fset)) | |
31953 | { | |
31954 | p_ver_ret = p_ver; | |
31955 | goto found; | |
31956 | } | |
31957 | } | |
31958 | else if (p_ver_ret == NULL) | |
31959 | { | |
31960 | arm_feature_set needed_ext_fset; | |
31961 | ||
31962 | ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset); | |
31963 | ||
31964 | /* Architecture has all features needed when using some | |
31965 | extensions. Record it and continue searching in case there | |
31966 | exist an architecture providing all needed features without | |
31967 | the need for extensions (eg. ARMv6S-M Vs ARMv6-M with | |
31968 | OS extension). */ | |
31969 | if (have_ext_for_needed_feat_p (&known_arch_fset, | |
31970 | &needed_ext_fset)) | |
31971 | p_ver_ret = p_ver; | |
31972 | } | |
31973 | } | |
31974 | } | |
31975 | ||
31976 | if (p_ver_ret == NULL) | |
31977 | return -1; | |
31978 | ||
31979 | found: | |
31980 | /* Tag_CPU_arch_profile. */ | |
31981 | if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a) | |
31982 | || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8) | |
31983 | || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics) | |
31984 | && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))) | |
31985 | *profile = 'A'; | |
31986 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)) | |
31987 | *profile = 'R'; | |
31988 | else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m)) | |
31989 | *profile = 'M'; | |
31990 | else | |
31991 | *profile = '\0'; | |
31992 | return p_ver_ret->val; | |
31993 | } | |
31994 | ||
ee065d83 | 31995 | /* Set the public EABI object attributes. */ |
0198d5e6 | 31996 | |
c168ce07 | 31997 | static void |
ee065d83 PB |
31998 | aeabi_set_public_attributes (void) |
31999 | { | |
b90d5ba0 | 32000 | char profile = '\0'; |
2c6b98ea | 32001 | int arch = -1; |
90ec0d68 | 32002 | int virt_sec = 0; |
bca38921 | 32003 | int fp16_optional = 0; |
2c6b98ea TP |
32004 | int skip_exact_match = 0; |
32005 | arm_feature_set flags, flags_arch, flags_ext; | |
ee065d83 | 32006 | |
54bab281 TP |
32007 | /* Autodetection mode, choose the architecture based the instructions |
32008 | actually used. */ | |
32009 | if (no_cpu_selected ()) | |
32010 | { | |
32011 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); | |
ddd7f988 | 32012 | |
54bab281 TP |
32013 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) |
32014 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
ddd7f988 | 32015 | |
54bab281 TP |
32016 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) |
32017 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
ddd7f988 | 32018 | |
54bab281 | 32019 | /* Code run during relaxation relies on selected_cpu being set. */ |
4d354d8b TP |
32020 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
32021 | flags_ext = arm_arch_none; | |
32022 | ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext); | |
32023 | selected_ext = flags_ext; | |
54bab281 TP |
32024 | selected_cpu = flags; |
32025 | } | |
32026 | /* Otherwise, choose the architecture based on the capabilities of the | |
32027 | requested cpu. */ | |
32028 | else | |
4d354d8b TP |
32029 | { |
32030 | ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext); | |
32031 | ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any); | |
32032 | flags_ext = selected_ext; | |
32033 | flags = selected_cpu; | |
32034 | } | |
32035 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu); | |
7f78eb34 | 32036 | |
ddd7f988 | 32037 | /* Allow the user to override the reported architecture. */ |
4d354d8b | 32038 | if (!ARM_FEATURE_ZERO (selected_object_arch)) |
7a1d4c38 | 32039 | { |
4d354d8b | 32040 | ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any); |
2c6b98ea | 32041 | flags_ext = arm_arch_none; |
7a1d4c38 | 32042 | } |
2c6b98ea | 32043 | else |
4d354d8b | 32044 | skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any); |
2c6b98ea TP |
32045 | |
32046 | /* When this function is run again after relaxation has happened there is no | |
32047 | way to determine whether an architecture or CPU was specified by the user: | |
32048 | - selected_cpu is set above for relaxation to work; | |
32049 | - march_cpu_opt is not set if only -mcpu or .cpu is used; | |
32050 | - mcpu_cpu_opt is set to arm_arch_any for autodetection. | |
32051 | Therefore, if not in -march=all case we first try an exact match and fall | |
32052 | back to autodetection. */ | |
32053 | if (!skip_exact_match) | |
32054 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1); | |
32055 | if (arch == -1) | |
32056 | arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0); | |
32057 | if (arch == -1) | |
32058 | as_bad (_("no architecture contains all the instructions used\n")); | |
9e3c6df6 | 32059 | |
ee065d83 PB |
32060 | /* Tag_CPU_name. */ |
32061 | if (selected_cpu_name[0]) | |
32062 | { | |
91d6fa6a | 32063 | char *q; |
ee065d83 | 32064 | |
91d6fa6a NC |
32065 | q = selected_cpu_name; |
32066 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
32067 | { |
32068 | int i; | |
5f4273c7 | 32069 | |
91d6fa6a NC |
32070 | q += 4; |
32071 | for (i = 0; q[i]; i++) | |
32072 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 32073 | } |
91d6fa6a | 32074 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 32075 | } |
62f3b8c8 | 32076 | |
ee065d83 | 32077 | /* Tag_CPU_arch. */ |
ee3c0378 | 32078 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 32079 | |
62b3e311 | 32080 | /* Tag_CPU_arch_profile. */ |
69239280 MGD |
32081 | if (profile != '\0') |
32082 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 32083 | |
15afaa63 | 32084 | /* Tag_DSP_extension. */ |
4d354d8b | 32085 | if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp)) |
6c290d53 | 32086 | aeabi_set_attribute_int (Tag_DSP_extension, 1); |
15afaa63 | 32087 | |
2c6b98ea | 32088 | ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any); |
ee065d83 | 32089 | /* Tag_ARM_ISA_use. */ |
ee3c0378 | 32090 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
2c6b98ea | 32091 | || ARM_FEATURE_ZERO (flags_arch)) |
ee3c0378 | 32092 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); |
62f3b8c8 | 32093 | |
ee065d83 | 32094 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 | 32095 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
2c6b98ea | 32096 | || ARM_FEATURE_ZERO (flags_arch)) |
4ed7ed8d TP |
32097 | { |
32098 | int thumb_isa_use; | |
32099 | ||
32100 | if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) | |
16a1fa25 | 32101 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)) |
4ed7ed8d TP |
32102 | thumb_isa_use = 3; |
32103 | else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2)) | |
32104 | thumb_isa_use = 2; | |
32105 | else | |
32106 | thumb_isa_use = 1; | |
32107 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use); | |
32108 | } | |
62f3b8c8 | 32109 | |
ee065d83 | 32110 | /* Tag_VFP_arch. */ |
a715796b TG |
32111 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
32112 | aeabi_set_attribute_int (Tag_VFP_arch, | |
32113 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
32114 | ? 7 : 8); | |
bca38921 | 32115 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
62f3b8c8 PB |
32116 | aeabi_set_attribute_int (Tag_VFP_arch, |
32117 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
32118 | ? 5 : 6); | |
32119 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
32120 | { |
32121 | fp16_optional = 1; | |
32122 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
32123 | } | |
ada65aa3 | 32124 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
32125 | { |
32126 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
32127 | fp16_optional = 1; | |
32128 | } | |
ee3c0378 AS |
32129 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
32130 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
32131 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 32132 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 32133 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 32134 | |
4547cb56 NC |
32135 | /* Tag_ABI_HardFP_use. */ |
32136 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
32137 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
32138 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
32139 | ||
ee065d83 | 32140 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
32141 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
32142 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
32143 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
32144 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 32145 | |
ee3c0378 | 32146 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
9411fd44 MW |
32147 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1)) |
32148 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4); | |
32149 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) | |
bca38921 MGD |
32150 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); |
32151 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
32152 | { | |
32153 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
32154 | { | |
32155 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
32156 | } | |
32157 | else | |
32158 | { | |
32159 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
32160 | fp16_optional = 1; | |
32161 | } | |
32162 | } | |
fa94de6b | 32163 | |
a7ad558c AV |
32164 | if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext)) |
32165 | aeabi_set_attribute_int (Tag_MVE_arch, 2); | |
32166 | else if (ARM_CPU_HAS_FEATURE (flags, mve_ext)) | |
32167 | aeabi_set_attribute_int (Tag_MVE_arch, 1); | |
32168 | ||
ee3c0378 | 32169 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 32170 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 32171 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 32172 | |
69239280 MGD |
32173 | /* Tag_DIV_use. |
32174 | ||
32175 | We set Tag_DIV_use to two when integer divide instructions have been used | |
32176 | in ARM state, or when Thumb integer divide instructions have been used, | |
32177 | but we have no architecture profile set, nor have we any ARM instructions. | |
32178 | ||
4ed7ed8d TP |
32179 | For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied |
32180 | by the base architecture. | |
bca38921 | 32181 | |
69239280 | 32182 | For new architectures we will have to check these tests. */ |
031254f2 | 32183 | gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN); |
4ed7ed8d TP |
32184 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) |
32185 | || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)) | |
bca38921 MGD |
32186 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
32187 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
32188 | || (profile == '\0' | |
32189 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
32190 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 32191 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
32192 | |
32193 | /* Tag_MP_extension_use. */ | |
32194 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
32195 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
32196 | |
32197 | /* Tag Virtualization_use. */ | |
32198 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
32199 | virt_sec |= 1; |
32200 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
32201 | virt_sec |= 2; | |
32202 | if (virt_sec != 0) | |
32203 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
5312fe52 BW |
32204 | |
32205 | if (fp16_format != ARM_FP16_FORMAT_DEFAULT) | |
32206 | aeabi_set_attribute_int (Tag_ABI_FP_16bit_format, fp16_format); | |
ee065d83 PB |
32207 | } |
32208 | ||
c168ce07 TP |
32209 | /* Post relaxation hook. Recompute ARM attributes now that relaxation is |
32210 | finished and free extension feature bits which will not be used anymore. */ | |
0198d5e6 | 32211 | |
c168ce07 TP |
32212 | void |
32213 | arm_md_post_relax (void) | |
32214 | { | |
32215 | aeabi_set_public_attributes (); | |
4d354d8b TP |
32216 | XDELETE (mcpu_ext_opt); |
32217 | mcpu_ext_opt = NULL; | |
32218 | XDELETE (march_ext_opt); | |
32219 | march_ext_opt = NULL; | |
c168ce07 TP |
32220 | } |
32221 | ||
104d59d1 | 32222 | /* Add the default contents for the .ARM.attributes section. */ |
0198d5e6 | 32223 | |
ee065d83 PB |
32224 | void |
32225 | arm_md_end (void) | |
32226 | { | |
ee065d83 PB |
32227 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
32228 | return; | |
32229 | ||
32230 | aeabi_set_public_attributes (); | |
ee065d83 | 32231 | } |
8463be01 | 32232 | #endif /* OBJ_ELF */ |
ee065d83 | 32233 | |
ee065d83 PB |
32234 | /* Parse a .cpu directive. */ |
32235 | ||
32236 | static void | |
32237 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
32238 | { | |
e74cfd16 | 32239 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
32240 | char *name; |
32241 | char saved_char; | |
32242 | ||
32243 | name = input_line_pointer; | |
5f4273c7 | 32244 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
32245 | input_line_pointer++; |
32246 | saved_char = *input_line_pointer; | |
32247 | *input_line_pointer = 0; | |
32248 | ||
32249 | /* Skip the first "all" entry. */ | |
32250 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
32251 | if (streq (opt->name, name)) | |
32252 | { | |
4d354d8b TP |
32253 | selected_arch = opt->value; |
32254 | selected_ext = opt->ext; | |
32255 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); | |
ee065d83 | 32256 | if (opt->canonical_name) |
5f4273c7 | 32257 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
32258 | else |
32259 | { | |
32260 | int i; | |
32261 | for (i = 0; opt->name[i]; i++) | |
32262 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 32263 | |
ee065d83 PB |
32264 | selected_cpu_name[i] = 0; |
32265 | } | |
4d354d8b TP |
32266 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
32267 | ||
ee065d83 PB |
32268 | *input_line_pointer = saved_char; |
32269 | demand_empty_rest_of_line (); | |
32270 | return; | |
32271 | } | |
32272 | as_bad (_("unknown cpu `%s'"), name); | |
32273 | *input_line_pointer = saved_char; | |
32274 | ignore_rest_of_line (); | |
32275 | } | |
32276 | ||
ee065d83 PB |
32277 | /* Parse a .arch directive. */ |
32278 | ||
32279 | static void | |
32280 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
32281 | { | |
e74cfd16 | 32282 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
32283 | char saved_char; |
32284 | char *name; | |
32285 | ||
32286 | name = input_line_pointer; | |
5f4273c7 | 32287 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
32288 | input_line_pointer++; |
32289 | saved_char = *input_line_pointer; | |
32290 | *input_line_pointer = 0; | |
32291 | ||
32292 | /* Skip the first "all" entry. */ | |
32293 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
32294 | if (streq (opt->name, name)) | |
32295 | { | |
4d354d8b TP |
32296 | selected_arch = opt->value; |
32297 | selected_ext = arm_arch_none; | |
32298 | selected_cpu = selected_arch; | |
5f4273c7 | 32299 | strcpy (selected_cpu_name, opt->name); |
4d354d8b | 32300 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); |
ee065d83 PB |
32301 | *input_line_pointer = saved_char; |
32302 | demand_empty_rest_of_line (); | |
32303 | return; | |
32304 | } | |
32305 | ||
32306 | as_bad (_("unknown architecture `%s'\n"), name); | |
32307 | *input_line_pointer = saved_char; | |
32308 | ignore_rest_of_line (); | |
32309 | } | |
32310 | ||
7a1d4c38 PB |
32311 | /* Parse a .object_arch directive. */ |
32312 | ||
32313 | static void | |
32314 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
32315 | { | |
32316 | const struct arm_arch_option_table *opt; | |
32317 | char saved_char; | |
32318 | char *name; | |
32319 | ||
32320 | name = input_line_pointer; | |
5f4273c7 | 32321 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
32322 | input_line_pointer++; |
32323 | saved_char = *input_line_pointer; | |
32324 | *input_line_pointer = 0; | |
32325 | ||
32326 | /* Skip the first "all" entry. */ | |
32327 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
32328 | if (streq (opt->name, name)) | |
32329 | { | |
4d354d8b | 32330 | selected_object_arch = opt->value; |
7a1d4c38 PB |
32331 | *input_line_pointer = saved_char; |
32332 | demand_empty_rest_of_line (); | |
32333 | return; | |
32334 | } | |
32335 | ||
32336 | as_bad (_("unknown architecture `%s'\n"), name); | |
32337 | *input_line_pointer = saved_char; | |
32338 | ignore_rest_of_line (); | |
32339 | } | |
32340 | ||
69133863 MGD |
32341 | /* Parse a .arch_extension directive. */ |
32342 | ||
32343 | static void | |
32344 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
32345 | { | |
32346 | const struct arm_option_extension_value_table *opt; | |
32347 | char saved_char; | |
32348 | char *name; | |
32349 | int adding_value = 1; | |
32350 | ||
32351 | name = input_line_pointer; | |
32352 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
32353 | input_line_pointer++; | |
32354 | saved_char = *input_line_pointer; | |
32355 | *input_line_pointer = 0; | |
32356 | ||
32357 | if (strlen (name) >= 2 | |
32358 | && strncmp (name, "no", 2) == 0) | |
32359 | { | |
32360 | adding_value = 0; | |
32361 | name += 2; | |
32362 | } | |
32363 | ||
32364 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
32365 | if (streq (opt->name, name)) | |
32366 | { | |
d942732e TP |
32367 | int i, nb_allowed_archs = |
32368 | sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]); | |
32369 | for (i = 0; i < nb_allowed_archs; i++) | |
32370 | { | |
32371 | /* Empty entry. */ | |
4d354d8b | 32372 | if (ARM_CPU_IS_ANY (opt->allowed_archs[i])) |
d942732e | 32373 | continue; |
4d354d8b | 32374 | if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch)) |
d942732e TP |
32375 | break; |
32376 | } | |
32377 | ||
32378 | if (i == nb_allowed_archs) | |
69133863 MGD |
32379 | { |
32380 | as_bad (_("architectural extension `%s' is not allowed for the " | |
32381 | "current base architecture"), name); | |
32382 | break; | |
32383 | } | |
32384 | ||
32385 | if (adding_value) | |
4d354d8b | 32386 | ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext, |
5a70a223 | 32387 | opt->merge_value); |
69133863 | 32388 | else |
4d354d8b | 32389 | ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value); |
69133863 | 32390 | |
4d354d8b TP |
32391 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext); |
32392 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); | |
69133863 MGD |
32393 | *input_line_pointer = saved_char; |
32394 | demand_empty_rest_of_line (); | |
3d030cdb TP |
32395 | /* Allowing Thumb division instructions for ARMv7 in autodetection rely |
32396 | on this return so that duplicate extensions (extensions with the | |
32397 | same name as a previous extension in the list) are not considered | |
32398 | for command-line parsing. */ | |
69133863 MGD |
32399 | return; |
32400 | } | |
32401 | ||
32402 | if (opt->name == NULL) | |
e673710a | 32403 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
32404 | |
32405 | *input_line_pointer = saved_char; | |
32406 | ignore_rest_of_line (); | |
32407 | } | |
32408 | ||
ee065d83 PB |
32409 | /* Parse a .fpu directive. */ |
32410 | ||
32411 | static void | |
32412 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
32413 | { | |
69133863 | 32414 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
32415 | char saved_char; |
32416 | char *name; | |
32417 | ||
32418 | name = input_line_pointer; | |
5f4273c7 | 32419 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
32420 | input_line_pointer++; |
32421 | saved_char = *input_line_pointer; | |
32422 | *input_line_pointer = 0; | |
5f4273c7 | 32423 | |
ee065d83 PB |
32424 | for (opt = arm_fpus; opt->name != NULL; opt++) |
32425 | if (streq (opt->name, name)) | |
32426 | { | |
4d354d8b TP |
32427 | selected_fpu = opt->value; |
32428 | #ifndef CPU_DEFAULT | |
32429 | if (no_cpu_selected ()) | |
32430 | ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu); | |
32431 | else | |
32432 | #endif | |
32433 | ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu); | |
ee065d83 PB |
32434 | *input_line_pointer = saved_char; |
32435 | demand_empty_rest_of_line (); | |
32436 | return; | |
32437 | } | |
32438 | ||
32439 | as_bad (_("unknown floating point format `%s'\n"), name); | |
32440 | *input_line_pointer = saved_char; | |
32441 | ignore_rest_of_line (); | |
32442 | } | |
ee065d83 | 32443 | |
794ba86a | 32444 | /* Copy symbol information. */ |
f31fef98 | 32445 | |
794ba86a DJ |
32446 | void |
32447 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
32448 | { | |
32449 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
32450 | } | |
e04befd0 | 32451 | |
f31fef98 | 32452 | #ifdef OBJ_ELF |
e04befd0 AS |
32453 | /* Given a symbolic attribute NAME, return the proper integer value. |
32454 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 32455 | |
e04befd0 AS |
32456 | int |
32457 | arm_convert_symbolic_attribute (const char *name) | |
32458 | { | |
f31fef98 NC |
32459 | static const struct |
32460 | { | |
32461 | const char * name; | |
32462 | const int tag; | |
32463 | } | |
32464 | attribute_table[] = | |
32465 | { | |
32466 | /* When you modify this table you should | |
32467 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 32468 | #define T(tag) {#tag, tag} |
f31fef98 NC |
32469 | T (Tag_CPU_raw_name), |
32470 | T (Tag_CPU_name), | |
32471 | T (Tag_CPU_arch), | |
32472 | T (Tag_CPU_arch_profile), | |
32473 | T (Tag_ARM_ISA_use), | |
32474 | T (Tag_THUMB_ISA_use), | |
75375b3e | 32475 | T (Tag_FP_arch), |
f31fef98 NC |
32476 | T (Tag_VFP_arch), |
32477 | T (Tag_WMMX_arch), | |
32478 | T (Tag_Advanced_SIMD_arch), | |
32479 | T (Tag_PCS_config), | |
32480 | T (Tag_ABI_PCS_R9_use), | |
32481 | T (Tag_ABI_PCS_RW_data), | |
32482 | T (Tag_ABI_PCS_RO_data), | |
32483 | T (Tag_ABI_PCS_GOT_use), | |
32484 | T (Tag_ABI_PCS_wchar_t), | |
32485 | T (Tag_ABI_FP_rounding), | |
32486 | T (Tag_ABI_FP_denormal), | |
32487 | T (Tag_ABI_FP_exceptions), | |
32488 | T (Tag_ABI_FP_user_exceptions), | |
32489 | T (Tag_ABI_FP_number_model), | |
75375b3e | 32490 | T (Tag_ABI_align_needed), |
f31fef98 | 32491 | T (Tag_ABI_align8_needed), |
75375b3e | 32492 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
32493 | T (Tag_ABI_align8_preserved), |
32494 | T (Tag_ABI_enum_size), | |
32495 | T (Tag_ABI_HardFP_use), | |
32496 | T (Tag_ABI_VFP_args), | |
32497 | T (Tag_ABI_WMMX_args), | |
32498 | T (Tag_ABI_optimization_goals), | |
32499 | T (Tag_ABI_FP_optimization_goals), | |
32500 | T (Tag_compatibility), | |
32501 | T (Tag_CPU_unaligned_access), | |
75375b3e | 32502 | T (Tag_FP_HP_extension), |
f31fef98 NC |
32503 | T (Tag_VFP_HP_extension), |
32504 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
32505 | T (Tag_MPextension_use), |
32506 | T (Tag_DIV_use), | |
f31fef98 NC |
32507 | T (Tag_nodefaults), |
32508 | T (Tag_also_compatible_with), | |
32509 | T (Tag_conformance), | |
32510 | T (Tag_T2EE_use), | |
32511 | T (Tag_Virtualization_use), | |
15afaa63 | 32512 | T (Tag_DSP_extension), |
a7ad558c | 32513 | T (Tag_MVE_arch), |
cd21e546 | 32514 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 32515 | #undef T |
f31fef98 | 32516 | }; |
e04befd0 AS |
32517 | unsigned int i; |
32518 | ||
32519 | if (name == NULL) | |
32520 | return -1; | |
32521 | ||
f31fef98 | 32522 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 32523 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
32524 | return attribute_table[i].tag; |
32525 | ||
32526 | return -1; | |
32527 | } | |
267bf995 | 32528 | |
93ef582d NC |
32529 | /* Apply sym value for relocations only in the case that they are for |
32530 | local symbols in the same segment as the fixup and you have the | |
32531 | respective architectural feature for blx and simple switches. */ | |
0198d5e6 | 32532 | |
267bf995 | 32533 | int |
93ef582d | 32534 | arm_apply_sym_value (struct fix * fixP, segT this_seg) |
267bf995 RR |
32535 | { |
32536 | if (fixP->fx_addsy | |
32537 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
93ef582d NC |
32538 | /* PR 17444: If the local symbol is in a different section then a reloc |
32539 | will always be generated for it, so applying the symbol value now | |
32540 | will result in a double offset being stored in the relocation. */ | |
32541 | && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg) | |
34e77a92 | 32542 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
32543 | { |
32544 | switch (fixP->fx_r_type) | |
32545 | { | |
32546 | case BFD_RELOC_ARM_PCREL_BLX: | |
32547 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
32548 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
32549 | return 1; | |
32550 | break; | |
32551 | ||
32552 | case BFD_RELOC_ARM_PCREL_CALL: | |
32553 | case BFD_RELOC_THUMB_PCREL_BLX: | |
32554 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
93ef582d | 32555 | return 1; |
267bf995 RR |
32556 | break; |
32557 | ||
32558 | default: | |
32559 | break; | |
32560 | } | |
32561 | ||
32562 | } | |
32563 | return 0; | |
32564 | } | |
f31fef98 | 32565 | #endif /* OBJ_ELF */ |