Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
4a58c4bd | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 MGD |
100 | /* The code that was here used to select a default CPU depending on compiler |
101 | pre-defines which were only present when doing native builds, thus | |
102 | changing gas' default behaviour depending upon the build host. | |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
7e806470 | 198 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 199 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 200 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 201 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 202 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 203 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 204 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
205 | |
206 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
207 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
208 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
209 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 210 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 211 | |
2d447fca JM |
212 | static const arm_feature_set arm_cext_iwmmxt2 = |
213 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
214 | static const arm_feature_set arm_cext_iwmmxt = |
215 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
216 | static const arm_feature_set arm_cext_xscale = | |
217 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
218 | static const arm_feature_set arm_cext_maverick = | |
219 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
220 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
221 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
222 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
223 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
224 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
225 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 226 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 227 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
228 | static const arm_feature_set fpu_vfp_ext_d32 = |
229 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
230 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
231 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
232 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
233 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
234 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
235 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
e74cfd16 | 236 | |
33a392fb | 237 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
238 | /* Record user cpu selection for object attributes. */ |
239 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
240 | /* Must be long enough to hold any of the names in arm_cpus. */ |
241 | static char selected_cpu_name[16]; | |
7cc69913 | 242 | #ifdef OBJ_ELF |
deeaaff8 DJ |
243 | # ifdef EABI_DEFAULT |
244 | static int meabi_flags = EABI_DEFAULT; | |
245 | # else | |
d507cf36 | 246 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 247 | # endif |
e1da3f5b | 248 | |
ee3c0378 AS |
249 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
250 | ||
e1da3f5b | 251 | bfd_boolean |
5f4273c7 | 252 | arm_is_eabi (void) |
e1da3f5b PB |
253 | { |
254 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
255 | } | |
7cc69913 | 256 | #endif |
b99bd4ef | 257 | |
b99bd4ef | 258 | #ifdef OBJ_ELF |
c19d1205 | 259 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
260 | symbolS * GOT_symbol; |
261 | #endif | |
262 | ||
b99bd4ef NC |
263 | /* 0: assemble for ARM, |
264 | 1: assemble for Thumb, | |
265 | 2: assemble for Thumb even though target CPU does not support thumb | |
266 | instructions. */ | |
267 | static int thumb_mode = 0; | |
8dc2430f NC |
268 | /* A value distinct from the possible values for thumb_mode that we |
269 | can use to record whether thumb_mode has been copied into the | |
270 | tc_frag_data field of a frag. */ | |
271 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 272 | |
e07e6e58 NC |
273 | /* Specifies the intrinsic IT insn behavior mode. */ |
274 | enum implicit_it_mode | |
275 | { | |
276 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
277 | IMPLICIT_IT_MODE_ARM = 0x01, | |
278 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
279 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
280 | }; | |
281 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
282 | ||
c19d1205 ZW |
283 | /* If unified_syntax is true, we are processing the new unified |
284 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
285 | ||
286 | - Immediate operands do not require a # prefix. | |
287 | - Conditional affixes always appear at the end of the | |
288 | instruction. (For backward compatibility, those instructions | |
289 | that formerly had them in the middle, continue to accept them | |
290 | there.) | |
291 | - The IT instruction may appear, and if it does is validated | |
292 | against subsequent conditional affixes. It does not generate | |
293 | machine code. | |
294 | ||
295 | Important differences from the old Thumb mode: | |
296 | ||
297 | - Immediate operands do not require a # prefix. | |
298 | - Most of the V6T2 instructions are only available in unified mode. | |
299 | - The .N and .W suffixes are recognized and honored (it is an error | |
300 | if they cannot be honored). | |
301 | - All instructions set the flags if and only if they have an 's' affix. | |
302 | - Conditional affixes may be used. They are validated against | |
303 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
304 | conditional affix except in the scope of an IT instruction. */ | |
305 | ||
306 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 307 | |
5287ad62 JB |
308 | enum neon_el_type |
309 | { | |
dcbf9037 | 310 | NT_invtype, |
5287ad62 JB |
311 | NT_untyped, |
312 | NT_integer, | |
313 | NT_float, | |
314 | NT_poly, | |
315 | NT_signed, | |
dcbf9037 | 316 | NT_unsigned |
5287ad62 JB |
317 | }; |
318 | ||
319 | struct neon_type_el | |
320 | { | |
321 | enum neon_el_type type; | |
322 | unsigned size; | |
323 | }; | |
324 | ||
325 | #define NEON_MAX_TYPE_ELS 4 | |
326 | ||
327 | struct neon_type | |
328 | { | |
329 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
330 | unsigned elems; | |
331 | }; | |
332 | ||
e07e6e58 NC |
333 | enum it_instruction_type |
334 | { | |
335 | OUTSIDE_IT_INSN, | |
336 | INSIDE_IT_INSN, | |
337 | INSIDE_IT_LAST_INSN, | |
338 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
339 | if inside, should be the last one. */ | |
340 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
341 | i.e. BKPT and NOP. */ | |
342 | IT_INSN /* The IT insn has been parsed. */ | |
343 | }; | |
344 | ||
b99bd4ef NC |
345 | struct arm_it |
346 | { | |
c19d1205 | 347 | const char * error; |
b99bd4ef | 348 | unsigned long instruction; |
c19d1205 ZW |
349 | int size; |
350 | int size_req; | |
351 | int cond; | |
037e8744 JB |
352 | /* "uncond_value" is set to the value in place of the conditional field in |
353 | unconditional versions of the instruction, or -1 if nothing is | |
354 | appropriate. */ | |
355 | int uncond_value; | |
5287ad62 | 356 | struct neon_type vectype; |
88714cb8 DG |
357 | /* This does not indicate an actual NEON instruction, only that |
358 | the mnemonic accepts neon-style type suffixes. */ | |
359 | int is_neon; | |
0110f2b8 PB |
360 | /* Set to the opcode if the instruction needs relaxation. |
361 | Zero if the instruction is not relaxed. */ | |
362 | unsigned long relax; | |
b99bd4ef NC |
363 | struct |
364 | { | |
365 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
366 | expressionS exp; |
367 | int pc_rel; | |
b99bd4ef | 368 | } reloc; |
b99bd4ef | 369 | |
e07e6e58 NC |
370 | enum it_instruction_type it_insn_type; |
371 | ||
c19d1205 ZW |
372 | struct |
373 | { | |
374 | unsigned reg; | |
ca3f61f7 | 375 | signed int imm; |
dcbf9037 | 376 | struct neon_type_el vectype; |
ca3f61f7 NC |
377 | unsigned present : 1; /* Operand present. */ |
378 | unsigned isreg : 1; /* Operand was a register. */ | |
379 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
380 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
381 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 382 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
383 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
384 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
385 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 386 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 387 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 388 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
389 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
390 | unsigned writeback : 1; /* Operand has trailing ! */ | |
391 | unsigned preind : 1; /* Preindexed address. */ | |
392 | unsigned postind : 1; /* Postindexed address. */ | |
393 | unsigned negative : 1; /* Index register was negated. */ | |
394 | unsigned shifted : 1; /* Shift applied to operation. */ | |
395 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 396 | } operands[6]; |
b99bd4ef NC |
397 | }; |
398 | ||
c19d1205 | 399 | static struct arm_it inst; |
b99bd4ef NC |
400 | |
401 | #define NUM_FLOAT_VALS 8 | |
402 | ||
05d2d07e | 403 | const char * fp_const[] = |
b99bd4ef NC |
404 | { |
405 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
406 | }; | |
407 | ||
c19d1205 | 408 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
409 | #define MAX_LITTLENUMS 6 |
410 | ||
411 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
412 | ||
413 | #define FAIL (-1) | |
414 | #define SUCCESS (0) | |
415 | ||
416 | #define SUFF_S 1 | |
417 | #define SUFF_D 2 | |
418 | #define SUFF_E 3 | |
419 | #define SUFF_P 4 | |
420 | ||
c19d1205 ZW |
421 | #define CP_T_X 0x00008000 |
422 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 423 | |
c19d1205 ZW |
424 | #define CONDS_BIT 0x00100000 |
425 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
426 | |
427 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
428 | ||
429 | struct asm_cond | |
430 | { | |
d3ce72d0 | 431 | const char * template_name; |
c921be7d | 432 | unsigned long value; |
b99bd4ef NC |
433 | }; |
434 | ||
c19d1205 | 435 | #define COND_ALWAYS 0xE |
b99bd4ef | 436 | |
b99bd4ef NC |
437 | struct asm_psr |
438 | { | |
d3ce72d0 | 439 | const char * template_name; |
c921be7d | 440 | unsigned long field; |
b99bd4ef NC |
441 | }; |
442 | ||
62b3e311 PB |
443 | struct asm_barrier_opt |
444 | { | |
d3ce72d0 | 445 | const char * template_name; |
c921be7d | 446 | unsigned long value; |
62b3e311 PB |
447 | }; |
448 | ||
2d2255b5 | 449 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
450 | #define SPSR_BIT (1 << 22) |
451 | ||
c19d1205 ZW |
452 | /* The individual PSR flag bits. */ |
453 | #define PSR_c (1 << 16) | |
454 | #define PSR_x (1 << 17) | |
455 | #define PSR_s (1 << 18) | |
456 | #define PSR_f (1 << 19) | |
b99bd4ef | 457 | |
c19d1205 | 458 | struct reloc_entry |
bfae80f2 | 459 | { |
c921be7d NC |
460 | char * name; |
461 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
462 | }; |
463 | ||
5287ad62 | 464 | enum vfp_reg_pos |
bfae80f2 | 465 | { |
5287ad62 JB |
466 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
467 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
468 | }; |
469 | ||
470 | enum vfp_ldstm_type | |
471 | { | |
472 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
473 | }; | |
474 | ||
dcbf9037 JB |
475 | /* Bits for DEFINED field in neon_typed_alias. */ |
476 | #define NTA_HASTYPE 1 | |
477 | #define NTA_HASINDEX 2 | |
478 | ||
479 | struct neon_typed_alias | |
480 | { | |
c921be7d NC |
481 | unsigned char defined; |
482 | unsigned char index; | |
483 | struct neon_type_el eltype; | |
dcbf9037 JB |
484 | }; |
485 | ||
c19d1205 ZW |
486 | /* ARM register categories. This includes coprocessor numbers and various |
487 | architecture extensions' registers. */ | |
488 | enum arm_reg_type | |
bfae80f2 | 489 | { |
c19d1205 ZW |
490 | REG_TYPE_RN, |
491 | REG_TYPE_CP, | |
492 | REG_TYPE_CN, | |
493 | REG_TYPE_FN, | |
494 | REG_TYPE_VFS, | |
495 | REG_TYPE_VFD, | |
5287ad62 | 496 | REG_TYPE_NQ, |
037e8744 | 497 | REG_TYPE_VFSD, |
5287ad62 | 498 | REG_TYPE_NDQ, |
037e8744 | 499 | REG_TYPE_NSDQ, |
c19d1205 ZW |
500 | REG_TYPE_VFC, |
501 | REG_TYPE_MVF, | |
502 | REG_TYPE_MVD, | |
503 | REG_TYPE_MVFX, | |
504 | REG_TYPE_MVDX, | |
505 | REG_TYPE_MVAX, | |
506 | REG_TYPE_DSPSC, | |
507 | REG_TYPE_MMXWR, | |
508 | REG_TYPE_MMXWC, | |
509 | REG_TYPE_MMXWCG, | |
510 | REG_TYPE_XSCALE, | |
90ec0d68 | 511 | REG_TYPE_RNB |
bfae80f2 RE |
512 | }; |
513 | ||
dcbf9037 JB |
514 | /* Structure for a hash table entry for a register. |
515 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
516 | information which states whether a vector type or index is specified (for a | |
517 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
518 | struct reg_entry |
519 | { | |
c921be7d | 520 | const char * name; |
90ec0d68 | 521 | unsigned int number; |
c921be7d NC |
522 | unsigned char type; |
523 | unsigned char builtin; | |
524 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
525 | }; |
526 | ||
c19d1205 | 527 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 528 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
529 | { |
530 | N_("ARM register expected"), | |
531 | N_("bad or missing co-processor number"), | |
532 | N_("co-processor register expected"), | |
533 | N_("FPA register expected"), | |
534 | N_("VFP single precision register expected"), | |
5287ad62 JB |
535 | N_("VFP/Neon double precision register expected"), |
536 | N_("Neon quad precision register expected"), | |
037e8744 | 537 | N_("VFP single or double precision register expected"), |
5287ad62 | 538 | N_("Neon double or quad precision register expected"), |
037e8744 | 539 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
540 | N_("VFP system register expected"), |
541 | N_("Maverick MVF register expected"), | |
542 | N_("Maverick MVD register expected"), | |
543 | N_("Maverick MVFX register expected"), | |
544 | N_("Maverick MVDX register expected"), | |
545 | N_("Maverick MVAX register expected"), | |
546 | N_("Maverick DSPSC register expected"), | |
547 | N_("iWMMXt data register expected"), | |
548 | N_("iWMMXt control register expected"), | |
549 | N_("iWMMXt scalar register expected"), | |
550 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
551 | }; |
552 | ||
c19d1205 ZW |
553 | /* Some well known registers that we refer to directly elsewhere. */ |
554 | #define REG_SP 13 | |
555 | #define REG_LR 14 | |
556 | #define REG_PC 15 | |
404ff6b5 | 557 | |
b99bd4ef NC |
558 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
559 | take 2: */ | |
c19d1205 | 560 | #define INSN_SIZE 4 |
b99bd4ef NC |
561 | |
562 | struct asm_opcode | |
563 | { | |
564 | /* Basic string to match. */ | |
d3ce72d0 | 565 | const char * template_name; |
c19d1205 ZW |
566 | |
567 | /* Parameters to instruction. */ | |
5be8be5d | 568 | unsigned int operands[8]; |
c19d1205 ZW |
569 | |
570 | /* Conditional tag - see opcode_lookup. */ | |
571 | unsigned int tag : 4; | |
b99bd4ef NC |
572 | |
573 | /* Basic instruction code. */ | |
c19d1205 | 574 | unsigned int avalue : 28; |
b99bd4ef | 575 | |
c19d1205 ZW |
576 | /* Thumb-format instruction code. */ |
577 | unsigned int tvalue; | |
b99bd4ef | 578 | |
90e4755a | 579 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
580 | const arm_feature_set * avariant; |
581 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
582 | |
583 | /* Function to call to encode instruction in ARM format. */ | |
584 | void (* aencode) (void); | |
b99bd4ef | 585 | |
c19d1205 ZW |
586 | /* Function to call to encode instruction in Thumb format. */ |
587 | void (* tencode) (void); | |
b99bd4ef NC |
588 | }; |
589 | ||
a737bd4d NC |
590 | /* Defines for various bits that we will want to toggle. */ |
591 | #define INST_IMMEDIATE 0x02000000 | |
592 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 593 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
594 | #define SHIFT_BY_REG 0x00000010 |
595 | #define PRE_INDEX 0x01000000 | |
596 | #define INDEX_UP 0x00800000 | |
597 | #define WRITE_BACK 0x00200000 | |
598 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 599 | #define CPSI_MMOD 0x00020000 |
90e4755a | 600 | |
a737bd4d NC |
601 | #define LITERAL_MASK 0xf000f000 |
602 | #define OPCODE_MASK 0xfe1fffff | |
603 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 604 | |
efd81785 PB |
605 | #define T2_SUBS_PC_LR 0xf3de8f00 |
606 | ||
a737bd4d | 607 | #define DATA_OP_SHIFT 21 |
90e4755a | 608 | |
ef8d22e6 PB |
609 | #define T2_OPCODE_MASK 0xfe1fffff |
610 | #define T2_DATA_OP_SHIFT 21 | |
611 | ||
a737bd4d NC |
612 | /* Codes to distinguish the arithmetic instructions. */ |
613 | #define OPCODE_AND 0 | |
614 | #define OPCODE_EOR 1 | |
615 | #define OPCODE_SUB 2 | |
616 | #define OPCODE_RSB 3 | |
617 | #define OPCODE_ADD 4 | |
618 | #define OPCODE_ADC 5 | |
619 | #define OPCODE_SBC 6 | |
620 | #define OPCODE_RSC 7 | |
621 | #define OPCODE_TST 8 | |
622 | #define OPCODE_TEQ 9 | |
623 | #define OPCODE_CMP 10 | |
624 | #define OPCODE_CMN 11 | |
625 | #define OPCODE_ORR 12 | |
626 | #define OPCODE_MOV 13 | |
627 | #define OPCODE_BIC 14 | |
628 | #define OPCODE_MVN 15 | |
90e4755a | 629 | |
ef8d22e6 PB |
630 | #define T2_OPCODE_AND 0 |
631 | #define T2_OPCODE_BIC 1 | |
632 | #define T2_OPCODE_ORR 2 | |
633 | #define T2_OPCODE_ORN 3 | |
634 | #define T2_OPCODE_EOR 4 | |
635 | #define T2_OPCODE_ADD 8 | |
636 | #define T2_OPCODE_ADC 10 | |
637 | #define T2_OPCODE_SBC 11 | |
638 | #define T2_OPCODE_SUB 13 | |
639 | #define T2_OPCODE_RSB 14 | |
640 | ||
a737bd4d NC |
641 | #define T_OPCODE_MUL 0x4340 |
642 | #define T_OPCODE_TST 0x4200 | |
643 | #define T_OPCODE_CMN 0x42c0 | |
644 | #define T_OPCODE_NEG 0x4240 | |
645 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 646 | |
a737bd4d NC |
647 | #define T_OPCODE_ADD_R3 0x1800 |
648 | #define T_OPCODE_SUB_R3 0x1a00 | |
649 | #define T_OPCODE_ADD_HI 0x4400 | |
650 | #define T_OPCODE_ADD_ST 0xb000 | |
651 | #define T_OPCODE_SUB_ST 0xb080 | |
652 | #define T_OPCODE_ADD_SP 0xa800 | |
653 | #define T_OPCODE_ADD_PC 0xa000 | |
654 | #define T_OPCODE_ADD_I8 0x3000 | |
655 | #define T_OPCODE_SUB_I8 0x3800 | |
656 | #define T_OPCODE_ADD_I3 0x1c00 | |
657 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 658 | |
a737bd4d NC |
659 | #define T_OPCODE_ASR_R 0x4100 |
660 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
661 | #define T_OPCODE_LSR_R 0x40c0 |
662 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
663 | #define T_OPCODE_ASR_I 0x1000 |
664 | #define T_OPCODE_LSL_I 0x0000 | |
665 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 666 | |
a737bd4d NC |
667 | #define T_OPCODE_MOV_I8 0x2000 |
668 | #define T_OPCODE_CMP_I8 0x2800 | |
669 | #define T_OPCODE_CMP_LR 0x4280 | |
670 | #define T_OPCODE_MOV_HR 0x4600 | |
671 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 672 | |
a737bd4d NC |
673 | #define T_OPCODE_LDR_PC 0x4800 |
674 | #define T_OPCODE_LDR_SP 0x9800 | |
675 | #define T_OPCODE_STR_SP 0x9000 | |
676 | #define T_OPCODE_LDR_IW 0x6800 | |
677 | #define T_OPCODE_STR_IW 0x6000 | |
678 | #define T_OPCODE_LDR_IH 0x8800 | |
679 | #define T_OPCODE_STR_IH 0x8000 | |
680 | #define T_OPCODE_LDR_IB 0x7800 | |
681 | #define T_OPCODE_STR_IB 0x7000 | |
682 | #define T_OPCODE_LDR_RW 0x5800 | |
683 | #define T_OPCODE_STR_RW 0x5000 | |
684 | #define T_OPCODE_LDR_RH 0x5a00 | |
685 | #define T_OPCODE_STR_RH 0x5200 | |
686 | #define T_OPCODE_LDR_RB 0x5c00 | |
687 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 688 | |
a737bd4d NC |
689 | #define T_OPCODE_PUSH 0xb400 |
690 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 691 | |
2fc8bdac | 692 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 693 | |
a737bd4d | 694 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 695 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 696 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 697 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
698 | |
699 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 700 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
701 | #define BAD_PC _("r15 not allowed here") |
702 | #define BAD_COND _("instruction cannot be conditional") | |
703 | #define BAD_OVERLAP _("registers may not be the same") | |
704 | #define BAD_HIREG _("lo register required") | |
705 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 706 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
707 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
708 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 709 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
710 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
711 | #define BAD_IT_COND _("incorrect condition in IT block") | |
712 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 713 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
714 | #define BAD_PC_ADDRESSING \ |
715 | _("cannot use register index with PC-relative addressing") | |
716 | #define BAD_PC_WRITEBACK \ | |
717 | _("cannot use writeback with PC-relative addressing") | |
c19d1205 | 718 | |
c921be7d NC |
719 | static struct hash_control * arm_ops_hsh; |
720 | static struct hash_control * arm_cond_hsh; | |
721 | static struct hash_control * arm_shift_hsh; | |
722 | static struct hash_control * arm_psr_hsh; | |
723 | static struct hash_control * arm_v7m_psr_hsh; | |
724 | static struct hash_control * arm_reg_hsh; | |
725 | static struct hash_control * arm_reloc_hsh; | |
726 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 727 | |
b99bd4ef NC |
728 | /* Stuff needed to resolve the label ambiguity |
729 | As: | |
730 | ... | |
731 | label: <insn> | |
732 | may differ from: | |
733 | ... | |
734 | label: | |
5f4273c7 | 735 | <insn> */ |
b99bd4ef NC |
736 | |
737 | symbolS * last_label_seen; | |
b34976b6 | 738 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 739 | |
3d0c9500 NC |
740 | /* Literal pool structure. Held on a per-section |
741 | and per-sub-section basis. */ | |
a737bd4d | 742 | |
c19d1205 | 743 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 744 | typedef struct literal_pool |
b99bd4ef | 745 | { |
c921be7d NC |
746 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
747 | unsigned int next_free_entry; | |
748 | unsigned int id; | |
749 | symbolS * symbol; | |
750 | segT section; | |
751 | subsegT sub_section; | |
752 | struct literal_pool * next; | |
3d0c9500 | 753 | } literal_pool; |
b99bd4ef | 754 | |
3d0c9500 NC |
755 | /* Pointer to a linked list of literal pools. */ |
756 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 757 | |
e07e6e58 NC |
758 | #ifdef OBJ_ELF |
759 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
760 | #else | |
761 | static struct current_it now_it; | |
762 | #endif | |
763 | ||
764 | static inline int | |
765 | now_it_compatible (int cond) | |
766 | { | |
767 | return (cond & ~1) == (now_it.cc & ~1); | |
768 | } | |
769 | ||
770 | static inline int | |
771 | conditional_insn (void) | |
772 | { | |
773 | return inst.cond != COND_ALWAYS; | |
774 | } | |
775 | ||
776 | static int in_it_block (void); | |
777 | ||
778 | static int handle_it_state (void); | |
779 | ||
780 | static void force_automatic_it_block_close (void); | |
781 | ||
c921be7d NC |
782 | static void it_fsm_post_encode (void); |
783 | ||
e07e6e58 NC |
784 | #define set_it_insn_type(type) \ |
785 | do \ | |
786 | { \ | |
787 | inst.it_insn_type = type; \ | |
788 | if (handle_it_state () == FAIL) \ | |
789 | return; \ | |
790 | } \ | |
791 | while (0) | |
792 | ||
c921be7d NC |
793 | #define set_it_insn_type_nonvoid(type, failret) \ |
794 | do \ | |
795 | { \ | |
796 | inst.it_insn_type = type; \ | |
797 | if (handle_it_state () == FAIL) \ | |
798 | return failret; \ | |
799 | } \ | |
800 | while(0) | |
801 | ||
e07e6e58 NC |
802 | #define set_it_insn_type_last() \ |
803 | do \ | |
804 | { \ | |
805 | if (inst.cond == COND_ALWAYS) \ | |
806 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
807 | else \ | |
808 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
809 | } \ | |
810 | while (0) | |
811 | ||
c19d1205 | 812 | /* Pure syntax. */ |
b99bd4ef | 813 | |
c19d1205 ZW |
814 | /* This array holds the chars that always start a comment. If the |
815 | pre-processor is disabled, these aren't very useful. */ | |
816 | const char comment_chars[] = "@"; | |
3d0c9500 | 817 | |
c19d1205 ZW |
818 | /* This array holds the chars that only start a comment at the beginning of |
819 | a line. If the line seems to have the form '# 123 filename' | |
820 | .line and .file directives will appear in the pre-processed output. */ | |
821 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
822 | first line of the input file. This is because the compiler outputs | |
823 | #NO_APP at the beginning of its output. */ | |
824 | /* Also note that comments like this one will always work. */ | |
825 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 826 | |
c19d1205 | 827 | const char line_separator_chars[] = ";"; |
b99bd4ef | 828 | |
c19d1205 ZW |
829 | /* Chars that can be used to separate mant |
830 | from exp in floating point numbers. */ | |
831 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 832 | |
c19d1205 ZW |
833 | /* Chars that mean this number is a floating point constant. */ |
834 | /* As in 0f12.456 */ | |
835 | /* or 0d1.2345e12 */ | |
b99bd4ef | 836 | |
c19d1205 | 837 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 838 | |
c19d1205 ZW |
839 | /* Prefix characters that indicate the start of an immediate |
840 | value. */ | |
841 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 842 | |
c19d1205 ZW |
843 | /* Separator character handling. */ |
844 | ||
845 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
846 | ||
847 | static inline int | |
848 | skip_past_char (char ** str, char c) | |
849 | { | |
850 | if (**str == c) | |
851 | { | |
852 | (*str)++; | |
853 | return SUCCESS; | |
3d0c9500 | 854 | } |
c19d1205 ZW |
855 | else |
856 | return FAIL; | |
857 | } | |
c921be7d | 858 | |
c19d1205 | 859 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 860 | |
c19d1205 ZW |
861 | /* Arithmetic expressions (possibly involving symbols). */ |
862 | ||
863 | /* Return TRUE if anything in the expression is a bignum. */ | |
864 | ||
865 | static int | |
866 | walk_no_bignums (symbolS * sp) | |
867 | { | |
868 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
869 | return 1; | |
870 | ||
871 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 872 | { |
c19d1205 ZW |
873 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
874 | || (symbol_get_value_expression (sp)->X_op_symbol | |
875 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
876 | } |
877 | ||
c19d1205 | 878 | return 0; |
3d0c9500 NC |
879 | } |
880 | ||
c19d1205 ZW |
881 | static int in_my_get_expression = 0; |
882 | ||
883 | /* Third argument to my_get_expression. */ | |
884 | #define GE_NO_PREFIX 0 | |
885 | #define GE_IMM_PREFIX 1 | |
886 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
887 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
888 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
889 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 890 | |
b99bd4ef | 891 | static int |
c19d1205 | 892 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 893 | { |
c19d1205 ZW |
894 | char * save_in; |
895 | segT seg; | |
b99bd4ef | 896 | |
c19d1205 ZW |
897 | /* In unified syntax, all prefixes are optional. */ |
898 | if (unified_syntax) | |
5287ad62 JB |
899 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
900 | : GE_OPT_PREFIX; | |
b99bd4ef | 901 | |
c19d1205 | 902 | switch (prefix_mode) |
b99bd4ef | 903 | { |
c19d1205 ZW |
904 | case GE_NO_PREFIX: break; |
905 | case GE_IMM_PREFIX: | |
906 | if (!is_immediate_prefix (**str)) | |
907 | { | |
908 | inst.error = _("immediate expression requires a # prefix"); | |
909 | return FAIL; | |
910 | } | |
911 | (*str)++; | |
912 | break; | |
913 | case GE_OPT_PREFIX: | |
5287ad62 | 914 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
915 | if (is_immediate_prefix (**str)) |
916 | (*str)++; | |
917 | break; | |
918 | default: abort (); | |
919 | } | |
b99bd4ef | 920 | |
c19d1205 | 921 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 922 | |
c19d1205 ZW |
923 | save_in = input_line_pointer; |
924 | input_line_pointer = *str; | |
925 | in_my_get_expression = 1; | |
926 | seg = expression (ep); | |
927 | in_my_get_expression = 0; | |
928 | ||
f86adc07 | 929 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 930 | { |
f86adc07 | 931 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
932 | *str = input_line_pointer; |
933 | input_line_pointer = save_in; | |
934 | if (inst.error == NULL) | |
f86adc07 NS |
935 | inst.error = (ep->X_op == O_absent |
936 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
937 | return 1; |
938 | } | |
b99bd4ef | 939 | |
c19d1205 ZW |
940 | #ifdef OBJ_AOUT |
941 | if (seg != absolute_section | |
942 | && seg != text_section | |
943 | && seg != data_section | |
944 | && seg != bss_section | |
945 | && seg != undefined_section) | |
946 | { | |
947 | inst.error = _("bad segment"); | |
948 | *str = input_line_pointer; | |
949 | input_line_pointer = save_in; | |
950 | return 1; | |
b99bd4ef | 951 | } |
87975d2a AM |
952 | #else |
953 | (void) seg; | |
c19d1205 | 954 | #endif |
b99bd4ef | 955 | |
c19d1205 ZW |
956 | /* Get rid of any bignums now, so that we don't generate an error for which |
957 | we can't establish a line number later on. Big numbers are never valid | |
958 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
959 | if (prefix_mode != GE_OPT_PREFIX_BIG |
960 | && (ep->X_op == O_big | |
961 | || (ep->X_add_symbol | |
962 | && (walk_no_bignums (ep->X_add_symbol) | |
963 | || (ep->X_op_symbol | |
964 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
965 | { |
966 | inst.error = _("invalid constant"); | |
967 | *str = input_line_pointer; | |
968 | input_line_pointer = save_in; | |
969 | return 1; | |
970 | } | |
b99bd4ef | 971 | |
c19d1205 ZW |
972 | *str = input_line_pointer; |
973 | input_line_pointer = save_in; | |
974 | return 0; | |
b99bd4ef NC |
975 | } |
976 | ||
c19d1205 ZW |
977 | /* Turn a string in input_line_pointer into a floating point constant |
978 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
979 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
980 | returned, or NULL on OK. | |
b99bd4ef | 981 | |
c19d1205 ZW |
982 | Note that fp constants aren't represent in the normal way on the ARM. |
983 | In big endian mode, things are as expected. However, in little endian | |
984 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
985 | within the words. For example, (double) 1.1 in big endian mode is | |
986 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
987 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 988 | |
c19d1205 | 989 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 990 | |
c19d1205 ZW |
991 | char * |
992 | md_atof (int type, char * litP, int * sizeP) | |
993 | { | |
994 | int prec; | |
995 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
996 | char *t; | |
997 | int i; | |
b99bd4ef | 998 | |
c19d1205 ZW |
999 | switch (type) |
1000 | { | |
1001 | case 'f': | |
1002 | case 'F': | |
1003 | case 's': | |
1004 | case 'S': | |
1005 | prec = 2; | |
1006 | break; | |
b99bd4ef | 1007 | |
c19d1205 ZW |
1008 | case 'd': |
1009 | case 'D': | |
1010 | case 'r': | |
1011 | case 'R': | |
1012 | prec = 4; | |
1013 | break; | |
b99bd4ef | 1014 | |
c19d1205 ZW |
1015 | case 'x': |
1016 | case 'X': | |
499ac353 | 1017 | prec = 5; |
c19d1205 | 1018 | break; |
b99bd4ef | 1019 | |
c19d1205 ZW |
1020 | case 'p': |
1021 | case 'P': | |
499ac353 | 1022 | prec = 5; |
c19d1205 | 1023 | break; |
a737bd4d | 1024 | |
c19d1205 ZW |
1025 | default: |
1026 | *sizeP = 0; | |
499ac353 | 1027 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1028 | } |
b99bd4ef | 1029 | |
c19d1205 ZW |
1030 | t = atof_ieee (input_line_pointer, type, words); |
1031 | if (t) | |
1032 | input_line_pointer = t; | |
499ac353 | 1033 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1034 | |
c19d1205 ZW |
1035 | if (target_big_endian) |
1036 | { | |
1037 | for (i = 0; i < prec; i++) | |
1038 | { | |
499ac353 NC |
1039 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1040 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1041 | } |
1042 | } | |
1043 | else | |
1044 | { | |
e74cfd16 | 1045 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1046 | for (i = prec - 1; i >= 0; i--) |
1047 | { | |
499ac353 NC |
1048 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1049 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1050 | } |
1051 | else | |
1052 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1053 | For an 8 byte float the order is 1 0 3 2. */ | |
1054 | for (i = 0; i < prec; i += 2) | |
1055 | { | |
499ac353 NC |
1056 | md_number_to_chars (litP, (valueT) words[i + 1], |
1057 | sizeof (LITTLENUM_TYPE)); | |
1058 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1059 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1060 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1061 | } |
1062 | } | |
b99bd4ef | 1063 | |
499ac353 | 1064 | return NULL; |
c19d1205 | 1065 | } |
b99bd4ef | 1066 | |
c19d1205 ZW |
1067 | /* We handle all bad expressions here, so that we can report the faulty |
1068 | instruction in the error message. */ | |
1069 | void | |
91d6fa6a | 1070 | md_operand (expressionS * exp) |
c19d1205 ZW |
1071 | { |
1072 | if (in_my_get_expression) | |
91d6fa6a | 1073 | exp->X_op = O_illegal; |
b99bd4ef NC |
1074 | } |
1075 | ||
c19d1205 | 1076 | /* Immediate values. */ |
b99bd4ef | 1077 | |
c19d1205 ZW |
1078 | /* Generic immediate-value read function for use in directives. |
1079 | Accepts anything that 'expression' can fold to a constant. | |
1080 | *val receives the number. */ | |
1081 | #ifdef OBJ_ELF | |
1082 | static int | |
1083 | immediate_for_directive (int *val) | |
b99bd4ef | 1084 | { |
c19d1205 ZW |
1085 | expressionS exp; |
1086 | exp.X_op = O_illegal; | |
b99bd4ef | 1087 | |
c19d1205 ZW |
1088 | if (is_immediate_prefix (*input_line_pointer)) |
1089 | { | |
1090 | input_line_pointer++; | |
1091 | expression (&exp); | |
1092 | } | |
b99bd4ef | 1093 | |
c19d1205 ZW |
1094 | if (exp.X_op != O_constant) |
1095 | { | |
1096 | as_bad (_("expected #constant")); | |
1097 | ignore_rest_of_line (); | |
1098 | return FAIL; | |
1099 | } | |
1100 | *val = exp.X_add_number; | |
1101 | return SUCCESS; | |
b99bd4ef | 1102 | } |
c19d1205 | 1103 | #endif |
b99bd4ef | 1104 | |
c19d1205 | 1105 | /* Register parsing. */ |
b99bd4ef | 1106 | |
c19d1205 ZW |
1107 | /* Generic register parser. CCP points to what should be the |
1108 | beginning of a register name. If it is indeed a valid register | |
1109 | name, advance CCP over it and return the reg_entry structure; | |
1110 | otherwise return NULL. Does not issue diagnostics. */ | |
1111 | ||
1112 | static struct reg_entry * | |
1113 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1114 | { |
c19d1205 ZW |
1115 | char *start = *ccp; |
1116 | char *p; | |
1117 | struct reg_entry *reg; | |
b99bd4ef | 1118 | |
c19d1205 ZW |
1119 | #ifdef REGISTER_PREFIX |
1120 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1121 | return NULL; |
c19d1205 ZW |
1122 | start++; |
1123 | #endif | |
1124 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1125 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1126 | start++; | |
1127 | #endif | |
b99bd4ef | 1128 | |
c19d1205 ZW |
1129 | p = start; |
1130 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1131 | return NULL; | |
b99bd4ef | 1132 | |
c19d1205 ZW |
1133 | do |
1134 | p++; | |
1135 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1136 | ||
1137 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1138 | ||
1139 | if (!reg) | |
1140 | return NULL; | |
1141 | ||
1142 | *ccp = p; | |
1143 | return reg; | |
b99bd4ef NC |
1144 | } |
1145 | ||
1146 | static int | |
dcbf9037 JB |
1147 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1148 | enum arm_reg_type type) | |
b99bd4ef | 1149 | { |
c19d1205 ZW |
1150 | /* Alternative syntaxes are accepted for a few register classes. */ |
1151 | switch (type) | |
1152 | { | |
1153 | case REG_TYPE_MVF: | |
1154 | case REG_TYPE_MVD: | |
1155 | case REG_TYPE_MVFX: | |
1156 | case REG_TYPE_MVDX: | |
1157 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1158 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1159 | return reg->number; |
1160 | break; | |
69b97547 | 1161 | |
c19d1205 ZW |
1162 | case REG_TYPE_CP: |
1163 | /* For backward compatibility, a bare number is valid here. */ | |
1164 | { | |
1165 | unsigned long processor = strtoul (start, ccp, 10); | |
1166 | if (*ccp != start && processor <= 15) | |
1167 | return processor; | |
1168 | } | |
6057a28f | 1169 | |
c19d1205 ZW |
1170 | case REG_TYPE_MMXWC: |
1171 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1172 | instructions that take WC registers. */ | |
79134647 | 1173 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1174 | return reg->number; |
6057a28f | 1175 | break; |
c19d1205 | 1176 | |
6057a28f | 1177 | default: |
c19d1205 | 1178 | break; |
6057a28f NC |
1179 | } |
1180 | ||
dcbf9037 JB |
1181 | return FAIL; |
1182 | } | |
1183 | ||
1184 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1185 | return value is the register number or FAIL. */ | |
1186 | ||
1187 | static int | |
1188 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1189 | { | |
1190 | char *start = *ccp; | |
1191 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1192 | int ret; | |
1193 | ||
1194 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1195 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1196 | return FAIL; | |
1197 | ||
1198 | if (reg && reg->type == type) | |
1199 | return reg->number; | |
1200 | ||
1201 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1202 | return ret; | |
1203 | ||
c19d1205 ZW |
1204 | *ccp = start; |
1205 | return FAIL; | |
1206 | } | |
69b97547 | 1207 | |
dcbf9037 JB |
1208 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1209 | character. Does no verification at this stage that the type fits the opcode | |
1210 | properly. E.g., | |
1211 | ||
1212 | .i32.i32.s16 | |
1213 | .s32.f32 | |
1214 | .u16 | |
1215 | ||
1216 | Can all be legally parsed by this function. | |
1217 | ||
1218 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1219 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1220 | type, FAIL if not. */ | |
1221 | ||
1222 | static int | |
1223 | parse_neon_type (struct neon_type *type, char **str) | |
1224 | { | |
1225 | char *ptr = *str; | |
1226 | ||
1227 | if (type) | |
1228 | type->elems = 0; | |
1229 | ||
1230 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1231 | { | |
1232 | enum neon_el_type thistype = NT_untyped; | |
1233 | unsigned thissize = -1u; | |
1234 | ||
1235 | if (*ptr != '.') | |
1236 | break; | |
1237 | ||
1238 | ptr++; | |
1239 | ||
1240 | /* Just a size without an explicit type. */ | |
1241 | if (ISDIGIT (*ptr)) | |
1242 | goto parsesize; | |
1243 | ||
1244 | switch (TOLOWER (*ptr)) | |
1245 | { | |
1246 | case 'i': thistype = NT_integer; break; | |
1247 | case 'f': thistype = NT_float; break; | |
1248 | case 'p': thistype = NT_poly; break; | |
1249 | case 's': thistype = NT_signed; break; | |
1250 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1251 | case 'd': |
1252 | thistype = NT_float; | |
1253 | thissize = 64; | |
1254 | ptr++; | |
1255 | goto done; | |
dcbf9037 JB |
1256 | default: |
1257 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1258 | return FAIL; | |
1259 | } | |
1260 | ||
1261 | ptr++; | |
1262 | ||
1263 | /* .f is an abbreviation for .f32. */ | |
1264 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1265 | thissize = 32; | |
1266 | else | |
1267 | { | |
1268 | parsesize: | |
1269 | thissize = strtoul (ptr, &ptr, 10); | |
1270 | ||
1271 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1272 | && thissize != 64) | |
1273 | { | |
1274 | as_bad (_("bad size %d in type specifier"), thissize); | |
1275 | return FAIL; | |
1276 | } | |
1277 | } | |
1278 | ||
037e8744 | 1279 | done: |
dcbf9037 JB |
1280 | if (type) |
1281 | { | |
1282 | type->el[type->elems].type = thistype; | |
1283 | type->el[type->elems].size = thissize; | |
1284 | type->elems++; | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | /* Empty/missing type is not a successful parse. */ | |
1289 | if (type->elems == 0) | |
1290 | return FAIL; | |
1291 | ||
1292 | *str = ptr; | |
1293 | ||
1294 | return SUCCESS; | |
1295 | } | |
1296 | ||
1297 | /* Errors may be set multiple times during parsing or bit encoding | |
1298 | (particularly in the Neon bits), but usually the earliest error which is set | |
1299 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1300 | errors by calling this function. */ | |
1301 | ||
1302 | static void | |
1303 | first_error (const char *err) | |
1304 | { | |
1305 | if (!inst.error) | |
1306 | inst.error = err; | |
1307 | } | |
1308 | ||
1309 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1310 | static int | |
1311 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1312 | { | |
1313 | char *str = *ccp; | |
1314 | struct neon_type optype; | |
1315 | ||
1316 | if (*str == '.') | |
1317 | { | |
1318 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1319 | { | |
1320 | if (optype.elems == 1) | |
1321 | *vectype = optype.el[0]; | |
1322 | else | |
1323 | { | |
1324 | first_error (_("only one type should be specified for operand")); | |
1325 | return FAIL; | |
1326 | } | |
1327 | } | |
1328 | else | |
1329 | { | |
1330 | first_error (_("vector type expected")); | |
1331 | return FAIL; | |
1332 | } | |
1333 | } | |
1334 | else | |
1335 | return FAIL; | |
5f4273c7 | 1336 | |
dcbf9037 | 1337 | *ccp = str; |
5f4273c7 | 1338 | |
dcbf9037 JB |
1339 | return SUCCESS; |
1340 | } | |
1341 | ||
1342 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1343 | a 4-bit integer. */ | |
1344 | ||
1345 | #define NEON_ALL_LANES 15 | |
1346 | #define NEON_INTERLEAVE_LANES 14 | |
1347 | ||
1348 | /* Parse either a register or a scalar, with an optional type. Return the | |
1349 | register number, and optionally fill in the actual type of the register | |
1350 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1351 | type/index information in *TYPEINFO. */ | |
1352 | ||
1353 | static int | |
1354 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1355 | enum arm_reg_type *rtype, | |
1356 | struct neon_typed_alias *typeinfo) | |
1357 | { | |
1358 | char *str = *ccp; | |
1359 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1360 | struct neon_typed_alias atype; | |
1361 | struct neon_type_el parsetype; | |
1362 | ||
1363 | atype.defined = 0; | |
1364 | atype.index = -1; | |
1365 | atype.eltype.type = NT_invtype; | |
1366 | atype.eltype.size = -1; | |
1367 | ||
1368 | /* Try alternate syntax for some types of register. Note these are mutually | |
1369 | exclusive with the Neon syntax extensions. */ | |
1370 | if (reg == NULL) | |
1371 | { | |
1372 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1373 | if (altreg != FAIL) | |
1374 | *ccp = str; | |
1375 | if (typeinfo) | |
1376 | *typeinfo = atype; | |
1377 | return altreg; | |
1378 | } | |
1379 | ||
037e8744 JB |
1380 | /* Undo polymorphism when a set of register types may be accepted. */ |
1381 | if ((type == REG_TYPE_NDQ | |
1382 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1383 | || (type == REG_TYPE_VFSD | |
1384 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1385 | || (type == REG_TYPE_NSDQ | |
1386 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1387 | || reg->type == REG_TYPE_NQ)) |
1388 | || (type == REG_TYPE_MMXWC | |
1389 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1390 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1391 | |
1392 | if (type != reg->type) | |
1393 | return FAIL; | |
1394 | ||
1395 | if (reg->neon) | |
1396 | atype = *reg->neon; | |
5f4273c7 | 1397 | |
dcbf9037 JB |
1398 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1399 | { | |
1400 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1401 | { | |
1402 | first_error (_("can't redefine type for operand")); | |
1403 | return FAIL; | |
1404 | } | |
1405 | atype.defined |= NTA_HASTYPE; | |
1406 | atype.eltype = parsetype; | |
1407 | } | |
5f4273c7 | 1408 | |
dcbf9037 JB |
1409 | if (skip_past_char (&str, '[') == SUCCESS) |
1410 | { | |
1411 | if (type != REG_TYPE_VFD) | |
1412 | { | |
1413 | first_error (_("only D registers may be indexed")); | |
1414 | return FAIL; | |
1415 | } | |
5f4273c7 | 1416 | |
dcbf9037 JB |
1417 | if ((atype.defined & NTA_HASINDEX) != 0) |
1418 | { | |
1419 | first_error (_("can't change index for operand")); | |
1420 | return FAIL; | |
1421 | } | |
1422 | ||
1423 | atype.defined |= NTA_HASINDEX; | |
1424 | ||
1425 | if (skip_past_char (&str, ']') == SUCCESS) | |
1426 | atype.index = NEON_ALL_LANES; | |
1427 | else | |
1428 | { | |
1429 | expressionS exp; | |
1430 | ||
1431 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1432 | ||
1433 | if (exp.X_op != O_constant) | |
1434 | { | |
1435 | first_error (_("constant expression required")); | |
1436 | return FAIL; | |
1437 | } | |
1438 | ||
1439 | if (skip_past_char (&str, ']') == FAIL) | |
1440 | return FAIL; | |
1441 | ||
1442 | atype.index = exp.X_add_number; | |
1443 | } | |
1444 | } | |
5f4273c7 | 1445 | |
dcbf9037 JB |
1446 | if (typeinfo) |
1447 | *typeinfo = atype; | |
5f4273c7 | 1448 | |
dcbf9037 JB |
1449 | if (rtype) |
1450 | *rtype = type; | |
5f4273c7 | 1451 | |
dcbf9037 | 1452 | *ccp = str; |
5f4273c7 | 1453 | |
dcbf9037 JB |
1454 | return reg->number; |
1455 | } | |
1456 | ||
1457 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1458 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1459 | register (e.g. Neon double or quad reg when either has been requested). | |
1460 | - If this is a Neon vector type with additional type information, fill | |
1461 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1462 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1463 | |
1464 | static int | |
1465 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1466 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1467 | { | |
1468 | struct neon_typed_alias atype; | |
1469 | char *str = *ccp; | |
1470 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1471 | ||
1472 | if (reg == FAIL) | |
1473 | return FAIL; | |
1474 | ||
0855e32b NS |
1475 | /* Do not allow regname(... to parse as a register. */ |
1476 | if (*str == '(') | |
1477 | return FAIL; | |
1478 | ||
dcbf9037 JB |
1479 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1480 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1481 | { | |
1482 | first_error (_("register operand expected, but got scalar")); | |
1483 | return FAIL; | |
1484 | } | |
1485 | ||
1486 | if (vectype) | |
1487 | *vectype = atype.eltype; | |
1488 | ||
1489 | *ccp = str; | |
1490 | ||
1491 | return reg; | |
1492 | } | |
1493 | ||
1494 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1495 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1496 | ||
5287ad62 JB |
1497 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1498 | have enough information to be able to do a good job bounds-checking. So, we | |
1499 | just do easy checks here, and do further checks later. */ | |
1500 | ||
1501 | static int | |
dcbf9037 | 1502 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1503 | { |
dcbf9037 | 1504 | int reg; |
5287ad62 | 1505 | char *str = *ccp; |
dcbf9037 | 1506 | struct neon_typed_alias atype; |
5f4273c7 | 1507 | |
dcbf9037 | 1508 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1509 | |
dcbf9037 | 1510 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1511 | return FAIL; |
5f4273c7 | 1512 | |
dcbf9037 | 1513 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1514 | { |
dcbf9037 | 1515 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1516 | return FAIL; |
1517 | } | |
dcbf9037 | 1518 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1519 | { |
dcbf9037 | 1520 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1521 | return FAIL; |
1522 | } | |
5f4273c7 | 1523 | |
dcbf9037 JB |
1524 | if (type) |
1525 | *type = atype.eltype; | |
5f4273c7 | 1526 | |
5287ad62 | 1527 | *ccp = str; |
5f4273c7 | 1528 | |
dcbf9037 | 1529 | return reg * 16 + atype.index; |
5287ad62 JB |
1530 | } |
1531 | ||
c19d1205 | 1532 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1533 | |
c19d1205 ZW |
1534 | static long |
1535 | parse_reg_list (char ** strp) | |
1536 | { | |
1537 | char * str = * strp; | |
1538 | long range = 0; | |
1539 | int another_range; | |
a737bd4d | 1540 | |
c19d1205 ZW |
1541 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1542 | do | |
6057a28f | 1543 | { |
c19d1205 | 1544 | another_range = 0; |
a737bd4d | 1545 | |
c19d1205 ZW |
1546 | if (*str == '{') |
1547 | { | |
1548 | int in_range = 0; | |
1549 | int cur_reg = -1; | |
a737bd4d | 1550 | |
c19d1205 ZW |
1551 | str++; |
1552 | do | |
1553 | { | |
1554 | int reg; | |
6057a28f | 1555 | |
dcbf9037 | 1556 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1557 | { |
dcbf9037 | 1558 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1559 | return FAIL; |
1560 | } | |
a737bd4d | 1561 | |
c19d1205 ZW |
1562 | if (in_range) |
1563 | { | |
1564 | int i; | |
a737bd4d | 1565 | |
c19d1205 ZW |
1566 | if (reg <= cur_reg) |
1567 | { | |
dcbf9037 | 1568 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1569 | return FAIL; |
1570 | } | |
40a18ebd | 1571 | |
c19d1205 ZW |
1572 | for (i = cur_reg + 1; i < reg; i++) |
1573 | { | |
1574 | if (range & (1 << i)) | |
1575 | as_tsktsk | |
1576 | (_("Warning: duplicated register (r%d) in register list"), | |
1577 | i); | |
1578 | else | |
1579 | range |= 1 << i; | |
1580 | } | |
1581 | in_range = 0; | |
1582 | } | |
a737bd4d | 1583 | |
c19d1205 ZW |
1584 | if (range & (1 << reg)) |
1585 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1586 | reg); | |
1587 | else if (reg <= cur_reg) | |
1588 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1589 | |
c19d1205 ZW |
1590 | range |= 1 << reg; |
1591 | cur_reg = reg; | |
1592 | } | |
1593 | while (skip_past_comma (&str) != FAIL | |
1594 | || (in_range = 1, *str++ == '-')); | |
1595 | str--; | |
a737bd4d | 1596 | |
c19d1205 ZW |
1597 | if (*str++ != '}') |
1598 | { | |
dcbf9037 | 1599 | first_error (_("missing `}'")); |
c19d1205 ZW |
1600 | return FAIL; |
1601 | } | |
1602 | } | |
1603 | else | |
1604 | { | |
91d6fa6a | 1605 | expressionS exp; |
40a18ebd | 1606 | |
91d6fa6a | 1607 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1608 | return FAIL; |
40a18ebd | 1609 | |
91d6fa6a | 1610 | if (exp.X_op == O_constant) |
c19d1205 | 1611 | { |
91d6fa6a NC |
1612 | if (exp.X_add_number |
1613 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1614 | { |
1615 | inst.error = _("invalid register mask"); | |
1616 | return FAIL; | |
1617 | } | |
a737bd4d | 1618 | |
91d6fa6a | 1619 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1620 | { |
91d6fa6a | 1621 | int regno = range & exp.X_add_number; |
a737bd4d | 1622 | |
c19d1205 ZW |
1623 | regno &= -regno; |
1624 | regno = (1 << regno) - 1; | |
1625 | as_tsktsk | |
1626 | (_("Warning: duplicated register (r%d) in register list"), | |
1627 | regno); | |
1628 | } | |
a737bd4d | 1629 | |
91d6fa6a | 1630 | range |= exp.X_add_number; |
c19d1205 ZW |
1631 | } |
1632 | else | |
1633 | { | |
1634 | if (inst.reloc.type != 0) | |
1635 | { | |
1636 | inst.error = _("expression too complex"); | |
1637 | return FAIL; | |
1638 | } | |
a737bd4d | 1639 | |
91d6fa6a | 1640 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1641 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1642 | inst.reloc.pc_rel = 0; | |
1643 | } | |
1644 | } | |
a737bd4d | 1645 | |
c19d1205 ZW |
1646 | if (*str == '|' || *str == '+') |
1647 | { | |
1648 | str++; | |
1649 | another_range = 1; | |
1650 | } | |
a737bd4d | 1651 | } |
c19d1205 | 1652 | while (another_range); |
a737bd4d | 1653 | |
c19d1205 ZW |
1654 | *strp = str; |
1655 | return range; | |
a737bd4d NC |
1656 | } |
1657 | ||
5287ad62 JB |
1658 | /* Types of registers in a list. */ |
1659 | ||
1660 | enum reg_list_els | |
1661 | { | |
1662 | REGLIST_VFP_S, | |
1663 | REGLIST_VFP_D, | |
1664 | REGLIST_NEON_D | |
1665 | }; | |
1666 | ||
c19d1205 ZW |
1667 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1668 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1669 | register. Parses registers of type ETYPE. |
1670 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1671 | - Q registers can be used to specify pairs of D registers | |
1672 | - { } can be omitted from around a singleton register list | |
1673 | FIXME: This is not implemented, as it would require backtracking in | |
1674 | some cases, e.g.: | |
1675 | vtbl.8 d3,d4,d5 | |
1676 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1677 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1678 | - 32 D registers may be used (also true for VFPv3). |
1679 | FIXME: Types are ignored in these register lists, which is probably a | |
1680 | bug. */ | |
6057a28f | 1681 | |
c19d1205 | 1682 | static int |
037e8744 | 1683 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1684 | { |
037e8744 | 1685 | char *str = *ccp; |
c19d1205 ZW |
1686 | int base_reg; |
1687 | int new_base; | |
21d799b5 | 1688 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1689 | int max_regs = 0; |
c19d1205 ZW |
1690 | int count = 0; |
1691 | int warned = 0; | |
1692 | unsigned long mask = 0; | |
a737bd4d | 1693 | int i; |
6057a28f | 1694 | |
037e8744 | 1695 | if (*str != '{') |
5287ad62 JB |
1696 | { |
1697 | inst.error = _("expecting {"); | |
1698 | return FAIL; | |
1699 | } | |
6057a28f | 1700 | |
037e8744 | 1701 | str++; |
6057a28f | 1702 | |
5287ad62 | 1703 | switch (etype) |
c19d1205 | 1704 | { |
5287ad62 | 1705 | case REGLIST_VFP_S: |
c19d1205 ZW |
1706 | regtype = REG_TYPE_VFS; |
1707 | max_regs = 32; | |
5287ad62 | 1708 | break; |
5f4273c7 | 1709 | |
5287ad62 JB |
1710 | case REGLIST_VFP_D: |
1711 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1712 | break; |
5f4273c7 | 1713 | |
b7fc2769 JB |
1714 | case REGLIST_NEON_D: |
1715 | regtype = REG_TYPE_NDQ; | |
1716 | break; | |
1717 | } | |
1718 | ||
1719 | if (etype != REGLIST_VFP_S) | |
1720 | { | |
b1cc4aeb PB |
1721 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1722 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1723 | { |
1724 | max_regs = 32; | |
1725 | if (thumb_mode) | |
1726 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1727 | fpu_vfp_ext_d32); |
5287ad62 JB |
1728 | else |
1729 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1730 | fpu_vfp_ext_d32); |
5287ad62 JB |
1731 | } |
1732 | else | |
1733 | max_regs = 16; | |
c19d1205 | 1734 | } |
6057a28f | 1735 | |
c19d1205 | 1736 | base_reg = max_regs; |
a737bd4d | 1737 | |
c19d1205 ZW |
1738 | do |
1739 | { | |
5287ad62 | 1740 | int setmask = 1, addregs = 1; |
dcbf9037 | 1741 | |
037e8744 | 1742 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1743 | |
c19d1205 | 1744 | if (new_base == FAIL) |
a737bd4d | 1745 | { |
dcbf9037 | 1746 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1747 | return FAIL; |
1748 | } | |
5f4273c7 | 1749 | |
b7fc2769 JB |
1750 | if (new_base >= max_regs) |
1751 | { | |
1752 | first_error (_("register out of range in list")); | |
1753 | return FAIL; | |
1754 | } | |
5f4273c7 | 1755 | |
5287ad62 JB |
1756 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1757 | if (regtype == REG_TYPE_NQ) | |
1758 | { | |
1759 | setmask = 3; | |
1760 | addregs = 2; | |
1761 | } | |
1762 | ||
c19d1205 ZW |
1763 | if (new_base < base_reg) |
1764 | base_reg = new_base; | |
a737bd4d | 1765 | |
5287ad62 | 1766 | if (mask & (setmask << new_base)) |
c19d1205 | 1767 | { |
dcbf9037 | 1768 | first_error (_("invalid register list")); |
c19d1205 | 1769 | return FAIL; |
a737bd4d | 1770 | } |
a737bd4d | 1771 | |
c19d1205 ZW |
1772 | if ((mask >> new_base) != 0 && ! warned) |
1773 | { | |
1774 | as_tsktsk (_("register list not in ascending order")); | |
1775 | warned = 1; | |
1776 | } | |
0bbf2aa4 | 1777 | |
5287ad62 JB |
1778 | mask |= setmask << new_base; |
1779 | count += addregs; | |
0bbf2aa4 | 1780 | |
037e8744 | 1781 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1782 | { |
1783 | int high_range; | |
0bbf2aa4 | 1784 | |
037e8744 | 1785 | str++; |
0bbf2aa4 | 1786 | |
037e8744 | 1787 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1788 | == FAIL) |
c19d1205 ZW |
1789 | { |
1790 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1791 | return FAIL; | |
1792 | } | |
0bbf2aa4 | 1793 | |
b7fc2769 JB |
1794 | if (high_range >= max_regs) |
1795 | { | |
1796 | first_error (_("register out of range in list")); | |
1797 | return FAIL; | |
1798 | } | |
1799 | ||
5287ad62 JB |
1800 | if (regtype == REG_TYPE_NQ) |
1801 | high_range = high_range + 1; | |
1802 | ||
c19d1205 ZW |
1803 | if (high_range <= new_base) |
1804 | { | |
1805 | inst.error = _("register range not in ascending order"); | |
1806 | return FAIL; | |
1807 | } | |
0bbf2aa4 | 1808 | |
5287ad62 | 1809 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1810 | { |
5287ad62 | 1811 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1812 | { |
c19d1205 ZW |
1813 | inst.error = _("invalid register list"); |
1814 | return FAIL; | |
0bbf2aa4 | 1815 | } |
c19d1205 | 1816 | |
5287ad62 JB |
1817 | mask |= setmask << new_base; |
1818 | count += addregs; | |
0bbf2aa4 | 1819 | } |
0bbf2aa4 | 1820 | } |
0bbf2aa4 | 1821 | } |
037e8744 | 1822 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1823 | |
037e8744 | 1824 | str++; |
0bbf2aa4 | 1825 | |
c19d1205 ZW |
1826 | /* Sanity check -- should have raised a parse error above. */ |
1827 | if (count == 0 || count > max_regs) | |
1828 | abort (); | |
1829 | ||
1830 | *pbase = base_reg; | |
1831 | ||
1832 | /* Final test -- the registers must be consecutive. */ | |
1833 | mask >>= base_reg; | |
1834 | for (i = 0; i < count; i++) | |
1835 | { | |
1836 | if ((mask & (1u << i)) == 0) | |
1837 | { | |
1838 | inst.error = _("non-contiguous register range"); | |
1839 | return FAIL; | |
1840 | } | |
1841 | } | |
1842 | ||
037e8744 JB |
1843 | *ccp = str; |
1844 | ||
c19d1205 | 1845 | return count; |
b99bd4ef NC |
1846 | } |
1847 | ||
dcbf9037 JB |
1848 | /* True if two alias types are the same. */ |
1849 | ||
c921be7d | 1850 | static bfd_boolean |
dcbf9037 JB |
1851 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1852 | { | |
1853 | if (!a && !b) | |
c921be7d | 1854 | return TRUE; |
5f4273c7 | 1855 | |
dcbf9037 | 1856 | if (!a || !b) |
c921be7d | 1857 | return FALSE; |
dcbf9037 JB |
1858 | |
1859 | if (a->defined != b->defined) | |
c921be7d | 1860 | return FALSE; |
5f4273c7 | 1861 | |
dcbf9037 JB |
1862 | if ((a->defined & NTA_HASTYPE) != 0 |
1863 | && (a->eltype.type != b->eltype.type | |
1864 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1865 | return FALSE; |
dcbf9037 JB |
1866 | |
1867 | if ((a->defined & NTA_HASINDEX) != 0 | |
1868 | && (a->index != b->index)) | |
c921be7d | 1869 | return FALSE; |
5f4273c7 | 1870 | |
c921be7d | 1871 | return TRUE; |
dcbf9037 JB |
1872 | } |
1873 | ||
5287ad62 JB |
1874 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1875 | The base register is put in *PBASE. | |
dcbf9037 | 1876 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1877 | the return value. |
1878 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1879 | Bits [6:5] encode the list length (minus one). |
1880 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1881 | |
5287ad62 | 1882 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1883 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1884 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1885 | ||
1886 | static int | |
dcbf9037 JB |
1887 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1888 | struct neon_type_el *eltype) | |
5287ad62 JB |
1889 | { |
1890 | char *ptr = *str; | |
1891 | int base_reg = -1; | |
1892 | int reg_incr = -1; | |
1893 | int count = 0; | |
1894 | int lane = -1; | |
1895 | int leading_brace = 0; | |
1896 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1897 | const char *const incr_error = _("register stride must be 1 or 2"); |
1898 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1899 | struct neon_typed_alias firsttype; |
5f4273c7 | 1900 | |
5287ad62 JB |
1901 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1902 | leading_brace = 1; | |
5f4273c7 | 1903 | |
5287ad62 JB |
1904 | do |
1905 | { | |
dcbf9037 JB |
1906 | struct neon_typed_alias atype; |
1907 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1908 | ||
5287ad62 JB |
1909 | if (getreg == FAIL) |
1910 | { | |
dcbf9037 | 1911 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1912 | return FAIL; |
1913 | } | |
5f4273c7 | 1914 | |
5287ad62 JB |
1915 | if (base_reg == -1) |
1916 | { | |
1917 | base_reg = getreg; | |
1918 | if (rtype == REG_TYPE_NQ) | |
1919 | { | |
1920 | reg_incr = 1; | |
5287ad62 | 1921 | } |
dcbf9037 | 1922 | firsttype = atype; |
5287ad62 JB |
1923 | } |
1924 | else if (reg_incr == -1) | |
1925 | { | |
1926 | reg_incr = getreg - base_reg; | |
1927 | if (reg_incr < 1 || reg_incr > 2) | |
1928 | { | |
dcbf9037 | 1929 | first_error (_(incr_error)); |
5287ad62 JB |
1930 | return FAIL; |
1931 | } | |
1932 | } | |
1933 | else if (getreg != base_reg + reg_incr * count) | |
1934 | { | |
dcbf9037 JB |
1935 | first_error (_(incr_error)); |
1936 | return FAIL; | |
1937 | } | |
1938 | ||
c921be7d | 1939 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1940 | { |
1941 | first_error (_(type_error)); | |
5287ad62 JB |
1942 | return FAIL; |
1943 | } | |
5f4273c7 | 1944 | |
5287ad62 JB |
1945 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1946 | modes. */ | |
1947 | if (ptr[0] == '-') | |
1948 | { | |
dcbf9037 | 1949 | struct neon_typed_alias htype; |
5287ad62 JB |
1950 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1951 | if (lane == -1) | |
1952 | lane = NEON_INTERLEAVE_LANES; | |
1953 | else if (lane != NEON_INTERLEAVE_LANES) | |
1954 | { | |
dcbf9037 | 1955 | first_error (_(type_error)); |
5287ad62 JB |
1956 | return FAIL; |
1957 | } | |
1958 | if (reg_incr == -1) | |
1959 | reg_incr = 1; | |
1960 | else if (reg_incr != 1) | |
1961 | { | |
dcbf9037 | 1962 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1963 | return FAIL; |
1964 | } | |
1965 | ptr++; | |
dcbf9037 | 1966 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1967 | if (hireg == FAIL) |
1968 | { | |
dcbf9037 JB |
1969 | first_error (_(reg_expected_msgs[rtype])); |
1970 | return FAIL; | |
1971 | } | |
c921be7d | 1972 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
1973 | { |
1974 | first_error (_(type_error)); | |
5287ad62 JB |
1975 | return FAIL; |
1976 | } | |
1977 | count += hireg + dregs - getreg; | |
1978 | continue; | |
1979 | } | |
5f4273c7 | 1980 | |
5287ad62 JB |
1981 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1982 | if (rtype == REG_TYPE_NQ) | |
1983 | { | |
1984 | count += 2; | |
1985 | continue; | |
1986 | } | |
5f4273c7 | 1987 | |
dcbf9037 | 1988 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1989 | { |
dcbf9037 JB |
1990 | if (lane == -1) |
1991 | lane = atype.index; | |
1992 | else if (lane != atype.index) | |
5287ad62 | 1993 | { |
dcbf9037 JB |
1994 | first_error (_(type_error)); |
1995 | return FAIL; | |
5287ad62 JB |
1996 | } |
1997 | } | |
1998 | else if (lane == -1) | |
1999 | lane = NEON_INTERLEAVE_LANES; | |
2000 | else if (lane != NEON_INTERLEAVE_LANES) | |
2001 | { | |
dcbf9037 | 2002 | first_error (_(type_error)); |
5287ad62 JB |
2003 | return FAIL; |
2004 | } | |
2005 | count++; | |
2006 | } | |
2007 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2008 | |
5287ad62 JB |
2009 | /* No lane set by [x]. We must be interleaving structures. */ |
2010 | if (lane == -1) | |
2011 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2012 | |
5287ad62 JB |
2013 | /* Sanity check. */ |
2014 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2015 | || (count > 1 && reg_incr == -1)) | |
2016 | { | |
dcbf9037 | 2017 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2018 | return FAIL; |
2019 | } | |
2020 | ||
2021 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2022 | { | |
dcbf9037 | 2023 | first_error (_("expected }")); |
5287ad62 JB |
2024 | return FAIL; |
2025 | } | |
5f4273c7 | 2026 | |
5287ad62 JB |
2027 | if (reg_incr == -1) |
2028 | reg_incr = 1; | |
2029 | ||
dcbf9037 JB |
2030 | if (eltype) |
2031 | *eltype = firsttype.eltype; | |
2032 | ||
5287ad62 JB |
2033 | *pbase = base_reg; |
2034 | *str = ptr; | |
5f4273c7 | 2035 | |
5287ad62 JB |
2036 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2037 | } | |
2038 | ||
c19d1205 ZW |
2039 | /* Parse an explicit relocation suffix on an expression. This is |
2040 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2041 | arm_reloc_hsh contains no entries, so this function can only | |
2042 | succeed if there is no () after the word. Returns -1 on error, | |
2043 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
2044 | static int | |
2045 | parse_reloc (char **str) | |
b99bd4ef | 2046 | { |
c19d1205 ZW |
2047 | struct reloc_entry *r; |
2048 | char *p, *q; | |
b99bd4ef | 2049 | |
c19d1205 ZW |
2050 | if (**str != '(') |
2051 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2052 | |
c19d1205 ZW |
2053 | p = *str + 1; |
2054 | q = p; | |
2055 | ||
2056 | while (*q && *q != ')' && *q != ',') | |
2057 | q++; | |
2058 | if (*q != ')') | |
2059 | return -1; | |
2060 | ||
21d799b5 NC |
2061 | if ((r = (struct reloc_entry *) |
2062 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2063 | return -1; |
2064 | ||
2065 | *str = q + 1; | |
2066 | return r->reloc; | |
b99bd4ef NC |
2067 | } |
2068 | ||
c19d1205 ZW |
2069 | /* Directives: register aliases. */ |
2070 | ||
dcbf9037 | 2071 | static struct reg_entry * |
90ec0d68 | 2072 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2073 | { |
d3ce72d0 | 2074 | struct reg_entry *new_reg; |
c19d1205 | 2075 | const char *name; |
b99bd4ef | 2076 | |
d3ce72d0 | 2077 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2078 | { |
d3ce72d0 | 2079 | if (new_reg->builtin) |
c19d1205 | 2080 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2081 | |
c19d1205 ZW |
2082 | /* Only warn about a redefinition if it's not defined as the |
2083 | same register. */ | |
d3ce72d0 | 2084 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2085 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2086 | |
d929913e | 2087 | return NULL; |
c19d1205 | 2088 | } |
b99bd4ef | 2089 | |
c19d1205 | 2090 | name = xstrdup (str); |
d3ce72d0 | 2091 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2092 | |
d3ce72d0 NC |
2093 | new_reg->name = name; |
2094 | new_reg->number = number; | |
2095 | new_reg->type = type; | |
2096 | new_reg->builtin = FALSE; | |
2097 | new_reg->neon = NULL; | |
b99bd4ef | 2098 | |
d3ce72d0 | 2099 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2100 | abort (); |
5f4273c7 | 2101 | |
d3ce72d0 | 2102 | return new_reg; |
dcbf9037 JB |
2103 | } |
2104 | ||
2105 | static void | |
2106 | insert_neon_reg_alias (char *str, int number, int type, | |
2107 | struct neon_typed_alias *atype) | |
2108 | { | |
2109 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2110 | |
dcbf9037 JB |
2111 | if (!reg) |
2112 | { | |
2113 | first_error (_("attempt to redefine typed alias")); | |
2114 | return; | |
2115 | } | |
5f4273c7 | 2116 | |
dcbf9037 JB |
2117 | if (atype) |
2118 | { | |
21d799b5 NC |
2119 | reg->neon = (struct neon_typed_alias *) |
2120 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2121 | *reg->neon = *atype; |
2122 | } | |
c19d1205 | 2123 | } |
b99bd4ef | 2124 | |
c19d1205 | 2125 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2126 | |
c19d1205 | 2127 | new_register_name .req existing_register_name |
b99bd4ef | 2128 | |
c19d1205 | 2129 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2130 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2131 | |
d929913e | 2132 | static bfd_boolean |
c19d1205 ZW |
2133 | create_register_alias (char * newname, char *p) |
2134 | { | |
2135 | struct reg_entry *old; | |
2136 | char *oldname, *nbuf; | |
2137 | size_t nlen; | |
b99bd4ef | 2138 | |
c19d1205 ZW |
2139 | /* The input scrubber ensures that whitespace after the mnemonic is |
2140 | collapsed to single spaces. */ | |
2141 | oldname = p; | |
2142 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2143 | return FALSE; |
b99bd4ef | 2144 | |
c19d1205 ZW |
2145 | oldname += 6; |
2146 | if (*oldname == '\0') | |
d929913e | 2147 | return FALSE; |
b99bd4ef | 2148 | |
21d799b5 | 2149 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2150 | if (!old) |
b99bd4ef | 2151 | { |
c19d1205 | 2152 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2153 | return TRUE; |
b99bd4ef NC |
2154 | } |
2155 | ||
c19d1205 ZW |
2156 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2157 | the desired alias name, and p points to its end. If not, then | |
2158 | the desired alias name is in the global original_case_string. */ | |
2159 | #ifdef TC_CASE_SENSITIVE | |
2160 | nlen = p - newname; | |
2161 | #else | |
2162 | newname = original_case_string; | |
2163 | nlen = strlen (newname); | |
2164 | #endif | |
b99bd4ef | 2165 | |
21d799b5 | 2166 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2167 | memcpy (nbuf, newname, nlen); |
2168 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2169 | |
c19d1205 ZW |
2170 | /* Create aliases under the new name as stated; an all-lowercase |
2171 | version of the new name; and an all-uppercase version of the new | |
2172 | name. */ | |
d929913e NC |
2173 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2174 | { | |
2175 | for (p = nbuf; *p; p++) | |
2176 | *p = TOUPPER (*p); | |
c19d1205 | 2177 | |
d929913e NC |
2178 | if (strncmp (nbuf, newname, nlen)) |
2179 | { | |
2180 | /* If this attempt to create an additional alias fails, do not bother | |
2181 | trying to create the all-lower case alias. We will fail and issue | |
2182 | a second, duplicate error message. This situation arises when the | |
2183 | programmer does something like: | |
2184 | foo .req r0 | |
2185 | Foo .req r1 | |
2186 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2187 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2188 | first .req. */ |
2189 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2190 | return TRUE; | |
2191 | } | |
c19d1205 | 2192 | |
d929913e NC |
2193 | for (p = nbuf; *p; p++) |
2194 | *p = TOLOWER (*p); | |
c19d1205 | 2195 | |
d929913e NC |
2196 | if (strncmp (nbuf, newname, nlen)) |
2197 | insert_reg_alias (nbuf, old->number, old->type); | |
2198 | } | |
c19d1205 | 2199 | |
d929913e | 2200 | return TRUE; |
b99bd4ef NC |
2201 | } |
2202 | ||
dcbf9037 JB |
2203 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2204 | X .dn d5.s32[1] | |
2205 | Y .qn 6.s16 | |
2206 | Z .dn d7 | |
2207 | T .dn Z[0] | |
2208 | These typed registers can be used instead of the types specified after the | |
2209 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2210 | specified directly, e.g.: | |
5f4273c7 | 2211 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2212 | |
c921be7d | 2213 | static bfd_boolean |
dcbf9037 JB |
2214 | create_neon_reg_alias (char *newname, char *p) |
2215 | { | |
2216 | enum arm_reg_type basetype; | |
2217 | struct reg_entry *basereg; | |
2218 | struct reg_entry mybasereg; | |
2219 | struct neon_type ntype; | |
2220 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2221 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2222 | int namelen; |
5f4273c7 | 2223 | |
dcbf9037 JB |
2224 | typeinfo.defined = 0; |
2225 | typeinfo.eltype.type = NT_invtype; | |
2226 | typeinfo.eltype.size = -1; | |
2227 | typeinfo.index = -1; | |
5f4273c7 | 2228 | |
dcbf9037 | 2229 | nameend = p; |
5f4273c7 | 2230 | |
dcbf9037 JB |
2231 | if (strncmp (p, " .dn ", 5) == 0) |
2232 | basetype = REG_TYPE_VFD; | |
2233 | else if (strncmp (p, " .qn ", 5) == 0) | |
2234 | basetype = REG_TYPE_NQ; | |
2235 | else | |
c921be7d | 2236 | return FALSE; |
5f4273c7 | 2237 | |
dcbf9037 | 2238 | p += 5; |
5f4273c7 | 2239 | |
dcbf9037 | 2240 | if (*p == '\0') |
c921be7d | 2241 | return FALSE; |
5f4273c7 | 2242 | |
dcbf9037 JB |
2243 | basereg = arm_reg_parse_multi (&p); |
2244 | ||
2245 | if (basereg && basereg->type != basetype) | |
2246 | { | |
2247 | as_bad (_("bad type for register")); | |
c921be7d | 2248 | return FALSE; |
dcbf9037 JB |
2249 | } |
2250 | ||
2251 | if (basereg == NULL) | |
2252 | { | |
2253 | expressionS exp; | |
2254 | /* Try parsing as an integer. */ | |
2255 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2256 | if (exp.X_op != O_constant) | |
2257 | { | |
2258 | as_bad (_("expression must be constant")); | |
c921be7d | 2259 | return FALSE; |
dcbf9037 JB |
2260 | } |
2261 | basereg = &mybasereg; | |
2262 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2263 | : exp.X_add_number; | |
2264 | basereg->neon = 0; | |
2265 | } | |
2266 | ||
2267 | if (basereg->neon) | |
2268 | typeinfo = *basereg->neon; | |
2269 | ||
2270 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2271 | { | |
2272 | /* We got a type. */ | |
2273 | if (typeinfo.defined & NTA_HASTYPE) | |
2274 | { | |
2275 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2276 | return FALSE; |
dcbf9037 | 2277 | } |
5f4273c7 | 2278 | |
dcbf9037 JB |
2279 | typeinfo.defined |= NTA_HASTYPE; |
2280 | if (ntype.elems != 1) | |
2281 | { | |
2282 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2283 | return FALSE; |
dcbf9037 JB |
2284 | } |
2285 | typeinfo.eltype = ntype.el[0]; | |
2286 | } | |
5f4273c7 | 2287 | |
dcbf9037 JB |
2288 | if (skip_past_char (&p, '[') == SUCCESS) |
2289 | { | |
2290 | expressionS exp; | |
2291 | /* We got a scalar index. */ | |
5f4273c7 | 2292 | |
dcbf9037 JB |
2293 | if (typeinfo.defined & NTA_HASINDEX) |
2294 | { | |
2295 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2296 | return FALSE; |
dcbf9037 | 2297 | } |
5f4273c7 | 2298 | |
dcbf9037 | 2299 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2300 | |
dcbf9037 JB |
2301 | if (exp.X_op != O_constant) |
2302 | { | |
2303 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2304 | return FALSE; |
dcbf9037 | 2305 | } |
5f4273c7 | 2306 | |
dcbf9037 JB |
2307 | typeinfo.defined |= NTA_HASINDEX; |
2308 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2309 | |
dcbf9037 JB |
2310 | if (skip_past_char (&p, ']') == FAIL) |
2311 | { | |
2312 | as_bad (_("expecting ]")); | |
c921be7d | 2313 | return FALSE; |
dcbf9037 JB |
2314 | } |
2315 | } | |
2316 | ||
15735687 NS |
2317 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2318 | the desired alias name, and p points to its end. If not, then | |
2319 | the desired alias name is in the global original_case_string. */ | |
2320 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2321 | namelen = nameend - newname; |
15735687 NS |
2322 | #else |
2323 | newname = original_case_string; | |
2324 | namelen = strlen (newname); | |
2325 | #endif | |
2326 | ||
21d799b5 | 2327 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2328 | strncpy (namebuf, newname, namelen); |
2329 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2330 | |
dcbf9037 JB |
2331 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2332 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2333 | |
dcbf9037 JB |
2334 | /* Insert name in all uppercase. */ |
2335 | for (p = namebuf; *p; p++) | |
2336 | *p = TOUPPER (*p); | |
5f4273c7 | 2337 | |
dcbf9037 JB |
2338 | if (strncmp (namebuf, newname, namelen)) |
2339 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2340 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2341 | |
dcbf9037 JB |
2342 | /* Insert name in all lowercase. */ |
2343 | for (p = namebuf; *p; p++) | |
2344 | *p = TOLOWER (*p); | |
5f4273c7 | 2345 | |
dcbf9037 JB |
2346 | if (strncmp (namebuf, newname, namelen)) |
2347 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2348 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2349 | |
c921be7d | 2350 | return TRUE; |
dcbf9037 JB |
2351 | } |
2352 | ||
c19d1205 ZW |
2353 | /* Should never be called, as .req goes between the alias and the |
2354 | register name, not at the beginning of the line. */ | |
c921be7d | 2355 | |
b99bd4ef | 2356 | static void |
c19d1205 | 2357 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2358 | { |
c19d1205 ZW |
2359 | as_bad (_("invalid syntax for .req directive")); |
2360 | } | |
b99bd4ef | 2361 | |
dcbf9037 JB |
2362 | static void |
2363 | s_dn (int a ATTRIBUTE_UNUSED) | |
2364 | { | |
2365 | as_bad (_("invalid syntax for .dn directive")); | |
2366 | } | |
2367 | ||
2368 | static void | |
2369 | s_qn (int a ATTRIBUTE_UNUSED) | |
2370 | { | |
2371 | as_bad (_("invalid syntax for .qn directive")); | |
2372 | } | |
2373 | ||
c19d1205 ZW |
2374 | /* The .unreq directive deletes an alias which was previously defined |
2375 | by .req. For example: | |
b99bd4ef | 2376 | |
c19d1205 ZW |
2377 | my_alias .req r11 |
2378 | .unreq my_alias */ | |
b99bd4ef NC |
2379 | |
2380 | static void | |
c19d1205 | 2381 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2382 | { |
c19d1205 ZW |
2383 | char * name; |
2384 | char saved_char; | |
b99bd4ef | 2385 | |
c19d1205 ZW |
2386 | name = input_line_pointer; |
2387 | ||
2388 | while (*input_line_pointer != 0 | |
2389 | && *input_line_pointer != ' ' | |
2390 | && *input_line_pointer != '\n') | |
2391 | ++input_line_pointer; | |
2392 | ||
2393 | saved_char = *input_line_pointer; | |
2394 | *input_line_pointer = 0; | |
2395 | ||
2396 | if (!*name) | |
2397 | as_bad (_("invalid syntax for .unreq directive")); | |
2398 | else | |
2399 | { | |
21d799b5 NC |
2400 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2401 | name); | |
c19d1205 ZW |
2402 | |
2403 | if (!reg) | |
2404 | as_bad (_("unknown register alias '%s'"), name); | |
2405 | else if (reg->builtin) | |
2406 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
2407 | name); | |
2408 | else | |
2409 | { | |
d929913e NC |
2410 | char * p; |
2411 | char * nbuf; | |
2412 | ||
db0bc284 | 2413 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2414 | free ((char *) reg->name); |
dcbf9037 JB |
2415 | if (reg->neon) |
2416 | free (reg->neon); | |
c19d1205 | 2417 | free (reg); |
d929913e NC |
2418 | |
2419 | /* Also locate the all upper case and all lower case versions. | |
2420 | Do not complain if we cannot find one or the other as it | |
2421 | was probably deleted above. */ | |
5f4273c7 | 2422 | |
d929913e NC |
2423 | nbuf = strdup (name); |
2424 | for (p = nbuf; *p; p++) | |
2425 | *p = TOUPPER (*p); | |
21d799b5 | 2426 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2427 | if (reg) |
2428 | { | |
db0bc284 | 2429 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2430 | free ((char *) reg->name); |
2431 | if (reg->neon) | |
2432 | free (reg->neon); | |
2433 | free (reg); | |
2434 | } | |
2435 | ||
2436 | for (p = nbuf; *p; p++) | |
2437 | *p = TOLOWER (*p); | |
21d799b5 | 2438 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2439 | if (reg) |
2440 | { | |
db0bc284 | 2441 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2442 | free ((char *) reg->name); |
2443 | if (reg->neon) | |
2444 | free (reg->neon); | |
2445 | free (reg); | |
2446 | } | |
2447 | ||
2448 | free (nbuf); | |
c19d1205 ZW |
2449 | } |
2450 | } | |
b99bd4ef | 2451 | |
c19d1205 | 2452 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2453 | demand_empty_rest_of_line (); |
2454 | } | |
2455 | ||
c19d1205 ZW |
2456 | /* Directives: Instruction set selection. */ |
2457 | ||
2458 | #ifdef OBJ_ELF | |
2459 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2460 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2461 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2462 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2463 | ||
cd000bff DJ |
2464 | /* Create a new mapping symbol for the transition to STATE. */ |
2465 | ||
2466 | static void | |
2467 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2468 | { |
a737bd4d | 2469 | symbolS * symbolP; |
c19d1205 ZW |
2470 | const char * symname; |
2471 | int type; | |
b99bd4ef | 2472 | |
c19d1205 | 2473 | switch (state) |
b99bd4ef | 2474 | { |
c19d1205 ZW |
2475 | case MAP_DATA: |
2476 | symname = "$d"; | |
2477 | type = BSF_NO_FLAGS; | |
2478 | break; | |
2479 | case MAP_ARM: | |
2480 | symname = "$a"; | |
2481 | type = BSF_NO_FLAGS; | |
2482 | break; | |
2483 | case MAP_THUMB: | |
2484 | symname = "$t"; | |
2485 | type = BSF_NO_FLAGS; | |
2486 | break; | |
c19d1205 ZW |
2487 | default: |
2488 | abort (); | |
2489 | } | |
2490 | ||
cd000bff | 2491 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2492 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2493 | ||
2494 | switch (state) | |
2495 | { | |
2496 | case MAP_ARM: | |
2497 | THUMB_SET_FUNC (symbolP, 0); | |
2498 | ARM_SET_THUMB (symbolP, 0); | |
2499 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2500 | break; | |
2501 | ||
2502 | case MAP_THUMB: | |
2503 | THUMB_SET_FUNC (symbolP, 1); | |
2504 | ARM_SET_THUMB (symbolP, 1); | |
2505 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2506 | break; | |
2507 | ||
2508 | case MAP_DATA: | |
2509 | default: | |
cd000bff DJ |
2510 | break; |
2511 | } | |
2512 | ||
2513 | /* Save the mapping symbols for future reference. Also check that | |
2514 | we do not place two mapping symbols at the same offset within a | |
2515 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2516 | check_mapping_symbols. |
2517 | ||
2518 | If .fill or other data filling directive generates zero sized data, | |
2519 | the mapping symbol for the following code will have the same value | |
2520 | as the one generated for the data filling directive. In this case, | |
2521 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2522 | if (value == 0) |
2523 | { | |
2de7820f JZ |
2524 | if (frag->tc_frag_data.first_map != NULL) |
2525 | { | |
2526 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2527 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2528 | } | |
cd000bff DJ |
2529 | frag->tc_frag_data.first_map = symbolP; |
2530 | } | |
2531 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2532 | { |
2533 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2534 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2535 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2536 | } | |
cd000bff DJ |
2537 | frag->tc_frag_data.last_map = symbolP; |
2538 | } | |
2539 | ||
2540 | /* We must sometimes convert a region marked as code to data during | |
2541 | code alignment, if an odd number of bytes have to be padded. The | |
2542 | code mapping symbol is pushed to an aligned address. */ | |
2543 | ||
2544 | static void | |
2545 | insert_data_mapping_symbol (enum mstate state, | |
2546 | valueT value, fragS *frag, offsetT bytes) | |
2547 | { | |
2548 | /* If there was already a mapping symbol, remove it. */ | |
2549 | if (frag->tc_frag_data.last_map != NULL | |
2550 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2551 | { | |
2552 | symbolS *symp = frag->tc_frag_data.last_map; | |
2553 | ||
2554 | if (value == 0) | |
2555 | { | |
2556 | know (frag->tc_frag_data.first_map == symp); | |
2557 | frag->tc_frag_data.first_map = NULL; | |
2558 | } | |
2559 | frag->tc_frag_data.last_map = NULL; | |
2560 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2561 | } |
cd000bff DJ |
2562 | |
2563 | make_mapping_symbol (MAP_DATA, value, frag); | |
2564 | make_mapping_symbol (state, value + bytes, frag); | |
2565 | } | |
2566 | ||
2567 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2568 | ||
2569 | /* Set the mapping state to STATE. Only call this when about to | |
2570 | emit some STATE bytes to the file. */ | |
2571 | ||
2572 | void | |
2573 | mapping_state (enum mstate state) | |
2574 | { | |
940b5ce0 DJ |
2575 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2576 | ||
cd000bff DJ |
2577 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2578 | ||
2579 | if (mapstate == state) | |
2580 | /* The mapping symbol has already been emitted. | |
2581 | There is nothing else to do. */ | |
2582 | return; | |
2583 | else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
2584 | /* This case will be evaluated later in the next else. */ | |
2585 | return; | |
2586 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2587 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2588 | { | |
2589 | /* Only add the symbol if the offset is > 0: | |
2590 | if we're at the first frag, check it's size > 0; | |
2591 | if we're not at the first frag, then for sure | |
2592 | the offset is > 0. */ | |
2593 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2594 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2595 | ||
2596 | if (add_symbol) | |
2597 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2598 | } | |
2599 | ||
2600 | mapping_state_2 (state, 0); | |
2601 | #undef TRANSITION | |
2602 | } | |
2603 | ||
2604 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2605 | allocated. Put the mapping symbol that far back. */ | |
2606 | ||
2607 | static void | |
2608 | mapping_state_2 (enum mstate state, int max_chars) | |
2609 | { | |
940b5ce0 DJ |
2610 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2611 | ||
2612 | if (!SEG_NORMAL (now_seg)) | |
2613 | return; | |
2614 | ||
cd000bff DJ |
2615 | if (mapstate == state) |
2616 | /* The mapping symbol has already been emitted. | |
2617 | There is nothing else to do. */ | |
2618 | return; | |
2619 | ||
cd000bff DJ |
2620 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2621 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2622 | } |
2623 | #else | |
d3106081 NS |
2624 | #define mapping_state(x) ((void)0) |
2625 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2626 | #endif |
2627 | ||
2628 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2629 | ||
4343666d | 2630 | #ifdef OBJ_COFF |
c19d1205 ZW |
2631 | static symbolS * |
2632 | find_real_start (symbolS * symbolP) | |
2633 | { | |
2634 | char * real_start; | |
2635 | const char * name = S_GET_NAME (symbolP); | |
2636 | symbolS * new_target; | |
2637 | ||
2638 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2639 | #define STUB_NAME ".real_start_of" | |
2640 | ||
2641 | if (name == NULL) | |
2642 | abort (); | |
2643 | ||
37f6032b ZW |
2644 | /* The compiler may generate BL instructions to local labels because |
2645 | it needs to perform a branch to a far away location. These labels | |
2646 | do not have a corresponding ".real_start_of" label. We check | |
2647 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2648 | the ".real_start_of" convention for nonlocal branches. */ | |
2649 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2650 | return symbolP; |
2651 | ||
37f6032b | 2652 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2653 | new_target = symbol_find (real_start); |
2654 | ||
2655 | if (new_target == NULL) | |
2656 | { | |
bd3ba5d1 | 2657 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2658 | new_target = symbolP; |
2659 | } | |
2660 | ||
c19d1205 ZW |
2661 | return new_target; |
2662 | } | |
4343666d | 2663 | #endif |
c19d1205 ZW |
2664 | |
2665 | static void | |
2666 | opcode_select (int width) | |
2667 | { | |
2668 | switch (width) | |
2669 | { | |
2670 | case 16: | |
2671 | if (! thumb_mode) | |
2672 | { | |
e74cfd16 | 2673 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2674 | as_bad (_("selected processor does not support THUMB opcodes")); |
2675 | ||
2676 | thumb_mode = 1; | |
2677 | /* No need to force the alignment, since we will have been | |
2678 | coming from ARM mode, which is word-aligned. */ | |
2679 | record_alignment (now_seg, 1); | |
2680 | } | |
c19d1205 ZW |
2681 | break; |
2682 | ||
2683 | case 32: | |
2684 | if (thumb_mode) | |
2685 | { | |
e74cfd16 | 2686 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2687 | as_bad (_("selected processor does not support ARM opcodes")); |
2688 | ||
2689 | thumb_mode = 0; | |
2690 | ||
2691 | if (!need_pass_2) | |
2692 | frag_align (2, 0, 0); | |
2693 | ||
2694 | record_alignment (now_seg, 1); | |
2695 | } | |
c19d1205 ZW |
2696 | break; |
2697 | ||
2698 | default: | |
2699 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2700 | } | |
2701 | } | |
2702 | ||
2703 | static void | |
2704 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2705 | { | |
2706 | opcode_select (32); | |
2707 | demand_empty_rest_of_line (); | |
2708 | } | |
2709 | ||
2710 | static void | |
2711 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2712 | { | |
2713 | opcode_select (16); | |
2714 | demand_empty_rest_of_line (); | |
2715 | } | |
2716 | ||
2717 | static void | |
2718 | s_code (int unused ATTRIBUTE_UNUSED) | |
2719 | { | |
2720 | int temp; | |
2721 | ||
2722 | temp = get_absolute_expression (); | |
2723 | switch (temp) | |
2724 | { | |
2725 | case 16: | |
2726 | case 32: | |
2727 | opcode_select (temp); | |
2728 | break; | |
2729 | ||
2730 | default: | |
2731 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2732 | } | |
2733 | } | |
2734 | ||
2735 | static void | |
2736 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2737 | { | |
2738 | /* If we are not already in thumb mode go into it, EVEN if | |
2739 | the target processor does not support thumb instructions. | |
2740 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2741 | to compile interworking support functions even if the | |
2742 | target processor should not support interworking. */ | |
2743 | if (! thumb_mode) | |
2744 | { | |
2745 | thumb_mode = 2; | |
2746 | record_alignment (now_seg, 1); | |
2747 | } | |
2748 | ||
2749 | demand_empty_rest_of_line (); | |
2750 | } | |
2751 | ||
2752 | static void | |
2753 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2754 | { | |
2755 | s_thumb (0); | |
2756 | ||
2757 | /* The following label is the name/address of the start of a Thumb function. | |
2758 | We need to know this for the interworking support. */ | |
2759 | label_is_thumb_function_name = TRUE; | |
2760 | } | |
2761 | ||
2762 | /* Perform a .set directive, but also mark the alias as | |
2763 | being a thumb function. */ | |
2764 | ||
2765 | static void | |
2766 | s_thumb_set (int equiv) | |
2767 | { | |
2768 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2769 | We cannot just call that code as we need to get at the symbol that | |
2770 | is created. */ | |
2771 | char * name; | |
2772 | char delim; | |
2773 | char * end_name; | |
2774 | symbolS * symbolP; | |
2775 | ||
2776 | /* Especial apologies for the random logic: | |
2777 | This just grew, and could be parsed much more simply! | |
2778 | Dean - in haste. */ | |
2779 | name = input_line_pointer; | |
2780 | delim = get_symbol_end (); | |
2781 | end_name = input_line_pointer; | |
2782 | *end_name = delim; | |
2783 | ||
2784 | if (*input_line_pointer != ',') | |
2785 | { | |
2786 | *end_name = 0; | |
2787 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2788 | *end_name = delim; |
2789 | ignore_rest_of_line (); | |
2790 | return; | |
2791 | } | |
2792 | ||
2793 | input_line_pointer++; | |
2794 | *end_name = 0; | |
2795 | ||
2796 | if (name[0] == '.' && name[1] == '\0') | |
2797 | { | |
2798 | /* XXX - this should not happen to .thumb_set. */ | |
2799 | abort (); | |
2800 | } | |
2801 | ||
2802 | if ((symbolP = symbol_find (name)) == NULL | |
2803 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2804 | { | |
2805 | #ifndef NO_LISTING | |
2806 | /* When doing symbol listings, play games with dummy fragments living | |
2807 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2808 | for this symbol. */ |
b99bd4ef NC |
2809 | if (listing & LISTING_SYMBOLS) |
2810 | { | |
2811 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2812 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2813 | |
2814 | memset (dummy_frag, 0, sizeof (fragS)); | |
2815 | dummy_frag->fr_type = rs_fill; | |
2816 | dummy_frag->line = listing_tail; | |
2817 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2818 | dummy_frag->fr_symbol = symbolP; | |
2819 | } | |
2820 | else | |
2821 | #endif | |
2822 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2823 | ||
2824 | #ifdef OBJ_COFF | |
2825 | /* "set" symbols are local unless otherwise specified. */ | |
2826 | SF_SET_LOCAL (symbolP); | |
2827 | #endif /* OBJ_COFF */ | |
2828 | } /* Make a new symbol. */ | |
2829 | ||
2830 | symbol_table_insert (symbolP); | |
2831 | ||
2832 | * end_name = delim; | |
2833 | ||
2834 | if (equiv | |
2835 | && S_IS_DEFINED (symbolP) | |
2836 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2837 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2838 | ||
2839 | pseudo_set (symbolP); | |
2840 | ||
2841 | demand_empty_rest_of_line (); | |
2842 | ||
c19d1205 | 2843 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2844 | |
2845 | THUMB_SET_FUNC (symbolP, 1); | |
2846 | ARM_SET_THUMB (symbolP, 1); | |
2847 | #if defined OBJ_ELF || defined OBJ_COFF | |
2848 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2849 | #endif | |
2850 | } | |
2851 | ||
c19d1205 | 2852 | /* Directives: Mode selection. */ |
b99bd4ef | 2853 | |
c19d1205 ZW |
2854 | /* .syntax [unified|divided] - choose the new unified syntax |
2855 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2856 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2857 | static void |
c19d1205 | 2858 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2859 | { |
c19d1205 ZW |
2860 | char *name, delim; |
2861 | ||
2862 | name = input_line_pointer; | |
2863 | delim = get_symbol_end (); | |
2864 | ||
2865 | if (!strcasecmp (name, "unified")) | |
2866 | unified_syntax = TRUE; | |
2867 | else if (!strcasecmp (name, "divided")) | |
2868 | unified_syntax = FALSE; | |
2869 | else | |
2870 | { | |
2871 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2872 | return; | |
2873 | } | |
2874 | *input_line_pointer = delim; | |
b99bd4ef NC |
2875 | demand_empty_rest_of_line (); |
2876 | } | |
2877 | ||
c19d1205 ZW |
2878 | /* Directives: sectioning and alignment. */ |
2879 | ||
2880 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2881 | ||
b99bd4ef | 2882 | static void |
c19d1205 | 2883 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2884 | { |
a737bd4d | 2885 | int temp; |
dce323d1 | 2886 | bfd_boolean fill_p; |
c19d1205 ZW |
2887 | long temp_fill; |
2888 | long max_alignment = 15; | |
b99bd4ef NC |
2889 | |
2890 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2891 | if (temp > max_alignment) |
2892 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2893 | else if (temp < 0) | |
b99bd4ef | 2894 | { |
c19d1205 ZW |
2895 | as_bad (_("alignment negative. 0 assumed.")); |
2896 | temp = 0; | |
2897 | } | |
b99bd4ef | 2898 | |
c19d1205 ZW |
2899 | if (*input_line_pointer == ',') |
2900 | { | |
2901 | input_line_pointer++; | |
2902 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2903 | fill_p = TRUE; |
b99bd4ef | 2904 | } |
c19d1205 | 2905 | else |
dce323d1 PB |
2906 | { |
2907 | fill_p = FALSE; | |
2908 | temp_fill = 0; | |
2909 | } | |
b99bd4ef | 2910 | |
c19d1205 ZW |
2911 | if (!temp) |
2912 | temp = 2; | |
b99bd4ef | 2913 | |
c19d1205 ZW |
2914 | /* Only make a frag if we HAVE to. */ |
2915 | if (temp && !need_pass_2) | |
dce323d1 PB |
2916 | { |
2917 | if (!fill_p && subseg_text_p (now_seg)) | |
2918 | frag_align_code (temp, 0); | |
2919 | else | |
2920 | frag_align (temp, (int) temp_fill, 0); | |
2921 | } | |
c19d1205 ZW |
2922 | demand_empty_rest_of_line (); |
2923 | ||
2924 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2925 | } |
2926 | ||
c19d1205 ZW |
2927 | static void |
2928 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2929 | { |
c19d1205 ZW |
2930 | /* We don't support putting frags in the BSS segment, we fake it by |
2931 | marking in_bss, then looking at s_skip for clues. */ | |
2932 | subseg_set (bss_section, 0); | |
2933 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2934 | |
2935 | #ifdef md_elf_section_change_hook | |
2936 | md_elf_section_change_hook (); | |
2937 | #endif | |
c19d1205 | 2938 | } |
b99bd4ef | 2939 | |
c19d1205 ZW |
2940 | static void |
2941 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2942 | { | |
2943 | /* Never make frag if expect extra pass. */ | |
2944 | if (!need_pass_2) | |
2945 | frag_align (1, 0, 0); | |
b99bd4ef | 2946 | |
c19d1205 | 2947 | record_alignment (now_seg, 1); |
b99bd4ef | 2948 | |
c19d1205 | 2949 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2950 | } |
2951 | ||
c19d1205 | 2952 | /* Directives: Literal pools. */ |
a737bd4d | 2953 | |
c19d1205 ZW |
2954 | static literal_pool * |
2955 | find_literal_pool (void) | |
a737bd4d | 2956 | { |
c19d1205 | 2957 | literal_pool * pool; |
a737bd4d | 2958 | |
c19d1205 | 2959 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2960 | { |
c19d1205 ZW |
2961 | if (pool->section == now_seg |
2962 | && pool->sub_section == now_subseg) | |
2963 | break; | |
a737bd4d NC |
2964 | } |
2965 | ||
c19d1205 | 2966 | return pool; |
a737bd4d NC |
2967 | } |
2968 | ||
c19d1205 ZW |
2969 | static literal_pool * |
2970 | find_or_make_literal_pool (void) | |
a737bd4d | 2971 | { |
c19d1205 ZW |
2972 | /* Next literal pool ID number. */ |
2973 | static unsigned int latest_pool_num = 1; | |
2974 | literal_pool * pool; | |
a737bd4d | 2975 | |
c19d1205 | 2976 | pool = find_literal_pool (); |
a737bd4d | 2977 | |
c19d1205 | 2978 | if (pool == NULL) |
a737bd4d | 2979 | { |
c19d1205 | 2980 | /* Create a new pool. */ |
21d799b5 | 2981 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
2982 | if (! pool) |
2983 | return NULL; | |
a737bd4d | 2984 | |
c19d1205 ZW |
2985 | pool->next_free_entry = 0; |
2986 | pool->section = now_seg; | |
2987 | pool->sub_section = now_subseg; | |
2988 | pool->next = list_of_pools; | |
2989 | pool->symbol = NULL; | |
2990 | ||
2991 | /* Add it to the list. */ | |
2992 | list_of_pools = pool; | |
a737bd4d | 2993 | } |
a737bd4d | 2994 | |
c19d1205 ZW |
2995 | /* New pools, and emptied pools, will have a NULL symbol. */ |
2996 | if (pool->symbol == NULL) | |
a737bd4d | 2997 | { |
c19d1205 ZW |
2998 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
2999 | (valueT) 0, &zero_address_frag); | |
3000 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3001 | } |
3002 | ||
c19d1205 ZW |
3003 | /* Done. */ |
3004 | return pool; | |
a737bd4d NC |
3005 | } |
3006 | ||
c19d1205 | 3007 | /* Add the literal in the global 'inst' |
5f4273c7 | 3008 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3009 | |
3010 | static int | |
c19d1205 | 3011 | add_to_lit_pool (void) |
b99bd4ef | 3012 | { |
c19d1205 ZW |
3013 | literal_pool * pool; |
3014 | unsigned int entry; | |
b99bd4ef | 3015 | |
c19d1205 ZW |
3016 | pool = find_or_make_literal_pool (); |
3017 | ||
3018 | /* Check if this literal value is already in the pool. */ | |
3019 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3020 | { |
c19d1205 ZW |
3021 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3022 | && (inst.reloc.exp.X_op == O_constant) | |
3023 | && (pool->literals[entry].X_add_number | |
3024 | == inst.reloc.exp.X_add_number) | |
3025 | && (pool->literals[entry].X_unsigned | |
3026 | == inst.reloc.exp.X_unsigned)) | |
3027 | break; | |
3028 | ||
3029 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3030 | && (inst.reloc.exp.X_op == O_symbol) | |
3031 | && (pool->literals[entry].X_add_number | |
3032 | == inst.reloc.exp.X_add_number) | |
3033 | && (pool->literals[entry].X_add_symbol | |
3034 | == inst.reloc.exp.X_add_symbol) | |
3035 | && (pool->literals[entry].X_op_symbol | |
3036 | == inst.reloc.exp.X_op_symbol)) | |
3037 | break; | |
b99bd4ef NC |
3038 | } |
3039 | ||
c19d1205 ZW |
3040 | /* Do we need to create a new entry? */ |
3041 | if (entry == pool->next_free_entry) | |
3042 | { | |
3043 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3044 | { | |
3045 | inst.error = _("literal pool overflow"); | |
3046 | return FAIL; | |
3047 | } | |
3048 | ||
3049 | pool->literals[entry] = inst.reloc.exp; | |
3050 | pool->next_free_entry += 1; | |
3051 | } | |
b99bd4ef | 3052 | |
c19d1205 ZW |
3053 | inst.reloc.exp.X_op = O_symbol; |
3054 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3055 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3056 | |
c19d1205 | 3057 | return SUCCESS; |
b99bd4ef NC |
3058 | } |
3059 | ||
c19d1205 ZW |
3060 | /* Can't use symbol_new here, so have to create a symbol and then at |
3061 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3062 | |
c19d1205 ZW |
3063 | static void |
3064 | symbol_locate (symbolS * symbolP, | |
3065 | const char * name, /* It is copied, the caller can modify. */ | |
3066 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3067 | valueT valu, /* Symbol value. */ | |
3068 | fragS * frag) /* Associated fragment. */ | |
3069 | { | |
3070 | unsigned int name_length; | |
3071 | char * preserved_copy_of_name; | |
e16bb312 | 3072 | |
c19d1205 ZW |
3073 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3074 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3075 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3076 | |
c19d1205 ZW |
3077 | #ifdef tc_canonicalize_symbol_name |
3078 | preserved_copy_of_name = | |
3079 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3080 | #endif | |
b99bd4ef | 3081 | |
c19d1205 | 3082 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3083 | |
c19d1205 ZW |
3084 | S_SET_SEGMENT (symbolP, segment); |
3085 | S_SET_VALUE (symbolP, valu); | |
3086 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3087 | |
c19d1205 | 3088 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3089 | |
c19d1205 ZW |
3090 | /* Link to end of symbol chain. */ |
3091 | { | |
3092 | extern int symbol_table_frozen; | |
b99bd4ef | 3093 | |
c19d1205 ZW |
3094 | if (symbol_table_frozen) |
3095 | abort (); | |
3096 | } | |
b99bd4ef | 3097 | |
c19d1205 | 3098 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3099 | |
c19d1205 | 3100 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3101 | |
c19d1205 ZW |
3102 | #ifdef tc_symbol_new_hook |
3103 | tc_symbol_new_hook (symbolP); | |
3104 | #endif | |
3105 | ||
3106 | #ifdef DEBUG_SYMS | |
3107 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3108 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3109 | } |
3110 | ||
b99bd4ef | 3111 | |
c19d1205 ZW |
3112 | static void |
3113 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3114 | { |
c19d1205 ZW |
3115 | unsigned int entry; |
3116 | literal_pool * pool; | |
3117 | char sym_name[20]; | |
b99bd4ef | 3118 | |
c19d1205 ZW |
3119 | pool = find_literal_pool (); |
3120 | if (pool == NULL | |
3121 | || pool->symbol == NULL | |
3122 | || pool->next_free_entry == 0) | |
3123 | return; | |
b99bd4ef | 3124 | |
c19d1205 | 3125 | mapping_state (MAP_DATA); |
b99bd4ef | 3126 | |
c19d1205 ZW |
3127 | /* Align pool as you have word accesses. |
3128 | Only make a frag if we have to. */ | |
3129 | if (!need_pass_2) | |
3130 | frag_align (2, 0, 0); | |
b99bd4ef | 3131 | |
c19d1205 | 3132 | record_alignment (now_seg, 2); |
b99bd4ef | 3133 | |
c19d1205 | 3134 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3135 | |
c19d1205 ZW |
3136 | symbol_locate (pool->symbol, sym_name, now_seg, |
3137 | (valueT) frag_now_fix (), frag_now); | |
3138 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3139 | |
c19d1205 | 3140 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3141 | |
c19d1205 ZW |
3142 | #if defined OBJ_COFF || defined OBJ_ELF |
3143 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3144 | #endif | |
6c43fab6 | 3145 | |
c19d1205 ZW |
3146 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
3147 | /* First output the expression in the instruction to the pool. */ | |
3148 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 3149 | |
c19d1205 ZW |
3150 | /* Mark the pool as empty. */ |
3151 | pool->next_free_entry = 0; | |
3152 | pool->symbol = NULL; | |
b99bd4ef NC |
3153 | } |
3154 | ||
c19d1205 ZW |
3155 | #ifdef OBJ_ELF |
3156 | /* Forward declarations for functions below, in the MD interface | |
3157 | section. */ | |
3158 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3159 | static valueT create_unwind_entry (int); | |
3160 | static void start_unwind_section (const segT, int); | |
3161 | static void add_unwind_opcode (valueT, int); | |
3162 | static void flush_pending_unwind (void); | |
b99bd4ef | 3163 | |
c19d1205 | 3164 | /* Directives: Data. */ |
b99bd4ef | 3165 | |
c19d1205 ZW |
3166 | static void |
3167 | s_arm_elf_cons (int nbytes) | |
3168 | { | |
3169 | expressionS exp; | |
b99bd4ef | 3170 | |
c19d1205 ZW |
3171 | #ifdef md_flush_pending_output |
3172 | md_flush_pending_output (); | |
3173 | #endif | |
b99bd4ef | 3174 | |
c19d1205 | 3175 | if (is_it_end_of_statement ()) |
b99bd4ef | 3176 | { |
c19d1205 ZW |
3177 | demand_empty_rest_of_line (); |
3178 | return; | |
b99bd4ef NC |
3179 | } |
3180 | ||
c19d1205 ZW |
3181 | #ifdef md_cons_align |
3182 | md_cons_align (nbytes); | |
3183 | #endif | |
b99bd4ef | 3184 | |
c19d1205 ZW |
3185 | mapping_state (MAP_DATA); |
3186 | do | |
b99bd4ef | 3187 | { |
c19d1205 ZW |
3188 | int reloc; |
3189 | char *base = input_line_pointer; | |
b99bd4ef | 3190 | |
c19d1205 | 3191 | expression (& exp); |
b99bd4ef | 3192 | |
c19d1205 ZW |
3193 | if (exp.X_op != O_symbol) |
3194 | emit_expr (&exp, (unsigned int) nbytes); | |
3195 | else | |
3196 | { | |
3197 | char *before_reloc = input_line_pointer; | |
3198 | reloc = parse_reloc (&input_line_pointer); | |
3199 | if (reloc == -1) | |
3200 | { | |
3201 | as_bad (_("unrecognized relocation suffix")); | |
3202 | ignore_rest_of_line (); | |
3203 | return; | |
3204 | } | |
3205 | else if (reloc == BFD_RELOC_UNUSED) | |
3206 | emit_expr (&exp, (unsigned int) nbytes); | |
3207 | else | |
3208 | { | |
21d799b5 NC |
3209 | reloc_howto_type *howto = (reloc_howto_type *) |
3210 | bfd_reloc_type_lookup (stdoutput, | |
3211 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3212 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3213 | |
2fc8bdac ZW |
3214 | if (reloc == BFD_RELOC_ARM_PLT32) |
3215 | { | |
3216 | as_bad (_("(plt) is only valid on branch targets")); | |
3217 | reloc = BFD_RELOC_UNUSED; | |
3218 | size = 0; | |
3219 | } | |
3220 | ||
c19d1205 | 3221 | if (size > nbytes) |
2fc8bdac | 3222 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3223 | howto->name, nbytes); |
3224 | else | |
3225 | { | |
3226 | /* We've parsed an expression stopping at O_symbol. | |
3227 | But there may be more expression left now that we | |
3228 | have parsed the relocation marker. Parse it again. | |
3229 | XXX Surely there is a cleaner way to do this. */ | |
3230 | char *p = input_line_pointer; | |
3231 | int offset; | |
21d799b5 | 3232 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3233 | memcpy (save_buf, base, input_line_pointer - base); |
3234 | memmove (base + (input_line_pointer - before_reloc), | |
3235 | base, before_reloc - base); | |
3236 | ||
3237 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3238 | expression (&exp); | |
3239 | memcpy (base, save_buf, p - base); | |
3240 | ||
3241 | offset = nbytes - size; | |
3242 | p = frag_more ((int) nbytes); | |
3243 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3244 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3245 | } |
3246 | } | |
3247 | } | |
b99bd4ef | 3248 | } |
c19d1205 | 3249 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3250 | |
c19d1205 ZW |
3251 | /* Put terminator back into stream. */ |
3252 | input_line_pointer --; | |
3253 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3254 | } |
3255 | ||
c921be7d NC |
3256 | /* Emit an expression containing a 32-bit thumb instruction. |
3257 | Implementation based on put_thumb32_insn. */ | |
3258 | ||
3259 | static void | |
3260 | emit_thumb32_expr (expressionS * exp) | |
3261 | { | |
3262 | expressionS exp_high = *exp; | |
3263 | ||
3264 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3265 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3266 | exp->X_add_number &= 0xffff; | |
3267 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3268 | } | |
3269 | ||
3270 | /* Guess the instruction size based on the opcode. */ | |
3271 | ||
3272 | static int | |
3273 | thumb_insn_size (int opcode) | |
3274 | { | |
3275 | if ((unsigned int) opcode < 0xe800u) | |
3276 | return 2; | |
3277 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3278 | return 4; | |
3279 | else | |
3280 | return 0; | |
3281 | } | |
3282 | ||
3283 | static bfd_boolean | |
3284 | emit_insn (expressionS *exp, int nbytes) | |
3285 | { | |
3286 | int size = 0; | |
3287 | ||
3288 | if (exp->X_op == O_constant) | |
3289 | { | |
3290 | size = nbytes; | |
3291 | ||
3292 | if (size == 0) | |
3293 | size = thumb_insn_size (exp->X_add_number); | |
3294 | ||
3295 | if (size != 0) | |
3296 | { | |
3297 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3298 | { | |
3299 | as_bad (_(".inst.n operand too big. "\ | |
3300 | "Use .inst.w instead")); | |
3301 | size = 0; | |
3302 | } | |
3303 | else | |
3304 | { | |
3305 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3306 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3307 | else | |
3308 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3309 | ||
3310 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3311 | emit_thumb32_expr (exp); | |
3312 | else | |
3313 | emit_expr (exp, (unsigned int) size); | |
3314 | ||
3315 | it_fsm_post_encode (); | |
3316 | } | |
3317 | } | |
3318 | else | |
3319 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3320 | "Use .inst.n/.inst.w instead")); | |
3321 | } | |
3322 | else | |
3323 | as_bad (_("constant expression required")); | |
3324 | ||
3325 | return (size != 0); | |
3326 | } | |
3327 | ||
3328 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3329 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3330 | ||
3331 | static void | |
3332 | s_arm_elf_inst (int nbytes) | |
3333 | { | |
3334 | if (is_it_end_of_statement ()) | |
3335 | { | |
3336 | demand_empty_rest_of_line (); | |
3337 | return; | |
3338 | } | |
3339 | ||
3340 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3341 | but will ensure not to be in DATA state. */ | |
3342 | ||
3343 | if (thumb_mode) | |
3344 | mapping_state (MAP_THUMB); | |
3345 | else | |
3346 | { | |
3347 | if (nbytes != 0) | |
3348 | { | |
3349 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3350 | ignore_rest_of_line (); | |
3351 | return; | |
3352 | } | |
3353 | ||
3354 | nbytes = 4; | |
3355 | ||
3356 | mapping_state (MAP_ARM); | |
3357 | } | |
3358 | ||
3359 | do | |
3360 | { | |
3361 | expressionS exp; | |
3362 | ||
3363 | expression (& exp); | |
3364 | ||
3365 | if (! emit_insn (& exp, nbytes)) | |
3366 | { | |
3367 | ignore_rest_of_line (); | |
3368 | return; | |
3369 | } | |
3370 | } | |
3371 | while (*input_line_pointer++ == ','); | |
3372 | ||
3373 | /* Put terminator back into stream. */ | |
3374 | input_line_pointer --; | |
3375 | demand_empty_rest_of_line (); | |
3376 | } | |
b99bd4ef | 3377 | |
c19d1205 | 3378 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3379 | |
c19d1205 ZW |
3380 | static void |
3381 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3382 | { | |
3383 | expressionS exp; | |
3384 | char *p; | |
3385 | valueT highbit; | |
b99bd4ef | 3386 | |
c19d1205 ZW |
3387 | highbit = 0; |
3388 | if (*input_line_pointer == '1') | |
3389 | highbit = 0x80000000; | |
3390 | else if (*input_line_pointer != '0') | |
3391 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3392 | |
c19d1205 ZW |
3393 | input_line_pointer++; |
3394 | if (*input_line_pointer != ',') | |
3395 | as_bad (_("missing comma")); | |
3396 | input_line_pointer++; | |
b99bd4ef | 3397 | |
c19d1205 ZW |
3398 | #ifdef md_flush_pending_output |
3399 | md_flush_pending_output (); | |
3400 | #endif | |
b99bd4ef | 3401 | |
c19d1205 ZW |
3402 | #ifdef md_cons_align |
3403 | md_cons_align (4); | |
3404 | #endif | |
b99bd4ef | 3405 | |
c19d1205 | 3406 | mapping_state (MAP_DATA); |
b99bd4ef | 3407 | |
c19d1205 | 3408 | expression (&exp); |
b99bd4ef | 3409 | |
c19d1205 ZW |
3410 | p = frag_more (4); |
3411 | md_number_to_chars (p, highbit, 4); | |
3412 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3413 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3414 | |
c19d1205 | 3415 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3416 | } |
3417 | ||
c19d1205 | 3418 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3419 | |
c19d1205 | 3420 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3421 | |
c19d1205 ZW |
3422 | static void |
3423 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3424 | { | |
3425 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3426 | if (unwind.proc_start) |
3427 | { | |
c921be7d | 3428 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3429 | return; |
3430 | } | |
3431 | ||
c19d1205 ZW |
3432 | /* Mark the start of the function. */ |
3433 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3434 | |
c19d1205 ZW |
3435 | /* Reset the rest of the unwind info. */ |
3436 | unwind.opcode_count = 0; | |
3437 | unwind.table_entry = NULL; | |
3438 | unwind.personality_routine = NULL; | |
3439 | unwind.personality_index = -1; | |
3440 | unwind.frame_size = 0; | |
3441 | unwind.fp_offset = 0; | |
fdfde340 | 3442 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3443 | unwind.fp_used = 0; |
3444 | unwind.sp_restored = 0; | |
3445 | } | |
b99bd4ef | 3446 | |
b99bd4ef | 3447 | |
c19d1205 ZW |
3448 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3449 | for the function. */ | |
b99bd4ef | 3450 | |
c19d1205 ZW |
3451 | static void |
3452 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3453 | { | |
3454 | demand_empty_rest_of_line (); | |
921e5f0a | 3455 | if (!unwind.proc_start) |
c921be7d | 3456 | as_bad (MISSING_FNSTART); |
921e5f0a | 3457 | |
c19d1205 | 3458 | if (unwind.table_entry) |
6decc662 | 3459 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3460 | |
c19d1205 ZW |
3461 | create_unwind_entry (1); |
3462 | } | |
a737bd4d | 3463 | |
c19d1205 | 3464 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3465 | |
c19d1205 ZW |
3466 | static void |
3467 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3468 | { | |
3469 | long where; | |
3470 | char *ptr; | |
3471 | valueT val; | |
940b5ce0 | 3472 | unsigned int marked_pr_dependency; |
f02232aa | 3473 | |
c19d1205 | 3474 | demand_empty_rest_of_line (); |
f02232aa | 3475 | |
921e5f0a PB |
3476 | if (!unwind.proc_start) |
3477 | { | |
c921be7d | 3478 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3479 | return; |
3480 | } | |
3481 | ||
c19d1205 ZW |
3482 | /* Add eh table entry. */ |
3483 | if (unwind.table_entry == NULL) | |
3484 | val = create_unwind_entry (0); | |
3485 | else | |
3486 | val = 0; | |
f02232aa | 3487 | |
c19d1205 ZW |
3488 | /* Add index table entry. This is two words. */ |
3489 | start_unwind_section (unwind.saved_seg, 1); | |
3490 | frag_align (2, 0, 0); | |
3491 | record_alignment (now_seg, 2); | |
b99bd4ef | 3492 | |
c19d1205 ZW |
3493 | ptr = frag_more (8); |
3494 | where = frag_now_fix () - 8; | |
f02232aa | 3495 | |
c19d1205 ZW |
3496 | /* Self relative offset of the function start. */ |
3497 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3498 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3499 | |
c19d1205 ZW |
3500 | /* Indicate dependency on EHABI-defined personality routines to the |
3501 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3502 | marked_pr_dependency |
3503 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3504 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3505 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3506 | { | |
5f4273c7 NC |
3507 | static const char *const name[] = |
3508 | { | |
3509 | "__aeabi_unwind_cpp_pr0", | |
3510 | "__aeabi_unwind_cpp_pr1", | |
3511 | "__aeabi_unwind_cpp_pr2" | |
3512 | }; | |
c19d1205 ZW |
3513 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3514 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3515 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3516 | |= 1 << unwind.personality_index; |
c19d1205 | 3517 | } |
f02232aa | 3518 | |
c19d1205 ZW |
3519 | if (val) |
3520 | /* Inline exception table entry. */ | |
3521 | md_number_to_chars (ptr + 4, val, 4); | |
3522 | else | |
3523 | /* Self relative offset of the table entry. */ | |
3524 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3525 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3526 | |
c19d1205 ZW |
3527 | /* Restore the original section. */ |
3528 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3529 | |
3530 | unwind.proc_start = NULL; | |
c19d1205 | 3531 | } |
f02232aa | 3532 | |
f02232aa | 3533 | |
c19d1205 | 3534 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3535 | |
c19d1205 ZW |
3536 | static void |
3537 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3538 | { | |
3539 | demand_empty_rest_of_line (); | |
921e5f0a | 3540 | if (!unwind.proc_start) |
c921be7d | 3541 | as_bad (MISSING_FNSTART); |
921e5f0a | 3542 | |
c19d1205 ZW |
3543 | if (unwind.personality_routine || unwind.personality_index != -1) |
3544 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3545 | |
c19d1205 ZW |
3546 | unwind.personality_index = -2; |
3547 | } | |
b99bd4ef | 3548 | |
b99bd4ef | 3549 | |
c19d1205 | 3550 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3551 | |
c19d1205 ZW |
3552 | static void |
3553 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3554 | { | |
3555 | expressionS exp; | |
b99bd4ef | 3556 | |
921e5f0a | 3557 | if (!unwind.proc_start) |
c921be7d | 3558 | as_bad (MISSING_FNSTART); |
921e5f0a | 3559 | |
c19d1205 ZW |
3560 | if (unwind.personality_routine || unwind.personality_index != -1) |
3561 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3562 | |
c19d1205 | 3563 | expression (&exp); |
b99bd4ef | 3564 | |
c19d1205 ZW |
3565 | if (exp.X_op != O_constant |
3566 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3567 | { |
c19d1205 ZW |
3568 | as_bad (_("bad personality routine number")); |
3569 | ignore_rest_of_line (); | |
3570 | return; | |
b99bd4ef NC |
3571 | } |
3572 | ||
c19d1205 | 3573 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3574 | |
c19d1205 ZW |
3575 | demand_empty_rest_of_line (); |
3576 | } | |
e16bb312 | 3577 | |
e16bb312 | 3578 | |
c19d1205 | 3579 | /* Parse a personality directive. */ |
e16bb312 | 3580 | |
c19d1205 ZW |
3581 | static void |
3582 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3583 | { | |
3584 | char *name, *p, c; | |
a737bd4d | 3585 | |
921e5f0a | 3586 | if (!unwind.proc_start) |
c921be7d | 3587 | as_bad (MISSING_FNSTART); |
921e5f0a | 3588 | |
c19d1205 ZW |
3589 | if (unwind.personality_routine || unwind.personality_index != -1) |
3590 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3591 | |
c19d1205 ZW |
3592 | name = input_line_pointer; |
3593 | c = get_symbol_end (); | |
3594 | p = input_line_pointer; | |
3595 | unwind.personality_routine = symbol_find_or_make (name); | |
3596 | *p = c; | |
3597 | demand_empty_rest_of_line (); | |
3598 | } | |
e16bb312 | 3599 | |
e16bb312 | 3600 | |
c19d1205 | 3601 | /* Parse a directive saving core registers. */ |
e16bb312 | 3602 | |
c19d1205 ZW |
3603 | static void |
3604 | s_arm_unwind_save_core (void) | |
e16bb312 | 3605 | { |
c19d1205 ZW |
3606 | valueT op; |
3607 | long range; | |
3608 | int n; | |
e16bb312 | 3609 | |
c19d1205 ZW |
3610 | range = parse_reg_list (&input_line_pointer); |
3611 | if (range == FAIL) | |
e16bb312 | 3612 | { |
c19d1205 ZW |
3613 | as_bad (_("expected register list")); |
3614 | ignore_rest_of_line (); | |
3615 | return; | |
3616 | } | |
e16bb312 | 3617 | |
c19d1205 | 3618 | demand_empty_rest_of_line (); |
e16bb312 | 3619 | |
c19d1205 ZW |
3620 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3621 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3622 | ip because it is clobbered by calls. */ | |
3623 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3624 | && (range & 0x3000) == 0x1000) | |
3625 | { | |
3626 | unwind.opcode_count--; | |
3627 | unwind.sp_restored = 0; | |
3628 | range = (range | 0x2000) & ~0x1000; | |
3629 | unwind.pending_offset = 0; | |
3630 | } | |
e16bb312 | 3631 | |
01ae4198 DJ |
3632 | /* Pop r4-r15. */ |
3633 | if (range & 0xfff0) | |
c19d1205 | 3634 | { |
01ae4198 DJ |
3635 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3636 | registers starting with r4, plus maybe r14. */ | |
3637 | for (n = 0; n < 8; n++) | |
3638 | { | |
3639 | /* Break at the first non-saved register. */ | |
3640 | if ((range & (1 << (n + 4))) == 0) | |
3641 | break; | |
3642 | } | |
3643 | /* See if there are any other bits set. */ | |
3644 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3645 | { | |
3646 | /* Use the long form. */ | |
3647 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3648 | add_unwind_opcode (op, 2); | |
3649 | } | |
0dd132b6 | 3650 | else |
01ae4198 DJ |
3651 | { |
3652 | /* Use the short form. */ | |
3653 | if (range & 0x4000) | |
3654 | op = 0xa8; /* Pop r14. */ | |
3655 | else | |
3656 | op = 0xa0; /* Do not pop r14. */ | |
3657 | op |= (n - 1); | |
3658 | add_unwind_opcode (op, 1); | |
3659 | } | |
c19d1205 | 3660 | } |
0dd132b6 | 3661 | |
c19d1205 ZW |
3662 | /* Pop r0-r3. */ |
3663 | if (range & 0xf) | |
3664 | { | |
3665 | op = 0xb100 | (range & 0xf); | |
3666 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3667 | } |
3668 | ||
c19d1205 ZW |
3669 | /* Record the number of bytes pushed. */ |
3670 | for (n = 0; n < 16; n++) | |
3671 | { | |
3672 | if (range & (1 << n)) | |
3673 | unwind.frame_size += 4; | |
3674 | } | |
0dd132b6 NC |
3675 | } |
3676 | ||
c19d1205 ZW |
3677 | |
3678 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3679 | |
3680 | static void | |
c19d1205 | 3681 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3682 | { |
c19d1205 ZW |
3683 | expressionS exp; |
3684 | int num_regs; | |
3685 | valueT op; | |
b99bd4ef | 3686 | |
c19d1205 ZW |
3687 | /* Get Number of registers to transfer. */ |
3688 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3689 | expression (&exp); | |
3690 | else | |
3691 | exp.X_op = O_illegal; | |
b99bd4ef | 3692 | |
c19d1205 | 3693 | if (exp.X_op != O_constant) |
b99bd4ef | 3694 | { |
c19d1205 ZW |
3695 | as_bad (_("expected , <constant>")); |
3696 | ignore_rest_of_line (); | |
b99bd4ef NC |
3697 | return; |
3698 | } | |
3699 | ||
c19d1205 ZW |
3700 | num_regs = exp.X_add_number; |
3701 | ||
3702 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3703 | { |
c19d1205 ZW |
3704 | as_bad (_("number of registers must be in the range [1:4]")); |
3705 | ignore_rest_of_line (); | |
b99bd4ef NC |
3706 | return; |
3707 | } | |
3708 | ||
c19d1205 | 3709 | demand_empty_rest_of_line (); |
b99bd4ef | 3710 | |
c19d1205 ZW |
3711 | if (reg == 4) |
3712 | { | |
3713 | /* Short form. */ | |
3714 | op = 0xb4 | (num_regs - 1); | |
3715 | add_unwind_opcode (op, 1); | |
3716 | } | |
b99bd4ef NC |
3717 | else |
3718 | { | |
c19d1205 ZW |
3719 | /* Long form. */ |
3720 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3721 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3722 | } |
c19d1205 | 3723 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3724 | } |
3725 | ||
c19d1205 | 3726 | |
fa073d69 MS |
3727 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3728 | ||
3729 | static void | |
3730 | s_arm_unwind_save_vfp_armv6 (void) | |
3731 | { | |
3732 | int count; | |
3733 | unsigned int start; | |
3734 | valueT op; | |
3735 | int num_vfpv3_regs = 0; | |
3736 | int num_regs_below_16; | |
3737 | ||
3738 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3739 | if (count == FAIL) | |
3740 | { | |
3741 | as_bad (_("expected register list")); | |
3742 | ignore_rest_of_line (); | |
3743 | return; | |
3744 | } | |
3745 | ||
3746 | demand_empty_rest_of_line (); | |
3747 | ||
3748 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3749 | than FSTMX/FLDMX-style ones). */ | |
3750 | ||
3751 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3752 | if (start >= 16) | |
3753 | num_vfpv3_regs = count; | |
3754 | else if (start + count > 16) | |
3755 | num_vfpv3_regs = start + count - 16; | |
3756 | ||
3757 | if (num_vfpv3_regs > 0) | |
3758 | { | |
3759 | int start_offset = start > 16 ? start - 16 : 0; | |
3760 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3761 | add_unwind_opcode (op, 2); | |
3762 | } | |
3763 | ||
3764 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3765 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3766 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3767 | if (num_regs_below_16 > 0) |
3768 | { | |
3769 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3770 | add_unwind_opcode (op, 2); | |
3771 | } | |
3772 | ||
3773 | unwind.frame_size += count * 8; | |
3774 | } | |
3775 | ||
3776 | ||
3777 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3778 | |
3779 | static void | |
c19d1205 | 3780 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3781 | { |
c19d1205 | 3782 | int count; |
ca3f61f7 | 3783 | unsigned int reg; |
c19d1205 | 3784 | valueT op; |
b99bd4ef | 3785 | |
5287ad62 | 3786 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3787 | if (count == FAIL) |
b99bd4ef | 3788 | { |
c19d1205 ZW |
3789 | as_bad (_("expected register list")); |
3790 | ignore_rest_of_line (); | |
b99bd4ef NC |
3791 | return; |
3792 | } | |
3793 | ||
c19d1205 | 3794 | demand_empty_rest_of_line (); |
b99bd4ef | 3795 | |
c19d1205 | 3796 | if (reg == 8) |
b99bd4ef | 3797 | { |
c19d1205 ZW |
3798 | /* Short form. */ |
3799 | op = 0xb8 | (count - 1); | |
3800 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3801 | } |
c19d1205 | 3802 | else |
b99bd4ef | 3803 | { |
c19d1205 ZW |
3804 | /* Long form. */ |
3805 | op = 0xb300 | (reg << 4) | (count - 1); | |
3806 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3807 | } |
c19d1205 ZW |
3808 | unwind.frame_size += count * 8 + 4; |
3809 | } | |
b99bd4ef | 3810 | |
b99bd4ef | 3811 | |
c19d1205 ZW |
3812 | /* Parse a directive saving iWMMXt data registers. */ |
3813 | ||
3814 | static void | |
3815 | s_arm_unwind_save_mmxwr (void) | |
3816 | { | |
3817 | int reg; | |
3818 | int hi_reg; | |
3819 | int i; | |
3820 | unsigned mask = 0; | |
3821 | valueT op; | |
b99bd4ef | 3822 | |
c19d1205 ZW |
3823 | if (*input_line_pointer == '{') |
3824 | input_line_pointer++; | |
b99bd4ef | 3825 | |
c19d1205 | 3826 | do |
b99bd4ef | 3827 | { |
dcbf9037 | 3828 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3829 | |
c19d1205 | 3830 | if (reg == FAIL) |
b99bd4ef | 3831 | { |
9b7132d3 | 3832 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3833 | goto error; |
b99bd4ef NC |
3834 | } |
3835 | ||
c19d1205 ZW |
3836 | if (mask >> reg) |
3837 | as_tsktsk (_("register list not in ascending order")); | |
3838 | mask |= 1 << reg; | |
b99bd4ef | 3839 | |
c19d1205 ZW |
3840 | if (*input_line_pointer == '-') |
3841 | { | |
3842 | input_line_pointer++; | |
dcbf9037 | 3843 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3844 | if (hi_reg == FAIL) |
3845 | { | |
9b7132d3 | 3846 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3847 | goto error; |
3848 | } | |
3849 | else if (reg >= hi_reg) | |
3850 | { | |
3851 | as_bad (_("bad register range")); | |
3852 | goto error; | |
3853 | } | |
3854 | for (; reg < hi_reg; reg++) | |
3855 | mask |= 1 << reg; | |
3856 | } | |
3857 | } | |
3858 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3859 | |
c19d1205 ZW |
3860 | if (*input_line_pointer == '}') |
3861 | input_line_pointer++; | |
b99bd4ef | 3862 | |
c19d1205 | 3863 | demand_empty_rest_of_line (); |
b99bd4ef | 3864 | |
708587a4 | 3865 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3866 | the list. */ |
3867 | flush_pending_unwind (); | |
b99bd4ef | 3868 | |
c19d1205 | 3869 | for (i = 0; i < 16; i++) |
b99bd4ef | 3870 | { |
c19d1205 ZW |
3871 | if (mask & (1 << i)) |
3872 | unwind.frame_size += 8; | |
b99bd4ef NC |
3873 | } |
3874 | ||
c19d1205 ZW |
3875 | /* Attempt to combine with a previous opcode. We do this because gcc |
3876 | likes to output separate unwind directives for a single block of | |
3877 | registers. */ | |
3878 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3879 | { |
c19d1205 ZW |
3880 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3881 | if ((i & 0xf8) == 0xc0) | |
3882 | { | |
3883 | i &= 7; | |
3884 | /* Only merge if the blocks are contiguous. */ | |
3885 | if (i < 6) | |
3886 | { | |
3887 | if ((mask & 0xfe00) == (1 << 9)) | |
3888 | { | |
3889 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3890 | unwind.opcode_count--; | |
3891 | } | |
3892 | } | |
3893 | else if (i == 6 && unwind.opcode_count >= 2) | |
3894 | { | |
3895 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3896 | reg = i >> 4; | |
3897 | i &= 0xf; | |
b99bd4ef | 3898 | |
c19d1205 ZW |
3899 | op = 0xffff << (reg - 1); |
3900 | if (reg > 0 | |
87a1fd79 | 3901 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3902 | { |
3903 | op = (1 << (reg + i + 1)) - 1; | |
3904 | op &= ~((1 << reg) - 1); | |
3905 | mask |= op; | |
3906 | unwind.opcode_count -= 2; | |
3907 | } | |
3908 | } | |
3909 | } | |
b99bd4ef NC |
3910 | } |
3911 | ||
c19d1205 ZW |
3912 | hi_reg = 15; |
3913 | /* We want to generate opcodes in the order the registers have been | |
3914 | saved, ie. descending order. */ | |
3915 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3916 | { |
c19d1205 ZW |
3917 | /* Save registers in blocks. */ |
3918 | if (reg < 0 | |
3919 | || !(mask & (1 << reg))) | |
3920 | { | |
3921 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3922 | preceding block. */ |
c19d1205 ZW |
3923 | if (reg != hi_reg) |
3924 | { | |
3925 | if (reg == 9) | |
3926 | { | |
3927 | /* Short form. */ | |
3928 | op = 0xc0 | (hi_reg - 10); | |
3929 | add_unwind_opcode (op, 1); | |
3930 | } | |
3931 | else | |
3932 | { | |
3933 | /* Long form. */ | |
3934 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3935 | add_unwind_opcode (op, 2); | |
3936 | } | |
3937 | } | |
3938 | hi_reg = reg - 1; | |
3939 | } | |
b99bd4ef NC |
3940 | } |
3941 | ||
c19d1205 ZW |
3942 | return; |
3943 | error: | |
3944 | ignore_rest_of_line (); | |
b99bd4ef NC |
3945 | } |
3946 | ||
3947 | static void | |
c19d1205 | 3948 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3949 | { |
c19d1205 ZW |
3950 | int reg; |
3951 | int hi_reg; | |
3952 | unsigned mask = 0; | |
3953 | valueT op; | |
b99bd4ef | 3954 | |
c19d1205 ZW |
3955 | if (*input_line_pointer == '{') |
3956 | input_line_pointer++; | |
b99bd4ef | 3957 | |
c19d1205 | 3958 | do |
b99bd4ef | 3959 | { |
dcbf9037 | 3960 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3961 | |
c19d1205 ZW |
3962 | if (reg == FAIL) |
3963 | { | |
9b7132d3 | 3964 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3965 | goto error; |
3966 | } | |
b99bd4ef | 3967 | |
c19d1205 ZW |
3968 | reg -= 8; |
3969 | if (mask >> reg) | |
3970 | as_tsktsk (_("register list not in ascending order")); | |
3971 | mask |= 1 << reg; | |
b99bd4ef | 3972 | |
c19d1205 ZW |
3973 | if (*input_line_pointer == '-') |
3974 | { | |
3975 | input_line_pointer++; | |
dcbf9037 | 3976 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3977 | if (hi_reg == FAIL) |
3978 | { | |
9b7132d3 | 3979 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3980 | goto error; |
3981 | } | |
3982 | else if (reg >= hi_reg) | |
3983 | { | |
3984 | as_bad (_("bad register range")); | |
3985 | goto error; | |
3986 | } | |
3987 | for (; reg < hi_reg; reg++) | |
3988 | mask |= 1 << reg; | |
3989 | } | |
b99bd4ef | 3990 | } |
c19d1205 | 3991 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 3992 | |
c19d1205 ZW |
3993 | if (*input_line_pointer == '}') |
3994 | input_line_pointer++; | |
b99bd4ef | 3995 | |
c19d1205 ZW |
3996 | demand_empty_rest_of_line (); |
3997 | ||
708587a4 | 3998 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3999 | the list. */ |
4000 | flush_pending_unwind (); | |
b99bd4ef | 4001 | |
c19d1205 | 4002 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4003 | { |
c19d1205 ZW |
4004 | if (mask & (1 << reg)) |
4005 | unwind.frame_size += 4; | |
b99bd4ef | 4006 | } |
c19d1205 ZW |
4007 | op = 0xc700 | mask; |
4008 | add_unwind_opcode (op, 2); | |
4009 | return; | |
4010 | error: | |
4011 | ignore_rest_of_line (); | |
b99bd4ef NC |
4012 | } |
4013 | ||
c19d1205 | 4014 | |
fa073d69 MS |
4015 | /* Parse an unwind_save directive. |
4016 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4017 | |
b99bd4ef | 4018 | static void |
fa073d69 | 4019 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4020 | { |
c19d1205 ZW |
4021 | char *peek; |
4022 | struct reg_entry *reg; | |
4023 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4024 | |
921e5f0a | 4025 | if (!unwind.proc_start) |
c921be7d | 4026 | as_bad (MISSING_FNSTART); |
921e5f0a | 4027 | |
c19d1205 ZW |
4028 | /* Figure out what sort of save we have. */ |
4029 | peek = input_line_pointer; | |
b99bd4ef | 4030 | |
c19d1205 | 4031 | if (*peek == '{') |
b99bd4ef | 4032 | { |
c19d1205 ZW |
4033 | had_brace = TRUE; |
4034 | peek++; | |
b99bd4ef NC |
4035 | } |
4036 | ||
c19d1205 | 4037 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4038 | |
c19d1205 | 4039 | if (!reg) |
b99bd4ef | 4040 | { |
c19d1205 ZW |
4041 | as_bad (_("register expected")); |
4042 | ignore_rest_of_line (); | |
b99bd4ef NC |
4043 | return; |
4044 | } | |
4045 | ||
c19d1205 | 4046 | switch (reg->type) |
b99bd4ef | 4047 | { |
c19d1205 ZW |
4048 | case REG_TYPE_FN: |
4049 | if (had_brace) | |
4050 | { | |
4051 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4052 | ignore_rest_of_line (); | |
4053 | return; | |
4054 | } | |
93ac2687 | 4055 | input_line_pointer = peek; |
c19d1205 | 4056 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4057 | return; |
c19d1205 ZW |
4058 | |
4059 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4060 | case REG_TYPE_VFD: |
4061 | if (arch_v6) | |
4062 | s_arm_unwind_save_vfp_armv6 (); | |
4063 | else | |
4064 | s_arm_unwind_save_vfp (); | |
4065 | return; | |
c19d1205 ZW |
4066 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4067 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4068 | ||
4069 | default: | |
4070 | as_bad (_(".unwind_save does not support this kind of register")); | |
4071 | ignore_rest_of_line (); | |
b99bd4ef | 4072 | } |
c19d1205 | 4073 | } |
b99bd4ef | 4074 | |
b99bd4ef | 4075 | |
c19d1205 ZW |
4076 | /* Parse an unwind_movsp directive. */ |
4077 | ||
4078 | static void | |
4079 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4080 | { | |
4081 | int reg; | |
4082 | valueT op; | |
4fa3602b | 4083 | int offset; |
c19d1205 | 4084 | |
921e5f0a | 4085 | if (!unwind.proc_start) |
c921be7d | 4086 | as_bad (MISSING_FNSTART); |
921e5f0a | 4087 | |
dcbf9037 | 4088 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4089 | if (reg == FAIL) |
b99bd4ef | 4090 | { |
9b7132d3 | 4091 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4092 | ignore_rest_of_line (); |
b99bd4ef NC |
4093 | return; |
4094 | } | |
4fa3602b PB |
4095 | |
4096 | /* Optional constant. */ | |
4097 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4098 | { | |
4099 | if (immediate_for_directive (&offset) == FAIL) | |
4100 | return; | |
4101 | } | |
4102 | else | |
4103 | offset = 0; | |
4104 | ||
c19d1205 | 4105 | demand_empty_rest_of_line (); |
b99bd4ef | 4106 | |
c19d1205 | 4107 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4108 | { |
c19d1205 | 4109 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4110 | return; |
4111 | } | |
4112 | ||
c19d1205 ZW |
4113 | if (unwind.fp_reg != REG_SP) |
4114 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4115 | |
c19d1205 ZW |
4116 | /* Generate opcode to restore the value. */ |
4117 | op = 0x90 | reg; | |
4118 | add_unwind_opcode (op, 1); | |
4119 | ||
4120 | /* Record the information for later. */ | |
4121 | unwind.fp_reg = reg; | |
4fa3602b | 4122 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4123 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4124 | } |
4125 | ||
c19d1205 ZW |
4126 | /* Parse an unwind_pad directive. */ |
4127 | ||
b05fe5cf | 4128 | static void |
c19d1205 | 4129 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4130 | { |
c19d1205 | 4131 | int offset; |
b05fe5cf | 4132 | |
921e5f0a | 4133 | if (!unwind.proc_start) |
c921be7d | 4134 | as_bad (MISSING_FNSTART); |
921e5f0a | 4135 | |
c19d1205 ZW |
4136 | if (immediate_for_directive (&offset) == FAIL) |
4137 | return; | |
b99bd4ef | 4138 | |
c19d1205 ZW |
4139 | if (offset & 3) |
4140 | { | |
4141 | as_bad (_("stack increment must be multiple of 4")); | |
4142 | ignore_rest_of_line (); | |
4143 | return; | |
4144 | } | |
b99bd4ef | 4145 | |
c19d1205 ZW |
4146 | /* Don't generate any opcodes, just record the details for later. */ |
4147 | unwind.frame_size += offset; | |
4148 | unwind.pending_offset += offset; | |
4149 | ||
4150 | demand_empty_rest_of_line (); | |
4151 | } | |
4152 | ||
4153 | /* Parse an unwind_setfp directive. */ | |
4154 | ||
4155 | static void | |
4156 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4157 | { |
c19d1205 ZW |
4158 | int sp_reg; |
4159 | int fp_reg; | |
4160 | int offset; | |
4161 | ||
921e5f0a | 4162 | if (!unwind.proc_start) |
c921be7d | 4163 | as_bad (MISSING_FNSTART); |
921e5f0a | 4164 | |
dcbf9037 | 4165 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4166 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4167 | sp_reg = FAIL; | |
4168 | else | |
dcbf9037 | 4169 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4170 | |
c19d1205 ZW |
4171 | if (fp_reg == FAIL || sp_reg == FAIL) |
4172 | { | |
4173 | as_bad (_("expected <reg>, <reg>")); | |
4174 | ignore_rest_of_line (); | |
4175 | return; | |
4176 | } | |
b99bd4ef | 4177 | |
c19d1205 ZW |
4178 | /* Optional constant. */ |
4179 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4180 | { | |
4181 | if (immediate_for_directive (&offset) == FAIL) | |
4182 | return; | |
4183 | } | |
4184 | else | |
4185 | offset = 0; | |
a737bd4d | 4186 | |
c19d1205 | 4187 | demand_empty_rest_of_line (); |
a737bd4d | 4188 | |
fdfde340 | 4189 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4190 | { |
c19d1205 ZW |
4191 | as_bad (_("register must be either sp or set by a previous" |
4192 | "unwind_movsp directive")); | |
4193 | return; | |
a737bd4d NC |
4194 | } |
4195 | ||
c19d1205 ZW |
4196 | /* Don't generate any opcodes, just record the information for later. */ |
4197 | unwind.fp_reg = fp_reg; | |
4198 | unwind.fp_used = 1; | |
fdfde340 | 4199 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4200 | unwind.fp_offset = unwind.frame_size - offset; |
4201 | else | |
4202 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4203 | } |
4204 | ||
c19d1205 ZW |
4205 | /* Parse an unwind_raw directive. */ |
4206 | ||
4207 | static void | |
4208 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4209 | { |
c19d1205 | 4210 | expressionS exp; |
708587a4 | 4211 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4212 | unsigned char op[16]; |
4213 | int count; | |
a737bd4d | 4214 | |
921e5f0a | 4215 | if (!unwind.proc_start) |
c921be7d | 4216 | as_bad (MISSING_FNSTART); |
921e5f0a | 4217 | |
c19d1205 ZW |
4218 | expression (&exp); |
4219 | if (exp.X_op == O_constant | |
4220 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4221 | { |
c19d1205 ZW |
4222 | unwind.frame_size += exp.X_add_number; |
4223 | expression (&exp); | |
4224 | } | |
4225 | else | |
4226 | exp.X_op = O_illegal; | |
a737bd4d | 4227 | |
c19d1205 ZW |
4228 | if (exp.X_op != O_constant) |
4229 | { | |
4230 | as_bad (_("expected <offset>, <opcode>")); | |
4231 | ignore_rest_of_line (); | |
4232 | return; | |
4233 | } | |
a737bd4d | 4234 | |
c19d1205 | 4235 | count = 0; |
a737bd4d | 4236 | |
c19d1205 ZW |
4237 | /* Parse the opcode. */ |
4238 | for (;;) | |
4239 | { | |
4240 | if (count >= 16) | |
4241 | { | |
4242 | as_bad (_("unwind opcode too long")); | |
4243 | ignore_rest_of_line (); | |
a737bd4d | 4244 | } |
c19d1205 | 4245 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4246 | { |
c19d1205 ZW |
4247 | as_bad (_("invalid unwind opcode")); |
4248 | ignore_rest_of_line (); | |
4249 | return; | |
a737bd4d | 4250 | } |
c19d1205 | 4251 | op[count++] = exp.X_add_number; |
a737bd4d | 4252 | |
c19d1205 ZW |
4253 | /* Parse the next byte. */ |
4254 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4255 | break; | |
a737bd4d | 4256 | |
c19d1205 ZW |
4257 | expression (&exp); |
4258 | } | |
b99bd4ef | 4259 | |
c19d1205 ZW |
4260 | /* Add the opcode bytes in reverse order. */ |
4261 | while (count--) | |
4262 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4263 | |
c19d1205 | 4264 | demand_empty_rest_of_line (); |
b99bd4ef | 4265 | } |
ee065d83 PB |
4266 | |
4267 | ||
4268 | /* Parse a .eabi_attribute directive. */ | |
4269 | ||
4270 | static void | |
4271 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4272 | { | |
ee3c0378 AS |
4273 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4274 | ||
4275 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4276 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4277 | } |
4278 | ||
0855e32b NS |
4279 | /* Emit a tls fix for the symbol. */ |
4280 | ||
4281 | static void | |
4282 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4283 | { | |
4284 | char *p; | |
4285 | expressionS exp; | |
4286 | #ifdef md_flush_pending_output | |
4287 | md_flush_pending_output (); | |
4288 | #endif | |
4289 | ||
4290 | #ifdef md_cons_align | |
4291 | md_cons_align (4); | |
4292 | #endif | |
4293 | ||
4294 | /* Since we're just labelling the code, there's no need to define a | |
4295 | mapping symbol. */ | |
4296 | expression (&exp); | |
4297 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4298 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4299 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4300 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4301 | } | |
cdf9ccec | 4302 | #endif /* OBJ_ELF */ |
0855e32b | 4303 | |
ee065d83 | 4304 | static void s_arm_arch (int); |
7a1d4c38 | 4305 | static void s_arm_object_arch (int); |
ee065d83 PB |
4306 | static void s_arm_cpu (int); |
4307 | static void s_arm_fpu (int); | |
69133863 | 4308 | static void s_arm_arch_extension (int); |
b99bd4ef | 4309 | |
f0927246 NC |
4310 | #ifdef TE_PE |
4311 | ||
4312 | static void | |
5f4273c7 | 4313 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4314 | { |
4315 | expressionS exp; | |
4316 | ||
4317 | do | |
4318 | { | |
4319 | expression (&exp); | |
4320 | if (exp.X_op == O_symbol) | |
4321 | exp.X_op = O_secrel; | |
4322 | ||
4323 | emit_expr (&exp, 4); | |
4324 | } | |
4325 | while (*input_line_pointer++ == ','); | |
4326 | ||
4327 | input_line_pointer--; | |
4328 | demand_empty_rest_of_line (); | |
4329 | } | |
4330 | #endif /* TE_PE */ | |
4331 | ||
c19d1205 ZW |
4332 | /* This table describes all the machine specific pseudo-ops the assembler |
4333 | has to support. The fields are: | |
4334 | pseudo-op name without dot | |
4335 | function to call to execute this pseudo-op | |
4336 | Integer arg to pass to the function. */ | |
b99bd4ef | 4337 | |
c19d1205 | 4338 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4339 | { |
c19d1205 ZW |
4340 | /* Never called because '.req' does not start a line. */ |
4341 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4342 | /* Following two are likewise never called. */ |
4343 | { "dn", s_dn, 0 }, | |
4344 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4345 | { "unreq", s_unreq, 0 }, |
4346 | { "bss", s_bss, 0 }, | |
4347 | { "align", s_align, 0 }, | |
4348 | { "arm", s_arm, 0 }, | |
4349 | { "thumb", s_thumb, 0 }, | |
4350 | { "code", s_code, 0 }, | |
4351 | { "force_thumb", s_force_thumb, 0 }, | |
4352 | { "thumb_func", s_thumb_func, 0 }, | |
4353 | { "thumb_set", s_thumb_set, 0 }, | |
4354 | { "even", s_even, 0 }, | |
4355 | { "ltorg", s_ltorg, 0 }, | |
4356 | { "pool", s_ltorg, 0 }, | |
4357 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4358 | { "cpu", s_arm_cpu, 0 }, |
4359 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4360 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4361 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4362 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4363 | #ifdef OBJ_ELF |
c921be7d NC |
4364 | { "word", s_arm_elf_cons, 4 }, |
4365 | { "long", s_arm_elf_cons, 4 }, | |
4366 | { "inst.n", s_arm_elf_inst, 2 }, | |
4367 | { "inst.w", s_arm_elf_inst, 4 }, | |
4368 | { "inst", s_arm_elf_inst, 0 }, | |
4369 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4370 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4371 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4372 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4373 | { "personality", s_arm_unwind_personality, 0 }, | |
4374 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4375 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4376 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4377 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4378 | { "movsp", s_arm_unwind_movsp, 0 }, |
4379 | { "pad", s_arm_unwind_pad, 0 }, | |
4380 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4381 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4382 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4383 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4384 | #else |
4385 | { "word", cons, 4}, | |
f0927246 NC |
4386 | |
4387 | /* These are used for dwarf. */ | |
4388 | {"2byte", cons, 2}, | |
4389 | {"4byte", cons, 4}, | |
4390 | {"8byte", cons, 8}, | |
4391 | /* These are used for dwarf2. */ | |
4392 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4393 | { "loc", dwarf2_directive_loc, 0 }, | |
4394 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4395 | #endif |
4396 | { "extend", float_cons, 'x' }, | |
4397 | { "ldouble", float_cons, 'x' }, | |
4398 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4399 | #ifdef TE_PE |
4400 | {"secrel32", pe_directive_secrel, 0}, | |
4401 | #endif | |
c19d1205 ZW |
4402 | { 0, 0, 0 } |
4403 | }; | |
4404 | \f | |
4405 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4406 | |
c19d1205 ZW |
4407 | /* Generic immediate-value read function for use in insn parsing. |
4408 | STR points to the beginning of the immediate (the leading #); | |
4409 | VAL receives the value; if the value is outside [MIN, MAX] | |
4410 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4411 | optional. */ | |
b99bd4ef | 4412 | |
c19d1205 ZW |
4413 | static int |
4414 | parse_immediate (char **str, int *val, int min, int max, | |
4415 | bfd_boolean prefix_opt) | |
4416 | { | |
4417 | expressionS exp; | |
4418 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4419 | if (exp.X_op != O_constant) | |
b99bd4ef | 4420 | { |
c19d1205 ZW |
4421 | inst.error = _("constant expression required"); |
4422 | return FAIL; | |
4423 | } | |
b99bd4ef | 4424 | |
c19d1205 ZW |
4425 | if (exp.X_add_number < min || exp.X_add_number > max) |
4426 | { | |
4427 | inst.error = _("immediate value out of range"); | |
4428 | return FAIL; | |
4429 | } | |
b99bd4ef | 4430 | |
c19d1205 ZW |
4431 | *val = exp.X_add_number; |
4432 | return SUCCESS; | |
4433 | } | |
b99bd4ef | 4434 | |
5287ad62 | 4435 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4436 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4437 | instructions. Puts the result directly in inst.operands[i]. */ |
4438 | ||
4439 | static int | |
4440 | parse_big_immediate (char **str, int i) | |
4441 | { | |
4442 | expressionS exp; | |
4443 | char *ptr = *str; | |
4444 | ||
4445 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4446 | ||
4447 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4448 | { |
4449 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4450 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4451 | O_constant. We have to be careful not to break compilation for | |
4452 | 32-bit X_add_number, though. */ | |
4453 | if ((exp.X_add_number & ~0xffffffffl) != 0) | |
4454 | { | |
4455 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4456 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4457 | inst.operands[i].regisimm = 1; | |
4458 | } | |
4459 | } | |
5287ad62 | 4460 | else if (exp.X_op == O_big |
95b75c01 | 4461 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) |
5287ad62 JB |
4462 | { |
4463 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4464 | |
5287ad62 JB |
4465 | /* Bignums have their least significant bits in |
4466 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4467 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4468 | gas_assert (parts != 0); |
95b75c01 NC |
4469 | |
4470 | /* Make sure that the number is not too big. | |
4471 | PR 11972: Bignums can now be sign-extended to the | |
4472 | size of a .octa so check that the out of range bits | |
4473 | are all zero or all one. */ | |
4474 | if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) | |
4475 | { | |
4476 | LITTLENUM_TYPE m = -1; | |
4477 | ||
4478 | if (generic_bignum[parts * 2] != 0 | |
4479 | && generic_bignum[parts * 2] != m) | |
4480 | return FAIL; | |
4481 | ||
4482 | for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) | |
4483 | if (generic_bignum[j] != generic_bignum[j-1]) | |
4484 | return FAIL; | |
4485 | } | |
4486 | ||
5287ad62 JB |
4487 | inst.operands[i].imm = 0; |
4488 | for (j = 0; j < parts; j++, idx++) | |
4489 | inst.operands[i].imm |= generic_bignum[idx] | |
4490 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4491 | inst.operands[i].reg = 0; | |
4492 | for (j = 0; j < parts; j++, idx++) | |
4493 | inst.operands[i].reg |= generic_bignum[idx] | |
4494 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4495 | inst.operands[i].regisimm = 1; | |
4496 | } | |
4497 | else | |
4498 | return FAIL; | |
5f4273c7 | 4499 | |
5287ad62 JB |
4500 | *str = ptr; |
4501 | ||
4502 | return SUCCESS; | |
4503 | } | |
4504 | ||
c19d1205 ZW |
4505 | /* Returns the pseudo-register number of an FPA immediate constant, |
4506 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4507 | |
c19d1205 ZW |
4508 | static int |
4509 | parse_fpa_immediate (char ** str) | |
4510 | { | |
4511 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4512 | char * save_in; | |
4513 | expressionS exp; | |
4514 | int i; | |
4515 | int j; | |
b99bd4ef | 4516 | |
c19d1205 ZW |
4517 | /* First try and match exact strings, this is to guarantee |
4518 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4519 | |
c19d1205 ZW |
4520 | for (i = 0; fp_const[i]; i++) |
4521 | { | |
4522 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4523 | { |
c19d1205 | 4524 | char *start = *str; |
b99bd4ef | 4525 | |
c19d1205 ZW |
4526 | *str += strlen (fp_const[i]); |
4527 | if (is_end_of_line[(unsigned char) **str]) | |
4528 | return i + 8; | |
4529 | *str = start; | |
4530 | } | |
4531 | } | |
b99bd4ef | 4532 | |
c19d1205 ZW |
4533 | /* Just because we didn't get a match doesn't mean that the constant |
4534 | isn't valid, just that it is in a format that we don't | |
4535 | automatically recognize. Try parsing it with the standard | |
4536 | expression routines. */ | |
b99bd4ef | 4537 | |
c19d1205 | 4538 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4539 | |
c19d1205 ZW |
4540 | /* Look for a raw floating point number. */ |
4541 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4542 | && is_end_of_line[(unsigned char) *save_in]) | |
4543 | { | |
4544 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4545 | { | |
4546 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4547 | { |
c19d1205 ZW |
4548 | if (words[j] != fp_values[i][j]) |
4549 | break; | |
b99bd4ef NC |
4550 | } |
4551 | ||
c19d1205 | 4552 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4553 | { |
c19d1205 ZW |
4554 | *str = save_in; |
4555 | return i + 8; | |
b99bd4ef NC |
4556 | } |
4557 | } | |
4558 | } | |
b99bd4ef | 4559 | |
c19d1205 ZW |
4560 | /* Try and parse a more complex expression, this will probably fail |
4561 | unless the code uses a floating point prefix (eg "0f"). */ | |
4562 | save_in = input_line_pointer; | |
4563 | input_line_pointer = *str; | |
4564 | if (expression (&exp) == absolute_section | |
4565 | && exp.X_op == O_big | |
4566 | && exp.X_add_number < 0) | |
4567 | { | |
4568 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4569 | Ditto for 15. */ | |
4570 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4571 | { | |
4572 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4573 | { | |
4574 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4575 | { | |
4576 | if (words[j] != fp_values[i][j]) | |
4577 | break; | |
4578 | } | |
b99bd4ef | 4579 | |
c19d1205 ZW |
4580 | if (j == MAX_LITTLENUMS) |
4581 | { | |
4582 | *str = input_line_pointer; | |
4583 | input_line_pointer = save_in; | |
4584 | return i + 8; | |
4585 | } | |
4586 | } | |
4587 | } | |
b99bd4ef NC |
4588 | } |
4589 | ||
c19d1205 ZW |
4590 | *str = input_line_pointer; |
4591 | input_line_pointer = save_in; | |
4592 | inst.error = _("invalid FPA immediate expression"); | |
4593 | return FAIL; | |
b99bd4ef NC |
4594 | } |
4595 | ||
136da414 JB |
4596 | /* Returns 1 if a number has "quarter-precision" float format |
4597 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4598 | ||
4599 | static int | |
4600 | is_quarter_float (unsigned imm) | |
4601 | { | |
4602 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4603 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4604 | } | |
4605 | ||
4606 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4607 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4608 | The zero and minus-zero cases need special handling, since they can't be |
4609 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4610 | loaded as integer constants. */ | |
136da414 JB |
4611 | |
4612 | static unsigned | |
4613 | parse_qfloat_immediate (char **ccp, int *immed) | |
4614 | { | |
4615 | char *str = *ccp; | |
c96612cc | 4616 | char *fpnum; |
136da414 | 4617 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4618 | int found_fpchar = 0; |
5f4273c7 | 4619 | |
136da414 | 4620 | skip_past_char (&str, '#'); |
5f4273c7 | 4621 | |
c96612cc JB |
4622 | /* We must not accidentally parse an integer as a floating-point number. Make |
4623 | sure that the value we parse is not an integer by checking for special | |
4624 | characters '.' or 'e'. | |
4625 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4626 | information isn't in a very usable state at parse time. */ | |
4627 | fpnum = str; | |
4628 | skip_whitespace (fpnum); | |
4629 | ||
4630 | if (strncmp (fpnum, "0x", 2) == 0) | |
4631 | return FAIL; | |
4632 | else | |
4633 | { | |
4634 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4635 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4636 | { | |
4637 | found_fpchar = 1; | |
4638 | break; | |
4639 | } | |
4640 | ||
4641 | if (!found_fpchar) | |
4642 | return FAIL; | |
4643 | } | |
5f4273c7 | 4644 | |
136da414 JB |
4645 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4646 | { | |
4647 | unsigned fpword = 0; | |
4648 | int i; | |
5f4273c7 | 4649 | |
136da414 JB |
4650 | /* Our FP word must be 32 bits (single-precision FP). */ |
4651 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4652 | { | |
4653 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4654 | fpword |= words[i]; | |
4655 | } | |
5f4273c7 | 4656 | |
c96612cc | 4657 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4658 | *immed = fpword; |
4659 | else | |
4660 | return FAIL; | |
4661 | ||
4662 | *ccp = str; | |
5f4273c7 | 4663 | |
136da414 JB |
4664 | return SUCCESS; |
4665 | } | |
5f4273c7 | 4666 | |
136da414 JB |
4667 | return FAIL; |
4668 | } | |
4669 | ||
c19d1205 ZW |
4670 | /* Shift operands. */ |
4671 | enum shift_kind | |
b99bd4ef | 4672 | { |
c19d1205 ZW |
4673 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4674 | }; | |
b99bd4ef | 4675 | |
c19d1205 ZW |
4676 | struct asm_shift_name |
4677 | { | |
4678 | const char *name; | |
4679 | enum shift_kind kind; | |
4680 | }; | |
b99bd4ef | 4681 | |
c19d1205 ZW |
4682 | /* Third argument to parse_shift. */ |
4683 | enum parse_shift_mode | |
4684 | { | |
4685 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4686 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4687 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4688 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4689 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4690 | }; | |
b99bd4ef | 4691 | |
c19d1205 ZW |
4692 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4693 | This has three forms: | |
b99bd4ef | 4694 | |
c19d1205 ZW |
4695 | (LSL|LSR|ASL|ASR|ROR) Rs |
4696 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4697 | RRX | |
b99bd4ef | 4698 | |
c19d1205 ZW |
4699 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4700 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4701 | |
c19d1205 ZW |
4702 | static int |
4703 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4704 | { |
c19d1205 ZW |
4705 | const struct asm_shift_name *shift_name; |
4706 | enum shift_kind shift; | |
4707 | char *s = *str; | |
4708 | char *p = s; | |
4709 | int reg; | |
b99bd4ef | 4710 | |
c19d1205 ZW |
4711 | for (p = *str; ISALPHA (*p); p++) |
4712 | ; | |
b99bd4ef | 4713 | |
c19d1205 | 4714 | if (p == *str) |
b99bd4ef | 4715 | { |
c19d1205 ZW |
4716 | inst.error = _("shift expression expected"); |
4717 | return FAIL; | |
b99bd4ef NC |
4718 | } |
4719 | ||
21d799b5 NC |
4720 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4721 | p - *str); | |
c19d1205 ZW |
4722 | |
4723 | if (shift_name == NULL) | |
b99bd4ef | 4724 | { |
c19d1205 ZW |
4725 | inst.error = _("shift expression expected"); |
4726 | return FAIL; | |
b99bd4ef NC |
4727 | } |
4728 | ||
c19d1205 | 4729 | shift = shift_name->kind; |
b99bd4ef | 4730 | |
c19d1205 ZW |
4731 | switch (mode) |
4732 | { | |
4733 | case NO_SHIFT_RESTRICT: | |
4734 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4735 | |
c19d1205 ZW |
4736 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4737 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4738 | { | |
4739 | inst.error = _("'LSL' or 'ASR' required"); | |
4740 | return FAIL; | |
4741 | } | |
4742 | break; | |
b99bd4ef | 4743 | |
c19d1205 ZW |
4744 | case SHIFT_LSL_IMMEDIATE: |
4745 | if (shift != SHIFT_LSL) | |
4746 | { | |
4747 | inst.error = _("'LSL' required"); | |
4748 | return FAIL; | |
4749 | } | |
4750 | break; | |
b99bd4ef | 4751 | |
c19d1205 ZW |
4752 | case SHIFT_ASR_IMMEDIATE: |
4753 | if (shift != SHIFT_ASR) | |
4754 | { | |
4755 | inst.error = _("'ASR' required"); | |
4756 | return FAIL; | |
4757 | } | |
4758 | break; | |
b99bd4ef | 4759 | |
c19d1205 ZW |
4760 | default: abort (); |
4761 | } | |
b99bd4ef | 4762 | |
c19d1205 ZW |
4763 | if (shift != SHIFT_RRX) |
4764 | { | |
4765 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4766 | skip_whitespace (p); | |
b99bd4ef | 4767 | |
c19d1205 | 4768 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4769 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4770 | { |
4771 | inst.operands[i].imm = reg; | |
4772 | inst.operands[i].immisreg = 1; | |
4773 | } | |
4774 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4775 | return FAIL; | |
4776 | } | |
4777 | inst.operands[i].shift_kind = shift; | |
4778 | inst.operands[i].shifted = 1; | |
4779 | *str = p; | |
4780 | return SUCCESS; | |
b99bd4ef NC |
4781 | } |
4782 | ||
c19d1205 | 4783 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4784 | |
c19d1205 ZW |
4785 | #<immediate> |
4786 | #<immediate>, <rotate> | |
4787 | <Rm> | |
4788 | <Rm>, <shift> | |
b99bd4ef | 4789 | |
c19d1205 ZW |
4790 | where <shift> is defined by parse_shift above, and <rotate> is a |
4791 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4792 | is deferred to md_apply_fix. */ |
b99bd4ef | 4793 | |
c19d1205 ZW |
4794 | static int |
4795 | parse_shifter_operand (char **str, int i) | |
4796 | { | |
4797 | int value; | |
91d6fa6a | 4798 | expressionS exp; |
b99bd4ef | 4799 | |
dcbf9037 | 4800 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4801 | { |
4802 | inst.operands[i].reg = value; | |
4803 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4804 | |
c19d1205 ZW |
4805 | /* parse_shift will override this if appropriate */ |
4806 | inst.reloc.exp.X_op = O_constant; | |
4807 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4808 | |
c19d1205 ZW |
4809 | if (skip_past_comma (str) == FAIL) |
4810 | return SUCCESS; | |
b99bd4ef | 4811 | |
c19d1205 ZW |
4812 | /* Shift operation on register. */ |
4813 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4814 | } |
4815 | ||
c19d1205 ZW |
4816 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4817 | return FAIL; | |
b99bd4ef | 4818 | |
c19d1205 | 4819 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4820 | { |
c19d1205 | 4821 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4822 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4823 | return FAIL; |
b99bd4ef | 4824 | |
91d6fa6a | 4825 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4826 | { |
4827 | inst.error = _("constant expression expected"); | |
4828 | return FAIL; | |
4829 | } | |
b99bd4ef | 4830 | |
91d6fa6a | 4831 | value = exp.X_add_number; |
c19d1205 ZW |
4832 | if (value < 0 || value > 30 || value % 2 != 0) |
4833 | { | |
4834 | inst.error = _("invalid rotation"); | |
4835 | return FAIL; | |
4836 | } | |
4837 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4838 | { | |
4839 | inst.error = _("invalid constant"); | |
4840 | return FAIL; | |
4841 | } | |
09d92015 | 4842 | |
55cf6793 | 4843 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4844 | inst.reloc.exp.X_add_number |
4845 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4846 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4847 | } |
4848 | ||
c19d1205 ZW |
4849 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4850 | inst.reloc.pc_rel = 0; | |
4851 | return SUCCESS; | |
09d92015 MM |
4852 | } |
4853 | ||
4962c51a MS |
4854 | /* Group relocation information. Each entry in the table contains the |
4855 | textual name of the relocation as may appear in assembler source | |
4856 | and must end with a colon. | |
4857 | Along with this textual name are the relocation codes to be used if | |
4858 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4859 | an LDR, an LDRS, or an LDC. */ | |
4860 | ||
4861 | struct group_reloc_table_entry | |
4862 | { | |
4863 | const char *name; | |
4864 | int alu_code; | |
4865 | int ldr_code; | |
4866 | int ldrs_code; | |
4867 | int ldc_code; | |
4868 | }; | |
4869 | ||
4870 | typedef enum | |
4871 | { | |
4872 | /* Varieties of non-ALU group relocation. */ | |
4873 | ||
4874 | GROUP_LDR, | |
4875 | GROUP_LDRS, | |
4876 | GROUP_LDC | |
4877 | } group_reloc_type; | |
4878 | ||
4879 | static struct group_reloc_table_entry group_reloc_table[] = | |
4880 | { /* Program counter relative: */ | |
4881 | { "pc_g0_nc", | |
4882 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4883 | 0, /* LDR */ | |
4884 | 0, /* LDRS */ | |
4885 | 0 }, /* LDC */ | |
4886 | { "pc_g0", | |
4887 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4888 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4889 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4890 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4891 | { "pc_g1_nc", | |
4892 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4893 | 0, /* LDR */ | |
4894 | 0, /* LDRS */ | |
4895 | 0 }, /* LDC */ | |
4896 | { "pc_g1", | |
4897 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4898 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4899 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4900 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4901 | { "pc_g2", | |
4902 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4903 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4904 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4905 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4906 | /* Section base relative */ | |
4907 | { "sb_g0_nc", | |
4908 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4909 | 0, /* LDR */ | |
4910 | 0, /* LDRS */ | |
4911 | 0 }, /* LDC */ | |
4912 | { "sb_g0", | |
4913 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4914 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4915 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4916 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4917 | { "sb_g1_nc", | |
4918 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4919 | 0, /* LDR */ | |
4920 | 0, /* LDRS */ | |
4921 | 0 }, /* LDC */ | |
4922 | { "sb_g1", | |
4923 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4924 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4925 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4926 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4927 | { "sb_g2", | |
4928 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4929 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4930 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4931 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4932 | ||
4933 | /* Given the address of a pointer pointing to the textual name of a group | |
4934 | relocation as may appear in assembler source, attempt to find its details | |
4935 | in group_reloc_table. The pointer will be updated to the character after | |
4936 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4937 | otherwise. On success, *entry will be updated to point at the relevant | |
4938 | group_reloc_table entry. */ | |
4939 | ||
4940 | static int | |
4941 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4942 | { | |
4943 | unsigned int i; | |
4944 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4945 | { | |
4946 | int length = strlen (group_reloc_table[i].name); | |
4947 | ||
5f4273c7 NC |
4948 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4949 | && (*str)[length] == ':') | |
4962c51a MS |
4950 | { |
4951 | *out = &group_reloc_table[i]; | |
4952 | *str += (length + 1); | |
4953 | return SUCCESS; | |
4954 | } | |
4955 | } | |
4956 | ||
4957 | return FAIL; | |
4958 | } | |
4959 | ||
4960 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4961 | (as for parse_shifter_operand) where group relocations are allowed: | |
4962 | ||
4963 | #<immediate> | |
4964 | #<immediate>, <rotate> | |
4965 | #:<group_reloc>:<expression> | |
4966 | <Rm> | |
4967 | <Rm>, <shift> | |
4968 | ||
4969 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4970 | The hashes are optional. | |
4971 | ||
4972 | Everything else is as for parse_shifter_operand. */ | |
4973 | ||
4974 | static parse_operand_result | |
4975 | parse_shifter_operand_group_reloc (char **str, int i) | |
4976 | { | |
4977 | /* Determine if we have the sequence of characters #: or just : | |
4978 | coming next. If we do, then we check for a group relocation. | |
4979 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4980 | ||
4981 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4982 | || (*str)[0] == ':') | |
4983 | { | |
4984 | struct group_reloc_table_entry *entry; | |
4985 | ||
4986 | if ((*str)[0] == '#') | |
4987 | (*str) += 2; | |
4988 | else | |
4989 | (*str)++; | |
4990 | ||
4991 | /* Try to parse a group relocation. Anything else is an error. */ | |
4992 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
4993 | { | |
4994 | inst.error = _("unknown group relocation"); | |
4995 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
4996 | } | |
4997 | ||
4998 | /* We now have the group relocation table entry corresponding to | |
4999 | the name in the assembler source. Next, we parse the expression. */ | |
5000 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
5001 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5002 | ||
5003 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5004 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5005 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5006 | |
5007 | return PARSE_OPERAND_SUCCESS; | |
5008 | } | |
5009 | else | |
5010 | return parse_shifter_operand (str, i) == SUCCESS | |
5011 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
5012 | ||
5013 | /* Never reached. */ | |
5014 | } | |
5015 | ||
8e560766 MGD |
5016 | /* Parse a Neon alignment expression. Information is written to |
5017 | inst.operands[i]. We assume the initial ':' has been skipped. | |
5018 | ||
5019 | align .imm = align << 8, .immisalign=1, .preind=0 */ | |
5020 | static parse_operand_result | |
5021 | parse_neon_alignment (char **str, int i) | |
5022 | { | |
5023 | char *p = *str; | |
5024 | expressionS exp; | |
5025 | ||
5026 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5027 | ||
5028 | if (exp.X_op != O_constant) | |
5029 | { | |
5030 | inst.error = _("alignment must be constant"); | |
5031 | return PARSE_OPERAND_FAIL; | |
5032 | } | |
5033 | ||
5034 | inst.operands[i].imm = exp.X_add_number << 8; | |
5035 | inst.operands[i].immisalign = 1; | |
5036 | /* Alignments are not pre-indexes. */ | |
5037 | inst.operands[i].preind = 0; | |
5038 | ||
5039 | *str = p; | |
5040 | return PARSE_OPERAND_SUCCESS; | |
5041 | } | |
5042 | ||
c19d1205 ZW |
5043 | /* Parse all forms of an ARM address expression. Information is written |
5044 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5045 | |
c19d1205 | 5046 | Preindexed addressing (.preind=1): |
09d92015 | 5047 | |
c19d1205 ZW |
5048 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5049 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5050 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5051 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5052 | |
c19d1205 | 5053 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5054 | |
c19d1205 | 5055 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5056 | |
c19d1205 ZW |
5057 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5058 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5059 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5060 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5061 | |
c19d1205 | 5062 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5063 | |
c19d1205 | 5064 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5065 | |
c19d1205 | 5066 | Other: |
09d92015 | 5067 | |
c19d1205 ZW |
5068 | [Rn]{!} shorthand for [Rn,#0]{!} |
5069 | =immediate .isreg=0 .reloc.exp=immediate | |
5070 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5071 | |
c19d1205 ZW |
5072 | It is the caller's responsibility to check for addressing modes not |
5073 | supported by the instruction, and to set inst.reloc.type. */ | |
5074 | ||
4962c51a MS |
5075 | static parse_operand_result |
5076 | parse_address_main (char **str, int i, int group_relocations, | |
5077 | group_reloc_type group_type) | |
09d92015 | 5078 | { |
c19d1205 ZW |
5079 | char *p = *str; |
5080 | int reg; | |
09d92015 | 5081 | |
c19d1205 | 5082 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5083 | { |
c19d1205 ZW |
5084 | if (skip_past_char (&p, '=') == FAIL) |
5085 | { | |
974da60d | 5086 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5087 | inst.reloc.pc_rel = 1; |
5088 | inst.operands[i].reg = REG_PC; | |
5089 | inst.operands[i].isreg = 1; | |
5090 | inst.operands[i].preind = 1; | |
5091 | } | |
974da60d | 5092 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5093 | |
c19d1205 | 5094 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5095 | return PARSE_OPERAND_FAIL; |
09d92015 | 5096 | |
c19d1205 | 5097 | *str = p; |
4962c51a | 5098 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5099 | } |
5100 | ||
dcbf9037 | 5101 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5102 | { |
c19d1205 | 5103 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5104 | return PARSE_OPERAND_FAIL; |
09d92015 | 5105 | } |
c19d1205 ZW |
5106 | inst.operands[i].reg = reg; |
5107 | inst.operands[i].isreg = 1; | |
09d92015 | 5108 | |
c19d1205 | 5109 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5110 | { |
c19d1205 | 5111 | inst.operands[i].preind = 1; |
09d92015 | 5112 | |
c19d1205 ZW |
5113 | if (*p == '+') p++; |
5114 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5115 | ||
dcbf9037 | 5116 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5117 | { |
c19d1205 ZW |
5118 | inst.operands[i].imm = reg; |
5119 | inst.operands[i].immisreg = 1; | |
5120 | ||
5121 | if (skip_past_comma (&p) == SUCCESS) | |
5122 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5123 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5124 | } |
5287ad62 | 5125 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5126 | { |
5127 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5128 | code before we get to see it here. This may be subject to | |
5129 | change. */ | |
5130 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5131 | ||
5132 | if (result != PARSE_OPERAND_SUCCESS) | |
5133 | return result; | |
5134 | } | |
c19d1205 ZW |
5135 | else |
5136 | { | |
5137 | if (inst.operands[i].negative) | |
5138 | { | |
5139 | inst.operands[i].negative = 0; | |
5140 | p--; | |
5141 | } | |
4962c51a | 5142 | |
5f4273c7 NC |
5143 | if (group_relocations |
5144 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5145 | { |
5146 | struct group_reloc_table_entry *entry; | |
5147 | ||
5148 | /* Skip over the #: or : sequence. */ | |
5149 | if (*p == '#') | |
5150 | p += 2; | |
5151 | else | |
5152 | p++; | |
5153 | ||
5154 | /* Try to parse a group relocation. Anything else is an | |
5155 | error. */ | |
5156 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5157 | { | |
5158 | inst.error = _("unknown group relocation"); | |
5159 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5160 | } | |
5161 | ||
5162 | /* We now have the group relocation table entry corresponding to | |
5163 | the name in the assembler source. Next, we parse the | |
5164 | expression. */ | |
5165 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5166 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5167 | ||
5168 | /* Record the relocation type. */ | |
5169 | switch (group_type) | |
5170 | { | |
5171 | case GROUP_LDR: | |
21d799b5 | 5172 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5173 | break; |
5174 | ||
5175 | case GROUP_LDRS: | |
21d799b5 | 5176 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5177 | break; |
5178 | ||
5179 | case GROUP_LDC: | |
21d799b5 | 5180 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5181 | break; |
5182 | ||
5183 | default: | |
9c2799c2 | 5184 | gas_assert (0); |
4962c51a MS |
5185 | } |
5186 | ||
5187 | if (inst.reloc.type == 0) | |
5188 | { | |
5189 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5190 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5191 | } | |
5192 | } | |
5193 | else | |
5194 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5195 | return PARSE_OPERAND_FAIL; | |
09d92015 MM |
5196 | } |
5197 | } | |
8e560766 MGD |
5198 | else if (skip_past_char (&p, ':') == SUCCESS) |
5199 | { | |
5200 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5201 | before we get to see it here. This may be subject to change. */ | |
5202 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5203 | ||
5204 | if (result != PARSE_OPERAND_SUCCESS) | |
5205 | return result; | |
5206 | } | |
09d92015 | 5207 | |
c19d1205 | 5208 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5209 | { |
c19d1205 | 5210 | inst.error = _("']' expected"); |
4962c51a | 5211 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5212 | } |
5213 | ||
c19d1205 ZW |
5214 | if (skip_past_char (&p, '!') == SUCCESS) |
5215 | inst.operands[i].writeback = 1; | |
09d92015 | 5216 | |
c19d1205 | 5217 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5218 | { |
c19d1205 ZW |
5219 | if (skip_past_char (&p, '{') == SUCCESS) |
5220 | { | |
5221 | /* [Rn], {expr} - unindexed, with option */ | |
5222 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5223 | 0, 255, TRUE) == FAIL) |
4962c51a | 5224 | return PARSE_OPERAND_FAIL; |
09d92015 | 5225 | |
c19d1205 ZW |
5226 | if (skip_past_char (&p, '}') == FAIL) |
5227 | { | |
5228 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5229 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5230 | } |
5231 | if (inst.operands[i].preind) | |
5232 | { | |
5233 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5234 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5235 | } |
5236 | *str = p; | |
4962c51a | 5237 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5238 | } |
c19d1205 ZW |
5239 | else |
5240 | { | |
5241 | inst.operands[i].postind = 1; | |
5242 | inst.operands[i].writeback = 1; | |
09d92015 | 5243 | |
c19d1205 ZW |
5244 | if (inst.operands[i].preind) |
5245 | { | |
5246 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5247 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5248 | } |
09d92015 | 5249 | |
c19d1205 ZW |
5250 | if (*p == '+') p++; |
5251 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5252 | |
dcbf9037 | 5253 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5254 | { |
5287ad62 JB |
5255 | /* We might be using the immediate for alignment already. If we |
5256 | are, OR the register number into the low-order bits. */ | |
5257 | if (inst.operands[i].immisalign) | |
5258 | inst.operands[i].imm |= reg; | |
5259 | else | |
5260 | inst.operands[i].imm = reg; | |
c19d1205 | 5261 | inst.operands[i].immisreg = 1; |
a737bd4d | 5262 | |
c19d1205 ZW |
5263 | if (skip_past_comma (&p) == SUCCESS) |
5264 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5265 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5266 | } |
5267 | else | |
5268 | { | |
5269 | if (inst.operands[i].negative) | |
5270 | { | |
5271 | inst.operands[i].negative = 0; | |
5272 | p--; | |
5273 | } | |
5274 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5275 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5276 | } |
5277 | } | |
a737bd4d NC |
5278 | } |
5279 | ||
c19d1205 ZW |
5280 | /* If at this point neither .preind nor .postind is set, we have a |
5281 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5282 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5283 | { | |
5284 | inst.operands[i].preind = 1; | |
5285 | inst.reloc.exp.X_op = O_constant; | |
5286 | inst.reloc.exp.X_add_number = 0; | |
5287 | } | |
5288 | *str = p; | |
4962c51a MS |
5289 | return PARSE_OPERAND_SUCCESS; |
5290 | } | |
5291 | ||
5292 | static int | |
5293 | parse_address (char **str, int i) | |
5294 | { | |
21d799b5 | 5295 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5296 | ? SUCCESS : FAIL; |
5297 | } | |
5298 | ||
5299 | static parse_operand_result | |
5300 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5301 | { | |
5302 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5303 | } |
5304 | ||
b6895b4f PB |
5305 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5306 | static int | |
5307 | parse_half (char **str) | |
5308 | { | |
5309 | char * p; | |
5f4273c7 | 5310 | |
b6895b4f PB |
5311 | p = *str; |
5312 | skip_past_char (&p, '#'); | |
5f4273c7 | 5313 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5314 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5315 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5316 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5317 | ||
5318 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5319 | { | |
5320 | p += 9; | |
5f4273c7 | 5321 | skip_whitespace (p); |
b6895b4f PB |
5322 | } |
5323 | ||
5324 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5325 | return FAIL; | |
5326 | ||
5327 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5328 | { | |
5329 | if (inst.reloc.exp.X_op != O_constant) | |
5330 | { | |
5331 | inst.error = _("constant expression expected"); | |
5332 | return FAIL; | |
5333 | } | |
5334 | if (inst.reloc.exp.X_add_number < 0 | |
5335 | || inst.reloc.exp.X_add_number > 0xffff) | |
5336 | { | |
5337 | inst.error = _("immediate value out of range"); | |
5338 | return FAIL; | |
5339 | } | |
5340 | } | |
5341 | *str = p; | |
5342 | return SUCCESS; | |
5343 | } | |
5344 | ||
c19d1205 | 5345 | /* Miscellaneous. */ |
a737bd4d | 5346 | |
c19d1205 ZW |
5347 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5348 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5349 | static int | |
d2cd1205 | 5350 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5351 | { |
c19d1205 ZW |
5352 | char *p; |
5353 | unsigned long psr_field; | |
62b3e311 PB |
5354 | const struct asm_psr *psr; |
5355 | char *start; | |
d2cd1205 | 5356 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5357 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5358 | |
c19d1205 ZW |
5359 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5360 | feature for ease of use and backwards compatibility. */ | |
5361 | p = *str; | |
62b3e311 | 5362 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5363 | { |
5364 | if (m_profile) | |
5365 | goto unsupported_psr; | |
5366 | ||
5367 | psr_field = SPSR_BIT; | |
5368 | } | |
5369 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5370 | { | |
5371 | if (m_profile) | |
5372 | goto unsupported_psr; | |
5373 | ||
5374 | psr_field = 0; | |
5375 | } | |
5376 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5377 | { | |
5378 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5379 | and ARMv7-R architecture CPUs. */ | |
5380 | is_apsr = TRUE; | |
5381 | psr_field = 0; | |
5382 | } | |
5383 | else if (m_profile) | |
62b3e311 PB |
5384 | { |
5385 | start = p; | |
5386 | do | |
5387 | p++; | |
5388 | while (ISALNUM (*p) || *p == '_'); | |
5389 | ||
d2cd1205 JB |
5390 | if (strncasecmp (start, "iapsr", 5) == 0 |
5391 | || strncasecmp (start, "eapsr", 5) == 0 | |
5392 | || strncasecmp (start, "xpsr", 4) == 0 | |
5393 | || strncasecmp (start, "psr", 3) == 0) | |
5394 | p = start + strcspn (start, "rR") + 1; | |
5395 | ||
21d799b5 NC |
5396 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5397 | p - start); | |
d2cd1205 | 5398 | |
62b3e311 PB |
5399 | if (!psr) |
5400 | return FAIL; | |
09d92015 | 5401 | |
d2cd1205 JB |
5402 | /* If APSR is being written, a bitfield may be specified. Note that |
5403 | APSR itself is handled above. */ | |
5404 | if (psr->field <= 3) | |
5405 | { | |
5406 | psr_field = psr->field; | |
5407 | is_apsr = TRUE; | |
5408 | goto check_suffix; | |
5409 | } | |
5410 | ||
62b3e311 | 5411 | *str = p; |
d2cd1205 JB |
5412 | /* M-profile MSR instructions have the mask field set to "10", except |
5413 | *PSR variants which modify APSR, which may use a different mask (and | |
5414 | have been handled already). Do that by setting the PSR_f field | |
5415 | here. */ | |
5416 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5417 | } |
d2cd1205 JB |
5418 | else |
5419 | goto unsupported_psr; | |
09d92015 | 5420 | |
62b3e311 | 5421 | p += 4; |
d2cd1205 | 5422 | check_suffix: |
c19d1205 ZW |
5423 | if (*p == '_') |
5424 | { | |
5425 | /* A suffix follows. */ | |
c19d1205 ZW |
5426 | p++; |
5427 | start = p; | |
a737bd4d | 5428 | |
c19d1205 ZW |
5429 | do |
5430 | p++; | |
5431 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5432 | |
d2cd1205 JB |
5433 | if (is_apsr) |
5434 | { | |
5435 | /* APSR uses a notation for bits, rather than fields. */ | |
5436 | unsigned int nzcvq_bits = 0; | |
5437 | unsigned int g_bit = 0; | |
5438 | char *bit; | |
5439 | ||
5440 | for (bit = start; bit != p; bit++) | |
5441 | { | |
5442 | switch (TOLOWER (*bit)) | |
5443 | { | |
5444 | case 'n': | |
5445 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5446 | break; | |
5447 | ||
5448 | case 'z': | |
5449 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5450 | break; | |
5451 | ||
5452 | case 'c': | |
5453 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5454 | break; | |
5455 | ||
5456 | case 'v': | |
5457 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5458 | break; | |
5459 | ||
5460 | case 'q': | |
5461 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5462 | break; | |
5463 | ||
5464 | case 'g': | |
5465 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5466 | break; | |
5467 | ||
5468 | default: | |
5469 | inst.error = _("unexpected bit specified after APSR"); | |
5470 | return FAIL; | |
5471 | } | |
5472 | } | |
5473 | ||
5474 | if (nzcvq_bits == 0x1f) | |
5475 | psr_field |= PSR_f; | |
5476 | ||
5477 | if (g_bit == 0x1) | |
5478 | { | |
5479 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
5480 | { | |
5481 | inst.error = _("selected processor does not " | |
5482 | "support DSP extension"); | |
5483 | return FAIL; | |
5484 | } | |
5485 | ||
5486 | psr_field |= PSR_s; | |
5487 | } | |
5488 | ||
5489 | if ((nzcvq_bits & 0x20) != 0 | |
5490 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5491 | || (g_bit & 0x2) != 0) | |
5492 | { | |
5493 | inst.error = _("bad bitmask specified after APSR"); | |
5494 | return FAIL; | |
5495 | } | |
5496 | } | |
5497 | else | |
5498 | { | |
5499 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, | |
5500 | p - start); | |
5501 | if (!psr) | |
5502 | goto error; | |
a737bd4d | 5503 | |
d2cd1205 JB |
5504 | psr_field |= psr->field; |
5505 | } | |
a737bd4d | 5506 | } |
c19d1205 | 5507 | else |
a737bd4d | 5508 | { |
c19d1205 ZW |
5509 | if (ISALNUM (*p)) |
5510 | goto error; /* Garbage after "[CS]PSR". */ | |
5511 | ||
d2cd1205 JB |
5512 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
5513 | is deprecated, but allow it anyway. */ | |
5514 | if (is_apsr && lhs) | |
5515 | { | |
5516 | psr_field |= PSR_f; | |
5517 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5518 | "deprecated")); | |
5519 | } | |
5520 | else if (!m_profile) | |
5521 | /* These bits are never right for M-profile devices: don't set them | |
5522 | (only code paths which read/write APSR reach here). */ | |
5523 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5524 | } |
c19d1205 ZW |
5525 | *str = p; |
5526 | return psr_field; | |
a737bd4d | 5527 | |
d2cd1205 JB |
5528 | unsupported_psr: |
5529 | inst.error = _("selected processor does not support requested special " | |
5530 | "purpose register"); | |
5531 | return FAIL; | |
5532 | ||
c19d1205 ZW |
5533 | error: |
5534 | inst.error = _("flag for {c}psr instruction expected"); | |
5535 | return FAIL; | |
a737bd4d NC |
5536 | } |
5537 | ||
c19d1205 ZW |
5538 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5539 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5540 | |
c19d1205 ZW |
5541 | static int |
5542 | parse_cps_flags (char **str) | |
a737bd4d | 5543 | { |
c19d1205 ZW |
5544 | int val = 0; |
5545 | int saw_a_flag = 0; | |
5546 | char *s = *str; | |
a737bd4d | 5547 | |
c19d1205 ZW |
5548 | for (;;) |
5549 | switch (*s++) | |
5550 | { | |
5551 | case '\0': case ',': | |
5552 | goto done; | |
a737bd4d | 5553 | |
c19d1205 ZW |
5554 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5555 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5556 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5557 | |
c19d1205 ZW |
5558 | default: |
5559 | inst.error = _("unrecognized CPS flag"); | |
5560 | return FAIL; | |
5561 | } | |
a737bd4d | 5562 | |
c19d1205 ZW |
5563 | done: |
5564 | if (saw_a_flag == 0) | |
a737bd4d | 5565 | { |
c19d1205 ZW |
5566 | inst.error = _("missing CPS flags"); |
5567 | return FAIL; | |
a737bd4d | 5568 | } |
a737bd4d | 5569 | |
c19d1205 ZW |
5570 | *str = s - 1; |
5571 | return val; | |
a737bd4d NC |
5572 | } |
5573 | ||
c19d1205 ZW |
5574 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5575 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5576 | |
5577 | static int | |
c19d1205 | 5578 | parse_endian_specifier (char **str) |
a737bd4d | 5579 | { |
c19d1205 ZW |
5580 | int little_endian; |
5581 | char *s = *str; | |
a737bd4d | 5582 | |
c19d1205 ZW |
5583 | if (strncasecmp (s, "BE", 2)) |
5584 | little_endian = 0; | |
5585 | else if (strncasecmp (s, "LE", 2)) | |
5586 | little_endian = 1; | |
5587 | else | |
a737bd4d | 5588 | { |
c19d1205 | 5589 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5590 | return FAIL; |
5591 | } | |
5592 | ||
c19d1205 | 5593 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5594 | { |
c19d1205 | 5595 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5596 | return FAIL; |
5597 | } | |
5598 | ||
c19d1205 ZW |
5599 | *str = s + 2; |
5600 | return little_endian; | |
5601 | } | |
a737bd4d | 5602 | |
c19d1205 ZW |
5603 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5604 | value suitable for poking into the rotate field of an sxt or sxta | |
5605 | instruction, or FAIL on error. */ | |
5606 | ||
5607 | static int | |
5608 | parse_ror (char **str) | |
5609 | { | |
5610 | int rot; | |
5611 | char *s = *str; | |
5612 | ||
5613 | if (strncasecmp (s, "ROR", 3) == 0) | |
5614 | s += 3; | |
5615 | else | |
a737bd4d | 5616 | { |
c19d1205 | 5617 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5618 | return FAIL; |
5619 | } | |
c19d1205 ZW |
5620 | |
5621 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5622 | return FAIL; | |
5623 | ||
5624 | switch (rot) | |
a737bd4d | 5625 | { |
c19d1205 ZW |
5626 | case 0: *str = s; return 0x0; |
5627 | case 8: *str = s; return 0x1; | |
5628 | case 16: *str = s; return 0x2; | |
5629 | case 24: *str = s; return 0x3; | |
5630 | ||
5631 | default: | |
5632 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5633 | return FAIL; |
5634 | } | |
c19d1205 | 5635 | } |
a737bd4d | 5636 | |
c19d1205 ZW |
5637 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5638 | range 0 .. 14, or FAIL. */ | |
5639 | static int | |
5640 | parse_cond (char **str) | |
5641 | { | |
c462b453 | 5642 | char *q; |
c19d1205 | 5643 | const struct asm_cond *c; |
c462b453 PB |
5644 | int n; |
5645 | /* Condition codes are always 2 characters, so matching up to | |
5646 | 3 characters is sufficient. */ | |
5647 | char cond[3]; | |
a737bd4d | 5648 | |
c462b453 PB |
5649 | q = *str; |
5650 | n = 0; | |
5651 | while (ISALPHA (*q) && n < 3) | |
5652 | { | |
e07e6e58 | 5653 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5654 | q++; |
5655 | n++; | |
5656 | } | |
a737bd4d | 5657 | |
21d799b5 | 5658 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5659 | if (!c) |
a737bd4d | 5660 | { |
c19d1205 | 5661 | inst.error = _("condition required"); |
a737bd4d NC |
5662 | return FAIL; |
5663 | } | |
5664 | ||
c19d1205 ZW |
5665 | *str = q; |
5666 | return c->value; | |
5667 | } | |
5668 | ||
62b3e311 PB |
5669 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5670 | option, or FAIL. */ | |
5671 | static int | |
5672 | parse_barrier (char **str) | |
5673 | { | |
5674 | char *p, *q; | |
5675 | const struct asm_barrier_opt *o; | |
5676 | ||
5677 | p = q = *str; | |
5678 | while (ISALPHA (*q)) | |
5679 | q++; | |
5680 | ||
21d799b5 NC |
5681 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5682 | q - p); | |
62b3e311 PB |
5683 | if (!o) |
5684 | return FAIL; | |
5685 | ||
5686 | *str = q; | |
5687 | return o->value; | |
5688 | } | |
5689 | ||
92e90b6e PB |
5690 | /* Parse the operands of a table branch instruction. Similar to a memory |
5691 | operand. */ | |
5692 | static int | |
5693 | parse_tb (char **str) | |
5694 | { | |
5695 | char * p = *str; | |
5696 | int reg; | |
5697 | ||
5698 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5699 | { |
5700 | inst.error = _("'[' expected"); | |
5701 | return FAIL; | |
5702 | } | |
92e90b6e | 5703 | |
dcbf9037 | 5704 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5705 | { |
5706 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5707 | return FAIL; | |
5708 | } | |
5709 | inst.operands[0].reg = reg; | |
5710 | ||
5711 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5712 | { |
5713 | inst.error = _("',' expected"); | |
5714 | return FAIL; | |
5715 | } | |
5f4273c7 | 5716 | |
dcbf9037 | 5717 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5718 | { |
5719 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5720 | return FAIL; | |
5721 | } | |
5722 | inst.operands[0].imm = reg; | |
5723 | ||
5724 | if (skip_past_comma (&p) == SUCCESS) | |
5725 | { | |
5726 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5727 | return FAIL; | |
5728 | if (inst.reloc.exp.X_add_number != 1) | |
5729 | { | |
5730 | inst.error = _("invalid shift"); | |
5731 | return FAIL; | |
5732 | } | |
5733 | inst.operands[0].shifted = 1; | |
5734 | } | |
5735 | ||
5736 | if (skip_past_char (&p, ']') == FAIL) | |
5737 | { | |
5738 | inst.error = _("']' expected"); | |
5739 | return FAIL; | |
5740 | } | |
5741 | *str = p; | |
5742 | return SUCCESS; | |
5743 | } | |
5744 | ||
5287ad62 JB |
5745 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5746 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5747 | Up to four operands may be read; this function handles setting the |
5748 | ".present" field for each read operand itself. | |
5287ad62 JB |
5749 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5750 | else returns FAIL. */ | |
5751 | ||
5752 | static int | |
5753 | parse_neon_mov (char **str, int *which_operand) | |
5754 | { | |
5755 | int i = *which_operand, val; | |
5756 | enum arm_reg_type rtype; | |
5757 | char *ptr = *str; | |
dcbf9037 | 5758 | struct neon_type_el optype; |
5f4273c7 | 5759 | |
dcbf9037 | 5760 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5761 | { |
5762 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5763 | inst.operands[i].reg = val; | |
5764 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5765 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5766 | inst.operands[i++].present = 1; |
5767 | ||
5768 | if (skip_past_comma (&ptr) == FAIL) | |
5769 | goto wanted_comma; | |
5f4273c7 | 5770 | |
dcbf9037 | 5771 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5772 | goto wanted_arm; |
5f4273c7 | 5773 | |
5287ad62 JB |
5774 | inst.operands[i].reg = val; |
5775 | inst.operands[i].isreg = 1; | |
5776 | inst.operands[i].present = 1; | |
5777 | } | |
037e8744 | 5778 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5779 | != FAIL) |
5287ad62 JB |
5780 | { |
5781 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5782 | if (skip_past_comma (&ptr) == FAIL) | |
5783 | goto wanted_comma; | |
5f4273c7 | 5784 | |
5287ad62 JB |
5785 | inst.operands[i].reg = val; |
5786 | inst.operands[i].isreg = 1; | |
5787 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5788 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5789 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5790 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5791 | inst.operands[i++].present = 1; |
5792 | ||
dcbf9037 | 5793 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5794 | { |
037e8744 JB |
5795 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5796 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5797 | inst.operands[i].reg = val; |
5798 | inst.operands[i].isreg = 1; | |
037e8744 | 5799 | inst.operands[i].present = 1; |
5287ad62 JB |
5800 | |
5801 | if (rtype == REG_TYPE_NQ) | |
5802 | { | |
dcbf9037 | 5803 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5804 | return FAIL; |
5805 | } | |
037e8744 JB |
5806 | else if (rtype != REG_TYPE_VFS) |
5807 | { | |
5808 | i++; | |
5809 | if (skip_past_comma (&ptr) == FAIL) | |
5810 | goto wanted_comma; | |
5811 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5812 | goto wanted_arm; | |
5813 | inst.operands[i].reg = val; | |
5814 | inst.operands[i].isreg = 1; | |
5815 | inst.operands[i].present = 1; | |
5816 | } | |
5287ad62 | 5817 | } |
037e8744 JB |
5818 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5819 | &optype)) != FAIL) | |
5287ad62 JB |
5820 | { |
5821 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5822 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5823 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5824 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5825 | |
5826 | inst.operands[i].reg = val; | |
5827 | inst.operands[i].isreg = 1; | |
5828 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5829 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5830 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5831 | inst.operands[i].vectype = optype; |
5287ad62 | 5832 | inst.operands[i].present = 1; |
5f4273c7 | 5833 | |
037e8744 JB |
5834 | if (skip_past_comma (&ptr) == SUCCESS) |
5835 | { | |
5836 | /* Case 15. */ | |
5837 | i++; | |
5838 | ||
5839 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5840 | goto wanted_arm; | |
5841 | ||
5842 | inst.operands[i].reg = val; | |
5843 | inst.operands[i].isreg = 1; | |
5844 | inst.operands[i++].present = 1; | |
5f4273c7 | 5845 | |
037e8744 JB |
5846 | if (skip_past_comma (&ptr) == FAIL) |
5847 | goto wanted_comma; | |
5f4273c7 | 5848 | |
037e8744 JB |
5849 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5850 | goto wanted_arm; | |
5f4273c7 | 5851 | |
037e8744 JB |
5852 | inst.operands[i].reg = val; |
5853 | inst.operands[i].isreg = 1; | |
5854 | inst.operands[i++].present = 1; | |
5855 | } | |
5287ad62 | 5856 | } |
4641781c PB |
5857 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5858 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5859 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5860 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5861 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5862 | inst.operands[i].immisfloat = 1; | |
5863 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5864 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5865 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5866 | ; | |
5287ad62 JB |
5867 | else |
5868 | { | |
dcbf9037 | 5869 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5870 | return FAIL; |
5871 | } | |
5872 | } | |
dcbf9037 | 5873 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5874 | { |
5875 | /* Cases 6, 7. */ | |
5876 | inst.operands[i].reg = val; | |
5877 | inst.operands[i].isreg = 1; | |
5878 | inst.operands[i++].present = 1; | |
5f4273c7 | 5879 | |
5287ad62 JB |
5880 | if (skip_past_comma (&ptr) == FAIL) |
5881 | goto wanted_comma; | |
5f4273c7 | 5882 | |
dcbf9037 | 5883 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5884 | { |
5885 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5886 | inst.operands[i].reg = val; | |
5887 | inst.operands[i].isscalar = 1; | |
5888 | inst.operands[i].present = 1; | |
dcbf9037 | 5889 | inst.operands[i].vectype = optype; |
5287ad62 | 5890 | } |
dcbf9037 | 5891 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5892 | { |
5893 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5894 | inst.operands[i].reg = val; | |
5895 | inst.operands[i].isreg = 1; | |
5896 | inst.operands[i++].present = 1; | |
5f4273c7 | 5897 | |
5287ad62 JB |
5898 | if (skip_past_comma (&ptr) == FAIL) |
5899 | goto wanted_comma; | |
5f4273c7 | 5900 | |
037e8744 | 5901 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5902 | == FAIL) |
5287ad62 | 5903 | { |
037e8744 | 5904 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5905 | return FAIL; |
5906 | } | |
5907 | ||
5908 | inst.operands[i].reg = val; | |
5909 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5910 | inst.operands[i].isvec = 1; |
5911 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5912 | inst.operands[i].vectype = optype; |
5287ad62 | 5913 | inst.operands[i].present = 1; |
5f4273c7 | 5914 | |
037e8744 JB |
5915 | if (rtype == REG_TYPE_VFS) |
5916 | { | |
5917 | /* Case 14. */ | |
5918 | i++; | |
5919 | if (skip_past_comma (&ptr) == FAIL) | |
5920 | goto wanted_comma; | |
5921 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5922 | &optype)) == FAIL) | |
5923 | { | |
5924 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5925 | return FAIL; | |
5926 | } | |
5927 | inst.operands[i].reg = val; | |
5928 | inst.operands[i].isreg = 1; | |
5929 | inst.operands[i].isvec = 1; | |
5930 | inst.operands[i].issingle = 1; | |
5931 | inst.operands[i].vectype = optype; | |
5932 | inst.operands[i].present = 1; | |
5933 | } | |
5934 | } | |
5935 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5936 | != FAIL) | |
5937 | { | |
5938 | /* Case 13. */ | |
5939 | inst.operands[i].reg = val; | |
5940 | inst.operands[i].isreg = 1; | |
5941 | inst.operands[i].isvec = 1; | |
5942 | inst.operands[i].issingle = 1; | |
5943 | inst.operands[i].vectype = optype; | |
5944 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5945 | } |
5946 | } | |
5947 | else | |
5948 | { | |
dcbf9037 | 5949 | first_error (_("parse error")); |
5287ad62 JB |
5950 | return FAIL; |
5951 | } | |
5952 | ||
5953 | /* Successfully parsed the operands. Update args. */ | |
5954 | *which_operand = i; | |
5955 | *str = ptr; | |
5956 | return SUCCESS; | |
5957 | ||
5f4273c7 | 5958 | wanted_comma: |
dcbf9037 | 5959 | first_error (_("expected comma")); |
5287ad62 | 5960 | return FAIL; |
5f4273c7 NC |
5961 | |
5962 | wanted_arm: | |
dcbf9037 | 5963 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 5964 | return FAIL; |
5287ad62 JB |
5965 | } |
5966 | ||
5be8be5d DG |
5967 | /* Use this macro when the operand constraints are different |
5968 | for ARM and THUMB (e.g. ldrd). */ | |
5969 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
5970 | ((arm_operand) | ((thumb_operand) << 16)) | |
5971 | ||
c19d1205 ZW |
5972 | /* Matcher codes for parse_operands. */ |
5973 | enum operand_parse_code | |
5974 | { | |
5975 | OP_stop, /* end of line */ | |
5976 | ||
5977 | OP_RR, /* ARM register */ | |
5978 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 5979 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 5980 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
55881a11 MGD |
5981 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
5982 | optional trailing ! */ | |
c19d1205 ZW |
5983 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
5984 | OP_RCP, /* Coprocessor number */ | |
5985 | OP_RCN, /* Coprocessor register */ | |
5986 | OP_RF, /* FPA register */ | |
5987 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
5988 | OP_RVD, /* VFP double precision register (0..15) */ |
5989 | OP_RND, /* Neon double precision register (0..31) */ | |
5990 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 5991 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 5992 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 5993 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 5994 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
5995 | OP_RVC, /* VFP control register */ |
5996 | OP_RMF, /* Maverick F register */ | |
5997 | OP_RMD, /* Maverick D register */ | |
5998 | OP_RMFX, /* Maverick FX register */ | |
5999 | OP_RMDX, /* Maverick DX register */ | |
6000 | OP_RMAX, /* Maverick AX register */ | |
6001 | OP_RMDS, /* Maverick DSPSC register */ | |
6002 | OP_RIWR, /* iWMMXt wR register */ | |
6003 | OP_RIWC, /* iWMMXt wC register */ | |
6004 | OP_RIWG, /* iWMMXt wCG register */ | |
6005 | OP_RXA, /* XScale accumulator register */ | |
6006 | ||
6007 | OP_REGLST, /* ARM register list */ | |
6008 | OP_VRSLST, /* VFP single-precision register list */ | |
6009 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6010 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6011 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6012 | OP_NSTRLST, /* Neon element/structure list */ | |
6013 | ||
5287ad62 | 6014 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6015 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 6016 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6017 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6018 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6019 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6020 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6021 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6022 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6023 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6024 | |
6025 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6026 | OP_I7, /* immediate value 0 .. 7 */ |
6027 | OP_I15, /* 0 .. 15 */ | |
6028 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6029 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6030 | OP_I31, /* 0 .. 31 */ |
6031 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6032 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6033 | OP_I32z, /* 0 .. 32 */ |
6034 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6035 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6036 | OP_I64, /* 1 .. 64 */ |
6037 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6038 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6039 | |
6040 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6041 | OP_I7b, /* 0 .. 7 */ | |
6042 | OP_I15b, /* 0 .. 15 */ | |
6043 | OP_I31b, /* 0 .. 31 */ | |
6044 | ||
6045 | OP_SH, /* shifter operand */ | |
4962c51a | 6046 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6047 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6048 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6049 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6050 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6051 | OP_EXP, /* arbitrary expression */ |
6052 | OP_EXPi, /* same, with optional immediate prefix */ | |
6053 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6054 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6055 | |
6056 | OP_CPSF, /* CPS flags */ | |
6057 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6058 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6059 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6060 | OP_COND, /* conditional code */ |
92e90b6e | 6061 | OP_TB, /* Table branch. */ |
c19d1205 | 6062 | |
037e8744 JB |
6063 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6064 | ||
c19d1205 ZW |
6065 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6066 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6067 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6068 | OP_RF_IF, /* FPA register or immediate */ | |
6069 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6070 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6071 | |
6072 | /* Optional operands. */ | |
6073 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6074 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6075 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
6076 | OP_oIffffb, /* 0 .. 65535 */ |
6077 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6078 | ||
6079 | OP_oRR, /* ARM register */ | |
6080 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6081 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6082 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6083 | OP_oRND, /* Optional Neon double precision register */ |
6084 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6085 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6086 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6087 | OP_oSHll, /* LSL immediate */ |
6088 | OP_oSHar, /* ASR immediate */ | |
6089 | OP_oSHllar, /* LSL or ASR immediate */ | |
6090 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6091 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6092 | |
5be8be5d DG |
6093 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6094 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6095 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6096 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6097 | ||
c19d1205 ZW |
6098 | OP_FIRST_OPTIONAL = OP_oI7b |
6099 | }; | |
a737bd4d | 6100 | |
c19d1205 ZW |
6101 | /* Generic instruction operand parser. This does no encoding and no |
6102 | semantic validation; it merely squirrels values away in the inst | |
6103 | structure. Returns SUCCESS or FAIL depending on whether the | |
6104 | specified grammar matched. */ | |
6105 | static int | |
5be8be5d | 6106 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6107 | { |
5be8be5d | 6108 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6109 | char *backtrack_pos = 0; |
6110 | const char *backtrack_error = 0; | |
6111 | int i, val, backtrack_index = 0; | |
5287ad62 | 6112 | enum arm_reg_type rtype; |
4962c51a | 6113 | parse_operand_result result; |
5be8be5d | 6114 | unsigned int op_parse_code; |
c19d1205 | 6115 | |
e07e6e58 NC |
6116 | #define po_char_or_fail(chr) \ |
6117 | do \ | |
6118 | { \ | |
6119 | if (skip_past_char (&str, chr) == FAIL) \ | |
6120 | goto bad_args; \ | |
6121 | } \ | |
6122 | while (0) | |
c19d1205 | 6123 | |
e07e6e58 NC |
6124 | #define po_reg_or_fail(regtype) \ |
6125 | do \ | |
dcbf9037 | 6126 | { \ |
e07e6e58 NC |
6127 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
6128 | & inst.operands[i].vectype); \ | |
6129 | if (val == FAIL) \ | |
6130 | { \ | |
6131 | first_error (_(reg_expected_msgs[regtype])); \ | |
6132 | goto failure; \ | |
6133 | } \ | |
6134 | inst.operands[i].reg = val; \ | |
6135 | inst.operands[i].isreg = 1; \ | |
6136 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6137 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6138 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6139 | || rtype == REG_TYPE_VFD \ | |
6140 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6141 | } \ |
e07e6e58 NC |
6142 | while (0) |
6143 | ||
6144 | #define po_reg_or_goto(regtype, label) \ | |
6145 | do \ | |
6146 | { \ | |
6147 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6148 | & inst.operands[i].vectype); \ | |
6149 | if (val == FAIL) \ | |
6150 | goto label; \ | |
dcbf9037 | 6151 | \ |
e07e6e58 NC |
6152 | inst.operands[i].reg = val; \ |
6153 | inst.operands[i].isreg = 1; \ | |
6154 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6155 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6156 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6157 | || rtype == REG_TYPE_VFD \ | |
6158 | || rtype == REG_TYPE_NQ); \ | |
6159 | } \ | |
6160 | while (0) | |
6161 | ||
6162 | #define po_imm_or_fail(min, max, popt) \ | |
6163 | do \ | |
6164 | { \ | |
6165 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6166 | goto failure; \ | |
6167 | inst.operands[i].imm = val; \ | |
6168 | } \ | |
6169 | while (0) | |
6170 | ||
6171 | #define po_scalar_or_goto(elsz, label) \ | |
6172 | do \ | |
6173 | { \ | |
6174 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6175 | if (val == FAIL) \ | |
6176 | goto label; \ | |
6177 | inst.operands[i].reg = val; \ | |
6178 | inst.operands[i].isscalar = 1; \ | |
6179 | } \ | |
6180 | while (0) | |
6181 | ||
6182 | #define po_misc_or_fail(expr) \ | |
6183 | do \ | |
6184 | { \ | |
6185 | if (expr) \ | |
6186 | goto failure; \ | |
6187 | } \ | |
6188 | while (0) | |
6189 | ||
6190 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6191 | do \ | |
6192 | { \ | |
6193 | result = expr; \ | |
6194 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6195 | backtrack_pos = 0; \ | |
6196 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6197 | goto failure; \ | |
6198 | } \ | |
6199 | while (0) | |
4962c51a | 6200 | |
52e7f43d RE |
6201 | #define po_barrier_or_imm(str) \ |
6202 | do \ | |
6203 | { \ | |
6204 | val = parse_barrier (&str); \ | |
6205 | if (val == FAIL) \ | |
6206 | { \ | |
6207 | if (ISALPHA (*str)) \ | |
6208 | goto failure; \ | |
6209 | else \ | |
6210 | goto immediate; \ | |
6211 | } \ | |
6212 | else \ | |
6213 | { \ | |
6214 | if ((inst.instruction & 0xf0) == 0x60 \ | |
6215 | && val != 0xf) \ | |
6216 | { \ | |
6217 | /* ISB can only take SY as an option. */ \ | |
6218 | inst.error = _("invalid barrier type"); \ | |
6219 | goto failure; \ | |
6220 | } \ | |
6221 | } \ | |
6222 | } \ | |
6223 | while (0) | |
6224 | ||
c19d1205 ZW |
6225 | skip_whitespace (str); |
6226 | ||
6227 | for (i = 0; upat[i] != OP_stop; i++) | |
6228 | { | |
5be8be5d DG |
6229 | op_parse_code = upat[i]; |
6230 | if (op_parse_code >= 1<<16) | |
6231 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6232 | : (op_parse_code & ((1<<16)-1)); | |
6233 | ||
6234 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6235 | { |
6236 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6237 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6238 | backtrack_pos = str; |
6239 | backtrack_error = inst.error; | |
6240 | backtrack_index = i; | |
6241 | } | |
6242 | ||
b6702015 | 6243 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6244 | po_char_or_fail (','); |
6245 | ||
5be8be5d | 6246 | switch (op_parse_code) |
c19d1205 ZW |
6247 | { |
6248 | /* Registers */ | |
6249 | case OP_oRRnpc: | |
5be8be5d | 6250 | case OP_oRRnpcsp: |
c19d1205 | 6251 | case OP_RRnpc: |
5be8be5d | 6252 | case OP_RRnpcsp: |
c19d1205 ZW |
6253 | case OP_oRR: |
6254 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6255 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6256 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6257 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6258 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6259 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6260 | case OP_oRND: |
6261 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6262 | case OP_RVC: |
6263 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6264 | break; | |
6265 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6266 | coproc_reg: | |
6267 | po_reg_or_fail (REG_TYPE_CN); | |
6268 | break; | |
c19d1205 ZW |
6269 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6270 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6271 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6272 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6273 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6274 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6275 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6276 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6277 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6278 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6279 | case OP_oRNQ: |
6280 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6281 | case OP_oRNDQ: | |
6282 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6283 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6284 | case OP_oRNSDQ: | |
6285 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6286 | |
6287 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6288 | scalars are accepted here, so deal with those in later code. */ | |
6289 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6290 | ||
5287ad62 JB |
6291 | case OP_RNDQ_I0: |
6292 | { | |
6293 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6294 | break; | |
6295 | try_imm0: | |
6296 | po_imm_or_fail (0, 0, TRUE); | |
6297 | } | |
6298 | break; | |
6299 | ||
037e8744 JB |
6300 | case OP_RVSD_I0: |
6301 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6302 | break; | |
6303 | ||
5287ad62 JB |
6304 | case OP_RR_RNSC: |
6305 | { | |
6306 | po_scalar_or_goto (8, try_rr); | |
6307 | break; | |
6308 | try_rr: | |
6309 | po_reg_or_fail (REG_TYPE_RN); | |
6310 | } | |
6311 | break; | |
6312 | ||
037e8744 JB |
6313 | case OP_RNSDQ_RNSC: |
6314 | { | |
6315 | po_scalar_or_goto (8, try_nsdq); | |
6316 | break; | |
6317 | try_nsdq: | |
6318 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6319 | } | |
6320 | break; | |
6321 | ||
5287ad62 JB |
6322 | case OP_RNDQ_RNSC: |
6323 | { | |
6324 | po_scalar_or_goto (8, try_ndq); | |
6325 | break; | |
6326 | try_ndq: | |
6327 | po_reg_or_fail (REG_TYPE_NDQ); | |
6328 | } | |
6329 | break; | |
6330 | ||
6331 | case OP_RND_RNSC: | |
6332 | { | |
6333 | po_scalar_or_goto (8, try_vfd); | |
6334 | break; | |
6335 | try_vfd: | |
6336 | po_reg_or_fail (REG_TYPE_VFD); | |
6337 | } | |
6338 | break; | |
6339 | ||
6340 | case OP_VMOV: | |
6341 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6342 | not careful then bad things might happen. */ | |
6343 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6344 | break; | |
6345 | ||
4316f0d2 | 6346 | case OP_RNDQ_Ibig: |
5287ad62 | 6347 | { |
4316f0d2 | 6348 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6349 | break; |
4316f0d2 | 6350 | try_immbig: |
5287ad62 JB |
6351 | /* There's a possibility of getting a 64-bit immediate here, so |
6352 | we need special handling. */ | |
6353 | if (parse_big_immediate (&str, i) == FAIL) | |
6354 | { | |
6355 | inst.error = _("immediate value is out of range"); | |
6356 | goto failure; | |
6357 | } | |
6358 | } | |
6359 | break; | |
6360 | ||
6361 | case OP_RNDQ_I63b: | |
6362 | { | |
6363 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6364 | break; | |
6365 | try_shimm: | |
6366 | po_imm_or_fail (0, 63, TRUE); | |
6367 | } | |
6368 | break; | |
c19d1205 ZW |
6369 | |
6370 | case OP_RRnpcb: | |
6371 | po_char_or_fail ('['); | |
6372 | po_reg_or_fail (REG_TYPE_RN); | |
6373 | po_char_or_fail (']'); | |
6374 | break; | |
a737bd4d | 6375 | |
55881a11 | 6376 | case OP_RRnpctw: |
c19d1205 | 6377 | case OP_RRw: |
b6702015 | 6378 | case OP_oRRw: |
c19d1205 ZW |
6379 | po_reg_or_fail (REG_TYPE_RN); |
6380 | if (skip_past_char (&str, '!') == SUCCESS) | |
6381 | inst.operands[i].writeback = 1; | |
6382 | break; | |
6383 | ||
6384 | /* Immediates */ | |
6385 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6386 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6387 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6388 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6389 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6390 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6391 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6392 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6393 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6394 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6395 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6396 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6397 | |
6398 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6399 | case OP_oI7b: | |
6400 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6401 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6402 | case OP_oI31b: | |
6403 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6404 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
6405 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6406 | ||
6407 | /* Immediate variants */ | |
6408 | case OP_oI255c: | |
6409 | po_char_or_fail ('{'); | |
6410 | po_imm_or_fail (0, 255, TRUE); | |
6411 | po_char_or_fail ('}'); | |
6412 | break; | |
6413 | ||
6414 | case OP_I31w: | |
6415 | /* The expression parser chokes on a trailing !, so we have | |
6416 | to find it first and zap it. */ | |
6417 | { | |
6418 | char *s = str; | |
6419 | while (*s && *s != ',') | |
6420 | s++; | |
6421 | if (s[-1] == '!') | |
6422 | { | |
6423 | s[-1] = '\0'; | |
6424 | inst.operands[i].writeback = 1; | |
6425 | } | |
6426 | po_imm_or_fail (0, 31, TRUE); | |
6427 | if (str == s - 1) | |
6428 | str = s; | |
6429 | } | |
6430 | break; | |
6431 | ||
6432 | /* Expressions */ | |
6433 | case OP_EXPi: EXPi: | |
6434 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6435 | GE_OPT_PREFIX)); | |
6436 | break; | |
6437 | ||
6438 | case OP_EXP: | |
6439 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6440 | GE_NO_PREFIX)); | |
6441 | break; | |
6442 | ||
6443 | case OP_EXPr: EXPr: | |
6444 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6445 | GE_NO_PREFIX)); | |
6446 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6447 | { |
c19d1205 ZW |
6448 | val = parse_reloc (&str); |
6449 | if (val == -1) | |
6450 | { | |
6451 | inst.error = _("unrecognized relocation suffix"); | |
6452 | goto failure; | |
6453 | } | |
6454 | else if (val != BFD_RELOC_UNUSED) | |
6455 | { | |
6456 | inst.operands[i].imm = val; | |
6457 | inst.operands[i].hasreloc = 1; | |
6458 | } | |
a737bd4d | 6459 | } |
c19d1205 | 6460 | break; |
a737bd4d | 6461 | |
b6895b4f PB |
6462 | /* Operand for MOVW or MOVT. */ |
6463 | case OP_HALF: | |
6464 | po_misc_or_fail (parse_half (&str)); | |
6465 | break; | |
6466 | ||
e07e6e58 | 6467 | /* Register or expression. */ |
c19d1205 ZW |
6468 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6469 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6470 | |
e07e6e58 | 6471 | /* Register or immediate. */ |
c19d1205 ZW |
6472 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6473 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6474 | |
c19d1205 ZW |
6475 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6476 | IF: | |
6477 | if (!is_immediate_prefix (*str)) | |
6478 | goto bad_args; | |
6479 | str++; | |
6480 | val = parse_fpa_immediate (&str); | |
6481 | if (val == FAIL) | |
6482 | goto failure; | |
6483 | /* FPA immediates are encoded as registers 8-15. | |
6484 | parse_fpa_immediate has already applied the offset. */ | |
6485 | inst.operands[i].reg = val; | |
6486 | inst.operands[i].isreg = 1; | |
6487 | break; | |
09d92015 | 6488 | |
2d447fca JM |
6489 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6490 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6491 | ||
e07e6e58 | 6492 | /* Two kinds of register. */ |
c19d1205 ZW |
6493 | case OP_RIWR_RIWC: |
6494 | { | |
6495 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6496 | if (!rege |
6497 | || (rege->type != REG_TYPE_MMXWR | |
6498 | && rege->type != REG_TYPE_MMXWC | |
6499 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6500 | { |
6501 | inst.error = _("iWMMXt data or control register expected"); | |
6502 | goto failure; | |
6503 | } | |
6504 | inst.operands[i].reg = rege->number; | |
6505 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6506 | } | |
6507 | break; | |
09d92015 | 6508 | |
41adaa5c JM |
6509 | case OP_RIWC_RIWG: |
6510 | { | |
6511 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6512 | if (!rege | |
6513 | || (rege->type != REG_TYPE_MMXWC | |
6514 | && rege->type != REG_TYPE_MMXWCG)) | |
6515 | { | |
6516 | inst.error = _("iWMMXt control register expected"); | |
6517 | goto failure; | |
6518 | } | |
6519 | inst.operands[i].reg = rege->number; | |
6520 | inst.operands[i].isreg = 1; | |
6521 | } | |
6522 | break; | |
6523 | ||
c19d1205 ZW |
6524 | /* Misc */ |
6525 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6526 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6527 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6528 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6529 | case OP_oBARRIER_I15: |
6530 | po_barrier_or_imm (str); break; | |
6531 | immediate: | |
6532 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
6533 | goto failure; | |
6534 | break; | |
c19d1205 | 6535 | |
d2cd1205 JB |
6536 | case OP_wPSR: |
6537 | case OP_rPSR: | |
90ec0d68 MGD |
6538 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6539 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6540 | { | |
6541 | inst.error = _("Banked registers are not available with this " | |
6542 | "architecture."); | |
6543 | goto failure; | |
6544 | } | |
6545 | break; | |
d2cd1205 JB |
6546 | try_psr: |
6547 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6548 | break; | |
037e8744 JB |
6549 | |
6550 | case OP_APSR_RR: | |
6551 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6552 | break; | |
6553 | try_apsr: | |
6554 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6555 | instruction). */ | |
6556 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6557 | { | |
6558 | unsigned found = 0; | |
6559 | str += 5; | |
6560 | while (found < 15) | |
6561 | switch (*str++) | |
6562 | { | |
6563 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6564 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6565 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6566 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6567 | default: found = 16; | |
6568 | } | |
6569 | if (found != 15) | |
6570 | goto failure; | |
6571 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6572 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6573 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6574 | } |
6575 | else | |
6576 | goto failure; | |
6577 | break; | |
6578 | ||
92e90b6e PB |
6579 | case OP_TB: |
6580 | po_misc_or_fail (parse_tb (&str)); | |
6581 | break; | |
6582 | ||
e07e6e58 | 6583 | /* Register lists. */ |
c19d1205 ZW |
6584 | case OP_REGLST: |
6585 | val = parse_reg_list (&str); | |
6586 | if (*str == '^') | |
6587 | { | |
6588 | inst.operands[1].writeback = 1; | |
6589 | str++; | |
6590 | } | |
6591 | break; | |
09d92015 | 6592 | |
c19d1205 | 6593 | case OP_VRSLST: |
5287ad62 | 6594 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6595 | break; |
09d92015 | 6596 | |
c19d1205 | 6597 | case OP_VRDLST: |
5287ad62 | 6598 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6599 | break; |
a737bd4d | 6600 | |
037e8744 JB |
6601 | case OP_VRSDLST: |
6602 | /* Allow Q registers too. */ | |
6603 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6604 | REGLIST_NEON_D); | |
6605 | if (val == FAIL) | |
6606 | { | |
6607 | inst.error = NULL; | |
6608 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6609 | REGLIST_VFP_S); | |
6610 | inst.operands[i].issingle = 1; | |
6611 | } | |
6612 | break; | |
6613 | ||
5287ad62 JB |
6614 | case OP_NRDLST: |
6615 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6616 | REGLIST_NEON_D); | |
6617 | break; | |
6618 | ||
6619 | case OP_NSTRLST: | |
dcbf9037 JB |
6620 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6621 | &inst.operands[i].vectype); | |
5287ad62 JB |
6622 | break; |
6623 | ||
c19d1205 ZW |
6624 | /* Addressing modes */ |
6625 | case OP_ADDR: | |
6626 | po_misc_or_fail (parse_address (&str, i)); | |
6627 | break; | |
09d92015 | 6628 | |
4962c51a MS |
6629 | case OP_ADDRGLDR: |
6630 | po_misc_or_fail_no_backtrack ( | |
6631 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6632 | break; | |
6633 | ||
6634 | case OP_ADDRGLDRS: | |
6635 | po_misc_or_fail_no_backtrack ( | |
6636 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6637 | break; | |
6638 | ||
6639 | case OP_ADDRGLDC: | |
6640 | po_misc_or_fail_no_backtrack ( | |
6641 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6642 | break; | |
6643 | ||
c19d1205 ZW |
6644 | case OP_SH: |
6645 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6646 | break; | |
09d92015 | 6647 | |
4962c51a MS |
6648 | case OP_SHG: |
6649 | po_misc_or_fail_no_backtrack ( | |
6650 | parse_shifter_operand_group_reloc (&str, i)); | |
6651 | break; | |
6652 | ||
c19d1205 ZW |
6653 | case OP_oSHll: |
6654 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6655 | break; | |
09d92015 | 6656 | |
c19d1205 ZW |
6657 | case OP_oSHar: |
6658 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6659 | break; | |
09d92015 | 6660 | |
c19d1205 ZW |
6661 | case OP_oSHllar: |
6662 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6663 | break; | |
09d92015 | 6664 | |
c19d1205 | 6665 | default: |
5be8be5d | 6666 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6667 | } |
09d92015 | 6668 | |
c19d1205 ZW |
6669 | /* Various value-based sanity checks and shared operations. We |
6670 | do not signal immediate failures for the register constraints; | |
6671 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6672 | switch (op_parse_code) |
c19d1205 ZW |
6673 | { |
6674 | case OP_oRRnpc: | |
6675 | case OP_RRnpc: | |
6676 | case OP_RRnpcb: | |
6677 | case OP_RRw: | |
b6702015 | 6678 | case OP_oRRw: |
c19d1205 ZW |
6679 | case OP_RRnpc_I0: |
6680 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6681 | inst.error = BAD_PC; | |
6682 | break; | |
09d92015 | 6683 | |
5be8be5d DG |
6684 | case OP_oRRnpcsp: |
6685 | case OP_RRnpcsp: | |
6686 | if (inst.operands[i].isreg) | |
6687 | { | |
6688 | if (inst.operands[i].reg == REG_PC) | |
6689 | inst.error = BAD_PC; | |
6690 | else if (inst.operands[i].reg == REG_SP) | |
6691 | inst.error = BAD_SP; | |
6692 | } | |
6693 | break; | |
6694 | ||
55881a11 MGD |
6695 | case OP_RRnpctw: |
6696 | if (inst.operands[i].isreg | |
6697 | && inst.operands[i].reg == REG_PC | |
6698 | && (inst.operands[i].writeback || thumb)) | |
6699 | inst.error = BAD_PC; | |
6700 | break; | |
6701 | ||
c19d1205 ZW |
6702 | case OP_CPSF: |
6703 | case OP_ENDI: | |
6704 | case OP_oROR: | |
d2cd1205 JB |
6705 | case OP_wPSR: |
6706 | case OP_rPSR: | |
c19d1205 | 6707 | case OP_COND: |
52e7f43d | 6708 | case OP_oBARRIER_I15: |
c19d1205 ZW |
6709 | case OP_REGLST: |
6710 | case OP_VRSLST: | |
6711 | case OP_VRDLST: | |
037e8744 | 6712 | case OP_VRSDLST: |
5287ad62 JB |
6713 | case OP_NRDLST: |
6714 | case OP_NSTRLST: | |
c19d1205 ZW |
6715 | if (val == FAIL) |
6716 | goto failure; | |
6717 | inst.operands[i].imm = val; | |
6718 | break; | |
a737bd4d | 6719 | |
c19d1205 ZW |
6720 | default: |
6721 | break; | |
6722 | } | |
09d92015 | 6723 | |
c19d1205 ZW |
6724 | /* If we get here, this operand was successfully parsed. */ |
6725 | inst.operands[i].present = 1; | |
6726 | continue; | |
09d92015 | 6727 | |
c19d1205 | 6728 | bad_args: |
09d92015 | 6729 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6730 | |
6731 | failure: | |
6732 | if (!backtrack_pos) | |
d252fdde PB |
6733 | { |
6734 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6735 | default here just in case. */ |
d252fdde PB |
6736 | if (!inst.error) |
6737 | inst.error = _("syntax error"); | |
6738 | return FAIL; | |
6739 | } | |
c19d1205 ZW |
6740 | |
6741 | /* Do not backtrack over a trailing optional argument that | |
6742 | absorbed some text. We will only fail again, with the | |
6743 | 'garbage following instruction' error message, which is | |
6744 | probably less helpful than the current one. */ | |
6745 | if (backtrack_index == i && backtrack_pos != str | |
6746 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6747 | { |
6748 | if (!inst.error) | |
6749 | inst.error = _("syntax error"); | |
6750 | return FAIL; | |
6751 | } | |
c19d1205 ZW |
6752 | |
6753 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6754 | str = backtrack_pos; | |
6755 | inst.error = backtrack_error; | |
6756 | inst.operands[backtrack_index].present = 0; | |
6757 | i = backtrack_index; | |
6758 | backtrack_pos = 0; | |
09d92015 | 6759 | } |
09d92015 | 6760 | |
c19d1205 ZW |
6761 | /* Check that we have parsed all the arguments. */ |
6762 | if (*str != '\0' && !inst.error) | |
6763 | inst.error = _("garbage following instruction"); | |
09d92015 | 6764 | |
c19d1205 | 6765 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6766 | } |
6767 | ||
c19d1205 ZW |
6768 | #undef po_char_or_fail |
6769 | #undef po_reg_or_fail | |
6770 | #undef po_reg_or_goto | |
6771 | #undef po_imm_or_fail | |
5287ad62 | 6772 | #undef po_scalar_or_fail |
52e7f43d | 6773 | #undef po_barrier_or_imm |
e07e6e58 | 6774 | |
c19d1205 | 6775 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6776 | #define constraint(expr, err) \ |
6777 | do \ | |
c19d1205 | 6778 | { \ |
e07e6e58 NC |
6779 | if (expr) \ |
6780 | { \ | |
6781 | inst.error = err; \ | |
6782 | return; \ | |
6783 | } \ | |
c19d1205 | 6784 | } \ |
e07e6e58 | 6785 | while (0) |
c19d1205 | 6786 | |
fdfde340 JM |
6787 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6788 | instructions are unpredictable if these registers are used. This | |
6789 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6790 | #define reject_bad_reg(reg) \ | |
6791 | do \ | |
6792 | if (reg == REG_SP || reg == REG_PC) \ | |
6793 | { \ | |
6794 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6795 | return; \ | |
6796 | } \ | |
6797 | while (0) | |
6798 | ||
94206790 MM |
6799 | /* If REG is R13 (the stack pointer), warn that its use is |
6800 | deprecated. */ | |
6801 | #define warn_deprecated_sp(reg) \ | |
6802 | do \ | |
6803 | if (warn_on_deprecated && reg == REG_SP) \ | |
6804 | as_warn (_("use of r13 is deprecated")); \ | |
6805 | while (0) | |
6806 | ||
c19d1205 ZW |
6807 | /* Functions for operand encoding. ARM, then Thumb. */ |
6808 | ||
6809 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6810 | ||
6811 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6812 | return the encoded form. Otherwise, return FAIL. */ | |
6813 | ||
6814 | static unsigned int | |
6815 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6816 | { |
c19d1205 ZW |
6817 | unsigned int a, i; |
6818 | ||
6819 | for (i = 0; i < 32; i += 2) | |
6820 | if ((a = rotate_left (val, i)) <= 0xff) | |
6821 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6822 | ||
6823 | return FAIL; | |
09d92015 MM |
6824 | } |
6825 | ||
c19d1205 ZW |
6826 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6827 | return the encoded form. Otherwise, return FAIL. */ | |
6828 | static unsigned int | |
6829 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6830 | { |
c19d1205 | 6831 | unsigned int a, i; |
09d92015 | 6832 | |
9c3c69f2 | 6833 | if (val <= 0xff) |
c19d1205 | 6834 | return val; |
a737bd4d | 6835 | |
9c3c69f2 | 6836 | for (i = 1; i <= 24; i++) |
09d92015 | 6837 | { |
9c3c69f2 PB |
6838 | a = val >> i; |
6839 | if ((val & ~(0xff << i)) == 0) | |
6840 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6841 | } |
a737bd4d | 6842 | |
c19d1205 ZW |
6843 | a = val & 0xff; |
6844 | if (val == ((a << 16) | a)) | |
6845 | return 0x100 | a; | |
6846 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6847 | return 0x300 | a; | |
09d92015 | 6848 | |
c19d1205 ZW |
6849 | a = val & 0xff00; |
6850 | if (val == ((a << 16) | a)) | |
6851 | return 0x200 | (a >> 8); | |
a737bd4d | 6852 | |
c19d1205 | 6853 | return FAIL; |
09d92015 | 6854 | } |
5287ad62 | 6855 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6856 | |
6857 | static void | |
5287ad62 JB |
6858 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6859 | { | |
6860 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6861 | && reg > 15) | |
6862 | { | |
b1cc4aeb | 6863 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6864 | { |
6865 | if (thumb_mode) | |
6866 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6867 | fpu_vfp_ext_d32); |
5287ad62 JB |
6868 | else |
6869 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6870 | fpu_vfp_ext_d32); |
5287ad62 JB |
6871 | } |
6872 | else | |
6873 | { | |
dcbf9037 | 6874 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6875 | return; |
6876 | } | |
6877 | } | |
6878 | ||
c19d1205 | 6879 | switch (pos) |
09d92015 | 6880 | { |
c19d1205 ZW |
6881 | case VFP_REG_Sd: |
6882 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6883 | break; | |
6884 | ||
6885 | case VFP_REG_Sn: | |
6886 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6887 | break; | |
6888 | ||
6889 | case VFP_REG_Sm: | |
6890 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6891 | break; | |
6892 | ||
5287ad62 JB |
6893 | case VFP_REG_Dd: |
6894 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6895 | break; | |
5f4273c7 | 6896 | |
5287ad62 JB |
6897 | case VFP_REG_Dn: |
6898 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6899 | break; | |
5f4273c7 | 6900 | |
5287ad62 JB |
6901 | case VFP_REG_Dm: |
6902 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6903 | break; | |
6904 | ||
c19d1205 ZW |
6905 | default: |
6906 | abort (); | |
09d92015 | 6907 | } |
09d92015 MM |
6908 | } |
6909 | ||
c19d1205 | 6910 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6911 | if any, is handled by md_apply_fix. */ |
09d92015 | 6912 | static void |
c19d1205 | 6913 | encode_arm_shift (int i) |
09d92015 | 6914 | { |
c19d1205 ZW |
6915 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6916 | inst.instruction |= SHIFT_ROR << 5; | |
6917 | else | |
09d92015 | 6918 | { |
c19d1205 ZW |
6919 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6920 | if (inst.operands[i].immisreg) | |
6921 | { | |
6922 | inst.instruction |= SHIFT_BY_REG; | |
6923 | inst.instruction |= inst.operands[i].imm << 8; | |
6924 | } | |
6925 | else | |
6926 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6927 | } |
c19d1205 | 6928 | } |
09d92015 | 6929 | |
c19d1205 ZW |
6930 | static void |
6931 | encode_arm_shifter_operand (int i) | |
6932 | { | |
6933 | if (inst.operands[i].isreg) | |
09d92015 | 6934 | { |
c19d1205 ZW |
6935 | inst.instruction |= inst.operands[i].reg; |
6936 | encode_arm_shift (i); | |
09d92015 | 6937 | } |
c19d1205 ZW |
6938 | else |
6939 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6940 | } |
6941 | ||
c19d1205 | 6942 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6943 | static void |
c19d1205 | 6944 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6945 | { |
9c2799c2 | 6946 | gas_assert (inst.operands[i].isreg); |
c19d1205 | 6947 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6948 | |
c19d1205 | 6949 | if (inst.operands[i].preind) |
09d92015 | 6950 | { |
c19d1205 ZW |
6951 | if (is_t) |
6952 | { | |
6953 | inst.error = _("instruction does not accept preindexed addressing"); | |
6954 | return; | |
6955 | } | |
6956 | inst.instruction |= PRE_INDEX; | |
6957 | if (inst.operands[i].writeback) | |
6958 | inst.instruction |= WRITE_BACK; | |
09d92015 | 6959 | |
c19d1205 ZW |
6960 | } |
6961 | else if (inst.operands[i].postind) | |
6962 | { | |
9c2799c2 | 6963 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
6964 | if (is_t) |
6965 | inst.instruction |= WRITE_BACK; | |
6966 | } | |
6967 | else /* unindexed - only for coprocessor */ | |
09d92015 | 6968 | { |
c19d1205 | 6969 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
6970 | return; |
6971 | } | |
6972 | ||
c19d1205 ZW |
6973 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
6974 | && (((inst.instruction & 0x000f0000) >> 16) | |
6975 | == ((inst.instruction & 0x0000f000) >> 12))) | |
6976 | as_warn ((inst.instruction & LOAD_BIT) | |
6977 | ? _("destination register same as write-back base") | |
6978 | : _("source register same as write-back base")); | |
09d92015 MM |
6979 | } |
6980 | ||
c19d1205 ZW |
6981 | /* inst.operands[i] was set up by parse_address. Encode it into an |
6982 | ARM-format mode 2 load or store instruction. If is_t is true, | |
6983 | reject forms that cannot be used with a T instruction (i.e. not | |
6984 | post-indexed). */ | |
a737bd4d | 6985 | static void |
c19d1205 | 6986 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 6987 | { |
5be8be5d DG |
6988 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
6989 | ||
c19d1205 | 6990 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 6991 | |
c19d1205 | 6992 | if (inst.operands[i].immisreg) |
09d92015 | 6993 | { |
5be8be5d DG |
6994 | constraint ((inst.operands[i].imm == REG_PC |
6995 | || (is_pc && inst.operands[i].writeback)), | |
6996 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
6997 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
6998 | inst.instruction |= inst.operands[i].imm; | |
6999 | if (!inst.operands[i].negative) | |
7000 | inst.instruction |= INDEX_UP; | |
7001 | if (inst.operands[i].shifted) | |
7002 | { | |
7003 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7004 | inst.instruction |= SHIFT_ROR << 5; | |
7005 | else | |
7006 | { | |
7007 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7008 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7009 | } | |
7010 | } | |
09d92015 | 7011 | } |
c19d1205 | 7012 | else /* immediate offset in inst.reloc */ |
09d92015 | 7013 | { |
5be8be5d DG |
7014 | if (is_pc && !inst.reloc.pc_rel) |
7015 | { | |
7016 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7017 | |
7018 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7019 | cannot use PC in addressing. | |
7020 | PC cannot be used in writeback addressing, either. */ | |
7021 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7022 | BAD_PC_ADDRESSING); |
23a10334 | 7023 | |
dc5ec521 | 7024 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7025 | if (warn_on_deprecated |
7026 | && !is_load | |
7027 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
7028 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
7029 | } |
7030 | ||
c19d1205 ZW |
7031 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7032 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 7033 | } |
09d92015 MM |
7034 | } |
7035 | ||
c19d1205 ZW |
7036 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7037 | ARM-format mode 3 load or store instruction. Reject forms that | |
7038 | cannot be used with such instructions. If is_t is true, reject | |
7039 | forms that cannot be used with a T instruction (i.e. not | |
7040 | post-indexed). */ | |
7041 | static void | |
7042 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7043 | { |
c19d1205 | 7044 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7045 | { |
c19d1205 ZW |
7046 | inst.error = _("instruction does not accept scaled register index"); |
7047 | return; | |
09d92015 | 7048 | } |
a737bd4d | 7049 | |
c19d1205 | 7050 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7051 | |
c19d1205 ZW |
7052 | if (inst.operands[i].immisreg) |
7053 | { | |
5be8be5d DG |
7054 | constraint ((inst.operands[i].imm == REG_PC |
7055 | || inst.operands[i].reg == REG_PC), | |
7056 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7057 | inst.instruction |= inst.operands[i].imm; |
7058 | if (!inst.operands[i].negative) | |
7059 | inst.instruction |= INDEX_UP; | |
7060 | } | |
7061 | else /* immediate offset in inst.reloc */ | |
7062 | { | |
5be8be5d DG |
7063 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7064 | && inst.operands[i].writeback), | |
7065 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7066 | inst.instruction |= HWOFFSET_IMM; |
7067 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
7068 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 7069 | } |
a737bd4d NC |
7070 | } |
7071 | ||
c19d1205 ZW |
7072 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7073 | ARM-format instruction. Reject all forms which cannot be encoded | |
7074 | into a coprocessor load/store instruction. If wb_ok is false, | |
7075 | reject use of writeback; if unind_ok is false, reject use of | |
7076 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
7077 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
7078 | (in which case it is preserved). */ | |
09d92015 | 7079 | |
c19d1205 ZW |
7080 | static int |
7081 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 7082 | { |
c19d1205 | 7083 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7084 | |
9c2799c2 | 7085 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 7086 | |
c19d1205 | 7087 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 7088 | { |
9c2799c2 | 7089 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
7090 | if (!unind_ok) |
7091 | { | |
7092 | inst.error = _("instruction does not support unindexed addressing"); | |
7093 | return FAIL; | |
7094 | } | |
7095 | inst.instruction |= inst.operands[i].imm; | |
7096 | inst.instruction |= INDEX_UP; | |
7097 | return SUCCESS; | |
09d92015 | 7098 | } |
a737bd4d | 7099 | |
c19d1205 ZW |
7100 | if (inst.operands[i].preind) |
7101 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 7102 | |
c19d1205 | 7103 | if (inst.operands[i].writeback) |
09d92015 | 7104 | { |
c19d1205 ZW |
7105 | if (inst.operands[i].reg == REG_PC) |
7106 | { | |
7107 | inst.error = _("pc may not be used with write-back"); | |
7108 | return FAIL; | |
7109 | } | |
7110 | if (!wb_ok) | |
7111 | { | |
7112 | inst.error = _("instruction does not support writeback"); | |
7113 | return FAIL; | |
7114 | } | |
7115 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7116 | } |
a737bd4d | 7117 | |
c19d1205 | 7118 | if (reloc_override) |
21d799b5 | 7119 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
7120 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
7121 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7122 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
7123 | { | |
7124 | if (thumb_mode) | |
7125 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7126 | else | |
7127 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
7128 | } | |
7129 | ||
c19d1205 ZW |
7130 | return SUCCESS; |
7131 | } | |
a737bd4d | 7132 | |
c19d1205 ZW |
7133 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7134 | Determine whether it can be performed with a move instruction; if | |
7135 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7136 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7137 | load and return FALSE. If this is not a valid thing to do in the | |
7138 | current context, set inst.error and return TRUE. | |
a737bd4d | 7139 | |
c19d1205 ZW |
7140 | inst.operands[i] describes the destination register. */ |
7141 | ||
c921be7d | 7142 | static bfd_boolean |
c19d1205 ZW |
7143 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
7144 | { | |
53365c0d PB |
7145 | unsigned long tbit; |
7146 | ||
7147 | if (thumb_p) | |
7148 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7149 | else | |
7150 | tbit = LOAD_BIT; | |
7151 | ||
7152 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7153 | { |
c19d1205 | 7154 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7155 | return TRUE; |
09d92015 | 7156 | } |
c19d1205 | 7157 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
7158 | { |
7159 | inst.error = _("constant expression expected"); | |
c921be7d | 7160 | return TRUE; |
09d92015 | 7161 | } |
c19d1205 | 7162 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 7163 | { |
c19d1205 ZW |
7164 | if (thumb_p) |
7165 | { | |
53365c0d | 7166 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
7167 | { |
7168 | /* This can be done with a mov(1) instruction. */ | |
7169 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7170 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 7171 | return TRUE; |
c19d1205 ZW |
7172 | } |
7173 | } | |
7174 | else | |
7175 | { | |
7176 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7177 | if (value != FAIL) | |
7178 | { | |
7179 | /* This can be done with a mov instruction. */ | |
7180 | inst.instruction &= LITERAL_MASK; | |
7181 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7182 | inst.instruction |= value & 0xfff; | |
c921be7d | 7183 | return TRUE; |
c19d1205 | 7184 | } |
09d92015 | 7185 | |
c19d1205 ZW |
7186 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
7187 | if (value != FAIL) | |
7188 | { | |
7189 | /* This can be done with a mvn instruction. */ | |
7190 | inst.instruction &= LITERAL_MASK; | |
7191 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7192 | inst.instruction |= value & 0xfff; | |
c921be7d | 7193 | return TRUE; |
c19d1205 ZW |
7194 | } |
7195 | } | |
09d92015 MM |
7196 | } |
7197 | ||
c19d1205 ZW |
7198 | if (add_to_lit_pool () == FAIL) |
7199 | { | |
7200 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 7201 | return TRUE; |
c19d1205 ZW |
7202 | } |
7203 | inst.operands[1].reg = REG_PC; | |
7204 | inst.operands[1].isreg = 1; | |
7205 | inst.operands[1].preind = 1; | |
7206 | inst.reloc.pc_rel = 1; | |
7207 | inst.reloc.type = (thumb_p | |
7208 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7209 | : (mode_3 | |
7210 | ? BFD_RELOC_ARM_HWLITERAL | |
7211 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 7212 | return FALSE; |
09d92015 MM |
7213 | } |
7214 | ||
5f4273c7 | 7215 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7216 | First some generics; their names are taken from the conventional |
7217 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7218 | |
a737bd4d | 7219 | static void |
c19d1205 | 7220 | do_noargs (void) |
09d92015 | 7221 | { |
c19d1205 | 7222 | } |
a737bd4d | 7223 | |
c19d1205 ZW |
7224 | static void |
7225 | do_rd (void) | |
7226 | { | |
7227 | inst.instruction |= inst.operands[0].reg << 12; | |
7228 | } | |
a737bd4d | 7229 | |
c19d1205 ZW |
7230 | static void |
7231 | do_rd_rm (void) | |
7232 | { | |
7233 | inst.instruction |= inst.operands[0].reg << 12; | |
7234 | inst.instruction |= inst.operands[1].reg; | |
7235 | } | |
09d92015 | 7236 | |
c19d1205 ZW |
7237 | static void |
7238 | do_rd_rn (void) | |
7239 | { | |
7240 | inst.instruction |= inst.operands[0].reg << 12; | |
7241 | inst.instruction |= inst.operands[1].reg << 16; | |
7242 | } | |
a737bd4d | 7243 | |
c19d1205 ZW |
7244 | static void |
7245 | do_rn_rd (void) | |
7246 | { | |
7247 | inst.instruction |= inst.operands[0].reg << 16; | |
7248 | inst.instruction |= inst.operands[1].reg << 12; | |
7249 | } | |
09d92015 | 7250 | |
c19d1205 ZW |
7251 | static void |
7252 | do_rd_rm_rn (void) | |
7253 | { | |
9a64e435 | 7254 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7255 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7256 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7257 | { |
7258 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7259 | _("Rn must not overlap other operands")); | |
7260 | ||
7261 | /* SWP{b} is deprecated for ARMv6* and ARMv7. */ | |
7262 | if (warn_on_deprecated | |
7263 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7264 | as_warn (_("swp{b} use is deprecated for this architecture")); | |
7265 | ||
7266 | } | |
c19d1205 ZW |
7267 | inst.instruction |= inst.operands[0].reg << 12; |
7268 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7269 | inst.instruction |= Rn << 16; |
c19d1205 | 7270 | } |
09d92015 | 7271 | |
c19d1205 ZW |
7272 | static void |
7273 | do_rd_rn_rm (void) | |
7274 | { | |
7275 | inst.instruction |= inst.operands[0].reg << 12; | |
7276 | inst.instruction |= inst.operands[1].reg << 16; | |
7277 | inst.instruction |= inst.operands[2].reg; | |
7278 | } | |
a737bd4d | 7279 | |
c19d1205 ZW |
7280 | static void |
7281 | do_rm_rd_rn (void) | |
7282 | { | |
5be8be5d DG |
7283 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7284 | constraint (((inst.reloc.exp.X_op != O_constant | |
7285 | && inst.reloc.exp.X_op != O_illegal) | |
7286 | || inst.reloc.exp.X_add_number != 0), | |
7287 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7288 | inst.instruction |= inst.operands[0].reg; |
7289 | inst.instruction |= inst.operands[1].reg << 12; | |
7290 | inst.instruction |= inst.operands[2].reg << 16; | |
7291 | } | |
09d92015 | 7292 | |
c19d1205 ZW |
7293 | static void |
7294 | do_imm0 (void) | |
7295 | { | |
7296 | inst.instruction |= inst.operands[0].imm; | |
7297 | } | |
09d92015 | 7298 | |
c19d1205 ZW |
7299 | static void |
7300 | do_rd_cpaddr (void) | |
7301 | { | |
7302 | inst.instruction |= inst.operands[0].reg << 12; | |
7303 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7304 | } |
a737bd4d | 7305 | |
c19d1205 ZW |
7306 | /* ARM instructions, in alphabetical order by function name (except |
7307 | that wrapper functions appear immediately after the function they | |
7308 | wrap). */ | |
09d92015 | 7309 | |
c19d1205 ZW |
7310 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7311 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7312 | |
7313 | static void | |
c19d1205 | 7314 | do_adr (void) |
09d92015 | 7315 | { |
c19d1205 | 7316 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7317 | |
c19d1205 ZW |
7318 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7319 | out to be negative. */ | |
7320 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7321 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7322 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7323 | } |
b99bd4ef | 7324 | |
c19d1205 ZW |
7325 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7326 | into a relative address of the form: | |
7327 | add rd, pc, #low(label-.-8)" | |
7328 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7329 | |
c19d1205 ZW |
7330 | static void |
7331 | do_adrl (void) | |
7332 | { | |
7333 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7334 | |
c19d1205 ZW |
7335 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7336 | out to be negative. */ | |
7337 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7338 | inst.reloc.pc_rel = 1; |
7339 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7340 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7341 | } |
7342 | ||
b99bd4ef | 7343 | static void |
c19d1205 | 7344 | do_arit (void) |
b99bd4ef | 7345 | { |
c19d1205 ZW |
7346 | if (!inst.operands[1].present) |
7347 | inst.operands[1].reg = inst.operands[0].reg; | |
7348 | inst.instruction |= inst.operands[0].reg << 12; | |
7349 | inst.instruction |= inst.operands[1].reg << 16; | |
7350 | encode_arm_shifter_operand (2); | |
7351 | } | |
b99bd4ef | 7352 | |
62b3e311 PB |
7353 | static void |
7354 | do_barrier (void) | |
7355 | { | |
7356 | if (inst.operands[0].present) | |
7357 | { | |
7358 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
7359 | && inst.operands[0].imm > 0xf |
7360 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 7361 | _("bad barrier type")); |
62b3e311 PB |
7362 | inst.instruction |= inst.operands[0].imm; |
7363 | } | |
7364 | else | |
7365 | inst.instruction |= 0xf; | |
7366 | } | |
7367 | ||
c19d1205 ZW |
7368 | static void |
7369 | do_bfc (void) | |
7370 | { | |
7371 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7372 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7373 | /* The instruction encoding stores the LSB and MSB, | |
7374 | not the LSB and width. */ | |
7375 | inst.instruction |= inst.operands[0].reg << 12; | |
7376 | inst.instruction |= inst.operands[1].imm << 7; | |
7377 | inst.instruction |= (msb - 1) << 16; | |
7378 | } | |
b99bd4ef | 7379 | |
c19d1205 ZW |
7380 | static void |
7381 | do_bfi (void) | |
7382 | { | |
7383 | unsigned int msb; | |
b99bd4ef | 7384 | |
c19d1205 ZW |
7385 | /* #0 in second position is alternative syntax for bfc, which is |
7386 | the same instruction but with REG_PC in the Rm field. */ | |
7387 | if (!inst.operands[1].isreg) | |
7388 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7389 | |
c19d1205 ZW |
7390 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7391 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7392 | /* The instruction encoding stores the LSB and MSB, | |
7393 | not the LSB and width. */ | |
7394 | inst.instruction |= inst.operands[0].reg << 12; | |
7395 | inst.instruction |= inst.operands[1].reg; | |
7396 | inst.instruction |= inst.operands[2].imm << 7; | |
7397 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7398 | } |
7399 | ||
b99bd4ef | 7400 | static void |
c19d1205 | 7401 | do_bfx (void) |
b99bd4ef | 7402 | { |
c19d1205 ZW |
7403 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7404 | _("bit-field extends past end of register")); | |
7405 | inst.instruction |= inst.operands[0].reg << 12; | |
7406 | inst.instruction |= inst.operands[1].reg; | |
7407 | inst.instruction |= inst.operands[2].imm << 7; | |
7408 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7409 | } | |
09d92015 | 7410 | |
c19d1205 ZW |
7411 | /* ARM V5 breakpoint instruction (argument parse) |
7412 | BKPT <16 bit unsigned immediate> | |
7413 | Instruction is not conditional. | |
7414 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7415 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7416 | |
c19d1205 ZW |
7417 | static void |
7418 | do_bkpt (void) | |
7419 | { | |
7420 | /* Top 12 of 16 bits to bits 19:8. */ | |
7421 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7422 | |
c19d1205 ZW |
7423 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7424 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7425 | } | |
09d92015 | 7426 | |
c19d1205 ZW |
7427 | static void |
7428 | encode_branch (int default_reloc) | |
7429 | { | |
7430 | if (inst.operands[0].hasreloc) | |
7431 | { | |
0855e32b NS |
7432 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
7433 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
7434 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
7435 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
7436 | ? BFD_RELOC_ARM_PLT32 | |
7437 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 7438 | } |
b99bd4ef | 7439 | else |
9ae92b05 | 7440 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 7441 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7442 | } |
7443 | ||
b99bd4ef | 7444 | static void |
c19d1205 | 7445 | do_branch (void) |
b99bd4ef | 7446 | { |
39b41c9c PB |
7447 | #ifdef OBJ_ELF |
7448 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7449 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7450 | else | |
7451 | #endif | |
7452 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7453 | } | |
7454 | ||
7455 | static void | |
7456 | do_bl (void) | |
7457 | { | |
7458 | #ifdef OBJ_ELF | |
7459 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7460 | { | |
7461 | if (inst.cond == COND_ALWAYS) | |
7462 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7463 | else | |
7464 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7465 | } | |
7466 | else | |
7467 | #endif | |
7468 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7469 | } |
b99bd4ef | 7470 | |
c19d1205 ZW |
7471 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7472 | BLX <target_addr> ie BLX(1) | |
7473 | BLX{<condition>} <Rm> ie BLX(2) | |
7474 | Unfortunately, there are two different opcodes for this mnemonic. | |
7475 | So, the insns[].value is not used, and the code here zaps values | |
7476 | into inst.instruction. | |
7477 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7478 | |
c19d1205 ZW |
7479 | static void |
7480 | do_blx (void) | |
7481 | { | |
7482 | if (inst.operands[0].isreg) | |
b99bd4ef | 7483 | { |
c19d1205 ZW |
7484 | /* Arg is a register; the opcode provided by insns[] is correct. |
7485 | It is not illegal to do "blx pc", just useless. */ | |
7486 | if (inst.operands[0].reg == REG_PC) | |
7487 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7488 | |
c19d1205 ZW |
7489 | inst.instruction |= inst.operands[0].reg; |
7490 | } | |
7491 | else | |
b99bd4ef | 7492 | { |
c19d1205 | 7493 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7494 | conditionally, and the opcode must be adjusted. |
7495 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7496 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7497 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7498 | inst.instruction = 0xfa000000; |
267bf995 | 7499 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7500 | } |
c19d1205 ZW |
7501 | } |
7502 | ||
7503 | static void | |
7504 | do_bx (void) | |
7505 | { | |
845b51d6 PB |
7506 | bfd_boolean want_reloc; |
7507 | ||
c19d1205 ZW |
7508 | if (inst.operands[0].reg == REG_PC) |
7509 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7510 | |
c19d1205 | 7511 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7512 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7513 | it is for ARMv4t or earlier. */ | |
7514 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7515 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7516 | want_reloc = TRUE; | |
7517 | ||
5ad34203 | 7518 | #ifdef OBJ_ELF |
845b51d6 | 7519 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7520 | #endif |
584206db | 7521 | want_reloc = FALSE; |
845b51d6 PB |
7522 | |
7523 | if (want_reloc) | |
7524 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7525 | } |
7526 | ||
c19d1205 ZW |
7527 | |
7528 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7529 | |
7530 | static void | |
c19d1205 | 7531 | do_bxj (void) |
a737bd4d | 7532 | { |
c19d1205 ZW |
7533 | if (inst.operands[0].reg == REG_PC) |
7534 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7535 | ||
7536 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7537 | } |
7538 | ||
c19d1205 ZW |
7539 | /* Co-processor data operation: |
7540 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7541 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7542 | static void | |
7543 | do_cdp (void) | |
7544 | { | |
7545 | inst.instruction |= inst.operands[0].reg << 8; | |
7546 | inst.instruction |= inst.operands[1].imm << 20; | |
7547 | inst.instruction |= inst.operands[2].reg << 12; | |
7548 | inst.instruction |= inst.operands[3].reg << 16; | |
7549 | inst.instruction |= inst.operands[4].reg; | |
7550 | inst.instruction |= inst.operands[5].imm << 5; | |
7551 | } | |
a737bd4d NC |
7552 | |
7553 | static void | |
c19d1205 | 7554 | do_cmp (void) |
a737bd4d | 7555 | { |
c19d1205 ZW |
7556 | inst.instruction |= inst.operands[0].reg << 16; |
7557 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7558 | } |
7559 | ||
c19d1205 ZW |
7560 | /* Transfer between coprocessor and ARM registers. |
7561 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7562 | MRC2 | |
7563 | MCR{cond} | |
7564 | MCR2 | |
7565 | ||
7566 | No special properties. */ | |
09d92015 MM |
7567 | |
7568 | static void | |
c19d1205 | 7569 | do_co_reg (void) |
09d92015 | 7570 | { |
fdfde340 JM |
7571 | unsigned Rd; |
7572 | ||
7573 | Rd = inst.operands[2].reg; | |
7574 | if (thumb_mode) | |
7575 | { | |
7576 | if (inst.instruction == 0xee000010 | |
7577 | || inst.instruction == 0xfe000010) | |
7578 | /* MCR, MCR2 */ | |
7579 | reject_bad_reg (Rd); | |
7580 | else | |
7581 | /* MRC, MRC2 */ | |
7582 | constraint (Rd == REG_SP, BAD_SP); | |
7583 | } | |
7584 | else | |
7585 | { | |
7586 | /* MCR */ | |
7587 | if (inst.instruction == 0xe000010) | |
7588 | constraint (Rd == REG_PC, BAD_PC); | |
7589 | } | |
7590 | ||
7591 | ||
c19d1205 ZW |
7592 | inst.instruction |= inst.operands[0].reg << 8; |
7593 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7594 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7595 | inst.instruction |= inst.operands[3].reg << 16; |
7596 | inst.instruction |= inst.operands[4].reg; | |
7597 | inst.instruction |= inst.operands[5].imm << 5; | |
7598 | } | |
09d92015 | 7599 | |
c19d1205 ZW |
7600 | /* Transfer between coprocessor register and pair of ARM registers. |
7601 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7602 | MCRR2 | |
7603 | MRRC{cond} | |
7604 | MRRC2 | |
b99bd4ef | 7605 | |
c19d1205 | 7606 | Two XScale instructions are special cases of these: |
09d92015 | 7607 | |
c19d1205 ZW |
7608 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7609 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7610 | |
5f4273c7 | 7611 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7612 | |
c19d1205 ZW |
7613 | static void |
7614 | do_co_reg2c (void) | |
7615 | { | |
fdfde340 JM |
7616 | unsigned Rd, Rn; |
7617 | ||
7618 | Rd = inst.operands[2].reg; | |
7619 | Rn = inst.operands[3].reg; | |
7620 | ||
7621 | if (thumb_mode) | |
7622 | { | |
7623 | reject_bad_reg (Rd); | |
7624 | reject_bad_reg (Rn); | |
7625 | } | |
7626 | else | |
7627 | { | |
7628 | constraint (Rd == REG_PC, BAD_PC); | |
7629 | constraint (Rn == REG_PC, BAD_PC); | |
7630 | } | |
7631 | ||
c19d1205 ZW |
7632 | inst.instruction |= inst.operands[0].reg << 8; |
7633 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7634 | inst.instruction |= Rd << 12; |
7635 | inst.instruction |= Rn << 16; | |
c19d1205 | 7636 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7637 | } |
7638 | ||
c19d1205 ZW |
7639 | static void |
7640 | do_cpsi (void) | |
7641 | { | |
7642 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7643 | if (inst.operands[1].present) |
7644 | { | |
7645 | inst.instruction |= CPSI_MMOD; | |
7646 | inst.instruction |= inst.operands[1].imm; | |
7647 | } | |
c19d1205 | 7648 | } |
b99bd4ef | 7649 | |
62b3e311 PB |
7650 | static void |
7651 | do_dbg (void) | |
7652 | { | |
7653 | inst.instruction |= inst.operands[0].imm; | |
7654 | } | |
7655 | ||
eea54501 MGD |
7656 | static void |
7657 | do_div (void) | |
7658 | { | |
7659 | unsigned Rd, Rn, Rm; | |
7660 | ||
7661 | Rd = inst.operands[0].reg; | |
7662 | Rn = (inst.operands[1].present | |
7663 | ? inst.operands[1].reg : Rd); | |
7664 | Rm = inst.operands[2].reg; | |
7665 | ||
7666 | constraint ((Rd == REG_PC), BAD_PC); | |
7667 | constraint ((Rn == REG_PC), BAD_PC); | |
7668 | constraint ((Rm == REG_PC), BAD_PC); | |
7669 | ||
7670 | inst.instruction |= Rd << 16; | |
7671 | inst.instruction |= Rn << 0; | |
7672 | inst.instruction |= Rm << 8; | |
7673 | } | |
7674 | ||
b99bd4ef | 7675 | static void |
c19d1205 | 7676 | do_it (void) |
b99bd4ef | 7677 | { |
c19d1205 | 7678 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7679 | process it to do the validation as if in |
7680 | thumb mode, just in case the code gets | |
7681 | assembled for thumb using the unified syntax. */ | |
7682 | ||
c19d1205 | 7683 | inst.size = 0; |
e07e6e58 NC |
7684 | if (unified_syntax) |
7685 | { | |
7686 | set_it_insn_type (IT_INSN); | |
7687 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7688 | now_it.cc = inst.operands[0].imm; | |
7689 | } | |
09d92015 | 7690 | } |
b99bd4ef | 7691 | |
09d92015 | 7692 | static void |
c19d1205 | 7693 | do_ldmstm (void) |
ea6ef066 | 7694 | { |
c19d1205 ZW |
7695 | int base_reg = inst.operands[0].reg; |
7696 | int range = inst.operands[1].imm; | |
ea6ef066 | 7697 | |
c19d1205 ZW |
7698 | inst.instruction |= base_reg << 16; |
7699 | inst.instruction |= range; | |
ea6ef066 | 7700 | |
c19d1205 ZW |
7701 | if (inst.operands[1].writeback) |
7702 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7703 | |
c19d1205 | 7704 | if (inst.operands[0].writeback) |
ea6ef066 | 7705 | { |
c19d1205 ZW |
7706 | inst.instruction |= WRITE_BACK; |
7707 | /* Check for unpredictable uses of writeback. */ | |
7708 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7709 | { |
c19d1205 ZW |
7710 | /* Not allowed in LDM type 2. */ |
7711 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7712 | && ((range & (1 << REG_PC)) == 0)) | |
7713 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7714 | /* Only allowed if base reg not in list for other types. */ | |
7715 | else if (range & (1 << base_reg)) | |
7716 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7717 | } | |
7718 | else /* STM. */ | |
7719 | { | |
7720 | /* Not allowed for type 2. */ | |
7721 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7722 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7723 | /* Only allowed if base reg not in list, or first in list. */ | |
7724 | else if ((range & (1 << base_reg)) | |
7725 | && (range & ((1 << base_reg) - 1))) | |
7726 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7727 | } |
ea6ef066 | 7728 | } |
a737bd4d NC |
7729 | } |
7730 | ||
c19d1205 ZW |
7731 | /* ARMv5TE load-consecutive (argument parse) |
7732 | Mode is like LDRH. | |
7733 | ||
7734 | LDRccD R, mode | |
7735 | STRccD R, mode. */ | |
7736 | ||
a737bd4d | 7737 | static void |
c19d1205 | 7738 | do_ldrd (void) |
a737bd4d | 7739 | { |
c19d1205 ZW |
7740 | constraint (inst.operands[0].reg % 2 != 0, |
7741 | _("first destination register must be even")); | |
7742 | constraint (inst.operands[1].present | |
7743 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7744 | _("can only load two consecutive registers")); | |
7745 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
7746 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7747 | |
c19d1205 ZW |
7748 | if (!inst.operands[1].present) |
7749 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7750 | |
c19d1205 | 7751 | if (inst.instruction & LOAD_BIT) |
a737bd4d | 7752 | { |
c19d1205 ZW |
7753 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7754 | register and the first register written; we have to diagnose | |
7755 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7756 | |
c19d1205 ZW |
7757 | if (inst.operands[2].reg == inst.operands[1].reg |
7758 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7759 | as_warn (_("base register written back, and overlaps " | |
7760 | "second destination register")); | |
b05fe5cf | 7761 | |
c19d1205 ZW |
7762 | /* For an index-register load, the index register must not overlap the |
7763 | destination (even if not write-back). */ | |
7764 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
7765 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
7766 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 7767 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 7768 | } |
c19d1205 ZW |
7769 | |
7770 | inst.instruction |= inst.operands[0].reg << 12; | |
7771 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7772 | } |
7773 | ||
7774 | static void | |
c19d1205 | 7775 | do_ldrex (void) |
b05fe5cf | 7776 | { |
c19d1205 ZW |
7777 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7778 | || inst.operands[1].postind || inst.operands[1].writeback | |
7779 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7780 | || inst.operands[1].negative |
7781 | /* This can arise if the programmer has written | |
7782 | strex rN, rM, foo | |
7783 | or if they have mistakenly used a register name as the last | |
7784 | operand, eg: | |
7785 | strex rN, rM, rX | |
7786 | It is very difficult to distinguish between these two cases | |
7787 | because "rX" might actually be a label. ie the register | |
7788 | name has been occluded by a symbol of the same name. So we | |
7789 | just generate a general 'bad addressing mode' type error | |
7790 | message and leave it up to the programmer to discover the | |
7791 | true cause and fix their mistake. */ | |
7792 | || (inst.operands[1].reg == REG_PC), | |
7793 | BAD_ADDR_MODE); | |
b05fe5cf | 7794 | |
c19d1205 ZW |
7795 | constraint (inst.reloc.exp.X_op != O_constant |
7796 | || inst.reloc.exp.X_add_number != 0, | |
7797 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7798 | |
5be8be5d DG |
7799 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
7800 | ||
c19d1205 ZW |
7801 | inst.instruction |= inst.operands[0].reg << 12; |
7802 | inst.instruction |= inst.operands[1].reg << 16; | |
7803 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7804 | } |
7805 | ||
7806 | static void | |
c19d1205 | 7807 | do_ldrexd (void) |
b05fe5cf | 7808 | { |
c19d1205 ZW |
7809 | constraint (inst.operands[0].reg % 2 != 0, |
7810 | _("even register required")); | |
7811 | constraint (inst.operands[1].present | |
7812 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7813 | _("can only load two consecutive registers")); | |
7814 | /* If op 1 were present and equal to PC, this function wouldn't | |
7815 | have been called in the first place. */ | |
7816 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7817 | |
c19d1205 ZW |
7818 | inst.instruction |= inst.operands[0].reg << 12; |
7819 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7820 | } |
7821 | ||
7822 | static void | |
c19d1205 | 7823 | do_ldst (void) |
b05fe5cf | 7824 | { |
c19d1205 ZW |
7825 | inst.instruction |= inst.operands[0].reg << 12; |
7826 | if (!inst.operands[1].isreg) | |
7827 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7828 | return; |
c19d1205 | 7829 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7830 | } |
7831 | ||
7832 | static void | |
c19d1205 | 7833 | do_ldstt (void) |
b05fe5cf | 7834 | { |
c19d1205 ZW |
7835 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7836 | reject [Rn,...]. */ | |
7837 | if (inst.operands[1].preind) | |
b05fe5cf | 7838 | { |
bd3ba5d1 NC |
7839 | constraint (inst.reloc.exp.X_op != O_constant |
7840 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7841 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7842 | |
c19d1205 ZW |
7843 | inst.operands[1].preind = 0; |
7844 | inst.operands[1].postind = 1; | |
7845 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7846 | } |
c19d1205 ZW |
7847 | inst.instruction |= inst.operands[0].reg << 12; |
7848 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7849 | } | |
b05fe5cf | 7850 | |
c19d1205 | 7851 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7852 | |
c19d1205 ZW |
7853 | static void |
7854 | do_ldstv4 (void) | |
7855 | { | |
ff4a8d2b | 7856 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7857 | inst.instruction |= inst.operands[0].reg << 12; |
7858 | if (!inst.operands[1].isreg) | |
7859 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7860 | return; |
c19d1205 | 7861 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7862 | } |
7863 | ||
7864 | static void | |
c19d1205 | 7865 | do_ldsttv4 (void) |
b05fe5cf | 7866 | { |
c19d1205 ZW |
7867 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7868 | reject [Rn,...]. */ | |
7869 | if (inst.operands[1].preind) | |
b05fe5cf | 7870 | { |
bd3ba5d1 NC |
7871 | constraint (inst.reloc.exp.X_op != O_constant |
7872 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7873 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7874 | |
c19d1205 ZW |
7875 | inst.operands[1].preind = 0; |
7876 | inst.operands[1].postind = 1; | |
7877 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7878 | } |
c19d1205 ZW |
7879 | inst.instruction |= inst.operands[0].reg << 12; |
7880 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7881 | } | |
b05fe5cf | 7882 | |
c19d1205 ZW |
7883 | /* Co-processor register load/store. |
7884 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
7885 | static void | |
7886 | do_lstc (void) | |
7887 | { | |
7888 | inst.instruction |= inst.operands[0].reg << 8; | |
7889 | inst.instruction |= inst.operands[1].reg << 12; | |
7890 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
7891 | } |
7892 | ||
b05fe5cf | 7893 | static void |
c19d1205 | 7894 | do_mlas (void) |
b05fe5cf | 7895 | { |
8fb9d7b9 | 7896 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 7897 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 7898 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 7899 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 7900 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 7901 | |
c19d1205 ZW |
7902 | inst.instruction |= inst.operands[0].reg << 16; |
7903 | inst.instruction |= inst.operands[1].reg; | |
7904 | inst.instruction |= inst.operands[2].reg << 8; | |
7905 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 7906 | } |
b05fe5cf | 7907 | |
c19d1205 ZW |
7908 | static void |
7909 | do_mov (void) | |
7910 | { | |
7911 | inst.instruction |= inst.operands[0].reg << 12; | |
7912 | encode_arm_shifter_operand (1); | |
7913 | } | |
b05fe5cf | 7914 | |
c19d1205 ZW |
7915 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
7916 | static void | |
7917 | do_mov16 (void) | |
7918 | { | |
b6895b4f PB |
7919 | bfd_vma imm; |
7920 | bfd_boolean top; | |
7921 | ||
7922 | top = (inst.instruction & 0x00400000) != 0; | |
7923 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
7924 | _(":lower16: not allowed this instruction")); | |
7925 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7926 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7927 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7928 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7929 | { | |
7930 | imm = inst.reloc.exp.X_add_number; | |
7931 | /* The value is in two pieces: 0:11, 16:19. */ | |
7932 | inst.instruction |= (imm & 0x00000fff); | |
7933 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7934 | } | |
b05fe5cf | 7935 | } |
b99bd4ef | 7936 | |
037e8744 JB |
7937 | static void do_vfp_nsyn_opcode (const char *); |
7938 | ||
7939 | static int | |
7940 | do_vfp_nsyn_mrs (void) | |
7941 | { | |
7942 | if (inst.operands[0].isvec) | |
7943 | { | |
7944 | if (inst.operands[1].reg != 1) | |
7945 | first_error (_("operand 1 must be FPSCR")); | |
7946 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
7947 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
7948 | do_vfp_nsyn_opcode ("fmstat"); | |
7949 | } | |
7950 | else if (inst.operands[1].isvec) | |
7951 | do_vfp_nsyn_opcode ("fmrx"); | |
7952 | else | |
7953 | return FAIL; | |
5f4273c7 | 7954 | |
037e8744 JB |
7955 | return SUCCESS; |
7956 | } | |
7957 | ||
7958 | static int | |
7959 | do_vfp_nsyn_msr (void) | |
7960 | { | |
7961 | if (inst.operands[0].isvec) | |
7962 | do_vfp_nsyn_opcode ("fmxr"); | |
7963 | else | |
7964 | return FAIL; | |
7965 | ||
7966 | return SUCCESS; | |
7967 | } | |
7968 | ||
f7c21dc7 NC |
7969 | static void |
7970 | do_vmrs (void) | |
7971 | { | |
7972 | unsigned Rt = inst.operands[0].reg; | |
7973 | ||
7974 | if (thumb_mode && inst.operands[0].reg == REG_SP) | |
7975 | { | |
7976 | inst.error = BAD_SP; | |
7977 | return; | |
7978 | } | |
7979 | ||
7980 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
7981 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
7982 | { | |
7983 | inst.error = BAD_PC; | |
7984 | return; | |
7985 | } | |
7986 | ||
7987 | if (inst.operands[1].reg != 1) | |
7988 | first_error (_("operand 1 must be FPSCR")); | |
7989 | ||
7990 | inst.instruction |= (Rt << 12); | |
7991 | } | |
7992 | ||
7993 | static void | |
7994 | do_vmsr (void) | |
7995 | { | |
7996 | unsigned Rt = inst.operands[1].reg; | |
7997 | ||
7998 | if (thumb_mode) | |
7999 | reject_bad_reg (Rt); | |
8000 | else if (Rt == REG_PC) | |
8001 | { | |
8002 | inst.error = BAD_PC; | |
8003 | return; | |
8004 | } | |
8005 | ||
8006 | if (inst.operands[0].reg != 1) | |
8007 | first_error (_("operand 0 must be FPSCR")); | |
8008 | ||
8009 | inst.instruction |= (Rt << 12); | |
8010 | } | |
8011 | ||
b99bd4ef | 8012 | static void |
c19d1205 | 8013 | do_mrs (void) |
b99bd4ef | 8014 | { |
90ec0d68 MGD |
8015 | unsigned br; |
8016 | ||
037e8744 JB |
8017 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8018 | return; | |
8019 | ||
ff4a8d2b | 8020 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8021 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8022 | |
8023 | if (inst.operands[1].isreg) | |
8024 | { | |
8025 | br = inst.operands[1].reg; | |
8026 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8027 | as_bad (_("bad register for mrs")); | |
8028 | } | |
8029 | else | |
8030 | { | |
8031 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8032 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8033 | != (PSR_c|PSR_f), | |
d2cd1205 | 8034 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8035 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8036 | } | |
8037 | ||
8038 | inst.instruction |= br; | |
c19d1205 | 8039 | } |
b99bd4ef | 8040 | |
c19d1205 ZW |
8041 | /* Two possible forms: |
8042 | "{C|S}PSR_<field>, Rm", | |
8043 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8044 | |
c19d1205 ZW |
8045 | static void |
8046 | do_msr (void) | |
8047 | { | |
037e8744 JB |
8048 | if (do_vfp_nsyn_msr () == SUCCESS) |
8049 | return; | |
8050 | ||
c19d1205 ZW |
8051 | inst.instruction |= inst.operands[0].imm; |
8052 | if (inst.operands[1].isreg) | |
8053 | inst.instruction |= inst.operands[1].reg; | |
8054 | else | |
b99bd4ef | 8055 | { |
c19d1205 ZW |
8056 | inst.instruction |= INST_IMMEDIATE; |
8057 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8058 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8059 | } |
b99bd4ef NC |
8060 | } |
8061 | ||
c19d1205 ZW |
8062 | static void |
8063 | do_mul (void) | |
a737bd4d | 8064 | { |
ff4a8d2b NC |
8065 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8066 | ||
c19d1205 ZW |
8067 | if (!inst.operands[2].present) |
8068 | inst.operands[2].reg = inst.operands[0].reg; | |
8069 | inst.instruction |= inst.operands[0].reg << 16; | |
8070 | inst.instruction |= inst.operands[1].reg; | |
8071 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8072 | |
8fb9d7b9 MS |
8073 | if (inst.operands[0].reg == inst.operands[1].reg |
8074 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8075 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8076 | } |
8077 | ||
c19d1205 ZW |
8078 | /* Long Multiply Parser |
8079 | UMULL RdLo, RdHi, Rm, Rs | |
8080 | SMULL RdLo, RdHi, Rm, Rs | |
8081 | UMLAL RdLo, RdHi, Rm, Rs | |
8082 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8083 | |
8084 | static void | |
c19d1205 | 8085 | do_mull (void) |
b99bd4ef | 8086 | { |
c19d1205 ZW |
8087 | inst.instruction |= inst.operands[0].reg << 12; |
8088 | inst.instruction |= inst.operands[1].reg << 16; | |
8089 | inst.instruction |= inst.operands[2].reg; | |
8090 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8091 | |
682b27ad PB |
8092 | /* rdhi and rdlo must be different. */ |
8093 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8094 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8095 | ||
8096 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8097 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8098 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8099 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8100 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8101 | } | |
b99bd4ef | 8102 | |
c19d1205 ZW |
8103 | static void |
8104 | do_nop (void) | |
8105 | { | |
e7495e45 NS |
8106 | if (inst.operands[0].present |
8107 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8108 | { |
8109 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8110 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8111 | inst.instruction |= 0x0320f000; |
8112 | if (inst.operands[0].present) | |
8113 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8114 | } |
b99bd4ef NC |
8115 | } |
8116 | ||
c19d1205 ZW |
8117 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8118 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8119 | Condition defaults to COND_ALWAYS. | |
8120 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8121 | |
8122 | static void | |
c19d1205 | 8123 | do_pkhbt (void) |
b99bd4ef | 8124 | { |
c19d1205 ZW |
8125 | inst.instruction |= inst.operands[0].reg << 12; |
8126 | inst.instruction |= inst.operands[1].reg << 16; | |
8127 | inst.instruction |= inst.operands[2].reg; | |
8128 | if (inst.operands[3].present) | |
8129 | encode_arm_shift (3); | |
8130 | } | |
b99bd4ef | 8131 | |
c19d1205 | 8132 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8133 | |
c19d1205 ZW |
8134 | static void |
8135 | do_pkhtb (void) | |
8136 | { | |
8137 | if (!inst.operands[3].present) | |
b99bd4ef | 8138 | { |
c19d1205 ZW |
8139 | /* If the shift specifier is omitted, turn the instruction |
8140 | into pkhbt rd, rm, rn. */ | |
8141 | inst.instruction &= 0xfff00010; | |
8142 | inst.instruction |= inst.operands[0].reg << 12; | |
8143 | inst.instruction |= inst.operands[1].reg; | |
8144 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8145 | } |
8146 | else | |
8147 | { | |
c19d1205 ZW |
8148 | inst.instruction |= inst.operands[0].reg << 12; |
8149 | inst.instruction |= inst.operands[1].reg << 16; | |
8150 | inst.instruction |= inst.operands[2].reg; | |
8151 | encode_arm_shift (3); | |
b99bd4ef NC |
8152 | } |
8153 | } | |
8154 | ||
c19d1205 | 8155 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 8156 | MP Extensions: Preload for write |
c19d1205 | 8157 | |
60e5ef9f | 8158 | PLD(W) <addr_mode> |
c19d1205 ZW |
8159 | |
8160 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
8161 | |
8162 | static void | |
c19d1205 | 8163 | do_pld (void) |
b99bd4ef | 8164 | { |
c19d1205 ZW |
8165 | constraint (!inst.operands[0].isreg, |
8166 | _("'[' expected after PLD mnemonic")); | |
8167 | constraint (inst.operands[0].postind, | |
8168 | _("post-indexed expression used in preload instruction")); | |
8169 | constraint (inst.operands[0].writeback, | |
8170 | _("writeback used in preload instruction")); | |
8171 | constraint (!inst.operands[0].preind, | |
8172 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
8173 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
8174 | } | |
b99bd4ef | 8175 | |
62b3e311 PB |
8176 | /* ARMv7: PLI <addr_mode> */ |
8177 | static void | |
8178 | do_pli (void) | |
8179 | { | |
8180 | constraint (!inst.operands[0].isreg, | |
8181 | _("'[' expected after PLI mnemonic")); | |
8182 | constraint (inst.operands[0].postind, | |
8183 | _("post-indexed expression used in preload instruction")); | |
8184 | constraint (inst.operands[0].writeback, | |
8185 | _("writeback used in preload instruction")); | |
8186 | constraint (!inst.operands[0].preind, | |
8187 | _("unindexed addressing used in preload instruction")); | |
8188 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
8189 | inst.instruction &= ~PRE_INDEX; | |
8190 | } | |
8191 | ||
c19d1205 ZW |
8192 | static void |
8193 | do_push_pop (void) | |
8194 | { | |
8195 | inst.operands[1] = inst.operands[0]; | |
8196 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
8197 | inst.operands[0].isreg = 1; | |
8198 | inst.operands[0].writeback = 1; | |
8199 | inst.operands[0].reg = REG_SP; | |
8200 | do_ldmstm (); | |
8201 | } | |
b99bd4ef | 8202 | |
c19d1205 ZW |
8203 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
8204 | word at the specified address and the following word | |
8205 | respectively. | |
8206 | Unconditionally executed. | |
8207 | Error if Rn is R15. */ | |
b99bd4ef | 8208 | |
c19d1205 ZW |
8209 | static void |
8210 | do_rfe (void) | |
8211 | { | |
8212 | inst.instruction |= inst.operands[0].reg << 16; | |
8213 | if (inst.operands[0].writeback) | |
8214 | inst.instruction |= WRITE_BACK; | |
8215 | } | |
b99bd4ef | 8216 | |
c19d1205 | 8217 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 8218 | |
c19d1205 ZW |
8219 | static void |
8220 | do_ssat (void) | |
8221 | { | |
8222 | inst.instruction |= inst.operands[0].reg << 12; | |
8223 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
8224 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8225 | |
c19d1205 ZW |
8226 | if (inst.operands[3].present) |
8227 | encode_arm_shift (3); | |
b99bd4ef NC |
8228 | } |
8229 | ||
c19d1205 | 8230 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
8231 | |
8232 | static void | |
c19d1205 | 8233 | do_usat (void) |
b99bd4ef | 8234 | { |
c19d1205 ZW |
8235 | inst.instruction |= inst.operands[0].reg << 12; |
8236 | inst.instruction |= inst.operands[1].imm << 16; | |
8237 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8238 | |
c19d1205 ZW |
8239 | if (inst.operands[3].present) |
8240 | encode_arm_shift (3); | |
b99bd4ef NC |
8241 | } |
8242 | ||
c19d1205 | 8243 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
8244 | |
8245 | static void | |
c19d1205 | 8246 | do_ssat16 (void) |
09d92015 | 8247 | { |
c19d1205 ZW |
8248 | inst.instruction |= inst.operands[0].reg << 12; |
8249 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
8250 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
8251 | } |
8252 | ||
c19d1205 ZW |
8253 | static void |
8254 | do_usat16 (void) | |
a737bd4d | 8255 | { |
c19d1205 ZW |
8256 | inst.instruction |= inst.operands[0].reg << 12; |
8257 | inst.instruction |= inst.operands[1].imm << 16; | |
8258 | inst.instruction |= inst.operands[2].reg; | |
8259 | } | |
a737bd4d | 8260 | |
c19d1205 ZW |
8261 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
8262 | preserving the other bits. | |
a737bd4d | 8263 | |
c19d1205 ZW |
8264 | setend <endian_specifier>, where <endian_specifier> is either |
8265 | BE or LE. */ | |
a737bd4d | 8266 | |
c19d1205 ZW |
8267 | static void |
8268 | do_setend (void) | |
8269 | { | |
8270 | if (inst.operands[0].imm) | |
8271 | inst.instruction |= 0x200; | |
a737bd4d NC |
8272 | } |
8273 | ||
8274 | static void | |
c19d1205 | 8275 | do_shift (void) |
a737bd4d | 8276 | { |
c19d1205 ZW |
8277 | unsigned int Rm = (inst.operands[1].present |
8278 | ? inst.operands[1].reg | |
8279 | : inst.operands[0].reg); | |
a737bd4d | 8280 | |
c19d1205 ZW |
8281 | inst.instruction |= inst.operands[0].reg << 12; |
8282 | inst.instruction |= Rm; | |
8283 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8284 | { |
c19d1205 ZW |
8285 | inst.instruction |= inst.operands[2].reg << 8; |
8286 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
8287 | } |
8288 | else | |
c19d1205 | 8289 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8290 | } |
8291 | ||
09d92015 | 8292 | static void |
3eb17e6b | 8293 | do_smc (void) |
09d92015 | 8294 | { |
3eb17e6b | 8295 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8296 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8297 | } |
8298 | ||
90ec0d68 MGD |
8299 | static void |
8300 | do_hvc (void) | |
8301 | { | |
8302 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
8303 | inst.reloc.pc_rel = 0; | |
8304 | } | |
8305 | ||
09d92015 | 8306 | static void |
c19d1205 | 8307 | do_swi (void) |
09d92015 | 8308 | { |
c19d1205 ZW |
8309 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8310 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8311 | } |
8312 | ||
c19d1205 ZW |
8313 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8314 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8315 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8316 | Error if any register is R15. */ | |
e16bb312 | 8317 | |
c19d1205 ZW |
8318 | static void |
8319 | do_smla (void) | |
e16bb312 | 8320 | { |
c19d1205 ZW |
8321 | inst.instruction |= inst.operands[0].reg << 16; |
8322 | inst.instruction |= inst.operands[1].reg; | |
8323 | inst.instruction |= inst.operands[2].reg << 8; | |
8324 | inst.instruction |= inst.operands[3].reg << 12; | |
8325 | } | |
a737bd4d | 8326 | |
c19d1205 ZW |
8327 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8328 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8329 | Error if any register is R15. | |
8330 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8331 | |
c19d1205 ZW |
8332 | static void |
8333 | do_smlal (void) | |
8334 | { | |
8335 | inst.instruction |= inst.operands[0].reg << 12; | |
8336 | inst.instruction |= inst.operands[1].reg << 16; | |
8337 | inst.instruction |= inst.operands[2].reg; | |
8338 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8339 | |
c19d1205 ZW |
8340 | if (inst.operands[0].reg == inst.operands[1].reg) |
8341 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8342 | } | |
a737bd4d | 8343 | |
c19d1205 ZW |
8344 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8345 | SMULxy{cond} Rd,Rm,Rs | |
8346 | Error if any register is R15. */ | |
a737bd4d | 8347 | |
c19d1205 ZW |
8348 | static void |
8349 | do_smul (void) | |
8350 | { | |
8351 | inst.instruction |= inst.operands[0].reg << 16; | |
8352 | inst.instruction |= inst.operands[1].reg; | |
8353 | inst.instruction |= inst.operands[2].reg << 8; | |
8354 | } | |
a737bd4d | 8355 | |
b6702015 PB |
8356 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8357 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8358 | |
c19d1205 ZW |
8359 | static void |
8360 | do_srs (void) | |
8361 | { | |
b6702015 PB |
8362 | int reg; |
8363 | ||
8364 | if (inst.operands[0].present) | |
8365 | { | |
8366 | reg = inst.operands[0].reg; | |
fdfde340 | 8367 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8368 | } |
8369 | else | |
fdfde340 | 8370 | reg = REG_SP; |
b6702015 PB |
8371 | |
8372 | inst.instruction |= reg << 16; | |
8373 | inst.instruction |= inst.operands[1].imm; | |
8374 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8375 | inst.instruction |= WRITE_BACK; |
8376 | } | |
a737bd4d | 8377 | |
c19d1205 | 8378 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8379 | |
c19d1205 ZW |
8380 | static void |
8381 | do_strex (void) | |
8382 | { | |
8383 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8384 | || inst.operands[2].postind || inst.operands[2].writeback | |
8385 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8386 | || inst.operands[2].negative |
8387 | /* See comment in do_ldrex(). */ | |
8388 | || (inst.operands[2].reg == REG_PC), | |
8389 | BAD_ADDR_MODE); | |
a737bd4d | 8390 | |
c19d1205 ZW |
8391 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8392 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8393 | |
c19d1205 ZW |
8394 | constraint (inst.reloc.exp.X_op != O_constant |
8395 | || inst.reloc.exp.X_add_number != 0, | |
8396 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8397 | |
c19d1205 ZW |
8398 | inst.instruction |= inst.operands[0].reg << 12; |
8399 | inst.instruction |= inst.operands[1].reg; | |
8400 | inst.instruction |= inst.operands[2].reg << 16; | |
8401 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8402 | } |
8403 | ||
8404 | static void | |
c19d1205 | 8405 | do_strexd (void) |
e16bb312 | 8406 | { |
c19d1205 ZW |
8407 | constraint (inst.operands[1].reg % 2 != 0, |
8408 | _("even register required")); | |
8409 | constraint (inst.operands[2].present | |
8410 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8411 | _("can only store two consecutive registers")); | |
8412 | /* If op 2 were present and equal to PC, this function wouldn't | |
8413 | have been called in the first place. */ | |
8414 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8415 | |
c19d1205 ZW |
8416 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8417 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8418 | || inst.operands[0].reg == inst.operands[3].reg, | |
8419 | BAD_OVERLAP); | |
e16bb312 | 8420 | |
c19d1205 ZW |
8421 | inst.instruction |= inst.operands[0].reg << 12; |
8422 | inst.instruction |= inst.operands[1].reg; | |
8423 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8424 | } |
8425 | ||
c19d1205 ZW |
8426 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8427 | extends it to 32-bits, and adds the result to a value in another | |
8428 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8429 | before extracting the 16-bit value. | |
8430 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8431 | Condition defaults to COND_ALWAYS. | |
8432 | Error if any register uses R15. */ | |
8433 | ||
e16bb312 | 8434 | static void |
c19d1205 | 8435 | do_sxtah (void) |
e16bb312 | 8436 | { |
c19d1205 ZW |
8437 | inst.instruction |= inst.operands[0].reg << 12; |
8438 | inst.instruction |= inst.operands[1].reg << 16; | |
8439 | inst.instruction |= inst.operands[2].reg; | |
8440 | inst.instruction |= inst.operands[3].imm << 10; | |
8441 | } | |
e16bb312 | 8442 | |
c19d1205 | 8443 | /* ARM V6 SXTH. |
e16bb312 | 8444 | |
c19d1205 ZW |
8445 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8446 | Condition defaults to COND_ALWAYS. | |
8447 | Error if any register uses R15. */ | |
e16bb312 NC |
8448 | |
8449 | static void | |
c19d1205 | 8450 | do_sxth (void) |
e16bb312 | 8451 | { |
c19d1205 ZW |
8452 | inst.instruction |= inst.operands[0].reg << 12; |
8453 | inst.instruction |= inst.operands[1].reg; | |
8454 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8455 | } |
c19d1205 ZW |
8456 | \f |
8457 | /* VFP instructions. In a logical order: SP variant first, monad | |
8458 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8459 | |
8460 | static void | |
c19d1205 | 8461 | do_vfp_sp_monadic (void) |
e16bb312 | 8462 | { |
5287ad62 JB |
8463 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8464 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8465 | } |
8466 | ||
8467 | static void | |
c19d1205 | 8468 | do_vfp_sp_dyadic (void) |
e16bb312 | 8469 | { |
5287ad62 JB |
8470 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8471 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8472 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8473 | } |
8474 | ||
8475 | static void | |
c19d1205 | 8476 | do_vfp_sp_compare_z (void) |
e16bb312 | 8477 | { |
5287ad62 | 8478 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8479 | } |
8480 | ||
8481 | static void | |
c19d1205 | 8482 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8483 | { |
5287ad62 JB |
8484 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8485 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8486 | } |
8487 | ||
8488 | static void | |
c19d1205 | 8489 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8490 | { |
5287ad62 JB |
8491 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8492 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8493 | } |
8494 | ||
8495 | static void | |
c19d1205 | 8496 | do_vfp_reg_from_sp (void) |
e16bb312 | 8497 | { |
c19d1205 | 8498 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8499 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8500 | } |
8501 | ||
8502 | static void | |
c19d1205 | 8503 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8504 | { |
c19d1205 ZW |
8505 | constraint (inst.operands[2].imm != 2, |
8506 | _("only two consecutive VFP SP registers allowed here")); | |
8507 | inst.instruction |= inst.operands[0].reg << 12; | |
8508 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8509 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8510 | } |
8511 | ||
8512 | static void | |
c19d1205 | 8513 | do_vfp_sp_from_reg (void) |
e16bb312 | 8514 | { |
5287ad62 | 8515 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8516 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8517 | } |
8518 | ||
8519 | static void | |
c19d1205 | 8520 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8521 | { |
c19d1205 ZW |
8522 | constraint (inst.operands[0].imm != 2, |
8523 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8524 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8525 | inst.instruction |= inst.operands[1].reg << 12; |
8526 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8527 | } |
8528 | ||
8529 | static void | |
c19d1205 | 8530 | do_vfp_sp_ldst (void) |
e16bb312 | 8531 | { |
5287ad62 | 8532 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8533 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8534 | } |
8535 | ||
8536 | static void | |
c19d1205 | 8537 | do_vfp_dp_ldst (void) |
e16bb312 | 8538 | { |
5287ad62 | 8539 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8540 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8541 | } |
8542 | ||
c19d1205 | 8543 | |
e16bb312 | 8544 | static void |
c19d1205 | 8545 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8546 | { |
c19d1205 ZW |
8547 | if (inst.operands[0].writeback) |
8548 | inst.instruction |= WRITE_BACK; | |
8549 | else | |
8550 | constraint (ldstm_type != VFP_LDSTMIA, | |
8551 | _("this addressing mode requires base-register writeback")); | |
8552 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8553 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8554 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8555 | } |
8556 | ||
8557 | static void | |
c19d1205 | 8558 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8559 | { |
c19d1205 | 8560 | int count; |
e16bb312 | 8561 | |
c19d1205 ZW |
8562 | if (inst.operands[0].writeback) |
8563 | inst.instruction |= WRITE_BACK; | |
8564 | else | |
8565 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8566 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8567 | |
c19d1205 | 8568 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8569 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8570 | |
c19d1205 ZW |
8571 | count = inst.operands[1].imm << 1; |
8572 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8573 | count += 1; | |
e16bb312 | 8574 | |
c19d1205 | 8575 | inst.instruction |= count; |
e16bb312 NC |
8576 | } |
8577 | ||
8578 | static void | |
c19d1205 | 8579 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8580 | { |
c19d1205 | 8581 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8582 | } |
8583 | ||
8584 | static void | |
c19d1205 | 8585 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8586 | { |
c19d1205 | 8587 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8588 | } |
8589 | ||
8590 | static void | |
c19d1205 | 8591 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8592 | { |
c19d1205 | 8593 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8594 | } |
8595 | ||
8596 | static void | |
c19d1205 | 8597 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8598 | { |
c19d1205 | 8599 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8600 | } |
8601 | ||
8602 | static void | |
c19d1205 | 8603 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8604 | { |
c19d1205 ZW |
8605 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8606 | } | |
e16bb312 | 8607 | |
c19d1205 ZW |
8608 | static void |
8609 | do_vfp_xp_ldstmdb (void) | |
8610 | { | |
8611 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8612 | } |
5287ad62 JB |
8613 | |
8614 | static void | |
8615 | do_vfp_dp_rd_rm (void) | |
8616 | { | |
8617 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8618 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8619 | } | |
8620 | ||
8621 | static void | |
8622 | do_vfp_dp_rn_rd (void) | |
8623 | { | |
8624 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8625 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8626 | } | |
8627 | ||
8628 | static void | |
8629 | do_vfp_dp_rd_rn (void) | |
8630 | { | |
8631 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8632 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8633 | } | |
8634 | ||
8635 | static void | |
8636 | do_vfp_dp_rd_rn_rm (void) | |
8637 | { | |
8638 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8639 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8640 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8641 | } | |
8642 | ||
8643 | static void | |
8644 | do_vfp_dp_rd (void) | |
8645 | { | |
8646 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8647 | } | |
8648 | ||
8649 | static void | |
8650 | do_vfp_dp_rm_rd_rn (void) | |
8651 | { | |
8652 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8653 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8654 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8655 | } | |
8656 | ||
8657 | /* VFPv3 instructions. */ | |
8658 | static void | |
8659 | do_vfp_sp_const (void) | |
8660 | { | |
8661 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8662 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8663 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8664 | } |
8665 | ||
8666 | static void | |
8667 | do_vfp_dp_const (void) | |
8668 | { | |
8669 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8670 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8671 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8672 | } |
8673 | ||
8674 | static void | |
8675 | vfp_conv (int srcsize) | |
8676 | { | |
8677 | unsigned immbits = srcsize - inst.operands[1].imm; | |
8678 | inst.instruction |= (immbits & 1) << 5; | |
8679 | inst.instruction |= (immbits >> 1); | |
8680 | } | |
8681 | ||
8682 | static void | |
8683 | do_vfp_sp_conv_16 (void) | |
8684 | { | |
8685 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8686 | vfp_conv (16); | |
8687 | } | |
8688 | ||
8689 | static void | |
8690 | do_vfp_dp_conv_16 (void) | |
8691 | { | |
8692 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8693 | vfp_conv (16); | |
8694 | } | |
8695 | ||
8696 | static void | |
8697 | do_vfp_sp_conv_32 (void) | |
8698 | { | |
8699 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8700 | vfp_conv (32); | |
8701 | } | |
8702 | ||
8703 | static void | |
8704 | do_vfp_dp_conv_32 (void) | |
8705 | { | |
8706 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8707 | vfp_conv (32); | |
8708 | } | |
c19d1205 ZW |
8709 | \f |
8710 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8711 | |
c19d1205 ZW |
8712 | static void |
8713 | do_fpa_cmp (void) | |
8714 | { | |
8715 | inst.instruction |= inst.operands[0].reg << 16; | |
8716 | inst.instruction |= inst.operands[1].reg; | |
8717 | } | |
b99bd4ef NC |
8718 | |
8719 | static void | |
c19d1205 | 8720 | do_fpa_ldmstm (void) |
b99bd4ef | 8721 | { |
c19d1205 ZW |
8722 | inst.instruction |= inst.operands[0].reg << 12; |
8723 | switch (inst.operands[1].imm) | |
8724 | { | |
8725 | case 1: inst.instruction |= CP_T_X; break; | |
8726 | case 2: inst.instruction |= CP_T_Y; break; | |
8727 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8728 | case 4: break; | |
8729 | default: abort (); | |
8730 | } | |
b99bd4ef | 8731 | |
c19d1205 ZW |
8732 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8733 | { | |
8734 | /* The instruction specified "ea" or "fd", so we can only accept | |
8735 | [Rn]{!}. The instruction does not really support stacking or | |
8736 | unstacking, so we have to emulate these by setting appropriate | |
8737 | bits and offsets. */ | |
8738 | constraint (inst.reloc.exp.X_op != O_constant | |
8739 | || inst.reloc.exp.X_add_number != 0, | |
8740 | _("this instruction does not support indexing")); | |
b99bd4ef | 8741 | |
c19d1205 ZW |
8742 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8743 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8744 | |
c19d1205 ZW |
8745 | if (!(inst.instruction & INDEX_UP)) |
8746 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8747 | |
c19d1205 ZW |
8748 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8749 | { | |
8750 | inst.operands[2].preind = 0; | |
8751 | inst.operands[2].postind = 1; | |
8752 | } | |
8753 | } | |
b99bd4ef | 8754 | |
c19d1205 | 8755 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8756 | } |
c19d1205 ZW |
8757 | \f |
8758 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8759 | |
c19d1205 ZW |
8760 | static void |
8761 | do_iwmmxt_tandorc (void) | |
8762 | { | |
8763 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8764 | } | |
b99bd4ef | 8765 | |
c19d1205 ZW |
8766 | static void |
8767 | do_iwmmxt_textrc (void) | |
8768 | { | |
8769 | inst.instruction |= inst.operands[0].reg << 12; | |
8770 | inst.instruction |= inst.operands[1].imm; | |
8771 | } | |
b99bd4ef NC |
8772 | |
8773 | static void | |
c19d1205 | 8774 | do_iwmmxt_textrm (void) |
b99bd4ef | 8775 | { |
c19d1205 ZW |
8776 | inst.instruction |= inst.operands[0].reg << 12; |
8777 | inst.instruction |= inst.operands[1].reg << 16; | |
8778 | inst.instruction |= inst.operands[2].imm; | |
8779 | } | |
b99bd4ef | 8780 | |
c19d1205 ZW |
8781 | static void |
8782 | do_iwmmxt_tinsr (void) | |
8783 | { | |
8784 | inst.instruction |= inst.operands[0].reg << 16; | |
8785 | inst.instruction |= inst.operands[1].reg << 12; | |
8786 | inst.instruction |= inst.operands[2].imm; | |
8787 | } | |
b99bd4ef | 8788 | |
c19d1205 ZW |
8789 | static void |
8790 | do_iwmmxt_tmia (void) | |
8791 | { | |
8792 | inst.instruction |= inst.operands[0].reg << 5; | |
8793 | inst.instruction |= inst.operands[1].reg; | |
8794 | inst.instruction |= inst.operands[2].reg << 12; | |
8795 | } | |
b99bd4ef | 8796 | |
c19d1205 ZW |
8797 | static void |
8798 | do_iwmmxt_waligni (void) | |
8799 | { | |
8800 | inst.instruction |= inst.operands[0].reg << 12; | |
8801 | inst.instruction |= inst.operands[1].reg << 16; | |
8802 | inst.instruction |= inst.operands[2].reg; | |
8803 | inst.instruction |= inst.operands[3].imm << 20; | |
8804 | } | |
b99bd4ef | 8805 | |
2d447fca JM |
8806 | static void |
8807 | do_iwmmxt_wmerge (void) | |
8808 | { | |
8809 | inst.instruction |= inst.operands[0].reg << 12; | |
8810 | inst.instruction |= inst.operands[1].reg << 16; | |
8811 | inst.instruction |= inst.operands[2].reg; | |
8812 | inst.instruction |= inst.operands[3].imm << 21; | |
8813 | } | |
8814 | ||
c19d1205 ZW |
8815 | static void |
8816 | do_iwmmxt_wmov (void) | |
8817 | { | |
8818 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8819 | inst.instruction |= inst.operands[0].reg << 12; | |
8820 | inst.instruction |= inst.operands[1].reg << 16; | |
8821 | inst.instruction |= inst.operands[1].reg; | |
8822 | } | |
b99bd4ef | 8823 | |
c19d1205 ZW |
8824 | static void |
8825 | do_iwmmxt_wldstbh (void) | |
8826 | { | |
8f06b2d8 | 8827 | int reloc; |
c19d1205 | 8828 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8829 | if (thumb_mode) |
8830 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8831 | else | |
8832 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8833 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8834 | } |
8835 | ||
c19d1205 ZW |
8836 | static void |
8837 | do_iwmmxt_wldstw (void) | |
8838 | { | |
8839 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8840 | if (!inst.operands[0].isreg) | |
8841 | { | |
8842 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8843 | inst.instruction |= 0xf0000000; | |
8844 | } | |
b99bd4ef | 8845 | |
c19d1205 ZW |
8846 | inst.instruction |= inst.operands[0].reg << 12; |
8847 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8848 | } | |
b99bd4ef NC |
8849 | |
8850 | static void | |
c19d1205 | 8851 | do_iwmmxt_wldstd (void) |
b99bd4ef | 8852 | { |
c19d1205 | 8853 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
8854 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
8855 | && inst.operands[1].immisreg) | |
8856 | { | |
8857 | inst.instruction &= ~0x1a000ff; | |
8858 | inst.instruction |= (0xf << 28); | |
8859 | if (inst.operands[1].preind) | |
8860 | inst.instruction |= PRE_INDEX; | |
8861 | if (!inst.operands[1].negative) | |
8862 | inst.instruction |= INDEX_UP; | |
8863 | if (inst.operands[1].writeback) | |
8864 | inst.instruction |= WRITE_BACK; | |
8865 | inst.instruction |= inst.operands[1].reg << 16; | |
8866 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
8867 | inst.instruction |= inst.operands[1].imm; | |
8868 | } | |
8869 | else | |
8870 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 8871 | } |
b99bd4ef | 8872 | |
c19d1205 ZW |
8873 | static void |
8874 | do_iwmmxt_wshufh (void) | |
8875 | { | |
8876 | inst.instruction |= inst.operands[0].reg << 12; | |
8877 | inst.instruction |= inst.operands[1].reg << 16; | |
8878 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
8879 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
8880 | } | |
b99bd4ef | 8881 | |
c19d1205 ZW |
8882 | static void |
8883 | do_iwmmxt_wzero (void) | |
8884 | { | |
8885 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
8886 | inst.instruction |= inst.operands[0].reg; | |
8887 | inst.instruction |= inst.operands[0].reg << 12; | |
8888 | inst.instruction |= inst.operands[0].reg << 16; | |
8889 | } | |
2d447fca JM |
8890 | |
8891 | static void | |
8892 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
8893 | { | |
8894 | if (inst.operands[2].isreg) | |
8895 | do_rd_rn_rm (); | |
8896 | else { | |
8897 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
8898 | _("immediate operand requires iWMMXt2")); | |
8899 | do_rd_rn (); | |
8900 | if (inst.operands[2].imm == 0) | |
8901 | { | |
8902 | switch ((inst.instruction >> 20) & 0xf) | |
8903 | { | |
8904 | case 4: | |
8905 | case 5: | |
8906 | case 6: | |
5f4273c7 | 8907 | case 7: |
2d447fca JM |
8908 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
8909 | inst.operands[2].imm = 16; | |
8910 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
8911 | break; | |
8912 | case 8: | |
8913 | case 9: | |
8914 | case 10: | |
8915 | case 11: | |
8916 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
8917 | inst.operands[2].imm = 32; | |
8918 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
8919 | break; | |
8920 | case 12: | |
8921 | case 13: | |
8922 | case 14: | |
8923 | case 15: | |
8924 | { | |
8925 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
8926 | unsigned long wrn; | |
8927 | wrn = (inst.instruction >> 16) & 0xf; | |
8928 | inst.instruction &= 0xff0fff0f; | |
8929 | inst.instruction |= wrn; | |
8930 | /* Bail out here; the instruction is now assembled. */ | |
8931 | return; | |
8932 | } | |
8933 | } | |
8934 | } | |
8935 | /* Map 32 -> 0, etc. */ | |
8936 | inst.operands[2].imm &= 0x1f; | |
8937 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
8938 | } | |
8939 | } | |
c19d1205 ZW |
8940 | \f |
8941 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
8942 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 8943 | |
c19d1205 | 8944 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 8945 | |
c19d1205 ZW |
8946 | static void |
8947 | do_mav_triple (void) | |
8948 | { | |
8949 | inst.instruction |= inst.operands[0].reg << 16; | |
8950 | inst.instruction |= inst.operands[1].reg; | |
8951 | inst.instruction |= inst.operands[2].reg << 12; | |
8952 | } | |
b99bd4ef | 8953 | |
c19d1205 ZW |
8954 | /* Insns like "foo W,X,Y,Z". |
8955 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 8956 | |
c19d1205 ZW |
8957 | static void |
8958 | do_mav_quad (void) | |
8959 | { | |
8960 | inst.instruction |= inst.operands[0].reg << 5; | |
8961 | inst.instruction |= inst.operands[1].reg << 12; | |
8962 | inst.instruction |= inst.operands[2].reg << 16; | |
8963 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
8964 | } |
8965 | ||
c19d1205 ZW |
8966 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
8967 | static void | |
8968 | do_mav_dspsc (void) | |
a737bd4d | 8969 | { |
c19d1205 ZW |
8970 | inst.instruction |= inst.operands[1].reg << 12; |
8971 | } | |
a737bd4d | 8972 | |
c19d1205 ZW |
8973 | /* Maverick shift immediate instructions. |
8974 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
8975 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 8976 | |
c19d1205 ZW |
8977 | static void |
8978 | do_mav_shift (void) | |
8979 | { | |
8980 | int imm = inst.operands[2].imm; | |
a737bd4d | 8981 | |
c19d1205 ZW |
8982 | inst.instruction |= inst.operands[0].reg << 12; |
8983 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 8984 | |
c19d1205 ZW |
8985 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
8986 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
8987 | Bit 4 should be 0. */ | |
8988 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 8989 | |
c19d1205 ZW |
8990 | inst.instruction |= imm; |
8991 | } | |
8992 | \f | |
8993 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 8994 | |
c19d1205 ZW |
8995 | /* Xscale multiply-accumulate (argument parse) |
8996 | MIAcc acc0,Rm,Rs | |
8997 | MIAPHcc acc0,Rm,Rs | |
8998 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 8999 | |
c19d1205 ZW |
9000 | static void |
9001 | do_xsc_mia (void) | |
9002 | { | |
9003 | inst.instruction |= inst.operands[1].reg; | |
9004 | inst.instruction |= inst.operands[2].reg << 12; | |
9005 | } | |
a737bd4d | 9006 | |
c19d1205 | 9007 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9008 | |
c19d1205 | 9009 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9010 | |
c19d1205 ZW |
9011 | static void |
9012 | do_xsc_mar (void) | |
9013 | { | |
9014 | inst.instruction |= inst.operands[1].reg << 12; | |
9015 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9016 | } |
9017 | ||
c19d1205 | 9018 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9019 | |
c19d1205 | 9020 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9021 | |
9022 | static void | |
c19d1205 | 9023 | do_xsc_mra (void) |
b99bd4ef | 9024 | { |
c19d1205 ZW |
9025 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9026 | inst.instruction |= inst.operands[0].reg << 12; | |
9027 | inst.instruction |= inst.operands[1].reg << 16; | |
9028 | } | |
9029 | \f | |
9030 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9031 | |
c19d1205 ZW |
9032 | /* inst.operands[i] is a shifted-register operand; encode |
9033 | it into inst.instruction in the format used by Thumb32. */ | |
9034 | ||
9035 | static void | |
9036 | encode_thumb32_shifted_operand (int i) | |
9037 | { | |
9038 | unsigned int value = inst.reloc.exp.X_add_number; | |
9039 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9040 | |
9c3c69f2 PB |
9041 | constraint (inst.operands[i].immisreg, |
9042 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9043 | inst.instruction |= inst.operands[i].reg; |
9044 | if (shift == SHIFT_RRX) | |
9045 | inst.instruction |= SHIFT_ROR << 4; | |
9046 | else | |
b99bd4ef | 9047 | { |
c19d1205 ZW |
9048 | constraint (inst.reloc.exp.X_op != O_constant, |
9049 | _("expression too complex")); | |
9050 | ||
9051 | constraint (value > 32 | |
9052 | || (value == 32 && (shift == SHIFT_LSL | |
9053 | || shift == SHIFT_ROR)), | |
9054 | _("shift expression is too large")); | |
9055 | ||
9056 | if (value == 0) | |
9057 | shift = SHIFT_LSL; | |
9058 | else if (value == 32) | |
9059 | value = 0; | |
9060 | ||
9061 | inst.instruction |= shift << 4; | |
9062 | inst.instruction |= (value & 0x1c) << 10; | |
9063 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9064 | } |
c19d1205 | 9065 | } |
b99bd4ef | 9066 | |
b99bd4ef | 9067 | |
c19d1205 ZW |
9068 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9069 | Thumb32 format load or store instruction. Reject forms that cannot | |
9070 | be used with such instructions. If is_t is true, reject forms that | |
9071 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9072 | that cannot be used with a D instruction. If it is a store insn, |
9073 | reject PC in Rn. */ | |
b99bd4ef | 9074 | |
c19d1205 ZW |
9075 | static void |
9076 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9077 | { | |
5be8be5d | 9078 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9079 | |
9080 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9081 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9082 | |
c19d1205 ZW |
9083 | inst.instruction |= inst.operands[i].reg << 16; |
9084 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9085 | { |
5be8be5d | 9086 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9087 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9088 | constraint (inst.operands[i].negative, | |
9089 | _("Thumb does not support negative register indexing")); | |
9090 | constraint (inst.operands[i].postind, | |
9091 | _("Thumb does not support register post-indexing")); | |
9092 | constraint (inst.operands[i].writeback, | |
9093 | _("Thumb does not support register indexing with writeback")); | |
9094 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
9095 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 9096 | |
f40d1643 | 9097 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 9098 | if (inst.operands[i].shifted) |
b99bd4ef | 9099 | { |
c19d1205 ZW |
9100 | constraint (inst.reloc.exp.X_op != O_constant, |
9101 | _("expression too complex")); | |
9c3c69f2 PB |
9102 | constraint (inst.reloc.exp.X_add_number < 0 |
9103 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 9104 | _("shift out of range")); |
9c3c69f2 | 9105 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
9106 | } |
9107 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9108 | } | |
9109 | else if (inst.operands[i].preind) | |
9110 | { | |
5be8be5d | 9111 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 9112 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 9113 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
9114 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
9115 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
9116 | |
9117 | if (is_d) | |
9118 | { | |
9119 | inst.instruction |= 0x01000000; | |
9120 | if (inst.operands[i].writeback) | |
9121 | inst.instruction |= 0x00200000; | |
b99bd4ef | 9122 | } |
c19d1205 | 9123 | else |
b99bd4ef | 9124 | { |
c19d1205 ZW |
9125 | inst.instruction |= 0x00000c00; |
9126 | if (inst.operands[i].writeback) | |
9127 | inst.instruction |= 0x00000100; | |
b99bd4ef | 9128 | } |
c19d1205 | 9129 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 9130 | } |
c19d1205 | 9131 | else if (inst.operands[i].postind) |
b99bd4ef | 9132 | { |
9c2799c2 | 9133 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
9134 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
9135 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
9136 | ||
9137 | if (is_d) | |
9138 | inst.instruction |= 0x00200000; | |
9139 | else | |
9140 | inst.instruction |= 0x00000900; | |
9141 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
9142 | } | |
9143 | else /* unindexed - only for coprocessor */ | |
9144 | inst.error = _("instruction does not accept unindexed addressing"); | |
9145 | } | |
9146 | ||
9147 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
9148 | encodings (the latter only in post-V6T2 cores). The index is the | |
9149 | value used in the insns table below. When there is more than one | |
9150 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
9151 | holds variant (1). |
9152 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 9153 | #define T16_32_TAB \ |
21d799b5 NC |
9154 | X(_adc, 4140, eb400000), \ |
9155 | X(_adcs, 4140, eb500000), \ | |
9156 | X(_add, 1c00, eb000000), \ | |
9157 | X(_adds, 1c00, eb100000), \ | |
9158 | X(_addi, 0000, f1000000), \ | |
9159 | X(_addis, 0000, f1100000), \ | |
9160 | X(_add_pc,000f, f20f0000), \ | |
9161 | X(_add_sp,000d, f10d0000), \ | |
9162 | X(_adr, 000f, f20f0000), \ | |
9163 | X(_and, 4000, ea000000), \ | |
9164 | X(_ands, 4000, ea100000), \ | |
9165 | X(_asr, 1000, fa40f000), \ | |
9166 | X(_asrs, 1000, fa50f000), \ | |
9167 | X(_b, e000, f000b000), \ | |
9168 | X(_bcond, d000, f0008000), \ | |
9169 | X(_bic, 4380, ea200000), \ | |
9170 | X(_bics, 4380, ea300000), \ | |
9171 | X(_cmn, 42c0, eb100f00), \ | |
9172 | X(_cmp, 2800, ebb00f00), \ | |
9173 | X(_cpsie, b660, f3af8400), \ | |
9174 | X(_cpsid, b670, f3af8600), \ | |
9175 | X(_cpy, 4600, ea4f0000), \ | |
9176 | X(_dec_sp,80dd, f1ad0d00), \ | |
9177 | X(_eor, 4040, ea800000), \ | |
9178 | X(_eors, 4040, ea900000), \ | |
9179 | X(_inc_sp,00dd, f10d0d00), \ | |
9180 | X(_ldmia, c800, e8900000), \ | |
9181 | X(_ldr, 6800, f8500000), \ | |
9182 | X(_ldrb, 7800, f8100000), \ | |
9183 | X(_ldrh, 8800, f8300000), \ | |
9184 | X(_ldrsb, 5600, f9100000), \ | |
9185 | X(_ldrsh, 5e00, f9300000), \ | |
9186 | X(_ldr_pc,4800, f85f0000), \ | |
9187 | X(_ldr_pc2,4800, f85f0000), \ | |
9188 | X(_ldr_sp,9800, f85d0000), \ | |
9189 | X(_lsl, 0000, fa00f000), \ | |
9190 | X(_lsls, 0000, fa10f000), \ | |
9191 | X(_lsr, 0800, fa20f000), \ | |
9192 | X(_lsrs, 0800, fa30f000), \ | |
9193 | X(_mov, 2000, ea4f0000), \ | |
9194 | X(_movs, 2000, ea5f0000), \ | |
9195 | X(_mul, 4340, fb00f000), \ | |
9196 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
9197 | X(_mvn, 43c0, ea6f0000), \ | |
9198 | X(_mvns, 43c0, ea7f0000), \ | |
9199 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
9200 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
9201 | X(_orr, 4300, ea400000), \ | |
9202 | X(_orrs, 4300, ea500000), \ | |
9203 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
9204 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
9205 | X(_rev, ba00, fa90f080), \ | |
9206 | X(_rev16, ba40, fa90f090), \ | |
9207 | X(_revsh, bac0, fa90f0b0), \ | |
9208 | X(_ror, 41c0, fa60f000), \ | |
9209 | X(_rors, 41c0, fa70f000), \ | |
9210 | X(_sbc, 4180, eb600000), \ | |
9211 | X(_sbcs, 4180, eb700000), \ | |
9212 | X(_stmia, c000, e8800000), \ | |
9213 | X(_str, 6000, f8400000), \ | |
9214 | X(_strb, 7000, f8000000), \ | |
9215 | X(_strh, 8000, f8200000), \ | |
9216 | X(_str_sp,9000, f84d0000), \ | |
9217 | X(_sub, 1e00, eba00000), \ | |
9218 | X(_subs, 1e00, ebb00000), \ | |
9219 | X(_subi, 8000, f1a00000), \ | |
9220 | X(_subis, 8000, f1b00000), \ | |
9221 | X(_sxtb, b240, fa4ff080), \ | |
9222 | X(_sxth, b200, fa0ff080), \ | |
9223 | X(_tst, 4200, ea100f00), \ | |
9224 | X(_uxtb, b2c0, fa5ff080), \ | |
9225 | X(_uxth, b280, fa1ff080), \ | |
9226 | X(_nop, bf00, f3af8000), \ | |
9227 | X(_yield, bf10, f3af8001), \ | |
9228 | X(_wfe, bf20, f3af8002), \ | |
9229 | X(_wfi, bf30, f3af8003), \ | |
9230 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
9231 | |
9232 | /* To catch errors in encoding functions, the codes are all offset by | |
9233 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
9234 | as 16-bit instructions. */ | |
21d799b5 | 9235 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
9236 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
9237 | #undef X | |
9238 | ||
9239 | #define X(a,b,c) 0x##b | |
9240 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
9241 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
9242 | #undef X | |
9243 | ||
9244 | #define X(a,b,c) 0x##c | |
9245 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
9246 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
9247 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
9248 | #undef X |
9249 | #undef T16_32_TAB | |
9250 | ||
9251 | /* Thumb instruction encoders, in alphabetical order. */ | |
9252 | ||
92e90b6e | 9253 | /* ADDW or SUBW. */ |
c921be7d | 9254 | |
92e90b6e PB |
9255 | static void |
9256 | do_t_add_sub_w (void) | |
9257 | { | |
9258 | int Rd, Rn; | |
9259 | ||
9260 | Rd = inst.operands[0].reg; | |
9261 | Rn = inst.operands[1].reg; | |
9262 | ||
539d4391 NC |
9263 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
9264 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
9265 | if (Rn == REG_SP) | |
9266 | constraint (Rd == REG_PC, BAD_PC); | |
9267 | else | |
9268 | reject_bad_reg (Rd); | |
fdfde340 | 9269 | |
92e90b6e PB |
9270 | inst.instruction |= (Rn << 16) | (Rd << 8); |
9271 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9272 | } | |
9273 | ||
c19d1205 ZW |
9274 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9275 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9276 | ||
9277 | static void | |
9278 | do_t_add_sub (void) | |
9279 | { | |
9280 | int Rd, Rs, Rn; | |
9281 | ||
9282 | Rd = inst.operands[0].reg; | |
9283 | Rs = (inst.operands[1].present | |
9284 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9285 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9286 | ||
e07e6e58 NC |
9287 | if (Rd == REG_PC) |
9288 | set_it_insn_type_last (); | |
9289 | ||
c19d1205 ZW |
9290 | if (unified_syntax) |
9291 | { | |
0110f2b8 PB |
9292 | bfd_boolean flags; |
9293 | bfd_boolean narrow; | |
9294 | int opcode; | |
9295 | ||
9296 | flags = (inst.instruction == T_MNEM_adds | |
9297 | || inst.instruction == T_MNEM_subs); | |
9298 | if (flags) | |
e07e6e58 | 9299 | narrow = !in_it_block (); |
0110f2b8 | 9300 | else |
e07e6e58 | 9301 | narrow = in_it_block (); |
c19d1205 | 9302 | if (!inst.operands[2].isreg) |
b99bd4ef | 9303 | { |
16805f35 PB |
9304 | int add; |
9305 | ||
fdfde340 JM |
9306 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9307 | ||
16805f35 PB |
9308 | add = (inst.instruction == T_MNEM_add |
9309 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9310 | opcode = 0; |
9311 | if (inst.size_req != 4) | |
9312 | { | |
0110f2b8 PB |
9313 | /* Attempt to use a narrow opcode, with relaxation if |
9314 | appropriate. */ | |
9315 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9316 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9317 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9318 | opcode = T_MNEM_add_sp; | |
9319 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9320 | opcode = T_MNEM_add_pc; | |
9321 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9322 | { | |
9323 | if (flags) | |
9324 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9325 | else | |
9326 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9327 | } | |
9328 | if (opcode) | |
9329 | { | |
9330 | inst.instruction = THUMB_OP16(opcode); | |
9331 | inst.instruction |= (Rd << 4) | Rs; | |
9332 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9333 | if (inst.size_req != 2) | |
9334 | inst.relax = opcode; | |
9335 | } | |
9336 | else | |
9337 | constraint (inst.size_req == 2, BAD_HIREG); | |
9338 | } | |
9339 | if (inst.size_req == 4 | |
9340 | || (inst.size_req != 2 && !opcode)) | |
9341 | { | |
efd81785 PB |
9342 | if (Rd == REG_PC) |
9343 | { | |
fdfde340 | 9344 | constraint (add, BAD_PC); |
efd81785 PB |
9345 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9346 | _("only SUBS PC, LR, #const allowed")); | |
9347 | constraint (inst.reloc.exp.X_op != O_constant, | |
9348 | _("expression too complex")); | |
9349 | constraint (inst.reloc.exp.X_add_number < 0 | |
9350 | || inst.reloc.exp.X_add_number > 0xff, | |
9351 | _("immediate value out of range")); | |
9352 | inst.instruction = T2_SUBS_PC_LR | |
9353 | | inst.reloc.exp.X_add_number; | |
9354 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9355 | return; | |
9356 | } | |
9357 | else if (Rs == REG_PC) | |
16805f35 PB |
9358 | { |
9359 | /* Always use addw/subw. */ | |
9360 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9361 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9362 | } | |
9363 | else | |
9364 | { | |
9365 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9366 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9367 | | 0x10000000; | |
9368 | if (flags) | |
9369 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9370 | else | |
9371 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9372 | } | |
dc4503c6 PB |
9373 | inst.instruction |= Rd << 8; |
9374 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9375 | } |
b99bd4ef | 9376 | } |
c19d1205 ZW |
9377 | else |
9378 | { | |
9379 | Rn = inst.operands[2].reg; | |
9380 | /* See if we can do this with a 16-bit instruction. */ | |
9381 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9382 | { | |
e27ec89e PB |
9383 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9384 | narrow = FALSE; | |
9385 | ||
9386 | if (narrow) | |
c19d1205 | 9387 | { |
e27ec89e PB |
9388 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9389 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9390 | ? T_OPCODE_ADD_R3 |
9391 | : T_OPCODE_SUB_R3); | |
9392 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9393 | return; | |
9394 | } | |
b99bd4ef | 9395 | |
7e806470 | 9396 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9397 | { |
7e806470 PB |
9398 | /* Thumb-1 cores (except v6-M) require at least one high |
9399 | register in a narrow non flag setting add. */ | |
9400 | if (Rd > 7 || Rn > 7 | |
9401 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9402 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9403 | { |
7e806470 PB |
9404 | if (Rd == Rn) |
9405 | { | |
9406 | Rn = Rs; | |
9407 | Rs = Rd; | |
9408 | } | |
c19d1205 ZW |
9409 | inst.instruction = T_OPCODE_ADD_HI; |
9410 | inst.instruction |= (Rd & 8) << 4; | |
9411 | inst.instruction |= (Rd & 7); | |
9412 | inst.instruction |= Rn << 3; | |
9413 | return; | |
9414 | } | |
c19d1205 ZW |
9415 | } |
9416 | } | |
c921be7d | 9417 | |
fdfde340 JM |
9418 | constraint (Rd == REG_PC, BAD_PC); |
9419 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9420 | constraint (Rs == REG_PC, BAD_PC); | |
9421 | reject_bad_reg (Rn); | |
9422 | ||
c19d1205 ZW |
9423 | /* If we get here, it can't be done in 16 bits. */ |
9424 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9425 | _("shift must be constant")); | |
9426 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9427 | inst.instruction |= Rd << 8; | |
9428 | inst.instruction |= Rs << 16; | |
9429 | encode_thumb32_shifted_operand (2); | |
9430 | } | |
9431 | } | |
9432 | else | |
9433 | { | |
9434 | constraint (inst.instruction == T_MNEM_adds | |
9435 | || inst.instruction == T_MNEM_subs, | |
9436 | BAD_THUMB32); | |
b99bd4ef | 9437 | |
c19d1205 | 9438 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9439 | { |
c19d1205 ZW |
9440 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9441 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9442 | BAD_HIREG); | |
9443 | ||
9444 | inst.instruction = (inst.instruction == T_MNEM_add | |
9445 | ? 0x0000 : 0x8000); | |
9446 | inst.instruction |= (Rd << 4) | Rs; | |
9447 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9448 | return; |
9449 | } | |
9450 | ||
c19d1205 ZW |
9451 | Rn = inst.operands[2].reg; |
9452 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9453 | |
c19d1205 ZW |
9454 | /* We now have Rd, Rs, and Rn set to registers. */ |
9455 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9456 | { |
c19d1205 ZW |
9457 | /* Can't do this for SUB. */ |
9458 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9459 | inst.instruction = T_OPCODE_ADD_HI; | |
9460 | inst.instruction |= (Rd & 8) << 4; | |
9461 | inst.instruction |= (Rd & 7); | |
9462 | if (Rs == Rd) | |
9463 | inst.instruction |= Rn << 3; | |
9464 | else if (Rn == Rd) | |
9465 | inst.instruction |= Rs << 3; | |
9466 | else | |
9467 | constraint (1, _("dest must overlap one source register")); | |
9468 | } | |
9469 | else | |
9470 | { | |
9471 | inst.instruction = (inst.instruction == T_MNEM_add | |
9472 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9473 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9474 | } |
b99bd4ef | 9475 | } |
b99bd4ef NC |
9476 | } |
9477 | ||
c19d1205 ZW |
9478 | static void |
9479 | do_t_adr (void) | |
9480 | { | |
fdfde340 JM |
9481 | unsigned Rd; |
9482 | ||
9483 | Rd = inst.operands[0].reg; | |
9484 | reject_bad_reg (Rd); | |
9485 | ||
9486 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9487 | { |
9488 | /* Defer to section relaxation. */ | |
9489 | inst.relax = inst.instruction; | |
9490 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9491 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9492 | } |
9493 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9494 | { |
0110f2b8 | 9495 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9496 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9497 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9498 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9499 | inst.reloc.pc_rel = 1; | |
9500 | } | |
9501 | else | |
9502 | { | |
0110f2b8 | 9503 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9504 | inst.instruction = THUMB_OP16 (inst.instruction); |
9505 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9506 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9507 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9508 | |
fdfde340 | 9509 | inst.instruction |= Rd << 4; |
e9f89963 | 9510 | } |
c19d1205 | 9511 | } |
b99bd4ef | 9512 | |
c19d1205 ZW |
9513 | /* Arithmetic instructions for which there is just one 16-bit |
9514 | instruction encoding, and it allows only two low registers. | |
9515 | For maximal compatibility with ARM syntax, we allow three register | |
9516 | operands even when Thumb-32 instructions are not available, as long | |
9517 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9518 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9519 | static void |
c19d1205 | 9520 | do_t_arit3 (void) |
b99bd4ef | 9521 | { |
c19d1205 | 9522 | int Rd, Rs, Rn; |
b99bd4ef | 9523 | |
c19d1205 ZW |
9524 | Rd = inst.operands[0].reg; |
9525 | Rs = (inst.operands[1].present | |
9526 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9527 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9528 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9529 | |
fdfde340 JM |
9530 | reject_bad_reg (Rd); |
9531 | reject_bad_reg (Rs); | |
9532 | if (inst.operands[2].isreg) | |
9533 | reject_bad_reg (Rn); | |
9534 | ||
c19d1205 | 9535 | if (unified_syntax) |
b99bd4ef | 9536 | { |
c19d1205 ZW |
9537 | if (!inst.operands[2].isreg) |
9538 | { | |
9539 | /* For an immediate, we always generate a 32-bit opcode; | |
9540 | section relaxation will shrink it later if possible. */ | |
9541 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9542 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9543 | inst.instruction |= Rd << 8; | |
9544 | inst.instruction |= Rs << 16; | |
9545 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9546 | } | |
9547 | else | |
9548 | { | |
e27ec89e PB |
9549 | bfd_boolean narrow; |
9550 | ||
c19d1205 | 9551 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9552 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9553 | narrow = !in_it_block (); |
e27ec89e | 9554 | else |
e07e6e58 | 9555 | narrow = in_it_block (); |
e27ec89e PB |
9556 | |
9557 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9558 | narrow = FALSE; | |
9559 | if (inst.operands[2].shifted) | |
9560 | narrow = FALSE; | |
9561 | if (inst.size_req == 4) | |
9562 | narrow = FALSE; | |
9563 | ||
9564 | if (narrow | |
c19d1205 ZW |
9565 | && Rd == Rs) |
9566 | { | |
9567 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9568 | inst.instruction |= Rd; | |
9569 | inst.instruction |= Rn << 3; | |
9570 | return; | |
9571 | } | |
b99bd4ef | 9572 | |
c19d1205 ZW |
9573 | /* If we get here, it can't be done in 16 bits. */ |
9574 | constraint (inst.operands[2].shifted | |
9575 | && inst.operands[2].immisreg, | |
9576 | _("shift must be constant")); | |
9577 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9578 | inst.instruction |= Rd << 8; | |
9579 | inst.instruction |= Rs << 16; | |
9580 | encode_thumb32_shifted_operand (2); | |
9581 | } | |
a737bd4d | 9582 | } |
c19d1205 | 9583 | else |
b99bd4ef | 9584 | { |
c19d1205 ZW |
9585 | /* On its face this is a lie - the instruction does set the |
9586 | flags. However, the only supported mnemonic in this mode | |
9587 | says it doesn't. */ | |
9588 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9589 | |
c19d1205 ZW |
9590 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9591 | _("unshifted register required")); | |
9592 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9593 | constraint (Rd != Rs, | |
9594 | _("dest and source1 must be the same register")); | |
a737bd4d | 9595 | |
c19d1205 ZW |
9596 | inst.instruction = THUMB_OP16 (inst.instruction); |
9597 | inst.instruction |= Rd; | |
9598 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9599 | } |
a737bd4d | 9600 | } |
b99bd4ef | 9601 | |
c19d1205 ZW |
9602 | /* Similarly, but for instructions where the arithmetic operation is |
9603 | commutative, so we can allow either of them to be different from | |
9604 | the destination operand in a 16-bit instruction. For instance, all | |
9605 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9606 | accepted. */ | |
9607 | static void | |
9608 | do_t_arit3c (void) | |
a737bd4d | 9609 | { |
c19d1205 | 9610 | int Rd, Rs, Rn; |
b99bd4ef | 9611 | |
c19d1205 ZW |
9612 | Rd = inst.operands[0].reg; |
9613 | Rs = (inst.operands[1].present | |
9614 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9615 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9616 | Rn = inst.operands[2].reg; | |
c921be7d | 9617 | |
fdfde340 JM |
9618 | reject_bad_reg (Rd); |
9619 | reject_bad_reg (Rs); | |
9620 | if (inst.operands[2].isreg) | |
9621 | reject_bad_reg (Rn); | |
a737bd4d | 9622 | |
c19d1205 | 9623 | if (unified_syntax) |
a737bd4d | 9624 | { |
c19d1205 | 9625 | if (!inst.operands[2].isreg) |
b99bd4ef | 9626 | { |
c19d1205 ZW |
9627 | /* For an immediate, we always generate a 32-bit opcode; |
9628 | section relaxation will shrink it later if possible. */ | |
9629 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9630 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9631 | inst.instruction |= Rd << 8; | |
9632 | inst.instruction |= Rs << 16; | |
9633 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9634 | } |
c19d1205 | 9635 | else |
a737bd4d | 9636 | { |
e27ec89e PB |
9637 | bfd_boolean narrow; |
9638 | ||
c19d1205 | 9639 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9640 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9641 | narrow = !in_it_block (); |
e27ec89e | 9642 | else |
e07e6e58 | 9643 | narrow = in_it_block (); |
e27ec89e PB |
9644 | |
9645 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9646 | narrow = FALSE; | |
9647 | if (inst.operands[2].shifted) | |
9648 | narrow = FALSE; | |
9649 | if (inst.size_req == 4) | |
9650 | narrow = FALSE; | |
9651 | ||
9652 | if (narrow) | |
a737bd4d | 9653 | { |
c19d1205 | 9654 | if (Rd == Rs) |
a737bd4d | 9655 | { |
c19d1205 ZW |
9656 | inst.instruction = THUMB_OP16 (inst.instruction); |
9657 | inst.instruction |= Rd; | |
9658 | inst.instruction |= Rn << 3; | |
9659 | return; | |
a737bd4d | 9660 | } |
c19d1205 | 9661 | if (Rd == Rn) |
a737bd4d | 9662 | { |
c19d1205 ZW |
9663 | inst.instruction = THUMB_OP16 (inst.instruction); |
9664 | inst.instruction |= Rd; | |
9665 | inst.instruction |= Rs << 3; | |
9666 | return; | |
a737bd4d NC |
9667 | } |
9668 | } | |
c19d1205 ZW |
9669 | |
9670 | /* If we get here, it can't be done in 16 bits. */ | |
9671 | constraint (inst.operands[2].shifted | |
9672 | && inst.operands[2].immisreg, | |
9673 | _("shift must be constant")); | |
9674 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9675 | inst.instruction |= Rd << 8; | |
9676 | inst.instruction |= Rs << 16; | |
9677 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9678 | } |
b99bd4ef | 9679 | } |
c19d1205 ZW |
9680 | else |
9681 | { | |
9682 | /* On its face this is a lie - the instruction does set the | |
9683 | flags. However, the only supported mnemonic in this mode | |
9684 | says it doesn't. */ | |
9685 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9686 | |
c19d1205 ZW |
9687 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9688 | _("unshifted register required")); | |
9689 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9690 | ||
9691 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9692 | inst.instruction |= Rd; | |
9693 | ||
9694 | if (Rd == Rs) | |
9695 | inst.instruction |= Rn << 3; | |
9696 | else if (Rd == Rn) | |
9697 | inst.instruction |= Rs << 3; | |
9698 | else | |
9699 | constraint (1, _("dest must overlap one source register")); | |
9700 | } | |
a737bd4d NC |
9701 | } |
9702 | ||
62b3e311 PB |
9703 | static void |
9704 | do_t_barrier (void) | |
9705 | { | |
9706 | if (inst.operands[0].present) | |
9707 | { | |
9708 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
9709 | && inst.operands[0].imm > 0xf |
9710 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 9711 | _("bad barrier type")); |
62b3e311 PB |
9712 | inst.instruction |= inst.operands[0].imm; |
9713 | } | |
9714 | else | |
9715 | inst.instruction |= 0xf; | |
9716 | } | |
9717 | ||
c19d1205 ZW |
9718 | static void |
9719 | do_t_bfc (void) | |
a737bd4d | 9720 | { |
fdfde340 | 9721 | unsigned Rd; |
c19d1205 ZW |
9722 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9723 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9724 | /* The instruction encoding stores the LSB and MSB, | |
9725 | not the LSB and width. */ | |
fdfde340 JM |
9726 | Rd = inst.operands[0].reg; |
9727 | reject_bad_reg (Rd); | |
9728 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9729 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9730 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9731 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9732 | } |
9733 | ||
c19d1205 ZW |
9734 | static void |
9735 | do_t_bfi (void) | |
b99bd4ef | 9736 | { |
fdfde340 | 9737 | int Rd, Rn; |
c19d1205 | 9738 | unsigned int msb; |
b99bd4ef | 9739 | |
fdfde340 JM |
9740 | Rd = inst.operands[0].reg; |
9741 | reject_bad_reg (Rd); | |
9742 | ||
c19d1205 ZW |
9743 | /* #0 in second position is alternative syntax for bfc, which is |
9744 | the same instruction but with REG_PC in the Rm field. */ | |
9745 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9746 | Rn = REG_PC; |
9747 | else | |
9748 | { | |
9749 | Rn = inst.operands[1].reg; | |
9750 | reject_bad_reg (Rn); | |
9751 | } | |
b99bd4ef | 9752 | |
c19d1205 ZW |
9753 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9754 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9755 | /* The instruction encoding stores the LSB and MSB, | |
9756 | not the LSB and width. */ | |
fdfde340 JM |
9757 | inst.instruction |= Rd << 8; |
9758 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9759 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9760 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9761 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9762 | } |
9763 | ||
c19d1205 ZW |
9764 | static void |
9765 | do_t_bfx (void) | |
b99bd4ef | 9766 | { |
fdfde340 JM |
9767 | unsigned Rd, Rn; |
9768 | ||
9769 | Rd = inst.operands[0].reg; | |
9770 | Rn = inst.operands[1].reg; | |
9771 | ||
9772 | reject_bad_reg (Rd); | |
9773 | reject_bad_reg (Rn); | |
9774 | ||
c19d1205 ZW |
9775 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9776 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9777 | inst.instruction |= Rd << 8; |
9778 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9779 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9780 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9781 | inst.instruction |= inst.operands[3].imm - 1; | |
9782 | } | |
b99bd4ef | 9783 | |
c19d1205 ZW |
9784 | /* ARM V5 Thumb BLX (argument parse) |
9785 | BLX <target_addr> which is BLX(1) | |
9786 | BLX <Rm> which is BLX(2) | |
9787 | Unfortunately, there are two different opcodes for this mnemonic. | |
9788 | So, the insns[].value is not used, and the code here zaps values | |
9789 | into inst.instruction. | |
b99bd4ef | 9790 | |
c19d1205 ZW |
9791 | ??? How to take advantage of the additional two bits of displacement |
9792 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9793 | |
c19d1205 ZW |
9794 | static void |
9795 | do_t_blx (void) | |
9796 | { | |
e07e6e58 NC |
9797 | set_it_insn_type_last (); |
9798 | ||
c19d1205 | 9799 | if (inst.operands[0].isreg) |
fdfde340 JM |
9800 | { |
9801 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9802 | /* We have a register, so this is BLX(2). */ | |
9803 | inst.instruction |= inst.operands[0].reg << 3; | |
9804 | } | |
b99bd4ef NC |
9805 | else |
9806 | { | |
c19d1205 | 9807 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9808 | inst.instruction = 0xf000e800; |
0855e32b | 9809 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
9810 | } |
9811 | } | |
9812 | ||
c19d1205 ZW |
9813 | static void |
9814 | do_t_branch (void) | |
b99bd4ef | 9815 | { |
0110f2b8 | 9816 | int opcode; |
dfa9f0d5 | 9817 | int cond; |
9ae92b05 | 9818 | int reloc; |
dfa9f0d5 | 9819 | |
e07e6e58 NC |
9820 | cond = inst.cond; |
9821 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9822 | ||
9823 | if (in_it_block ()) | |
dfa9f0d5 PB |
9824 | { |
9825 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9826 | branches. */ | |
9827 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9828 | } |
9829 | else | |
9830 | cond = inst.cond; | |
9831 | ||
9832 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9833 | opcode = T_MNEM_bcond; |
9834 | else | |
9835 | opcode = inst.instruction; | |
9836 | ||
12d6b0b7 RS |
9837 | if (unified_syntax |
9838 | && (inst.size_req == 4 | |
9839 | || (inst.size_req != 2 && inst.operands[0].hasreloc))) | |
c19d1205 | 9840 | { |
0110f2b8 | 9841 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 9842 | if (cond == COND_ALWAYS) |
9ae92b05 | 9843 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
9844 | else |
9845 | { | |
9c2799c2 | 9846 | gas_assert (cond != 0xF); |
dfa9f0d5 | 9847 | inst.instruction |= cond << 22; |
9ae92b05 | 9848 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
9849 | } |
9850 | } | |
b99bd4ef NC |
9851 | else |
9852 | { | |
0110f2b8 | 9853 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 9854 | if (cond == COND_ALWAYS) |
9ae92b05 | 9855 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 9856 | else |
b99bd4ef | 9857 | { |
dfa9f0d5 | 9858 | inst.instruction |= cond << 8; |
9ae92b05 | 9859 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 9860 | } |
0110f2b8 PB |
9861 | /* Allow section relaxation. */ |
9862 | if (unified_syntax && inst.size_req != 2) | |
9863 | inst.relax = opcode; | |
b99bd4ef | 9864 | } |
9ae92b05 | 9865 | inst.reloc.type = reloc; |
c19d1205 | 9866 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
9867 | } |
9868 | ||
9869 | static void | |
c19d1205 | 9870 | do_t_bkpt (void) |
b99bd4ef | 9871 | { |
dfa9f0d5 PB |
9872 | constraint (inst.cond != COND_ALWAYS, |
9873 | _("instruction is always unconditional")); | |
c19d1205 | 9874 | if (inst.operands[0].present) |
b99bd4ef | 9875 | { |
c19d1205 ZW |
9876 | constraint (inst.operands[0].imm > 255, |
9877 | _("immediate value out of range")); | |
9878 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 9879 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 9880 | } |
b99bd4ef NC |
9881 | } |
9882 | ||
9883 | static void | |
c19d1205 | 9884 | do_t_branch23 (void) |
b99bd4ef | 9885 | { |
e07e6e58 | 9886 | set_it_insn_type_last (); |
0855e32b NS |
9887 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
9888 | ||
9889 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in | |
9890 | this file. We used to simply ignore the PLT reloc type here -- | |
9891 | the branch encoding is now needed to deal with TLSCALL relocs. | |
9892 | So if we see a PLT reloc now, put it back to how it used to be to | |
9893 | keep the preexisting behaviour. */ | |
9894 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
9895 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 9896 | |
4343666d | 9897 | #if defined(OBJ_COFF) |
c19d1205 ZW |
9898 | /* If the destination of the branch is a defined symbol which does not have |
9899 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9900 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9901 | function and change the branch to refer to that function instead. */ | |
9902 | if ( inst.reloc.exp.X_op == O_symbol | |
9903 | && inst.reloc.exp.X_add_symbol != NULL | |
9904 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
9905 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
9906 | inst.reloc.exp.X_add_symbol = | |
9907 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 9908 | #endif |
90e4755a RE |
9909 | } |
9910 | ||
9911 | static void | |
c19d1205 | 9912 | do_t_bx (void) |
90e4755a | 9913 | { |
e07e6e58 | 9914 | set_it_insn_type_last (); |
c19d1205 ZW |
9915 | inst.instruction |= inst.operands[0].reg << 3; |
9916 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
9917 | should cause the alignment to be checked once it is known. This is | |
9918 | because BX PC only works if the instruction is word aligned. */ | |
9919 | } | |
90e4755a | 9920 | |
c19d1205 ZW |
9921 | static void |
9922 | do_t_bxj (void) | |
9923 | { | |
fdfde340 | 9924 | int Rm; |
90e4755a | 9925 | |
e07e6e58 | 9926 | set_it_insn_type_last (); |
fdfde340 JM |
9927 | Rm = inst.operands[0].reg; |
9928 | reject_bad_reg (Rm); | |
9929 | inst.instruction |= Rm << 16; | |
90e4755a RE |
9930 | } |
9931 | ||
9932 | static void | |
c19d1205 | 9933 | do_t_clz (void) |
90e4755a | 9934 | { |
fdfde340 JM |
9935 | unsigned Rd; |
9936 | unsigned Rm; | |
9937 | ||
9938 | Rd = inst.operands[0].reg; | |
9939 | Rm = inst.operands[1].reg; | |
9940 | ||
9941 | reject_bad_reg (Rd); | |
9942 | reject_bad_reg (Rm); | |
9943 | ||
9944 | inst.instruction |= Rd << 8; | |
9945 | inst.instruction |= Rm << 16; | |
9946 | inst.instruction |= Rm; | |
c19d1205 | 9947 | } |
90e4755a | 9948 | |
dfa9f0d5 PB |
9949 | static void |
9950 | do_t_cps (void) | |
9951 | { | |
e07e6e58 | 9952 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
9953 | inst.instruction |= inst.operands[0].imm; |
9954 | } | |
9955 | ||
c19d1205 ZW |
9956 | static void |
9957 | do_t_cpsi (void) | |
9958 | { | |
e07e6e58 | 9959 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 9960 | if (unified_syntax |
62b3e311 PB |
9961 | && (inst.operands[1].present || inst.size_req == 4) |
9962 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 9963 | { |
c19d1205 ZW |
9964 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
9965 | inst.instruction = 0xf3af8000; | |
9966 | inst.instruction |= imod << 9; | |
9967 | inst.instruction |= inst.operands[0].imm << 5; | |
9968 | if (inst.operands[1].present) | |
9969 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 9970 | } |
c19d1205 | 9971 | else |
90e4755a | 9972 | { |
62b3e311 PB |
9973 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
9974 | && (inst.operands[0].imm & 4), | |
9975 | _("selected processor does not support 'A' form " | |
9976 | "of this instruction")); | |
9977 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
9978 | _("Thumb does not support the 2-argument " |
9979 | "form of this instruction")); | |
9980 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 9981 | } |
90e4755a RE |
9982 | } |
9983 | ||
c19d1205 ZW |
9984 | /* THUMB CPY instruction (argument parse). */ |
9985 | ||
90e4755a | 9986 | static void |
c19d1205 | 9987 | do_t_cpy (void) |
90e4755a | 9988 | { |
c19d1205 | 9989 | if (inst.size_req == 4) |
90e4755a | 9990 | { |
c19d1205 ZW |
9991 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
9992 | inst.instruction |= inst.operands[0].reg << 8; | |
9993 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 9994 | } |
c19d1205 | 9995 | else |
90e4755a | 9996 | { |
c19d1205 ZW |
9997 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
9998 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
9999 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10000 | } |
90e4755a RE |
10001 | } |
10002 | ||
90e4755a | 10003 | static void |
25fe350b | 10004 | do_t_cbz (void) |
90e4755a | 10005 | { |
e07e6e58 | 10006 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10007 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10008 | inst.instruction |= inst.operands[0].reg; | |
10009 | inst.reloc.pc_rel = 1; | |
10010 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10011 | } | |
90e4755a | 10012 | |
62b3e311 PB |
10013 | static void |
10014 | do_t_dbg (void) | |
10015 | { | |
10016 | inst.instruction |= inst.operands[0].imm; | |
10017 | } | |
10018 | ||
10019 | static void | |
10020 | do_t_div (void) | |
10021 | { | |
fdfde340 JM |
10022 | unsigned Rd, Rn, Rm; |
10023 | ||
10024 | Rd = inst.operands[0].reg; | |
10025 | Rn = (inst.operands[1].present | |
10026 | ? inst.operands[1].reg : Rd); | |
10027 | Rm = inst.operands[2].reg; | |
10028 | ||
10029 | reject_bad_reg (Rd); | |
10030 | reject_bad_reg (Rn); | |
10031 | reject_bad_reg (Rm); | |
10032 | ||
10033 | inst.instruction |= Rd << 8; | |
10034 | inst.instruction |= Rn << 16; | |
10035 | inst.instruction |= Rm; | |
62b3e311 PB |
10036 | } |
10037 | ||
c19d1205 ZW |
10038 | static void |
10039 | do_t_hint (void) | |
10040 | { | |
10041 | if (unified_syntax && inst.size_req == 4) | |
10042 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10043 | else | |
10044 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10045 | } | |
90e4755a | 10046 | |
c19d1205 ZW |
10047 | static void |
10048 | do_t_it (void) | |
10049 | { | |
10050 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10051 | |
e07e6e58 NC |
10052 | set_it_insn_type (IT_INSN); |
10053 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10054 | now_it.cc = cond; | |
e27ec89e PB |
10055 | |
10056 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10057 | if ((cond & 0x1) == 0x0) |
90e4755a | 10058 | { |
c19d1205 | 10059 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10060 | |
c19d1205 ZW |
10061 | if ((mask & 0x7) == 0) |
10062 | /* no conversion needed */; | |
10063 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
10064 | mask ^= 0x8; |
10065 | else if ((mask & 0x1) == 0) | |
10066 | mask ^= 0xC; | |
c19d1205 | 10067 | else |
e27ec89e | 10068 | mask ^= 0xE; |
90e4755a | 10069 | |
e27ec89e PB |
10070 | inst.instruction &= 0xfff0; |
10071 | inst.instruction |= mask; | |
c19d1205 | 10072 | } |
90e4755a | 10073 | |
c19d1205 ZW |
10074 | inst.instruction |= cond << 4; |
10075 | } | |
90e4755a | 10076 | |
3c707909 PB |
10077 | /* Helper function used for both push/pop and ldm/stm. */ |
10078 | static void | |
10079 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
10080 | { | |
10081 | bfd_boolean load; | |
10082 | ||
10083 | load = (inst.instruction & (1 << 20)) != 0; | |
10084 | ||
10085 | if (mask & (1 << 13)) | |
10086 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
10087 | |
10088 | if ((mask & (1 << base)) != 0 | |
10089 | && writeback) | |
10090 | inst.error = _("having the base register in the register list when " | |
10091 | "using write back is UNPREDICTABLE"); | |
10092 | ||
3c707909 PB |
10093 | if (load) |
10094 | { | |
e07e6e58 NC |
10095 | if (mask & (1 << 15)) |
10096 | { | |
10097 | if (mask & (1 << 14)) | |
10098 | inst.error = _("LR and PC should not both be in register list"); | |
10099 | else | |
10100 | set_it_insn_type_last (); | |
10101 | } | |
3c707909 PB |
10102 | } |
10103 | else | |
10104 | { | |
10105 | if (mask & (1 << 15)) | |
10106 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
10107 | } |
10108 | ||
10109 | if ((mask & (mask - 1)) == 0) | |
10110 | { | |
10111 | /* Single register transfers implemented as str/ldr. */ | |
10112 | if (writeback) | |
10113 | { | |
10114 | if (inst.instruction & (1 << 23)) | |
10115 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
10116 | else | |
10117 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
10118 | } | |
10119 | else | |
10120 | { | |
10121 | if (inst.instruction & (1 << 23)) | |
10122 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
10123 | else | |
10124 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
10125 | } | |
10126 | ||
10127 | inst.instruction |= 0xf8400000; | |
10128 | if (load) | |
10129 | inst.instruction |= 0x00100000; | |
10130 | ||
5f4273c7 | 10131 | mask = ffs (mask) - 1; |
3c707909 PB |
10132 | mask <<= 12; |
10133 | } | |
10134 | else if (writeback) | |
10135 | inst.instruction |= WRITE_BACK; | |
10136 | ||
10137 | inst.instruction |= mask; | |
10138 | inst.instruction |= base << 16; | |
10139 | } | |
10140 | ||
c19d1205 ZW |
10141 | static void |
10142 | do_t_ldmstm (void) | |
10143 | { | |
10144 | /* This really doesn't seem worth it. */ | |
10145 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10146 | _("expression too complex")); | |
10147 | constraint (inst.operands[1].writeback, | |
10148 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 10149 | |
c19d1205 ZW |
10150 | if (unified_syntax) |
10151 | { | |
3c707909 PB |
10152 | bfd_boolean narrow; |
10153 | unsigned mask; | |
10154 | ||
10155 | narrow = FALSE; | |
c19d1205 ZW |
10156 | /* See if we can use a 16-bit instruction. */ |
10157 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
10158 | && inst.size_req != 4 | |
3c707909 | 10159 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 10160 | { |
3c707909 | 10161 | mask = 1 << inst.operands[0].reg; |
90e4755a | 10162 | |
eab4f823 | 10163 | if (inst.operands[0].reg <= 7) |
90e4755a | 10164 | { |
3c707909 | 10165 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
10166 | ? inst.operands[0].writeback |
10167 | : (inst.operands[0].writeback | |
10168 | == !(inst.operands[1].imm & mask))) | |
10169 | { | |
10170 | if (inst.instruction == T_MNEM_stmia | |
10171 | && (inst.operands[1].imm & mask) | |
10172 | && (inst.operands[1].imm & (mask - 1))) | |
10173 | as_warn (_("value stored for r%d is UNKNOWN"), | |
10174 | inst.operands[0].reg); | |
3c707909 | 10175 | |
eab4f823 MGD |
10176 | inst.instruction = THUMB_OP16 (inst.instruction); |
10177 | inst.instruction |= inst.operands[0].reg << 8; | |
10178 | inst.instruction |= inst.operands[1].imm; | |
10179 | narrow = TRUE; | |
10180 | } | |
10181 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10182 | { | |
10183 | /* This means 1 register in reg list one of 3 situations: | |
10184 | 1. Instruction is stmia, but without writeback. | |
10185 | 2. lmdia without writeback, but with Rn not in | |
10186 | reglist. | |
10187 | 3. ldmia with writeback, but with Rn in reglist. | |
10188 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
10189 | case 1 and 2 which can be converted into a 16-bit | |
10190 | str or ldr. The SP cases are handled below. */ | |
10191 | unsigned long opcode; | |
10192 | /* First, record an error for Case 3. */ | |
10193 | if (inst.operands[1].imm & mask | |
10194 | && inst.operands[0].writeback) | |
10195 | inst.error = | |
10196 | _("having the base register in the register list when " | |
10197 | "using write back is UNPREDICTABLE"); | |
10198 | ||
10199 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
10200 | : T_MNEM_ldr); | |
10201 | inst.instruction = THUMB_OP16 (opcode); | |
10202 | inst.instruction |= inst.operands[0].reg << 3; | |
10203 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
10204 | narrow = TRUE; | |
10205 | } | |
90e4755a | 10206 | } |
eab4f823 | 10207 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 10208 | { |
eab4f823 MGD |
10209 | if (inst.operands[0].writeback) |
10210 | { | |
10211 | inst.instruction = | |
10212 | THUMB_OP16 (inst.instruction == T_MNEM_stmia | |
10213 | ? T_MNEM_push : T_MNEM_pop); | |
10214 | inst.instruction |= inst.operands[1].imm; | |
10215 | narrow = TRUE; | |
10216 | } | |
10217 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10218 | { | |
10219 | inst.instruction = | |
10220 | THUMB_OP16 (inst.instruction == T_MNEM_stmia | |
10221 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); | |
10222 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); | |
10223 | narrow = TRUE; | |
10224 | } | |
90e4755a | 10225 | } |
3c707909 PB |
10226 | } |
10227 | ||
10228 | if (!narrow) | |
10229 | { | |
c19d1205 ZW |
10230 | if (inst.instruction < 0xffff) |
10231 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 10232 | |
5f4273c7 NC |
10233 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
10234 | inst.operands[0].writeback); | |
90e4755a RE |
10235 | } |
10236 | } | |
c19d1205 | 10237 | else |
90e4755a | 10238 | { |
c19d1205 ZW |
10239 | constraint (inst.operands[0].reg > 7 |
10240 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
10241 | constraint (inst.instruction != T_MNEM_ldmia |
10242 | && inst.instruction != T_MNEM_stmia, | |
10243 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 10244 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 10245 | { |
c19d1205 ZW |
10246 | if (!inst.operands[0].writeback) |
10247 | as_warn (_("this instruction will write back the base register")); | |
10248 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
10249 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 10250 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 10251 | inst.operands[0].reg); |
f03698e6 | 10252 | } |
c19d1205 | 10253 | else |
90e4755a | 10254 | { |
c19d1205 ZW |
10255 | if (!inst.operands[0].writeback |
10256 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10257 | as_warn (_("this instruction will write back the base register")); | |
10258 | else if (inst.operands[0].writeback | |
10259 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10260 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
10261 | } |
10262 | ||
c19d1205 ZW |
10263 | inst.instruction = THUMB_OP16 (inst.instruction); |
10264 | inst.instruction |= inst.operands[0].reg << 8; | |
10265 | inst.instruction |= inst.operands[1].imm; | |
10266 | } | |
10267 | } | |
e28cd48c | 10268 | |
c19d1205 ZW |
10269 | static void |
10270 | do_t_ldrex (void) | |
10271 | { | |
10272 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
10273 | || inst.operands[1].postind || inst.operands[1].writeback | |
10274 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
10275 | || inst.operands[1].negative, | |
01cfc07f | 10276 | BAD_ADDR_MODE); |
e28cd48c | 10277 | |
5be8be5d DG |
10278 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
10279 | ||
c19d1205 ZW |
10280 | inst.instruction |= inst.operands[0].reg << 12; |
10281 | inst.instruction |= inst.operands[1].reg << 16; | |
10282 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
10283 | } | |
e28cd48c | 10284 | |
c19d1205 ZW |
10285 | static void |
10286 | do_t_ldrexd (void) | |
10287 | { | |
10288 | if (!inst.operands[1].present) | |
1cac9012 | 10289 | { |
c19d1205 ZW |
10290 | constraint (inst.operands[0].reg == REG_LR, |
10291 | _("r14 not allowed as first register " | |
10292 | "when second register is omitted")); | |
10293 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 10294 | } |
c19d1205 ZW |
10295 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
10296 | BAD_OVERLAP); | |
b99bd4ef | 10297 | |
c19d1205 ZW |
10298 | inst.instruction |= inst.operands[0].reg << 12; |
10299 | inst.instruction |= inst.operands[1].reg << 8; | |
10300 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10301 | } |
10302 | ||
10303 | static void | |
c19d1205 | 10304 | do_t_ldst (void) |
b99bd4ef | 10305 | { |
0110f2b8 PB |
10306 | unsigned long opcode; |
10307 | int Rn; | |
10308 | ||
e07e6e58 NC |
10309 | if (inst.operands[0].isreg |
10310 | && !inst.operands[0].preind | |
10311 | && inst.operands[0].reg == REG_PC) | |
10312 | set_it_insn_type_last (); | |
10313 | ||
0110f2b8 | 10314 | opcode = inst.instruction; |
c19d1205 | 10315 | if (unified_syntax) |
b99bd4ef | 10316 | { |
53365c0d PB |
10317 | if (!inst.operands[1].isreg) |
10318 | { | |
10319 | if (opcode <= 0xffff) | |
10320 | inst.instruction = THUMB_OP32 (opcode); | |
10321 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10322 | return; | |
10323 | } | |
0110f2b8 PB |
10324 | if (inst.operands[1].isreg |
10325 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10326 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10327 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10328 | && opcode <= 0xffff |
10329 | && inst.size_req != 4) | |
c19d1205 | 10330 | { |
0110f2b8 PB |
10331 | /* Insn may have a 16-bit form. */ |
10332 | Rn = inst.operands[1].reg; | |
10333 | if (inst.operands[1].immisreg) | |
10334 | { | |
10335 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10336 | /* [Rn, Rik] */ |
0110f2b8 PB |
10337 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10338 | goto op16; | |
5be8be5d DG |
10339 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10340 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10341 | } |
10342 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10343 | && opcode != T_MNEM_ldrsb) | |
10344 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10345 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10346 | { | |
10347 | /* [Rn, #const] */ | |
10348 | if (Rn > 7) | |
10349 | { | |
10350 | if (Rn == REG_PC) | |
10351 | { | |
10352 | if (inst.reloc.pc_rel) | |
10353 | opcode = T_MNEM_ldr_pc2; | |
10354 | else | |
10355 | opcode = T_MNEM_ldr_pc; | |
10356 | } | |
10357 | else | |
10358 | { | |
10359 | if (opcode == T_MNEM_ldr) | |
10360 | opcode = T_MNEM_ldr_sp; | |
10361 | else | |
10362 | opcode = T_MNEM_str_sp; | |
10363 | } | |
10364 | inst.instruction = inst.operands[0].reg << 8; | |
10365 | } | |
10366 | else | |
10367 | { | |
10368 | inst.instruction = inst.operands[0].reg; | |
10369 | inst.instruction |= inst.operands[1].reg << 3; | |
10370 | } | |
10371 | inst.instruction |= THUMB_OP16 (opcode); | |
10372 | if (inst.size_req == 2) | |
10373 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10374 | else | |
10375 | inst.relax = opcode; | |
10376 | return; | |
10377 | } | |
c19d1205 | 10378 | } |
0110f2b8 | 10379 | /* Definitely a 32-bit variant. */ |
5be8be5d DG |
10380 | |
10381 | /* Do some validations regarding addressing modes. */ | |
10382 | if (inst.operands[1].immisreg && opcode != T_MNEM_ldr | |
10383 | && opcode != T_MNEM_str) | |
10384 | reject_bad_reg (inst.operands[1].imm); | |
10385 | ||
0110f2b8 | 10386 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10387 | inst.instruction |= inst.operands[0].reg << 12; |
10388 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
10389 | return; |
10390 | } | |
10391 | ||
c19d1205 ZW |
10392 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10393 | ||
10394 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10395 | { |
c19d1205 ZW |
10396 | /* Only [Rn,Rm] is acceptable. */ |
10397 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10398 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10399 | || inst.operands[1].postind || inst.operands[1].shifted | |
10400 | || inst.operands[1].negative, | |
10401 | _("Thumb does not support this addressing mode")); | |
10402 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10403 | goto op16; | |
b99bd4ef | 10404 | } |
5f4273c7 | 10405 | |
c19d1205 ZW |
10406 | inst.instruction = THUMB_OP16 (inst.instruction); |
10407 | if (!inst.operands[1].isreg) | |
10408 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10409 | return; | |
b99bd4ef | 10410 | |
c19d1205 ZW |
10411 | constraint (!inst.operands[1].preind |
10412 | || inst.operands[1].shifted | |
10413 | || inst.operands[1].writeback, | |
10414 | _("Thumb does not support this addressing mode")); | |
10415 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10416 | { |
c19d1205 ZW |
10417 | constraint (inst.instruction & 0x0600, |
10418 | _("byte or halfword not valid for base register")); | |
10419 | constraint (inst.operands[1].reg == REG_PC | |
10420 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10421 | _("r15 based store not allowed")); | |
10422 | constraint (inst.operands[1].immisreg, | |
10423 | _("invalid base register for register offset")); | |
b99bd4ef | 10424 | |
c19d1205 ZW |
10425 | if (inst.operands[1].reg == REG_PC) |
10426 | inst.instruction = T_OPCODE_LDR_PC; | |
10427 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10428 | inst.instruction = T_OPCODE_LDR_SP; | |
10429 | else | |
10430 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10431 | |
c19d1205 ZW |
10432 | inst.instruction |= inst.operands[0].reg << 8; |
10433 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10434 | return; | |
10435 | } | |
90e4755a | 10436 | |
c19d1205 ZW |
10437 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10438 | if (!inst.operands[1].immisreg) | |
10439 | { | |
10440 | /* Immediate offset. */ | |
10441 | inst.instruction |= inst.operands[0].reg; | |
10442 | inst.instruction |= inst.operands[1].reg << 3; | |
10443 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10444 | return; | |
10445 | } | |
90e4755a | 10446 | |
c19d1205 ZW |
10447 | /* Register offset. */ |
10448 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10449 | constraint (inst.operands[1].negative, | |
10450 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10451 | |
c19d1205 ZW |
10452 | op16: |
10453 | switch (inst.instruction) | |
10454 | { | |
10455 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10456 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10457 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10458 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10459 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10460 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10461 | case 0x5600 /* ldrsb */: | |
10462 | case 0x5e00 /* ldrsh */: break; | |
10463 | default: abort (); | |
10464 | } | |
90e4755a | 10465 | |
c19d1205 ZW |
10466 | inst.instruction |= inst.operands[0].reg; |
10467 | inst.instruction |= inst.operands[1].reg << 3; | |
10468 | inst.instruction |= inst.operands[1].imm << 6; | |
10469 | } | |
90e4755a | 10470 | |
c19d1205 ZW |
10471 | static void |
10472 | do_t_ldstd (void) | |
10473 | { | |
10474 | if (!inst.operands[1].present) | |
b99bd4ef | 10475 | { |
c19d1205 ZW |
10476 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10477 | constraint (inst.operands[0].reg == REG_LR, | |
10478 | _("r14 not allowed here")); | |
b99bd4ef | 10479 | } |
c19d1205 ZW |
10480 | inst.instruction |= inst.operands[0].reg << 12; |
10481 | inst.instruction |= inst.operands[1].reg << 8; | |
10482 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10483 | } |
10484 | ||
c19d1205 ZW |
10485 | static void |
10486 | do_t_ldstt (void) | |
10487 | { | |
10488 | inst.instruction |= inst.operands[0].reg << 12; | |
10489 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10490 | } | |
a737bd4d | 10491 | |
b99bd4ef | 10492 | static void |
c19d1205 | 10493 | do_t_mla (void) |
b99bd4ef | 10494 | { |
fdfde340 | 10495 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10496 | |
fdfde340 JM |
10497 | Rd = inst.operands[0].reg; |
10498 | Rn = inst.operands[1].reg; | |
10499 | Rm = inst.operands[2].reg; | |
10500 | Ra = inst.operands[3].reg; | |
10501 | ||
10502 | reject_bad_reg (Rd); | |
10503 | reject_bad_reg (Rn); | |
10504 | reject_bad_reg (Rm); | |
10505 | reject_bad_reg (Ra); | |
10506 | ||
10507 | inst.instruction |= Rd << 8; | |
10508 | inst.instruction |= Rn << 16; | |
10509 | inst.instruction |= Rm; | |
10510 | inst.instruction |= Ra << 12; | |
c19d1205 | 10511 | } |
b99bd4ef | 10512 | |
c19d1205 ZW |
10513 | static void |
10514 | do_t_mlal (void) | |
10515 | { | |
fdfde340 JM |
10516 | unsigned RdLo, RdHi, Rn, Rm; |
10517 | ||
10518 | RdLo = inst.operands[0].reg; | |
10519 | RdHi = inst.operands[1].reg; | |
10520 | Rn = inst.operands[2].reg; | |
10521 | Rm = inst.operands[3].reg; | |
10522 | ||
10523 | reject_bad_reg (RdLo); | |
10524 | reject_bad_reg (RdHi); | |
10525 | reject_bad_reg (Rn); | |
10526 | reject_bad_reg (Rm); | |
10527 | ||
10528 | inst.instruction |= RdLo << 12; | |
10529 | inst.instruction |= RdHi << 8; | |
10530 | inst.instruction |= Rn << 16; | |
10531 | inst.instruction |= Rm; | |
c19d1205 | 10532 | } |
b99bd4ef | 10533 | |
c19d1205 ZW |
10534 | static void |
10535 | do_t_mov_cmp (void) | |
10536 | { | |
fdfde340 JM |
10537 | unsigned Rn, Rm; |
10538 | ||
10539 | Rn = inst.operands[0].reg; | |
10540 | Rm = inst.operands[1].reg; | |
10541 | ||
e07e6e58 NC |
10542 | if (Rn == REG_PC) |
10543 | set_it_insn_type_last (); | |
10544 | ||
c19d1205 | 10545 | if (unified_syntax) |
b99bd4ef | 10546 | { |
c19d1205 ZW |
10547 | int r0off = (inst.instruction == T_MNEM_mov |
10548 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10549 | unsigned long opcode; |
3d388997 PB |
10550 | bfd_boolean narrow; |
10551 | bfd_boolean low_regs; | |
10552 | ||
fdfde340 | 10553 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10554 | opcode = inst.instruction; |
e07e6e58 | 10555 | if (in_it_block ()) |
0110f2b8 | 10556 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10557 | else |
0110f2b8 | 10558 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10559 | if (inst.size_req == 4 |
10560 | || inst.operands[1].shifted) | |
10561 | narrow = FALSE; | |
10562 | ||
efd81785 PB |
10563 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10564 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10565 | && !inst.operands[1].shifted | |
fdfde340 JM |
10566 | && Rn == REG_PC |
10567 | && Rm == REG_LR) | |
efd81785 PB |
10568 | { |
10569 | inst.instruction = T2_SUBS_PC_LR; | |
10570 | return; | |
10571 | } | |
10572 | ||
fdfde340 JM |
10573 | if (opcode == T_MNEM_cmp) |
10574 | { | |
10575 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10576 | if (narrow) |
10577 | { | |
10578 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10579 | but valid. */ | |
10580 | warn_deprecated_sp (Rm); | |
10581 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10582 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10583 | tools reject R15, so we do too. */ | |
10584 | constraint (Rm == REG_PC, BAD_PC); | |
10585 | } | |
10586 | else | |
10587 | reject_bad_reg (Rm); | |
fdfde340 JM |
10588 | } |
10589 | else if (opcode == T_MNEM_mov | |
10590 | || opcode == T_MNEM_movs) | |
10591 | { | |
10592 | if (inst.operands[1].isreg) | |
10593 | { | |
10594 | if (opcode == T_MNEM_movs) | |
10595 | { | |
10596 | reject_bad_reg (Rn); | |
10597 | reject_bad_reg (Rm); | |
10598 | } | |
76fa04a4 MGD |
10599 | else if (narrow) |
10600 | { | |
10601 | /* This is mov.n. */ | |
10602 | if ((Rn == REG_SP || Rn == REG_PC) | |
10603 | && (Rm == REG_SP || Rm == REG_PC)) | |
10604 | { | |
10605 | as_warn (_("Use of r%u as a source register is " | |
10606 | "deprecated when r%u is the destination " | |
10607 | "register."), Rm, Rn); | |
10608 | } | |
10609 | } | |
10610 | else | |
10611 | { | |
10612 | /* This is mov.w. */ | |
10613 | constraint (Rn == REG_PC, BAD_PC); | |
10614 | constraint (Rm == REG_PC, BAD_PC); | |
10615 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
10616 | } | |
fdfde340 JM |
10617 | } |
10618 | else | |
10619 | reject_bad_reg (Rn); | |
10620 | } | |
10621 | ||
c19d1205 ZW |
10622 | if (!inst.operands[1].isreg) |
10623 | { | |
0110f2b8 | 10624 | /* Immediate operand. */ |
e07e6e58 | 10625 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10626 | narrow = 0; |
10627 | if (low_regs && narrow) | |
10628 | { | |
10629 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10630 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10631 | if (inst.size_req == 2) |
10632 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10633 | else | |
10634 | inst.relax = opcode; | |
10635 | } | |
10636 | else | |
10637 | { | |
10638 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10639 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10640 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10641 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10642 | } | |
c19d1205 | 10643 | } |
728ca7c9 PB |
10644 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10645 | && (inst.instruction == T_MNEM_mov | |
10646 | || inst.instruction == T_MNEM_movs)) | |
10647 | { | |
10648 | /* Register shifts are encoded as separate shift instructions. */ | |
10649 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10650 | ||
e07e6e58 | 10651 | if (in_it_block ()) |
728ca7c9 PB |
10652 | narrow = !flags; |
10653 | else | |
10654 | narrow = flags; | |
10655 | ||
10656 | if (inst.size_req == 4) | |
10657 | narrow = FALSE; | |
10658 | ||
10659 | if (!low_regs || inst.operands[1].imm > 7) | |
10660 | narrow = FALSE; | |
10661 | ||
fdfde340 | 10662 | if (Rn != Rm) |
728ca7c9 PB |
10663 | narrow = FALSE; |
10664 | ||
10665 | switch (inst.operands[1].shift_kind) | |
10666 | { | |
10667 | case SHIFT_LSL: | |
10668 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
10669 | break; | |
10670 | case SHIFT_ASR: | |
10671 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
10672 | break; | |
10673 | case SHIFT_LSR: | |
10674 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
10675 | break; | |
10676 | case SHIFT_ROR: | |
10677 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
10678 | break; | |
10679 | default: | |
5f4273c7 | 10680 | abort (); |
728ca7c9 PB |
10681 | } |
10682 | ||
10683 | inst.instruction = opcode; | |
10684 | if (narrow) | |
10685 | { | |
fdfde340 | 10686 | inst.instruction |= Rn; |
728ca7c9 PB |
10687 | inst.instruction |= inst.operands[1].imm << 3; |
10688 | } | |
10689 | else | |
10690 | { | |
10691 | if (flags) | |
10692 | inst.instruction |= CONDS_BIT; | |
10693 | ||
fdfde340 JM |
10694 | inst.instruction |= Rn << 8; |
10695 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
10696 | inst.instruction |= inst.operands[1].imm; |
10697 | } | |
10698 | } | |
3d388997 | 10699 | else if (!narrow) |
c19d1205 | 10700 | { |
728ca7c9 PB |
10701 | /* Some mov with immediate shift have narrow variants. |
10702 | Register shifts are handled above. */ | |
10703 | if (low_regs && inst.operands[1].shifted | |
10704 | && (inst.instruction == T_MNEM_mov | |
10705 | || inst.instruction == T_MNEM_movs)) | |
10706 | { | |
e07e6e58 | 10707 | if (in_it_block ()) |
728ca7c9 PB |
10708 | narrow = (inst.instruction == T_MNEM_mov); |
10709 | else | |
10710 | narrow = (inst.instruction == T_MNEM_movs); | |
10711 | } | |
10712 | ||
10713 | if (narrow) | |
10714 | { | |
10715 | switch (inst.operands[1].shift_kind) | |
10716 | { | |
10717 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10718 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
10719 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
10720 | default: narrow = FALSE; break; | |
10721 | } | |
10722 | } | |
10723 | ||
10724 | if (narrow) | |
10725 | { | |
fdfde340 JM |
10726 | inst.instruction |= Rn; |
10727 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
10728 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10729 | } | |
10730 | else | |
10731 | { | |
10732 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10733 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
10734 | encode_thumb32_shifted_operand (1); |
10735 | } | |
c19d1205 ZW |
10736 | } |
10737 | else | |
10738 | switch (inst.instruction) | |
10739 | { | |
10740 | case T_MNEM_mov: | |
10741 | inst.instruction = T_OPCODE_MOV_HR; | |
fdfde340 JM |
10742 | inst.instruction |= (Rn & 0x8) << 4; |
10743 | inst.instruction |= (Rn & 0x7); | |
10744 | inst.instruction |= Rm << 3; | |
c19d1205 | 10745 | break; |
b99bd4ef | 10746 | |
c19d1205 ZW |
10747 | case T_MNEM_movs: |
10748 | /* We know we have low registers at this point. | |
941a8a52 MGD |
10749 | Generate LSLS Rd, Rs, #0. */ |
10750 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
10751 | inst.instruction |= Rn; |
10752 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10753 | break; |
10754 | ||
10755 | case T_MNEM_cmp: | |
3d388997 | 10756 | if (low_regs) |
c19d1205 ZW |
10757 | { |
10758 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
10759 | inst.instruction |= Rn; |
10760 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10761 | } |
10762 | else | |
10763 | { | |
10764 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
10765 | inst.instruction |= (Rn & 0x8) << 4; |
10766 | inst.instruction |= (Rn & 0x7); | |
10767 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10768 | } |
10769 | break; | |
10770 | } | |
b99bd4ef NC |
10771 | return; |
10772 | } | |
10773 | ||
c19d1205 | 10774 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
10775 | |
10776 | /* PR 10443: Do not silently ignore shifted operands. */ | |
10777 | constraint (inst.operands[1].shifted, | |
10778 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
10779 | ||
c19d1205 | 10780 | if (inst.operands[1].isreg) |
b99bd4ef | 10781 | { |
fdfde340 | 10782 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10783 | { |
c19d1205 ZW |
10784 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10785 | since a MOV instruction produces unpredictable results. */ | |
10786 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10787 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10788 | else |
c19d1205 | 10789 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10790 | |
fdfde340 JM |
10791 | inst.instruction |= Rn; |
10792 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10793 | } |
10794 | else | |
10795 | { | |
c19d1205 ZW |
10796 | if (inst.instruction == T_OPCODE_MOV_I8) |
10797 | inst.instruction = T_OPCODE_MOV_HR; | |
10798 | else | |
10799 | inst.instruction = T_OPCODE_CMP_HR; | |
10800 | do_t_cpy (); | |
b99bd4ef NC |
10801 | } |
10802 | } | |
c19d1205 | 10803 | else |
b99bd4ef | 10804 | { |
fdfde340 | 10805 | constraint (Rn > 7, |
c19d1205 | 10806 | _("only lo regs allowed with immediate")); |
fdfde340 | 10807 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
10808 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
10809 | } | |
10810 | } | |
b99bd4ef | 10811 | |
c19d1205 ZW |
10812 | static void |
10813 | do_t_mov16 (void) | |
10814 | { | |
fdfde340 | 10815 | unsigned Rd; |
b6895b4f PB |
10816 | bfd_vma imm; |
10817 | bfd_boolean top; | |
10818 | ||
10819 | top = (inst.instruction & 0x00800000) != 0; | |
10820 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
10821 | { | |
10822 | constraint (top, _(":lower16: not allowed this instruction")); | |
10823 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
10824 | } | |
10825 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
10826 | { | |
10827 | constraint (!top, _(":upper16: not allowed this instruction")); | |
10828 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
10829 | } | |
10830 | ||
fdfde340 JM |
10831 | Rd = inst.operands[0].reg; |
10832 | reject_bad_reg (Rd); | |
10833 | ||
10834 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
10835 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
10836 | { | |
10837 | imm = inst.reloc.exp.X_add_number; | |
10838 | inst.instruction |= (imm & 0xf000) << 4; | |
10839 | inst.instruction |= (imm & 0x0800) << 15; | |
10840 | inst.instruction |= (imm & 0x0700) << 4; | |
10841 | inst.instruction |= (imm & 0x00ff); | |
10842 | } | |
c19d1205 | 10843 | } |
b99bd4ef | 10844 | |
c19d1205 ZW |
10845 | static void |
10846 | do_t_mvn_tst (void) | |
10847 | { | |
fdfde340 | 10848 | unsigned Rn, Rm; |
c921be7d | 10849 | |
fdfde340 JM |
10850 | Rn = inst.operands[0].reg; |
10851 | Rm = inst.operands[1].reg; | |
10852 | ||
10853 | if (inst.instruction == T_MNEM_cmp | |
10854 | || inst.instruction == T_MNEM_cmn) | |
10855 | constraint (Rn == REG_PC, BAD_PC); | |
10856 | else | |
10857 | reject_bad_reg (Rn); | |
10858 | reject_bad_reg (Rm); | |
10859 | ||
c19d1205 ZW |
10860 | if (unified_syntax) |
10861 | { | |
10862 | int r0off = (inst.instruction == T_MNEM_mvn | |
10863 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
10864 | bfd_boolean narrow; |
10865 | ||
10866 | if (inst.size_req == 4 | |
10867 | || inst.instruction > 0xffff | |
10868 | || inst.operands[1].shifted | |
fdfde340 | 10869 | || Rn > 7 || Rm > 7) |
3d388997 PB |
10870 | narrow = FALSE; |
10871 | else if (inst.instruction == T_MNEM_cmn) | |
10872 | narrow = TRUE; | |
10873 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10874 | narrow = !in_it_block (); |
3d388997 | 10875 | else |
e07e6e58 | 10876 | narrow = in_it_block (); |
3d388997 | 10877 | |
c19d1205 | 10878 | if (!inst.operands[1].isreg) |
b99bd4ef | 10879 | { |
c19d1205 ZW |
10880 | /* For an immediate, we always generate a 32-bit opcode; |
10881 | section relaxation will shrink it later if possible. */ | |
10882 | if (inst.instruction < 0xffff) | |
10883 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10884 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10885 | inst.instruction |= Rn << r0off; |
c19d1205 | 10886 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 10887 | } |
c19d1205 | 10888 | else |
b99bd4ef | 10889 | { |
c19d1205 | 10890 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 10891 | if (narrow) |
b99bd4ef | 10892 | { |
c19d1205 | 10893 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10894 | inst.instruction |= Rn; |
10895 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10896 | } |
c19d1205 | 10897 | else |
b99bd4ef | 10898 | { |
c19d1205 ZW |
10899 | constraint (inst.operands[1].shifted |
10900 | && inst.operands[1].immisreg, | |
10901 | _("shift must be constant")); | |
10902 | if (inst.instruction < 0xffff) | |
10903 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10904 | inst.instruction |= Rn << r0off; |
c19d1205 | 10905 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 10906 | } |
b99bd4ef NC |
10907 | } |
10908 | } | |
10909 | else | |
10910 | { | |
c19d1205 ZW |
10911 | constraint (inst.instruction > 0xffff |
10912 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
10913 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
10914 | _("unshifted register required")); | |
fdfde340 | 10915 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10916 | BAD_HIREG); |
b99bd4ef | 10917 | |
c19d1205 | 10918 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10919 | inst.instruction |= Rn; |
10920 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10921 | } |
b99bd4ef NC |
10922 | } |
10923 | ||
b05fe5cf | 10924 | static void |
c19d1205 | 10925 | do_t_mrs (void) |
b05fe5cf | 10926 | { |
fdfde340 | 10927 | unsigned Rd; |
037e8744 JB |
10928 | |
10929 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
10930 | return; | |
10931 | ||
90ec0d68 MGD |
10932 | Rd = inst.operands[0].reg; |
10933 | reject_bad_reg (Rd); | |
10934 | inst.instruction |= Rd << 8; | |
10935 | ||
10936 | if (inst.operands[1].isreg) | |
62b3e311 | 10937 | { |
90ec0d68 MGD |
10938 | unsigned br = inst.operands[1].reg; |
10939 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
10940 | as_bad (_("bad register for mrs")); | |
10941 | ||
10942 | inst.instruction |= br & (0xf << 16); | |
10943 | inst.instruction |= (br & 0x300) >> 4; | |
10944 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
10945 | } |
10946 | else | |
10947 | { | |
90ec0d68 | 10948 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 10949 | |
d2cd1205 JB |
10950 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
10951 | constraint (flags != 0, _("selected processor does not support " | |
10952 | "requested special purpose register")); | |
90ec0d68 | 10953 | else |
d2cd1205 JB |
10954 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
10955 | devices). */ | |
10956 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
10957 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 10958 | |
90ec0d68 MGD |
10959 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
10960 | inst.instruction |= inst.operands[1].imm & 0xff; | |
10961 | inst.instruction |= 0xf0000; | |
10962 | } | |
c19d1205 | 10963 | } |
b05fe5cf | 10964 | |
c19d1205 ZW |
10965 | static void |
10966 | do_t_msr (void) | |
10967 | { | |
62b3e311 | 10968 | int flags; |
fdfde340 | 10969 | unsigned Rn; |
62b3e311 | 10970 | |
037e8744 JB |
10971 | if (do_vfp_nsyn_msr () == SUCCESS) |
10972 | return; | |
10973 | ||
c19d1205 ZW |
10974 | constraint (!inst.operands[1].isreg, |
10975 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
10976 | |
10977 | if (inst.operands[0].isreg) | |
10978 | flags = (int)(inst.operands[0].reg); | |
10979 | else | |
10980 | flags = inst.operands[0].imm; | |
10981 | ||
d2cd1205 | 10982 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 10983 | { |
d2cd1205 JB |
10984 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
10985 | ||
10986 | constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
10987 | && (bits & ~(PSR_s | PSR_f)) != 0) | |
10988 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
10989 | && bits != PSR_f), | |
10990 | _("selected processor does not support requested special " | |
10991 | "purpose register")); | |
62b3e311 PB |
10992 | } |
10993 | else | |
d2cd1205 JB |
10994 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
10995 | "requested special purpose register")); | |
c921be7d | 10996 | |
fdfde340 JM |
10997 | Rn = inst.operands[1].reg; |
10998 | reject_bad_reg (Rn); | |
10999 | ||
62b3e311 | 11000 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11001 | inst.instruction |= (flags & 0xf0000) >> 8; |
11002 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11003 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11004 | inst.instruction |= Rn << 16; |
c19d1205 | 11005 | } |
b05fe5cf | 11006 | |
c19d1205 ZW |
11007 | static void |
11008 | do_t_mul (void) | |
11009 | { | |
17828f45 | 11010 | bfd_boolean narrow; |
fdfde340 | 11011 | unsigned Rd, Rn, Rm; |
17828f45 | 11012 | |
c19d1205 ZW |
11013 | if (!inst.operands[2].present) |
11014 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11015 | |
fdfde340 JM |
11016 | Rd = inst.operands[0].reg; |
11017 | Rn = inst.operands[1].reg; | |
11018 | Rm = inst.operands[2].reg; | |
11019 | ||
17828f45 | 11020 | if (unified_syntax) |
b05fe5cf | 11021 | { |
17828f45 | 11022 | if (inst.size_req == 4 |
fdfde340 JM |
11023 | || (Rd != Rn |
11024 | && Rd != Rm) | |
11025 | || Rn > 7 | |
11026 | || Rm > 7) | |
17828f45 JM |
11027 | narrow = FALSE; |
11028 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 11029 | narrow = !in_it_block (); |
17828f45 | 11030 | else |
e07e6e58 | 11031 | narrow = in_it_block (); |
b05fe5cf | 11032 | } |
c19d1205 | 11033 | else |
b05fe5cf | 11034 | { |
17828f45 | 11035 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 11036 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11037 | BAD_HIREG); |
17828f45 JM |
11038 | narrow = TRUE; |
11039 | } | |
b05fe5cf | 11040 | |
17828f45 JM |
11041 | if (narrow) |
11042 | { | |
11043 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 11044 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 11045 | inst.instruction |= Rd; |
b05fe5cf | 11046 | |
fdfde340 JM |
11047 | if (Rd == Rn) |
11048 | inst.instruction |= Rm << 3; | |
11049 | else if (Rd == Rm) | |
11050 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
11051 | else |
11052 | constraint (1, _("dest must overlap one source register")); | |
11053 | } | |
17828f45 JM |
11054 | else |
11055 | { | |
e07e6e58 NC |
11056 | constraint (inst.instruction != T_MNEM_mul, |
11057 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
11058 | /* 32-bit MUL. */ |
11059 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11060 | inst.instruction |= Rd << 8; |
11061 | inst.instruction |= Rn << 16; | |
11062 | inst.instruction |= Rm << 0; | |
11063 | ||
11064 | reject_bad_reg (Rd); | |
11065 | reject_bad_reg (Rn); | |
11066 | reject_bad_reg (Rm); | |
17828f45 | 11067 | } |
c19d1205 | 11068 | } |
b05fe5cf | 11069 | |
c19d1205 ZW |
11070 | static void |
11071 | do_t_mull (void) | |
11072 | { | |
fdfde340 | 11073 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 11074 | |
fdfde340 JM |
11075 | RdLo = inst.operands[0].reg; |
11076 | RdHi = inst.operands[1].reg; | |
11077 | Rn = inst.operands[2].reg; | |
11078 | Rm = inst.operands[3].reg; | |
11079 | ||
11080 | reject_bad_reg (RdLo); | |
11081 | reject_bad_reg (RdHi); | |
11082 | reject_bad_reg (Rn); | |
11083 | reject_bad_reg (Rm); | |
11084 | ||
11085 | inst.instruction |= RdLo << 12; | |
11086 | inst.instruction |= RdHi << 8; | |
11087 | inst.instruction |= Rn << 16; | |
11088 | inst.instruction |= Rm; | |
11089 | ||
11090 | if (RdLo == RdHi) | |
c19d1205 ZW |
11091 | as_tsktsk (_("rdhi and rdlo must be different")); |
11092 | } | |
b05fe5cf | 11093 | |
c19d1205 ZW |
11094 | static void |
11095 | do_t_nop (void) | |
11096 | { | |
e07e6e58 NC |
11097 | set_it_insn_type (NEUTRAL_IT_INSN); |
11098 | ||
c19d1205 ZW |
11099 | if (unified_syntax) |
11100 | { | |
11101 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 11102 | { |
c19d1205 ZW |
11103 | inst.instruction = THUMB_OP32 (inst.instruction); |
11104 | inst.instruction |= inst.operands[0].imm; | |
11105 | } | |
11106 | else | |
11107 | { | |
bc2d1808 NC |
11108 | /* PR9722: Check for Thumb2 availability before |
11109 | generating a thumb2 nop instruction. */ | |
afa62d5e | 11110 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
11111 | { |
11112 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11113 | inst.instruction |= inst.operands[0].imm << 4; | |
11114 | } | |
11115 | else | |
11116 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
11117 | } |
11118 | } | |
11119 | else | |
11120 | { | |
11121 | constraint (inst.operands[0].present, | |
11122 | _("Thumb does not support NOP with hints")); | |
11123 | inst.instruction = 0x46c0; | |
11124 | } | |
11125 | } | |
b05fe5cf | 11126 | |
c19d1205 ZW |
11127 | static void |
11128 | do_t_neg (void) | |
11129 | { | |
11130 | if (unified_syntax) | |
11131 | { | |
3d388997 PB |
11132 | bfd_boolean narrow; |
11133 | ||
11134 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11135 | narrow = !in_it_block (); |
3d388997 | 11136 | else |
e07e6e58 | 11137 | narrow = in_it_block (); |
3d388997 PB |
11138 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11139 | narrow = FALSE; | |
11140 | if (inst.size_req == 4) | |
11141 | narrow = FALSE; | |
11142 | ||
11143 | if (!narrow) | |
c19d1205 ZW |
11144 | { |
11145 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11146 | inst.instruction |= inst.operands[0].reg << 8; | |
11147 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
11148 | } |
11149 | else | |
11150 | { | |
c19d1205 ZW |
11151 | inst.instruction = THUMB_OP16 (inst.instruction); |
11152 | inst.instruction |= inst.operands[0].reg; | |
11153 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
11154 | } |
11155 | } | |
11156 | else | |
11157 | { | |
c19d1205 ZW |
11158 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
11159 | BAD_HIREG); | |
11160 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
11161 | ||
11162 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11163 | inst.instruction |= inst.operands[0].reg; | |
11164 | inst.instruction |= inst.operands[1].reg << 3; | |
11165 | } | |
11166 | } | |
11167 | ||
1c444d06 JM |
11168 | static void |
11169 | do_t_orn (void) | |
11170 | { | |
11171 | unsigned Rd, Rn; | |
11172 | ||
11173 | Rd = inst.operands[0].reg; | |
11174 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
11175 | ||
fdfde340 JM |
11176 | reject_bad_reg (Rd); |
11177 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
11178 | reject_bad_reg (Rn); | |
11179 | ||
1c444d06 JM |
11180 | inst.instruction |= Rd << 8; |
11181 | inst.instruction |= Rn << 16; | |
11182 | ||
11183 | if (!inst.operands[2].isreg) | |
11184 | { | |
11185 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11186 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11187 | } | |
11188 | else | |
11189 | { | |
11190 | unsigned Rm; | |
11191 | ||
11192 | Rm = inst.operands[2].reg; | |
fdfde340 | 11193 | reject_bad_reg (Rm); |
1c444d06 JM |
11194 | |
11195 | constraint (inst.operands[2].shifted | |
11196 | && inst.operands[2].immisreg, | |
11197 | _("shift must be constant")); | |
11198 | encode_thumb32_shifted_operand (2); | |
11199 | } | |
11200 | } | |
11201 | ||
c19d1205 ZW |
11202 | static void |
11203 | do_t_pkhbt (void) | |
11204 | { | |
fdfde340 JM |
11205 | unsigned Rd, Rn, Rm; |
11206 | ||
11207 | Rd = inst.operands[0].reg; | |
11208 | Rn = inst.operands[1].reg; | |
11209 | Rm = inst.operands[2].reg; | |
11210 | ||
11211 | reject_bad_reg (Rd); | |
11212 | reject_bad_reg (Rn); | |
11213 | reject_bad_reg (Rm); | |
11214 | ||
11215 | inst.instruction |= Rd << 8; | |
11216 | inst.instruction |= Rn << 16; | |
11217 | inst.instruction |= Rm; | |
c19d1205 ZW |
11218 | if (inst.operands[3].present) |
11219 | { | |
11220 | unsigned int val = inst.reloc.exp.X_add_number; | |
11221 | constraint (inst.reloc.exp.X_op != O_constant, | |
11222 | _("expression too complex")); | |
11223 | inst.instruction |= (val & 0x1c) << 10; | |
11224 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 11225 | } |
c19d1205 | 11226 | } |
b05fe5cf | 11227 | |
c19d1205 ZW |
11228 | static void |
11229 | do_t_pkhtb (void) | |
11230 | { | |
11231 | if (!inst.operands[3].present) | |
1ef52f49 NC |
11232 | { |
11233 | unsigned Rtmp; | |
11234 | ||
11235 | inst.instruction &= ~0x00000020; | |
11236 | ||
11237 | /* PR 10168. Swap the Rm and Rn registers. */ | |
11238 | Rtmp = inst.operands[1].reg; | |
11239 | inst.operands[1].reg = inst.operands[2].reg; | |
11240 | inst.operands[2].reg = Rtmp; | |
11241 | } | |
c19d1205 | 11242 | do_t_pkhbt (); |
b05fe5cf ZW |
11243 | } |
11244 | ||
c19d1205 ZW |
11245 | static void |
11246 | do_t_pld (void) | |
11247 | { | |
fdfde340 JM |
11248 | if (inst.operands[0].immisreg) |
11249 | reject_bad_reg (inst.operands[0].imm); | |
11250 | ||
c19d1205 ZW |
11251 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
11252 | } | |
b05fe5cf | 11253 | |
c19d1205 ZW |
11254 | static void |
11255 | do_t_push_pop (void) | |
b99bd4ef | 11256 | { |
e9f89963 | 11257 | unsigned mask; |
5f4273c7 | 11258 | |
c19d1205 ZW |
11259 | constraint (inst.operands[0].writeback, |
11260 | _("push/pop do not support {reglist}^")); | |
11261 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11262 | _("expression too complex")); | |
b99bd4ef | 11263 | |
e9f89963 PB |
11264 | mask = inst.operands[0].imm; |
11265 | if ((mask & ~0xff) == 0) | |
3c707909 | 11266 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 11267 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 11268 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 11269 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 11270 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 11271 | { |
c19d1205 ZW |
11272 | inst.instruction = THUMB_OP16 (inst.instruction); |
11273 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 11274 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
11275 | } |
11276 | else if (unified_syntax) | |
11277 | { | |
3c707909 | 11278 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 11279 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
11280 | } |
11281 | else | |
11282 | { | |
11283 | inst.error = _("invalid register list to push/pop instruction"); | |
11284 | return; | |
11285 | } | |
c19d1205 | 11286 | } |
b99bd4ef | 11287 | |
c19d1205 ZW |
11288 | static void |
11289 | do_t_rbit (void) | |
11290 | { | |
fdfde340 JM |
11291 | unsigned Rd, Rm; |
11292 | ||
11293 | Rd = inst.operands[0].reg; | |
11294 | Rm = inst.operands[1].reg; | |
11295 | ||
11296 | reject_bad_reg (Rd); | |
11297 | reject_bad_reg (Rm); | |
11298 | ||
11299 | inst.instruction |= Rd << 8; | |
11300 | inst.instruction |= Rm << 16; | |
11301 | inst.instruction |= Rm; | |
c19d1205 | 11302 | } |
b99bd4ef | 11303 | |
c19d1205 ZW |
11304 | static void |
11305 | do_t_rev (void) | |
11306 | { | |
fdfde340 JM |
11307 | unsigned Rd, Rm; |
11308 | ||
11309 | Rd = inst.operands[0].reg; | |
11310 | Rm = inst.operands[1].reg; | |
11311 | ||
11312 | reject_bad_reg (Rd); | |
11313 | reject_bad_reg (Rm); | |
11314 | ||
11315 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
11316 | && inst.size_req != 4) |
11317 | { | |
11318 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
11319 | inst.instruction |= Rd; |
11320 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11321 | } |
11322 | else if (unified_syntax) | |
11323 | { | |
11324 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11325 | inst.instruction |= Rd << 8; |
11326 | inst.instruction |= Rm << 16; | |
11327 | inst.instruction |= Rm; | |
c19d1205 ZW |
11328 | } |
11329 | else | |
11330 | inst.error = BAD_HIREG; | |
11331 | } | |
b99bd4ef | 11332 | |
1c444d06 JM |
11333 | static void |
11334 | do_t_rrx (void) | |
11335 | { | |
11336 | unsigned Rd, Rm; | |
11337 | ||
11338 | Rd = inst.operands[0].reg; | |
11339 | Rm = inst.operands[1].reg; | |
11340 | ||
fdfde340 JM |
11341 | reject_bad_reg (Rd); |
11342 | reject_bad_reg (Rm); | |
c921be7d | 11343 | |
1c444d06 JM |
11344 | inst.instruction |= Rd << 8; |
11345 | inst.instruction |= Rm; | |
11346 | } | |
11347 | ||
c19d1205 ZW |
11348 | static void |
11349 | do_t_rsb (void) | |
11350 | { | |
fdfde340 | 11351 | unsigned Rd, Rs; |
b99bd4ef | 11352 | |
c19d1205 ZW |
11353 | Rd = inst.operands[0].reg; |
11354 | Rs = (inst.operands[1].present | |
11355 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11356 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11357 | |
fdfde340 JM |
11358 | reject_bad_reg (Rd); |
11359 | reject_bad_reg (Rs); | |
11360 | if (inst.operands[2].isreg) | |
11361 | reject_bad_reg (inst.operands[2].reg); | |
11362 | ||
c19d1205 ZW |
11363 | inst.instruction |= Rd << 8; |
11364 | inst.instruction |= Rs << 16; | |
11365 | if (!inst.operands[2].isreg) | |
11366 | { | |
026d3abb PB |
11367 | bfd_boolean narrow; |
11368 | ||
11369 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11370 | narrow = !in_it_block (); |
026d3abb | 11371 | else |
e07e6e58 | 11372 | narrow = in_it_block (); |
026d3abb PB |
11373 | |
11374 | if (Rd > 7 || Rs > 7) | |
11375 | narrow = FALSE; | |
11376 | ||
11377 | if (inst.size_req == 4 || !unified_syntax) | |
11378 | narrow = FALSE; | |
11379 | ||
11380 | if (inst.reloc.exp.X_op != O_constant | |
11381 | || inst.reloc.exp.X_add_number != 0) | |
11382 | narrow = FALSE; | |
11383 | ||
11384 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11385 | relaxation, but it doesn't seem worth the hassle. */ | |
11386 | if (narrow) | |
11387 | { | |
11388 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11389 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11390 | inst.instruction |= Rs << 3; | |
11391 | inst.instruction |= Rd; | |
11392 | } | |
11393 | else | |
11394 | { | |
11395 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11396 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11397 | } | |
c19d1205 ZW |
11398 | } |
11399 | else | |
11400 | encode_thumb32_shifted_operand (2); | |
11401 | } | |
b99bd4ef | 11402 | |
c19d1205 ZW |
11403 | static void |
11404 | do_t_setend (void) | |
11405 | { | |
e07e6e58 | 11406 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11407 | if (inst.operands[0].imm) |
11408 | inst.instruction |= 0x8; | |
11409 | } | |
b99bd4ef | 11410 | |
c19d1205 ZW |
11411 | static void |
11412 | do_t_shift (void) | |
11413 | { | |
11414 | if (!inst.operands[1].present) | |
11415 | inst.operands[1].reg = inst.operands[0].reg; | |
11416 | ||
11417 | if (unified_syntax) | |
11418 | { | |
3d388997 PB |
11419 | bfd_boolean narrow; |
11420 | int shift_kind; | |
11421 | ||
11422 | switch (inst.instruction) | |
11423 | { | |
11424 | case T_MNEM_asr: | |
11425 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11426 | case T_MNEM_lsl: | |
11427 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11428 | case T_MNEM_lsr: | |
11429 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11430 | case T_MNEM_ror: | |
11431 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11432 | default: abort (); | |
11433 | } | |
11434 | ||
11435 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11436 | narrow = !in_it_block (); |
3d388997 | 11437 | else |
e07e6e58 | 11438 | narrow = in_it_block (); |
3d388997 PB |
11439 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11440 | narrow = FALSE; | |
11441 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11442 | narrow = FALSE; | |
11443 | if (inst.operands[2].isreg | |
11444 | && (inst.operands[1].reg != inst.operands[0].reg | |
11445 | || inst.operands[2].reg > 7)) | |
11446 | narrow = FALSE; | |
11447 | if (inst.size_req == 4) | |
11448 | narrow = FALSE; | |
11449 | ||
fdfde340 JM |
11450 | reject_bad_reg (inst.operands[0].reg); |
11451 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11452 | |
3d388997 | 11453 | if (!narrow) |
c19d1205 ZW |
11454 | { |
11455 | if (inst.operands[2].isreg) | |
b99bd4ef | 11456 | { |
fdfde340 | 11457 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11458 | inst.instruction = THUMB_OP32 (inst.instruction); |
11459 | inst.instruction |= inst.operands[0].reg << 8; | |
11460 | inst.instruction |= inst.operands[1].reg << 16; | |
11461 | inst.instruction |= inst.operands[2].reg; | |
11462 | } | |
11463 | else | |
11464 | { | |
11465 | inst.operands[1].shifted = 1; | |
3d388997 | 11466 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11467 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11468 | ? T_MNEM_movs : T_MNEM_mov); | |
11469 | inst.instruction |= inst.operands[0].reg << 8; | |
11470 | encode_thumb32_shifted_operand (1); | |
11471 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11472 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11473 | } |
11474 | } | |
11475 | else | |
11476 | { | |
c19d1205 | 11477 | if (inst.operands[2].isreg) |
b99bd4ef | 11478 | { |
3d388997 | 11479 | switch (shift_kind) |
b99bd4ef | 11480 | { |
3d388997 PB |
11481 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11482 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11483 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11484 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11485 | default: abort (); |
b99bd4ef | 11486 | } |
5f4273c7 | 11487 | |
c19d1205 ZW |
11488 | inst.instruction |= inst.operands[0].reg; |
11489 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
11490 | } |
11491 | else | |
11492 | { | |
3d388997 | 11493 | switch (shift_kind) |
b99bd4ef | 11494 | { |
3d388997 PB |
11495 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11496 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11497 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11498 | default: abort (); |
b99bd4ef | 11499 | } |
c19d1205 ZW |
11500 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11501 | inst.instruction |= inst.operands[0].reg; | |
11502 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11503 | } |
11504 | } | |
c19d1205 ZW |
11505 | } |
11506 | else | |
11507 | { | |
11508 | constraint (inst.operands[0].reg > 7 | |
11509 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11510 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11511 | |
c19d1205 ZW |
11512 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11513 | { | |
11514 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11515 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11516 | _("source1 and dest must be same register")); | |
b99bd4ef | 11517 | |
c19d1205 ZW |
11518 | switch (inst.instruction) |
11519 | { | |
11520 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11521 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11522 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11523 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11524 | default: abort (); | |
11525 | } | |
5f4273c7 | 11526 | |
c19d1205 ZW |
11527 | inst.instruction |= inst.operands[0].reg; |
11528 | inst.instruction |= inst.operands[2].reg << 3; | |
11529 | } | |
11530 | else | |
b99bd4ef | 11531 | { |
c19d1205 ZW |
11532 | switch (inst.instruction) |
11533 | { | |
11534 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11535 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11536 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11537 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11538 | default: abort (); | |
11539 | } | |
11540 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11541 | inst.instruction |= inst.operands[0].reg; | |
11542 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11543 | } |
11544 | } | |
b99bd4ef NC |
11545 | } |
11546 | ||
11547 | static void | |
c19d1205 | 11548 | do_t_simd (void) |
b99bd4ef | 11549 | { |
fdfde340 JM |
11550 | unsigned Rd, Rn, Rm; |
11551 | ||
11552 | Rd = inst.operands[0].reg; | |
11553 | Rn = inst.operands[1].reg; | |
11554 | Rm = inst.operands[2].reg; | |
11555 | ||
11556 | reject_bad_reg (Rd); | |
11557 | reject_bad_reg (Rn); | |
11558 | reject_bad_reg (Rm); | |
11559 | ||
11560 | inst.instruction |= Rd << 8; | |
11561 | inst.instruction |= Rn << 16; | |
11562 | inst.instruction |= Rm; | |
c19d1205 | 11563 | } |
b99bd4ef | 11564 | |
03ee1b7f NC |
11565 | static void |
11566 | do_t_simd2 (void) | |
11567 | { | |
11568 | unsigned Rd, Rn, Rm; | |
11569 | ||
11570 | Rd = inst.operands[0].reg; | |
11571 | Rm = inst.operands[1].reg; | |
11572 | Rn = inst.operands[2].reg; | |
11573 | ||
11574 | reject_bad_reg (Rd); | |
11575 | reject_bad_reg (Rn); | |
11576 | reject_bad_reg (Rm); | |
11577 | ||
11578 | inst.instruction |= Rd << 8; | |
11579 | inst.instruction |= Rn << 16; | |
11580 | inst.instruction |= Rm; | |
11581 | } | |
11582 | ||
c19d1205 | 11583 | static void |
3eb17e6b | 11584 | do_t_smc (void) |
c19d1205 ZW |
11585 | { |
11586 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
11587 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
11588 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
11589 | constraint (inst.reloc.exp.X_op != O_constant, |
11590 | _("expression too complex")); | |
11591 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11592 | inst.instruction |= (value & 0xf000) >> 12; | |
11593 | inst.instruction |= (value & 0x0ff0); | |
11594 | inst.instruction |= (value & 0x000f) << 16; | |
11595 | } | |
b99bd4ef | 11596 | |
90ec0d68 MGD |
11597 | static void |
11598 | do_t_hvc (void) | |
11599 | { | |
11600 | unsigned int value = inst.reloc.exp.X_add_number; | |
11601 | ||
11602 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11603 | inst.instruction |= (value & 0x0fff); | |
11604 | inst.instruction |= (value & 0xf000) << 4; | |
11605 | } | |
11606 | ||
c19d1205 | 11607 | static void |
3a21c15a | 11608 | do_t_ssat_usat (int bias) |
c19d1205 | 11609 | { |
fdfde340 JM |
11610 | unsigned Rd, Rn; |
11611 | ||
11612 | Rd = inst.operands[0].reg; | |
11613 | Rn = inst.operands[2].reg; | |
11614 | ||
11615 | reject_bad_reg (Rd); | |
11616 | reject_bad_reg (Rn); | |
11617 | ||
11618 | inst.instruction |= Rd << 8; | |
3a21c15a | 11619 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11620 | inst.instruction |= Rn << 16; |
b99bd4ef | 11621 | |
c19d1205 | 11622 | if (inst.operands[3].present) |
b99bd4ef | 11623 | { |
3a21c15a NC |
11624 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
11625 | ||
11626 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11627 | ||
c19d1205 ZW |
11628 | constraint (inst.reloc.exp.X_op != O_constant, |
11629 | _("expression too complex")); | |
b99bd4ef | 11630 | |
3a21c15a | 11631 | if (shift_amount != 0) |
6189168b | 11632 | { |
3a21c15a NC |
11633 | constraint (shift_amount > 31, |
11634 | _("shift expression is too large")); | |
11635 | ||
c19d1205 | 11636 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
11637 | inst.instruction |= 0x00200000; /* sh bit. */ |
11638 | ||
11639 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
11640 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
11641 | } |
11642 | } | |
b99bd4ef | 11643 | } |
c921be7d | 11644 | |
3a21c15a NC |
11645 | static void |
11646 | do_t_ssat (void) | |
11647 | { | |
11648 | do_t_ssat_usat (1); | |
11649 | } | |
b99bd4ef | 11650 | |
0dd132b6 | 11651 | static void |
c19d1205 | 11652 | do_t_ssat16 (void) |
0dd132b6 | 11653 | { |
fdfde340 JM |
11654 | unsigned Rd, Rn; |
11655 | ||
11656 | Rd = inst.operands[0].reg; | |
11657 | Rn = inst.operands[2].reg; | |
11658 | ||
11659 | reject_bad_reg (Rd); | |
11660 | reject_bad_reg (Rn); | |
11661 | ||
11662 | inst.instruction |= Rd << 8; | |
c19d1205 | 11663 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 11664 | inst.instruction |= Rn << 16; |
c19d1205 | 11665 | } |
0dd132b6 | 11666 | |
c19d1205 ZW |
11667 | static void |
11668 | do_t_strex (void) | |
11669 | { | |
11670 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
11671 | || inst.operands[2].postind || inst.operands[2].writeback | |
11672 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
11673 | || inst.operands[2].negative, | |
01cfc07f | 11674 | BAD_ADDR_MODE); |
0dd132b6 | 11675 | |
5be8be5d DG |
11676 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
11677 | ||
c19d1205 ZW |
11678 | inst.instruction |= inst.operands[0].reg << 8; |
11679 | inst.instruction |= inst.operands[1].reg << 12; | |
11680 | inst.instruction |= inst.operands[2].reg << 16; | |
11681 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
11682 | } |
11683 | ||
b99bd4ef | 11684 | static void |
c19d1205 | 11685 | do_t_strexd (void) |
b99bd4ef | 11686 | { |
c19d1205 ZW |
11687 | if (!inst.operands[2].present) |
11688 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 11689 | |
c19d1205 ZW |
11690 | constraint (inst.operands[0].reg == inst.operands[1].reg |
11691 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 11692 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 11693 | BAD_OVERLAP); |
b99bd4ef | 11694 | |
c19d1205 ZW |
11695 | inst.instruction |= inst.operands[0].reg; |
11696 | inst.instruction |= inst.operands[1].reg << 12; | |
11697 | inst.instruction |= inst.operands[2].reg << 8; | |
11698 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
11699 | } |
11700 | ||
11701 | static void | |
c19d1205 | 11702 | do_t_sxtah (void) |
b99bd4ef | 11703 | { |
fdfde340 JM |
11704 | unsigned Rd, Rn, Rm; |
11705 | ||
11706 | Rd = inst.operands[0].reg; | |
11707 | Rn = inst.operands[1].reg; | |
11708 | Rm = inst.operands[2].reg; | |
11709 | ||
11710 | reject_bad_reg (Rd); | |
11711 | reject_bad_reg (Rn); | |
11712 | reject_bad_reg (Rm); | |
11713 | ||
11714 | inst.instruction |= Rd << 8; | |
11715 | inst.instruction |= Rn << 16; | |
11716 | inst.instruction |= Rm; | |
c19d1205 ZW |
11717 | inst.instruction |= inst.operands[3].imm << 4; |
11718 | } | |
b99bd4ef | 11719 | |
c19d1205 ZW |
11720 | static void |
11721 | do_t_sxth (void) | |
11722 | { | |
fdfde340 JM |
11723 | unsigned Rd, Rm; |
11724 | ||
11725 | Rd = inst.operands[0].reg; | |
11726 | Rm = inst.operands[1].reg; | |
11727 | ||
11728 | reject_bad_reg (Rd); | |
11729 | reject_bad_reg (Rm); | |
c921be7d NC |
11730 | |
11731 | if (inst.instruction <= 0xffff | |
11732 | && inst.size_req != 4 | |
fdfde340 | 11733 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 11734 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 11735 | { |
c19d1205 | 11736 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11737 | inst.instruction |= Rd; |
11738 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11739 | } |
c19d1205 | 11740 | else if (unified_syntax) |
b99bd4ef | 11741 | { |
c19d1205 ZW |
11742 | if (inst.instruction <= 0xffff) |
11743 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11744 | inst.instruction |= Rd << 8; |
11745 | inst.instruction |= Rm; | |
c19d1205 | 11746 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 11747 | } |
c19d1205 | 11748 | else |
b99bd4ef | 11749 | { |
c19d1205 ZW |
11750 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
11751 | _("Thumb encoding does not support rotation")); | |
11752 | constraint (1, BAD_HIREG); | |
b99bd4ef | 11753 | } |
c19d1205 | 11754 | } |
b99bd4ef | 11755 | |
c19d1205 ZW |
11756 | static void |
11757 | do_t_swi (void) | |
11758 | { | |
b2a5fbdc MGD |
11759 | /* We have to do the following check manually as ARM_EXT_OS only applies |
11760 | to ARM_EXT_V6M. */ | |
11761 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
11762 | { | |
ac7f631b NC |
11763 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
11764 | /* This only applies to the v6m howver, not later architectures. */ | |
11765 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
11766 | as_bad (_("SVC is not permitted on this architecture")); |
11767 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
11768 | } | |
11769 | ||
c19d1205 ZW |
11770 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
11771 | } | |
b99bd4ef | 11772 | |
92e90b6e PB |
11773 | static void |
11774 | do_t_tb (void) | |
11775 | { | |
fdfde340 | 11776 | unsigned Rn, Rm; |
92e90b6e PB |
11777 | int half; |
11778 | ||
11779 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 11780 | set_it_insn_type_last (); |
dfa9f0d5 PB |
11781 | constraint (inst.operands[0].immisreg, |
11782 | _("instruction requires register index")); | |
fdfde340 JM |
11783 | |
11784 | Rn = inst.operands[0].reg; | |
11785 | Rm = inst.operands[0].imm; | |
c921be7d | 11786 | |
fdfde340 JM |
11787 | constraint (Rn == REG_SP, BAD_SP); |
11788 | reject_bad_reg (Rm); | |
11789 | ||
92e90b6e PB |
11790 | constraint (!half && inst.operands[0].shifted, |
11791 | _("instruction does not allow shifted index")); | |
fdfde340 | 11792 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
11793 | } |
11794 | ||
c19d1205 ZW |
11795 | static void |
11796 | do_t_usat (void) | |
11797 | { | |
3a21c15a | 11798 | do_t_ssat_usat (0); |
b99bd4ef NC |
11799 | } |
11800 | ||
11801 | static void | |
c19d1205 | 11802 | do_t_usat16 (void) |
b99bd4ef | 11803 | { |
fdfde340 JM |
11804 | unsigned Rd, Rn; |
11805 | ||
11806 | Rd = inst.operands[0].reg; | |
11807 | Rn = inst.operands[2].reg; | |
11808 | ||
11809 | reject_bad_reg (Rd); | |
11810 | reject_bad_reg (Rn); | |
11811 | ||
11812 | inst.instruction |= Rd << 8; | |
c19d1205 | 11813 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 11814 | inst.instruction |= Rn << 16; |
b99bd4ef | 11815 | } |
c19d1205 | 11816 | |
5287ad62 | 11817 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 11818 | |
5287ad62 | 11819 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 11820 | |
5287ad62 JB |
11821 | /* An "invalid" code for the following tables. */ |
11822 | #define N_INV -1u | |
11823 | ||
11824 | struct neon_tab_entry | |
b99bd4ef | 11825 | { |
5287ad62 JB |
11826 | unsigned integer; |
11827 | unsigned float_or_poly; | |
11828 | unsigned scalar_or_imm; | |
11829 | }; | |
5f4273c7 | 11830 | |
5287ad62 JB |
11831 | /* Map overloaded Neon opcodes to their respective encodings. */ |
11832 | #define NEON_ENC_TAB \ | |
11833 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
11834 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
11835 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
11836 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
11837 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
11838 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
11839 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
11840 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
11841 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
11842 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
11843 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
11844 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 11845 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
11846 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
11847 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
11848 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
11849 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
11850 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
11851 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
11852 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
11853 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
11854 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
11855 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
11856 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
11857 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
11858 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
11859 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
11860 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
11861 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
11862 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
11863 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
11864 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
11865 | X(veor, 0x1000110, N_INV, N_INV), \ | |
11866 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
11867 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
11868 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
11869 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
11870 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
11871 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
11872 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
11873 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
11874 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
11875 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
11876 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
11877 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
11878 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
11879 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
11880 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
11881 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
11882 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
11883 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
11884 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
11885 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
11886 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
11887 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
11888 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
11889 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
11890 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
11891 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
11892 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
11893 | |
11894 | enum neon_opc | |
11895 | { | |
11896 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
11897 | NEON_ENC_TAB | |
11898 | #undef X | |
11899 | }; | |
b99bd4ef | 11900 | |
5287ad62 JB |
11901 | static const struct neon_tab_entry neon_enc_tab[] = |
11902 | { | |
11903 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
11904 | NEON_ENC_TAB | |
11905 | #undef X | |
11906 | }; | |
b99bd4ef | 11907 | |
88714cb8 DG |
11908 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
11909 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11910 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11911 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11912 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11913 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11914 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11915 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11916 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11917 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11918 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 11919 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 11920 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 11921 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 11922 | |
88714cb8 DG |
11923 | #define NEON_ENCODE(type, inst) \ |
11924 | do \ | |
11925 | { \ | |
11926 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
11927 | inst.is_neon = 1; \ | |
11928 | } \ | |
11929 | while (0) | |
11930 | ||
11931 | #define check_neon_suffixes \ | |
11932 | do \ | |
11933 | { \ | |
11934 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
11935 | { \ | |
11936 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
11937 | return; \ | |
11938 | } \ | |
11939 | } \ | |
11940 | while (0) | |
11941 | ||
037e8744 JB |
11942 | /* Define shapes for instruction operands. The following mnemonic characters |
11943 | are used in this table: | |
5287ad62 | 11944 | |
037e8744 | 11945 | F - VFP S<n> register |
5287ad62 JB |
11946 | D - Neon D<n> register |
11947 | Q - Neon Q<n> register | |
11948 | I - Immediate | |
11949 | S - Scalar | |
11950 | R - ARM register | |
11951 | L - D<n> register list | |
5f4273c7 | 11952 | |
037e8744 JB |
11953 | This table is used to generate various data: |
11954 | - enumerations of the form NS_DDR to be used as arguments to | |
11955 | neon_select_shape. | |
11956 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 11957 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 11958 | |
037e8744 JB |
11959 | #define NEON_SHAPE_DEF \ |
11960 | X(3, (D, D, D), DOUBLE), \ | |
11961 | X(3, (Q, Q, Q), QUAD), \ | |
11962 | X(3, (D, D, I), DOUBLE), \ | |
11963 | X(3, (Q, Q, I), QUAD), \ | |
11964 | X(3, (D, D, S), DOUBLE), \ | |
11965 | X(3, (Q, Q, S), QUAD), \ | |
11966 | X(2, (D, D), DOUBLE), \ | |
11967 | X(2, (Q, Q), QUAD), \ | |
11968 | X(2, (D, S), DOUBLE), \ | |
11969 | X(2, (Q, S), QUAD), \ | |
11970 | X(2, (D, R), DOUBLE), \ | |
11971 | X(2, (Q, R), QUAD), \ | |
11972 | X(2, (D, I), DOUBLE), \ | |
11973 | X(2, (Q, I), QUAD), \ | |
11974 | X(3, (D, L, D), DOUBLE), \ | |
11975 | X(2, (D, Q), MIXED), \ | |
11976 | X(2, (Q, D), MIXED), \ | |
11977 | X(3, (D, Q, I), MIXED), \ | |
11978 | X(3, (Q, D, I), MIXED), \ | |
11979 | X(3, (Q, D, D), MIXED), \ | |
11980 | X(3, (D, Q, Q), MIXED), \ | |
11981 | X(3, (Q, Q, D), MIXED), \ | |
11982 | X(3, (Q, D, S), MIXED), \ | |
11983 | X(3, (D, Q, S), MIXED), \ | |
11984 | X(4, (D, D, D, I), DOUBLE), \ | |
11985 | X(4, (Q, Q, Q, I), QUAD), \ | |
11986 | X(2, (F, F), SINGLE), \ | |
11987 | X(3, (F, F, F), SINGLE), \ | |
11988 | X(2, (F, I), SINGLE), \ | |
11989 | X(2, (F, D), MIXED), \ | |
11990 | X(2, (D, F), MIXED), \ | |
11991 | X(3, (F, F, I), MIXED), \ | |
11992 | X(4, (R, R, F, F), SINGLE), \ | |
11993 | X(4, (F, F, R, R), SINGLE), \ | |
11994 | X(3, (D, R, R), DOUBLE), \ | |
11995 | X(3, (R, R, D), DOUBLE), \ | |
11996 | X(2, (S, R), SINGLE), \ | |
11997 | X(2, (R, S), SINGLE), \ | |
11998 | X(2, (F, R), SINGLE), \ | |
11999 | X(2, (R, F), SINGLE) | |
12000 | ||
12001 | #define S2(A,B) NS_##A##B | |
12002 | #define S3(A,B,C) NS_##A##B##C | |
12003 | #define S4(A,B,C,D) NS_##A##B##C##D | |
12004 | ||
12005 | #define X(N, L, C) S##N L | |
12006 | ||
5287ad62 JB |
12007 | enum neon_shape |
12008 | { | |
037e8744 JB |
12009 | NEON_SHAPE_DEF, |
12010 | NS_NULL | |
5287ad62 | 12011 | }; |
b99bd4ef | 12012 | |
037e8744 JB |
12013 | #undef X |
12014 | #undef S2 | |
12015 | #undef S3 | |
12016 | #undef S4 | |
12017 | ||
12018 | enum neon_shape_class | |
12019 | { | |
12020 | SC_SINGLE, | |
12021 | SC_DOUBLE, | |
12022 | SC_QUAD, | |
12023 | SC_MIXED | |
12024 | }; | |
12025 | ||
12026 | #define X(N, L, C) SC_##C | |
12027 | ||
12028 | static enum neon_shape_class neon_shape_class[] = | |
12029 | { | |
12030 | NEON_SHAPE_DEF | |
12031 | }; | |
12032 | ||
12033 | #undef X | |
12034 | ||
12035 | enum neon_shape_el | |
12036 | { | |
12037 | SE_F, | |
12038 | SE_D, | |
12039 | SE_Q, | |
12040 | SE_I, | |
12041 | SE_S, | |
12042 | SE_R, | |
12043 | SE_L | |
12044 | }; | |
12045 | ||
12046 | /* Register widths of above. */ | |
12047 | static unsigned neon_shape_el_size[] = | |
12048 | { | |
12049 | 32, | |
12050 | 64, | |
12051 | 128, | |
12052 | 0, | |
12053 | 32, | |
12054 | 32, | |
12055 | 0 | |
12056 | }; | |
12057 | ||
12058 | struct neon_shape_info | |
12059 | { | |
12060 | unsigned els; | |
12061 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
12062 | }; | |
12063 | ||
12064 | #define S2(A,B) { SE_##A, SE_##B } | |
12065 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
12066 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
12067 | ||
12068 | #define X(N, L, C) { N, S##N L } | |
12069 | ||
12070 | static struct neon_shape_info neon_shape_tab[] = | |
12071 | { | |
12072 | NEON_SHAPE_DEF | |
12073 | }; | |
12074 | ||
12075 | #undef X | |
12076 | #undef S2 | |
12077 | #undef S3 | |
12078 | #undef S4 | |
12079 | ||
5287ad62 JB |
12080 | /* Bit masks used in type checking given instructions. |
12081 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
12082 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
12083 | set, various other bits can be set as well in order to modify the meaning of | |
12084 | the type constraint. */ | |
12085 | ||
12086 | enum neon_type_mask | |
12087 | { | |
8e79c3df CM |
12088 | N_S8 = 0x0000001, |
12089 | N_S16 = 0x0000002, | |
12090 | N_S32 = 0x0000004, | |
12091 | N_S64 = 0x0000008, | |
12092 | N_U8 = 0x0000010, | |
12093 | N_U16 = 0x0000020, | |
12094 | N_U32 = 0x0000040, | |
12095 | N_U64 = 0x0000080, | |
12096 | N_I8 = 0x0000100, | |
12097 | N_I16 = 0x0000200, | |
12098 | N_I32 = 0x0000400, | |
12099 | N_I64 = 0x0000800, | |
12100 | N_8 = 0x0001000, | |
12101 | N_16 = 0x0002000, | |
12102 | N_32 = 0x0004000, | |
12103 | N_64 = 0x0008000, | |
12104 | N_P8 = 0x0010000, | |
12105 | N_P16 = 0x0020000, | |
12106 | N_F16 = 0x0040000, | |
12107 | N_F32 = 0x0080000, | |
12108 | N_F64 = 0x0100000, | |
c921be7d NC |
12109 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
12110 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 12111 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
12112 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
12113 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
12114 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
12115 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
12116 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
12117 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
12118 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 12119 | N_UTYP = 0, |
037e8744 | 12120 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
12121 | }; |
12122 | ||
dcbf9037 JB |
12123 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
12124 | ||
5287ad62 JB |
12125 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
12126 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
12127 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
12128 | #define N_SUF_32 (N_SU_32 | N_F32) | |
12129 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
12130 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
12131 | ||
12132 | /* Pass this as the first type argument to neon_check_type to ignore types | |
12133 | altogether. */ | |
12134 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
12135 | ||
037e8744 JB |
12136 | /* Select a "shape" for the current instruction (describing register types or |
12137 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
12138 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
12139 | function of operand parsing, so this function doesn't need to be called. | |
12140 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
12141 | |
12142 | static enum neon_shape | |
037e8744 | 12143 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 12144 | { |
037e8744 JB |
12145 | va_list ap; |
12146 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
12147 | |
12148 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
12149 | many arguments we should have, so this makes the assumption that we have | |
12150 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
12151 | true in the future. */ | |
12152 | if (!inst.operands[1].present) | |
12153 | inst.operands[1] = inst.operands[0]; | |
12154 | ||
037e8744 | 12155 | va_start (ap, shape); |
5f4273c7 | 12156 | |
21d799b5 | 12157 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
12158 | { |
12159 | unsigned j; | |
12160 | int matches = 1; | |
12161 | ||
12162 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
12163 | { | |
12164 | if (!inst.operands[j].present) | |
12165 | { | |
12166 | matches = 0; | |
12167 | break; | |
12168 | } | |
12169 | ||
12170 | switch (neon_shape_tab[shape].el[j]) | |
12171 | { | |
12172 | case SE_F: | |
12173 | if (!(inst.operands[j].isreg | |
12174 | && inst.operands[j].isvec | |
12175 | && inst.operands[j].issingle | |
12176 | && !inst.operands[j].isquad)) | |
12177 | matches = 0; | |
12178 | break; | |
12179 | ||
12180 | case SE_D: | |
12181 | if (!(inst.operands[j].isreg | |
12182 | && inst.operands[j].isvec | |
12183 | && !inst.operands[j].isquad | |
12184 | && !inst.operands[j].issingle)) | |
12185 | matches = 0; | |
12186 | break; | |
12187 | ||
12188 | case SE_R: | |
12189 | if (!(inst.operands[j].isreg | |
12190 | && !inst.operands[j].isvec)) | |
12191 | matches = 0; | |
12192 | break; | |
12193 | ||
12194 | case SE_Q: | |
12195 | if (!(inst.operands[j].isreg | |
12196 | && inst.operands[j].isvec | |
12197 | && inst.operands[j].isquad | |
12198 | && !inst.operands[j].issingle)) | |
12199 | matches = 0; | |
12200 | break; | |
12201 | ||
12202 | case SE_I: | |
12203 | if (!(!inst.operands[j].isreg | |
12204 | && !inst.operands[j].isscalar)) | |
12205 | matches = 0; | |
12206 | break; | |
12207 | ||
12208 | case SE_S: | |
12209 | if (!(!inst.operands[j].isreg | |
12210 | && inst.operands[j].isscalar)) | |
12211 | matches = 0; | |
12212 | break; | |
12213 | ||
12214 | case SE_L: | |
12215 | break; | |
12216 | } | |
3fde54a2 JZ |
12217 | if (!matches) |
12218 | break; | |
037e8744 JB |
12219 | } |
12220 | if (matches) | |
5287ad62 | 12221 | break; |
037e8744 | 12222 | } |
5f4273c7 | 12223 | |
037e8744 | 12224 | va_end (ap); |
5287ad62 | 12225 | |
037e8744 JB |
12226 | if (shape == NS_NULL && first_shape != NS_NULL) |
12227 | first_error (_("invalid instruction shape")); | |
5287ad62 | 12228 | |
037e8744 JB |
12229 | return shape; |
12230 | } | |
5287ad62 | 12231 | |
037e8744 JB |
12232 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
12233 | means the Q bit should be set). */ | |
12234 | ||
12235 | static int | |
12236 | neon_quad (enum neon_shape shape) | |
12237 | { | |
12238 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 12239 | } |
037e8744 | 12240 | |
5287ad62 JB |
12241 | static void |
12242 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
12243 | unsigned *g_size) | |
12244 | { | |
12245 | /* Allow modification to be made to types which are constrained to be | |
12246 | based on the key element, based on bits set alongside N_EQK. */ | |
12247 | if ((typebits & N_EQK) != 0) | |
12248 | { | |
12249 | if ((typebits & N_HLF) != 0) | |
12250 | *g_size /= 2; | |
12251 | else if ((typebits & N_DBL) != 0) | |
12252 | *g_size *= 2; | |
12253 | if ((typebits & N_SGN) != 0) | |
12254 | *g_type = NT_signed; | |
12255 | else if ((typebits & N_UNS) != 0) | |
12256 | *g_type = NT_unsigned; | |
12257 | else if ((typebits & N_INT) != 0) | |
12258 | *g_type = NT_integer; | |
12259 | else if ((typebits & N_FLT) != 0) | |
12260 | *g_type = NT_float; | |
dcbf9037 JB |
12261 | else if ((typebits & N_SIZ) != 0) |
12262 | *g_type = NT_untyped; | |
5287ad62 JB |
12263 | } |
12264 | } | |
5f4273c7 | 12265 | |
5287ad62 JB |
12266 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
12267 | operand type, i.e. the single type specified in a Neon instruction when it | |
12268 | is the only one given. */ | |
12269 | ||
12270 | static struct neon_type_el | |
12271 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
12272 | { | |
12273 | struct neon_type_el dest = *key; | |
5f4273c7 | 12274 | |
9c2799c2 | 12275 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 12276 | |
5287ad62 JB |
12277 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
12278 | ||
12279 | return dest; | |
12280 | } | |
12281 | ||
12282 | /* Convert Neon type and size into compact bitmask representation. */ | |
12283 | ||
12284 | static enum neon_type_mask | |
12285 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
12286 | { | |
12287 | switch (type) | |
12288 | { | |
12289 | case NT_untyped: | |
12290 | switch (size) | |
12291 | { | |
12292 | case 8: return N_8; | |
12293 | case 16: return N_16; | |
12294 | case 32: return N_32; | |
12295 | case 64: return N_64; | |
12296 | default: ; | |
12297 | } | |
12298 | break; | |
12299 | ||
12300 | case NT_integer: | |
12301 | switch (size) | |
12302 | { | |
12303 | case 8: return N_I8; | |
12304 | case 16: return N_I16; | |
12305 | case 32: return N_I32; | |
12306 | case 64: return N_I64; | |
12307 | default: ; | |
12308 | } | |
12309 | break; | |
12310 | ||
12311 | case NT_float: | |
037e8744 JB |
12312 | switch (size) |
12313 | { | |
8e79c3df | 12314 | case 16: return N_F16; |
037e8744 JB |
12315 | case 32: return N_F32; |
12316 | case 64: return N_F64; | |
12317 | default: ; | |
12318 | } | |
5287ad62 JB |
12319 | break; |
12320 | ||
12321 | case NT_poly: | |
12322 | switch (size) | |
12323 | { | |
12324 | case 8: return N_P8; | |
12325 | case 16: return N_P16; | |
12326 | default: ; | |
12327 | } | |
12328 | break; | |
12329 | ||
12330 | case NT_signed: | |
12331 | switch (size) | |
12332 | { | |
12333 | case 8: return N_S8; | |
12334 | case 16: return N_S16; | |
12335 | case 32: return N_S32; | |
12336 | case 64: return N_S64; | |
12337 | default: ; | |
12338 | } | |
12339 | break; | |
12340 | ||
12341 | case NT_unsigned: | |
12342 | switch (size) | |
12343 | { | |
12344 | case 8: return N_U8; | |
12345 | case 16: return N_U16; | |
12346 | case 32: return N_U32; | |
12347 | case 64: return N_U64; | |
12348 | default: ; | |
12349 | } | |
12350 | break; | |
12351 | ||
12352 | default: ; | |
12353 | } | |
5f4273c7 | 12354 | |
5287ad62 JB |
12355 | return N_UTYP; |
12356 | } | |
12357 | ||
12358 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
12359 | handles the case where a single bit is set in the mask. */ | |
12360 | ||
dcbf9037 | 12361 | static int |
5287ad62 JB |
12362 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12363 | enum neon_type_mask mask) | |
12364 | { | |
dcbf9037 JB |
12365 | if ((mask & N_EQK) != 0) |
12366 | return FAIL; | |
12367 | ||
5287ad62 JB |
12368 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12369 | *size = 8; | |
dcbf9037 | 12370 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12371 | *size = 16; |
dcbf9037 | 12372 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12373 | *size = 32; |
037e8744 | 12374 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12375 | *size = 64; |
dcbf9037 JB |
12376 | else |
12377 | return FAIL; | |
12378 | ||
5287ad62 JB |
12379 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12380 | *type = NT_signed; | |
dcbf9037 | 12381 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12382 | *type = NT_unsigned; |
dcbf9037 | 12383 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12384 | *type = NT_integer; |
dcbf9037 | 12385 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12386 | *type = NT_untyped; |
dcbf9037 | 12387 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12388 | *type = NT_poly; |
037e8744 | 12389 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12390 | *type = NT_float; |
dcbf9037 JB |
12391 | else |
12392 | return FAIL; | |
5f4273c7 | 12393 | |
dcbf9037 | 12394 | return SUCCESS; |
5287ad62 JB |
12395 | } |
12396 | ||
12397 | /* Modify a bitmask of allowed types. This is only needed for type | |
12398 | relaxation. */ | |
12399 | ||
12400 | static unsigned | |
12401 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12402 | { | |
12403 | unsigned size; | |
12404 | enum neon_el_type type; | |
12405 | unsigned destmask; | |
12406 | int i; | |
5f4273c7 | 12407 | |
5287ad62 | 12408 | destmask = 0; |
5f4273c7 | 12409 | |
5287ad62 JB |
12410 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12411 | { | |
21d799b5 NC |
12412 | if (el_type_of_type_chk (&type, &size, |
12413 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12414 | { |
12415 | neon_modify_type_size (mods, &type, &size); | |
12416 | destmask |= type_chk_of_el_type (type, size); | |
12417 | } | |
5287ad62 | 12418 | } |
5f4273c7 | 12419 | |
5287ad62 JB |
12420 | return destmask; |
12421 | } | |
12422 | ||
12423 | /* Check type and return type classification. | |
12424 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12425 | type given in: | |
12426 | - the second operand, if there is one | |
12427 | - the operand, if there is no second operand | |
12428 | - the result, if there are no operands. | |
12429 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12430 | which is set on a per-instruction basis, which is the one which matters when | |
12431 | only one data type is written. | |
12432 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12433 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12434 | |
12435 | static struct neon_type_el | |
12436 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12437 | { | |
12438 | va_list ap; | |
12439 | unsigned i, pass, key_el = 0; | |
12440 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12441 | enum neon_el_type k_type = NT_invtype; | |
12442 | unsigned k_size = -1u; | |
12443 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12444 | unsigned key_allowed = 0; | |
12445 | ||
12446 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12447 | Fill in the missing operand here, if it was omitted. */ | |
12448 | if (els > 1 && !inst.operands[1].present) | |
12449 | inst.operands[1] = inst.operands[0]; | |
12450 | ||
12451 | /* Suck up all the varargs. */ | |
12452 | va_start (ap, ns); | |
12453 | for (i = 0; i < els; i++) | |
12454 | { | |
12455 | unsigned thisarg = va_arg (ap, unsigned); | |
12456 | if (thisarg == N_IGNORE_TYPE) | |
12457 | { | |
12458 | va_end (ap); | |
12459 | return badtype; | |
12460 | } | |
12461 | types[i] = thisarg; | |
12462 | if ((thisarg & N_KEY) != 0) | |
12463 | key_el = i; | |
12464 | } | |
12465 | va_end (ap); | |
12466 | ||
dcbf9037 JB |
12467 | if (inst.vectype.elems > 0) |
12468 | for (i = 0; i < els; i++) | |
12469 | if (inst.operands[i].vectype.type != NT_invtype) | |
12470 | { | |
12471 | first_error (_("types specified in both the mnemonic and operands")); | |
12472 | return badtype; | |
12473 | } | |
12474 | ||
5287ad62 JB |
12475 | /* Duplicate inst.vectype elements here as necessary. |
12476 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12477 | particularly when an insn takes one register and one non-register | |
12478 | operand. */ | |
12479 | if (inst.vectype.elems == 1 && els > 1) | |
12480 | { | |
12481 | unsigned j; | |
12482 | inst.vectype.elems = els; | |
12483 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12484 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12485 | if (j != key_el) |
12486 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12487 | types[j]); | |
12488 | } | |
12489 | else if (inst.vectype.elems == 0 && els > 0) | |
12490 | { | |
12491 | unsigned j; | |
12492 | /* No types were given after the mnemonic, so look for types specified | |
12493 | after each operand. We allow some flexibility here; as long as the | |
12494 | "key" operand has a type, we can infer the others. */ | |
12495 | for (j = 0; j < els; j++) | |
12496 | if (inst.operands[j].vectype.type != NT_invtype) | |
12497 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12498 | ||
12499 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12500 | { |
dcbf9037 JB |
12501 | for (j = 0; j < els; j++) |
12502 | if (inst.operands[j].vectype.type == NT_invtype) | |
12503 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12504 | types[j]); | |
12505 | } | |
12506 | else | |
12507 | { | |
12508 | first_error (_("operand types can't be inferred")); | |
12509 | return badtype; | |
5287ad62 JB |
12510 | } |
12511 | } | |
12512 | else if (inst.vectype.elems != els) | |
12513 | { | |
dcbf9037 | 12514 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12515 | return badtype; |
12516 | } | |
12517 | ||
12518 | for (pass = 0; pass < 2; pass++) | |
12519 | { | |
12520 | for (i = 0; i < els; i++) | |
12521 | { | |
12522 | unsigned thisarg = types[i]; | |
12523 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12524 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12525 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12526 | unsigned g_size = inst.vectype.el[i].size; | |
12527 | ||
12528 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12529 | integer types if sign-specific variants are unavailable. */ | |
12530 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12531 | && (types_allowed & N_SU_ALL) == 0) | |
12532 | g_type = NT_integer; | |
12533 | ||
12534 | /* If only untyped args are allowed, decay any more specific types to | |
12535 | them. Some instructions only care about signs for some element | |
12536 | sizes, so handle that properly. */ | |
12537 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12538 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12539 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12540 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12541 | g_type = NT_untyped; | |
12542 | ||
12543 | if (pass == 0) | |
12544 | { | |
12545 | if ((thisarg & N_KEY) != 0) | |
12546 | { | |
12547 | k_type = g_type; | |
12548 | k_size = g_size; | |
12549 | key_allowed = thisarg & ~N_KEY; | |
12550 | } | |
12551 | } | |
12552 | else | |
12553 | { | |
037e8744 JB |
12554 | if ((thisarg & N_VFP) != 0) |
12555 | { | |
99b253c5 NC |
12556 | enum neon_shape_el regshape; |
12557 | unsigned regwidth, match; | |
12558 | ||
12559 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12560 | if (ns == NS_NULL) | |
12561 | { | |
12562 | first_error (_("invalid instruction shape")); | |
12563 | return badtype; | |
12564 | } | |
12565 | regshape = neon_shape_tab[ns].el[i]; | |
12566 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12567 | |
12568 | /* In VFP mode, operands must match register widths. If we | |
12569 | have a key operand, use its width, else use the width of | |
12570 | the current operand. */ | |
12571 | if (k_size != -1u) | |
12572 | match = k_size; | |
12573 | else | |
12574 | match = g_size; | |
12575 | ||
12576 | if (regwidth != match) | |
12577 | { | |
12578 | first_error (_("operand size must match register width")); | |
12579 | return badtype; | |
12580 | } | |
12581 | } | |
5f4273c7 | 12582 | |
5287ad62 JB |
12583 | if ((thisarg & N_EQK) == 0) |
12584 | { | |
12585 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12586 | ||
12587 | if ((given_type & types_allowed) == 0) | |
12588 | { | |
dcbf9037 | 12589 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12590 | return badtype; |
12591 | } | |
12592 | } | |
12593 | else | |
12594 | { | |
12595 | enum neon_el_type mod_k_type = k_type; | |
12596 | unsigned mod_k_size = k_size; | |
12597 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12598 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12599 | { | |
dcbf9037 | 12600 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12601 | return badtype; |
12602 | } | |
12603 | } | |
12604 | } | |
12605 | } | |
12606 | } | |
12607 | ||
12608 | return inst.vectype.el[key_el]; | |
12609 | } | |
12610 | ||
037e8744 | 12611 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12612 | |
037e8744 JB |
12613 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12614 | ||
12615 | static void | |
12616 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12617 | { |
88714cb8 DG |
12618 | inst.is_neon = 1; |
12619 | ||
5287ad62 | 12620 | if (thumb_mode) |
037e8744 | 12621 | inst.instruction |= 0xe0000000; |
5287ad62 | 12622 | else |
037e8744 | 12623 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
12624 | } |
12625 | ||
037e8744 JB |
12626 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
12627 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
12628 | etc. It is assumed that operand parsing has already been done, and that the | |
12629 | operands are in the form expected by the given opcode (this isn't necessarily | |
12630 | the same as the form in which they were parsed, hence some massaging must | |
12631 | take place before this function is called). | |
12632 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 12633 | |
037e8744 JB |
12634 | static void |
12635 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 12636 | { |
037e8744 | 12637 | const struct asm_opcode *opcode; |
5f4273c7 | 12638 | |
21d799b5 | 12639 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 12640 | |
037e8744 JB |
12641 | if (!opcode) |
12642 | abort (); | |
5287ad62 | 12643 | |
037e8744 JB |
12644 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
12645 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
12646 | _(BAD_FPU)); | |
5287ad62 | 12647 | |
88714cb8 DG |
12648 | inst.is_neon = 1; |
12649 | ||
037e8744 JB |
12650 | if (thumb_mode) |
12651 | { | |
12652 | inst.instruction = opcode->tvalue; | |
12653 | opcode->tencode (); | |
12654 | } | |
12655 | else | |
12656 | { | |
12657 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
12658 | opcode->aencode (); | |
12659 | } | |
12660 | } | |
5287ad62 JB |
12661 | |
12662 | static void | |
037e8744 | 12663 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 12664 | { |
037e8744 JB |
12665 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
12666 | ||
12667 | if (rs == NS_FFF) | |
12668 | { | |
12669 | if (is_add) | |
12670 | do_vfp_nsyn_opcode ("fadds"); | |
12671 | else | |
12672 | do_vfp_nsyn_opcode ("fsubs"); | |
12673 | } | |
12674 | else | |
12675 | { | |
12676 | if (is_add) | |
12677 | do_vfp_nsyn_opcode ("faddd"); | |
12678 | else | |
12679 | do_vfp_nsyn_opcode ("fsubd"); | |
12680 | } | |
12681 | } | |
12682 | ||
12683 | /* Check operand types to see if this is a VFP instruction, and if so call | |
12684 | PFN (). */ | |
12685 | ||
12686 | static int | |
12687 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
12688 | { | |
12689 | enum neon_shape rs; | |
12690 | struct neon_type_el et; | |
12691 | ||
12692 | switch (args) | |
12693 | { | |
12694 | case 2: | |
12695 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12696 | et = neon_check_type (2, rs, | |
12697 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12698 | break; | |
5f4273c7 | 12699 | |
037e8744 JB |
12700 | case 3: |
12701 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12702 | et = neon_check_type (3, rs, | |
12703 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12704 | break; | |
12705 | ||
12706 | default: | |
12707 | abort (); | |
12708 | } | |
12709 | ||
12710 | if (et.type != NT_invtype) | |
12711 | { | |
12712 | pfn (rs); | |
12713 | return SUCCESS; | |
12714 | } | |
037e8744 | 12715 | |
99b253c5 | 12716 | inst.error = NULL; |
037e8744 JB |
12717 | return FAIL; |
12718 | } | |
12719 | ||
12720 | static void | |
12721 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
12722 | { | |
12723 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 12724 | |
037e8744 JB |
12725 | if (rs == NS_FFF) |
12726 | { | |
12727 | if (is_mla) | |
12728 | do_vfp_nsyn_opcode ("fmacs"); | |
12729 | else | |
1ee69515 | 12730 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
12731 | } |
12732 | else | |
12733 | { | |
12734 | if (is_mla) | |
12735 | do_vfp_nsyn_opcode ("fmacd"); | |
12736 | else | |
1ee69515 | 12737 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
12738 | } |
12739 | } | |
12740 | ||
62f3b8c8 PB |
12741 | static void |
12742 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
12743 | { | |
12744 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
12745 | ||
12746 | if (rs == NS_FFF) | |
12747 | { | |
12748 | if (is_fma) | |
12749 | do_vfp_nsyn_opcode ("ffmas"); | |
12750 | else | |
12751 | do_vfp_nsyn_opcode ("ffnmas"); | |
12752 | } | |
12753 | else | |
12754 | { | |
12755 | if (is_fma) | |
12756 | do_vfp_nsyn_opcode ("ffmad"); | |
12757 | else | |
12758 | do_vfp_nsyn_opcode ("ffnmad"); | |
12759 | } | |
12760 | } | |
12761 | ||
037e8744 JB |
12762 | static void |
12763 | do_vfp_nsyn_mul (enum neon_shape rs) | |
12764 | { | |
12765 | if (rs == NS_FFF) | |
12766 | do_vfp_nsyn_opcode ("fmuls"); | |
12767 | else | |
12768 | do_vfp_nsyn_opcode ("fmuld"); | |
12769 | } | |
12770 | ||
12771 | static void | |
12772 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
12773 | { | |
12774 | int is_neg = (inst.instruction & 0x80) != 0; | |
12775 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
12776 | ||
12777 | if (rs == NS_FF) | |
12778 | { | |
12779 | if (is_neg) | |
12780 | do_vfp_nsyn_opcode ("fnegs"); | |
12781 | else | |
12782 | do_vfp_nsyn_opcode ("fabss"); | |
12783 | } | |
12784 | else | |
12785 | { | |
12786 | if (is_neg) | |
12787 | do_vfp_nsyn_opcode ("fnegd"); | |
12788 | else | |
12789 | do_vfp_nsyn_opcode ("fabsd"); | |
12790 | } | |
12791 | } | |
12792 | ||
12793 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
12794 | insns belong to Neon, and are handled elsewhere. */ | |
12795 | ||
12796 | static void | |
12797 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
12798 | { | |
12799 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
12800 | if (is_ldm) | |
12801 | { | |
12802 | if (is_dbmode) | |
12803 | do_vfp_nsyn_opcode ("fldmdbs"); | |
12804 | else | |
12805 | do_vfp_nsyn_opcode ("fldmias"); | |
12806 | } | |
12807 | else | |
12808 | { | |
12809 | if (is_dbmode) | |
12810 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12811 | else | |
12812 | do_vfp_nsyn_opcode ("fstmias"); | |
12813 | } | |
12814 | } | |
12815 | ||
037e8744 JB |
12816 | static void |
12817 | do_vfp_nsyn_sqrt (void) | |
12818 | { | |
12819 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12820 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12821 | |
037e8744 JB |
12822 | if (rs == NS_FF) |
12823 | do_vfp_nsyn_opcode ("fsqrts"); | |
12824 | else | |
12825 | do_vfp_nsyn_opcode ("fsqrtd"); | |
12826 | } | |
12827 | ||
12828 | static void | |
12829 | do_vfp_nsyn_div (void) | |
12830 | { | |
12831 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12832 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12833 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12834 | |
037e8744 JB |
12835 | if (rs == NS_FFF) |
12836 | do_vfp_nsyn_opcode ("fdivs"); | |
12837 | else | |
12838 | do_vfp_nsyn_opcode ("fdivd"); | |
12839 | } | |
12840 | ||
12841 | static void | |
12842 | do_vfp_nsyn_nmul (void) | |
12843 | { | |
12844 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12845 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12846 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12847 | |
037e8744 JB |
12848 | if (rs == NS_FFF) |
12849 | { | |
88714cb8 | 12850 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12851 | do_vfp_sp_dyadic (); |
12852 | } | |
12853 | else | |
12854 | { | |
88714cb8 | 12855 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12856 | do_vfp_dp_rd_rn_rm (); |
12857 | } | |
12858 | do_vfp_cond_or_thumb (); | |
12859 | } | |
12860 | ||
12861 | static void | |
12862 | do_vfp_nsyn_cmp (void) | |
12863 | { | |
12864 | if (inst.operands[1].isreg) | |
12865 | { | |
12866 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12867 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12868 | |
037e8744 JB |
12869 | if (rs == NS_FF) |
12870 | { | |
88714cb8 | 12871 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12872 | do_vfp_sp_monadic (); |
12873 | } | |
12874 | else | |
12875 | { | |
88714cb8 | 12876 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12877 | do_vfp_dp_rd_rm (); |
12878 | } | |
12879 | } | |
12880 | else | |
12881 | { | |
12882 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
12883 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
12884 | ||
12885 | switch (inst.instruction & 0x0fffffff) | |
12886 | { | |
12887 | case N_MNEM_vcmp: | |
12888 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
12889 | break; | |
12890 | case N_MNEM_vcmpe: | |
12891 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
12892 | break; | |
12893 | default: | |
12894 | abort (); | |
12895 | } | |
5f4273c7 | 12896 | |
037e8744 JB |
12897 | if (rs == NS_FI) |
12898 | { | |
88714cb8 | 12899 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12900 | do_vfp_sp_compare_z (); |
12901 | } | |
12902 | else | |
12903 | { | |
88714cb8 | 12904 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12905 | do_vfp_dp_rd (); |
12906 | } | |
12907 | } | |
12908 | do_vfp_cond_or_thumb (); | |
12909 | } | |
12910 | ||
12911 | static void | |
12912 | nsyn_insert_sp (void) | |
12913 | { | |
12914 | inst.operands[1] = inst.operands[0]; | |
12915 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 12916 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
12917 | inst.operands[0].isreg = 1; |
12918 | inst.operands[0].writeback = 1; | |
12919 | inst.operands[0].present = 1; | |
12920 | } | |
12921 | ||
12922 | static void | |
12923 | do_vfp_nsyn_push (void) | |
12924 | { | |
12925 | nsyn_insert_sp (); | |
12926 | if (inst.operands[1].issingle) | |
12927 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12928 | else | |
12929 | do_vfp_nsyn_opcode ("fstmdbd"); | |
12930 | } | |
12931 | ||
12932 | static void | |
12933 | do_vfp_nsyn_pop (void) | |
12934 | { | |
12935 | nsyn_insert_sp (); | |
12936 | if (inst.operands[1].issingle) | |
22b5b651 | 12937 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 12938 | else |
22b5b651 | 12939 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
12940 | } |
12941 | ||
12942 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
12943 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
12944 | ||
88714cb8 DG |
12945 | static void |
12946 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 12947 | { |
88714cb8 DG |
12948 | unsigned int i = insn->instruction; |
12949 | insn->is_neon = 1; | |
12950 | ||
037e8744 JB |
12951 | if (thumb_mode) |
12952 | { | |
12953 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
12954 | if (i & (1 << 24)) | |
12955 | i |= 1 << 28; | |
5f4273c7 | 12956 | |
037e8744 | 12957 | i &= ~(1 << 24); |
5f4273c7 | 12958 | |
037e8744 JB |
12959 | i |= 0xef000000; |
12960 | } | |
12961 | else | |
12962 | i |= 0xf2000000; | |
5f4273c7 | 12963 | |
88714cb8 | 12964 | insn->instruction = i; |
037e8744 JB |
12965 | } |
12966 | ||
12967 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
12968 | (0, 1, 2, 3). */ | |
12969 | ||
12970 | static unsigned | |
12971 | neon_logbits (unsigned x) | |
12972 | { | |
12973 | return ffs (x) - 4; | |
12974 | } | |
12975 | ||
12976 | #define LOW4(R) ((R) & 0xf) | |
12977 | #define HI1(R) (((R) >> 4) & 1) | |
12978 | ||
12979 | /* Encode insns with bit pattern: | |
12980 | ||
12981 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
12982 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 12983 | |
037e8744 JB |
12984 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
12985 | different meaning for some instruction. */ | |
12986 | ||
12987 | static void | |
12988 | neon_three_same (int isquad, int ubit, int size) | |
12989 | { | |
12990 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
12991 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
12992 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
12993 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
12994 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
12995 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
12996 | inst.instruction |= (isquad != 0) << 6; | |
12997 | inst.instruction |= (ubit != 0) << 24; | |
12998 | if (size != -1) | |
12999 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 13000 | |
88714cb8 | 13001 | neon_dp_fixup (&inst); |
037e8744 JB |
13002 | } |
13003 | ||
13004 | /* Encode instructions of the form: | |
13005 | ||
13006 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
13007 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
13008 | |
13009 | Don't write size if SIZE == -1. */ | |
13010 | ||
13011 | static void | |
13012 | neon_two_same (int qbit, int ubit, int size) | |
13013 | { | |
13014 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13015 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13016 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13017 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13018 | inst.instruction |= (qbit != 0) << 6; | |
13019 | inst.instruction |= (ubit != 0) << 24; | |
13020 | ||
13021 | if (size != -1) | |
13022 | inst.instruction |= neon_logbits (size) << 18; | |
13023 | ||
88714cb8 | 13024 | neon_dp_fixup (&inst); |
5287ad62 JB |
13025 | } |
13026 | ||
13027 | /* Neon instruction encoders, in approximate order of appearance. */ | |
13028 | ||
13029 | static void | |
13030 | do_neon_dyadic_i_su (void) | |
13031 | { | |
037e8744 | 13032 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13033 | struct neon_type_el et = neon_check_type (3, rs, |
13034 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 13035 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13036 | } |
13037 | ||
13038 | static void | |
13039 | do_neon_dyadic_i64_su (void) | |
13040 | { | |
037e8744 | 13041 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13042 | struct neon_type_el et = neon_check_type (3, rs, |
13043 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 13044 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13045 | } |
13046 | ||
13047 | static void | |
13048 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
13049 | unsigned immbits) | |
13050 | { | |
13051 | unsigned size = et.size >> 3; | |
13052 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13053 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13054 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13055 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13056 | inst.instruction |= (isquad != 0) << 6; | |
13057 | inst.instruction |= immbits << 16; | |
13058 | inst.instruction |= (size >> 3) << 7; | |
13059 | inst.instruction |= (size & 0x7) << 19; | |
13060 | if (write_ubit) | |
13061 | inst.instruction |= (uval != 0) << 24; | |
13062 | ||
88714cb8 | 13063 | neon_dp_fixup (&inst); |
5287ad62 JB |
13064 | } |
13065 | ||
13066 | static void | |
13067 | do_neon_shl_imm (void) | |
13068 | { | |
13069 | if (!inst.operands[2].isreg) | |
13070 | { | |
037e8744 | 13071 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13072 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 13073 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13074 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
13075 | } |
13076 | else | |
13077 | { | |
037e8744 | 13078 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13079 | struct neon_type_el et = neon_check_type (3, rs, |
13080 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13081 | unsigned int tmp; |
13082 | ||
13083 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
13084 | vshl.xx Dd, Dm, Dn | |
13085 | whereas other 3-register operations encoded by neon_three_same have | |
13086 | syntax like: | |
13087 | vadd.xx Dd, Dn, Dm | |
13088 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
13089 | here. */ | |
13090 | tmp = inst.operands[2].reg; | |
13091 | inst.operands[2].reg = inst.operands[1].reg; | |
13092 | inst.operands[1].reg = tmp; | |
88714cb8 | 13093 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13094 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13095 | } |
13096 | } | |
13097 | ||
13098 | static void | |
13099 | do_neon_qshl_imm (void) | |
13100 | { | |
13101 | if (!inst.operands[2].isreg) | |
13102 | { | |
037e8744 | 13103 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13104 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 13105 | |
88714cb8 | 13106 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13107 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
13108 | inst.operands[2].imm); |
13109 | } | |
13110 | else | |
13111 | { | |
037e8744 | 13112 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13113 | struct neon_type_el et = neon_check_type (3, rs, |
13114 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13115 | unsigned int tmp; |
13116 | ||
13117 | /* See note in do_neon_shl_imm. */ | |
13118 | tmp = inst.operands[2].reg; | |
13119 | inst.operands[2].reg = inst.operands[1].reg; | |
13120 | inst.operands[1].reg = tmp; | |
88714cb8 | 13121 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13122 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13123 | } |
13124 | } | |
13125 | ||
627907b7 JB |
13126 | static void |
13127 | do_neon_rshl (void) | |
13128 | { | |
13129 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
13130 | struct neon_type_el et = neon_check_type (3, rs, | |
13131 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
13132 | unsigned int tmp; | |
13133 | ||
13134 | tmp = inst.operands[2].reg; | |
13135 | inst.operands[2].reg = inst.operands[1].reg; | |
13136 | inst.operands[1].reg = tmp; | |
13137 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
13138 | } | |
13139 | ||
5287ad62 JB |
13140 | static int |
13141 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
13142 | { | |
036dc3f7 PB |
13143 | /* Handle .I8 pseudo-instructions. */ |
13144 | if (size == 8) | |
5287ad62 | 13145 | { |
5287ad62 JB |
13146 | /* Unfortunately, this will make everything apart from zero out-of-range. |
13147 | FIXME is this the intended semantics? There doesn't seem much point in | |
13148 | accepting .I8 if so. */ | |
13149 | immediate |= immediate << 8; | |
13150 | size = 16; | |
036dc3f7 PB |
13151 | } |
13152 | ||
13153 | if (size >= 32) | |
13154 | { | |
13155 | if (immediate == (immediate & 0x000000ff)) | |
13156 | { | |
13157 | *immbits = immediate; | |
13158 | return 0x1; | |
13159 | } | |
13160 | else if (immediate == (immediate & 0x0000ff00)) | |
13161 | { | |
13162 | *immbits = immediate >> 8; | |
13163 | return 0x3; | |
13164 | } | |
13165 | else if (immediate == (immediate & 0x00ff0000)) | |
13166 | { | |
13167 | *immbits = immediate >> 16; | |
13168 | return 0x5; | |
13169 | } | |
13170 | else if (immediate == (immediate & 0xff000000)) | |
13171 | { | |
13172 | *immbits = immediate >> 24; | |
13173 | return 0x7; | |
13174 | } | |
13175 | if ((immediate & 0xffff) != (immediate >> 16)) | |
13176 | goto bad_immediate; | |
13177 | immediate &= 0xffff; | |
5287ad62 JB |
13178 | } |
13179 | ||
13180 | if (immediate == (immediate & 0x000000ff)) | |
13181 | { | |
13182 | *immbits = immediate; | |
036dc3f7 | 13183 | return 0x9; |
5287ad62 JB |
13184 | } |
13185 | else if (immediate == (immediate & 0x0000ff00)) | |
13186 | { | |
13187 | *immbits = immediate >> 8; | |
036dc3f7 | 13188 | return 0xb; |
5287ad62 JB |
13189 | } |
13190 | ||
13191 | bad_immediate: | |
dcbf9037 | 13192 | first_error (_("immediate value out of range")); |
5287ad62 JB |
13193 | return FAIL; |
13194 | } | |
13195 | ||
13196 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
13197 | A, B, C, D. */ | |
13198 | ||
13199 | static int | |
13200 | neon_bits_same_in_bytes (unsigned imm) | |
13201 | { | |
13202 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
13203 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
13204 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
13205 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
13206 | } | |
13207 | ||
13208 | /* For immediate of above form, return 0bABCD. */ | |
13209 | ||
13210 | static unsigned | |
13211 | neon_squash_bits (unsigned imm) | |
13212 | { | |
13213 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
13214 | | ((imm & 0x01000000) >> 21); | |
13215 | } | |
13216 | ||
136da414 | 13217 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
13218 | |
13219 | static unsigned | |
13220 | neon_qfloat_bits (unsigned imm) | |
13221 | { | |
136da414 | 13222 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
13223 | } |
13224 | ||
13225 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
13226 | the instruction. *OP is passed as the initial value of the op field, and | |
13227 | may be set to a different value depending on the constant (i.e. | |
13228 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 13229 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 13230 | try smaller element sizes. */ |
5287ad62 JB |
13231 | |
13232 | static int | |
c96612cc JB |
13233 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
13234 | unsigned *immbits, int *op, int size, | |
13235 | enum neon_el_type type) | |
5287ad62 | 13236 | { |
c96612cc JB |
13237 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
13238 | float. */ | |
13239 | if (type == NT_float && !float_p) | |
13240 | return FAIL; | |
13241 | ||
136da414 JB |
13242 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
13243 | { | |
13244 | if (size != 32 || *op == 1) | |
13245 | return FAIL; | |
13246 | *immbits = neon_qfloat_bits (immlo); | |
13247 | return 0xf; | |
13248 | } | |
036dc3f7 PB |
13249 | |
13250 | if (size == 64) | |
5287ad62 | 13251 | { |
036dc3f7 PB |
13252 | if (neon_bits_same_in_bytes (immhi) |
13253 | && neon_bits_same_in_bytes (immlo)) | |
13254 | { | |
13255 | if (*op == 1) | |
13256 | return FAIL; | |
13257 | *immbits = (neon_squash_bits (immhi) << 4) | |
13258 | | neon_squash_bits (immlo); | |
13259 | *op = 1; | |
13260 | return 0xe; | |
13261 | } | |
13262 | ||
13263 | if (immhi != immlo) | |
13264 | return FAIL; | |
5287ad62 | 13265 | } |
036dc3f7 PB |
13266 | |
13267 | if (size >= 32) | |
5287ad62 | 13268 | { |
036dc3f7 PB |
13269 | if (immlo == (immlo & 0x000000ff)) |
13270 | { | |
13271 | *immbits = immlo; | |
13272 | return 0x0; | |
13273 | } | |
13274 | else if (immlo == (immlo & 0x0000ff00)) | |
13275 | { | |
13276 | *immbits = immlo >> 8; | |
13277 | return 0x2; | |
13278 | } | |
13279 | else if (immlo == (immlo & 0x00ff0000)) | |
13280 | { | |
13281 | *immbits = immlo >> 16; | |
13282 | return 0x4; | |
13283 | } | |
13284 | else if (immlo == (immlo & 0xff000000)) | |
13285 | { | |
13286 | *immbits = immlo >> 24; | |
13287 | return 0x6; | |
13288 | } | |
13289 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
13290 | { | |
13291 | *immbits = (immlo >> 8) & 0xff; | |
13292 | return 0xc; | |
13293 | } | |
13294 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
13295 | { | |
13296 | *immbits = (immlo >> 16) & 0xff; | |
13297 | return 0xd; | |
13298 | } | |
13299 | ||
13300 | if ((immlo & 0xffff) != (immlo >> 16)) | |
13301 | return FAIL; | |
13302 | immlo &= 0xffff; | |
5287ad62 | 13303 | } |
036dc3f7 PB |
13304 | |
13305 | if (size >= 16) | |
5287ad62 | 13306 | { |
036dc3f7 PB |
13307 | if (immlo == (immlo & 0x000000ff)) |
13308 | { | |
13309 | *immbits = immlo; | |
13310 | return 0x8; | |
13311 | } | |
13312 | else if (immlo == (immlo & 0x0000ff00)) | |
13313 | { | |
13314 | *immbits = immlo >> 8; | |
13315 | return 0xa; | |
13316 | } | |
13317 | ||
13318 | if ((immlo & 0xff) != (immlo >> 8)) | |
13319 | return FAIL; | |
13320 | immlo &= 0xff; | |
5287ad62 | 13321 | } |
036dc3f7 PB |
13322 | |
13323 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 13324 | { |
036dc3f7 PB |
13325 | /* Don't allow MVN with 8-bit immediate. */ |
13326 | if (*op == 1) | |
13327 | return FAIL; | |
13328 | *immbits = immlo; | |
13329 | return 0xe; | |
5287ad62 | 13330 | } |
5287ad62 JB |
13331 | |
13332 | return FAIL; | |
13333 | } | |
13334 | ||
13335 | /* Write immediate bits [7:0] to the following locations: | |
13336 | ||
13337 | |28/24|23 19|18 16|15 4|3 0| | |
13338 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
13339 | ||
13340 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
13341 | ||
13342 | static void | |
13343 | neon_write_immbits (unsigned immbits) | |
13344 | { | |
13345 | inst.instruction |= immbits & 0xf; | |
13346 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
13347 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
13348 | } | |
13349 | ||
13350 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
13351 | ||
13352 | static void | |
13353 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
13354 | { | |
13355 | unsigned immlo = xlo ? *xlo : 0; | |
13356 | unsigned immhi = xhi ? *xhi : 0; | |
13357 | ||
13358 | switch (size) | |
13359 | { | |
13360 | case 8: | |
13361 | immlo = (~immlo) & 0xff; | |
13362 | break; | |
13363 | ||
13364 | case 16: | |
13365 | immlo = (~immlo) & 0xffff; | |
13366 | break; | |
13367 | ||
13368 | case 64: | |
13369 | immhi = (~immhi) & 0xffffffff; | |
13370 | /* fall through. */ | |
13371 | ||
13372 | case 32: | |
13373 | immlo = (~immlo) & 0xffffffff; | |
13374 | break; | |
13375 | ||
13376 | default: | |
13377 | abort (); | |
13378 | } | |
13379 | ||
13380 | if (xlo) | |
13381 | *xlo = immlo; | |
13382 | ||
13383 | if (xhi) | |
13384 | *xhi = immhi; | |
13385 | } | |
13386 | ||
13387 | static void | |
13388 | do_neon_logic (void) | |
13389 | { | |
13390 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13391 | { | |
037e8744 | 13392 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13393 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13394 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13395 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13396 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13397 | } |
13398 | else | |
13399 | { | |
4316f0d2 DG |
13400 | const int three_ops_form = (inst.operands[2].present |
13401 | && !inst.operands[2].isreg); | |
13402 | const int immoperand = (three_ops_form ? 2 : 1); | |
13403 | enum neon_shape rs = (three_ops_form | |
13404 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13405 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13406 | struct neon_type_el et = neon_check_type (2, rs, |
13407 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13408 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13409 | unsigned immbits; |
13410 | int cmode; | |
5f4273c7 | 13411 | |
5287ad62 JB |
13412 | if (et.type == NT_invtype) |
13413 | return; | |
5f4273c7 | 13414 | |
4316f0d2 DG |
13415 | if (three_ops_form) |
13416 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13417 | _("first and second operands shall be the same register")); | |
13418 | ||
88714cb8 | 13419 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13420 | |
4316f0d2 | 13421 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13422 | if (et.size == 64) |
13423 | { | |
13424 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13425 | pattern. */ | |
4316f0d2 DG |
13426 | if (immbits != (inst.operands[immoperand].regisimm ? |
13427 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13428 | { |
13429 | /* Set immbits to an invalid constant. */ | |
13430 | immbits = 0xdeadbeef; | |
13431 | } | |
13432 | } | |
13433 | ||
5287ad62 JB |
13434 | switch (opcode) |
13435 | { | |
13436 | case N_MNEM_vbic: | |
036dc3f7 | 13437 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13438 | break; |
5f4273c7 | 13439 | |
5287ad62 | 13440 | case N_MNEM_vorr: |
036dc3f7 | 13441 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13442 | break; |
5f4273c7 | 13443 | |
5287ad62 JB |
13444 | case N_MNEM_vand: |
13445 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13446 | neon_invert_size (&immbits, 0, et.size); |
13447 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13448 | break; | |
5f4273c7 | 13449 | |
5287ad62 JB |
13450 | case N_MNEM_vorn: |
13451 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13452 | neon_invert_size (&immbits, 0, et.size); |
13453 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13454 | break; | |
5f4273c7 | 13455 | |
5287ad62 JB |
13456 | default: |
13457 | abort (); | |
13458 | } | |
13459 | ||
13460 | if (cmode == FAIL) | |
13461 | return; | |
13462 | ||
037e8744 | 13463 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13464 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13465 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13466 | inst.instruction |= cmode << 8; | |
13467 | neon_write_immbits (immbits); | |
5f4273c7 | 13468 | |
88714cb8 | 13469 | neon_dp_fixup (&inst); |
5287ad62 JB |
13470 | } |
13471 | } | |
13472 | ||
13473 | static void | |
13474 | do_neon_bitfield (void) | |
13475 | { | |
037e8744 | 13476 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13477 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13478 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13479 | } |
13480 | ||
13481 | static void | |
dcbf9037 JB |
13482 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13483 | unsigned destbits) | |
5287ad62 | 13484 | { |
037e8744 | 13485 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13486 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13487 | types | N_KEY); | |
5287ad62 JB |
13488 | if (et.type == NT_float) |
13489 | { | |
88714cb8 | 13490 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13491 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13492 | } |
13493 | else | |
13494 | { | |
88714cb8 | 13495 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13496 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13497 | } |
13498 | } | |
13499 | ||
13500 | static void | |
13501 | do_neon_dyadic_if_su (void) | |
13502 | { | |
dcbf9037 | 13503 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13504 | } |
13505 | ||
13506 | static void | |
13507 | do_neon_dyadic_if_su_d (void) | |
13508 | { | |
13509 | /* This version only allow D registers, but that constraint is enforced during | |
13510 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13511 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13512 | } |
13513 | ||
5287ad62 JB |
13514 | static void |
13515 | do_neon_dyadic_if_i_d (void) | |
13516 | { | |
428e3f1f PB |
13517 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13518 | affected if we specify unsigned args. */ | |
13519 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13520 | } |
13521 | ||
037e8744 JB |
13522 | enum vfp_or_neon_is_neon_bits |
13523 | { | |
13524 | NEON_CHECK_CC = 1, | |
13525 | NEON_CHECK_ARCH = 2 | |
13526 | }; | |
13527 | ||
13528 | /* Call this function if an instruction which may have belonged to the VFP or | |
13529 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13530 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13531 | things: | |
13532 | ||
13533 | - Make sure the user hasn't attempted to make a Neon instruction | |
13534 | conditional. | |
13535 | - Alter the value in the condition code field if necessary. | |
13536 | - Make sure that the arch supports Neon instructions. | |
13537 | ||
13538 | Which of these operations take place depends on bits from enum | |
13539 | vfp_or_neon_is_neon_bits. | |
13540 | ||
13541 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13542 | current instruction's condition is COND_ALWAYS, the condition field is | |
13543 | changed to inst.uncond_value. This is necessary because instructions shared | |
13544 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13545 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13546 | ||
13547 | static int | |
13548 | vfp_or_neon_is_neon (unsigned check) | |
13549 | { | |
13550 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13551 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13552 | { | |
13553 | if (inst.cond != COND_ALWAYS) | |
13554 | { | |
13555 | first_error (_(BAD_COND)); | |
13556 | return FAIL; | |
13557 | } | |
13558 | if (inst.uncond_value != -1) | |
13559 | inst.instruction |= inst.uncond_value << 28; | |
13560 | } | |
5f4273c7 | 13561 | |
037e8744 JB |
13562 | if ((check & NEON_CHECK_ARCH) |
13563 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13564 | { | |
13565 | first_error (_(BAD_FPU)); | |
13566 | return FAIL; | |
13567 | } | |
5f4273c7 | 13568 | |
037e8744 JB |
13569 | return SUCCESS; |
13570 | } | |
13571 | ||
5287ad62 JB |
13572 | static void |
13573 | do_neon_addsub_if_i (void) | |
13574 | { | |
037e8744 JB |
13575 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13576 | return; | |
13577 | ||
13578 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13579 | return; | |
13580 | ||
5287ad62 JB |
13581 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13582 | affected if we specify unsigned args. */ | |
dcbf9037 | 13583 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13584 | } |
13585 | ||
13586 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13587 | result to be: | |
13588 | V<op> A,B (A is operand 0, B is operand 2) | |
13589 | to mean: | |
13590 | V<op> A,B,A | |
13591 | not: | |
13592 | V<op> A,B,B | |
13593 | so handle that case specially. */ | |
13594 | ||
13595 | static void | |
13596 | neon_exchange_operands (void) | |
13597 | { | |
13598 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13599 | if (inst.operands[1].present) | |
13600 | { | |
13601 | /* Swap operands[1] and operands[2]. */ | |
13602 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13603 | inst.operands[1] = inst.operands[2]; | |
13604 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13605 | } | |
13606 | else | |
13607 | { | |
13608 | inst.operands[1] = inst.operands[2]; | |
13609 | inst.operands[2] = inst.operands[0]; | |
13610 | } | |
13611 | } | |
13612 | ||
13613 | static void | |
13614 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13615 | { | |
13616 | if (inst.operands[2].isreg) | |
13617 | { | |
13618 | if (invert) | |
13619 | neon_exchange_operands (); | |
dcbf9037 | 13620 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
13621 | } |
13622 | else | |
13623 | { | |
037e8744 | 13624 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
13625 | struct neon_type_el et = neon_check_type (2, rs, |
13626 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 13627 | |
88714cb8 | 13628 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13629 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13630 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13631 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13632 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13633 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13634 | inst.instruction |= (et.type == NT_float) << 10; |
13635 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13636 | |
88714cb8 | 13637 | neon_dp_fixup (&inst); |
5287ad62 JB |
13638 | } |
13639 | } | |
13640 | ||
13641 | static void | |
13642 | do_neon_cmp (void) | |
13643 | { | |
13644 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
13645 | } | |
13646 | ||
13647 | static void | |
13648 | do_neon_cmp_inv (void) | |
13649 | { | |
13650 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
13651 | } | |
13652 | ||
13653 | static void | |
13654 | do_neon_ceq (void) | |
13655 | { | |
13656 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
13657 | } | |
13658 | ||
13659 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
13660 | scalars, which are encoded in 5 bits, M : Rm. | |
13661 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
13662 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
13663 | index in M. */ | |
13664 | ||
13665 | static unsigned | |
13666 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
13667 | { | |
dcbf9037 JB |
13668 | unsigned regno = NEON_SCALAR_REG (scalar); |
13669 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
13670 | |
13671 | switch (elsize) | |
13672 | { | |
13673 | case 16: | |
13674 | if (regno > 7 || elno > 3) | |
13675 | goto bad_scalar; | |
13676 | return regno | (elno << 3); | |
5f4273c7 | 13677 | |
5287ad62 JB |
13678 | case 32: |
13679 | if (regno > 15 || elno > 1) | |
13680 | goto bad_scalar; | |
13681 | return regno | (elno << 4); | |
13682 | ||
13683 | default: | |
13684 | bad_scalar: | |
dcbf9037 | 13685 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
13686 | } |
13687 | ||
13688 | return 0; | |
13689 | } | |
13690 | ||
13691 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
13692 | ||
13693 | static void | |
13694 | neon_mul_mac (struct neon_type_el et, int ubit) | |
13695 | { | |
dcbf9037 JB |
13696 | unsigned scalar; |
13697 | ||
13698 | /* Give a more helpful error message if we have an invalid type. */ | |
13699 | if (et.type == NT_invtype) | |
13700 | return; | |
5f4273c7 | 13701 | |
dcbf9037 | 13702 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
13703 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13704 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13705 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13706 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13707 | inst.instruction |= LOW4 (scalar); | |
13708 | inst.instruction |= HI1 (scalar) << 5; | |
13709 | inst.instruction |= (et.type == NT_float) << 8; | |
13710 | inst.instruction |= neon_logbits (et.size) << 20; | |
13711 | inst.instruction |= (ubit != 0) << 24; | |
13712 | ||
88714cb8 | 13713 | neon_dp_fixup (&inst); |
5287ad62 JB |
13714 | } |
13715 | ||
13716 | static void | |
13717 | do_neon_mac_maybe_scalar (void) | |
13718 | { | |
037e8744 JB |
13719 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
13720 | return; | |
13721 | ||
13722 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13723 | return; | |
13724 | ||
5287ad62 JB |
13725 | if (inst.operands[2].isscalar) |
13726 | { | |
037e8744 | 13727 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13728 | struct neon_type_el et = neon_check_type (3, rs, |
13729 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 13730 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13731 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13732 | } |
13733 | else | |
428e3f1f PB |
13734 | { |
13735 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
13736 | affected if we specify unsigned args. */ | |
13737 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13738 | } | |
5287ad62 JB |
13739 | } |
13740 | ||
62f3b8c8 PB |
13741 | static void |
13742 | do_neon_fmac (void) | |
13743 | { | |
13744 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
13745 | return; | |
13746 | ||
13747 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13748 | return; | |
13749 | ||
13750 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13751 | } | |
13752 | ||
5287ad62 JB |
13753 | static void |
13754 | do_neon_tst (void) | |
13755 | { | |
037e8744 | 13756 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13757 | struct neon_type_el et = neon_check_type (3, rs, |
13758 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 13759 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13760 | } |
13761 | ||
13762 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
13763 | same types as the MAC equivalents. The polynomial type for this instruction | |
13764 | is encoded the same as the integer type. */ | |
13765 | ||
13766 | static void | |
13767 | do_neon_mul (void) | |
13768 | { | |
037e8744 JB |
13769 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
13770 | return; | |
13771 | ||
13772 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13773 | return; | |
13774 | ||
5287ad62 JB |
13775 | if (inst.operands[2].isscalar) |
13776 | do_neon_mac_maybe_scalar (); | |
13777 | else | |
dcbf9037 | 13778 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
13779 | } |
13780 | ||
13781 | static void | |
13782 | do_neon_qdmulh (void) | |
13783 | { | |
13784 | if (inst.operands[2].isscalar) | |
13785 | { | |
037e8744 | 13786 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13787 | struct neon_type_el et = neon_check_type (3, rs, |
13788 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13789 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13790 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13791 | } |
13792 | else | |
13793 | { | |
037e8744 | 13794 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13795 | struct neon_type_el et = neon_check_type (3, rs, |
13796 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13797 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 13798 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 13799 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13800 | } |
13801 | } | |
13802 | ||
13803 | static void | |
13804 | do_neon_fcmp_absolute (void) | |
13805 | { | |
037e8744 | 13806 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13807 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
13808 | /* Size field comes from bit mask. */ | |
037e8744 | 13809 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
13810 | } |
13811 | ||
13812 | static void | |
13813 | do_neon_fcmp_absolute_inv (void) | |
13814 | { | |
13815 | neon_exchange_operands (); | |
13816 | do_neon_fcmp_absolute (); | |
13817 | } | |
13818 | ||
13819 | static void | |
13820 | do_neon_step (void) | |
13821 | { | |
037e8744 | 13822 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 13823 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 13824 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13825 | } |
13826 | ||
13827 | static void | |
13828 | do_neon_abs_neg (void) | |
13829 | { | |
037e8744 JB |
13830 | enum neon_shape rs; |
13831 | struct neon_type_el et; | |
5f4273c7 | 13832 | |
037e8744 JB |
13833 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
13834 | return; | |
13835 | ||
13836 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13837 | return; | |
13838 | ||
13839 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
13840 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 13841 | |
5287ad62 JB |
13842 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13843 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13844 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13845 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13846 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13847 | inst.instruction |= (et.type == NT_float) << 10; |
13848 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13849 | |
88714cb8 | 13850 | neon_dp_fixup (&inst); |
5287ad62 JB |
13851 | } |
13852 | ||
13853 | static void | |
13854 | do_neon_sli (void) | |
13855 | { | |
037e8744 | 13856 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13857 | struct neon_type_el et = neon_check_type (2, rs, |
13858 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13859 | int imm = inst.operands[2].imm; | |
13860 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13861 | _("immediate out of range for insert")); | |
037e8744 | 13862 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13863 | } |
13864 | ||
13865 | static void | |
13866 | do_neon_sri (void) | |
13867 | { | |
037e8744 | 13868 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13869 | struct neon_type_el et = neon_check_type (2, rs, |
13870 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13871 | int imm = inst.operands[2].imm; | |
13872 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13873 | _("immediate out of range for insert")); | |
037e8744 | 13874 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
13875 | } |
13876 | ||
13877 | static void | |
13878 | do_neon_qshlu_imm (void) | |
13879 | { | |
037e8744 | 13880 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13881 | struct neon_type_el et = neon_check_type (2, rs, |
13882 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
13883 | int imm = inst.operands[2].imm; | |
13884 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13885 | _("immediate out of range for shift")); | |
13886 | /* Only encodes the 'U present' variant of the instruction. | |
13887 | In this case, signed types have OP (bit 8) set to 0. | |
13888 | Unsigned types have OP set to 1. */ | |
13889 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
13890 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 13891 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13892 | } |
13893 | ||
13894 | static void | |
13895 | do_neon_qmovn (void) | |
13896 | { | |
13897 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13898 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13899 | /* Saturating move where operands can be signed or unsigned, and the | |
13900 | destination has the same signedness. */ | |
88714cb8 | 13901 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13902 | if (et.type == NT_unsigned) |
13903 | inst.instruction |= 0xc0; | |
13904 | else | |
13905 | inst.instruction |= 0x80; | |
13906 | neon_two_same (0, 1, et.size / 2); | |
13907 | } | |
13908 | ||
13909 | static void | |
13910 | do_neon_qmovun (void) | |
13911 | { | |
13912 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13913 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13914 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 13915 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13916 | neon_two_same (0, 1, et.size / 2); |
13917 | } | |
13918 | ||
13919 | static void | |
13920 | do_neon_rshift_sat_narrow (void) | |
13921 | { | |
13922 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13923 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13924 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13925 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13926 | int imm = inst.operands[2].imm; | |
13927 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13928 | right. */ | |
13929 | et.size /= 2; | |
5f4273c7 | 13930 | |
5287ad62 JB |
13931 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
13932 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
13933 | if (imm == 0) | |
13934 | { | |
13935 | inst.operands[2].present = 0; | |
13936 | inst.instruction = N_MNEM_vqmovn; | |
13937 | do_neon_qmovn (); | |
13938 | return; | |
13939 | } | |
5f4273c7 | 13940 | |
5287ad62 JB |
13941 | constraint (imm < 1 || (unsigned)imm > et.size, |
13942 | _("immediate out of range")); | |
13943 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
13944 | } | |
13945 | ||
13946 | static void | |
13947 | do_neon_rshift_sat_narrow_u (void) | |
13948 | { | |
13949 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13950 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
13951 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13952 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13953 | int imm = inst.operands[2].imm; | |
13954 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13955 | right. */ | |
13956 | et.size /= 2; | |
13957 | ||
13958 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
13959 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
13960 | if (imm == 0) | |
13961 | { | |
13962 | inst.operands[2].present = 0; | |
13963 | inst.instruction = N_MNEM_vqmovun; | |
13964 | do_neon_qmovun (); | |
13965 | return; | |
13966 | } | |
13967 | ||
13968 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13969 | _("immediate out of range")); | |
13970 | /* FIXME: The manual is kind of unclear about what value U should have in | |
13971 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
13972 | must be 1. */ | |
13973 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
13974 | } | |
13975 | ||
13976 | static void | |
13977 | do_neon_movn (void) | |
13978 | { | |
13979 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13980 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 13981 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13982 | neon_two_same (0, 1, et.size / 2); |
13983 | } | |
13984 | ||
13985 | static void | |
13986 | do_neon_rshift_narrow (void) | |
13987 | { | |
13988 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
13989 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
13990 | int imm = inst.operands[2].imm; | |
13991 | /* This gets the bounds check, size encoding and immediate bits calculation | |
13992 | right. */ | |
13993 | et.size /= 2; | |
5f4273c7 | 13994 | |
5287ad62 JB |
13995 | /* If immediate is zero then we are a pseudo-instruction for |
13996 | VMOVN.I<size> <Dd>, <Qm> */ | |
13997 | if (imm == 0) | |
13998 | { | |
13999 | inst.operands[2].present = 0; | |
14000 | inst.instruction = N_MNEM_vmovn; | |
14001 | do_neon_movn (); | |
14002 | return; | |
14003 | } | |
5f4273c7 | 14004 | |
5287ad62 JB |
14005 | constraint (imm < 1 || (unsigned)imm > et.size, |
14006 | _("immediate out of range for narrowing operation")); | |
14007 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
14008 | } | |
14009 | ||
14010 | static void | |
14011 | do_neon_shll (void) | |
14012 | { | |
14013 | /* FIXME: Type checking when lengthening. */ | |
14014 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14015 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14016 | unsigned imm = inst.operands[2].imm; | |
14017 | ||
14018 | if (imm == et.size) | |
14019 | { | |
14020 | /* Maximum shift variant. */ | |
88714cb8 | 14021 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14022 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14023 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14024 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14025 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14026 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14027 | |
88714cb8 | 14028 | neon_dp_fixup (&inst); |
5287ad62 JB |
14029 | } |
14030 | else | |
14031 | { | |
14032 | /* A more-specific type check for non-max versions. */ | |
14033 | et = neon_check_type (2, NS_QDI, | |
14034 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 14035 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14036 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14037 | } | |
14038 | } | |
14039 | ||
037e8744 | 14040 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14041 | the current instruction is. */ |
14042 | ||
14043 | static int | |
14044 | neon_cvt_flavour (enum neon_shape rs) | |
14045 | { | |
037e8744 JB |
14046 | #define CVT_VAR(C,X,Y) \ |
14047 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
14048 | if (et.type != NT_invtype) \ | |
14049 | { \ | |
14050 | inst.error = NULL; \ | |
14051 | return (C); \ | |
5287ad62 JB |
14052 | } |
14053 | struct neon_type_el et; | |
037e8744 JB |
14054 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
14055 | || rs == NS_FF) ? N_VFP : 0; | |
14056 | /* The instruction versions which take an immediate take one register | |
14057 | argument, which is extended to the width of the full register. Thus the | |
14058 | "source" and "destination" registers must have the same width. Hack that | |
14059 | here by making the size equal to the key (wider, in this case) operand. */ | |
14060 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14061 | |
5287ad62 JB |
14062 | CVT_VAR (0, N_S32, N_F32); |
14063 | CVT_VAR (1, N_U32, N_F32); | |
14064 | CVT_VAR (2, N_F32, N_S32); | |
14065 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
14066 | /* Half-precision conversions. */ |
14067 | CVT_VAR (4, N_F32, N_F16); | |
14068 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 14069 | |
037e8744 | 14070 | whole_reg = N_VFP; |
5f4273c7 | 14071 | |
037e8744 | 14072 | /* VFP instructions. */ |
8e79c3df CM |
14073 | CVT_VAR (6, N_F32, N_F64); |
14074 | CVT_VAR (7, N_F64, N_F32); | |
14075 | CVT_VAR (8, N_S32, N_F64 | key); | |
14076 | CVT_VAR (9, N_U32, N_F64 | key); | |
14077 | CVT_VAR (10, N_F64 | key, N_S32); | |
14078 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 14079 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
14080 | CVT_VAR (12, N_F32 | key, N_S16); |
14081 | CVT_VAR (13, N_F32 | key, N_U16); | |
14082 | CVT_VAR (14, N_F64 | key, N_S16); | |
14083 | CVT_VAR (15, N_F64 | key, N_U16); | |
14084 | CVT_VAR (16, N_S16, N_F32 | key); | |
14085 | CVT_VAR (17, N_U16, N_F32 | key); | |
14086 | CVT_VAR (18, N_S16, N_F64 | key); | |
14087 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 14088 | |
5287ad62 JB |
14089 | return -1; |
14090 | #undef CVT_VAR | |
14091 | } | |
14092 | ||
037e8744 JB |
14093 | /* Neon-syntax VFP conversions. */ |
14094 | ||
5287ad62 | 14095 | static void |
037e8744 | 14096 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 14097 | { |
037e8744 | 14098 | const char *opname = 0; |
5f4273c7 | 14099 | |
037e8744 | 14100 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14101 | { |
037e8744 JB |
14102 | /* Conversions with immediate bitshift. */ |
14103 | const char *enc[] = | |
14104 | { | |
14105 | "ftosls", | |
14106 | "ftouls", | |
14107 | "fsltos", | |
14108 | "fultos", | |
14109 | NULL, | |
14110 | NULL, | |
8e79c3df CM |
14111 | NULL, |
14112 | NULL, | |
037e8744 JB |
14113 | "ftosld", |
14114 | "ftould", | |
14115 | "fsltod", | |
14116 | "fultod", | |
14117 | "fshtos", | |
14118 | "fuhtos", | |
14119 | "fshtod", | |
14120 | "fuhtod", | |
14121 | "ftoshs", | |
14122 | "ftouhs", | |
14123 | "ftoshd", | |
14124 | "ftouhd" | |
14125 | }; | |
14126 | ||
14127 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14128 | { | |
14129 | opname = enc[flavour]; | |
14130 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14131 | _("operands 0 and 1 must be the same register")); | |
14132 | inst.operands[1] = inst.operands[2]; | |
14133 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
14134 | } | |
5287ad62 JB |
14135 | } |
14136 | else | |
14137 | { | |
037e8744 JB |
14138 | /* Conversions without bitshift. */ |
14139 | const char *enc[] = | |
14140 | { | |
14141 | "ftosis", | |
14142 | "ftouis", | |
14143 | "fsitos", | |
14144 | "fuitos", | |
8e79c3df CM |
14145 | "NULL", |
14146 | "NULL", | |
037e8744 JB |
14147 | "fcvtsd", |
14148 | "fcvtds", | |
14149 | "ftosid", | |
14150 | "ftouid", | |
14151 | "fsitod", | |
14152 | "fuitod" | |
14153 | }; | |
14154 | ||
14155 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14156 | opname = enc[flavour]; | |
14157 | } | |
14158 | ||
14159 | if (opname) | |
14160 | do_vfp_nsyn_opcode (opname); | |
14161 | } | |
14162 | ||
14163 | static void | |
14164 | do_vfp_nsyn_cvtz (void) | |
14165 | { | |
14166 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
14167 | int flavour = neon_cvt_flavour (rs); | |
14168 | const char *enc[] = | |
14169 | { | |
14170 | "ftosizs", | |
14171 | "ftouizs", | |
14172 | NULL, | |
14173 | NULL, | |
14174 | NULL, | |
14175 | NULL, | |
8e79c3df CM |
14176 | NULL, |
14177 | NULL, | |
037e8744 JB |
14178 | "ftosizd", |
14179 | "ftouizd" | |
14180 | }; | |
14181 | ||
14182 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
14183 | do_vfp_nsyn_opcode (enc[flavour]); | |
14184 | } | |
f31fef98 | 14185 | |
037e8744 | 14186 | static void |
e3e535bc | 14187 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
14188 | { |
14189 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 14190 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
14191 | int flavour = neon_cvt_flavour (rs); |
14192 | ||
e3e535bc NC |
14193 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
14194 | if (round_to_zero | |
14195 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
14196 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
14197 | && (rs == NS_FD || rs == NS_FF)) | |
14198 | { | |
14199 | do_vfp_nsyn_cvtz (); | |
14200 | return; | |
14201 | } | |
14202 | ||
037e8744 | 14203 | /* VFP rather than Neon conversions. */ |
8e79c3df | 14204 | if (flavour >= 6) |
037e8744 JB |
14205 | { |
14206 | do_vfp_nsyn_cvt (rs, flavour); | |
14207 | return; | |
14208 | } | |
14209 | ||
14210 | switch (rs) | |
14211 | { | |
14212 | case NS_DDI: | |
14213 | case NS_QQI: | |
14214 | { | |
35997600 NC |
14215 | unsigned immbits; |
14216 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
14217 | ||
037e8744 JB |
14218 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
14219 | return; | |
14220 | ||
14221 | /* Fixed-point conversion with #0 immediate is encoded as an | |
14222 | integer conversion. */ | |
14223 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
14224 | goto int_encode; | |
35997600 | 14225 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 14226 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
14227 | if (flavour != -1) |
14228 | inst.instruction |= enctab[flavour]; | |
14229 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14230 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14231 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14232 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14233 | inst.instruction |= neon_quad (rs) << 6; | |
14234 | inst.instruction |= 1 << 21; | |
14235 | inst.instruction |= immbits << 16; | |
14236 | ||
88714cb8 | 14237 | neon_dp_fixup (&inst); |
037e8744 JB |
14238 | } |
14239 | break; | |
14240 | ||
14241 | case NS_DD: | |
14242 | case NS_QQ: | |
14243 | int_encode: | |
14244 | { | |
14245 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
14246 | ||
88714cb8 | 14247 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
14248 | |
14249 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14250 | return; | |
14251 | ||
14252 | if (flavour != -1) | |
14253 | inst.instruction |= enctab[flavour]; | |
14254 | ||
14255 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14256 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14257 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14258 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14259 | inst.instruction |= neon_quad (rs) << 6; | |
14260 | inst.instruction |= 2 << 18; | |
14261 | ||
88714cb8 | 14262 | neon_dp_fixup (&inst); |
037e8744 JB |
14263 | } |
14264 | break; | |
14265 | ||
8e79c3df CM |
14266 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
14267 | case NS_QD: | |
14268 | case NS_DQ: | |
14269 | ||
14270 | if ((rs == NS_DQ) | |
14271 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
14272 | { | |
14273 | as_bad (_("operand size must match register width")); | |
14274 | break; | |
14275 | } | |
14276 | ||
14277 | if ((rs == NS_QD) | |
14278 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
14279 | { | |
14280 | as_bad (_("operand size must match register width")); | |
14281 | break; | |
14282 | } | |
14283 | ||
14284 | if (rs == NS_DQ) | |
14285 | inst.instruction = 0x3b60600; | |
14286 | else | |
14287 | inst.instruction = 0x3b60700; | |
14288 | ||
14289 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14290 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14291 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14292 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 14293 | neon_dp_fixup (&inst); |
8e79c3df CM |
14294 | break; |
14295 | ||
037e8744 JB |
14296 | default: |
14297 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
14298 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 14299 | } |
5287ad62 JB |
14300 | } |
14301 | ||
e3e535bc NC |
14302 | static void |
14303 | do_neon_cvtr (void) | |
14304 | { | |
14305 | do_neon_cvt_1 (FALSE); | |
14306 | } | |
14307 | ||
14308 | static void | |
14309 | do_neon_cvt (void) | |
14310 | { | |
14311 | do_neon_cvt_1 (TRUE); | |
14312 | } | |
14313 | ||
8e79c3df CM |
14314 | static void |
14315 | do_neon_cvtb (void) | |
14316 | { | |
14317 | inst.instruction = 0xeb20a40; | |
14318 | ||
14319 | /* The sizes are attached to the mnemonic. */ | |
14320 | if (inst.vectype.el[0].type != NT_invtype | |
14321 | && inst.vectype.el[0].size == 16) | |
14322 | inst.instruction |= 0x00010000; | |
14323 | ||
14324 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
14325 | else if (inst.operands[0].vectype.type != NT_invtype | |
14326 | && inst.operands[0].vectype.size == 16) | |
14327 | inst.instruction |= 0x00010000; | |
14328 | ||
14329 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
14330 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
14331 | do_vfp_cond_or_thumb (); | |
14332 | } | |
14333 | ||
14334 | ||
14335 | static void | |
14336 | do_neon_cvtt (void) | |
14337 | { | |
14338 | do_neon_cvtb (); | |
14339 | inst.instruction |= 0x80; | |
14340 | } | |
14341 | ||
5287ad62 JB |
14342 | static void |
14343 | neon_move_immediate (void) | |
14344 | { | |
037e8744 JB |
14345 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
14346 | struct neon_type_el et = neon_check_type (2, rs, | |
14347 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 14348 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 14349 | int op, cmode, float_p; |
5287ad62 | 14350 | |
037e8744 JB |
14351 | constraint (et.type == NT_invtype, |
14352 | _("operand size must be specified for immediate VMOV")); | |
14353 | ||
5287ad62 JB |
14354 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
14355 | op = (inst.instruction & (1 << 5)) != 0; | |
14356 | ||
14357 | immlo = inst.operands[1].imm; | |
14358 | if (inst.operands[1].regisimm) | |
14359 | immhi = inst.operands[1].reg; | |
14360 | ||
14361 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14362 | _("immediate has bits set outside the operand size")); | |
14363 | ||
c96612cc JB |
14364 | float_p = inst.operands[1].immisfloat; |
14365 | ||
14366 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14367 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14368 | { |
14369 | /* Invert relevant bits only. */ | |
14370 | neon_invert_size (&immlo, &immhi, et.size); | |
14371 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14372 | with one or the other; those cases are caught by | |
14373 | neon_cmode_for_move_imm. */ | |
14374 | op = !op; | |
c96612cc JB |
14375 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14376 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14377 | { |
dcbf9037 | 14378 | first_error (_("immediate out of range")); |
5287ad62 JB |
14379 | return; |
14380 | } | |
14381 | } | |
14382 | ||
14383 | inst.instruction &= ~(1 << 5); | |
14384 | inst.instruction |= op << 5; | |
14385 | ||
14386 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14387 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14388 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14389 | inst.instruction |= cmode << 8; |
14390 | ||
14391 | neon_write_immbits (immbits); | |
14392 | } | |
14393 | ||
14394 | static void | |
14395 | do_neon_mvn (void) | |
14396 | { | |
14397 | if (inst.operands[1].isreg) | |
14398 | { | |
037e8744 | 14399 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14400 | |
88714cb8 | 14401 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14402 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14403 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14404 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14405 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14406 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14407 | } |
14408 | else | |
14409 | { | |
88714cb8 | 14410 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14411 | neon_move_immediate (); |
14412 | } | |
14413 | ||
88714cb8 | 14414 | neon_dp_fixup (&inst); |
5287ad62 JB |
14415 | } |
14416 | ||
14417 | /* Encode instructions of form: | |
14418 | ||
14419 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14420 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14421 | |
14422 | static void | |
14423 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14424 | { | |
14425 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14426 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14427 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14428 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14429 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14430 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14431 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14432 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14433 | |
88714cb8 | 14434 | neon_dp_fixup (&inst); |
5287ad62 JB |
14435 | } |
14436 | ||
14437 | static void | |
14438 | do_neon_dyadic_long (void) | |
14439 | { | |
14440 | /* FIXME: Type checking for lengthening op. */ | |
14441 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14442 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14443 | neon_mixed_length (et, et.size); | |
14444 | } | |
14445 | ||
14446 | static void | |
14447 | do_neon_abal (void) | |
14448 | { | |
14449 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14450 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14451 | neon_mixed_length (et, et.size); | |
14452 | } | |
14453 | ||
14454 | static void | |
14455 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14456 | { | |
14457 | if (inst.operands[2].isscalar) | |
14458 | { | |
dcbf9037 JB |
14459 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14460 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14461 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14462 | neon_mul_mac (et, et.type == NT_unsigned); |
14463 | } | |
14464 | else | |
14465 | { | |
14466 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14467 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14468 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14469 | neon_mixed_length (et, et.size); |
14470 | } | |
14471 | } | |
14472 | ||
14473 | static void | |
14474 | do_neon_mac_maybe_scalar_long (void) | |
14475 | { | |
14476 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14477 | } | |
14478 | ||
14479 | static void | |
14480 | do_neon_dyadic_wide (void) | |
14481 | { | |
14482 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14483 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14484 | neon_mixed_length (et, et.size); | |
14485 | } | |
14486 | ||
14487 | static void | |
14488 | do_neon_dyadic_narrow (void) | |
14489 | { | |
14490 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14491 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14492 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14493 | so force the operand type to integer. */ | |
14494 | et.type = NT_integer; | |
5287ad62 JB |
14495 | neon_mixed_length (et, et.size / 2); |
14496 | } | |
14497 | ||
14498 | static void | |
14499 | do_neon_mul_sat_scalar_long (void) | |
14500 | { | |
14501 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14502 | } | |
14503 | ||
14504 | static void | |
14505 | do_neon_vmull (void) | |
14506 | { | |
14507 | if (inst.operands[2].isscalar) | |
14508 | do_neon_mac_maybe_scalar_long (); | |
14509 | else | |
14510 | { | |
14511 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14512 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14513 | if (et.type == NT_poly) | |
88714cb8 | 14514 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14515 | else |
88714cb8 | 14516 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14517 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14518 | zero. Should be OK as-is. */ | |
14519 | neon_mixed_length (et, et.size); | |
14520 | } | |
14521 | } | |
14522 | ||
14523 | static void | |
14524 | do_neon_ext (void) | |
14525 | { | |
037e8744 | 14526 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14527 | struct neon_type_el et = neon_check_type (3, rs, |
14528 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14529 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14530 | |
14531 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14532 | _("shift out of range")); | |
5287ad62 JB |
14533 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14534 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14535 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14536 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14537 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14538 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14539 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14540 | inst.instruction |= imm << 8; |
5f4273c7 | 14541 | |
88714cb8 | 14542 | neon_dp_fixup (&inst); |
5287ad62 JB |
14543 | } |
14544 | ||
14545 | static void | |
14546 | do_neon_rev (void) | |
14547 | { | |
037e8744 | 14548 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14549 | struct neon_type_el et = neon_check_type (2, rs, |
14550 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14551 | unsigned op = (inst.instruction >> 7) & 3; | |
14552 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14553 | extract it here to check the elements to be reversed are smaller. | |
14554 | Otherwise we'd get a reserved instruction. */ | |
14555 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14556 | gas_assert (elsize != 0); |
5287ad62 JB |
14557 | constraint (et.size >= elsize, |
14558 | _("elements must be smaller than reversal region")); | |
037e8744 | 14559 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14560 | } |
14561 | ||
14562 | static void | |
14563 | do_neon_dup (void) | |
14564 | { | |
14565 | if (inst.operands[1].isscalar) | |
14566 | { | |
037e8744 | 14567 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14568 | struct neon_type_el et = neon_check_type (2, rs, |
14569 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14570 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14571 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14572 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14573 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14574 | |
14575 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14576 | return; | |
14577 | ||
88714cb8 | 14578 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14579 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14580 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14581 | inst.instruction |= LOW4 (dm); | |
14582 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14583 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14584 | inst.instruction |= x << 17; |
14585 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14586 | |
88714cb8 | 14587 | neon_dp_fixup (&inst); |
5287ad62 JB |
14588 | } |
14589 | else | |
14590 | { | |
037e8744 JB |
14591 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14592 | struct neon_type_el et = neon_check_type (2, rs, | |
14593 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14594 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14595 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14596 | switch (et.size) |
14597 | { | |
14598 | case 8: inst.instruction |= 0x400000; break; | |
14599 | case 16: inst.instruction |= 0x000020; break; | |
14600 | case 32: inst.instruction |= 0x000000; break; | |
14601 | default: break; | |
14602 | } | |
14603 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14604 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14605 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14606 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14607 | /* The encoding for this instruction is identical for the ARM and Thumb |
14608 | variants, except for the condition field. */ | |
037e8744 | 14609 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14610 | } |
14611 | } | |
14612 | ||
14613 | /* VMOV has particularly many variations. It can be one of: | |
14614 | 0. VMOV<c><q> <Qd>, <Qm> | |
14615 | 1. VMOV<c><q> <Dd>, <Dm> | |
14616 | (Register operations, which are VORR with Rm = Rn.) | |
14617 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14618 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14619 | (Immediate loads.) | |
14620 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
14621 | (ARM register to scalar.) | |
14622 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
14623 | (Two ARM registers to vector.) | |
14624 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
14625 | (Scalar to ARM register.) | |
14626 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
14627 | (Vector to two ARM registers.) | |
037e8744 JB |
14628 | 8. VMOV.F32 <Sd>, <Sm> |
14629 | 9. VMOV.F64 <Dd>, <Dm> | |
14630 | (VFP register moves.) | |
14631 | 10. VMOV.F32 <Sd>, #imm | |
14632 | 11. VMOV.F64 <Dd>, #imm | |
14633 | (VFP float immediate load.) | |
14634 | 12. VMOV <Rd>, <Sm> | |
14635 | (VFP single to ARM reg.) | |
14636 | 13. VMOV <Sd>, <Rm> | |
14637 | (ARM reg to VFP single.) | |
14638 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
14639 | (Two ARM regs to two VFP singles.) | |
14640 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
14641 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 14642 | |
037e8744 JB |
14643 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
14644 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 14645 | |
5287ad62 | 14646 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 14647 | |
b7fc2769 JB |
14648 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
14649 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 14650 | |
5287ad62 | 14651 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 14652 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
14653 | |
14654 | static void | |
14655 | do_neon_mov (void) | |
14656 | { | |
037e8744 JB |
14657 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
14658 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
14659 | NS_NULL); | |
14660 | struct neon_type_el et; | |
14661 | const char *ldconst = 0; | |
5287ad62 | 14662 | |
037e8744 | 14663 | switch (rs) |
5287ad62 | 14664 | { |
037e8744 JB |
14665 | case NS_DD: /* case 1/9. */ |
14666 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14667 | /* It is not an error here if no type is given. */ | |
14668 | inst.error = NULL; | |
14669 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14670 | { |
037e8744 JB |
14671 | do_vfp_nsyn_opcode ("fcpyd"); |
14672 | break; | |
5287ad62 | 14673 | } |
037e8744 | 14674 | /* fall through. */ |
5287ad62 | 14675 | |
037e8744 JB |
14676 | case NS_QQ: /* case 0/1. */ |
14677 | { | |
14678 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14679 | return; | |
14680 | /* The architecture manual I have doesn't explicitly state which | |
14681 | value the U bit should have for register->register moves, but | |
14682 | the equivalent VORR instruction has U = 0, so do that. */ | |
14683 | inst.instruction = 0x0200110; | |
14684 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14685 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14686 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14687 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14688 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14689 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14690 | inst.instruction |= neon_quad (rs) << 6; | |
14691 | ||
88714cb8 | 14692 | neon_dp_fixup (&inst); |
037e8744 JB |
14693 | } |
14694 | break; | |
5f4273c7 | 14695 | |
037e8744 JB |
14696 | case NS_DI: /* case 3/11. */ |
14697 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14698 | inst.error = NULL; | |
14699 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14700 | { |
037e8744 JB |
14701 | /* case 11 (fconstd). */ |
14702 | ldconst = "fconstd"; | |
14703 | goto encode_fconstd; | |
5287ad62 | 14704 | } |
037e8744 JB |
14705 | /* fall through. */ |
14706 | ||
14707 | case NS_QI: /* case 2/3. */ | |
14708 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14709 | return; | |
14710 | inst.instruction = 0x0800010; | |
14711 | neon_move_immediate (); | |
88714cb8 | 14712 | neon_dp_fixup (&inst); |
5287ad62 | 14713 | break; |
5f4273c7 | 14714 | |
037e8744 JB |
14715 | case NS_SR: /* case 4. */ |
14716 | { | |
14717 | unsigned bcdebits = 0; | |
91d6fa6a | 14718 | int logsize; |
037e8744 JB |
14719 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
14720 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
14721 | ||
91d6fa6a NC |
14722 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
14723 | logsize = neon_logbits (et.size); | |
14724 | ||
037e8744 JB |
14725 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14726 | _(BAD_FPU)); | |
14727 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14728 | && et.size != 32, _(BAD_FPU)); | |
14729 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14730 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14731 | ||
14732 | switch (et.size) | |
14733 | { | |
14734 | case 8: bcdebits = 0x8; break; | |
14735 | case 16: bcdebits = 0x1; break; | |
14736 | case 32: bcdebits = 0x0; break; | |
14737 | default: ; | |
14738 | } | |
14739 | ||
14740 | bcdebits |= x << logsize; | |
14741 | ||
14742 | inst.instruction = 0xe000b10; | |
14743 | do_vfp_cond_or_thumb (); | |
14744 | inst.instruction |= LOW4 (dn) << 16; | |
14745 | inst.instruction |= HI1 (dn) << 7; | |
14746 | inst.instruction |= inst.operands[1].reg << 12; | |
14747 | inst.instruction |= (bcdebits & 3) << 5; | |
14748 | inst.instruction |= (bcdebits >> 2) << 21; | |
14749 | } | |
14750 | break; | |
5f4273c7 | 14751 | |
037e8744 | 14752 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 14753 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 14754 | _(BAD_FPU)); |
b7fc2769 | 14755 | |
037e8744 JB |
14756 | inst.instruction = 0xc400b10; |
14757 | do_vfp_cond_or_thumb (); | |
14758 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
14759 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
14760 | inst.instruction |= inst.operands[1].reg << 12; | |
14761 | inst.instruction |= inst.operands[2].reg << 16; | |
14762 | break; | |
5f4273c7 | 14763 | |
037e8744 JB |
14764 | case NS_RS: /* case 6. */ |
14765 | { | |
91d6fa6a | 14766 | unsigned logsize; |
037e8744 JB |
14767 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
14768 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
14769 | unsigned abcdebits = 0; | |
14770 | ||
91d6fa6a NC |
14771 | et = neon_check_type (2, NS_NULL, |
14772 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
14773 | logsize = neon_logbits (et.size); | |
14774 | ||
037e8744 JB |
14775 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14776 | _(BAD_FPU)); | |
14777 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14778 | && et.size != 32, _(BAD_FPU)); | |
14779 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14780 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14781 | ||
14782 | switch (et.size) | |
14783 | { | |
14784 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
14785 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
14786 | case 32: abcdebits = 0x00; break; | |
14787 | default: ; | |
14788 | } | |
14789 | ||
14790 | abcdebits |= x << logsize; | |
14791 | inst.instruction = 0xe100b10; | |
14792 | do_vfp_cond_or_thumb (); | |
14793 | inst.instruction |= LOW4 (dn) << 16; | |
14794 | inst.instruction |= HI1 (dn) << 7; | |
14795 | inst.instruction |= inst.operands[0].reg << 12; | |
14796 | inst.instruction |= (abcdebits & 3) << 5; | |
14797 | inst.instruction |= (abcdebits >> 2) << 21; | |
14798 | } | |
14799 | break; | |
5f4273c7 | 14800 | |
037e8744 JB |
14801 | case NS_RRD: /* case 7 (fmrrd). */ |
14802 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
14803 | _(BAD_FPU)); | |
14804 | ||
14805 | inst.instruction = 0xc500b10; | |
14806 | do_vfp_cond_or_thumb (); | |
14807 | inst.instruction |= inst.operands[0].reg << 12; | |
14808 | inst.instruction |= inst.operands[1].reg << 16; | |
14809 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14810 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14811 | break; | |
5f4273c7 | 14812 | |
037e8744 JB |
14813 | case NS_FF: /* case 8 (fcpys). */ |
14814 | do_vfp_nsyn_opcode ("fcpys"); | |
14815 | break; | |
5f4273c7 | 14816 | |
037e8744 JB |
14817 | case NS_FI: /* case 10 (fconsts). */ |
14818 | ldconst = "fconsts"; | |
14819 | encode_fconstd: | |
14820 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 14821 | { |
037e8744 JB |
14822 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
14823 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
14824 | } |
14825 | else | |
037e8744 JB |
14826 | first_error (_("immediate out of range")); |
14827 | break; | |
5f4273c7 | 14828 | |
037e8744 JB |
14829 | case NS_RF: /* case 12 (fmrs). */ |
14830 | do_vfp_nsyn_opcode ("fmrs"); | |
14831 | break; | |
5f4273c7 | 14832 | |
037e8744 JB |
14833 | case NS_FR: /* case 13 (fmsr). */ |
14834 | do_vfp_nsyn_opcode ("fmsr"); | |
14835 | break; | |
5f4273c7 | 14836 | |
037e8744 JB |
14837 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
14838 | (one of which is a list), but we have parsed four. Do some fiddling to | |
14839 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
14840 | expect. */ | |
14841 | case NS_RRFF: /* case 14 (fmrrs). */ | |
14842 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
14843 | _("VFP registers must be adjacent")); | |
14844 | inst.operands[2].imm = 2; | |
14845 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14846 | do_vfp_nsyn_opcode ("fmrrs"); | |
14847 | break; | |
5f4273c7 | 14848 | |
037e8744 JB |
14849 | case NS_FFRR: /* case 15 (fmsrr). */ |
14850 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
14851 | _("VFP registers must be adjacent")); | |
14852 | inst.operands[1] = inst.operands[2]; | |
14853 | inst.operands[2] = inst.operands[3]; | |
14854 | inst.operands[0].imm = 2; | |
14855 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14856 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 14857 | break; |
5f4273c7 | 14858 | |
5287ad62 JB |
14859 | default: |
14860 | abort (); | |
14861 | } | |
14862 | } | |
14863 | ||
14864 | static void | |
14865 | do_neon_rshift_round_imm (void) | |
14866 | { | |
037e8744 | 14867 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14868 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
14869 | int imm = inst.operands[2].imm; | |
14870 | ||
14871 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
14872 | if (imm == 0) | |
14873 | { | |
14874 | inst.operands[2].present = 0; | |
14875 | do_neon_mov (); | |
14876 | return; | |
14877 | } | |
14878 | ||
14879 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14880 | _("immediate out of range for shift")); | |
037e8744 | 14881 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
14882 | et.size - imm); |
14883 | } | |
14884 | ||
14885 | static void | |
14886 | do_neon_movl (void) | |
14887 | { | |
14888 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
14889 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14890 | unsigned sizebits = et.size >> 3; | |
14891 | inst.instruction |= sizebits << 19; | |
14892 | neon_two_same (0, et.type == NT_unsigned, -1); | |
14893 | } | |
14894 | ||
14895 | static void | |
14896 | do_neon_trn (void) | |
14897 | { | |
037e8744 | 14898 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14899 | struct neon_type_el et = neon_check_type (2, rs, |
14900 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 14901 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14902 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14903 | } |
14904 | ||
14905 | static void | |
14906 | do_neon_zip_uzp (void) | |
14907 | { | |
037e8744 | 14908 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14909 | struct neon_type_el et = neon_check_type (2, rs, |
14910 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14911 | if (rs == NS_DD && et.size == 32) | |
14912 | { | |
14913 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
14914 | inst.instruction = N_MNEM_vtrn; | |
14915 | do_neon_trn (); | |
14916 | return; | |
14917 | } | |
037e8744 | 14918 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14919 | } |
14920 | ||
14921 | static void | |
14922 | do_neon_sat_abs_neg (void) | |
14923 | { | |
037e8744 | 14924 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14925 | struct neon_type_el et = neon_check_type (2, rs, |
14926 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14927 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14928 | } |
14929 | ||
14930 | static void | |
14931 | do_neon_pair_long (void) | |
14932 | { | |
037e8744 | 14933 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14934 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
14935 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
14936 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 14937 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14938 | } |
14939 | ||
14940 | static void | |
14941 | do_neon_recip_est (void) | |
14942 | { | |
037e8744 | 14943 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14944 | struct neon_type_el et = neon_check_type (2, rs, |
14945 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
14946 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 14947 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14948 | } |
14949 | ||
14950 | static void | |
14951 | do_neon_cls (void) | |
14952 | { | |
037e8744 | 14953 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14954 | struct neon_type_el et = neon_check_type (2, rs, |
14955 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 14956 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14957 | } |
14958 | ||
14959 | static void | |
14960 | do_neon_clz (void) | |
14961 | { | |
037e8744 | 14962 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14963 | struct neon_type_el et = neon_check_type (2, rs, |
14964 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 14965 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14966 | } |
14967 | ||
14968 | static void | |
14969 | do_neon_cnt (void) | |
14970 | { | |
037e8744 | 14971 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14972 | struct neon_type_el et = neon_check_type (2, rs, |
14973 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 14974 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14975 | } |
14976 | ||
14977 | static void | |
14978 | do_neon_swp (void) | |
14979 | { | |
037e8744 JB |
14980 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
14981 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
14982 | } |
14983 | ||
14984 | static void | |
14985 | do_neon_tbl_tbx (void) | |
14986 | { | |
14987 | unsigned listlenbits; | |
dcbf9037 | 14988 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 14989 | |
5287ad62 JB |
14990 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
14991 | { | |
dcbf9037 | 14992 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
14993 | return; |
14994 | } | |
5f4273c7 | 14995 | |
5287ad62 JB |
14996 | listlenbits = inst.operands[1].imm - 1; |
14997 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14998 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14999 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15000 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15001 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15002 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15003 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 15004 | |
88714cb8 | 15005 | neon_dp_fixup (&inst); |
5287ad62 JB |
15006 | } |
15007 | ||
15008 | static void | |
15009 | do_neon_ldm_stm (void) | |
15010 | { | |
15011 | /* P, U and L bits are part of bitmask. */ | |
15012 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
15013 | unsigned offsetbits = inst.operands[1].imm * 2; | |
15014 | ||
037e8744 JB |
15015 | if (inst.operands[1].issingle) |
15016 | { | |
15017 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
15018 | return; | |
15019 | } | |
15020 | ||
5287ad62 JB |
15021 | constraint (is_dbmode && !inst.operands[0].writeback, |
15022 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
15023 | ||
15024 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
15025 | _("register list must contain at least 1 and at most 16 " | |
15026 | "registers")); | |
15027 | ||
15028 | inst.instruction |= inst.operands[0].reg << 16; | |
15029 | inst.instruction |= inst.operands[0].writeback << 21; | |
15030 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
15031 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
15032 | ||
15033 | inst.instruction |= offsetbits; | |
5f4273c7 | 15034 | |
037e8744 | 15035 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15036 | } |
15037 | ||
15038 | static void | |
15039 | do_neon_ldr_str (void) | |
15040 | { | |
5287ad62 | 15041 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 15042 | |
6844b2c2 MGD |
15043 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
15044 | And is UNPREDICTABLE in thumb mode. */ | |
15045 | if (!is_ldr | |
15046 | && inst.operands[1].reg == REG_PC | |
15047 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
15048 | { | |
15049 | if (!thumb_mode && warn_on_deprecated) | |
15050 | as_warn (_("Use of PC here is deprecated")); | |
15051 | else | |
15052 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
15053 | } | |
15054 | ||
037e8744 JB |
15055 | if (inst.operands[0].issingle) |
15056 | { | |
cd2f129f JB |
15057 | if (is_ldr) |
15058 | do_vfp_nsyn_opcode ("flds"); | |
15059 | else | |
15060 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
15061 | } |
15062 | else | |
5287ad62 | 15063 | { |
cd2f129f JB |
15064 | if (is_ldr) |
15065 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 15066 | else |
cd2f129f | 15067 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 15068 | } |
5287ad62 JB |
15069 | } |
15070 | ||
15071 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
15072 | instructions. */ | |
15073 | ||
15074 | static void | |
15075 | do_neon_ld_st_interleave (void) | |
15076 | { | |
037e8744 | 15077 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
15078 | N_8 | N_16 | N_32 | N_64); |
15079 | unsigned alignbits = 0; | |
15080 | unsigned idx; | |
15081 | /* The bits in this table go: | |
15082 | 0: register stride of one (0) or two (1) | |
15083 | 1,2: register list length, minus one (1, 2, 3, 4). | |
15084 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
15085 | We use -1 for invalid entries. */ | |
15086 | const int typetable[] = | |
15087 | { | |
15088 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
15089 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
15090 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
15091 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
15092 | }; | |
15093 | int typebits; | |
15094 | ||
dcbf9037 JB |
15095 | if (et.type == NT_invtype) |
15096 | return; | |
15097 | ||
5287ad62 JB |
15098 | if (inst.operands[1].immisalign) |
15099 | switch (inst.operands[1].imm >> 8) | |
15100 | { | |
15101 | case 64: alignbits = 1; break; | |
15102 | case 128: | |
e23c0ad8 JZ |
15103 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
15104 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
15105 | goto bad_alignment; |
15106 | alignbits = 2; | |
15107 | break; | |
15108 | case 256: | |
e23c0ad8 | 15109 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
15110 | goto bad_alignment; |
15111 | alignbits = 3; | |
15112 | break; | |
15113 | default: | |
15114 | bad_alignment: | |
dcbf9037 | 15115 | first_error (_("bad alignment")); |
5287ad62 JB |
15116 | return; |
15117 | } | |
15118 | ||
15119 | inst.instruction |= alignbits << 4; | |
15120 | inst.instruction |= neon_logbits (et.size) << 6; | |
15121 | ||
15122 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
15123 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
15124 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
15125 | up the right value for "type" in a table based on this value and the given | |
15126 | list style, then stick it back. */ | |
15127 | idx = ((inst.operands[0].imm >> 4) & 7) | |
15128 | | (((inst.instruction >> 8) & 3) << 3); | |
15129 | ||
15130 | typebits = typetable[idx]; | |
5f4273c7 | 15131 | |
5287ad62 JB |
15132 | constraint (typebits == -1, _("bad list type for instruction")); |
15133 | ||
15134 | inst.instruction &= ~0xf00; | |
15135 | inst.instruction |= typebits << 8; | |
15136 | } | |
15137 | ||
15138 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
15139 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
15140 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
15141 | values, terminated with -1. */ | |
15142 | ||
15143 | static int | |
15144 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
15145 | { | |
15146 | va_list ap; | |
15147 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 15148 | |
5287ad62 JB |
15149 | if (!inst.operands[1].immisalign) |
15150 | { | |
15151 | *do_align = 0; | |
15152 | return SUCCESS; | |
15153 | } | |
5f4273c7 | 15154 | |
5287ad62 JB |
15155 | va_start (ap, do_align); |
15156 | ||
15157 | do | |
15158 | { | |
15159 | thissize = va_arg (ap, int); | |
15160 | if (thissize == -1) | |
15161 | break; | |
15162 | thisalign = va_arg (ap, int); | |
15163 | ||
15164 | if (size == thissize && align == thisalign) | |
15165 | result = SUCCESS; | |
15166 | } | |
15167 | while (result != SUCCESS); | |
15168 | ||
15169 | va_end (ap); | |
15170 | ||
15171 | if (result == SUCCESS) | |
15172 | *do_align = 1; | |
15173 | else | |
dcbf9037 | 15174 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 15175 | |
5287ad62 JB |
15176 | return result; |
15177 | } | |
15178 | ||
15179 | static void | |
15180 | do_neon_ld_st_lane (void) | |
15181 | { | |
037e8744 | 15182 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15183 | int align_good, do_align = 0; |
15184 | int logsize = neon_logbits (et.size); | |
15185 | int align = inst.operands[1].imm >> 8; | |
15186 | int n = (inst.instruction >> 8) & 3; | |
15187 | int max_el = 64 / et.size; | |
5f4273c7 | 15188 | |
dcbf9037 JB |
15189 | if (et.type == NT_invtype) |
15190 | return; | |
5f4273c7 | 15191 | |
5287ad62 JB |
15192 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
15193 | _("bad list length")); | |
15194 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
15195 | _("scalar index out of range")); | |
15196 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
15197 | && et.size == 8, | |
15198 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 15199 | |
5287ad62 JB |
15200 | switch (n) |
15201 | { | |
15202 | case 0: /* VLD1 / VST1. */ | |
15203 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
15204 | 32, 32, -1); | |
15205 | if (align_good == FAIL) | |
15206 | return; | |
15207 | if (do_align) | |
15208 | { | |
15209 | unsigned alignbits = 0; | |
15210 | switch (et.size) | |
15211 | { | |
15212 | case 16: alignbits = 0x1; break; | |
15213 | case 32: alignbits = 0x3; break; | |
15214 | default: ; | |
15215 | } | |
15216 | inst.instruction |= alignbits << 4; | |
15217 | } | |
15218 | break; | |
15219 | ||
15220 | case 1: /* VLD2 / VST2. */ | |
15221 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
15222 | 32, 64, -1); | |
15223 | if (align_good == FAIL) | |
15224 | return; | |
15225 | if (do_align) | |
15226 | inst.instruction |= 1 << 4; | |
15227 | break; | |
15228 | ||
15229 | case 2: /* VLD3 / VST3. */ | |
15230 | constraint (inst.operands[1].immisalign, | |
15231 | _("can't use alignment with this instruction")); | |
15232 | break; | |
15233 | ||
15234 | case 3: /* VLD4 / VST4. */ | |
15235 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15236 | 16, 64, 32, 64, 32, 128, -1); | |
15237 | if (align_good == FAIL) | |
15238 | return; | |
15239 | if (do_align) | |
15240 | { | |
15241 | unsigned alignbits = 0; | |
15242 | switch (et.size) | |
15243 | { | |
15244 | case 8: alignbits = 0x1; break; | |
15245 | case 16: alignbits = 0x1; break; | |
15246 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
15247 | default: ; | |
15248 | } | |
15249 | inst.instruction |= alignbits << 4; | |
15250 | } | |
15251 | break; | |
15252 | ||
15253 | default: ; | |
15254 | } | |
15255 | ||
15256 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
15257 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15258 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 15259 | |
5287ad62 JB |
15260 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
15261 | inst.instruction |= logsize << 10; | |
15262 | } | |
15263 | ||
15264 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
15265 | ||
15266 | static void | |
15267 | do_neon_ld_dup (void) | |
15268 | { | |
037e8744 | 15269 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15270 | int align_good, do_align = 0; |
15271 | ||
dcbf9037 JB |
15272 | if (et.type == NT_invtype) |
15273 | return; | |
15274 | ||
5287ad62 JB |
15275 | switch ((inst.instruction >> 8) & 3) |
15276 | { | |
15277 | case 0: /* VLD1. */ | |
9c2799c2 | 15278 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
15279 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
15280 | &do_align, 16, 16, 32, 32, -1); | |
15281 | if (align_good == FAIL) | |
15282 | return; | |
15283 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
15284 | { | |
15285 | case 1: break; | |
15286 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 15287 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
15288 | } |
15289 | inst.instruction |= neon_logbits (et.size) << 6; | |
15290 | break; | |
15291 | ||
15292 | case 1: /* VLD2. */ | |
15293 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
15294 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
15295 | if (align_good == FAIL) | |
15296 | return; | |
15297 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
15298 | _("bad list length")); | |
15299 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15300 | inst.instruction |= 1 << 5; | |
15301 | inst.instruction |= neon_logbits (et.size) << 6; | |
15302 | break; | |
15303 | ||
15304 | case 2: /* VLD3. */ | |
15305 | constraint (inst.operands[1].immisalign, | |
15306 | _("can't use alignment with this instruction")); | |
15307 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
15308 | _("bad list length")); | |
15309 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15310 | inst.instruction |= 1 << 5; | |
15311 | inst.instruction |= neon_logbits (et.size) << 6; | |
15312 | break; | |
15313 | ||
15314 | case 3: /* VLD4. */ | |
15315 | { | |
15316 | int align = inst.operands[1].imm >> 8; | |
15317 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15318 | 16, 64, 32, 64, 32, 128, -1); | |
15319 | if (align_good == FAIL) | |
15320 | return; | |
15321 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
15322 | _("bad list length")); | |
15323 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15324 | inst.instruction |= 1 << 5; | |
15325 | if (et.size == 32 && align == 128) | |
15326 | inst.instruction |= 0x3 << 6; | |
15327 | else | |
15328 | inst.instruction |= neon_logbits (et.size) << 6; | |
15329 | } | |
15330 | break; | |
15331 | ||
15332 | default: ; | |
15333 | } | |
15334 | ||
15335 | inst.instruction |= do_align << 4; | |
15336 | } | |
15337 | ||
15338 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
15339 | apart from bits [11:4]. */ | |
15340 | ||
15341 | static void | |
15342 | do_neon_ldx_stx (void) | |
15343 | { | |
b1a769ed DG |
15344 | if (inst.operands[1].isreg) |
15345 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
15346 | ||
5287ad62 JB |
15347 | switch (NEON_LANE (inst.operands[0].imm)) |
15348 | { | |
15349 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 15350 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
15351 | do_neon_ld_st_interleave (); |
15352 | break; | |
5f4273c7 | 15353 | |
5287ad62 | 15354 | case NEON_ALL_LANES: |
88714cb8 | 15355 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
15356 | do_neon_ld_dup (); |
15357 | break; | |
5f4273c7 | 15358 | |
5287ad62 | 15359 | default: |
88714cb8 | 15360 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
15361 | do_neon_ld_st_lane (); |
15362 | } | |
15363 | ||
15364 | /* L bit comes from bit mask. */ | |
15365 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15366 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15367 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 15368 | |
5287ad62 JB |
15369 | if (inst.operands[1].postind) |
15370 | { | |
15371 | int postreg = inst.operands[1].imm & 0xf; | |
15372 | constraint (!inst.operands[1].immisreg, | |
15373 | _("post-index must be a register")); | |
15374 | constraint (postreg == 0xd || postreg == 0xf, | |
15375 | _("bad register for post-index")); | |
15376 | inst.instruction |= postreg; | |
15377 | } | |
15378 | else if (inst.operands[1].writeback) | |
15379 | { | |
15380 | inst.instruction |= 0xd; | |
15381 | } | |
15382 | else | |
5f4273c7 NC |
15383 | inst.instruction |= 0xf; |
15384 | ||
5287ad62 JB |
15385 | if (thumb_mode) |
15386 | inst.instruction |= 0xf9000000; | |
15387 | else | |
15388 | inst.instruction |= 0xf4000000; | |
15389 | } | |
5287ad62 JB |
15390 | \f |
15391 | /* Overall per-instruction processing. */ | |
15392 | ||
15393 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15394 | This is so that we can handle symbols that are an arbitrary distance from | |
15395 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15396 | which returns part of an address in a form which will be valid for | |
15397 | a data instruction. We do this by pushing the expression into a symbol | |
15398 | in the expr_section, and creating a fix for that. */ | |
15399 | ||
15400 | static void | |
15401 | fix_new_arm (fragS * frag, | |
15402 | int where, | |
15403 | short int size, | |
15404 | expressionS * exp, | |
15405 | int pc_rel, | |
15406 | int reloc) | |
15407 | { | |
15408 | fixS * new_fix; | |
15409 | ||
15410 | switch (exp->X_op) | |
15411 | { | |
15412 | case O_constant: | |
15413 | case O_symbol: | |
15414 | case O_add: | |
15415 | case O_subtract: | |
21d799b5 NC |
15416 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15417 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15418 | break; |
15419 | ||
15420 | default: | |
21d799b5 NC |
15421 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15422 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15423 | break; |
15424 | } | |
15425 | ||
15426 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15427 | instruction. */ | |
15428 | new_fix->tc_fix_data = thumb_mode; | |
15429 | } | |
15430 | ||
15431 | /* Create a frg for an instruction requiring relaxation. */ | |
15432 | static void | |
15433 | output_relax_insn (void) | |
15434 | { | |
15435 | char * to; | |
15436 | symbolS *sym; | |
0110f2b8 PB |
15437 | int offset; |
15438 | ||
6e1cb1a6 PB |
15439 | /* The size of the instruction is unknown, so tie the debug info to the |
15440 | start of the instruction. */ | |
15441 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15442 | |
0110f2b8 PB |
15443 | switch (inst.reloc.exp.X_op) |
15444 | { | |
15445 | case O_symbol: | |
15446 | sym = inst.reloc.exp.X_add_symbol; | |
15447 | offset = inst.reloc.exp.X_add_number; | |
15448 | break; | |
15449 | case O_constant: | |
15450 | sym = NULL; | |
15451 | offset = inst.reloc.exp.X_add_number; | |
15452 | break; | |
15453 | default: | |
15454 | sym = make_expr_symbol (&inst.reloc.exp); | |
15455 | offset = 0; | |
15456 | break; | |
15457 | } | |
15458 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15459 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15460 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15461 | } |
15462 | ||
15463 | /* Write a 32-bit thumb instruction to buf. */ | |
15464 | static void | |
15465 | put_thumb32_insn (char * buf, unsigned long insn) | |
15466 | { | |
15467 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15468 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15469 | } | |
15470 | ||
b99bd4ef | 15471 | static void |
c19d1205 | 15472 | output_inst (const char * str) |
b99bd4ef | 15473 | { |
c19d1205 | 15474 | char * to = NULL; |
b99bd4ef | 15475 | |
c19d1205 | 15476 | if (inst.error) |
b99bd4ef | 15477 | { |
c19d1205 | 15478 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15479 | return; |
15480 | } | |
5f4273c7 NC |
15481 | if (inst.relax) |
15482 | { | |
15483 | output_relax_insn (); | |
0110f2b8 | 15484 | return; |
5f4273c7 | 15485 | } |
c19d1205 ZW |
15486 | if (inst.size == 0) |
15487 | return; | |
b99bd4ef | 15488 | |
c19d1205 | 15489 | to = frag_more (inst.size); |
8dc2430f NC |
15490 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15491 | what type of NOP padding to use, if necessary. We override any previous | |
15492 | setting so that if the mode has changed then the NOPS that we use will | |
15493 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15494 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15495 | |
15496 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15497 | { |
9c2799c2 | 15498 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15499 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15500 | } |
c19d1205 | 15501 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15502 | { |
9c2799c2 | 15503 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15504 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15505 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15506 | } |
c19d1205 ZW |
15507 | else |
15508 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15509 | |
c19d1205 ZW |
15510 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15511 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15512 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15513 | inst.reloc.type); | |
b99bd4ef | 15514 | |
c19d1205 | 15515 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15516 | } |
b99bd4ef | 15517 | |
e07e6e58 NC |
15518 | static char * |
15519 | output_it_inst (int cond, int mask, char * to) | |
15520 | { | |
15521 | unsigned long instruction = 0xbf00; | |
15522 | ||
15523 | mask &= 0xf; | |
15524 | instruction |= mask; | |
15525 | instruction |= cond << 4; | |
15526 | ||
15527 | if (to == NULL) | |
15528 | { | |
15529 | to = frag_more (2); | |
15530 | #ifdef OBJ_ELF | |
15531 | dwarf2_emit_insn (2); | |
15532 | #endif | |
15533 | } | |
15534 | ||
15535 | md_number_to_chars (to, instruction, 2); | |
15536 | ||
15537 | return to; | |
15538 | } | |
15539 | ||
c19d1205 ZW |
15540 | /* Tag values used in struct asm_opcode's tag field. */ |
15541 | enum opcode_tag | |
15542 | { | |
15543 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15544 | The ARM condition field is still 0xE. */ | |
15545 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15546 | and carries 0xF in its ARM condition field. */ | |
15547 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15548 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15549 | suffix, others place 0xF where the condition field | |
15550 | would be. */ | |
c19d1205 ZW |
15551 | OT_cinfix3, /* Instruction takes a conditional infix, |
15552 | beginning at character index 3. (In | |
15553 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15554 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15555 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15556 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15557 | character index 3, even in unified mode. Used for | |
15558 | legacy instructions where suffix and infix forms | |
15559 | may be ambiguous. */ | |
c19d1205 | 15560 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15561 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15562 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15563 | instruction that takes a conditional infix | |
15564 | at an unusual position. In unified mode, | |
15565 | this variant will accept a suffix. */ | |
15566 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15567 | are the conditional variants of instructions that | |
15568 | take conditional infixes in unusual positions. | |
15569 | The infix appears at character index | |
15570 | (tag - OT_odd_infix_0). These are not accepted | |
15571 | in unified mode. */ | |
15572 | }; | |
b99bd4ef | 15573 | |
c19d1205 ZW |
15574 | /* Subroutine of md_assemble, responsible for looking up the primary |
15575 | opcode from the mnemonic the user wrote. STR points to the | |
15576 | beginning of the mnemonic. | |
15577 | ||
15578 | This is not simply a hash table lookup, because of conditional | |
15579 | variants. Most instructions have conditional variants, which are | |
15580 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15581 | to encode each conditional variant as a literal string in the opcode | |
15582 | table, it would have approximately 20,000 entries. | |
15583 | ||
15584 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15585 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15586 | instructions take the affix as an infix, notably the s-variants of | |
15587 | the arithmetic instructions. Of those instructions, all but six | |
15588 | have the infix appear after the third character of the mnemonic. | |
15589 | ||
15590 | Accordingly, the algorithm for looking up primary opcodes given | |
15591 | an identifier is: | |
15592 | ||
15593 | 1. Look up the identifier in the opcode table. | |
15594 | If we find a match, go to step U. | |
15595 | ||
15596 | 2. Look up the last two characters of the identifier in the | |
15597 | conditions table. If we find a match, look up the first N-2 | |
15598 | characters of the identifier in the opcode table. If we | |
15599 | find a match, go to step CE. | |
15600 | ||
15601 | 3. Look up the fourth and fifth characters of the identifier in | |
15602 | the conditions table. If we find a match, extract those | |
15603 | characters from the identifier, and look up the remaining | |
15604 | characters in the opcode table. If we find a match, go | |
15605 | to step CM. | |
15606 | ||
15607 | 4. Fail. | |
15608 | ||
15609 | U. Examine the tag field of the opcode structure, in case this is | |
15610 | one of the six instructions with its conditional infix in an | |
15611 | unusual place. If it is, the tag tells us where to find the | |
15612 | infix; look it up in the conditions table and set inst.cond | |
15613 | accordingly. Otherwise, this is an unconditional instruction. | |
15614 | Again set inst.cond accordingly. Return the opcode structure. | |
15615 | ||
15616 | CE. Examine the tag field to make sure this is an instruction that | |
15617 | should receive a conditional suffix. If it is not, fail. | |
15618 | Otherwise, set inst.cond from the suffix we already looked up, | |
15619 | and return the opcode structure. | |
15620 | ||
15621 | CM. Examine the tag field to make sure this is an instruction that | |
15622 | should receive a conditional infix after the third character. | |
15623 | If it is not, fail. Otherwise, undo the edits to the current | |
15624 | line of input and proceed as for case CE. */ | |
15625 | ||
15626 | static const struct asm_opcode * | |
15627 | opcode_lookup (char **str) | |
15628 | { | |
15629 | char *end, *base; | |
15630 | char *affix; | |
15631 | const struct asm_opcode *opcode; | |
15632 | const struct asm_cond *cond; | |
e3cb604e | 15633 | char save[2]; |
c19d1205 ZW |
15634 | |
15635 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 15636 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 15637 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 15638 | if (*end == ' ' || *end == '.') |
c19d1205 | 15639 | break; |
b99bd4ef | 15640 | |
c19d1205 | 15641 | if (end == base) |
c921be7d | 15642 | return NULL; |
b99bd4ef | 15643 | |
5287ad62 | 15644 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 15645 | if (end[0] == '.') |
b99bd4ef | 15646 | { |
5287ad62 | 15647 | int offset = 2; |
5f4273c7 | 15648 | |
267d2029 JB |
15649 | /* The .w and .n suffixes are only valid if the unified syntax is in |
15650 | use. */ | |
15651 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 15652 | inst.size_req = 4; |
267d2029 | 15653 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
15654 | inst.size_req = 2; |
15655 | else | |
5287ad62 JB |
15656 | offset = 0; |
15657 | ||
15658 | inst.vectype.elems = 0; | |
15659 | ||
15660 | *str = end + offset; | |
b99bd4ef | 15661 | |
5f4273c7 | 15662 | if (end[offset] == '.') |
5287ad62 | 15663 | { |
267d2029 JB |
15664 | /* See if we have a Neon type suffix (possible in either unified or |
15665 | non-unified ARM syntax mode). */ | |
dcbf9037 | 15666 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 15667 | return NULL; |
5287ad62 JB |
15668 | } |
15669 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 15670 | return NULL; |
b99bd4ef | 15671 | } |
c19d1205 ZW |
15672 | else |
15673 | *str = end; | |
b99bd4ef | 15674 | |
c19d1205 | 15675 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
15676 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15677 | end - base); | |
c19d1205 | 15678 | if (opcode) |
b99bd4ef | 15679 | { |
c19d1205 ZW |
15680 | /* step U */ |
15681 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 15682 | { |
c19d1205 ZW |
15683 | inst.cond = COND_ALWAYS; |
15684 | return opcode; | |
b99bd4ef | 15685 | } |
b99bd4ef | 15686 | |
278df34e | 15687 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
15688 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15689 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 15690 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 15691 | gas_assert (cond); |
b99bd4ef | 15692 | |
c19d1205 ZW |
15693 | inst.cond = cond->value; |
15694 | return opcode; | |
15695 | } | |
b99bd4ef | 15696 | |
c19d1205 ZW |
15697 | /* Cannot have a conditional suffix on a mnemonic of less than two |
15698 | characters. */ | |
15699 | if (end - base < 3) | |
c921be7d | 15700 | return NULL; |
b99bd4ef | 15701 | |
c19d1205 ZW |
15702 | /* Look for suffixed mnemonic. */ |
15703 | affix = end - 2; | |
21d799b5 NC |
15704 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
15705 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
15706 | affix - base); | |
c19d1205 ZW |
15707 | if (opcode && cond) |
15708 | { | |
15709 | /* step CE */ | |
15710 | switch (opcode->tag) | |
15711 | { | |
e3cb604e PB |
15712 | case OT_cinfix3_legacy: |
15713 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
15714 | break; | |
15715 | ||
c19d1205 | 15716 | case OT_cinfix3: |
088fa78e | 15717 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
15718 | case OT_odd_infix_unc: |
15719 | if (!unified_syntax) | |
e3cb604e | 15720 | return 0; |
c19d1205 ZW |
15721 | /* else fall through */ |
15722 | ||
15723 | case OT_csuffix: | |
037e8744 | 15724 | case OT_csuffixF: |
c19d1205 ZW |
15725 | case OT_csuf_or_in3: |
15726 | inst.cond = cond->value; | |
15727 | return opcode; | |
15728 | ||
15729 | case OT_unconditional: | |
15730 | case OT_unconditionalF: | |
dfa9f0d5 | 15731 | if (thumb_mode) |
c921be7d | 15732 | inst.cond = cond->value; |
dfa9f0d5 PB |
15733 | else |
15734 | { | |
c921be7d | 15735 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
15736 | inst.error = BAD_COND; |
15737 | inst.cond = COND_ALWAYS; | |
15738 | } | |
c19d1205 | 15739 | return opcode; |
b99bd4ef | 15740 | |
c19d1205 | 15741 | default: |
c921be7d | 15742 | return NULL; |
c19d1205 ZW |
15743 | } |
15744 | } | |
b99bd4ef | 15745 | |
c19d1205 ZW |
15746 | /* Cannot have a usual-position infix on a mnemonic of less than |
15747 | six characters (five would be a suffix). */ | |
15748 | if (end - base < 6) | |
c921be7d | 15749 | return NULL; |
b99bd4ef | 15750 | |
c19d1205 ZW |
15751 | /* Look for infixed mnemonic in the usual position. */ |
15752 | affix = base + 3; | |
21d799b5 | 15753 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 15754 | if (!cond) |
c921be7d | 15755 | return NULL; |
e3cb604e PB |
15756 | |
15757 | memcpy (save, affix, 2); | |
15758 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
15759 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15760 | (end - base) - 2); | |
e3cb604e PB |
15761 | memmove (affix + 2, affix, (end - affix) - 2); |
15762 | memcpy (affix, save, 2); | |
15763 | ||
088fa78e KH |
15764 | if (opcode |
15765 | && (opcode->tag == OT_cinfix3 | |
15766 | || opcode->tag == OT_cinfix3_deprecated | |
15767 | || opcode->tag == OT_csuf_or_in3 | |
15768 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 15769 | { |
c921be7d | 15770 | /* Step CM. */ |
278df34e | 15771 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
15772 | && (opcode->tag == OT_cinfix3 |
15773 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
15774 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15775 | ||
15776 | inst.cond = cond->value; | |
15777 | return opcode; | |
b99bd4ef NC |
15778 | } |
15779 | ||
c921be7d | 15780 | return NULL; |
b99bd4ef NC |
15781 | } |
15782 | ||
e07e6e58 NC |
15783 | /* This function generates an initial IT instruction, leaving its block |
15784 | virtually open for the new instructions. Eventually, | |
15785 | the mask will be updated by now_it_add_mask () each time | |
15786 | a new instruction needs to be included in the IT block. | |
15787 | Finally, the block is closed with close_automatic_it_block (). | |
15788 | The block closure can be requested either from md_assemble (), | |
15789 | a tencode (), or due to a label hook. */ | |
15790 | ||
15791 | static void | |
15792 | new_automatic_it_block (int cond) | |
15793 | { | |
15794 | now_it.state = AUTOMATIC_IT_BLOCK; | |
15795 | now_it.mask = 0x18; | |
15796 | now_it.cc = cond; | |
15797 | now_it.block_length = 1; | |
cd000bff | 15798 | mapping_state (MAP_THUMB); |
e07e6e58 NC |
15799 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
15800 | } | |
15801 | ||
15802 | /* Close an automatic IT block. | |
15803 | See comments in new_automatic_it_block (). */ | |
15804 | ||
15805 | static void | |
15806 | close_automatic_it_block (void) | |
15807 | { | |
15808 | now_it.mask = 0x10; | |
15809 | now_it.block_length = 0; | |
15810 | } | |
15811 | ||
15812 | /* Update the mask of the current automatically-generated IT | |
15813 | instruction. See comments in new_automatic_it_block (). */ | |
15814 | ||
15815 | static void | |
15816 | now_it_add_mask (int cond) | |
15817 | { | |
15818 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
15819 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
15820 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 15821 | const int resulting_bit = (cond & 1); |
c921be7d | 15822 | |
e07e6e58 NC |
15823 | now_it.mask &= 0xf; |
15824 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15825 | resulting_bit, | |
15826 | (5 - now_it.block_length)); | |
15827 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15828 | 1, | |
15829 | ((5 - now_it.block_length) - 1) ); | |
15830 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
15831 | ||
15832 | #undef CLEAR_BIT | |
15833 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
15834 | } |
15835 | ||
15836 | /* The IT blocks handling machinery is accessed through the these functions: | |
15837 | it_fsm_pre_encode () from md_assemble () | |
15838 | set_it_insn_type () optional, from the tencode functions | |
15839 | set_it_insn_type_last () ditto | |
15840 | in_it_block () ditto | |
15841 | it_fsm_post_encode () from md_assemble () | |
15842 | force_automatic_it_block_close () from label habdling functions | |
15843 | ||
15844 | Rationale: | |
15845 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
15846 | initializing the IT insn type with a generic initial value depending | |
15847 | on the inst.condition. | |
15848 | 2) During the tencode function, two things may happen: | |
15849 | a) The tencode function overrides the IT insn type by | |
15850 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
15851 | b) The tencode function queries the IT block state by | |
15852 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
15853 | ||
15854 | Both set_it_insn_type and in_it_block run the internal FSM state | |
15855 | handling function (handle_it_state), because: a) setting the IT insn | |
15856 | type may incur in an invalid state (exiting the function), | |
15857 | and b) querying the state requires the FSM to be updated. | |
15858 | Specifically we want to avoid creating an IT block for conditional | |
15859 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
15860 | determine whether an IT block is required until the tencode () routine | |
15861 | has decided what type of instruction this actually it. | |
15862 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
15863 | set_it_insn_type has to be called first. | |
15864 | ||
15865 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
15866 | determines the insn IT type depending on the inst.cond code. | |
15867 | When a tencode () routine encodes an instruction that can be | |
15868 | either outside an IT block, or, in the case of being inside, has to be | |
15869 | the last one, set_it_insn_type_last () will determine the proper | |
15870 | IT instruction type based on the inst.cond code. Otherwise, | |
15871 | set_it_insn_type can be called for overriding that logic or | |
15872 | for covering other cases. | |
15873 | ||
15874 | Calling handle_it_state () may not transition the IT block state to | |
15875 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
15876 | still queried. Instead, if the FSM determines that the state should | |
15877 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
15878 | after the tencode () function: that's what it_fsm_post_encode () does. | |
15879 | ||
15880 | Since in_it_block () calls the state handling function to get an | |
15881 | updated state, an error may occur (due to invalid insns combination). | |
15882 | In that case, inst.error is set. | |
15883 | Therefore, inst.error has to be checked after the execution of | |
15884 | the tencode () routine. | |
15885 | ||
15886 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
15887 | any pending state change (if any) that didn't take place in | |
15888 | handle_it_state () as explained above. */ | |
15889 | ||
15890 | static void | |
15891 | it_fsm_pre_encode (void) | |
15892 | { | |
15893 | if (inst.cond != COND_ALWAYS) | |
15894 | inst.it_insn_type = INSIDE_IT_INSN; | |
15895 | else | |
15896 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
15897 | ||
15898 | now_it.state_handled = 0; | |
15899 | } | |
15900 | ||
15901 | /* IT state FSM handling function. */ | |
15902 | ||
15903 | static int | |
15904 | handle_it_state (void) | |
15905 | { | |
15906 | now_it.state_handled = 1; | |
15907 | ||
15908 | switch (now_it.state) | |
15909 | { | |
15910 | case OUTSIDE_IT_BLOCK: | |
15911 | switch (inst.it_insn_type) | |
15912 | { | |
15913 | case OUTSIDE_IT_INSN: | |
15914 | break; | |
15915 | ||
15916 | case INSIDE_IT_INSN: | |
15917 | case INSIDE_IT_LAST_INSN: | |
15918 | if (thumb_mode == 0) | |
15919 | { | |
c921be7d | 15920 | if (unified_syntax |
e07e6e58 NC |
15921 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
15922 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
15923 | " for Thumb.")); | |
15924 | } | |
15925 | else | |
15926 | { | |
15927 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
15928 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
15929 | { | |
15930 | /* Automatically generate the IT instruction. */ | |
15931 | new_automatic_it_block (inst.cond); | |
15932 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
15933 | close_automatic_it_block (); | |
15934 | } | |
15935 | else | |
15936 | { | |
15937 | inst.error = BAD_OUT_IT; | |
15938 | return FAIL; | |
15939 | } | |
15940 | } | |
15941 | break; | |
15942 | ||
15943 | case IF_INSIDE_IT_LAST_INSN: | |
15944 | case NEUTRAL_IT_INSN: | |
15945 | break; | |
15946 | ||
15947 | case IT_INSN: | |
15948 | now_it.state = MANUAL_IT_BLOCK; | |
15949 | now_it.block_length = 0; | |
15950 | break; | |
15951 | } | |
15952 | break; | |
15953 | ||
15954 | case AUTOMATIC_IT_BLOCK: | |
15955 | /* Three things may happen now: | |
15956 | a) We should increment current it block size; | |
15957 | b) We should close current it block (closing insn or 4 insns); | |
15958 | c) We should close current it block and start a new one (due | |
15959 | to incompatible conditions or | |
15960 | 4 insns-length block reached). */ | |
15961 | ||
15962 | switch (inst.it_insn_type) | |
15963 | { | |
15964 | case OUTSIDE_IT_INSN: | |
15965 | /* The closure of the block shall happen immediatelly, | |
15966 | so any in_it_block () call reports the block as closed. */ | |
15967 | force_automatic_it_block_close (); | |
15968 | break; | |
15969 | ||
15970 | case INSIDE_IT_INSN: | |
15971 | case INSIDE_IT_LAST_INSN: | |
15972 | case IF_INSIDE_IT_LAST_INSN: | |
15973 | now_it.block_length++; | |
15974 | ||
15975 | if (now_it.block_length > 4 | |
15976 | || !now_it_compatible (inst.cond)) | |
15977 | { | |
15978 | force_automatic_it_block_close (); | |
15979 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
15980 | new_automatic_it_block (inst.cond); | |
15981 | } | |
15982 | else | |
15983 | { | |
15984 | now_it_add_mask (inst.cond); | |
15985 | } | |
15986 | ||
15987 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
15988 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
15989 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
15990 | close_automatic_it_block (); | |
15991 | break; | |
15992 | ||
15993 | case NEUTRAL_IT_INSN: | |
15994 | now_it.block_length++; | |
15995 | ||
15996 | if (now_it.block_length > 4) | |
15997 | force_automatic_it_block_close (); | |
15998 | else | |
15999 | now_it_add_mask (now_it.cc & 1); | |
16000 | break; | |
16001 | ||
16002 | case IT_INSN: | |
16003 | close_automatic_it_block (); | |
16004 | now_it.state = MANUAL_IT_BLOCK; | |
16005 | break; | |
16006 | } | |
16007 | break; | |
16008 | ||
16009 | case MANUAL_IT_BLOCK: | |
16010 | { | |
16011 | /* Check conditional suffixes. */ | |
16012 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
16013 | int is_last; | |
16014 | now_it.mask <<= 1; | |
16015 | now_it.mask &= 0x1f; | |
16016 | is_last = (now_it.mask == 0x10); | |
16017 | ||
16018 | switch (inst.it_insn_type) | |
16019 | { | |
16020 | case OUTSIDE_IT_INSN: | |
16021 | inst.error = BAD_NOT_IT; | |
16022 | return FAIL; | |
16023 | ||
16024 | case INSIDE_IT_INSN: | |
16025 | if (cond != inst.cond) | |
16026 | { | |
16027 | inst.error = BAD_IT_COND; | |
16028 | return FAIL; | |
16029 | } | |
16030 | break; | |
16031 | ||
16032 | case INSIDE_IT_LAST_INSN: | |
16033 | case IF_INSIDE_IT_LAST_INSN: | |
16034 | if (cond != inst.cond) | |
16035 | { | |
16036 | inst.error = BAD_IT_COND; | |
16037 | return FAIL; | |
16038 | } | |
16039 | if (!is_last) | |
16040 | { | |
16041 | inst.error = BAD_BRANCH; | |
16042 | return FAIL; | |
16043 | } | |
16044 | break; | |
16045 | ||
16046 | case NEUTRAL_IT_INSN: | |
16047 | /* The BKPT instruction is unconditional even in an IT block. */ | |
16048 | break; | |
16049 | ||
16050 | case IT_INSN: | |
16051 | inst.error = BAD_IT_IT; | |
16052 | return FAIL; | |
16053 | } | |
16054 | } | |
16055 | break; | |
16056 | } | |
16057 | ||
16058 | return SUCCESS; | |
16059 | } | |
16060 | ||
16061 | static void | |
16062 | it_fsm_post_encode (void) | |
16063 | { | |
16064 | int is_last; | |
16065 | ||
16066 | if (!now_it.state_handled) | |
16067 | handle_it_state (); | |
16068 | ||
16069 | is_last = (now_it.mask == 0x10); | |
16070 | if (is_last) | |
16071 | { | |
16072 | now_it.state = OUTSIDE_IT_BLOCK; | |
16073 | now_it.mask = 0; | |
16074 | } | |
16075 | } | |
16076 | ||
16077 | static void | |
16078 | force_automatic_it_block_close (void) | |
16079 | { | |
16080 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
16081 | { | |
16082 | close_automatic_it_block (); | |
16083 | now_it.state = OUTSIDE_IT_BLOCK; | |
16084 | now_it.mask = 0; | |
16085 | } | |
16086 | } | |
16087 | ||
16088 | static int | |
16089 | in_it_block (void) | |
16090 | { | |
16091 | if (!now_it.state_handled) | |
16092 | handle_it_state (); | |
16093 | ||
16094 | return now_it.state != OUTSIDE_IT_BLOCK; | |
16095 | } | |
16096 | ||
c19d1205 ZW |
16097 | void |
16098 | md_assemble (char *str) | |
b99bd4ef | 16099 | { |
c19d1205 ZW |
16100 | char *p = str; |
16101 | const struct asm_opcode * opcode; | |
b99bd4ef | 16102 | |
c19d1205 ZW |
16103 | /* Align the previous label if needed. */ |
16104 | if (last_label_seen != NULL) | |
b99bd4ef | 16105 | { |
c19d1205 ZW |
16106 | symbol_set_frag (last_label_seen, frag_now); |
16107 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
16108 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
16109 | } |
16110 | ||
c19d1205 ZW |
16111 | memset (&inst, '\0', sizeof (inst)); |
16112 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 16113 | |
c19d1205 ZW |
16114 | opcode = opcode_lookup (&p); |
16115 | if (!opcode) | |
b99bd4ef | 16116 | { |
c19d1205 | 16117 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 16118 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
16119 | if (! create_register_alias (str, p) |
16120 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 16121 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 16122 | |
b99bd4ef NC |
16123 | return; |
16124 | } | |
16125 | ||
278df34e | 16126 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
16127 | as_warn (_("s suffix on comparison instruction is deprecated")); |
16128 | ||
037e8744 JB |
16129 | /* The value which unconditional instructions should have in place of the |
16130 | condition field. */ | |
16131 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
16132 | ||
c19d1205 | 16133 | if (thumb_mode) |
b99bd4ef | 16134 | { |
e74cfd16 | 16135 | arm_feature_set variant; |
8f06b2d8 PB |
16136 | |
16137 | variant = cpu_variant; | |
16138 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
16139 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
16140 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 16141 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
16142 | if (!opcode->tvariant |
16143 | || (thumb_mode == 1 | |
16144 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 16145 | { |
bf3eeda7 | 16146 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
16147 | return; |
16148 | } | |
c19d1205 ZW |
16149 | if (inst.cond != COND_ALWAYS && !unified_syntax |
16150 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 16151 | { |
c19d1205 | 16152 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
16153 | return; |
16154 | } | |
16155 | ||
752d5da4 | 16156 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 16157 | { |
7e806470 | 16158 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
16159 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
16160 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
16161 | { | |
16162 | /* Two things are addressed here. | |
16163 | 1) Implicit require narrow instructions on Thumb-1. | |
16164 | This avoids relaxation accidentally introducing Thumb-2 | |
16165 | instructions. | |
16166 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
16167 | if (inst.size_req == 0) | |
16168 | inst.size_req = 2; | |
16169 | else if (inst.size_req == 4) | |
16170 | { | |
bf3eeda7 | 16171 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
16172 | return; |
16173 | } | |
16174 | } | |
076d447c PB |
16175 | } |
16176 | ||
c19d1205 ZW |
16177 | inst.instruction = opcode->tvalue; |
16178 | ||
5be8be5d | 16179 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
16180 | { |
16181 | /* Prepare the it_insn_type for those encodings that don't set | |
16182 | it. */ | |
16183 | it_fsm_pre_encode (); | |
c19d1205 | 16184 | |
e07e6e58 NC |
16185 | opcode->tencode (); |
16186 | ||
16187 | it_fsm_post_encode (); | |
16188 | } | |
e27ec89e | 16189 | |
0110f2b8 | 16190 | if (!(inst.error || inst.relax)) |
b99bd4ef | 16191 | { |
9c2799c2 | 16192 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
16193 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
16194 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 16195 | { |
c19d1205 | 16196 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
16197 | return; |
16198 | } | |
16199 | } | |
076d447c PB |
16200 | |
16201 | /* Something has gone badly wrong if we try to relax a fixed size | |
16202 | instruction. */ | |
9c2799c2 | 16203 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 16204 | |
e74cfd16 PB |
16205 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16206 | *opcode->tvariant); | |
ee065d83 | 16207 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 16208 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 16209 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 16210 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
16211 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
16212 | || inst.relax) | |
e07e6e58 NC |
16213 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
16214 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
16215 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16216 | arm_ext_v6t2); | |
cd000bff | 16217 | |
88714cb8 DG |
16218 | check_neon_suffixes; |
16219 | ||
cd000bff | 16220 | if (!inst.error) |
c877a2f2 NC |
16221 | { |
16222 | mapping_state (MAP_THUMB); | |
16223 | } | |
c19d1205 | 16224 | } |
3e9e4fcf | 16225 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 16226 | { |
845b51d6 PB |
16227 | bfd_boolean is_bx; |
16228 | ||
16229 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
16230 | is_bx = (opcode->aencode == do_bx); | |
16231 | ||
c19d1205 | 16232 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
16233 | if (!(is_bx && fix_v4bx) |
16234 | && !(opcode->avariant && | |
16235 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 16236 | { |
bf3eeda7 | 16237 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 16238 | return; |
b99bd4ef | 16239 | } |
c19d1205 | 16240 | if (inst.size_req) |
b99bd4ef | 16241 | { |
c19d1205 ZW |
16242 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
16243 | return; | |
b99bd4ef NC |
16244 | } |
16245 | ||
c19d1205 ZW |
16246 | inst.instruction = opcode->avalue; |
16247 | if (opcode->tag == OT_unconditionalF) | |
16248 | inst.instruction |= 0xF << 28; | |
16249 | else | |
16250 | inst.instruction |= inst.cond << 28; | |
16251 | inst.size = INSN_SIZE; | |
5be8be5d | 16252 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
16253 | { |
16254 | it_fsm_pre_encode (); | |
16255 | opcode->aencode (); | |
16256 | it_fsm_post_encode (); | |
16257 | } | |
ee065d83 PB |
16258 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
16259 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 16260 | if (is_bx) |
e74cfd16 | 16261 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 16262 | else |
e74cfd16 PB |
16263 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
16264 | *opcode->avariant); | |
88714cb8 DG |
16265 | |
16266 | check_neon_suffixes; | |
16267 | ||
cd000bff | 16268 | if (!inst.error) |
c877a2f2 NC |
16269 | { |
16270 | mapping_state (MAP_ARM); | |
16271 | } | |
b99bd4ef | 16272 | } |
3e9e4fcf JB |
16273 | else |
16274 | { | |
16275 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
16276 | "-- `%s'"), str); | |
16277 | return; | |
16278 | } | |
c19d1205 ZW |
16279 | output_inst (str); |
16280 | } | |
b99bd4ef | 16281 | |
e07e6e58 NC |
16282 | static void |
16283 | check_it_blocks_finished (void) | |
16284 | { | |
16285 | #ifdef OBJ_ELF | |
16286 | asection *sect; | |
16287 | ||
16288 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
16289 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
16290 | == MANUAL_IT_BLOCK) | |
16291 | { | |
16292 | as_warn (_("section '%s' finished with an open IT block."), | |
16293 | sect->name); | |
16294 | } | |
16295 | #else | |
16296 | if (now_it.state == MANUAL_IT_BLOCK) | |
16297 | as_warn (_("file finished with an open IT block.")); | |
16298 | #endif | |
16299 | } | |
16300 | ||
c19d1205 ZW |
16301 | /* Various frobbings of labels and their addresses. */ |
16302 | ||
16303 | void | |
16304 | arm_start_line_hook (void) | |
16305 | { | |
16306 | last_label_seen = NULL; | |
b99bd4ef NC |
16307 | } |
16308 | ||
c19d1205 ZW |
16309 | void |
16310 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 16311 | { |
c19d1205 | 16312 | last_label_seen = sym; |
b99bd4ef | 16313 | |
c19d1205 | 16314 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 16315 | |
c19d1205 ZW |
16316 | #if defined OBJ_COFF || defined OBJ_ELF |
16317 | ARM_SET_INTERWORK (sym, support_interwork); | |
16318 | #endif | |
b99bd4ef | 16319 | |
e07e6e58 NC |
16320 | force_automatic_it_block_close (); |
16321 | ||
5f4273c7 | 16322 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
16323 | as Thumb functions. This is because these labels, whilst |
16324 | they exist inside Thumb code, are not the entry points for | |
16325 | possible ARM->Thumb calls. Also, these labels can be used | |
16326 | as part of a computed goto or switch statement. eg gcc | |
16327 | can generate code that looks like this: | |
b99bd4ef | 16328 | |
c19d1205 ZW |
16329 | ldr r2, [pc, .Laaa] |
16330 | lsl r3, r3, #2 | |
16331 | ldr r2, [r3, r2] | |
16332 | mov pc, r2 | |
b99bd4ef | 16333 | |
c19d1205 ZW |
16334 | .Lbbb: .word .Lxxx |
16335 | .Lccc: .word .Lyyy | |
16336 | ..etc... | |
16337 | .Laaa: .word Lbbb | |
b99bd4ef | 16338 | |
c19d1205 ZW |
16339 | The first instruction loads the address of the jump table. |
16340 | The second instruction converts a table index into a byte offset. | |
16341 | The third instruction gets the jump address out of the table. | |
16342 | The fourth instruction performs the jump. | |
b99bd4ef | 16343 | |
c19d1205 ZW |
16344 | If the address stored at .Laaa is that of a symbol which has the |
16345 | Thumb_Func bit set, then the linker will arrange for this address | |
16346 | to have the bottom bit set, which in turn would mean that the | |
16347 | address computation performed by the third instruction would end | |
16348 | up with the bottom bit set. Since the ARM is capable of unaligned | |
16349 | word loads, the instruction would then load the incorrect address | |
16350 | out of the jump table, and chaos would ensue. */ | |
16351 | if (label_is_thumb_function_name | |
16352 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
16353 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 16354 | { |
c19d1205 ZW |
16355 | /* When the address of a Thumb function is taken the bottom |
16356 | bit of that address should be set. This will allow | |
16357 | interworking between Arm and Thumb functions to work | |
16358 | correctly. */ | |
b99bd4ef | 16359 | |
c19d1205 | 16360 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 16361 | |
c19d1205 | 16362 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 16363 | } |
07a53e5c | 16364 | |
07a53e5c | 16365 | dwarf2_emit_label (sym); |
b99bd4ef NC |
16366 | } |
16367 | ||
c921be7d | 16368 | bfd_boolean |
c19d1205 | 16369 | arm_data_in_code (void) |
b99bd4ef | 16370 | { |
c19d1205 | 16371 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16372 | { |
c19d1205 ZW |
16373 | *input_line_pointer = '/'; |
16374 | input_line_pointer += 5; | |
16375 | *input_line_pointer = 0; | |
c921be7d | 16376 | return TRUE; |
b99bd4ef NC |
16377 | } |
16378 | ||
c921be7d | 16379 | return FALSE; |
b99bd4ef NC |
16380 | } |
16381 | ||
c19d1205 ZW |
16382 | char * |
16383 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16384 | { |
c19d1205 | 16385 | int len; |
b99bd4ef | 16386 | |
c19d1205 ZW |
16387 | if (thumb_mode && (len = strlen (name)) > 5 |
16388 | && streq (name + len - 5, "/data")) | |
16389 | *(name + len - 5) = 0; | |
b99bd4ef | 16390 | |
c19d1205 | 16391 | return name; |
b99bd4ef | 16392 | } |
c19d1205 ZW |
16393 | \f |
16394 | /* Table of all register names defined by default. The user can | |
16395 | define additional names with .req. Note that all register names | |
16396 | should appear in both upper and lowercase variants. Some registers | |
16397 | also have mixed-case names. */ | |
b99bd4ef | 16398 | |
dcbf9037 | 16399 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16400 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16401 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16402 | #define REGSET(p,t) \ |
16403 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16404 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16405 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16406 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16407 | #define REGSETH(p,t) \ |
16408 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16409 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16410 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16411 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16412 | #define REGSET2(p,t) \ | |
16413 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16414 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16415 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16416 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
16417 | #define SPLRBANK(base,bank,t) \ |
16418 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
16419 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
16420 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
16421 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
16422 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
16423 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 16424 | |
c19d1205 | 16425 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16426 | { |
c19d1205 ZW |
16427 | /* ARM integer registers. */ |
16428 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16429 | |
c19d1205 ZW |
16430 | /* ATPCS synonyms. */ |
16431 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16432 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16433 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16434 | |
c19d1205 ZW |
16435 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16436 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16437 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16438 | |
c19d1205 ZW |
16439 | /* Well-known aliases. */ |
16440 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16441 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16442 | ||
16443 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16444 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16445 | ||
16446 | /* Coprocessor numbers. */ | |
16447 | REGSET(p, CP), REGSET(P, CP), | |
16448 | ||
16449 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16450 | compatibility. */ | |
16451 | REGSET(c, CN), REGSET(C, CN), | |
16452 | REGSET(cr, CN), REGSET(CR, CN), | |
16453 | ||
90ec0d68 MGD |
16454 | /* ARM banked registers. */ |
16455 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
16456 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
16457 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
16458 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
16459 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
16460 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
16461 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
16462 | ||
16463 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
16464 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
16465 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
16466 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
16467 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
16468 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB), | |
16469 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), | |
16470 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
16471 | ||
16472 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
16473 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
16474 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
16475 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
16476 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
16477 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
16478 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
16479 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), | |
16480 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), | |
16481 | ||
c19d1205 ZW |
16482 | /* FPA registers. */ |
16483 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16484 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16485 | ||
16486 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16487 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16488 | ||
16489 | /* VFP SP registers. */ | |
5287ad62 JB |
16490 | REGSET(s,VFS), REGSET(S,VFS), |
16491 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16492 | |
16493 | /* VFP DP Registers. */ | |
5287ad62 JB |
16494 | REGSET(d,VFD), REGSET(D,VFD), |
16495 | /* Extra Neon DP registers. */ | |
16496 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16497 | ||
16498 | /* Neon QP registers. */ | |
16499 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16500 | |
16501 | /* VFP control registers. */ | |
16502 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16503 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16504 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16505 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16506 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16507 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16508 | |
16509 | /* Maverick DSP coprocessor registers. */ | |
16510 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16511 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16512 | ||
16513 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16514 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16515 | REGDEF(dspsc,0,DSPSC), | |
16516 | ||
16517 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16518 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16519 | REGDEF(DSPSC,0,DSPSC), | |
16520 | ||
16521 | /* iWMMXt data registers - p0, c0-15. */ | |
16522 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16523 | ||
16524 | /* iWMMXt control registers - p1, c0-3. */ | |
16525 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16526 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16527 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16528 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16529 | ||
16530 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16531 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16532 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16533 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
16534 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
16535 | ||
16536 | /* XScale accumulator registers. */ | |
16537 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
16538 | }; | |
16539 | #undef REGDEF | |
16540 | #undef REGNUM | |
16541 | #undef REGSET | |
7ed4c4c5 | 16542 | |
c19d1205 ZW |
16543 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
16544 | within psr_required_here. */ | |
16545 | static const struct asm_psr psrs[] = | |
16546 | { | |
16547 | /* Backward compatibility notation. Note that "all" is no longer | |
16548 | truly all possible PSR bits. */ | |
16549 | {"all", PSR_c | PSR_f}, | |
16550 | {"flg", PSR_f}, | |
16551 | {"ctl", PSR_c}, | |
16552 | ||
16553 | /* Individual flags. */ | |
16554 | {"f", PSR_f}, | |
16555 | {"c", PSR_c}, | |
16556 | {"x", PSR_x}, | |
16557 | {"s", PSR_s}, | |
59b42a0d | 16558 | |
c19d1205 ZW |
16559 | /* Combinations of flags. */ |
16560 | {"fs", PSR_f | PSR_s}, | |
16561 | {"fx", PSR_f | PSR_x}, | |
16562 | {"fc", PSR_f | PSR_c}, | |
16563 | {"sf", PSR_s | PSR_f}, | |
16564 | {"sx", PSR_s | PSR_x}, | |
16565 | {"sc", PSR_s | PSR_c}, | |
16566 | {"xf", PSR_x | PSR_f}, | |
16567 | {"xs", PSR_x | PSR_s}, | |
16568 | {"xc", PSR_x | PSR_c}, | |
16569 | {"cf", PSR_c | PSR_f}, | |
16570 | {"cs", PSR_c | PSR_s}, | |
16571 | {"cx", PSR_c | PSR_x}, | |
16572 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
16573 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
16574 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
16575 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
16576 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
16577 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
16578 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
16579 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
16580 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
16581 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
16582 | {"scf", PSR_s | PSR_c | PSR_f}, | |
16583 | {"scx", PSR_s | PSR_c | PSR_x}, | |
16584 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
16585 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
16586 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
16587 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
16588 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
16589 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
16590 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
16591 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
16592 | {"csf", PSR_c | PSR_s | PSR_f}, | |
16593 | {"csx", PSR_c | PSR_s | PSR_x}, | |
16594 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
16595 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
16596 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
16597 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
16598 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
16599 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
16600 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
16601 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
16602 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
16603 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
16604 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
16605 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
16606 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
16607 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
16608 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
16609 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
16610 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
16611 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
16612 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
16613 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
16614 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
16615 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
16616 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
16617 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
16618 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
16619 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
16620 | }; | |
16621 | ||
62b3e311 PB |
16622 | /* Table of V7M psr names. */ |
16623 | static const struct asm_psr v7m_psrs[] = | |
16624 | { | |
2b744c99 PB |
16625 | {"apsr", 0 }, {"APSR", 0 }, |
16626 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
16627 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
16628 | {"psr", 3 }, {"PSR", 3 }, | |
16629 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
16630 | {"ipsr", 5 }, {"IPSR", 5 }, | |
16631 | {"epsr", 6 }, {"EPSR", 6 }, | |
16632 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
16633 | {"msp", 8 }, {"MSP", 8 }, | |
16634 | {"psp", 9 }, {"PSP", 9 }, | |
16635 | {"primask", 16}, {"PRIMASK", 16}, | |
16636 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
16637 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
16638 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
16639 | {"faultmask", 19}, {"FAULTMASK", 19}, |
16640 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
16641 | }; |
16642 | ||
c19d1205 ZW |
16643 | /* Table of all shift-in-operand names. */ |
16644 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 16645 | { |
c19d1205 ZW |
16646 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
16647 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
16648 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
16649 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
16650 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
16651 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
16652 | }; | |
b99bd4ef | 16653 | |
c19d1205 ZW |
16654 | /* Table of all explicit relocation names. */ |
16655 | #ifdef OBJ_ELF | |
16656 | static struct reloc_entry reloc_names[] = | |
16657 | { | |
16658 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
16659 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
16660 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
16661 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
16662 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
16663 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
16664 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
16665 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
16666 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
16667 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 16668 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
16669 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
16670 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
16671 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, | |
16672 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, | |
16673 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, | |
16674 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, | |
16675 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} | |
c19d1205 ZW |
16676 | }; |
16677 | #endif | |
b99bd4ef | 16678 | |
c19d1205 ZW |
16679 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
16680 | static const struct asm_cond conds[] = | |
16681 | { | |
16682 | {"eq", 0x0}, | |
16683 | {"ne", 0x1}, | |
16684 | {"cs", 0x2}, {"hs", 0x2}, | |
16685 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
16686 | {"mi", 0x4}, | |
16687 | {"pl", 0x5}, | |
16688 | {"vs", 0x6}, | |
16689 | {"vc", 0x7}, | |
16690 | {"hi", 0x8}, | |
16691 | {"ls", 0x9}, | |
16692 | {"ge", 0xa}, | |
16693 | {"lt", 0xb}, | |
16694 | {"gt", 0xc}, | |
16695 | {"le", 0xd}, | |
16696 | {"al", 0xe} | |
16697 | }; | |
bfae80f2 | 16698 | |
62b3e311 PB |
16699 | static struct asm_barrier_opt barrier_opt_names[] = |
16700 | { | |
52e7f43d RE |
16701 | { "sy", 0xf }, { "SY", 0xf }, |
16702 | { "un", 0x7 }, { "UN", 0x7 }, | |
16703 | { "st", 0xe }, { "ST", 0xe }, | |
16704 | { "unst", 0x6 }, { "UNST", 0x6 }, | |
16705 | { "ish", 0xb }, { "ISH", 0xb }, | |
16706 | { "sh", 0xb }, { "SH", 0xb }, | |
16707 | { "ishst", 0xa }, { "ISHST", 0xa }, | |
16708 | { "shst", 0xa }, { "SHST", 0xa }, | |
16709 | { "nsh", 0x7 }, { "NSH", 0x7 }, | |
16710 | { "nshst", 0x6 }, { "NSHST", 0x6 }, | |
16711 | { "osh", 0x3 }, { "OSH", 0x3 }, | |
16712 | { "oshst", 0x2 }, { "OSHST", 0x2 } | |
62b3e311 PB |
16713 | }; |
16714 | ||
c19d1205 ZW |
16715 | /* Table of ARM-format instructions. */ |
16716 | ||
16717 | /* Macros for gluing together operand strings. N.B. In all cases | |
16718 | other than OPS0, the trailing OP_stop comes from default | |
16719 | zero-initialization of the unspecified elements of the array. */ | |
16720 | #define OPS0() { OP_stop, } | |
16721 | #define OPS1(a) { OP_##a, } | |
16722 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
16723 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
16724 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
16725 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
16726 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
16727 | ||
5be8be5d DG |
16728 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
16729 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
16730 | MIX_ARM_THUMB_OPERANDS macro. | |
16731 | In order to use these macros, prefix the number of operands with _ | |
16732 | e.g. _3. */ | |
16733 | #define OPS_1(a) { a, } | |
16734 | #define OPS_2(a,b) { a,b, } | |
16735 | #define OPS_3(a,b,c) { a,b,c, } | |
16736 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
16737 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
16738 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
16739 | ||
c19d1205 ZW |
16740 | /* These macros abstract out the exact format of the mnemonic table and |
16741 | save some repeated characters. */ | |
16742 | ||
16743 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
16744 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16745 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16746 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16747 | |
16748 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
16749 | a T_MNEM_xyz enumerator. */ | |
16750 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 16751 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16752 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16753 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16754 | |
16755 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
16756 | infix after the third character. */ | |
16757 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16758 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16759 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 16760 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16761 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 16762 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 16763 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16764 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 16765 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16766 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16767 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16768 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 16769 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16770 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16771 | |
16772 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
16773 | appear in the condition table. */ | |
16774 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16775 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 16776 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16777 | |
16778 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16779 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
16780 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
16781 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
16782 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
16783 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
16784 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
16785 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
16786 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
16787 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
16788 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
16789 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
16790 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
16791 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
16792 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
16793 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
16794 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
16795 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
16796 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
16797 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
16798 | |
16799 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16800 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
16801 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 16802 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16803 | |
16804 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
16805 | field is still 0xE. Many of the Thumb variants can be executed |
16806 | conditionally, so this is checked separately. */ | |
c19d1205 | 16807 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16808 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16809 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16810 | |
16811 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
16812 | condition code field. */ | |
16813 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16814 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16815 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16816 | |
16817 | /* ARM-only variants of all the above. */ | |
6a86118a | 16818 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 16819 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
16820 | |
16821 | #define C3(mnem, op, nops, ops, ae) \ | |
16822 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
16823 | ||
e3cb604e PB |
16824 | /* Legacy mnemonics that always have conditional infix after the third |
16825 | character. */ | |
16826 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16827 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16828 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16829 | ||
8f06b2d8 PB |
16830 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
16831 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16832 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16833 | |
e3cb604e PB |
16834 | /* Legacy coprocessor instructions where conditional infix and conditional |
16835 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
16836 | not just the potentially ambiguous ones. */ | |
16837 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16838 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16839 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
16840 | ||
16841 | /* Coprocessor, takes either a suffix or a position-3 infix | |
16842 | (for an FPA corner case). */ | |
16843 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16844 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 16845 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16846 | |
6a86118a | 16847 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
16848 | { m1 #m2 m3, OPS##nops ops, \ |
16849 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
16850 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16851 | ||
16852 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
16853 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
16854 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
16855 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
16856 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
16857 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
16858 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
16859 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
16860 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
16861 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
16862 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
16863 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
16864 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
16865 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
16866 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
16867 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
16868 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
16869 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
16870 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
16871 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
16872 | |
16873 | #define UE(mnem, op, nops, ops, ae) \ | |
16874 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16875 | ||
16876 | #define UF(mnem, op, nops, ops, ae) \ | |
16877 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16878 | ||
5287ad62 JB |
16879 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
16880 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
16881 | use the same encoding function for each. */ | |
16882 | #define NUF(mnem, op, nops, ops, enc) \ | |
16883 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
16884 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
16885 | ||
16886 | /* Neon data processing, version which indirects through neon_enc_tab for | |
16887 | the various overloaded versions of opcodes. */ | |
16888 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 16889 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16890 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16891 | ||
16892 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
16893 | version. */ | |
037e8744 JB |
16894 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
16895 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
16896 | THUMB_VARIANT, do_##enc, do_##enc } |
16897 | ||
037e8744 | 16898 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16899 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16900 | |
16901 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16902 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16903 | |
5287ad62 | 16904 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 16905 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 16906 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16907 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16908 | ||
037e8744 | 16909 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16910 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16911 | |
16912 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 16913 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 16914 | |
c19d1205 ZW |
16915 | #define do_0 0 |
16916 | ||
c19d1205 | 16917 | static const struct asm_opcode insns[] = |
bfae80f2 | 16918 | { |
e74cfd16 PB |
16919 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
16920 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
16921 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
16922 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
16923 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
16924 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
16925 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
16926 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
16927 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16928 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
16929 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
16930 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16931 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
16932 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
16933 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
16934 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
16935 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
16936 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
16937 | |
16938 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
16939 | for setting PSR flag bits. They are obsolete in V6 and do not | |
16940 | have Thumb equivalents. */ | |
21d799b5 NC |
16941 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
16942 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
16943 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
16944 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16945 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
16946 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
16947 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16948 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
16949 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
16950 | ||
16951 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
16952 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
16953 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
16954 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
16955 | ||
16956 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
16957 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
16958 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
16959 | OP_RRnpc), | |
16960 | OP_ADDRGLDR),ldst, t_ldst), | |
16961 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
16962 | |
16963 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16964 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16965 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16966 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16967 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16968 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
16969 | ||
16970 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
16971 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
16972 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
16973 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 16974 | |
c19d1205 | 16975 | /* Pseudo ops. */ |
21d799b5 | 16976 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 16977 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 16978 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
16979 | |
16980 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
16981 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
16982 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
16983 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
16984 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
16985 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
16986 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
16987 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
16988 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
16989 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
16990 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
16991 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
16992 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 16993 | |
16a4cf17 | 16994 | /* These may simplify to neg. */ |
21d799b5 NC |
16995 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
16996 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 16997 | |
c921be7d NC |
16998 | #undef THUMB_VARIANT |
16999 | #define THUMB_VARIANT & arm_ext_v6 | |
17000 | ||
21d799b5 | 17001 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
17002 | |
17003 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
17004 | #undef THUMB_VARIANT |
17005 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17006 | ||
21d799b5 NC |
17007 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
17008 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
17009 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 17010 | |
5be8be5d DG |
17011 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
17012 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
17013 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
17014 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 17015 | |
21d799b5 NC |
17016 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17017 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 17018 | |
21d799b5 NC |
17019 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17020 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
17021 | |
17022 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 17023 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
17024 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
17025 | ||
17026 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
17027 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
17028 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
17029 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
17030 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
17031 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
17032 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
17033 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
17034 | ||
c921be7d NC |
17035 | #undef ARM_VARIANT |
17036 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
17037 | #undef THUMB_VARIANT | |
17038 | #define THUMB_VARIANT & arm_ext_v4t | |
17039 | ||
21d799b5 NC |
17040 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
17041 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 17042 | |
c921be7d NC |
17043 | #undef THUMB_VARIANT |
17044 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17045 | ||
21d799b5 | 17046 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
17047 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
17048 | ||
17049 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
17050 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
17051 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17052 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17053 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17054 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17055 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 17056 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 17057 | |
c921be7d NC |
17058 | #undef ARM_VARIANT |
17059 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
17060 | ||
21d799b5 | 17061 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
17062 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
17063 | ||
c921be7d NC |
17064 | #undef ARM_VARIANT |
17065 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
17066 | #undef THUMB_VARIANT | |
17067 | #define THUMB_VARIANT & arm_ext_msr | |
17068 | ||
d2cd1205 JB |
17069 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
17070 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 17071 | |
c921be7d NC |
17072 | #undef ARM_VARIANT |
17073 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
17074 | #undef THUMB_VARIANT | |
17075 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17076 | ||
21d799b5 NC |
17077 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
17078 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17079 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17080 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17081 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17082 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17083 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17084 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 17085 | |
c921be7d NC |
17086 | #undef ARM_VARIANT |
17087 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
17088 | #undef THUMB_VARIANT | |
17089 | #define THUMB_VARIANT & arm_ext_v4t | |
17090 | ||
5be8be5d DG |
17091 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
17092 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17093 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17094 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17095 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17096 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 17097 | |
c921be7d NC |
17098 | #undef ARM_VARIANT |
17099 | #define ARM_VARIANT & arm_ext_v4t_5 | |
17100 | ||
c19d1205 ZW |
17101 | /* ARM Architecture 4T. */ |
17102 | /* Note: bx (and blx) are required on V5, even if the processor does | |
17103 | not support Thumb. */ | |
21d799b5 | 17104 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 17105 | |
c921be7d NC |
17106 | #undef ARM_VARIANT |
17107 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
17108 | #undef THUMB_VARIANT | |
17109 | #define THUMB_VARIANT & arm_ext_v5t | |
17110 | ||
c19d1205 ZW |
17111 | /* Note: blx has 2 variants; the .value coded here is for |
17112 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
17113 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
17114 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 17115 | |
c921be7d NC |
17116 | #undef THUMB_VARIANT |
17117 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17118 | ||
21d799b5 NC |
17119 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
17120 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17121 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17122 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17123 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17124 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
17125 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
17126 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 17127 | |
c921be7d NC |
17128 | #undef ARM_VARIANT |
17129 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
17130 | #undef THUMB_VARIANT |
17131 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 17132 | |
21d799b5 NC |
17133 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17134 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17135 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17136 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17137 | |
21d799b5 NC |
17138 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17139 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17140 | |
21d799b5 NC |
17141 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
17142 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17143 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17144 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 17145 | |
21d799b5 NC |
17146 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17147 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17148 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17149 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17150 | |
21d799b5 NC |
17151 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17152 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17153 | |
03ee1b7f NC |
17154 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
17155 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17156 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17157 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 17158 | |
c921be7d NC |
17159 | #undef ARM_VARIANT |
17160 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
17161 | #undef THUMB_VARIANT |
17162 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 17163 | |
21d799b5 | 17164 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
17165 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
17166 | ldrd, t_ldstd), | |
17167 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
17168 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 17169 | |
21d799b5 NC |
17170 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17171 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 17172 | |
c921be7d NC |
17173 | #undef ARM_VARIANT |
17174 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
17175 | ||
21d799b5 | 17176 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 17177 | |
c921be7d NC |
17178 | #undef ARM_VARIANT |
17179 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
17180 | #undef THUMB_VARIANT | |
17181 | #define THUMB_VARIANT & arm_ext_v6 | |
17182 | ||
21d799b5 NC |
17183 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
17184 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
17185 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17186 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17187 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17188 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17189 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17190 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17191 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17192 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 17193 | |
c921be7d NC |
17194 | #undef THUMB_VARIANT |
17195 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17196 | ||
5be8be5d DG |
17197 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
17198 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17199 | strex, t_strex), | |
21d799b5 NC |
17200 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17201 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 17202 | |
21d799b5 NC |
17203 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
17204 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 17205 | |
9e3c6df6 | 17206 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
17207 | #undef THUMB_VARIANT |
17208 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
17209 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
17210 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
17211 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
17212 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17213 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
17214 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
17215 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
17216 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17217 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
17218 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
17219 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
17220 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 17221 | |
9e3c6df6 PB |
17222 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
17223 | #undef THUMB_VARIANT | |
17224 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
17225 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
17226 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
17227 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
17228 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17229 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17230 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17231 | /* Old name for QASX. */ |
21d799b5 NC |
17232 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17233 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17234 | /* Old name for QSAX. */ |
21d799b5 NC |
17235 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17236 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17237 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17238 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17239 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17240 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17241 | /* Old name for SASX. */ |
21d799b5 NC |
17242 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17243 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17244 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17245 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17246 | /* Old name for SHASX. */ |
21d799b5 NC |
17247 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17248 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17249 | /* Old name for SHSAX. */ |
21d799b5 NC |
17250 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17251 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17252 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17253 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17254 | /* Old name for SSAX. */ |
21d799b5 NC |
17255 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17256 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17257 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17258 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17259 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17260 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17261 | /* Old name for UASX. */ |
21d799b5 NC |
17262 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17263 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17264 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17265 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17266 | /* Old name for UHASX. */ |
21d799b5 NC |
17267 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17268 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17269 | /* Old name for UHSAX. */ |
21d799b5 NC |
17270 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17271 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17272 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17273 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17274 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17275 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17276 | /* Old name for UQASX. */ |
21d799b5 NC |
17277 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17278 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17279 | /* Old name for UQSAX. */ |
21d799b5 NC |
17280 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17281 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17282 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17283 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17284 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17285 | /* Old name for USAX. */ |
21d799b5 NC |
17286 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17287 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
17288 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
17289 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17290 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17291 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17292 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17293 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17294 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17295 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17296 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17297 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17298 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17299 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17300 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17301 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17302 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17303 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17304 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17305 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17306 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17307 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17308 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17309 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17310 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17311 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17312 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17313 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17314 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
17315 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
17316 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
17317 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17318 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17319 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 17320 | |
c921be7d NC |
17321 | #undef ARM_VARIANT |
17322 | #define ARM_VARIANT & arm_ext_v6k | |
17323 | #undef THUMB_VARIANT | |
17324 | #define THUMB_VARIANT & arm_ext_v6k | |
17325 | ||
21d799b5 NC |
17326 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
17327 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
17328 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
17329 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 17330 | |
c921be7d NC |
17331 | #undef THUMB_VARIANT |
17332 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
17333 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
17334 | ldrexd, t_ldrexd), | |
17335 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
17336 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 17337 | |
c921be7d NC |
17338 | #undef THUMB_VARIANT |
17339 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
17340 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
17341 | rd_rn, rd_rn), | |
17342 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
17343 | rd_rn, rd_rn), | |
17344 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17345 | strex, rm_rd_rn), | |
17346 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17347 | strex, rm_rd_rn), | |
21d799b5 | 17348 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 17349 | |
c921be7d | 17350 | #undef ARM_VARIANT |
f4c65163 MGD |
17351 | #define ARM_VARIANT & arm_ext_sec |
17352 | #undef THUMB_VARIANT | |
17353 | #define THUMB_VARIANT & arm_ext_sec | |
c921be7d | 17354 | |
21d799b5 | 17355 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 17356 | |
90ec0d68 MGD |
17357 | #undef ARM_VARIANT |
17358 | #define ARM_VARIANT & arm_ext_virt | |
17359 | #undef THUMB_VARIANT | |
17360 | #define THUMB_VARIANT & arm_ext_virt | |
17361 | ||
17362 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
17363 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
17364 | ||
c921be7d NC |
17365 | #undef ARM_VARIANT |
17366 | #define ARM_VARIANT & arm_ext_v6t2 | |
f4c65163 MGD |
17367 | #undef THUMB_VARIANT |
17368 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 17369 | |
21d799b5 NC |
17370 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
17371 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
17372 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
17373 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 17374 | |
21d799b5 NC |
17375 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
17376 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17377 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17378 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 17379 | |
5be8be5d DG |
17380 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
17381 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17382 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17383 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 17384 | |
bf3eeda7 NS |
17385 | /* Thumb-only instructions. */ |
17386 | #undef ARM_VARIANT | |
17387 | #define ARM_VARIANT NULL | |
17388 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
17389 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
17390 | |
17391 | /* ARM does not really have an IT instruction, so always allow it. | |
17392 | The opcode is copied from Thumb in order to allow warnings in | |
17393 | -mimplicit-it=[never | arm] modes. */ | |
17394 | #undef ARM_VARIANT | |
17395 | #define ARM_VARIANT & arm_ext_v1 | |
17396 | ||
21d799b5 NC |
17397 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
17398 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
17399 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
17400 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
17401 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
17402 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
17403 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
17404 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
17405 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
17406 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
17407 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
17408 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
17409 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
17410 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
17411 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 17412 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
17413 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
17414 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 17415 | |
92e90b6e | 17416 | /* Thumb2 only instructions. */ |
c921be7d NC |
17417 | #undef ARM_VARIANT |
17418 | #define ARM_VARIANT NULL | |
92e90b6e | 17419 | |
21d799b5 NC |
17420 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
17421 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
17422 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
17423 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
17424 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
17425 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 17426 | |
eea54501 MGD |
17427 | /* Hardware division instructions. */ |
17428 | #undef ARM_VARIANT | |
17429 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
17430 | #undef THUMB_VARIANT |
17431 | #define THUMB_VARIANT & arm_ext_div | |
17432 | ||
eea54501 MGD |
17433 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
17434 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 17435 | |
7e806470 | 17436 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17437 | #undef ARM_VARIANT |
17438 | #define ARM_VARIANT & arm_ext_barrier | |
17439 | #undef THUMB_VARIANT | |
17440 | #define THUMB_VARIANT & arm_ext_barrier | |
17441 | ||
52e7f43d RE |
17442 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), |
17443 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), | |
17444 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), | |
7e806470 | 17445 | |
62b3e311 | 17446 | /* ARM V7 instructions. */ |
c921be7d NC |
17447 | #undef ARM_VARIANT |
17448 | #define ARM_VARIANT & arm_ext_v7 | |
17449 | #undef THUMB_VARIANT | |
17450 | #define THUMB_VARIANT & arm_ext_v7 | |
17451 | ||
21d799b5 NC |
17452 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17453 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17454 | |
60e5ef9f MGD |
17455 | #undef ARM_VARIANT |
17456 | #define ARM_VARIANT & arm_ext_mp | |
17457 | #undef THUMB_VARIANT | |
17458 | #define THUMB_VARIANT & arm_ext_mp | |
17459 | ||
17460 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
17461 | ||
c921be7d NC |
17462 | #undef ARM_VARIANT |
17463 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
17464 | ||
21d799b5 NC |
17465 | cCE("wfs", e200110, 1, (RR), rd), |
17466 | cCE("rfs", e300110, 1, (RR), rd), | |
17467 | cCE("wfc", e400110, 1, (RR), rd), | |
17468 | cCE("rfc", e500110, 1, (RR), rd), | |
17469 | ||
17470 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17471 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17472 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17473 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17474 | ||
17475 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17476 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17477 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17478 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17479 | ||
17480 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
17481 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
17482 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
17483 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
17484 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
17485 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
17486 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
17487 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
17488 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
17489 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
17490 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
17491 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
17492 | ||
17493 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
17494 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
17495 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17496 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17497 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17498 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17499 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17500 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17501 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17502 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17503 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17504 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17505 | ||
17506 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17507 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17508 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17509 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17510 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17511 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17512 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17513 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17514 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17515 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17516 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17517 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17518 | ||
17519 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17520 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17521 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17522 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17523 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17524 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17525 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17526 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17527 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17528 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17529 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17530 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17531 | ||
17532 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17533 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
17534 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
17535 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
17536 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
17537 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
17538 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
17539 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
17540 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
17541 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
17542 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
17543 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
17544 | ||
17545 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
17546 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
17547 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
17548 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
17549 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
17550 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
17551 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
17552 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
17553 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
17554 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
17555 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
17556 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
17557 | ||
17558 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
17559 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
17560 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
17561 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
17562 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
17563 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
17564 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
17565 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
17566 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
17567 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
17568 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
17569 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
17570 | ||
17571 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
17572 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
17573 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
17574 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
17575 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
17576 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
17577 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
17578 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
17579 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
17580 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
17581 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
17582 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
17583 | ||
17584 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
17585 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
17586 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
17587 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
17588 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
17589 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
17590 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
17591 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
17592 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
17593 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
17594 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
17595 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
17596 | ||
17597 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
17598 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
17599 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
17600 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
17601 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
17602 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
17603 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
17604 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
17605 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
17606 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
17607 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
17608 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
17609 | ||
17610 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
17611 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
17612 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
17613 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
17614 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
17615 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
17616 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
17617 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
17618 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
17619 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
17620 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
17621 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
17622 | ||
17623 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
17624 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
17625 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
17626 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
17627 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
17628 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
17629 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
17630 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
17631 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
17632 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
17633 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
17634 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
17635 | ||
17636 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
17637 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
17638 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
17639 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
17640 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
17641 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
17642 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
17643 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
17644 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
17645 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
17646 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
17647 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
17648 | ||
17649 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
17650 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
17651 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
17652 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
17653 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
17654 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
17655 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
17656 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
17657 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
17658 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
17659 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
17660 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
17661 | ||
17662 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
17663 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
17664 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
17665 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
17666 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
17667 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
17668 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
17669 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
17670 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
17671 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
17672 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
17673 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
17674 | ||
17675 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
17676 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
17677 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
17678 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
17679 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
17680 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
17681 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
17682 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
17683 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
17684 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
17685 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
17686 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
17687 | ||
17688 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17689 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17690 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17691 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17692 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17693 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17694 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17695 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17696 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17697 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17698 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17699 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17700 | ||
17701 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17702 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17703 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17704 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17705 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17706 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17707 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17708 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17709 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17710 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17711 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17712 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17713 | ||
17714 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17715 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17716 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17717 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17718 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17719 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17720 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17721 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17722 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17723 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17724 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17725 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17726 | ||
17727 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17728 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17729 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17730 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17731 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17732 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17733 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17734 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17735 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17736 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17737 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17738 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17739 | ||
17740 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17741 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17742 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17743 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17744 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17745 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17746 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17747 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17748 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17749 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17750 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17751 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17752 | ||
17753 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17754 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17755 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17756 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17757 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17758 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17759 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17760 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17761 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17762 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17763 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17764 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17765 | ||
17766 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17767 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17768 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17769 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17770 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17771 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17772 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17773 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17774 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17775 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17776 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17777 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17778 | ||
17779 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17780 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17781 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17782 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17783 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17784 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17785 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17786 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17787 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17788 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17789 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17790 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17791 | ||
17792 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17793 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17794 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17795 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17796 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17797 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17798 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17799 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17800 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17801 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17802 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17803 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17804 | ||
17805 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17806 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17807 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17808 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17809 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17810 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17811 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17812 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17813 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17814 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17815 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17816 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17817 | ||
17818 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17819 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17820 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17821 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17822 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17823 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17824 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17825 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17826 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17827 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17828 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17829 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17830 | ||
17831 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17832 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17833 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17834 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17835 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17836 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17837 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17838 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17839 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17840 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17841 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17842 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17843 | ||
17844 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17845 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17846 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17847 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17848 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17849 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17850 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17851 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17852 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17853 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17854 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17855 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17856 | ||
17857 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
17858 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
17859 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
17860 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
17861 | ||
17862 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
17863 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
17864 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
17865 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
17866 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
17867 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
17868 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
17869 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
17870 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
17871 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
17872 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
17873 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 17874 | |
c19d1205 ZW |
17875 | /* The implementation of the FIX instruction is broken on some |
17876 | assemblers, in that it accepts a precision specifier as well as a | |
17877 | rounding specifier, despite the fact that this is meaningless. | |
17878 | To be more compatible, we accept it as well, though of course it | |
17879 | does not set any bits. */ | |
21d799b5 NC |
17880 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
17881 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
17882 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
17883 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
17884 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
17885 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
17886 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
17887 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
17888 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
17889 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
17890 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
17891 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
17892 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 17893 | |
c19d1205 | 17894 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
17895 | #undef ARM_VARIANT |
17896 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
17897 | ||
21d799b5 NC |
17898 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
17899 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17900 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17901 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17902 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17903 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 17904 | |
c921be7d NC |
17905 | #undef ARM_VARIANT |
17906 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
17907 | ||
c19d1205 | 17908 | /* Moves and type conversions. */ |
21d799b5 NC |
17909 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
17910 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
17911 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
17912 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
f7c21dc7 NC |
17913 | cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), |
17914 | cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
17915 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17916 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17917 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17918 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17919 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17920 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17921 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
17922 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
17923 | |
17924 | /* Memory operations. */ | |
21d799b5 NC |
17925 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
17926 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
17927 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
17928 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17929 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17930 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17931 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17932 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17933 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17934 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17935 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17936 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
17937 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17938 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
17939 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17940 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
17941 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
17942 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 17943 | |
c19d1205 | 17944 | /* Monadic operations. */ |
21d799b5 NC |
17945 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
17946 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
17947 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
17948 | |
17949 | /* Dyadic operations. */ | |
21d799b5 NC |
17950 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
17951 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17952 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17953 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17954 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17955 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17956 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17957 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
17958 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 17959 | |
c19d1205 | 17960 | /* Comparisons. */ |
21d799b5 NC |
17961 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
17962 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
17963 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
17964 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 17965 | |
62f3b8c8 PB |
17966 | /* Double precision load/store are still present on single precision |
17967 | implementations. */ | |
17968 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
17969 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
17970 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
17971 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17972 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17973 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17974 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17975 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
17976 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
17977 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 17978 | |
c921be7d NC |
17979 | #undef ARM_VARIANT |
17980 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
17981 | ||
c19d1205 | 17982 | /* Moves and type conversions. */ |
21d799b5 NC |
17983 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
17984 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17985 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17986 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17987 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
17988 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17989 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
17990 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17991 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
17992 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17993 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17994 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
17995 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 17996 | |
c19d1205 | 17997 | /* Monadic operations. */ |
21d799b5 NC |
17998 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
17999 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18000 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
18001 | |
18002 | /* Dyadic operations. */ | |
21d799b5 NC |
18003 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
18004 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18005 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18006 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18007 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18008 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18009 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18010 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18011 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 18012 | |
c19d1205 | 18013 | /* Comparisons. */ |
21d799b5 NC |
18014 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18015 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
18016 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18017 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 18018 | |
c921be7d NC |
18019 | #undef ARM_VARIANT |
18020 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
18021 | ||
21d799b5 NC |
18022 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
18023 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
18024 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
18025 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 18026 | |
037e8744 JB |
18027 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
18028 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
18029 | #undef ARM_VARIANT |
18030 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
18031 | #undef THUMB_VARIANT | |
18032 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
18033 | ||
037e8744 JB |
18034 | /* These mnemonics are unique to VFP. */ |
18035 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
18036 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
18037 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
18038 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18039 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18040 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
18041 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
18042 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
18043 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
18044 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
18045 | ||
18046 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
18047 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
18048 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
18049 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 18050 | |
21d799b5 NC |
18051 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
18052 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
18053 | |
18054 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18055 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18056 | ||
55881a11 MGD |
18057 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
18058 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18059 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18060 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18061 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18062 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
18063 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
18064 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 18065 | |
e3e535bc NC |
18066 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), |
18067 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), | |
21d799b5 NC |
18068 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
18069 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 18070 | |
037e8744 JB |
18071 | |
18072 | /* NOTE: All VMOV encoding is special-cased! */ | |
18073 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
18074 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
18075 | ||
c921be7d NC |
18076 | #undef THUMB_VARIANT |
18077 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
18078 | #undef ARM_VARIANT | |
18079 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
18080 | ||
5287ad62 JB |
18081 | /* Data processing with three registers of the same length. */ |
18082 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
18083 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
18084 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
18085 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18086 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18087 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18088 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18089 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18090 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18091 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18092 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18093 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
18094 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18095 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
18096 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
18097 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
18098 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
18099 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
18100 | /* If not immediate, fall back to neon_dyadic_i64_su. |
18101 | shl_imm should accept I8 I16 I32 I64, | |
18102 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
18103 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
18104 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
18105 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
18106 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 18107 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
18108 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
18109 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18110 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18111 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18112 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18113 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18114 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18115 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18116 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
18117 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
18118 | /* Bitfield ops, untyped. */ |
18119 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18120 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18121 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18122 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18123 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18124 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18125 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
18126 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
18127 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18128 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18129 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18130 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18131 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
18132 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
18133 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
18134 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
18135 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18136 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
18137 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18138 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18139 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
18140 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18141 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 18142 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
18143 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
18144 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 18145 | /* As above, D registers only. */ |
21d799b5 NC |
18146 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
18147 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 18148 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
18149 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
18150 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
18151 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 18152 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
18153 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
18154 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
18155 | /* vtst takes sizes 8, 16, 32. */ |
18156 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
18157 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
18158 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 18159 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 18160 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
18161 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
18162 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
18163 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
18164 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
18165 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
18166 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
18167 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
18168 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
18169 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
18170 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
18171 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
18172 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
18173 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
18174 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18175 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
18176 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18177 | ||
18178 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 18179 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
18180 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
18181 | ||
18182 | /* Data processing with two registers and a shift amount. */ | |
18183 | /* Right shifts, and variants with rounding. | |
18184 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18185 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18186 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18187 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18188 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18189 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18190 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18191 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18192 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18193 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
18194 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
18195 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
18196 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
18197 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
18198 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18199 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
18200 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
18201 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
18202 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
18203 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18204 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18205 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
18206 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18207 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18208 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
18209 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18210 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18211 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 18212 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 18213 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 18214 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 18215 | |
4316f0d2 DG |
18216 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
18217 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
18218 | |
18219 | /* Data processing, three registers of different lengths. */ | |
18220 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
18221 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
18222 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18223 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18224 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18225 | /* If not scalar, fall back to neon_dyadic_long. | |
18226 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
18227 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
18228 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
18229 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
18230 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18231 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18232 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
18233 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18234 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18235 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18236 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18237 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
18238 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
18239 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
18240 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
18241 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
18242 | S16 S32 U16 U32. */ | |
21d799b5 | 18243 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
18244 | |
18245 | /* Extract. Size 8. */ | |
3b8d421e PB |
18246 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
18247 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
18248 | |
18249 | /* Two registers, miscellaneous. */ | |
18250 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
18251 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
18252 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
18253 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
18254 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
18255 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
18256 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
18257 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
18258 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
18259 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
18260 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
18261 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
18262 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 18263 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 18264 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 18265 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 18266 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 18267 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
18268 | /* VZIP / VUZP. Sizes 8 16 32. */ |
18269 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18270 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
18271 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18272 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
18273 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
18274 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18275 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18276 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18277 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18278 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
18279 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
18280 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
18281 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
18282 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
18283 | /* Reciprocal estimates. Types U32 F32. */ | |
18284 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
18285 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
18286 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
18287 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
18288 | /* VCLS. Types S8 S16 S32. */ | |
18289 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
18290 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
18291 | /* VCLZ. Types I8 I16 I32. */ | |
18292 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
18293 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
18294 | /* VCNT. Size 8. */ | |
18295 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
18296 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
18297 | /* Two address, untyped. */ | |
18298 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
18299 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
18300 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
18301 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
18302 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
18303 | |
18304 | /* Table lookup. Size 8. */ | |
18305 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18306 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18307 | ||
c921be7d NC |
18308 | #undef THUMB_VARIANT |
18309 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
18310 | #undef ARM_VARIANT | |
18311 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
18312 | ||
5287ad62 | 18313 | /* Neon element/structure load/store. */ |
21d799b5 NC |
18314 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
18315 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18316 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18317 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18318 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18319 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18320 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18321 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 18322 | |
c921be7d | 18323 | #undef THUMB_VARIANT |
62f3b8c8 PB |
18324 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
18325 | #undef ARM_VARIANT | |
18326 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
18327 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
18328 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18329 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18330 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18331 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18332 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18333 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18334 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18335 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18336 | ||
18337 | #undef THUMB_VARIANT | |
c921be7d NC |
18338 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
18339 | #undef ARM_VARIANT | |
18340 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
18341 | ||
21d799b5 | 18342 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 18343 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18344 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18345 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18346 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18347 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18348 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18349 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18350 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 18351 | |
62f3b8c8 PB |
18352 | #undef ARM_VARIANT |
18353 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
18354 | #undef THUMB_VARIANT | |
18355 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
18356 | /* Mnemonics shared by Neon and VFP. These are included in the | |
18357 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
18358 | FMA instructions. */ | |
18359 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18360 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18361 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
18362 | the v form should always be used. */ | |
18363 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18364 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18365 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18366 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18367 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18368 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18369 | ||
5287ad62 | 18370 | #undef THUMB_VARIANT |
c921be7d NC |
18371 | #undef ARM_VARIANT |
18372 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
18373 | ||
21d799b5 NC |
18374 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
18375 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18376 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18377 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18378 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18379 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18380 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
18381 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 18382 | |
c921be7d NC |
18383 | #undef ARM_VARIANT |
18384 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
18385 | ||
21d799b5 NC |
18386 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
18387 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
18388 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
18389 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
18390 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
18391 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
18392 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
18393 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
18394 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
18395 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18396 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18397 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18398 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18399 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18400 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18401 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18402 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18403 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18404 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
18405 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
18406 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18407 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18408 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18409 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18410 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18411 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18412 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
18413 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
18414 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
18415 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
18416 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
18417 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
18418 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
18419 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
18420 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
18421 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
18422 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
18423 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18424 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18425 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18426 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18427 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18428 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18429 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18430 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18431 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18432 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
18433 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18434 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18435 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18436 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18437 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18438 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18439 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18440 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18441 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18442 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18443 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18444 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18445 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18446 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18447 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18448 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18449 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18450 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18451 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18452 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18453 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18454 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18455 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18456 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18457 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18458 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18459 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18460 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18461 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18462 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18463 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18464 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18465 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18466 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18467 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18468 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18469 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18470 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18471 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18472 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18473 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18474 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
18475 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18476 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18477 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18478 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18479 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18480 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18481 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18482 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18483 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18484 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18485 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18486 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18487 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18488 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18489 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18490 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18491 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18492 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18493 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18494 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18495 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18496 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18497 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18498 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18499 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18500 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18501 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18502 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18503 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18504 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18505 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18506 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18507 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18508 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18509 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18510 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18511 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18512 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18513 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18514 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18515 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18516 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18517 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18518 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18519 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18520 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18521 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18522 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18523 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18524 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18525 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18526 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18527 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18528 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18529 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18530 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18531 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18532 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18533 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
18534 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18535 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18536 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18537 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
18538 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
18539 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
18540 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
18541 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
18542 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
18543 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18544 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18545 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18546 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18547 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 18548 | |
c921be7d NC |
18549 | #undef ARM_VARIANT |
18550 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
18551 | ||
21d799b5 NC |
18552 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
18553 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
18554 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
18555 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
18556 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
18557 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
18558 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18559 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18560 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18561 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18562 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18563 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18564 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18565 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18566 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18567 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18568 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18569 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18570 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18571 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18572 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
18573 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18574 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18575 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18576 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18577 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18578 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18579 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18580 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18581 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18582 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18583 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18584 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18585 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18586 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18587 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18588 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18589 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18590 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18591 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18592 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18593 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18594 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18595 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18596 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18597 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18598 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18599 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18600 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18601 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18602 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18603 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18604 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18605 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18606 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18607 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18608 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 18609 | |
c921be7d NC |
18610 | #undef ARM_VARIANT |
18611 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
18612 | ||
21d799b5 NC |
18613 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
18614 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18615 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18616 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18617 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
18618 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18619 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18620 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18621 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
18622 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
18623 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
18624 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
18625 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
18626 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
18627 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
18628 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
18629 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
18630 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
18631 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
18632 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
18633 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
18634 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
18635 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
18636 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
18637 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
18638 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
18639 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
18640 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
18641 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
18642 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
18643 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
18644 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
18645 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
18646 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
18647 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
18648 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
18649 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
18650 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
18651 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
18652 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
18653 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
18654 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
18655 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
18656 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
18657 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
18658 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
18659 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
18660 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
18661 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
18662 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
18663 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
18664 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
18665 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
18666 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
18667 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18668 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18669 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18670 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18671 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18672 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18673 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
18674 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
18675 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
18676 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
18677 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18678 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18679 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18680 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18681 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18682 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18683 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18684 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18685 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18686 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18687 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
18688 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
18689 | }; |
18690 | #undef ARM_VARIANT | |
18691 | #undef THUMB_VARIANT | |
18692 | #undef TCE | |
18693 | #undef TCM | |
18694 | #undef TUE | |
18695 | #undef TUF | |
18696 | #undef TCC | |
8f06b2d8 | 18697 | #undef cCE |
e3cb604e PB |
18698 | #undef cCL |
18699 | #undef C3E | |
c19d1205 ZW |
18700 | #undef CE |
18701 | #undef CM | |
18702 | #undef UE | |
18703 | #undef UF | |
18704 | #undef UT | |
5287ad62 JB |
18705 | #undef NUF |
18706 | #undef nUF | |
18707 | #undef NCE | |
18708 | #undef nCE | |
c19d1205 ZW |
18709 | #undef OPS0 |
18710 | #undef OPS1 | |
18711 | #undef OPS2 | |
18712 | #undef OPS3 | |
18713 | #undef OPS4 | |
18714 | #undef OPS5 | |
18715 | #undef OPS6 | |
18716 | #undef do_0 | |
18717 | \f | |
18718 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 18719 | |
c19d1205 ZW |
18720 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
18721 | for use in the a.out file, and stores them in the array pointed to by buf. | |
18722 | This knows about the endian-ness of the target machine and does | |
18723 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
18724 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
18725 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 18726 | |
c19d1205 ZW |
18727 | void |
18728 | md_number_to_chars (char * buf, valueT val, int n) | |
18729 | { | |
18730 | if (target_big_endian) | |
18731 | number_to_chars_bigendian (buf, val, n); | |
18732 | else | |
18733 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
18734 | } |
18735 | ||
c19d1205 ZW |
18736 | static valueT |
18737 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 18738 | { |
c19d1205 ZW |
18739 | valueT result = 0; |
18740 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 18741 | |
c19d1205 | 18742 | if (target_big_endian) |
b99bd4ef | 18743 | { |
c19d1205 ZW |
18744 | while (n--) |
18745 | { | |
18746 | result <<= 8; | |
18747 | result |= (*where++ & 255); | |
18748 | } | |
b99bd4ef | 18749 | } |
c19d1205 | 18750 | else |
b99bd4ef | 18751 | { |
c19d1205 ZW |
18752 | while (n--) |
18753 | { | |
18754 | result <<= 8; | |
18755 | result |= (where[n] & 255); | |
18756 | } | |
bfae80f2 | 18757 | } |
b99bd4ef | 18758 | |
c19d1205 | 18759 | return result; |
bfae80f2 | 18760 | } |
b99bd4ef | 18761 | |
c19d1205 | 18762 | /* MD interface: Sections. */ |
b99bd4ef | 18763 | |
0110f2b8 PB |
18764 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
18765 | 2 bytes. */ | |
18766 | ||
c19d1205 | 18767 | int |
0110f2b8 | 18768 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
18769 | segT segtype ATTRIBUTE_UNUSED) |
18770 | { | |
0110f2b8 PB |
18771 | fragp->fr_var = 2; |
18772 | return 2; | |
18773 | } | |
18774 | ||
18775 | /* Convert a machine dependent frag. */ | |
18776 | ||
18777 | void | |
18778 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
18779 | { | |
18780 | unsigned long insn; | |
18781 | unsigned long old_op; | |
18782 | char *buf; | |
18783 | expressionS exp; | |
18784 | fixS *fixp; | |
18785 | int reloc_type; | |
18786 | int pc_rel; | |
18787 | int opcode; | |
18788 | ||
18789 | buf = fragp->fr_literal + fragp->fr_fix; | |
18790 | ||
18791 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
18792 | if (fragp->fr_symbol) |
18793 | { | |
0110f2b8 PB |
18794 | exp.X_op = O_symbol; |
18795 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
18796 | } |
18797 | else | |
18798 | { | |
0110f2b8 | 18799 | exp.X_op = O_constant; |
5f4273c7 | 18800 | } |
0110f2b8 PB |
18801 | exp.X_add_number = fragp->fr_offset; |
18802 | opcode = fragp->fr_subtype; | |
18803 | switch (opcode) | |
18804 | { | |
18805 | case T_MNEM_ldr_pc: | |
18806 | case T_MNEM_ldr_pc2: | |
18807 | case T_MNEM_ldr_sp: | |
18808 | case T_MNEM_str_sp: | |
18809 | case T_MNEM_ldr: | |
18810 | case T_MNEM_ldrb: | |
18811 | case T_MNEM_ldrh: | |
18812 | case T_MNEM_str: | |
18813 | case T_MNEM_strb: | |
18814 | case T_MNEM_strh: | |
18815 | if (fragp->fr_var == 4) | |
18816 | { | |
5f4273c7 | 18817 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
18818 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
18819 | { | |
18820 | insn |= (old_op & 0x700) << 4; | |
18821 | } | |
18822 | else | |
18823 | { | |
18824 | insn |= (old_op & 7) << 12; | |
18825 | insn |= (old_op & 0x38) << 13; | |
18826 | } | |
18827 | insn |= 0x00000c00; | |
18828 | put_thumb32_insn (buf, insn); | |
18829 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
18830 | } | |
18831 | else | |
18832 | { | |
18833 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
18834 | } | |
18835 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
18836 | break; | |
18837 | case T_MNEM_adr: | |
18838 | if (fragp->fr_var == 4) | |
18839 | { | |
18840 | insn = THUMB_OP32 (opcode); | |
18841 | insn |= (old_op & 0xf0) << 4; | |
18842 | put_thumb32_insn (buf, insn); | |
18843 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
18844 | } | |
18845 | else | |
18846 | { | |
18847 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18848 | exp.X_add_number -= 4; | |
18849 | } | |
18850 | pc_rel = 1; | |
18851 | break; | |
18852 | case T_MNEM_mov: | |
18853 | case T_MNEM_movs: | |
18854 | case T_MNEM_cmp: | |
18855 | case T_MNEM_cmn: | |
18856 | if (fragp->fr_var == 4) | |
18857 | { | |
18858 | int r0off = (opcode == T_MNEM_mov | |
18859 | || opcode == T_MNEM_movs) ? 0 : 8; | |
18860 | insn = THUMB_OP32 (opcode); | |
18861 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
18862 | insn |= (old_op & 0x700) << r0off; | |
18863 | put_thumb32_insn (buf, insn); | |
18864 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
18865 | } | |
18866 | else | |
18867 | { | |
18868 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
18869 | } | |
18870 | pc_rel = 0; | |
18871 | break; | |
18872 | case T_MNEM_b: | |
18873 | if (fragp->fr_var == 4) | |
18874 | { | |
18875 | insn = THUMB_OP32(opcode); | |
18876 | put_thumb32_insn (buf, insn); | |
18877 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
18878 | } | |
18879 | else | |
18880 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
18881 | pc_rel = 1; | |
18882 | break; | |
18883 | case T_MNEM_bcond: | |
18884 | if (fragp->fr_var == 4) | |
18885 | { | |
18886 | insn = THUMB_OP32(opcode); | |
18887 | insn |= (old_op & 0xf00) << 14; | |
18888 | put_thumb32_insn (buf, insn); | |
18889 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
18890 | } | |
18891 | else | |
18892 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
18893 | pc_rel = 1; | |
18894 | break; | |
18895 | case T_MNEM_add_sp: | |
18896 | case T_MNEM_add_pc: | |
18897 | case T_MNEM_inc_sp: | |
18898 | case T_MNEM_dec_sp: | |
18899 | if (fragp->fr_var == 4) | |
18900 | { | |
18901 | /* ??? Choose between add and addw. */ | |
18902 | insn = THUMB_OP32 (opcode); | |
18903 | insn |= (old_op & 0xf0) << 4; | |
18904 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18905 | if (opcode == T_MNEM_add_pc) |
18906 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
18907 | else | |
18908 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
18909 | } |
18910 | else | |
18911 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18912 | pc_rel = 0; | |
18913 | break; | |
18914 | ||
18915 | case T_MNEM_addi: | |
18916 | case T_MNEM_addis: | |
18917 | case T_MNEM_subi: | |
18918 | case T_MNEM_subis: | |
18919 | if (fragp->fr_var == 4) | |
18920 | { | |
18921 | insn = THUMB_OP32 (opcode); | |
18922 | insn |= (old_op & 0xf0) << 4; | |
18923 | insn |= (old_op & 0xf) << 16; | |
18924 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
18925 | if (insn & (1 << 20)) |
18926 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
18927 | else | |
18928 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
18929 | } |
18930 | else | |
18931 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18932 | pc_rel = 0; | |
18933 | break; | |
18934 | default: | |
5f4273c7 | 18935 | abort (); |
0110f2b8 PB |
18936 | } |
18937 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 18938 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
18939 | fixp->fx_file = fragp->fr_file; |
18940 | fixp->fx_line = fragp->fr_line; | |
18941 | fragp->fr_fix += fragp->fr_var; | |
18942 | } | |
18943 | ||
18944 | /* Return the size of a relaxable immediate operand instruction. | |
18945 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
18946 | static int | |
18947 | relax_immediate (fragS *fragp, int size, int shift) | |
18948 | { | |
18949 | offsetT offset; | |
18950 | offsetT mask; | |
18951 | offsetT low; | |
18952 | ||
18953 | /* ??? Should be able to do better than this. */ | |
18954 | if (fragp->fr_symbol) | |
18955 | return 4; | |
18956 | ||
18957 | low = (1 << shift) - 1; | |
18958 | mask = (1 << (shift + size)) - (1 << shift); | |
18959 | offset = fragp->fr_offset; | |
18960 | /* Force misaligned offsets to 32-bit variant. */ | |
18961 | if (offset & low) | |
5e77afaa | 18962 | return 4; |
0110f2b8 PB |
18963 | if (offset & ~mask) |
18964 | return 4; | |
18965 | return 2; | |
18966 | } | |
18967 | ||
5e77afaa PB |
18968 | /* Get the address of a symbol during relaxation. */ |
18969 | static addressT | |
5f4273c7 | 18970 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
18971 | { |
18972 | fragS *sym_frag; | |
18973 | addressT addr; | |
18974 | symbolS *sym; | |
18975 | ||
18976 | sym = fragp->fr_symbol; | |
18977 | sym_frag = symbol_get_frag (sym); | |
18978 | know (S_GET_SEGMENT (sym) != absolute_section | |
18979 | || sym_frag == &zero_address_frag); | |
18980 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
18981 | ||
18982 | /* If frag has yet to be reached on this pass, assume it will | |
18983 | move by STRETCH just as we did. If this is not so, it will | |
18984 | be because some frag between grows, and that will force | |
18985 | another pass. */ | |
18986 | ||
18987 | if (stretch != 0 | |
18988 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
18989 | { |
18990 | fragS *f; | |
18991 | ||
18992 | /* Adjust stretch for any alignment frag. Note that if have | |
18993 | been expanding the earlier code, the symbol may be | |
18994 | defined in what appears to be an earlier frag. FIXME: | |
18995 | This doesn't handle the fr_subtype field, which specifies | |
18996 | a maximum number of bytes to skip when doing an | |
18997 | alignment. */ | |
18998 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
18999 | { | |
19000 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
19001 | { | |
19002 | if (stretch < 0) | |
19003 | stretch = - ((- stretch) | |
19004 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
19005 | else | |
19006 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
19007 | if (stretch == 0) | |
19008 | break; | |
19009 | } | |
19010 | } | |
19011 | if (f != NULL) | |
19012 | addr += stretch; | |
19013 | } | |
5e77afaa PB |
19014 | |
19015 | return addr; | |
19016 | } | |
19017 | ||
0110f2b8 PB |
19018 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
19019 | load. */ | |
19020 | static int | |
5e77afaa | 19021 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
19022 | { |
19023 | addressT addr; | |
19024 | offsetT val; | |
19025 | ||
19026 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
19027 | if (fragp->fr_symbol == NULL |
19028 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
19029 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19030 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19031 | return 4; |
19032 | ||
5f4273c7 | 19033 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19034 | addr = fragp->fr_address + fragp->fr_fix; |
19035 | addr = (addr + 4) & ~3; | |
5e77afaa | 19036 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 19037 | if (val & 3) |
5e77afaa | 19038 | return 4; |
0110f2b8 PB |
19039 | val -= addr; |
19040 | if (val < 0 || val > 1020) | |
19041 | return 4; | |
19042 | return 2; | |
19043 | } | |
19044 | ||
19045 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
19046 | static int | |
19047 | relax_addsub (fragS *fragp, asection *sec) | |
19048 | { | |
19049 | char *buf; | |
19050 | int op; | |
19051 | ||
19052 | buf = fragp->fr_literal + fragp->fr_fix; | |
19053 | op = bfd_get_16(sec->owner, buf); | |
19054 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
19055 | return relax_immediate (fragp, 8, 0); | |
19056 | else | |
19057 | return relax_immediate (fragp, 3, 0); | |
19058 | } | |
19059 | ||
19060 | ||
19061 | /* Return the size of a relaxable branch instruction. BITS is the | |
19062 | size of the offset field in the narrow instruction. */ | |
19063 | ||
19064 | static int | |
5e77afaa | 19065 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
19066 | { |
19067 | addressT addr; | |
19068 | offsetT val; | |
19069 | offsetT limit; | |
19070 | ||
19071 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 19072 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
19073 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19074 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19075 | return 4; |
19076 | ||
267bf995 RR |
19077 | #ifdef OBJ_ELF |
19078 | if (S_IS_DEFINED (fragp->fr_symbol) | |
19079 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
19080 | return 4; | |
0d9b4b55 NC |
19081 | |
19082 | /* PR 12532. Global symbols with default visibility might | |
19083 | be preempted, so do not relax relocations to them. */ | |
19084 | if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT) | |
19085 | && (! S_IS_LOCAL (fragp->fr_symbol))) | |
19086 | return 4; | |
267bf995 RR |
19087 | #endif |
19088 | ||
5f4273c7 | 19089 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19090 | addr = fragp->fr_address + fragp->fr_fix + 4; |
19091 | val -= addr; | |
19092 | ||
19093 | /* Offset is a signed value *2 */ | |
19094 | limit = 1 << bits; | |
19095 | if (val >= limit || val < -limit) | |
19096 | return 4; | |
19097 | return 2; | |
19098 | } | |
19099 | ||
19100 | ||
19101 | /* Relax a machine dependent frag. This returns the amount by which | |
19102 | the current size of the frag should change. */ | |
19103 | ||
19104 | int | |
5e77afaa | 19105 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
19106 | { |
19107 | int oldsize; | |
19108 | int newsize; | |
19109 | ||
19110 | oldsize = fragp->fr_var; | |
19111 | switch (fragp->fr_subtype) | |
19112 | { | |
19113 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 19114 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19115 | break; |
19116 | case T_MNEM_ldr_pc: | |
19117 | case T_MNEM_ldr_sp: | |
19118 | case T_MNEM_str_sp: | |
5f4273c7 | 19119 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
19120 | break; |
19121 | case T_MNEM_ldr: | |
19122 | case T_MNEM_str: | |
5f4273c7 | 19123 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
19124 | break; |
19125 | case T_MNEM_ldrh: | |
19126 | case T_MNEM_strh: | |
5f4273c7 | 19127 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
19128 | break; |
19129 | case T_MNEM_ldrb: | |
19130 | case T_MNEM_strb: | |
5f4273c7 | 19131 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
19132 | break; |
19133 | case T_MNEM_adr: | |
5f4273c7 | 19134 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19135 | break; |
19136 | case T_MNEM_mov: | |
19137 | case T_MNEM_movs: | |
19138 | case T_MNEM_cmp: | |
19139 | case T_MNEM_cmn: | |
5f4273c7 | 19140 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
19141 | break; |
19142 | case T_MNEM_b: | |
5f4273c7 | 19143 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
19144 | break; |
19145 | case T_MNEM_bcond: | |
5f4273c7 | 19146 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
19147 | break; |
19148 | case T_MNEM_add_sp: | |
19149 | case T_MNEM_add_pc: | |
19150 | newsize = relax_immediate (fragp, 8, 2); | |
19151 | break; | |
19152 | case T_MNEM_inc_sp: | |
19153 | case T_MNEM_dec_sp: | |
19154 | newsize = relax_immediate (fragp, 7, 2); | |
19155 | break; | |
19156 | case T_MNEM_addi: | |
19157 | case T_MNEM_addis: | |
19158 | case T_MNEM_subi: | |
19159 | case T_MNEM_subis: | |
19160 | newsize = relax_addsub (fragp, sec); | |
19161 | break; | |
19162 | default: | |
5f4273c7 | 19163 | abort (); |
0110f2b8 | 19164 | } |
5e77afaa PB |
19165 | |
19166 | fragp->fr_var = newsize; | |
19167 | /* Freeze wide instructions that are at or before the same location as | |
19168 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
19169 | Don't freeze them unconditionally because targets may be artificially |
19170 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 19171 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 19172 | { |
0110f2b8 | 19173 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 19174 | frag_wane (fragp); |
0110f2b8 | 19175 | } |
5e77afaa | 19176 | |
0110f2b8 | 19177 | return newsize - oldsize; |
c19d1205 | 19178 | } |
b99bd4ef | 19179 | |
c19d1205 | 19180 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 19181 | |
c19d1205 ZW |
19182 | valueT |
19183 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
19184 | valueT size) | |
19185 | { | |
f0927246 NC |
19186 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
19187 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
19188 | { | |
19189 | /* For a.out, force the section size to be aligned. If we don't do | |
19190 | this, BFD will align it for us, but it will not write out the | |
19191 | final bytes of the section. This may be a bug in BFD, but it is | |
19192 | easier to fix it here since that is how the other a.out targets | |
19193 | work. */ | |
19194 | int align; | |
19195 | ||
19196 | align = bfd_get_section_alignment (stdoutput, segment); | |
19197 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
19198 | } | |
c19d1205 | 19199 | #endif |
f0927246 NC |
19200 | |
19201 | return size; | |
bfae80f2 | 19202 | } |
b99bd4ef | 19203 | |
c19d1205 ZW |
19204 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
19205 | of an rs_align_code fragment. */ | |
19206 | ||
19207 | void | |
19208 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 19209 | { |
e7495e45 NS |
19210 | static char const arm_noop[2][2][4] = |
19211 | { | |
19212 | { /* ARMv1 */ | |
19213 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
19214 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
19215 | }, | |
19216 | { /* ARMv6k */ | |
19217 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
19218 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
19219 | }, | |
19220 | }; | |
19221 | static char const thumb_noop[2][2][2] = | |
19222 | { | |
19223 | { /* Thumb-1 */ | |
19224 | {0xc0, 0x46}, /* LE */ | |
19225 | {0x46, 0xc0}, /* BE */ | |
19226 | }, | |
19227 | { /* Thumb-2 */ | |
19228 | {0x00, 0xbf}, /* LE */ | |
19229 | {0xbf, 0x00} /* BE */ | |
19230 | } | |
19231 | }; | |
19232 | static char const wide_thumb_noop[2][4] = | |
19233 | { /* Wide Thumb-2 */ | |
19234 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
19235 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
19236 | }; | |
c921be7d | 19237 | |
e7495e45 | 19238 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
19239 | char * p; |
19240 | const char * noop; | |
e7495e45 | 19241 | const char *narrow_noop = NULL; |
cd000bff DJ |
19242 | #ifdef OBJ_ELF |
19243 | enum mstate state; | |
19244 | #endif | |
bfae80f2 | 19245 | |
c19d1205 | 19246 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
19247 | return; |
19248 | ||
c19d1205 ZW |
19249 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
19250 | p = fragP->fr_literal + fragP->fr_fix; | |
19251 | fix = 0; | |
bfae80f2 | 19252 | |
c19d1205 ZW |
19253 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
19254 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 19255 | |
cd000bff | 19256 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 19257 | |
cd000bff | 19258 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 19259 | { |
e7495e45 NS |
19260 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
19261 | { | |
19262 | narrow_noop = thumb_noop[1][target_big_endian]; | |
19263 | noop = wide_thumb_noop[target_big_endian]; | |
19264 | } | |
c19d1205 | 19265 | else |
e7495e45 NS |
19266 | noop = thumb_noop[0][target_big_endian]; |
19267 | noop_size = 2; | |
cd000bff DJ |
19268 | #ifdef OBJ_ELF |
19269 | state = MAP_THUMB; | |
19270 | #endif | |
7ed4c4c5 NC |
19271 | } |
19272 | else | |
19273 | { | |
e7495e45 NS |
19274 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
19275 | [target_big_endian]; | |
19276 | noop_size = 4; | |
cd000bff DJ |
19277 | #ifdef OBJ_ELF |
19278 | state = MAP_ARM; | |
19279 | #endif | |
7ed4c4c5 | 19280 | } |
c921be7d | 19281 | |
e7495e45 | 19282 | fragP->fr_var = noop_size; |
c921be7d | 19283 | |
c19d1205 | 19284 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 19285 | { |
c19d1205 | 19286 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
19287 | #ifdef OBJ_ELF |
19288 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
19289 | #endif | |
c19d1205 ZW |
19290 | memset (p, 0, fix); |
19291 | p += fix; | |
19292 | bytes -= fix; | |
a737bd4d | 19293 | } |
a737bd4d | 19294 | |
e7495e45 NS |
19295 | if (narrow_noop) |
19296 | { | |
19297 | if (bytes & noop_size) | |
19298 | { | |
19299 | /* Insert a narrow noop. */ | |
19300 | memcpy (p, narrow_noop, noop_size); | |
19301 | p += noop_size; | |
19302 | bytes -= noop_size; | |
19303 | fix += noop_size; | |
19304 | } | |
19305 | ||
19306 | /* Use wide noops for the remainder */ | |
19307 | noop_size = 4; | |
19308 | } | |
19309 | ||
c19d1205 | 19310 | while (bytes >= noop_size) |
a737bd4d | 19311 | { |
c19d1205 ZW |
19312 | memcpy (p, noop, noop_size); |
19313 | p += noop_size; | |
19314 | bytes -= noop_size; | |
19315 | fix += noop_size; | |
a737bd4d NC |
19316 | } |
19317 | ||
c19d1205 | 19318 | fragP->fr_fix += fix; |
a737bd4d NC |
19319 | } |
19320 | ||
c19d1205 ZW |
19321 | /* Called from md_do_align. Used to create an alignment |
19322 | frag in a code section. */ | |
19323 | ||
19324 | void | |
19325 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 19326 | { |
c19d1205 | 19327 | char * p; |
7ed4c4c5 | 19328 | |
c19d1205 | 19329 | /* We assume that there will never be a requirement |
6ec8e702 | 19330 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 19331 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
19332 | { |
19333 | char err_msg[128]; | |
19334 | ||
19335 | sprintf (err_msg, | |
19336 | _("alignments greater than %d bytes not supported in .text sections."), | |
19337 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 19338 | as_fatal ("%s", err_msg); |
6ec8e702 | 19339 | } |
bfae80f2 | 19340 | |
c19d1205 ZW |
19341 | p = frag_var (rs_align_code, |
19342 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
19343 | 1, | |
19344 | (relax_substateT) max, | |
19345 | (symbolS *) NULL, | |
19346 | (offsetT) n, | |
19347 | (char *) NULL); | |
19348 | *p = 0; | |
19349 | } | |
bfae80f2 | 19350 | |
8dc2430f NC |
19351 | /* Perform target specific initialisation of a frag. |
19352 | Note - despite the name this initialisation is not done when the frag | |
19353 | is created, but only when its type is assigned. A frag can be created | |
19354 | and used a long time before its type is set, so beware of assuming that | |
19355 | this initialisationis performed first. */ | |
bfae80f2 | 19356 | |
cd000bff DJ |
19357 | #ifndef OBJ_ELF |
19358 | void | |
19359 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
19360 | { | |
19361 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 19362 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
19363 | } |
19364 | ||
19365 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 19366 | void |
cd000bff | 19367 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 19368 | { |
8dc2430f NC |
19369 | /* If the current ARM vs THUMB mode has not already |
19370 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
19371 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
19372 | { | |
19373 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
19374 | ||
19375 | /* Record a mapping symbol for alignment frags. We will delete this | |
19376 | later if the alignment ends up empty. */ | |
19377 | switch (fragP->fr_type) | |
19378 | { | |
19379 | case rs_align: | |
19380 | case rs_align_test: | |
19381 | case rs_fill: | |
19382 | mapping_state_2 (MAP_DATA, max_chars); | |
19383 | break; | |
19384 | case rs_align_code: | |
19385 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
19386 | break; | |
19387 | default: | |
19388 | break; | |
19389 | } | |
19390 | } | |
bfae80f2 RE |
19391 | } |
19392 | ||
c19d1205 ZW |
19393 | /* When we change sections we need to issue a new mapping symbol. */ |
19394 | ||
19395 | void | |
19396 | arm_elf_change_section (void) | |
bfae80f2 | 19397 | { |
c19d1205 ZW |
19398 | /* Link an unlinked unwind index table section to the .text section. */ |
19399 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
19400 | && elf_linked_to_section (now_seg) == NULL) | |
19401 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
19402 | } |
19403 | ||
c19d1205 ZW |
19404 | int |
19405 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 19406 | { |
c19d1205 ZW |
19407 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
19408 | return SHT_ARM_EXIDX; | |
e45d0630 | 19409 | |
c19d1205 ZW |
19410 | return -1; |
19411 | } | |
19412 | \f | |
19413 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 19414 | |
c19d1205 | 19415 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 19416 | |
5f4273c7 | 19417 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 19418 | |
bfae80f2 | 19419 | static void |
c19d1205 | 19420 | flush_pending_unwind (void) |
bfae80f2 | 19421 | { |
c19d1205 | 19422 | offsetT offset; |
bfae80f2 | 19423 | |
c19d1205 ZW |
19424 | offset = unwind.pending_offset; |
19425 | unwind.pending_offset = 0; | |
19426 | if (offset != 0) | |
19427 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
19428 | } |
19429 | ||
c19d1205 ZW |
19430 | /* Add an opcode to this list for this function. Two-byte opcodes should |
19431 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
19432 | order. */ | |
19433 | ||
bfae80f2 | 19434 | static void |
c19d1205 | 19435 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 19436 | { |
c19d1205 ZW |
19437 | /* Add any deferred stack adjustment. */ |
19438 | if (unwind.pending_offset) | |
19439 | flush_pending_unwind (); | |
bfae80f2 | 19440 | |
c19d1205 | 19441 | unwind.sp_restored = 0; |
bfae80f2 | 19442 | |
c19d1205 | 19443 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 19444 | { |
c19d1205 ZW |
19445 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
19446 | if (unwind.opcodes) | |
21d799b5 NC |
19447 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
19448 | unwind.opcode_alloc); | |
c19d1205 | 19449 | else |
21d799b5 | 19450 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 19451 | } |
c19d1205 | 19452 | while (length > 0) |
bfae80f2 | 19453 | { |
c19d1205 ZW |
19454 | length--; |
19455 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
19456 | op >>= 8; | |
19457 | unwind.opcode_count++; | |
bfae80f2 | 19458 | } |
bfae80f2 RE |
19459 | } |
19460 | ||
c19d1205 ZW |
19461 | /* Add unwind opcodes to adjust the stack pointer. */ |
19462 | ||
bfae80f2 | 19463 | static void |
c19d1205 | 19464 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 19465 | { |
c19d1205 | 19466 | valueT op; |
bfae80f2 | 19467 | |
c19d1205 | 19468 | if (offset > 0x200) |
bfae80f2 | 19469 | { |
c19d1205 ZW |
19470 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
19471 | char bytes[5]; | |
19472 | int n; | |
19473 | valueT o; | |
bfae80f2 | 19474 | |
c19d1205 ZW |
19475 | /* Long form: 0xb2, uleb128. */ |
19476 | /* This might not fit in a word so add the individual bytes, | |
19477 | remembering the list is built in reverse order. */ | |
19478 | o = (valueT) ((offset - 0x204) >> 2); | |
19479 | if (o == 0) | |
19480 | add_unwind_opcode (0, 1); | |
bfae80f2 | 19481 | |
c19d1205 ZW |
19482 | /* Calculate the uleb128 encoding of the offset. */ |
19483 | n = 0; | |
19484 | while (o) | |
19485 | { | |
19486 | bytes[n] = o & 0x7f; | |
19487 | o >>= 7; | |
19488 | if (o) | |
19489 | bytes[n] |= 0x80; | |
19490 | n++; | |
19491 | } | |
19492 | /* Add the insn. */ | |
19493 | for (; n; n--) | |
19494 | add_unwind_opcode (bytes[n - 1], 1); | |
19495 | add_unwind_opcode (0xb2, 1); | |
19496 | } | |
19497 | else if (offset > 0x100) | |
bfae80f2 | 19498 | { |
c19d1205 ZW |
19499 | /* Two short opcodes. */ |
19500 | add_unwind_opcode (0x3f, 1); | |
19501 | op = (offset - 0x104) >> 2; | |
19502 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19503 | } |
c19d1205 ZW |
19504 | else if (offset > 0) |
19505 | { | |
19506 | /* Short opcode. */ | |
19507 | op = (offset - 4) >> 2; | |
19508 | add_unwind_opcode (op, 1); | |
19509 | } | |
19510 | else if (offset < 0) | |
bfae80f2 | 19511 | { |
c19d1205 ZW |
19512 | offset = -offset; |
19513 | while (offset > 0x100) | |
bfae80f2 | 19514 | { |
c19d1205 ZW |
19515 | add_unwind_opcode (0x7f, 1); |
19516 | offset -= 0x100; | |
bfae80f2 | 19517 | } |
c19d1205 ZW |
19518 | op = ((offset - 4) >> 2) | 0x40; |
19519 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19520 | } |
bfae80f2 RE |
19521 | } |
19522 | ||
c19d1205 ZW |
19523 | /* Finish the list of unwind opcodes for this function. */ |
19524 | static void | |
19525 | finish_unwind_opcodes (void) | |
bfae80f2 | 19526 | { |
c19d1205 | 19527 | valueT op; |
bfae80f2 | 19528 | |
c19d1205 | 19529 | if (unwind.fp_used) |
bfae80f2 | 19530 | { |
708587a4 | 19531 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
19532 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
19533 | flush_pending_unwind (); | |
bfae80f2 | 19534 | |
c19d1205 ZW |
19535 | /* After restoring sp from the frame pointer. */ |
19536 | op = 0x90 | unwind.fp_reg; | |
19537 | add_unwind_opcode (op, 1); | |
19538 | } | |
19539 | else | |
19540 | flush_pending_unwind (); | |
bfae80f2 RE |
19541 | } |
19542 | ||
bfae80f2 | 19543 | |
c19d1205 ZW |
19544 | /* Start an exception table entry. If idx is nonzero this is an index table |
19545 | entry. */ | |
bfae80f2 RE |
19546 | |
19547 | static void | |
c19d1205 | 19548 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 19549 | { |
c19d1205 ZW |
19550 | const char * text_name; |
19551 | const char * prefix; | |
19552 | const char * prefix_once; | |
19553 | const char * group_name; | |
19554 | size_t prefix_len; | |
19555 | size_t text_len; | |
19556 | char * sec_name; | |
19557 | size_t sec_name_len; | |
19558 | int type; | |
19559 | int flags; | |
19560 | int linkonce; | |
bfae80f2 | 19561 | |
c19d1205 | 19562 | if (idx) |
bfae80f2 | 19563 | { |
c19d1205 ZW |
19564 | prefix = ELF_STRING_ARM_unwind; |
19565 | prefix_once = ELF_STRING_ARM_unwind_once; | |
19566 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 19567 | } |
c19d1205 | 19568 | else |
bfae80f2 | 19569 | { |
c19d1205 ZW |
19570 | prefix = ELF_STRING_ARM_unwind_info; |
19571 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
19572 | type = SHT_PROGBITS; | |
bfae80f2 RE |
19573 | } |
19574 | ||
c19d1205 ZW |
19575 | text_name = segment_name (text_seg); |
19576 | if (streq (text_name, ".text")) | |
19577 | text_name = ""; | |
19578 | ||
19579 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
19580 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 19581 | { |
c19d1205 ZW |
19582 | prefix = prefix_once; |
19583 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
19584 | } |
19585 | ||
c19d1205 ZW |
19586 | prefix_len = strlen (prefix); |
19587 | text_len = strlen (text_name); | |
19588 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 19589 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
19590 | memcpy (sec_name, prefix, prefix_len); |
19591 | memcpy (sec_name + prefix_len, text_name, text_len); | |
19592 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 19593 | |
c19d1205 ZW |
19594 | flags = SHF_ALLOC; |
19595 | linkonce = 0; | |
19596 | group_name = 0; | |
bfae80f2 | 19597 | |
c19d1205 ZW |
19598 | /* Handle COMDAT group. */ |
19599 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 19600 | { |
c19d1205 ZW |
19601 | group_name = elf_group_name (text_seg); |
19602 | if (group_name == NULL) | |
19603 | { | |
bd3ba5d1 | 19604 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
19605 | segment_name (text_seg)); |
19606 | ignore_rest_of_line (); | |
19607 | return; | |
19608 | } | |
19609 | flags |= SHF_GROUP; | |
19610 | linkonce = 1; | |
bfae80f2 RE |
19611 | } |
19612 | ||
c19d1205 | 19613 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 19614 | |
5f4273c7 | 19615 | /* Set the section link for index tables. */ |
c19d1205 ZW |
19616 | if (idx) |
19617 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
19618 | } |
19619 | ||
bfae80f2 | 19620 | |
c19d1205 ZW |
19621 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
19622 | personality routine data. Returns zero, or the index table value for | |
19623 | and inline entry. */ | |
19624 | ||
19625 | static valueT | |
19626 | create_unwind_entry (int have_data) | |
bfae80f2 | 19627 | { |
c19d1205 ZW |
19628 | int size; |
19629 | addressT where; | |
19630 | char *ptr; | |
19631 | /* The current word of data. */ | |
19632 | valueT data; | |
19633 | /* The number of bytes left in this word. */ | |
19634 | int n; | |
bfae80f2 | 19635 | |
c19d1205 | 19636 | finish_unwind_opcodes (); |
bfae80f2 | 19637 | |
c19d1205 ZW |
19638 | /* Remember the current text section. */ |
19639 | unwind.saved_seg = now_seg; | |
19640 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 19641 | |
c19d1205 | 19642 | start_unwind_section (now_seg, 0); |
bfae80f2 | 19643 | |
c19d1205 | 19644 | if (unwind.personality_routine == NULL) |
bfae80f2 | 19645 | { |
c19d1205 ZW |
19646 | if (unwind.personality_index == -2) |
19647 | { | |
19648 | if (have_data) | |
5f4273c7 | 19649 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
19650 | return 1; /* EXIDX_CANTUNWIND. */ |
19651 | } | |
bfae80f2 | 19652 | |
c19d1205 ZW |
19653 | /* Use a default personality routine if none is specified. */ |
19654 | if (unwind.personality_index == -1) | |
19655 | { | |
19656 | if (unwind.opcode_count > 3) | |
19657 | unwind.personality_index = 1; | |
19658 | else | |
19659 | unwind.personality_index = 0; | |
19660 | } | |
bfae80f2 | 19661 | |
c19d1205 ZW |
19662 | /* Space for the personality routine entry. */ |
19663 | if (unwind.personality_index == 0) | |
19664 | { | |
19665 | if (unwind.opcode_count > 3) | |
19666 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 19667 | |
c19d1205 ZW |
19668 | if (!have_data) |
19669 | { | |
19670 | /* All the data is inline in the index table. */ | |
19671 | data = 0x80; | |
19672 | n = 3; | |
19673 | while (unwind.opcode_count > 0) | |
19674 | { | |
19675 | unwind.opcode_count--; | |
19676 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19677 | n--; | |
19678 | } | |
bfae80f2 | 19679 | |
c19d1205 ZW |
19680 | /* Pad with "finish" opcodes. */ |
19681 | while (n--) | |
19682 | data = (data << 8) | 0xb0; | |
bfae80f2 | 19683 | |
c19d1205 ZW |
19684 | return data; |
19685 | } | |
19686 | size = 0; | |
19687 | } | |
19688 | else | |
19689 | /* We get two opcodes "free" in the first word. */ | |
19690 | size = unwind.opcode_count - 2; | |
19691 | } | |
19692 | else | |
19693 | /* An extra byte is required for the opcode count. */ | |
19694 | size = unwind.opcode_count + 1; | |
bfae80f2 | 19695 | |
c19d1205 ZW |
19696 | size = (size + 3) >> 2; |
19697 | if (size > 0xff) | |
19698 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 19699 | |
c19d1205 ZW |
19700 | frag_align (2, 0, 0); |
19701 | record_alignment (now_seg, 2); | |
19702 | unwind.table_entry = expr_build_dot (); | |
19703 | ||
19704 | /* Allocate the table entry. */ | |
19705 | ptr = frag_more ((size << 2) + 4); | |
19706 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 19707 | |
c19d1205 | 19708 | switch (unwind.personality_index) |
bfae80f2 | 19709 | { |
c19d1205 ZW |
19710 | case -1: |
19711 | /* ??? Should this be a PLT generating relocation? */ | |
19712 | /* Custom personality routine. */ | |
19713 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
19714 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 19715 | |
c19d1205 ZW |
19716 | where += 4; |
19717 | ptr += 4; | |
bfae80f2 | 19718 | |
c19d1205 ZW |
19719 | /* Set the first byte to the number of additional words. */ |
19720 | data = size - 1; | |
19721 | n = 3; | |
19722 | break; | |
bfae80f2 | 19723 | |
c19d1205 ZW |
19724 | /* ABI defined personality routines. */ |
19725 | case 0: | |
19726 | /* Three opcodes bytes are packed into the first word. */ | |
19727 | data = 0x80; | |
19728 | n = 3; | |
19729 | break; | |
bfae80f2 | 19730 | |
c19d1205 ZW |
19731 | case 1: |
19732 | case 2: | |
19733 | /* The size and first two opcode bytes go in the first word. */ | |
19734 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
19735 | n = 2; | |
19736 | break; | |
bfae80f2 | 19737 | |
c19d1205 ZW |
19738 | default: |
19739 | /* Should never happen. */ | |
19740 | abort (); | |
19741 | } | |
bfae80f2 | 19742 | |
c19d1205 ZW |
19743 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
19744 | time. */ | |
19745 | while (unwind.opcode_count > 0) | |
19746 | { | |
19747 | if (n == 0) | |
19748 | { | |
19749 | md_number_to_chars (ptr, data, 4); | |
19750 | ptr += 4; | |
19751 | n = 4; | |
19752 | data = 0; | |
19753 | } | |
19754 | unwind.opcode_count--; | |
19755 | n--; | |
19756 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19757 | } | |
19758 | ||
19759 | /* Finish off the last word. */ | |
19760 | if (n < 4) | |
19761 | { | |
19762 | /* Pad with "finish" opcodes. */ | |
19763 | while (n--) | |
19764 | data = (data << 8) | 0xb0; | |
19765 | ||
19766 | md_number_to_chars (ptr, data, 4); | |
19767 | } | |
19768 | ||
19769 | if (!have_data) | |
19770 | { | |
19771 | /* Add an empty descriptor if there is no user-specified data. */ | |
19772 | ptr = frag_more (4); | |
19773 | md_number_to_chars (ptr, 0, 4); | |
19774 | } | |
19775 | ||
19776 | return 0; | |
bfae80f2 RE |
19777 | } |
19778 | ||
f0927246 NC |
19779 | |
19780 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
19781 | ||
19782 | void | |
19783 | tc_arm_frame_initial_instructions (void) | |
19784 | { | |
19785 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
19786 | } | |
19787 | #endif /* OBJ_ELF */ | |
19788 | ||
c19d1205 ZW |
19789 | /* Convert REGNAME to a DWARF-2 register number. */ |
19790 | ||
19791 | int | |
1df69f4f | 19792 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 19793 | { |
1df69f4f | 19794 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
19795 | |
19796 | if (reg == FAIL) | |
19797 | return -1; | |
19798 | ||
19799 | return reg; | |
bfae80f2 RE |
19800 | } |
19801 | ||
f0927246 | 19802 | #ifdef TE_PE |
c19d1205 | 19803 | void |
f0927246 | 19804 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 19805 | { |
91d6fa6a | 19806 | expressionS exp; |
bfae80f2 | 19807 | |
91d6fa6a NC |
19808 | exp.X_op = O_secrel; |
19809 | exp.X_add_symbol = symbol; | |
19810 | exp.X_add_number = 0; | |
19811 | emit_expr (&exp, size); | |
f0927246 NC |
19812 | } |
19813 | #endif | |
bfae80f2 | 19814 | |
c19d1205 | 19815 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 19816 | |
2fc8bdac ZW |
19817 | /* Return the address within the segment that a PC-relative fixup is |
19818 | relative to. For ARM, PC-relative fixups applied to instructions | |
19819 | are generally relative to the location of the fixup plus 8 bytes. | |
19820 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
19821 | require special handling. */ | |
bfae80f2 | 19822 | |
c19d1205 | 19823 | long |
2fc8bdac | 19824 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 19825 | { |
2fc8bdac ZW |
19826 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
19827 | ||
19828 | /* If this is pc-relative and we are going to emit a relocation | |
19829 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
19830 | will need. Otherwise we want to use the calculated base. |
19831 | For WinCE we skip the bias for externals as well, since this | |
19832 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 19833 | if (fixP->fx_pcrel |
2fc8bdac | 19834 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
19835 | || (arm_force_relocation (fixP) |
19836 | #ifdef TE_WINCE | |
19837 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19838 | #endif | |
19839 | ))) | |
2fc8bdac | 19840 | base = 0; |
bfae80f2 | 19841 | |
267bf995 | 19842 | |
c19d1205 | 19843 | switch (fixP->fx_r_type) |
bfae80f2 | 19844 | { |
2fc8bdac ZW |
19845 | /* PC relative addressing on the Thumb is slightly odd as the |
19846 | bottom two bits of the PC are forced to zero for the | |
19847 | calculation. This happens *after* application of the | |
19848 | pipeline offset. However, Thumb adrl already adjusts for | |
19849 | this, so we need not do it again. */ | |
c19d1205 | 19850 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 19851 | return base & ~3; |
c19d1205 ZW |
19852 | |
19853 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
19854 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 19855 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 19856 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 19857 | return (base + 4) & ~3; |
c19d1205 | 19858 | |
2fc8bdac ZW |
19859 | /* Thumb branches are simply offset by +4. */ |
19860 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
19861 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
19862 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
19863 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 19864 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 19865 | return base + 4; |
bfae80f2 | 19866 | |
267bf995 | 19867 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
19868 | if (fixP->fx_addsy |
19869 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19870 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19871 | && ARM_IS_FUNC (fixP->fx_addsy) |
19872 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19873 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
19874 | return base + 4; | |
19875 | ||
00adf2d4 JB |
19876 | /* BLX is like branches above, but forces the low two bits of PC to |
19877 | zero. */ | |
486499d0 CL |
19878 | case BFD_RELOC_THUMB_PCREL_BLX: |
19879 | if (fixP->fx_addsy | |
19880 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19881 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19882 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19883 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19884 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
19885 | return (base + 4) & ~3; |
19886 | ||
2fc8bdac ZW |
19887 | /* ARM mode branches are offset by +8. However, the Windows CE |
19888 | loader expects the relocation not to take this into account. */ | |
267bf995 | 19889 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
19890 | if (fixP->fx_addsy |
19891 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19892 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19893 | && ARM_IS_FUNC (fixP->fx_addsy) |
19894 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19895 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19896 | return base + 8; |
267bf995 | 19897 | |
486499d0 CL |
19898 | case BFD_RELOC_ARM_PCREL_CALL: |
19899 | if (fixP->fx_addsy | |
19900 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19901 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19902 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19903 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19904 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19905 | return base + 8; |
267bf995 | 19906 | |
2fc8bdac | 19907 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 19908 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 19909 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 19910 | #ifdef TE_WINCE |
5f4273c7 | 19911 | /* When handling fixups immediately, because we have already |
53baae48 NC |
19912 | discovered the value of a symbol, or the address of the frag involved |
19913 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
19914 | see fixup_segment() in write.c | |
19915 | The S_IS_EXTERNAL test handles the case of global symbols. | |
19916 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
19917 | if (fixP->fx_pcrel | |
19918 | && fixP->fx_addsy != NULL | |
19919 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
19920 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
19921 | return base + 8; | |
2fc8bdac | 19922 | return base; |
c19d1205 | 19923 | #else |
2fc8bdac | 19924 | return base + 8; |
c19d1205 | 19925 | #endif |
2fc8bdac | 19926 | |
267bf995 | 19927 | |
2fc8bdac ZW |
19928 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
19929 | branches, the Windows CE loader *does* expect the relocation | |
19930 | to take this into account. */ | |
19931 | case BFD_RELOC_ARM_OFFSET_IMM: | |
19932 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
19933 | case BFD_RELOC_ARM_HWLITERAL: | |
19934 | case BFD_RELOC_ARM_LITERAL: | |
19935 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
19936 | return base + 8; | |
19937 | ||
19938 | ||
19939 | /* Other PC-relative relocations are un-offset. */ | |
19940 | default: | |
19941 | return base; | |
19942 | } | |
bfae80f2 RE |
19943 | } |
19944 | ||
c19d1205 ZW |
19945 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
19946 | Otherwise we have no need to default values of symbols. */ | |
19947 | ||
19948 | symbolS * | |
19949 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 19950 | { |
c19d1205 ZW |
19951 | #ifdef OBJ_ELF |
19952 | if (name[0] == '_' && name[1] == 'G' | |
19953 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
19954 | { | |
19955 | if (!GOT_symbol) | |
19956 | { | |
19957 | if (symbol_find (name)) | |
bd3ba5d1 | 19958 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 19959 | |
c19d1205 ZW |
19960 | GOT_symbol = symbol_new (name, undefined_section, |
19961 | (valueT) 0, & zero_address_frag); | |
19962 | } | |
bfae80f2 | 19963 | |
c19d1205 | 19964 | return GOT_symbol; |
bfae80f2 | 19965 | } |
c19d1205 | 19966 | #endif |
bfae80f2 | 19967 | |
c921be7d | 19968 | return NULL; |
bfae80f2 RE |
19969 | } |
19970 | ||
55cf6793 | 19971 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
19972 | computed as two separate immediate values, added together. We |
19973 | already know that this value cannot be computed by just one ARM | |
19974 | instruction. */ | |
19975 | ||
19976 | static unsigned int | |
19977 | validate_immediate_twopart (unsigned int val, | |
19978 | unsigned int * highpart) | |
bfae80f2 | 19979 | { |
c19d1205 ZW |
19980 | unsigned int a; |
19981 | unsigned int i; | |
bfae80f2 | 19982 | |
c19d1205 ZW |
19983 | for (i = 0; i < 32; i += 2) |
19984 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
19985 | { | |
19986 | if (a & 0xff00) | |
19987 | { | |
19988 | if (a & ~ 0xffff) | |
19989 | continue; | |
19990 | * highpart = (a >> 8) | ((i + 24) << 7); | |
19991 | } | |
19992 | else if (a & 0xff0000) | |
19993 | { | |
19994 | if (a & 0xff000000) | |
19995 | continue; | |
19996 | * highpart = (a >> 16) | ((i + 16) << 7); | |
19997 | } | |
19998 | else | |
19999 | { | |
9c2799c2 | 20000 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
20001 | * highpart = (a >> 24) | ((i + 8) << 7); |
20002 | } | |
bfae80f2 | 20003 | |
c19d1205 ZW |
20004 | return (a & 0xff) | (i << 7); |
20005 | } | |
bfae80f2 | 20006 | |
c19d1205 | 20007 | return FAIL; |
bfae80f2 RE |
20008 | } |
20009 | ||
c19d1205 ZW |
20010 | static int |
20011 | validate_offset_imm (unsigned int val, int hwse) | |
20012 | { | |
20013 | if ((hwse && val > 255) || val > 4095) | |
20014 | return FAIL; | |
20015 | return val; | |
20016 | } | |
bfae80f2 | 20017 | |
55cf6793 | 20018 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
20019 | negative immediate constant by altering the instruction. A bit of |
20020 | a hack really. | |
20021 | MOV <-> MVN | |
20022 | AND <-> BIC | |
20023 | ADC <-> SBC | |
20024 | by inverting the second operand, and | |
20025 | ADD <-> SUB | |
20026 | CMP <-> CMN | |
20027 | by negating the second operand. */ | |
bfae80f2 | 20028 | |
c19d1205 ZW |
20029 | static int |
20030 | negate_data_op (unsigned long * instruction, | |
20031 | unsigned long value) | |
bfae80f2 | 20032 | { |
c19d1205 ZW |
20033 | int op, new_inst; |
20034 | unsigned long negated, inverted; | |
bfae80f2 | 20035 | |
c19d1205 ZW |
20036 | negated = encode_arm_immediate (-value); |
20037 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 20038 | |
c19d1205 ZW |
20039 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
20040 | switch (op) | |
bfae80f2 | 20041 | { |
c19d1205 ZW |
20042 | /* First negates. */ |
20043 | case OPCODE_SUB: /* ADD <-> SUB */ | |
20044 | new_inst = OPCODE_ADD; | |
20045 | value = negated; | |
20046 | break; | |
bfae80f2 | 20047 | |
c19d1205 ZW |
20048 | case OPCODE_ADD: |
20049 | new_inst = OPCODE_SUB; | |
20050 | value = negated; | |
20051 | break; | |
bfae80f2 | 20052 | |
c19d1205 ZW |
20053 | case OPCODE_CMP: /* CMP <-> CMN */ |
20054 | new_inst = OPCODE_CMN; | |
20055 | value = negated; | |
20056 | break; | |
bfae80f2 | 20057 | |
c19d1205 ZW |
20058 | case OPCODE_CMN: |
20059 | new_inst = OPCODE_CMP; | |
20060 | value = negated; | |
20061 | break; | |
bfae80f2 | 20062 | |
c19d1205 ZW |
20063 | /* Now Inverted ops. */ |
20064 | case OPCODE_MOV: /* MOV <-> MVN */ | |
20065 | new_inst = OPCODE_MVN; | |
20066 | value = inverted; | |
20067 | break; | |
bfae80f2 | 20068 | |
c19d1205 ZW |
20069 | case OPCODE_MVN: |
20070 | new_inst = OPCODE_MOV; | |
20071 | value = inverted; | |
20072 | break; | |
bfae80f2 | 20073 | |
c19d1205 ZW |
20074 | case OPCODE_AND: /* AND <-> BIC */ |
20075 | new_inst = OPCODE_BIC; | |
20076 | value = inverted; | |
20077 | break; | |
bfae80f2 | 20078 | |
c19d1205 ZW |
20079 | case OPCODE_BIC: |
20080 | new_inst = OPCODE_AND; | |
20081 | value = inverted; | |
20082 | break; | |
bfae80f2 | 20083 | |
c19d1205 ZW |
20084 | case OPCODE_ADC: /* ADC <-> SBC */ |
20085 | new_inst = OPCODE_SBC; | |
20086 | value = inverted; | |
20087 | break; | |
bfae80f2 | 20088 | |
c19d1205 ZW |
20089 | case OPCODE_SBC: |
20090 | new_inst = OPCODE_ADC; | |
20091 | value = inverted; | |
20092 | break; | |
bfae80f2 | 20093 | |
c19d1205 ZW |
20094 | /* We cannot do anything. */ |
20095 | default: | |
20096 | return FAIL; | |
b99bd4ef NC |
20097 | } |
20098 | ||
c19d1205 ZW |
20099 | if (value == (unsigned) FAIL) |
20100 | return FAIL; | |
20101 | ||
20102 | *instruction &= OPCODE_MASK; | |
20103 | *instruction |= new_inst << DATA_OP_SHIFT; | |
20104 | return value; | |
b99bd4ef NC |
20105 | } |
20106 | ||
ef8d22e6 PB |
20107 | /* Like negate_data_op, but for Thumb-2. */ |
20108 | ||
20109 | static unsigned int | |
16dd5e42 | 20110 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
20111 | { |
20112 | int op, new_inst; | |
20113 | int rd; | |
16dd5e42 | 20114 | unsigned int negated, inverted; |
ef8d22e6 PB |
20115 | |
20116 | negated = encode_thumb32_immediate (-value); | |
20117 | inverted = encode_thumb32_immediate (~value); | |
20118 | ||
20119 | rd = (*instruction >> 8) & 0xf; | |
20120 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
20121 | switch (op) | |
20122 | { | |
20123 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
20124 | case T2_OPCODE_SUB: | |
20125 | new_inst = T2_OPCODE_ADD; | |
20126 | value = negated; | |
20127 | break; | |
20128 | ||
20129 | case T2_OPCODE_ADD: | |
20130 | new_inst = T2_OPCODE_SUB; | |
20131 | value = negated; | |
20132 | break; | |
20133 | ||
20134 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
20135 | case T2_OPCODE_ORR: | |
20136 | new_inst = T2_OPCODE_ORN; | |
20137 | value = inverted; | |
20138 | break; | |
20139 | ||
20140 | case T2_OPCODE_ORN: | |
20141 | new_inst = T2_OPCODE_ORR; | |
20142 | value = inverted; | |
20143 | break; | |
20144 | ||
20145 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
20146 | case T2_OPCODE_AND: | |
20147 | new_inst = T2_OPCODE_BIC; | |
20148 | if (rd == 15) | |
20149 | value = FAIL; | |
20150 | else | |
20151 | value = inverted; | |
20152 | break; | |
20153 | ||
20154 | case T2_OPCODE_BIC: | |
20155 | new_inst = T2_OPCODE_AND; | |
20156 | value = inverted; | |
20157 | break; | |
20158 | ||
20159 | /* ADC <-> SBC */ | |
20160 | case T2_OPCODE_ADC: | |
20161 | new_inst = T2_OPCODE_SBC; | |
20162 | value = inverted; | |
20163 | break; | |
20164 | ||
20165 | case T2_OPCODE_SBC: | |
20166 | new_inst = T2_OPCODE_ADC; | |
20167 | value = inverted; | |
20168 | break; | |
20169 | ||
20170 | /* We cannot do anything. */ | |
20171 | default: | |
20172 | return FAIL; | |
20173 | } | |
20174 | ||
16dd5e42 | 20175 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
20176 | return FAIL; |
20177 | ||
20178 | *instruction &= T2_OPCODE_MASK; | |
20179 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
20180 | return value; | |
20181 | } | |
20182 | ||
8f06b2d8 PB |
20183 | /* Read a 32-bit thumb instruction from buf. */ |
20184 | static unsigned long | |
20185 | get_thumb32_insn (char * buf) | |
20186 | { | |
20187 | unsigned long insn; | |
20188 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
20189 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20190 | ||
20191 | return insn; | |
20192 | } | |
20193 | ||
a8bc6c78 PB |
20194 | |
20195 | /* We usually want to set the low bit on the address of thumb function | |
20196 | symbols. In particular .word foo - . should have the low bit set. | |
20197 | Generic code tries to fold the difference of two symbols to | |
20198 | a constant. Prevent this and force a relocation when the first symbols | |
20199 | is a thumb function. */ | |
c921be7d NC |
20200 | |
20201 | bfd_boolean | |
a8bc6c78 PB |
20202 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
20203 | { | |
20204 | if (op == O_subtract | |
20205 | && l->X_op == O_symbol | |
20206 | && r->X_op == O_symbol | |
20207 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
20208 | { | |
20209 | l->X_op = O_subtract; | |
20210 | l->X_op_symbol = r->X_add_symbol; | |
20211 | l->X_add_number -= r->X_add_number; | |
c921be7d | 20212 | return TRUE; |
a8bc6c78 | 20213 | } |
c921be7d | 20214 | |
a8bc6c78 | 20215 | /* Process as normal. */ |
c921be7d | 20216 | return FALSE; |
a8bc6c78 PB |
20217 | } |
20218 | ||
4a42ebbc RR |
20219 | /* Encode Thumb2 unconditional branches and calls. The encoding |
20220 | for the 2 are identical for the immediate values. */ | |
20221 | ||
20222 | static void | |
20223 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
20224 | { | |
20225 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
20226 | offsetT newval; | |
20227 | offsetT newval2; | |
20228 | addressT S, I1, I2, lo, hi; | |
20229 | ||
20230 | S = (value >> 24) & 0x01; | |
20231 | I1 = (value >> 23) & 0x01; | |
20232 | I2 = (value >> 22) & 0x01; | |
20233 | hi = (value >> 12) & 0x3ff; | |
20234 | lo = (value >> 1) & 0x7ff; | |
20235 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20236 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20237 | newval |= (S << 10) | hi; | |
20238 | newval2 &= ~T2I1I2MASK; | |
20239 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
20240 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20241 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20242 | } | |
20243 | ||
c19d1205 | 20244 | void |
55cf6793 | 20245 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
20246 | valueT * valP, |
20247 | segT seg) | |
20248 | { | |
20249 | offsetT value = * valP; | |
20250 | offsetT newval; | |
20251 | unsigned int newimm; | |
20252 | unsigned long temp; | |
20253 | int sign; | |
20254 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 20255 | |
9c2799c2 | 20256 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 20257 | |
c19d1205 | 20258 | /* Note whether this will delete the relocation. */ |
4962c51a | 20259 | |
c19d1205 ZW |
20260 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
20261 | fixP->fx_done = 1; | |
b99bd4ef | 20262 | |
adbaf948 | 20263 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 20264 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
20265 | for emit_reloc. */ |
20266 | value &= 0xffffffff; | |
20267 | value ^= 0x80000000; | |
5f4273c7 | 20268 | value -= 0x80000000; |
adbaf948 ZW |
20269 | |
20270 | *valP = value; | |
c19d1205 | 20271 | fixP->fx_addnumber = value; |
b99bd4ef | 20272 | |
adbaf948 ZW |
20273 | /* Same treatment for fixP->fx_offset. */ |
20274 | fixP->fx_offset &= 0xffffffff; | |
20275 | fixP->fx_offset ^= 0x80000000; | |
20276 | fixP->fx_offset -= 0x80000000; | |
20277 | ||
c19d1205 | 20278 | switch (fixP->fx_r_type) |
b99bd4ef | 20279 | { |
c19d1205 ZW |
20280 | case BFD_RELOC_NONE: |
20281 | /* This will need to go in the object file. */ | |
20282 | fixP->fx_done = 0; | |
20283 | break; | |
b99bd4ef | 20284 | |
c19d1205 ZW |
20285 | case BFD_RELOC_ARM_IMMEDIATE: |
20286 | /* We claim that this fixup has been processed here, | |
20287 | even if in fact we generate an error because we do | |
20288 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20289 | fixP->fx_done = 1; | |
b99bd4ef | 20290 | |
77db8e2e | 20291 | if (fixP->fx_addsy) |
b99bd4ef | 20292 | { |
77db8e2e | 20293 | const char *msg = 0; |
b99bd4ef | 20294 | |
77db8e2e NC |
20295 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20296 | msg = _("undefined symbol %s used as an immediate value"); | |
20297 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20298 | msg = _("symbol %s is in a different section"); | |
20299 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20300 | msg = _("symbol %s is weak and may be overridden later"); | |
20301 | ||
20302 | if (msg) | |
20303 | { | |
20304 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20305 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20306 | break; | |
20307 | } | |
42e5fcbf AS |
20308 | } |
20309 | ||
c19d1205 ZW |
20310 | newimm = encode_arm_immediate (value); |
20311 | temp = md_chars_to_number (buf, INSN_SIZE); | |
20312 | ||
20313 | /* If the instruction will fail, see if we can fix things up by | |
20314 | changing the opcode. */ | |
20315 | if (newimm == (unsigned int) FAIL | |
20316 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 20317 | { |
c19d1205 ZW |
20318 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20319 | _("invalid constant (%lx) after fixup"), | |
20320 | (unsigned long) value); | |
20321 | break; | |
b99bd4ef | 20322 | } |
b99bd4ef | 20323 | |
c19d1205 ZW |
20324 | newimm |= (temp & 0xfffff000); |
20325 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
20326 | break; | |
b99bd4ef | 20327 | |
c19d1205 ZW |
20328 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
20329 | { | |
20330 | unsigned int highpart = 0; | |
20331 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 20332 | |
77db8e2e | 20333 | if (fixP->fx_addsy) |
42e5fcbf | 20334 | { |
77db8e2e | 20335 | const char *msg = 0; |
42e5fcbf | 20336 | |
77db8e2e NC |
20337 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20338 | msg = _("undefined symbol %s used as an immediate value"); | |
20339 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20340 | msg = _("symbol %s is in a different section"); | |
20341 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20342 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 20343 | |
77db8e2e NC |
20344 | if (msg) |
20345 | { | |
20346 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20347 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20348 | break; | |
20349 | } | |
20350 | } | |
20351 | ||
c19d1205 ZW |
20352 | newimm = encode_arm_immediate (value); |
20353 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 20354 | |
c19d1205 ZW |
20355 | /* If the instruction will fail, see if we can fix things up by |
20356 | changing the opcode. */ | |
20357 | if (newimm == (unsigned int) FAIL | |
20358 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
20359 | { | |
20360 | /* No ? OK - try using two ADD instructions to generate | |
20361 | the value. */ | |
20362 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 20363 | |
c19d1205 ZW |
20364 | /* Yes - then make sure that the second instruction is |
20365 | also an add. */ | |
20366 | if (newimm != (unsigned int) FAIL) | |
20367 | newinsn = temp; | |
20368 | /* Still No ? Try using a negated value. */ | |
20369 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
20370 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
20371 | /* Otherwise - give up. */ | |
20372 | else | |
20373 | { | |
20374 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20375 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
20376 | (long) value); | |
20377 | break; | |
20378 | } | |
b99bd4ef | 20379 | |
c19d1205 ZW |
20380 | /* Replace the first operand in the 2nd instruction (which |
20381 | is the PC) with the destination register. We have | |
20382 | already added in the PC in the first instruction and we | |
20383 | do not want to do it again. */ | |
20384 | newinsn &= ~ 0xf0000; | |
20385 | newinsn |= ((newinsn & 0x0f000) << 4); | |
20386 | } | |
b99bd4ef | 20387 | |
c19d1205 ZW |
20388 | newimm |= (temp & 0xfffff000); |
20389 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 20390 | |
c19d1205 ZW |
20391 | highpart |= (newinsn & 0xfffff000); |
20392 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
20393 | } | |
20394 | break; | |
b99bd4ef | 20395 | |
c19d1205 | 20396 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20397 | if (!fixP->fx_done && seg->use_rela_p) |
20398 | value = 0; | |
20399 | ||
c19d1205 ZW |
20400 | case BFD_RELOC_ARM_LITERAL: |
20401 | sign = value >= 0; | |
b99bd4ef | 20402 | |
c19d1205 ZW |
20403 | if (value < 0) |
20404 | value = - value; | |
b99bd4ef | 20405 | |
c19d1205 | 20406 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 20407 | { |
c19d1205 ZW |
20408 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
20409 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20410 | _("invalid literal constant: pool needs to be closer")); | |
20411 | else | |
20412 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20413 | _("bad immediate value for offset (%ld)"), | |
20414 | (long) value); | |
20415 | break; | |
f03698e6 RE |
20416 | } |
20417 | ||
c19d1205 ZW |
20418 | newval = md_chars_to_number (buf, INSN_SIZE); |
20419 | newval &= 0xff7ff000; | |
20420 | newval |= value | (sign ? INDEX_UP : 0); | |
20421 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20422 | break; | |
b99bd4ef | 20423 | |
c19d1205 ZW |
20424 | case BFD_RELOC_ARM_OFFSET_IMM8: |
20425 | case BFD_RELOC_ARM_HWLITERAL: | |
20426 | sign = value >= 0; | |
b99bd4ef | 20427 | |
c19d1205 ZW |
20428 | if (value < 0) |
20429 | value = - value; | |
b99bd4ef | 20430 | |
c19d1205 | 20431 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 20432 | { |
c19d1205 ZW |
20433 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
20434 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20435 | _("invalid literal constant: pool needs to be closer")); | |
20436 | else | |
f9d4405b | 20437 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
20438 | (long) value); |
20439 | break; | |
b99bd4ef NC |
20440 | } |
20441 | ||
c19d1205 ZW |
20442 | newval = md_chars_to_number (buf, INSN_SIZE); |
20443 | newval &= 0xff7ff0f0; | |
20444 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
20445 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20446 | break; | |
b99bd4ef | 20447 | |
c19d1205 ZW |
20448 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
20449 | if (value < 0 || value > 1020 || value % 4 != 0) | |
20450 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20451 | _("bad immediate value for offset (%ld)"), (long) value); | |
20452 | value /= 4; | |
b99bd4ef | 20453 | |
c19d1205 | 20454 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
20455 | newval |= value; |
20456 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
20457 | break; | |
b99bd4ef | 20458 | |
c19d1205 ZW |
20459 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
20460 | /* This is a complicated relocation used for all varieties of Thumb32 | |
20461 | load/store instruction with immediate offset: | |
20462 | ||
20463 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
20464 | *4, optional writeback(W) | |
20465 | (doubleword load/store) | |
20466 | ||
20467 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
20468 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
20469 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
20470 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
20471 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
20472 | ||
20473 | Uppercase letters indicate bits that are already encoded at | |
20474 | this point. Lowercase letters are our problem. For the | |
20475 | second block of instructions, the secondary opcode nybble | |
20476 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
20477 | a PC-relative operation. */ | |
20478 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20479 | newval <<= 16; | |
20480 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 20481 | |
c19d1205 | 20482 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 20483 | { |
c19d1205 ZW |
20484 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
20485 | if (value >= 0) | |
20486 | newval |= (1 << 23); | |
20487 | else | |
20488 | value = -value; | |
20489 | if (value % 4 != 0) | |
20490 | { | |
20491 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20492 | _("offset not a multiple of 4")); | |
20493 | break; | |
20494 | } | |
20495 | value /= 4; | |
216d22bc | 20496 | if (value > 0xff) |
c19d1205 ZW |
20497 | { |
20498 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20499 | _("offset out of range")); | |
20500 | break; | |
20501 | } | |
20502 | newval &= ~0xff; | |
b99bd4ef | 20503 | } |
c19d1205 | 20504 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 20505 | { |
c19d1205 ZW |
20506 | /* PC-relative, 12-bit offset. */ |
20507 | if (value >= 0) | |
20508 | newval |= (1 << 23); | |
20509 | else | |
20510 | value = -value; | |
216d22bc | 20511 | if (value > 0xfff) |
c19d1205 ZW |
20512 | { |
20513 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20514 | _("offset out of range")); | |
20515 | break; | |
20516 | } | |
20517 | newval &= ~0xfff; | |
b99bd4ef | 20518 | } |
c19d1205 | 20519 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 20520 | { |
c19d1205 ZW |
20521 | /* Writeback: 8-bit, +/- offset. */ |
20522 | if (value >= 0) | |
20523 | newval |= (1 << 9); | |
20524 | else | |
20525 | value = -value; | |
216d22bc | 20526 | if (value > 0xff) |
c19d1205 ZW |
20527 | { |
20528 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20529 | _("offset out of range")); | |
20530 | break; | |
20531 | } | |
20532 | newval &= ~0xff; | |
b99bd4ef | 20533 | } |
c19d1205 | 20534 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 20535 | { |
c19d1205 | 20536 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 20537 | if (value < 0 || value > 0xff) |
b99bd4ef | 20538 | { |
c19d1205 ZW |
20539 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20540 | _("offset out of range")); | |
20541 | break; | |
b99bd4ef | 20542 | } |
c19d1205 ZW |
20543 | newval &= ~0xff; |
20544 | newval |= value; | |
b99bd4ef NC |
20545 | } |
20546 | else | |
b99bd4ef | 20547 | { |
c19d1205 ZW |
20548 | /* Positive 12-bit or negative 8-bit offset. */ |
20549 | int limit; | |
20550 | if (value >= 0) | |
b99bd4ef | 20551 | { |
c19d1205 ZW |
20552 | newval |= (1 << 23); |
20553 | limit = 0xfff; | |
20554 | } | |
20555 | else | |
20556 | { | |
20557 | value = -value; | |
20558 | limit = 0xff; | |
20559 | } | |
20560 | if (value > limit) | |
20561 | { | |
20562 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20563 | _("offset out of range")); | |
20564 | break; | |
b99bd4ef | 20565 | } |
c19d1205 | 20566 | newval &= ~limit; |
b99bd4ef | 20567 | } |
b99bd4ef | 20568 | |
c19d1205 ZW |
20569 | newval |= value; |
20570 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
20571 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
20572 | break; | |
404ff6b5 | 20573 | |
c19d1205 ZW |
20574 | case BFD_RELOC_ARM_SHIFT_IMM: |
20575 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20576 | if (((unsigned long) value) > 32 | |
20577 | || (value == 32 | |
20578 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
20579 | { | |
20580 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20581 | _("shift expression is too large")); | |
20582 | break; | |
20583 | } | |
404ff6b5 | 20584 | |
c19d1205 ZW |
20585 | if (value == 0) |
20586 | /* Shifts of zero must be done as lsl. */ | |
20587 | newval &= ~0x60; | |
20588 | else if (value == 32) | |
20589 | value = 0; | |
20590 | newval &= 0xfffff07f; | |
20591 | newval |= (value & 0x1f) << 7; | |
20592 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20593 | break; | |
404ff6b5 | 20594 | |
c19d1205 | 20595 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 20596 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 20597 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 20598 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
20599 | /* We claim that this fixup has been processed here, |
20600 | even if in fact we generate an error because we do | |
20601 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20602 | fixP->fx_done = 1; | |
404ff6b5 | 20603 | |
c19d1205 ZW |
20604 | if (fixP->fx_addsy |
20605 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
20606 | { | |
20607 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20608 | _("undefined symbol %s used as an immediate value"), | |
20609 | S_GET_NAME (fixP->fx_addsy)); | |
20610 | break; | |
20611 | } | |
404ff6b5 | 20612 | |
c19d1205 ZW |
20613 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20614 | newval <<= 16; | |
20615 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 20616 | |
16805f35 PB |
20617 | newimm = FAIL; |
20618 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
20619 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
20620 | { |
20621 | newimm = encode_thumb32_immediate (value); | |
20622 | if (newimm == (unsigned int) FAIL) | |
20623 | newimm = thumb32_negate_data_op (&newval, value); | |
20624 | } | |
16805f35 PB |
20625 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
20626 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 20627 | { |
16805f35 PB |
20628 | /* Turn add/sum into addw/subw. */ |
20629 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
20630 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
20631 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
20632 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 20633 | { |
40f246e3 NC |
20634 | /* 12 bit immediate for addw/subw. */ |
20635 | if (value < 0) | |
20636 | { | |
20637 | value = -value; | |
20638 | newval ^= 0x00a00000; | |
20639 | } | |
20640 | if (value > 0xfff) | |
20641 | newimm = (unsigned int) FAIL; | |
20642 | else | |
20643 | newimm = value; | |
e9f89963 | 20644 | } |
92e90b6e | 20645 | } |
cc8a6dd0 | 20646 | |
c19d1205 | 20647 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 20648 | { |
c19d1205 ZW |
20649 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20650 | _("invalid constant (%lx) after fixup"), | |
20651 | (unsigned long) value); | |
20652 | break; | |
3631a3c8 NC |
20653 | } |
20654 | ||
c19d1205 ZW |
20655 | newval |= (newimm & 0x800) << 15; |
20656 | newval |= (newimm & 0x700) << 4; | |
20657 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 20658 | |
c19d1205 ZW |
20659 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
20660 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
20661 | break; | |
a737bd4d | 20662 | |
3eb17e6b | 20663 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
20664 | if (((unsigned long) value) > 0xffff) |
20665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 20666 | _("invalid smc expression")); |
2fc8bdac | 20667 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20668 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
20669 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20670 | break; | |
a737bd4d | 20671 | |
90ec0d68 MGD |
20672 | case BFD_RELOC_ARM_HVC: |
20673 | if (((unsigned long) value) > 0xffff) | |
20674 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20675 | _("invalid hvc expression")); | |
20676 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20677 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
20678 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20679 | break; | |
20680 | ||
c19d1205 | 20681 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 20682 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
20683 | { |
20684 | if (((unsigned long) value) > 0xff) | |
20685 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20686 | _("invalid swi expression")); | |
2fc8bdac | 20687 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
20688 | newval |= value; |
20689 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20690 | } | |
20691 | else | |
20692 | { | |
20693 | if (((unsigned long) value) > 0x00ffffff) | |
20694 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20695 | _("invalid swi expression")); | |
2fc8bdac | 20696 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20697 | newval |= value; |
20698 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20699 | } | |
20700 | break; | |
a737bd4d | 20701 | |
c19d1205 ZW |
20702 | case BFD_RELOC_ARM_MULTI: |
20703 | if (((unsigned long) value) > 0xffff) | |
20704 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20705 | _("invalid expression in load/store multiple")); | |
20706 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
20707 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20708 | break; | |
a737bd4d | 20709 | |
c19d1205 | 20710 | #ifdef OBJ_ELF |
39b41c9c | 20711 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
20712 | |
20713 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
20714 | && fixP->fx_addsy | |
34e77a92 | 20715 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20716 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20717 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20718 | /* Flip the bl to blx. This is a simple flip | |
20719 | bit here because we generate PCREL_CALL for | |
20720 | unconditional bls. */ | |
20721 | { | |
20722 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20723 | newval = newval | 0x10000000; | |
20724 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20725 | temp = 1; | |
20726 | fixP->fx_done = 1; | |
20727 | } | |
39b41c9c PB |
20728 | else |
20729 | temp = 3; | |
20730 | goto arm_branch_common; | |
20731 | ||
20732 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
20733 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20734 | && fixP->fx_addsy | |
34e77a92 | 20735 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20736 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20737 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20738 | { | |
20739 | /* This would map to a bl<cond>, b<cond>, | |
20740 | b<always> to a Thumb function. We | |
20741 | need to force a relocation for this particular | |
20742 | case. */ | |
20743 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20744 | fixP->fx_done = 0; | |
20745 | } | |
20746 | ||
2fc8bdac | 20747 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20748 | #endif |
39b41c9c PB |
20749 | case BFD_RELOC_ARM_PCREL_BRANCH: |
20750 | temp = 3; | |
20751 | goto arm_branch_common; | |
a737bd4d | 20752 | |
39b41c9c | 20753 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 20754 | |
39b41c9c | 20755 | temp = 1; |
267bf995 RR |
20756 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20757 | && fixP->fx_addsy | |
34e77a92 | 20758 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20759 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20760 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
20761 | { | |
20762 | /* Flip the blx to a bl and warn. */ | |
20763 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20764 | newval = 0xeb000000; | |
20765 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20766 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
20767 | name); | |
20768 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20769 | temp = 3; | |
20770 | fixP->fx_done = 1; | |
20771 | } | |
20772 | ||
20773 | #ifdef OBJ_ELF | |
20774 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
20775 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
20776 | #endif | |
20777 | ||
39b41c9c | 20778 | arm_branch_common: |
c19d1205 | 20779 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
20780 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
20781 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
20782 | also be be clear. */ | |
20783 | if (value & temp) | |
c19d1205 | 20784 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
20785 | _("misaligned branch destination")); |
20786 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
20787 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
20788 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20789 | _("branch out of range")); | |
a737bd4d | 20790 | |
2fc8bdac | 20791 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20792 | { |
2fc8bdac ZW |
20793 | newval = md_chars_to_number (buf, INSN_SIZE); |
20794 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
20795 | /* Set the H bit on BLX instructions. */ |
20796 | if (temp == 1) | |
20797 | { | |
20798 | if (value & 2) | |
20799 | newval |= 0x01000000; | |
20800 | else | |
20801 | newval &= ~0x01000000; | |
20802 | } | |
2fc8bdac | 20803 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 20804 | } |
c19d1205 | 20805 | break; |
a737bd4d | 20806 | |
25fe350b MS |
20807 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
20808 | /* CBZ can only branch forward. */ | |
a737bd4d | 20809 | |
738755b0 MS |
20810 | /* Attempts to use CBZ to branch to the next instruction |
20811 | (which, strictly speaking, are prohibited) will be turned into | |
20812 | no-ops. | |
20813 | ||
20814 | FIXME: It may be better to remove the instruction completely and | |
20815 | perform relaxation. */ | |
20816 | if (value == -2) | |
2fc8bdac ZW |
20817 | { |
20818 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 20819 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
20820 | md_number_to_chars (buf, newval, THUMB_SIZE); |
20821 | } | |
738755b0 MS |
20822 | else |
20823 | { | |
20824 | if (value & ~0x7e) | |
20825 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20826 | _("branch out of range")); | |
20827 | ||
20828 | if (fixP->fx_done || !seg->use_rela_p) | |
20829 | { | |
20830 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20831 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
20832 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20833 | } | |
20834 | } | |
c19d1205 | 20835 | break; |
a737bd4d | 20836 | |
c19d1205 | 20837 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
20838 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
20839 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20840 | _("branch out of range")); | |
a737bd4d | 20841 | |
2fc8bdac ZW |
20842 | if (fixP->fx_done || !seg->use_rela_p) |
20843 | { | |
20844 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20845 | newval |= (value & 0x1ff) >> 1; | |
20846 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20847 | } | |
c19d1205 | 20848 | break; |
a737bd4d | 20849 | |
c19d1205 | 20850 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
20851 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
20852 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20853 | _("branch out of range")); | |
a737bd4d | 20854 | |
2fc8bdac ZW |
20855 | if (fixP->fx_done || !seg->use_rela_p) |
20856 | { | |
20857 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20858 | newval |= (value & 0xfff) >> 1; | |
20859 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20860 | } | |
c19d1205 | 20861 | break; |
a737bd4d | 20862 | |
c19d1205 | 20863 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
20864 | if (fixP->fx_addsy |
20865 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20866 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20867 | && ARM_IS_FUNC (fixP->fx_addsy) |
20868 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20869 | { | |
20870 | /* Force a relocation for a branch 20 bits wide. */ | |
20871 | fixP->fx_done = 0; | |
20872 | } | |
2fc8bdac ZW |
20873 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
20874 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20875 | _("conditional branch out of range")); | |
404ff6b5 | 20876 | |
2fc8bdac ZW |
20877 | if (fixP->fx_done || !seg->use_rela_p) |
20878 | { | |
20879 | offsetT newval2; | |
20880 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 20881 | |
2fc8bdac ZW |
20882 | S = (value & 0x00100000) >> 20; |
20883 | J2 = (value & 0x00080000) >> 19; | |
20884 | J1 = (value & 0x00040000) >> 18; | |
20885 | hi = (value & 0x0003f000) >> 12; | |
20886 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 20887 | |
2fc8bdac ZW |
20888 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20889 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20890 | newval |= (S << 10) | hi; | |
20891 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
20892 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20893 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20894 | } | |
c19d1205 | 20895 | break; |
6c43fab6 | 20896 | |
c19d1205 | 20897 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
20898 | |
20899 | /* If there is a blx from a thumb state function to | |
20900 | another thumb function flip this to a bl and warn | |
20901 | about it. */ | |
20902 | ||
20903 | if (fixP->fx_addsy | |
34e77a92 | 20904 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20905 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20906 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20907 | { | |
20908 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20909 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20910 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
20911 | name); | |
20912 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20913 | newval = newval | 0x1000; | |
20914 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20915 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20916 | fixP->fx_done = 1; | |
20917 | } | |
20918 | ||
20919 | ||
20920 | goto thumb_bl_common; | |
20921 | ||
c19d1205 | 20922 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
20923 | |
20924 | /* A bl from Thumb state ISA to an internal ARM state function | |
20925 | is converted to a blx. */ | |
20926 | if (fixP->fx_addsy | |
20927 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20928 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20929 | && ARM_IS_FUNC (fixP->fx_addsy) |
20930 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20931 | { | |
20932 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20933 | newval = newval & ~0x1000; | |
20934 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
20935 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
20936 | fixP->fx_done = 1; | |
20937 | } | |
20938 | ||
20939 | thumb_bl_common: | |
20940 | ||
20941 | #ifdef OBJ_ELF | |
20942 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
20943 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
20944 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
20945 | #endif | |
20946 | ||
2fc8bdac ZW |
20947 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
20948 | /* For a BLX instruction, make sure that the relocation is rounded up | |
20949 | to a word boundary. This follows the semantics of the instruction | |
20950 | which specifies that bit 1 of the target address will come from bit | |
20951 | 1 of the base address. */ | |
20952 | value = (value + 1) & ~ 1; | |
404ff6b5 | 20953 | |
2fc8bdac | 20954 | |
4a42ebbc RR |
20955 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
20956 | { | |
20957 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
20958 | { | |
20959 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20960 | _("branch out of range")); | |
20961 | } | |
20962 | else if ((value & ~0x1ffffff) | |
20963 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
20964 | { | |
20965 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20966 | _("Thumb2 branch out of range")); | |
20967 | } | |
c19d1205 | 20968 | } |
4a42ebbc RR |
20969 | |
20970 | if (fixP->fx_done || !seg->use_rela_p) | |
20971 | encode_thumb2_b_bl_offset (buf, value); | |
20972 | ||
c19d1205 | 20973 | break; |
404ff6b5 | 20974 | |
c19d1205 | 20975 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
20976 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
20977 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20978 | _("branch out of range")); | |
6c43fab6 | 20979 | |
2fc8bdac | 20980 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 20981 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 20982 | |
2fc8bdac | 20983 | break; |
a737bd4d | 20984 | |
2fc8bdac ZW |
20985 | case BFD_RELOC_8: |
20986 | if (fixP->fx_done || !seg->use_rela_p) | |
20987 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 20988 | break; |
a737bd4d | 20989 | |
c19d1205 | 20990 | case BFD_RELOC_16: |
2fc8bdac | 20991 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20992 | md_number_to_chars (buf, value, 2); |
c19d1205 | 20993 | break; |
a737bd4d | 20994 | |
c19d1205 | 20995 | #ifdef OBJ_ELF |
0855e32b NS |
20996 | case BFD_RELOC_ARM_TLS_CALL: |
20997 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
20998 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
20999 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
21000 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21001 | break; | |
21002 | ||
21003 | case BFD_RELOC_ARM_TLS_GOTDESC: | |
c19d1205 ZW |
21004 | case BFD_RELOC_ARM_TLS_GD32: |
21005 | case BFD_RELOC_ARM_TLS_LE32: | |
21006 | case BFD_RELOC_ARM_TLS_IE32: | |
21007 | case BFD_RELOC_ARM_TLS_LDM32: | |
21008 | case BFD_RELOC_ARM_TLS_LDO32: | |
21009 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21010 | /* fall through */ | |
6c43fab6 | 21011 | |
c19d1205 ZW |
21012 | case BFD_RELOC_ARM_GOT32: |
21013 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
21014 | if (fixP->fx_done || !seg->use_rela_p) |
21015 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 21016 | break; |
b43420e6 NC |
21017 | |
21018 | case BFD_RELOC_ARM_GOT_PREL: | |
21019 | if (fixP->fx_done || !seg->use_rela_p) | |
21020 | md_number_to_chars (buf, value, 4); | |
21021 | break; | |
21022 | ||
9a6f4e97 NS |
21023 | case BFD_RELOC_ARM_TARGET2: |
21024 | /* TARGET2 is not partial-inplace, so we need to write the | |
21025 | addend here for REL targets, because it won't be written out | |
21026 | during reloc processing later. */ | |
21027 | if (fixP->fx_done || !seg->use_rela_p) | |
21028 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
21029 | break; | |
c19d1205 | 21030 | #endif |
6c43fab6 | 21031 | |
c19d1205 ZW |
21032 | case BFD_RELOC_RVA: |
21033 | case BFD_RELOC_32: | |
21034 | case BFD_RELOC_ARM_TARGET1: | |
21035 | case BFD_RELOC_ARM_ROSEGREL32: | |
21036 | case BFD_RELOC_ARM_SBREL32: | |
21037 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
21038 | #ifdef TE_PE |
21039 | case BFD_RELOC_32_SECREL: | |
21040 | #endif | |
2fc8bdac | 21041 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
21042 | #ifdef TE_WINCE |
21043 | /* For WinCE we only do this for pcrel fixups. */ | |
21044 | if (fixP->fx_done || fixP->fx_pcrel) | |
21045 | #endif | |
21046 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 21047 | break; |
6c43fab6 | 21048 | |
c19d1205 ZW |
21049 | #ifdef OBJ_ELF |
21050 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 21051 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
21052 | { |
21053 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
21054 | if ((value ^ (value >> 1)) & 0x40000000) | |
21055 | { | |
21056 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21057 | _("rel31 relocation overflow")); | |
21058 | } | |
21059 | newval |= value & 0x7fffffff; | |
21060 | md_number_to_chars (buf, newval, 4); | |
21061 | } | |
21062 | break; | |
c19d1205 | 21063 | #endif |
a737bd4d | 21064 | |
c19d1205 | 21065 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 21066 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
21067 | if (value < -1023 || value > 1023 || (value & 3)) |
21068 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21069 | _("co-processor offset out of range")); | |
21070 | cp_off_common: | |
21071 | sign = value >= 0; | |
21072 | if (value < 0) | |
21073 | value = -value; | |
8f06b2d8 PB |
21074 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21075 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21076 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21077 | else | |
21078 | newval = get_thumb32_insn (buf); | |
21079 | newval &= 0xff7fff00; | |
c19d1205 | 21080 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
8f06b2d8 PB |
21081 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21082 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21083 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21084 | else | |
21085 | put_thumb32_insn (buf, newval); | |
c19d1205 | 21086 | break; |
a737bd4d | 21087 | |
c19d1205 | 21088 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 21089 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
21090 | if (value < -255 || value > 255) |
21091 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21092 | _("co-processor offset out of range")); | |
df7849c5 | 21093 | value *= 4; |
c19d1205 | 21094 | goto cp_off_common; |
6c43fab6 | 21095 | |
c19d1205 ZW |
21096 | case BFD_RELOC_ARM_THUMB_OFFSET: |
21097 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21098 | /* Exactly what ranges, and where the offset is inserted depends | |
21099 | on the type of instruction, we can establish this from the | |
21100 | top 4 bits. */ | |
21101 | switch (newval >> 12) | |
21102 | { | |
21103 | case 4: /* PC load. */ | |
21104 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
21105 | forced to zero for these loads; md_pcrel_from has already | |
21106 | compensated for this. */ | |
21107 | if (value & 3) | |
21108 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21109 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
21110 | (((unsigned long) fixP->fx_frag->fr_address |
21111 | + (unsigned long) fixP->fx_where) & ~3) | |
21112 | + (unsigned long) value); | |
a737bd4d | 21113 | |
c19d1205 ZW |
21114 | if (value & ~0x3fc) |
21115 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21116 | _("invalid offset, value too big (0x%08lX)"), | |
21117 | (long) value); | |
a737bd4d | 21118 | |
c19d1205 ZW |
21119 | newval |= value >> 2; |
21120 | break; | |
a737bd4d | 21121 | |
c19d1205 ZW |
21122 | case 9: /* SP load/store. */ |
21123 | if (value & ~0x3fc) | |
21124 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21125 | _("invalid offset, value too big (0x%08lX)"), | |
21126 | (long) value); | |
21127 | newval |= value >> 2; | |
21128 | break; | |
6c43fab6 | 21129 | |
c19d1205 ZW |
21130 | case 6: /* Word load/store. */ |
21131 | if (value & ~0x7c) | |
21132 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21133 | _("invalid offset, value too big (0x%08lX)"), | |
21134 | (long) value); | |
21135 | newval |= value << 4; /* 6 - 2. */ | |
21136 | break; | |
a737bd4d | 21137 | |
c19d1205 ZW |
21138 | case 7: /* Byte load/store. */ |
21139 | if (value & ~0x1f) | |
21140 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21141 | _("invalid offset, value too big (0x%08lX)"), | |
21142 | (long) value); | |
21143 | newval |= value << 6; | |
21144 | break; | |
a737bd4d | 21145 | |
c19d1205 ZW |
21146 | case 8: /* Halfword load/store. */ |
21147 | if (value & ~0x3e) | |
21148 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21149 | _("invalid offset, value too big (0x%08lX)"), | |
21150 | (long) value); | |
21151 | newval |= value << 5; /* 6 - 1. */ | |
21152 | break; | |
a737bd4d | 21153 | |
c19d1205 ZW |
21154 | default: |
21155 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21156 | "Unable to process relocation for thumb opcode: %lx", | |
21157 | (unsigned long) newval); | |
21158 | break; | |
21159 | } | |
21160 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21161 | break; | |
a737bd4d | 21162 | |
c19d1205 ZW |
21163 | case BFD_RELOC_ARM_THUMB_ADD: |
21164 | /* This is a complicated relocation, since we use it for all of | |
21165 | the following immediate relocations: | |
a737bd4d | 21166 | |
c19d1205 ZW |
21167 | 3bit ADD/SUB |
21168 | 8bit ADD/SUB | |
21169 | 9bit ADD/SUB SP word-aligned | |
21170 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 21171 | |
c19d1205 ZW |
21172 | The type of instruction being processed is encoded in the |
21173 | instruction field: | |
a737bd4d | 21174 | |
c19d1205 ZW |
21175 | 0x8000 SUB |
21176 | 0x00F0 Rd | |
21177 | 0x000F Rs | |
21178 | */ | |
21179 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21180 | { | |
21181 | int rd = (newval >> 4) & 0xf; | |
21182 | int rs = newval & 0xf; | |
21183 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 21184 | |
c19d1205 ZW |
21185 | /* Check for HI regs, only very restricted cases allowed: |
21186 | Adjusting SP, and using PC or SP to get an address. */ | |
21187 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
21188 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
21189 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21190 | _("invalid Hi register with immediate")); | |
a737bd4d | 21191 | |
c19d1205 ZW |
21192 | /* If value is negative, choose the opposite instruction. */ |
21193 | if (value < 0) | |
21194 | { | |
21195 | value = -value; | |
21196 | subtract = !subtract; | |
21197 | if (value < 0) | |
21198 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21199 | _("immediate value out of range")); | |
21200 | } | |
a737bd4d | 21201 | |
c19d1205 ZW |
21202 | if (rd == REG_SP) |
21203 | { | |
21204 | if (value & ~0x1fc) | |
21205 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21206 | _("invalid immediate for stack address calculation")); | |
21207 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
21208 | newval |= value >> 2; | |
21209 | } | |
21210 | else if (rs == REG_PC || rs == REG_SP) | |
21211 | { | |
21212 | if (subtract || value & ~0x3fc) | |
21213 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21214 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
21215 | (unsigned long) value); | |
21216 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
21217 | newval |= rd << 8; | |
21218 | newval |= value >> 2; | |
21219 | } | |
21220 | else if (rs == rd) | |
21221 | { | |
21222 | if (value & ~0xff) | |
21223 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21224 | _("immediate value out of range")); | |
21225 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
21226 | newval |= (rd << 8) | value; | |
21227 | } | |
21228 | else | |
21229 | { | |
21230 | if (value & ~0x7) | |
21231 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21232 | _("immediate value out of range")); | |
21233 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
21234 | newval |= rd | (rs << 3) | (value << 6); | |
21235 | } | |
21236 | } | |
21237 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21238 | break; | |
a737bd4d | 21239 | |
c19d1205 ZW |
21240 | case BFD_RELOC_ARM_THUMB_IMM: |
21241 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21242 | if (value < 0 || value > 255) | |
21243 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 21244 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
21245 | (long) value); |
21246 | newval |= value; | |
21247 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21248 | break; | |
a737bd4d | 21249 | |
c19d1205 ZW |
21250 | case BFD_RELOC_ARM_THUMB_SHIFT: |
21251 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
21252 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
21253 | temp = newval & 0xf800; | |
21254 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
21255 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21256 | _("invalid shift value: %ld"), (long) value); | |
21257 | /* Shifts of zero must be encoded as LSL. */ | |
21258 | if (value == 0) | |
21259 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
21260 | /* Shifts of 32 are encoded as zero. */ | |
21261 | else if (value == 32) | |
21262 | value = 0; | |
21263 | newval |= value << 6; | |
21264 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21265 | break; | |
a737bd4d | 21266 | |
c19d1205 ZW |
21267 | case BFD_RELOC_VTABLE_INHERIT: |
21268 | case BFD_RELOC_VTABLE_ENTRY: | |
21269 | fixP->fx_done = 0; | |
21270 | return; | |
6c43fab6 | 21271 | |
b6895b4f PB |
21272 | case BFD_RELOC_ARM_MOVW: |
21273 | case BFD_RELOC_ARM_MOVT: | |
21274 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21275 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21276 | if (fixP->fx_done || !seg->use_rela_p) | |
21277 | { | |
21278 | /* REL format relocations are limited to a 16-bit addend. */ | |
21279 | if (!fixP->fx_done) | |
21280 | { | |
39623e12 | 21281 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 21282 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 21283 | _("offset out of range")); |
b6895b4f PB |
21284 | } |
21285 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21286 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21287 | { | |
21288 | value >>= 16; | |
21289 | } | |
21290 | ||
21291 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21292 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21293 | { | |
21294 | newval = get_thumb32_insn (buf); | |
21295 | newval &= 0xfbf08f00; | |
21296 | newval |= (value & 0xf000) << 4; | |
21297 | newval |= (value & 0x0800) << 15; | |
21298 | newval |= (value & 0x0700) << 4; | |
21299 | newval |= (value & 0x00ff); | |
21300 | put_thumb32_insn (buf, newval); | |
21301 | } | |
21302 | else | |
21303 | { | |
21304 | newval = md_chars_to_number (buf, 4); | |
21305 | newval &= 0xfff0f000; | |
21306 | newval |= value & 0x0fff; | |
21307 | newval |= (value & 0xf000) << 4; | |
21308 | md_number_to_chars (buf, newval, 4); | |
21309 | } | |
21310 | } | |
21311 | return; | |
21312 | ||
4962c51a MS |
21313 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21314 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21315 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21316 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21317 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21318 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21319 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21320 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21321 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21322 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 21323 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21324 | if (!seg->use_rela_p) |
21325 | { | |
21326 | bfd_vma insn; | |
21327 | bfd_vma encoded_addend; | |
21328 | bfd_vma addend_abs = abs (value); | |
21329 | ||
21330 | /* Check that the absolute value of the addend can be | |
21331 | expressed as an 8-bit constant plus a rotation. */ | |
21332 | encoded_addend = encode_arm_immediate (addend_abs); | |
21333 | if (encoded_addend == (unsigned int) FAIL) | |
21334 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21335 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 21336 | (unsigned long) addend_abs); |
4962c51a MS |
21337 | |
21338 | /* Extract the instruction. */ | |
21339 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21340 | ||
21341 | /* If the addend is positive, use an ADD instruction. | |
21342 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
21343 | insn &= 0xff1fffff; | |
21344 | if (value < 0) | |
21345 | insn |= 1 << 22; | |
21346 | else | |
21347 | insn |= 1 << 23; | |
21348 | ||
21349 | /* Place the encoded addend into the first 12 bits of the | |
21350 | instruction. */ | |
21351 | insn &= 0xfffff000; | |
21352 | insn |= encoded_addend; | |
5f4273c7 NC |
21353 | |
21354 | /* Update the instruction. */ | |
4962c51a MS |
21355 | md_number_to_chars (buf, insn, INSN_SIZE); |
21356 | } | |
21357 | break; | |
21358 | ||
21359 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21360 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21361 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21362 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21363 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21364 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 21365 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21366 | if (!seg->use_rela_p) |
21367 | { | |
21368 | bfd_vma insn; | |
21369 | bfd_vma addend_abs = abs (value); | |
21370 | ||
21371 | /* Check that the absolute value of the addend can be | |
21372 | encoded in 12 bits. */ | |
21373 | if (addend_abs >= 0x1000) | |
21374 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21375 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 21376 | (unsigned long) addend_abs); |
4962c51a MS |
21377 | |
21378 | /* Extract the instruction. */ | |
21379 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21380 | ||
21381 | /* If the addend is negative, clear bit 23 of the instruction. | |
21382 | Otherwise set it. */ | |
21383 | if (value < 0) | |
21384 | insn &= ~(1 << 23); | |
21385 | else | |
21386 | insn |= 1 << 23; | |
21387 | ||
21388 | /* Place the absolute value of the addend into the first 12 bits | |
21389 | of the instruction. */ | |
21390 | insn &= 0xfffff000; | |
21391 | insn |= addend_abs; | |
5f4273c7 NC |
21392 | |
21393 | /* Update the instruction. */ | |
4962c51a MS |
21394 | md_number_to_chars (buf, insn, INSN_SIZE); |
21395 | } | |
21396 | break; | |
21397 | ||
21398 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21399 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21400 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21401 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21402 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21403 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 21404 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21405 | if (!seg->use_rela_p) |
21406 | { | |
21407 | bfd_vma insn; | |
21408 | bfd_vma addend_abs = abs (value); | |
21409 | ||
21410 | /* Check that the absolute value of the addend can be | |
21411 | encoded in 8 bits. */ | |
21412 | if (addend_abs >= 0x100) | |
21413 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21414 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 21415 | (unsigned long) addend_abs); |
4962c51a MS |
21416 | |
21417 | /* Extract the instruction. */ | |
21418 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21419 | ||
21420 | /* If the addend is negative, clear bit 23 of the instruction. | |
21421 | Otherwise set it. */ | |
21422 | if (value < 0) | |
21423 | insn &= ~(1 << 23); | |
21424 | else | |
21425 | insn |= 1 << 23; | |
21426 | ||
21427 | /* Place the first four bits of the absolute value of the addend | |
21428 | into the first 4 bits of the instruction, and the remaining | |
21429 | four into bits 8 .. 11. */ | |
21430 | insn &= 0xfffff0f0; | |
21431 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
21432 | |
21433 | /* Update the instruction. */ | |
4962c51a MS |
21434 | md_number_to_chars (buf, insn, INSN_SIZE); |
21435 | } | |
21436 | break; | |
21437 | ||
21438 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21439 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21440 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21441 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21442 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21443 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 21444 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21445 | if (!seg->use_rela_p) |
21446 | { | |
21447 | bfd_vma insn; | |
21448 | bfd_vma addend_abs = abs (value); | |
21449 | ||
21450 | /* Check that the absolute value of the addend is a multiple of | |
21451 | four and, when divided by four, fits in 8 bits. */ | |
21452 | if (addend_abs & 0x3) | |
21453 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21454 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 21455 | (unsigned long) addend_abs); |
4962c51a MS |
21456 | |
21457 | if ((addend_abs >> 2) > 0xff) | |
21458 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21459 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 21460 | (unsigned long) addend_abs); |
4962c51a MS |
21461 | |
21462 | /* Extract the instruction. */ | |
21463 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21464 | ||
21465 | /* If the addend is negative, clear bit 23 of the instruction. | |
21466 | Otherwise set it. */ | |
21467 | if (value < 0) | |
21468 | insn &= ~(1 << 23); | |
21469 | else | |
21470 | insn |= 1 << 23; | |
21471 | ||
21472 | /* Place the addend (divided by four) into the first eight | |
21473 | bits of the instruction. */ | |
21474 | insn &= 0xfffffff0; | |
21475 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
21476 | |
21477 | /* Update the instruction. */ | |
4962c51a MS |
21478 | md_number_to_chars (buf, insn, INSN_SIZE); |
21479 | } | |
21480 | break; | |
21481 | ||
845b51d6 PB |
21482 | case BFD_RELOC_ARM_V4BX: |
21483 | /* This will need to go in the object file. */ | |
21484 | fixP->fx_done = 0; | |
21485 | break; | |
21486 | ||
c19d1205 ZW |
21487 | case BFD_RELOC_UNUSED: |
21488 | default: | |
21489 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21490 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
21491 | } | |
6c43fab6 RE |
21492 | } |
21493 | ||
c19d1205 ZW |
21494 | /* Translate internal representation of relocation info to BFD target |
21495 | format. */ | |
a737bd4d | 21496 | |
c19d1205 | 21497 | arelent * |
00a97672 | 21498 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 21499 | { |
c19d1205 ZW |
21500 | arelent * reloc; |
21501 | bfd_reloc_code_real_type code; | |
a737bd4d | 21502 | |
21d799b5 | 21503 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 21504 | |
21d799b5 | 21505 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
21506 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
21507 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 21508 | |
2fc8bdac | 21509 | if (fixp->fx_pcrel) |
00a97672 RS |
21510 | { |
21511 | if (section->use_rela_p) | |
21512 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
21513 | else | |
21514 | fixp->fx_offset = reloc->address; | |
21515 | } | |
c19d1205 | 21516 | reloc->addend = fixp->fx_offset; |
a737bd4d | 21517 | |
c19d1205 | 21518 | switch (fixp->fx_r_type) |
a737bd4d | 21519 | { |
c19d1205 ZW |
21520 | case BFD_RELOC_8: |
21521 | if (fixp->fx_pcrel) | |
21522 | { | |
21523 | code = BFD_RELOC_8_PCREL; | |
21524 | break; | |
21525 | } | |
a737bd4d | 21526 | |
c19d1205 ZW |
21527 | case BFD_RELOC_16: |
21528 | if (fixp->fx_pcrel) | |
21529 | { | |
21530 | code = BFD_RELOC_16_PCREL; | |
21531 | break; | |
21532 | } | |
6c43fab6 | 21533 | |
c19d1205 ZW |
21534 | case BFD_RELOC_32: |
21535 | if (fixp->fx_pcrel) | |
21536 | { | |
21537 | code = BFD_RELOC_32_PCREL; | |
21538 | break; | |
21539 | } | |
a737bd4d | 21540 | |
b6895b4f PB |
21541 | case BFD_RELOC_ARM_MOVW: |
21542 | if (fixp->fx_pcrel) | |
21543 | { | |
21544 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
21545 | break; | |
21546 | } | |
21547 | ||
21548 | case BFD_RELOC_ARM_MOVT: | |
21549 | if (fixp->fx_pcrel) | |
21550 | { | |
21551 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
21552 | break; | |
21553 | } | |
21554 | ||
21555 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21556 | if (fixp->fx_pcrel) | |
21557 | { | |
21558 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
21559 | break; | |
21560 | } | |
21561 | ||
21562 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21563 | if (fixp->fx_pcrel) | |
21564 | { | |
21565 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
21566 | break; | |
21567 | } | |
21568 | ||
c19d1205 ZW |
21569 | case BFD_RELOC_NONE: |
21570 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
21571 | case BFD_RELOC_ARM_PCREL_BLX: | |
21572 | case BFD_RELOC_RVA: | |
21573 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21574 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21575 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21576 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21577 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21578 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
21579 | case BFD_RELOC_VTABLE_ENTRY: |
21580 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
21581 | #ifdef TE_PE |
21582 | case BFD_RELOC_32_SECREL: | |
21583 | #endif | |
c19d1205 ZW |
21584 | code = fixp->fx_r_type; |
21585 | break; | |
a737bd4d | 21586 | |
00adf2d4 JB |
21587 | case BFD_RELOC_THUMB_PCREL_BLX: |
21588 | #ifdef OBJ_ELF | |
21589 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21590 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21591 | else | |
21592 | #endif | |
21593 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
21594 | break; | |
21595 | ||
c19d1205 ZW |
21596 | case BFD_RELOC_ARM_LITERAL: |
21597 | case BFD_RELOC_ARM_HWLITERAL: | |
21598 | /* If this is called then the a literal has | |
21599 | been referenced across a section boundary. */ | |
21600 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21601 | _("literal referenced across section boundary")); | |
21602 | return NULL; | |
a737bd4d | 21603 | |
c19d1205 | 21604 | #ifdef OBJ_ELF |
0855e32b NS |
21605 | case BFD_RELOC_ARM_TLS_CALL: |
21606 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21607 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21608 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
21609 | case BFD_RELOC_ARM_GOT32: |
21610 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 21611 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
21612 | case BFD_RELOC_ARM_PLT32: |
21613 | case BFD_RELOC_ARM_TARGET1: | |
21614 | case BFD_RELOC_ARM_ROSEGREL32: | |
21615 | case BFD_RELOC_ARM_SBREL32: | |
21616 | case BFD_RELOC_ARM_PREL31: | |
21617 | case BFD_RELOC_ARM_TARGET2: | |
21618 | case BFD_RELOC_ARM_TLS_LE32: | |
21619 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
21620 | case BFD_RELOC_ARM_PCREL_CALL: |
21621 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
21622 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21623 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21624 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21625 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21626 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21627 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21628 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21629 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21630 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21631 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21632 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21633 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21634 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21635 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21636 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21637 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21638 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21639 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21640 | case BFD_RELOC_ARM_ALU_SB_G2: | |
21641 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21642 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21643 | case BFD_RELOC_ARM_LDR_SB_G2: | |
21644 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21645 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21646 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
21647 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21648 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21649 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 21650 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
21651 | code = fixp->fx_r_type; |
21652 | break; | |
a737bd4d | 21653 | |
0855e32b | 21654 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
21655 | case BFD_RELOC_ARM_TLS_GD32: |
21656 | case BFD_RELOC_ARM_TLS_IE32: | |
21657 | case BFD_RELOC_ARM_TLS_LDM32: | |
21658 | /* BFD will include the symbol's address in the addend. | |
21659 | But we don't want that, so subtract it out again here. */ | |
21660 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
21661 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
21662 | code = fixp->fx_r_type; | |
21663 | break; | |
21664 | #endif | |
a737bd4d | 21665 | |
c19d1205 ZW |
21666 | case BFD_RELOC_ARM_IMMEDIATE: |
21667 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21668 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
21669 | return NULL; | |
a737bd4d | 21670 | |
c19d1205 ZW |
21671 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21672 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21673 | _("ADRL used for a symbol not defined in the same file")); | |
21674 | return NULL; | |
a737bd4d | 21675 | |
c19d1205 | 21676 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
21677 | if (section->use_rela_p) |
21678 | { | |
21679 | code = fixp->fx_r_type; | |
21680 | break; | |
21681 | } | |
21682 | ||
c19d1205 ZW |
21683 | if (fixp->fx_addsy != NULL |
21684 | && !S_IS_DEFINED (fixp->fx_addsy) | |
21685 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 21686 | { |
c19d1205 ZW |
21687 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21688 | _("undefined local label `%s'"), | |
21689 | S_GET_NAME (fixp->fx_addsy)); | |
21690 | return NULL; | |
a737bd4d NC |
21691 | } |
21692 | ||
c19d1205 ZW |
21693 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21694 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
21695 | return NULL; | |
a737bd4d | 21696 | |
c19d1205 ZW |
21697 | default: |
21698 | { | |
21699 | char * type; | |
6c43fab6 | 21700 | |
c19d1205 ZW |
21701 | switch (fixp->fx_r_type) |
21702 | { | |
21703 | case BFD_RELOC_NONE: type = "NONE"; break; | |
21704 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
21705 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 21706 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
21707 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
21708 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
21709 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 21710 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 21711 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
21712 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
21713 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
21714 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
21715 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
21716 | default: type = _("<unknown>"); break; | |
21717 | } | |
21718 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21719 | _("cannot represent %s relocation in this object file format"), | |
21720 | type); | |
21721 | return NULL; | |
21722 | } | |
a737bd4d | 21723 | } |
6c43fab6 | 21724 | |
c19d1205 ZW |
21725 | #ifdef OBJ_ELF |
21726 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
21727 | && GOT_symbol | |
21728 | && fixp->fx_addsy == GOT_symbol) | |
21729 | { | |
21730 | code = BFD_RELOC_ARM_GOTPC; | |
21731 | reloc->addend = fixp->fx_offset = reloc->address; | |
21732 | } | |
21733 | #endif | |
6c43fab6 | 21734 | |
c19d1205 | 21735 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 21736 | |
c19d1205 ZW |
21737 | if (reloc->howto == NULL) |
21738 | { | |
21739 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21740 | _("cannot represent %s relocation in this object file format"), | |
21741 | bfd_get_reloc_code_name (code)); | |
21742 | return NULL; | |
21743 | } | |
6c43fab6 | 21744 | |
c19d1205 ZW |
21745 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
21746 | vtable entry to be used in the relocation's section offset. */ | |
21747 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
21748 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 21749 | |
c19d1205 | 21750 | return reloc; |
6c43fab6 RE |
21751 | } |
21752 | ||
c19d1205 | 21753 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 21754 | |
c19d1205 ZW |
21755 | void |
21756 | cons_fix_new_arm (fragS * frag, | |
21757 | int where, | |
21758 | int size, | |
21759 | expressionS * exp) | |
6c43fab6 | 21760 | { |
c19d1205 ZW |
21761 | bfd_reloc_code_real_type type; |
21762 | int pcrel = 0; | |
6c43fab6 | 21763 | |
c19d1205 ZW |
21764 | /* Pick a reloc. |
21765 | FIXME: @@ Should look at CPU word size. */ | |
21766 | switch (size) | |
21767 | { | |
21768 | case 1: | |
21769 | type = BFD_RELOC_8; | |
21770 | break; | |
21771 | case 2: | |
21772 | type = BFD_RELOC_16; | |
21773 | break; | |
21774 | case 4: | |
21775 | default: | |
21776 | type = BFD_RELOC_32; | |
21777 | break; | |
21778 | case 8: | |
21779 | type = BFD_RELOC_64; | |
21780 | break; | |
21781 | } | |
6c43fab6 | 21782 | |
f0927246 NC |
21783 | #ifdef TE_PE |
21784 | if (exp->X_op == O_secrel) | |
21785 | { | |
21786 | exp->X_op = O_symbol; | |
21787 | type = BFD_RELOC_32_SECREL; | |
21788 | } | |
21789 | #endif | |
21790 | ||
c19d1205 ZW |
21791 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
21792 | } | |
6c43fab6 | 21793 | |
4343666d | 21794 | #if defined (OBJ_COFF) |
c19d1205 ZW |
21795 | void |
21796 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 21797 | { |
c19d1205 ZW |
21798 | /* If the destination of the branch is a defined symbol which does not have |
21799 | the THUMB_FUNC attribute, then we must be calling a function which has | |
21800 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
21801 | function and change the branch to refer to that function instead. */ | |
21802 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
21803 | && fixP->fx_addsy != NULL | |
21804 | && S_IS_DEFINED (fixP->fx_addsy) | |
21805 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 21806 | { |
c19d1205 | 21807 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 21808 | } |
c19d1205 ZW |
21809 | } |
21810 | #endif | |
6c43fab6 | 21811 | |
267bf995 | 21812 | |
c19d1205 ZW |
21813 | int |
21814 | arm_force_relocation (struct fix * fixp) | |
21815 | { | |
21816 | #if defined (OBJ_COFF) && defined (TE_PE) | |
21817 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
21818 | return 1; | |
21819 | #endif | |
6c43fab6 | 21820 | |
267bf995 RR |
21821 | /* In case we have a call or a branch to a function in ARM ISA mode from |
21822 | a thumb function or vice-versa force the relocation. These relocations | |
21823 | are cleared off for some cores that might have blx and simple transformations | |
21824 | are possible. */ | |
21825 | ||
21826 | #ifdef OBJ_ELF | |
21827 | switch (fixp->fx_r_type) | |
21828 | { | |
21829 | case BFD_RELOC_ARM_PCREL_JUMP: | |
21830 | case BFD_RELOC_ARM_PCREL_CALL: | |
21831 | case BFD_RELOC_THUMB_PCREL_BLX: | |
21832 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
21833 | return 1; | |
21834 | break; | |
21835 | ||
21836 | case BFD_RELOC_ARM_PCREL_BLX: | |
21837 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
21838 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21839 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21840 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
21841 | return 1; | |
21842 | break; | |
21843 | ||
21844 | default: | |
21845 | break; | |
21846 | } | |
21847 | #endif | |
21848 | ||
c19d1205 ZW |
21849 | /* Resolve these relocations even if the symbol is extern or weak. */ |
21850 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
21851 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 | 21852 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
16805f35 | 21853 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
21854 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
21855 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
21856 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 21857 | return 0; |
a737bd4d | 21858 | |
4962c51a MS |
21859 | /* Always leave these relocations for the linker. */ |
21860 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21861 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21862 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
21863 | return 1; | |
21864 | ||
f0291e4c PB |
21865 | /* Always generate relocations against function symbols. */ |
21866 | if (fixp->fx_r_type == BFD_RELOC_32 | |
21867 | && fixp->fx_addsy | |
21868 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
21869 | return 1; | |
21870 | ||
c19d1205 | 21871 | return generic_force_reloc (fixp); |
404ff6b5 AH |
21872 | } |
21873 | ||
0ffdc86c | 21874 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
21875 | /* Relocations against function names must be left unadjusted, |
21876 | so that the linker can use this information to generate interworking | |
21877 | stubs. The MIPS version of this function | |
c19d1205 ZW |
21878 | also prevents relocations that are mips-16 specific, but I do not |
21879 | know why it does this. | |
404ff6b5 | 21880 | |
c19d1205 ZW |
21881 | FIXME: |
21882 | There is one other problem that ought to be addressed here, but | |
21883 | which currently is not: Taking the address of a label (rather | |
21884 | than a function) and then later jumping to that address. Such | |
21885 | addresses also ought to have their bottom bit set (assuming that | |
21886 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 21887 | |
c19d1205 ZW |
21888 | bfd_boolean |
21889 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 21890 | { |
c19d1205 ZW |
21891 | if (fixP->fx_addsy == NULL) |
21892 | return 1; | |
404ff6b5 | 21893 | |
e28387c3 PB |
21894 | /* Preserve relocations against symbols with function type. */ |
21895 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 21896 | return FALSE; |
e28387c3 | 21897 | |
c19d1205 ZW |
21898 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
21899 | && fixP->fx_subsy == NULL) | |
c921be7d | 21900 | return FALSE; |
a737bd4d | 21901 | |
c19d1205 ZW |
21902 | /* We need the symbol name for the VTABLE entries. */ |
21903 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
21904 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 21905 | return FALSE; |
404ff6b5 | 21906 | |
c19d1205 ZW |
21907 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
21908 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
21909 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
21910 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
21911 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
21912 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
21913 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
21914 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
21915 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
21916 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
21917 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
21918 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
21919 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
21920 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 21921 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 21922 | return FALSE; |
a737bd4d | 21923 | |
4962c51a MS |
21924 | /* Similarly for group relocations. */ |
21925 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21926 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21927 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 21928 | return FALSE; |
4962c51a | 21929 | |
79947c54 CD |
21930 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
21931 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
21932 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21933 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
21934 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
21935 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21936 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
21937 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
21938 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 21939 | return FALSE; |
79947c54 | 21940 | |
c921be7d | 21941 | return TRUE; |
a737bd4d | 21942 | } |
0ffdc86c NC |
21943 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
21944 | ||
21945 | #ifdef OBJ_ELF | |
404ff6b5 | 21946 | |
c19d1205 ZW |
21947 | const char * |
21948 | elf32_arm_target_format (void) | |
404ff6b5 | 21949 | { |
c19d1205 ZW |
21950 | #ifdef TE_SYMBIAN |
21951 | return (target_big_endian | |
21952 | ? "elf32-bigarm-symbian" | |
21953 | : "elf32-littlearm-symbian"); | |
21954 | #elif defined (TE_VXWORKS) | |
21955 | return (target_big_endian | |
21956 | ? "elf32-bigarm-vxworks" | |
21957 | : "elf32-littlearm-vxworks"); | |
21958 | #else | |
21959 | if (target_big_endian) | |
21960 | return "elf32-bigarm"; | |
21961 | else | |
21962 | return "elf32-littlearm"; | |
21963 | #endif | |
404ff6b5 AH |
21964 | } |
21965 | ||
c19d1205 ZW |
21966 | void |
21967 | armelf_frob_symbol (symbolS * symp, | |
21968 | int * puntp) | |
404ff6b5 | 21969 | { |
c19d1205 ZW |
21970 | elf_frob_symbol (symp, puntp); |
21971 | } | |
21972 | #endif | |
404ff6b5 | 21973 | |
c19d1205 | 21974 | /* MD interface: Finalization. */ |
a737bd4d | 21975 | |
c19d1205 ZW |
21976 | void |
21977 | arm_cleanup (void) | |
21978 | { | |
21979 | literal_pool * pool; | |
a737bd4d | 21980 | |
e07e6e58 NC |
21981 | /* Ensure that all the IT blocks are properly closed. */ |
21982 | check_it_blocks_finished (); | |
21983 | ||
c19d1205 ZW |
21984 | for (pool = list_of_pools; pool; pool = pool->next) |
21985 | { | |
5f4273c7 | 21986 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
21987 | subseg_set (pool->section, pool->sub_section); |
21988 | #ifdef OBJ_ELF | |
21989 | arm_elf_change_section (); | |
21990 | #endif | |
21991 | s_ltorg (0); | |
21992 | } | |
404ff6b5 AH |
21993 | } |
21994 | ||
cd000bff DJ |
21995 | #ifdef OBJ_ELF |
21996 | /* Remove any excess mapping symbols generated for alignment frags in | |
21997 | SEC. We may have created a mapping symbol before a zero byte | |
21998 | alignment; remove it if there's a mapping symbol after the | |
21999 | alignment. */ | |
22000 | static void | |
22001 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
22002 | void *dummy ATTRIBUTE_UNUSED) | |
22003 | { | |
22004 | segment_info_type *seginfo = seg_info (sec); | |
22005 | fragS *fragp; | |
22006 | ||
22007 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
22008 | return; | |
22009 | ||
22010 | for (fragp = seginfo->frchainP->frch_root; | |
22011 | fragp != NULL; | |
22012 | fragp = fragp->fr_next) | |
22013 | { | |
22014 | symbolS *sym = fragp->tc_frag_data.last_map; | |
22015 | fragS *next = fragp->fr_next; | |
22016 | ||
22017 | /* Variable-sized frags have been converted to fixed size by | |
22018 | this point. But if this was variable-sized to start with, | |
22019 | there will be a fixed-size frag after it. So don't handle | |
22020 | next == NULL. */ | |
22021 | if (sym == NULL || next == NULL) | |
22022 | continue; | |
22023 | ||
22024 | if (S_GET_VALUE (sym) < next->fr_address) | |
22025 | /* Not at the end of this frag. */ | |
22026 | continue; | |
22027 | know (S_GET_VALUE (sym) == next->fr_address); | |
22028 | ||
22029 | do | |
22030 | { | |
22031 | if (next->tc_frag_data.first_map != NULL) | |
22032 | { | |
22033 | /* Next frag starts with a mapping symbol. Discard this | |
22034 | one. */ | |
22035 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22036 | break; | |
22037 | } | |
22038 | ||
22039 | if (next->fr_next == NULL) | |
22040 | { | |
22041 | /* This mapping symbol is at the end of the section. Discard | |
22042 | it. */ | |
22043 | know (next->fr_fix == 0 && next->fr_var == 0); | |
22044 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22045 | break; | |
22046 | } | |
22047 | ||
22048 | /* As long as we have empty frags without any mapping symbols, | |
22049 | keep looking. */ | |
22050 | /* If the next frag is non-empty and does not start with a | |
22051 | mapping symbol, then this mapping symbol is required. */ | |
22052 | if (next->fr_address != next->fr_next->fr_address) | |
22053 | break; | |
22054 | ||
22055 | next = next->fr_next; | |
22056 | } | |
22057 | while (next != NULL); | |
22058 | } | |
22059 | } | |
22060 | #endif | |
22061 | ||
c19d1205 ZW |
22062 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
22063 | ARM ones. */ | |
404ff6b5 | 22064 | |
c19d1205 ZW |
22065 | void |
22066 | arm_adjust_symtab (void) | |
404ff6b5 | 22067 | { |
c19d1205 ZW |
22068 | #ifdef OBJ_COFF |
22069 | symbolS * sym; | |
404ff6b5 | 22070 | |
c19d1205 ZW |
22071 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
22072 | { | |
22073 | if (ARM_IS_THUMB (sym)) | |
22074 | { | |
22075 | if (THUMB_IS_FUNC (sym)) | |
22076 | { | |
22077 | /* Mark the symbol as a Thumb function. */ | |
22078 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
22079 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
22080 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 22081 | |
c19d1205 ZW |
22082 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
22083 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
22084 | else | |
22085 | as_bad (_("%s: unexpected function type: %d"), | |
22086 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
22087 | } | |
22088 | else switch (S_GET_STORAGE_CLASS (sym)) | |
22089 | { | |
22090 | case C_EXT: | |
22091 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
22092 | break; | |
22093 | case C_STAT: | |
22094 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
22095 | break; | |
22096 | case C_LABEL: | |
22097 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
22098 | break; | |
22099 | default: | |
22100 | /* Do nothing. */ | |
22101 | break; | |
22102 | } | |
22103 | } | |
a737bd4d | 22104 | |
c19d1205 ZW |
22105 | if (ARM_IS_INTERWORK (sym)) |
22106 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 22107 | } |
c19d1205 ZW |
22108 | #endif |
22109 | #ifdef OBJ_ELF | |
22110 | symbolS * sym; | |
22111 | char bind; | |
404ff6b5 | 22112 | |
c19d1205 | 22113 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 22114 | { |
c19d1205 ZW |
22115 | if (ARM_IS_THUMB (sym)) |
22116 | { | |
22117 | elf_symbol_type * elf_sym; | |
404ff6b5 | 22118 | |
c19d1205 ZW |
22119 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
22120 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 22121 | |
b0796911 PB |
22122 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
22123 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
22124 | { |
22125 | /* If it's a .thumb_func, declare it as so, | |
22126 | otherwise tag label as .code 16. */ | |
22127 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
22128 | elf_sym->internal_elf_sym.st_target_internal |
22129 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 22130 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
22131 | elf_sym->internal_elf_sym.st_info = |
22132 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
22133 | } | |
22134 | } | |
22135 | } | |
cd000bff DJ |
22136 | |
22137 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
22138 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
22139 | /* Now do generic ELF adjustments. */ |
22140 | elf_adjust_symtab (); | |
c19d1205 | 22141 | #endif |
404ff6b5 AH |
22142 | } |
22143 | ||
c19d1205 | 22144 | /* MD interface: Initialization. */ |
404ff6b5 | 22145 | |
a737bd4d | 22146 | static void |
c19d1205 | 22147 | set_constant_flonums (void) |
a737bd4d | 22148 | { |
c19d1205 | 22149 | int i; |
404ff6b5 | 22150 | |
c19d1205 ZW |
22151 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
22152 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
22153 | abort (); | |
a737bd4d | 22154 | } |
404ff6b5 | 22155 | |
3e9e4fcf JB |
22156 | /* Auto-select Thumb mode if it's the only available instruction set for the |
22157 | given architecture. */ | |
22158 | ||
22159 | static void | |
22160 | autoselect_thumb_from_cpu_variant (void) | |
22161 | { | |
22162 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
22163 | opcode_select (16); | |
22164 | } | |
22165 | ||
c19d1205 ZW |
22166 | void |
22167 | md_begin (void) | |
a737bd4d | 22168 | { |
c19d1205 ZW |
22169 | unsigned mach; |
22170 | unsigned int i; | |
404ff6b5 | 22171 | |
c19d1205 ZW |
22172 | if ( (arm_ops_hsh = hash_new ()) == NULL |
22173 | || (arm_cond_hsh = hash_new ()) == NULL | |
22174 | || (arm_shift_hsh = hash_new ()) == NULL | |
22175 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 22176 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 22177 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
22178 | || (arm_reloc_hsh = hash_new ()) == NULL |
22179 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
22180 | as_fatal (_("virtual memory exhausted")); |
22181 | ||
22182 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 22183 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 22184 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 22185 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 22186 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 22187 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 22188 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 22189 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 22190 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
22191 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
22192 | (void *) (v7m_psrs + i)); | |
c19d1205 | 22193 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 22194 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
22195 | for (i = 0; |
22196 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
22197 | i++) | |
d3ce72d0 | 22198 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 22199 | (void *) (barrier_opt_names + i)); |
c19d1205 ZW |
22200 | #ifdef OBJ_ELF |
22201 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
5a49b8ac | 22202 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); |
c19d1205 ZW |
22203 | #endif |
22204 | ||
22205 | set_constant_flonums (); | |
404ff6b5 | 22206 | |
c19d1205 ZW |
22207 | /* Set the cpu variant based on the command-line options. We prefer |
22208 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
22209 | -mfpu= over any other way of setting the floating point unit. | |
22210 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 22211 | if (legacy_cpu) |
404ff6b5 | 22212 | { |
e74cfd16 | 22213 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
22214 | as_bad (_("use of old and new-style options to set CPU type")); |
22215 | ||
22216 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 22217 | } |
e74cfd16 | 22218 | else if (!mcpu_cpu_opt) |
c19d1205 | 22219 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 22220 | |
e74cfd16 | 22221 | if (legacy_fpu) |
c19d1205 | 22222 | { |
e74cfd16 | 22223 | if (mfpu_opt) |
c19d1205 | 22224 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
22225 | |
22226 | mfpu_opt = legacy_fpu; | |
22227 | } | |
e74cfd16 | 22228 | else if (!mfpu_opt) |
03b1477f | 22229 | { |
45eb4c1b NS |
22230 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
22231 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
22232 | /* Some environments specify a default FPU. If they don't, infer it |
22233 | from the processor. */ | |
e74cfd16 | 22234 | if (mcpu_fpu_opt) |
03b1477f RE |
22235 | mfpu_opt = mcpu_fpu_opt; |
22236 | else | |
22237 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 22238 | #else |
e74cfd16 | 22239 | mfpu_opt = &fpu_default; |
39c2da32 | 22240 | #endif |
03b1477f RE |
22241 | } |
22242 | ||
e74cfd16 | 22243 | if (!mfpu_opt) |
03b1477f | 22244 | { |
493cb6ef | 22245 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 22246 | mfpu_opt = &fpu_default; |
493cb6ef | 22247 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 22248 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 22249 | else |
e74cfd16 | 22250 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
22251 | } |
22252 | ||
ee065d83 | 22253 | #ifdef CPU_DEFAULT |
e74cfd16 | 22254 | if (!mcpu_cpu_opt) |
ee065d83 | 22255 | { |
e74cfd16 PB |
22256 | mcpu_cpu_opt = &cpu_default; |
22257 | selected_cpu = cpu_default; | |
ee065d83 | 22258 | } |
e74cfd16 PB |
22259 | #else |
22260 | if (mcpu_cpu_opt) | |
22261 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 22262 | else |
e74cfd16 | 22263 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 22264 | #endif |
03b1477f | 22265 | |
e74cfd16 | 22266 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 22267 | |
3e9e4fcf JB |
22268 | autoselect_thumb_from_cpu_variant (); |
22269 | ||
e74cfd16 | 22270 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 22271 | |
f17c130b | 22272 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 22273 | { |
7cc69913 NC |
22274 | unsigned int flags = 0; |
22275 | ||
22276 | #if defined OBJ_ELF | |
22277 | flags = meabi_flags; | |
d507cf36 PB |
22278 | |
22279 | switch (meabi_flags) | |
33a392fb | 22280 | { |
d507cf36 | 22281 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 22282 | #endif |
d507cf36 PB |
22283 | /* Set the flags in the private structure. */ |
22284 | if (uses_apcs_26) flags |= F_APCS26; | |
22285 | if (support_interwork) flags |= F_INTERWORK; | |
22286 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 22287 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 22288 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
22289 | flags |= F_SOFT_FLOAT; |
22290 | ||
d507cf36 PB |
22291 | switch (mfloat_abi_opt) |
22292 | { | |
22293 | case ARM_FLOAT_ABI_SOFT: | |
22294 | case ARM_FLOAT_ABI_SOFTFP: | |
22295 | flags |= F_SOFT_FLOAT; | |
22296 | break; | |
33a392fb | 22297 | |
d507cf36 PB |
22298 | case ARM_FLOAT_ABI_HARD: |
22299 | if (flags & F_SOFT_FLOAT) | |
22300 | as_bad (_("hard-float conflicts with specified fpu")); | |
22301 | break; | |
22302 | } | |
03b1477f | 22303 | |
e74cfd16 PB |
22304 | /* Using pure-endian doubles (even if soft-float). */ |
22305 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 22306 | flags |= F_VFP_FLOAT; |
f17c130b | 22307 | |
fde78edd | 22308 | #if defined OBJ_ELF |
e74cfd16 | 22309 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 22310 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
22311 | break; |
22312 | ||
8cb51566 | 22313 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 22314 | case EF_ARM_EABI_VER5: |
c19d1205 | 22315 | /* No additional flags to set. */ |
d507cf36 PB |
22316 | break; |
22317 | ||
22318 | default: | |
22319 | abort (); | |
22320 | } | |
7cc69913 | 22321 | #endif |
b99bd4ef NC |
22322 | bfd_set_private_flags (stdoutput, flags); |
22323 | ||
22324 | /* We have run out flags in the COFF header to encode the | |
22325 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 22326 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
22327 | if (atpcs) |
22328 | { | |
22329 | asection * sec; | |
22330 | ||
22331 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
22332 | ||
22333 | if (sec != NULL) | |
22334 | { | |
22335 | bfd_set_section_flags | |
22336 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
22337 | bfd_set_section_size (stdoutput, sec, 0); | |
22338 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
22339 | } | |
22340 | } | |
7cc69913 | 22341 | } |
f17c130b | 22342 | #endif |
b99bd4ef NC |
22343 | |
22344 | /* Record the CPU type as well. */ | |
2d447fca JM |
22345 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
22346 | mach = bfd_mach_arm_iWMMXt2; | |
22347 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 22348 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 22349 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 22350 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 22351 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 22352 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 22353 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 22354 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 22355 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 22356 | { |
e74cfd16 | 22357 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22358 | mach = bfd_mach_arm_5T; |
22359 | else | |
22360 | mach = bfd_mach_arm_5; | |
22361 | } | |
e74cfd16 | 22362 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 22363 | { |
e74cfd16 | 22364 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22365 | mach = bfd_mach_arm_4T; |
22366 | else | |
22367 | mach = bfd_mach_arm_4; | |
22368 | } | |
e74cfd16 | 22369 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 22370 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
22371 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
22372 | mach = bfd_mach_arm_3; | |
22373 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
22374 | mach = bfd_mach_arm_2a; | |
22375 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
22376 | mach = bfd_mach_arm_2; | |
22377 | else | |
22378 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
22379 | |
22380 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
22381 | } | |
22382 | ||
c19d1205 | 22383 | /* Command line processing. */ |
b99bd4ef | 22384 | |
c19d1205 ZW |
22385 | /* md_parse_option |
22386 | Invocation line includes a switch not recognized by the base assembler. | |
22387 | See if it's a processor-specific option. | |
b99bd4ef | 22388 | |
c19d1205 ZW |
22389 | This routine is somewhat complicated by the need for backwards |
22390 | compatibility (since older releases of gcc can't be changed). | |
22391 | The new options try to make the interface as compatible as | |
22392 | possible with GCC. | |
b99bd4ef | 22393 | |
c19d1205 | 22394 | New options (supported) are: |
b99bd4ef | 22395 | |
c19d1205 ZW |
22396 | -mcpu=<cpu name> Assemble for selected processor |
22397 | -march=<architecture name> Assemble for selected architecture | |
22398 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
22399 | -EB/-mbig-endian Big-endian | |
22400 | -EL/-mlittle-endian Little-endian | |
22401 | -k Generate PIC code | |
22402 | -mthumb Start in Thumb mode | |
22403 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 22404 | |
278df34e | 22405 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 22406 | |
c19d1205 | 22407 | For now we will also provide support for: |
b99bd4ef | 22408 | |
c19d1205 ZW |
22409 | -mapcs-32 32-bit Program counter |
22410 | -mapcs-26 26-bit Program counter | |
22411 | -macps-float Floats passed in FP registers | |
22412 | -mapcs-reentrant Reentrant code | |
22413 | -matpcs | |
22414 | (sometime these will probably be replaced with -mapcs=<list of options> | |
22415 | and -matpcs=<list of options>) | |
b99bd4ef | 22416 | |
c19d1205 ZW |
22417 | The remaining options are only supported for back-wards compatibility. |
22418 | Cpu variants, the arm part is optional: | |
22419 | -m[arm]1 Currently not supported. | |
22420 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
22421 | -m[arm]3 Arm 3 processor | |
22422 | -m[arm]6[xx], Arm 6 processors | |
22423 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
22424 | -m[arm]8[10] Arm 8 processors | |
22425 | -m[arm]9[20][tdmi] Arm 9 processors | |
22426 | -mstrongarm[110[0]] StrongARM processors | |
22427 | -mxscale XScale processors | |
22428 | -m[arm]v[2345[t[e]]] Arm architectures | |
22429 | -mall All (except the ARM1) | |
22430 | FP variants: | |
22431 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
22432 | -mfpe-old (No float load/store multiples) | |
22433 | -mvfpxd VFP Single precision | |
22434 | -mvfp All VFP | |
22435 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 22436 | |
c19d1205 ZW |
22437 | The following CPU names are recognized: |
22438 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
22439 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
22440 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
22441 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
22442 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
22443 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
22444 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 22445 | |
c19d1205 | 22446 | */ |
b99bd4ef | 22447 | |
c19d1205 | 22448 | const char * md_shortopts = "m:k"; |
b99bd4ef | 22449 | |
c19d1205 ZW |
22450 | #ifdef ARM_BI_ENDIAN |
22451 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
22452 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 22453 | #else |
c19d1205 ZW |
22454 | #if TARGET_BYTES_BIG_ENDIAN |
22455 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 22456 | #else |
c19d1205 ZW |
22457 | #define OPTION_EL (OPTION_MD_BASE + 1) |
22458 | #endif | |
b99bd4ef | 22459 | #endif |
845b51d6 | 22460 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 22461 | |
c19d1205 | 22462 | struct option md_longopts[] = |
b99bd4ef | 22463 | { |
c19d1205 ZW |
22464 | #ifdef OPTION_EB |
22465 | {"EB", no_argument, NULL, OPTION_EB}, | |
22466 | #endif | |
22467 | #ifdef OPTION_EL | |
22468 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 22469 | #endif |
845b51d6 | 22470 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
22471 | {NULL, no_argument, NULL, 0} |
22472 | }; | |
b99bd4ef | 22473 | |
c19d1205 | 22474 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 22475 | |
c19d1205 | 22476 | struct arm_option_table |
b99bd4ef | 22477 | { |
c19d1205 ZW |
22478 | char *option; /* Option name to match. */ |
22479 | char *help; /* Help information. */ | |
22480 | int *var; /* Variable to change. */ | |
22481 | int value; /* What to change it to. */ | |
22482 | char *deprecated; /* If non-null, print this message. */ | |
22483 | }; | |
b99bd4ef | 22484 | |
c19d1205 ZW |
22485 | struct arm_option_table arm_opts[] = |
22486 | { | |
22487 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
22488 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
22489 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
22490 | &support_interwork, 1, NULL}, | |
22491 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
22492 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
22493 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
22494 | 1, NULL}, | |
22495 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
22496 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
22497 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
22498 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
22499 | NULL}, | |
b99bd4ef | 22500 | |
c19d1205 ZW |
22501 | /* These are recognized by the assembler, but have no affect on code. */ |
22502 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
22503 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
22504 | |
22505 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
22506 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
22507 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
22508 | {NULL, NULL, NULL, 0, NULL} |
22509 | }; | |
22510 | ||
22511 | struct arm_legacy_option_table | |
22512 | { | |
22513 | char *option; /* Option name to match. */ | |
22514 | const arm_feature_set **var; /* Variable to change. */ | |
22515 | const arm_feature_set value; /* What to change it to. */ | |
22516 | char *deprecated; /* If non-null, print this message. */ | |
22517 | }; | |
b99bd4ef | 22518 | |
e74cfd16 PB |
22519 | const struct arm_legacy_option_table arm_legacy_opts[] = |
22520 | { | |
c19d1205 ZW |
22521 | /* DON'T add any new processors to this list -- we want the whole list |
22522 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
22523 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
22524 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
22525 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22526 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22527 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22528 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22529 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22530 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22531 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22532 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22533 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22534 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22535 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22536 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22537 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22538 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22539 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22540 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22541 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22542 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22543 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22544 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22545 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22546 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22547 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22548 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22549 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22550 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22551 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22552 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22553 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22554 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22555 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22556 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22557 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22558 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22559 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22560 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22561 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22562 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22563 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22564 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22565 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22566 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22567 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22568 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22569 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22570 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22571 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22572 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22573 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22574 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22575 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22576 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22577 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22578 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22579 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22580 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22581 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22582 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22583 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22584 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22585 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22586 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22587 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22588 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22589 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22590 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22591 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
22592 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 22593 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 22594 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22595 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 22596 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22597 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
22598 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
22599 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
22600 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 22601 | |
c19d1205 | 22602 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22603 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
22604 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
22605 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22606 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22607 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22608 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22609 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22610 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22611 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22612 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22613 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22614 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22615 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22616 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22617 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22618 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22619 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
22620 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 22621 | |
c19d1205 | 22622 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22623 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
22624 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
22625 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
22626 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 22627 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 22628 | |
e74cfd16 | 22629 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 22630 | }; |
7ed4c4c5 | 22631 | |
c19d1205 | 22632 | struct arm_cpu_option_table |
7ed4c4c5 | 22633 | { |
c19d1205 | 22634 | char *name; |
e74cfd16 | 22635 | const arm_feature_set value; |
c19d1205 ZW |
22636 | /* For some CPUs we assume an FPU unless the user explicitly sets |
22637 | -mfpu=... */ | |
e74cfd16 | 22638 | const arm_feature_set default_fpu; |
ee065d83 PB |
22639 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
22640 | case. */ | |
22641 | const char *canonical_name; | |
c19d1205 | 22642 | }; |
7ed4c4c5 | 22643 | |
c19d1205 ZW |
22644 | /* This list should, at a minimum, contain all the cpu names |
22645 | recognized by GCC. */ | |
e74cfd16 | 22646 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 22647 | { |
ee065d83 PB |
22648 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
22649 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
22650 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
22651 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22652 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22653 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22654 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22655 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22656 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22657 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22658 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22659 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22660 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22661 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22662 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22663 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22664 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22665 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22666 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22667 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22668 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22669 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22670 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22671 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22672 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22673 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22674 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22675 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22676 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22677 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22678 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22679 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22680 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22681 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22682 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22683 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22684 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22685 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22686 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22687 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
22688 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22689 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22690 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22691 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
7fac0536 NC |
22692 | {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, |
22693 | {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
22694 | /* For V5 or later processors we default to using VFP; but the user |
22695 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
22696 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
22697 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22698 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22699 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22700 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
22701 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22702 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
22703 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22704 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22705 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
22706 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22707 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22708 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22709 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22710 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22711 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
22712 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22713 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22714 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22715 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
22716 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
4a58c4bd NC |
22717 | {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, |
22718 | {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22719 | {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22720 | {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
7fac0536 | 22721 | {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, |
ee065d83 PB |
22722 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, |
22723 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
22724 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
22725 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
4ff9b924 MGD |
22726 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"}, |
22727 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"}, | |
ee065d83 PB |
22728 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, |
22729 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
22730 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
22731 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
f4c65163 MGD |
22732 | {"cortex-a5", ARM_ARCH_V7A_MP_SEC, |
22733 | FPU_NONE, "Cortex-A5"}, | |
22734 | {"cortex-a8", ARM_ARCH_V7A_SEC, | |
22735 | ARM_FEATURE (0, FPU_VFP_V3 | |
5287ad62 | 22736 | | FPU_NEON_EXT_V1), |
4ff9b924 | 22737 | "Cortex-A8"}, |
f4c65163 MGD |
22738 | {"cortex-a9", ARM_ARCH_V7A_MP_SEC, |
22739 | ARM_FEATURE (0, FPU_VFP_V3 | |
15290f0a | 22740 | | FPU_NEON_EXT_V1), |
4ff9b924 | 22741 | "Cortex-A9"}, |
90ec0d68 | 22742 | {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, |
eea54501 | 22743 | FPU_ARCH_NEON_VFP_V4, |
dbb1f804 | 22744 | "Cortex-A15"}, |
4ff9b924 MGD |
22745 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"}, |
22746 | {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
22747 | "Cortex-R4F"}, | |
22748 | {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"}, | |
22749 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"}, | |
b2a5fbdc MGD |
22750 | {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"}, |
22751 | {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"}, | |
c19d1205 | 22752 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 22753 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22754 | /* ??? iwmmxt is not a processor. */ |
ee065d83 | 22755 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
2d447fca | 22756 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, |
ee065d83 | 22757 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22758 | /* Maverick */ |
e07e6e58 | 22759 | {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
e74cfd16 | 22760 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} |
c19d1205 | 22761 | }; |
7ed4c4c5 | 22762 | |
c19d1205 | 22763 | struct arm_arch_option_table |
7ed4c4c5 | 22764 | { |
c19d1205 | 22765 | char *name; |
e74cfd16 PB |
22766 | const arm_feature_set value; |
22767 | const arm_feature_set default_fpu; | |
c19d1205 | 22768 | }; |
7ed4c4c5 | 22769 | |
c19d1205 ZW |
22770 | /* This list should, at a minimum, contain all the architecture names |
22771 | recognized by GCC. */ | |
e74cfd16 | 22772 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
22773 | { |
22774 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
22775 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
22776 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
22777 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22778 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22779 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
22780 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
22781 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
22782 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
22783 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
22784 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
22785 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
22786 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
22787 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
22788 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
22789 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
22790 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
22791 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22792 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22793 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
22794 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
22795 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
22796 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
22797 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
22798 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
22799 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
7e806470 | 22800 | {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, |
b2a5fbdc | 22801 | {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP}, |
62b3e311 | 22802 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
c450d570 PB |
22803 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
22804 | Accept the non-dashed form for compatibility with old toolchains. */ | |
62b3e311 PB |
22805 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22806 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22807 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c450d570 PB |
22808 | {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22809 | {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22810 | {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
9e3c6df6 | 22811 | {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP}, |
c19d1205 ZW |
22812 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
22813 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
2d447fca | 22814 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, |
e74cfd16 | 22815 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 22816 | }; |
7ed4c4c5 | 22817 | |
69133863 MGD |
22818 | /* ISA extensions in the co-processor and main instruction set space. */ |
22819 | struct arm_option_extension_value_table | |
c19d1205 ZW |
22820 | { |
22821 | char *name; | |
e74cfd16 | 22822 | const arm_feature_set value; |
69133863 | 22823 | const arm_feature_set allowed_archs; |
c19d1205 | 22824 | }; |
7ed4c4c5 | 22825 | |
69133863 MGD |
22826 | /* The following table must be in alphabetical order with a NULL last entry. |
22827 | */ | |
22828 | static const struct arm_option_extension_value_table arm_extensions[] = | |
c19d1205 | 22829 | { |
eea54501 MGD |
22830 | {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
22831 | ARM_FEATURE (ARM_EXT_V7A, 0)}, | |
69133863 MGD |
22832 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY}, |
22833 | {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY}, | |
22834 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY}, | |
60e5ef9f MGD |
22835 | {"mp", ARM_FEATURE (ARM_EXT_MP, 0), |
22836 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)}, | |
b2a5fbdc MGD |
22837 | {"os", ARM_FEATURE (ARM_EXT_OS, 0), |
22838 | ARM_FEATURE (ARM_EXT_V6M, 0)}, | |
f4c65163 MGD |
22839 | {"sec", ARM_FEATURE (ARM_EXT_SEC, 0), |
22840 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)}, | |
90ec0d68 MGD |
22841 | {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
22842 | ARM_FEATURE (ARM_EXT_V7A, 0)}, | |
69133863 | 22843 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY}, |
60e5ef9f | 22844 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
69133863 MGD |
22845 | }; |
22846 | ||
22847 | /* ISA floating-point and Advanced SIMD extensions. */ | |
22848 | struct arm_option_fpu_value_table | |
22849 | { | |
22850 | char *name; | |
22851 | const arm_feature_set value; | |
c19d1205 | 22852 | }; |
7ed4c4c5 | 22853 | |
c19d1205 ZW |
22854 | /* This list should, at a minimum, contain all the fpu names |
22855 | recognized by GCC. */ | |
69133863 | 22856 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
22857 | { |
22858 | {"softfpa", FPU_NONE}, | |
22859 | {"fpe", FPU_ARCH_FPE}, | |
22860 | {"fpe2", FPU_ARCH_FPE}, | |
22861 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
22862 | {"fpa", FPU_ARCH_FPA}, | |
22863 | {"fpa10", FPU_ARCH_FPA}, | |
22864 | {"fpa11", FPU_ARCH_FPA}, | |
22865 | {"arm7500fe", FPU_ARCH_FPA}, | |
22866 | {"softvfp", FPU_ARCH_VFP}, | |
22867 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
22868 | {"vfp", FPU_ARCH_VFP_V2}, | |
22869 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 22870 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
22871 | {"vfp10", FPU_ARCH_VFP_V2}, |
22872 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
22873 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
22874 | {"vfpv2", FPU_ARCH_VFP_V2}, |
22875 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 22876 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 22877 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
22878 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
22879 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
22880 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
22881 | {"arm1020t", FPU_ARCH_VFP_V1}, |
22882 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
22883 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
22884 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
22885 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 22886 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 22887 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
22888 | {"vfpv4", FPU_ARCH_VFP_V4}, |
22889 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 22890 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 22891 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
e74cfd16 PB |
22892 | {NULL, ARM_ARCH_NONE} |
22893 | }; | |
22894 | ||
22895 | struct arm_option_value_table | |
22896 | { | |
22897 | char *name; | |
22898 | long value; | |
c19d1205 | 22899 | }; |
7ed4c4c5 | 22900 | |
e74cfd16 | 22901 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
22902 | { |
22903 | {"hard", ARM_FLOAT_ABI_HARD}, | |
22904 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
22905 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 22906 | {NULL, 0} |
c19d1205 | 22907 | }; |
7ed4c4c5 | 22908 | |
c19d1205 | 22909 | #ifdef OBJ_ELF |
3a4a14e9 | 22910 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 22911 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
22912 | { |
22913 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
22914 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 22915 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 22916 | {NULL, 0} |
c19d1205 ZW |
22917 | }; |
22918 | #endif | |
7ed4c4c5 | 22919 | |
c19d1205 ZW |
22920 | struct arm_long_option_table |
22921 | { | |
22922 | char * option; /* Substring to match. */ | |
22923 | char * help; /* Help information. */ | |
22924 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
22925 | char * deprecated; /* If non-null, print this message. */ | |
22926 | }; | |
7ed4c4c5 | 22927 | |
c921be7d | 22928 | static bfd_boolean |
e74cfd16 | 22929 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 22930 | { |
21d799b5 NC |
22931 | arm_feature_set *ext_set = (arm_feature_set *) |
22932 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 22933 | |
69133863 MGD |
22934 | /* We insist on extensions being specified in alphabetical order, and with |
22935 | extensions being added before being removed. We achieve this by having | |
22936 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
22937 | ADDING_VALUE variable to indicate whether we are adding an extension (1) | |
22938 | or removing it (0) and only allowing it to change in the order | |
22939 | -1 -> 1 -> 0. */ | |
22940 | const struct arm_option_extension_value_table * opt = NULL; | |
22941 | int adding_value = -1; | |
22942 | ||
e74cfd16 PB |
22943 | /* Copy the feature set, so that we can modify it. */ |
22944 | *ext_set = **opt_p; | |
22945 | *opt_p = ext_set; | |
22946 | ||
c19d1205 | 22947 | while (str != NULL && *str != 0) |
7ed4c4c5 | 22948 | { |
c19d1205 | 22949 | char * ext; |
69133863 | 22950 | size_t optlen; |
7ed4c4c5 | 22951 | |
c19d1205 ZW |
22952 | if (*str != '+') |
22953 | { | |
22954 | as_bad (_("invalid architectural extension")); | |
c921be7d | 22955 | return FALSE; |
c19d1205 | 22956 | } |
7ed4c4c5 | 22957 | |
c19d1205 ZW |
22958 | str++; |
22959 | ext = strchr (str, '+'); | |
7ed4c4c5 | 22960 | |
c19d1205 ZW |
22961 | if (ext != NULL) |
22962 | optlen = ext - str; | |
22963 | else | |
22964 | optlen = strlen (str); | |
7ed4c4c5 | 22965 | |
69133863 MGD |
22966 | if (optlen >= 2 |
22967 | && strncmp (str, "no", 2) == 0) | |
22968 | { | |
22969 | if (adding_value != 0) | |
22970 | { | |
22971 | adding_value = 0; | |
22972 | opt = arm_extensions; | |
22973 | } | |
22974 | ||
22975 | optlen -= 2; | |
22976 | str += 2; | |
22977 | } | |
22978 | else if (optlen > 0) | |
22979 | { | |
22980 | if (adding_value == -1) | |
22981 | { | |
22982 | adding_value = 1; | |
22983 | opt = arm_extensions; | |
22984 | } | |
22985 | else if (adding_value != 1) | |
22986 | { | |
22987 | as_bad (_("must specify extensions to add before specifying " | |
22988 | "those to remove")); | |
22989 | return FALSE; | |
22990 | } | |
22991 | } | |
22992 | ||
c19d1205 ZW |
22993 | if (optlen == 0) |
22994 | { | |
22995 | as_bad (_("missing architectural extension")); | |
c921be7d | 22996 | return FALSE; |
c19d1205 | 22997 | } |
7ed4c4c5 | 22998 | |
69133863 MGD |
22999 | gas_assert (adding_value != -1); |
23000 | gas_assert (opt != NULL); | |
23001 | ||
23002 | /* Scan over the options table trying to find an exact match. */ | |
23003 | for (; opt->name != NULL; opt++) | |
23004 | if (strncmp (opt->name, str, optlen) == 0 | |
23005 | && strlen (opt->name) == optlen) | |
c19d1205 | 23006 | { |
69133863 MGD |
23007 | /* Check we can apply the extension to this architecture. */ |
23008 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
23009 | { | |
23010 | as_bad (_("extension does not apply to the base architecture")); | |
23011 | return FALSE; | |
23012 | } | |
23013 | ||
23014 | /* Add or remove the extension. */ | |
23015 | if (adding_value) | |
23016 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); | |
23017 | else | |
23018 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); | |
23019 | ||
c19d1205 ZW |
23020 | break; |
23021 | } | |
7ed4c4c5 | 23022 | |
c19d1205 ZW |
23023 | if (opt->name == NULL) |
23024 | { | |
69133863 MGD |
23025 | /* Did we fail to find an extension because it wasn't specified in |
23026 | alphabetical order, or because it does not exist? */ | |
23027 | ||
23028 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
23029 | if (strncmp (opt->name, str, optlen) == 0) | |
23030 | break; | |
23031 | ||
23032 | if (opt->name == NULL) | |
23033 | as_bad (_("unknown architectural extension `%s'"), str); | |
23034 | else | |
23035 | as_bad (_("architectural extensions must be specified in " | |
23036 | "alphabetical order")); | |
23037 | ||
c921be7d | 23038 | return FALSE; |
c19d1205 | 23039 | } |
69133863 MGD |
23040 | else |
23041 | { | |
23042 | /* We should skip the extension we've just matched the next time | |
23043 | round. */ | |
23044 | opt++; | |
23045 | } | |
7ed4c4c5 | 23046 | |
c19d1205 ZW |
23047 | str = ext; |
23048 | }; | |
7ed4c4c5 | 23049 | |
c921be7d | 23050 | return TRUE; |
c19d1205 | 23051 | } |
7ed4c4c5 | 23052 | |
c921be7d | 23053 | static bfd_boolean |
c19d1205 | 23054 | arm_parse_cpu (char * str) |
7ed4c4c5 | 23055 | { |
e74cfd16 | 23056 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
23057 | char * ext = strchr (str, '+'); |
23058 | int optlen; | |
7ed4c4c5 | 23059 | |
c19d1205 ZW |
23060 | if (ext != NULL) |
23061 | optlen = ext - str; | |
7ed4c4c5 | 23062 | else |
c19d1205 | 23063 | optlen = strlen (str); |
7ed4c4c5 | 23064 | |
c19d1205 | 23065 | if (optlen == 0) |
7ed4c4c5 | 23066 | { |
c19d1205 | 23067 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 23068 | return FALSE; |
7ed4c4c5 NC |
23069 | } |
23070 | ||
c19d1205 ZW |
23071 | for (opt = arm_cpus; opt->name != NULL; opt++) |
23072 | if (strncmp (opt->name, str, optlen) == 0) | |
23073 | { | |
e74cfd16 PB |
23074 | mcpu_cpu_opt = &opt->value; |
23075 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 23076 | if (opt->canonical_name) |
5f4273c7 | 23077 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23078 | else |
23079 | { | |
23080 | int i; | |
c921be7d | 23081 | |
ee065d83 PB |
23082 | for (i = 0; i < optlen; i++) |
23083 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
23084 | selected_cpu_name[i] = 0; | |
23085 | } | |
7ed4c4c5 | 23086 | |
c19d1205 ZW |
23087 | if (ext != NULL) |
23088 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 23089 | |
c921be7d | 23090 | return TRUE; |
c19d1205 | 23091 | } |
7ed4c4c5 | 23092 | |
c19d1205 | 23093 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 23094 | return FALSE; |
7ed4c4c5 NC |
23095 | } |
23096 | ||
c921be7d | 23097 | static bfd_boolean |
c19d1205 | 23098 | arm_parse_arch (char * str) |
7ed4c4c5 | 23099 | { |
e74cfd16 | 23100 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
23101 | char *ext = strchr (str, '+'); |
23102 | int optlen; | |
7ed4c4c5 | 23103 | |
c19d1205 ZW |
23104 | if (ext != NULL) |
23105 | optlen = ext - str; | |
7ed4c4c5 | 23106 | else |
c19d1205 | 23107 | optlen = strlen (str); |
7ed4c4c5 | 23108 | |
c19d1205 | 23109 | if (optlen == 0) |
7ed4c4c5 | 23110 | { |
c19d1205 | 23111 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 23112 | return FALSE; |
7ed4c4c5 NC |
23113 | } |
23114 | ||
c19d1205 | 23115 | for (opt = arm_archs; opt->name != NULL; opt++) |
69133863 | 23116 | if (strncmp (opt->name, str, optlen) == 0) |
c19d1205 | 23117 | { |
e74cfd16 PB |
23118 | march_cpu_opt = &opt->value; |
23119 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 23120 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 23121 | |
c19d1205 ZW |
23122 | if (ext != NULL) |
23123 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 23124 | |
c921be7d | 23125 | return TRUE; |
c19d1205 ZW |
23126 | } |
23127 | ||
23128 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 23129 | return FALSE; |
7ed4c4c5 | 23130 | } |
eb043451 | 23131 | |
c921be7d | 23132 | static bfd_boolean |
c19d1205 ZW |
23133 | arm_parse_fpu (char * str) |
23134 | { | |
69133863 | 23135 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 23136 | |
c19d1205 ZW |
23137 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23138 | if (streq (opt->name, str)) | |
23139 | { | |
e74cfd16 | 23140 | mfpu_opt = &opt->value; |
c921be7d | 23141 | return TRUE; |
c19d1205 | 23142 | } |
b99bd4ef | 23143 | |
c19d1205 | 23144 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 23145 | return FALSE; |
c19d1205 ZW |
23146 | } |
23147 | ||
c921be7d | 23148 | static bfd_boolean |
c19d1205 | 23149 | arm_parse_float_abi (char * str) |
b99bd4ef | 23150 | { |
e74cfd16 | 23151 | const struct arm_option_value_table * opt; |
b99bd4ef | 23152 | |
c19d1205 ZW |
23153 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
23154 | if (streq (opt->name, str)) | |
23155 | { | |
23156 | mfloat_abi_opt = opt->value; | |
c921be7d | 23157 | return TRUE; |
c19d1205 | 23158 | } |
cc8a6dd0 | 23159 | |
c19d1205 | 23160 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 23161 | return FALSE; |
c19d1205 | 23162 | } |
b99bd4ef | 23163 | |
c19d1205 | 23164 | #ifdef OBJ_ELF |
c921be7d | 23165 | static bfd_boolean |
c19d1205 ZW |
23166 | arm_parse_eabi (char * str) |
23167 | { | |
e74cfd16 | 23168 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 23169 | |
c19d1205 ZW |
23170 | for (opt = arm_eabis; opt->name != NULL; opt++) |
23171 | if (streq (opt->name, str)) | |
23172 | { | |
23173 | meabi_flags = opt->value; | |
c921be7d | 23174 | return TRUE; |
c19d1205 ZW |
23175 | } |
23176 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 23177 | return FALSE; |
c19d1205 ZW |
23178 | } |
23179 | #endif | |
cc8a6dd0 | 23180 | |
c921be7d | 23181 | static bfd_boolean |
e07e6e58 NC |
23182 | arm_parse_it_mode (char * str) |
23183 | { | |
c921be7d | 23184 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
23185 | |
23186 | if (streq ("arm", str)) | |
23187 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
23188 | else if (streq ("thumb", str)) | |
23189 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
23190 | else if (streq ("always", str)) | |
23191 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
23192 | else if (streq ("never", str)) | |
23193 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
23194 | else | |
23195 | { | |
23196 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
23197 | "arm, thumb, always, or never."), str); | |
c921be7d | 23198 | ret = FALSE; |
e07e6e58 NC |
23199 | } |
23200 | ||
23201 | return ret; | |
23202 | } | |
23203 | ||
c19d1205 ZW |
23204 | struct arm_long_option_table arm_long_opts[] = |
23205 | { | |
23206 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
23207 | arm_parse_cpu, NULL}, | |
23208 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
23209 | arm_parse_arch, NULL}, | |
23210 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
23211 | arm_parse_fpu, NULL}, | |
23212 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
23213 | arm_parse_float_abi, NULL}, | |
23214 | #ifdef OBJ_ELF | |
7fac0536 | 23215 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
23216 | arm_parse_eabi, NULL}, |
23217 | #endif | |
e07e6e58 NC |
23218 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
23219 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
23220 | {NULL, NULL, 0, NULL} |
23221 | }; | |
cc8a6dd0 | 23222 | |
c19d1205 ZW |
23223 | int |
23224 | md_parse_option (int c, char * arg) | |
23225 | { | |
23226 | struct arm_option_table *opt; | |
e74cfd16 | 23227 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 23228 | struct arm_long_option_table *lopt; |
b99bd4ef | 23229 | |
c19d1205 | 23230 | switch (c) |
b99bd4ef | 23231 | { |
c19d1205 ZW |
23232 | #ifdef OPTION_EB |
23233 | case OPTION_EB: | |
23234 | target_big_endian = 1; | |
23235 | break; | |
23236 | #endif | |
cc8a6dd0 | 23237 | |
c19d1205 ZW |
23238 | #ifdef OPTION_EL |
23239 | case OPTION_EL: | |
23240 | target_big_endian = 0; | |
23241 | break; | |
23242 | #endif | |
b99bd4ef | 23243 | |
845b51d6 PB |
23244 | case OPTION_FIX_V4BX: |
23245 | fix_v4bx = TRUE; | |
23246 | break; | |
23247 | ||
c19d1205 ZW |
23248 | case 'a': |
23249 | /* Listing option. Just ignore these, we don't support additional | |
23250 | ones. */ | |
23251 | return 0; | |
b99bd4ef | 23252 | |
c19d1205 ZW |
23253 | default: |
23254 | for (opt = arm_opts; opt->option != NULL; opt++) | |
23255 | { | |
23256 | if (c == opt->option[0] | |
23257 | && ((arg == NULL && opt->option[1] == 0) | |
23258 | || streq (arg, opt->option + 1))) | |
23259 | { | |
c19d1205 | 23260 | /* If the option is deprecated, tell the user. */ |
278df34e | 23261 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
23262 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23263 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 23264 | |
c19d1205 ZW |
23265 | if (opt->var != NULL) |
23266 | *opt->var = opt->value; | |
cc8a6dd0 | 23267 | |
c19d1205 ZW |
23268 | return 1; |
23269 | } | |
23270 | } | |
b99bd4ef | 23271 | |
e74cfd16 PB |
23272 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
23273 | { | |
23274 | if (c == fopt->option[0] | |
23275 | && ((arg == NULL && fopt->option[1] == 0) | |
23276 | || streq (arg, fopt->option + 1))) | |
23277 | { | |
e74cfd16 | 23278 | /* If the option is deprecated, tell the user. */ |
278df34e | 23279 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
23280 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23281 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
23282 | |
23283 | if (fopt->var != NULL) | |
23284 | *fopt->var = &fopt->value; | |
23285 | ||
23286 | return 1; | |
23287 | } | |
23288 | } | |
23289 | ||
c19d1205 ZW |
23290 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23291 | { | |
23292 | /* These options are expected to have an argument. */ | |
23293 | if (c == lopt->option[0] | |
23294 | && arg != NULL | |
23295 | && strncmp (arg, lopt->option + 1, | |
23296 | strlen (lopt->option + 1)) == 0) | |
23297 | { | |
c19d1205 | 23298 | /* If the option is deprecated, tell the user. */ |
278df34e | 23299 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
23300 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
23301 | _(lopt->deprecated)); | |
b99bd4ef | 23302 | |
c19d1205 ZW |
23303 | /* Call the sup-option parser. */ |
23304 | return lopt->func (arg + strlen (lopt->option) - 1); | |
23305 | } | |
23306 | } | |
a737bd4d | 23307 | |
c19d1205 ZW |
23308 | return 0; |
23309 | } | |
a394c00f | 23310 | |
c19d1205 ZW |
23311 | return 1; |
23312 | } | |
a394c00f | 23313 | |
c19d1205 ZW |
23314 | void |
23315 | md_show_usage (FILE * fp) | |
a394c00f | 23316 | { |
c19d1205 ZW |
23317 | struct arm_option_table *opt; |
23318 | struct arm_long_option_table *lopt; | |
a394c00f | 23319 | |
c19d1205 | 23320 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 23321 | |
c19d1205 ZW |
23322 | for (opt = arm_opts; opt->option != NULL; opt++) |
23323 | if (opt->help != NULL) | |
23324 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 23325 | |
c19d1205 ZW |
23326 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23327 | if (lopt->help != NULL) | |
23328 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 23329 | |
c19d1205 ZW |
23330 | #ifdef OPTION_EB |
23331 | fprintf (fp, _("\ | |
23332 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
23333 | #endif |
23334 | ||
c19d1205 ZW |
23335 | #ifdef OPTION_EL |
23336 | fprintf (fp, _("\ | |
23337 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 23338 | #endif |
845b51d6 PB |
23339 | |
23340 | fprintf (fp, _("\ | |
23341 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 23342 | } |
ee065d83 PB |
23343 | |
23344 | ||
23345 | #ifdef OBJ_ELF | |
62b3e311 PB |
23346 | typedef struct |
23347 | { | |
23348 | int val; | |
23349 | arm_feature_set flags; | |
23350 | } cpu_arch_ver_table; | |
23351 | ||
23352 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
23353 | least features first. */ | |
23354 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
23355 | { | |
23356 | {1, ARM_ARCH_V4}, | |
23357 | {2, ARM_ARCH_V4T}, | |
23358 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 23359 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
23360 | {4, ARM_ARCH_V5TE}, |
23361 | {5, ARM_ARCH_V5TEJ}, | |
23362 | {6, ARM_ARCH_V6}, | |
7e806470 | 23363 | {9, ARM_ARCH_V6K}, |
f4c65163 | 23364 | {7, ARM_ARCH_V6Z}, |
91e22acd | 23365 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 23366 | {12, ARM_ARCH_V6SM}, |
7e806470 | 23367 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
23368 | {10, ARM_ARCH_V7A}, |
23369 | {10, ARM_ARCH_V7R}, | |
23370 | {10, ARM_ARCH_V7M}, | |
23371 | {0, ARM_ARCH_NONE} | |
23372 | }; | |
23373 | ||
ee3c0378 AS |
23374 | /* Set an attribute if it has not already been set by the user. */ |
23375 | static void | |
23376 | aeabi_set_attribute_int (int tag, int value) | |
23377 | { | |
23378 | if (tag < 1 | |
23379 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23380 | || !attributes_set_explicitly[tag]) | |
23381 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
23382 | } | |
23383 | ||
23384 | static void | |
23385 | aeabi_set_attribute_string (int tag, const char *value) | |
23386 | { | |
23387 | if (tag < 1 | |
23388 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23389 | || !attributes_set_explicitly[tag]) | |
23390 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
23391 | } | |
23392 | ||
ee065d83 PB |
23393 | /* Set the public EABI object attributes. */ |
23394 | static void | |
23395 | aeabi_set_public_attributes (void) | |
23396 | { | |
23397 | int arch; | |
90ec0d68 | 23398 | int virt_sec = 0; |
e74cfd16 | 23399 | arm_feature_set flags; |
62b3e311 PB |
23400 | arm_feature_set tmp; |
23401 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
23402 | |
23403 | /* Choose the architecture based on the capabilities of the requested cpu | |
23404 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
23405 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
23406 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
23407 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
7a1d4c38 PB |
23408 | /*Allow the user to override the reported architecture. */ |
23409 | if (object_arch) | |
23410 | { | |
23411 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
23412 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
23413 | } | |
23414 | ||
251665fc MGD |
23415 | /* We need to make sure that the attributes do not identify us as v6S-M |
23416 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
23417 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
23418 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
23419 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); | |
23420 | ||
62b3e311 PB |
23421 | tmp = flags; |
23422 | arch = 0; | |
23423 | for (p = cpu_arch_ver; p->val; p++) | |
23424 | { | |
23425 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
23426 | { | |
23427 | arch = p->val; | |
23428 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
23429 | } | |
23430 | } | |
ee065d83 | 23431 | |
9e3c6df6 PB |
23432 | /* The table lookup above finds the last architecture to contribute |
23433 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
23434 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
23435 | We can not search for the last entry which is entirely used, | |
23436 | because if no CPU is specified we build up only those flags | |
23437 | actually used. Perhaps we should separate out the specified | |
23438 | and implicit cases. Avoid taking this path for -march=all by | |
23439 | checking for contradictory v7-A / v7-M features. */ | |
23440 | if (arch == 10 | |
23441 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
23442 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
23443 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
23444 | arch = 13; | |
23445 | ||
ee065d83 PB |
23446 | /* Tag_CPU_name. */ |
23447 | if (selected_cpu_name[0]) | |
23448 | { | |
91d6fa6a | 23449 | char *q; |
ee065d83 | 23450 | |
91d6fa6a NC |
23451 | q = selected_cpu_name; |
23452 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
23453 | { |
23454 | int i; | |
5f4273c7 | 23455 | |
91d6fa6a NC |
23456 | q += 4; |
23457 | for (i = 0; q[i]; i++) | |
23458 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 23459 | } |
91d6fa6a | 23460 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 23461 | } |
62f3b8c8 | 23462 | |
ee065d83 | 23463 | /* Tag_CPU_arch. */ |
ee3c0378 | 23464 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 23465 | |
62b3e311 PB |
23466 | /* Tag_CPU_arch_profile. */ |
23467 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 23468 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 23469 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 23470 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 23471 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 23472 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
62f3b8c8 | 23473 | |
ee065d83 | 23474 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
23475 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
23476 | || arch == 0) | |
23477 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 23478 | |
ee065d83 | 23479 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
23480 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
23481 | || arch == 0) | |
23482 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
23483 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 23484 | |
ee065d83 | 23485 | /* Tag_VFP_arch. */ |
62f3b8c8 PB |
23486 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
23487 | aeabi_set_attribute_int (Tag_VFP_arch, | |
23488 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
23489 | ? 5 : 6); | |
23490 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
ee3c0378 | 23491 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
ada65aa3 | 23492 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
ee3c0378 AS |
23493 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
23494 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
23495 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
23496 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
23497 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
23498 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 23499 | |
4547cb56 NC |
23500 | /* Tag_ABI_HardFP_use. */ |
23501 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
23502 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
23503 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
23504 | ||
ee065d83 | 23505 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
23506 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
23507 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
23508 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
23509 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 23510 | |
ee3c0378 | 23511 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
8e79c3df | 23512 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
62f3b8c8 PB |
23513 | aeabi_set_attribute_int |
23514 | (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) | |
23515 | ? 2 : 1)); | |
23516 | ||
ee3c0378 | 23517 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
62f3b8c8 | 23518 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) |
ee3c0378 | 23519 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 NC |
23520 | |
23521 | /* Tag_DIV_use. */ | |
eea54501 MGD |
23522 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)) |
23523 | aeabi_set_attribute_int (Tag_DIV_use, 2); | |
23524 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) | |
4547cb56 | 23525 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
4547cb56 NC |
23526 | else |
23527 | aeabi_set_attribute_int (Tag_DIV_use, 1); | |
60e5ef9f MGD |
23528 | |
23529 | /* Tag_MP_extension_use. */ | |
23530 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
23531 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
23532 | |
23533 | /* Tag Virtualization_use. */ | |
23534 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
23535 | virt_sec |= 1; |
23536 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
23537 | virt_sec |= 2; | |
23538 | if (virt_sec != 0) | |
23539 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
23540 | } |
23541 | ||
104d59d1 | 23542 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
23543 | void |
23544 | arm_md_end (void) | |
23545 | { | |
ee065d83 PB |
23546 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
23547 | return; | |
23548 | ||
23549 | aeabi_set_public_attributes (); | |
ee065d83 | 23550 | } |
8463be01 | 23551 | #endif /* OBJ_ELF */ |
ee065d83 PB |
23552 | |
23553 | ||
23554 | /* Parse a .cpu directive. */ | |
23555 | ||
23556 | static void | |
23557 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
23558 | { | |
e74cfd16 | 23559 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
23560 | char *name; |
23561 | char saved_char; | |
23562 | ||
23563 | name = input_line_pointer; | |
5f4273c7 | 23564 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23565 | input_line_pointer++; |
23566 | saved_char = *input_line_pointer; | |
23567 | *input_line_pointer = 0; | |
23568 | ||
23569 | /* Skip the first "all" entry. */ | |
23570 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
23571 | if (streq (opt->name, name)) | |
23572 | { | |
e74cfd16 PB |
23573 | mcpu_cpu_opt = &opt->value; |
23574 | selected_cpu = opt->value; | |
ee065d83 | 23575 | if (opt->canonical_name) |
5f4273c7 | 23576 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23577 | else |
23578 | { | |
23579 | int i; | |
23580 | for (i = 0; opt->name[i]; i++) | |
23581 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
23582 | selected_cpu_name[i] = 0; | |
23583 | } | |
e74cfd16 | 23584 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23585 | *input_line_pointer = saved_char; |
23586 | demand_empty_rest_of_line (); | |
23587 | return; | |
23588 | } | |
23589 | as_bad (_("unknown cpu `%s'"), name); | |
23590 | *input_line_pointer = saved_char; | |
23591 | ignore_rest_of_line (); | |
23592 | } | |
23593 | ||
23594 | ||
23595 | /* Parse a .arch directive. */ | |
23596 | ||
23597 | static void | |
23598 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
23599 | { | |
e74cfd16 | 23600 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
23601 | char saved_char; |
23602 | char *name; | |
23603 | ||
23604 | name = input_line_pointer; | |
5f4273c7 | 23605 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23606 | input_line_pointer++; |
23607 | saved_char = *input_line_pointer; | |
23608 | *input_line_pointer = 0; | |
23609 | ||
23610 | /* Skip the first "all" entry. */ | |
23611 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23612 | if (streq (opt->name, name)) | |
23613 | { | |
e74cfd16 PB |
23614 | mcpu_cpu_opt = &opt->value; |
23615 | selected_cpu = opt->value; | |
5f4273c7 | 23616 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 23617 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23618 | *input_line_pointer = saved_char; |
23619 | demand_empty_rest_of_line (); | |
23620 | return; | |
23621 | } | |
23622 | ||
23623 | as_bad (_("unknown architecture `%s'\n"), name); | |
23624 | *input_line_pointer = saved_char; | |
23625 | ignore_rest_of_line (); | |
23626 | } | |
23627 | ||
23628 | ||
7a1d4c38 PB |
23629 | /* Parse a .object_arch directive. */ |
23630 | ||
23631 | static void | |
23632 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
23633 | { | |
23634 | const struct arm_arch_option_table *opt; | |
23635 | char saved_char; | |
23636 | char *name; | |
23637 | ||
23638 | name = input_line_pointer; | |
5f4273c7 | 23639 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
23640 | input_line_pointer++; |
23641 | saved_char = *input_line_pointer; | |
23642 | *input_line_pointer = 0; | |
23643 | ||
23644 | /* Skip the first "all" entry. */ | |
23645 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23646 | if (streq (opt->name, name)) | |
23647 | { | |
23648 | object_arch = &opt->value; | |
23649 | *input_line_pointer = saved_char; | |
23650 | demand_empty_rest_of_line (); | |
23651 | return; | |
23652 | } | |
23653 | ||
23654 | as_bad (_("unknown architecture `%s'\n"), name); | |
23655 | *input_line_pointer = saved_char; | |
23656 | ignore_rest_of_line (); | |
23657 | } | |
23658 | ||
69133863 MGD |
23659 | /* Parse a .arch_extension directive. */ |
23660 | ||
23661 | static void | |
23662 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
23663 | { | |
23664 | const struct arm_option_extension_value_table *opt; | |
23665 | char saved_char; | |
23666 | char *name; | |
23667 | int adding_value = 1; | |
23668 | ||
23669 | name = input_line_pointer; | |
23670 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
23671 | input_line_pointer++; | |
23672 | saved_char = *input_line_pointer; | |
23673 | *input_line_pointer = 0; | |
23674 | ||
23675 | if (strlen (name) >= 2 | |
23676 | && strncmp (name, "no", 2) == 0) | |
23677 | { | |
23678 | adding_value = 0; | |
23679 | name += 2; | |
23680 | } | |
23681 | ||
23682 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
23683 | if (streq (opt->name, name)) | |
23684 | { | |
23685 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
23686 | { | |
23687 | as_bad (_("architectural extension `%s' is not allowed for the " | |
23688 | "current base architecture"), name); | |
23689 | break; | |
23690 | } | |
23691 | ||
23692 | if (adding_value) | |
23693 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); | |
23694 | else | |
23695 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); | |
23696 | ||
23697 | mcpu_cpu_opt = &selected_cpu; | |
23698 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
23699 | *input_line_pointer = saved_char; | |
23700 | demand_empty_rest_of_line (); | |
23701 | return; | |
23702 | } | |
23703 | ||
23704 | if (opt->name == NULL) | |
23705 | as_bad (_("unknown architecture `%s'\n"), name); | |
23706 | ||
23707 | *input_line_pointer = saved_char; | |
23708 | ignore_rest_of_line (); | |
23709 | } | |
23710 | ||
ee065d83 PB |
23711 | /* Parse a .fpu directive. */ |
23712 | ||
23713 | static void | |
23714 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
23715 | { | |
69133863 | 23716 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
23717 | char saved_char; |
23718 | char *name; | |
23719 | ||
23720 | name = input_line_pointer; | |
5f4273c7 | 23721 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23722 | input_line_pointer++; |
23723 | saved_char = *input_line_pointer; | |
23724 | *input_line_pointer = 0; | |
5f4273c7 | 23725 | |
ee065d83 PB |
23726 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23727 | if (streq (opt->name, name)) | |
23728 | { | |
e74cfd16 PB |
23729 | mfpu_opt = &opt->value; |
23730 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
23731 | *input_line_pointer = saved_char; |
23732 | demand_empty_rest_of_line (); | |
23733 | return; | |
23734 | } | |
23735 | ||
23736 | as_bad (_("unknown floating point format `%s'\n"), name); | |
23737 | *input_line_pointer = saved_char; | |
23738 | ignore_rest_of_line (); | |
23739 | } | |
ee065d83 | 23740 | |
794ba86a | 23741 | /* Copy symbol information. */ |
f31fef98 | 23742 | |
794ba86a DJ |
23743 | void |
23744 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
23745 | { | |
23746 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
23747 | } | |
e04befd0 | 23748 | |
f31fef98 | 23749 | #ifdef OBJ_ELF |
e04befd0 AS |
23750 | /* Given a symbolic attribute NAME, return the proper integer value. |
23751 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 23752 | |
e04befd0 AS |
23753 | int |
23754 | arm_convert_symbolic_attribute (const char *name) | |
23755 | { | |
f31fef98 NC |
23756 | static const struct |
23757 | { | |
23758 | const char * name; | |
23759 | const int tag; | |
23760 | } | |
23761 | attribute_table[] = | |
23762 | { | |
23763 | /* When you modify this table you should | |
23764 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 23765 | #define T(tag) {#tag, tag} |
f31fef98 NC |
23766 | T (Tag_CPU_raw_name), |
23767 | T (Tag_CPU_name), | |
23768 | T (Tag_CPU_arch), | |
23769 | T (Tag_CPU_arch_profile), | |
23770 | T (Tag_ARM_ISA_use), | |
23771 | T (Tag_THUMB_ISA_use), | |
75375b3e | 23772 | T (Tag_FP_arch), |
f31fef98 NC |
23773 | T (Tag_VFP_arch), |
23774 | T (Tag_WMMX_arch), | |
23775 | T (Tag_Advanced_SIMD_arch), | |
23776 | T (Tag_PCS_config), | |
23777 | T (Tag_ABI_PCS_R9_use), | |
23778 | T (Tag_ABI_PCS_RW_data), | |
23779 | T (Tag_ABI_PCS_RO_data), | |
23780 | T (Tag_ABI_PCS_GOT_use), | |
23781 | T (Tag_ABI_PCS_wchar_t), | |
23782 | T (Tag_ABI_FP_rounding), | |
23783 | T (Tag_ABI_FP_denormal), | |
23784 | T (Tag_ABI_FP_exceptions), | |
23785 | T (Tag_ABI_FP_user_exceptions), | |
23786 | T (Tag_ABI_FP_number_model), | |
75375b3e | 23787 | T (Tag_ABI_align_needed), |
f31fef98 | 23788 | T (Tag_ABI_align8_needed), |
75375b3e | 23789 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
23790 | T (Tag_ABI_align8_preserved), |
23791 | T (Tag_ABI_enum_size), | |
23792 | T (Tag_ABI_HardFP_use), | |
23793 | T (Tag_ABI_VFP_args), | |
23794 | T (Tag_ABI_WMMX_args), | |
23795 | T (Tag_ABI_optimization_goals), | |
23796 | T (Tag_ABI_FP_optimization_goals), | |
23797 | T (Tag_compatibility), | |
23798 | T (Tag_CPU_unaligned_access), | |
75375b3e | 23799 | T (Tag_FP_HP_extension), |
f31fef98 NC |
23800 | T (Tag_VFP_HP_extension), |
23801 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
23802 | T (Tag_MPextension_use), |
23803 | T (Tag_DIV_use), | |
f31fef98 NC |
23804 | T (Tag_nodefaults), |
23805 | T (Tag_also_compatible_with), | |
23806 | T (Tag_conformance), | |
23807 | T (Tag_T2EE_use), | |
23808 | T (Tag_Virtualization_use), | |
cd21e546 | 23809 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 23810 | #undef T |
f31fef98 | 23811 | }; |
e04befd0 AS |
23812 | unsigned int i; |
23813 | ||
23814 | if (name == NULL) | |
23815 | return -1; | |
23816 | ||
f31fef98 | 23817 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 23818 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
23819 | return attribute_table[i].tag; |
23820 | ||
23821 | return -1; | |
23822 | } | |
267bf995 RR |
23823 | |
23824 | ||
23825 | /* Apply sym value for relocations only in the case that | |
23826 | they are for local symbols and you have the respective | |
23827 | architectural feature for blx and simple switches. */ | |
23828 | int | |
23829 | arm_apply_sym_value (struct fix * fixP) | |
23830 | { | |
23831 | if (fixP->fx_addsy | |
23832 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 23833 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
23834 | { |
23835 | switch (fixP->fx_r_type) | |
23836 | { | |
23837 | case BFD_RELOC_ARM_PCREL_BLX: | |
23838 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23839 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
23840 | return 1; | |
23841 | break; | |
23842 | ||
23843 | case BFD_RELOC_ARM_PCREL_CALL: | |
23844 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23845 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
23846 | return 1; | |
23847 | break; | |
23848 | ||
23849 | default: | |
23850 | break; | |
23851 | } | |
23852 | ||
23853 | } | |
23854 | return 0; | |
23855 | } | |
f31fef98 | 23856 | #endif /* OBJ_ELF */ |