Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
fa94de6b | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
3da1d841 | 35 | #include "libiberty.h" |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 | 100 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 101 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
102 | changing gas' default behaviour depending upon the build host. |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
bca38921 | 198 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0); |
7e806470 | 199 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 200 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 201 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 202 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 203 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 204 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 205 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
206 | |
207 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
208 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
209 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
210 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 211 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 212 | |
2d447fca JM |
213 | static const arm_feature_set arm_cext_iwmmxt2 = |
214 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
215 | static const arm_feature_set arm_cext_iwmmxt = |
216 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
217 | static const arm_feature_set arm_cext_xscale = | |
218 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
219 | static const arm_feature_set arm_cext_maverick = | |
220 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
221 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
222 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
223 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
224 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
225 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
226 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 227 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 228 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
229 | static const arm_feature_set fpu_vfp_ext_d32 = |
230 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
231 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
232 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
233 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
234 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
235 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
236 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
bca38921 MGD |
237 | static const arm_feature_set fpu_vfp_ext_armv8 = |
238 | ARM_FEATURE (0, FPU_VFP_EXT_ARMV8); | |
239 | static const arm_feature_set fpu_neon_ext_armv8 = | |
240 | ARM_FEATURE (0, FPU_NEON_EXT_ARMV8); | |
241 | static const arm_feature_set fpu_crypto_ext_armv8 = | |
242 | ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8); | |
e74cfd16 | 243 | |
33a392fb | 244 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
245 | /* Record user cpu selection for object attributes. */ |
246 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
247 | /* Must be long enough to hold any of the names in arm_cpus. */ |
248 | static char selected_cpu_name[16]; | |
8d67f500 NC |
249 | |
250 | /* Return if no cpu was selected on command-line. */ | |
251 | static bfd_boolean | |
252 | no_cpu_selected (void) | |
253 | { | |
254 | return selected_cpu.core == arm_arch_none.core | |
255 | && selected_cpu.coproc == arm_arch_none.coproc; | |
256 | } | |
257 | ||
7cc69913 | 258 | #ifdef OBJ_ELF |
deeaaff8 DJ |
259 | # ifdef EABI_DEFAULT |
260 | static int meabi_flags = EABI_DEFAULT; | |
261 | # else | |
d507cf36 | 262 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 263 | # endif |
e1da3f5b | 264 | |
ee3c0378 AS |
265 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
266 | ||
e1da3f5b | 267 | bfd_boolean |
5f4273c7 | 268 | arm_is_eabi (void) |
e1da3f5b PB |
269 | { |
270 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
271 | } | |
7cc69913 | 272 | #endif |
b99bd4ef | 273 | |
b99bd4ef | 274 | #ifdef OBJ_ELF |
c19d1205 | 275 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
276 | symbolS * GOT_symbol; |
277 | #endif | |
278 | ||
b99bd4ef NC |
279 | /* 0: assemble for ARM, |
280 | 1: assemble for Thumb, | |
281 | 2: assemble for Thumb even though target CPU does not support thumb | |
282 | instructions. */ | |
283 | static int thumb_mode = 0; | |
8dc2430f NC |
284 | /* A value distinct from the possible values for thumb_mode that we |
285 | can use to record whether thumb_mode has been copied into the | |
286 | tc_frag_data field of a frag. */ | |
287 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 288 | |
e07e6e58 NC |
289 | /* Specifies the intrinsic IT insn behavior mode. */ |
290 | enum implicit_it_mode | |
291 | { | |
292 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
293 | IMPLICIT_IT_MODE_ARM = 0x01, | |
294 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
295 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
296 | }; | |
297 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
298 | ||
c19d1205 ZW |
299 | /* If unified_syntax is true, we are processing the new unified |
300 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
301 | ||
302 | - Immediate operands do not require a # prefix. | |
303 | - Conditional affixes always appear at the end of the | |
304 | instruction. (For backward compatibility, those instructions | |
305 | that formerly had them in the middle, continue to accept them | |
306 | there.) | |
307 | - The IT instruction may appear, and if it does is validated | |
308 | against subsequent conditional affixes. It does not generate | |
309 | machine code. | |
310 | ||
311 | Important differences from the old Thumb mode: | |
312 | ||
313 | - Immediate operands do not require a # prefix. | |
314 | - Most of the V6T2 instructions are only available in unified mode. | |
315 | - The .N and .W suffixes are recognized and honored (it is an error | |
316 | if they cannot be honored). | |
317 | - All instructions set the flags if and only if they have an 's' affix. | |
318 | - Conditional affixes may be used. They are validated against | |
319 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
320 | conditional affix except in the scope of an IT instruction. */ | |
321 | ||
322 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 323 | |
5287ad62 JB |
324 | enum neon_el_type |
325 | { | |
dcbf9037 | 326 | NT_invtype, |
5287ad62 JB |
327 | NT_untyped, |
328 | NT_integer, | |
329 | NT_float, | |
330 | NT_poly, | |
331 | NT_signed, | |
dcbf9037 | 332 | NT_unsigned |
5287ad62 JB |
333 | }; |
334 | ||
335 | struct neon_type_el | |
336 | { | |
337 | enum neon_el_type type; | |
338 | unsigned size; | |
339 | }; | |
340 | ||
341 | #define NEON_MAX_TYPE_ELS 4 | |
342 | ||
343 | struct neon_type | |
344 | { | |
345 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
346 | unsigned elems; | |
347 | }; | |
348 | ||
e07e6e58 NC |
349 | enum it_instruction_type |
350 | { | |
351 | OUTSIDE_IT_INSN, | |
352 | INSIDE_IT_INSN, | |
353 | INSIDE_IT_LAST_INSN, | |
354 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
355 | if inside, should be the last one. */ | |
356 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
357 | i.e. BKPT and NOP. */ | |
358 | IT_INSN /* The IT insn has been parsed. */ | |
359 | }; | |
360 | ||
ad6cec43 MGD |
361 | /* The maximum number of operands we need. */ |
362 | #define ARM_IT_MAX_OPERANDS 6 | |
363 | ||
b99bd4ef NC |
364 | struct arm_it |
365 | { | |
c19d1205 | 366 | const char * error; |
b99bd4ef | 367 | unsigned long instruction; |
c19d1205 ZW |
368 | int size; |
369 | int size_req; | |
370 | int cond; | |
037e8744 JB |
371 | /* "uncond_value" is set to the value in place of the conditional field in |
372 | unconditional versions of the instruction, or -1 if nothing is | |
373 | appropriate. */ | |
374 | int uncond_value; | |
5287ad62 | 375 | struct neon_type vectype; |
88714cb8 DG |
376 | /* This does not indicate an actual NEON instruction, only that |
377 | the mnemonic accepts neon-style type suffixes. */ | |
378 | int is_neon; | |
0110f2b8 PB |
379 | /* Set to the opcode if the instruction needs relaxation. |
380 | Zero if the instruction is not relaxed. */ | |
381 | unsigned long relax; | |
b99bd4ef NC |
382 | struct |
383 | { | |
384 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
385 | expressionS exp; |
386 | int pc_rel; | |
b99bd4ef | 387 | } reloc; |
b99bd4ef | 388 | |
e07e6e58 NC |
389 | enum it_instruction_type it_insn_type; |
390 | ||
c19d1205 ZW |
391 | struct |
392 | { | |
393 | unsigned reg; | |
ca3f61f7 | 394 | signed int imm; |
dcbf9037 | 395 | struct neon_type_el vectype; |
ca3f61f7 NC |
396 | unsigned present : 1; /* Operand present. */ |
397 | unsigned isreg : 1; /* Operand was a register. */ | |
398 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
399 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
400 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 401 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
402 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
403 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
404 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 405 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 406 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 407 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
408 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
409 | unsigned writeback : 1; /* Operand has trailing ! */ | |
410 | unsigned preind : 1; /* Preindexed address. */ | |
411 | unsigned postind : 1; /* Postindexed address. */ | |
412 | unsigned negative : 1; /* Index register was negated. */ | |
413 | unsigned shifted : 1; /* Shift applied to operation. */ | |
414 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 415 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
416 | }; |
417 | ||
c19d1205 | 418 | static struct arm_it inst; |
b99bd4ef NC |
419 | |
420 | #define NUM_FLOAT_VALS 8 | |
421 | ||
05d2d07e | 422 | const char * fp_const[] = |
b99bd4ef NC |
423 | { |
424 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
425 | }; | |
426 | ||
c19d1205 | 427 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
428 | #define MAX_LITTLENUMS 6 |
429 | ||
430 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
431 | ||
432 | #define FAIL (-1) | |
433 | #define SUCCESS (0) | |
434 | ||
435 | #define SUFF_S 1 | |
436 | #define SUFF_D 2 | |
437 | #define SUFF_E 3 | |
438 | #define SUFF_P 4 | |
439 | ||
c19d1205 ZW |
440 | #define CP_T_X 0x00008000 |
441 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 442 | |
c19d1205 ZW |
443 | #define CONDS_BIT 0x00100000 |
444 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
445 | |
446 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
447 | ||
448 | struct asm_cond | |
449 | { | |
d3ce72d0 | 450 | const char * template_name; |
c921be7d | 451 | unsigned long value; |
b99bd4ef NC |
452 | }; |
453 | ||
c19d1205 | 454 | #define COND_ALWAYS 0xE |
b99bd4ef | 455 | |
b99bd4ef NC |
456 | struct asm_psr |
457 | { | |
d3ce72d0 | 458 | const char * template_name; |
c921be7d | 459 | unsigned long field; |
b99bd4ef NC |
460 | }; |
461 | ||
62b3e311 PB |
462 | struct asm_barrier_opt |
463 | { | |
e797f7e0 MGD |
464 | const char * template_name; |
465 | unsigned long value; | |
466 | const arm_feature_set arch; | |
62b3e311 PB |
467 | }; |
468 | ||
2d2255b5 | 469 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
470 | #define SPSR_BIT (1 << 22) |
471 | ||
c19d1205 ZW |
472 | /* The individual PSR flag bits. */ |
473 | #define PSR_c (1 << 16) | |
474 | #define PSR_x (1 << 17) | |
475 | #define PSR_s (1 << 18) | |
476 | #define PSR_f (1 << 19) | |
b99bd4ef | 477 | |
c19d1205 | 478 | struct reloc_entry |
bfae80f2 | 479 | { |
c921be7d NC |
480 | char * name; |
481 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
482 | }; |
483 | ||
5287ad62 | 484 | enum vfp_reg_pos |
bfae80f2 | 485 | { |
5287ad62 JB |
486 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
487 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
488 | }; |
489 | ||
490 | enum vfp_ldstm_type | |
491 | { | |
492 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
493 | }; | |
494 | ||
dcbf9037 JB |
495 | /* Bits for DEFINED field in neon_typed_alias. */ |
496 | #define NTA_HASTYPE 1 | |
497 | #define NTA_HASINDEX 2 | |
498 | ||
499 | struct neon_typed_alias | |
500 | { | |
c921be7d NC |
501 | unsigned char defined; |
502 | unsigned char index; | |
503 | struct neon_type_el eltype; | |
dcbf9037 JB |
504 | }; |
505 | ||
c19d1205 ZW |
506 | /* ARM register categories. This includes coprocessor numbers and various |
507 | architecture extensions' registers. */ | |
508 | enum arm_reg_type | |
bfae80f2 | 509 | { |
c19d1205 ZW |
510 | REG_TYPE_RN, |
511 | REG_TYPE_CP, | |
512 | REG_TYPE_CN, | |
513 | REG_TYPE_FN, | |
514 | REG_TYPE_VFS, | |
515 | REG_TYPE_VFD, | |
5287ad62 | 516 | REG_TYPE_NQ, |
037e8744 | 517 | REG_TYPE_VFSD, |
5287ad62 | 518 | REG_TYPE_NDQ, |
037e8744 | 519 | REG_TYPE_NSDQ, |
c19d1205 ZW |
520 | REG_TYPE_VFC, |
521 | REG_TYPE_MVF, | |
522 | REG_TYPE_MVD, | |
523 | REG_TYPE_MVFX, | |
524 | REG_TYPE_MVDX, | |
525 | REG_TYPE_MVAX, | |
526 | REG_TYPE_DSPSC, | |
527 | REG_TYPE_MMXWR, | |
528 | REG_TYPE_MMXWC, | |
529 | REG_TYPE_MMXWCG, | |
530 | REG_TYPE_XSCALE, | |
90ec0d68 | 531 | REG_TYPE_RNB |
bfae80f2 RE |
532 | }; |
533 | ||
dcbf9037 JB |
534 | /* Structure for a hash table entry for a register. |
535 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
536 | information which states whether a vector type or index is specified (for a | |
537 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
538 | struct reg_entry |
539 | { | |
c921be7d | 540 | const char * name; |
90ec0d68 | 541 | unsigned int number; |
c921be7d NC |
542 | unsigned char type; |
543 | unsigned char builtin; | |
544 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
545 | }; |
546 | ||
c19d1205 | 547 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 548 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
549 | { |
550 | N_("ARM register expected"), | |
551 | N_("bad or missing co-processor number"), | |
552 | N_("co-processor register expected"), | |
553 | N_("FPA register expected"), | |
554 | N_("VFP single precision register expected"), | |
5287ad62 JB |
555 | N_("VFP/Neon double precision register expected"), |
556 | N_("Neon quad precision register expected"), | |
037e8744 | 557 | N_("VFP single or double precision register expected"), |
5287ad62 | 558 | N_("Neon double or quad precision register expected"), |
037e8744 | 559 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
560 | N_("VFP system register expected"), |
561 | N_("Maverick MVF register expected"), | |
562 | N_("Maverick MVD register expected"), | |
563 | N_("Maverick MVFX register expected"), | |
564 | N_("Maverick MVDX register expected"), | |
565 | N_("Maverick MVAX register expected"), | |
566 | N_("Maverick DSPSC register expected"), | |
567 | N_("iWMMXt data register expected"), | |
568 | N_("iWMMXt control register expected"), | |
569 | N_("iWMMXt scalar register expected"), | |
570 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
571 | }; |
572 | ||
c19d1205 | 573 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 574 | #define REG_R12 12 |
c19d1205 ZW |
575 | #define REG_SP 13 |
576 | #define REG_LR 14 | |
577 | #define REG_PC 15 | |
404ff6b5 | 578 | |
b99bd4ef NC |
579 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
580 | take 2: */ | |
c19d1205 | 581 | #define INSN_SIZE 4 |
b99bd4ef NC |
582 | |
583 | struct asm_opcode | |
584 | { | |
585 | /* Basic string to match. */ | |
d3ce72d0 | 586 | const char * template_name; |
c19d1205 ZW |
587 | |
588 | /* Parameters to instruction. */ | |
5be8be5d | 589 | unsigned int operands[8]; |
c19d1205 ZW |
590 | |
591 | /* Conditional tag - see opcode_lookup. */ | |
592 | unsigned int tag : 4; | |
b99bd4ef NC |
593 | |
594 | /* Basic instruction code. */ | |
c19d1205 | 595 | unsigned int avalue : 28; |
b99bd4ef | 596 | |
c19d1205 ZW |
597 | /* Thumb-format instruction code. */ |
598 | unsigned int tvalue; | |
b99bd4ef | 599 | |
90e4755a | 600 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
601 | const arm_feature_set * avariant; |
602 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
603 | |
604 | /* Function to call to encode instruction in ARM format. */ | |
605 | void (* aencode) (void); | |
b99bd4ef | 606 | |
c19d1205 ZW |
607 | /* Function to call to encode instruction in Thumb format. */ |
608 | void (* tencode) (void); | |
b99bd4ef NC |
609 | }; |
610 | ||
a737bd4d NC |
611 | /* Defines for various bits that we will want to toggle. */ |
612 | #define INST_IMMEDIATE 0x02000000 | |
613 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 614 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
615 | #define SHIFT_BY_REG 0x00000010 |
616 | #define PRE_INDEX 0x01000000 | |
617 | #define INDEX_UP 0x00800000 | |
618 | #define WRITE_BACK 0x00200000 | |
619 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 620 | #define CPSI_MMOD 0x00020000 |
90e4755a | 621 | |
a737bd4d NC |
622 | #define LITERAL_MASK 0xf000f000 |
623 | #define OPCODE_MASK 0xfe1fffff | |
624 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 625 | |
efd81785 PB |
626 | #define T2_SUBS_PC_LR 0xf3de8f00 |
627 | ||
a737bd4d | 628 | #define DATA_OP_SHIFT 21 |
90e4755a | 629 | |
ef8d22e6 PB |
630 | #define T2_OPCODE_MASK 0xfe1fffff |
631 | #define T2_DATA_OP_SHIFT 21 | |
632 | ||
6530b175 NC |
633 | #define A_COND_MASK 0xf0000000 |
634 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
635 | ||
636 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
637 | #define A1_OPCODE_PUSH 0x092d0000 | |
638 | #define A2_OPCODE_PUSH 0x052d0004 | |
639 | #define A2_OPCODE_POP 0x049d0004 | |
640 | ||
a737bd4d NC |
641 | /* Codes to distinguish the arithmetic instructions. */ |
642 | #define OPCODE_AND 0 | |
643 | #define OPCODE_EOR 1 | |
644 | #define OPCODE_SUB 2 | |
645 | #define OPCODE_RSB 3 | |
646 | #define OPCODE_ADD 4 | |
647 | #define OPCODE_ADC 5 | |
648 | #define OPCODE_SBC 6 | |
649 | #define OPCODE_RSC 7 | |
650 | #define OPCODE_TST 8 | |
651 | #define OPCODE_TEQ 9 | |
652 | #define OPCODE_CMP 10 | |
653 | #define OPCODE_CMN 11 | |
654 | #define OPCODE_ORR 12 | |
655 | #define OPCODE_MOV 13 | |
656 | #define OPCODE_BIC 14 | |
657 | #define OPCODE_MVN 15 | |
90e4755a | 658 | |
ef8d22e6 PB |
659 | #define T2_OPCODE_AND 0 |
660 | #define T2_OPCODE_BIC 1 | |
661 | #define T2_OPCODE_ORR 2 | |
662 | #define T2_OPCODE_ORN 3 | |
663 | #define T2_OPCODE_EOR 4 | |
664 | #define T2_OPCODE_ADD 8 | |
665 | #define T2_OPCODE_ADC 10 | |
666 | #define T2_OPCODE_SBC 11 | |
667 | #define T2_OPCODE_SUB 13 | |
668 | #define T2_OPCODE_RSB 14 | |
669 | ||
a737bd4d NC |
670 | #define T_OPCODE_MUL 0x4340 |
671 | #define T_OPCODE_TST 0x4200 | |
672 | #define T_OPCODE_CMN 0x42c0 | |
673 | #define T_OPCODE_NEG 0x4240 | |
674 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 675 | |
a737bd4d NC |
676 | #define T_OPCODE_ADD_R3 0x1800 |
677 | #define T_OPCODE_SUB_R3 0x1a00 | |
678 | #define T_OPCODE_ADD_HI 0x4400 | |
679 | #define T_OPCODE_ADD_ST 0xb000 | |
680 | #define T_OPCODE_SUB_ST 0xb080 | |
681 | #define T_OPCODE_ADD_SP 0xa800 | |
682 | #define T_OPCODE_ADD_PC 0xa000 | |
683 | #define T_OPCODE_ADD_I8 0x3000 | |
684 | #define T_OPCODE_SUB_I8 0x3800 | |
685 | #define T_OPCODE_ADD_I3 0x1c00 | |
686 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 687 | |
a737bd4d NC |
688 | #define T_OPCODE_ASR_R 0x4100 |
689 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
690 | #define T_OPCODE_LSR_R 0x40c0 |
691 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
692 | #define T_OPCODE_ASR_I 0x1000 |
693 | #define T_OPCODE_LSL_I 0x0000 | |
694 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 695 | |
a737bd4d NC |
696 | #define T_OPCODE_MOV_I8 0x2000 |
697 | #define T_OPCODE_CMP_I8 0x2800 | |
698 | #define T_OPCODE_CMP_LR 0x4280 | |
699 | #define T_OPCODE_MOV_HR 0x4600 | |
700 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 701 | |
a737bd4d NC |
702 | #define T_OPCODE_LDR_PC 0x4800 |
703 | #define T_OPCODE_LDR_SP 0x9800 | |
704 | #define T_OPCODE_STR_SP 0x9000 | |
705 | #define T_OPCODE_LDR_IW 0x6800 | |
706 | #define T_OPCODE_STR_IW 0x6000 | |
707 | #define T_OPCODE_LDR_IH 0x8800 | |
708 | #define T_OPCODE_STR_IH 0x8000 | |
709 | #define T_OPCODE_LDR_IB 0x7800 | |
710 | #define T_OPCODE_STR_IB 0x7000 | |
711 | #define T_OPCODE_LDR_RW 0x5800 | |
712 | #define T_OPCODE_STR_RW 0x5000 | |
713 | #define T_OPCODE_LDR_RH 0x5a00 | |
714 | #define T_OPCODE_STR_RH 0x5200 | |
715 | #define T_OPCODE_LDR_RB 0x5c00 | |
716 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 717 | |
a737bd4d NC |
718 | #define T_OPCODE_PUSH 0xb400 |
719 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 720 | |
2fc8bdac | 721 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 722 | |
a737bd4d | 723 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 724 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 725 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 726 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
727 | |
728 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 729 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
730 | #define BAD_PC _("r15 not allowed here") |
731 | #define BAD_COND _("instruction cannot be conditional") | |
732 | #define BAD_OVERLAP _("registers may not be the same") | |
733 | #define BAD_HIREG _("lo register required") | |
734 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 735 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
736 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
737 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 738 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
739 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
740 | #define BAD_IT_COND _("incorrect condition in IT block") | |
741 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 742 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
743 | #define BAD_PC_ADDRESSING \ |
744 | _("cannot use register index with PC-relative addressing") | |
745 | #define BAD_PC_WRITEBACK \ | |
746 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 747 | #define BAD_RANGE _("branch out of range") |
c19d1205 | 748 | |
c921be7d NC |
749 | static struct hash_control * arm_ops_hsh; |
750 | static struct hash_control * arm_cond_hsh; | |
751 | static struct hash_control * arm_shift_hsh; | |
752 | static struct hash_control * arm_psr_hsh; | |
753 | static struct hash_control * arm_v7m_psr_hsh; | |
754 | static struct hash_control * arm_reg_hsh; | |
755 | static struct hash_control * arm_reloc_hsh; | |
756 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 757 | |
b99bd4ef NC |
758 | /* Stuff needed to resolve the label ambiguity |
759 | As: | |
760 | ... | |
761 | label: <insn> | |
762 | may differ from: | |
763 | ... | |
764 | label: | |
5f4273c7 | 765 | <insn> */ |
b99bd4ef NC |
766 | |
767 | symbolS * last_label_seen; | |
b34976b6 | 768 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 769 | |
3d0c9500 NC |
770 | /* Literal pool structure. Held on a per-section |
771 | and per-sub-section basis. */ | |
a737bd4d | 772 | |
c19d1205 | 773 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 774 | typedef struct literal_pool |
b99bd4ef | 775 | { |
c921be7d NC |
776 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
777 | unsigned int next_free_entry; | |
778 | unsigned int id; | |
779 | symbolS * symbol; | |
780 | segT section; | |
781 | subsegT sub_section; | |
a8040cf2 NC |
782 | #ifdef OBJ_ELF |
783 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
784 | #endif | |
c921be7d | 785 | struct literal_pool * next; |
3d0c9500 | 786 | } literal_pool; |
b99bd4ef | 787 | |
3d0c9500 NC |
788 | /* Pointer to a linked list of literal pools. */ |
789 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 790 | |
e07e6e58 NC |
791 | #ifdef OBJ_ELF |
792 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
793 | #else | |
794 | static struct current_it now_it; | |
795 | #endif | |
796 | ||
797 | static inline int | |
798 | now_it_compatible (int cond) | |
799 | { | |
800 | return (cond & ~1) == (now_it.cc & ~1); | |
801 | } | |
802 | ||
803 | static inline int | |
804 | conditional_insn (void) | |
805 | { | |
806 | return inst.cond != COND_ALWAYS; | |
807 | } | |
808 | ||
809 | static int in_it_block (void); | |
810 | ||
811 | static int handle_it_state (void); | |
812 | ||
813 | static void force_automatic_it_block_close (void); | |
814 | ||
c921be7d NC |
815 | static void it_fsm_post_encode (void); |
816 | ||
e07e6e58 NC |
817 | #define set_it_insn_type(type) \ |
818 | do \ | |
819 | { \ | |
820 | inst.it_insn_type = type; \ | |
821 | if (handle_it_state () == FAIL) \ | |
822 | return; \ | |
823 | } \ | |
824 | while (0) | |
825 | ||
c921be7d NC |
826 | #define set_it_insn_type_nonvoid(type, failret) \ |
827 | do \ | |
828 | { \ | |
829 | inst.it_insn_type = type; \ | |
830 | if (handle_it_state () == FAIL) \ | |
831 | return failret; \ | |
832 | } \ | |
833 | while(0) | |
834 | ||
e07e6e58 NC |
835 | #define set_it_insn_type_last() \ |
836 | do \ | |
837 | { \ | |
838 | if (inst.cond == COND_ALWAYS) \ | |
839 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
840 | else \ | |
841 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
842 | } \ | |
843 | while (0) | |
844 | ||
c19d1205 | 845 | /* Pure syntax. */ |
b99bd4ef | 846 | |
c19d1205 ZW |
847 | /* This array holds the chars that always start a comment. If the |
848 | pre-processor is disabled, these aren't very useful. */ | |
849 | const char comment_chars[] = "@"; | |
3d0c9500 | 850 | |
c19d1205 ZW |
851 | /* This array holds the chars that only start a comment at the beginning of |
852 | a line. If the line seems to have the form '# 123 filename' | |
853 | .line and .file directives will appear in the pre-processed output. */ | |
854 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
855 | first line of the input file. This is because the compiler outputs | |
856 | #NO_APP at the beginning of its output. */ | |
857 | /* Also note that comments like this one will always work. */ | |
858 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 859 | |
c19d1205 | 860 | const char line_separator_chars[] = ";"; |
b99bd4ef | 861 | |
c19d1205 ZW |
862 | /* Chars that can be used to separate mant |
863 | from exp in floating point numbers. */ | |
864 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 865 | |
c19d1205 ZW |
866 | /* Chars that mean this number is a floating point constant. */ |
867 | /* As in 0f12.456 */ | |
868 | /* or 0d1.2345e12 */ | |
b99bd4ef | 869 | |
c19d1205 | 870 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 871 | |
c19d1205 ZW |
872 | /* Prefix characters that indicate the start of an immediate |
873 | value. */ | |
874 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 875 | |
c19d1205 ZW |
876 | /* Separator character handling. */ |
877 | ||
878 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
879 | ||
880 | static inline int | |
881 | skip_past_char (char ** str, char c) | |
882 | { | |
883 | if (**str == c) | |
884 | { | |
885 | (*str)++; | |
886 | return SUCCESS; | |
3d0c9500 | 887 | } |
c19d1205 ZW |
888 | else |
889 | return FAIL; | |
890 | } | |
c921be7d | 891 | |
c19d1205 | 892 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 893 | |
c19d1205 ZW |
894 | /* Arithmetic expressions (possibly involving symbols). */ |
895 | ||
896 | /* Return TRUE if anything in the expression is a bignum. */ | |
897 | ||
898 | static int | |
899 | walk_no_bignums (symbolS * sp) | |
900 | { | |
901 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
902 | return 1; | |
903 | ||
904 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 905 | { |
c19d1205 ZW |
906 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
907 | || (symbol_get_value_expression (sp)->X_op_symbol | |
908 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
909 | } |
910 | ||
c19d1205 | 911 | return 0; |
3d0c9500 NC |
912 | } |
913 | ||
c19d1205 ZW |
914 | static int in_my_get_expression = 0; |
915 | ||
916 | /* Third argument to my_get_expression. */ | |
917 | #define GE_NO_PREFIX 0 | |
918 | #define GE_IMM_PREFIX 1 | |
919 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
920 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
921 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
922 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 923 | |
b99bd4ef | 924 | static int |
c19d1205 | 925 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 926 | { |
c19d1205 ZW |
927 | char * save_in; |
928 | segT seg; | |
b99bd4ef | 929 | |
c19d1205 ZW |
930 | /* In unified syntax, all prefixes are optional. */ |
931 | if (unified_syntax) | |
5287ad62 JB |
932 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
933 | : GE_OPT_PREFIX; | |
b99bd4ef | 934 | |
c19d1205 | 935 | switch (prefix_mode) |
b99bd4ef | 936 | { |
c19d1205 ZW |
937 | case GE_NO_PREFIX: break; |
938 | case GE_IMM_PREFIX: | |
939 | if (!is_immediate_prefix (**str)) | |
940 | { | |
941 | inst.error = _("immediate expression requires a # prefix"); | |
942 | return FAIL; | |
943 | } | |
944 | (*str)++; | |
945 | break; | |
946 | case GE_OPT_PREFIX: | |
5287ad62 | 947 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
948 | if (is_immediate_prefix (**str)) |
949 | (*str)++; | |
950 | break; | |
951 | default: abort (); | |
952 | } | |
b99bd4ef | 953 | |
c19d1205 | 954 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 955 | |
c19d1205 ZW |
956 | save_in = input_line_pointer; |
957 | input_line_pointer = *str; | |
958 | in_my_get_expression = 1; | |
959 | seg = expression (ep); | |
960 | in_my_get_expression = 0; | |
961 | ||
f86adc07 | 962 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 963 | { |
f86adc07 | 964 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
965 | *str = input_line_pointer; |
966 | input_line_pointer = save_in; | |
967 | if (inst.error == NULL) | |
f86adc07 NS |
968 | inst.error = (ep->X_op == O_absent |
969 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
970 | return 1; |
971 | } | |
b99bd4ef | 972 | |
c19d1205 ZW |
973 | #ifdef OBJ_AOUT |
974 | if (seg != absolute_section | |
975 | && seg != text_section | |
976 | && seg != data_section | |
977 | && seg != bss_section | |
978 | && seg != undefined_section) | |
979 | { | |
980 | inst.error = _("bad segment"); | |
981 | *str = input_line_pointer; | |
982 | input_line_pointer = save_in; | |
983 | return 1; | |
b99bd4ef | 984 | } |
87975d2a AM |
985 | #else |
986 | (void) seg; | |
c19d1205 | 987 | #endif |
b99bd4ef | 988 | |
c19d1205 ZW |
989 | /* Get rid of any bignums now, so that we don't generate an error for which |
990 | we can't establish a line number later on. Big numbers are never valid | |
991 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
992 | if (prefix_mode != GE_OPT_PREFIX_BIG |
993 | && (ep->X_op == O_big | |
994 | || (ep->X_add_symbol | |
995 | && (walk_no_bignums (ep->X_add_symbol) | |
996 | || (ep->X_op_symbol | |
997 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
998 | { |
999 | inst.error = _("invalid constant"); | |
1000 | *str = input_line_pointer; | |
1001 | input_line_pointer = save_in; | |
1002 | return 1; | |
1003 | } | |
b99bd4ef | 1004 | |
c19d1205 ZW |
1005 | *str = input_line_pointer; |
1006 | input_line_pointer = save_in; | |
1007 | return 0; | |
b99bd4ef NC |
1008 | } |
1009 | ||
c19d1205 ZW |
1010 | /* Turn a string in input_line_pointer into a floating point constant |
1011 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1012 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1013 | returned, or NULL on OK. | |
b99bd4ef | 1014 | |
c19d1205 ZW |
1015 | Note that fp constants aren't represent in the normal way on the ARM. |
1016 | In big endian mode, things are as expected. However, in little endian | |
1017 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1018 | within the words. For example, (double) 1.1 in big endian mode is | |
1019 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1020 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1021 | |
c19d1205 | 1022 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1023 | |
c19d1205 ZW |
1024 | char * |
1025 | md_atof (int type, char * litP, int * sizeP) | |
1026 | { | |
1027 | int prec; | |
1028 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1029 | char *t; | |
1030 | int i; | |
b99bd4ef | 1031 | |
c19d1205 ZW |
1032 | switch (type) |
1033 | { | |
1034 | case 'f': | |
1035 | case 'F': | |
1036 | case 's': | |
1037 | case 'S': | |
1038 | prec = 2; | |
1039 | break; | |
b99bd4ef | 1040 | |
c19d1205 ZW |
1041 | case 'd': |
1042 | case 'D': | |
1043 | case 'r': | |
1044 | case 'R': | |
1045 | prec = 4; | |
1046 | break; | |
b99bd4ef | 1047 | |
c19d1205 ZW |
1048 | case 'x': |
1049 | case 'X': | |
499ac353 | 1050 | prec = 5; |
c19d1205 | 1051 | break; |
b99bd4ef | 1052 | |
c19d1205 ZW |
1053 | case 'p': |
1054 | case 'P': | |
499ac353 | 1055 | prec = 5; |
c19d1205 | 1056 | break; |
a737bd4d | 1057 | |
c19d1205 ZW |
1058 | default: |
1059 | *sizeP = 0; | |
499ac353 | 1060 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1061 | } |
b99bd4ef | 1062 | |
c19d1205 ZW |
1063 | t = atof_ieee (input_line_pointer, type, words); |
1064 | if (t) | |
1065 | input_line_pointer = t; | |
499ac353 | 1066 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1067 | |
c19d1205 ZW |
1068 | if (target_big_endian) |
1069 | { | |
1070 | for (i = 0; i < prec; i++) | |
1071 | { | |
499ac353 NC |
1072 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1073 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1074 | } |
1075 | } | |
1076 | else | |
1077 | { | |
e74cfd16 | 1078 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1079 | for (i = prec - 1; i >= 0; i--) |
1080 | { | |
499ac353 NC |
1081 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1082 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1083 | } |
1084 | else | |
1085 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1086 | For an 8 byte float the order is 1 0 3 2. */ | |
1087 | for (i = 0; i < prec; i += 2) | |
1088 | { | |
499ac353 NC |
1089 | md_number_to_chars (litP, (valueT) words[i + 1], |
1090 | sizeof (LITTLENUM_TYPE)); | |
1091 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1092 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1093 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1094 | } |
1095 | } | |
b99bd4ef | 1096 | |
499ac353 | 1097 | return NULL; |
c19d1205 | 1098 | } |
b99bd4ef | 1099 | |
c19d1205 ZW |
1100 | /* We handle all bad expressions here, so that we can report the faulty |
1101 | instruction in the error message. */ | |
1102 | void | |
91d6fa6a | 1103 | md_operand (expressionS * exp) |
c19d1205 ZW |
1104 | { |
1105 | if (in_my_get_expression) | |
91d6fa6a | 1106 | exp->X_op = O_illegal; |
b99bd4ef NC |
1107 | } |
1108 | ||
c19d1205 | 1109 | /* Immediate values. */ |
b99bd4ef | 1110 | |
c19d1205 ZW |
1111 | /* Generic immediate-value read function for use in directives. |
1112 | Accepts anything that 'expression' can fold to a constant. | |
1113 | *val receives the number. */ | |
1114 | #ifdef OBJ_ELF | |
1115 | static int | |
1116 | immediate_for_directive (int *val) | |
b99bd4ef | 1117 | { |
c19d1205 ZW |
1118 | expressionS exp; |
1119 | exp.X_op = O_illegal; | |
b99bd4ef | 1120 | |
c19d1205 ZW |
1121 | if (is_immediate_prefix (*input_line_pointer)) |
1122 | { | |
1123 | input_line_pointer++; | |
1124 | expression (&exp); | |
1125 | } | |
b99bd4ef | 1126 | |
c19d1205 ZW |
1127 | if (exp.X_op != O_constant) |
1128 | { | |
1129 | as_bad (_("expected #constant")); | |
1130 | ignore_rest_of_line (); | |
1131 | return FAIL; | |
1132 | } | |
1133 | *val = exp.X_add_number; | |
1134 | return SUCCESS; | |
b99bd4ef | 1135 | } |
c19d1205 | 1136 | #endif |
b99bd4ef | 1137 | |
c19d1205 | 1138 | /* Register parsing. */ |
b99bd4ef | 1139 | |
c19d1205 ZW |
1140 | /* Generic register parser. CCP points to what should be the |
1141 | beginning of a register name. If it is indeed a valid register | |
1142 | name, advance CCP over it and return the reg_entry structure; | |
1143 | otherwise return NULL. Does not issue diagnostics. */ | |
1144 | ||
1145 | static struct reg_entry * | |
1146 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1147 | { |
c19d1205 ZW |
1148 | char *start = *ccp; |
1149 | char *p; | |
1150 | struct reg_entry *reg; | |
b99bd4ef | 1151 | |
c19d1205 ZW |
1152 | #ifdef REGISTER_PREFIX |
1153 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1154 | return NULL; |
c19d1205 ZW |
1155 | start++; |
1156 | #endif | |
1157 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1158 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1159 | start++; | |
1160 | #endif | |
b99bd4ef | 1161 | |
c19d1205 ZW |
1162 | p = start; |
1163 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1164 | return NULL; | |
b99bd4ef | 1165 | |
c19d1205 ZW |
1166 | do |
1167 | p++; | |
1168 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1169 | ||
1170 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1171 | ||
1172 | if (!reg) | |
1173 | return NULL; | |
1174 | ||
1175 | *ccp = p; | |
1176 | return reg; | |
b99bd4ef NC |
1177 | } |
1178 | ||
1179 | static int | |
dcbf9037 JB |
1180 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1181 | enum arm_reg_type type) | |
b99bd4ef | 1182 | { |
c19d1205 ZW |
1183 | /* Alternative syntaxes are accepted for a few register classes. */ |
1184 | switch (type) | |
1185 | { | |
1186 | case REG_TYPE_MVF: | |
1187 | case REG_TYPE_MVD: | |
1188 | case REG_TYPE_MVFX: | |
1189 | case REG_TYPE_MVDX: | |
1190 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1191 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1192 | return reg->number; |
1193 | break; | |
69b97547 | 1194 | |
c19d1205 ZW |
1195 | case REG_TYPE_CP: |
1196 | /* For backward compatibility, a bare number is valid here. */ | |
1197 | { | |
1198 | unsigned long processor = strtoul (start, ccp, 10); | |
1199 | if (*ccp != start && processor <= 15) | |
1200 | return processor; | |
1201 | } | |
6057a28f | 1202 | |
c19d1205 ZW |
1203 | case REG_TYPE_MMXWC: |
1204 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1205 | instructions that take WC registers. */ | |
79134647 | 1206 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1207 | return reg->number; |
6057a28f | 1208 | break; |
c19d1205 | 1209 | |
6057a28f | 1210 | default: |
c19d1205 | 1211 | break; |
6057a28f NC |
1212 | } |
1213 | ||
dcbf9037 JB |
1214 | return FAIL; |
1215 | } | |
1216 | ||
1217 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1218 | return value is the register number or FAIL. */ | |
1219 | ||
1220 | static int | |
1221 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1222 | { | |
1223 | char *start = *ccp; | |
1224 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1225 | int ret; | |
1226 | ||
1227 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1228 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1229 | return FAIL; | |
1230 | ||
1231 | if (reg && reg->type == type) | |
1232 | return reg->number; | |
1233 | ||
1234 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1235 | return ret; | |
1236 | ||
c19d1205 ZW |
1237 | *ccp = start; |
1238 | return FAIL; | |
1239 | } | |
69b97547 | 1240 | |
dcbf9037 JB |
1241 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1242 | character. Does no verification at this stage that the type fits the opcode | |
1243 | properly. E.g., | |
1244 | ||
1245 | .i32.i32.s16 | |
1246 | .s32.f32 | |
1247 | .u16 | |
1248 | ||
1249 | Can all be legally parsed by this function. | |
1250 | ||
1251 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1252 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1253 | type, FAIL if not. */ | |
1254 | ||
1255 | static int | |
1256 | parse_neon_type (struct neon_type *type, char **str) | |
1257 | { | |
1258 | char *ptr = *str; | |
1259 | ||
1260 | if (type) | |
1261 | type->elems = 0; | |
1262 | ||
1263 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1264 | { | |
1265 | enum neon_el_type thistype = NT_untyped; | |
1266 | unsigned thissize = -1u; | |
1267 | ||
1268 | if (*ptr != '.') | |
1269 | break; | |
1270 | ||
1271 | ptr++; | |
1272 | ||
1273 | /* Just a size without an explicit type. */ | |
1274 | if (ISDIGIT (*ptr)) | |
1275 | goto parsesize; | |
1276 | ||
1277 | switch (TOLOWER (*ptr)) | |
1278 | { | |
1279 | case 'i': thistype = NT_integer; break; | |
1280 | case 'f': thistype = NT_float; break; | |
1281 | case 'p': thistype = NT_poly; break; | |
1282 | case 's': thistype = NT_signed; break; | |
1283 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1284 | case 'd': |
1285 | thistype = NT_float; | |
1286 | thissize = 64; | |
1287 | ptr++; | |
1288 | goto done; | |
dcbf9037 JB |
1289 | default: |
1290 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1291 | return FAIL; | |
1292 | } | |
1293 | ||
1294 | ptr++; | |
1295 | ||
1296 | /* .f is an abbreviation for .f32. */ | |
1297 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1298 | thissize = 32; | |
1299 | else | |
1300 | { | |
1301 | parsesize: | |
1302 | thissize = strtoul (ptr, &ptr, 10); | |
1303 | ||
1304 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1305 | && thissize != 64) | |
1306 | { | |
1307 | as_bad (_("bad size %d in type specifier"), thissize); | |
1308 | return FAIL; | |
1309 | } | |
1310 | } | |
1311 | ||
037e8744 | 1312 | done: |
dcbf9037 JB |
1313 | if (type) |
1314 | { | |
1315 | type->el[type->elems].type = thistype; | |
1316 | type->el[type->elems].size = thissize; | |
1317 | type->elems++; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /* Empty/missing type is not a successful parse. */ | |
1322 | if (type->elems == 0) | |
1323 | return FAIL; | |
1324 | ||
1325 | *str = ptr; | |
1326 | ||
1327 | return SUCCESS; | |
1328 | } | |
1329 | ||
1330 | /* Errors may be set multiple times during parsing or bit encoding | |
1331 | (particularly in the Neon bits), but usually the earliest error which is set | |
1332 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1333 | errors by calling this function. */ | |
1334 | ||
1335 | static void | |
1336 | first_error (const char *err) | |
1337 | { | |
1338 | if (!inst.error) | |
1339 | inst.error = err; | |
1340 | } | |
1341 | ||
1342 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1343 | static int | |
1344 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1345 | { | |
1346 | char *str = *ccp; | |
1347 | struct neon_type optype; | |
1348 | ||
1349 | if (*str == '.') | |
1350 | { | |
1351 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1352 | { | |
1353 | if (optype.elems == 1) | |
1354 | *vectype = optype.el[0]; | |
1355 | else | |
1356 | { | |
1357 | first_error (_("only one type should be specified for operand")); | |
1358 | return FAIL; | |
1359 | } | |
1360 | } | |
1361 | else | |
1362 | { | |
1363 | first_error (_("vector type expected")); | |
1364 | return FAIL; | |
1365 | } | |
1366 | } | |
1367 | else | |
1368 | return FAIL; | |
5f4273c7 | 1369 | |
dcbf9037 | 1370 | *ccp = str; |
5f4273c7 | 1371 | |
dcbf9037 JB |
1372 | return SUCCESS; |
1373 | } | |
1374 | ||
1375 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1376 | a 4-bit integer. */ | |
1377 | ||
1378 | #define NEON_ALL_LANES 15 | |
1379 | #define NEON_INTERLEAVE_LANES 14 | |
1380 | ||
1381 | /* Parse either a register or a scalar, with an optional type. Return the | |
1382 | register number, and optionally fill in the actual type of the register | |
1383 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1384 | type/index information in *TYPEINFO. */ | |
1385 | ||
1386 | static int | |
1387 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1388 | enum arm_reg_type *rtype, | |
1389 | struct neon_typed_alias *typeinfo) | |
1390 | { | |
1391 | char *str = *ccp; | |
1392 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1393 | struct neon_typed_alias atype; | |
1394 | struct neon_type_el parsetype; | |
1395 | ||
1396 | atype.defined = 0; | |
1397 | atype.index = -1; | |
1398 | atype.eltype.type = NT_invtype; | |
1399 | atype.eltype.size = -1; | |
1400 | ||
1401 | /* Try alternate syntax for some types of register. Note these are mutually | |
1402 | exclusive with the Neon syntax extensions. */ | |
1403 | if (reg == NULL) | |
1404 | { | |
1405 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1406 | if (altreg != FAIL) | |
1407 | *ccp = str; | |
1408 | if (typeinfo) | |
1409 | *typeinfo = atype; | |
1410 | return altreg; | |
1411 | } | |
1412 | ||
037e8744 JB |
1413 | /* Undo polymorphism when a set of register types may be accepted. */ |
1414 | if ((type == REG_TYPE_NDQ | |
1415 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1416 | || (type == REG_TYPE_VFSD | |
1417 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1418 | || (type == REG_TYPE_NSDQ | |
1419 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1420 | || reg->type == REG_TYPE_NQ)) |
1421 | || (type == REG_TYPE_MMXWC | |
1422 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1423 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1424 | |
1425 | if (type != reg->type) | |
1426 | return FAIL; | |
1427 | ||
1428 | if (reg->neon) | |
1429 | atype = *reg->neon; | |
5f4273c7 | 1430 | |
dcbf9037 JB |
1431 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1432 | { | |
1433 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1434 | { | |
1435 | first_error (_("can't redefine type for operand")); | |
1436 | return FAIL; | |
1437 | } | |
1438 | atype.defined |= NTA_HASTYPE; | |
1439 | atype.eltype = parsetype; | |
1440 | } | |
5f4273c7 | 1441 | |
dcbf9037 JB |
1442 | if (skip_past_char (&str, '[') == SUCCESS) |
1443 | { | |
1444 | if (type != REG_TYPE_VFD) | |
1445 | { | |
1446 | first_error (_("only D registers may be indexed")); | |
1447 | return FAIL; | |
1448 | } | |
5f4273c7 | 1449 | |
dcbf9037 JB |
1450 | if ((atype.defined & NTA_HASINDEX) != 0) |
1451 | { | |
1452 | first_error (_("can't change index for operand")); | |
1453 | return FAIL; | |
1454 | } | |
1455 | ||
1456 | atype.defined |= NTA_HASINDEX; | |
1457 | ||
1458 | if (skip_past_char (&str, ']') == SUCCESS) | |
1459 | atype.index = NEON_ALL_LANES; | |
1460 | else | |
1461 | { | |
1462 | expressionS exp; | |
1463 | ||
1464 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1465 | ||
1466 | if (exp.X_op != O_constant) | |
1467 | { | |
1468 | first_error (_("constant expression required")); | |
1469 | return FAIL; | |
1470 | } | |
1471 | ||
1472 | if (skip_past_char (&str, ']') == FAIL) | |
1473 | return FAIL; | |
1474 | ||
1475 | atype.index = exp.X_add_number; | |
1476 | } | |
1477 | } | |
5f4273c7 | 1478 | |
dcbf9037 JB |
1479 | if (typeinfo) |
1480 | *typeinfo = atype; | |
5f4273c7 | 1481 | |
dcbf9037 JB |
1482 | if (rtype) |
1483 | *rtype = type; | |
5f4273c7 | 1484 | |
dcbf9037 | 1485 | *ccp = str; |
5f4273c7 | 1486 | |
dcbf9037 JB |
1487 | return reg->number; |
1488 | } | |
1489 | ||
1490 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1491 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1492 | register (e.g. Neon double or quad reg when either has been requested). | |
1493 | - If this is a Neon vector type with additional type information, fill | |
1494 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1495 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1496 | |
1497 | static int | |
1498 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1499 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1500 | { | |
1501 | struct neon_typed_alias atype; | |
1502 | char *str = *ccp; | |
1503 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1504 | ||
1505 | if (reg == FAIL) | |
1506 | return FAIL; | |
1507 | ||
0855e32b NS |
1508 | /* Do not allow regname(... to parse as a register. */ |
1509 | if (*str == '(') | |
1510 | return FAIL; | |
1511 | ||
dcbf9037 JB |
1512 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1513 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1514 | { | |
1515 | first_error (_("register operand expected, but got scalar")); | |
1516 | return FAIL; | |
1517 | } | |
1518 | ||
1519 | if (vectype) | |
1520 | *vectype = atype.eltype; | |
1521 | ||
1522 | *ccp = str; | |
1523 | ||
1524 | return reg; | |
1525 | } | |
1526 | ||
1527 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1528 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1529 | ||
5287ad62 JB |
1530 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1531 | have enough information to be able to do a good job bounds-checking. So, we | |
1532 | just do easy checks here, and do further checks later. */ | |
1533 | ||
1534 | static int | |
dcbf9037 | 1535 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1536 | { |
dcbf9037 | 1537 | int reg; |
5287ad62 | 1538 | char *str = *ccp; |
dcbf9037 | 1539 | struct neon_typed_alias atype; |
5f4273c7 | 1540 | |
dcbf9037 | 1541 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1542 | |
dcbf9037 | 1543 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1544 | return FAIL; |
5f4273c7 | 1545 | |
dcbf9037 | 1546 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1547 | { |
dcbf9037 | 1548 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1549 | return FAIL; |
1550 | } | |
dcbf9037 | 1551 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1552 | { |
dcbf9037 | 1553 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1554 | return FAIL; |
1555 | } | |
5f4273c7 | 1556 | |
dcbf9037 JB |
1557 | if (type) |
1558 | *type = atype.eltype; | |
5f4273c7 | 1559 | |
5287ad62 | 1560 | *ccp = str; |
5f4273c7 | 1561 | |
dcbf9037 | 1562 | return reg * 16 + atype.index; |
5287ad62 JB |
1563 | } |
1564 | ||
c19d1205 | 1565 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1566 | |
c19d1205 ZW |
1567 | static long |
1568 | parse_reg_list (char ** strp) | |
1569 | { | |
1570 | char * str = * strp; | |
1571 | long range = 0; | |
1572 | int another_range; | |
a737bd4d | 1573 | |
c19d1205 ZW |
1574 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1575 | do | |
6057a28f | 1576 | { |
c19d1205 | 1577 | another_range = 0; |
a737bd4d | 1578 | |
c19d1205 ZW |
1579 | if (*str == '{') |
1580 | { | |
1581 | int in_range = 0; | |
1582 | int cur_reg = -1; | |
a737bd4d | 1583 | |
c19d1205 ZW |
1584 | str++; |
1585 | do | |
1586 | { | |
1587 | int reg; | |
6057a28f | 1588 | |
dcbf9037 | 1589 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1590 | { |
dcbf9037 | 1591 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1592 | return FAIL; |
1593 | } | |
a737bd4d | 1594 | |
c19d1205 ZW |
1595 | if (in_range) |
1596 | { | |
1597 | int i; | |
a737bd4d | 1598 | |
c19d1205 ZW |
1599 | if (reg <= cur_reg) |
1600 | { | |
dcbf9037 | 1601 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1602 | return FAIL; |
1603 | } | |
40a18ebd | 1604 | |
c19d1205 ZW |
1605 | for (i = cur_reg + 1; i < reg; i++) |
1606 | { | |
1607 | if (range & (1 << i)) | |
1608 | as_tsktsk | |
1609 | (_("Warning: duplicated register (r%d) in register list"), | |
1610 | i); | |
1611 | else | |
1612 | range |= 1 << i; | |
1613 | } | |
1614 | in_range = 0; | |
1615 | } | |
a737bd4d | 1616 | |
c19d1205 ZW |
1617 | if (range & (1 << reg)) |
1618 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1619 | reg); | |
1620 | else if (reg <= cur_reg) | |
1621 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1622 | |
c19d1205 ZW |
1623 | range |= 1 << reg; |
1624 | cur_reg = reg; | |
1625 | } | |
1626 | while (skip_past_comma (&str) != FAIL | |
1627 | || (in_range = 1, *str++ == '-')); | |
1628 | str--; | |
a737bd4d | 1629 | |
c19d1205 ZW |
1630 | if (*str++ != '}') |
1631 | { | |
dcbf9037 | 1632 | first_error (_("missing `}'")); |
c19d1205 ZW |
1633 | return FAIL; |
1634 | } | |
1635 | } | |
1636 | else | |
1637 | { | |
91d6fa6a | 1638 | expressionS exp; |
40a18ebd | 1639 | |
91d6fa6a | 1640 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1641 | return FAIL; |
40a18ebd | 1642 | |
91d6fa6a | 1643 | if (exp.X_op == O_constant) |
c19d1205 | 1644 | { |
91d6fa6a NC |
1645 | if (exp.X_add_number |
1646 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1647 | { |
1648 | inst.error = _("invalid register mask"); | |
1649 | return FAIL; | |
1650 | } | |
a737bd4d | 1651 | |
91d6fa6a | 1652 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1653 | { |
91d6fa6a | 1654 | int regno = range & exp.X_add_number; |
a737bd4d | 1655 | |
c19d1205 ZW |
1656 | regno &= -regno; |
1657 | regno = (1 << regno) - 1; | |
1658 | as_tsktsk | |
1659 | (_("Warning: duplicated register (r%d) in register list"), | |
1660 | regno); | |
1661 | } | |
a737bd4d | 1662 | |
91d6fa6a | 1663 | range |= exp.X_add_number; |
c19d1205 ZW |
1664 | } |
1665 | else | |
1666 | { | |
1667 | if (inst.reloc.type != 0) | |
1668 | { | |
1669 | inst.error = _("expression too complex"); | |
1670 | return FAIL; | |
1671 | } | |
a737bd4d | 1672 | |
91d6fa6a | 1673 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1674 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1675 | inst.reloc.pc_rel = 0; | |
1676 | } | |
1677 | } | |
a737bd4d | 1678 | |
c19d1205 ZW |
1679 | if (*str == '|' || *str == '+') |
1680 | { | |
1681 | str++; | |
1682 | another_range = 1; | |
1683 | } | |
a737bd4d | 1684 | } |
c19d1205 | 1685 | while (another_range); |
a737bd4d | 1686 | |
c19d1205 ZW |
1687 | *strp = str; |
1688 | return range; | |
a737bd4d NC |
1689 | } |
1690 | ||
5287ad62 JB |
1691 | /* Types of registers in a list. */ |
1692 | ||
1693 | enum reg_list_els | |
1694 | { | |
1695 | REGLIST_VFP_S, | |
1696 | REGLIST_VFP_D, | |
1697 | REGLIST_NEON_D | |
1698 | }; | |
1699 | ||
c19d1205 ZW |
1700 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1701 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1702 | register. Parses registers of type ETYPE. |
1703 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1704 | - Q registers can be used to specify pairs of D registers | |
1705 | - { } can be omitted from around a singleton register list | |
1706 | FIXME: This is not implemented, as it would require backtracking in | |
1707 | some cases, e.g.: | |
1708 | vtbl.8 d3,d4,d5 | |
1709 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1710 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1711 | - 32 D registers may be used (also true for VFPv3). |
1712 | FIXME: Types are ignored in these register lists, which is probably a | |
1713 | bug. */ | |
6057a28f | 1714 | |
c19d1205 | 1715 | static int |
037e8744 | 1716 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1717 | { |
037e8744 | 1718 | char *str = *ccp; |
c19d1205 ZW |
1719 | int base_reg; |
1720 | int new_base; | |
21d799b5 | 1721 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1722 | int max_regs = 0; |
c19d1205 ZW |
1723 | int count = 0; |
1724 | int warned = 0; | |
1725 | unsigned long mask = 0; | |
a737bd4d | 1726 | int i; |
6057a28f | 1727 | |
037e8744 | 1728 | if (*str != '{') |
5287ad62 JB |
1729 | { |
1730 | inst.error = _("expecting {"); | |
1731 | return FAIL; | |
1732 | } | |
6057a28f | 1733 | |
037e8744 | 1734 | str++; |
6057a28f | 1735 | |
5287ad62 | 1736 | switch (etype) |
c19d1205 | 1737 | { |
5287ad62 | 1738 | case REGLIST_VFP_S: |
c19d1205 ZW |
1739 | regtype = REG_TYPE_VFS; |
1740 | max_regs = 32; | |
5287ad62 | 1741 | break; |
5f4273c7 | 1742 | |
5287ad62 JB |
1743 | case REGLIST_VFP_D: |
1744 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1745 | break; |
5f4273c7 | 1746 | |
b7fc2769 JB |
1747 | case REGLIST_NEON_D: |
1748 | regtype = REG_TYPE_NDQ; | |
1749 | break; | |
1750 | } | |
1751 | ||
1752 | if (etype != REGLIST_VFP_S) | |
1753 | { | |
b1cc4aeb PB |
1754 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1755 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1756 | { |
1757 | max_regs = 32; | |
1758 | if (thumb_mode) | |
1759 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1760 | fpu_vfp_ext_d32); |
5287ad62 JB |
1761 | else |
1762 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1763 | fpu_vfp_ext_d32); |
5287ad62 JB |
1764 | } |
1765 | else | |
1766 | max_regs = 16; | |
c19d1205 | 1767 | } |
6057a28f | 1768 | |
c19d1205 | 1769 | base_reg = max_regs; |
a737bd4d | 1770 | |
c19d1205 ZW |
1771 | do |
1772 | { | |
5287ad62 | 1773 | int setmask = 1, addregs = 1; |
dcbf9037 | 1774 | |
037e8744 | 1775 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1776 | |
c19d1205 | 1777 | if (new_base == FAIL) |
a737bd4d | 1778 | { |
dcbf9037 | 1779 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1780 | return FAIL; |
1781 | } | |
5f4273c7 | 1782 | |
b7fc2769 JB |
1783 | if (new_base >= max_regs) |
1784 | { | |
1785 | first_error (_("register out of range in list")); | |
1786 | return FAIL; | |
1787 | } | |
5f4273c7 | 1788 | |
5287ad62 JB |
1789 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1790 | if (regtype == REG_TYPE_NQ) | |
1791 | { | |
1792 | setmask = 3; | |
1793 | addregs = 2; | |
1794 | } | |
1795 | ||
c19d1205 ZW |
1796 | if (new_base < base_reg) |
1797 | base_reg = new_base; | |
a737bd4d | 1798 | |
5287ad62 | 1799 | if (mask & (setmask << new_base)) |
c19d1205 | 1800 | { |
dcbf9037 | 1801 | first_error (_("invalid register list")); |
c19d1205 | 1802 | return FAIL; |
a737bd4d | 1803 | } |
a737bd4d | 1804 | |
c19d1205 ZW |
1805 | if ((mask >> new_base) != 0 && ! warned) |
1806 | { | |
1807 | as_tsktsk (_("register list not in ascending order")); | |
1808 | warned = 1; | |
1809 | } | |
0bbf2aa4 | 1810 | |
5287ad62 JB |
1811 | mask |= setmask << new_base; |
1812 | count += addregs; | |
0bbf2aa4 | 1813 | |
037e8744 | 1814 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1815 | { |
1816 | int high_range; | |
0bbf2aa4 | 1817 | |
037e8744 | 1818 | str++; |
0bbf2aa4 | 1819 | |
037e8744 | 1820 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1821 | == FAIL) |
c19d1205 ZW |
1822 | { |
1823 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1824 | return FAIL; | |
1825 | } | |
0bbf2aa4 | 1826 | |
b7fc2769 JB |
1827 | if (high_range >= max_regs) |
1828 | { | |
1829 | first_error (_("register out of range in list")); | |
1830 | return FAIL; | |
1831 | } | |
1832 | ||
5287ad62 JB |
1833 | if (regtype == REG_TYPE_NQ) |
1834 | high_range = high_range + 1; | |
1835 | ||
c19d1205 ZW |
1836 | if (high_range <= new_base) |
1837 | { | |
1838 | inst.error = _("register range not in ascending order"); | |
1839 | return FAIL; | |
1840 | } | |
0bbf2aa4 | 1841 | |
5287ad62 | 1842 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1843 | { |
5287ad62 | 1844 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1845 | { |
c19d1205 ZW |
1846 | inst.error = _("invalid register list"); |
1847 | return FAIL; | |
0bbf2aa4 | 1848 | } |
c19d1205 | 1849 | |
5287ad62 JB |
1850 | mask |= setmask << new_base; |
1851 | count += addregs; | |
0bbf2aa4 | 1852 | } |
0bbf2aa4 | 1853 | } |
0bbf2aa4 | 1854 | } |
037e8744 | 1855 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1856 | |
037e8744 | 1857 | str++; |
0bbf2aa4 | 1858 | |
c19d1205 ZW |
1859 | /* Sanity check -- should have raised a parse error above. */ |
1860 | if (count == 0 || count > max_regs) | |
1861 | abort (); | |
1862 | ||
1863 | *pbase = base_reg; | |
1864 | ||
1865 | /* Final test -- the registers must be consecutive. */ | |
1866 | mask >>= base_reg; | |
1867 | for (i = 0; i < count; i++) | |
1868 | { | |
1869 | if ((mask & (1u << i)) == 0) | |
1870 | { | |
1871 | inst.error = _("non-contiguous register range"); | |
1872 | return FAIL; | |
1873 | } | |
1874 | } | |
1875 | ||
037e8744 JB |
1876 | *ccp = str; |
1877 | ||
c19d1205 | 1878 | return count; |
b99bd4ef NC |
1879 | } |
1880 | ||
dcbf9037 JB |
1881 | /* True if two alias types are the same. */ |
1882 | ||
c921be7d | 1883 | static bfd_boolean |
dcbf9037 JB |
1884 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1885 | { | |
1886 | if (!a && !b) | |
c921be7d | 1887 | return TRUE; |
5f4273c7 | 1888 | |
dcbf9037 | 1889 | if (!a || !b) |
c921be7d | 1890 | return FALSE; |
dcbf9037 JB |
1891 | |
1892 | if (a->defined != b->defined) | |
c921be7d | 1893 | return FALSE; |
5f4273c7 | 1894 | |
dcbf9037 JB |
1895 | if ((a->defined & NTA_HASTYPE) != 0 |
1896 | && (a->eltype.type != b->eltype.type | |
1897 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1898 | return FALSE; |
dcbf9037 JB |
1899 | |
1900 | if ((a->defined & NTA_HASINDEX) != 0 | |
1901 | && (a->index != b->index)) | |
c921be7d | 1902 | return FALSE; |
5f4273c7 | 1903 | |
c921be7d | 1904 | return TRUE; |
dcbf9037 JB |
1905 | } |
1906 | ||
5287ad62 JB |
1907 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1908 | The base register is put in *PBASE. | |
dcbf9037 | 1909 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1910 | the return value. |
1911 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1912 | Bits [6:5] encode the list length (minus one). |
1913 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1914 | |
5287ad62 | 1915 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1916 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1917 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1918 | ||
1919 | static int | |
dcbf9037 JB |
1920 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1921 | struct neon_type_el *eltype) | |
5287ad62 JB |
1922 | { |
1923 | char *ptr = *str; | |
1924 | int base_reg = -1; | |
1925 | int reg_incr = -1; | |
1926 | int count = 0; | |
1927 | int lane = -1; | |
1928 | int leading_brace = 0; | |
1929 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1930 | const char *const incr_error = _("register stride must be 1 or 2"); |
1931 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1932 | struct neon_typed_alias firsttype; |
5f4273c7 | 1933 | |
5287ad62 JB |
1934 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1935 | leading_brace = 1; | |
5f4273c7 | 1936 | |
5287ad62 JB |
1937 | do |
1938 | { | |
dcbf9037 JB |
1939 | struct neon_typed_alias atype; |
1940 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1941 | ||
5287ad62 JB |
1942 | if (getreg == FAIL) |
1943 | { | |
dcbf9037 | 1944 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1945 | return FAIL; |
1946 | } | |
5f4273c7 | 1947 | |
5287ad62 JB |
1948 | if (base_reg == -1) |
1949 | { | |
1950 | base_reg = getreg; | |
1951 | if (rtype == REG_TYPE_NQ) | |
1952 | { | |
1953 | reg_incr = 1; | |
5287ad62 | 1954 | } |
dcbf9037 | 1955 | firsttype = atype; |
5287ad62 JB |
1956 | } |
1957 | else if (reg_incr == -1) | |
1958 | { | |
1959 | reg_incr = getreg - base_reg; | |
1960 | if (reg_incr < 1 || reg_incr > 2) | |
1961 | { | |
dcbf9037 | 1962 | first_error (_(incr_error)); |
5287ad62 JB |
1963 | return FAIL; |
1964 | } | |
1965 | } | |
1966 | else if (getreg != base_reg + reg_incr * count) | |
1967 | { | |
dcbf9037 JB |
1968 | first_error (_(incr_error)); |
1969 | return FAIL; | |
1970 | } | |
1971 | ||
c921be7d | 1972 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1973 | { |
1974 | first_error (_(type_error)); | |
5287ad62 JB |
1975 | return FAIL; |
1976 | } | |
5f4273c7 | 1977 | |
5287ad62 JB |
1978 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1979 | modes. */ | |
1980 | if (ptr[0] == '-') | |
1981 | { | |
dcbf9037 | 1982 | struct neon_typed_alias htype; |
5287ad62 JB |
1983 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1984 | if (lane == -1) | |
1985 | lane = NEON_INTERLEAVE_LANES; | |
1986 | else if (lane != NEON_INTERLEAVE_LANES) | |
1987 | { | |
dcbf9037 | 1988 | first_error (_(type_error)); |
5287ad62 JB |
1989 | return FAIL; |
1990 | } | |
1991 | if (reg_incr == -1) | |
1992 | reg_incr = 1; | |
1993 | else if (reg_incr != 1) | |
1994 | { | |
dcbf9037 | 1995 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1996 | return FAIL; |
1997 | } | |
1998 | ptr++; | |
dcbf9037 | 1999 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
2000 | if (hireg == FAIL) |
2001 | { | |
dcbf9037 JB |
2002 | first_error (_(reg_expected_msgs[rtype])); |
2003 | return FAIL; | |
2004 | } | |
c921be7d | 2005 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
2006 | { |
2007 | first_error (_(type_error)); | |
5287ad62 JB |
2008 | return FAIL; |
2009 | } | |
2010 | count += hireg + dregs - getreg; | |
2011 | continue; | |
2012 | } | |
5f4273c7 | 2013 | |
5287ad62 JB |
2014 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2015 | if (rtype == REG_TYPE_NQ) | |
2016 | { | |
2017 | count += 2; | |
2018 | continue; | |
2019 | } | |
5f4273c7 | 2020 | |
dcbf9037 | 2021 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 2022 | { |
dcbf9037 JB |
2023 | if (lane == -1) |
2024 | lane = atype.index; | |
2025 | else if (lane != atype.index) | |
5287ad62 | 2026 | { |
dcbf9037 JB |
2027 | first_error (_(type_error)); |
2028 | return FAIL; | |
5287ad62 JB |
2029 | } |
2030 | } | |
2031 | else if (lane == -1) | |
2032 | lane = NEON_INTERLEAVE_LANES; | |
2033 | else if (lane != NEON_INTERLEAVE_LANES) | |
2034 | { | |
dcbf9037 | 2035 | first_error (_(type_error)); |
5287ad62 JB |
2036 | return FAIL; |
2037 | } | |
2038 | count++; | |
2039 | } | |
2040 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2041 | |
5287ad62 JB |
2042 | /* No lane set by [x]. We must be interleaving structures. */ |
2043 | if (lane == -1) | |
2044 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2045 | |
5287ad62 JB |
2046 | /* Sanity check. */ |
2047 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2048 | || (count > 1 && reg_incr == -1)) | |
2049 | { | |
dcbf9037 | 2050 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2051 | return FAIL; |
2052 | } | |
2053 | ||
2054 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2055 | { | |
dcbf9037 | 2056 | first_error (_("expected }")); |
5287ad62 JB |
2057 | return FAIL; |
2058 | } | |
5f4273c7 | 2059 | |
5287ad62 JB |
2060 | if (reg_incr == -1) |
2061 | reg_incr = 1; | |
2062 | ||
dcbf9037 JB |
2063 | if (eltype) |
2064 | *eltype = firsttype.eltype; | |
2065 | ||
5287ad62 JB |
2066 | *pbase = base_reg; |
2067 | *str = ptr; | |
5f4273c7 | 2068 | |
5287ad62 JB |
2069 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2070 | } | |
2071 | ||
c19d1205 ZW |
2072 | /* Parse an explicit relocation suffix on an expression. This is |
2073 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2074 | arm_reloc_hsh contains no entries, so this function can only | |
2075 | succeed if there is no () after the word. Returns -1 on error, | |
2076 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2077 | |
c19d1205 ZW |
2078 | static int |
2079 | parse_reloc (char **str) | |
b99bd4ef | 2080 | { |
c19d1205 ZW |
2081 | struct reloc_entry *r; |
2082 | char *p, *q; | |
b99bd4ef | 2083 | |
c19d1205 ZW |
2084 | if (**str != '(') |
2085 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2086 | |
c19d1205 ZW |
2087 | p = *str + 1; |
2088 | q = p; | |
2089 | ||
2090 | while (*q && *q != ')' && *q != ',') | |
2091 | q++; | |
2092 | if (*q != ')') | |
2093 | return -1; | |
2094 | ||
21d799b5 NC |
2095 | if ((r = (struct reloc_entry *) |
2096 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2097 | return -1; |
2098 | ||
2099 | *str = q + 1; | |
2100 | return r->reloc; | |
b99bd4ef NC |
2101 | } |
2102 | ||
c19d1205 ZW |
2103 | /* Directives: register aliases. */ |
2104 | ||
dcbf9037 | 2105 | static struct reg_entry * |
90ec0d68 | 2106 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2107 | { |
d3ce72d0 | 2108 | struct reg_entry *new_reg; |
c19d1205 | 2109 | const char *name; |
b99bd4ef | 2110 | |
d3ce72d0 | 2111 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2112 | { |
d3ce72d0 | 2113 | if (new_reg->builtin) |
c19d1205 | 2114 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2115 | |
c19d1205 ZW |
2116 | /* Only warn about a redefinition if it's not defined as the |
2117 | same register. */ | |
d3ce72d0 | 2118 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2119 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2120 | |
d929913e | 2121 | return NULL; |
c19d1205 | 2122 | } |
b99bd4ef | 2123 | |
c19d1205 | 2124 | name = xstrdup (str); |
d3ce72d0 | 2125 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2126 | |
d3ce72d0 NC |
2127 | new_reg->name = name; |
2128 | new_reg->number = number; | |
2129 | new_reg->type = type; | |
2130 | new_reg->builtin = FALSE; | |
2131 | new_reg->neon = NULL; | |
b99bd4ef | 2132 | |
d3ce72d0 | 2133 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2134 | abort (); |
5f4273c7 | 2135 | |
d3ce72d0 | 2136 | return new_reg; |
dcbf9037 JB |
2137 | } |
2138 | ||
2139 | static void | |
2140 | insert_neon_reg_alias (char *str, int number, int type, | |
2141 | struct neon_typed_alias *atype) | |
2142 | { | |
2143 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2144 | |
dcbf9037 JB |
2145 | if (!reg) |
2146 | { | |
2147 | first_error (_("attempt to redefine typed alias")); | |
2148 | return; | |
2149 | } | |
5f4273c7 | 2150 | |
dcbf9037 JB |
2151 | if (atype) |
2152 | { | |
21d799b5 NC |
2153 | reg->neon = (struct neon_typed_alias *) |
2154 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2155 | *reg->neon = *atype; |
2156 | } | |
c19d1205 | 2157 | } |
b99bd4ef | 2158 | |
c19d1205 | 2159 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2160 | |
c19d1205 | 2161 | new_register_name .req existing_register_name |
b99bd4ef | 2162 | |
c19d1205 | 2163 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2164 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2165 | |
d929913e | 2166 | static bfd_boolean |
c19d1205 ZW |
2167 | create_register_alias (char * newname, char *p) |
2168 | { | |
2169 | struct reg_entry *old; | |
2170 | char *oldname, *nbuf; | |
2171 | size_t nlen; | |
b99bd4ef | 2172 | |
c19d1205 ZW |
2173 | /* The input scrubber ensures that whitespace after the mnemonic is |
2174 | collapsed to single spaces. */ | |
2175 | oldname = p; | |
2176 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2177 | return FALSE; |
b99bd4ef | 2178 | |
c19d1205 ZW |
2179 | oldname += 6; |
2180 | if (*oldname == '\0') | |
d929913e | 2181 | return FALSE; |
b99bd4ef | 2182 | |
21d799b5 | 2183 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2184 | if (!old) |
b99bd4ef | 2185 | { |
c19d1205 | 2186 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2187 | return TRUE; |
b99bd4ef NC |
2188 | } |
2189 | ||
c19d1205 ZW |
2190 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2191 | the desired alias name, and p points to its end. If not, then | |
2192 | the desired alias name is in the global original_case_string. */ | |
2193 | #ifdef TC_CASE_SENSITIVE | |
2194 | nlen = p - newname; | |
2195 | #else | |
2196 | newname = original_case_string; | |
2197 | nlen = strlen (newname); | |
2198 | #endif | |
b99bd4ef | 2199 | |
21d799b5 | 2200 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2201 | memcpy (nbuf, newname, nlen); |
2202 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2203 | |
c19d1205 ZW |
2204 | /* Create aliases under the new name as stated; an all-lowercase |
2205 | version of the new name; and an all-uppercase version of the new | |
2206 | name. */ | |
d929913e NC |
2207 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2208 | { | |
2209 | for (p = nbuf; *p; p++) | |
2210 | *p = TOUPPER (*p); | |
c19d1205 | 2211 | |
d929913e NC |
2212 | if (strncmp (nbuf, newname, nlen)) |
2213 | { | |
2214 | /* If this attempt to create an additional alias fails, do not bother | |
2215 | trying to create the all-lower case alias. We will fail and issue | |
2216 | a second, duplicate error message. This situation arises when the | |
2217 | programmer does something like: | |
2218 | foo .req r0 | |
2219 | Foo .req r1 | |
2220 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2221 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2222 | first .req. */ |
2223 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2224 | return TRUE; | |
2225 | } | |
c19d1205 | 2226 | |
d929913e NC |
2227 | for (p = nbuf; *p; p++) |
2228 | *p = TOLOWER (*p); | |
c19d1205 | 2229 | |
d929913e NC |
2230 | if (strncmp (nbuf, newname, nlen)) |
2231 | insert_reg_alias (nbuf, old->number, old->type); | |
2232 | } | |
c19d1205 | 2233 | |
d929913e | 2234 | return TRUE; |
b99bd4ef NC |
2235 | } |
2236 | ||
dcbf9037 JB |
2237 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2238 | X .dn d5.s32[1] | |
2239 | Y .qn 6.s16 | |
2240 | Z .dn d7 | |
2241 | T .dn Z[0] | |
2242 | These typed registers can be used instead of the types specified after the | |
2243 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2244 | specified directly, e.g.: | |
5f4273c7 | 2245 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2246 | |
c921be7d | 2247 | static bfd_boolean |
dcbf9037 JB |
2248 | create_neon_reg_alias (char *newname, char *p) |
2249 | { | |
2250 | enum arm_reg_type basetype; | |
2251 | struct reg_entry *basereg; | |
2252 | struct reg_entry mybasereg; | |
2253 | struct neon_type ntype; | |
2254 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2255 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2256 | int namelen; |
5f4273c7 | 2257 | |
dcbf9037 JB |
2258 | typeinfo.defined = 0; |
2259 | typeinfo.eltype.type = NT_invtype; | |
2260 | typeinfo.eltype.size = -1; | |
2261 | typeinfo.index = -1; | |
5f4273c7 | 2262 | |
dcbf9037 | 2263 | nameend = p; |
5f4273c7 | 2264 | |
dcbf9037 JB |
2265 | if (strncmp (p, " .dn ", 5) == 0) |
2266 | basetype = REG_TYPE_VFD; | |
2267 | else if (strncmp (p, " .qn ", 5) == 0) | |
2268 | basetype = REG_TYPE_NQ; | |
2269 | else | |
c921be7d | 2270 | return FALSE; |
5f4273c7 | 2271 | |
dcbf9037 | 2272 | p += 5; |
5f4273c7 | 2273 | |
dcbf9037 | 2274 | if (*p == '\0') |
c921be7d | 2275 | return FALSE; |
5f4273c7 | 2276 | |
dcbf9037 JB |
2277 | basereg = arm_reg_parse_multi (&p); |
2278 | ||
2279 | if (basereg && basereg->type != basetype) | |
2280 | { | |
2281 | as_bad (_("bad type for register")); | |
c921be7d | 2282 | return FALSE; |
dcbf9037 JB |
2283 | } |
2284 | ||
2285 | if (basereg == NULL) | |
2286 | { | |
2287 | expressionS exp; | |
2288 | /* Try parsing as an integer. */ | |
2289 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2290 | if (exp.X_op != O_constant) | |
2291 | { | |
2292 | as_bad (_("expression must be constant")); | |
c921be7d | 2293 | return FALSE; |
dcbf9037 JB |
2294 | } |
2295 | basereg = &mybasereg; | |
2296 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2297 | : exp.X_add_number; | |
2298 | basereg->neon = 0; | |
2299 | } | |
2300 | ||
2301 | if (basereg->neon) | |
2302 | typeinfo = *basereg->neon; | |
2303 | ||
2304 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2305 | { | |
2306 | /* We got a type. */ | |
2307 | if (typeinfo.defined & NTA_HASTYPE) | |
2308 | { | |
2309 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2310 | return FALSE; |
dcbf9037 | 2311 | } |
5f4273c7 | 2312 | |
dcbf9037 JB |
2313 | typeinfo.defined |= NTA_HASTYPE; |
2314 | if (ntype.elems != 1) | |
2315 | { | |
2316 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2317 | return FALSE; |
dcbf9037 JB |
2318 | } |
2319 | typeinfo.eltype = ntype.el[0]; | |
2320 | } | |
5f4273c7 | 2321 | |
dcbf9037 JB |
2322 | if (skip_past_char (&p, '[') == SUCCESS) |
2323 | { | |
2324 | expressionS exp; | |
2325 | /* We got a scalar index. */ | |
5f4273c7 | 2326 | |
dcbf9037 JB |
2327 | if (typeinfo.defined & NTA_HASINDEX) |
2328 | { | |
2329 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2330 | return FALSE; |
dcbf9037 | 2331 | } |
5f4273c7 | 2332 | |
dcbf9037 | 2333 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2334 | |
dcbf9037 JB |
2335 | if (exp.X_op != O_constant) |
2336 | { | |
2337 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2338 | return FALSE; |
dcbf9037 | 2339 | } |
5f4273c7 | 2340 | |
dcbf9037 JB |
2341 | typeinfo.defined |= NTA_HASINDEX; |
2342 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2343 | |
dcbf9037 JB |
2344 | if (skip_past_char (&p, ']') == FAIL) |
2345 | { | |
2346 | as_bad (_("expecting ]")); | |
c921be7d | 2347 | return FALSE; |
dcbf9037 JB |
2348 | } |
2349 | } | |
2350 | ||
15735687 NS |
2351 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2352 | the desired alias name, and p points to its end. If not, then | |
2353 | the desired alias name is in the global original_case_string. */ | |
2354 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2355 | namelen = nameend - newname; |
15735687 NS |
2356 | #else |
2357 | newname = original_case_string; | |
2358 | namelen = strlen (newname); | |
2359 | #endif | |
2360 | ||
21d799b5 | 2361 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2362 | strncpy (namebuf, newname, namelen); |
2363 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2364 | |
dcbf9037 JB |
2365 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2366 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2367 | |
dcbf9037 JB |
2368 | /* Insert name in all uppercase. */ |
2369 | for (p = namebuf; *p; p++) | |
2370 | *p = TOUPPER (*p); | |
5f4273c7 | 2371 | |
dcbf9037 JB |
2372 | if (strncmp (namebuf, newname, namelen)) |
2373 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2374 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2375 | |
dcbf9037 JB |
2376 | /* Insert name in all lowercase. */ |
2377 | for (p = namebuf; *p; p++) | |
2378 | *p = TOLOWER (*p); | |
5f4273c7 | 2379 | |
dcbf9037 JB |
2380 | if (strncmp (namebuf, newname, namelen)) |
2381 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2382 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2383 | |
c921be7d | 2384 | return TRUE; |
dcbf9037 JB |
2385 | } |
2386 | ||
c19d1205 ZW |
2387 | /* Should never be called, as .req goes between the alias and the |
2388 | register name, not at the beginning of the line. */ | |
c921be7d | 2389 | |
b99bd4ef | 2390 | static void |
c19d1205 | 2391 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2392 | { |
c19d1205 ZW |
2393 | as_bad (_("invalid syntax for .req directive")); |
2394 | } | |
b99bd4ef | 2395 | |
dcbf9037 JB |
2396 | static void |
2397 | s_dn (int a ATTRIBUTE_UNUSED) | |
2398 | { | |
2399 | as_bad (_("invalid syntax for .dn directive")); | |
2400 | } | |
2401 | ||
2402 | static void | |
2403 | s_qn (int a ATTRIBUTE_UNUSED) | |
2404 | { | |
2405 | as_bad (_("invalid syntax for .qn directive")); | |
2406 | } | |
2407 | ||
c19d1205 ZW |
2408 | /* The .unreq directive deletes an alias which was previously defined |
2409 | by .req. For example: | |
b99bd4ef | 2410 | |
c19d1205 ZW |
2411 | my_alias .req r11 |
2412 | .unreq my_alias */ | |
b99bd4ef NC |
2413 | |
2414 | static void | |
c19d1205 | 2415 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2416 | { |
c19d1205 ZW |
2417 | char * name; |
2418 | char saved_char; | |
b99bd4ef | 2419 | |
c19d1205 ZW |
2420 | name = input_line_pointer; |
2421 | ||
2422 | while (*input_line_pointer != 0 | |
2423 | && *input_line_pointer != ' ' | |
2424 | && *input_line_pointer != '\n') | |
2425 | ++input_line_pointer; | |
2426 | ||
2427 | saved_char = *input_line_pointer; | |
2428 | *input_line_pointer = 0; | |
2429 | ||
2430 | if (!*name) | |
2431 | as_bad (_("invalid syntax for .unreq directive")); | |
2432 | else | |
2433 | { | |
21d799b5 NC |
2434 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2435 | name); | |
c19d1205 ZW |
2436 | |
2437 | if (!reg) | |
2438 | as_bad (_("unknown register alias '%s'"), name); | |
2439 | else if (reg->builtin) | |
a1727c1a | 2440 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2441 | name); |
2442 | else | |
2443 | { | |
d929913e NC |
2444 | char * p; |
2445 | char * nbuf; | |
2446 | ||
db0bc284 | 2447 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2448 | free ((char *) reg->name); |
dcbf9037 JB |
2449 | if (reg->neon) |
2450 | free (reg->neon); | |
c19d1205 | 2451 | free (reg); |
d929913e NC |
2452 | |
2453 | /* Also locate the all upper case and all lower case versions. | |
2454 | Do not complain if we cannot find one or the other as it | |
2455 | was probably deleted above. */ | |
5f4273c7 | 2456 | |
d929913e NC |
2457 | nbuf = strdup (name); |
2458 | for (p = nbuf; *p; p++) | |
2459 | *p = TOUPPER (*p); | |
21d799b5 | 2460 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2461 | if (reg) |
2462 | { | |
db0bc284 | 2463 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2464 | free ((char *) reg->name); |
2465 | if (reg->neon) | |
2466 | free (reg->neon); | |
2467 | free (reg); | |
2468 | } | |
2469 | ||
2470 | for (p = nbuf; *p; p++) | |
2471 | *p = TOLOWER (*p); | |
21d799b5 | 2472 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2473 | if (reg) |
2474 | { | |
db0bc284 | 2475 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2476 | free ((char *) reg->name); |
2477 | if (reg->neon) | |
2478 | free (reg->neon); | |
2479 | free (reg); | |
2480 | } | |
2481 | ||
2482 | free (nbuf); | |
c19d1205 ZW |
2483 | } |
2484 | } | |
b99bd4ef | 2485 | |
c19d1205 | 2486 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2487 | demand_empty_rest_of_line (); |
2488 | } | |
2489 | ||
c19d1205 ZW |
2490 | /* Directives: Instruction set selection. */ |
2491 | ||
2492 | #ifdef OBJ_ELF | |
2493 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2494 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2495 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2496 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2497 | ||
cd000bff DJ |
2498 | /* Create a new mapping symbol for the transition to STATE. */ |
2499 | ||
2500 | static void | |
2501 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2502 | { |
a737bd4d | 2503 | symbolS * symbolP; |
c19d1205 ZW |
2504 | const char * symname; |
2505 | int type; | |
b99bd4ef | 2506 | |
c19d1205 | 2507 | switch (state) |
b99bd4ef | 2508 | { |
c19d1205 ZW |
2509 | case MAP_DATA: |
2510 | symname = "$d"; | |
2511 | type = BSF_NO_FLAGS; | |
2512 | break; | |
2513 | case MAP_ARM: | |
2514 | symname = "$a"; | |
2515 | type = BSF_NO_FLAGS; | |
2516 | break; | |
2517 | case MAP_THUMB: | |
2518 | symname = "$t"; | |
2519 | type = BSF_NO_FLAGS; | |
2520 | break; | |
c19d1205 ZW |
2521 | default: |
2522 | abort (); | |
2523 | } | |
2524 | ||
cd000bff | 2525 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2526 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2527 | ||
2528 | switch (state) | |
2529 | { | |
2530 | case MAP_ARM: | |
2531 | THUMB_SET_FUNC (symbolP, 0); | |
2532 | ARM_SET_THUMB (symbolP, 0); | |
2533 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2534 | break; | |
2535 | ||
2536 | case MAP_THUMB: | |
2537 | THUMB_SET_FUNC (symbolP, 1); | |
2538 | ARM_SET_THUMB (symbolP, 1); | |
2539 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2540 | break; | |
2541 | ||
2542 | case MAP_DATA: | |
2543 | default: | |
cd000bff DJ |
2544 | break; |
2545 | } | |
2546 | ||
2547 | /* Save the mapping symbols for future reference. Also check that | |
2548 | we do not place two mapping symbols at the same offset within a | |
2549 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2550 | check_mapping_symbols. |
2551 | ||
2552 | If .fill or other data filling directive generates zero sized data, | |
2553 | the mapping symbol for the following code will have the same value | |
2554 | as the one generated for the data filling directive. In this case, | |
2555 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2556 | if (value == 0) |
2557 | { | |
2de7820f JZ |
2558 | if (frag->tc_frag_data.first_map != NULL) |
2559 | { | |
2560 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2561 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2562 | } | |
cd000bff DJ |
2563 | frag->tc_frag_data.first_map = symbolP; |
2564 | } | |
2565 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2566 | { |
2567 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2568 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2569 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2570 | } | |
cd000bff DJ |
2571 | frag->tc_frag_data.last_map = symbolP; |
2572 | } | |
2573 | ||
2574 | /* We must sometimes convert a region marked as code to data during | |
2575 | code alignment, if an odd number of bytes have to be padded. The | |
2576 | code mapping symbol is pushed to an aligned address. */ | |
2577 | ||
2578 | static void | |
2579 | insert_data_mapping_symbol (enum mstate state, | |
2580 | valueT value, fragS *frag, offsetT bytes) | |
2581 | { | |
2582 | /* If there was already a mapping symbol, remove it. */ | |
2583 | if (frag->tc_frag_data.last_map != NULL | |
2584 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2585 | { | |
2586 | symbolS *symp = frag->tc_frag_data.last_map; | |
2587 | ||
2588 | if (value == 0) | |
2589 | { | |
2590 | know (frag->tc_frag_data.first_map == symp); | |
2591 | frag->tc_frag_data.first_map = NULL; | |
2592 | } | |
2593 | frag->tc_frag_data.last_map = NULL; | |
2594 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2595 | } |
cd000bff DJ |
2596 | |
2597 | make_mapping_symbol (MAP_DATA, value, frag); | |
2598 | make_mapping_symbol (state, value + bytes, frag); | |
2599 | } | |
2600 | ||
2601 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2602 | ||
2603 | /* Set the mapping state to STATE. Only call this when about to | |
2604 | emit some STATE bytes to the file. */ | |
2605 | ||
2606 | void | |
2607 | mapping_state (enum mstate state) | |
2608 | { | |
940b5ce0 DJ |
2609 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2610 | ||
cd000bff DJ |
2611 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2612 | ||
2613 | if (mapstate == state) | |
2614 | /* The mapping symbol has already been emitted. | |
2615 | There is nothing else to do. */ | |
2616 | return; | |
49c62a33 NC |
2617 | |
2618 | if (state == MAP_ARM || state == MAP_THUMB) | |
2619 | /* PR gas/12931 | |
2620 | All ARM instructions require 4-byte alignment. | |
2621 | (Almost) all Thumb instructions require 2-byte alignment. | |
2622 | ||
2623 | When emitting instructions into any section, mark the section | |
2624 | appropriately. | |
2625 | ||
2626 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2627 | but themselves require 2-byte alignment; this applies to some | |
2628 | PC- relative forms. However, these cases will invovle implicit | |
2629 | literal pool generation or an explicit .align >=2, both of | |
2630 | which will cause the section to me marked with sufficient | |
2631 | alignment. Thus, we don't handle those cases here. */ | |
2632 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2633 | ||
2634 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
cd000bff DJ |
2635 | /* This case will be evaluated later in the next else. */ |
2636 | return; | |
2637 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2638 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2639 | { | |
2640 | /* Only add the symbol if the offset is > 0: | |
2641 | if we're at the first frag, check it's size > 0; | |
2642 | if we're not at the first frag, then for sure | |
2643 | the offset is > 0. */ | |
2644 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2645 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2646 | ||
2647 | if (add_symbol) | |
2648 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2649 | } | |
2650 | ||
2651 | mapping_state_2 (state, 0); | |
2652 | #undef TRANSITION | |
2653 | } | |
2654 | ||
2655 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2656 | allocated. Put the mapping symbol that far back. */ | |
2657 | ||
2658 | static void | |
2659 | mapping_state_2 (enum mstate state, int max_chars) | |
2660 | { | |
940b5ce0 DJ |
2661 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2662 | ||
2663 | if (!SEG_NORMAL (now_seg)) | |
2664 | return; | |
2665 | ||
cd000bff DJ |
2666 | if (mapstate == state) |
2667 | /* The mapping symbol has already been emitted. | |
2668 | There is nothing else to do. */ | |
2669 | return; | |
2670 | ||
cd000bff DJ |
2671 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2672 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2673 | } |
2674 | #else | |
d3106081 NS |
2675 | #define mapping_state(x) ((void)0) |
2676 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2677 | #endif |
2678 | ||
2679 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2680 | ||
4343666d | 2681 | #ifdef OBJ_COFF |
c19d1205 ZW |
2682 | static symbolS * |
2683 | find_real_start (symbolS * symbolP) | |
2684 | { | |
2685 | char * real_start; | |
2686 | const char * name = S_GET_NAME (symbolP); | |
2687 | symbolS * new_target; | |
2688 | ||
2689 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2690 | #define STUB_NAME ".real_start_of" | |
2691 | ||
2692 | if (name == NULL) | |
2693 | abort (); | |
2694 | ||
37f6032b ZW |
2695 | /* The compiler may generate BL instructions to local labels because |
2696 | it needs to perform a branch to a far away location. These labels | |
2697 | do not have a corresponding ".real_start_of" label. We check | |
2698 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2699 | the ".real_start_of" convention for nonlocal branches. */ | |
2700 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2701 | return symbolP; |
2702 | ||
37f6032b | 2703 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2704 | new_target = symbol_find (real_start); |
2705 | ||
2706 | if (new_target == NULL) | |
2707 | { | |
bd3ba5d1 | 2708 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2709 | new_target = symbolP; |
2710 | } | |
2711 | ||
c19d1205 ZW |
2712 | return new_target; |
2713 | } | |
4343666d | 2714 | #endif |
c19d1205 ZW |
2715 | |
2716 | static void | |
2717 | opcode_select (int width) | |
2718 | { | |
2719 | switch (width) | |
2720 | { | |
2721 | case 16: | |
2722 | if (! thumb_mode) | |
2723 | { | |
e74cfd16 | 2724 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2725 | as_bad (_("selected processor does not support THUMB opcodes")); |
2726 | ||
2727 | thumb_mode = 1; | |
2728 | /* No need to force the alignment, since we will have been | |
2729 | coming from ARM mode, which is word-aligned. */ | |
2730 | record_alignment (now_seg, 1); | |
2731 | } | |
c19d1205 ZW |
2732 | break; |
2733 | ||
2734 | case 32: | |
2735 | if (thumb_mode) | |
2736 | { | |
e74cfd16 | 2737 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2738 | as_bad (_("selected processor does not support ARM opcodes")); |
2739 | ||
2740 | thumb_mode = 0; | |
2741 | ||
2742 | if (!need_pass_2) | |
2743 | frag_align (2, 0, 0); | |
2744 | ||
2745 | record_alignment (now_seg, 1); | |
2746 | } | |
c19d1205 ZW |
2747 | break; |
2748 | ||
2749 | default: | |
2750 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2751 | } | |
2752 | } | |
2753 | ||
2754 | static void | |
2755 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2756 | { | |
2757 | opcode_select (32); | |
2758 | demand_empty_rest_of_line (); | |
2759 | } | |
2760 | ||
2761 | static void | |
2762 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2763 | { | |
2764 | opcode_select (16); | |
2765 | demand_empty_rest_of_line (); | |
2766 | } | |
2767 | ||
2768 | static void | |
2769 | s_code (int unused ATTRIBUTE_UNUSED) | |
2770 | { | |
2771 | int temp; | |
2772 | ||
2773 | temp = get_absolute_expression (); | |
2774 | switch (temp) | |
2775 | { | |
2776 | case 16: | |
2777 | case 32: | |
2778 | opcode_select (temp); | |
2779 | break; | |
2780 | ||
2781 | default: | |
2782 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2783 | } | |
2784 | } | |
2785 | ||
2786 | static void | |
2787 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2788 | { | |
2789 | /* If we are not already in thumb mode go into it, EVEN if | |
2790 | the target processor does not support thumb instructions. | |
2791 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2792 | to compile interworking support functions even if the | |
2793 | target processor should not support interworking. */ | |
2794 | if (! thumb_mode) | |
2795 | { | |
2796 | thumb_mode = 2; | |
2797 | record_alignment (now_seg, 1); | |
2798 | } | |
2799 | ||
2800 | demand_empty_rest_of_line (); | |
2801 | } | |
2802 | ||
2803 | static void | |
2804 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2805 | { | |
2806 | s_thumb (0); | |
2807 | ||
2808 | /* The following label is the name/address of the start of a Thumb function. | |
2809 | We need to know this for the interworking support. */ | |
2810 | label_is_thumb_function_name = TRUE; | |
2811 | } | |
2812 | ||
2813 | /* Perform a .set directive, but also mark the alias as | |
2814 | being a thumb function. */ | |
2815 | ||
2816 | static void | |
2817 | s_thumb_set (int equiv) | |
2818 | { | |
2819 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2820 | We cannot just call that code as we need to get at the symbol that | |
2821 | is created. */ | |
2822 | char * name; | |
2823 | char delim; | |
2824 | char * end_name; | |
2825 | symbolS * symbolP; | |
2826 | ||
2827 | /* Especial apologies for the random logic: | |
2828 | This just grew, and could be parsed much more simply! | |
2829 | Dean - in haste. */ | |
2830 | name = input_line_pointer; | |
2831 | delim = get_symbol_end (); | |
2832 | end_name = input_line_pointer; | |
2833 | *end_name = delim; | |
2834 | ||
2835 | if (*input_line_pointer != ',') | |
2836 | { | |
2837 | *end_name = 0; | |
2838 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2839 | *end_name = delim; |
2840 | ignore_rest_of_line (); | |
2841 | return; | |
2842 | } | |
2843 | ||
2844 | input_line_pointer++; | |
2845 | *end_name = 0; | |
2846 | ||
2847 | if (name[0] == '.' && name[1] == '\0') | |
2848 | { | |
2849 | /* XXX - this should not happen to .thumb_set. */ | |
2850 | abort (); | |
2851 | } | |
2852 | ||
2853 | if ((symbolP = symbol_find (name)) == NULL | |
2854 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2855 | { | |
2856 | #ifndef NO_LISTING | |
2857 | /* When doing symbol listings, play games with dummy fragments living | |
2858 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2859 | for this symbol. */ |
b99bd4ef NC |
2860 | if (listing & LISTING_SYMBOLS) |
2861 | { | |
2862 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2863 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2864 | |
2865 | memset (dummy_frag, 0, sizeof (fragS)); | |
2866 | dummy_frag->fr_type = rs_fill; | |
2867 | dummy_frag->line = listing_tail; | |
2868 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2869 | dummy_frag->fr_symbol = symbolP; | |
2870 | } | |
2871 | else | |
2872 | #endif | |
2873 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2874 | ||
2875 | #ifdef OBJ_COFF | |
2876 | /* "set" symbols are local unless otherwise specified. */ | |
2877 | SF_SET_LOCAL (symbolP); | |
2878 | #endif /* OBJ_COFF */ | |
2879 | } /* Make a new symbol. */ | |
2880 | ||
2881 | symbol_table_insert (symbolP); | |
2882 | ||
2883 | * end_name = delim; | |
2884 | ||
2885 | if (equiv | |
2886 | && S_IS_DEFINED (symbolP) | |
2887 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2888 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2889 | ||
2890 | pseudo_set (symbolP); | |
2891 | ||
2892 | demand_empty_rest_of_line (); | |
2893 | ||
c19d1205 | 2894 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2895 | |
2896 | THUMB_SET_FUNC (symbolP, 1); | |
2897 | ARM_SET_THUMB (symbolP, 1); | |
2898 | #if defined OBJ_ELF || defined OBJ_COFF | |
2899 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2900 | #endif | |
2901 | } | |
2902 | ||
c19d1205 | 2903 | /* Directives: Mode selection. */ |
b99bd4ef | 2904 | |
c19d1205 ZW |
2905 | /* .syntax [unified|divided] - choose the new unified syntax |
2906 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2907 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2908 | static void |
c19d1205 | 2909 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2910 | { |
c19d1205 ZW |
2911 | char *name, delim; |
2912 | ||
2913 | name = input_line_pointer; | |
2914 | delim = get_symbol_end (); | |
2915 | ||
2916 | if (!strcasecmp (name, "unified")) | |
2917 | unified_syntax = TRUE; | |
2918 | else if (!strcasecmp (name, "divided")) | |
2919 | unified_syntax = FALSE; | |
2920 | else | |
2921 | { | |
2922 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2923 | return; | |
2924 | } | |
2925 | *input_line_pointer = delim; | |
b99bd4ef NC |
2926 | demand_empty_rest_of_line (); |
2927 | } | |
2928 | ||
c19d1205 ZW |
2929 | /* Directives: sectioning and alignment. */ |
2930 | ||
2931 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2932 | ||
b99bd4ef | 2933 | static void |
c19d1205 | 2934 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2935 | { |
a737bd4d | 2936 | int temp; |
dce323d1 | 2937 | bfd_boolean fill_p; |
c19d1205 ZW |
2938 | long temp_fill; |
2939 | long max_alignment = 15; | |
b99bd4ef NC |
2940 | |
2941 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2942 | if (temp > max_alignment) |
2943 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2944 | else if (temp < 0) | |
b99bd4ef | 2945 | { |
c19d1205 ZW |
2946 | as_bad (_("alignment negative. 0 assumed.")); |
2947 | temp = 0; | |
2948 | } | |
b99bd4ef | 2949 | |
c19d1205 ZW |
2950 | if (*input_line_pointer == ',') |
2951 | { | |
2952 | input_line_pointer++; | |
2953 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2954 | fill_p = TRUE; |
b99bd4ef | 2955 | } |
c19d1205 | 2956 | else |
dce323d1 PB |
2957 | { |
2958 | fill_p = FALSE; | |
2959 | temp_fill = 0; | |
2960 | } | |
b99bd4ef | 2961 | |
c19d1205 ZW |
2962 | if (!temp) |
2963 | temp = 2; | |
b99bd4ef | 2964 | |
c19d1205 ZW |
2965 | /* Only make a frag if we HAVE to. */ |
2966 | if (temp && !need_pass_2) | |
dce323d1 PB |
2967 | { |
2968 | if (!fill_p && subseg_text_p (now_seg)) | |
2969 | frag_align_code (temp, 0); | |
2970 | else | |
2971 | frag_align (temp, (int) temp_fill, 0); | |
2972 | } | |
c19d1205 ZW |
2973 | demand_empty_rest_of_line (); |
2974 | ||
2975 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2976 | } |
2977 | ||
c19d1205 ZW |
2978 | static void |
2979 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2980 | { |
c19d1205 ZW |
2981 | /* We don't support putting frags in the BSS segment, we fake it by |
2982 | marking in_bss, then looking at s_skip for clues. */ | |
2983 | subseg_set (bss_section, 0); | |
2984 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2985 | |
2986 | #ifdef md_elf_section_change_hook | |
2987 | md_elf_section_change_hook (); | |
2988 | #endif | |
c19d1205 | 2989 | } |
b99bd4ef | 2990 | |
c19d1205 ZW |
2991 | static void |
2992 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2993 | { | |
2994 | /* Never make frag if expect extra pass. */ | |
2995 | if (!need_pass_2) | |
2996 | frag_align (1, 0, 0); | |
b99bd4ef | 2997 | |
c19d1205 | 2998 | record_alignment (now_seg, 1); |
b99bd4ef | 2999 | |
c19d1205 | 3000 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3001 | } |
3002 | ||
c19d1205 | 3003 | /* Directives: Literal pools. */ |
a737bd4d | 3004 | |
c19d1205 ZW |
3005 | static literal_pool * |
3006 | find_literal_pool (void) | |
a737bd4d | 3007 | { |
c19d1205 | 3008 | literal_pool * pool; |
a737bd4d | 3009 | |
c19d1205 | 3010 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3011 | { |
c19d1205 ZW |
3012 | if (pool->section == now_seg |
3013 | && pool->sub_section == now_subseg) | |
3014 | break; | |
a737bd4d NC |
3015 | } |
3016 | ||
c19d1205 | 3017 | return pool; |
a737bd4d NC |
3018 | } |
3019 | ||
c19d1205 ZW |
3020 | static literal_pool * |
3021 | find_or_make_literal_pool (void) | |
a737bd4d | 3022 | { |
c19d1205 ZW |
3023 | /* Next literal pool ID number. */ |
3024 | static unsigned int latest_pool_num = 1; | |
3025 | literal_pool * pool; | |
a737bd4d | 3026 | |
c19d1205 | 3027 | pool = find_literal_pool (); |
a737bd4d | 3028 | |
c19d1205 | 3029 | if (pool == NULL) |
a737bd4d | 3030 | { |
c19d1205 | 3031 | /* Create a new pool. */ |
21d799b5 | 3032 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3033 | if (! pool) |
3034 | return NULL; | |
a737bd4d | 3035 | |
c19d1205 ZW |
3036 | pool->next_free_entry = 0; |
3037 | pool->section = now_seg; | |
3038 | pool->sub_section = now_subseg; | |
3039 | pool->next = list_of_pools; | |
3040 | pool->symbol = NULL; | |
3041 | ||
3042 | /* Add it to the list. */ | |
3043 | list_of_pools = pool; | |
a737bd4d | 3044 | } |
a737bd4d | 3045 | |
c19d1205 ZW |
3046 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3047 | if (pool->symbol == NULL) | |
a737bd4d | 3048 | { |
c19d1205 ZW |
3049 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3050 | (valueT) 0, &zero_address_frag); | |
3051 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3052 | } |
3053 | ||
c19d1205 ZW |
3054 | /* Done. */ |
3055 | return pool; | |
a737bd4d NC |
3056 | } |
3057 | ||
c19d1205 | 3058 | /* Add the literal in the global 'inst' |
5f4273c7 | 3059 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3060 | |
3061 | static int | |
c19d1205 | 3062 | add_to_lit_pool (void) |
b99bd4ef | 3063 | { |
c19d1205 ZW |
3064 | literal_pool * pool; |
3065 | unsigned int entry; | |
b99bd4ef | 3066 | |
c19d1205 ZW |
3067 | pool = find_or_make_literal_pool (); |
3068 | ||
3069 | /* Check if this literal value is already in the pool. */ | |
3070 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3071 | { |
c19d1205 ZW |
3072 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3073 | && (inst.reloc.exp.X_op == O_constant) | |
3074 | && (pool->literals[entry].X_add_number | |
3075 | == inst.reloc.exp.X_add_number) | |
3076 | && (pool->literals[entry].X_unsigned | |
3077 | == inst.reloc.exp.X_unsigned)) | |
3078 | break; | |
3079 | ||
3080 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3081 | && (inst.reloc.exp.X_op == O_symbol) | |
3082 | && (pool->literals[entry].X_add_number | |
3083 | == inst.reloc.exp.X_add_number) | |
3084 | && (pool->literals[entry].X_add_symbol | |
3085 | == inst.reloc.exp.X_add_symbol) | |
3086 | && (pool->literals[entry].X_op_symbol | |
3087 | == inst.reloc.exp.X_op_symbol)) | |
3088 | break; | |
b99bd4ef NC |
3089 | } |
3090 | ||
c19d1205 ZW |
3091 | /* Do we need to create a new entry? */ |
3092 | if (entry == pool->next_free_entry) | |
3093 | { | |
3094 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3095 | { | |
3096 | inst.error = _("literal pool overflow"); | |
3097 | return FAIL; | |
3098 | } | |
3099 | ||
3100 | pool->literals[entry] = inst.reloc.exp; | |
a8040cf2 NC |
3101 | #ifdef OBJ_ELF |
3102 | /* PR ld/12974: Record the location of the first source line to reference | |
3103 | this entry in the literal pool. If it turns out during linking that the | |
3104 | symbol does not exist we will be able to give an accurate line number for | |
3105 | the (first use of the) missing reference. */ | |
3106 | if (debug_type == DEBUG_DWARF2) | |
3107 | dwarf2_where (pool->locs + entry); | |
3108 | #endif | |
c19d1205 ZW |
3109 | pool->next_free_entry += 1; |
3110 | } | |
b99bd4ef | 3111 | |
c19d1205 ZW |
3112 | inst.reloc.exp.X_op = O_symbol; |
3113 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3114 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3115 | |
c19d1205 | 3116 | return SUCCESS; |
b99bd4ef NC |
3117 | } |
3118 | ||
c19d1205 ZW |
3119 | /* Can't use symbol_new here, so have to create a symbol and then at |
3120 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3121 | |
c19d1205 ZW |
3122 | static void |
3123 | symbol_locate (symbolS * symbolP, | |
3124 | const char * name, /* It is copied, the caller can modify. */ | |
3125 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3126 | valueT valu, /* Symbol value. */ | |
3127 | fragS * frag) /* Associated fragment. */ | |
3128 | { | |
3129 | unsigned int name_length; | |
3130 | char * preserved_copy_of_name; | |
e16bb312 | 3131 | |
c19d1205 ZW |
3132 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3133 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3134 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3135 | |
c19d1205 ZW |
3136 | #ifdef tc_canonicalize_symbol_name |
3137 | preserved_copy_of_name = | |
3138 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3139 | #endif | |
b99bd4ef | 3140 | |
c19d1205 | 3141 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3142 | |
c19d1205 ZW |
3143 | S_SET_SEGMENT (symbolP, segment); |
3144 | S_SET_VALUE (symbolP, valu); | |
3145 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3146 | |
c19d1205 | 3147 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3148 | |
c19d1205 ZW |
3149 | /* Link to end of symbol chain. */ |
3150 | { | |
3151 | extern int symbol_table_frozen; | |
b99bd4ef | 3152 | |
c19d1205 ZW |
3153 | if (symbol_table_frozen) |
3154 | abort (); | |
3155 | } | |
b99bd4ef | 3156 | |
c19d1205 | 3157 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3158 | |
c19d1205 | 3159 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3160 | |
c19d1205 ZW |
3161 | #ifdef tc_symbol_new_hook |
3162 | tc_symbol_new_hook (symbolP); | |
3163 | #endif | |
3164 | ||
3165 | #ifdef DEBUG_SYMS | |
3166 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3167 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3168 | } |
3169 | ||
b99bd4ef | 3170 | |
c19d1205 ZW |
3171 | static void |
3172 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3173 | { |
c19d1205 ZW |
3174 | unsigned int entry; |
3175 | literal_pool * pool; | |
3176 | char sym_name[20]; | |
b99bd4ef | 3177 | |
c19d1205 ZW |
3178 | pool = find_literal_pool (); |
3179 | if (pool == NULL | |
3180 | || pool->symbol == NULL | |
3181 | || pool->next_free_entry == 0) | |
3182 | return; | |
b99bd4ef | 3183 | |
c19d1205 | 3184 | mapping_state (MAP_DATA); |
b99bd4ef | 3185 | |
c19d1205 ZW |
3186 | /* Align pool as you have word accesses. |
3187 | Only make a frag if we have to. */ | |
3188 | if (!need_pass_2) | |
3189 | frag_align (2, 0, 0); | |
b99bd4ef | 3190 | |
c19d1205 | 3191 | record_alignment (now_seg, 2); |
b99bd4ef | 3192 | |
c19d1205 | 3193 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3194 | |
c19d1205 ZW |
3195 | symbol_locate (pool->symbol, sym_name, now_seg, |
3196 | (valueT) frag_now_fix (), frag_now); | |
3197 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3198 | |
c19d1205 | 3199 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3200 | |
c19d1205 ZW |
3201 | #if defined OBJ_COFF || defined OBJ_ELF |
3202 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3203 | #endif | |
6c43fab6 | 3204 | |
c19d1205 | 3205 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3206 | { |
3207 | #ifdef OBJ_ELF | |
3208 | if (debug_type == DEBUG_DWARF2) | |
3209 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3210 | #endif | |
3211 | /* First output the expression in the instruction to the pool. */ | |
3212 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
3213 | } | |
b99bd4ef | 3214 | |
c19d1205 ZW |
3215 | /* Mark the pool as empty. */ |
3216 | pool->next_free_entry = 0; | |
3217 | pool->symbol = NULL; | |
b99bd4ef NC |
3218 | } |
3219 | ||
c19d1205 ZW |
3220 | #ifdef OBJ_ELF |
3221 | /* Forward declarations for functions below, in the MD interface | |
3222 | section. */ | |
3223 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3224 | static valueT create_unwind_entry (int); | |
3225 | static void start_unwind_section (const segT, int); | |
3226 | static void add_unwind_opcode (valueT, int); | |
3227 | static void flush_pending_unwind (void); | |
b99bd4ef | 3228 | |
c19d1205 | 3229 | /* Directives: Data. */ |
b99bd4ef | 3230 | |
c19d1205 ZW |
3231 | static void |
3232 | s_arm_elf_cons (int nbytes) | |
3233 | { | |
3234 | expressionS exp; | |
b99bd4ef | 3235 | |
c19d1205 ZW |
3236 | #ifdef md_flush_pending_output |
3237 | md_flush_pending_output (); | |
3238 | #endif | |
b99bd4ef | 3239 | |
c19d1205 | 3240 | if (is_it_end_of_statement ()) |
b99bd4ef | 3241 | { |
c19d1205 ZW |
3242 | demand_empty_rest_of_line (); |
3243 | return; | |
b99bd4ef NC |
3244 | } |
3245 | ||
c19d1205 ZW |
3246 | #ifdef md_cons_align |
3247 | md_cons_align (nbytes); | |
3248 | #endif | |
b99bd4ef | 3249 | |
c19d1205 ZW |
3250 | mapping_state (MAP_DATA); |
3251 | do | |
b99bd4ef | 3252 | { |
c19d1205 ZW |
3253 | int reloc; |
3254 | char *base = input_line_pointer; | |
b99bd4ef | 3255 | |
c19d1205 | 3256 | expression (& exp); |
b99bd4ef | 3257 | |
c19d1205 ZW |
3258 | if (exp.X_op != O_symbol) |
3259 | emit_expr (&exp, (unsigned int) nbytes); | |
3260 | else | |
3261 | { | |
3262 | char *before_reloc = input_line_pointer; | |
3263 | reloc = parse_reloc (&input_line_pointer); | |
3264 | if (reloc == -1) | |
3265 | { | |
3266 | as_bad (_("unrecognized relocation suffix")); | |
3267 | ignore_rest_of_line (); | |
3268 | return; | |
3269 | } | |
3270 | else if (reloc == BFD_RELOC_UNUSED) | |
3271 | emit_expr (&exp, (unsigned int) nbytes); | |
3272 | else | |
3273 | { | |
21d799b5 NC |
3274 | reloc_howto_type *howto = (reloc_howto_type *) |
3275 | bfd_reloc_type_lookup (stdoutput, | |
3276 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3277 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3278 | |
2fc8bdac ZW |
3279 | if (reloc == BFD_RELOC_ARM_PLT32) |
3280 | { | |
3281 | as_bad (_("(plt) is only valid on branch targets")); | |
3282 | reloc = BFD_RELOC_UNUSED; | |
3283 | size = 0; | |
3284 | } | |
3285 | ||
c19d1205 | 3286 | if (size > nbytes) |
2fc8bdac | 3287 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3288 | howto->name, nbytes); |
3289 | else | |
3290 | { | |
3291 | /* We've parsed an expression stopping at O_symbol. | |
3292 | But there may be more expression left now that we | |
3293 | have parsed the relocation marker. Parse it again. | |
3294 | XXX Surely there is a cleaner way to do this. */ | |
3295 | char *p = input_line_pointer; | |
3296 | int offset; | |
21d799b5 | 3297 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3298 | memcpy (save_buf, base, input_line_pointer - base); |
3299 | memmove (base + (input_line_pointer - before_reloc), | |
3300 | base, before_reloc - base); | |
3301 | ||
3302 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3303 | expression (&exp); | |
3304 | memcpy (base, save_buf, p - base); | |
3305 | ||
3306 | offset = nbytes - size; | |
3307 | p = frag_more ((int) nbytes); | |
3308 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3309 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3310 | } |
3311 | } | |
3312 | } | |
b99bd4ef | 3313 | } |
c19d1205 | 3314 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3315 | |
c19d1205 ZW |
3316 | /* Put terminator back into stream. */ |
3317 | input_line_pointer --; | |
3318 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3319 | } |
3320 | ||
c921be7d NC |
3321 | /* Emit an expression containing a 32-bit thumb instruction. |
3322 | Implementation based on put_thumb32_insn. */ | |
3323 | ||
3324 | static void | |
3325 | emit_thumb32_expr (expressionS * exp) | |
3326 | { | |
3327 | expressionS exp_high = *exp; | |
3328 | ||
3329 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3330 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3331 | exp->X_add_number &= 0xffff; | |
3332 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3333 | } | |
3334 | ||
3335 | /* Guess the instruction size based on the opcode. */ | |
3336 | ||
3337 | static int | |
3338 | thumb_insn_size (int opcode) | |
3339 | { | |
3340 | if ((unsigned int) opcode < 0xe800u) | |
3341 | return 2; | |
3342 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3343 | return 4; | |
3344 | else | |
3345 | return 0; | |
3346 | } | |
3347 | ||
3348 | static bfd_boolean | |
3349 | emit_insn (expressionS *exp, int nbytes) | |
3350 | { | |
3351 | int size = 0; | |
3352 | ||
3353 | if (exp->X_op == O_constant) | |
3354 | { | |
3355 | size = nbytes; | |
3356 | ||
3357 | if (size == 0) | |
3358 | size = thumb_insn_size (exp->X_add_number); | |
3359 | ||
3360 | if (size != 0) | |
3361 | { | |
3362 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3363 | { | |
3364 | as_bad (_(".inst.n operand too big. "\ | |
3365 | "Use .inst.w instead")); | |
3366 | size = 0; | |
3367 | } | |
3368 | else | |
3369 | { | |
3370 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3371 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3372 | else | |
3373 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3374 | ||
3375 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3376 | emit_thumb32_expr (exp); | |
3377 | else | |
3378 | emit_expr (exp, (unsigned int) size); | |
3379 | ||
3380 | it_fsm_post_encode (); | |
3381 | } | |
3382 | } | |
3383 | else | |
3384 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3385 | "Use .inst.n/.inst.w instead")); | |
3386 | } | |
3387 | else | |
3388 | as_bad (_("constant expression required")); | |
3389 | ||
3390 | return (size != 0); | |
3391 | } | |
3392 | ||
3393 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3394 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3395 | ||
3396 | static void | |
3397 | s_arm_elf_inst (int nbytes) | |
3398 | { | |
3399 | if (is_it_end_of_statement ()) | |
3400 | { | |
3401 | demand_empty_rest_of_line (); | |
3402 | return; | |
3403 | } | |
3404 | ||
3405 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3406 | but will ensure not to be in DATA state. */ | |
3407 | ||
3408 | if (thumb_mode) | |
3409 | mapping_state (MAP_THUMB); | |
3410 | else | |
3411 | { | |
3412 | if (nbytes != 0) | |
3413 | { | |
3414 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3415 | ignore_rest_of_line (); | |
3416 | return; | |
3417 | } | |
3418 | ||
3419 | nbytes = 4; | |
3420 | ||
3421 | mapping_state (MAP_ARM); | |
3422 | } | |
3423 | ||
3424 | do | |
3425 | { | |
3426 | expressionS exp; | |
3427 | ||
3428 | expression (& exp); | |
3429 | ||
3430 | if (! emit_insn (& exp, nbytes)) | |
3431 | { | |
3432 | ignore_rest_of_line (); | |
3433 | return; | |
3434 | } | |
3435 | } | |
3436 | while (*input_line_pointer++ == ','); | |
3437 | ||
3438 | /* Put terminator back into stream. */ | |
3439 | input_line_pointer --; | |
3440 | demand_empty_rest_of_line (); | |
3441 | } | |
b99bd4ef | 3442 | |
c19d1205 | 3443 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3444 | |
c19d1205 ZW |
3445 | static void |
3446 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3447 | { | |
3448 | expressionS exp; | |
3449 | char *p; | |
3450 | valueT highbit; | |
b99bd4ef | 3451 | |
c19d1205 ZW |
3452 | highbit = 0; |
3453 | if (*input_line_pointer == '1') | |
3454 | highbit = 0x80000000; | |
3455 | else if (*input_line_pointer != '0') | |
3456 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3457 | |
c19d1205 ZW |
3458 | input_line_pointer++; |
3459 | if (*input_line_pointer != ',') | |
3460 | as_bad (_("missing comma")); | |
3461 | input_line_pointer++; | |
b99bd4ef | 3462 | |
c19d1205 ZW |
3463 | #ifdef md_flush_pending_output |
3464 | md_flush_pending_output (); | |
3465 | #endif | |
b99bd4ef | 3466 | |
c19d1205 ZW |
3467 | #ifdef md_cons_align |
3468 | md_cons_align (4); | |
3469 | #endif | |
b99bd4ef | 3470 | |
c19d1205 | 3471 | mapping_state (MAP_DATA); |
b99bd4ef | 3472 | |
c19d1205 | 3473 | expression (&exp); |
b99bd4ef | 3474 | |
c19d1205 ZW |
3475 | p = frag_more (4); |
3476 | md_number_to_chars (p, highbit, 4); | |
3477 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3478 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3479 | |
c19d1205 | 3480 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3481 | } |
3482 | ||
c19d1205 | 3483 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3484 | |
c19d1205 | 3485 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3486 | |
c19d1205 ZW |
3487 | static void |
3488 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3489 | { | |
3490 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3491 | if (unwind.proc_start) |
3492 | { | |
c921be7d | 3493 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3494 | return; |
3495 | } | |
3496 | ||
c19d1205 ZW |
3497 | /* Mark the start of the function. */ |
3498 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3499 | |
c19d1205 ZW |
3500 | /* Reset the rest of the unwind info. */ |
3501 | unwind.opcode_count = 0; | |
3502 | unwind.table_entry = NULL; | |
3503 | unwind.personality_routine = NULL; | |
3504 | unwind.personality_index = -1; | |
3505 | unwind.frame_size = 0; | |
3506 | unwind.fp_offset = 0; | |
fdfde340 | 3507 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3508 | unwind.fp_used = 0; |
3509 | unwind.sp_restored = 0; | |
3510 | } | |
b99bd4ef | 3511 | |
b99bd4ef | 3512 | |
c19d1205 ZW |
3513 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3514 | for the function. */ | |
b99bd4ef | 3515 | |
c19d1205 ZW |
3516 | static void |
3517 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3518 | { | |
3519 | demand_empty_rest_of_line (); | |
921e5f0a | 3520 | if (!unwind.proc_start) |
c921be7d | 3521 | as_bad (MISSING_FNSTART); |
921e5f0a | 3522 | |
c19d1205 | 3523 | if (unwind.table_entry) |
6decc662 | 3524 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3525 | |
c19d1205 ZW |
3526 | create_unwind_entry (1); |
3527 | } | |
a737bd4d | 3528 | |
c19d1205 | 3529 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3530 | |
c19d1205 ZW |
3531 | static void |
3532 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3533 | { | |
3534 | long where; | |
3535 | char *ptr; | |
3536 | valueT val; | |
940b5ce0 | 3537 | unsigned int marked_pr_dependency; |
f02232aa | 3538 | |
c19d1205 | 3539 | demand_empty_rest_of_line (); |
f02232aa | 3540 | |
921e5f0a PB |
3541 | if (!unwind.proc_start) |
3542 | { | |
c921be7d | 3543 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3544 | return; |
3545 | } | |
3546 | ||
c19d1205 ZW |
3547 | /* Add eh table entry. */ |
3548 | if (unwind.table_entry == NULL) | |
3549 | val = create_unwind_entry (0); | |
3550 | else | |
3551 | val = 0; | |
f02232aa | 3552 | |
c19d1205 ZW |
3553 | /* Add index table entry. This is two words. */ |
3554 | start_unwind_section (unwind.saved_seg, 1); | |
3555 | frag_align (2, 0, 0); | |
3556 | record_alignment (now_seg, 2); | |
b99bd4ef | 3557 | |
c19d1205 | 3558 | ptr = frag_more (8); |
5011093d | 3559 | memset (ptr, 0, 8); |
c19d1205 | 3560 | where = frag_now_fix () - 8; |
f02232aa | 3561 | |
c19d1205 ZW |
3562 | /* Self relative offset of the function start. */ |
3563 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3564 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3565 | |
c19d1205 ZW |
3566 | /* Indicate dependency on EHABI-defined personality routines to the |
3567 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3568 | marked_pr_dependency |
3569 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3570 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3571 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3572 | { | |
5f4273c7 NC |
3573 | static const char *const name[] = |
3574 | { | |
3575 | "__aeabi_unwind_cpp_pr0", | |
3576 | "__aeabi_unwind_cpp_pr1", | |
3577 | "__aeabi_unwind_cpp_pr2" | |
3578 | }; | |
c19d1205 ZW |
3579 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3580 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3581 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3582 | |= 1 << unwind.personality_index; |
c19d1205 | 3583 | } |
f02232aa | 3584 | |
c19d1205 ZW |
3585 | if (val) |
3586 | /* Inline exception table entry. */ | |
3587 | md_number_to_chars (ptr + 4, val, 4); | |
3588 | else | |
3589 | /* Self relative offset of the table entry. */ | |
3590 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3591 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3592 | |
c19d1205 ZW |
3593 | /* Restore the original section. */ |
3594 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3595 | |
3596 | unwind.proc_start = NULL; | |
c19d1205 | 3597 | } |
f02232aa | 3598 | |
f02232aa | 3599 | |
c19d1205 | 3600 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3601 | |
c19d1205 ZW |
3602 | static void |
3603 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3604 | { | |
3605 | demand_empty_rest_of_line (); | |
921e5f0a | 3606 | if (!unwind.proc_start) |
c921be7d | 3607 | as_bad (MISSING_FNSTART); |
921e5f0a | 3608 | |
c19d1205 ZW |
3609 | if (unwind.personality_routine || unwind.personality_index != -1) |
3610 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3611 | |
c19d1205 ZW |
3612 | unwind.personality_index = -2; |
3613 | } | |
b99bd4ef | 3614 | |
b99bd4ef | 3615 | |
c19d1205 | 3616 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3617 | |
c19d1205 ZW |
3618 | static void |
3619 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3620 | { | |
3621 | expressionS exp; | |
b99bd4ef | 3622 | |
921e5f0a | 3623 | if (!unwind.proc_start) |
c921be7d | 3624 | as_bad (MISSING_FNSTART); |
921e5f0a | 3625 | |
c19d1205 ZW |
3626 | if (unwind.personality_routine || unwind.personality_index != -1) |
3627 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3628 | |
c19d1205 | 3629 | expression (&exp); |
b99bd4ef | 3630 | |
c19d1205 ZW |
3631 | if (exp.X_op != O_constant |
3632 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3633 | { |
c19d1205 ZW |
3634 | as_bad (_("bad personality routine number")); |
3635 | ignore_rest_of_line (); | |
3636 | return; | |
b99bd4ef NC |
3637 | } |
3638 | ||
c19d1205 | 3639 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3640 | |
c19d1205 ZW |
3641 | demand_empty_rest_of_line (); |
3642 | } | |
e16bb312 | 3643 | |
e16bb312 | 3644 | |
c19d1205 | 3645 | /* Parse a personality directive. */ |
e16bb312 | 3646 | |
c19d1205 ZW |
3647 | static void |
3648 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3649 | { | |
3650 | char *name, *p, c; | |
a737bd4d | 3651 | |
921e5f0a | 3652 | if (!unwind.proc_start) |
c921be7d | 3653 | as_bad (MISSING_FNSTART); |
921e5f0a | 3654 | |
c19d1205 ZW |
3655 | if (unwind.personality_routine || unwind.personality_index != -1) |
3656 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3657 | |
c19d1205 ZW |
3658 | name = input_line_pointer; |
3659 | c = get_symbol_end (); | |
3660 | p = input_line_pointer; | |
3661 | unwind.personality_routine = symbol_find_or_make (name); | |
3662 | *p = c; | |
3663 | demand_empty_rest_of_line (); | |
3664 | } | |
e16bb312 | 3665 | |
e16bb312 | 3666 | |
c19d1205 | 3667 | /* Parse a directive saving core registers. */ |
e16bb312 | 3668 | |
c19d1205 ZW |
3669 | static void |
3670 | s_arm_unwind_save_core (void) | |
e16bb312 | 3671 | { |
c19d1205 ZW |
3672 | valueT op; |
3673 | long range; | |
3674 | int n; | |
e16bb312 | 3675 | |
c19d1205 ZW |
3676 | range = parse_reg_list (&input_line_pointer); |
3677 | if (range == FAIL) | |
e16bb312 | 3678 | { |
c19d1205 ZW |
3679 | as_bad (_("expected register list")); |
3680 | ignore_rest_of_line (); | |
3681 | return; | |
3682 | } | |
e16bb312 | 3683 | |
c19d1205 | 3684 | demand_empty_rest_of_line (); |
e16bb312 | 3685 | |
c19d1205 ZW |
3686 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3687 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3688 | ip because it is clobbered by calls. */ | |
3689 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3690 | && (range & 0x3000) == 0x1000) | |
3691 | { | |
3692 | unwind.opcode_count--; | |
3693 | unwind.sp_restored = 0; | |
3694 | range = (range | 0x2000) & ~0x1000; | |
3695 | unwind.pending_offset = 0; | |
3696 | } | |
e16bb312 | 3697 | |
01ae4198 DJ |
3698 | /* Pop r4-r15. */ |
3699 | if (range & 0xfff0) | |
c19d1205 | 3700 | { |
01ae4198 DJ |
3701 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3702 | registers starting with r4, plus maybe r14. */ | |
3703 | for (n = 0; n < 8; n++) | |
3704 | { | |
3705 | /* Break at the first non-saved register. */ | |
3706 | if ((range & (1 << (n + 4))) == 0) | |
3707 | break; | |
3708 | } | |
3709 | /* See if there are any other bits set. */ | |
3710 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3711 | { | |
3712 | /* Use the long form. */ | |
3713 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3714 | add_unwind_opcode (op, 2); | |
3715 | } | |
0dd132b6 | 3716 | else |
01ae4198 DJ |
3717 | { |
3718 | /* Use the short form. */ | |
3719 | if (range & 0x4000) | |
3720 | op = 0xa8; /* Pop r14. */ | |
3721 | else | |
3722 | op = 0xa0; /* Do not pop r14. */ | |
3723 | op |= (n - 1); | |
3724 | add_unwind_opcode (op, 1); | |
3725 | } | |
c19d1205 | 3726 | } |
0dd132b6 | 3727 | |
c19d1205 ZW |
3728 | /* Pop r0-r3. */ |
3729 | if (range & 0xf) | |
3730 | { | |
3731 | op = 0xb100 | (range & 0xf); | |
3732 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3733 | } |
3734 | ||
c19d1205 ZW |
3735 | /* Record the number of bytes pushed. */ |
3736 | for (n = 0; n < 16; n++) | |
3737 | { | |
3738 | if (range & (1 << n)) | |
3739 | unwind.frame_size += 4; | |
3740 | } | |
0dd132b6 NC |
3741 | } |
3742 | ||
c19d1205 ZW |
3743 | |
3744 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3745 | |
3746 | static void | |
c19d1205 | 3747 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3748 | { |
c19d1205 ZW |
3749 | expressionS exp; |
3750 | int num_regs; | |
3751 | valueT op; | |
b99bd4ef | 3752 | |
c19d1205 ZW |
3753 | /* Get Number of registers to transfer. */ |
3754 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3755 | expression (&exp); | |
3756 | else | |
3757 | exp.X_op = O_illegal; | |
b99bd4ef | 3758 | |
c19d1205 | 3759 | if (exp.X_op != O_constant) |
b99bd4ef | 3760 | { |
c19d1205 ZW |
3761 | as_bad (_("expected , <constant>")); |
3762 | ignore_rest_of_line (); | |
b99bd4ef NC |
3763 | return; |
3764 | } | |
3765 | ||
c19d1205 ZW |
3766 | num_regs = exp.X_add_number; |
3767 | ||
3768 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3769 | { |
c19d1205 ZW |
3770 | as_bad (_("number of registers must be in the range [1:4]")); |
3771 | ignore_rest_of_line (); | |
b99bd4ef NC |
3772 | return; |
3773 | } | |
3774 | ||
c19d1205 | 3775 | demand_empty_rest_of_line (); |
b99bd4ef | 3776 | |
c19d1205 ZW |
3777 | if (reg == 4) |
3778 | { | |
3779 | /* Short form. */ | |
3780 | op = 0xb4 | (num_regs - 1); | |
3781 | add_unwind_opcode (op, 1); | |
3782 | } | |
b99bd4ef NC |
3783 | else |
3784 | { | |
c19d1205 ZW |
3785 | /* Long form. */ |
3786 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3787 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3788 | } |
c19d1205 | 3789 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3790 | } |
3791 | ||
c19d1205 | 3792 | |
fa073d69 MS |
3793 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3794 | ||
3795 | static void | |
3796 | s_arm_unwind_save_vfp_armv6 (void) | |
3797 | { | |
3798 | int count; | |
3799 | unsigned int start; | |
3800 | valueT op; | |
3801 | int num_vfpv3_regs = 0; | |
3802 | int num_regs_below_16; | |
3803 | ||
3804 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3805 | if (count == FAIL) | |
3806 | { | |
3807 | as_bad (_("expected register list")); | |
3808 | ignore_rest_of_line (); | |
3809 | return; | |
3810 | } | |
3811 | ||
3812 | demand_empty_rest_of_line (); | |
3813 | ||
3814 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3815 | than FSTMX/FLDMX-style ones). */ | |
3816 | ||
3817 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3818 | if (start >= 16) | |
3819 | num_vfpv3_regs = count; | |
3820 | else if (start + count > 16) | |
3821 | num_vfpv3_regs = start + count - 16; | |
3822 | ||
3823 | if (num_vfpv3_regs > 0) | |
3824 | { | |
3825 | int start_offset = start > 16 ? start - 16 : 0; | |
3826 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3827 | add_unwind_opcode (op, 2); | |
3828 | } | |
3829 | ||
3830 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3831 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3832 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3833 | if (num_regs_below_16 > 0) |
3834 | { | |
3835 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3836 | add_unwind_opcode (op, 2); | |
3837 | } | |
3838 | ||
3839 | unwind.frame_size += count * 8; | |
3840 | } | |
3841 | ||
3842 | ||
3843 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3844 | |
3845 | static void | |
c19d1205 | 3846 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3847 | { |
c19d1205 | 3848 | int count; |
ca3f61f7 | 3849 | unsigned int reg; |
c19d1205 | 3850 | valueT op; |
b99bd4ef | 3851 | |
5287ad62 | 3852 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3853 | if (count == FAIL) |
b99bd4ef | 3854 | { |
c19d1205 ZW |
3855 | as_bad (_("expected register list")); |
3856 | ignore_rest_of_line (); | |
b99bd4ef NC |
3857 | return; |
3858 | } | |
3859 | ||
c19d1205 | 3860 | demand_empty_rest_of_line (); |
b99bd4ef | 3861 | |
c19d1205 | 3862 | if (reg == 8) |
b99bd4ef | 3863 | { |
c19d1205 ZW |
3864 | /* Short form. */ |
3865 | op = 0xb8 | (count - 1); | |
3866 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3867 | } |
c19d1205 | 3868 | else |
b99bd4ef | 3869 | { |
c19d1205 ZW |
3870 | /* Long form. */ |
3871 | op = 0xb300 | (reg << 4) | (count - 1); | |
3872 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3873 | } |
c19d1205 ZW |
3874 | unwind.frame_size += count * 8 + 4; |
3875 | } | |
b99bd4ef | 3876 | |
b99bd4ef | 3877 | |
c19d1205 ZW |
3878 | /* Parse a directive saving iWMMXt data registers. */ |
3879 | ||
3880 | static void | |
3881 | s_arm_unwind_save_mmxwr (void) | |
3882 | { | |
3883 | int reg; | |
3884 | int hi_reg; | |
3885 | int i; | |
3886 | unsigned mask = 0; | |
3887 | valueT op; | |
b99bd4ef | 3888 | |
c19d1205 ZW |
3889 | if (*input_line_pointer == '{') |
3890 | input_line_pointer++; | |
b99bd4ef | 3891 | |
c19d1205 | 3892 | do |
b99bd4ef | 3893 | { |
dcbf9037 | 3894 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3895 | |
c19d1205 | 3896 | if (reg == FAIL) |
b99bd4ef | 3897 | { |
9b7132d3 | 3898 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3899 | goto error; |
b99bd4ef NC |
3900 | } |
3901 | ||
c19d1205 ZW |
3902 | if (mask >> reg) |
3903 | as_tsktsk (_("register list not in ascending order")); | |
3904 | mask |= 1 << reg; | |
b99bd4ef | 3905 | |
c19d1205 ZW |
3906 | if (*input_line_pointer == '-') |
3907 | { | |
3908 | input_line_pointer++; | |
dcbf9037 | 3909 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3910 | if (hi_reg == FAIL) |
3911 | { | |
9b7132d3 | 3912 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3913 | goto error; |
3914 | } | |
3915 | else if (reg >= hi_reg) | |
3916 | { | |
3917 | as_bad (_("bad register range")); | |
3918 | goto error; | |
3919 | } | |
3920 | for (; reg < hi_reg; reg++) | |
3921 | mask |= 1 << reg; | |
3922 | } | |
3923 | } | |
3924 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3925 | |
c19d1205 ZW |
3926 | if (*input_line_pointer == '}') |
3927 | input_line_pointer++; | |
b99bd4ef | 3928 | |
c19d1205 | 3929 | demand_empty_rest_of_line (); |
b99bd4ef | 3930 | |
708587a4 | 3931 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3932 | the list. */ |
3933 | flush_pending_unwind (); | |
b99bd4ef | 3934 | |
c19d1205 | 3935 | for (i = 0; i < 16; i++) |
b99bd4ef | 3936 | { |
c19d1205 ZW |
3937 | if (mask & (1 << i)) |
3938 | unwind.frame_size += 8; | |
b99bd4ef NC |
3939 | } |
3940 | ||
c19d1205 ZW |
3941 | /* Attempt to combine with a previous opcode. We do this because gcc |
3942 | likes to output separate unwind directives for a single block of | |
3943 | registers. */ | |
3944 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3945 | { |
c19d1205 ZW |
3946 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3947 | if ((i & 0xf8) == 0xc0) | |
3948 | { | |
3949 | i &= 7; | |
3950 | /* Only merge if the blocks are contiguous. */ | |
3951 | if (i < 6) | |
3952 | { | |
3953 | if ((mask & 0xfe00) == (1 << 9)) | |
3954 | { | |
3955 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3956 | unwind.opcode_count--; | |
3957 | } | |
3958 | } | |
3959 | else if (i == 6 && unwind.opcode_count >= 2) | |
3960 | { | |
3961 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3962 | reg = i >> 4; | |
3963 | i &= 0xf; | |
b99bd4ef | 3964 | |
c19d1205 ZW |
3965 | op = 0xffff << (reg - 1); |
3966 | if (reg > 0 | |
87a1fd79 | 3967 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3968 | { |
3969 | op = (1 << (reg + i + 1)) - 1; | |
3970 | op &= ~((1 << reg) - 1); | |
3971 | mask |= op; | |
3972 | unwind.opcode_count -= 2; | |
3973 | } | |
3974 | } | |
3975 | } | |
b99bd4ef NC |
3976 | } |
3977 | ||
c19d1205 ZW |
3978 | hi_reg = 15; |
3979 | /* We want to generate opcodes in the order the registers have been | |
3980 | saved, ie. descending order. */ | |
3981 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3982 | { |
c19d1205 ZW |
3983 | /* Save registers in blocks. */ |
3984 | if (reg < 0 | |
3985 | || !(mask & (1 << reg))) | |
3986 | { | |
3987 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3988 | preceding block. */ |
c19d1205 ZW |
3989 | if (reg != hi_reg) |
3990 | { | |
3991 | if (reg == 9) | |
3992 | { | |
3993 | /* Short form. */ | |
3994 | op = 0xc0 | (hi_reg - 10); | |
3995 | add_unwind_opcode (op, 1); | |
3996 | } | |
3997 | else | |
3998 | { | |
3999 | /* Long form. */ | |
4000 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4001 | add_unwind_opcode (op, 2); | |
4002 | } | |
4003 | } | |
4004 | hi_reg = reg - 1; | |
4005 | } | |
b99bd4ef NC |
4006 | } |
4007 | ||
c19d1205 ZW |
4008 | return; |
4009 | error: | |
4010 | ignore_rest_of_line (); | |
b99bd4ef NC |
4011 | } |
4012 | ||
4013 | static void | |
c19d1205 | 4014 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4015 | { |
c19d1205 ZW |
4016 | int reg; |
4017 | int hi_reg; | |
4018 | unsigned mask = 0; | |
4019 | valueT op; | |
b99bd4ef | 4020 | |
c19d1205 ZW |
4021 | if (*input_line_pointer == '{') |
4022 | input_line_pointer++; | |
b99bd4ef | 4023 | |
c19d1205 | 4024 | do |
b99bd4ef | 4025 | { |
dcbf9037 | 4026 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4027 | |
c19d1205 ZW |
4028 | if (reg == FAIL) |
4029 | { | |
9b7132d3 | 4030 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4031 | goto error; |
4032 | } | |
b99bd4ef | 4033 | |
c19d1205 ZW |
4034 | reg -= 8; |
4035 | if (mask >> reg) | |
4036 | as_tsktsk (_("register list not in ascending order")); | |
4037 | mask |= 1 << reg; | |
b99bd4ef | 4038 | |
c19d1205 ZW |
4039 | if (*input_line_pointer == '-') |
4040 | { | |
4041 | input_line_pointer++; | |
dcbf9037 | 4042 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4043 | if (hi_reg == FAIL) |
4044 | { | |
9b7132d3 | 4045 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4046 | goto error; |
4047 | } | |
4048 | else if (reg >= hi_reg) | |
4049 | { | |
4050 | as_bad (_("bad register range")); | |
4051 | goto error; | |
4052 | } | |
4053 | for (; reg < hi_reg; reg++) | |
4054 | mask |= 1 << reg; | |
4055 | } | |
b99bd4ef | 4056 | } |
c19d1205 | 4057 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4058 | |
c19d1205 ZW |
4059 | if (*input_line_pointer == '}') |
4060 | input_line_pointer++; | |
b99bd4ef | 4061 | |
c19d1205 ZW |
4062 | demand_empty_rest_of_line (); |
4063 | ||
708587a4 | 4064 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4065 | the list. */ |
4066 | flush_pending_unwind (); | |
b99bd4ef | 4067 | |
c19d1205 | 4068 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4069 | { |
c19d1205 ZW |
4070 | if (mask & (1 << reg)) |
4071 | unwind.frame_size += 4; | |
b99bd4ef | 4072 | } |
c19d1205 ZW |
4073 | op = 0xc700 | mask; |
4074 | add_unwind_opcode (op, 2); | |
4075 | return; | |
4076 | error: | |
4077 | ignore_rest_of_line (); | |
b99bd4ef NC |
4078 | } |
4079 | ||
c19d1205 | 4080 | |
fa073d69 MS |
4081 | /* Parse an unwind_save directive. |
4082 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4083 | |
b99bd4ef | 4084 | static void |
fa073d69 | 4085 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4086 | { |
c19d1205 ZW |
4087 | char *peek; |
4088 | struct reg_entry *reg; | |
4089 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4090 | |
921e5f0a | 4091 | if (!unwind.proc_start) |
c921be7d | 4092 | as_bad (MISSING_FNSTART); |
921e5f0a | 4093 | |
c19d1205 ZW |
4094 | /* Figure out what sort of save we have. */ |
4095 | peek = input_line_pointer; | |
b99bd4ef | 4096 | |
c19d1205 | 4097 | if (*peek == '{') |
b99bd4ef | 4098 | { |
c19d1205 ZW |
4099 | had_brace = TRUE; |
4100 | peek++; | |
b99bd4ef NC |
4101 | } |
4102 | ||
c19d1205 | 4103 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4104 | |
c19d1205 | 4105 | if (!reg) |
b99bd4ef | 4106 | { |
c19d1205 ZW |
4107 | as_bad (_("register expected")); |
4108 | ignore_rest_of_line (); | |
b99bd4ef NC |
4109 | return; |
4110 | } | |
4111 | ||
c19d1205 | 4112 | switch (reg->type) |
b99bd4ef | 4113 | { |
c19d1205 ZW |
4114 | case REG_TYPE_FN: |
4115 | if (had_brace) | |
4116 | { | |
4117 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4118 | ignore_rest_of_line (); | |
4119 | return; | |
4120 | } | |
93ac2687 | 4121 | input_line_pointer = peek; |
c19d1205 | 4122 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4123 | return; |
c19d1205 ZW |
4124 | |
4125 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4126 | case REG_TYPE_VFD: |
4127 | if (arch_v6) | |
4128 | s_arm_unwind_save_vfp_armv6 (); | |
4129 | else | |
4130 | s_arm_unwind_save_vfp (); | |
4131 | return; | |
c19d1205 ZW |
4132 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4133 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4134 | ||
4135 | default: | |
4136 | as_bad (_(".unwind_save does not support this kind of register")); | |
4137 | ignore_rest_of_line (); | |
b99bd4ef | 4138 | } |
c19d1205 | 4139 | } |
b99bd4ef | 4140 | |
b99bd4ef | 4141 | |
c19d1205 ZW |
4142 | /* Parse an unwind_movsp directive. */ |
4143 | ||
4144 | static void | |
4145 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4146 | { | |
4147 | int reg; | |
4148 | valueT op; | |
4fa3602b | 4149 | int offset; |
c19d1205 | 4150 | |
921e5f0a | 4151 | if (!unwind.proc_start) |
c921be7d | 4152 | as_bad (MISSING_FNSTART); |
921e5f0a | 4153 | |
dcbf9037 | 4154 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4155 | if (reg == FAIL) |
b99bd4ef | 4156 | { |
9b7132d3 | 4157 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4158 | ignore_rest_of_line (); |
b99bd4ef NC |
4159 | return; |
4160 | } | |
4fa3602b PB |
4161 | |
4162 | /* Optional constant. */ | |
4163 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4164 | { | |
4165 | if (immediate_for_directive (&offset) == FAIL) | |
4166 | return; | |
4167 | } | |
4168 | else | |
4169 | offset = 0; | |
4170 | ||
c19d1205 | 4171 | demand_empty_rest_of_line (); |
b99bd4ef | 4172 | |
c19d1205 | 4173 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4174 | { |
c19d1205 | 4175 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4176 | return; |
4177 | } | |
4178 | ||
c19d1205 ZW |
4179 | if (unwind.fp_reg != REG_SP) |
4180 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4181 | |
c19d1205 ZW |
4182 | /* Generate opcode to restore the value. */ |
4183 | op = 0x90 | reg; | |
4184 | add_unwind_opcode (op, 1); | |
4185 | ||
4186 | /* Record the information for later. */ | |
4187 | unwind.fp_reg = reg; | |
4fa3602b | 4188 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4189 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4190 | } |
4191 | ||
c19d1205 ZW |
4192 | /* Parse an unwind_pad directive. */ |
4193 | ||
b05fe5cf | 4194 | static void |
c19d1205 | 4195 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4196 | { |
c19d1205 | 4197 | int offset; |
b05fe5cf | 4198 | |
921e5f0a | 4199 | if (!unwind.proc_start) |
c921be7d | 4200 | as_bad (MISSING_FNSTART); |
921e5f0a | 4201 | |
c19d1205 ZW |
4202 | if (immediate_for_directive (&offset) == FAIL) |
4203 | return; | |
b99bd4ef | 4204 | |
c19d1205 ZW |
4205 | if (offset & 3) |
4206 | { | |
4207 | as_bad (_("stack increment must be multiple of 4")); | |
4208 | ignore_rest_of_line (); | |
4209 | return; | |
4210 | } | |
b99bd4ef | 4211 | |
c19d1205 ZW |
4212 | /* Don't generate any opcodes, just record the details for later. */ |
4213 | unwind.frame_size += offset; | |
4214 | unwind.pending_offset += offset; | |
4215 | ||
4216 | demand_empty_rest_of_line (); | |
4217 | } | |
4218 | ||
4219 | /* Parse an unwind_setfp directive. */ | |
4220 | ||
4221 | static void | |
4222 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4223 | { |
c19d1205 ZW |
4224 | int sp_reg; |
4225 | int fp_reg; | |
4226 | int offset; | |
4227 | ||
921e5f0a | 4228 | if (!unwind.proc_start) |
c921be7d | 4229 | as_bad (MISSING_FNSTART); |
921e5f0a | 4230 | |
dcbf9037 | 4231 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4232 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4233 | sp_reg = FAIL; | |
4234 | else | |
dcbf9037 | 4235 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4236 | |
c19d1205 ZW |
4237 | if (fp_reg == FAIL || sp_reg == FAIL) |
4238 | { | |
4239 | as_bad (_("expected <reg>, <reg>")); | |
4240 | ignore_rest_of_line (); | |
4241 | return; | |
4242 | } | |
b99bd4ef | 4243 | |
c19d1205 ZW |
4244 | /* Optional constant. */ |
4245 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4246 | { | |
4247 | if (immediate_for_directive (&offset) == FAIL) | |
4248 | return; | |
4249 | } | |
4250 | else | |
4251 | offset = 0; | |
a737bd4d | 4252 | |
c19d1205 | 4253 | demand_empty_rest_of_line (); |
a737bd4d | 4254 | |
fdfde340 | 4255 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4256 | { |
c19d1205 ZW |
4257 | as_bad (_("register must be either sp or set by a previous" |
4258 | "unwind_movsp directive")); | |
4259 | return; | |
a737bd4d NC |
4260 | } |
4261 | ||
c19d1205 ZW |
4262 | /* Don't generate any opcodes, just record the information for later. */ |
4263 | unwind.fp_reg = fp_reg; | |
4264 | unwind.fp_used = 1; | |
fdfde340 | 4265 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4266 | unwind.fp_offset = unwind.frame_size - offset; |
4267 | else | |
4268 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4269 | } |
4270 | ||
c19d1205 ZW |
4271 | /* Parse an unwind_raw directive. */ |
4272 | ||
4273 | static void | |
4274 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4275 | { |
c19d1205 | 4276 | expressionS exp; |
708587a4 | 4277 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4278 | unsigned char op[16]; |
4279 | int count; | |
a737bd4d | 4280 | |
921e5f0a | 4281 | if (!unwind.proc_start) |
c921be7d | 4282 | as_bad (MISSING_FNSTART); |
921e5f0a | 4283 | |
c19d1205 ZW |
4284 | expression (&exp); |
4285 | if (exp.X_op == O_constant | |
4286 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4287 | { |
c19d1205 ZW |
4288 | unwind.frame_size += exp.X_add_number; |
4289 | expression (&exp); | |
4290 | } | |
4291 | else | |
4292 | exp.X_op = O_illegal; | |
a737bd4d | 4293 | |
c19d1205 ZW |
4294 | if (exp.X_op != O_constant) |
4295 | { | |
4296 | as_bad (_("expected <offset>, <opcode>")); | |
4297 | ignore_rest_of_line (); | |
4298 | return; | |
4299 | } | |
a737bd4d | 4300 | |
c19d1205 | 4301 | count = 0; |
a737bd4d | 4302 | |
c19d1205 ZW |
4303 | /* Parse the opcode. */ |
4304 | for (;;) | |
4305 | { | |
4306 | if (count >= 16) | |
4307 | { | |
4308 | as_bad (_("unwind opcode too long")); | |
4309 | ignore_rest_of_line (); | |
a737bd4d | 4310 | } |
c19d1205 | 4311 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4312 | { |
c19d1205 ZW |
4313 | as_bad (_("invalid unwind opcode")); |
4314 | ignore_rest_of_line (); | |
4315 | return; | |
a737bd4d | 4316 | } |
c19d1205 | 4317 | op[count++] = exp.X_add_number; |
a737bd4d | 4318 | |
c19d1205 ZW |
4319 | /* Parse the next byte. */ |
4320 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4321 | break; | |
a737bd4d | 4322 | |
c19d1205 ZW |
4323 | expression (&exp); |
4324 | } | |
b99bd4ef | 4325 | |
c19d1205 ZW |
4326 | /* Add the opcode bytes in reverse order. */ |
4327 | while (count--) | |
4328 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4329 | |
c19d1205 | 4330 | demand_empty_rest_of_line (); |
b99bd4ef | 4331 | } |
ee065d83 PB |
4332 | |
4333 | ||
4334 | /* Parse a .eabi_attribute directive. */ | |
4335 | ||
4336 | static void | |
4337 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4338 | { | |
ee3c0378 AS |
4339 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4340 | ||
4341 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4342 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4343 | } |
4344 | ||
0855e32b NS |
4345 | /* Emit a tls fix for the symbol. */ |
4346 | ||
4347 | static void | |
4348 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4349 | { | |
4350 | char *p; | |
4351 | expressionS exp; | |
4352 | #ifdef md_flush_pending_output | |
4353 | md_flush_pending_output (); | |
4354 | #endif | |
4355 | ||
4356 | #ifdef md_cons_align | |
4357 | md_cons_align (4); | |
4358 | #endif | |
4359 | ||
4360 | /* Since we're just labelling the code, there's no need to define a | |
4361 | mapping symbol. */ | |
4362 | expression (&exp); | |
4363 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4364 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4365 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4366 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4367 | } | |
cdf9ccec | 4368 | #endif /* OBJ_ELF */ |
0855e32b | 4369 | |
ee065d83 | 4370 | static void s_arm_arch (int); |
7a1d4c38 | 4371 | static void s_arm_object_arch (int); |
ee065d83 PB |
4372 | static void s_arm_cpu (int); |
4373 | static void s_arm_fpu (int); | |
69133863 | 4374 | static void s_arm_arch_extension (int); |
b99bd4ef | 4375 | |
f0927246 NC |
4376 | #ifdef TE_PE |
4377 | ||
4378 | static void | |
5f4273c7 | 4379 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4380 | { |
4381 | expressionS exp; | |
4382 | ||
4383 | do | |
4384 | { | |
4385 | expression (&exp); | |
4386 | if (exp.X_op == O_symbol) | |
4387 | exp.X_op = O_secrel; | |
4388 | ||
4389 | emit_expr (&exp, 4); | |
4390 | } | |
4391 | while (*input_line_pointer++ == ','); | |
4392 | ||
4393 | input_line_pointer--; | |
4394 | demand_empty_rest_of_line (); | |
4395 | } | |
4396 | #endif /* TE_PE */ | |
4397 | ||
c19d1205 ZW |
4398 | /* This table describes all the machine specific pseudo-ops the assembler |
4399 | has to support. The fields are: | |
4400 | pseudo-op name without dot | |
4401 | function to call to execute this pseudo-op | |
4402 | Integer arg to pass to the function. */ | |
b99bd4ef | 4403 | |
c19d1205 | 4404 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4405 | { |
c19d1205 ZW |
4406 | /* Never called because '.req' does not start a line. */ |
4407 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4408 | /* Following two are likewise never called. */ |
4409 | { "dn", s_dn, 0 }, | |
4410 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4411 | { "unreq", s_unreq, 0 }, |
4412 | { "bss", s_bss, 0 }, | |
4413 | { "align", s_align, 0 }, | |
4414 | { "arm", s_arm, 0 }, | |
4415 | { "thumb", s_thumb, 0 }, | |
4416 | { "code", s_code, 0 }, | |
4417 | { "force_thumb", s_force_thumb, 0 }, | |
4418 | { "thumb_func", s_thumb_func, 0 }, | |
4419 | { "thumb_set", s_thumb_set, 0 }, | |
4420 | { "even", s_even, 0 }, | |
4421 | { "ltorg", s_ltorg, 0 }, | |
4422 | { "pool", s_ltorg, 0 }, | |
4423 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4424 | { "cpu", s_arm_cpu, 0 }, |
4425 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4426 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4427 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4428 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4429 | #ifdef OBJ_ELF |
c921be7d NC |
4430 | { "word", s_arm_elf_cons, 4 }, |
4431 | { "long", s_arm_elf_cons, 4 }, | |
4432 | { "inst.n", s_arm_elf_inst, 2 }, | |
4433 | { "inst.w", s_arm_elf_inst, 4 }, | |
4434 | { "inst", s_arm_elf_inst, 0 }, | |
4435 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4436 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4437 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4438 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4439 | { "personality", s_arm_unwind_personality, 0 }, | |
4440 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4441 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4442 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4443 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4444 | { "movsp", s_arm_unwind_movsp, 0 }, |
4445 | { "pad", s_arm_unwind_pad, 0 }, | |
4446 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4447 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4448 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4449 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4450 | #else |
4451 | { "word", cons, 4}, | |
f0927246 NC |
4452 | |
4453 | /* These are used for dwarf. */ | |
4454 | {"2byte", cons, 2}, | |
4455 | {"4byte", cons, 4}, | |
4456 | {"8byte", cons, 8}, | |
4457 | /* These are used for dwarf2. */ | |
4458 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4459 | { "loc", dwarf2_directive_loc, 0 }, | |
4460 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4461 | #endif |
4462 | { "extend", float_cons, 'x' }, | |
4463 | { "ldouble", float_cons, 'x' }, | |
4464 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4465 | #ifdef TE_PE |
4466 | {"secrel32", pe_directive_secrel, 0}, | |
4467 | #endif | |
c19d1205 ZW |
4468 | { 0, 0, 0 } |
4469 | }; | |
4470 | \f | |
4471 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4472 | |
c19d1205 ZW |
4473 | /* Generic immediate-value read function for use in insn parsing. |
4474 | STR points to the beginning of the immediate (the leading #); | |
4475 | VAL receives the value; if the value is outside [MIN, MAX] | |
4476 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4477 | optional. */ | |
b99bd4ef | 4478 | |
c19d1205 ZW |
4479 | static int |
4480 | parse_immediate (char **str, int *val, int min, int max, | |
4481 | bfd_boolean prefix_opt) | |
4482 | { | |
4483 | expressionS exp; | |
4484 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4485 | if (exp.X_op != O_constant) | |
b99bd4ef | 4486 | { |
c19d1205 ZW |
4487 | inst.error = _("constant expression required"); |
4488 | return FAIL; | |
4489 | } | |
b99bd4ef | 4490 | |
c19d1205 ZW |
4491 | if (exp.X_add_number < min || exp.X_add_number > max) |
4492 | { | |
4493 | inst.error = _("immediate value out of range"); | |
4494 | return FAIL; | |
4495 | } | |
b99bd4ef | 4496 | |
c19d1205 ZW |
4497 | *val = exp.X_add_number; |
4498 | return SUCCESS; | |
4499 | } | |
b99bd4ef | 4500 | |
5287ad62 | 4501 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4502 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4503 | instructions. Puts the result directly in inst.operands[i]. */ |
4504 | ||
4505 | static int | |
4506 | parse_big_immediate (char **str, int i) | |
4507 | { | |
4508 | expressionS exp; | |
4509 | char *ptr = *str; | |
4510 | ||
4511 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4512 | ||
4513 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4514 | { |
4515 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4516 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4517 | O_constant. We have to be careful not to break compilation for | |
4518 | 32-bit X_add_number, though. */ | |
58ad575f | 4519 | if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 PB |
4520 | { |
4521 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4522 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4523 | inst.operands[i].regisimm = 1; | |
4524 | } | |
4525 | } | |
5287ad62 | 4526 | else if (exp.X_op == O_big |
95b75c01 | 4527 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) |
5287ad62 JB |
4528 | { |
4529 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4530 | |
5287ad62 JB |
4531 | /* Bignums have their least significant bits in |
4532 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4533 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4534 | gas_assert (parts != 0); |
95b75c01 NC |
4535 | |
4536 | /* Make sure that the number is not too big. | |
4537 | PR 11972: Bignums can now be sign-extended to the | |
4538 | size of a .octa so check that the out of range bits | |
4539 | are all zero or all one. */ | |
4540 | if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) | |
4541 | { | |
4542 | LITTLENUM_TYPE m = -1; | |
4543 | ||
4544 | if (generic_bignum[parts * 2] != 0 | |
4545 | && generic_bignum[parts * 2] != m) | |
4546 | return FAIL; | |
4547 | ||
4548 | for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) | |
4549 | if (generic_bignum[j] != generic_bignum[j-1]) | |
4550 | return FAIL; | |
4551 | } | |
4552 | ||
5287ad62 JB |
4553 | inst.operands[i].imm = 0; |
4554 | for (j = 0; j < parts; j++, idx++) | |
4555 | inst.operands[i].imm |= generic_bignum[idx] | |
4556 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4557 | inst.operands[i].reg = 0; | |
4558 | for (j = 0; j < parts; j++, idx++) | |
4559 | inst.operands[i].reg |= generic_bignum[idx] | |
4560 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4561 | inst.operands[i].regisimm = 1; | |
4562 | } | |
4563 | else | |
4564 | return FAIL; | |
5f4273c7 | 4565 | |
5287ad62 JB |
4566 | *str = ptr; |
4567 | ||
4568 | return SUCCESS; | |
4569 | } | |
4570 | ||
c19d1205 ZW |
4571 | /* Returns the pseudo-register number of an FPA immediate constant, |
4572 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4573 | |
c19d1205 ZW |
4574 | static int |
4575 | parse_fpa_immediate (char ** str) | |
4576 | { | |
4577 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4578 | char * save_in; | |
4579 | expressionS exp; | |
4580 | int i; | |
4581 | int j; | |
b99bd4ef | 4582 | |
c19d1205 ZW |
4583 | /* First try and match exact strings, this is to guarantee |
4584 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4585 | |
c19d1205 ZW |
4586 | for (i = 0; fp_const[i]; i++) |
4587 | { | |
4588 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4589 | { |
c19d1205 | 4590 | char *start = *str; |
b99bd4ef | 4591 | |
c19d1205 ZW |
4592 | *str += strlen (fp_const[i]); |
4593 | if (is_end_of_line[(unsigned char) **str]) | |
4594 | return i + 8; | |
4595 | *str = start; | |
4596 | } | |
4597 | } | |
b99bd4ef | 4598 | |
c19d1205 ZW |
4599 | /* Just because we didn't get a match doesn't mean that the constant |
4600 | isn't valid, just that it is in a format that we don't | |
4601 | automatically recognize. Try parsing it with the standard | |
4602 | expression routines. */ | |
b99bd4ef | 4603 | |
c19d1205 | 4604 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4605 | |
c19d1205 ZW |
4606 | /* Look for a raw floating point number. */ |
4607 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4608 | && is_end_of_line[(unsigned char) *save_in]) | |
4609 | { | |
4610 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4611 | { | |
4612 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4613 | { |
c19d1205 ZW |
4614 | if (words[j] != fp_values[i][j]) |
4615 | break; | |
b99bd4ef NC |
4616 | } |
4617 | ||
c19d1205 | 4618 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4619 | { |
c19d1205 ZW |
4620 | *str = save_in; |
4621 | return i + 8; | |
b99bd4ef NC |
4622 | } |
4623 | } | |
4624 | } | |
b99bd4ef | 4625 | |
c19d1205 ZW |
4626 | /* Try and parse a more complex expression, this will probably fail |
4627 | unless the code uses a floating point prefix (eg "0f"). */ | |
4628 | save_in = input_line_pointer; | |
4629 | input_line_pointer = *str; | |
4630 | if (expression (&exp) == absolute_section | |
4631 | && exp.X_op == O_big | |
4632 | && exp.X_add_number < 0) | |
4633 | { | |
4634 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4635 | Ditto for 15. */ | |
4636 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4637 | { | |
4638 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4639 | { | |
4640 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4641 | { | |
4642 | if (words[j] != fp_values[i][j]) | |
4643 | break; | |
4644 | } | |
b99bd4ef | 4645 | |
c19d1205 ZW |
4646 | if (j == MAX_LITTLENUMS) |
4647 | { | |
4648 | *str = input_line_pointer; | |
4649 | input_line_pointer = save_in; | |
4650 | return i + 8; | |
4651 | } | |
4652 | } | |
4653 | } | |
b99bd4ef NC |
4654 | } |
4655 | ||
c19d1205 ZW |
4656 | *str = input_line_pointer; |
4657 | input_line_pointer = save_in; | |
4658 | inst.error = _("invalid FPA immediate expression"); | |
4659 | return FAIL; | |
b99bd4ef NC |
4660 | } |
4661 | ||
136da414 JB |
4662 | /* Returns 1 if a number has "quarter-precision" float format |
4663 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4664 | ||
4665 | static int | |
4666 | is_quarter_float (unsigned imm) | |
4667 | { | |
4668 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4669 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4670 | } | |
4671 | ||
4672 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4673 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4674 | The zero and minus-zero cases need special handling, since they can't be |
4675 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4676 | loaded as integer constants. */ | |
136da414 JB |
4677 | |
4678 | static unsigned | |
4679 | parse_qfloat_immediate (char **ccp, int *immed) | |
4680 | { | |
4681 | char *str = *ccp; | |
c96612cc | 4682 | char *fpnum; |
136da414 | 4683 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4684 | int found_fpchar = 0; |
5f4273c7 | 4685 | |
136da414 | 4686 | skip_past_char (&str, '#'); |
5f4273c7 | 4687 | |
c96612cc JB |
4688 | /* We must not accidentally parse an integer as a floating-point number. Make |
4689 | sure that the value we parse is not an integer by checking for special | |
4690 | characters '.' or 'e'. | |
4691 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4692 | information isn't in a very usable state at parse time. */ | |
4693 | fpnum = str; | |
4694 | skip_whitespace (fpnum); | |
4695 | ||
4696 | if (strncmp (fpnum, "0x", 2) == 0) | |
4697 | return FAIL; | |
4698 | else | |
4699 | { | |
4700 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4701 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4702 | { | |
4703 | found_fpchar = 1; | |
4704 | break; | |
4705 | } | |
4706 | ||
4707 | if (!found_fpchar) | |
4708 | return FAIL; | |
4709 | } | |
5f4273c7 | 4710 | |
136da414 JB |
4711 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4712 | { | |
4713 | unsigned fpword = 0; | |
4714 | int i; | |
5f4273c7 | 4715 | |
136da414 JB |
4716 | /* Our FP word must be 32 bits (single-precision FP). */ |
4717 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4718 | { | |
4719 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4720 | fpword |= words[i]; | |
4721 | } | |
5f4273c7 | 4722 | |
c96612cc | 4723 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4724 | *immed = fpword; |
4725 | else | |
4726 | return FAIL; | |
4727 | ||
4728 | *ccp = str; | |
5f4273c7 | 4729 | |
136da414 JB |
4730 | return SUCCESS; |
4731 | } | |
5f4273c7 | 4732 | |
136da414 JB |
4733 | return FAIL; |
4734 | } | |
4735 | ||
c19d1205 ZW |
4736 | /* Shift operands. */ |
4737 | enum shift_kind | |
b99bd4ef | 4738 | { |
c19d1205 ZW |
4739 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4740 | }; | |
b99bd4ef | 4741 | |
c19d1205 ZW |
4742 | struct asm_shift_name |
4743 | { | |
4744 | const char *name; | |
4745 | enum shift_kind kind; | |
4746 | }; | |
b99bd4ef | 4747 | |
c19d1205 ZW |
4748 | /* Third argument to parse_shift. */ |
4749 | enum parse_shift_mode | |
4750 | { | |
4751 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4752 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4753 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4754 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4755 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4756 | }; | |
b99bd4ef | 4757 | |
c19d1205 ZW |
4758 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4759 | This has three forms: | |
b99bd4ef | 4760 | |
c19d1205 ZW |
4761 | (LSL|LSR|ASL|ASR|ROR) Rs |
4762 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4763 | RRX | |
b99bd4ef | 4764 | |
c19d1205 ZW |
4765 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4766 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4767 | |
c19d1205 ZW |
4768 | static int |
4769 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4770 | { |
c19d1205 ZW |
4771 | const struct asm_shift_name *shift_name; |
4772 | enum shift_kind shift; | |
4773 | char *s = *str; | |
4774 | char *p = s; | |
4775 | int reg; | |
b99bd4ef | 4776 | |
c19d1205 ZW |
4777 | for (p = *str; ISALPHA (*p); p++) |
4778 | ; | |
b99bd4ef | 4779 | |
c19d1205 | 4780 | if (p == *str) |
b99bd4ef | 4781 | { |
c19d1205 ZW |
4782 | inst.error = _("shift expression expected"); |
4783 | return FAIL; | |
b99bd4ef NC |
4784 | } |
4785 | ||
21d799b5 NC |
4786 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4787 | p - *str); | |
c19d1205 ZW |
4788 | |
4789 | if (shift_name == NULL) | |
b99bd4ef | 4790 | { |
c19d1205 ZW |
4791 | inst.error = _("shift expression expected"); |
4792 | return FAIL; | |
b99bd4ef NC |
4793 | } |
4794 | ||
c19d1205 | 4795 | shift = shift_name->kind; |
b99bd4ef | 4796 | |
c19d1205 ZW |
4797 | switch (mode) |
4798 | { | |
4799 | case NO_SHIFT_RESTRICT: | |
4800 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4801 | |
c19d1205 ZW |
4802 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4803 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4804 | { | |
4805 | inst.error = _("'LSL' or 'ASR' required"); | |
4806 | return FAIL; | |
4807 | } | |
4808 | break; | |
b99bd4ef | 4809 | |
c19d1205 ZW |
4810 | case SHIFT_LSL_IMMEDIATE: |
4811 | if (shift != SHIFT_LSL) | |
4812 | { | |
4813 | inst.error = _("'LSL' required"); | |
4814 | return FAIL; | |
4815 | } | |
4816 | break; | |
b99bd4ef | 4817 | |
c19d1205 ZW |
4818 | case SHIFT_ASR_IMMEDIATE: |
4819 | if (shift != SHIFT_ASR) | |
4820 | { | |
4821 | inst.error = _("'ASR' required"); | |
4822 | return FAIL; | |
4823 | } | |
4824 | break; | |
b99bd4ef | 4825 | |
c19d1205 ZW |
4826 | default: abort (); |
4827 | } | |
b99bd4ef | 4828 | |
c19d1205 ZW |
4829 | if (shift != SHIFT_RRX) |
4830 | { | |
4831 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4832 | skip_whitespace (p); | |
b99bd4ef | 4833 | |
c19d1205 | 4834 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4835 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4836 | { |
4837 | inst.operands[i].imm = reg; | |
4838 | inst.operands[i].immisreg = 1; | |
4839 | } | |
4840 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4841 | return FAIL; | |
4842 | } | |
4843 | inst.operands[i].shift_kind = shift; | |
4844 | inst.operands[i].shifted = 1; | |
4845 | *str = p; | |
4846 | return SUCCESS; | |
b99bd4ef NC |
4847 | } |
4848 | ||
c19d1205 | 4849 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4850 | |
c19d1205 ZW |
4851 | #<immediate> |
4852 | #<immediate>, <rotate> | |
4853 | <Rm> | |
4854 | <Rm>, <shift> | |
b99bd4ef | 4855 | |
c19d1205 ZW |
4856 | where <shift> is defined by parse_shift above, and <rotate> is a |
4857 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4858 | is deferred to md_apply_fix. */ |
b99bd4ef | 4859 | |
c19d1205 ZW |
4860 | static int |
4861 | parse_shifter_operand (char **str, int i) | |
4862 | { | |
4863 | int value; | |
91d6fa6a | 4864 | expressionS exp; |
b99bd4ef | 4865 | |
dcbf9037 | 4866 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4867 | { |
4868 | inst.operands[i].reg = value; | |
4869 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4870 | |
c19d1205 ZW |
4871 | /* parse_shift will override this if appropriate */ |
4872 | inst.reloc.exp.X_op = O_constant; | |
4873 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4874 | |
c19d1205 ZW |
4875 | if (skip_past_comma (str) == FAIL) |
4876 | return SUCCESS; | |
b99bd4ef | 4877 | |
c19d1205 ZW |
4878 | /* Shift operation on register. */ |
4879 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4880 | } |
4881 | ||
c19d1205 ZW |
4882 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4883 | return FAIL; | |
b99bd4ef | 4884 | |
c19d1205 | 4885 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4886 | { |
c19d1205 | 4887 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4888 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4889 | return FAIL; |
b99bd4ef | 4890 | |
91d6fa6a | 4891 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4892 | { |
4893 | inst.error = _("constant expression expected"); | |
4894 | return FAIL; | |
4895 | } | |
b99bd4ef | 4896 | |
91d6fa6a | 4897 | value = exp.X_add_number; |
c19d1205 ZW |
4898 | if (value < 0 || value > 30 || value % 2 != 0) |
4899 | { | |
4900 | inst.error = _("invalid rotation"); | |
4901 | return FAIL; | |
4902 | } | |
4903 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4904 | { | |
4905 | inst.error = _("invalid constant"); | |
4906 | return FAIL; | |
4907 | } | |
09d92015 | 4908 | |
a415b1cd JB |
4909 | /* Encode as specified. */ |
4910 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
4911 | return SUCCESS; | |
09d92015 MM |
4912 | } |
4913 | ||
c19d1205 ZW |
4914 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4915 | inst.reloc.pc_rel = 0; | |
4916 | return SUCCESS; | |
09d92015 MM |
4917 | } |
4918 | ||
4962c51a MS |
4919 | /* Group relocation information. Each entry in the table contains the |
4920 | textual name of the relocation as may appear in assembler source | |
4921 | and must end with a colon. | |
4922 | Along with this textual name are the relocation codes to be used if | |
4923 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4924 | an LDR, an LDRS, or an LDC. */ | |
4925 | ||
4926 | struct group_reloc_table_entry | |
4927 | { | |
4928 | const char *name; | |
4929 | int alu_code; | |
4930 | int ldr_code; | |
4931 | int ldrs_code; | |
4932 | int ldc_code; | |
4933 | }; | |
4934 | ||
4935 | typedef enum | |
4936 | { | |
4937 | /* Varieties of non-ALU group relocation. */ | |
4938 | ||
4939 | GROUP_LDR, | |
4940 | GROUP_LDRS, | |
4941 | GROUP_LDC | |
4942 | } group_reloc_type; | |
4943 | ||
4944 | static struct group_reloc_table_entry group_reloc_table[] = | |
4945 | { /* Program counter relative: */ | |
4946 | { "pc_g0_nc", | |
4947 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4948 | 0, /* LDR */ | |
4949 | 0, /* LDRS */ | |
4950 | 0 }, /* LDC */ | |
4951 | { "pc_g0", | |
4952 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4953 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4954 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4955 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4956 | { "pc_g1_nc", | |
4957 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4958 | 0, /* LDR */ | |
4959 | 0, /* LDRS */ | |
4960 | 0 }, /* LDC */ | |
4961 | { "pc_g1", | |
4962 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4963 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4964 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4965 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4966 | { "pc_g2", | |
4967 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4968 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4969 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4970 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4971 | /* Section base relative */ | |
4972 | { "sb_g0_nc", | |
4973 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4974 | 0, /* LDR */ | |
4975 | 0, /* LDRS */ | |
4976 | 0 }, /* LDC */ | |
4977 | { "sb_g0", | |
4978 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4979 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4980 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4981 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4982 | { "sb_g1_nc", | |
4983 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4984 | 0, /* LDR */ | |
4985 | 0, /* LDRS */ | |
4986 | 0 }, /* LDC */ | |
4987 | { "sb_g1", | |
4988 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4989 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4990 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4991 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4992 | { "sb_g2", | |
4993 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4994 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4995 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4996 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4997 | ||
4998 | /* Given the address of a pointer pointing to the textual name of a group | |
4999 | relocation as may appear in assembler source, attempt to find its details | |
5000 | in group_reloc_table. The pointer will be updated to the character after | |
5001 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5002 | otherwise. On success, *entry will be updated to point at the relevant | |
5003 | group_reloc_table entry. */ | |
5004 | ||
5005 | static int | |
5006 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5007 | { | |
5008 | unsigned int i; | |
5009 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5010 | { | |
5011 | int length = strlen (group_reloc_table[i].name); | |
5012 | ||
5f4273c7 NC |
5013 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5014 | && (*str)[length] == ':') | |
4962c51a MS |
5015 | { |
5016 | *out = &group_reloc_table[i]; | |
5017 | *str += (length + 1); | |
5018 | return SUCCESS; | |
5019 | } | |
5020 | } | |
5021 | ||
5022 | return FAIL; | |
5023 | } | |
5024 | ||
5025 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5026 | (as for parse_shifter_operand) where group relocations are allowed: | |
5027 | ||
5028 | #<immediate> | |
5029 | #<immediate>, <rotate> | |
5030 | #:<group_reloc>:<expression> | |
5031 | <Rm> | |
5032 | <Rm>, <shift> | |
5033 | ||
5034 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5035 | The hashes are optional. | |
5036 | ||
5037 | Everything else is as for parse_shifter_operand. */ | |
5038 | ||
5039 | static parse_operand_result | |
5040 | parse_shifter_operand_group_reloc (char **str, int i) | |
5041 | { | |
5042 | /* Determine if we have the sequence of characters #: or just : | |
5043 | coming next. If we do, then we check for a group relocation. | |
5044 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5045 | ||
5046 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5047 | || (*str)[0] == ':') | |
5048 | { | |
5049 | struct group_reloc_table_entry *entry; | |
5050 | ||
5051 | if ((*str)[0] == '#') | |
5052 | (*str) += 2; | |
5053 | else | |
5054 | (*str)++; | |
5055 | ||
5056 | /* Try to parse a group relocation. Anything else is an error. */ | |
5057 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
5058 | { | |
5059 | inst.error = _("unknown group relocation"); | |
5060 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5061 | } | |
5062 | ||
5063 | /* We now have the group relocation table entry corresponding to | |
5064 | the name in the assembler source. Next, we parse the expression. */ | |
5065 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
5066 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5067 | ||
5068 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5069 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5070 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5071 | |
5072 | return PARSE_OPERAND_SUCCESS; | |
5073 | } | |
5074 | else | |
5075 | return parse_shifter_operand (str, i) == SUCCESS | |
5076 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
5077 | ||
5078 | /* Never reached. */ | |
5079 | } | |
5080 | ||
8e560766 MGD |
5081 | /* Parse a Neon alignment expression. Information is written to |
5082 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5083 | |
8e560766 MGD |
5084 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5085 | static parse_operand_result | |
5086 | parse_neon_alignment (char **str, int i) | |
5087 | { | |
5088 | char *p = *str; | |
5089 | expressionS exp; | |
5090 | ||
5091 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5092 | ||
5093 | if (exp.X_op != O_constant) | |
5094 | { | |
5095 | inst.error = _("alignment must be constant"); | |
5096 | return PARSE_OPERAND_FAIL; | |
5097 | } | |
5098 | ||
5099 | inst.operands[i].imm = exp.X_add_number << 8; | |
5100 | inst.operands[i].immisalign = 1; | |
5101 | /* Alignments are not pre-indexes. */ | |
5102 | inst.operands[i].preind = 0; | |
5103 | ||
5104 | *str = p; | |
5105 | return PARSE_OPERAND_SUCCESS; | |
5106 | } | |
5107 | ||
c19d1205 ZW |
5108 | /* Parse all forms of an ARM address expression. Information is written |
5109 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5110 | |
c19d1205 | 5111 | Preindexed addressing (.preind=1): |
09d92015 | 5112 | |
c19d1205 ZW |
5113 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5114 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5115 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5116 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5117 | |
c19d1205 | 5118 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5119 | |
c19d1205 | 5120 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5121 | |
c19d1205 ZW |
5122 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5123 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5124 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5125 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5126 | |
c19d1205 | 5127 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5128 | |
c19d1205 | 5129 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5130 | |
c19d1205 | 5131 | Other: |
09d92015 | 5132 | |
c19d1205 ZW |
5133 | [Rn]{!} shorthand for [Rn,#0]{!} |
5134 | =immediate .isreg=0 .reloc.exp=immediate | |
5135 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5136 | |
c19d1205 ZW |
5137 | It is the caller's responsibility to check for addressing modes not |
5138 | supported by the instruction, and to set inst.reloc.type. */ | |
5139 | ||
4962c51a MS |
5140 | static parse_operand_result |
5141 | parse_address_main (char **str, int i, int group_relocations, | |
5142 | group_reloc_type group_type) | |
09d92015 | 5143 | { |
c19d1205 ZW |
5144 | char *p = *str; |
5145 | int reg; | |
09d92015 | 5146 | |
c19d1205 | 5147 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5148 | { |
c19d1205 ZW |
5149 | if (skip_past_char (&p, '=') == FAIL) |
5150 | { | |
974da60d | 5151 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5152 | inst.reloc.pc_rel = 1; |
5153 | inst.operands[i].reg = REG_PC; | |
5154 | inst.operands[i].isreg = 1; | |
5155 | inst.operands[i].preind = 1; | |
5156 | } | |
974da60d | 5157 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5158 | |
c19d1205 | 5159 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5160 | return PARSE_OPERAND_FAIL; |
09d92015 | 5161 | |
c19d1205 | 5162 | *str = p; |
4962c51a | 5163 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5164 | } |
5165 | ||
dcbf9037 | 5166 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5167 | { |
c19d1205 | 5168 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5169 | return PARSE_OPERAND_FAIL; |
09d92015 | 5170 | } |
c19d1205 ZW |
5171 | inst.operands[i].reg = reg; |
5172 | inst.operands[i].isreg = 1; | |
09d92015 | 5173 | |
c19d1205 | 5174 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5175 | { |
c19d1205 | 5176 | inst.operands[i].preind = 1; |
09d92015 | 5177 | |
c19d1205 ZW |
5178 | if (*p == '+') p++; |
5179 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5180 | ||
dcbf9037 | 5181 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5182 | { |
c19d1205 ZW |
5183 | inst.operands[i].imm = reg; |
5184 | inst.operands[i].immisreg = 1; | |
5185 | ||
5186 | if (skip_past_comma (&p) == SUCCESS) | |
5187 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5188 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5189 | } |
5287ad62 | 5190 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5191 | { |
5192 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5193 | code before we get to see it here. This may be subject to | |
5194 | change. */ | |
5195 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5196 | |
8e560766 MGD |
5197 | if (result != PARSE_OPERAND_SUCCESS) |
5198 | return result; | |
5199 | } | |
c19d1205 ZW |
5200 | else |
5201 | { | |
5202 | if (inst.operands[i].negative) | |
5203 | { | |
5204 | inst.operands[i].negative = 0; | |
5205 | p--; | |
5206 | } | |
4962c51a | 5207 | |
5f4273c7 NC |
5208 | if (group_relocations |
5209 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5210 | { |
5211 | struct group_reloc_table_entry *entry; | |
5212 | ||
5213 | /* Skip over the #: or : sequence. */ | |
5214 | if (*p == '#') | |
5215 | p += 2; | |
5216 | else | |
5217 | p++; | |
5218 | ||
5219 | /* Try to parse a group relocation. Anything else is an | |
5220 | error. */ | |
5221 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5222 | { | |
5223 | inst.error = _("unknown group relocation"); | |
5224 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5225 | } | |
5226 | ||
5227 | /* We now have the group relocation table entry corresponding to | |
5228 | the name in the assembler source. Next, we parse the | |
5229 | expression. */ | |
5230 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5231 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5232 | ||
5233 | /* Record the relocation type. */ | |
5234 | switch (group_type) | |
5235 | { | |
5236 | case GROUP_LDR: | |
21d799b5 | 5237 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5238 | break; |
5239 | ||
5240 | case GROUP_LDRS: | |
21d799b5 | 5241 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5242 | break; |
5243 | ||
5244 | case GROUP_LDC: | |
21d799b5 | 5245 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5246 | break; |
5247 | ||
5248 | default: | |
9c2799c2 | 5249 | gas_assert (0); |
4962c51a MS |
5250 | } |
5251 | ||
5252 | if (inst.reloc.type == 0) | |
5253 | { | |
5254 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5255 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5256 | } | |
5257 | } | |
5258 | else | |
26d97720 NS |
5259 | { |
5260 | char *q = p; | |
5261 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5262 | return PARSE_OPERAND_FAIL; | |
5263 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5264 | if (inst.reloc.exp.X_op == O_constant | |
5265 | && inst.reloc.exp.X_add_number == 0) | |
5266 | { | |
5267 | skip_whitespace (q); | |
5268 | if (*q == '#') | |
5269 | { | |
5270 | q++; | |
5271 | skip_whitespace (q); | |
5272 | } | |
5273 | if (*q == '-') | |
5274 | inst.operands[i].negative = 1; | |
5275 | } | |
5276 | } | |
09d92015 MM |
5277 | } |
5278 | } | |
8e560766 MGD |
5279 | else if (skip_past_char (&p, ':') == SUCCESS) |
5280 | { | |
5281 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5282 | before we get to see it here. This may be subject to change. */ | |
5283 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5284 | |
8e560766 MGD |
5285 | if (result != PARSE_OPERAND_SUCCESS) |
5286 | return result; | |
5287 | } | |
09d92015 | 5288 | |
c19d1205 | 5289 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5290 | { |
c19d1205 | 5291 | inst.error = _("']' expected"); |
4962c51a | 5292 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5293 | } |
5294 | ||
c19d1205 ZW |
5295 | if (skip_past_char (&p, '!') == SUCCESS) |
5296 | inst.operands[i].writeback = 1; | |
09d92015 | 5297 | |
c19d1205 | 5298 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5299 | { |
c19d1205 ZW |
5300 | if (skip_past_char (&p, '{') == SUCCESS) |
5301 | { | |
5302 | /* [Rn], {expr} - unindexed, with option */ | |
5303 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5304 | 0, 255, TRUE) == FAIL) |
4962c51a | 5305 | return PARSE_OPERAND_FAIL; |
09d92015 | 5306 | |
c19d1205 ZW |
5307 | if (skip_past_char (&p, '}') == FAIL) |
5308 | { | |
5309 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5310 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5311 | } |
5312 | if (inst.operands[i].preind) | |
5313 | { | |
5314 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5315 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5316 | } |
5317 | *str = p; | |
4962c51a | 5318 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5319 | } |
c19d1205 ZW |
5320 | else |
5321 | { | |
5322 | inst.operands[i].postind = 1; | |
5323 | inst.operands[i].writeback = 1; | |
09d92015 | 5324 | |
c19d1205 ZW |
5325 | if (inst.operands[i].preind) |
5326 | { | |
5327 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5328 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5329 | } |
09d92015 | 5330 | |
c19d1205 ZW |
5331 | if (*p == '+') p++; |
5332 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5333 | |
dcbf9037 | 5334 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5335 | { |
5287ad62 JB |
5336 | /* We might be using the immediate for alignment already. If we |
5337 | are, OR the register number into the low-order bits. */ | |
5338 | if (inst.operands[i].immisalign) | |
5339 | inst.operands[i].imm |= reg; | |
5340 | else | |
5341 | inst.operands[i].imm = reg; | |
c19d1205 | 5342 | inst.operands[i].immisreg = 1; |
a737bd4d | 5343 | |
c19d1205 ZW |
5344 | if (skip_past_comma (&p) == SUCCESS) |
5345 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5346 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5347 | } |
5348 | else | |
5349 | { | |
26d97720 | 5350 | char *q = p; |
c19d1205 ZW |
5351 | if (inst.operands[i].negative) |
5352 | { | |
5353 | inst.operands[i].negative = 0; | |
5354 | p--; | |
5355 | } | |
5356 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5357 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5358 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5359 | if (inst.reloc.exp.X_op == O_constant | |
5360 | && inst.reloc.exp.X_add_number == 0) | |
5361 | { | |
5362 | skip_whitespace (q); | |
5363 | if (*q == '#') | |
5364 | { | |
5365 | q++; | |
5366 | skip_whitespace (q); | |
5367 | } | |
5368 | if (*q == '-') | |
5369 | inst.operands[i].negative = 1; | |
5370 | } | |
c19d1205 ZW |
5371 | } |
5372 | } | |
a737bd4d NC |
5373 | } |
5374 | ||
c19d1205 ZW |
5375 | /* If at this point neither .preind nor .postind is set, we have a |
5376 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5377 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5378 | { | |
5379 | inst.operands[i].preind = 1; | |
5380 | inst.reloc.exp.X_op = O_constant; | |
5381 | inst.reloc.exp.X_add_number = 0; | |
5382 | } | |
5383 | *str = p; | |
4962c51a MS |
5384 | return PARSE_OPERAND_SUCCESS; |
5385 | } | |
5386 | ||
5387 | static int | |
5388 | parse_address (char **str, int i) | |
5389 | { | |
21d799b5 | 5390 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5391 | ? SUCCESS : FAIL; |
5392 | } | |
5393 | ||
5394 | static parse_operand_result | |
5395 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5396 | { | |
5397 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5398 | } |
5399 | ||
b6895b4f PB |
5400 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5401 | static int | |
5402 | parse_half (char **str) | |
5403 | { | |
5404 | char * p; | |
5f4273c7 | 5405 | |
b6895b4f PB |
5406 | p = *str; |
5407 | skip_past_char (&p, '#'); | |
5f4273c7 | 5408 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5409 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5410 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5411 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5412 | ||
5413 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5414 | { | |
5415 | p += 9; | |
5f4273c7 | 5416 | skip_whitespace (p); |
b6895b4f PB |
5417 | } |
5418 | ||
5419 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5420 | return FAIL; | |
5421 | ||
5422 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5423 | { | |
5424 | if (inst.reloc.exp.X_op != O_constant) | |
5425 | { | |
5426 | inst.error = _("constant expression expected"); | |
5427 | return FAIL; | |
5428 | } | |
5429 | if (inst.reloc.exp.X_add_number < 0 | |
5430 | || inst.reloc.exp.X_add_number > 0xffff) | |
5431 | { | |
5432 | inst.error = _("immediate value out of range"); | |
5433 | return FAIL; | |
5434 | } | |
5435 | } | |
5436 | *str = p; | |
5437 | return SUCCESS; | |
5438 | } | |
5439 | ||
c19d1205 | 5440 | /* Miscellaneous. */ |
a737bd4d | 5441 | |
c19d1205 ZW |
5442 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5443 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5444 | static int | |
d2cd1205 | 5445 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5446 | { |
c19d1205 ZW |
5447 | char *p; |
5448 | unsigned long psr_field; | |
62b3e311 PB |
5449 | const struct asm_psr *psr; |
5450 | char *start; | |
d2cd1205 | 5451 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5452 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5453 | |
a4482bb6 NC |
5454 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5455 | be TRUE, but we want to ignore it in this case as we are building for any | |
5456 | CPU type, including non-m variants. */ | |
5457 | if (selected_cpu.core == arm_arch_any.core) | |
5458 | m_profile = FALSE; | |
5459 | ||
c19d1205 ZW |
5460 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5461 | feature for ease of use and backwards compatibility. */ | |
5462 | p = *str; | |
62b3e311 | 5463 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5464 | { |
5465 | if (m_profile) | |
5466 | goto unsupported_psr; | |
fa94de6b | 5467 | |
d2cd1205 JB |
5468 | psr_field = SPSR_BIT; |
5469 | } | |
5470 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5471 | { | |
5472 | if (m_profile) | |
5473 | goto unsupported_psr; | |
5474 | ||
5475 | psr_field = 0; | |
5476 | } | |
5477 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5478 | { | |
5479 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5480 | and ARMv7-R architecture CPUs. */ | |
5481 | is_apsr = TRUE; | |
5482 | psr_field = 0; | |
5483 | } | |
5484 | else if (m_profile) | |
62b3e311 PB |
5485 | { |
5486 | start = p; | |
5487 | do | |
5488 | p++; | |
5489 | while (ISALNUM (*p) || *p == '_'); | |
5490 | ||
d2cd1205 JB |
5491 | if (strncasecmp (start, "iapsr", 5) == 0 |
5492 | || strncasecmp (start, "eapsr", 5) == 0 | |
5493 | || strncasecmp (start, "xpsr", 4) == 0 | |
5494 | || strncasecmp (start, "psr", 3) == 0) | |
5495 | p = start + strcspn (start, "rR") + 1; | |
5496 | ||
21d799b5 NC |
5497 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5498 | p - start); | |
d2cd1205 | 5499 | |
62b3e311 PB |
5500 | if (!psr) |
5501 | return FAIL; | |
09d92015 | 5502 | |
d2cd1205 JB |
5503 | /* If APSR is being written, a bitfield may be specified. Note that |
5504 | APSR itself is handled above. */ | |
5505 | if (psr->field <= 3) | |
5506 | { | |
5507 | psr_field = psr->field; | |
5508 | is_apsr = TRUE; | |
5509 | goto check_suffix; | |
5510 | } | |
5511 | ||
62b3e311 | 5512 | *str = p; |
d2cd1205 JB |
5513 | /* M-profile MSR instructions have the mask field set to "10", except |
5514 | *PSR variants which modify APSR, which may use a different mask (and | |
5515 | have been handled already). Do that by setting the PSR_f field | |
5516 | here. */ | |
5517 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5518 | } |
d2cd1205 JB |
5519 | else |
5520 | goto unsupported_psr; | |
09d92015 | 5521 | |
62b3e311 | 5522 | p += 4; |
d2cd1205 | 5523 | check_suffix: |
c19d1205 ZW |
5524 | if (*p == '_') |
5525 | { | |
5526 | /* A suffix follows. */ | |
c19d1205 ZW |
5527 | p++; |
5528 | start = p; | |
a737bd4d | 5529 | |
c19d1205 ZW |
5530 | do |
5531 | p++; | |
5532 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5533 | |
d2cd1205 JB |
5534 | if (is_apsr) |
5535 | { | |
5536 | /* APSR uses a notation for bits, rather than fields. */ | |
5537 | unsigned int nzcvq_bits = 0; | |
5538 | unsigned int g_bit = 0; | |
5539 | char *bit; | |
fa94de6b | 5540 | |
d2cd1205 JB |
5541 | for (bit = start; bit != p; bit++) |
5542 | { | |
5543 | switch (TOLOWER (*bit)) | |
5544 | { | |
5545 | case 'n': | |
5546 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5547 | break; | |
5548 | ||
5549 | case 'z': | |
5550 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5551 | break; | |
5552 | ||
5553 | case 'c': | |
5554 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5555 | break; | |
5556 | ||
5557 | case 'v': | |
5558 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5559 | break; | |
fa94de6b | 5560 | |
d2cd1205 JB |
5561 | case 'q': |
5562 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5563 | break; | |
fa94de6b | 5564 | |
d2cd1205 JB |
5565 | case 'g': |
5566 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5567 | break; | |
fa94de6b | 5568 | |
d2cd1205 JB |
5569 | default: |
5570 | inst.error = _("unexpected bit specified after APSR"); | |
5571 | return FAIL; | |
5572 | } | |
5573 | } | |
fa94de6b | 5574 | |
d2cd1205 JB |
5575 | if (nzcvq_bits == 0x1f) |
5576 | psr_field |= PSR_f; | |
fa94de6b | 5577 | |
d2cd1205 JB |
5578 | if (g_bit == 0x1) |
5579 | { | |
5580 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
5581 | { | |
5582 | inst.error = _("selected processor does not " | |
5583 | "support DSP extension"); | |
5584 | return FAIL; | |
5585 | } | |
5586 | ||
5587 | psr_field |= PSR_s; | |
5588 | } | |
fa94de6b | 5589 | |
d2cd1205 JB |
5590 | if ((nzcvq_bits & 0x20) != 0 |
5591 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5592 | || (g_bit & 0x2) != 0) | |
5593 | { | |
5594 | inst.error = _("bad bitmask specified after APSR"); | |
5595 | return FAIL; | |
5596 | } | |
5597 | } | |
5598 | else | |
5599 | { | |
5600 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, | |
5601 | p - start); | |
5602 | if (!psr) | |
5603 | goto error; | |
a737bd4d | 5604 | |
d2cd1205 JB |
5605 | psr_field |= psr->field; |
5606 | } | |
a737bd4d | 5607 | } |
c19d1205 | 5608 | else |
a737bd4d | 5609 | { |
c19d1205 ZW |
5610 | if (ISALNUM (*p)) |
5611 | goto error; /* Garbage after "[CS]PSR". */ | |
5612 | ||
d2cd1205 JB |
5613 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
5614 | is deprecated, but allow it anyway. */ | |
5615 | if (is_apsr && lhs) | |
5616 | { | |
5617 | psr_field |= PSR_f; | |
5618 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5619 | "deprecated")); | |
5620 | } | |
5621 | else if (!m_profile) | |
5622 | /* These bits are never right for M-profile devices: don't set them | |
5623 | (only code paths which read/write APSR reach here). */ | |
5624 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5625 | } |
c19d1205 ZW |
5626 | *str = p; |
5627 | return psr_field; | |
a737bd4d | 5628 | |
d2cd1205 JB |
5629 | unsupported_psr: |
5630 | inst.error = _("selected processor does not support requested special " | |
5631 | "purpose register"); | |
5632 | return FAIL; | |
5633 | ||
c19d1205 ZW |
5634 | error: |
5635 | inst.error = _("flag for {c}psr instruction expected"); | |
5636 | return FAIL; | |
a737bd4d NC |
5637 | } |
5638 | ||
c19d1205 ZW |
5639 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5640 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5641 | |
c19d1205 ZW |
5642 | static int |
5643 | parse_cps_flags (char **str) | |
a737bd4d | 5644 | { |
c19d1205 ZW |
5645 | int val = 0; |
5646 | int saw_a_flag = 0; | |
5647 | char *s = *str; | |
a737bd4d | 5648 | |
c19d1205 ZW |
5649 | for (;;) |
5650 | switch (*s++) | |
5651 | { | |
5652 | case '\0': case ',': | |
5653 | goto done; | |
a737bd4d | 5654 | |
c19d1205 ZW |
5655 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5656 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5657 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5658 | |
c19d1205 ZW |
5659 | default: |
5660 | inst.error = _("unrecognized CPS flag"); | |
5661 | return FAIL; | |
5662 | } | |
a737bd4d | 5663 | |
c19d1205 ZW |
5664 | done: |
5665 | if (saw_a_flag == 0) | |
a737bd4d | 5666 | { |
c19d1205 ZW |
5667 | inst.error = _("missing CPS flags"); |
5668 | return FAIL; | |
a737bd4d | 5669 | } |
a737bd4d | 5670 | |
c19d1205 ZW |
5671 | *str = s - 1; |
5672 | return val; | |
a737bd4d NC |
5673 | } |
5674 | ||
c19d1205 ZW |
5675 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5676 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5677 | |
5678 | static int | |
c19d1205 | 5679 | parse_endian_specifier (char **str) |
a737bd4d | 5680 | { |
c19d1205 ZW |
5681 | int little_endian; |
5682 | char *s = *str; | |
a737bd4d | 5683 | |
c19d1205 ZW |
5684 | if (strncasecmp (s, "BE", 2)) |
5685 | little_endian = 0; | |
5686 | else if (strncasecmp (s, "LE", 2)) | |
5687 | little_endian = 1; | |
5688 | else | |
a737bd4d | 5689 | { |
c19d1205 | 5690 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5691 | return FAIL; |
5692 | } | |
5693 | ||
c19d1205 | 5694 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5695 | { |
c19d1205 | 5696 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5697 | return FAIL; |
5698 | } | |
5699 | ||
c19d1205 ZW |
5700 | *str = s + 2; |
5701 | return little_endian; | |
5702 | } | |
a737bd4d | 5703 | |
c19d1205 ZW |
5704 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5705 | value suitable for poking into the rotate field of an sxt or sxta | |
5706 | instruction, or FAIL on error. */ | |
5707 | ||
5708 | static int | |
5709 | parse_ror (char **str) | |
5710 | { | |
5711 | int rot; | |
5712 | char *s = *str; | |
5713 | ||
5714 | if (strncasecmp (s, "ROR", 3) == 0) | |
5715 | s += 3; | |
5716 | else | |
a737bd4d | 5717 | { |
c19d1205 | 5718 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5719 | return FAIL; |
5720 | } | |
c19d1205 ZW |
5721 | |
5722 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5723 | return FAIL; | |
5724 | ||
5725 | switch (rot) | |
a737bd4d | 5726 | { |
c19d1205 ZW |
5727 | case 0: *str = s; return 0x0; |
5728 | case 8: *str = s; return 0x1; | |
5729 | case 16: *str = s; return 0x2; | |
5730 | case 24: *str = s; return 0x3; | |
5731 | ||
5732 | default: | |
5733 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5734 | return FAIL; |
5735 | } | |
c19d1205 | 5736 | } |
a737bd4d | 5737 | |
c19d1205 ZW |
5738 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5739 | range 0 .. 14, or FAIL. */ | |
5740 | static int | |
5741 | parse_cond (char **str) | |
5742 | { | |
c462b453 | 5743 | char *q; |
c19d1205 | 5744 | const struct asm_cond *c; |
c462b453 PB |
5745 | int n; |
5746 | /* Condition codes are always 2 characters, so matching up to | |
5747 | 3 characters is sufficient. */ | |
5748 | char cond[3]; | |
a737bd4d | 5749 | |
c462b453 PB |
5750 | q = *str; |
5751 | n = 0; | |
5752 | while (ISALPHA (*q) && n < 3) | |
5753 | { | |
e07e6e58 | 5754 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5755 | q++; |
5756 | n++; | |
5757 | } | |
a737bd4d | 5758 | |
21d799b5 | 5759 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5760 | if (!c) |
a737bd4d | 5761 | { |
c19d1205 | 5762 | inst.error = _("condition required"); |
a737bd4d NC |
5763 | return FAIL; |
5764 | } | |
5765 | ||
c19d1205 ZW |
5766 | *str = q; |
5767 | return c->value; | |
5768 | } | |
5769 | ||
e797f7e0 MGD |
5770 | /* If the given feature available in the selected CPU, mark it as used. |
5771 | Returns TRUE iff feature is available. */ | |
5772 | static bfd_boolean | |
5773 | mark_feature_used (const arm_feature_set *feature) | |
5774 | { | |
5775 | /* Ensure the option is valid on the current architecture. */ | |
5776 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
5777 | return FALSE; | |
5778 | ||
5779 | /* Add the appropriate architecture feature for the barrier option used. | |
5780 | */ | |
5781 | if (thumb_mode) | |
5782 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
5783 | else | |
5784 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
5785 | ||
5786 | return TRUE; | |
5787 | } | |
5788 | ||
62b3e311 PB |
5789 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5790 | option, or FAIL. */ | |
5791 | static int | |
5792 | parse_barrier (char **str) | |
5793 | { | |
5794 | char *p, *q; | |
5795 | const struct asm_barrier_opt *o; | |
5796 | ||
5797 | p = q = *str; | |
5798 | while (ISALPHA (*q)) | |
5799 | q++; | |
5800 | ||
21d799b5 NC |
5801 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5802 | q - p); | |
62b3e311 PB |
5803 | if (!o) |
5804 | return FAIL; | |
5805 | ||
e797f7e0 MGD |
5806 | if (!mark_feature_used (&o->arch)) |
5807 | return FAIL; | |
5808 | ||
62b3e311 PB |
5809 | *str = q; |
5810 | return o->value; | |
5811 | } | |
5812 | ||
92e90b6e PB |
5813 | /* Parse the operands of a table branch instruction. Similar to a memory |
5814 | operand. */ | |
5815 | static int | |
5816 | parse_tb (char **str) | |
5817 | { | |
5818 | char * p = *str; | |
5819 | int reg; | |
5820 | ||
5821 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5822 | { |
5823 | inst.error = _("'[' expected"); | |
5824 | return FAIL; | |
5825 | } | |
92e90b6e | 5826 | |
dcbf9037 | 5827 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5828 | { |
5829 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5830 | return FAIL; | |
5831 | } | |
5832 | inst.operands[0].reg = reg; | |
5833 | ||
5834 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5835 | { |
5836 | inst.error = _("',' expected"); | |
5837 | return FAIL; | |
5838 | } | |
5f4273c7 | 5839 | |
dcbf9037 | 5840 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5841 | { |
5842 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5843 | return FAIL; | |
5844 | } | |
5845 | inst.operands[0].imm = reg; | |
5846 | ||
5847 | if (skip_past_comma (&p) == SUCCESS) | |
5848 | { | |
5849 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5850 | return FAIL; | |
5851 | if (inst.reloc.exp.X_add_number != 1) | |
5852 | { | |
5853 | inst.error = _("invalid shift"); | |
5854 | return FAIL; | |
5855 | } | |
5856 | inst.operands[0].shifted = 1; | |
5857 | } | |
5858 | ||
5859 | if (skip_past_char (&p, ']') == FAIL) | |
5860 | { | |
5861 | inst.error = _("']' expected"); | |
5862 | return FAIL; | |
5863 | } | |
5864 | *str = p; | |
5865 | return SUCCESS; | |
5866 | } | |
5867 | ||
5287ad62 JB |
5868 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5869 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5870 | Up to four operands may be read; this function handles setting the |
5871 | ".present" field for each read operand itself. | |
5287ad62 JB |
5872 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5873 | else returns FAIL. */ | |
5874 | ||
5875 | static int | |
5876 | parse_neon_mov (char **str, int *which_operand) | |
5877 | { | |
5878 | int i = *which_operand, val; | |
5879 | enum arm_reg_type rtype; | |
5880 | char *ptr = *str; | |
dcbf9037 | 5881 | struct neon_type_el optype; |
5f4273c7 | 5882 | |
dcbf9037 | 5883 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5884 | { |
5885 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5886 | inst.operands[i].reg = val; | |
5887 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5888 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5889 | inst.operands[i++].present = 1; |
5890 | ||
5891 | if (skip_past_comma (&ptr) == FAIL) | |
5892 | goto wanted_comma; | |
5f4273c7 | 5893 | |
dcbf9037 | 5894 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5895 | goto wanted_arm; |
5f4273c7 | 5896 | |
5287ad62 JB |
5897 | inst.operands[i].reg = val; |
5898 | inst.operands[i].isreg = 1; | |
5899 | inst.operands[i].present = 1; | |
5900 | } | |
037e8744 | 5901 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5902 | != FAIL) |
5287ad62 JB |
5903 | { |
5904 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5905 | if (skip_past_comma (&ptr) == FAIL) | |
5906 | goto wanted_comma; | |
5f4273c7 | 5907 | |
5287ad62 JB |
5908 | inst.operands[i].reg = val; |
5909 | inst.operands[i].isreg = 1; | |
5910 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5911 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5912 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5913 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5914 | inst.operands[i++].present = 1; |
5915 | ||
dcbf9037 | 5916 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5917 | { |
037e8744 JB |
5918 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5919 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5920 | inst.operands[i].reg = val; |
5921 | inst.operands[i].isreg = 1; | |
037e8744 | 5922 | inst.operands[i].present = 1; |
5287ad62 JB |
5923 | |
5924 | if (rtype == REG_TYPE_NQ) | |
5925 | { | |
dcbf9037 | 5926 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5927 | return FAIL; |
5928 | } | |
037e8744 JB |
5929 | else if (rtype != REG_TYPE_VFS) |
5930 | { | |
5931 | i++; | |
5932 | if (skip_past_comma (&ptr) == FAIL) | |
5933 | goto wanted_comma; | |
5934 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5935 | goto wanted_arm; | |
5936 | inst.operands[i].reg = val; | |
5937 | inst.operands[i].isreg = 1; | |
5938 | inst.operands[i].present = 1; | |
5939 | } | |
5287ad62 | 5940 | } |
037e8744 JB |
5941 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5942 | &optype)) != FAIL) | |
5287ad62 JB |
5943 | { |
5944 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5945 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5946 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5947 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5948 | |
5949 | inst.operands[i].reg = val; | |
5950 | inst.operands[i].isreg = 1; | |
5951 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5952 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5953 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5954 | inst.operands[i].vectype = optype; |
5287ad62 | 5955 | inst.operands[i].present = 1; |
5f4273c7 | 5956 | |
037e8744 JB |
5957 | if (skip_past_comma (&ptr) == SUCCESS) |
5958 | { | |
5959 | /* Case 15. */ | |
5960 | i++; | |
5961 | ||
5962 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5963 | goto wanted_arm; | |
5964 | ||
5965 | inst.operands[i].reg = val; | |
5966 | inst.operands[i].isreg = 1; | |
5967 | inst.operands[i++].present = 1; | |
5f4273c7 | 5968 | |
037e8744 JB |
5969 | if (skip_past_comma (&ptr) == FAIL) |
5970 | goto wanted_comma; | |
5f4273c7 | 5971 | |
037e8744 JB |
5972 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5973 | goto wanted_arm; | |
5f4273c7 | 5974 | |
037e8744 JB |
5975 | inst.operands[i].reg = val; |
5976 | inst.operands[i].isreg = 1; | |
1b11b49f | 5977 | inst.operands[i].present = 1; |
037e8744 | 5978 | } |
5287ad62 | 5979 | } |
4641781c PB |
5980 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5981 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5982 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5983 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5984 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5985 | inst.operands[i].immisfloat = 1; | |
5986 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5987 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5988 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5989 | ; | |
5287ad62 JB |
5990 | else |
5991 | { | |
dcbf9037 | 5992 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5993 | return FAIL; |
5994 | } | |
5995 | } | |
dcbf9037 | 5996 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5997 | { |
5998 | /* Cases 6, 7. */ | |
5999 | inst.operands[i].reg = val; | |
6000 | inst.operands[i].isreg = 1; | |
6001 | inst.operands[i++].present = 1; | |
5f4273c7 | 6002 | |
5287ad62 JB |
6003 | if (skip_past_comma (&ptr) == FAIL) |
6004 | goto wanted_comma; | |
5f4273c7 | 6005 | |
dcbf9037 | 6006 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
6007 | { |
6008 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6009 | inst.operands[i].reg = val; | |
6010 | inst.operands[i].isscalar = 1; | |
6011 | inst.operands[i].present = 1; | |
dcbf9037 | 6012 | inst.operands[i].vectype = optype; |
5287ad62 | 6013 | } |
dcbf9037 | 6014 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
6015 | { |
6016 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
6017 | inst.operands[i].reg = val; | |
6018 | inst.operands[i].isreg = 1; | |
6019 | inst.operands[i++].present = 1; | |
5f4273c7 | 6020 | |
5287ad62 JB |
6021 | if (skip_past_comma (&ptr) == FAIL) |
6022 | goto wanted_comma; | |
5f4273c7 | 6023 | |
037e8744 | 6024 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 6025 | == FAIL) |
5287ad62 | 6026 | { |
037e8744 | 6027 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
6028 | return FAIL; |
6029 | } | |
6030 | ||
6031 | inst.operands[i].reg = val; | |
6032 | inst.operands[i].isreg = 1; | |
037e8744 JB |
6033 | inst.operands[i].isvec = 1; |
6034 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 6035 | inst.operands[i].vectype = optype; |
5287ad62 | 6036 | inst.operands[i].present = 1; |
5f4273c7 | 6037 | |
037e8744 JB |
6038 | if (rtype == REG_TYPE_VFS) |
6039 | { | |
6040 | /* Case 14. */ | |
6041 | i++; | |
6042 | if (skip_past_comma (&ptr) == FAIL) | |
6043 | goto wanted_comma; | |
6044 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6045 | &optype)) == FAIL) | |
6046 | { | |
6047 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6048 | return FAIL; | |
6049 | } | |
6050 | inst.operands[i].reg = val; | |
6051 | inst.operands[i].isreg = 1; | |
6052 | inst.operands[i].isvec = 1; | |
6053 | inst.operands[i].issingle = 1; | |
6054 | inst.operands[i].vectype = optype; | |
6055 | inst.operands[i].present = 1; | |
6056 | } | |
6057 | } | |
6058 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
6059 | != FAIL) | |
6060 | { | |
6061 | /* Case 13. */ | |
6062 | inst.operands[i].reg = val; | |
6063 | inst.operands[i].isreg = 1; | |
6064 | inst.operands[i].isvec = 1; | |
6065 | inst.operands[i].issingle = 1; | |
6066 | inst.operands[i].vectype = optype; | |
1b11b49f | 6067 | inst.operands[i].present = 1; |
5287ad62 JB |
6068 | } |
6069 | } | |
6070 | else | |
6071 | { | |
dcbf9037 | 6072 | first_error (_("parse error")); |
5287ad62 JB |
6073 | return FAIL; |
6074 | } | |
6075 | ||
6076 | /* Successfully parsed the operands. Update args. */ | |
6077 | *which_operand = i; | |
6078 | *str = ptr; | |
6079 | return SUCCESS; | |
6080 | ||
5f4273c7 | 6081 | wanted_comma: |
dcbf9037 | 6082 | first_error (_("expected comma")); |
5287ad62 | 6083 | return FAIL; |
5f4273c7 NC |
6084 | |
6085 | wanted_arm: | |
dcbf9037 | 6086 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6087 | return FAIL; |
5287ad62 JB |
6088 | } |
6089 | ||
5be8be5d DG |
6090 | /* Use this macro when the operand constraints are different |
6091 | for ARM and THUMB (e.g. ldrd). */ | |
6092 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6093 | ((arm_operand) | ((thumb_operand) << 16)) | |
6094 | ||
c19d1205 ZW |
6095 | /* Matcher codes for parse_operands. */ |
6096 | enum operand_parse_code | |
6097 | { | |
6098 | OP_stop, /* end of line */ | |
6099 | ||
6100 | OP_RR, /* ARM register */ | |
6101 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6102 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6103 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6104 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6105 | optional trailing ! */ |
c19d1205 ZW |
6106 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6107 | OP_RCP, /* Coprocessor number */ | |
6108 | OP_RCN, /* Coprocessor register */ | |
6109 | OP_RF, /* FPA register */ | |
6110 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6111 | OP_RVD, /* VFP double precision register (0..15) */ |
6112 | OP_RND, /* Neon double precision register (0..31) */ | |
6113 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6114 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6115 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6116 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6117 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6118 | OP_RVC, /* VFP control register */ |
6119 | OP_RMF, /* Maverick F register */ | |
6120 | OP_RMD, /* Maverick D register */ | |
6121 | OP_RMFX, /* Maverick FX register */ | |
6122 | OP_RMDX, /* Maverick DX register */ | |
6123 | OP_RMAX, /* Maverick AX register */ | |
6124 | OP_RMDS, /* Maverick DSPSC register */ | |
6125 | OP_RIWR, /* iWMMXt wR register */ | |
6126 | OP_RIWC, /* iWMMXt wC register */ | |
6127 | OP_RIWG, /* iWMMXt wCG register */ | |
6128 | OP_RXA, /* XScale accumulator register */ | |
6129 | ||
6130 | OP_REGLST, /* ARM register list */ | |
6131 | OP_VRSLST, /* VFP single-precision register list */ | |
6132 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6133 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6134 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6135 | OP_NSTRLST, /* Neon element/structure list */ | |
6136 | ||
5287ad62 | 6137 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6138 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 6139 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6140 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6141 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6142 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6143 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6144 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6145 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6146 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6147 | |
6148 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6149 | OP_I7, /* immediate value 0 .. 7 */ |
6150 | OP_I15, /* 0 .. 15 */ | |
6151 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6152 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6153 | OP_I31, /* 0 .. 31 */ |
6154 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6155 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6156 | OP_I32z, /* 0 .. 32 */ |
6157 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6158 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6159 | OP_I64, /* 1 .. 64 */ |
6160 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6161 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6162 | |
6163 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6164 | OP_I7b, /* 0 .. 7 */ | |
6165 | OP_I15b, /* 0 .. 15 */ | |
6166 | OP_I31b, /* 0 .. 31 */ | |
6167 | ||
6168 | OP_SH, /* shifter operand */ | |
4962c51a | 6169 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6170 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6171 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6172 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6173 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6174 | OP_EXP, /* arbitrary expression */ |
6175 | OP_EXPi, /* same, with optional immediate prefix */ | |
6176 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6177 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6178 | |
6179 | OP_CPSF, /* CPS flags */ | |
6180 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6181 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6182 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6183 | OP_COND, /* conditional code */ |
92e90b6e | 6184 | OP_TB, /* Table branch. */ |
c19d1205 | 6185 | |
037e8744 JB |
6186 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6187 | ||
c19d1205 ZW |
6188 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6189 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6190 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6191 | OP_RF_IF, /* FPA register or immediate */ | |
6192 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6193 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6194 | |
6195 | /* Optional operands. */ | |
6196 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6197 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6198 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6199 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6200 | OP_oIffffb, /* 0 .. 65535 */ |
6201 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6202 | ||
6203 | OP_oRR, /* ARM register */ | |
6204 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6205 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6206 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6207 | OP_oRND, /* Optional Neon double precision register */ |
6208 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6209 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6210 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6211 | OP_oSHll, /* LSL immediate */ |
6212 | OP_oSHar, /* ASR immediate */ | |
6213 | OP_oSHllar, /* LSL or ASR immediate */ | |
6214 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6215 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6216 | |
5be8be5d DG |
6217 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6218 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6219 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6220 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6221 | ||
c19d1205 ZW |
6222 | OP_FIRST_OPTIONAL = OP_oI7b |
6223 | }; | |
a737bd4d | 6224 | |
c19d1205 ZW |
6225 | /* Generic instruction operand parser. This does no encoding and no |
6226 | semantic validation; it merely squirrels values away in the inst | |
6227 | structure. Returns SUCCESS or FAIL depending on whether the | |
6228 | specified grammar matched. */ | |
6229 | static int | |
5be8be5d | 6230 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6231 | { |
5be8be5d | 6232 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6233 | char *backtrack_pos = 0; |
6234 | const char *backtrack_error = 0; | |
99aad254 | 6235 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6236 | enum arm_reg_type rtype; |
4962c51a | 6237 | parse_operand_result result; |
5be8be5d | 6238 | unsigned int op_parse_code; |
c19d1205 | 6239 | |
e07e6e58 NC |
6240 | #define po_char_or_fail(chr) \ |
6241 | do \ | |
6242 | { \ | |
6243 | if (skip_past_char (&str, chr) == FAIL) \ | |
6244 | goto bad_args; \ | |
6245 | } \ | |
6246 | while (0) | |
c19d1205 | 6247 | |
e07e6e58 NC |
6248 | #define po_reg_or_fail(regtype) \ |
6249 | do \ | |
dcbf9037 | 6250 | { \ |
e07e6e58 NC |
6251 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
6252 | & inst.operands[i].vectype); \ | |
6253 | if (val == FAIL) \ | |
6254 | { \ | |
6255 | first_error (_(reg_expected_msgs[regtype])); \ | |
6256 | goto failure; \ | |
6257 | } \ | |
6258 | inst.operands[i].reg = val; \ | |
6259 | inst.operands[i].isreg = 1; \ | |
6260 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6261 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6262 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6263 | || rtype == REG_TYPE_VFD \ | |
6264 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6265 | } \ |
e07e6e58 NC |
6266 | while (0) |
6267 | ||
6268 | #define po_reg_or_goto(regtype, label) \ | |
6269 | do \ | |
6270 | { \ | |
6271 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6272 | & inst.operands[i].vectype); \ | |
6273 | if (val == FAIL) \ | |
6274 | goto label; \ | |
dcbf9037 | 6275 | \ |
e07e6e58 NC |
6276 | inst.operands[i].reg = val; \ |
6277 | inst.operands[i].isreg = 1; \ | |
6278 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6279 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6280 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6281 | || rtype == REG_TYPE_VFD \ | |
6282 | || rtype == REG_TYPE_NQ); \ | |
6283 | } \ | |
6284 | while (0) | |
6285 | ||
6286 | #define po_imm_or_fail(min, max, popt) \ | |
6287 | do \ | |
6288 | { \ | |
6289 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6290 | goto failure; \ | |
6291 | inst.operands[i].imm = val; \ | |
6292 | } \ | |
6293 | while (0) | |
6294 | ||
6295 | #define po_scalar_or_goto(elsz, label) \ | |
6296 | do \ | |
6297 | { \ | |
6298 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6299 | if (val == FAIL) \ | |
6300 | goto label; \ | |
6301 | inst.operands[i].reg = val; \ | |
6302 | inst.operands[i].isscalar = 1; \ | |
6303 | } \ | |
6304 | while (0) | |
6305 | ||
6306 | #define po_misc_or_fail(expr) \ | |
6307 | do \ | |
6308 | { \ | |
6309 | if (expr) \ | |
6310 | goto failure; \ | |
6311 | } \ | |
6312 | while (0) | |
6313 | ||
6314 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6315 | do \ | |
6316 | { \ | |
6317 | result = expr; \ | |
6318 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6319 | backtrack_pos = 0; \ | |
6320 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6321 | goto failure; \ | |
6322 | } \ | |
6323 | while (0) | |
4962c51a | 6324 | |
52e7f43d RE |
6325 | #define po_barrier_or_imm(str) \ |
6326 | do \ | |
6327 | { \ | |
6328 | val = parse_barrier (&str); \ | |
6329 | if (val == FAIL) \ | |
6330 | { \ | |
6331 | if (ISALPHA (*str)) \ | |
6332 | goto failure; \ | |
6333 | else \ | |
6334 | goto immediate; \ | |
6335 | } \ | |
6336 | else \ | |
6337 | { \ | |
6338 | if ((inst.instruction & 0xf0) == 0x60 \ | |
6339 | && val != 0xf) \ | |
6340 | { \ | |
6341 | /* ISB can only take SY as an option. */ \ | |
6342 | inst.error = _("invalid barrier type"); \ | |
6343 | goto failure; \ | |
6344 | } \ | |
6345 | } \ | |
6346 | } \ | |
6347 | while (0) | |
6348 | ||
c19d1205 ZW |
6349 | skip_whitespace (str); |
6350 | ||
6351 | for (i = 0; upat[i] != OP_stop; i++) | |
6352 | { | |
5be8be5d DG |
6353 | op_parse_code = upat[i]; |
6354 | if (op_parse_code >= 1<<16) | |
6355 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6356 | : (op_parse_code & ((1<<16)-1)); | |
6357 | ||
6358 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6359 | { |
6360 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6361 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6362 | backtrack_pos = str; |
6363 | backtrack_error = inst.error; | |
6364 | backtrack_index = i; | |
6365 | } | |
6366 | ||
b6702015 | 6367 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6368 | po_char_or_fail (','); |
6369 | ||
5be8be5d | 6370 | switch (op_parse_code) |
c19d1205 ZW |
6371 | { |
6372 | /* Registers */ | |
6373 | case OP_oRRnpc: | |
5be8be5d | 6374 | case OP_oRRnpcsp: |
c19d1205 | 6375 | case OP_RRnpc: |
5be8be5d | 6376 | case OP_RRnpcsp: |
c19d1205 ZW |
6377 | case OP_oRR: |
6378 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6379 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6380 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6381 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6382 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6383 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6384 | case OP_oRND: |
6385 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6386 | case OP_RVC: |
6387 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6388 | break; | |
6389 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6390 | coproc_reg: | |
6391 | po_reg_or_fail (REG_TYPE_CN); | |
6392 | break; | |
c19d1205 ZW |
6393 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6394 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6395 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6396 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6397 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6398 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6399 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6400 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6401 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6402 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6403 | case OP_oRNQ: |
6404 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6405 | case OP_oRNDQ: | |
6406 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6407 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6408 | case OP_oRNSDQ: | |
6409 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6410 | |
6411 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6412 | scalars are accepted here, so deal with those in later code. */ | |
6413 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6414 | ||
5287ad62 JB |
6415 | case OP_RNDQ_I0: |
6416 | { | |
6417 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6418 | break; | |
6419 | try_imm0: | |
6420 | po_imm_or_fail (0, 0, TRUE); | |
6421 | } | |
6422 | break; | |
6423 | ||
037e8744 JB |
6424 | case OP_RVSD_I0: |
6425 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6426 | break; | |
6427 | ||
5287ad62 JB |
6428 | case OP_RR_RNSC: |
6429 | { | |
6430 | po_scalar_or_goto (8, try_rr); | |
6431 | break; | |
6432 | try_rr: | |
6433 | po_reg_or_fail (REG_TYPE_RN); | |
6434 | } | |
6435 | break; | |
6436 | ||
037e8744 JB |
6437 | case OP_RNSDQ_RNSC: |
6438 | { | |
6439 | po_scalar_or_goto (8, try_nsdq); | |
6440 | break; | |
6441 | try_nsdq: | |
6442 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6443 | } | |
6444 | break; | |
6445 | ||
5287ad62 JB |
6446 | case OP_RNDQ_RNSC: |
6447 | { | |
6448 | po_scalar_or_goto (8, try_ndq); | |
6449 | break; | |
6450 | try_ndq: | |
6451 | po_reg_or_fail (REG_TYPE_NDQ); | |
6452 | } | |
6453 | break; | |
6454 | ||
6455 | case OP_RND_RNSC: | |
6456 | { | |
6457 | po_scalar_or_goto (8, try_vfd); | |
6458 | break; | |
6459 | try_vfd: | |
6460 | po_reg_or_fail (REG_TYPE_VFD); | |
6461 | } | |
6462 | break; | |
6463 | ||
6464 | case OP_VMOV: | |
6465 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6466 | not careful then bad things might happen. */ | |
6467 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6468 | break; | |
6469 | ||
4316f0d2 | 6470 | case OP_RNDQ_Ibig: |
5287ad62 | 6471 | { |
4316f0d2 | 6472 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6473 | break; |
4316f0d2 | 6474 | try_immbig: |
5287ad62 JB |
6475 | /* There's a possibility of getting a 64-bit immediate here, so |
6476 | we need special handling. */ | |
6477 | if (parse_big_immediate (&str, i) == FAIL) | |
6478 | { | |
6479 | inst.error = _("immediate value is out of range"); | |
6480 | goto failure; | |
6481 | } | |
6482 | } | |
6483 | break; | |
6484 | ||
6485 | case OP_RNDQ_I63b: | |
6486 | { | |
6487 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6488 | break; | |
6489 | try_shimm: | |
6490 | po_imm_or_fail (0, 63, TRUE); | |
6491 | } | |
6492 | break; | |
c19d1205 ZW |
6493 | |
6494 | case OP_RRnpcb: | |
6495 | po_char_or_fail ('['); | |
6496 | po_reg_or_fail (REG_TYPE_RN); | |
6497 | po_char_or_fail (']'); | |
6498 | break; | |
a737bd4d | 6499 | |
55881a11 | 6500 | case OP_RRnpctw: |
c19d1205 | 6501 | case OP_RRw: |
b6702015 | 6502 | case OP_oRRw: |
c19d1205 ZW |
6503 | po_reg_or_fail (REG_TYPE_RN); |
6504 | if (skip_past_char (&str, '!') == SUCCESS) | |
6505 | inst.operands[i].writeback = 1; | |
6506 | break; | |
6507 | ||
6508 | /* Immediates */ | |
6509 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6510 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6511 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6512 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6513 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6514 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6515 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6516 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6517 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6518 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6519 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6520 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6521 | |
6522 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6523 | case OP_oI7b: | |
6524 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6525 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6526 | case OP_oI31b: | |
6527 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6528 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
5f1af56b | 6529 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; |
c19d1205 ZW |
6530 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6531 | ||
6532 | /* Immediate variants */ | |
6533 | case OP_oI255c: | |
6534 | po_char_or_fail ('{'); | |
6535 | po_imm_or_fail (0, 255, TRUE); | |
6536 | po_char_or_fail ('}'); | |
6537 | break; | |
6538 | ||
6539 | case OP_I31w: | |
6540 | /* The expression parser chokes on a trailing !, so we have | |
6541 | to find it first and zap it. */ | |
6542 | { | |
6543 | char *s = str; | |
6544 | while (*s && *s != ',') | |
6545 | s++; | |
6546 | if (s[-1] == '!') | |
6547 | { | |
6548 | s[-1] = '\0'; | |
6549 | inst.operands[i].writeback = 1; | |
6550 | } | |
6551 | po_imm_or_fail (0, 31, TRUE); | |
6552 | if (str == s - 1) | |
6553 | str = s; | |
6554 | } | |
6555 | break; | |
6556 | ||
6557 | /* Expressions */ | |
6558 | case OP_EXPi: EXPi: | |
6559 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6560 | GE_OPT_PREFIX)); | |
6561 | break; | |
6562 | ||
6563 | case OP_EXP: | |
6564 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6565 | GE_NO_PREFIX)); | |
6566 | break; | |
6567 | ||
6568 | case OP_EXPr: EXPr: | |
6569 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6570 | GE_NO_PREFIX)); | |
6571 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6572 | { |
c19d1205 ZW |
6573 | val = parse_reloc (&str); |
6574 | if (val == -1) | |
6575 | { | |
6576 | inst.error = _("unrecognized relocation suffix"); | |
6577 | goto failure; | |
6578 | } | |
6579 | else if (val != BFD_RELOC_UNUSED) | |
6580 | { | |
6581 | inst.operands[i].imm = val; | |
6582 | inst.operands[i].hasreloc = 1; | |
6583 | } | |
a737bd4d | 6584 | } |
c19d1205 | 6585 | break; |
a737bd4d | 6586 | |
b6895b4f PB |
6587 | /* Operand for MOVW or MOVT. */ |
6588 | case OP_HALF: | |
6589 | po_misc_or_fail (parse_half (&str)); | |
6590 | break; | |
6591 | ||
e07e6e58 | 6592 | /* Register or expression. */ |
c19d1205 ZW |
6593 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6594 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6595 | |
e07e6e58 | 6596 | /* Register or immediate. */ |
c19d1205 ZW |
6597 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6598 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6599 | |
c19d1205 ZW |
6600 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6601 | IF: | |
6602 | if (!is_immediate_prefix (*str)) | |
6603 | goto bad_args; | |
6604 | str++; | |
6605 | val = parse_fpa_immediate (&str); | |
6606 | if (val == FAIL) | |
6607 | goto failure; | |
6608 | /* FPA immediates are encoded as registers 8-15. | |
6609 | parse_fpa_immediate has already applied the offset. */ | |
6610 | inst.operands[i].reg = val; | |
6611 | inst.operands[i].isreg = 1; | |
6612 | break; | |
09d92015 | 6613 | |
2d447fca JM |
6614 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6615 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6616 | ||
e07e6e58 | 6617 | /* Two kinds of register. */ |
c19d1205 ZW |
6618 | case OP_RIWR_RIWC: |
6619 | { | |
6620 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6621 | if (!rege |
6622 | || (rege->type != REG_TYPE_MMXWR | |
6623 | && rege->type != REG_TYPE_MMXWC | |
6624 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6625 | { |
6626 | inst.error = _("iWMMXt data or control register expected"); | |
6627 | goto failure; | |
6628 | } | |
6629 | inst.operands[i].reg = rege->number; | |
6630 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6631 | } | |
6632 | break; | |
09d92015 | 6633 | |
41adaa5c JM |
6634 | case OP_RIWC_RIWG: |
6635 | { | |
6636 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6637 | if (!rege | |
6638 | || (rege->type != REG_TYPE_MMXWC | |
6639 | && rege->type != REG_TYPE_MMXWCG)) | |
6640 | { | |
6641 | inst.error = _("iWMMXt control register expected"); | |
6642 | goto failure; | |
6643 | } | |
6644 | inst.operands[i].reg = rege->number; | |
6645 | inst.operands[i].isreg = 1; | |
6646 | } | |
6647 | break; | |
6648 | ||
c19d1205 ZW |
6649 | /* Misc */ |
6650 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6651 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6652 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6653 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6654 | case OP_oBARRIER_I15: |
6655 | po_barrier_or_imm (str); break; | |
6656 | immediate: | |
6657 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
6658 | goto failure; | |
6659 | break; | |
c19d1205 | 6660 | |
fa94de6b | 6661 | case OP_wPSR: |
d2cd1205 | 6662 | case OP_rPSR: |
90ec0d68 MGD |
6663 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6664 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6665 | { | |
6666 | inst.error = _("Banked registers are not available with this " | |
6667 | "architecture."); | |
6668 | goto failure; | |
6669 | } | |
6670 | break; | |
d2cd1205 JB |
6671 | try_psr: |
6672 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6673 | break; | |
037e8744 JB |
6674 | |
6675 | case OP_APSR_RR: | |
6676 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6677 | break; | |
6678 | try_apsr: | |
6679 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6680 | instruction). */ | |
6681 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6682 | { | |
6683 | unsigned found = 0; | |
6684 | str += 5; | |
6685 | while (found < 15) | |
6686 | switch (*str++) | |
6687 | { | |
6688 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6689 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6690 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6691 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6692 | default: found = 16; | |
6693 | } | |
6694 | if (found != 15) | |
6695 | goto failure; | |
6696 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6697 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6698 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6699 | } |
6700 | else | |
6701 | goto failure; | |
6702 | break; | |
6703 | ||
92e90b6e PB |
6704 | case OP_TB: |
6705 | po_misc_or_fail (parse_tb (&str)); | |
6706 | break; | |
6707 | ||
e07e6e58 | 6708 | /* Register lists. */ |
c19d1205 ZW |
6709 | case OP_REGLST: |
6710 | val = parse_reg_list (&str); | |
6711 | if (*str == '^') | |
6712 | { | |
6713 | inst.operands[1].writeback = 1; | |
6714 | str++; | |
6715 | } | |
6716 | break; | |
09d92015 | 6717 | |
c19d1205 | 6718 | case OP_VRSLST: |
5287ad62 | 6719 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6720 | break; |
09d92015 | 6721 | |
c19d1205 | 6722 | case OP_VRDLST: |
5287ad62 | 6723 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6724 | break; |
a737bd4d | 6725 | |
037e8744 JB |
6726 | case OP_VRSDLST: |
6727 | /* Allow Q registers too. */ | |
6728 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6729 | REGLIST_NEON_D); | |
6730 | if (val == FAIL) | |
6731 | { | |
6732 | inst.error = NULL; | |
6733 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6734 | REGLIST_VFP_S); | |
6735 | inst.operands[i].issingle = 1; | |
6736 | } | |
6737 | break; | |
6738 | ||
5287ad62 JB |
6739 | case OP_NRDLST: |
6740 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6741 | REGLIST_NEON_D); | |
6742 | break; | |
6743 | ||
6744 | case OP_NSTRLST: | |
dcbf9037 JB |
6745 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6746 | &inst.operands[i].vectype); | |
5287ad62 JB |
6747 | break; |
6748 | ||
c19d1205 ZW |
6749 | /* Addressing modes */ |
6750 | case OP_ADDR: | |
6751 | po_misc_or_fail (parse_address (&str, i)); | |
6752 | break; | |
09d92015 | 6753 | |
4962c51a MS |
6754 | case OP_ADDRGLDR: |
6755 | po_misc_or_fail_no_backtrack ( | |
6756 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6757 | break; | |
6758 | ||
6759 | case OP_ADDRGLDRS: | |
6760 | po_misc_or_fail_no_backtrack ( | |
6761 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6762 | break; | |
6763 | ||
6764 | case OP_ADDRGLDC: | |
6765 | po_misc_or_fail_no_backtrack ( | |
6766 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6767 | break; | |
6768 | ||
c19d1205 ZW |
6769 | case OP_SH: |
6770 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6771 | break; | |
09d92015 | 6772 | |
4962c51a MS |
6773 | case OP_SHG: |
6774 | po_misc_or_fail_no_backtrack ( | |
6775 | parse_shifter_operand_group_reloc (&str, i)); | |
6776 | break; | |
6777 | ||
c19d1205 ZW |
6778 | case OP_oSHll: |
6779 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6780 | break; | |
09d92015 | 6781 | |
c19d1205 ZW |
6782 | case OP_oSHar: |
6783 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6784 | break; | |
09d92015 | 6785 | |
c19d1205 ZW |
6786 | case OP_oSHllar: |
6787 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6788 | break; | |
09d92015 | 6789 | |
c19d1205 | 6790 | default: |
5be8be5d | 6791 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6792 | } |
09d92015 | 6793 | |
c19d1205 ZW |
6794 | /* Various value-based sanity checks and shared operations. We |
6795 | do not signal immediate failures for the register constraints; | |
6796 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6797 | switch (op_parse_code) |
c19d1205 ZW |
6798 | { |
6799 | case OP_oRRnpc: | |
6800 | case OP_RRnpc: | |
6801 | case OP_RRnpcb: | |
6802 | case OP_RRw: | |
b6702015 | 6803 | case OP_oRRw: |
c19d1205 ZW |
6804 | case OP_RRnpc_I0: |
6805 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6806 | inst.error = BAD_PC; | |
6807 | break; | |
09d92015 | 6808 | |
5be8be5d DG |
6809 | case OP_oRRnpcsp: |
6810 | case OP_RRnpcsp: | |
6811 | if (inst.operands[i].isreg) | |
6812 | { | |
6813 | if (inst.operands[i].reg == REG_PC) | |
6814 | inst.error = BAD_PC; | |
6815 | else if (inst.operands[i].reg == REG_SP) | |
6816 | inst.error = BAD_SP; | |
6817 | } | |
6818 | break; | |
6819 | ||
55881a11 | 6820 | case OP_RRnpctw: |
fa94de6b RM |
6821 | if (inst.operands[i].isreg |
6822 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
6823 | && (inst.operands[i].writeback || thumb)) |
6824 | inst.error = BAD_PC; | |
6825 | break; | |
6826 | ||
c19d1205 ZW |
6827 | case OP_CPSF: |
6828 | case OP_ENDI: | |
6829 | case OP_oROR: | |
d2cd1205 JB |
6830 | case OP_wPSR: |
6831 | case OP_rPSR: | |
c19d1205 | 6832 | case OP_COND: |
52e7f43d | 6833 | case OP_oBARRIER_I15: |
c19d1205 ZW |
6834 | case OP_REGLST: |
6835 | case OP_VRSLST: | |
6836 | case OP_VRDLST: | |
037e8744 | 6837 | case OP_VRSDLST: |
5287ad62 JB |
6838 | case OP_NRDLST: |
6839 | case OP_NSTRLST: | |
c19d1205 ZW |
6840 | if (val == FAIL) |
6841 | goto failure; | |
6842 | inst.operands[i].imm = val; | |
6843 | break; | |
a737bd4d | 6844 | |
c19d1205 ZW |
6845 | default: |
6846 | break; | |
6847 | } | |
09d92015 | 6848 | |
c19d1205 ZW |
6849 | /* If we get here, this operand was successfully parsed. */ |
6850 | inst.operands[i].present = 1; | |
6851 | continue; | |
09d92015 | 6852 | |
c19d1205 | 6853 | bad_args: |
09d92015 | 6854 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6855 | |
6856 | failure: | |
6857 | if (!backtrack_pos) | |
d252fdde PB |
6858 | { |
6859 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6860 | default here just in case. */ |
d252fdde PB |
6861 | if (!inst.error) |
6862 | inst.error = _("syntax error"); | |
6863 | return FAIL; | |
6864 | } | |
c19d1205 ZW |
6865 | |
6866 | /* Do not backtrack over a trailing optional argument that | |
6867 | absorbed some text. We will only fail again, with the | |
6868 | 'garbage following instruction' error message, which is | |
6869 | probably less helpful than the current one. */ | |
6870 | if (backtrack_index == i && backtrack_pos != str | |
6871 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6872 | { |
6873 | if (!inst.error) | |
6874 | inst.error = _("syntax error"); | |
6875 | return FAIL; | |
6876 | } | |
c19d1205 ZW |
6877 | |
6878 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6879 | str = backtrack_pos; | |
6880 | inst.error = backtrack_error; | |
6881 | inst.operands[backtrack_index].present = 0; | |
6882 | i = backtrack_index; | |
6883 | backtrack_pos = 0; | |
09d92015 | 6884 | } |
09d92015 | 6885 | |
c19d1205 ZW |
6886 | /* Check that we have parsed all the arguments. */ |
6887 | if (*str != '\0' && !inst.error) | |
6888 | inst.error = _("garbage following instruction"); | |
09d92015 | 6889 | |
c19d1205 | 6890 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6891 | } |
6892 | ||
c19d1205 ZW |
6893 | #undef po_char_or_fail |
6894 | #undef po_reg_or_fail | |
6895 | #undef po_reg_or_goto | |
6896 | #undef po_imm_or_fail | |
5287ad62 | 6897 | #undef po_scalar_or_fail |
52e7f43d | 6898 | #undef po_barrier_or_imm |
e07e6e58 | 6899 | |
c19d1205 | 6900 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6901 | #define constraint(expr, err) \ |
6902 | do \ | |
c19d1205 | 6903 | { \ |
e07e6e58 NC |
6904 | if (expr) \ |
6905 | { \ | |
6906 | inst.error = err; \ | |
6907 | return; \ | |
6908 | } \ | |
c19d1205 | 6909 | } \ |
e07e6e58 | 6910 | while (0) |
c19d1205 | 6911 | |
fdfde340 JM |
6912 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6913 | instructions are unpredictable if these registers are used. This | |
6914 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6915 | #define reject_bad_reg(reg) \ | |
6916 | do \ | |
6917 | if (reg == REG_SP || reg == REG_PC) \ | |
6918 | { \ | |
6919 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6920 | return; \ | |
6921 | } \ | |
6922 | while (0) | |
6923 | ||
94206790 MM |
6924 | /* If REG is R13 (the stack pointer), warn that its use is |
6925 | deprecated. */ | |
6926 | #define warn_deprecated_sp(reg) \ | |
6927 | do \ | |
6928 | if (warn_on_deprecated && reg == REG_SP) \ | |
6929 | as_warn (_("use of r13 is deprecated")); \ | |
6930 | while (0) | |
6931 | ||
c19d1205 ZW |
6932 | /* Functions for operand encoding. ARM, then Thumb. */ |
6933 | ||
6934 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6935 | ||
6936 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6937 | return the encoded form. Otherwise, return FAIL. */ | |
6938 | ||
6939 | static unsigned int | |
6940 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6941 | { |
c19d1205 ZW |
6942 | unsigned int a, i; |
6943 | ||
6944 | for (i = 0; i < 32; i += 2) | |
6945 | if ((a = rotate_left (val, i)) <= 0xff) | |
6946 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6947 | ||
6948 | return FAIL; | |
09d92015 MM |
6949 | } |
6950 | ||
c19d1205 ZW |
6951 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6952 | return the encoded form. Otherwise, return FAIL. */ | |
6953 | static unsigned int | |
6954 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6955 | { |
c19d1205 | 6956 | unsigned int a, i; |
09d92015 | 6957 | |
9c3c69f2 | 6958 | if (val <= 0xff) |
c19d1205 | 6959 | return val; |
a737bd4d | 6960 | |
9c3c69f2 | 6961 | for (i = 1; i <= 24; i++) |
09d92015 | 6962 | { |
9c3c69f2 PB |
6963 | a = val >> i; |
6964 | if ((val & ~(0xff << i)) == 0) | |
6965 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6966 | } |
a737bd4d | 6967 | |
c19d1205 ZW |
6968 | a = val & 0xff; |
6969 | if (val == ((a << 16) | a)) | |
6970 | return 0x100 | a; | |
6971 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6972 | return 0x300 | a; | |
09d92015 | 6973 | |
c19d1205 ZW |
6974 | a = val & 0xff00; |
6975 | if (val == ((a << 16) | a)) | |
6976 | return 0x200 | (a >> 8); | |
a737bd4d | 6977 | |
c19d1205 | 6978 | return FAIL; |
09d92015 | 6979 | } |
5287ad62 | 6980 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6981 | |
6982 | static void | |
5287ad62 JB |
6983 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6984 | { | |
6985 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6986 | && reg > 15) | |
6987 | { | |
b1cc4aeb | 6988 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6989 | { |
6990 | if (thumb_mode) | |
6991 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6992 | fpu_vfp_ext_d32); |
5287ad62 JB |
6993 | else |
6994 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6995 | fpu_vfp_ext_d32); |
5287ad62 JB |
6996 | } |
6997 | else | |
6998 | { | |
dcbf9037 | 6999 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
7000 | return; |
7001 | } | |
7002 | } | |
7003 | ||
c19d1205 | 7004 | switch (pos) |
09d92015 | 7005 | { |
c19d1205 ZW |
7006 | case VFP_REG_Sd: |
7007 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
7008 | break; | |
7009 | ||
7010 | case VFP_REG_Sn: | |
7011 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
7012 | break; | |
7013 | ||
7014 | case VFP_REG_Sm: | |
7015 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
7016 | break; | |
7017 | ||
5287ad62 JB |
7018 | case VFP_REG_Dd: |
7019 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
7020 | break; | |
5f4273c7 | 7021 | |
5287ad62 JB |
7022 | case VFP_REG_Dn: |
7023 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7024 | break; | |
5f4273c7 | 7025 | |
5287ad62 JB |
7026 | case VFP_REG_Dm: |
7027 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7028 | break; | |
7029 | ||
c19d1205 ZW |
7030 | default: |
7031 | abort (); | |
09d92015 | 7032 | } |
09d92015 MM |
7033 | } |
7034 | ||
c19d1205 | 7035 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7036 | if any, is handled by md_apply_fix. */ |
09d92015 | 7037 | static void |
c19d1205 | 7038 | encode_arm_shift (int i) |
09d92015 | 7039 | { |
c19d1205 ZW |
7040 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7041 | inst.instruction |= SHIFT_ROR << 5; | |
7042 | else | |
09d92015 | 7043 | { |
c19d1205 ZW |
7044 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7045 | if (inst.operands[i].immisreg) | |
7046 | { | |
7047 | inst.instruction |= SHIFT_BY_REG; | |
7048 | inst.instruction |= inst.operands[i].imm << 8; | |
7049 | } | |
7050 | else | |
7051 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7052 | } |
c19d1205 | 7053 | } |
09d92015 | 7054 | |
c19d1205 ZW |
7055 | static void |
7056 | encode_arm_shifter_operand (int i) | |
7057 | { | |
7058 | if (inst.operands[i].isreg) | |
09d92015 | 7059 | { |
c19d1205 ZW |
7060 | inst.instruction |= inst.operands[i].reg; |
7061 | encode_arm_shift (i); | |
09d92015 | 7062 | } |
c19d1205 | 7063 | else |
a415b1cd JB |
7064 | { |
7065 | inst.instruction |= INST_IMMEDIATE; | |
7066 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7067 | inst.instruction |= inst.operands[i].imm; | |
7068 | } | |
09d92015 MM |
7069 | } |
7070 | ||
c19d1205 | 7071 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7072 | static void |
c19d1205 | 7073 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7074 | { |
2b2f5df9 NC |
7075 | /* PR 14260: |
7076 | Generate an error if the operand is not a register. */ | |
7077 | constraint (!inst.operands[i].isreg, | |
7078 | _("Instruction does not support =N addresses")); | |
7079 | ||
c19d1205 | 7080 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7081 | |
c19d1205 | 7082 | if (inst.operands[i].preind) |
09d92015 | 7083 | { |
c19d1205 ZW |
7084 | if (is_t) |
7085 | { | |
7086 | inst.error = _("instruction does not accept preindexed addressing"); | |
7087 | return; | |
7088 | } | |
7089 | inst.instruction |= PRE_INDEX; | |
7090 | if (inst.operands[i].writeback) | |
7091 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7092 | |
c19d1205 ZW |
7093 | } |
7094 | else if (inst.operands[i].postind) | |
7095 | { | |
9c2799c2 | 7096 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7097 | if (is_t) |
7098 | inst.instruction |= WRITE_BACK; | |
7099 | } | |
7100 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7101 | { |
c19d1205 | 7102 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7103 | return; |
7104 | } | |
7105 | ||
c19d1205 ZW |
7106 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7107 | && (((inst.instruction & 0x000f0000) >> 16) | |
7108 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7109 | as_warn ((inst.instruction & LOAD_BIT) | |
7110 | ? _("destination register same as write-back base") | |
7111 | : _("source register same as write-back base")); | |
09d92015 MM |
7112 | } |
7113 | ||
c19d1205 ZW |
7114 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7115 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7116 | reject forms that cannot be used with a T instruction (i.e. not | |
7117 | post-indexed). */ | |
a737bd4d | 7118 | static void |
c19d1205 | 7119 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7120 | { |
5be8be5d DG |
7121 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7122 | ||
c19d1205 | 7123 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7124 | |
c19d1205 | 7125 | if (inst.operands[i].immisreg) |
09d92015 | 7126 | { |
5be8be5d DG |
7127 | constraint ((inst.operands[i].imm == REG_PC |
7128 | || (is_pc && inst.operands[i].writeback)), | |
7129 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7130 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7131 | inst.instruction |= inst.operands[i].imm; | |
7132 | if (!inst.operands[i].negative) | |
7133 | inst.instruction |= INDEX_UP; | |
7134 | if (inst.operands[i].shifted) | |
7135 | { | |
7136 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7137 | inst.instruction |= SHIFT_ROR << 5; | |
7138 | else | |
7139 | { | |
7140 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7141 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7142 | } | |
7143 | } | |
09d92015 | 7144 | } |
c19d1205 | 7145 | else /* immediate offset in inst.reloc */ |
09d92015 | 7146 | { |
5be8be5d DG |
7147 | if (is_pc && !inst.reloc.pc_rel) |
7148 | { | |
7149 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7150 | |
7151 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7152 | cannot use PC in addressing. | |
7153 | PC cannot be used in writeback addressing, either. */ | |
7154 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7155 | BAD_PC_ADDRESSING); |
23a10334 | 7156 | |
dc5ec521 | 7157 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7158 | if (warn_on_deprecated |
7159 | && !is_load | |
7160 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
7161 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
7162 | } |
7163 | ||
c19d1205 | 7164 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7165 | { |
7166 | /* Prefer + for zero encoded value. */ | |
7167 | if (!inst.operands[i].negative) | |
7168 | inst.instruction |= INDEX_UP; | |
7169 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7170 | } | |
09d92015 | 7171 | } |
09d92015 MM |
7172 | } |
7173 | ||
c19d1205 ZW |
7174 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7175 | ARM-format mode 3 load or store instruction. Reject forms that | |
7176 | cannot be used with such instructions. If is_t is true, reject | |
7177 | forms that cannot be used with a T instruction (i.e. not | |
7178 | post-indexed). */ | |
7179 | static void | |
7180 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7181 | { |
c19d1205 | 7182 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7183 | { |
c19d1205 ZW |
7184 | inst.error = _("instruction does not accept scaled register index"); |
7185 | return; | |
09d92015 | 7186 | } |
a737bd4d | 7187 | |
c19d1205 | 7188 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7189 | |
c19d1205 ZW |
7190 | if (inst.operands[i].immisreg) |
7191 | { | |
5be8be5d DG |
7192 | constraint ((inst.operands[i].imm == REG_PC |
7193 | || inst.operands[i].reg == REG_PC), | |
7194 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7195 | inst.instruction |= inst.operands[i].imm; |
7196 | if (!inst.operands[i].negative) | |
7197 | inst.instruction |= INDEX_UP; | |
7198 | } | |
7199 | else /* immediate offset in inst.reloc */ | |
7200 | { | |
5be8be5d DG |
7201 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7202 | && inst.operands[i].writeback), | |
7203 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7204 | inst.instruction |= HWOFFSET_IMM; |
7205 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7206 | { |
7207 | /* Prefer + for zero encoded value. */ | |
7208 | if (!inst.operands[i].negative) | |
7209 | inst.instruction |= INDEX_UP; | |
7210 | ||
7211 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7212 | } | |
c19d1205 | 7213 | } |
a737bd4d NC |
7214 | } |
7215 | ||
c19d1205 ZW |
7216 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7217 | ARM-format instruction. Reject all forms which cannot be encoded | |
7218 | into a coprocessor load/store instruction. If wb_ok is false, | |
7219 | reject use of writeback; if unind_ok is false, reject use of | |
7220 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
7221 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
7222 | (in which case it is preserved). */ | |
09d92015 | 7223 | |
c19d1205 ZW |
7224 | static int |
7225 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 7226 | { |
c19d1205 | 7227 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7228 | |
9c2799c2 | 7229 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 7230 | |
c19d1205 | 7231 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 7232 | { |
9c2799c2 | 7233 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
7234 | if (!unind_ok) |
7235 | { | |
7236 | inst.error = _("instruction does not support unindexed addressing"); | |
7237 | return FAIL; | |
7238 | } | |
7239 | inst.instruction |= inst.operands[i].imm; | |
7240 | inst.instruction |= INDEX_UP; | |
7241 | return SUCCESS; | |
09d92015 | 7242 | } |
a737bd4d | 7243 | |
c19d1205 ZW |
7244 | if (inst.operands[i].preind) |
7245 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 7246 | |
c19d1205 | 7247 | if (inst.operands[i].writeback) |
09d92015 | 7248 | { |
c19d1205 ZW |
7249 | if (inst.operands[i].reg == REG_PC) |
7250 | { | |
7251 | inst.error = _("pc may not be used with write-back"); | |
7252 | return FAIL; | |
7253 | } | |
7254 | if (!wb_ok) | |
7255 | { | |
7256 | inst.error = _("instruction does not support writeback"); | |
7257 | return FAIL; | |
7258 | } | |
7259 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7260 | } |
a737bd4d | 7261 | |
c19d1205 | 7262 | if (reloc_override) |
21d799b5 | 7263 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
7264 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
7265 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7266 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
7267 | { | |
7268 | if (thumb_mode) | |
7269 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7270 | else | |
7271 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
7272 | } | |
7273 | ||
26d97720 NS |
7274 | /* Prefer + for zero encoded value. */ |
7275 | if (!inst.operands[i].negative) | |
7276 | inst.instruction |= INDEX_UP; | |
7277 | ||
c19d1205 ZW |
7278 | return SUCCESS; |
7279 | } | |
a737bd4d | 7280 | |
c19d1205 ZW |
7281 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7282 | Determine whether it can be performed with a move instruction; if | |
7283 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7284 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7285 | load and return FALSE. If this is not a valid thing to do in the | |
7286 | current context, set inst.error and return TRUE. | |
a737bd4d | 7287 | |
c19d1205 ZW |
7288 | inst.operands[i] describes the destination register. */ |
7289 | ||
c921be7d | 7290 | static bfd_boolean |
c19d1205 ZW |
7291 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
7292 | { | |
53365c0d PB |
7293 | unsigned long tbit; |
7294 | ||
7295 | if (thumb_p) | |
7296 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7297 | else | |
7298 | tbit = LOAD_BIT; | |
7299 | ||
7300 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7301 | { |
c19d1205 | 7302 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7303 | return TRUE; |
09d92015 | 7304 | } |
c19d1205 | 7305 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
7306 | { |
7307 | inst.error = _("constant expression expected"); | |
c921be7d | 7308 | return TRUE; |
09d92015 | 7309 | } |
c19d1205 | 7310 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 7311 | { |
c19d1205 ZW |
7312 | if (thumb_p) |
7313 | { | |
53365c0d | 7314 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
7315 | { |
7316 | /* This can be done with a mov(1) instruction. */ | |
7317 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7318 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 7319 | return TRUE; |
c19d1205 ZW |
7320 | } |
7321 | } | |
7322 | else | |
7323 | { | |
7324 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7325 | if (value != FAIL) | |
7326 | { | |
7327 | /* This can be done with a mov instruction. */ | |
7328 | inst.instruction &= LITERAL_MASK; | |
7329 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7330 | inst.instruction |= value & 0xfff; | |
c921be7d | 7331 | return TRUE; |
c19d1205 | 7332 | } |
09d92015 | 7333 | |
c19d1205 ZW |
7334 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
7335 | if (value != FAIL) | |
7336 | { | |
7337 | /* This can be done with a mvn instruction. */ | |
7338 | inst.instruction &= LITERAL_MASK; | |
7339 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7340 | inst.instruction |= value & 0xfff; | |
c921be7d | 7341 | return TRUE; |
c19d1205 ZW |
7342 | } |
7343 | } | |
09d92015 MM |
7344 | } |
7345 | ||
c19d1205 ZW |
7346 | if (add_to_lit_pool () == FAIL) |
7347 | { | |
7348 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 7349 | return TRUE; |
c19d1205 ZW |
7350 | } |
7351 | inst.operands[1].reg = REG_PC; | |
7352 | inst.operands[1].isreg = 1; | |
7353 | inst.operands[1].preind = 1; | |
7354 | inst.reloc.pc_rel = 1; | |
7355 | inst.reloc.type = (thumb_p | |
7356 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7357 | : (mode_3 | |
7358 | ? BFD_RELOC_ARM_HWLITERAL | |
7359 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 7360 | return FALSE; |
09d92015 MM |
7361 | } |
7362 | ||
5f4273c7 | 7363 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7364 | First some generics; their names are taken from the conventional |
7365 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7366 | |
a737bd4d | 7367 | static void |
c19d1205 | 7368 | do_noargs (void) |
09d92015 | 7369 | { |
c19d1205 | 7370 | } |
a737bd4d | 7371 | |
c19d1205 ZW |
7372 | static void |
7373 | do_rd (void) | |
7374 | { | |
7375 | inst.instruction |= inst.operands[0].reg << 12; | |
7376 | } | |
a737bd4d | 7377 | |
c19d1205 ZW |
7378 | static void |
7379 | do_rd_rm (void) | |
7380 | { | |
7381 | inst.instruction |= inst.operands[0].reg << 12; | |
7382 | inst.instruction |= inst.operands[1].reg; | |
7383 | } | |
09d92015 | 7384 | |
c19d1205 ZW |
7385 | static void |
7386 | do_rd_rn (void) | |
7387 | { | |
7388 | inst.instruction |= inst.operands[0].reg << 12; | |
7389 | inst.instruction |= inst.operands[1].reg << 16; | |
7390 | } | |
a737bd4d | 7391 | |
c19d1205 ZW |
7392 | static void |
7393 | do_rn_rd (void) | |
7394 | { | |
7395 | inst.instruction |= inst.operands[0].reg << 16; | |
7396 | inst.instruction |= inst.operands[1].reg << 12; | |
7397 | } | |
09d92015 | 7398 | |
59d09be6 MGD |
7399 | static bfd_boolean |
7400 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
7401 | { | |
7402 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
7403 | { | |
7404 | as_warn ("%s", msg); | |
7405 | return TRUE; | |
7406 | } | |
7407 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
7408 | { | |
7409 | as_bad ("%s", msg); | |
7410 | return TRUE; | |
7411 | } | |
7412 | ||
7413 | return FALSE; | |
7414 | } | |
7415 | ||
c19d1205 ZW |
7416 | static void |
7417 | do_rd_rm_rn (void) | |
7418 | { | |
9a64e435 | 7419 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7420 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7421 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7422 | { |
7423 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7424 | _("Rn must not overlap other operands")); | |
7425 | ||
59d09be6 MGD |
7426 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
7427 | */ | |
7428 | if (!check_obsolete (&arm_ext_v8, | |
7429 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
7430 | && warn_on_deprecated | |
7431 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
7432 | as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7")); | |
56adecf4 | 7433 | } |
59d09be6 | 7434 | |
c19d1205 ZW |
7435 | inst.instruction |= inst.operands[0].reg << 12; |
7436 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7437 | inst.instruction |= Rn << 16; |
c19d1205 | 7438 | } |
09d92015 | 7439 | |
c19d1205 ZW |
7440 | static void |
7441 | do_rd_rn_rm (void) | |
7442 | { | |
7443 | inst.instruction |= inst.operands[0].reg << 12; | |
7444 | inst.instruction |= inst.operands[1].reg << 16; | |
7445 | inst.instruction |= inst.operands[2].reg; | |
7446 | } | |
a737bd4d | 7447 | |
c19d1205 ZW |
7448 | static void |
7449 | do_rm_rd_rn (void) | |
7450 | { | |
5be8be5d DG |
7451 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7452 | constraint (((inst.reloc.exp.X_op != O_constant | |
7453 | && inst.reloc.exp.X_op != O_illegal) | |
7454 | || inst.reloc.exp.X_add_number != 0), | |
7455 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7456 | inst.instruction |= inst.operands[0].reg; |
7457 | inst.instruction |= inst.operands[1].reg << 12; | |
7458 | inst.instruction |= inst.operands[2].reg << 16; | |
7459 | } | |
09d92015 | 7460 | |
c19d1205 ZW |
7461 | static void |
7462 | do_imm0 (void) | |
7463 | { | |
7464 | inst.instruction |= inst.operands[0].imm; | |
7465 | } | |
09d92015 | 7466 | |
c19d1205 ZW |
7467 | static void |
7468 | do_rd_cpaddr (void) | |
7469 | { | |
7470 | inst.instruction |= inst.operands[0].reg << 12; | |
7471 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7472 | } |
a737bd4d | 7473 | |
c19d1205 ZW |
7474 | /* ARM instructions, in alphabetical order by function name (except |
7475 | that wrapper functions appear immediately after the function they | |
7476 | wrap). */ | |
09d92015 | 7477 | |
c19d1205 ZW |
7478 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7479 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7480 | |
7481 | static void | |
c19d1205 | 7482 | do_adr (void) |
09d92015 | 7483 | { |
c19d1205 | 7484 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7485 | |
c19d1205 ZW |
7486 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7487 | out to be negative. */ | |
7488 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7489 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7490 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7491 | } |
b99bd4ef | 7492 | |
c19d1205 ZW |
7493 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7494 | into a relative address of the form: | |
7495 | add rd, pc, #low(label-.-8)" | |
7496 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7497 | |
c19d1205 ZW |
7498 | static void |
7499 | do_adrl (void) | |
7500 | { | |
7501 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7502 | |
c19d1205 ZW |
7503 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7504 | out to be negative. */ | |
7505 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7506 | inst.reloc.pc_rel = 1; |
7507 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7508 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7509 | } |
7510 | ||
b99bd4ef | 7511 | static void |
c19d1205 | 7512 | do_arit (void) |
b99bd4ef | 7513 | { |
c19d1205 ZW |
7514 | if (!inst.operands[1].present) |
7515 | inst.operands[1].reg = inst.operands[0].reg; | |
7516 | inst.instruction |= inst.operands[0].reg << 12; | |
7517 | inst.instruction |= inst.operands[1].reg << 16; | |
7518 | encode_arm_shifter_operand (2); | |
7519 | } | |
b99bd4ef | 7520 | |
62b3e311 PB |
7521 | static void |
7522 | do_barrier (void) | |
7523 | { | |
7524 | if (inst.operands[0].present) | |
7525 | { | |
7526 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
7527 | && inst.operands[0].imm > 0xf |
7528 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 7529 | _("bad barrier type")); |
62b3e311 PB |
7530 | inst.instruction |= inst.operands[0].imm; |
7531 | } | |
7532 | else | |
7533 | inst.instruction |= 0xf; | |
7534 | } | |
7535 | ||
c19d1205 ZW |
7536 | static void |
7537 | do_bfc (void) | |
7538 | { | |
7539 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7540 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7541 | /* The instruction encoding stores the LSB and MSB, | |
7542 | not the LSB and width. */ | |
7543 | inst.instruction |= inst.operands[0].reg << 12; | |
7544 | inst.instruction |= inst.operands[1].imm << 7; | |
7545 | inst.instruction |= (msb - 1) << 16; | |
7546 | } | |
b99bd4ef | 7547 | |
c19d1205 ZW |
7548 | static void |
7549 | do_bfi (void) | |
7550 | { | |
7551 | unsigned int msb; | |
b99bd4ef | 7552 | |
c19d1205 ZW |
7553 | /* #0 in second position is alternative syntax for bfc, which is |
7554 | the same instruction but with REG_PC in the Rm field. */ | |
7555 | if (!inst.operands[1].isreg) | |
7556 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7557 | |
c19d1205 ZW |
7558 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7559 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7560 | /* The instruction encoding stores the LSB and MSB, | |
7561 | not the LSB and width. */ | |
7562 | inst.instruction |= inst.operands[0].reg << 12; | |
7563 | inst.instruction |= inst.operands[1].reg; | |
7564 | inst.instruction |= inst.operands[2].imm << 7; | |
7565 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7566 | } |
7567 | ||
b99bd4ef | 7568 | static void |
c19d1205 | 7569 | do_bfx (void) |
b99bd4ef | 7570 | { |
c19d1205 ZW |
7571 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7572 | _("bit-field extends past end of register")); | |
7573 | inst.instruction |= inst.operands[0].reg << 12; | |
7574 | inst.instruction |= inst.operands[1].reg; | |
7575 | inst.instruction |= inst.operands[2].imm << 7; | |
7576 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7577 | } | |
09d92015 | 7578 | |
c19d1205 ZW |
7579 | /* ARM V5 breakpoint instruction (argument parse) |
7580 | BKPT <16 bit unsigned immediate> | |
7581 | Instruction is not conditional. | |
7582 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7583 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7584 | |
c19d1205 ZW |
7585 | static void |
7586 | do_bkpt (void) | |
7587 | { | |
7588 | /* Top 12 of 16 bits to bits 19:8. */ | |
7589 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7590 | |
c19d1205 ZW |
7591 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7592 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7593 | } | |
09d92015 | 7594 | |
c19d1205 ZW |
7595 | static void |
7596 | encode_branch (int default_reloc) | |
7597 | { | |
7598 | if (inst.operands[0].hasreloc) | |
7599 | { | |
0855e32b NS |
7600 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
7601 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
7602 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
7603 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
7604 | ? BFD_RELOC_ARM_PLT32 | |
7605 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 7606 | } |
b99bd4ef | 7607 | else |
9ae92b05 | 7608 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 7609 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7610 | } |
7611 | ||
b99bd4ef | 7612 | static void |
c19d1205 | 7613 | do_branch (void) |
b99bd4ef | 7614 | { |
39b41c9c PB |
7615 | #ifdef OBJ_ELF |
7616 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7617 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7618 | else | |
7619 | #endif | |
7620 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7621 | } | |
7622 | ||
7623 | static void | |
7624 | do_bl (void) | |
7625 | { | |
7626 | #ifdef OBJ_ELF | |
7627 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7628 | { | |
7629 | if (inst.cond == COND_ALWAYS) | |
7630 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7631 | else | |
7632 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7633 | } | |
7634 | else | |
7635 | #endif | |
7636 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7637 | } |
b99bd4ef | 7638 | |
c19d1205 ZW |
7639 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7640 | BLX <target_addr> ie BLX(1) | |
7641 | BLX{<condition>} <Rm> ie BLX(2) | |
7642 | Unfortunately, there are two different opcodes for this mnemonic. | |
7643 | So, the insns[].value is not used, and the code here zaps values | |
7644 | into inst.instruction. | |
7645 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7646 | |
c19d1205 ZW |
7647 | static void |
7648 | do_blx (void) | |
7649 | { | |
7650 | if (inst.operands[0].isreg) | |
b99bd4ef | 7651 | { |
c19d1205 ZW |
7652 | /* Arg is a register; the opcode provided by insns[] is correct. |
7653 | It is not illegal to do "blx pc", just useless. */ | |
7654 | if (inst.operands[0].reg == REG_PC) | |
7655 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7656 | |
c19d1205 ZW |
7657 | inst.instruction |= inst.operands[0].reg; |
7658 | } | |
7659 | else | |
b99bd4ef | 7660 | { |
c19d1205 | 7661 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7662 | conditionally, and the opcode must be adjusted. |
7663 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7664 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7665 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7666 | inst.instruction = 0xfa000000; |
267bf995 | 7667 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7668 | } |
c19d1205 ZW |
7669 | } |
7670 | ||
7671 | static void | |
7672 | do_bx (void) | |
7673 | { | |
845b51d6 PB |
7674 | bfd_boolean want_reloc; |
7675 | ||
c19d1205 ZW |
7676 | if (inst.operands[0].reg == REG_PC) |
7677 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7678 | |
c19d1205 | 7679 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7680 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7681 | it is for ARMv4t or earlier. */ | |
7682 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7683 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7684 | want_reloc = TRUE; | |
7685 | ||
5ad34203 | 7686 | #ifdef OBJ_ELF |
845b51d6 | 7687 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7688 | #endif |
584206db | 7689 | want_reloc = FALSE; |
845b51d6 PB |
7690 | |
7691 | if (want_reloc) | |
7692 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7693 | } |
7694 | ||
c19d1205 ZW |
7695 | |
7696 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7697 | |
7698 | static void | |
c19d1205 | 7699 | do_bxj (void) |
a737bd4d | 7700 | { |
c19d1205 ZW |
7701 | if (inst.operands[0].reg == REG_PC) |
7702 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7703 | ||
7704 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7705 | } |
7706 | ||
c19d1205 ZW |
7707 | /* Co-processor data operation: |
7708 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7709 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7710 | static void | |
7711 | do_cdp (void) | |
7712 | { | |
7713 | inst.instruction |= inst.operands[0].reg << 8; | |
7714 | inst.instruction |= inst.operands[1].imm << 20; | |
7715 | inst.instruction |= inst.operands[2].reg << 12; | |
7716 | inst.instruction |= inst.operands[3].reg << 16; | |
7717 | inst.instruction |= inst.operands[4].reg; | |
7718 | inst.instruction |= inst.operands[5].imm << 5; | |
7719 | } | |
a737bd4d NC |
7720 | |
7721 | static void | |
c19d1205 | 7722 | do_cmp (void) |
a737bd4d | 7723 | { |
c19d1205 ZW |
7724 | inst.instruction |= inst.operands[0].reg << 16; |
7725 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7726 | } |
7727 | ||
c19d1205 ZW |
7728 | /* Transfer between coprocessor and ARM registers. |
7729 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7730 | MRC2 | |
7731 | MCR{cond} | |
7732 | MCR2 | |
7733 | ||
7734 | No special properties. */ | |
09d92015 | 7735 | |
dcbd0d71 MGD |
7736 | struct deprecated_coproc_regs_s |
7737 | { | |
7738 | unsigned cp; | |
7739 | int opc1; | |
7740 | unsigned crn; | |
7741 | unsigned crm; | |
7742 | int opc2; | |
7743 | arm_feature_set deprecated; | |
7744 | arm_feature_set obsoleted; | |
7745 | const char *dep_msg; | |
7746 | const char *obs_msg; | |
7747 | }; | |
7748 | ||
7749 | #define DEPR_ACCESS_V8 \ | |
7750 | N_("This coprocessor register access is deprecated in ARMv8") | |
7751 | ||
7752 | /* Table of all deprecated coprocessor registers. */ | |
7753 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
7754 | { | |
7755 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
7756 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7757 | DEPR_ACCESS_V8, NULL}, | |
7758 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
7759 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7760 | DEPR_ACCESS_V8, NULL}, | |
7761 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
7762 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7763 | DEPR_ACCESS_V8, NULL}, | |
7764 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
7765 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7766 | DEPR_ACCESS_V8, NULL}, | |
7767 | {14, 6, 0, 0, 0, /* TEECR. */ | |
7768 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7769 | DEPR_ACCESS_V8, NULL}, | |
7770 | }; | |
7771 | ||
7772 | #undef DEPR_ACCESS_V8 | |
7773 | ||
7774 | static const size_t deprecated_coproc_reg_count = | |
7775 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
7776 | ||
09d92015 | 7777 | static void |
c19d1205 | 7778 | do_co_reg (void) |
09d92015 | 7779 | { |
fdfde340 | 7780 | unsigned Rd; |
dcbd0d71 | 7781 | size_t i; |
fdfde340 JM |
7782 | |
7783 | Rd = inst.operands[2].reg; | |
7784 | if (thumb_mode) | |
7785 | { | |
7786 | if (inst.instruction == 0xee000010 | |
7787 | || inst.instruction == 0xfe000010) | |
7788 | /* MCR, MCR2 */ | |
7789 | reject_bad_reg (Rd); | |
7790 | else | |
7791 | /* MRC, MRC2 */ | |
7792 | constraint (Rd == REG_SP, BAD_SP); | |
7793 | } | |
7794 | else | |
7795 | { | |
7796 | /* MCR */ | |
7797 | if (inst.instruction == 0xe000010) | |
7798 | constraint (Rd == REG_PC, BAD_PC); | |
7799 | } | |
7800 | ||
dcbd0d71 MGD |
7801 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
7802 | { | |
7803 | const struct deprecated_coproc_regs_s *r = | |
7804 | deprecated_coproc_regs + i; | |
7805 | ||
7806 | if (inst.operands[0].reg == r->cp | |
7807 | && inst.operands[1].imm == r->opc1 | |
7808 | && inst.operands[3].reg == r->crn | |
7809 | && inst.operands[4].reg == r->crm | |
7810 | && inst.operands[5].imm == r->opc2) | |
7811 | { | |
7812 | if (!check_obsolete (&r->obsoleted, r->obs_msg) | |
7813 | && warn_on_deprecated | |
7814 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) | |
7815 | as_warn ("%s", r->dep_msg); | |
7816 | } | |
7817 | } | |
fdfde340 | 7818 | |
c19d1205 ZW |
7819 | inst.instruction |= inst.operands[0].reg << 8; |
7820 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7821 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7822 | inst.instruction |= inst.operands[3].reg << 16; |
7823 | inst.instruction |= inst.operands[4].reg; | |
7824 | inst.instruction |= inst.operands[5].imm << 5; | |
7825 | } | |
09d92015 | 7826 | |
c19d1205 ZW |
7827 | /* Transfer between coprocessor register and pair of ARM registers. |
7828 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7829 | MCRR2 | |
7830 | MRRC{cond} | |
7831 | MRRC2 | |
b99bd4ef | 7832 | |
c19d1205 | 7833 | Two XScale instructions are special cases of these: |
09d92015 | 7834 | |
c19d1205 ZW |
7835 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7836 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7837 | |
5f4273c7 | 7838 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7839 | |
c19d1205 ZW |
7840 | static void |
7841 | do_co_reg2c (void) | |
7842 | { | |
fdfde340 JM |
7843 | unsigned Rd, Rn; |
7844 | ||
7845 | Rd = inst.operands[2].reg; | |
7846 | Rn = inst.operands[3].reg; | |
7847 | ||
7848 | if (thumb_mode) | |
7849 | { | |
7850 | reject_bad_reg (Rd); | |
7851 | reject_bad_reg (Rn); | |
7852 | } | |
7853 | else | |
7854 | { | |
7855 | constraint (Rd == REG_PC, BAD_PC); | |
7856 | constraint (Rn == REG_PC, BAD_PC); | |
7857 | } | |
7858 | ||
c19d1205 ZW |
7859 | inst.instruction |= inst.operands[0].reg << 8; |
7860 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7861 | inst.instruction |= Rd << 12; |
7862 | inst.instruction |= Rn << 16; | |
c19d1205 | 7863 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7864 | } |
7865 | ||
c19d1205 ZW |
7866 | static void |
7867 | do_cpsi (void) | |
7868 | { | |
7869 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7870 | if (inst.operands[1].present) |
7871 | { | |
7872 | inst.instruction |= CPSI_MMOD; | |
7873 | inst.instruction |= inst.operands[1].imm; | |
7874 | } | |
c19d1205 | 7875 | } |
b99bd4ef | 7876 | |
62b3e311 PB |
7877 | static void |
7878 | do_dbg (void) | |
7879 | { | |
7880 | inst.instruction |= inst.operands[0].imm; | |
7881 | } | |
7882 | ||
eea54501 MGD |
7883 | static void |
7884 | do_div (void) | |
7885 | { | |
7886 | unsigned Rd, Rn, Rm; | |
7887 | ||
7888 | Rd = inst.operands[0].reg; | |
7889 | Rn = (inst.operands[1].present | |
7890 | ? inst.operands[1].reg : Rd); | |
7891 | Rm = inst.operands[2].reg; | |
7892 | ||
7893 | constraint ((Rd == REG_PC), BAD_PC); | |
7894 | constraint ((Rn == REG_PC), BAD_PC); | |
7895 | constraint ((Rm == REG_PC), BAD_PC); | |
7896 | ||
7897 | inst.instruction |= Rd << 16; | |
7898 | inst.instruction |= Rn << 0; | |
7899 | inst.instruction |= Rm << 8; | |
7900 | } | |
7901 | ||
b99bd4ef | 7902 | static void |
c19d1205 | 7903 | do_it (void) |
b99bd4ef | 7904 | { |
c19d1205 | 7905 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7906 | process it to do the validation as if in |
7907 | thumb mode, just in case the code gets | |
7908 | assembled for thumb using the unified syntax. */ | |
7909 | ||
c19d1205 | 7910 | inst.size = 0; |
e07e6e58 NC |
7911 | if (unified_syntax) |
7912 | { | |
7913 | set_it_insn_type (IT_INSN); | |
7914 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7915 | now_it.cc = inst.operands[0].imm; | |
7916 | } | |
09d92015 | 7917 | } |
b99bd4ef | 7918 | |
6530b175 NC |
7919 | /* If there is only one register in the register list, |
7920 | then return its register number. Otherwise return -1. */ | |
7921 | static int | |
7922 | only_one_reg_in_list (int range) | |
7923 | { | |
7924 | int i = ffs (range) - 1; | |
7925 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
7926 | } | |
7927 | ||
09d92015 | 7928 | static void |
6530b175 | 7929 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 7930 | { |
c19d1205 ZW |
7931 | int base_reg = inst.operands[0].reg; |
7932 | int range = inst.operands[1].imm; | |
6530b175 | 7933 | int one_reg; |
ea6ef066 | 7934 | |
c19d1205 ZW |
7935 | inst.instruction |= base_reg << 16; |
7936 | inst.instruction |= range; | |
ea6ef066 | 7937 | |
c19d1205 ZW |
7938 | if (inst.operands[1].writeback) |
7939 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7940 | |
c19d1205 | 7941 | if (inst.operands[0].writeback) |
ea6ef066 | 7942 | { |
c19d1205 ZW |
7943 | inst.instruction |= WRITE_BACK; |
7944 | /* Check for unpredictable uses of writeback. */ | |
7945 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7946 | { |
c19d1205 ZW |
7947 | /* Not allowed in LDM type 2. */ |
7948 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7949 | && ((range & (1 << REG_PC)) == 0)) | |
7950 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7951 | /* Only allowed if base reg not in list for other types. */ | |
7952 | else if (range & (1 << base_reg)) | |
7953 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7954 | } | |
7955 | else /* STM. */ | |
7956 | { | |
7957 | /* Not allowed for type 2. */ | |
7958 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7959 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7960 | /* Only allowed if base reg not in list, or first in list. */ | |
7961 | else if ((range & (1 << base_reg)) | |
7962 | && (range & ((1 << base_reg) - 1))) | |
7963 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7964 | } |
ea6ef066 | 7965 | } |
6530b175 NC |
7966 | |
7967 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
7968 | one_reg = only_one_reg_in_list (range); | |
7969 | if (from_push_pop_mnem && one_reg >= 0) | |
7970 | { | |
7971 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
7972 | ||
7973 | inst.instruction &= A_COND_MASK; | |
7974 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
7975 | inst.instruction |= one_reg << 12; | |
7976 | } | |
7977 | } | |
7978 | ||
7979 | static void | |
7980 | do_ldmstm (void) | |
7981 | { | |
7982 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
7983 | } |
7984 | ||
c19d1205 ZW |
7985 | /* ARMv5TE load-consecutive (argument parse) |
7986 | Mode is like LDRH. | |
7987 | ||
7988 | LDRccD R, mode | |
7989 | STRccD R, mode. */ | |
7990 | ||
a737bd4d | 7991 | static void |
c19d1205 | 7992 | do_ldrd (void) |
a737bd4d | 7993 | { |
c19d1205 | 7994 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 7995 | _("first transfer register must be even")); |
c19d1205 ZW |
7996 | constraint (inst.operands[1].present |
7997 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 7998 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
7999 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
8000 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 8001 | |
c19d1205 ZW |
8002 | if (!inst.operands[1].present) |
8003 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 8004 | |
c56791bb RE |
8005 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
8006 | register and the first register written; we have to diagnose | |
8007 | overlap between the base and the second register written here. */ | |
ea6ef066 | 8008 | |
c56791bb RE |
8009 | if (inst.operands[2].reg == inst.operands[1].reg |
8010 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
8011 | as_warn (_("base register written back, and overlaps " | |
8012 | "second transfer register")); | |
b05fe5cf | 8013 | |
c56791bb RE |
8014 | if (!(inst.instruction & V4_STR_BIT)) |
8015 | { | |
c19d1205 | 8016 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
8017 | destination (even if not write-back). */ |
8018 | if (inst.operands[2].immisreg | |
8019 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
8020 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
8021 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 8022 | } |
c19d1205 ZW |
8023 | inst.instruction |= inst.operands[0].reg << 12; |
8024 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8025 | } |
8026 | ||
8027 | static void | |
c19d1205 | 8028 | do_ldrex (void) |
b05fe5cf | 8029 | { |
c19d1205 ZW |
8030 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8031 | || inst.operands[1].postind || inst.operands[1].writeback | |
8032 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8033 | || inst.operands[1].negative |
8034 | /* This can arise if the programmer has written | |
8035 | strex rN, rM, foo | |
8036 | or if they have mistakenly used a register name as the last | |
8037 | operand, eg: | |
8038 | strex rN, rM, rX | |
8039 | It is very difficult to distinguish between these two cases | |
8040 | because "rX" might actually be a label. ie the register | |
8041 | name has been occluded by a symbol of the same name. So we | |
8042 | just generate a general 'bad addressing mode' type error | |
8043 | message and leave it up to the programmer to discover the | |
8044 | true cause and fix their mistake. */ | |
8045 | || (inst.operands[1].reg == REG_PC), | |
8046 | BAD_ADDR_MODE); | |
b05fe5cf | 8047 | |
c19d1205 ZW |
8048 | constraint (inst.reloc.exp.X_op != O_constant |
8049 | || inst.reloc.exp.X_add_number != 0, | |
8050 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 8051 | |
5be8be5d DG |
8052 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
8053 | ||
c19d1205 ZW |
8054 | inst.instruction |= inst.operands[0].reg << 12; |
8055 | inst.instruction |= inst.operands[1].reg << 16; | |
8056 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
8057 | } |
8058 | ||
8059 | static void | |
c19d1205 | 8060 | do_ldrexd (void) |
b05fe5cf | 8061 | { |
c19d1205 ZW |
8062 | constraint (inst.operands[0].reg % 2 != 0, |
8063 | _("even register required")); | |
8064 | constraint (inst.operands[1].present | |
8065 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
8066 | _("can only load two consecutive registers")); | |
8067 | /* If op 1 were present and equal to PC, this function wouldn't | |
8068 | have been called in the first place. */ | |
8069 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 8070 | |
c19d1205 ZW |
8071 | inst.instruction |= inst.operands[0].reg << 12; |
8072 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
8073 | } |
8074 | ||
1be5fd2e NC |
8075 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
8076 | which is not a multiple of four is UNPREDICTABLE. */ | |
8077 | static void | |
8078 | check_ldr_r15_aligned (void) | |
8079 | { | |
8080 | constraint (!(inst.operands[1].immisreg) | |
8081 | && (inst.operands[0].reg == REG_PC | |
8082 | && inst.operands[1].reg == REG_PC | |
8083 | && (inst.reloc.exp.X_add_number & 0x3)), | |
8084 | _("ldr to register 15 must be 4-byte alligned")); | |
8085 | } | |
8086 | ||
b05fe5cf | 8087 | static void |
c19d1205 | 8088 | do_ldst (void) |
b05fe5cf | 8089 | { |
c19d1205 ZW |
8090 | inst.instruction |= inst.operands[0].reg << 12; |
8091 | if (!inst.operands[1].isreg) | |
8092 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 8093 | return; |
c19d1205 | 8094 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 8095 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
8096 | } |
8097 | ||
8098 | static void | |
c19d1205 | 8099 | do_ldstt (void) |
b05fe5cf | 8100 | { |
c19d1205 ZW |
8101 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8102 | reject [Rn,...]. */ | |
8103 | if (inst.operands[1].preind) | |
b05fe5cf | 8104 | { |
bd3ba5d1 NC |
8105 | constraint (inst.reloc.exp.X_op != O_constant |
8106 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8107 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8108 | |
c19d1205 ZW |
8109 | inst.operands[1].preind = 0; |
8110 | inst.operands[1].postind = 1; | |
8111 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8112 | } |
c19d1205 ZW |
8113 | inst.instruction |= inst.operands[0].reg << 12; |
8114 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
8115 | } | |
b05fe5cf | 8116 | |
c19d1205 | 8117 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 8118 | |
c19d1205 ZW |
8119 | static void |
8120 | do_ldstv4 (void) | |
8121 | { | |
ff4a8d2b | 8122 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
8123 | inst.instruction |= inst.operands[0].reg << 12; |
8124 | if (!inst.operands[1].isreg) | |
8125 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 8126 | return; |
c19d1205 | 8127 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
8128 | } |
8129 | ||
8130 | static void | |
c19d1205 | 8131 | do_ldsttv4 (void) |
b05fe5cf | 8132 | { |
c19d1205 ZW |
8133 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8134 | reject [Rn,...]. */ | |
8135 | if (inst.operands[1].preind) | |
b05fe5cf | 8136 | { |
bd3ba5d1 NC |
8137 | constraint (inst.reloc.exp.X_op != O_constant |
8138 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8139 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8140 | |
c19d1205 ZW |
8141 | inst.operands[1].preind = 0; |
8142 | inst.operands[1].postind = 1; | |
8143 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8144 | } |
c19d1205 ZW |
8145 | inst.instruction |= inst.operands[0].reg << 12; |
8146 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
8147 | } | |
b05fe5cf | 8148 | |
c19d1205 ZW |
8149 | /* Co-processor register load/store. |
8150 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8151 | static void | |
8152 | do_lstc (void) | |
8153 | { | |
8154 | inst.instruction |= inst.operands[0].reg << 8; | |
8155 | inst.instruction |= inst.operands[1].reg << 12; | |
8156 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8157 | } |
8158 | ||
b05fe5cf | 8159 | static void |
c19d1205 | 8160 | do_mlas (void) |
b05fe5cf | 8161 | { |
8fb9d7b9 | 8162 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8163 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8164 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8165 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8166 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8167 | |
c19d1205 ZW |
8168 | inst.instruction |= inst.operands[0].reg << 16; |
8169 | inst.instruction |= inst.operands[1].reg; | |
8170 | inst.instruction |= inst.operands[2].reg << 8; | |
8171 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8172 | } |
b05fe5cf | 8173 | |
c19d1205 ZW |
8174 | static void |
8175 | do_mov (void) | |
8176 | { | |
8177 | inst.instruction |= inst.operands[0].reg << 12; | |
8178 | encode_arm_shifter_operand (1); | |
8179 | } | |
b05fe5cf | 8180 | |
c19d1205 ZW |
8181 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8182 | static void | |
8183 | do_mov16 (void) | |
8184 | { | |
b6895b4f PB |
8185 | bfd_vma imm; |
8186 | bfd_boolean top; | |
8187 | ||
8188 | top = (inst.instruction & 0x00400000) != 0; | |
8189 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8190 | _(":lower16: not allowed this instruction")); | |
8191 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8192 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8193 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8194 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8195 | { | |
8196 | imm = inst.reloc.exp.X_add_number; | |
8197 | /* The value is in two pieces: 0:11, 16:19. */ | |
8198 | inst.instruction |= (imm & 0x00000fff); | |
8199 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8200 | } | |
b05fe5cf | 8201 | } |
b99bd4ef | 8202 | |
037e8744 JB |
8203 | static void do_vfp_nsyn_opcode (const char *); |
8204 | ||
8205 | static int | |
8206 | do_vfp_nsyn_mrs (void) | |
8207 | { | |
8208 | if (inst.operands[0].isvec) | |
8209 | { | |
8210 | if (inst.operands[1].reg != 1) | |
8211 | first_error (_("operand 1 must be FPSCR")); | |
8212 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
8213 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8214 | do_vfp_nsyn_opcode ("fmstat"); | |
8215 | } | |
8216 | else if (inst.operands[1].isvec) | |
8217 | do_vfp_nsyn_opcode ("fmrx"); | |
8218 | else | |
8219 | return FAIL; | |
5f4273c7 | 8220 | |
037e8744 JB |
8221 | return SUCCESS; |
8222 | } | |
8223 | ||
8224 | static int | |
8225 | do_vfp_nsyn_msr (void) | |
8226 | { | |
8227 | if (inst.operands[0].isvec) | |
8228 | do_vfp_nsyn_opcode ("fmxr"); | |
8229 | else | |
8230 | return FAIL; | |
8231 | ||
8232 | return SUCCESS; | |
8233 | } | |
8234 | ||
f7c21dc7 NC |
8235 | static void |
8236 | do_vmrs (void) | |
8237 | { | |
8238 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 8239 | |
f7c21dc7 NC |
8240 | if (thumb_mode && inst.operands[0].reg == REG_SP) |
8241 | { | |
8242 | inst.error = BAD_SP; | |
8243 | return; | |
8244 | } | |
8245 | ||
8246 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
8247 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
8248 | { | |
8249 | inst.error = BAD_PC; | |
8250 | return; | |
8251 | } | |
8252 | ||
7465e07a NC |
8253 | switch (inst.operands[1].reg) |
8254 | { | |
8255 | case 0: /* FPSID */ | |
8256 | case 1: /* FPSCR */ | |
8257 | case 6: /* MVFR1 */ | |
8258 | case 7: /* MVFR0 */ | |
8259 | case 8: /* FPEXC */ | |
8260 | inst.instruction |= (inst.operands[1].reg << 16); | |
8261 | break; | |
8262 | default: | |
8263 | first_error (_("operand 1 must be a VFP extension System Register")); | |
8264 | } | |
f7c21dc7 NC |
8265 | |
8266 | inst.instruction |= (Rt << 12); | |
8267 | } | |
8268 | ||
8269 | static void | |
8270 | do_vmsr (void) | |
8271 | { | |
8272 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 8273 | |
f7c21dc7 NC |
8274 | if (thumb_mode) |
8275 | reject_bad_reg (Rt); | |
8276 | else if (Rt == REG_PC) | |
8277 | { | |
8278 | inst.error = BAD_PC; | |
8279 | return; | |
8280 | } | |
8281 | ||
7465e07a NC |
8282 | switch (inst.operands[0].reg) |
8283 | { | |
8284 | case 0: /* FPSID */ | |
8285 | case 1: /* FPSCR */ | |
8286 | case 8: /* FPEXC */ | |
8287 | inst.instruction |= (inst.operands[0].reg << 16); | |
8288 | break; | |
8289 | default: | |
8290 | first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC")); | |
8291 | } | |
f7c21dc7 NC |
8292 | |
8293 | inst.instruction |= (Rt << 12); | |
8294 | } | |
8295 | ||
b99bd4ef | 8296 | static void |
c19d1205 | 8297 | do_mrs (void) |
b99bd4ef | 8298 | { |
90ec0d68 MGD |
8299 | unsigned br; |
8300 | ||
037e8744 JB |
8301 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8302 | return; | |
8303 | ||
ff4a8d2b | 8304 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8305 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8306 | |
8307 | if (inst.operands[1].isreg) | |
8308 | { | |
8309 | br = inst.operands[1].reg; | |
8310 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8311 | as_bad (_("bad register for mrs")); | |
8312 | } | |
8313 | else | |
8314 | { | |
8315 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8316 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8317 | != (PSR_c|PSR_f), | |
d2cd1205 | 8318 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8319 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8320 | } | |
8321 | ||
8322 | inst.instruction |= br; | |
c19d1205 | 8323 | } |
b99bd4ef | 8324 | |
c19d1205 ZW |
8325 | /* Two possible forms: |
8326 | "{C|S}PSR_<field>, Rm", | |
8327 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8328 | |
c19d1205 ZW |
8329 | static void |
8330 | do_msr (void) | |
8331 | { | |
037e8744 JB |
8332 | if (do_vfp_nsyn_msr () == SUCCESS) |
8333 | return; | |
8334 | ||
c19d1205 ZW |
8335 | inst.instruction |= inst.operands[0].imm; |
8336 | if (inst.operands[1].isreg) | |
8337 | inst.instruction |= inst.operands[1].reg; | |
8338 | else | |
b99bd4ef | 8339 | { |
c19d1205 ZW |
8340 | inst.instruction |= INST_IMMEDIATE; |
8341 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8342 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8343 | } |
b99bd4ef NC |
8344 | } |
8345 | ||
c19d1205 ZW |
8346 | static void |
8347 | do_mul (void) | |
a737bd4d | 8348 | { |
ff4a8d2b NC |
8349 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8350 | ||
c19d1205 ZW |
8351 | if (!inst.operands[2].present) |
8352 | inst.operands[2].reg = inst.operands[0].reg; | |
8353 | inst.instruction |= inst.operands[0].reg << 16; | |
8354 | inst.instruction |= inst.operands[1].reg; | |
8355 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8356 | |
8fb9d7b9 MS |
8357 | if (inst.operands[0].reg == inst.operands[1].reg |
8358 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8359 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8360 | } |
8361 | ||
c19d1205 ZW |
8362 | /* Long Multiply Parser |
8363 | UMULL RdLo, RdHi, Rm, Rs | |
8364 | SMULL RdLo, RdHi, Rm, Rs | |
8365 | UMLAL RdLo, RdHi, Rm, Rs | |
8366 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8367 | |
8368 | static void | |
c19d1205 | 8369 | do_mull (void) |
b99bd4ef | 8370 | { |
c19d1205 ZW |
8371 | inst.instruction |= inst.operands[0].reg << 12; |
8372 | inst.instruction |= inst.operands[1].reg << 16; | |
8373 | inst.instruction |= inst.operands[2].reg; | |
8374 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8375 | |
682b27ad PB |
8376 | /* rdhi and rdlo must be different. */ |
8377 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8378 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8379 | ||
8380 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8381 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8382 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8383 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8384 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8385 | } | |
b99bd4ef | 8386 | |
c19d1205 ZW |
8387 | static void |
8388 | do_nop (void) | |
8389 | { | |
e7495e45 NS |
8390 | if (inst.operands[0].present |
8391 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8392 | { |
8393 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8394 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8395 | inst.instruction |= 0x0320f000; |
8396 | if (inst.operands[0].present) | |
8397 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8398 | } |
b99bd4ef NC |
8399 | } |
8400 | ||
c19d1205 ZW |
8401 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8402 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8403 | Condition defaults to COND_ALWAYS. | |
8404 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8405 | |
8406 | static void | |
c19d1205 | 8407 | do_pkhbt (void) |
b99bd4ef | 8408 | { |
c19d1205 ZW |
8409 | inst.instruction |= inst.operands[0].reg << 12; |
8410 | inst.instruction |= inst.operands[1].reg << 16; | |
8411 | inst.instruction |= inst.operands[2].reg; | |
8412 | if (inst.operands[3].present) | |
8413 | encode_arm_shift (3); | |
8414 | } | |
b99bd4ef | 8415 | |
c19d1205 | 8416 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8417 | |
c19d1205 ZW |
8418 | static void |
8419 | do_pkhtb (void) | |
8420 | { | |
8421 | if (!inst.operands[3].present) | |
b99bd4ef | 8422 | { |
c19d1205 ZW |
8423 | /* If the shift specifier is omitted, turn the instruction |
8424 | into pkhbt rd, rm, rn. */ | |
8425 | inst.instruction &= 0xfff00010; | |
8426 | inst.instruction |= inst.operands[0].reg << 12; | |
8427 | inst.instruction |= inst.operands[1].reg; | |
8428 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8429 | } |
8430 | else | |
8431 | { | |
c19d1205 ZW |
8432 | inst.instruction |= inst.operands[0].reg << 12; |
8433 | inst.instruction |= inst.operands[1].reg << 16; | |
8434 | inst.instruction |= inst.operands[2].reg; | |
8435 | encode_arm_shift (3); | |
b99bd4ef NC |
8436 | } |
8437 | } | |
8438 | ||
c19d1205 | 8439 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 8440 | MP Extensions: Preload for write |
c19d1205 | 8441 | |
60e5ef9f | 8442 | PLD(W) <addr_mode> |
c19d1205 ZW |
8443 | |
8444 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
8445 | |
8446 | static void | |
c19d1205 | 8447 | do_pld (void) |
b99bd4ef | 8448 | { |
c19d1205 ZW |
8449 | constraint (!inst.operands[0].isreg, |
8450 | _("'[' expected after PLD mnemonic")); | |
8451 | constraint (inst.operands[0].postind, | |
8452 | _("post-indexed expression used in preload instruction")); | |
8453 | constraint (inst.operands[0].writeback, | |
8454 | _("writeback used in preload instruction")); | |
8455 | constraint (!inst.operands[0].preind, | |
8456 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
8457 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
8458 | } | |
b99bd4ef | 8459 | |
62b3e311 PB |
8460 | /* ARMv7: PLI <addr_mode> */ |
8461 | static void | |
8462 | do_pli (void) | |
8463 | { | |
8464 | constraint (!inst.operands[0].isreg, | |
8465 | _("'[' expected after PLI mnemonic")); | |
8466 | constraint (inst.operands[0].postind, | |
8467 | _("post-indexed expression used in preload instruction")); | |
8468 | constraint (inst.operands[0].writeback, | |
8469 | _("writeback used in preload instruction")); | |
8470 | constraint (!inst.operands[0].preind, | |
8471 | _("unindexed addressing used in preload instruction")); | |
8472 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
8473 | inst.instruction &= ~PRE_INDEX; | |
8474 | } | |
8475 | ||
c19d1205 ZW |
8476 | static void |
8477 | do_push_pop (void) | |
8478 | { | |
8479 | inst.operands[1] = inst.operands[0]; | |
8480 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
8481 | inst.operands[0].isreg = 1; | |
8482 | inst.operands[0].writeback = 1; | |
8483 | inst.operands[0].reg = REG_SP; | |
6530b175 | 8484 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 8485 | } |
b99bd4ef | 8486 | |
c19d1205 ZW |
8487 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
8488 | word at the specified address and the following word | |
8489 | respectively. | |
8490 | Unconditionally executed. | |
8491 | Error if Rn is R15. */ | |
b99bd4ef | 8492 | |
c19d1205 ZW |
8493 | static void |
8494 | do_rfe (void) | |
8495 | { | |
8496 | inst.instruction |= inst.operands[0].reg << 16; | |
8497 | if (inst.operands[0].writeback) | |
8498 | inst.instruction |= WRITE_BACK; | |
8499 | } | |
b99bd4ef | 8500 | |
c19d1205 | 8501 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 8502 | |
c19d1205 ZW |
8503 | static void |
8504 | do_ssat (void) | |
8505 | { | |
8506 | inst.instruction |= inst.operands[0].reg << 12; | |
8507 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
8508 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8509 | |
c19d1205 ZW |
8510 | if (inst.operands[3].present) |
8511 | encode_arm_shift (3); | |
b99bd4ef NC |
8512 | } |
8513 | ||
c19d1205 | 8514 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
8515 | |
8516 | static void | |
c19d1205 | 8517 | do_usat (void) |
b99bd4ef | 8518 | { |
c19d1205 ZW |
8519 | inst.instruction |= inst.operands[0].reg << 12; |
8520 | inst.instruction |= inst.operands[1].imm << 16; | |
8521 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8522 | |
c19d1205 ZW |
8523 | if (inst.operands[3].present) |
8524 | encode_arm_shift (3); | |
b99bd4ef NC |
8525 | } |
8526 | ||
c19d1205 | 8527 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
8528 | |
8529 | static void | |
c19d1205 | 8530 | do_ssat16 (void) |
09d92015 | 8531 | { |
c19d1205 ZW |
8532 | inst.instruction |= inst.operands[0].reg << 12; |
8533 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
8534 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
8535 | } |
8536 | ||
c19d1205 ZW |
8537 | static void |
8538 | do_usat16 (void) | |
a737bd4d | 8539 | { |
c19d1205 ZW |
8540 | inst.instruction |= inst.operands[0].reg << 12; |
8541 | inst.instruction |= inst.operands[1].imm << 16; | |
8542 | inst.instruction |= inst.operands[2].reg; | |
8543 | } | |
a737bd4d | 8544 | |
c19d1205 ZW |
8545 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
8546 | preserving the other bits. | |
a737bd4d | 8547 | |
c19d1205 ZW |
8548 | setend <endian_specifier>, where <endian_specifier> is either |
8549 | BE or LE. */ | |
a737bd4d | 8550 | |
c19d1205 ZW |
8551 | static void |
8552 | do_setend (void) | |
8553 | { | |
12e37cbc MGD |
8554 | if (warn_on_deprecated |
8555 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
8556 | as_warn (_("setend use is deprecated for ARMv8")); | |
8557 | ||
c19d1205 ZW |
8558 | if (inst.operands[0].imm) |
8559 | inst.instruction |= 0x200; | |
a737bd4d NC |
8560 | } |
8561 | ||
8562 | static void | |
c19d1205 | 8563 | do_shift (void) |
a737bd4d | 8564 | { |
c19d1205 ZW |
8565 | unsigned int Rm = (inst.operands[1].present |
8566 | ? inst.operands[1].reg | |
8567 | : inst.operands[0].reg); | |
a737bd4d | 8568 | |
c19d1205 ZW |
8569 | inst.instruction |= inst.operands[0].reg << 12; |
8570 | inst.instruction |= Rm; | |
8571 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8572 | { |
c19d1205 ZW |
8573 | inst.instruction |= inst.operands[2].reg << 8; |
8574 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
8575 | /* PR 12854: Error on extraneous shifts. */ |
8576 | constraint (inst.operands[2].shifted, | |
8577 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
8578 | } |
8579 | else | |
c19d1205 | 8580 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8581 | } |
8582 | ||
09d92015 | 8583 | static void |
3eb17e6b | 8584 | do_smc (void) |
09d92015 | 8585 | { |
3eb17e6b | 8586 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8587 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8588 | } |
8589 | ||
90ec0d68 MGD |
8590 | static void |
8591 | do_hvc (void) | |
8592 | { | |
8593 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
8594 | inst.reloc.pc_rel = 0; | |
8595 | } | |
8596 | ||
09d92015 | 8597 | static void |
c19d1205 | 8598 | do_swi (void) |
09d92015 | 8599 | { |
c19d1205 ZW |
8600 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8601 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8602 | } |
8603 | ||
c19d1205 ZW |
8604 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8605 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8606 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8607 | Error if any register is R15. */ | |
e16bb312 | 8608 | |
c19d1205 ZW |
8609 | static void |
8610 | do_smla (void) | |
e16bb312 | 8611 | { |
c19d1205 ZW |
8612 | inst.instruction |= inst.operands[0].reg << 16; |
8613 | inst.instruction |= inst.operands[1].reg; | |
8614 | inst.instruction |= inst.operands[2].reg << 8; | |
8615 | inst.instruction |= inst.operands[3].reg << 12; | |
8616 | } | |
a737bd4d | 8617 | |
c19d1205 ZW |
8618 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8619 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8620 | Error if any register is R15. | |
8621 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8622 | |
c19d1205 ZW |
8623 | static void |
8624 | do_smlal (void) | |
8625 | { | |
8626 | inst.instruction |= inst.operands[0].reg << 12; | |
8627 | inst.instruction |= inst.operands[1].reg << 16; | |
8628 | inst.instruction |= inst.operands[2].reg; | |
8629 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8630 | |
c19d1205 ZW |
8631 | if (inst.operands[0].reg == inst.operands[1].reg) |
8632 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8633 | } | |
a737bd4d | 8634 | |
c19d1205 ZW |
8635 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8636 | SMULxy{cond} Rd,Rm,Rs | |
8637 | Error if any register is R15. */ | |
a737bd4d | 8638 | |
c19d1205 ZW |
8639 | static void |
8640 | do_smul (void) | |
8641 | { | |
8642 | inst.instruction |= inst.operands[0].reg << 16; | |
8643 | inst.instruction |= inst.operands[1].reg; | |
8644 | inst.instruction |= inst.operands[2].reg << 8; | |
8645 | } | |
a737bd4d | 8646 | |
b6702015 PB |
8647 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8648 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8649 | |
c19d1205 ZW |
8650 | static void |
8651 | do_srs (void) | |
8652 | { | |
b6702015 PB |
8653 | int reg; |
8654 | ||
8655 | if (inst.operands[0].present) | |
8656 | { | |
8657 | reg = inst.operands[0].reg; | |
fdfde340 | 8658 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8659 | } |
8660 | else | |
fdfde340 | 8661 | reg = REG_SP; |
b6702015 PB |
8662 | |
8663 | inst.instruction |= reg << 16; | |
8664 | inst.instruction |= inst.operands[1].imm; | |
8665 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8666 | inst.instruction |= WRITE_BACK; |
8667 | } | |
a737bd4d | 8668 | |
c19d1205 | 8669 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8670 | |
c19d1205 ZW |
8671 | static void |
8672 | do_strex (void) | |
8673 | { | |
8674 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8675 | || inst.operands[2].postind || inst.operands[2].writeback | |
8676 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8677 | || inst.operands[2].negative |
8678 | /* See comment in do_ldrex(). */ | |
8679 | || (inst.operands[2].reg == REG_PC), | |
8680 | BAD_ADDR_MODE); | |
a737bd4d | 8681 | |
c19d1205 ZW |
8682 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8683 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8684 | |
c19d1205 ZW |
8685 | constraint (inst.reloc.exp.X_op != O_constant |
8686 | || inst.reloc.exp.X_add_number != 0, | |
8687 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8688 | |
c19d1205 ZW |
8689 | inst.instruction |= inst.operands[0].reg << 12; |
8690 | inst.instruction |= inst.operands[1].reg; | |
8691 | inst.instruction |= inst.operands[2].reg << 16; | |
8692 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8693 | } |
8694 | ||
877807f8 NC |
8695 | static void |
8696 | do_t_strexbh (void) | |
8697 | { | |
8698 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8699 | || inst.operands[2].postind || inst.operands[2].writeback | |
8700 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
8701 | || inst.operands[2].negative, | |
8702 | BAD_ADDR_MODE); | |
8703 | ||
8704 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
8705 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
8706 | ||
8707 | do_rm_rd_rn (); | |
8708 | } | |
8709 | ||
e16bb312 | 8710 | static void |
c19d1205 | 8711 | do_strexd (void) |
e16bb312 | 8712 | { |
c19d1205 ZW |
8713 | constraint (inst.operands[1].reg % 2 != 0, |
8714 | _("even register required")); | |
8715 | constraint (inst.operands[2].present | |
8716 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8717 | _("can only store two consecutive registers")); | |
8718 | /* If op 2 were present and equal to PC, this function wouldn't | |
8719 | have been called in the first place. */ | |
8720 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8721 | |
c19d1205 ZW |
8722 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8723 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8724 | || inst.operands[0].reg == inst.operands[3].reg, | |
8725 | BAD_OVERLAP); | |
e16bb312 | 8726 | |
c19d1205 ZW |
8727 | inst.instruction |= inst.operands[0].reg << 12; |
8728 | inst.instruction |= inst.operands[1].reg; | |
8729 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8730 | } |
8731 | ||
c19d1205 ZW |
8732 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8733 | extends it to 32-bits, and adds the result to a value in another | |
8734 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8735 | before extracting the 16-bit value. | |
8736 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8737 | Condition defaults to COND_ALWAYS. | |
8738 | Error if any register uses R15. */ | |
8739 | ||
e16bb312 | 8740 | static void |
c19d1205 | 8741 | do_sxtah (void) |
e16bb312 | 8742 | { |
c19d1205 ZW |
8743 | inst.instruction |= inst.operands[0].reg << 12; |
8744 | inst.instruction |= inst.operands[1].reg << 16; | |
8745 | inst.instruction |= inst.operands[2].reg; | |
8746 | inst.instruction |= inst.operands[3].imm << 10; | |
8747 | } | |
e16bb312 | 8748 | |
c19d1205 | 8749 | /* ARM V6 SXTH. |
e16bb312 | 8750 | |
c19d1205 ZW |
8751 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8752 | Condition defaults to COND_ALWAYS. | |
8753 | Error if any register uses R15. */ | |
e16bb312 NC |
8754 | |
8755 | static void | |
c19d1205 | 8756 | do_sxth (void) |
e16bb312 | 8757 | { |
c19d1205 ZW |
8758 | inst.instruction |= inst.operands[0].reg << 12; |
8759 | inst.instruction |= inst.operands[1].reg; | |
8760 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8761 | } |
c19d1205 ZW |
8762 | \f |
8763 | /* VFP instructions. In a logical order: SP variant first, monad | |
8764 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8765 | |
8766 | static void | |
c19d1205 | 8767 | do_vfp_sp_monadic (void) |
e16bb312 | 8768 | { |
5287ad62 JB |
8769 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8770 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8771 | } |
8772 | ||
8773 | static void | |
c19d1205 | 8774 | do_vfp_sp_dyadic (void) |
e16bb312 | 8775 | { |
5287ad62 JB |
8776 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8777 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8778 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8779 | } |
8780 | ||
8781 | static void | |
c19d1205 | 8782 | do_vfp_sp_compare_z (void) |
e16bb312 | 8783 | { |
5287ad62 | 8784 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8785 | } |
8786 | ||
8787 | static void | |
c19d1205 | 8788 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8789 | { |
5287ad62 JB |
8790 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8791 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8792 | } |
8793 | ||
8794 | static void | |
c19d1205 | 8795 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8796 | { |
5287ad62 JB |
8797 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8798 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8799 | } |
8800 | ||
8801 | static void | |
c19d1205 | 8802 | do_vfp_reg_from_sp (void) |
e16bb312 | 8803 | { |
c19d1205 | 8804 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8805 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8806 | } |
8807 | ||
8808 | static void | |
c19d1205 | 8809 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8810 | { |
c19d1205 ZW |
8811 | constraint (inst.operands[2].imm != 2, |
8812 | _("only two consecutive VFP SP registers allowed here")); | |
8813 | inst.instruction |= inst.operands[0].reg << 12; | |
8814 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8815 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8816 | } |
8817 | ||
8818 | static void | |
c19d1205 | 8819 | do_vfp_sp_from_reg (void) |
e16bb312 | 8820 | { |
5287ad62 | 8821 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8822 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8823 | } |
8824 | ||
8825 | static void | |
c19d1205 | 8826 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8827 | { |
c19d1205 ZW |
8828 | constraint (inst.operands[0].imm != 2, |
8829 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8830 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8831 | inst.instruction |= inst.operands[1].reg << 12; |
8832 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8833 | } |
8834 | ||
8835 | static void | |
c19d1205 | 8836 | do_vfp_sp_ldst (void) |
e16bb312 | 8837 | { |
5287ad62 | 8838 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8839 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8840 | } |
8841 | ||
8842 | static void | |
c19d1205 | 8843 | do_vfp_dp_ldst (void) |
e16bb312 | 8844 | { |
5287ad62 | 8845 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8846 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8847 | } |
8848 | ||
c19d1205 | 8849 | |
e16bb312 | 8850 | static void |
c19d1205 | 8851 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8852 | { |
c19d1205 ZW |
8853 | if (inst.operands[0].writeback) |
8854 | inst.instruction |= WRITE_BACK; | |
8855 | else | |
8856 | constraint (ldstm_type != VFP_LDSTMIA, | |
8857 | _("this addressing mode requires base-register writeback")); | |
8858 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8859 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8860 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8861 | } |
8862 | ||
8863 | static void | |
c19d1205 | 8864 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8865 | { |
c19d1205 | 8866 | int count; |
e16bb312 | 8867 | |
c19d1205 ZW |
8868 | if (inst.operands[0].writeback) |
8869 | inst.instruction |= WRITE_BACK; | |
8870 | else | |
8871 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8872 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8873 | |
c19d1205 | 8874 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8875 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8876 | |
c19d1205 ZW |
8877 | count = inst.operands[1].imm << 1; |
8878 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8879 | count += 1; | |
e16bb312 | 8880 | |
c19d1205 | 8881 | inst.instruction |= count; |
e16bb312 NC |
8882 | } |
8883 | ||
8884 | static void | |
c19d1205 | 8885 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8886 | { |
c19d1205 | 8887 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8888 | } |
8889 | ||
8890 | static void | |
c19d1205 | 8891 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8892 | { |
c19d1205 | 8893 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8894 | } |
8895 | ||
8896 | static void | |
c19d1205 | 8897 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8898 | { |
c19d1205 | 8899 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8900 | } |
8901 | ||
8902 | static void | |
c19d1205 | 8903 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8904 | { |
c19d1205 | 8905 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8906 | } |
8907 | ||
8908 | static void | |
c19d1205 | 8909 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8910 | { |
c19d1205 ZW |
8911 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8912 | } | |
e16bb312 | 8913 | |
c19d1205 ZW |
8914 | static void |
8915 | do_vfp_xp_ldstmdb (void) | |
8916 | { | |
8917 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8918 | } |
5287ad62 JB |
8919 | |
8920 | static void | |
8921 | do_vfp_dp_rd_rm (void) | |
8922 | { | |
8923 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8924 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8925 | } | |
8926 | ||
8927 | static void | |
8928 | do_vfp_dp_rn_rd (void) | |
8929 | { | |
8930 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8931 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8932 | } | |
8933 | ||
8934 | static void | |
8935 | do_vfp_dp_rd_rn (void) | |
8936 | { | |
8937 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8938 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8939 | } | |
8940 | ||
8941 | static void | |
8942 | do_vfp_dp_rd_rn_rm (void) | |
8943 | { | |
8944 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8945 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8946 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8947 | } | |
8948 | ||
8949 | static void | |
8950 | do_vfp_dp_rd (void) | |
8951 | { | |
8952 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8953 | } | |
8954 | ||
8955 | static void | |
8956 | do_vfp_dp_rm_rd_rn (void) | |
8957 | { | |
8958 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8959 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8960 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8961 | } | |
8962 | ||
8963 | /* VFPv3 instructions. */ | |
8964 | static void | |
8965 | do_vfp_sp_const (void) | |
8966 | { | |
8967 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8968 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8969 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8970 | } |
8971 | ||
8972 | static void | |
8973 | do_vfp_dp_const (void) | |
8974 | { | |
8975 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8976 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8977 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8978 | } |
8979 | ||
8980 | static void | |
8981 | vfp_conv (int srcsize) | |
8982 | { | |
5f1af56b MGD |
8983 | int immbits = srcsize - inst.operands[1].imm; |
8984 | ||
fa94de6b RM |
8985 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
8986 | { | |
5f1af56b MGD |
8987 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
8988 | i.e. immbits must be in range 0 - 16. */ | |
8989 | inst.error = _("immediate value out of range, expected range [0, 16]"); | |
8990 | return; | |
8991 | } | |
fa94de6b | 8992 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
8993 | { |
8994 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
8995 | i.e. immbits must be in range 0 - 31. */ | |
8996 | inst.error = _("immediate value out of range, expected range [1, 32]"); | |
8997 | return; | |
8998 | } | |
8999 | ||
5287ad62 JB |
9000 | inst.instruction |= (immbits & 1) << 5; |
9001 | inst.instruction |= (immbits >> 1); | |
9002 | } | |
9003 | ||
9004 | static void | |
9005 | do_vfp_sp_conv_16 (void) | |
9006 | { | |
9007 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9008 | vfp_conv (16); | |
9009 | } | |
9010 | ||
9011 | static void | |
9012 | do_vfp_dp_conv_16 (void) | |
9013 | { | |
9014 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9015 | vfp_conv (16); | |
9016 | } | |
9017 | ||
9018 | static void | |
9019 | do_vfp_sp_conv_32 (void) | |
9020 | { | |
9021 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9022 | vfp_conv (32); | |
9023 | } | |
9024 | ||
9025 | static void | |
9026 | do_vfp_dp_conv_32 (void) | |
9027 | { | |
9028 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9029 | vfp_conv (32); | |
9030 | } | |
c19d1205 ZW |
9031 | \f |
9032 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 9033 | |
c19d1205 ZW |
9034 | static void |
9035 | do_fpa_cmp (void) | |
9036 | { | |
9037 | inst.instruction |= inst.operands[0].reg << 16; | |
9038 | inst.instruction |= inst.operands[1].reg; | |
9039 | } | |
b99bd4ef NC |
9040 | |
9041 | static void | |
c19d1205 | 9042 | do_fpa_ldmstm (void) |
b99bd4ef | 9043 | { |
c19d1205 ZW |
9044 | inst.instruction |= inst.operands[0].reg << 12; |
9045 | switch (inst.operands[1].imm) | |
9046 | { | |
9047 | case 1: inst.instruction |= CP_T_X; break; | |
9048 | case 2: inst.instruction |= CP_T_Y; break; | |
9049 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
9050 | case 4: break; | |
9051 | default: abort (); | |
9052 | } | |
b99bd4ef | 9053 | |
c19d1205 ZW |
9054 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
9055 | { | |
9056 | /* The instruction specified "ea" or "fd", so we can only accept | |
9057 | [Rn]{!}. The instruction does not really support stacking or | |
9058 | unstacking, so we have to emulate these by setting appropriate | |
9059 | bits and offsets. */ | |
9060 | constraint (inst.reloc.exp.X_op != O_constant | |
9061 | || inst.reloc.exp.X_add_number != 0, | |
9062 | _("this instruction does not support indexing")); | |
b99bd4ef | 9063 | |
c19d1205 ZW |
9064 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
9065 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 9066 | |
c19d1205 ZW |
9067 | if (!(inst.instruction & INDEX_UP)) |
9068 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 9069 | |
c19d1205 ZW |
9070 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
9071 | { | |
9072 | inst.operands[2].preind = 0; | |
9073 | inst.operands[2].postind = 1; | |
9074 | } | |
9075 | } | |
b99bd4ef | 9076 | |
c19d1205 | 9077 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 9078 | } |
c19d1205 ZW |
9079 | \f |
9080 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 9081 | |
c19d1205 ZW |
9082 | static void |
9083 | do_iwmmxt_tandorc (void) | |
9084 | { | |
9085 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
9086 | } | |
b99bd4ef | 9087 | |
c19d1205 ZW |
9088 | static void |
9089 | do_iwmmxt_textrc (void) | |
9090 | { | |
9091 | inst.instruction |= inst.operands[0].reg << 12; | |
9092 | inst.instruction |= inst.operands[1].imm; | |
9093 | } | |
b99bd4ef NC |
9094 | |
9095 | static void | |
c19d1205 | 9096 | do_iwmmxt_textrm (void) |
b99bd4ef | 9097 | { |
c19d1205 ZW |
9098 | inst.instruction |= inst.operands[0].reg << 12; |
9099 | inst.instruction |= inst.operands[1].reg << 16; | |
9100 | inst.instruction |= inst.operands[2].imm; | |
9101 | } | |
b99bd4ef | 9102 | |
c19d1205 ZW |
9103 | static void |
9104 | do_iwmmxt_tinsr (void) | |
9105 | { | |
9106 | inst.instruction |= inst.operands[0].reg << 16; | |
9107 | inst.instruction |= inst.operands[1].reg << 12; | |
9108 | inst.instruction |= inst.operands[2].imm; | |
9109 | } | |
b99bd4ef | 9110 | |
c19d1205 ZW |
9111 | static void |
9112 | do_iwmmxt_tmia (void) | |
9113 | { | |
9114 | inst.instruction |= inst.operands[0].reg << 5; | |
9115 | inst.instruction |= inst.operands[1].reg; | |
9116 | inst.instruction |= inst.operands[2].reg << 12; | |
9117 | } | |
b99bd4ef | 9118 | |
c19d1205 ZW |
9119 | static void |
9120 | do_iwmmxt_waligni (void) | |
9121 | { | |
9122 | inst.instruction |= inst.operands[0].reg << 12; | |
9123 | inst.instruction |= inst.operands[1].reg << 16; | |
9124 | inst.instruction |= inst.operands[2].reg; | |
9125 | inst.instruction |= inst.operands[3].imm << 20; | |
9126 | } | |
b99bd4ef | 9127 | |
2d447fca JM |
9128 | static void |
9129 | do_iwmmxt_wmerge (void) | |
9130 | { | |
9131 | inst.instruction |= inst.operands[0].reg << 12; | |
9132 | inst.instruction |= inst.operands[1].reg << 16; | |
9133 | inst.instruction |= inst.operands[2].reg; | |
9134 | inst.instruction |= inst.operands[3].imm << 21; | |
9135 | } | |
9136 | ||
c19d1205 ZW |
9137 | static void |
9138 | do_iwmmxt_wmov (void) | |
9139 | { | |
9140 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
9141 | inst.instruction |= inst.operands[0].reg << 12; | |
9142 | inst.instruction |= inst.operands[1].reg << 16; | |
9143 | inst.instruction |= inst.operands[1].reg; | |
9144 | } | |
b99bd4ef | 9145 | |
c19d1205 ZW |
9146 | static void |
9147 | do_iwmmxt_wldstbh (void) | |
9148 | { | |
8f06b2d8 | 9149 | int reloc; |
c19d1205 | 9150 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
9151 | if (thumb_mode) |
9152 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
9153 | else | |
9154 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
9155 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
9156 | } |
9157 | ||
c19d1205 ZW |
9158 | static void |
9159 | do_iwmmxt_wldstw (void) | |
9160 | { | |
9161 | /* RIWR_RIWC clears .isreg for a control register. */ | |
9162 | if (!inst.operands[0].isreg) | |
9163 | { | |
9164 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
9165 | inst.instruction |= 0xf0000000; | |
9166 | } | |
b99bd4ef | 9167 | |
c19d1205 ZW |
9168 | inst.instruction |= inst.operands[0].reg << 12; |
9169 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
9170 | } | |
b99bd4ef NC |
9171 | |
9172 | static void | |
c19d1205 | 9173 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9174 | { |
c19d1205 | 9175 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9176 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9177 | && inst.operands[1].immisreg) | |
9178 | { | |
9179 | inst.instruction &= ~0x1a000ff; | |
9180 | inst.instruction |= (0xf << 28); | |
9181 | if (inst.operands[1].preind) | |
9182 | inst.instruction |= PRE_INDEX; | |
9183 | if (!inst.operands[1].negative) | |
9184 | inst.instruction |= INDEX_UP; | |
9185 | if (inst.operands[1].writeback) | |
9186 | inst.instruction |= WRITE_BACK; | |
9187 | inst.instruction |= inst.operands[1].reg << 16; | |
9188 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9189 | inst.instruction |= inst.operands[1].imm; | |
9190 | } | |
9191 | else | |
9192 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9193 | } |
b99bd4ef | 9194 | |
c19d1205 ZW |
9195 | static void |
9196 | do_iwmmxt_wshufh (void) | |
9197 | { | |
9198 | inst.instruction |= inst.operands[0].reg << 12; | |
9199 | inst.instruction |= inst.operands[1].reg << 16; | |
9200 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9201 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9202 | } | |
b99bd4ef | 9203 | |
c19d1205 ZW |
9204 | static void |
9205 | do_iwmmxt_wzero (void) | |
9206 | { | |
9207 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
9208 | inst.instruction |= inst.operands[0].reg; | |
9209 | inst.instruction |= inst.operands[0].reg << 12; | |
9210 | inst.instruction |= inst.operands[0].reg << 16; | |
9211 | } | |
2d447fca JM |
9212 | |
9213 | static void | |
9214 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
9215 | { | |
9216 | if (inst.operands[2].isreg) | |
9217 | do_rd_rn_rm (); | |
9218 | else { | |
9219 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
9220 | _("immediate operand requires iWMMXt2")); | |
9221 | do_rd_rn (); | |
9222 | if (inst.operands[2].imm == 0) | |
9223 | { | |
9224 | switch ((inst.instruction >> 20) & 0xf) | |
9225 | { | |
9226 | case 4: | |
9227 | case 5: | |
9228 | case 6: | |
5f4273c7 | 9229 | case 7: |
2d447fca JM |
9230 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
9231 | inst.operands[2].imm = 16; | |
9232 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
9233 | break; | |
9234 | case 8: | |
9235 | case 9: | |
9236 | case 10: | |
9237 | case 11: | |
9238 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
9239 | inst.operands[2].imm = 32; | |
9240 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
9241 | break; | |
9242 | case 12: | |
9243 | case 13: | |
9244 | case 14: | |
9245 | case 15: | |
9246 | { | |
9247 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
9248 | unsigned long wrn; | |
9249 | wrn = (inst.instruction >> 16) & 0xf; | |
9250 | inst.instruction &= 0xff0fff0f; | |
9251 | inst.instruction |= wrn; | |
9252 | /* Bail out here; the instruction is now assembled. */ | |
9253 | return; | |
9254 | } | |
9255 | } | |
9256 | } | |
9257 | /* Map 32 -> 0, etc. */ | |
9258 | inst.operands[2].imm &= 0x1f; | |
9259 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
9260 | } | |
9261 | } | |
c19d1205 ZW |
9262 | \f |
9263 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
9264 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 9265 | |
c19d1205 | 9266 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 9267 | |
c19d1205 ZW |
9268 | static void |
9269 | do_mav_triple (void) | |
9270 | { | |
9271 | inst.instruction |= inst.operands[0].reg << 16; | |
9272 | inst.instruction |= inst.operands[1].reg; | |
9273 | inst.instruction |= inst.operands[2].reg << 12; | |
9274 | } | |
b99bd4ef | 9275 | |
c19d1205 ZW |
9276 | /* Insns like "foo W,X,Y,Z". |
9277 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 9278 | |
c19d1205 ZW |
9279 | static void |
9280 | do_mav_quad (void) | |
9281 | { | |
9282 | inst.instruction |= inst.operands[0].reg << 5; | |
9283 | inst.instruction |= inst.operands[1].reg << 12; | |
9284 | inst.instruction |= inst.operands[2].reg << 16; | |
9285 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
9286 | } |
9287 | ||
c19d1205 ZW |
9288 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
9289 | static void | |
9290 | do_mav_dspsc (void) | |
a737bd4d | 9291 | { |
c19d1205 ZW |
9292 | inst.instruction |= inst.operands[1].reg << 12; |
9293 | } | |
a737bd4d | 9294 | |
c19d1205 ZW |
9295 | /* Maverick shift immediate instructions. |
9296 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
9297 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 9298 | |
c19d1205 ZW |
9299 | static void |
9300 | do_mav_shift (void) | |
9301 | { | |
9302 | int imm = inst.operands[2].imm; | |
a737bd4d | 9303 | |
c19d1205 ZW |
9304 | inst.instruction |= inst.operands[0].reg << 12; |
9305 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 9306 | |
c19d1205 ZW |
9307 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
9308 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
9309 | Bit 4 should be 0. */ | |
9310 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 9311 | |
c19d1205 ZW |
9312 | inst.instruction |= imm; |
9313 | } | |
9314 | \f | |
9315 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 9316 | |
c19d1205 ZW |
9317 | /* Xscale multiply-accumulate (argument parse) |
9318 | MIAcc acc0,Rm,Rs | |
9319 | MIAPHcc acc0,Rm,Rs | |
9320 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 9321 | |
c19d1205 ZW |
9322 | static void |
9323 | do_xsc_mia (void) | |
9324 | { | |
9325 | inst.instruction |= inst.operands[1].reg; | |
9326 | inst.instruction |= inst.operands[2].reg << 12; | |
9327 | } | |
a737bd4d | 9328 | |
c19d1205 | 9329 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9330 | |
c19d1205 | 9331 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9332 | |
c19d1205 ZW |
9333 | static void |
9334 | do_xsc_mar (void) | |
9335 | { | |
9336 | inst.instruction |= inst.operands[1].reg << 12; | |
9337 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9338 | } |
9339 | ||
c19d1205 | 9340 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9341 | |
c19d1205 | 9342 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9343 | |
9344 | static void | |
c19d1205 | 9345 | do_xsc_mra (void) |
b99bd4ef | 9346 | { |
c19d1205 ZW |
9347 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9348 | inst.instruction |= inst.operands[0].reg << 12; | |
9349 | inst.instruction |= inst.operands[1].reg << 16; | |
9350 | } | |
9351 | \f | |
9352 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9353 | |
c19d1205 ZW |
9354 | /* inst.operands[i] is a shifted-register operand; encode |
9355 | it into inst.instruction in the format used by Thumb32. */ | |
9356 | ||
9357 | static void | |
9358 | encode_thumb32_shifted_operand (int i) | |
9359 | { | |
9360 | unsigned int value = inst.reloc.exp.X_add_number; | |
9361 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9362 | |
9c3c69f2 PB |
9363 | constraint (inst.operands[i].immisreg, |
9364 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9365 | inst.instruction |= inst.operands[i].reg; |
9366 | if (shift == SHIFT_RRX) | |
9367 | inst.instruction |= SHIFT_ROR << 4; | |
9368 | else | |
b99bd4ef | 9369 | { |
c19d1205 ZW |
9370 | constraint (inst.reloc.exp.X_op != O_constant, |
9371 | _("expression too complex")); | |
9372 | ||
9373 | constraint (value > 32 | |
9374 | || (value == 32 && (shift == SHIFT_LSL | |
9375 | || shift == SHIFT_ROR)), | |
9376 | _("shift expression is too large")); | |
9377 | ||
9378 | if (value == 0) | |
9379 | shift = SHIFT_LSL; | |
9380 | else if (value == 32) | |
9381 | value = 0; | |
9382 | ||
9383 | inst.instruction |= shift << 4; | |
9384 | inst.instruction |= (value & 0x1c) << 10; | |
9385 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9386 | } |
c19d1205 | 9387 | } |
b99bd4ef | 9388 | |
b99bd4ef | 9389 | |
c19d1205 ZW |
9390 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9391 | Thumb32 format load or store instruction. Reject forms that cannot | |
9392 | be used with such instructions. If is_t is true, reject forms that | |
9393 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9394 | that cannot be used with a D instruction. If it is a store insn, |
9395 | reject PC in Rn. */ | |
b99bd4ef | 9396 | |
c19d1205 ZW |
9397 | static void |
9398 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9399 | { | |
5be8be5d | 9400 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9401 | |
9402 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9403 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9404 | |
c19d1205 ZW |
9405 | inst.instruction |= inst.operands[i].reg << 16; |
9406 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9407 | { |
5be8be5d | 9408 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9409 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9410 | constraint (inst.operands[i].negative, | |
9411 | _("Thumb does not support negative register indexing")); | |
9412 | constraint (inst.operands[i].postind, | |
9413 | _("Thumb does not support register post-indexing")); | |
9414 | constraint (inst.operands[i].writeback, | |
9415 | _("Thumb does not support register indexing with writeback")); | |
9416 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
9417 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 9418 | |
f40d1643 | 9419 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 9420 | if (inst.operands[i].shifted) |
b99bd4ef | 9421 | { |
c19d1205 ZW |
9422 | constraint (inst.reloc.exp.X_op != O_constant, |
9423 | _("expression too complex")); | |
9c3c69f2 PB |
9424 | constraint (inst.reloc.exp.X_add_number < 0 |
9425 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 9426 | _("shift out of range")); |
9c3c69f2 | 9427 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
9428 | } |
9429 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9430 | } | |
9431 | else if (inst.operands[i].preind) | |
9432 | { | |
5be8be5d | 9433 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 9434 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 9435 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
9436 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
9437 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
9438 | |
9439 | if (is_d) | |
9440 | { | |
9441 | inst.instruction |= 0x01000000; | |
9442 | if (inst.operands[i].writeback) | |
9443 | inst.instruction |= 0x00200000; | |
b99bd4ef | 9444 | } |
c19d1205 | 9445 | else |
b99bd4ef | 9446 | { |
c19d1205 ZW |
9447 | inst.instruction |= 0x00000c00; |
9448 | if (inst.operands[i].writeback) | |
9449 | inst.instruction |= 0x00000100; | |
b99bd4ef | 9450 | } |
c19d1205 | 9451 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 9452 | } |
c19d1205 | 9453 | else if (inst.operands[i].postind) |
b99bd4ef | 9454 | { |
9c2799c2 | 9455 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
9456 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
9457 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
9458 | ||
9459 | if (is_d) | |
9460 | inst.instruction |= 0x00200000; | |
9461 | else | |
9462 | inst.instruction |= 0x00000900; | |
9463 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
9464 | } | |
9465 | else /* unindexed - only for coprocessor */ | |
9466 | inst.error = _("instruction does not accept unindexed addressing"); | |
9467 | } | |
9468 | ||
9469 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
9470 | encodings (the latter only in post-V6T2 cores). The index is the | |
9471 | value used in the insns table below. When there is more than one | |
9472 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
9473 | holds variant (1). |
9474 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 9475 | #define T16_32_TAB \ |
21d799b5 NC |
9476 | X(_adc, 4140, eb400000), \ |
9477 | X(_adcs, 4140, eb500000), \ | |
9478 | X(_add, 1c00, eb000000), \ | |
9479 | X(_adds, 1c00, eb100000), \ | |
9480 | X(_addi, 0000, f1000000), \ | |
9481 | X(_addis, 0000, f1100000), \ | |
9482 | X(_add_pc,000f, f20f0000), \ | |
9483 | X(_add_sp,000d, f10d0000), \ | |
9484 | X(_adr, 000f, f20f0000), \ | |
9485 | X(_and, 4000, ea000000), \ | |
9486 | X(_ands, 4000, ea100000), \ | |
9487 | X(_asr, 1000, fa40f000), \ | |
9488 | X(_asrs, 1000, fa50f000), \ | |
9489 | X(_b, e000, f000b000), \ | |
9490 | X(_bcond, d000, f0008000), \ | |
9491 | X(_bic, 4380, ea200000), \ | |
9492 | X(_bics, 4380, ea300000), \ | |
9493 | X(_cmn, 42c0, eb100f00), \ | |
9494 | X(_cmp, 2800, ebb00f00), \ | |
9495 | X(_cpsie, b660, f3af8400), \ | |
9496 | X(_cpsid, b670, f3af8600), \ | |
9497 | X(_cpy, 4600, ea4f0000), \ | |
9498 | X(_dec_sp,80dd, f1ad0d00), \ | |
9499 | X(_eor, 4040, ea800000), \ | |
9500 | X(_eors, 4040, ea900000), \ | |
9501 | X(_inc_sp,00dd, f10d0d00), \ | |
9502 | X(_ldmia, c800, e8900000), \ | |
9503 | X(_ldr, 6800, f8500000), \ | |
9504 | X(_ldrb, 7800, f8100000), \ | |
9505 | X(_ldrh, 8800, f8300000), \ | |
9506 | X(_ldrsb, 5600, f9100000), \ | |
9507 | X(_ldrsh, 5e00, f9300000), \ | |
9508 | X(_ldr_pc,4800, f85f0000), \ | |
9509 | X(_ldr_pc2,4800, f85f0000), \ | |
9510 | X(_ldr_sp,9800, f85d0000), \ | |
9511 | X(_lsl, 0000, fa00f000), \ | |
9512 | X(_lsls, 0000, fa10f000), \ | |
9513 | X(_lsr, 0800, fa20f000), \ | |
9514 | X(_lsrs, 0800, fa30f000), \ | |
9515 | X(_mov, 2000, ea4f0000), \ | |
9516 | X(_movs, 2000, ea5f0000), \ | |
9517 | X(_mul, 4340, fb00f000), \ | |
9518 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
9519 | X(_mvn, 43c0, ea6f0000), \ | |
9520 | X(_mvns, 43c0, ea7f0000), \ | |
9521 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
9522 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
9523 | X(_orr, 4300, ea400000), \ | |
9524 | X(_orrs, 4300, ea500000), \ | |
9525 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
9526 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
9527 | X(_rev, ba00, fa90f080), \ | |
9528 | X(_rev16, ba40, fa90f090), \ | |
9529 | X(_revsh, bac0, fa90f0b0), \ | |
9530 | X(_ror, 41c0, fa60f000), \ | |
9531 | X(_rors, 41c0, fa70f000), \ | |
9532 | X(_sbc, 4180, eb600000), \ | |
9533 | X(_sbcs, 4180, eb700000), \ | |
9534 | X(_stmia, c000, e8800000), \ | |
9535 | X(_str, 6000, f8400000), \ | |
9536 | X(_strb, 7000, f8000000), \ | |
9537 | X(_strh, 8000, f8200000), \ | |
9538 | X(_str_sp,9000, f84d0000), \ | |
9539 | X(_sub, 1e00, eba00000), \ | |
9540 | X(_subs, 1e00, ebb00000), \ | |
9541 | X(_subi, 8000, f1a00000), \ | |
9542 | X(_subis, 8000, f1b00000), \ | |
9543 | X(_sxtb, b240, fa4ff080), \ | |
9544 | X(_sxth, b200, fa0ff080), \ | |
9545 | X(_tst, 4200, ea100f00), \ | |
9546 | X(_uxtb, b2c0, fa5ff080), \ | |
9547 | X(_uxth, b280, fa1ff080), \ | |
9548 | X(_nop, bf00, f3af8000), \ | |
9549 | X(_yield, bf10, f3af8001), \ | |
9550 | X(_wfe, bf20, f3af8002), \ | |
9551 | X(_wfi, bf30, f3af8003), \ | |
53c4b28b MGD |
9552 | X(_sev, bf40, f3af8004), \ |
9553 | X(_sevl, bf50, f3af8005) | |
c19d1205 ZW |
9554 | |
9555 | /* To catch errors in encoding functions, the codes are all offset by | |
9556 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
9557 | as 16-bit instructions. */ | |
21d799b5 | 9558 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
9559 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
9560 | #undef X | |
9561 | ||
9562 | #define X(a,b,c) 0x##b | |
9563 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
9564 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
9565 | #undef X | |
9566 | ||
9567 | #define X(a,b,c) 0x##c | |
9568 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
9569 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
9570 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
9571 | #undef X |
9572 | #undef T16_32_TAB | |
9573 | ||
9574 | /* Thumb instruction encoders, in alphabetical order. */ | |
9575 | ||
92e90b6e | 9576 | /* ADDW or SUBW. */ |
c921be7d | 9577 | |
92e90b6e PB |
9578 | static void |
9579 | do_t_add_sub_w (void) | |
9580 | { | |
9581 | int Rd, Rn; | |
9582 | ||
9583 | Rd = inst.operands[0].reg; | |
9584 | Rn = inst.operands[1].reg; | |
9585 | ||
539d4391 NC |
9586 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
9587 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
9588 | if (Rn == REG_SP) | |
9589 | constraint (Rd == REG_PC, BAD_PC); | |
9590 | else | |
9591 | reject_bad_reg (Rd); | |
fdfde340 | 9592 | |
92e90b6e PB |
9593 | inst.instruction |= (Rn << 16) | (Rd << 8); |
9594 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9595 | } | |
9596 | ||
c19d1205 ZW |
9597 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9598 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9599 | ||
9600 | static void | |
9601 | do_t_add_sub (void) | |
9602 | { | |
9603 | int Rd, Rs, Rn; | |
9604 | ||
9605 | Rd = inst.operands[0].reg; | |
9606 | Rs = (inst.operands[1].present | |
9607 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9608 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9609 | ||
e07e6e58 NC |
9610 | if (Rd == REG_PC) |
9611 | set_it_insn_type_last (); | |
9612 | ||
c19d1205 ZW |
9613 | if (unified_syntax) |
9614 | { | |
0110f2b8 PB |
9615 | bfd_boolean flags; |
9616 | bfd_boolean narrow; | |
9617 | int opcode; | |
9618 | ||
9619 | flags = (inst.instruction == T_MNEM_adds | |
9620 | || inst.instruction == T_MNEM_subs); | |
9621 | if (flags) | |
e07e6e58 | 9622 | narrow = !in_it_block (); |
0110f2b8 | 9623 | else |
e07e6e58 | 9624 | narrow = in_it_block (); |
c19d1205 | 9625 | if (!inst.operands[2].isreg) |
b99bd4ef | 9626 | { |
16805f35 PB |
9627 | int add; |
9628 | ||
fdfde340 JM |
9629 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9630 | ||
16805f35 PB |
9631 | add = (inst.instruction == T_MNEM_add |
9632 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9633 | opcode = 0; |
9634 | if (inst.size_req != 4) | |
9635 | { | |
0110f2b8 PB |
9636 | /* Attempt to use a narrow opcode, with relaxation if |
9637 | appropriate. */ | |
9638 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9639 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9640 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9641 | opcode = T_MNEM_add_sp; | |
9642 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9643 | opcode = T_MNEM_add_pc; | |
9644 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9645 | { | |
9646 | if (flags) | |
9647 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9648 | else | |
9649 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9650 | } | |
9651 | if (opcode) | |
9652 | { | |
9653 | inst.instruction = THUMB_OP16(opcode); | |
9654 | inst.instruction |= (Rd << 4) | Rs; | |
9655 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9656 | if (inst.size_req != 2) | |
9657 | inst.relax = opcode; | |
9658 | } | |
9659 | else | |
9660 | constraint (inst.size_req == 2, BAD_HIREG); | |
9661 | } | |
9662 | if (inst.size_req == 4 | |
9663 | || (inst.size_req != 2 && !opcode)) | |
9664 | { | |
efd81785 PB |
9665 | if (Rd == REG_PC) |
9666 | { | |
fdfde340 | 9667 | constraint (add, BAD_PC); |
efd81785 PB |
9668 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9669 | _("only SUBS PC, LR, #const allowed")); | |
9670 | constraint (inst.reloc.exp.X_op != O_constant, | |
9671 | _("expression too complex")); | |
9672 | constraint (inst.reloc.exp.X_add_number < 0 | |
9673 | || inst.reloc.exp.X_add_number > 0xff, | |
9674 | _("immediate value out of range")); | |
9675 | inst.instruction = T2_SUBS_PC_LR | |
9676 | | inst.reloc.exp.X_add_number; | |
9677 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9678 | return; | |
9679 | } | |
9680 | else if (Rs == REG_PC) | |
16805f35 PB |
9681 | { |
9682 | /* Always use addw/subw. */ | |
9683 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9684 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9685 | } | |
9686 | else | |
9687 | { | |
9688 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9689 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9690 | | 0x10000000; | |
9691 | if (flags) | |
9692 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9693 | else | |
9694 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9695 | } | |
dc4503c6 PB |
9696 | inst.instruction |= Rd << 8; |
9697 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9698 | } |
b99bd4ef | 9699 | } |
c19d1205 ZW |
9700 | else |
9701 | { | |
5f4cb198 NC |
9702 | unsigned int value = inst.reloc.exp.X_add_number; |
9703 | unsigned int shift = inst.operands[2].shift_kind; | |
9704 | ||
c19d1205 ZW |
9705 | Rn = inst.operands[2].reg; |
9706 | /* See if we can do this with a 16-bit instruction. */ | |
9707 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9708 | { | |
e27ec89e PB |
9709 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9710 | narrow = FALSE; | |
9711 | ||
9712 | if (narrow) | |
c19d1205 | 9713 | { |
e27ec89e PB |
9714 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9715 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9716 | ? T_OPCODE_ADD_R3 |
9717 | : T_OPCODE_SUB_R3); | |
9718 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9719 | return; | |
9720 | } | |
b99bd4ef | 9721 | |
7e806470 | 9722 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9723 | { |
7e806470 PB |
9724 | /* Thumb-1 cores (except v6-M) require at least one high |
9725 | register in a narrow non flag setting add. */ | |
9726 | if (Rd > 7 || Rn > 7 | |
9727 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9728 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9729 | { |
7e806470 PB |
9730 | if (Rd == Rn) |
9731 | { | |
9732 | Rn = Rs; | |
9733 | Rs = Rd; | |
9734 | } | |
c19d1205 ZW |
9735 | inst.instruction = T_OPCODE_ADD_HI; |
9736 | inst.instruction |= (Rd & 8) << 4; | |
9737 | inst.instruction |= (Rd & 7); | |
9738 | inst.instruction |= Rn << 3; | |
9739 | return; | |
9740 | } | |
c19d1205 ZW |
9741 | } |
9742 | } | |
c921be7d | 9743 | |
fdfde340 JM |
9744 | constraint (Rd == REG_PC, BAD_PC); |
9745 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9746 | constraint (Rs == REG_PC, BAD_PC); | |
9747 | reject_bad_reg (Rn); | |
9748 | ||
c19d1205 ZW |
9749 | /* If we get here, it can't be done in 16 bits. */ |
9750 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9751 | _("shift must be constant")); | |
9752 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9753 | inst.instruction |= Rd << 8; | |
9754 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
9755 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
9756 | _("shift value over 3 not allowed in thumb mode")); | |
9757 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
9758 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
9759 | encode_thumb32_shifted_operand (2); |
9760 | } | |
9761 | } | |
9762 | else | |
9763 | { | |
9764 | constraint (inst.instruction == T_MNEM_adds | |
9765 | || inst.instruction == T_MNEM_subs, | |
9766 | BAD_THUMB32); | |
b99bd4ef | 9767 | |
c19d1205 | 9768 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9769 | { |
c19d1205 ZW |
9770 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9771 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9772 | BAD_HIREG); | |
9773 | ||
9774 | inst.instruction = (inst.instruction == T_MNEM_add | |
9775 | ? 0x0000 : 0x8000); | |
9776 | inst.instruction |= (Rd << 4) | Rs; | |
9777 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9778 | return; |
9779 | } | |
9780 | ||
c19d1205 ZW |
9781 | Rn = inst.operands[2].reg; |
9782 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9783 | |
c19d1205 ZW |
9784 | /* We now have Rd, Rs, and Rn set to registers. */ |
9785 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9786 | { |
c19d1205 ZW |
9787 | /* Can't do this for SUB. */ |
9788 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9789 | inst.instruction = T_OPCODE_ADD_HI; | |
9790 | inst.instruction |= (Rd & 8) << 4; | |
9791 | inst.instruction |= (Rd & 7); | |
9792 | if (Rs == Rd) | |
9793 | inst.instruction |= Rn << 3; | |
9794 | else if (Rn == Rd) | |
9795 | inst.instruction |= Rs << 3; | |
9796 | else | |
9797 | constraint (1, _("dest must overlap one source register")); | |
9798 | } | |
9799 | else | |
9800 | { | |
9801 | inst.instruction = (inst.instruction == T_MNEM_add | |
9802 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9803 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9804 | } |
b99bd4ef | 9805 | } |
b99bd4ef NC |
9806 | } |
9807 | ||
c19d1205 ZW |
9808 | static void |
9809 | do_t_adr (void) | |
9810 | { | |
fdfde340 JM |
9811 | unsigned Rd; |
9812 | ||
9813 | Rd = inst.operands[0].reg; | |
9814 | reject_bad_reg (Rd); | |
9815 | ||
9816 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9817 | { |
9818 | /* Defer to section relaxation. */ | |
9819 | inst.relax = inst.instruction; | |
9820 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9821 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9822 | } |
9823 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9824 | { |
0110f2b8 | 9825 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9826 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9827 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9828 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9829 | inst.reloc.pc_rel = 1; | |
9830 | } | |
9831 | else | |
9832 | { | |
0110f2b8 | 9833 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9834 | inst.instruction = THUMB_OP16 (inst.instruction); |
9835 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9836 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9837 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9838 | |
fdfde340 | 9839 | inst.instruction |= Rd << 4; |
e9f89963 | 9840 | } |
c19d1205 | 9841 | } |
b99bd4ef | 9842 | |
c19d1205 ZW |
9843 | /* Arithmetic instructions for which there is just one 16-bit |
9844 | instruction encoding, and it allows only two low registers. | |
9845 | For maximal compatibility with ARM syntax, we allow three register | |
9846 | operands even when Thumb-32 instructions are not available, as long | |
9847 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9848 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9849 | static void |
c19d1205 | 9850 | do_t_arit3 (void) |
b99bd4ef | 9851 | { |
c19d1205 | 9852 | int Rd, Rs, Rn; |
b99bd4ef | 9853 | |
c19d1205 ZW |
9854 | Rd = inst.operands[0].reg; |
9855 | Rs = (inst.operands[1].present | |
9856 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9857 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9858 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9859 | |
fdfde340 JM |
9860 | reject_bad_reg (Rd); |
9861 | reject_bad_reg (Rs); | |
9862 | if (inst.operands[2].isreg) | |
9863 | reject_bad_reg (Rn); | |
9864 | ||
c19d1205 | 9865 | if (unified_syntax) |
b99bd4ef | 9866 | { |
c19d1205 ZW |
9867 | if (!inst.operands[2].isreg) |
9868 | { | |
9869 | /* For an immediate, we always generate a 32-bit opcode; | |
9870 | section relaxation will shrink it later if possible. */ | |
9871 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9872 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9873 | inst.instruction |= Rd << 8; | |
9874 | inst.instruction |= Rs << 16; | |
9875 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9876 | } | |
9877 | else | |
9878 | { | |
e27ec89e PB |
9879 | bfd_boolean narrow; |
9880 | ||
c19d1205 | 9881 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9882 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9883 | narrow = !in_it_block (); |
e27ec89e | 9884 | else |
e07e6e58 | 9885 | narrow = in_it_block (); |
e27ec89e PB |
9886 | |
9887 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9888 | narrow = FALSE; | |
9889 | if (inst.operands[2].shifted) | |
9890 | narrow = FALSE; | |
9891 | if (inst.size_req == 4) | |
9892 | narrow = FALSE; | |
9893 | ||
9894 | if (narrow | |
c19d1205 ZW |
9895 | && Rd == Rs) |
9896 | { | |
9897 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9898 | inst.instruction |= Rd; | |
9899 | inst.instruction |= Rn << 3; | |
9900 | return; | |
9901 | } | |
b99bd4ef | 9902 | |
c19d1205 ZW |
9903 | /* If we get here, it can't be done in 16 bits. */ |
9904 | constraint (inst.operands[2].shifted | |
9905 | && inst.operands[2].immisreg, | |
9906 | _("shift must be constant")); | |
9907 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9908 | inst.instruction |= Rd << 8; | |
9909 | inst.instruction |= Rs << 16; | |
9910 | encode_thumb32_shifted_operand (2); | |
9911 | } | |
a737bd4d | 9912 | } |
c19d1205 | 9913 | else |
b99bd4ef | 9914 | { |
c19d1205 ZW |
9915 | /* On its face this is a lie - the instruction does set the |
9916 | flags. However, the only supported mnemonic in this mode | |
9917 | says it doesn't. */ | |
9918 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9919 | |
c19d1205 ZW |
9920 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9921 | _("unshifted register required")); | |
9922 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9923 | constraint (Rd != Rs, | |
9924 | _("dest and source1 must be the same register")); | |
a737bd4d | 9925 | |
c19d1205 ZW |
9926 | inst.instruction = THUMB_OP16 (inst.instruction); |
9927 | inst.instruction |= Rd; | |
9928 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9929 | } |
a737bd4d | 9930 | } |
b99bd4ef | 9931 | |
c19d1205 ZW |
9932 | /* Similarly, but for instructions where the arithmetic operation is |
9933 | commutative, so we can allow either of them to be different from | |
9934 | the destination operand in a 16-bit instruction. For instance, all | |
9935 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9936 | accepted. */ | |
9937 | static void | |
9938 | do_t_arit3c (void) | |
a737bd4d | 9939 | { |
c19d1205 | 9940 | int Rd, Rs, Rn; |
b99bd4ef | 9941 | |
c19d1205 ZW |
9942 | Rd = inst.operands[0].reg; |
9943 | Rs = (inst.operands[1].present | |
9944 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9945 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9946 | Rn = inst.operands[2].reg; | |
c921be7d | 9947 | |
fdfde340 JM |
9948 | reject_bad_reg (Rd); |
9949 | reject_bad_reg (Rs); | |
9950 | if (inst.operands[2].isreg) | |
9951 | reject_bad_reg (Rn); | |
a737bd4d | 9952 | |
c19d1205 | 9953 | if (unified_syntax) |
a737bd4d | 9954 | { |
c19d1205 | 9955 | if (!inst.operands[2].isreg) |
b99bd4ef | 9956 | { |
c19d1205 ZW |
9957 | /* For an immediate, we always generate a 32-bit opcode; |
9958 | section relaxation will shrink it later if possible. */ | |
9959 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9960 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9961 | inst.instruction |= Rd << 8; | |
9962 | inst.instruction |= Rs << 16; | |
9963 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9964 | } |
c19d1205 | 9965 | else |
a737bd4d | 9966 | { |
e27ec89e PB |
9967 | bfd_boolean narrow; |
9968 | ||
c19d1205 | 9969 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9970 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9971 | narrow = !in_it_block (); |
e27ec89e | 9972 | else |
e07e6e58 | 9973 | narrow = in_it_block (); |
e27ec89e PB |
9974 | |
9975 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9976 | narrow = FALSE; | |
9977 | if (inst.operands[2].shifted) | |
9978 | narrow = FALSE; | |
9979 | if (inst.size_req == 4) | |
9980 | narrow = FALSE; | |
9981 | ||
9982 | if (narrow) | |
a737bd4d | 9983 | { |
c19d1205 | 9984 | if (Rd == Rs) |
a737bd4d | 9985 | { |
c19d1205 ZW |
9986 | inst.instruction = THUMB_OP16 (inst.instruction); |
9987 | inst.instruction |= Rd; | |
9988 | inst.instruction |= Rn << 3; | |
9989 | return; | |
a737bd4d | 9990 | } |
c19d1205 | 9991 | if (Rd == Rn) |
a737bd4d | 9992 | { |
c19d1205 ZW |
9993 | inst.instruction = THUMB_OP16 (inst.instruction); |
9994 | inst.instruction |= Rd; | |
9995 | inst.instruction |= Rs << 3; | |
9996 | return; | |
a737bd4d NC |
9997 | } |
9998 | } | |
c19d1205 ZW |
9999 | |
10000 | /* If we get here, it can't be done in 16 bits. */ | |
10001 | constraint (inst.operands[2].shifted | |
10002 | && inst.operands[2].immisreg, | |
10003 | _("shift must be constant")); | |
10004 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10005 | inst.instruction |= Rd << 8; | |
10006 | inst.instruction |= Rs << 16; | |
10007 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 10008 | } |
b99bd4ef | 10009 | } |
c19d1205 ZW |
10010 | else |
10011 | { | |
10012 | /* On its face this is a lie - the instruction does set the | |
10013 | flags. However, the only supported mnemonic in this mode | |
10014 | says it doesn't. */ | |
10015 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10016 | |
c19d1205 ZW |
10017 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10018 | _("unshifted register required")); | |
10019 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10020 | ||
10021 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10022 | inst.instruction |= Rd; | |
10023 | ||
10024 | if (Rd == Rs) | |
10025 | inst.instruction |= Rn << 3; | |
10026 | else if (Rd == Rn) | |
10027 | inst.instruction |= Rs << 3; | |
10028 | else | |
10029 | constraint (1, _("dest must overlap one source register")); | |
10030 | } | |
a737bd4d NC |
10031 | } |
10032 | ||
62b3e311 PB |
10033 | static void |
10034 | do_t_barrier (void) | |
10035 | { | |
10036 | if (inst.operands[0].present) | |
10037 | { | |
10038 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
10039 | && inst.operands[0].imm > 0xf |
10040 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 10041 | _("bad barrier type")); |
62b3e311 PB |
10042 | inst.instruction |= inst.operands[0].imm; |
10043 | } | |
10044 | else | |
10045 | inst.instruction |= 0xf; | |
10046 | } | |
10047 | ||
c19d1205 ZW |
10048 | static void |
10049 | do_t_bfc (void) | |
a737bd4d | 10050 | { |
fdfde340 | 10051 | unsigned Rd; |
c19d1205 ZW |
10052 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
10053 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10054 | /* The instruction encoding stores the LSB and MSB, | |
10055 | not the LSB and width. */ | |
fdfde340 JM |
10056 | Rd = inst.operands[0].reg; |
10057 | reject_bad_reg (Rd); | |
10058 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
10059 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
10060 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
10061 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10062 | } |
10063 | ||
c19d1205 ZW |
10064 | static void |
10065 | do_t_bfi (void) | |
b99bd4ef | 10066 | { |
fdfde340 | 10067 | int Rd, Rn; |
c19d1205 | 10068 | unsigned int msb; |
b99bd4ef | 10069 | |
fdfde340 JM |
10070 | Rd = inst.operands[0].reg; |
10071 | reject_bad_reg (Rd); | |
10072 | ||
c19d1205 ZW |
10073 | /* #0 in second position is alternative syntax for bfc, which is |
10074 | the same instruction but with REG_PC in the Rm field. */ | |
10075 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
10076 | Rn = REG_PC; |
10077 | else | |
10078 | { | |
10079 | Rn = inst.operands[1].reg; | |
10080 | reject_bad_reg (Rn); | |
10081 | } | |
b99bd4ef | 10082 | |
c19d1205 ZW |
10083 | msb = inst.operands[2].imm + inst.operands[3].imm; |
10084 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10085 | /* The instruction encoding stores the LSB and MSB, | |
10086 | not the LSB and width. */ | |
fdfde340 JM |
10087 | inst.instruction |= Rd << 8; |
10088 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10089 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10090 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10091 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10092 | } |
10093 | ||
c19d1205 ZW |
10094 | static void |
10095 | do_t_bfx (void) | |
b99bd4ef | 10096 | { |
fdfde340 JM |
10097 | unsigned Rd, Rn; |
10098 | ||
10099 | Rd = inst.operands[0].reg; | |
10100 | Rn = inst.operands[1].reg; | |
10101 | ||
10102 | reject_bad_reg (Rd); | |
10103 | reject_bad_reg (Rn); | |
10104 | ||
c19d1205 ZW |
10105 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
10106 | _("bit-field extends past end of register")); | |
fdfde340 JM |
10107 | inst.instruction |= Rd << 8; |
10108 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10109 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10110 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10111 | inst.instruction |= inst.operands[3].imm - 1; | |
10112 | } | |
b99bd4ef | 10113 | |
c19d1205 ZW |
10114 | /* ARM V5 Thumb BLX (argument parse) |
10115 | BLX <target_addr> which is BLX(1) | |
10116 | BLX <Rm> which is BLX(2) | |
10117 | Unfortunately, there are two different opcodes for this mnemonic. | |
10118 | So, the insns[].value is not used, and the code here zaps values | |
10119 | into inst.instruction. | |
b99bd4ef | 10120 | |
c19d1205 ZW |
10121 | ??? How to take advantage of the additional two bits of displacement |
10122 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 10123 | |
c19d1205 ZW |
10124 | static void |
10125 | do_t_blx (void) | |
10126 | { | |
e07e6e58 NC |
10127 | set_it_insn_type_last (); |
10128 | ||
c19d1205 | 10129 | if (inst.operands[0].isreg) |
fdfde340 JM |
10130 | { |
10131 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
10132 | /* We have a register, so this is BLX(2). */ | |
10133 | inst.instruction |= inst.operands[0].reg << 3; | |
10134 | } | |
b99bd4ef NC |
10135 | else |
10136 | { | |
c19d1205 | 10137 | /* No register. This must be BLX(1). */ |
2fc8bdac | 10138 | inst.instruction = 0xf000e800; |
0855e32b | 10139 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
10140 | } |
10141 | } | |
10142 | ||
c19d1205 ZW |
10143 | static void |
10144 | do_t_branch (void) | |
b99bd4ef | 10145 | { |
0110f2b8 | 10146 | int opcode; |
dfa9f0d5 | 10147 | int cond; |
9ae92b05 | 10148 | int reloc; |
dfa9f0d5 | 10149 | |
e07e6e58 NC |
10150 | cond = inst.cond; |
10151 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
10152 | ||
10153 | if (in_it_block ()) | |
dfa9f0d5 PB |
10154 | { |
10155 | /* Conditional branches inside IT blocks are encoded as unconditional | |
10156 | branches. */ | |
10157 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
10158 | } |
10159 | else | |
10160 | cond = inst.cond; | |
10161 | ||
10162 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
10163 | opcode = T_MNEM_bcond; |
10164 | else | |
10165 | opcode = inst.instruction; | |
10166 | ||
12d6b0b7 RS |
10167 | if (unified_syntax |
10168 | && (inst.size_req == 4 | |
10960bfb PB |
10169 | || (inst.size_req != 2 |
10170 | && (inst.operands[0].hasreloc | |
10171 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10172 | { |
0110f2b8 | 10173 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10174 | if (cond == COND_ALWAYS) |
9ae92b05 | 10175 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10176 | else |
10177 | { | |
9c2799c2 | 10178 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10179 | inst.instruction |= cond << 22; |
9ae92b05 | 10180 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10181 | } |
10182 | } | |
b99bd4ef NC |
10183 | else |
10184 | { | |
0110f2b8 | 10185 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10186 | if (cond == COND_ALWAYS) |
9ae92b05 | 10187 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10188 | else |
b99bd4ef | 10189 | { |
dfa9f0d5 | 10190 | inst.instruction |= cond << 8; |
9ae92b05 | 10191 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10192 | } |
0110f2b8 PB |
10193 | /* Allow section relaxation. */ |
10194 | if (unified_syntax && inst.size_req != 2) | |
10195 | inst.relax = opcode; | |
b99bd4ef | 10196 | } |
9ae92b05 | 10197 | inst.reloc.type = reloc; |
c19d1205 | 10198 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10199 | } |
10200 | ||
8884b720 MGD |
10201 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
10202 | between the two is the maximum immediate allowed - which is passed in | |
10203 | RANGE. */ | |
b99bd4ef | 10204 | static void |
8884b720 | 10205 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 10206 | { |
dfa9f0d5 PB |
10207 | constraint (inst.cond != COND_ALWAYS, |
10208 | _("instruction is always unconditional")); | |
c19d1205 | 10209 | if (inst.operands[0].present) |
b99bd4ef | 10210 | { |
8884b720 | 10211 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
10212 | _("immediate value out of range")); |
10213 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 10214 | } |
8884b720 MGD |
10215 | |
10216 | set_it_insn_type (NEUTRAL_IT_INSN); | |
10217 | } | |
10218 | ||
10219 | static void | |
10220 | do_t_hlt (void) | |
10221 | { | |
10222 | do_t_bkpt_hlt1 (63); | |
10223 | } | |
10224 | ||
10225 | static void | |
10226 | do_t_bkpt (void) | |
10227 | { | |
10228 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
10229 | } |
10230 | ||
10231 | static void | |
c19d1205 | 10232 | do_t_branch23 (void) |
b99bd4ef | 10233 | { |
e07e6e58 | 10234 | set_it_insn_type_last (); |
0855e32b | 10235 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 10236 | |
0855e32b NS |
10237 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
10238 | this file. We used to simply ignore the PLT reloc type here -- | |
10239 | the branch encoding is now needed to deal with TLSCALL relocs. | |
10240 | So if we see a PLT reloc now, put it back to how it used to be to | |
10241 | keep the preexisting behaviour. */ | |
10242 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
10243 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 10244 | |
4343666d | 10245 | #if defined(OBJ_COFF) |
c19d1205 ZW |
10246 | /* If the destination of the branch is a defined symbol which does not have |
10247 | the THUMB_FUNC attribute, then we must be calling a function which has | |
10248 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
10249 | function and change the branch to refer to that function instead. */ | |
10250 | if ( inst.reloc.exp.X_op == O_symbol | |
10251 | && inst.reloc.exp.X_add_symbol != NULL | |
10252 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10253 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10254 | inst.reloc.exp.X_add_symbol = | |
10255 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 10256 | #endif |
90e4755a RE |
10257 | } |
10258 | ||
10259 | static void | |
c19d1205 | 10260 | do_t_bx (void) |
90e4755a | 10261 | { |
e07e6e58 | 10262 | set_it_insn_type_last (); |
c19d1205 ZW |
10263 | inst.instruction |= inst.operands[0].reg << 3; |
10264 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
10265 | should cause the alignment to be checked once it is known. This is | |
10266 | because BX PC only works if the instruction is word aligned. */ | |
10267 | } | |
90e4755a | 10268 | |
c19d1205 ZW |
10269 | static void |
10270 | do_t_bxj (void) | |
10271 | { | |
fdfde340 | 10272 | int Rm; |
90e4755a | 10273 | |
e07e6e58 | 10274 | set_it_insn_type_last (); |
fdfde340 JM |
10275 | Rm = inst.operands[0].reg; |
10276 | reject_bad_reg (Rm); | |
10277 | inst.instruction |= Rm << 16; | |
90e4755a RE |
10278 | } |
10279 | ||
10280 | static void | |
c19d1205 | 10281 | do_t_clz (void) |
90e4755a | 10282 | { |
fdfde340 JM |
10283 | unsigned Rd; |
10284 | unsigned Rm; | |
10285 | ||
10286 | Rd = inst.operands[0].reg; | |
10287 | Rm = inst.operands[1].reg; | |
10288 | ||
10289 | reject_bad_reg (Rd); | |
10290 | reject_bad_reg (Rm); | |
10291 | ||
10292 | inst.instruction |= Rd << 8; | |
10293 | inst.instruction |= Rm << 16; | |
10294 | inst.instruction |= Rm; | |
c19d1205 | 10295 | } |
90e4755a | 10296 | |
dfa9f0d5 PB |
10297 | static void |
10298 | do_t_cps (void) | |
10299 | { | |
e07e6e58 | 10300 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
10301 | inst.instruction |= inst.operands[0].imm; |
10302 | } | |
10303 | ||
c19d1205 ZW |
10304 | static void |
10305 | do_t_cpsi (void) | |
10306 | { | |
e07e6e58 | 10307 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 10308 | if (unified_syntax |
62b3e311 PB |
10309 | && (inst.operands[1].present || inst.size_req == 4) |
10310 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 10311 | { |
c19d1205 ZW |
10312 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
10313 | inst.instruction = 0xf3af8000; | |
10314 | inst.instruction |= imod << 9; | |
10315 | inst.instruction |= inst.operands[0].imm << 5; | |
10316 | if (inst.operands[1].present) | |
10317 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 10318 | } |
c19d1205 | 10319 | else |
90e4755a | 10320 | { |
62b3e311 PB |
10321 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
10322 | && (inst.operands[0].imm & 4), | |
10323 | _("selected processor does not support 'A' form " | |
10324 | "of this instruction")); | |
10325 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
10326 | _("Thumb does not support the 2-argument " |
10327 | "form of this instruction")); | |
10328 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 10329 | } |
90e4755a RE |
10330 | } |
10331 | ||
c19d1205 ZW |
10332 | /* THUMB CPY instruction (argument parse). */ |
10333 | ||
90e4755a | 10334 | static void |
c19d1205 | 10335 | do_t_cpy (void) |
90e4755a | 10336 | { |
c19d1205 | 10337 | if (inst.size_req == 4) |
90e4755a | 10338 | { |
c19d1205 ZW |
10339 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
10340 | inst.instruction |= inst.operands[0].reg << 8; | |
10341 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 10342 | } |
c19d1205 | 10343 | else |
90e4755a | 10344 | { |
c19d1205 ZW |
10345 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
10346 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
10347 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10348 | } |
90e4755a RE |
10349 | } |
10350 | ||
90e4755a | 10351 | static void |
25fe350b | 10352 | do_t_cbz (void) |
90e4755a | 10353 | { |
e07e6e58 | 10354 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10355 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10356 | inst.instruction |= inst.operands[0].reg; | |
10357 | inst.reloc.pc_rel = 1; | |
10358 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10359 | } | |
90e4755a | 10360 | |
62b3e311 PB |
10361 | static void |
10362 | do_t_dbg (void) | |
10363 | { | |
10364 | inst.instruction |= inst.operands[0].imm; | |
10365 | } | |
10366 | ||
10367 | static void | |
10368 | do_t_div (void) | |
10369 | { | |
fdfde340 JM |
10370 | unsigned Rd, Rn, Rm; |
10371 | ||
10372 | Rd = inst.operands[0].reg; | |
10373 | Rn = (inst.operands[1].present | |
10374 | ? inst.operands[1].reg : Rd); | |
10375 | Rm = inst.operands[2].reg; | |
10376 | ||
10377 | reject_bad_reg (Rd); | |
10378 | reject_bad_reg (Rn); | |
10379 | reject_bad_reg (Rm); | |
10380 | ||
10381 | inst.instruction |= Rd << 8; | |
10382 | inst.instruction |= Rn << 16; | |
10383 | inst.instruction |= Rm; | |
62b3e311 PB |
10384 | } |
10385 | ||
c19d1205 ZW |
10386 | static void |
10387 | do_t_hint (void) | |
10388 | { | |
10389 | if (unified_syntax && inst.size_req == 4) | |
10390 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10391 | else | |
10392 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10393 | } | |
90e4755a | 10394 | |
c19d1205 ZW |
10395 | static void |
10396 | do_t_it (void) | |
10397 | { | |
10398 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10399 | |
e07e6e58 NC |
10400 | set_it_insn_type (IT_INSN); |
10401 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10402 | now_it.cc = cond; | |
5a01bb1d | 10403 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
10404 | |
10405 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10406 | if ((cond & 0x1) == 0x0) |
90e4755a | 10407 | { |
c19d1205 | 10408 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10409 | |
c19d1205 | 10410 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
10411 | { |
10412 | /* No conversion needed. */ | |
10413 | now_it.block_length = 1; | |
10414 | } | |
c19d1205 | 10415 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
10416 | { |
10417 | mask ^= 0x8; | |
10418 | now_it.block_length = 2; | |
10419 | } | |
e27ec89e | 10420 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
10421 | { |
10422 | mask ^= 0xC; | |
10423 | now_it.block_length = 3; | |
10424 | } | |
c19d1205 | 10425 | else |
5a01bb1d MGD |
10426 | { |
10427 | mask ^= 0xE; | |
10428 | now_it.block_length = 4; | |
10429 | } | |
90e4755a | 10430 | |
e27ec89e PB |
10431 | inst.instruction &= 0xfff0; |
10432 | inst.instruction |= mask; | |
c19d1205 | 10433 | } |
90e4755a | 10434 | |
c19d1205 ZW |
10435 | inst.instruction |= cond << 4; |
10436 | } | |
90e4755a | 10437 | |
3c707909 PB |
10438 | /* Helper function used for both push/pop and ldm/stm. */ |
10439 | static void | |
10440 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
10441 | { | |
10442 | bfd_boolean load; | |
10443 | ||
10444 | load = (inst.instruction & (1 << 20)) != 0; | |
10445 | ||
10446 | if (mask & (1 << 13)) | |
10447 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
10448 | |
10449 | if ((mask & (1 << base)) != 0 | |
10450 | && writeback) | |
10451 | inst.error = _("having the base register in the register list when " | |
10452 | "using write back is UNPREDICTABLE"); | |
10453 | ||
3c707909 PB |
10454 | if (load) |
10455 | { | |
e07e6e58 NC |
10456 | if (mask & (1 << 15)) |
10457 | { | |
10458 | if (mask & (1 << 14)) | |
10459 | inst.error = _("LR and PC should not both be in register list"); | |
10460 | else | |
10461 | set_it_insn_type_last (); | |
10462 | } | |
3c707909 PB |
10463 | } |
10464 | else | |
10465 | { | |
10466 | if (mask & (1 << 15)) | |
10467 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
10468 | } |
10469 | ||
10470 | if ((mask & (mask - 1)) == 0) | |
10471 | { | |
10472 | /* Single register transfers implemented as str/ldr. */ | |
10473 | if (writeback) | |
10474 | { | |
10475 | if (inst.instruction & (1 << 23)) | |
10476 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
10477 | else | |
10478 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
10479 | } | |
10480 | else | |
10481 | { | |
10482 | if (inst.instruction & (1 << 23)) | |
10483 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
10484 | else | |
10485 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
10486 | } | |
10487 | ||
10488 | inst.instruction |= 0xf8400000; | |
10489 | if (load) | |
10490 | inst.instruction |= 0x00100000; | |
10491 | ||
5f4273c7 | 10492 | mask = ffs (mask) - 1; |
3c707909 PB |
10493 | mask <<= 12; |
10494 | } | |
10495 | else if (writeback) | |
10496 | inst.instruction |= WRITE_BACK; | |
10497 | ||
10498 | inst.instruction |= mask; | |
10499 | inst.instruction |= base << 16; | |
10500 | } | |
10501 | ||
c19d1205 ZW |
10502 | static void |
10503 | do_t_ldmstm (void) | |
10504 | { | |
10505 | /* This really doesn't seem worth it. */ | |
10506 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10507 | _("expression too complex")); | |
10508 | constraint (inst.operands[1].writeback, | |
10509 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 10510 | |
c19d1205 ZW |
10511 | if (unified_syntax) |
10512 | { | |
3c707909 PB |
10513 | bfd_boolean narrow; |
10514 | unsigned mask; | |
10515 | ||
10516 | narrow = FALSE; | |
c19d1205 ZW |
10517 | /* See if we can use a 16-bit instruction. */ |
10518 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
10519 | && inst.size_req != 4 | |
3c707909 | 10520 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 10521 | { |
3c707909 | 10522 | mask = 1 << inst.operands[0].reg; |
90e4755a | 10523 | |
eab4f823 | 10524 | if (inst.operands[0].reg <= 7) |
90e4755a | 10525 | { |
3c707909 | 10526 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
10527 | ? inst.operands[0].writeback |
10528 | : (inst.operands[0].writeback | |
10529 | == !(inst.operands[1].imm & mask))) | |
10530 | { | |
10531 | if (inst.instruction == T_MNEM_stmia | |
10532 | && (inst.operands[1].imm & mask) | |
10533 | && (inst.operands[1].imm & (mask - 1))) | |
10534 | as_warn (_("value stored for r%d is UNKNOWN"), | |
10535 | inst.operands[0].reg); | |
3c707909 | 10536 | |
eab4f823 MGD |
10537 | inst.instruction = THUMB_OP16 (inst.instruction); |
10538 | inst.instruction |= inst.operands[0].reg << 8; | |
10539 | inst.instruction |= inst.operands[1].imm; | |
10540 | narrow = TRUE; | |
10541 | } | |
10542 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10543 | { | |
10544 | /* This means 1 register in reg list one of 3 situations: | |
10545 | 1. Instruction is stmia, but without writeback. | |
10546 | 2. lmdia without writeback, but with Rn not in | |
10547 | reglist. | |
10548 | 3. ldmia with writeback, but with Rn in reglist. | |
10549 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
10550 | case 1 and 2 which can be converted into a 16-bit | |
10551 | str or ldr. The SP cases are handled below. */ | |
10552 | unsigned long opcode; | |
10553 | /* First, record an error for Case 3. */ | |
10554 | if (inst.operands[1].imm & mask | |
10555 | && inst.operands[0].writeback) | |
fa94de6b | 10556 | inst.error = |
eab4f823 MGD |
10557 | _("having the base register in the register list when " |
10558 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
10559 | |
10560 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
10561 | : T_MNEM_ldr); |
10562 | inst.instruction = THUMB_OP16 (opcode); | |
10563 | inst.instruction |= inst.operands[0].reg << 3; | |
10564 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
10565 | narrow = TRUE; | |
10566 | } | |
90e4755a | 10567 | } |
eab4f823 | 10568 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 10569 | { |
eab4f823 MGD |
10570 | if (inst.operands[0].writeback) |
10571 | { | |
fa94de6b | 10572 | inst.instruction = |
eab4f823 MGD |
10573 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
10574 | ? T_MNEM_push : T_MNEM_pop); | |
10575 | inst.instruction |= inst.operands[1].imm; | |
10576 | narrow = TRUE; | |
10577 | } | |
10578 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10579 | { | |
fa94de6b | 10580 | inst.instruction = |
eab4f823 MGD |
10581 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
10582 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); | |
10583 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); | |
10584 | narrow = TRUE; | |
10585 | } | |
90e4755a | 10586 | } |
3c707909 PB |
10587 | } |
10588 | ||
10589 | if (!narrow) | |
10590 | { | |
c19d1205 ZW |
10591 | if (inst.instruction < 0xffff) |
10592 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 10593 | |
5f4273c7 NC |
10594 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
10595 | inst.operands[0].writeback); | |
90e4755a RE |
10596 | } |
10597 | } | |
c19d1205 | 10598 | else |
90e4755a | 10599 | { |
c19d1205 ZW |
10600 | constraint (inst.operands[0].reg > 7 |
10601 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
10602 | constraint (inst.instruction != T_MNEM_ldmia |
10603 | && inst.instruction != T_MNEM_stmia, | |
10604 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 10605 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 10606 | { |
c19d1205 ZW |
10607 | if (!inst.operands[0].writeback) |
10608 | as_warn (_("this instruction will write back the base register")); | |
10609 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
10610 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 10611 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 10612 | inst.operands[0].reg); |
f03698e6 | 10613 | } |
c19d1205 | 10614 | else |
90e4755a | 10615 | { |
c19d1205 ZW |
10616 | if (!inst.operands[0].writeback |
10617 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10618 | as_warn (_("this instruction will write back the base register")); | |
10619 | else if (inst.operands[0].writeback | |
10620 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10621 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
10622 | } |
10623 | ||
c19d1205 ZW |
10624 | inst.instruction = THUMB_OP16 (inst.instruction); |
10625 | inst.instruction |= inst.operands[0].reg << 8; | |
10626 | inst.instruction |= inst.operands[1].imm; | |
10627 | } | |
10628 | } | |
e28cd48c | 10629 | |
c19d1205 ZW |
10630 | static void |
10631 | do_t_ldrex (void) | |
10632 | { | |
10633 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
10634 | || inst.operands[1].postind || inst.operands[1].writeback | |
10635 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
10636 | || inst.operands[1].negative, | |
01cfc07f | 10637 | BAD_ADDR_MODE); |
e28cd48c | 10638 | |
5be8be5d DG |
10639 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
10640 | ||
c19d1205 ZW |
10641 | inst.instruction |= inst.operands[0].reg << 12; |
10642 | inst.instruction |= inst.operands[1].reg << 16; | |
10643 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
10644 | } | |
e28cd48c | 10645 | |
c19d1205 ZW |
10646 | static void |
10647 | do_t_ldrexd (void) | |
10648 | { | |
10649 | if (!inst.operands[1].present) | |
1cac9012 | 10650 | { |
c19d1205 ZW |
10651 | constraint (inst.operands[0].reg == REG_LR, |
10652 | _("r14 not allowed as first register " | |
10653 | "when second register is omitted")); | |
10654 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 10655 | } |
c19d1205 ZW |
10656 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
10657 | BAD_OVERLAP); | |
b99bd4ef | 10658 | |
c19d1205 ZW |
10659 | inst.instruction |= inst.operands[0].reg << 12; |
10660 | inst.instruction |= inst.operands[1].reg << 8; | |
10661 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10662 | } |
10663 | ||
10664 | static void | |
c19d1205 | 10665 | do_t_ldst (void) |
b99bd4ef | 10666 | { |
0110f2b8 PB |
10667 | unsigned long opcode; |
10668 | int Rn; | |
10669 | ||
e07e6e58 NC |
10670 | if (inst.operands[0].isreg |
10671 | && !inst.operands[0].preind | |
10672 | && inst.operands[0].reg == REG_PC) | |
10673 | set_it_insn_type_last (); | |
10674 | ||
0110f2b8 | 10675 | opcode = inst.instruction; |
c19d1205 | 10676 | if (unified_syntax) |
b99bd4ef | 10677 | { |
53365c0d PB |
10678 | if (!inst.operands[1].isreg) |
10679 | { | |
10680 | if (opcode <= 0xffff) | |
10681 | inst.instruction = THUMB_OP32 (opcode); | |
10682 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10683 | return; | |
10684 | } | |
0110f2b8 PB |
10685 | if (inst.operands[1].isreg |
10686 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10687 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10688 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10689 | && opcode <= 0xffff |
10690 | && inst.size_req != 4) | |
c19d1205 | 10691 | { |
0110f2b8 PB |
10692 | /* Insn may have a 16-bit form. */ |
10693 | Rn = inst.operands[1].reg; | |
10694 | if (inst.operands[1].immisreg) | |
10695 | { | |
10696 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10697 | /* [Rn, Rik] */ |
0110f2b8 PB |
10698 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10699 | goto op16; | |
5be8be5d DG |
10700 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10701 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10702 | } |
10703 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10704 | && opcode != T_MNEM_ldrsb) | |
10705 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10706 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10707 | { | |
10708 | /* [Rn, #const] */ | |
10709 | if (Rn > 7) | |
10710 | { | |
10711 | if (Rn == REG_PC) | |
10712 | { | |
10713 | if (inst.reloc.pc_rel) | |
10714 | opcode = T_MNEM_ldr_pc2; | |
10715 | else | |
10716 | opcode = T_MNEM_ldr_pc; | |
10717 | } | |
10718 | else | |
10719 | { | |
10720 | if (opcode == T_MNEM_ldr) | |
10721 | opcode = T_MNEM_ldr_sp; | |
10722 | else | |
10723 | opcode = T_MNEM_str_sp; | |
10724 | } | |
10725 | inst.instruction = inst.operands[0].reg << 8; | |
10726 | } | |
10727 | else | |
10728 | { | |
10729 | inst.instruction = inst.operands[0].reg; | |
10730 | inst.instruction |= inst.operands[1].reg << 3; | |
10731 | } | |
10732 | inst.instruction |= THUMB_OP16 (opcode); | |
10733 | if (inst.size_req == 2) | |
10734 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10735 | else | |
10736 | inst.relax = opcode; | |
10737 | return; | |
10738 | } | |
c19d1205 | 10739 | } |
0110f2b8 | 10740 | /* Definitely a 32-bit variant. */ |
5be8be5d | 10741 | |
8d67f500 NC |
10742 | /* Warning for Erratum 752419. */ |
10743 | if (opcode == T_MNEM_ldr | |
10744 | && inst.operands[0].reg == REG_SP | |
10745 | && inst.operands[1].writeback == 1 | |
10746 | && !inst.operands[1].immisreg) | |
10747 | { | |
10748 | if (no_cpu_selected () | |
10749 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
10750 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) | |
10751 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
10752 | as_warn (_("This instruction may be unpredictable " | |
10753 | "if executed on M-profile cores " | |
10754 | "with interrupts enabled.")); | |
10755 | } | |
10756 | ||
5be8be5d | 10757 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 10758 | if (inst.operands[1].immisreg) |
5be8be5d DG |
10759 | reject_bad_reg (inst.operands[1].imm); |
10760 | ||
1be5fd2e NC |
10761 | constraint (inst.operands[1].writeback == 1 |
10762 | && inst.operands[0].reg == inst.operands[1].reg, | |
10763 | BAD_OVERLAP); | |
10764 | ||
0110f2b8 | 10765 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10766 | inst.instruction |= inst.operands[0].reg << 12; |
10767 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 10768 | check_ldr_r15_aligned (); |
b99bd4ef NC |
10769 | return; |
10770 | } | |
10771 | ||
c19d1205 ZW |
10772 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10773 | ||
10774 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10775 | { |
c19d1205 ZW |
10776 | /* Only [Rn,Rm] is acceptable. */ |
10777 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10778 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10779 | || inst.operands[1].postind || inst.operands[1].shifted | |
10780 | || inst.operands[1].negative, | |
10781 | _("Thumb does not support this addressing mode")); | |
10782 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10783 | goto op16; | |
b99bd4ef | 10784 | } |
5f4273c7 | 10785 | |
c19d1205 ZW |
10786 | inst.instruction = THUMB_OP16 (inst.instruction); |
10787 | if (!inst.operands[1].isreg) | |
10788 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10789 | return; | |
b99bd4ef | 10790 | |
c19d1205 ZW |
10791 | constraint (!inst.operands[1].preind |
10792 | || inst.operands[1].shifted | |
10793 | || inst.operands[1].writeback, | |
10794 | _("Thumb does not support this addressing mode")); | |
10795 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10796 | { |
c19d1205 ZW |
10797 | constraint (inst.instruction & 0x0600, |
10798 | _("byte or halfword not valid for base register")); | |
10799 | constraint (inst.operands[1].reg == REG_PC | |
10800 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10801 | _("r15 based store not allowed")); | |
10802 | constraint (inst.operands[1].immisreg, | |
10803 | _("invalid base register for register offset")); | |
b99bd4ef | 10804 | |
c19d1205 ZW |
10805 | if (inst.operands[1].reg == REG_PC) |
10806 | inst.instruction = T_OPCODE_LDR_PC; | |
10807 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10808 | inst.instruction = T_OPCODE_LDR_SP; | |
10809 | else | |
10810 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10811 | |
c19d1205 ZW |
10812 | inst.instruction |= inst.operands[0].reg << 8; |
10813 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10814 | return; | |
10815 | } | |
90e4755a | 10816 | |
c19d1205 ZW |
10817 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10818 | if (!inst.operands[1].immisreg) | |
10819 | { | |
10820 | /* Immediate offset. */ | |
10821 | inst.instruction |= inst.operands[0].reg; | |
10822 | inst.instruction |= inst.operands[1].reg << 3; | |
10823 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10824 | return; | |
10825 | } | |
90e4755a | 10826 | |
c19d1205 ZW |
10827 | /* Register offset. */ |
10828 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10829 | constraint (inst.operands[1].negative, | |
10830 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10831 | |
c19d1205 ZW |
10832 | op16: |
10833 | switch (inst.instruction) | |
10834 | { | |
10835 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10836 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10837 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10838 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10839 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10840 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10841 | case 0x5600 /* ldrsb */: | |
10842 | case 0x5e00 /* ldrsh */: break; | |
10843 | default: abort (); | |
10844 | } | |
90e4755a | 10845 | |
c19d1205 ZW |
10846 | inst.instruction |= inst.operands[0].reg; |
10847 | inst.instruction |= inst.operands[1].reg << 3; | |
10848 | inst.instruction |= inst.operands[1].imm << 6; | |
10849 | } | |
90e4755a | 10850 | |
c19d1205 ZW |
10851 | static void |
10852 | do_t_ldstd (void) | |
10853 | { | |
10854 | if (!inst.operands[1].present) | |
b99bd4ef | 10855 | { |
c19d1205 ZW |
10856 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10857 | constraint (inst.operands[0].reg == REG_LR, | |
10858 | _("r14 not allowed here")); | |
bd340a04 MGD |
10859 | constraint (inst.operands[0].reg == REG_R12, |
10860 | _("r12 not allowed here")); | |
b99bd4ef | 10861 | } |
bd340a04 MGD |
10862 | |
10863 | if (inst.operands[2].writeback | |
10864 | && (inst.operands[0].reg == inst.operands[2].reg | |
10865 | || inst.operands[1].reg == inst.operands[2].reg)) | |
10866 | as_warn (_("base register written back, and overlaps " | |
10867 | "one of transfer registers")); | |
10868 | ||
c19d1205 ZW |
10869 | inst.instruction |= inst.operands[0].reg << 12; |
10870 | inst.instruction |= inst.operands[1].reg << 8; | |
10871 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10872 | } |
10873 | ||
c19d1205 ZW |
10874 | static void |
10875 | do_t_ldstt (void) | |
10876 | { | |
10877 | inst.instruction |= inst.operands[0].reg << 12; | |
10878 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10879 | } | |
a737bd4d | 10880 | |
b99bd4ef | 10881 | static void |
c19d1205 | 10882 | do_t_mla (void) |
b99bd4ef | 10883 | { |
fdfde340 | 10884 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10885 | |
fdfde340 JM |
10886 | Rd = inst.operands[0].reg; |
10887 | Rn = inst.operands[1].reg; | |
10888 | Rm = inst.operands[2].reg; | |
10889 | Ra = inst.operands[3].reg; | |
10890 | ||
10891 | reject_bad_reg (Rd); | |
10892 | reject_bad_reg (Rn); | |
10893 | reject_bad_reg (Rm); | |
10894 | reject_bad_reg (Ra); | |
10895 | ||
10896 | inst.instruction |= Rd << 8; | |
10897 | inst.instruction |= Rn << 16; | |
10898 | inst.instruction |= Rm; | |
10899 | inst.instruction |= Ra << 12; | |
c19d1205 | 10900 | } |
b99bd4ef | 10901 | |
c19d1205 ZW |
10902 | static void |
10903 | do_t_mlal (void) | |
10904 | { | |
fdfde340 JM |
10905 | unsigned RdLo, RdHi, Rn, Rm; |
10906 | ||
10907 | RdLo = inst.operands[0].reg; | |
10908 | RdHi = inst.operands[1].reg; | |
10909 | Rn = inst.operands[2].reg; | |
10910 | Rm = inst.operands[3].reg; | |
10911 | ||
10912 | reject_bad_reg (RdLo); | |
10913 | reject_bad_reg (RdHi); | |
10914 | reject_bad_reg (Rn); | |
10915 | reject_bad_reg (Rm); | |
10916 | ||
10917 | inst.instruction |= RdLo << 12; | |
10918 | inst.instruction |= RdHi << 8; | |
10919 | inst.instruction |= Rn << 16; | |
10920 | inst.instruction |= Rm; | |
c19d1205 | 10921 | } |
b99bd4ef | 10922 | |
c19d1205 ZW |
10923 | static void |
10924 | do_t_mov_cmp (void) | |
10925 | { | |
fdfde340 JM |
10926 | unsigned Rn, Rm; |
10927 | ||
10928 | Rn = inst.operands[0].reg; | |
10929 | Rm = inst.operands[1].reg; | |
10930 | ||
e07e6e58 NC |
10931 | if (Rn == REG_PC) |
10932 | set_it_insn_type_last (); | |
10933 | ||
c19d1205 | 10934 | if (unified_syntax) |
b99bd4ef | 10935 | { |
c19d1205 ZW |
10936 | int r0off = (inst.instruction == T_MNEM_mov |
10937 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10938 | unsigned long opcode; |
3d388997 PB |
10939 | bfd_boolean narrow; |
10940 | bfd_boolean low_regs; | |
10941 | ||
fdfde340 | 10942 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10943 | opcode = inst.instruction; |
e07e6e58 | 10944 | if (in_it_block ()) |
0110f2b8 | 10945 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10946 | else |
0110f2b8 | 10947 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10948 | if (inst.size_req == 4 |
10949 | || inst.operands[1].shifted) | |
10950 | narrow = FALSE; | |
10951 | ||
efd81785 PB |
10952 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10953 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10954 | && !inst.operands[1].shifted | |
fdfde340 JM |
10955 | && Rn == REG_PC |
10956 | && Rm == REG_LR) | |
efd81785 PB |
10957 | { |
10958 | inst.instruction = T2_SUBS_PC_LR; | |
10959 | return; | |
10960 | } | |
10961 | ||
fdfde340 JM |
10962 | if (opcode == T_MNEM_cmp) |
10963 | { | |
10964 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10965 | if (narrow) |
10966 | { | |
10967 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10968 | but valid. */ | |
10969 | warn_deprecated_sp (Rm); | |
10970 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10971 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10972 | tools reject R15, so we do too. */ | |
10973 | constraint (Rm == REG_PC, BAD_PC); | |
10974 | } | |
10975 | else | |
10976 | reject_bad_reg (Rm); | |
fdfde340 JM |
10977 | } |
10978 | else if (opcode == T_MNEM_mov | |
10979 | || opcode == T_MNEM_movs) | |
10980 | { | |
10981 | if (inst.operands[1].isreg) | |
10982 | { | |
10983 | if (opcode == T_MNEM_movs) | |
10984 | { | |
10985 | reject_bad_reg (Rn); | |
10986 | reject_bad_reg (Rm); | |
10987 | } | |
76fa04a4 MGD |
10988 | else if (narrow) |
10989 | { | |
10990 | /* This is mov.n. */ | |
10991 | if ((Rn == REG_SP || Rn == REG_PC) | |
10992 | && (Rm == REG_SP || Rm == REG_PC)) | |
10993 | { | |
10994 | as_warn (_("Use of r%u as a source register is " | |
10995 | "deprecated when r%u is the destination " | |
10996 | "register."), Rm, Rn); | |
10997 | } | |
10998 | } | |
10999 | else | |
11000 | { | |
11001 | /* This is mov.w. */ | |
11002 | constraint (Rn == REG_PC, BAD_PC); | |
11003 | constraint (Rm == REG_PC, BAD_PC); | |
11004 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
11005 | } | |
fdfde340 JM |
11006 | } |
11007 | else | |
11008 | reject_bad_reg (Rn); | |
11009 | } | |
11010 | ||
c19d1205 ZW |
11011 | if (!inst.operands[1].isreg) |
11012 | { | |
0110f2b8 | 11013 | /* Immediate operand. */ |
e07e6e58 | 11014 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
11015 | narrow = 0; |
11016 | if (low_regs && narrow) | |
11017 | { | |
11018 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 11019 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
11020 | if (inst.size_req == 2) |
11021 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
11022 | else | |
11023 | inst.relax = opcode; | |
11024 | } | |
11025 | else | |
11026 | { | |
11027 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11028 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11029 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
11030 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
11031 | } | |
c19d1205 | 11032 | } |
728ca7c9 PB |
11033 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
11034 | && (inst.instruction == T_MNEM_mov | |
11035 | || inst.instruction == T_MNEM_movs)) | |
11036 | { | |
11037 | /* Register shifts are encoded as separate shift instructions. */ | |
11038 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
11039 | ||
e07e6e58 | 11040 | if (in_it_block ()) |
728ca7c9 PB |
11041 | narrow = !flags; |
11042 | else | |
11043 | narrow = flags; | |
11044 | ||
11045 | if (inst.size_req == 4) | |
11046 | narrow = FALSE; | |
11047 | ||
11048 | if (!low_regs || inst.operands[1].imm > 7) | |
11049 | narrow = FALSE; | |
11050 | ||
fdfde340 | 11051 | if (Rn != Rm) |
728ca7c9 PB |
11052 | narrow = FALSE; |
11053 | ||
11054 | switch (inst.operands[1].shift_kind) | |
11055 | { | |
11056 | case SHIFT_LSL: | |
11057 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
11058 | break; | |
11059 | case SHIFT_ASR: | |
11060 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
11061 | break; | |
11062 | case SHIFT_LSR: | |
11063 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
11064 | break; | |
11065 | case SHIFT_ROR: | |
11066 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
11067 | break; | |
11068 | default: | |
5f4273c7 | 11069 | abort (); |
728ca7c9 PB |
11070 | } |
11071 | ||
11072 | inst.instruction = opcode; | |
11073 | if (narrow) | |
11074 | { | |
fdfde340 | 11075 | inst.instruction |= Rn; |
728ca7c9 PB |
11076 | inst.instruction |= inst.operands[1].imm << 3; |
11077 | } | |
11078 | else | |
11079 | { | |
11080 | if (flags) | |
11081 | inst.instruction |= CONDS_BIT; | |
11082 | ||
fdfde340 JM |
11083 | inst.instruction |= Rn << 8; |
11084 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
11085 | inst.instruction |= inst.operands[1].imm; |
11086 | } | |
11087 | } | |
3d388997 | 11088 | else if (!narrow) |
c19d1205 | 11089 | { |
728ca7c9 PB |
11090 | /* Some mov with immediate shift have narrow variants. |
11091 | Register shifts are handled above. */ | |
11092 | if (low_regs && inst.operands[1].shifted | |
11093 | && (inst.instruction == T_MNEM_mov | |
11094 | || inst.instruction == T_MNEM_movs)) | |
11095 | { | |
e07e6e58 | 11096 | if (in_it_block ()) |
728ca7c9 PB |
11097 | narrow = (inst.instruction == T_MNEM_mov); |
11098 | else | |
11099 | narrow = (inst.instruction == T_MNEM_movs); | |
11100 | } | |
11101 | ||
11102 | if (narrow) | |
11103 | { | |
11104 | switch (inst.operands[1].shift_kind) | |
11105 | { | |
11106 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11107 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
11108 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
11109 | default: narrow = FALSE; break; | |
11110 | } | |
11111 | } | |
11112 | ||
11113 | if (narrow) | |
11114 | { | |
fdfde340 JM |
11115 | inst.instruction |= Rn; |
11116 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
11117 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11118 | } | |
11119 | else | |
11120 | { | |
11121 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11122 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
11123 | encode_thumb32_shifted_operand (1); |
11124 | } | |
c19d1205 ZW |
11125 | } |
11126 | else | |
11127 | switch (inst.instruction) | |
11128 | { | |
11129 | case T_MNEM_mov: | |
837b3435 | 11130 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
11131 | results. Don't allow this. */ |
11132 | if (low_regs) | |
11133 | { | |
11134 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
11135 | "MOV Rd, Rs with two low registers is not " | |
11136 | "permitted on this architecture"); | |
fa94de6b | 11137 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
11138 | arm_ext_v6); |
11139 | } | |
11140 | ||
c19d1205 | 11141 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
11142 | inst.instruction |= (Rn & 0x8) << 4; |
11143 | inst.instruction |= (Rn & 0x7); | |
11144 | inst.instruction |= Rm << 3; | |
c19d1205 | 11145 | break; |
b99bd4ef | 11146 | |
c19d1205 ZW |
11147 | case T_MNEM_movs: |
11148 | /* We know we have low registers at this point. | |
941a8a52 MGD |
11149 | Generate LSLS Rd, Rs, #0. */ |
11150 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
11151 | inst.instruction |= Rn; |
11152 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11153 | break; |
11154 | ||
11155 | case T_MNEM_cmp: | |
3d388997 | 11156 | if (low_regs) |
c19d1205 ZW |
11157 | { |
11158 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
11159 | inst.instruction |= Rn; |
11160 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11161 | } |
11162 | else | |
11163 | { | |
11164 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
11165 | inst.instruction |= (Rn & 0x8) << 4; |
11166 | inst.instruction |= (Rn & 0x7); | |
11167 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11168 | } |
11169 | break; | |
11170 | } | |
b99bd4ef NC |
11171 | return; |
11172 | } | |
11173 | ||
c19d1205 | 11174 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
11175 | |
11176 | /* PR 10443: Do not silently ignore shifted operands. */ | |
11177 | constraint (inst.operands[1].shifted, | |
11178 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
11179 | ||
c19d1205 | 11180 | if (inst.operands[1].isreg) |
b99bd4ef | 11181 | { |
fdfde340 | 11182 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 11183 | { |
c19d1205 ZW |
11184 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
11185 | since a MOV instruction produces unpredictable results. */ | |
11186 | if (inst.instruction == T_OPCODE_MOV_I8) | |
11187 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 11188 | else |
c19d1205 | 11189 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 11190 | |
fdfde340 JM |
11191 | inst.instruction |= Rn; |
11192 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
11193 | } |
11194 | else | |
11195 | { | |
c19d1205 ZW |
11196 | if (inst.instruction == T_OPCODE_MOV_I8) |
11197 | inst.instruction = T_OPCODE_MOV_HR; | |
11198 | else | |
11199 | inst.instruction = T_OPCODE_CMP_HR; | |
11200 | do_t_cpy (); | |
b99bd4ef NC |
11201 | } |
11202 | } | |
c19d1205 | 11203 | else |
b99bd4ef | 11204 | { |
fdfde340 | 11205 | constraint (Rn > 7, |
c19d1205 | 11206 | _("only lo regs allowed with immediate")); |
fdfde340 | 11207 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11208 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11209 | } | |
11210 | } | |
b99bd4ef | 11211 | |
c19d1205 ZW |
11212 | static void |
11213 | do_t_mov16 (void) | |
11214 | { | |
fdfde340 | 11215 | unsigned Rd; |
b6895b4f PB |
11216 | bfd_vma imm; |
11217 | bfd_boolean top; | |
11218 | ||
11219 | top = (inst.instruction & 0x00800000) != 0; | |
11220 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
11221 | { | |
11222 | constraint (top, _(":lower16: not allowed this instruction")); | |
11223 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
11224 | } | |
11225 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
11226 | { | |
11227 | constraint (!top, _(":upper16: not allowed this instruction")); | |
11228 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
11229 | } | |
11230 | ||
fdfde340 JM |
11231 | Rd = inst.operands[0].reg; |
11232 | reject_bad_reg (Rd); | |
11233 | ||
11234 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
11235 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
11236 | { | |
11237 | imm = inst.reloc.exp.X_add_number; | |
11238 | inst.instruction |= (imm & 0xf000) << 4; | |
11239 | inst.instruction |= (imm & 0x0800) << 15; | |
11240 | inst.instruction |= (imm & 0x0700) << 4; | |
11241 | inst.instruction |= (imm & 0x00ff); | |
11242 | } | |
c19d1205 | 11243 | } |
b99bd4ef | 11244 | |
c19d1205 ZW |
11245 | static void |
11246 | do_t_mvn_tst (void) | |
11247 | { | |
fdfde340 | 11248 | unsigned Rn, Rm; |
c921be7d | 11249 | |
fdfde340 JM |
11250 | Rn = inst.operands[0].reg; |
11251 | Rm = inst.operands[1].reg; | |
11252 | ||
11253 | if (inst.instruction == T_MNEM_cmp | |
11254 | || inst.instruction == T_MNEM_cmn) | |
11255 | constraint (Rn == REG_PC, BAD_PC); | |
11256 | else | |
11257 | reject_bad_reg (Rn); | |
11258 | reject_bad_reg (Rm); | |
11259 | ||
c19d1205 ZW |
11260 | if (unified_syntax) |
11261 | { | |
11262 | int r0off = (inst.instruction == T_MNEM_mvn | |
11263 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
11264 | bfd_boolean narrow; |
11265 | ||
11266 | if (inst.size_req == 4 | |
11267 | || inst.instruction > 0xffff | |
11268 | || inst.operands[1].shifted | |
fdfde340 | 11269 | || Rn > 7 || Rm > 7) |
3d388997 PB |
11270 | narrow = FALSE; |
11271 | else if (inst.instruction == T_MNEM_cmn) | |
11272 | narrow = TRUE; | |
11273 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11274 | narrow = !in_it_block (); |
3d388997 | 11275 | else |
e07e6e58 | 11276 | narrow = in_it_block (); |
3d388997 | 11277 | |
c19d1205 | 11278 | if (!inst.operands[1].isreg) |
b99bd4ef | 11279 | { |
c19d1205 ZW |
11280 | /* For an immediate, we always generate a 32-bit opcode; |
11281 | section relaxation will shrink it later if possible. */ | |
11282 | if (inst.instruction < 0xffff) | |
11283 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11284 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11285 | inst.instruction |= Rn << r0off; |
c19d1205 | 11286 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11287 | } |
c19d1205 | 11288 | else |
b99bd4ef | 11289 | { |
c19d1205 | 11290 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 11291 | if (narrow) |
b99bd4ef | 11292 | { |
c19d1205 | 11293 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11294 | inst.instruction |= Rn; |
11295 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11296 | } |
c19d1205 | 11297 | else |
b99bd4ef | 11298 | { |
c19d1205 ZW |
11299 | constraint (inst.operands[1].shifted |
11300 | && inst.operands[1].immisreg, | |
11301 | _("shift must be constant")); | |
11302 | if (inst.instruction < 0xffff) | |
11303 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11304 | inst.instruction |= Rn << r0off; |
c19d1205 | 11305 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 11306 | } |
b99bd4ef NC |
11307 | } |
11308 | } | |
11309 | else | |
11310 | { | |
c19d1205 ZW |
11311 | constraint (inst.instruction > 0xffff |
11312 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
11313 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
11314 | _("unshifted register required")); | |
fdfde340 | 11315 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11316 | BAD_HIREG); |
b99bd4ef | 11317 | |
c19d1205 | 11318 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11319 | inst.instruction |= Rn; |
11320 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11321 | } |
b99bd4ef NC |
11322 | } |
11323 | ||
b05fe5cf | 11324 | static void |
c19d1205 | 11325 | do_t_mrs (void) |
b05fe5cf | 11326 | { |
fdfde340 | 11327 | unsigned Rd; |
037e8744 JB |
11328 | |
11329 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
11330 | return; | |
11331 | ||
90ec0d68 MGD |
11332 | Rd = inst.operands[0].reg; |
11333 | reject_bad_reg (Rd); | |
11334 | inst.instruction |= Rd << 8; | |
11335 | ||
11336 | if (inst.operands[1].isreg) | |
62b3e311 | 11337 | { |
90ec0d68 MGD |
11338 | unsigned br = inst.operands[1].reg; |
11339 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
11340 | as_bad (_("bad register for mrs")); | |
11341 | ||
11342 | inst.instruction |= br & (0xf << 16); | |
11343 | inst.instruction |= (br & 0x300) >> 4; | |
11344 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
11345 | } |
11346 | else | |
11347 | { | |
90ec0d68 | 11348 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 11349 | |
d2cd1205 | 11350 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
11351 | { |
11352 | /* PR gas/12698: The constraint is only applied for m_profile. | |
11353 | If the user has specified -march=all, we want to ignore it as | |
11354 | we are building for any CPU type, including non-m variants. */ | |
11355 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; | |
11356 | constraint ((flags != 0) && m_profile, _("selected processor does " | |
11357 | "not support requested special purpose register")); | |
11358 | } | |
90ec0d68 | 11359 | else |
d2cd1205 JB |
11360 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
11361 | devices). */ | |
11362 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
11363 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 11364 | |
90ec0d68 MGD |
11365 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
11366 | inst.instruction |= inst.operands[1].imm & 0xff; | |
11367 | inst.instruction |= 0xf0000; | |
11368 | } | |
c19d1205 | 11369 | } |
b05fe5cf | 11370 | |
c19d1205 ZW |
11371 | static void |
11372 | do_t_msr (void) | |
11373 | { | |
62b3e311 | 11374 | int flags; |
fdfde340 | 11375 | unsigned Rn; |
62b3e311 | 11376 | |
037e8744 JB |
11377 | if (do_vfp_nsyn_msr () == SUCCESS) |
11378 | return; | |
11379 | ||
c19d1205 ZW |
11380 | constraint (!inst.operands[1].isreg, |
11381 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
11382 | |
11383 | if (inst.operands[0].isreg) | |
11384 | flags = (int)(inst.operands[0].reg); | |
11385 | else | |
11386 | flags = inst.operands[0].imm; | |
11387 | ||
d2cd1205 | 11388 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 11389 | { |
d2cd1205 JB |
11390 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
11391 | ||
1a43faaf NC |
11392 | /* PR gas/12698: The constraint is only applied for m_profile. |
11393 | If the user has specified -march=all, we want to ignore it as | |
11394 | we are building for any CPU type, including non-m variants. */ | |
11395 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; | |
11396 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11397 | && (bits & ~(PSR_s | PSR_f)) != 0) | |
11398 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11399 | && bits != PSR_f)) && m_profile, | |
11400 | _("selected processor does not support requested special " | |
11401 | "purpose register")); | |
62b3e311 PB |
11402 | } |
11403 | else | |
d2cd1205 JB |
11404 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
11405 | "requested special purpose register")); | |
c921be7d | 11406 | |
fdfde340 JM |
11407 | Rn = inst.operands[1].reg; |
11408 | reject_bad_reg (Rn); | |
11409 | ||
62b3e311 | 11410 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11411 | inst.instruction |= (flags & 0xf0000) >> 8; |
11412 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11413 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11414 | inst.instruction |= Rn << 16; |
c19d1205 | 11415 | } |
b05fe5cf | 11416 | |
c19d1205 ZW |
11417 | static void |
11418 | do_t_mul (void) | |
11419 | { | |
17828f45 | 11420 | bfd_boolean narrow; |
fdfde340 | 11421 | unsigned Rd, Rn, Rm; |
17828f45 | 11422 | |
c19d1205 ZW |
11423 | if (!inst.operands[2].present) |
11424 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11425 | |
fdfde340 JM |
11426 | Rd = inst.operands[0].reg; |
11427 | Rn = inst.operands[1].reg; | |
11428 | Rm = inst.operands[2].reg; | |
11429 | ||
17828f45 | 11430 | if (unified_syntax) |
b05fe5cf | 11431 | { |
17828f45 | 11432 | if (inst.size_req == 4 |
fdfde340 JM |
11433 | || (Rd != Rn |
11434 | && Rd != Rm) | |
11435 | || Rn > 7 | |
11436 | || Rm > 7) | |
17828f45 JM |
11437 | narrow = FALSE; |
11438 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 11439 | narrow = !in_it_block (); |
17828f45 | 11440 | else |
e07e6e58 | 11441 | narrow = in_it_block (); |
b05fe5cf | 11442 | } |
c19d1205 | 11443 | else |
b05fe5cf | 11444 | { |
17828f45 | 11445 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 11446 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11447 | BAD_HIREG); |
17828f45 JM |
11448 | narrow = TRUE; |
11449 | } | |
b05fe5cf | 11450 | |
17828f45 JM |
11451 | if (narrow) |
11452 | { | |
11453 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 11454 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 11455 | inst.instruction |= Rd; |
b05fe5cf | 11456 | |
fdfde340 JM |
11457 | if (Rd == Rn) |
11458 | inst.instruction |= Rm << 3; | |
11459 | else if (Rd == Rm) | |
11460 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
11461 | else |
11462 | constraint (1, _("dest must overlap one source register")); | |
11463 | } | |
17828f45 JM |
11464 | else |
11465 | { | |
e07e6e58 NC |
11466 | constraint (inst.instruction != T_MNEM_mul, |
11467 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
11468 | /* 32-bit MUL. */ |
11469 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11470 | inst.instruction |= Rd << 8; |
11471 | inst.instruction |= Rn << 16; | |
11472 | inst.instruction |= Rm << 0; | |
11473 | ||
11474 | reject_bad_reg (Rd); | |
11475 | reject_bad_reg (Rn); | |
11476 | reject_bad_reg (Rm); | |
17828f45 | 11477 | } |
c19d1205 | 11478 | } |
b05fe5cf | 11479 | |
c19d1205 ZW |
11480 | static void |
11481 | do_t_mull (void) | |
11482 | { | |
fdfde340 | 11483 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 11484 | |
fdfde340 JM |
11485 | RdLo = inst.operands[0].reg; |
11486 | RdHi = inst.operands[1].reg; | |
11487 | Rn = inst.operands[2].reg; | |
11488 | Rm = inst.operands[3].reg; | |
11489 | ||
11490 | reject_bad_reg (RdLo); | |
11491 | reject_bad_reg (RdHi); | |
11492 | reject_bad_reg (Rn); | |
11493 | reject_bad_reg (Rm); | |
11494 | ||
11495 | inst.instruction |= RdLo << 12; | |
11496 | inst.instruction |= RdHi << 8; | |
11497 | inst.instruction |= Rn << 16; | |
11498 | inst.instruction |= Rm; | |
11499 | ||
11500 | if (RdLo == RdHi) | |
c19d1205 ZW |
11501 | as_tsktsk (_("rdhi and rdlo must be different")); |
11502 | } | |
b05fe5cf | 11503 | |
c19d1205 ZW |
11504 | static void |
11505 | do_t_nop (void) | |
11506 | { | |
e07e6e58 NC |
11507 | set_it_insn_type (NEUTRAL_IT_INSN); |
11508 | ||
c19d1205 ZW |
11509 | if (unified_syntax) |
11510 | { | |
11511 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 11512 | { |
c19d1205 ZW |
11513 | inst.instruction = THUMB_OP32 (inst.instruction); |
11514 | inst.instruction |= inst.operands[0].imm; | |
11515 | } | |
11516 | else | |
11517 | { | |
bc2d1808 NC |
11518 | /* PR9722: Check for Thumb2 availability before |
11519 | generating a thumb2 nop instruction. */ | |
afa62d5e | 11520 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
11521 | { |
11522 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11523 | inst.instruction |= inst.operands[0].imm << 4; | |
11524 | } | |
11525 | else | |
11526 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
11527 | } |
11528 | } | |
11529 | else | |
11530 | { | |
11531 | constraint (inst.operands[0].present, | |
11532 | _("Thumb does not support NOP with hints")); | |
11533 | inst.instruction = 0x46c0; | |
11534 | } | |
11535 | } | |
b05fe5cf | 11536 | |
c19d1205 ZW |
11537 | static void |
11538 | do_t_neg (void) | |
11539 | { | |
11540 | if (unified_syntax) | |
11541 | { | |
3d388997 PB |
11542 | bfd_boolean narrow; |
11543 | ||
11544 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11545 | narrow = !in_it_block (); |
3d388997 | 11546 | else |
e07e6e58 | 11547 | narrow = in_it_block (); |
3d388997 PB |
11548 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11549 | narrow = FALSE; | |
11550 | if (inst.size_req == 4) | |
11551 | narrow = FALSE; | |
11552 | ||
11553 | if (!narrow) | |
c19d1205 ZW |
11554 | { |
11555 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11556 | inst.instruction |= inst.operands[0].reg << 8; | |
11557 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
11558 | } |
11559 | else | |
11560 | { | |
c19d1205 ZW |
11561 | inst.instruction = THUMB_OP16 (inst.instruction); |
11562 | inst.instruction |= inst.operands[0].reg; | |
11563 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
11564 | } |
11565 | } | |
11566 | else | |
11567 | { | |
c19d1205 ZW |
11568 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
11569 | BAD_HIREG); | |
11570 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
11571 | ||
11572 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11573 | inst.instruction |= inst.operands[0].reg; | |
11574 | inst.instruction |= inst.operands[1].reg << 3; | |
11575 | } | |
11576 | } | |
11577 | ||
1c444d06 JM |
11578 | static void |
11579 | do_t_orn (void) | |
11580 | { | |
11581 | unsigned Rd, Rn; | |
11582 | ||
11583 | Rd = inst.operands[0].reg; | |
11584 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
11585 | ||
fdfde340 JM |
11586 | reject_bad_reg (Rd); |
11587 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
11588 | reject_bad_reg (Rn); | |
11589 | ||
1c444d06 JM |
11590 | inst.instruction |= Rd << 8; |
11591 | inst.instruction |= Rn << 16; | |
11592 | ||
11593 | if (!inst.operands[2].isreg) | |
11594 | { | |
11595 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11596 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11597 | } | |
11598 | else | |
11599 | { | |
11600 | unsigned Rm; | |
11601 | ||
11602 | Rm = inst.operands[2].reg; | |
fdfde340 | 11603 | reject_bad_reg (Rm); |
1c444d06 JM |
11604 | |
11605 | constraint (inst.operands[2].shifted | |
11606 | && inst.operands[2].immisreg, | |
11607 | _("shift must be constant")); | |
11608 | encode_thumb32_shifted_operand (2); | |
11609 | } | |
11610 | } | |
11611 | ||
c19d1205 ZW |
11612 | static void |
11613 | do_t_pkhbt (void) | |
11614 | { | |
fdfde340 JM |
11615 | unsigned Rd, Rn, Rm; |
11616 | ||
11617 | Rd = inst.operands[0].reg; | |
11618 | Rn = inst.operands[1].reg; | |
11619 | Rm = inst.operands[2].reg; | |
11620 | ||
11621 | reject_bad_reg (Rd); | |
11622 | reject_bad_reg (Rn); | |
11623 | reject_bad_reg (Rm); | |
11624 | ||
11625 | inst.instruction |= Rd << 8; | |
11626 | inst.instruction |= Rn << 16; | |
11627 | inst.instruction |= Rm; | |
c19d1205 ZW |
11628 | if (inst.operands[3].present) |
11629 | { | |
11630 | unsigned int val = inst.reloc.exp.X_add_number; | |
11631 | constraint (inst.reloc.exp.X_op != O_constant, | |
11632 | _("expression too complex")); | |
11633 | inst.instruction |= (val & 0x1c) << 10; | |
11634 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 11635 | } |
c19d1205 | 11636 | } |
b05fe5cf | 11637 | |
c19d1205 ZW |
11638 | static void |
11639 | do_t_pkhtb (void) | |
11640 | { | |
11641 | if (!inst.operands[3].present) | |
1ef52f49 NC |
11642 | { |
11643 | unsigned Rtmp; | |
11644 | ||
11645 | inst.instruction &= ~0x00000020; | |
11646 | ||
11647 | /* PR 10168. Swap the Rm and Rn registers. */ | |
11648 | Rtmp = inst.operands[1].reg; | |
11649 | inst.operands[1].reg = inst.operands[2].reg; | |
11650 | inst.operands[2].reg = Rtmp; | |
11651 | } | |
c19d1205 | 11652 | do_t_pkhbt (); |
b05fe5cf ZW |
11653 | } |
11654 | ||
c19d1205 ZW |
11655 | static void |
11656 | do_t_pld (void) | |
11657 | { | |
fdfde340 JM |
11658 | if (inst.operands[0].immisreg) |
11659 | reject_bad_reg (inst.operands[0].imm); | |
11660 | ||
c19d1205 ZW |
11661 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
11662 | } | |
b05fe5cf | 11663 | |
c19d1205 ZW |
11664 | static void |
11665 | do_t_push_pop (void) | |
b99bd4ef | 11666 | { |
e9f89963 | 11667 | unsigned mask; |
5f4273c7 | 11668 | |
c19d1205 ZW |
11669 | constraint (inst.operands[0].writeback, |
11670 | _("push/pop do not support {reglist}^")); | |
11671 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11672 | _("expression too complex")); | |
b99bd4ef | 11673 | |
e9f89963 PB |
11674 | mask = inst.operands[0].imm; |
11675 | if ((mask & ~0xff) == 0) | |
3c707909 | 11676 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 11677 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 11678 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 11679 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 11680 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 11681 | { |
c19d1205 ZW |
11682 | inst.instruction = THUMB_OP16 (inst.instruction); |
11683 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 11684 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
11685 | } |
11686 | else if (unified_syntax) | |
11687 | { | |
3c707909 | 11688 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 11689 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
11690 | } |
11691 | else | |
11692 | { | |
11693 | inst.error = _("invalid register list to push/pop instruction"); | |
11694 | return; | |
11695 | } | |
c19d1205 | 11696 | } |
b99bd4ef | 11697 | |
c19d1205 ZW |
11698 | static void |
11699 | do_t_rbit (void) | |
11700 | { | |
fdfde340 JM |
11701 | unsigned Rd, Rm; |
11702 | ||
11703 | Rd = inst.operands[0].reg; | |
11704 | Rm = inst.operands[1].reg; | |
11705 | ||
11706 | reject_bad_reg (Rd); | |
11707 | reject_bad_reg (Rm); | |
11708 | ||
11709 | inst.instruction |= Rd << 8; | |
11710 | inst.instruction |= Rm << 16; | |
11711 | inst.instruction |= Rm; | |
c19d1205 | 11712 | } |
b99bd4ef | 11713 | |
c19d1205 ZW |
11714 | static void |
11715 | do_t_rev (void) | |
11716 | { | |
fdfde340 JM |
11717 | unsigned Rd, Rm; |
11718 | ||
11719 | Rd = inst.operands[0].reg; | |
11720 | Rm = inst.operands[1].reg; | |
11721 | ||
11722 | reject_bad_reg (Rd); | |
11723 | reject_bad_reg (Rm); | |
11724 | ||
11725 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
11726 | && inst.size_req != 4) |
11727 | { | |
11728 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
11729 | inst.instruction |= Rd; |
11730 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11731 | } |
11732 | else if (unified_syntax) | |
11733 | { | |
11734 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11735 | inst.instruction |= Rd << 8; |
11736 | inst.instruction |= Rm << 16; | |
11737 | inst.instruction |= Rm; | |
c19d1205 ZW |
11738 | } |
11739 | else | |
11740 | inst.error = BAD_HIREG; | |
11741 | } | |
b99bd4ef | 11742 | |
1c444d06 JM |
11743 | static void |
11744 | do_t_rrx (void) | |
11745 | { | |
11746 | unsigned Rd, Rm; | |
11747 | ||
11748 | Rd = inst.operands[0].reg; | |
11749 | Rm = inst.operands[1].reg; | |
11750 | ||
fdfde340 JM |
11751 | reject_bad_reg (Rd); |
11752 | reject_bad_reg (Rm); | |
c921be7d | 11753 | |
1c444d06 JM |
11754 | inst.instruction |= Rd << 8; |
11755 | inst.instruction |= Rm; | |
11756 | } | |
11757 | ||
c19d1205 ZW |
11758 | static void |
11759 | do_t_rsb (void) | |
11760 | { | |
fdfde340 | 11761 | unsigned Rd, Rs; |
b99bd4ef | 11762 | |
c19d1205 ZW |
11763 | Rd = inst.operands[0].reg; |
11764 | Rs = (inst.operands[1].present | |
11765 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11766 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11767 | |
fdfde340 JM |
11768 | reject_bad_reg (Rd); |
11769 | reject_bad_reg (Rs); | |
11770 | if (inst.operands[2].isreg) | |
11771 | reject_bad_reg (inst.operands[2].reg); | |
11772 | ||
c19d1205 ZW |
11773 | inst.instruction |= Rd << 8; |
11774 | inst.instruction |= Rs << 16; | |
11775 | if (!inst.operands[2].isreg) | |
11776 | { | |
026d3abb PB |
11777 | bfd_boolean narrow; |
11778 | ||
11779 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11780 | narrow = !in_it_block (); |
026d3abb | 11781 | else |
e07e6e58 | 11782 | narrow = in_it_block (); |
026d3abb PB |
11783 | |
11784 | if (Rd > 7 || Rs > 7) | |
11785 | narrow = FALSE; | |
11786 | ||
11787 | if (inst.size_req == 4 || !unified_syntax) | |
11788 | narrow = FALSE; | |
11789 | ||
11790 | if (inst.reloc.exp.X_op != O_constant | |
11791 | || inst.reloc.exp.X_add_number != 0) | |
11792 | narrow = FALSE; | |
11793 | ||
11794 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11795 | relaxation, but it doesn't seem worth the hassle. */ | |
11796 | if (narrow) | |
11797 | { | |
11798 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11799 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11800 | inst.instruction |= Rs << 3; | |
11801 | inst.instruction |= Rd; | |
11802 | } | |
11803 | else | |
11804 | { | |
11805 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11806 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11807 | } | |
c19d1205 ZW |
11808 | } |
11809 | else | |
11810 | encode_thumb32_shifted_operand (2); | |
11811 | } | |
b99bd4ef | 11812 | |
c19d1205 ZW |
11813 | static void |
11814 | do_t_setend (void) | |
11815 | { | |
12e37cbc MGD |
11816 | if (warn_on_deprecated |
11817 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
11818 | as_warn (_("setend use is deprecated for ARMv8")); | |
11819 | ||
e07e6e58 | 11820 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11821 | if (inst.operands[0].imm) |
11822 | inst.instruction |= 0x8; | |
11823 | } | |
b99bd4ef | 11824 | |
c19d1205 ZW |
11825 | static void |
11826 | do_t_shift (void) | |
11827 | { | |
11828 | if (!inst.operands[1].present) | |
11829 | inst.operands[1].reg = inst.operands[0].reg; | |
11830 | ||
11831 | if (unified_syntax) | |
11832 | { | |
3d388997 PB |
11833 | bfd_boolean narrow; |
11834 | int shift_kind; | |
11835 | ||
11836 | switch (inst.instruction) | |
11837 | { | |
11838 | case T_MNEM_asr: | |
11839 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11840 | case T_MNEM_lsl: | |
11841 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11842 | case T_MNEM_lsr: | |
11843 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11844 | case T_MNEM_ror: | |
11845 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11846 | default: abort (); | |
11847 | } | |
11848 | ||
11849 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11850 | narrow = !in_it_block (); |
3d388997 | 11851 | else |
e07e6e58 | 11852 | narrow = in_it_block (); |
3d388997 PB |
11853 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11854 | narrow = FALSE; | |
11855 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11856 | narrow = FALSE; | |
11857 | if (inst.operands[2].isreg | |
11858 | && (inst.operands[1].reg != inst.operands[0].reg | |
11859 | || inst.operands[2].reg > 7)) | |
11860 | narrow = FALSE; | |
11861 | if (inst.size_req == 4) | |
11862 | narrow = FALSE; | |
11863 | ||
fdfde340 JM |
11864 | reject_bad_reg (inst.operands[0].reg); |
11865 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11866 | |
3d388997 | 11867 | if (!narrow) |
c19d1205 ZW |
11868 | { |
11869 | if (inst.operands[2].isreg) | |
b99bd4ef | 11870 | { |
fdfde340 | 11871 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11872 | inst.instruction = THUMB_OP32 (inst.instruction); |
11873 | inst.instruction |= inst.operands[0].reg << 8; | |
11874 | inst.instruction |= inst.operands[1].reg << 16; | |
11875 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
11876 | |
11877 | /* PR 12854: Error on extraneous shifts. */ | |
11878 | constraint (inst.operands[2].shifted, | |
11879 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
11880 | } |
11881 | else | |
11882 | { | |
11883 | inst.operands[1].shifted = 1; | |
3d388997 | 11884 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11885 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11886 | ? T_MNEM_movs : T_MNEM_mov); | |
11887 | inst.instruction |= inst.operands[0].reg << 8; | |
11888 | encode_thumb32_shifted_operand (1); | |
11889 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11890 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11891 | } |
11892 | } | |
11893 | else | |
11894 | { | |
c19d1205 | 11895 | if (inst.operands[2].isreg) |
b99bd4ef | 11896 | { |
3d388997 | 11897 | switch (shift_kind) |
b99bd4ef | 11898 | { |
3d388997 PB |
11899 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11900 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11901 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11902 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11903 | default: abort (); |
b99bd4ef | 11904 | } |
5f4273c7 | 11905 | |
c19d1205 ZW |
11906 | inst.instruction |= inst.operands[0].reg; |
11907 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
11908 | |
11909 | /* PR 12854: Error on extraneous shifts. */ | |
11910 | constraint (inst.operands[2].shifted, | |
11911 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
11912 | } |
11913 | else | |
11914 | { | |
3d388997 | 11915 | switch (shift_kind) |
b99bd4ef | 11916 | { |
3d388997 PB |
11917 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11918 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11919 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11920 | default: abort (); |
b99bd4ef | 11921 | } |
c19d1205 ZW |
11922 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11923 | inst.instruction |= inst.operands[0].reg; | |
11924 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11925 | } |
11926 | } | |
c19d1205 ZW |
11927 | } |
11928 | else | |
11929 | { | |
11930 | constraint (inst.operands[0].reg > 7 | |
11931 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11932 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11933 | |
c19d1205 ZW |
11934 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11935 | { | |
11936 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11937 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11938 | _("source1 and dest must be same register")); | |
b99bd4ef | 11939 | |
c19d1205 ZW |
11940 | switch (inst.instruction) |
11941 | { | |
11942 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11943 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11944 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11945 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11946 | default: abort (); | |
11947 | } | |
5f4273c7 | 11948 | |
c19d1205 ZW |
11949 | inst.instruction |= inst.operands[0].reg; |
11950 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
11951 | |
11952 | /* PR 12854: Error on extraneous shifts. */ | |
11953 | constraint (inst.operands[2].shifted, | |
11954 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
11955 | } |
11956 | else | |
b99bd4ef | 11957 | { |
c19d1205 ZW |
11958 | switch (inst.instruction) |
11959 | { | |
11960 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11961 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11962 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11963 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11964 | default: abort (); | |
11965 | } | |
11966 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11967 | inst.instruction |= inst.operands[0].reg; | |
11968 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11969 | } |
11970 | } | |
b99bd4ef NC |
11971 | } |
11972 | ||
11973 | static void | |
c19d1205 | 11974 | do_t_simd (void) |
b99bd4ef | 11975 | { |
fdfde340 JM |
11976 | unsigned Rd, Rn, Rm; |
11977 | ||
11978 | Rd = inst.operands[0].reg; | |
11979 | Rn = inst.operands[1].reg; | |
11980 | Rm = inst.operands[2].reg; | |
11981 | ||
11982 | reject_bad_reg (Rd); | |
11983 | reject_bad_reg (Rn); | |
11984 | reject_bad_reg (Rm); | |
11985 | ||
11986 | inst.instruction |= Rd << 8; | |
11987 | inst.instruction |= Rn << 16; | |
11988 | inst.instruction |= Rm; | |
c19d1205 | 11989 | } |
b99bd4ef | 11990 | |
03ee1b7f NC |
11991 | static void |
11992 | do_t_simd2 (void) | |
11993 | { | |
11994 | unsigned Rd, Rn, Rm; | |
11995 | ||
11996 | Rd = inst.operands[0].reg; | |
11997 | Rm = inst.operands[1].reg; | |
11998 | Rn = inst.operands[2].reg; | |
11999 | ||
12000 | reject_bad_reg (Rd); | |
12001 | reject_bad_reg (Rn); | |
12002 | reject_bad_reg (Rm); | |
12003 | ||
12004 | inst.instruction |= Rd << 8; | |
12005 | inst.instruction |= Rn << 16; | |
12006 | inst.instruction |= Rm; | |
12007 | } | |
12008 | ||
c19d1205 | 12009 | static void |
3eb17e6b | 12010 | do_t_smc (void) |
c19d1205 ZW |
12011 | { |
12012 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
12013 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
12014 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
12015 | constraint (inst.reloc.exp.X_op != O_constant, |
12016 | _("expression too complex")); | |
12017 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12018 | inst.instruction |= (value & 0xf000) >> 12; | |
12019 | inst.instruction |= (value & 0x0ff0); | |
12020 | inst.instruction |= (value & 0x000f) << 16; | |
12021 | } | |
b99bd4ef | 12022 | |
90ec0d68 MGD |
12023 | static void |
12024 | do_t_hvc (void) | |
12025 | { | |
12026 | unsigned int value = inst.reloc.exp.X_add_number; | |
12027 | ||
12028 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12029 | inst.instruction |= (value & 0x0fff); | |
12030 | inst.instruction |= (value & 0xf000) << 4; | |
12031 | } | |
12032 | ||
c19d1205 | 12033 | static void |
3a21c15a | 12034 | do_t_ssat_usat (int bias) |
c19d1205 | 12035 | { |
fdfde340 JM |
12036 | unsigned Rd, Rn; |
12037 | ||
12038 | Rd = inst.operands[0].reg; | |
12039 | Rn = inst.operands[2].reg; | |
12040 | ||
12041 | reject_bad_reg (Rd); | |
12042 | reject_bad_reg (Rn); | |
12043 | ||
12044 | inst.instruction |= Rd << 8; | |
3a21c15a | 12045 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 12046 | inst.instruction |= Rn << 16; |
b99bd4ef | 12047 | |
c19d1205 | 12048 | if (inst.operands[3].present) |
b99bd4ef | 12049 | { |
3a21c15a NC |
12050 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
12051 | ||
12052 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12053 | ||
c19d1205 ZW |
12054 | constraint (inst.reloc.exp.X_op != O_constant, |
12055 | _("expression too complex")); | |
b99bd4ef | 12056 | |
3a21c15a | 12057 | if (shift_amount != 0) |
6189168b | 12058 | { |
3a21c15a NC |
12059 | constraint (shift_amount > 31, |
12060 | _("shift expression is too large")); | |
12061 | ||
c19d1205 | 12062 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
12063 | inst.instruction |= 0x00200000; /* sh bit. */ |
12064 | ||
12065 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
12066 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
12067 | } |
12068 | } | |
b99bd4ef | 12069 | } |
c921be7d | 12070 | |
3a21c15a NC |
12071 | static void |
12072 | do_t_ssat (void) | |
12073 | { | |
12074 | do_t_ssat_usat (1); | |
12075 | } | |
b99bd4ef | 12076 | |
0dd132b6 | 12077 | static void |
c19d1205 | 12078 | do_t_ssat16 (void) |
0dd132b6 | 12079 | { |
fdfde340 JM |
12080 | unsigned Rd, Rn; |
12081 | ||
12082 | Rd = inst.operands[0].reg; | |
12083 | Rn = inst.operands[2].reg; | |
12084 | ||
12085 | reject_bad_reg (Rd); | |
12086 | reject_bad_reg (Rn); | |
12087 | ||
12088 | inst.instruction |= Rd << 8; | |
c19d1205 | 12089 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 12090 | inst.instruction |= Rn << 16; |
c19d1205 | 12091 | } |
0dd132b6 | 12092 | |
c19d1205 ZW |
12093 | static void |
12094 | do_t_strex (void) | |
12095 | { | |
12096 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
12097 | || inst.operands[2].postind || inst.operands[2].writeback | |
12098 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
12099 | || inst.operands[2].negative, | |
01cfc07f | 12100 | BAD_ADDR_MODE); |
0dd132b6 | 12101 | |
5be8be5d DG |
12102 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
12103 | ||
c19d1205 ZW |
12104 | inst.instruction |= inst.operands[0].reg << 8; |
12105 | inst.instruction |= inst.operands[1].reg << 12; | |
12106 | inst.instruction |= inst.operands[2].reg << 16; | |
12107 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
12108 | } |
12109 | ||
b99bd4ef | 12110 | static void |
c19d1205 | 12111 | do_t_strexd (void) |
b99bd4ef | 12112 | { |
c19d1205 ZW |
12113 | if (!inst.operands[2].present) |
12114 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 12115 | |
c19d1205 ZW |
12116 | constraint (inst.operands[0].reg == inst.operands[1].reg |
12117 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 12118 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 12119 | BAD_OVERLAP); |
b99bd4ef | 12120 | |
c19d1205 ZW |
12121 | inst.instruction |= inst.operands[0].reg; |
12122 | inst.instruction |= inst.operands[1].reg << 12; | |
12123 | inst.instruction |= inst.operands[2].reg << 8; | |
12124 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
12125 | } |
12126 | ||
12127 | static void | |
c19d1205 | 12128 | do_t_sxtah (void) |
b99bd4ef | 12129 | { |
fdfde340 JM |
12130 | unsigned Rd, Rn, Rm; |
12131 | ||
12132 | Rd = inst.operands[0].reg; | |
12133 | Rn = inst.operands[1].reg; | |
12134 | Rm = inst.operands[2].reg; | |
12135 | ||
12136 | reject_bad_reg (Rd); | |
12137 | reject_bad_reg (Rn); | |
12138 | reject_bad_reg (Rm); | |
12139 | ||
12140 | inst.instruction |= Rd << 8; | |
12141 | inst.instruction |= Rn << 16; | |
12142 | inst.instruction |= Rm; | |
c19d1205 ZW |
12143 | inst.instruction |= inst.operands[3].imm << 4; |
12144 | } | |
b99bd4ef | 12145 | |
c19d1205 ZW |
12146 | static void |
12147 | do_t_sxth (void) | |
12148 | { | |
fdfde340 JM |
12149 | unsigned Rd, Rm; |
12150 | ||
12151 | Rd = inst.operands[0].reg; | |
12152 | Rm = inst.operands[1].reg; | |
12153 | ||
12154 | reject_bad_reg (Rd); | |
12155 | reject_bad_reg (Rm); | |
c921be7d NC |
12156 | |
12157 | if (inst.instruction <= 0xffff | |
12158 | && inst.size_req != 4 | |
fdfde340 | 12159 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 12160 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 12161 | { |
c19d1205 | 12162 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12163 | inst.instruction |= Rd; |
12164 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12165 | } |
c19d1205 | 12166 | else if (unified_syntax) |
b99bd4ef | 12167 | { |
c19d1205 ZW |
12168 | if (inst.instruction <= 0xffff) |
12169 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12170 | inst.instruction |= Rd << 8; |
12171 | inst.instruction |= Rm; | |
c19d1205 | 12172 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 12173 | } |
c19d1205 | 12174 | else |
b99bd4ef | 12175 | { |
c19d1205 ZW |
12176 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
12177 | _("Thumb encoding does not support rotation")); | |
12178 | constraint (1, BAD_HIREG); | |
b99bd4ef | 12179 | } |
c19d1205 | 12180 | } |
b99bd4ef | 12181 | |
c19d1205 ZW |
12182 | static void |
12183 | do_t_swi (void) | |
12184 | { | |
b2a5fbdc MGD |
12185 | /* We have to do the following check manually as ARM_EXT_OS only applies |
12186 | to ARM_EXT_V6M. */ | |
12187 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
12188 | { | |
ac7f631b NC |
12189 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
12190 | /* This only applies to the v6m howver, not later architectures. */ | |
12191 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
12192 | as_bad (_("SVC is not permitted on this architecture")); |
12193 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
12194 | } | |
12195 | ||
c19d1205 ZW |
12196 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
12197 | } | |
b99bd4ef | 12198 | |
92e90b6e PB |
12199 | static void |
12200 | do_t_tb (void) | |
12201 | { | |
fdfde340 | 12202 | unsigned Rn, Rm; |
92e90b6e PB |
12203 | int half; |
12204 | ||
12205 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 12206 | set_it_insn_type_last (); |
dfa9f0d5 PB |
12207 | constraint (inst.operands[0].immisreg, |
12208 | _("instruction requires register index")); | |
fdfde340 JM |
12209 | |
12210 | Rn = inst.operands[0].reg; | |
12211 | Rm = inst.operands[0].imm; | |
c921be7d | 12212 | |
fdfde340 JM |
12213 | constraint (Rn == REG_SP, BAD_SP); |
12214 | reject_bad_reg (Rm); | |
12215 | ||
92e90b6e PB |
12216 | constraint (!half && inst.operands[0].shifted, |
12217 | _("instruction does not allow shifted index")); | |
fdfde340 | 12218 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
12219 | } |
12220 | ||
c19d1205 ZW |
12221 | static void |
12222 | do_t_usat (void) | |
12223 | { | |
3a21c15a | 12224 | do_t_ssat_usat (0); |
b99bd4ef NC |
12225 | } |
12226 | ||
12227 | static void | |
c19d1205 | 12228 | do_t_usat16 (void) |
b99bd4ef | 12229 | { |
fdfde340 JM |
12230 | unsigned Rd, Rn; |
12231 | ||
12232 | Rd = inst.operands[0].reg; | |
12233 | Rn = inst.operands[2].reg; | |
12234 | ||
12235 | reject_bad_reg (Rd); | |
12236 | reject_bad_reg (Rn); | |
12237 | ||
12238 | inst.instruction |= Rd << 8; | |
c19d1205 | 12239 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 12240 | inst.instruction |= Rn << 16; |
b99bd4ef | 12241 | } |
c19d1205 | 12242 | |
5287ad62 | 12243 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 12244 | |
5287ad62 | 12245 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 12246 | |
5287ad62 JB |
12247 | /* An "invalid" code for the following tables. */ |
12248 | #define N_INV -1u | |
12249 | ||
12250 | struct neon_tab_entry | |
b99bd4ef | 12251 | { |
5287ad62 JB |
12252 | unsigned integer; |
12253 | unsigned float_or_poly; | |
12254 | unsigned scalar_or_imm; | |
12255 | }; | |
5f4273c7 | 12256 | |
5287ad62 JB |
12257 | /* Map overloaded Neon opcodes to their respective encodings. */ |
12258 | #define NEON_ENC_TAB \ | |
12259 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
12260 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
12261 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
12262 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
12263 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
12264 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
12265 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
12266 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
12267 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
12268 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
12269 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
12270 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 12271 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
12272 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
12273 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
12274 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
12275 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
12276 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
12277 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
12278 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
12279 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
12280 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
12281 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
12282 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
12283 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
12284 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
12285 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
12286 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
12287 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
12288 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
12289 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
12290 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
12291 | X(veor, 0x1000110, N_INV, N_INV), \ | |
12292 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
12293 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
12294 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
12295 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
12296 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
12297 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
12298 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
12299 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
12300 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
12301 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
12302 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
12303 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
12304 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
12305 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
12306 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
12307 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
12308 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
12309 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
12310 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
12311 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
12312 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
12313 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
12314 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
12315 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
12316 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
12317 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
12318 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
12319 | |
12320 | enum neon_opc | |
12321 | { | |
12322 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
12323 | NEON_ENC_TAB | |
12324 | #undef X | |
12325 | }; | |
b99bd4ef | 12326 | |
5287ad62 JB |
12327 | static const struct neon_tab_entry neon_enc_tab[] = |
12328 | { | |
12329 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
12330 | NEON_ENC_TAB | |
12331 | #undef X | |
12332 | }; | |
b99bd4ef | 12333 | |
88714cb8 DG |
12334 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
12335 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12336 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12337 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12338 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12339 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12340 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12341 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12342 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12343 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12344 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 12345 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 12346 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 12347 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 12348 | |
88714cb8 DG |
12349 | #define NEON_ENCODE(type, inst) \ |
12350 | do \ | |
12351 | { \ | |
12352 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
12353 | inst.is_neon = 1; \ | |
12354 | } \ | |
12355 | while (0) | |
12356 | ||
12357 | #define check_neon_suffixes \ | |
12358 | do \ | |
12359 | { \ | |
12360 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
12361 | { \ | |
12362 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
12363 | return; \ | |
12364 | } \ | |
12365 | } \ | |
12366 | while (0) | |
12367 | ||
037e8744 JB |
12368 | /* Define shapes for instruction operands. The following mnemonic characters |
12369 | are used in this table: | |
5287ad62 | 12370 | |
037e8744 | 12371 | F - VFP S<n> register |
5287ad62 JB |
12372 | D - Neon D<n> register |
12373 | Q - Neon Q<n> register | |
12374 | I - Immediate | |
12375 | S - Scalar | |
12376 | R - ARM register | |
12377 | L - D<n> register list | |
5f4273c7 | 12378 | |
037e8744 JB |
12379 | This table is used to generate various data: |
12380 | - enumerations of the form NS_DDR to be used as arguments to | |
12381 | neon_select_shape. | |
12382 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 12383 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 12384 | |
037e8744 JB |
12385 | #define NEON_SHAPE_DEF \ |
12386 | X(3, (D, D, D), DOUBLE), \ | |
12387 | X(3, (Q, Q, Q), QUAD), \ | |
12388 | X(3, (D, D, I), DOUBLE), \ | |
12389 | X(3, (Q, Q, I), QUAD), \ | |
12390 | X(3, (D, D, S), DOUBLE), \ | |
12391 | X(3, (Q, Q, S), QUAD), \ | |
12392 | X(2, (D, D), DOUBLE), \ | |
12393 | X(2, (Q, Q), QUAD), \ | |
12394 | X(2, (D, S), DOUBLE), \ | |
12395 | X(2, (Q, S), QUAD), \ | |
12396 | X(2, (D, R), DOUBLE), \ | |
12397 | X(2, (Q, R), QUAD), \ | |
12398 | X(2, (D, I), DOUBLE), \ | |
12399 | X(2, (Q, I), QUAD), \ | |
12400 | X(3, (D, L, D), DOUBLE), \ | |
12401 | X(2, (D, Q), MIXED), \ | |
12402 | X(2, (Q, D), MIXED), \ | |
12403 | X(3, (D, Q, I), MIXED), \ | |
12404 | X(3, (Q, D, I), MIXED), \ | |
12405 | X(3, (Q, D, D), MIXED), \ | |
12406 | X(3, (D, Q, Q), MIXED), \ | |
12407 | X(3, (Q, Q, D), MIXED), \ | |
12408 | X(3, (Q, D, S), MIXED), \ | |
12409 | X(3, (D, Q, S), MIXED), \ | |
12410 | X(4, (D, D, D, I), DOUBLE), \ | |
12411 | X(4, (Q, Q, Q, I), QUAD), \ | |
12412 | X(2, (F, F), SINGLE), \ | |
12413 | X(3, (F, F, F), SINGLE), \ | |
12414 | X(2, (F, I), SINGLE), \ | |
12415 | X(2, (F, D), MIXED), \ | |
12416 | X(2, (D, F), MIXED), \ | |
12417 | X(3, (F, F, I), MIXED), \ | |
12418 | X(4, (R, R, F, F), SINGLE), \ | |
12419 | X(4, (F, F, R, R), SINGLE), \ | |
12420 | X(3, (D, R, R), DOUBLE), \ | |
12421 | X(3, (R, R, D), DOUBLE), \ | |
12422 | X(2, (S, R), SINGLE), \ | |
12423 | X(2, (R, S), SINGLE), \ | |
12424 | X(2, (F, R), SINGLE), \ | |
12425 | X(2, (R, F), SINGLE) | |
12426 | ||
12427 | #define S2(A,B) NS_##A##B | |
12428 | #define S3(A,B,C) NS_##A##B##C | |
12429 | #define S4(A,B,C,D) NS_##A##B##C##D | |
12430 | ||
12431 | #define X(N, L, C) S##N L | |
12432 | ||
5287ad62 JB |
12433 | enum neon_shape |
12434 | { | |
037e8744 JB |
12435 | NEON_SHAPE_DEF, |
12436 | NS_NULL | |
5287ad62 | 12437 | }; |
b99bd4ef | 12438 | |
037e8744 JB |
12439 | #undef X |
12440 | #undef S2 | |
12441 | #undef S3 | |
12442 | #undef S4 | |
12443 | ||
12444 | enum neon_shape_class | |
12445 | { | |
12446 | SC_SINGLE, | |
12447 | SC_DOUBLE, | |
12448 | SC_QUAD, | |
12449 | SC_MIXED | |
12450 | }; | |
12451 | ||
12452 | #define X(N, L, C) SC_##C | |
12453 | ||
12454 | static enum neon_shape_class neon_shape_class[] = | |
12455 | { | |
12456 | NEON_SHAPE_DEF | |
12457 | }; | |
12458 | ||
12459 | #undef X | |
12460 | ||
12461 | enum neon_shape_el | |
12462 | { | |
12463 | SE_F, | |
12464 | SE_D, | |
12465 | SE_Q, | |
12466 | SE_I, | |
12467 | SE_S, | |
12468 | SE_R, | |
12469 | SE_L | |
12470 | }; | |
12471 | ||
12472 | /* Register widths of above. */ | |
12473 | static unsigned neon_shape_el_size[] = | |
12474 | { | |
12475 | 32, | |
12476 | 64, | |
12477 | 128, | |
12478 | 0, | |
12479 | 32, | |
12480 | 32, | |
12481 | 0 | |
12482 | }; | |
12483 | ||
12484 | struct neon_shape_info | |
12485 | { | |
12486 | unsigned els; | |
12487 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
12488 | }; | |
12489 | ||
12490 | #define S2(A,B) { SE_##A, SE_##B } | |
12491 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
12492 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
12493 | ||
12494 | #define X(N, L, C) { N, S##N L } | |
12495 | ||
12496 | static struct neon_shape_info neon_shape_tab[] = | |
12497 | { | |
12498 | NEON_SHAPE_DEF | |
12499 | }; | |
12500 | ||
12501 | #undef X | |
12502 | #undef S2 | |
12503 | #undef S3 | |
12504 | #undef S4 | |
12505 | ||
5287ad62 JB |
12506 | /* Bit masks used in type checking given instructions. |
12507 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
12508 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
12509 | set, various other bits can be set as well in order to modify the meaning of | |
12510 | the type constraint. */ | |
12511 | ||
12512 | enum neon_type_mask | |
12513 | { | |
8e79c3df CM |
12514 | N_S8 = 0x0000001, |
12515 | N_S16 = 0x0000002, | |
12516 | N_S32 = 0x0000004, | |
12517 | N_S64 = 0x0000008, | |
12518 | N_U8 = 0x0000010, | |
12519 | N_U16 = 0x0000020, | |
12520 | N_U32 = 0x0000040, | |
12521 | N_U64 = 0x0000080, | |
12522 | N_I8 = 0x0000100, | |
12523 | N_I16 = 0x0000200, | |
12524 | N_I32 = 0x0000400, | |
12525 | N_I64 = 0x0000800, | |
12526 | N_8 = 0x0001000, | |
12527 | N_16 = 0x0002000, | |
12528 | N_32 = 0x0004000, | |
12529 | N_64 = 0x0008000, | |
12530 | N_P8 = 0x0010000, | |
12531 | N_P16 = 0x0020000, | |
12532 | N_F16 = 0x0040000, | |
12533 | N_F32 = 0x0080000, | |
12534 | N_F64 = 0x0100000, | |
c921be7d NC |
12535 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
12536 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 12537 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
12538 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
12539 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
12540 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
12541 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
12542 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
12543 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
12544 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 12545 | N_UTYP = 0, |
037e8744 | 12546 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
12547 | }; |
12548 | ||
dcbf9037 JB |
12549 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
12550 | ||
5287ad62 JB |
12551 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
12552 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
12553 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
12554 | #define N_SUF_32 (N_SU_32 | N_F32) | |
12555 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
12556 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
12557 | ||
12558 | /* Pass this as the first type argument to neon_check_type to ignore types | |
12559 | altogether. */ | |
12560 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
12561 | ||
037e8744 JB |
12562 | /* Select a "shape" for the current instruction (describing register types or |
12563 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
12564 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
12565 | function of operand parsing, so this function doesn't need to be called. | |
12566 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
12567 | |
12568 | static enum neon_shape | |
037e8744 | 12569 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 12570 | { |
037e8744 JB |
12571 | va_list ap; |
12572 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
12573 | |
12574 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
12575 | many arguments we should have, so this makes the assumption that we have | |
12576 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
12577 | true in the future. */ | |
12578 | if (!inst.operands[1].present) | |
12579 | inst.operands[1] = inst.operands[0]; | |
12580 | ||
037e8744 | 12581 | va_start (ap, shape); |
5f4273c7 | 12582 | |
21d799b5 | 12583 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
12584 | { |
12585 | unsigned j; | |
12586 | int matches = 1; | |
12587 | ||
12588 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
12589 | { | |
12590 | if (!inst.operands[j].present) | |
12591 | { | |
12592 | matches = 0; | |
12593 | break; | |
12594 | } | |
12595 | ||
12596 | switch (neon_shape_tab[shape].el[j]) | |
12597 | { | |
12598 | case SE_F: | |
12599 | if (!(inst.operands[j].isreg | |
12600 | && inst.operands[j].isvec | |
12601 | && inst.operands[j].issingle | |
12602 | && !inst.operands[j].isquad)) | |
12603 | matches = 0; | |
12604 | break; | |
12605 | ||
12606 | case SE_D: | |
12607 | if (!(inst.operands[j].isreg | |
12608 | && inst.operands[j].isvec | |
12609 | && !inst.operands[j].isquad | |
12610 | && !inst.operands[j].issingle)) | |
12611 | matches = 0; | |
12612 | break; | |
12613 | ||
12614 | case SE_R: | |
12615 | if (!(inst.operands[j].isreg | |
12616 | && !inst.operands[j].isvec)) | |
12617 | matches = 0; | |
12618 | break; | |
12619 | ||
12620 | case SE_Q: | |
12621 | if (!(inst.operands[j].isreg | |
12622 | && inst.operands[j].isvec | |
12623 | && inst.operands[j].isquad | |
12624 | && !inst.operands[j].issingle)) | |
12625 | matches = 0; | |
12626 | break; | |
12627 | ||
12628 | case SE_I: | |
12629 | if (!(!inst.operands[j].isreg | |
12630 | && !inst.operands[j].isscalar)) | |
12631 | matches = 0; | |
12632 | break; | |
12633 | ||
12634 | case SE_S: | |
12635 | if (!(!inst.operands[j].isreg | |
12636 | && inst.operands[j].isscalar)) | |
12637 | matches = 0; | |
12638 | break; | |
12639 | ||
12640 | case SE_L: | |
12641 | break; | |
12642 | } | |
3fde54a2 JZ |
12643 | if (!matches) |
12644 | break; | |
037e8744 | 12645 | } |
ad6cec43 MGD |
12646 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
12647 | /* We've matched all the entries in the shape table, and we don't | |
12648 | have any left over operands which have not been matched. */ | |
5287ad62 | 12649 | break; |
037e8744 | 12650 | } |
5f4273c7 | 12651 | |
037e8744 | 12652 | va_end (ap); |
5287ad62 | 12653 | |
037e8744 JB |
12654 | if (shape == NS_NULL && first_shape != NS_NULL) |
12655 | first_error (_("invalid instruction shape")); | |
5287ad62 | 12656 | |
037e8744 JB |
12657 | return shape; |
12658 | } | |
5287ad62 | 12659 | |
037e8744 JB |
12660 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
12661 | means the Q bit should be set). */ | |
12662 | ||
12663 | static int | |
12664 | neon_quad (enum neon_shape shape) | |
12665 | { | |
12666 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 12667 | } |
037e8744 | 12668 | |
5287ad62 JB |
12669 | static void |
12670 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
12671 | unsigned *g_size) | |
12672 | { | |
12673 | /* Allow modification to be made to types which are constrained to be | |
12674 | based on the key element, based on bits set alongside N_EQK. */ | |
12675 | if ((typebits & N_EQK) != 0) | |
12676 | { | |
12677 | if ((typebits & N_HLF) != 0) | |
12678 | *g_size /= 2; | |
12679 | else if ((typebits & N_DBL) != 0) | |
12680 | *g_size *= 2; | |
12681 | if ((typebits & N_SGN) != 0) | |
12682 | *g_type = NT_signed; | |
12683 | else if ((typebits & N_UNS) != 0) | |
12684 | *g_type = NT_unsigned; | |
12685 | else if ((typebits & N_INT) != 0) | |
12686 | *g_type = NT_integer; | |
12687 | else if ((typebits & N_FLT) != 0) | |
12688 | *g_type = NT_float; | |
dcbf9037 JB |
12689 | else if ((typebits & N_SIZ) != 0) |
12690 | *g_type = NT_untyped; | |
5287ad62 JB |
12691 | } |
12692 | } | |
5f4273c7 | 12693 | |
5287ad62 JB |
12694 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
12695 | operand type, i.e. the single type specified in a Neon instruction when it | |
12696 | is the only one given. */ | |
12697 | ||
12698 | static struct neon_type_el | |
12699 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
12700 | { | |
12701 | struct neon_type_el dest = *key; | |
5f4273c7 | 12702 | |
9c2799c2 | 12703 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 12704 | |
5287ad62 JB |
12705 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
12706 | ||
12707 | return dest; | |
12708 | } | |
12709 | ||
12710 | /* Convert Neon type and size into compact bitmask representation. */ | |
12711 | ||
12712 | static enum neon_type_mask | |
12713 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
12714 | { | |
12715 | switch (type) | |
12716 | { | |
12717 | case NT_untyped: | |
12718 | switch (size) | |
12719 | { | |
12720 | case 8: return N_8; | |
12721 | case 16: return N_16; | |
12722 | case 32: return N_32; | |
12723 | case 64: return N_64; | |
12724 | default: ; | |
12725 | } | |
12726 | break; | |
12727 | ||
12728 | case NT_integer: | |
12729 | switch (size) | |
12730 | { | |
12731 | case 8: return N_I8; | |
12732 | case 16: return N_I16; | |
12733 | case 32: return N_I32; | |
12734 | case 64: return N_I64; | |
12735 | default: ; | |
12736 | } | |
12737 | break; | |
12738 | ||
12739 | case NT_float: | |
037e8744 JB |
12740 | switch (size) |
12741 | { | |
8e79c3df | 12742 | case 16: return N_F16; |
037e8744 JB |
12743 | case 32: return N_F32; |
12744 | case 64: return N_F64; | |
12745 | default: ; | |
12746 | } | |
5287ad62 JB |
12747 | break; |
12748 | ||
12749 | case NT_poly: | |
12750 | switch (size) | |
12751 | { | |
12752 | case 8: return N_P8; | |
12753 | case 16: return N_P16; | |
12754 | default: ; | |
12755 | } | |
12756 | break; | |
12757 | ||
12758 | case NT_signed: | |
12759 | switch (size) | |
12760 | { | |
12761 | case 8: return N_S8; | |
12762 | case 16: return N_S16; | |
12763 | case 32: return N_S32; | |
12764 | case 64: return N_S64; | |
12765 | default: ; | |
12766 | } | |
12767 | break; | |
12768 | ||
12769 | case NT_unsigned: | |
12770 | switch (size) | |
12771 | { | |
12772 | case 8: return N_U8; | |
12773 | case 16: return N_U16; | |
12774 | case 32: return N_U32; | |
12775 | case 64: return N_U64; | |
12776 | default: ; | |
12777 | } | |
12778 | break; | |
12779 | ||
12780 | default: ; | |
12781 | } | |
5f4273c7 | 12782 | |
5287ad62 JB |
12783 | return N_UTYP; |
12784 | } | |
12785 | ||
12786 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
12787 | handles the case where a single bit is set in the mask. */ | |
12788 | ||
dcbf9037 | 12789 | static int |
5287ad62 JB |
12790 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12791 | enum neon_type_mask mask) | |
12792 | { | |
dcbf9037 JB |
12793 | if ((mask & N_EQK) != 0) |
12794 | return FAIL; | |
12795 | ||
5287ad62 JB |
12796 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12797 | *size = 8; | |
dcbf9037 | 12798 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12799 | *size = 16; |
dcbf9037 | 12800 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12801 | *size = 32; |
037e8744 | 12802 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12803 | *size = 64; |
dcbf9037 JB |
12804 | else |
12805 | return FAIL; | |
12806 | ||
5287ad62 JB |
12807 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12808 | *type = NT_signed; | |
dcbf9037 | 12809 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12810 | *type = NT_unsigned; |
dcbf9037 | 12811 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12812 | *type = NT_integer; |
dcbf9037 | 12813 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12814 | *type = NT_untyped; |
dcbf9037 | 12815 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12816 | *type = NT_poly; |
037e8744 | 12817 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12818 | *type = NT_float; |
dcbf9037 JB |
12819 | else |
12820 | return FAIL; | |
5f4273c7 | 12821 | |
dcbf9037 | 12822 | return SUCCESS; |
5287ad62 JB |
12823 | } |
12824 | ||
12825 | /* Modify a bitmask of allowed types. This is only needed for type | |
12826 | relaxation. */ | |
12827 | ||
12828 | static unsigned | |
12829 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12830 | { | |
12831 | unsigned size; | |
12832 | enum neon_el_type type; | |
12833 | unsigned destmask; | |
12834 | int i; | |
5f4273c7 | 12835 | |
5287ad62 | 12836 | destmask = 0; |
5f4273c7 | 12837 | |
5287ad62 JB |
12838 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12839 | { | |
21d799b5 NC |
12840 | if (el_type_of_type_chk (&type, &size, |
12841 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12842 | { |
12843 | neon_modify_type_size (mods, &type, &size); | |
12844 | destmask |= type_chk_of_el_type (type, size); | |
12845 | } | |
5287ad62 | 12846 | } |
5f4273c7 | 12847 | |
5287ad62 JB |
12848 | return destmask; |
12849 | } | |
12850 | ||
12851 | /* Check type and return type classification. | |
12852 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12853 | type given in: | |
12854 | - the second operand, if there is one | |
12855 | - the operand, if there is no second operand | |
12856 | - the result, if there are no operands. | |
12857 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12858 | which is set on a per-instruction basis, which is the one which matters when | |
12859 | only one data type is written. | |
12860 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12861 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12862 | |
12863 | static struct neon_type_el | |
12864 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12865 | { | |
12866 | va_list ap; | |
12867 | unsigned i, pass, key_el = 0; | |
12868 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12869 | enum neon_el_type k_type = NT_invtype; | |
12870 | unsigned k_size = -1u; | |
12871 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12872 | unsigned key_allowed = 0; | |
12873 | ||
12874 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12875 | Fill in the missing operand here, if it was omitted. */ | |
12876 | if (els > 1 && !inst.operands[1].present) | |
12877 | inst.operands[1] = inst.operands[0]; | |
12878 | ||
12879 | /* Suck up all the varargs. */ | |
12880 | va_start (ap, ns); | |
12881 | for (i = 0; i < els; i++) | |
12882 | { | |
12883 | unsigned thisarg = va_arg (ap, unsigned); | |
12884 | if (thisarg == N_IGNORE_TYPE) | |
12885 | { | |
12886 | va_end (ap); | |
12887 | return badtype; | |
12888 | } | |
12889 | types[i] = thisarg; | |
12890 | if ((thisarg & N_KEY) != 0) | |
12891 | key_el = i; | |
12892 | } | |
12893 | va_end (ap); | |
12894 | ||
dcbf9037 JB |
12895 | if (inst.vectype.elems > 0) |
12896 | for (i = 0; i < els; i++) | |
12897 | if (inst.operands[i].vectype.type != NT_invtype) | |
12898 | { | |
12899 | first_error (_("types specified in both the mnemonic and operands")); | |
12900 | return badtype; | |
12901 | } | |
12902 | ||
5287ad62 JB |
12903 | /* Duplicate inst.vectype elements here as necessary. |
12904 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12905 | particularly when an insn takes one register and one non-register | |
12906 | operand. */ | |
12907 | if (inst.vectype.elems == 1 && els > 1) | |
12908 | { | |
12909 | unsigned j; | |
12910 | inst.vectype.elems = els; | |
12911 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12912 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12913 | if (j != key_el) |
12914 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12915 | types[j]); | |
12916 | } | |
12917 | else if (inst.vectype.elems == 0 && els > 0) | |
12918 | { | |
12919 | unsigned j; | |
12920 | /* No types were given after the mnemonic, so look for types specified | |
12921 | after each operand. We allow some flexibility here; as long as the | |
12922 | "key" operand has a type, we can infer the others. */ | |
12923 | for (j = 0; j < els; j++) | |
12924 | if (inst.operands[j].vectype.type != NT_invtype) | |
12925 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12926 | ||
12927 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12928 | { |
dcbf9037 JB |
12929 | for (j = 0; j < els; j++) |
12930 | if (inst.operands[j].vectype.type == NT_invtype) | |
12931 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12932 | types[j]); | |
12933 | } | |
12934 | else | |
12935 | { | |
12936 | first_error (_("operand types can't be inferred")); | |
12937 | return badtype; | |
5287ad62 JB |
12938 | } |
12939 | } | |
12940 | else if (inst.vectype.elems != els) | |
12941 | { | |
dcbf9037 | 12942 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12943 | return badtype; |
12944 | } | |
12945 | ||
12946 | for (pass = 0; pass < 2; pass++) | |
12947 | { | |
12948 | for (i = 0; i < els; i++) | |
12949 | { | |
12950 | unsigned thisarg = types[i]; | |
12951 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12952 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12953 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12954 | unsigned g_size = inst.vectype.el[i].size; | |
12955 | ||
12956 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12957 | integer types if sign-specific variants are unavailable. */ | |
12958 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12959 | && (types_allowed & N_SU_ALL) == 0) | |
12960 | g_type = NT_integer; | |
12961 | ||
12962 | /* If only untyped args are allowed, decay any more specific types to | |
12963 | them. Some instructions only care about signs for some element | |
12964 | sizes, so handle that properly. */ | |
12965 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12966 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12967 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12968 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12969 | g_type = NT_untyped; | |
12970 | ||
12971 | if (pass == 0) | |
12972 | { | |
12973 | if ((thisarg & N_KEY) != 0) | |
12974 | { | |
12975 | k_type = g_type; | |
12976 | k_size = g_size; | |
12977 | key_allowed = thisarg & ~N_KEY; | |
12978 | } | |
12979 | } | |
12980 | else | |
12981 | { | |
037e8744 JB |
12982 | if ((thisarg & N_VFP) != 0) |
12983 | { | |
99b253c5 NC |
12984 | enum neon_shape_el regshape; |
12985 | unsigned regwidth, match; | |
12986 | ||
12987 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12988 | if (ns == NS_NULL) | |
12989 | { | |
12990 | first_error (_("invalid instruction shape")); | |
12991 | return badtype; | |
12992 | } | |
12993 | regshape = neon_shape_tab[ns].el[i]; | |
12994 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12995 | |
12996 | /* In VFP mode, operands must match register widths. If we | |
12997 | have a key operand, use its width, else use the width of | |
12998 | the current operand. */ | |
12999 | if (k_size != -1u) | |
13000 | match = k_size; | |
13001 | else | |
13002 | match = g_size; | |
13003 | ||
13004 | if (regwidth != match) | |
13005 | { | |
13006 | first_error (_("operand size must match register width")); | |
13007 | return badtype; | |
13008 | } | |
13009 | } | |
5f4273c7 | 13010 | |
5287ad62 JB |
13011 | if ((thisarg & N_EQK) == 0) |
13012 | { | |
13013 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
13014 | ||
13015 | if ((given_type & types_allowed) == 0) | |
13016 | { | |
dcbf9037 | 13017 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
13018 | return badtype; |
13019 | } | |
13020 | } | |
13021 | else | |
13022 | { | |
13023 | enum neon_el_type mod_k_type = k_type; | |
13024 | unsigned mod_k_size = k_size; | |
13025 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
13026 | if (g_type != mod_k_type || g_size != mod_k_size) | |
13027 | { | |
dcbf9037 | 13028 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
13029 | return badtype; |
13030 | } | |
13031 | } | |
13032 | } | |
13033 | } | |
13034 | } | |
13035 | ||
13036 | return inst.vectype.el[key_el]; | |
13037 | } | |
13038 | ||
037e8744 | 13039 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 13040 | |
037e8744 JB |
13041 | /* Thumb VFP instructions have 0xE in the condition field. */ |
13042 | ||
13043 | static void | |
13044 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 13045 | { |
88714cb8 DG |
13046 | inst.is_neon = 1; |
13047 | ||
5287ad62 | 13048 | if (thumb_mode) |
037e8744 | 13049 | inst.instruction |= 0xe0000000; |
5287ad62 | 13050 | else |
037e8744 | 13051 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
13052 | } |
13053 | ||
037e8744 JB |
13054 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
13055 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
13056 | etc. It is assumed that operand parsing has already been done, and that the | |
13057 | operands are in the form expected by the given opcode (this isn't necessarily | |
13058 | the same as the form in which they were parsed, hence some massaging must | |
13059 | take place before this function is called). | |
13060 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 13061 | |
037e8744 JB |
13062 | static void |
13063 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 13064 | { |
037e8744 | 13065 | const struct asm_opcode *opcode; |
5f4273c7 | 13066 | |
21d799b5 | 13067 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 13068 | |
037e8744 JB |
13069 | if (!opcode) |
13070 | abort (); | |
5287ad62 | 13071 | |
037e8744 JB |
13072 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
13073 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
13074 | _(BAD_FPU)); | |
5287ad62 | 13075 | |
88714cb8 DG |
13076 | inst.is_neon = 1; |
13077 | ||
037e8744 JB |
13078 | if (thumb_mode) |
13079 | { | |
13080 | inst.instruction = opcode->tvalue; | |
13081 | opcode->tencode (); | |
13082 | } | |
13083 | else | |
13084 | { | |
13085 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
13086 | opcode->aencode (); | |
13087 | } | |
13088 | } | |
5287ad62 JB |
13089 | |
13090 | static void | |
037e8744 | 13091 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 13092 | { |
037e8744 JB |
13093 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
13094 | ||
13095 | if (rs == NS_FFF) | |
13096 | { | |
13097 | if (is_add) | |
13098 | do_vfp_nsyn_opcode ("fadds"); | |
13099 | else | |
13100 | do_vfp_nsyn_opcode ("fsubs"); | |
13101 | } | |
13102 | else | |
13103 | { | |
13104 | if (is_add) | |
13105 | do_vfp_nsyn_opcode ("faddd"); | |
13106 | else | |
13107 | do_vfp_nsyn_opcode ("fsubd"); | |
13108 | } | |
13109 | } | |
13110 | ||
13111 | /* Check operand types to see if this is a VFP instruction, and if so call | |
13112 | PFN (). */ | |
13113 | ||
13114 | static int | |
13115 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
13116 | { | |
13117 | enum neon_shape rs; | |
13118 | struct neon_type_el et; | |
13119 | ||
13120 | switch (args) | |
13121 | { | |
13122 | case 2: | |
13123 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13124 | et = neon_check_type (2, rs, | |
13125 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
13126 | break; | |
5f4273c7 | 13127 | |
037e8744 JB |
13128 | case 3: |
13129 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13130 | et = neon_check_type (3, rs, | |
13131 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
13132 | break; | |
13133 | ||
13134 | default: | |
13135 | abort (); | |
13136 | } | |
13137 | ||
13138 | if (et.type != NT_invtype) | |
13139 | { | |
13140 | pfn (rs); | |
13141 | return SUCCESS; | |
13142 | } | |
037e8744 | 13143 | |
99b253c5 | 13144 | inst.error = NULL; |
037e8744 JB |
13145 | return FAIL; |
13146 | } | |
13147 | ||
13148 | static void | |
13149 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
13150 | { | |
13151 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 13152 | |
037e8744 JB |
13153 | if (rs == NS_FFF) |
13154 | { | |
13155 | if (is_mla) | |
13156 | do_vfp_nsyn_opcode ("fmacs"); | |
13157 | else | |
1ee69515 | 13158 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
13159 | } |
13160 | else | |
13161 | { | |
13162 | if (is_mla) | |
13163 | do_vfp_nsyn_opcode ("fmacd"); | |
13164 | else | |
1ee69515 | 13165 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
13166 | } |
13167 | } | |
13168 | ||
62f3b8c8 PB |
13169 | static void |
13170 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
13171 | { | |
13172 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
13173 | ||
13174 | if (rs == NS_FFF) | |
13175 | { | |
13176 | if (is_fma) | |
13177 | do_vfp_nsyn_opcode ("ffmas"); | |
13178 | else | |
13179 | do_vfp_nsyn_opcode ("ffnmas"); | |
13180 | } | |
13181 | else | |
13182 | { | |
13183 | if (is_fma) | |
13184 | do_vfp_nsyn_opcode ("ffmad"); | |
13185 | else | |
13186 | do_vfp_nsyn_opcode ("ffnmad"); | |
13187 | } | |
13188 | } | |
13189 | ||
037e8744 JB |
13190 | static void |
13191 | do_vfp_nsyn_mul (enum neon_shape rs) | |
13192 | { | |
13193 | if (rs == NS_FFF) | |
13194 | do_vfp_nsyn_opcode ("fmuls"); | |
13195 | else | |
13196 | do_vfp_nsyn_opcode ("fmuld"); | |
13197 | } | |
13198 | ||
13199 | static void | |
13200 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
13201 | { | |
13202 | int is_neg = (inst.instruction & 0x80) != 0; | |
13203 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
13204 | ||
13205 | if (rs == NS_FF) | |
13206 | { | |
13207 | if (is_neg) | |
13208 | do_vfp_nsyn_opcode ("fnegs"); | |
13209 | else | |
13210 | do_vfp_nsyn_opcode ("fabss"); | |
13211 | } | |
13212 | else | |
13213 | { | |
13214 | if (is_neg) | |
13215 | do_vfp_nsyn_opcode ("fnegd"); | |
13216 | else | |
13217 | do_vfp_nsyn_opcode ("fabsd"); | |
13218 | } | |
13219 | } | |
13220 | ||
13221 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
13222 | insns belong to Neon, and are handled elsewhere. */ | |
13223 | ||
13224 | static void | |
13225 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
13226 | { | |
13227 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
13228 | if (is_ldm) | |
13229 | { | |
13230 | if (is_dbmode) | |
13231 | do_vfp_nsyn_opcode ("fldmdbs"); | |
13232 | else | |
13233 | do_vfp_nsyn_opcode ("fldmias"); | |
13234 | } | |
13235 | else | |
13236 | { | |
13237 | if (is_dbmode) | |
13238 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13239 | else | |
13240 | do_vfp_nsyn_opcode ("fstmias"); | |
13241 | } | |
13242 | } | |
13243 | ||
037e8744 JB |
13244 | static void |
13245 | do_vfp_nsyn_sqrt (void) | |
13246 | { | |
13247 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13248 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13249 | |
037e8744 JB |
13250 | if (rs == NS_FF) |
13251 | do_vfp_nsyn_opcode ("fsqrts"); | |
13252 | else | |
13253 | do_vfp_nsyn_opcode ("fsqrtd"); | |
13254 | } | |
13255 | ||
13256 | static void | |
13257 | do_vfp_nsyn_div (void) | |
13258 | { | |
13259 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13260 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13261 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13262 | |
037e8744 JB |
13263 | if (rs == NS_FFF) |
13264 | do_vfp_nsyn_opcode ("fdivs"); | |
13265 | else | |
13266 | do_vfp_nsyn_opcode ("fdivd"); | |
13267 | } | |
13268 | ||
13269 | static void | |
13270 | do_vfp_nsyn_nmul (void) | |
13271 | { | |
13272 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13273 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13274 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13275 | |
037e8744 JB |
13276 | if (rs == NS_FFF) |
13277 | { | |
88714cb8 | 13278 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13279 | do_vfp_sp_dyadic (); |
13280 | } | |
13281 | else | |
13282 | { | |
88714cb8 | 13283 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13284 | do_vfp_dp_rd_rn_rm (); |
13285 | } | |
13286 | do_vfp_cond_or_thumb (); | |
13287 | } | |
13288 | ||
13289 | static void | |
13290 | do_vfp_nsyn_cmp (void) | |
13291 | { | |
13292 | if (inst.operands[1].isreg) | |
13293 | { | |
13294 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13295 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13296 | |
037e8744 JB |
13297 | if (rs == NS_FF) |
13298 | { | |
88714cb8 | 13299 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13300 | do_vfp_sp_monadic (); |
13301 | } | |
13302 | else | |
13303 | { | |
88714cb8 | 13304 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13305 | do_vfp_dp_rd_rm (); |
13306 | } | |
13307 | } | |
13308 | else | |
13309 | { | |
13310 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
13311 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
13312 | ||
13313 | switch (inst.instruction & 0x0fffffff) | |
13314 | { | |
13315 | case N_MNEM_vcmp: | |
13316 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
13317 | break; | |
13318 | case N_MNEM_vcmpe: | |
13319 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
13320 | break; | |
13321 | default: | |
13322 | abort (); | |
13323 | } | |
5f4273c7 | 13324 | |
037e8744 JB |
13325 | if (rs == NS_FI) |
13326 | { | |
88714cb8 | 13327 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13328 | do_vfp_sp_compare_z (); |
13329 | } | |
13330 | else | |
13331 | { | |
88714cb8 | 13332 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13333 | do_vfp_dp_rd (); |
13334 | } | |
13335 | } | |
13336 | do_vfp_cond_or_thumb (); | |
13337 | } | |
13338 | ||
13339 | static void | |
13340 | nsyn_insert_sp (void) | |
13341 | { | |
13342 | inst.operands[1] = inst.operands[0]; | |
13343 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 13344 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
13345 | inst.operands[0].isreg = 1; |
13346 | inst.operands[0].writeback = 1; | |
13347 | inst.operands[0].present = 1; | |
13348 | } | |
13349 | ||
13350 | static void | |
13351 | do_vfp_nsyn_push (void) | |
13352 | { | |
13353 | nsyn_insert_sp (); | |
13354 | if (inst.operands[1].issingle) | |
13355 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13356 | else | |
13357 | do_vfp_nsyn_opcode ("fstmdbd"); | |
13358 | } | |
13359 | ||
13360 | static void | |
13361 | do_vfp_nsyn_pop (void) | |
13362 | { | |
13363 | nsyn_insert_sp (); | |
13364 | if (inst.operands[1].issingle) | |
22b5b651 | 13365 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 13366 | else |
22b5b651 | 13367 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
13368 | } |
13369 | ||
13370 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
13371 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
13372 | ||
88714cb8 DG |
13373 | static void |
13374 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 13375 | { |
88714cb8 DG |
13376 | unsigned int i = insn->instruction; |
13377 | insn->is_neon = 1; | |
13378 | ||
037e8744 JB |
13379 | if (thumb_mode) |
13380 | { | |
13381 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
13382 | if (i & (1 << 24)) | |
13383 | i |= 1 << 28; | |
5f4273c7 | 13384 | |
037e8744 | 13385 | i &= ~(1 << 24); |
5f4273c7 | 13386 | |
037e8744 JB |
13387 | i |= 0xef000000; |
13388 | } | |
13389 | else | |
13390 | i |= 0xf2000000; | |
5f4273c7 | 13391 | |
88714cb8 | 13392 | insn->instruction = i; |
037e8744 JB |
13393 | } |
13394 | ||
13395 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
13396 | (0, 1, 2, 3). */ | |
13397 | ||
13398 | static unsigned | |
13399 | neon_logbits (unsigned x) | |
13400 | { | |
13401 | return ffs (x) - 4; | |
13402 | } | |
13403 | ||
13404 | #define LOW4(R) ((R) & 0xf) | |
13405 | #define HI1(R) (((R) >> 4) & 1) | |
13406 | ||
13407 | /* Encode insns with bit pattern: | |
13408 | ||
13409 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
13410 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 13411 | |
037e8744 JB |
13412 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
13413 | different meaning for some instruction. */ | |
13414 | ||
13415 | static void | |
13416 | neon_three_same (int isquad, int ubit, int size) | |
13417 | { | |
13418 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13419 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13420 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13421 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13422 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13423 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
13424 | inst.instruction |= (isquad != 0) << 6; | |
13425 | inst.instruction |= (ubit != 0) << 24; | |
13426 | if (size != -1) | |
13427 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 13428 | |
88714cb8 | 13429 | neon_dp_fixup (&inst); |
037e8744 JB |
13430 | } |
13431 | ||
13432 | /* Encode instructions of the form: | |
13433 | ||
13434 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
13435 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
13436 | |
13437 | Don't write size if SIZE == -1. */ | |
13438 | ||
13439 | static void | |
13440 | neon_two_same (int qbit, int ubit, int size) | |
13441 | { | |
13442 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13443 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13444 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13445 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13446 | inst.instruction |= (qbit != 0) << 6; | |
13447 | inst.instruction |= (ubit != 0) << 24; | |
13448 | ||
13449 | if (size != -1) | |
13450 | inst.instruction |= neon_logbits (size) << 18; | |
13451 | ||
88714cb8 | 13452 | neon_dp_fixup (&inst); |
5287ad62 JB |
13453 | } |
13454 | ||
13455 | /* Neon instruction encoders, in approximate order of appearance. */ | |
13456 | ||
13457 | static void | |
13458 | do_neon_dyadic_i_su (void) | |
13459 | { | |
037e8744 | 13460 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13461 | struct neon_type_el et = neon_check_type (3, rs, |
13462 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 13463 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13464 | } |
13465 | ||
13466 | static void | |
13467 | do_neon_dyadic_i64_su (void) | |
13468 | { | |
037e8744 | 13469 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13470 | struct neon_type_el et = neon_check_type (3, rs, |
13471 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 13472 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13473 | } |
13474 | ||
13475 | static void | |
13476 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
13477 | unsigned immbits) | |
13478 | { | |
13479 | unsigned size = et.size >> 3; | |
13480 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13481 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13482 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13483 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13484 | inst.instruction |= (isquad != 0) << 6; | |
13485 | inst.instruction |= immbits << 16; | |
13486 | inst.instruction |= (size >> 3) << 7; | |
13487 | inst.instruction |= (size & 0x7) << 19; | |
13488 | if (write_ubit) | |
13489 | inst.instruction |= (uval != 0) << 24; | |
13490 | ||
88714cb8 | 13491 | neon_dp_fixup (&inst); |
5287ad62 JB |
13492 | } |
13493 | ||
13494 | static void | |
13495 | do_neon_shl_imm (void) | |
13496 | { | |
13497 | if (!inst.operands[2].isreg) | |
13498 | { | |
037e8744 | 13499 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13500 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 13501 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13502 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
13503 | } |
13504 | else | |
13505 | { | |
037e8744 | 13506 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13507 | struct neon_type_el et = neon_check_type (3, rs, |
13508 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13509 | unsigned int tmp; |
13510 | ||
13511 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
13512 | vshl.xx Dd, Dm, Dn | |
13513 | whereas other 3-register operations encoded by neon_three_same have | |
13514 | syntax like: | |
13515 | vadd.xx Dd, Dn, Dm | |
13516 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
13517 | here. */ | |
13518 | tmp = inst.operands[2].reg; | |
13519 | inst.operands[2].reg = inst.operands[1].reg; | |
13520 | inst.operands[1].reg = tmp; | |
88714cb8 | 13521 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13522 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13523 | } |
13524 | } | |
13525 | ||
13526 | static void | |
13527 | do_neon_qshl_imm (void) | |
13528 | { | |
13529 | if (!inst.operands[2].isreg) | |
13530 | { | |
037e8744 | 13531 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13532 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 13533 | |
88714cb8 | 13534 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13535 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
13536 | inst.operands[2].imm); |
13537 | } | |
13538 | else | |
13539 | { | |
037e8744 | 13540 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13541 | struct neon_type_el et = neon_check_type (3, rs, |
13542 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13543 | unsigned int tmp; |
13544 | ||
13545 | /* See note in do_neon_shl_imm. */ | |
13546 | tmp = inst.operands[2].reg; | |
13547 | inst.operands[2].reg = inst.operands[1].reg; | |
13548 | inst.operands[1].reg = tmp; | |
88714cb8 | 13549 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13550 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13551 | } |
13552 | } | |
13553 | ||
627907b7 JB |
13554 | static void |
13555 | do_neon_rshl (void) | |
13556 | { | |
13557 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
13558 | struct neon_type_el et = neon_check_type (3, rs, | |
13559 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
13560 | unsigned int tmp; | |
13561 | ||
13562 | tmp = inst.operands[2].reg; | |
13563 | inst.operands[2].reg = inst.operands[1].reg; | |
13564 | inst.operands[1].reg = tmp; | |
13565 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
13566 | } | |
13567 | ||
5287ad62 JB |
13568 | static int |
13569 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
13570 | { | |
036dc3f7 PB |
13571 | /* Handle .I8 pseudo-instructions. */ |
13572 | if (size == 8) | |
5287ad62 | 13573 | { |
5287ad62 JB |
13574 | /* Unfortunately, this will make everything apart from zero out-of-range. |
13575 | FIXME is this the intended semantics? There doesn't seem much point in | |
13576 | accepting .I8 if so. */ | |
13577 | immediate |= immediate << 8; | |
13578 | size = 16; | |
036dc3f7 PB |
13579 | } |
13580 | ||
13581 | if (size >= 32) | |
13582 | { | |
13583 | if (immediate == (immediate & 0x000000ff)) | |
13584 | { | |
13585 | *immbits = immediate; | |
13586 | return 0x1; | |
13587 | } | |
13588 | else if (immediate == (immediate & 0x0000ff00)) | |
13589 | { | |
13590 | *immbits = immediate >> 8; | |
13591 | return 0x3; | |
13592 | } | |
13593 | else if (immediate == (immediate & 0x00ff0000)) | |
13594 | { | |
13595 | *immbits = immediate >> 16; | |
13596 | return 0x5; | |
13597 | } | |
13598 | else if (immediate == (immediate & 0xff000000)) | |
13599 | { | |
13600 | *immbits = immediate >> 24; | |
13601 | return 0x7; | |
13602 | } | |
13603 | if ((immediate & 0xffff) != (immediate >> 16)) | |
13604 | goto bad_immediate; | |
13605 | immediate &= 0xffff; | |
5287ad62 JB |
13606 | } |
13607 | ||
13608 | if (immediate == (immediate & 0x000000ff)) | |
13609 | { | |
13610 | *immbits = immediate; | |
036dc3f7 | 13611 | return 0x9; |
5287ad62 JB |
13612 | } |
13613 | else if (immediate == (immediate & 0x0000ff00)) | |
13614 | { | |
13615 | *immbits = immediate >> 8; | |
036dc3f7 | 13616 | return 0xb; |
5287ad62 JB |
13617 | } |
13618 | ||
13619 | bad_immediate: | |
dcbf9037 | 13620 | first_error (_("immediate value out of range")); |
5287ad62 JB |
13621 | return FAIL; |
13622 | } | |
13623 | ||
13624 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
13625 | A, B, C, D. */ | |
13626 | ||
13627 | static int | |
13628 | neon_bits_same_in_bytes (unsigned imm) | |
13629 | { | |
13630 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
13631 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
13632 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
13633 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
13634 | } | |
13635 | ||
13636 | /* For immediate of above form, return 0bABCD. */ | |
13637 | ||
13638 | static unsigned | |
13639 | neon_squash_bits (unsigned imm) | |
13640 | { | |
13641 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
13642 | | ((imm & 0x01000000) >> 21); | |
13643 | } | |
13644 | ||
136da414 | 13645 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
13646 | |
13647 | static unsigned | |
13648 | neon_qfloat_bits (unsigned imm) | |
13649 | { | |
136da414 | 13650 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
13651 | } |
13652 | ||
13653 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
13654 | the instruction. *OP is passed as the initial value of the op field, and | |
13655 | may be set to a different value depending on the constant (i.e. | |
13656 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 13657 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 13658 | try smaller element sizes. */ |
5287ad62 JB |
13659 | |
13660 | static int | |
c96612cc JB |
13661 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
13662 | unsigned *immbits, int *op, int size, | |
13663 | enum neon_el_type type) | |
5287ad62 | 13664 | { |
c96612cc JB |
13665 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
13666 | float. */ | |
13667 | if (type == NT_float && !float_p) | |
13668 | return FAIL; | |
13669 | ||
136da414 JB |
13670 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
13671 | { | |
13672 | if (size != 32 || *op == 1) | |
13673 | return FAIL; | |
13674 | *immbits = neon_qfloat_bits (immlo); | |
13675 | return 0xf; | |
13676 | } | |
036dc3f7 PB |
13677 | |
13678 | if (size == 64) | |
5287ad62 | 13679 | { |
036dc3f7 PB |
13680 | if (neon_bits_same_in_bytes (immhi) |
13681 | && neon_bits_same_in_bytes (immlo)) | |
13682 | { | |
13683 | if (*op == 1) | |
13684 | return FAIL; | |
13685 | *immbits = (neon_squash_bits (immhi) << 4) | |
13686 | | neon_squash_bits (immlo); | |
13687 | *op = 1; | |
13688 | return 0xe; | |
13689 | } | |
13690 | ||
13691 | if (immhi != immlo) | |
13692 | return FAIL; | |
5287ad62 | 13693 | } |
036dc3f7 PB |
13694 | |
13695 | if (size >= 32) | |
5287ad62 | 13696 | { |
036dc3f7 PB |
13697 | if (immlo == (immlo & 0x000000ff)) |
13698 | { | |
13699 | *immbits = immlo; | |
13700 | return 0x0; | |
13701 | } | |
13702 | else if (immlo == (immlo & 0x0000ff00)) | |
13703 | { | |
13704 | *immbits = immlo >> 8; | |
13705 | return 0x2; | |
13706 | } | |
13707 | else if (immlo == (immlo & 0x00ff0000)) | |
13708 | { | |
13709 | *immbits = immlo >> 16; | |
13710 | return 0x4; | |
13711 | } | |
13712 | else if (immlo == (immlo & 0xff000000)) | |
13713 | { | |
13714 | *immbits = immlo >> 24; | |
13715 | return 0x6; | |
13716 | } | |
13717 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
13718 | { | |
13719 | *immbits = (immlo >> 8) & 0xff; | |
13720 | return 0xc; | |
13721 | } | |
13722 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
13723 | { | |
13724 | *immbits = (immlo >> 16) & 0xff; | |
13725 | return 0xd; | |
13726 | } | |
13727 | ||
13728 | if ((immlo & 0xffff) != (immlo >> 16)) | |
13729 | return FAIL; | |
13730 | immlo &= 0xffff; | |
5287ad62 | 13731 | } |
036dc3f7 PB |
13732 | |
13733 | if (size >= 16) | |
5287ad62 | 13734 | { |
036dc3f7 PB |
13735 | if (immlo == (immlo & 0x000000ff)) |
13736 | { | |
13737 | *immbits = immlo; | |
13738 | return 0x8; | |
13739 | } | |
13740 | else if (immlo == (immlo & 0x0000ff00)) | |
13741 | { | |
13742 | *immbits = immlo >> 8; | |
13743 | return 0xa; | |
13744 | } | |
13745 | ||
13746 | if ((immlo & 0xff) != (immlo >> 8)) | |
13747 | return FAIL; | |
13748 | immlo &= 0xff; | |
5287ad62 | 13749 | } |
036dc3f7 PB |
13750 | |
13751 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 13752 | { |
036dc3f7 PB |
13753 | /* Don't allow MVN with 8-bit immediate. */ |
13754 | if (*op == 1) | |
13755 | return FAIL; | |
13756 | *immbits = immlo; | |
13757 | return 0xe; | |
5287ad62 | 13758 | } |
5287ad62 JB |
13759 | |
13760 | return FAIL; | |
13761 | } | |
13762 | ||
13763 | /* Write immediate bits [7:0] to the following locations: | |
13764 | ||
13765 | |28/24|23 19|18 16|15 4|3 0| | |
13766 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
13767 | ||
13768 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
13769 | ||
13770 | static void | |
13771 | neon_write_immbits (unsigned immbits) | |
13772 | { | |
13773 | inst.instruction |= immbits & 0xf; | |
13774 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
13775 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
13776 | } | |
13777 | ||
13778 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
13779 | ||
13780 | static void | |
13781 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
13782 | { | |
13783 | unsigned immlo = xlo ? *xlo : 0; | |
13784 | unsigned immhi = xhi ? *xhi : 0; | |
13785 | ||
13786 | switch (size) | |
13787 | { | |
13788 | case 8: | |
13789 | immlo = (~immlo) & 0xff; | |
13790 | break; | |
13791 | ||
13792 | case 16: | |
13793 | immlo = (~immlo) & 0xffff; | |
13794 | break; | |
13795 | ||
13796 | case 64: | |
13797 | immhi = (~immhi) & 0xffffffff; | |
13798 | /* fall through. */ | |
13799 | ||
13800 | case 32: | |
13801 | immlo = (~immlo) & 0xffffffff; | |
13802 | break; | |
13803 | ||
13804 | default: | |
13805 | abort (); | |
13806 | } | |
13807 | ||
13808 | if (xlo) | |
13809 | *xlo = immlo; | |
13810 | ||
13811 | if (xhi) | |
13812 | *xhi = immhi; | |
13813 | } | |
13814 | ||
13815 | static void | |
13816 | do_neon_logic (void) | |
13817 | { | |
13818 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13819 | { | |
037e8744 | 13820 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13821 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13822 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13823 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13824 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13825 | } |
13826 | else | |
13827 | { | |
4316f0d2 DG |
13828 | const int three_ops_form = (inst.operands[2].present |
13829 | && !inst.operands[2].isreg); | |
13830 | const int immoperand = (three_ops_form ? 2 : 1); | |
13831 | enum neon_shape rs = (three_ops_form | |
13832 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13833 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13834 | struct neon_type_el et = neon_check_type (2, rs, |
13835 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13836 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13837 | unsigned immbits; |
13838 | int cmode; | |
5f4273c7 | 13839 | |
5287ad62 JB |
13840 | if (et.type == NT_invtype) |
13841 | return; | |
5f4273c7 | 13842 | |
4316f0d2 DG |
13843 | if (three_ops_form) |
13844 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13845 | _("first and second operands shall be the same register")); | |
13846 | ||
88714cb8 | 13847 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13848 | |
4316f0d2 | 13849 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13850 | if (et.size == 64) |
13851 | { | |
13852 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13853 | pattern. */ | |
4316f0d2 DG |
13854 | if (immbits != (inst.operands[immoperand].regisimm ? |
13855 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13856 | { |
13857 | /* Set immbits to an invalid constant. */ | |
13858 | immbits = 0xdeadbeef; | |
13859 | } | |
13860 | } | |
13861 | ||
5287ad62 JB |
13862 | switch (opcode) |
13863 | { | |
13864 | case N_MNEM_vbic: | |
036dc3f7 | 13865 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13866 | break; |
5f4273c7 | 13867 | |
5287ad62 | 13868 | case N_MNEM_vorr: |
036dc3f7 | 13869 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13870 | break; |
5f4273c7 | 13871 | |
5287ad62 JB |
13872 | case N_MNEM_vand: |
13873 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13874 | neon_invert_size (&immbits, 0, et.size); |
13875 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13876 | break; | |
5f4273c7 | 13877 | |
5287ad62 JB |
13878 | case N_MNEM_vorn: |
13879 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13880 | neon_invert_size (&immbits, 0, et.size); |
13881 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13882 | break; | |
5f4273c7 | 13883 | |
5287ad62 JB |
13884 | default: |
13885 | abort (); | |
13886 | } | |
13887 | ||
13888 | if (cmode == FAIL) | |
13889 | return; | |
13890 | ||
037e8744 | 13891 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13892 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13893 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13894 | inst.instruction |= cmode << 8; | |
13895 | neon_write_immbits (immbits); | |
5f4273c7 | 13896 | |
88714cb8 | 13897 | neon_dp_fixup (&inst); |
5287ad62 JB |
13898 | } |
13899 | } | |
13900 | ||
13901 | static void | |
13902 | do_neon_bitfield (void) | |
13903 | { | |
037e8744 | 13904 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13905 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13906 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13907 | } |
13908 | ||
13909 | static void | |
dcbf9037 JB |
13910 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13911 | unsigned destbits) | |
5287ad62 | 13912 | { |
037e8744 | 13913 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13914 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13915 | types | N_KEY); | |
5287ad62 JB |
13916 | if (et.type == NT_float) |
13917 | { | |
88714cb8 | 13918 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13919 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13920 | } |
13921 | else | |
13922 | { | |
88714cb8 | 13923 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13924 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13925 | } |
13926 | } | |
13927 | ||
13928 | static void | |
13929 | do_neon_dyadic_if_su (void) | |
13930 | { | |
dcbf9037 | 13931 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13932 | } |
13933 | ||
13934 | static void | |
13935 | do_neon_dyadic_if_su_d (void) | |
13936 | { | |
13937 | /* This version only allow D registers, but that constraint is enforced during | |
13938 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13939 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13940 | } |
13941 | ||
5287ad62 JB |
13942 | static void |
13943 | do_neon_dyadic_if_i_d (void) | |
13944 | { | |
428e3f1f PB |
13945 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13946 | affected if we specify unsigned args. */ | |
13947 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13948 | } |
13949 | ||
037e8744 JB |
13950 | enum vfp_or_neon_is_neon_bits |
13951 | { | |
13952 | NEON_CHECK_CC = 1, | |
13953 | NEON_CHECK_ARCH = 2 | |
13954 | }; | |
13955 | ||
13956 | /* Call this function if an instruction which may have belonged to the VFP or | |
13957 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13958 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13959 | things: | |
13960 | ||
13961 | - Make sure the user hasn't attempted to make a Neon instruction | |
13962 | conditional. | |
13963 | - Alter the value in the condition code field if necessary. | |
13964 | - Make sure that the arch supports Neon instructions. | |
13965 | ||
13966 | Which of these operations take place depends on bits from enum | |
13967 | vfp_or_neon_is_neon_bits. | |
13968 | ||
13969 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13970 | current instruction's condition is COND_ALWAYS, the condition field is | |
13971 | changed to inst.uncond_value. This is necessary because instructions shared | |
13972 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13973 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13974 | ||
13975 | static int | |
13976 | vfp_or_neon_is_neon (unsigned check) | |
13977 | { | |
13978 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13979 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13980 | { | |
13981 | if (inst.cond != COND_ALWAYS) | |
13982 | { | |
13983 | first_error (_(BAD_COND)); | |
13984 | return FAIL; | |
13985 | } | |
13986 | if (inst.uncond_value != -1) | |
13987 | inst.instruction |= inst.uncond_value << 28; | |
13988 | } | |
5f4273c7 | 13989 | |
037e8744 JB |
13990 | if ((check & NEON_CHECK_ARCH) |
13991 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13992 | { | |
13993 | first_error (_(BAD_FPU)); | |
13994 | return FAIL; | |
13995 | } | |
5f4273c7 | 13996 | |
037e8744 JB |
13997 | return SUCCESS; |
13998 | } | |
13999 | ||
5287ad62 JB |
14000 | static void |
14001 | do_neon_addsub_if_i (void) | |
14002 | { | |
037e8744 JB |
14003 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
14004 | return; | |
14005 | ||
14006 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14007 | return; | |
14008 | ||
5287ad62 JB |
14009 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14010 | affected if we specify unsigned args. */ | |
dcbf9037 | 14011 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
14012 | } |
14013 | ||
14014 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
14015 | result to be: | |
14016 | V<op> A,B (A is operand 0, B is operand 2) | |
14017 | to mean: | |
14018 | V<op> A,B,A | |
14019 | not: | |
14020 | V<op> A,B,B | |
14021 | so handle that case specially. */ | |
14022 | ||
14023 | static void | |
14024 | neon_exchange_operands (void) | |
14025 | { | |
14026 | void *scratch = alloca (sizeof (inst.operands[0])); | |
14027 | if (inst.operands[1].present) | |
14028 | { | |
14029 | /* Swap operands[1] and operands[2]. */ | |
14030 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
14031 | inst.operands[1] = inst.operands[2]; | |
14032 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
14033 | } | |
14034 | else | |
14035 | { | |
14036 | inst.operands[1] = inst.operands[2]; | |
14037 | inst.operands[2] = inst.operands[0]; | |
14038 | } | |
14039 | } | |
14040 | ||
14041 | static void | |
14042 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
14043 | { | |
14044 | if (inst.operands[2].isreg) | |
14045 | { | |
14046 | if (invert) | |
14047 | neon_exchange_operands (); | |
dcbf9037 | 14048 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
14049 | } |
14050 | else | |
14051 | { | |
037e8744 | 14052 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
14053 | struct neon_type_el et = neon_check_type (2, rs, |
14054 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 14055 | |
88714cb8 | 14056 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14057 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14058 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14059 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14060 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14061 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14062 | inst.instruction |= (et.type == NT_float) << 10; |
14063 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14064 | |
88714cb8 | 14065 | neon_dp_fixup (&inst); |
5287ad62 JB |
14066 | } |
14067 | } | |
14068 | ||
14069 | static void | |
14070 | do_neon_cmp (void) | |
14071 | { | |
14072 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
14073 | } | |
14074 | ||
14075 | static void | |
14076 | do_neon_cmp_inv (void) | |
14077 | { | |
14078 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
14079 | } | |
14080 | ||
14081 | static void | |
14082 | do_neon_ceq (void) | |
14083 | { | |
14084 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
14085 | } | |
14086 | ||
14087 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
14088 | scalars, which are encoded in 5 bits, M : Rm. | |
14089 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
14090 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
14091 | index in M. */ | |
14092 | ||
14093 | static unsigned | |
14094 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
14095 | { | |
dcbf9037 JB |
14096 | unsigned regno = NEON_SCALAR_REG (scalar); |
14097 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
14098 | |
14099 | switch (elsize) | |
14100 | { | |
14101 | case 16: | |
14102 | if (regno > 7 || elno > 3) | |
14103 | goto bad_scalar; | |
14104 | return regno | (elno << 3); | |
5f4273c7 | 14105 | |
5287ad62 JB |
14106 | case 32: |
14107 | if (regno > 15 || elno > 1) | |
14108 | goto bad_scalar; | |
14109 | return regno | (elno << 4); | |
14110 | ||
14111 | default: | |
14112 | bad_scalar: | |
dcbf9037 | 14113 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
14114 | } |
14115 | ||
14116 | return 0; | |
14117 | } | |
14118 | ||
14119 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
14120 | ||
14121 | static void | |
14122 | neon_mul_mac (struct neon_type_el et, int ubit) | |
14123 | { | |
dcbf9037 JB |
14124 | unsigned scalar; |
14125 | ||
14126 | /* Give a more helpful error message if we have an invalid type. */ | |
14127 | if (et.type == NT_invtype) | |
14128 | return; | |
5f4273c7 | 14129 | |
dcbf9037 | 14130 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
14131 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14132 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14133 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14134 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14135 | inst.instruction |= LOW4 (scalar); | |
14136 | inst.instruction |= HI1 (scalar) << 5; | |
14137 | inst.instruction |= (et.type == NT_float) << 8; | |
14138 | inst.instruction |= neon_logbits (et.size) << 20; | |
14139 | inst.instruction |= (ubit != 0) << 24; | |
14140 | ||
88714cb8 | 14141 | neon_dp_fixup (&inst); |
5287ad62 JB |
14142 | } |
14143 | ||
14144 | static void | |
14145 | do_neon_mac_maybe_scalar (void) | |
14146 | { | |
037e8744 JB |
14147 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
14148 | return; | |
14149 | ||
14150 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14151 | return; | |
14152 | ||
5287ad62 JB |
14153 | if (inst.operands[2].isscalar) |
14154 | { | |
037e8744 | 14155 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
14156 | struct neon_type_el et = neon_check_type (3, rs, |
14157 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 14158 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14159 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14160 | } |
14161 | else | |
428e3f1f PB |
14162 | { |
14163 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
14164 | affected if we specify unsigned args. */ | |
14165 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14166 | } | |
5287ad62 JB |
14167 | } |
14168 | ||
62f3b8c8 PB |
14169 | static void |
14170 | do_neon_fmac (void) | |
14171 | { | |
14172 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
14173 | return; | |
14174 | ||
14175 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14176 | return; | |
14177 | ||
14178 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14179 | } | |
14180 | ||
5287ad62 JB |
14181 | static void |
14182 | do_neon_tst (void) | |
14183 | { | |
037e8744 | 14184 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14185 | struct neon_type_el et = neon_check_type (3, rs, |
14186 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 14187 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14188 | } |
14189 | ||
14190 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
14191 | same types as the MAC equivalents. The polynomial type for this instruction | |
14192 | is encoded the same as the integer type. */ | |
14193 | ||
14194 | static void | |
14195 | do_neon_mul (void) | |
14196 | { | |
037e8744 JB |
14197 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
14198 | return; | |
14199 | ||
14200 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14201 | return; | |
14202 | ||
5287ad62 JB |
14203 | if (inst.operands[2].isscalar) |
14204 | do_neon_mac_maybe_scalar (); | |
14205 | else | |
dcbf9037 | 14206 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
14207 | } |
14208 | ||
14209 | static void | |
14210 | do_neon_qdmulh (void) | |
14211 | { | |
14212 | if (inst.operands[2].isscalar) | |
14213 | { | |
037e8744 | 14214 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
14215 | struct neon_type_el et = neon_check_type (3, rs, |
14216 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 14217 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14218 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14219 | } |
14220 | else | |
14221 | { | |
037e8744 | 14222 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14223 | struct neon_type_el et = neon_check_type (3, rs, |
14224 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 14225 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14226 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14227 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14228 | } |
14229 | } | |
14230 | ||
14231 | static void | |
14232 | do_neon_fcmp_absolute (void) | |
14233 | { | |
037e8744 | 14234 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14235 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14236 | /* Size field comes from bit mask. */ | |
037e8744 | 14237 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14238 | } |
14239 | ||
14240 | static void | |
14241 | do_neon_fcmp_absolute_inv (void) | |
14242 | { | |
14243 | neon_exchange_operands (); | |
14244 | do_neon_fcmp_absolute (); | |
14245 | } | |
14246 | ||
14247 | static void | |
14248 | do_neon_step (void) | |
14249 | { | |
037e8744 | 14250 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14251 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14252 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14253 | } |
14254 | ||
14255 | static void | |
14256 | do_neon_abs_neg (void) | |
14257 | { | |
037e8744 JB |
14258 | enum neon_shape rs; |
14259 | struct neon_type_el et; | |
5f4273c7 | 14260 | |
037e8744 JB |
14261 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14262 | return; | |
14263 | ||
14264 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14265 | return; | |
14266 | ||
14267 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14268 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14269 | |
5287ad62 JB |
14270 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14271 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14272 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14273 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14274 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14275 | inst.instruction |= (et.type == NT_float) << 10; |
14276 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14277 | |
88714cb8 | 14278 | neon_dp_fixup (&inst); |
5287ad62 JB |
14279 | } |
14280 | ||
14281 | static void | |
14282 | do_neon_sli (void) | |
14283 | { | |
037e8744 | 14284 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14285 | struct neon_type_el et = neon_check_type (2, rs, |
14286 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14287 | int imm = inst.operands[2].imm; | |
14288 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14289 | _("immediate out of range for insert")); | |
037e8744 | 14290 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14291 | } |
14292 | ||
14293 | static void | |
14294 | do_neon_sri (void) | |
14295 | { | |
037e8744 | 14296 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14297 | struct neon_type_el et = neon_check_type (2, rs, |
14298 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14299 | int imm = inst.operands[2].imm; | |
14300 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14301 | _("immediate out of range for insert")); | |
037e8744 | 14302 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14303 | } |
14304 | ||
14305 | static void | |
14306 | do_neon_qshlu_imm (void) | |
14307 | { | |
037e8744 | 14308 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14309 | struct neon_type_el et = neon_check_type (2, rs, |
14310 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14311 | int imm = inst.operands[2].imm; | |
14312 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14313 | _("immediate out of range for shift")); | |
14314 | /* Only encodes the 'U present' variant of the instruction. | |
14315 | In this case, signed types have OP (bit 8) set to 0. | |
14316 | Unsigned types have OP set to 1. */ | |
14317 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14318 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14319 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14320 | } |
14321 | ||
14322 | static void | |
14323 | do_neon_qmovn (void) | |
14324 | { | |
14325 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14326 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14327 | /* Saturating move where operands can be signed or unsigned, and the | |
14328 | destination has the same signedness. */ | |
88714cb8 | 14329 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14330 | if (et.type == NT_unsigned) |
14331 | inst.instruction |= 0xc0; | |
14332 | else | |
14333 | inst.instruction |= 0x80; | |
14334 | neon_two_same (0, 1, et.size / 2); | |
14335 | } | |
14336 | ||
14337 | static void | |
14338 | do_neon_qmovun (void) | |
14339 | { | |
14340 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14341 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14342 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14343 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14344 | neon_two_same (0, 1, et.size / 2); |
14345 | } | |
14346 | ||
14347 | static void | |
14348 | do_neon_rshift_sat_narrow (void) | |
14349 | { | |
14350 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14351 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14352 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14353 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14354 | int imm = inst.operands[2].imm; | |
14355 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14356 | right. */ | |
14357 | et.size /= 2; | |
5f4273c7 | 14358 | |
5287ad62 JB |
14359 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14360 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14361 | if (imm == 0) | |
14362 | { | |
14363 | inst.operands[2].present = 0; | |
14364 | inst.instruction = N_MNEM_vqmovn; | |
14365 | do_neon_qmovn (); | |
14366 | return; | |
14367 | } | |
5f4273c7 | 14368 | |
5287ad62 JB |
14369 | constraint (imm < 1 || (unsigned)imm > et.size, |
14370 | _("immediate out of range")); | |
14371 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
14372 | } | |
14373 | ||
14374 | static void | |
14375 | do_neon_rshift_sat_narrow_u (void) | |
14376 | { | |
14377 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14378 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14379 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14380 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14381 | int imm = inst.operands[2].imm; | |
14382 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14383 | right. */ | |
14384 | et.size /= 2; | |
14385 | ||
14386 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14387 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14388 | if (imm == 0) | |
14389 | { | |
14390 | inst.operands[2].present = 0; | |
14391 | inst.instruction = N_MNEM_vqmovun; | |
14392 | do_neon_qmovun (); | |
14393 | return; | |
14394 | } | |
14395 | ||
14396 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14397 | _("immediate out of range")); | |
14398 | /* FIXME: The manual is kind of unclear about what value U should have in | |
14399 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
14400 | must be 1. */ | |
14401 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
14402 | } | |
14403 | ||
14404 | static void | |
14405 | do_neon_movn (void) | |
14406 | { | |
14407 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14408 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 14409 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14410 | neon_two_same (0, 1, et.size / 2); |
14411 | } | |
14412 | ||
14413 | static void | |
14414 | do_neon_rshift_narrow (void) | |
14415 | { | |
14416 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14417 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
14418 | int imm = inst.operands[2].imm; | |
14419 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14420 | right. */ | |
14421 | et.size /= 2; | |
5f4273c7 | 14422 | |
5287ad62 JB |
14423 | /* If immediate is zero then we are a pseudo-instruction for |
14424 | VMOVN.I<size> <Dd>, <Qm> */ | |
14425 | if (imm == 0) | |
14426 | { | |
14427 | inst.operands[2].present = 0; | |
14428 | inst.instruction = N_MNEM_vmovn; | |
14429 | do_neon_movn (); | |
14430 | return; | |
14431 | } | |
5f4273c7 | 14432 | |
5287ad62 JB |
14433 | constraint (imm < 1 || (unsigned)imm > et.size, |
14434 | _("immediate out of range for narrowing operation")); | |
14435 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
14436 | } | |
14437 | ||
14438 | static void | |
14439 | do_neon_shll (void) | |
14440 | { | |
14441 | /* FIXME: Type checking when lengthening. */ | |
14442 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14443 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14444 | unsigned imm = inst.operands[2].imm; | |
14445 | ||
14446 | if (imm == et.size) | |
14447 | { | |
14448 | /* Maximum shift variant. */ | |
88714cb8 | 14449 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14450 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14451 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14452 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14453 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14454 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14455 | |
88714cb8 | 14456 | neon_dp_fixup (&inst); |
5287ad62 JB |
14457 | } |
14458 | else | |
14459 | { | |
14460 | /* A more-specific type check for non-max versions. */ | |
14461 | et = neon_check_type (2, NS_QDI, | |
14462 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 14463 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14464 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14465 | } | |
14466 | } | |
14467 | ||
037e8744 | 14468 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14469 | the current instruction is. */ |
14470 | ||
14471 | static int | |
14472 | neon_cvt_flavour (enum neon_shape rs) | |
14473 | { | |
037e8744 JB |
14474 | #define CVT_VAR(C,X,Y) \ |
14475 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
14476 | if (et.type != NT_invtype) \ | |
14477 | { \ | |
14478 | inst.error = NULL; \ | |
14479 | return (C); \ | |
5287ad62 JB |
14480 | } |
14481 | struct neon_type_el et; | |
037e8744 JB |
14482 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
14483 | || rs == NS_FF) ? N_VFP : 0; | |
14484 | /* The instruction versions which take an immediate take one register | |
14485 | argument, which is extended to the width of the full register. Thus the | |
14486 | "source" and "destination" registers must have the same width. Hack that | |
14487 | here by making the size equal to the key (wider, in this case) operand. */ | |
14488 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14489 | |
5287ad62 JB |
14490 | CVT_VAR (0, N_S32, N_F32); |
14491 | CVT_VAR (1, N_U32, N_F32); | |
14492 | CVT_VAR (2, N_F32, N_S32); | |
14493 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
14494 | /* Half-precision conversions. */ |
14495 | CVT_VAR (4, N_F32, N_F16); | |
14496 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 14497 | |
037e8744 | 14498 | whole_reg = N_VFP; |
5f4273c7 | 14499 | |
037e8744 | 14500 | /* VFP instructions. */ |
8e79c3df CM |
14501 | CVT_VAR (6, N_F32, N_F64); |
14502 | CVT_VAR (7, N_F64, N_F32); | |
14503 | CVT_VAR (8, N_S32, N_F64 | key); | |
14504 | CVT_VAR (9, N_U32, N_F64 | key); | |
14505 | CVT_VAR (10, N_F64 | key, N_S32); | |
14506 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 14507 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
14508 | CVT_VAR (12, N_F32 | key, N_S16); |
14509 | CVT_VAR (13, N_F32 | key, N_U16); | |
14510 | CVT_VAR (14, N_F64 | key, N_S16); | |
14511 | CVT_VAR (15, N_F64 | key, N_U16); | |
14512 | CVT_VAR (16, N_S16, N_F32 | key); | |
14513 | CVT_VAR (17, N_U16, N_F32 | key); | |
14514 | CVT_VAR (18, N_S16, N_F64 | key); | |
14515 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 14516 | |
5287ad62 JB |
14517 | return -1; |
14518 | #undef CVT_VAR | |
14519 | } | |
14520 | ||
037e8744 JB |
14521 | /* Neon-syntax VFP conversions. */ |
14522 | ||
5287ad62 | 14523 | static void |
037e8744 | 14524 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 14525 | { |
037e8744 | 14526 | const char *opname = 0; |
5f4273c7 | 14527 | |
037e8744 | 14528 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14529 | { |
037e8744 JB |
14530 | /* Conversions with immediate bitshift. */ |
14531 | const char *enc[] = | |
14532 | { | |
14533 | "ftosls", | |
14534 | "ftouls", | |
14535 | "fsltos", | |
14536 | "fultos", | |
14537 | NULL, | |
14538 | NULL, | |
8e79c3df CM |
14539 | NULL, |
14540 | NULL, | |
037e8744 JB |
14541 | "ftosld", |
14542 | "ftould", | |
14543 | "fsltod", | |
14544 | "fultod", | |
14545 | "fshtos", | |
14546 | "fuhtos", | |
14547 | "fshtod", | |
14548 | "fuhtod", | |
14549 | "ftoshs", | |
14550 | "ftouhs", | |
14551 | "ftoshd", | |
14552 | "ftouhd" | |
14553 | }; | |
14554 | ||
14555 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14556 | { | |
14557 | opname = enc[flavour]; | |
14558 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14559 | _("operands 0 and 1 must be the same register")); | |
14560 | inst.operands[1] = inst.operands[2]; | |
14561 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
14562 | } | |
5287ad62 JB |
14563 | } |
14564 | else | |
14565 | { | |
037e8744 JB |
14566 | /* Conversions without bitshift. */ |
14567 | const char *enc[] = | |
14568 | { | |
14569 | "ftosis", | |
14570 | "ftouis", | |
14571 | "fsitos", | |
14572 | "fuitos", | |
8e79c3df CM |
14573 | "NULL", |
14574 | "NULL", | |
037e8744 JB |
14575 | "fcvtsd", |
14576 | "fcvtds", | |
14577 | "ftosid", | |
14578 | "ftouid", | |
14579 | "fsitod", | |
14580 | "fuitod" | |
14581 | }; | |
14582 | ||
14583 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14584 | opname = enc[flavour]; | |
14585 | } | |
14586 | ||
14587 | if (opname) | |
14588 | do_vfp_nsyn_opcode (opname); | |
14589 | } | |
14590 | ||
14591 | static void | |
14592 | do_vfp_nsyn_cvtz (void) | |
14593 | { | |
14594 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
14595 | int flavour = neon_cvt_flavour (rs); | |
14596 | const char *enc[] = | |
14597 | { | |
14598 | "ftosizs", | |
14599 | "ftouizs", | |
14600 | NULL, | |
14601 | NULL, | |
14602 | NULL, | |
14603 | NULL, | |
8e79c3df CM |
14604 | NULL, |
14605 | NULL, | |
037e8744 JB |
14606 | "ftosizd", |
14607 | "ftouizd" | |
14608 | }; | |
14609 | ||
14610 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
14611 | do_vfp_nsyn_opcode (enc[flavour]); | |
14612 | } | |
f31fef98 | 14613 | |
037e8744 | 14614 | static void |
e3e535bc | 14615 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
14616 | { |
14617 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 14618 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
14619 | int flavour = neon_cvt_flavour (rs); |
14620 | ||
e3e535bc NC |
14621 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
14622 | if (round_to_zero | |
14623 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
14624 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
14625 | && (rs == NS_FD || rs == NS_FF)) | |
14626 | { | |
14627 | do_vfp_nsyn_cvtz (); | |
14628 | return; | |
14629 | } | |
14630 | ||
037e8744 | 14631 | /* VFP rather than Neon conversions. */ |
8e79c3df | 14632 | if (flavour >= 6) |
037e8744 JB |
14633 | { |
14634 | do_vfp_nsyn_cvt (rs, flavour); | |
14635 | return; | |
14636 | } | |
14637 | ||
14638 | switch (rs) | |
14639 | { | |
14640 | case NS_DDI: | |
14641 | case NS_QQI: | |
14642 | { | |
35997600 NC |
14643 | unsigned immbits; |
14644 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
14645 | ||
037e8744 JB |
14646 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
14647 | return; | |
14648 | ||
14649 | /* Fixed-point conversion with #0 immediate is encoded as an | |
14650 | integer conversion. */ | |
14651 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
14652 | goto int_encode; | |
35997600 | 14653 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 14654 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
14655 | if (flavour != -1) |
14656 | inst.instruction |= enctab[flavour]; | |
14657 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14658 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14659 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14660 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14661 | inst.instruction |= neon_quad (rs) << 6; | |
14662 | inst.instruction |= 1 << 21; | |
14663 | inst.instruction |= immbits << 16; | |
14664 | ||
88714cb8 | 14665 | neon_dp_fixup (&inst); |
037e8744 JB |
14666 | } |
14667 | break; | |
14668 | ||
14669 | case NS_DD: | |
14670 | case NS_QQ: | |
14671 | int_encode: | |
14672 | { | |
14673 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
14674 | ||
88714cb8 | 14675 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
14676 | |
14677 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14678 | return; | |
14679 | ||
14680 | if (flavour != -1) | |
14681 | inst.instruction |= enctab[flavour]; | |
14682 | ||
14683 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14684 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14685 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14686 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14687 | inst.instruction |= neon_quad (rs) << 6; | |
14688 | inst.instruction |= 2 << 18; | |
14689 | ||
88714cb8 | 14690 | neon_dp_fixup (&inst); |
037e8744 JB |
14691 | } |
14692 | break; | |
14693 | ||
8e79c3df CM |
14694 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
14695 | case NS_QD: | |
14696 | case NS_DQ: | |
14697 | ||
14698 | if ((rs == NS_DQ) | |
14699 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
14700 | { | |
14701 | as_bad (_("operand size must match register width")); | |
14702 | break; | |
14703 | } | |
14704 | ||
14705 | if ((rs == NS_QD) | |
14706 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
14707 | { | |
14708 | as_bad (_("operand size must match register width")); | |
14709 | break; | |
14710 | } | |
14711 | ||
14712 | if (rs == NS_DQ) | |
14713 | inst.instruction = 0x3b60600; | |
14714 | else | |
14715 | inst.instruction = 0x3b60700; | |
14716 | ||
14717 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14718 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14719 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14720 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 14721 | neon_dp_fixup (&inst); |
8e79c3df CM |
14722 | break; |
14723 | ||
037e8744 JB |
14724 | default: |
14725 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
14726 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 14727 | } |
5287ad62 JB |
14728 | } |
14729 | ||
e3e535bc NC |
14730 | static void |
14731 | do_neon_cvtr (void) | |
14732 | { | |
14733 | do_neon_cvt_1 (FALSE); | |
14734 | } | |
14735 | ||
14736 | static void | |
14737 | do_neon_cvt (void) | |
14738 | { | |
14739 | do_neon_cvt_1 (TRUE); | |
14740 | } | |
14741 | ||
8e79c3df CM |
14742 | static void |
14743 | do_neon_cvtb (void) | |
14744 | { | |
14745 | inst.instruction = 0xeb20a40; | |
14746 | ||
14747 | /* The sizes are attached to the mnemonic. */ | |
14748 | if (inst.vectype.el[0].type != NT_invtype | |
14749 | && inst.vectype.el[0].size == 16) | |
14750 | inst.instruction |= 0x00010000; | |
14751 | ||
14752 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
14753 | else if (inst.operands[0].vectype.type != NT_invtype | |
14754 | && inst.operands[0].vectype.size == 16) | |
14755 | inst.instruction |= 0x00010000; | |
14756 | ||
14757 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
14758 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
14759 | do_vfp_cond_or_thumb (); | |
14760 | } | |
14761 | ||
14762 | ||
14763 | static void | |
14764 | do_neon_cvtt (void) | |
14765 | { | |
14766 | do_neon_cvtb (); | |
14767 | inst.instruction |= 0x80; | |
14768 | } | |
14769 | ||
5287ad62 JB |
14770 | static void |
14771 | neon_move_immediate (void) | |
14772 | { | |
037e8744 JB |
14773 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
14774 | struct neon_type_el et = neon_check_type (2, rs, | |
14775 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 14776 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 14777 | int op, cmode, float_p; |
5287ad62 | 14778 | |
037e8744 JB |
14779 | constraint (et.type == NT_invtype, |
14780 | _("operand size must be specified for immediate VMOV")); | |
14781 | ||
5287ad62 JB |
14782 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
14783 | op = (inst.instruction & (1 << 5)) != 0; | |
14784 | ||
14785 | immlo = inst.operands[1].imm; | |
14786 | if (inst.operands[1].regisimm) | |
14787 | immhi = inst.operands[1].reg; | |
14788 | ||
14789 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14790 | _("immediate has bits set outside the operand size")); | |
14791 | ||
c96612cc JB |
14792 | float_p = inst.operands[1].immisfloat; |
14793 | ||
14794 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14795 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14796 | { |
14797 | /* Invert relevant bits only. */ | |
14798 | neon_invert_size (&immlo, &immhi, et.size); | |
14799 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14800 | with one or the other; those cases are caught by | |
14801 | neon_cmode_for_move_imm. */ | |
14802 | op = !op; | |
c96612cc JB |
14803 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14804 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14805 | { |
dcbf9037 | 14806 | first_error (_("immediate out of range")); |
5287ad62 JB |
14807 | return; |
14808 | } | |
14809 | } | |
14810 | ||
14811 | inst.instruction &= ~(1 << 5); | |
14812 | inst.instruction |= op << 5; | |
14813 | ||
14814 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14815 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14816 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14817 | inst.instruction |= cmode << 8; |
14818 | ||
14819 | neon_write_immbits (immbits); | |
14820 | } | |
14821 | ||
14822 | static void | |
14823 | do_neon_mvn (void) | |
14824 | { | |
14825 | if (inst.operands[1].isreg) | |
14826 | { | |
037e8744 | 14827 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14828 | |
88714cb8 | 14829 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14830 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14831 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14832 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14833 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14834 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14835 | } |
14836 | else | |
14837 | { | |
88714cb8 | 14838 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14839 | neon_move_immediate (); |
14840 | } | |
14841 | ||
88714cb8 | 14842 | neon_dp_fixup (&inst); |
5287ad62 JB |
14843 | } |
14844 | ||
14845 | /* Encode instructions of form: | |
14846 | ||
14847 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14848 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14849 | |
14850 | static void | |
14851 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14852 | { | |
14853 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14854 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14855 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14856 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14857 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14858 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14859 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14860 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14861 | |
88714cb8 | 14862 | neon_dp_fixup (&inst); |
5287ad62 JB |
14863 | } |
14864 | ||
14865 | static void | |
14866 | do_neon_dyadic_long (void) | |
14867 | { | |
14868 | /* FIXME: Type checking for lengthening op. */ | |
14869 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14870 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14871 | neon_mixed_length (et, et.size); | |
14872 | } | |
14873 | ||
14874 | static void | |
14875 | do_neon_abal (void) | |
14876 | { | |
14877 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14878 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14879 | neon_mixed_length (et, et.size); | |
14880 | } | |
14881 | ||
14882 | static void | |
14883 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14884 | { | |
14885 | if (inst.operands[2].isscalar) | |
14886 | { | |
dcbf9037 JB |
14887 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14888 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14889 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14890 | neon_mul_mac (et, et.type == NT_unsigned); |
14891 | } | |
14892 | else | |
14893 | { | |
14894 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14895 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14896 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14897 | neon_mixed_length (et, et.size); |
14898 | } | |
14899 | } | |
14900 | ||
14901 | static void | |
14902 | do_neon_mac_maybe_scalar_long (void) | |
14903 | { | |
14904 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14905 | } | |
14906 | ||
14907 | static void | |
14908 | do_neon_dyadic_wide (void) | |
14909 | { | |
14910 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14911 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14912 | neon_mixed_length (et, et.size); | |
14913 | } | |
14914 | ||
14915 | static void | |
14916 | do_neon_dyadic_narrow (void) | |
14917 | { | |
14918 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14919 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14920 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14921 | so force the operand type to integer. */ | |
14922 | et.type = NT_integer; | |
5287ad62 JB |
14923 | neon_mixed_length (et, et.size / 2); |
14924 | } | |
14925 | ||
14926 | static void | |
14927 | do_neon_mul_sat_scalar_long (void) | |
14928 | { | |
14929 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14930 | } | |
14931 | ||
14932 | static void | |
14933 | do_neon_vmull (void) | |
14934 | { | |
14935 | if (inst.operands[2].isscalar) | |
14936 | do_neon_mac_maybe_scalar_long (); | |
14937 | else | |
14938 | { | |
14939 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14940 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14941 | if (et.type == NT_poly) | |
88714cb8 | 14942 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14943 | else |
88714cb8 | 14944 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14945 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14946 | zero. Should be OK as-is. */ | |
14947 | neon_mixed_length (et, et.size); | |
14948 | } | |
14949 | } | |
14950 | ||
14951 | static void | |
14952 | do_neon_ext (void) | |
14953 | { | |
037e8744 | 14954 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14955 | struct neon_type_el et = neon_check_type (3, rs, |
14956 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14957 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14958 | |
14959 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14960 | _("shift out of range")); | |
5287ad62 JB |
14961 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14962 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14963 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14964 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14965 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14966 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14967 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14968 | inst.instruction |= imm << 8; |
5f4273c7 | 14969 | |
88714cb8 | 14970 | neon_dp_fixup (&inst); |
5287ad62 JB |
14971 | } |
14972 | ||
14973 | static void | |
14974 | do_neon_rev (void) | |
14975 | { | |
037e8744 | 14976 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14977 | struct neon_type_el et = neon_check_type (2, rs, |
14978 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14979 | unsigned op = (inst.instruction >> 7) & 3; | |
14980 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14981 | extract it here to check the elements to be reversed are smaller. | |
14982 | Otherwise we'd get a reserved instruction. */ | |
14983 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14984 | gas_assert (elsize != 0); |
5287ad62 JB |
14985 | constraint (et.size >= elsize, |
14986 | _("elements must be smaller than reversal region")); | |
037e8744 | 14987 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14988 | } |
14989 | ||
14990 | static void | |
14991 | do_neon_dup (void) | |
14992 | { | |
14993 | if (inst.operands[1].isscalar) | |
14994 | { | |
037e8744 | 14995 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14996 | struct neon_type_el et = neon_check_type (2, rs, |
14997 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14998 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14999 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 15000 | int logsize = neon_logbits (et.size); |
dcbf9037 | 15001 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
15002 | |
15003 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
15004 | return; | |
15005 | ||
88714cb8 | 15006 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15007 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15008 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15009 | inst.instruction |= LOW4 (dm); | |
15010 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 15011 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15012 | inst.instruction |= x << 17; |
15013 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 15014 | |
88714cb8 | 15015 | neon_dp_fixup (&inst); |
5287ad62 JB |
15016 | } |
15017 | else | |
15018 | { | |
037e8744 JB |
15019 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
15020 | struct neon_type_el et = neon_check_type (2, rs, | |
15021 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 15022 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 15023 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
15024 | switch (et.size) |
15025 | { | |
15026 | case 8: inst.instruction |= 0x400000; break; | |
15027 | case 16: inst.instruction |= 0x000020; break; | |
15028 | case 32: inst.instruction |= 0x000000; break; | |
15029 | default: break; | |
15030 | } | |
15031 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
15032 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
15033 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 15034 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
15035 | /* The encoding for this instruction is identical for the ARM and Thumb |
15036 | variants, except for the condition field. */ | |
037e8744 | 15037 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15038 | } |
15039 | } | |
15040 | ||
15041 | /* VMOV has particularly many variations. It can be one of: | |
15042 | 0. VMOV<c><q> <Qd>, <Qm> | |
15043 | 1. VMOV<c><q> <Dd>, <Dm> | |
15044 | (Register operations, which are VORR with Rm = Rn.) | |
15045 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
15046 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
15047 | (Immediate loads.) | |
15048 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
15049 | (ARM register to scalar.) | |
15050 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
15051 | (Two ARM registers to vector.) | |
15052 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
15053 | (Scalar to ARM register.) | |
15054 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
15055 | (Vector to two ARM registers.) | |
037e8744 JB |
15056 | 8. VMOV.F32 <Sd>, <Sm> |
15057 | 9. VMOV.F64 <Dd>, <Dm> | |
15058 | (VFP register moves.) | |
15059 | 10. VMOV.F32 <Sd>, #imm | |
15060 | 11. VMOV.F64 <Dd>, #imm | |
15061 | (VFP float immediate load.) | |
15062 | 12. VMOV <Rd>, <Sm> | |
15063 | (VFP single to ARM reg.) | |
15064 | 13. VMOV <Sd>, <Rm> | |
15065 | (ARM reg to VFP single.) | |
15066 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
15067 | (Two ARM regs to two VFP singles.) | |
15068 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
15069 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 15070 | |
037e8744 JB |
15071 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
15072 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 15073 | |
5287ad62 | 15074 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 15075 | |
b7fc2769 JB |
15076 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
15077 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 15078 | |
5287ad62 | 15079 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 15080 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
15081 | |
15082 | static void | |
15083 | do_neon_mov (void) | |
15084 | { | |
037e8744 JB |
15085 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
15086 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
15087 | NS_NULL); | |
15088 | struct neon_type_el et; | |
15089 | const char *ldconst = 0; | |
5287ad62 | 15090 | |
037e8744 | 15091 | switch (rs) |
5287ad62 | 15092 | { |
037e8744 JB |
15093 | case NS_DD: /* case 1/9. */ |
15094 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15095 | /* It is not an error here if no type is given. */ | |
15096 | inst.error = NULL; | |
15097 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 15098 | { |
037e8744 JB |
15099 | do_vfp_nsyn_opcode ("fcpyd"); |
15100 | break; | |
5287ad62 | 15101 | } |
037e8744 | 15102 | /* fall through. */ |
5287ad62 | 15103 | |
037e8744 JB |
15104 | case NS_QQ: /* case 0/1. */ |
15105 | { | |
15106 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15107 | return; | |
15108 | /* The architecture manual I have doesn't explicitly state which | |
15109 | value the U bit should have for register->register moves, but | |
15110 | the equivalent VORR instruction has U = 0, so do that. */ | |
15111 | inst.instruction = 0x0200110; | |
15112 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15113 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15114 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15115 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15116 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15117 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15118 | inst.instruction |= neon_quad (rs) << 6; | |
15119 | ||
88714cb8 | 15120 | neon_dp_fixup (&inst); |
037e8744 JB |
15121 | } |
15122 | break; | |
5f4273c7 | 15123 | |
037e8744 JB |
15124 | case NS_DI: /* case 3/11. */ |
15125 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15126 | inst.error = NULL; | |
15127 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 15128 | { |
037e8744 JB |
15129 | /* case 11 (fconstd). */ |
15130 | ldconst = "fconstd"; | |
15131 | goto encode_fconstd; | |
5287ad62 | 15132 | } |
037e8744 JB |
15133 | /* fall through. */ |
15134 | ||
15135 | case NS_QI: /* case 2/3. */ | |
15136 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15137 | return; | |
15138 | inst.instruction = 0x0800010; | |
15139 | neon_move_immediate (); | |
88714cb8 | 15140 | neon_dp_fixup (&inst); |
5287ad62 | 15141 | break; |
5f4273c7 | 15142 | |
037e8744 JB |
15143 | case NS_SR: /* case 4. */ |
15144 | { | |
15145 | unsigned bcdebits = 0; | |
91d6fa6a | 15146 | int logsize; |
037e8744 JB |
15147 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
15148 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
15149 | ||
91d6fa6a NC |
15150 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
15151 | logsize = neon_logbits (et.size); | |
15152 | ||
037e8744 JB |
15153 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
15154 | _(BAD_FPU)); | |
15155 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15156 | && et.size != 32, _(BAD_FPU)); | |
15157 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15158 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15159 | ||
15160 | switch (et.size) | |
15161 | { | |
15162 | case 8: bcdebits = 0x8; break; | |
15163 | case 16: bcdebits = 0x1; break; | |
15164 | case 32: bcdebits = 0x0; break; | |
15165 | default: ; | |
15166 | } | |
15167 | ||
15168 | bcdebits |= x << logsize; | |
15169 | ||
15170 | inst.instruction = 0xe000b10; | |
15171 | do_vfp_cond_or_thumb (); | |
15172 | inst.instruction |= LOW4 (dn) << 16; | |
15173 | inst.instruction |= HI1 (dn) << 7; | |
15174 | inst.instruction |= inst.operands[1].reg << 12; | |
15175 | inst.instruction |= (bcdebits & 3) << 5; | |
15176 | inst.instruction |= (bcdebits >> 2) << 21; | |
15177 | } | |
15178 | break; | |
5f4273c7 | 15179 | |
037e8744 | 15180 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 15181 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 15182 | _(BAD_FPU)); |
b7fc2769 | 15183 | |
037e8744 JB |
15184 | inst.instruction = 0xc400b10; |
15185 | do_vfp_cond_or_thumb (); | |
15186 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
15187 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
15188 | inst.instruction |= inst.operands[1].reg << 12; | |
15189 | inst.instruction |= inst.operands[2].reg << 16; | |
15190 | break; | |
5f4273c7 | 15191 | |
037e8744 JB |
15192 | case NS_RS: /* case 6. */ |
15193 | { | |
91d6fa6a | 15194 | unsigned logsize; |
037e8744 JB |
15195 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
15196 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
15197 | unsigned abcdebits = 0; | |
15198 | ||
91d6fa6a NC |
15199 | et = neon_check_type (2, NS_NULL, |
15200 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
15201 | logsize = neon_logbits (et.size); | |
15202 | ||
037e8744 JB |
15203 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
15204 | _(BAD_FPU)); | |
15205 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15206 | && et.size != 32, _(BAD_FPU)); | |
15207 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15208 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15209 | ||
15210 | switch (et.size) | |
15211 | { | |
15212 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
15213 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
15214 | case 32: abcdebits = 0x00; break; | |
15215 | default: ; | |
15216 | } | |
15217 | ||
15218 | abcdebits |= x << logsize; | |
15219 | inst.instruction = 0xe100b10; | |
15220 | do_vfp_cond_or_thumb (); | |
15221 | inst.instruction |= LOW4 (dn) << 16; | |
15222 | inst.instruction |= HI1 (dn) << 7; | |
15223 | inst.instruction |= inst.operands[0].reg << 12; | |
15224 | inst.instruction |= (abcdebits & 3) << 5; | |
15225 | inst.instruction |= (abcdebits >> 2) << 21; | |
15226 | } | |
15227 | break; | |
5f4273c7 | 15228 | |
037e8744 JB |
15229 | case NS_RRD: /* case 7 (fmrrd). */ |
15230 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
15231 | _(BAD_FPU)); | |
15232 | ||
15233 | inst.instruction = 0xc500b10; | |
15234 | do_vfp_cond_or_thumb (); | |
15235 | inst.instruction |= inst.operands[0].reg << 12; | |
15236 | inst.instruction |= inst.operands[1].reg << 16; | |
15237 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15238 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15239 | break; | |
5f4273c7 | 15240 | |
037e8744 JB |
15241 | case NS_FF: /* case 8 (fcpys). */ |
15242 | do_vfp_nsyn_opcode ("fcpys"); | |
15243 | break; | |
5f4273c7 | 15244 | |
037e8744 JB |
15245 | case NS_FI: /* case 10 (fconsts). */ |
15246 | ldconst = "fconsts"; | |
15247 | encode_fconstd: | |
15248 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 15249 | { |
037e8744 JB |
15250 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
15251 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
15252 | } |
15253 | else | |
037e8744 JB |
15254 | first_error (_("immediate out of range")); |
15255 | break; | |
5f4273c7 | 15256 | |
037e8744 JB |
15257 | case NS_RF: /* case 12 (fmrs). */ |
15258 | do_vfp_nsyn_opcode ("fmrs"); | |
15259 | break; | |
5f4273c7 | 15260 | |
037e8744 JB |
15261 | case NS_FR: /* case 13 (fmsr). */ |
15262 | do_vfp_nsyn_opcode ("fmsr"); | |
15263 | break; | |
5f4273c7 | 15264 | |
037e8744 JB |
15265 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
15266 | (one of which is a list), but we have parsed four. Do some fiddling to | |
15267 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
15268 | expect. */ | |
15269 | case NS_RRFF: /* case 14 (fmrrs). */ | |
15270 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
15271 | _("VFP registers must be adjacent")); | |
15272 | inst.operands[2].imm = 2; | |
15273 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15274 | do_vfp_nsyn_opcode ("fmrrs"); | |
15275 | break; | |
5f4273c7 | 15276 | |
037e8744 JB |
15277 | case NS_FFRR: /* case 15 (fmsrr). */ |
15278 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
15279 | _("VFP registers must be adjacent")); | |
15280 | inst.operands[1] = inst.operands[2]; | |
15281 | inst.operands[2] = inst.operands[3]; | |
15282 | inst.operands[0].imm = 2; | |
15283 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15284 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 15285 | break; |
5f4273c7 | 15286 | |
5287ad62 JB |
15287 | default: |
15288 | abort (); | |
15289 | } | |
15290 | } | |
15291 | ||
15292 | static void | |
15293 | do_neon_rshift_round_imm (void) | |
15294 | { | |
037e8744 | 15295 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15296 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
15297 | int imm = inst.operands[2].imm; | |
15298 | ||
15299 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
15300 | if (imm == 0) | |
15301 | { | |
15302 | inst.operands[2].present = 0; | |
15303 | do_neon_mov (); | |
15304 | return; | |
15305 | } | |
15306 | ||
15307 | constraint (imm < 1 || (unsigned)imm > et.size, | |
15308 | _("immediate out of range for shift")); | |
037e8744 | 15309 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
15310 | et.size - imm); |
15311 | } | |
15312 | ||
15313 | static void | |
15314 | do_neon_movl (void) | |
15315 | { | |
15316 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
15317 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15318 | unsigned sizebits = et.size >> 3; | |
15319 | inst.instruction |= sizebits << 19; | |
15320 | neon_two_same (0, et.type == NT_unsigned, -1); | |
15321 | } | |
15322 | ||
15323 | static void | |
15324 | do_neon_trn (void) | |
15325 | { | |
037e8744 | 15326 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15327 | struct neon_type_el et = neon_check_type (2, rs, |
15328 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 15329 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15330 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15331 | } |
15332 | ||
15333 | static void | |
15334 | do_neon_zip_uzp (void) | |
15335 | { | |
037e8744 | 15336 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15337 | struct neon_type_el et = neon_check_type (2, rs, |
15338 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15339 | if (rs == NS_DD && et.size == 32) | |
15340 | { | |
15341 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
15342 | inst.instruction = N_MNEM_vtrn; | |
15343 | do_neon_trn (); | |
15344 | return; | |
15345 | } | |
037e8744 | 15346 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15347 | } |
15348 | ||
15349 | static void | |
15350 | do_neon_sat_abs_neg (void) | |
15351 | { | |
037e8744 | 15352 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15353 | struct neon_type_el et = neon_check_type (2, rs, |
15354 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15355 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15356 | } |
15357 | ||
15358 | static void | |
15359 | do_neon_pair_long (void) | |
15360 | { | |
037e8744 | 15361 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15362 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
15363 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
15364 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 15365 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15366 | } |
15367 | ||
15368 | static void | |
15369 | do_neon_recip_est (void) | |
15370 | { | |
037e8744 | 15371 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15372 | struct neon_type_el et = neon_check_type (2, rs, |
15373 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
15374 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 15375 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15376 | } |
15377 | ||
15378 | static void | |
15379 | do_neon_cls (void) | |
15380 | { | |
037e8744 | 15381 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15382 | struct neon_type_el et = neon_check_type (2, rs, |
15383 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15384 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15385 | } |
15386 | ||
15387 | static void | |
15388 | do_neon_clz (void) | |
15389 | { | |
037e8744 | 15390 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15391 | struct neon_type_el et = neon_check_type (2, rs, |
15392 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 15393 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15394 | } |
15395 | ||
15396 | static void | |
15397 | do_neon_cnt (void) | |
15398 | { | |
037e8744 | 15399 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15400 | struct neon_type_el et = neon_check_type (2, rs, |
15401 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 15402 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15403 | } |
15404 | ||
15405 | static void | |
15406 | do_neon_swp (void) | |
15407 | { | |
037e8744 JB |
15408 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
15409 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
15410 | } |
15411 | ||
15412 | static void | |
15413 | do_neon_tbl_tbx (void) | |
15414 | { | |
15415 | unsigned listlenbits; | |
dcbf9037 | 15416 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 15417 | |
5287ad62 JB |
15418 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
15419 | { | |
dcbf9037 | 15420 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
15421 | return; |
15422 | } | |
5f4273c7 | 15423 | |
5287ad62 JB |
15424 | listlenbits = inst.operands[1].imm - 1; |
15425 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15426 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15427 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15428 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15429 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15430 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15431 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 15432 | |
88714cb8 | 15433 | neon_dp_fixup (&inst); |
5287ad62 JB |
15434 | } |
15435 | ||
15436 | static void | |
15437 | do_neon_ldm_stm (void) | |
15438 | { | |
15439 | /* P, U and L bits are part of bitmask. */ | |
15440 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
15441 | unsigned offsetbits = inst.operands[1].imm * 2; | |
15442 | ||
037e8744 JB |
15443 | if (inst.operands[1].issingle) |
15444 | { | |
15445 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
15446 | return; | |
15447 | } | |
15448 | ||
5287ad62 JB |
15449 | constraint (is_dbmode && !inst.operands[0].writeback, |
15450 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
15451 | ||
15452 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
15453 | _("register list must contain at least 1 and at most 16 " | |
15454 | "registers")); | |
15455 | ||
15456 | inst.instruction |= inst.operands[0].reg << 16; | |
15457 | inst.instruction |= inst.operands[0].writeback << 21; | |
15458 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
15459 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
15460 | ||
15461 | inst.instruction |= offsetbits; | |
5f4273c7 | 15462 | |
037e8744 | 15463 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15464 | } |
15465 | ||
15466 | static void | |
15467 | do_neon_ldr_str (void) | |
15468 | { | |
5287ad62 | 15469 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 15470 | |
6844b2c2 MGD |
15471 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
15472 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 15473 | if (!is_ldr |
6844b2c2 MGD |
15474 | && inst.operands[1].reg == REG_PC |
15475 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
15476 | { | |
15477 | if (!thumb_mode && warn_on_deprecated) | |
15478 | as_warn (_("Use of PC here is deprecated")); | |
15479 | else | |
15480 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
15481 | } | |
15482 | ||
037e8744 JB |
15483 | if (inst.operands[0].issingle) |
15484 | { | |
cd2f129f JB |
15485 | if (is_ldr) |
15486 | do_vfp_nsyn_opcode ("flds"); | |
15487 | else | |
15488 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
15489 | } |
15490 | else | |
5287ad62 | 15491 | { |
cd2f129f JB |
15492 | if (is_ldr) |
15493 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 15494 | else |
cd2f129f | 15495 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 15496 | } |
5287ad62 JB |
15497 | } |
15498 | ||
15499 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
15500 | instructions. */ | |
15501 | ||
15502 | static void | |
15503 | do_neon_ld_st_interleave (void) | |
15504 | { | |
037e8744 | 15505 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
15506 | N_8 | N_16 | N_32 | N_64); |
15507 | unsigned alignbits = 0; | |
15508 | unsigned idx; | |
15509 | /* The bits in this table go: | |
15510 | 0: register stride of one (0) or two (1) | |
15511 | 1,2: register list length, minus one (1, 2, 3, 4). | |
15512 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
15513 | We use -1 for invalid entries. */ | |
15514 | const int typetable[] = | |
15515 | { | |
15516 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
15517 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
15518 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
15519 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
15520 | }; | |
15521 | int typebits; | |
15522 | ||
dcbf9037 JB |
15523 | if (et.type == NT_invtype) |
15524 | return; | |
15525 | ||
5287ad62 JB |
15526 | if (inst.operands[1].immisalign) |
15527 | switch (inst.operands[1].imm >> 8) | |
15528 | { | |
15529 | case 64: alignbits = 1; break; | |
15530 | case 128: | |
e23c0ad8 JZ |
15531 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
15532 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
15533 | goto bad_alignment; |
15534 | alignbits = 2; | |
15535 | break; | |
15536 | case 256: | |
e23c0ad8 | 15537 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
15538 | goto bad_alignment; |
15539 | alignbits = 3; | |
15540 | break; | |
15541 | default: | |
15542 | bad_alignment: | |
dcbf9037 | 15543 | first_error (_("bad alignment")); |
5287ad62 JB |
15544 | return; |
15545 | } | |
15546 | ||
15547 | inst.instruction |= alignbits << 4; | |
15548 | inst.instruction |= neon_logbits (et.size) << 6; | |
15549 | ||
15550 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
15551 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
15552 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
15553 | up the right value for "type" in a table based on this value and the given | |
15554 | list style, then stick it back. */ | |
15555 | idx = ((inst.operands[0].imm >> 4) & 7) | |
15556 | | (((inst.instruction >> 8) & 3) << 3); | |
15557 | ||
15558 | typebits = typetable[idx]; | |
5f4273c7 | 15559 | |
5287ad62 JB |
15560 | constraint (typebits == -1, _("bad list type for instruction")); |
15561 | ||
15562 | inst.instruction &= ~0xf00; | |
15563 | inst.instruction |= typebits << 8; | |
15564 | } | |
15565 | ||
15566 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
15567 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
15568 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
15569 | values, terminated with -1. */ | |
15570 | ||
15571 | static int | |
15572 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
15573 | { | |
15574 | va_list ap; | |
15575 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 15576 | |
5287ad62 JB |
15577 | if (!inst.operands[1].immisalign) |
15578 | { | |
15579 | *do_align = 0; | |
15580 | return SUCCESS; | |
15581 | } | |
5f4273c7 | 15582 | |
5287ad62 JB |
15583 | va_start (ap, do_align); |
15584 | ||
15585 | do | |
15586 | { | |
15587 | thissize = va_arg (ap, int); | |
15588 | if (thissize == -1) | |
15589 | break; | |
15590 | thisalign = va_arg (ap, int); | |
15591 | ||
15592 | if (size == thissize && align == thisalign) | |
15593 | result = SUCCESS; | |
15594 | } | |
15595 | while (result != SUCCESS); | |
15596 | ||
15597 | va_end (ap); | |
15598 | ||
15599 | if (result == SUCCESS) | |
15600 | *do_align = 1; | |
15601 | else | |
dcbf9037 | 15602 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 15603 | |
5287ad62 JB |
15604 | return result; |
15605 | } | |
15606 | ||
15607 | static void | |
15608 | do_neon_ld_st_lane (void) | |
15609 | { | |
037e8744 | 15610 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15611 | int align_good, do_align = 0; |
15612 | int logsize = neon_logbits (et.size); | |
15613 | int align = inst.operands[1].imm >> 8; | |
15614 | int n = (inst.instruction >> 8) & 3; | |
15615 | int max_el = 64 / et.size; | |
5f4273c7 | 15616 | |
dcbf9037 JB |
15617 | if (et.type == NT_invtype) |
15618 | return; | |
5f4273c7 | 15619 | |
5287ad62 JB |
15620 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
15621 | _("bad list length")); | |
15622 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
15623 | _("scalar index out of range")); | |
15624 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
15625 | && et.size == 8, | |
15626 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 15627 | |
5287ad62 JB |
15628 | switch (n) |
15629 | { | |
15630 | case 0: /* VLD1 / VST1. */ | |
15631 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
15632 | 32, 32, -1); | |
15633 | if (align_good == FAIL) | |
15634 | return; | |
15635 | if (do_align) | |
15636 | { | |
15637 | unsigned alignbits = 0; | |
15638 | switch (et.size) | |
15639 | { | |
15640 | case 16: alignbits = 0x1; break; | |
15641 | case 32: alignbits = 0x3; break; | |
15642 | default: ; | |
15643 | } | |
15644 | inst.instruction |= alignbits << 4; | |
15645 | } | |
15646 | break; | |
15647 | ||
15648 | case 1: /* VLD2 / VST2. */ | |
15649 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
15650 | 32, 64, -1); | |
15651 | if (align_good == FAIL) | |
15652 | return; | |
15653 | if (do_align) | |
15654 | inst.instruction |= 1 << 4; | |
15655 | break; | |
15656 | ||
15657 | case 2: /* VLD3 / VST3. */ | |
15658 | constraint (inst.operands[1].immisalign, | |
15659 | _("can't use alignment with this instruction")); | |
15660 | break; | |
15661 | ||
15662 | case 3: /* VLD4 / VST4. */ | |
15663 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15664 | 16, 64, 32, 64, 32, 128, -1); | |
15665 | if (align_good == FAIL) | |
15666 | return; | |
15667 | if (do_align) | |
15668 | { | |
15669 | unsigned alignbits = 0; | |
15670 | switch (et.size) | |
15671 | { | |
15672 | case 8: alignbits = 0x1; break; | |
15673 | case 16: alignbits = 0x1; break; | |
15674 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
15675 | default: ; | |
15676 | } | |
15677 | inst.instruction |= alignbits << 4; | |
15678 | } | |
15679 | break; | |
15680 | ||
15681 | default: ; | |
15682 | } | |
15683 | ||
15684 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
15685 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15686 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 15687 | |
5287ad62 JB |
15688 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
15689 | inst.instruction |= logsize << 10; | |
15690 | } | |
15691 | ||
15692 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
15693 | ||
15694 | static void | |
15695 | do_neon_ld_dup (void) | |
15696 | { | |
037e8744 | 15697 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15698 | int align_good, do_align = 0; |
15699 | ||
dcbf9037 JB |
15700 | if (et.type == NT_invtype) |
15701 | return; | |
15702 | ||
5287ad62 JB |
15703 | switch ((inst.instruction >> 8) & 3) |
15704 | { | |
15705 | case 0: /* VLD1. */ | |
9c2799c2 | 15706 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
15707 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
15708 | &do_align, 16, 16, 32, 32, -1); | |
15709 | if (align_good == FAIL) | |
15710 | return; | |
15711 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
15712 | { | |
15713 | case 1: break; | |
15714 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 15715 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
15716 | } |
15717 | inst.instruction |= neon_logbits (et.size) << 6; | |
15718 | break; | |
15719 | ||
15720 | case 1: /* VLD2. */ | |
15721 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
15722 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
15723 | if (align_good == FAIL) | |
15724 | return; | |
15725 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
15726 | _("bad list length")); | |
15727 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15728 | inst.instruction |= 1 << 5; | |
15729 | inst.instruction |= neon_logbits (et.size) << 6; | |
15730 | break; | |
15731 | ||
15732 | case 2: /* VLD3. */ | |
15733 | constraint (inst.operands[1].immisalign, | |
15734 | _("can't use alignment with this instruction")); | |
15735 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
15736 | _("bad list length")); | |
15737 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15738 | inst.instruction |= 1 << 5; | |
15739 | inst.instruction |= neon_logbits (et.size) << 6; | |
15740 | break; | |
15741 | ||
15742 | case 3: /* VLD4. */ | |
15743 | { | |
15744 | int align = inst.operands[1].imm >> 8; | |
15745 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15746 | 16, 64, 32, 64, 32, 128, -1); | |
15747 | if (align_good == FAIL) | |
15748 | return; | |
15749 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
15750 | _("bad list length")); | |
15751 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15752 | inst.instruction |= 1 << 5; | |
15753 | if (et.size == 32 && align == 128) | |
15754 | inst.instruction |= 0x3 << 6; | |
15755 | else | |
15756 | inst.instruction |= neon_logbits (et.size) << 6; | |
15757 | } | |
15758 | break; | |
15759 | ||
15760 | default: ; | |
15761 | } | |
15762 | ||
15763 | inst.instruction |= do_align << 4; | |
15764 | } | |
15765 | ||
15766 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
15767 | apart from bits [11:4]. */ | |
15768 | ||
15769 | static void | |
15770 | do_neon_ldx_stx (void) | |
15771 | { | |
b1a769ed DG |
15772 | if (inst.operands[1].isreg) |
15773 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
15774 | ||
5287ad62 JB |
15775 | switch (NEON_LANE (inst.operands[0].imm)) |
15776 | { | |
15777 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 15778 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
15779 | do_neon_ld_st_interleave (); |
15780 | break; | |
5f4273c7 | 15781 | |
5287ad62 | 15782 | case NEON_ALL_LANES: |
88714cb8 | 15783 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
15784 | do_neon_ld_dup (); |
15785 | break; | |
5f4273c7 | 15786 | |
5287ad62 | 15787 | default: |
88714cb8 | 15788 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
15789 | do_neon_ld_st_lane (); |
15790 | } | |
15791 | ||
15792 | /* L bit comes from bit mask. */ | |
15793 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15794 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15795 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 15796 | |
5287ad62 JB |
15797 | if (inst.operands[1].postind) |
15798 | { | |
15799 | int postreg = inst.operands[1].imm & 0xf; | |
15800 | constraint (!inst.operands[1].immisreg, | |
15801 | _("post-index must be a register")); | |
15802 | constraint (postreg == 0xd || postreg == 0xf, | |
15803 | _("bad register for post-index")); | |
15804 | inst.instruction |= postreg; | |
15805 | } | |
15806 | else if (inst.operands[1].writeback) | |
15807 | { | |
15808 | inst.instruction |= 0xd; | |
15809 | } | |
15810 | else | |
5f4273c7 NC |
15811 | inst.instruction |= 0xf; |
15812 | ||
5287ad62 JB |
15813 | if (thumb_mode) |
15814 | inst.instruction |= 0xf9000000; | |
15815 | else | |
15816 | inst.instruction |= 0xf4000000; | |
15817 | } | |
5287ad62 JB |
15818 | \f |
15819 | /* Overall per-instruction processing. */ | |
15820 | ||
15821 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15822 | This is so that we can handle symbols that are an arbitrary distance from | |
15823 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15824 | which returns part of an address in a form which will be valid for | |
15825 | a data instruction. We do this by pushing the expression into a symbol | |
15826 | in the expr_section, and creating a fix for that. */ | |
15827 | ||
15828 | static void | |
15829 | fix_new_arm (fragS * frag, | |
15830 | int where, | |
15831 | short int size, | |
15832 | expressionS * exp, | |
15833 | int pc_rel, | |
15834 | int reloc) | |
15835 | { | |
15836 | fixS * new_fix; | |
15837 | ||
15838 | switch (exp->X_op) | |
15839 | { | |
15840 | case O_constant: | |
6e7ce2cd PB |
15841 | if (pc_rel) |
15842 | { | |
15843 | /* Create an absolute valued symbol, so we have something to | |
15844 | refer to in the object file. Unfortunately for us, gas's | |
15845 | generic expression parsing will already have folded out | |
15846 | any use of .set foo/.type foo %function that may have | |
15847 | been used to set type information of the target location, | |
15848 | that's being specified symbolically. We have to presume | |
15849 | the user knows what they are doing. */ | |
15850 | char name[16 + 8]; | |
15851 | symbolS *symbol; | |
15852 | ||
15853 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
15854 | ||
15855 | symbol = symbol_find_or_make (name); | |
15856 | S_SET_SEGMENT (symbol, absolute_section); | |
15857 | symbol_set_frag (symbol, &zero_address_frag); | |
15858 | S_SET_VALUE (symbol, exp->X_add_number); | |
15859 | exp->X_op = O_symbol; | |
15860 | exp->X_add_symbol = symbol; | |
15861 | exp->X_add_number = 0; | |
15862 | } | |
15863 | /* FALLTHROUGH */ | |
5287ad62 JB |
15864 | case O_symbol: |
15865 | case O_add: | |
15866 | case O_subtract: | |
21d799b5 NC |
15867 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15868 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15869 | break; |
15870 | ||
15871 | default: | |
21d799b5 NC |
15872 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15873 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15874 | break; |
15875 | } | |
15876 | ||
15877 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15878 | instruction. */ | |
15879 | new_fix->tc_fix_data = thumb_mode; | |
15880 | } | |
15881 | ||
15882 | /* Create a frg for an instruction requiring relaxation. */ | |
15883 | static void | |
15884 | output_relax_insn (void) | |
15885 | { | |
15886 | char * to; | |
15887 | symbolS *sym; | |
0110f2b8 PB |
15888 | int offset; |
15889 | ||
6e1cb1a6 PB |
15890 | /* The size of the instruction is unknown, so tie the debug info to the |
15891 | start of the instruction. */ | |
15892 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15893 | |
0110f2b8 PB |
15894 | switch (inst.reloc.exp.X_op) |
15895 | { | |
15896 | case O_symbol: | |
15897 | sym = inst.reloc.exp.X_add_symbol; | |
15898 | offset = inst.reloc.exp.X_add_number; | |
15899 | break; | |
15900 | case O_constant: | |
15901 | sym = NULL; | |
15902 | offset = inst.reloc.exp.X_add_number; | |
15903 | break; | |
15904 | default: | |
15905 | sym = make_expr_symbol (&inst.reloc.exp); | |
15906 | offset = 0; | |
15907 | break; | |
15908 | } | |
15909 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15910 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15911 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15912 | } |
15913 | ||
15914 | /* Write a 32-bit thumb instruction to buf. */ | |
15915 | static void | |
15916 | put_thumb32_insn (char * buf, unsigned long insn) | |
15917 | { | |
15918 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15919 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15920 | } | |
15921 | ||
b99bd4ef | 15922 | static void |
c19d1205 | 15923 | output_inst (const char * str) |
b99bd4ef | 15924 | { |
c19d1205 | 15925 | char * to = NULL; |
b99bd4ef | 15926 | |
c19d1205 | 15927 | if (inst.error) |
b99bd4ef | 15928 | { |
c19d1205 | 15929 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15930 | return; |
15931 | } | |
5f4273c7 NC |
15932 | if (inst.relax) |
15933 | { | |
15934 | output_relax_insn (); | |
0110f2b8 | 15935 | return; |
5f4273c7 | 15936 | } |
c19d1205 ZW |
15937 | if (inst.size == 0) |
15938 | return; | |
b99bd4ef | 15939 | |
c19d1205 | 15940 | to = frag_more (inst.size); |
8dc2430f NC |
15941 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15942 | what type of NOP padding to use, if necessary. We override any previous | |
15943 | setting so that if the mode has changed then the NOPS that we use will | |
15944 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15945 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15946 | |
15947 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15948 | { |
9c2799c2 | 15949 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15950 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15951 | } |
c19d1205 | 15952 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15953 | { |
9c2799c2 | 15954 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15955 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15956 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15957 | } |
c19d1205 ZW |
15958 | else |
15959 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15960 | |
c19d1205 ZW |
15961 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15962 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15963 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15964 | inst.reloc.type); | |
b99bd4ef | 15965 | |
c19d1205 | 15966 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15967 | } |
b99bd4ef | 15968 | |
e07e6e58 NC |
15969 | static char * |
15970 | output_it_inst (int cond, int mask, char * to) | |
15971 | { | |
15972 | unsigned long instruction = 0xbf00; | |
15973 | ||
15974 | mask &= 0xf; | |
15975 | instruction |= mask; | |
15976 | instruction |= cond << 4; | |
15977 | ||
15978 | if (to == NULL) | |
15979 | { | |
15980 | to = frag_more (2); | |
15981 | #ifdef OBJ_ELF | |
15982 | dwarf2_emit_insn (2); | |
15983 | #endif | |
15984 | } | |
15985 | ||
15986 | md_number_to_chars (to, instruction, 2); | |
15987 | ||
15988 | return to; | |
15989 | } | |
15990 | ||
c19d1205 ZW |
15991 | /* Tag values used in struct asm_opcode's tag field. */ |
15992 | enum opcode_tag | |
15993 | { | |
15994 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15995 | The ARM condition field is still 0xE. */ | |
15996 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15997 | and carries 0xF in its ARM condition field. */ | |
15998 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15999 | OT_csuffixF, /* Some forms of the instruction take a conditional |
16000 | suffix, others place 0xF where the condition field | |
16001 | would be. */ | |
c19d1205 ZW |
16002 | OT_cinfix3, /* Instruction takes a conditional infix, |
16003 | beginning at character index 3. (In | |
16004 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
16005 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
16006 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
16007 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
16008 | character index 3, even in unified mode. Used for | |
16009 | legacy instructions where suffix and infix forms | |
16010 | may be ambiguous. */ | |
c19d1205 | 16011 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 16012 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
16013 | OT_odd_infix_unc, /* This is the unconditional variant of an |
16014 | instruction that takes a conditional infix | |
16015 | at an unusual position. In unified mode, | |
16016 | this variant will accept a suffix. */ | |
16017 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
16018 | are the conditional variants of instructions that | |
16019 | take conditional infixes in unusual positions. | |
16020 | The infix appears at character index | |
16021 | (tag - OT_odd_infix_0). These are not accepted | |
16022 | in unified mode. */ | |
16023 | }; | |
b99bd4ef | 16024 | |
c19d1205 ZW |
16025 | /* Subroutine of md_assemble, responsible for looking up the primary |
16026 | opcode from the mnemonic the user wrote. STR points to the | |
16027 | beginning of the mnemonic. | |
16028 | ||
16029 | This is not simply a hash table lookup, because of conditional | |
16030 | variants. Most instructions have conditional variants, which are | |
16031 | expressed with a _conditional affix_ to the mnemonic. If we were | |
16032 | to encode each conditional variant as a literal string in the opcode | |
16033 | table, it would have approximately 20,000 entries. | |
16034 | ||
16035 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
16036 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
16037 | instructions take the affix as an infix, notably the s-variants of | |
16038 | the arithmetic instructions. Of those instructions, all but six | |
16039 | have the infix appear after the third character of the mnemonic. | |
16040 | ||
16041 | Accordingly, the algorithm for looking up primary opcodes given | |
16042 | an identifier is: | |
16043 | ||
16044 | 1. Look up the identifier in the opcode table. | |
16045 | If we find a match, go to step U. | |
16046 | ||
16047 | 2. Look up the last two characters of the identifier in the | |
16048 | conditions table. If we find a match, look up the first N-2 | |
16049 | characters of the identifier in the opcode table. If we | |
16050 | find a match, go to step CE. | |
16051 | ||
16052 | 3. Look up the fourth and fifth characters of the identifier in | |
16053 | the conditions table. If we find a match, extract those | |
16054 | characters from the identifier, and look up the remaining | |
16055 | characters in the opcode table. If we find a match, go | |
16056 | to step CM. | |
16057 | ||
16058 | 4. Fail. | |
16059 | ||
16060 | U. Examine the tag field of the opcode structure, in case this is | |
16061 | one of the six instructions with its conditional infix in an | |
16062 | unusual place. If it is, the tag tells us where to find the | |
16063 | infix; look it up in the conditions table and set inst.cond | |
16064 | accordingly. Otherwise, this is an unconditional instruction. | |
16065 | Again set inst.cond accordingly. Return the opcode structure. | |
16066 | ||
16067 | CE. Examine the tag field to make sure this is an instruction that | |
16068 | should receive a conditional suffix. If it is not, fail. | |
16069 | Otherwise, set inst.cond from the suffix we already looked up, | |
16070 | and return the opcode structure. | |
16071 | ||
16072 | CM. Examine the tag field to make sure this is an instruction that | |
16073 | should receive a conditional infix after the third character. | |
16074 | If it is not, fail. Otherwise, undo the edits to the current | |
16075 | line of input and proceed as for case CE. */ | |
16076 | ||
16077 | static const struct asm_opcode * | |
16078 | opcode_lookup (char **str) | |
16079 | { | |
16080 | char *end, *base; | |
16081 | char *affix; | |
16082 | const struct asm_opcode *opcode; | |
16083 | const struct asm_cond *cond; | |
e3cb604e | 16084 | char save[2]; |
c19d1205 ZW |
16085 | |
16086 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 16087 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 16088 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 16089 | if (*end == ' ' || *end == '.') |
c19d1205 | 16090 | break; |
b99bd4ef | 16091 | |
c19d1205 | 16092 | if (end == base) |
c921be7d | 16093 | return NULL; |
b99bd4ef | 16094 | |
5287ad62 | 16095 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 16096 | if (end[0] == '.') |
b99bd4ef | 16097 | { |
5287ad62 | 16098 | int offset = 2; |
5f4273c7 | 16099 | |
267d2029 JB |
16100 | /* The .w and .n suffixes are only valid if the unified syntax is in |
16101 | use. */ | |
16102 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 16103 | inst.size_req = 4; |
267d2029 | 16104 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
16105 | inst.size_req = 2; |
16106 | else | |
5287ad62 JB |
16107 | offset = 0; |
16108 | ||
16109 | inst.vectype.elems = 0; | |
16110 | ||
16111 | *str = end + offset; | |
b99bd4ef | 16112 | |
5f4273c7 | 16113 | if (end[offset] == '.') |
5287ad62 | 16114 | { |
267d2029 JB |
16115 | /* See if we have a Neon type suffix (possible in either unified or |
16116 | non-unified ARM syntax mode). */ | |
dcbf9037 | 16117 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 16118 | return NULL; |
5287ad62 JB |
16119 | } |
16120 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 16121 | return NULL; |
b99bd4ef | 16122 | } |
c19d1205 ZW |
16123 | else |
16124 | *str = end; | |
b99bd4ef | 16125 | |
c19d1205 | 16126 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
16127 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
16128 | end - base); | |
c19d1205 | 16129 | if (opcode) |
b99bd4ef | 16130 | { |
c19d1205 ZW |
16131 | /* step U */ |
16132 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 16133 | { |
c19d1205 ZW |
16134 | inst.cond = COND_ALWAYS; |
16135 | return opcode; | |
b99bd4ef | 16136 | } |
b99bd4ef | 16137 | |
278df34e | 16138 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
16139 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
16140 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 16141 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 16142 | gas_assert (cond); |
b99bd4ef | 16143 | |
c19d1205 ZW |
16144 | inst.cond = cond->value; |
16145 | return opcode; | |
16146 | } | |
b99bd4ef | 16147 | |
c19d1205 ZW |
16148 | /* Cannot have a conditional suffix on a mnemonic of less than two |
16149 | characters. */ | |
16150 | if (end - base < 3) | |
c921be7d | 16151 | return NULL; |
b99bd4ef | 16152 | |
c19d1205 ZW |
16153 | /* Look for suffixed mnemonic. */ |
16154 | affix = end - 2; | |
21d799b5 NC |
16155 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
16156 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
16157 | affix - base); | |
c19d1205 ZW |
16158 | if (opcode && cond) |
16159 | { | |
16160 | /* step CE */ | |
16161 | switch (opcode->tag) | |
16162 | { | |
e3cb604e PB |
16163 | case OT_cinfix3_legacy: |
16164 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
16165 | break; | |
16166 | ||
c19d1205 | 16167 | case OT_cinfix3: |
088fa78e | 16168 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
16169 | case OT_odd_infix_unc: |
16170 | if (!unified_syntax) | |
e3cb604e | 16171 | return 0; |
c19d1205 ZW |
16172 | /* else fall through */ |
16173 | ||
16174 | case OT_csuffix: | |
037e8744 | 16175 | case OT_csuffixF: |
c19d1205 ZW |
16176 | case OT_csuf_or_in3: |
16177 | inst.cond = cond->value; | |
16178 | return opcode; | |
16179 | ||
16180 | case OT_unconditional: | |
16181 | case OT_unconditionalF: | |
dfa9f0d5 | 16182 | if (thumb_mode) |
c921be7d | 16183 | inst.cond = cond->value; |
dfa9f0d5 PB |
16184 | else |
16185 | { | |
c921be7d | 16186 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
16187 | inst.error = BAD_COND; |
16188 | inst.cond = COND_ALWAYS; | |
16189 | } | |
c19d1205 | 16190 | return opcode; |
b99bd4ef | 16191 | |
c19d1205 | 16192 | default: |
c921be7d | 16193 | return NULL; |
c19d1205 ZW |
16194 | } |
16195 | } | |
b99bd4ef | 16196 | |
c19d1205 ZW |
16197 | /* Cannot have a usual-position infix on a mnemonic of less than |
16198 | six characters (five would be a suffix). */ | |
16199 | if (end - base < 6) | |
c921be7d | 16200 | return NULL; |
b99bd4ef | 16201 | |
c19d1205 ZW |
16202 | /* Look for infixed mnemonic in the usual position. */ |
16203 | affix = base + 3; | |
21d799b5 | 16204 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 16205 | if (!cond) |
c921be7d | 16206 | return NULL; |
e3cb604e PB |
16207 | |
16208 | memcpy (save, affix, 2); | |
16209 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
16210 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
16211 | (end - base) - 2); | |
e3cb604e PB |
16212 | memmove (affix + 2, affix, (end - affix) - 2); |
16213 | memcpy (affix, save, 2); | |
16214 | ||
088fa78e KH |
16215 | if (opcode |
16216 | && (opcode->tag == OT_cinfix3 | |
16217 | || opcode->tag == OT_cinfix3_deprecated | |
16218 | || opcode->tag == OT_csuf_or_in3 | |
16219 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 16220 | { |
c921be7d | 16221 | /* Step CM. */ |
278df34e | 16222 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
16223 | && (opcode->tag == OT_cinfix3 |
16224 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
16225 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
16226 | ||
16227 | inst.cond = cond->value; | |
16228 | return opcode; | |
b99bd4ef NC |
16229 | } |
16230 | ||
c921be7d | 16231 | return NULL; |
b99bd4ef NC |
16232 | } |
16233 | ||
e07e6e58 NC |
16234 | /* This function generates an initial IT instruction, leaving its block |
16235 | virtually open for the new instructions. Eventually, | |
16236 | the mask will be updated by now_it_add_mask () each time | |
16237 | a new instruction needs to be included in the IT block. | |
16238 | Finally, the block is closed with close_automatic_it_block (). | |
16239 | The block closure can be requested either from md_assemble (), | |
16240 | a tencode (), or due to a label hook. */ | |
16241 | ||
16242 | static void | |
16243 | new_automatic_it_block (int cond) | |
16244 | { | |
16245 | now_it.state = AUTOMATIC_IT_BLOCK; | |
16246 | now_it.mask = 0x18; | |
16247 | now_it.cc = cond; | |
16248 | now_it.block_length = 1; | |
cd000bff | 16249 | mapping_state (MAP_THUMB); |
e07e6e58 | 16250 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
16251 | now_it.warn_deprecated = FALSE; |
16252 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
16253 | } |
16254 | ||
16255 | /* Close an automatic IT block. | |
16256 | See comments in new_automatic_it_block (). */ | |
16257 | ||
16258 | static void | |
16259 | close_automatic_it_block (void) | |
16260 | { | |
16261 | now_it.mask = 0x10; | |
16262 | now_it.block_length = 0; | |
16263 | } | |
16264 | ||
16265 | /* Update the mask of the current automatically-generated IT | |
16266 | instruction. See comments in new_automatic_it_block (). */ | |
16267 | ||
16268 | static void | |
16269 | now_it_add_mask (int cond) | |
16270 | { | |
16271 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
16272 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
16273 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 16274 | const int resulting_bit = (cond & 1); |
c921be7d | 16275 | |
e07e6e58 NC |
16276 | now_it.mask &= 0xf; |
16277 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
16278 | resulting_bit, | |
16279 | (5 - now_it.block_length)); | |
16280 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
16281 | 1, | |
16282 | ((5 - now_it.block_length) - 1) ); | |
16283 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
16284 | ||
16285 | #undef CLEAR_BIT | |
16286 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
16287 | } |
16288 | ||
16289 | /* The IT blocks handling machinery is accessed through the these functions: | |
16290 | it_fsm_pre_encode () from md_assemble () | |
16291 | set_it_insn_type () optional, from the tencode functions | |
16292 | set_it_insn_type_last () ditto | |
16293 | in_it_block () ditto | |
16294 | it_fsm_post_encode () from md_assemble () | |
16295 | force_automatic_it_block_close () from label habdling functions | |
16296 | ||
16297 | Rationale: | |
16298 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
16299 | initializing the IT insn type with a generic initial value depending | |
16300 | on the inst.condition. | |
16301 | 2) During the tencode function, two things may happen: | |
16302 | a) The tencode function overrides the IT insn type by | |
16303 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
16304 | b) The tencode function queries the IT block state by | |
16305 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
16306 | ||
16307 | Both set_it_insn_type and in_it_block run the internal FSM state | |
16308 | handling function (handle_it_state), because: a) setting the IT insn | |
16309 | type may incur in an invalid state (exiting the function), | |
16310 | and b) querying the state requires the FSM to be updated. | |
16311 | Specifically we want to avoid creating an IT block for conditional | |
16312 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
16313 | determine whether an IT block is required until the tencode () routine | |
16314 | has decided what type of instruction this actually it. | |
16315 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
16316 | set_it_insn_type has to be called first. | |
16317 | ||
16318 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
16319 | determines the insn IT type depending on the inst.cond code. | |
16320 | When a tencode () routine encodes an instruction that can be | |
16321 | either outside an IT block, or, in the case of being inside, has to be | |
16322 | the last one, set_it_insn_type_last () will determine the proper | |
16323 | IT instruction type based on the inst.cond code. Otherwise, | |
16324 | set_it_insn_type can be called for overriding that logic or | |
16325 | for covering other cases. | |
16326 | ||
16327 | Calling handle_it_state () may not transition the IT block state to | |
16328 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
16329 | still queried. Instead, if the FSM determines that the state should | |
16330 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
16331 | after the tencode () function: that's what it_fsm_post_encode () does. | |
16332 | ||
16333 | Since in_it_block () calls the state handling function to get an | |
16334 | updated state, an error may occur (due to invalid insns combination). | |
16335 | In that case, inst.error is set. | |
16336 | Therefore, inst.error has to be checked after the execution of | |
16337 | the tencode () routine. | |
16338 | ||
16339 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
16340 | any pending state change (if any) that didn't take place in | |
16341 | handle_it_state () as explained above. */ | |
16342 | ||
16343 | static void | |
16344 | it_fsm_pre_encode (void) | |
16345 | { | |
16346 | if (inst.cond != COND_ALWAYS) | |
16347 | inst.it_insn_type = INSIDE_IT_INSN; | |
16348 | else | |
16349 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
16350 | ||
16351 | now_it.state_handled = 0; | |
16352 | } | |
16353 | ||
16354 | /* IT state FSM handling function. */ | |
16355 | ||
16356 | static int | |
16357 | handle_it_state (void) | |
16358 | { | |
16359 | now_it.state_handled = 1; | |
5a01bb1d | 16360 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
16361 | |
16362 | switch (now_it.state) | |
16363 | { | |
16364 | case OUTSIDE_IT_BLOCK: | |
16365 | switch (inst.it_insn_type) | |
16366 | { | |
16367 | case OUTSIDE_IT_INSN: | |
16368 | break; | |
16369 | ||
16370 | case INSIDE_IT_INSN: | |
16371 | case INSIDE_IT_LAST_INSN: | |
16372 | if (thumb_mode == 0) | |
16373 | { | |
c921be7d | 16374 | if (unified_syntax |
e07e6e58 NC |
16375 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
16376 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
16377 | " for Thumb.")); | |
16378 | } | |
16379 | else | |
16380 | { | |
16381 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
16382 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
16383 | { | |
16384 | /* Automatically generate the IT instruction. */ | |
16385 | new_automatic_it_block (inst.cond); | |
16386 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
16387 | close_automatic_it_block (); | |
16388 | } | |
16389 | else | |
16390 | { | |
16391 | inst.error = BAD_OUT_IT; | |
16392 | return FAIL; | |
16393 | } | |
16394 | } | |
16395 | break; | |
16396 | ||
16397 | case IF_INSIDE_IT_LAST_INSN: | |
16398 | case NEUTRAL_IT_INSN: | |
16399 | break; | |
16400 | ||
16401 | case IT_INSN: | |
16402 | now_it.state = MANUAL_IT_BLOCK; | |
16403 | now_it.block_length = 0; | |
16404 | break; | |
16405 | } | |
16406 | break; | |
16407 | ||
16408 | case AUTOMATIC_IT_BLOCK: | |
16409 | /* Three things may happen now: | |
16410 | a) We should increment current it block size; | |
16411 | b) We should close current it block (closing insn or 4 insns); | |
16412 | c) We should close current it block and start a new one (due | |
16413 | to incompatible conditions or | |
16414 | 4 insns-length block reached). */ | |
16415 | ||
16416 | switch (inst.it_insn_type) | |
16417 | { | |
16418 | case OUTSIDE_IT_INSN: | |
16419 | /* The closure of the block shall happen immediatelly, | |
16420 | so any in_it_block () call reports the block as closed. */ | |
16421 | force_automatic_it_block_close (); | |
16422 | break; | |
16423 | ||
16424 | case INSIDE_IT_INSN: | |
16425 | case INSIDE_IT_LAST_INSN: | |
16426 | case IF_INSIDE_IT_LAST_INSN: | |
16427 | now_it.block_length++; | |
16428 | ||
16429 | if (now_it.block_length > 4 | |
16430 | || !now_it_compatible (inst.cond)) | |
16431 | { | |
16432 | force_automatic_it_block_close (); | |
16433 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
16434 | new_automatic_it_block (inst.cond); | |
16435 | } | |
16436 | else | |
16437 | { | |
5a01bb1d | 16438 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
16439 | now_it_add_mask (inst.cond); |
16440 | } | |
16441 | ||
16442 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
16443 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
16444 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
16445 | close_automatic_it_block (); | |
16446 | break; | |
16447 | ||
16448 | case NEUTRAL_IT_INSN: | |
16449 | now_it.block_length++; | |
5a01bb1d | 16450 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
16451 | |
16452 | if (now_it.block_length > 4) | |
16453 | force_automatic_it_block_close (); | |
16454 | else | |
16455 | now_it_add_mask (now_it.cc & 1); | |
16456 | break; | |
16457 | ||
16458 | case IT_INSN: | |
16459 | close_automatic_it_block (); | |
16460 | now_it.state = MANUAL_IT_BLOCK; | |
16461 | break; | |
16462 | } | |
16463 | break; | |
16464 | ||
16465 | case MANUAL_IT_BLOCK: | |
16466 | { | |
16467 | /* Check conditional suffixes. */ | |
16468 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
16469 | int is_last; | |
16470 | now_it.mask <<= 1; | |
16471 | now_it.mask &= 0x1f; | |
16472 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 16473 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
16474 | |
16475 | switch (inst.it_insn_type) | |
16476 | { | |
16477 | case OUTSIDE_IT_INSN: | |
16478 | inst.error = BAD_NOT_IT; | |
16479 | return FAIL; | |
16480 | ||
16481 | case INSIDE_IT_INSN: | |
16482 | if (cond != inst.cond) | |
16483 | { | |
16484 | inst.error = BAD_IT_COND; | |
16485 | return FAIL; | |
16486 | } | |
16487 | break; | |
16488 | ||
16489 | case INSIDE_IT_LAST_INSN: | |
16490 | case IF_INSIDE_IT_LAST_INSN: | |
16491 | if (cond != inst.cond) | |
16492 | { | |
16493 | inst.error = BAD_IT_COND; | |
16494 | return FAIL; | |
16495 | } | |
16496 | if (!is_last) | |
16497 | { | |
16498 | inst.error = BAD_BRANCH; | |
16499 | return FAIL; | |
16500 | } | |
16501 | break; | |
16502 | ||
16503 | case NEUTRAL_IT_INSN: | |
16504 | /* The BKPT instruction is unconditional even in an IT block. */ | |
16505 | break; | |
16506 | ||
16507 | case IT_INSN: | |
16508 | inst.error = BAD_IT_IT; | |
16509 | return FAIL; | |
16510 | } | |
16511 | } | |
16512 | break; | |
16513 | } | |
16514 | ||
16515 | return SUCCESS; | |
16516 | } | |
16517 | ||
5a01bb1d MGD |
16518 | struct depr_insn_mask |
16519 | { | |
16520 | unsigned long pattern; | |
16521 | unsigned long mask; | |
16522 | const char* description; | |
16523 | }; | |
16524 | ||
16525 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
16526 | ARMv8. */ | |
16527 | static const struct depr_insn_mask depr_it_insns[] = { | |
16528 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
16529 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
16530 | { 0xa000, 0xb800, N_("ADR") }, | |
16531 | { 0x4800, 0xf800, N_("Literal loads") }, | |
16532 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
16533 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
16534 | { 0, 0, NULL } | |
16535 | }; | |
16536 | ||
e07e6e58 NC |
16537 | static void |
16538 | it_fsm_post_encode (void) | |
16539 | { | |
16540 | int is_last; | |
16541 | ||
16542 | if (!now_it.state_handled) | |
16543 | handle_it_state (); | |
16544 | ||
5a01bb1d MGD |
16545 | if (now_it.insn_cond |
16546 | && !now_it.warn_deprecated | |
16547 | && warn_on_deprecated | |
16548 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
16549 | { | |
16550 | if (inst.instruction >= 0x10000) | |
16551 | { | |
16552 | as_warn (_("it blocks containing wide Thumb instructions are " | |
16553 | "deprecated in ARMv8")); | |
16554 | now_it.warn_deprecated = TRUE; | |
16555 | } | |
16556 | else | |
16557 | { | |
16558 | const struct depr_insn_mask *p = depr_it_insns; | |
16559 | ||
16560 | while (p->mask != 0) | |
16561 | { | |
16562 | if ((inst.instruction & p->mask) == p->pattern) | |
16563 | { | |
16564 | as_warn (_("it blocks containing 16-bit Thumb intsructions " | |
16565 | "of the following class are deprecated in ARMv8: " | |
16566 | "%s"), p->description); | |
16567 | now_it.warn_deprecated = TRUE; | |
16568 | break; | |
16569 | } | |
16570 | ||
16571 | ++p; | |
16572 | } | |
16573 | } | |
16574 | ||
16575 | if (now_it.block_length > 1) | |
16576 | { | |
16577 | as_warn (_("it blocks of more than one conditional instruction are " | |
16578 | "deprecated in ARMv8")); | |
16579 | now_it.warn_deprecated = TRUE; | |
16580 | } | |
16581 | } | |
16582 | ||
e07e6e58 NC |
16583 | is_last = (now_it.mask == 0x10); |
16584 | if (is_last) | |
16585 | { | |
16586 | now_it.state = OUTSIDE_IT_BLOCK; | |
16587 | now_it.mask = 0; | |
16588 | } | |
16589 | } | |
16590 | ||
16591 | static void | |
16592 | force_automatic_it_block_close (void) | |
16593 | { | |
16594 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
16595 | { | |
16596 | close_automatic_it_block (); | |
16597 | now_it.state = OUTSIDE_IT_BLOCK; | |
16598 | now_it.mask = 0; | |
16599 | } | |
16600 | } | |
16601 | ||
16602 | static int | |
16603 | in_it_block (void) | |
16604 | { | |
16605 | if (!now_it.state_handled) | |
16606 | handle_it_state (); | |
16607 | ||
16608 | return now_it.state != OUTSIDE_IT_BLOCK; | |
16609 | } | |
16610 | ||
c19d1205 ZW |
16611 | void |
16612 | md_assemble (char *str) | |
b99bd4ef | 16613 | { |
c19d1205 ZW |
16614 | char *p = str; |
16615 | const struct asm_opcode * opcode; | |
b99bd4ef | 16616 | |
c19d1205 ZW |
16617 | /* Align the previous label if needed. */ |
16618 | if (last_label_seen != NULL) | |
b99bd4ef | 16619 | { |
c19d1205 ZW |
16620 | symbol_set_frag (last_label_seen, frag_now); |
16621 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
16622 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
16623 | } |
16624 | ||
c19d1205 ZW |
16625 | memset (&inst, '\0', sizeof (inst)); |
16626 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 16627 | |
c19d1205 ZW |
16628 | opcode = opcode_lookup (&p); |
16629 | if (!opcode) | |
b99bd4ef | 16630 | { |
c19d1205 | 16631 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 16632 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
16633 | if (! create_register_alias (str, p) |
16634 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 16635 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 16636 | |
b99bd4ef NC |
16637 | return; |
16638 | } | |
16639 | ||
278df34e | 16640 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
16641 | as_warn (_("s suffix on comparison instruction is deprecated")); |
16642 | ||
037e8744 JB |
16643 | /* The value which unconditional instructions should have in place of the |
16644 | condition field. */ | |
16645 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
16646 | ||
c19d1205 | 16647 | if (thumb_mode) |
b99bd4ef | 16648 | { |
e74cfd16 | 16649 | arm_feature_set variant; |
8f06b2d8 PB |
16650 | |
16651 | variant = cpu_variant; | |
16652 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
16653 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
16654 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 16655 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
16656 | if (!opcode->tvariant |
16657 | || (thumb_mode == 1 | |
16658 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 16659 | { |
bf3eeda7 | 16660 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
16661 | return; |
16662 | } | |
c19d1205 ZW |
16663 | if (inst.cond != COND_ALWAYS && !unified_syntax |
16664 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 16665 | { |
c19d1205 | 16666 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
16667 | return; |
16668 | } | |
16669 | ||
752d5da4 | 16670 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 16671 | { |
7e806470 | 16672 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
16673 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
16674 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
16675 | { | |
16676 | /* Two things are addressed here. | |
16677 | 1) Implicit require narrow instructions on Thumb-1. | |
16678 | This avoids relaxation accidentally introducing Thumb-2 | |
16679 | instructions. | |
16680 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
16681 | if (inst.size_req == 0) | |
16682 | inst.size_req = 2; | |
16683 | else if (inst.size_req == 4) | |
16684 | { | |
bf3eeda7 | 16685 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
16686 | return; |
16687 | } | |
16688 | } | |
076d447c PB |
16689 | } |
16690 | ||
c19d1205 ZW |
16691 | inst.instruction = opcode->tvalue; |
16692 | ||
5be8be5d | 16693 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
16694 | { |
16695 | /* Prepare the it_insn_type for those encodings that don't set | |
16696 | it. */ | |
16697 | it_fsm_pre_encode (); | |
c19d1205 | 16698 | |
e07e6e58 NC |
16699 | opcode->tencode (); |
16700 | ||
16701 | it_fsm_post_encode (); | |
16702 | } | |
e27ec89e | 16703 | |
0110f2b8 | 16704 | if (!(inst.error || inst.relax)) |
b99bd4ef | 16705 | { |
9c2799c2 | 16706 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
16707 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
16708 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 16709 | { |
c19d1205 | 16710 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
16711 | return; |
16712 | } | |
16713 | } | |
076d447c PB |
16714 | |
16715 | /* Something has gone badly wrong if we try to relax a fixed size | |
16716 | instruction. */ | |
9c2799c2 | 16717 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 16718 | |
e74cfd16 PB |
16719 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16720 | *opcode->tvariant); | |
ee065d83 | 16721 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 16722 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 16723 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 16724 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
16725 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
16726 | || inst.relax) | |
e07e6e58 NC |
16727 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
16728 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
16729 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16730 | arm_ext_v6t2); | |
cd000bff | 16731 | |
88714cb8 DG |
16732 | check_neon_suffixes; |
16733 | ||
cd000bff | 16734 | if (!inst.error) |
c877a2f2 NC |
16735 | { |
16736 | mapping_state (MAP_THUMB); | |
16737 | } | |
c19d1205 | 16738 | } |
3e9e4fcf | 16739 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 16740 | { |
845b51d6 PB |
16741 | bfd_boolean is_bx; |
16742 | ||
16743 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
16744 | is_bx = (opcode->aencode == do_bx); | |
16745 | ||
c19d1205 | 16746 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
16747 | if (!(is_bx && fix_v4bx) |
16748 | && !(opcode->avariant && | |
16749 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 16750 | { |
bf3eeda7 | 16751 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 16752 | return; |
b99bd4ef | 16753 | } |
c19d1205 | 16754 | if (inst.size_req) |
b99bd4ef | 16755 | { |
c19d1205 ZW |
16756 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
16757 | return; | |
b99bd4ef NC |
16758 | } |
16759 | ||
c19d1205 ZW |
16760 | inst.instruction = opcode->avalue; |
16761 | if (opcode->tag == OT_unconditionalF) | |
16762 | inst.instruction |= 0xF << 28; | |
16763 | else | |
16764 | inst.instruction |= inst.cond << 28; | |
16765 | inst.size = INSN_SIZE; | |
5be8be5d | 16766 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
16767 | { |
16768 | it_fsm_pre_encode (); | |
16769 | opcode->aencode (); | |
16770 | it_fsm_post_encode (); | |
16771 | } | |
ee065d83 PB |
16772 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
16773 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 16774 | if (is_bx) |
e74cfd16 | 16775 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 16776 | else |
e74cfd16 PB |
16777 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
16778 | *opcode->avariant); | |
88714cb8 DG |
16779 | |
16780 | check_neon_suffixes; | |
16781 | ||
cd000bff | 16782 | if (!inst.error) |
c877a2f2 NC |
16783 | { |
16784 | mapping_state (MAP_ARM); | |
16785 | } | |
b99bd4ef | 16786 | } |
3e9e4fcf JB |
16787 | else |
16788 | { | |
16789 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
16790 | "-- `%s'"), str); | |
16791 | return; | |
16792 | } | |
c19d1205 ZW |
16793 | output_inst (str); |
16794 | } | |
b99bd4ef | 16795 | |
e07e6e58 NC |
16796 | static void |
16797 | check_it_blocks_finished (void) | |
16798 | { | |
16799 | #ifdef OBJ_ELF | |
16800 | asection *sect; | |
16801 | ||
16802 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
16803 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
16804 | == MANUAL_IT_BLOCK) | |
16805 | { | |
16806 | as_warn (_("section '%s' finished with an open IT block."), | |
16807 | sect->name); | |
16808 | } | |
16809 | #else | |
16810 | if (now_it.state == MANUAL_IT_BLOCK) | |
16811 | as_warn (_("file finished with an open IT block.")); | |
16812 | #endif | |
16813 | } | |
16814 | ||
c19d1205 ZW |
16815 | /* Various frobbings of labels and their addresses. */ |
16816 | ||
16817 | void | |
16818 | arm_start_line_hook (void) | |
16819 | { | |
16820 | last_label_seen = NULL; | |
b99bd4ef NC |
16821 | } |
16822 | ||
c19d1205 ZW |
16823 | void |
16824 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 16825 | { |
c19d1205 | 16826 | last_label_seen = sym; |
b99bd4ef | 16827 | |
c19d1205 | 16828 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 16829 | |
c19d1205 ZW |
16830 | #if defined OBJ_COFF || defined OBJ_ELF |
16831 | ARM_SET_INTERWORK (sym, support_interwork); | |
16832 | #endif | |
b99bd4ef | 16833 | |
e07e6e58 NC |
16834 | force_automatic_it_block_close (); |
16835 | ||
5f4273c7 | 16836 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
16837 | as Thumb functions. This is because these labels, whilst |
16838 | they exist inside Thumb code, are not the entry points for | |
16839 | possible ARM->Thumb calls. Also, these labels can be used | |
16840 | as part of a computed goto or switch statement. eg gcc | |
16841 | can generate code that looks like this: | |
b99bd4ef | 16842 | |
c19d1205 ZW |
16843 | ldr r2, [pc, .Laaa] |
16844 | lsl r3, r3, #2 | |
16845 | ldr r2, [r3, r2] | |
16846 | mov pc, r2 | |
b99bd4ef | 16847 | |
c19d1205 ZW |
16848 | .Lbbb: .word .Lxxx |
16849 | .Lccc: .word .Lyyy | |
16850 | ..etc... | |
16851 | .Laaa: .word Lbbb | |
b99bd4ef | 16852 | |
c19d1205 ZW |
16853 | The first instruction loads the address of the jump table. |
16854 | The second instruction converts a table index into a byte offset. | |
16855 | The third instruction gets the jump address out of the table. | |
16856 | The fourth instruction performs the jump. | |
b99bd4ef | 16857 | |
c19d1205 ZW |
16858 | If the address stored at .Laaa is that of a symbol which has the |
16859 | Thumb_Func bit set, then the linker will arrange for this address | |
16860 | to have the bottom bit set, which in turn would mean that the | |
16861 | address computation performed by the third instruction would end | |
16862 | up with the bottom bit set. Since the ARM is capable of unaligned | |
16863 | word loads, the instruction would then load the incorrect address | |
16864 | out of the jump table, and chaos would ensue. */ | |
16865 | if (label_is_thumb_function_name | |
16866 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
16867 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 16868 | { |
c19d1205 ZW |
16869 | /* When the address of a Thumb function is taken the bottom |
16870 | bit of that address should be set. This will allow | |
16871 | interworking between Arm and Thumb functions to work | |
16872 | correctly. */ | |
b99bd4ef | 16873 | |
c19d1205 | 16874 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 16875 | |
c19d1205 | 16876 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 16877 | } |
07a53e5c | 16878 | |
07a53e5c | 16879 | dwarf2_emit_label (sym); |
b99bd4ef NC |
16880 | } |
16881 | ||
c921be7d | 16882 | bfd_boolean |
c19d1205 | 16883 | arm_data_in_code (void) |
b99bd4ef | 16884 | { |
c19d1205 | 16885 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16886 | { |
c19d1205 ZW |
16887 | *input_line_pointer = '/'; |
16888 | input_line_pointer += 5; | |
16889 | *input_line_pointer = 0; | |
c921be7d | 16890 | return TRUE; |
b99bd4ef NC |
16891 | } |
16892 | ||
c921be7d | 16893 | return FALSE; |
b99bd4ef NC |
16894 | } |
16895 | ||
c19d1205 ZW |
16896 | char * |
16897 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16898 | { |
c19d1205 | 16899 | int len; |
b99bd4ef | 16900 | |
c19d1205 ZW |
16901 | if (thumb_mode && (len = strlen (name)) > 5 |
16902 | && streq (name + len - 5, "/data")) | |
16903 | *(name + len - 5) = 0; | |
b99bd4ef | 16904 | |
c19d1205 | 16905 | return name; |
b99bd4ef | 16906 | } |
c19d1205 ZW |
16907 | \f |
16908 | /* Table of all register names defined by default. The user can | |
16909 | define additional names with .req. Note that all register names | |
16910 | should appear in both upper and lowercase variants. Some registers | |
16911 | also have mixed-case names. */ | |
b99bd4ef | 16912 | |
dcbf9037 | 16913 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16914 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16915 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16916 | #define REGSET(p,t) \ |
16917 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16918 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16919 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16920 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16921 | #define REGSETH(p,t) \ |
16922 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16923 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16924 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16925 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16926 | #define REGSET2(p,t) \ | |
16927 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16928 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16929 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16930 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
16931 | #define SPLRBANK(base,bank,t) \ |
16932 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
16933 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
16934 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
16935 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
16936 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
16937 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 16938 | |
c19d1205 | 16939 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16940 | { |
c19d1205 ZW |
16941 | /* ARM integer registers. */ |
16942 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16943 | |
c19d1205 ZW |
16944 | /* ATPCS synonyms. */ |
16945 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16946 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16947 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16948 | |
c19d1205 ZW |
16949 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16950 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16951 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16952 | |
c19d1205 ZW |
16953 | /* Well-known aliases. */ |
16954 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16955 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16956 | ||
16957 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16958 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16959 | ||
16960 | /* Coprocessor numbers. */ | |
16961 | REGSET(p, CP), REGSET(P, CP), | |
16962 | ||
16963 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16964 | compatibility. */ | |
16965 | REGSET(c, CN), REGSET(C, CN), | |
16966 | REGSET(cr, CN), REGSET(CR, CN), | |
16967 | ||
90ec0d68 MGD |
16968 | /* ARM banked registers. */ |
16969 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
16970 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
16971 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
16972 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
16973 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
16974 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
16975 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
16976 | ||
16977 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
16978 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
16979 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
16980 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
16981 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
16982 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB), | |
16983 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), | |
16984 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
16985 | ||
16986 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
16987 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
16988 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
16989 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
16990 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
16991 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
16992 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 16993 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
16994 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
16995 | ||
c19d1205 ZW |
16996 | /* FPA registers. */ |
16997 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16998 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16999 | ||
17000 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
17001 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
17002 | ||
17003 | /* VFP SP registers. */ | |
5287ad62 JB |
17004 | REGSET(s,VFS), REGSET(S,VFS), |
17005 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
17006 | |
17007 | /* VFP DP Registers. */ | |
5287ad62 JB |
17008 | REGSET(d,VFD), REGSET(D,VFD), |
17009 | /* Extra Neon DP registers. */ | |
17010 | REGSETH(d,VFD), REGSETH(D,VFD), | |
17011 | ||
17012 | /* Neon QP registers. */ | |
17013 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
17014 | |
17015 | /* VFP control registers. */ | |
17016 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
17017 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
17018 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
17019 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
17020 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
17021 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
17022 | |
17023 | /* Maverick DSP coprocessor registers. */ | |
17024 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
17025 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
17026 | ||
17027 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
17028 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
17029 | REGDEF(dspsc,0,DSPSC), | |
17030 | ||
17031 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
17032 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
17033 | REGDEF(DSPSC,0,DSPSC), | |
17034 | ||
17035 | /* iWMMXt data registers - p0, c0-15. */ | |
17036 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
17037 | ||
17038 | /* iWMMXt control registers - p1, c0-3. */ | |
17039 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
17040 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
17041 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
17042 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
17043 | ||
17044 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
17045 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
17046 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
17047 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
17048 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
17049 | ||
17050 | /* XScale accumulator registers. */ | |
17051 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
17052 | }; | |
17053 | #undef REGDEF | |
17054 | #undef REGNUM | |
17055 | #undef REGSET | |
7ed4c4c5 | 17056 | |
c19d1205 ZW |
17057 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
17058 | within psr_required_here. */ | |
17059 | static const struct asm_psr psrs[] = | |
17060 | { | |
17061 | /* Backward compatibility notation. Note that "all" is no longer | |
17062 | truly all possible PSR bits. */ | |
17063 | {"all", PSR_c | PSR_f}, | |
17064 | {"flg", PSR_f}, | |
17065 | {"ctl", PSR_c}, | |
17066 | ||
17067 | /* Individual flags. */ | |
17068 | {"f", PSR_f}, | |
17069 | {"c", PSR_c}, | |
17070 | {"x", PSR_x}, | |
17071 | {"s", PSR_s}, | |
59b42a0d | 17072 | |
c19d1205 ZW |
17073 | /* Combinations of flags. */ |
17074 | {"fs", PSR_f | PSR_s}, | |
17075 | {"fx", PSR_f | PSR_x}, | |
17076 | {"fc", PSR_f | PSR_c}, | |
17077 | {"sf", PSR_s | PSR_f}, | |
17078 | {"sx", PSR_s | PSR_x}, | |
17079 | {"sc", PSR_s | PSR_c}, | |
17080 | {"xf", PSR_x | PSR_f}, | |
17081 | {"xs", PSR_x | PSR_s}, | |
17082 | {"xc", PSR_x | PSR_c}, | |
17083 | {"cf", PSR_c | PSR_f}, | |
17084 | {"cs", PSR_c | PSR_s}, | |
17085 | {"cx", PSR_c | PSR_x}, | |
17086 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
17087 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
17088 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
17089 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
17090 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
17091 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
17092 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
17093 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
17094 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
17095 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
17096 | {"scf", PSR_s | PSR_c | PSR_f}, | |
17097 | {"scx", PSR_s | PSR_c | PSR_x}, | |
17098 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
17099 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
17100 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
17101 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
17102 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
17103 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
17104 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
17105 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
17106 | {"csf", PSR_c | PSR_s | PSR_f}, | |
17107 | {"csx", PSR_c | PSR_s | PSR_x}, | |
17108 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
17109 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
17110 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
17111 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
17112 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
17113 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
17114 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
17115 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
17116 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
17117 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
17118 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
17119 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
17120 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
17121 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
17122 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
17123 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
17124 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
17125 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
17126 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
17127 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
17128 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
17129 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
17130 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
17131 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
17132 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
17133 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
17134 | }; | |
17135 | ||
62b3e311 PB |
17136 | /* Table of V7M psr names. */ |
17137 | static const struct asm_psr v7m_psrs[] = | |
17138 | { | |
2b744c99 PB |
17139 | {"apsr", 0 }, {"APSR", 0 }, |
17140 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
17141 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
17142 | {"psr", 3 }, {"PSR", 3 }, | |
17143 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
17144 | {"ipsr", 5 }, {"IPSR", 5 }, | |
17145 | {"epsr", 6 }, {"EPSR", 6 }, | |
17146 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
17147 | {"msp", 8 }, {"MSP", 8 }, | |
17148 | {"psp", 9 }, {"PSP", 9 }, | |
17149 | {"primask", 16}, {"PRIMASK", 16}, | |
17150 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
17151 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
17152 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
17153 | {"faultmask", 19}, {"FAULTMASK", 19}, |
17154 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
17155 | }; |
17156 | ||
c19d1205 ZW |
17157 | /* Table of all shift-in-operand names. */ |
17158 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 17159 | { |
c19d1205 ZW |
17160 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
17161 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
17162 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
17163 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
17164 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
17165 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
17166 | }; | |
b99bd4ef | 17167 | |
c19d1205 ZW |
17168 | /* Table of all explicit relocation names. */ |
17169 | #ifdef OBJ_ELF | |
17170 | static struct reloc_entry reloc_names[] = | |
17171 | { | |
17172 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
17173 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
17174 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
17175 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
17176 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
17177 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
17178 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
17179 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
17180 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
17181 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 17182 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
17183 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
17184 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
17185 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, | |
17186 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, | |
17187 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, | |
17188 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, | |
17189 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} | |
c19d1205 ZW |
17190 | }; |
17191 | #endif | |
b99bd4ef | 17192 | |
c19d1205 ZW |
17193 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
17194 | static const struct asm_cond conds[] = | |
17195 | { | |
17196 | {"eq", 0x0}, | |
17197 | {"ne", 0x1}, | |
17198 | {"cs", 0x2}, {"hs", 0x2}, | |
17199 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
17200 | {"mi", 0x4}, | |
17201 | {"pl", 0x5}, | |
17202 | {"vs", 0x6}, | |
17203 | {"vc", 0x7}, | |
17204 | {"hi", 0x8}, | |
17205 | {"ls", 0x9}, | |
17206 | {"ge", 0xa}, | |
17207 | {"lt", 0xb}, | |
17208 | {"gt", 0xc}, | |
17209 | {"le", 0xd}, | |
17210 | {"al", 0xe} | |
17211 | }; | |
bfae80f2 | 17212 | |
e797f7e0 MGD |
17213 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
17214 | { L, CODE, ARM_FEATURE (FEAT, 0) }, \ | |
17215 | { U, CODE, ARM_FEATURE (FEAT, 0) } | |
17216 | ||
62b3e311 PB |
17217 | static struct asm_barrier_opt barrier_opt_names[] = |
17218 | { | |
e797f7e0 MGD |
17219 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
17220 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
17221 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
17222 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
17223 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
17224 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
17225 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
17226 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
17227 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
17228 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
17229 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
17230 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
17231 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
17232 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
17233 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
17234 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
17235 | }; |
17236 | ||
e797f7e0 MGD |
17237 | #undef UL_BARRIER |
17238 | ||
c19d1205 ZW |
17239 | /* Table of ARM-format instructions. */ |
17240 | ||
17241 | /* Macros for gluing together operand strings. N.B. In all cases | |
17242 | other than OPS0, the trailing OP_stop comes from default | |
17243 | zero-initialization of the unspecified elements of the array. */ | |
17244 | #define OPS0() { OP_stop, } | |
17245 | #define OPS1(a) { OP_##a, } | |
17246 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
17247 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
17248 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
17249 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
17250 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
17251 | ||
5be8be5d DG |
17252 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
17253 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
17254 | MIX_ARM_THUMB_OPERANDS macro. | |
17255 | In order to use these macros, prefix the number of operands with _ | |
17256 | e.g. _3. */ | |
17257 | #define OPS_1(a) { a, } | |
17258 | #define OPS_2(a,b) { a,b, } | |
17259 | #define OPS_3(a,b,c) { a,b,c, } | |
17260 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
17261 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
17262 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
17263 | ||
c19d1205 ZW |
17264 | /* These macros abstract out the exact format of the mnemonic table and |
17265 | save some repeated characters. */ | |
17266 | ||
17267 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
17268 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17269 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 17270 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17271 | |
17272 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
17273 | a T_MNEM_xyz enumerator. */ | |
17274 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 17275 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 17276 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17277 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17278 | |
17279 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
17280 | infix after the third character. */ | |
17281 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17282 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 17283 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 17284 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 17285 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 17286 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 17287 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 17288 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 17289 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 17290 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 17291 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17292 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 17293 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17294 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17295 | |
17296 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
17297 | appear in the condition table. */ | |
17298 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17299 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 17300 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17301 | |
17302 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
17303 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
17304 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
17305 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
17306 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
17307 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
17308 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
17309 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
17310 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
17311 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
17312 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
17313 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
17314 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
17315 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
17316 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
17317 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
17318 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
17319 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
17320 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
17321 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
17322 | |
17323 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
17324 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
17325 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 17326 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17327 | |
17328 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
17329 | field is still 0xE. Many of the Thumb variants can be executed |
17330 | conditionally, so this is checked separately. */ | |
c19d1205 | 17331 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 17332 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 17333 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17334 | |
17335 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
17336 | condition code field. */ | |
17337 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17338 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 17339 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17340 | |
17341 | /* ARM-only variants of all the above. */ | |
6a86118a | 17342 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 17343 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
17344 | |
17345 | #define C3(mnem, op, nops, ops, ae) \ | |
17346 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
17347 | ||
e3cb604e PB |
17348 | /* Legacy mnemonics that always have conditional infix after the third |
17349 | character. */ | |
17350 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17351 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
17352 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
17353 | ||
8f06b2d8 PB |
17354 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
17355 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17356 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 17357 | |
e3cb604e PB |
17358 | /* Legacy coprocessor instructions where conditional infix and conditional |
17359 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
17360 | not just the potentially ambiguous ones. */ | |
17361 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17362 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
17363 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
17364 | ||
17365 | /* Coprocessor, takes either a suffix or a position-3 infix | |
17366 | (for an FPA corner case). */ | |
17367 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17368 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 17369 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 17370 | |
6a86118a | 17371 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
17372 | { m1 #m2 m3, OPS##nops ops, \ |
17373 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
17374 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
17375 | ||
17376 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
17377 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
17378 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
17379 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
17380 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
17381 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
17382 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
17383 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
17384 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
17385 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
17386 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
17387 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
17388 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
17389 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
17390 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
17391 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
17392 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
17393 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
17394 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
17395 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
17396 | |
17397 | #define UE(mnem, op, nops, ops, ae) \ | |
17398 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
17399 | ||
17400 | #define UF(mnem, op, nops, ops, ae) \ | |
17401 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
17402 | ||
5287ad62 JB |
17403 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
17404 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
17405 | use the same encoding function for each. */ | |
17406 | #define NUF(mnem, op, nops, ops, enc) \ | |
17407 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
17408 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
17409 | ||
17410 | /* Neon data processing, version which indirects through neon_enc_tab for | |
17411 | the various overloaded versions of opcodes. */ | |
17412 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 17413 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17414 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17415 | ||
17416 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
17417 | version. */ | |
037e8744 JB |
17418 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
17419 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
17420 | THUMB_VARIANT, do_##enc, do_##enc } |
17421 | ||
037e8744 | 17422 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17423 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17424 | |
17425 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17426 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17427 | |
5287ad62 | 17428 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 17429 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 17430 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17431 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17432 | ||
037e8744 | 17433 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17434 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17435 | |
17436 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17437 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17438 | |
c19d1205 ZW |
17439 | #define do_0 0 |
17440 | ||
c19d1205 | 17441 | static const struct asm_opcode insns[] = |
bfae80f2 | 17442 | { |
e74cfd16 PB |
17443 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
17444 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
17445 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
17446 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
17447 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
17448 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
17449 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
17450 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
17451 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17452 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17453 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
17454 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17455 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
17456 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
17457 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
17458 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17459 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
17460 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
17461 | |
17462 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
17463 | for setting PSR flag bits. They are obsolete in V6 and do not | |
17464 | have Thumb equivalents. */ | |
21d799b5 NC |
17465 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
17466 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
17467 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
17468 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17469 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17470 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
17471 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17472 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17473 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
17474 | ||
17475 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
17476 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
17477 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
17478 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
17479 | ||
17480 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
17481 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
17482 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
17483 | OP_RRnpc), | |
17484 | OP_ADDRGLDR),ldst, t_ldst), | |
17485 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
17486 | |
17487 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17488 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17489 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17490 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17491 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17492 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17493 | ||
17494 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
17495 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
17496 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
17497 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 17498 | |
c19d1205 | 17499 | /* Pseudo ops. */ |
21d799b5 | 17500 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 17501 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 17502 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
17503 | |
17504 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
17505 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
17506 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
17507 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
17508 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
17509 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
17510 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
17511 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
17512 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
17513 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
17514 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
17515 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
17516 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 17517 | |
16a4cf17 | 17518 | /* These may simplify to neg. */ |
21d799b5 NC |
17519 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
17520 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 17521 | |
c921be7d NC |
17522 | #undef THUMB_VARIANT |
17523 | #define THUMB_VARIANT & arm_ext_v6 | |
17524 | ||
21d799b5 | 17525 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
17526 | |
17527 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
17528 | #undef THUMB_VARIANT |
17529 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17530 | ||
21d799b5 NC |
17531 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
17532 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
17533 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 17534 | |
5be8be5d DG |
17535 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
17536 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
17537 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
17538 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 17539 | |
21d799b5 NC |
17540 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17541 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 17542 | |
21d799b5 NC |
17543 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17544 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
17545 | |
17546 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 17547 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
17548 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
17549 | ||
17550 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
17551 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
17552 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
17553 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
17554 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
17555 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
17556 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
17557 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
17558 | ||
c921be7d NC |
17559 | #undef ARM_VARIANT |
17560 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
17561 | #undef THUMB_VARIANT | |
17562 | #define THUMB_VARIANT & arm_ext_v4t | |
17563 | ||
21d799b5 NC |
17564 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
17565 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 17566 | |
c921be7d NC |
17567 | #undef THUMB_VARIANT |
17568 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17569 | ||
21d799b5 | 17570 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
17571 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
17572 | ||
17573 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
17574 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
17575 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17576 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17577 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17578 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17579 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 17580 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 17581 | |
c921be7d NC |
17582 | #undef ARM_VARIANT |
17583 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
17584 | ||
21d799b5 | 17585 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
17586 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
17587 | ||
c921be7d NC |
17588 | #undef ARM_VARIANT |
17589 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
17590 | #undef THUMB_VARIANT | |
17591 | #define THUMB_VARIANT & arm_ext_msr | |
17592 | ||
d2cd1205 JB |
17593 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
17594 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 17595 | |
c921be7d NC |
17596 | #undef ARM_VARIANT |
17597 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
17598 | #undef THUMB_VARIANT | |
17599 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17600 | ||
21d799b5 NC |
17601 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
17602 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17603 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17604 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17605 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17606 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17607 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17608 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 17609 | |
c921be7d NC |
17610 | #undef ARM_VARIANT |
17611 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
17612 | #undef THUMB_VARIANT | |
17613 | #define THUMB_VARIANT & arm_ext_v4t | |
17614 | ||
5be8be5d DG |
17615 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
17616 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17617 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17618 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17619 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17620 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 17621 | |
c921be7d NC |
17622 | #undef ARM_VARIANT |
17623 | #define ARM_VARIANT & arm_ext_v4t_5 | |
17624 | ||
c19d1205 ZW |
17625 | /* ARM Architecture 4T. */ |
17626 | /* Note: bx (and blx) are required on V5, even if the processor does | |
17627 | not support Thumb. */ | |
21d799b5 | 17628 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 17629 | |
c921be7d NC |
17630 | #undef ARM_VARIANT |
17631 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
17632 | #undef THUMB_VARIANT | |
17633 | #define THUMB_VARIANT & arm_ext_v5t | |
17634 | ||
c19d1205 ZW |
17635 | /* Note: blx has 2 variants; the .value coded here is for |
17636 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
17637 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
17638 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 17639 | |
c921be7d NC |
17640 | #undef THUMB_VARIANT |
17641 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17642 | ||
21d799b5 NC |
17643 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
17644 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17645 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17646 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17647 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17648 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
17649 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
17650 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 17651 | |
c921be7d NC |
17652 | #undef ARM_VARIANT |
17653 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
17654 | #undef THUMB_VARIANT |
17655 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 17656 | |
21d799b5 NC |
17657 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17658 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17659 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17660 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17661 | |
21d799b5 NC |
17662 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17663 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17664 | |
21d799b5 NC |
17665 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
17666 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17667 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17668 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 17669 | |
21d799b5 NC |
17670 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17671 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17672 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17673 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17674 | |
21d799b5 NC |
17675 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17676 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17677 | |
03ee1b7f NC |
17678 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
17679 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17680 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17681 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 17682 | |
c921be7d NC |
17683 | #undef ARM_VARIANT |
17684 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
17685 | #undef THUMB_VARIANT |
17686 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 17687 | |
21d799b5 | 17688 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
17689 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
17690 | ldrd, t_ldstd), | |
17691 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
17692 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 17693 | |
21d799b5 NC |
17694 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17695 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 17696 | |
c921be7d NC |
17697 | #undef ARM_VARIANT |
17698 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
17699 | ||
21d799b5 | 17700 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 17701 | |
c921be7d NC |
17702 | #undef ARM_VARIANT |
17703 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
17704 | #undef THUMB_VARIANT | |
17705 | #define THUMB_VARIANT & arm_ext_v6 | |
17706 | ||
21d799b5 NC |
17707 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
17708 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
17709 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17710 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17711 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17712 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17713 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17714 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17715 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17716 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 17717 | |
c921be7d NC |
17718 | #undef THUMB_VARIANT |
17719 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17720 | ||
5be8be5d DG |
17721 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
17722 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17723 | strex, t_strex), | |
21d799b5 NC |
17724 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17725 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 17726 | |
21d799b5 NC |
17727 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
17728 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 17729 | |
9e3c6df6 | 17730 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
17731 | #undef THUMB_VARIANT |
17732 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
17733 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
17734 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
17735 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
17736 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17737 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
17738 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
17739 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
17740 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17741 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
17742 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
17743 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
17744 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 17745 | |
9e3c6df6 PB |
17746 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
17747 | #undef THUMB_VARIANT | |
17748 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
17749 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
17750 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
17751 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
17752 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17753 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17754 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17755 | /* Old name for QASX. */ |
21d799b5 NC |
17756 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17757 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17758 | /* Old name for QSAX. */ |
21d799b5 NC |
17759 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17760 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17761 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17762 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17763 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17764 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17765 | /* Old name for SASX. */ |
21d799b5 NC |
17766 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17767 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17768 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17769 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17770 | /* Old name for SHASX. */ |
21d799b5 NC |
17771 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17772 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17773 | /* Old name for SHSAX. */ |
21d799b5 NC |
17774 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17775 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17776 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17777 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17778 | /* Old name for SSAX. */ |
21d799b5 NC |
17779 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17780 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17781 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17782 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17783 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17784 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17785 | /* Old name for UASX. */ |
21d799b5 NC |
17786 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17787 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17788 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17789 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17790 | /* Old name for UHASX. */ |
21d799b5 NC |
17791 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17792 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17793 | /* Old name for UHSAX. */ |
21d799b5 NC |
17794 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17795 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17796 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17797 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17798 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17799 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17800 | /* Old name for UQASX. */ |
21d799b5 NC |
17801 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17802 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17803 | /* Old name for UQSAX. */ |
21d799b5 NC |
17804 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17805 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17806 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17807 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17808 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17809 | /* Old name for USAX. */ |
21d799b5 NC |
17810 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17811 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
17812 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
17813 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17814 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17815 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17816 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17817 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17818 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17819 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17820 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17821 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17822 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17823 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17824 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17825 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17826 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17827 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17828 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17829 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17830 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17831 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17832 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17833 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17834 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17835 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17836 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17837 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17838 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
17839 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
17840 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
17841 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17842 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17843 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 17844 | |
c921be7d NC |
17845 | #undef ARM_VARIANT |
17846 | #define ARM_VARIANT & arm_ext_v6k | |
17847 | #undef THUMB_VARIANT | |
17848 | #define THUMB_VARIANT & arm_ext_v6k | |
17849 | ||
21d799b5 NC |
17850 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
17851 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
17852 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
17853 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 17854 | |
c921be7d NC |
17855 | #undef THUMB_VARIANT |
17856 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
17857 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
17858 | ldrexd, t_ldrexd), | |
17859 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
17860 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 17861 | |
c921be7d NC |
17862 | #undef THUMB_VARIANT |
17863 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
17864 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
17865 | rd_rn, rd_rn), | |
17866 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
17867 | rd_rn, rd_rn), | |
17868 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 17869 | strex, t_strexbh), |
5be8be5d | 17870 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 17871 | strex, t_strexbh), |
21d799b5 | 17872 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 17873 | |
c921be7d | 17874 | #undef ARM_VARIANT |
f4c65163 MGD |
17875 | #define ARM_VARIANT & arm_ext_sec |
17876 | #undef THUMB_VARIANT | |
17877 | #define THUMB_VARIANT & arm_ext_sec | |
c921be7d | 17878 | |
21d799b5 | 17879 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 17880 | |
90ec0d68 MGD |
17881 | #undef ARM_VARIANT |
17882 | #define ARM_VARIANT & arm_ext_virt | |
17883 | #undef THUMB_VARIANT | |
17884 | #define THUMB_VARIANT & arm_ext_virt | |
17885 | ||
17886 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
17887 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
17888 | ||
c921be7d NC |
17889 | #undef ARM_VARIANT |
17890 | #define ARM_VARIANT & arm_ext_v6t2 | |
f4c65163 MGD |
17891 | #undef THUMB_VARIANT |
17892 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 17893 | |
21d799b5 NC |
17894 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
17895 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
17896 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
17897 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 17898 | |
21d799b5 NC |
17899 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
17900 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17901 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17902 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 17903 | |
5be8be5d DG |
17904 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
17905 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17906 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17907 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 17908 | |
bf3eeda7 NS |
17909 | /* Thumb-only instructions. */ |
17910 | #undef ARM_VARIANT | |
17911 | #define ARM_VARIANT NULL | |
17912 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
17913 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
17914 | |
17915 | /* ARM does not really have an IT instruction, so always allow it. | |
17916 | The opcode is copied from Thumb in order to allow warnings in | |
17917 | -mimplicit-it=[never | arm] modes. */ | |
17918 | #undef ARM_VARIANT | |
17919 | #define ARM_VARIANT & arm_ext_v1 | |
17920 | ||
21d799b5 NC |
17921 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
17922 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
17923 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
17924 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
17925 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
17926 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
17927 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
17928 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
17929 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
17930 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
17931 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
17932 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
17933 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
17934 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
17935 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 17936 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
17937 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
17938 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 17939 | |
92e90b6e | 17940 | /* Thumb2 only instructions. */ |
c921be7d NC |
17941 | #undef ARM_VARIANT |
17942 | #define ARM_VARIANT NULL | |
92e90b6e | 17943 | |
21d799b5 NC |
17944 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
17945 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
17946 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
17947 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
17948 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
17949 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 17950 | |
eea54501 MGD |
17951 | /* Hardware division instructions. */ |
17952 | #undef ARM_VARIANT | |
17953 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
17954 | #undef THUMB_VARIANT |
17955 | #define THUMB_VARIANT & arm_ext_div | |
17956 | ||
eea54501 MGD |
17957 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
17958 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 17959 | |
7e806470 | 17960 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17961 | #undef ARM_VARIANT |
17962 | #define ARM_VARIANT & arm_ext_barrier | |
17963 | #undef THUMB_VARIANT | |
17964 | #define THUMB_VARIANT & arm_ext_barrier | |
17965 | ||
52e7f43d RE |
17966 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), |
17967 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), | |
17968 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), | |
7e806470 | 17969 | |
62b3e311 | 17970 | /* ARM V7 instructions. */ |
c921be7d NC |
17971 | #undef ARM_VARIANT |
17972 | #define ARM_VARIANT & arm_ext_v7 | |
17973 | #undef THUMB_VARIANT | |
17974 | #define THUMB_VARIANT & arm_ext_v7 | |
17975 | ||
21d799b5 NC |
17976 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17977 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17978 | |
60e5ef9f MGD |
17979 | #undef ARM_VARIANT |
17980 | #define ARM_VARIANT & arm_ext_mp | |
17981 | #undef THUMB_VARIANT | |
17982 | #define THUMB_VARIANT & arm_ext_mp | |
17983 | ||
17984 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
17985 | ||
53c4b28b MGD |
17986 | /* AArchv8 instructions. */ |
17987 | #undef ARM_VARIANT | |
17988 | #define ARM_VARIANT & arm_ext_v8 | |
17989 | #undef THUMB_VARIANT | |
17990 | #define THUMB_VARIANT & arm_ext_v8 | |
17991 | ||
17992 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), | |
8884b720 | 17993 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), |
53c4b28b | 17994 | |
8884b720 | 17995 | /* ARMv8 T32 only. */ |
b79f7053 MGD |
17996 | #undef ARM_VARIANT |
17997 | #define ARM_VARIANT NULL | |
17998 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
17999 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
18000 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
18001 | ||
c921be7d NC |
18002 | #undef ARM_VARIANT |
18003 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
18004 | #undef THUMB_VARIANT |
18005 | #define THUMB_VARIANT NULL | |
c921be7d | 18006 | |
21d799b5 NC |
18007 | cCE("wfs", e200110, 1, (RR), rd), |
18008 | cCE("rfs", e300110, 1, (RR), rd), | |
18009 | cCE("wfc", e400110, 1, (RR), rd), | |
18010 | cCE("rfc", e500110, 1, (RR), rd), | |
18011 | ||
18012 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18013 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18014 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18015 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18016 | ||
18017 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18018 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18019 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18020 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
18021 | ||
18022 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
18023 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
18024 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
18025 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
18026 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
18027 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
18028 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
18029 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
18030 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
18031 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
18032 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
18033 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
18034 | ||
18035 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
18036 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
18037 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
18038 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
18039 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
18040 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
18041 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
18042 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
18043 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
18044 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
18045 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
18046 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
18047 | ||
18048 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
18049 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
18050 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
18051 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
18052 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
18053 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
18054 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
18055 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
18056 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
18057 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
18058 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
18059 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
18060 | ||
18061 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
18062 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
18063 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
18064 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
18065 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
18066 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
18067 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
18068 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
18069 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
18070 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
18071 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
18072 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
18073 | ||
18074 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
18075 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
18076 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
18077 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
18078 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
18079 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
18080 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
18081 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
18082 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
18083 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
18084 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
18085 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
18086 | ||
18087 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
18088 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
18089 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
18090 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
18091 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
18092 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
18093 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
18094 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
18095 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
18096 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
18097 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
18098 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
18099 | ||
18100 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
18101 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
18102 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
18103 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
18104 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
18105 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
18106 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
18107 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
18108 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
18109 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
18110 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
18111 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
18112 | ||
18113 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
18114 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
18115 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
18116 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
18117 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
18118 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
18119 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
18120 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
18121 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
18122 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
18123 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
18124 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
18125 | ||
18126 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
18127 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
18128 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
18129 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
18130 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
18131 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
18132 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
18133 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
18134 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
18135 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
18136 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
18137 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
18138 | ||
18139 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
18140 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
18141 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
18142 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
18143 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
18144 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
18145 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
18146 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
18147 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
18148 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
18149 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
18150 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
18151 | ||
18152 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
18153 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
18154 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
18155 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
18156 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
18157 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
18158 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
18159 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
18160 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
18161 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
18162 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
18163 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
18164 | ||
18165 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
18166 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
18167 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
18168 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
18169 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
18170 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
18171 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
18172 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
18173 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
18174 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
18175 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
18176 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
18177 | ||
18178 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
18179 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
18180 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
18181 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
18182 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
18183 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
18184 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
18185 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
18186 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
18187 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
18188 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
18189 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
18190 | ||
18191 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
18192 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
18193 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
18194 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
18195 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
18196 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
18197 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
18198 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
18199 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
18200 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
18201 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
18202 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
18203 | ||
18204 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
18205 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
18206 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
18207 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
18208 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
18209 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
18210 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
18211 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
18212 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
18213 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
18214 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
18215 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
18216 | ||
18217 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
18218 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
18219 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
18220 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
18221 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
18222 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
18223 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
18224 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
18225 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
18226 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
18227 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
18228 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
18229 | ||
18230 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18231 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18232 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18233 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18234 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18235 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18236 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18237 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18238 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18239 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18240 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18241 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18242 | ||
18243 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18244 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18245 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18246 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18247 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18248 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18249 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18250 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18251 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18252 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18253 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18254 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18255 | ||
18256 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18257 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18258 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18259 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18260 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18261 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18262 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18263 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18264 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18265 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18266 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18267 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18268 | ||
18269 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18270 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18271 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18272 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18273 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18274 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18275 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18276 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18277 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18278 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18279 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18280 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18281 | ||
18282 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18283 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18284 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18285 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18286 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18287 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18288 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18289 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18290 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18291 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18292 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18293 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18294 | ||
18295 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18296 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18297 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18298 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18299 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18300 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18301 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18302 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18303 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18304 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18305 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18306 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18307 | ||
18308 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18309 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18310 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18311 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18312 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18313 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18314 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18315 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18316 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18317 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18318 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18319 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18320 | ||
18321 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18322 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18323 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18324 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18325 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18326 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18327 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18328 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18329 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18330 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18331 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18332 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18333 | ||
18334 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18335 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18336 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18337 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18338 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18339 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18340 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18341 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18342 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18343 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18344 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18345 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18346 | ||
18347 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18348 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18349 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18350 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18351 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18352 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18353 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18354 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18355 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18356 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18357 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18358 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18359 | ||
18360 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18361 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18362 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18363 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18364 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18365 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18366 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18367 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18368 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18369 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18370 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18371 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18372 | ||
18373 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18374 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18375 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18376 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18377 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18378 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18379 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18380 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18381 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18382 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18383 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18384 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18385 | ||
18386 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18387 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18388 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18389 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18390 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18391 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18392 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18393 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18394 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18395 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18396 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18397 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18398 | ||
18399 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
18400 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
18401 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
18402 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
18403 | ||
18404 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
18405 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
18406 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
18407 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
18408 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
18409 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
18410 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
18411 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
18412 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
18413 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
18414 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
18415 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 18416 | |
c19d1205 ZW |
18417 | /* The implementation of the FIX instruction is broken on some |
18418 | assemblers, in that it accepts a precision specifier as well as a | |
18419 | rounding specifier, despite the fact that this is meaningless. | |
18420 | To be more compatible, we accept it as well, though of course it | |
18421 | does not set any bits. */ | |
21d799b5 NC |
18422 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
18423 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
18424 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
18425 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
18426 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
18427 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
18428 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
18429 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
18430 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
18431 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
18432 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
18433 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
18434 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 18435 | |
c19d1205 | 18436 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
18437 | #undef ARM_VARIANT |
18438 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
18439 | ||
21d799b5 NC |
18440 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
18441 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18442 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18443 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18444 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18445 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 18446 | |
c921be7d NC |
18447 | #undef ARM_VARIANT |
18448 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
18449 | ||
c19d1205 | 18450 | /* Moves and type conversions. */ |
21d799b5 NC |
18451 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
18452 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
18453 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
18454 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
18455 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
18456 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
18457 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18458 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18459 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18460 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18461 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18462 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18463 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
18464 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
18465 | |
18466 | /* Memory operations. */ | |
21d799b5 NC |
18467 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
18468 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
18469 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
18470 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18471 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18472 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18473 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18474 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18475 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18476 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18477 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18478 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18479 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18480 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18481 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18482 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18483 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18484 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 18485 | |
c19d1205 | 18486 | /* Monadic operations. */ |
21d799b5 NC |
18487 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18488 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18489 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
18490 | |
18491 | /* Dyadic operations. */ | |
21d799b5 NC |
18492 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
18493 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18494 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18495 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18496 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18497 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18498 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18499 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18500 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 18501 | |
c19d1205 | 18502 | /* Comparisons. */ |
21d799b5 NC |
18503 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
18504 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
18505 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18506 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 18507 | |
62f3b8c8 PB |
18508 | /* Double precision load/store are still present on single precision |
18509 | implementations. */ | |
18510 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
18511 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
18512 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
18513 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18514 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18515 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18516 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18517 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18518 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18519 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 18520 | |
c921be7d NC |
18521 | #undef ARM_VARIANT |
18522 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
18523 | ||
c19d1205 | 18524 | /* Moves and type conversions. */ |
21d799b5 NC |
18525 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18526 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18527 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18528 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18529 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18530 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18531 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18532 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18533 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18534 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18535 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18536 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18537 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 18538 | |
c19d1205 | 18539 | /* Monadic operations. */ |
21d799b5 NC |
18540 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
18541 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18542 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
18543 | |
18544 | /* Dyadic operations. */ | |
21d799b5 NC |
18545 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
18546 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18547 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18548 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18549 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18550 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18551 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18552 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18553 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 18554 | |
c19d1205 | 18555 | /* Comparisons. */ |
21d799b5 NC |
18556 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18557 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
18558 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18559 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 18560 | |
c921be7d NC |
18561 | #undef ARM_VARIANT |
18562 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
18563 | ||
21d799b5 NC |
18564 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
18565 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
18566 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
18567 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 18568 | |
037e8744 JB |
18569 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
18570 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
18571 | #undef ARM_VARIANT |
18572 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
18573 | #undef THUMB_VARIANT | |
18574 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
18575 | ||
037e8744 JB |
18576 | /* These mnemonics are unique to VFP. */ |
18577 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
18578 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
18579 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
18580 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18581 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18582 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
18583 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
18584 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
18585 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
18586 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
18587 | ||
18588 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
18589 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
18590 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
18591 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 18592 | |
21d799b5 NC |
18593 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
18594 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
18595 | |
18596 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18597 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18598 | ||
55881a11 MGD |
18599 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
18600 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18601 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18602 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18603 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18604 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
18605 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
18606 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 18607 | |
5f1af56b | 18608 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 18609 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
21d799b5 NC |
18610 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
18611 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 18612 | |
037e8744 JB |
18613 | |
18614 | /* NOTE: All VMOV encoding is special-cased! */ | |
18615 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
18616 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
18617 | ||
c921be7d NC |
18618 | #undef THUMB_VARIANT |
18619 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
18620 | #undef ARM_VARIANT | |
18621 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
18622 | ||
5287ad62 JB |
18623 | /* Data processing with three registers of the same length. */ |
18624 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
18625 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
18626 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
18627 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18628 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18629 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18630 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18631 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18632 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18633 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18634 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18635 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
18636 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18637 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
18638 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
18639 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
18640 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
18641 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
18642 | /* If not immediate, fall back to neon_dyadic_i64_su. |
18643 | shl_imm should accept I8 I16 I32 I64, | |
18644 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
18645 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
18646 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
18647 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
18648 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 18649 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
18650 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
18651 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18652 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18653 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18654 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18655 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18656 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18657 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18658 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
18659 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
18660 | /* Bitfield ops, untyped. */ |
18661 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18662 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18663 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18664 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18665 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18666 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18667 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
18668 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
18669 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18670 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18671 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18672 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18673 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
18674 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
18675 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
18676 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
18677 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18678 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
18679 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18680 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18681 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
18682 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18683 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 18684 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
18685 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
18686 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 18687 | /* As above, D registers only. */ |
21d799b5 NC |
18688 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
18689 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 18690 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
18691 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
18692 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
18693 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 18694 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
18695 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
18696 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
18697 | /* vtst takes sizes 8, 16, 32. */ |
18698 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
18699 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
18700 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 18701 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 18702 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
18703 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
18704 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
18705 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
18706 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
18707 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
18708 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
18709 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
18710 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
18711 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
18712 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
18713 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
18714 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
18715 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
18716 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18717 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
18718 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18719 | ||
18720 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 18721 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
18722 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
18723 | ||
18724 | /* Data processing with two registers and a shift amount. */ | |
18725 | /* Right shifts, and variants with rounding. | |
18726 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18727 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18728 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18729 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18730 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18731 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18732 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18733 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18734 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18735 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
18736 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
18737 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
18738 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
18739 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
18740 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18741 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
18742 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
18743 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
18744 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
18745 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18746 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18747 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
18748 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18749 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18750 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
18751 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18752 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18753 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 18754 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 18755 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 18756 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 18757 | |
4316f0d2 DG |
18758 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
18759 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
18760 | |
18761 | /* Data processing, three registers of different lengths. */ | |
18762 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
18763 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
18764 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18765 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18766 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18767 | /* If not scalar, fall back to neon_dyadic_long. | |
18768 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
18769 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
18770 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
18771 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
18772 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18773 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18774 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
18775 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18776 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18777 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18778 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18779 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
18780 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
18781 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
18782 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
18783 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
18784 | S16 S32 U16 U32. */ | |
21d799b5 | 18785 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
18786 | |
18787 | /* Extract. Size 8. */ | |
3b8d421e PB |
18788 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
18789 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
18790 | |
18791 | /* Two registers, miscellaneous. */ | |
18792 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
18793 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
18794 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
18795 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
18796 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
18797 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
18798 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
18799 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
18800 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
18801 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
18802 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
18803 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
18804 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 18805 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 18806 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 18807 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 18808 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 18809 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
18810 | /* VZIP / VUZP. Sizes 8 16 32. */ |
18811 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18812 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
18813 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18814 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
18815 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
18816 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18817 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18818 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18819 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18820 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
18821 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
18822 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
18823 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
18824 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
18825 | /* Reciprocal estimates. Types U32 F32. */ | |
18826 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
18827 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
18828 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
18829 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
18830 | /* VCLS. Types S8 S16 S32. */ | |
18831 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
18832 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
18833 | /* VCLZ. Types I8 I16 I32. */ | |
18834 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
18835 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
18836 | /* VCNT. Size 8. */ | |
18837 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
18838 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
18839 | /* Two address, untyped. */ | |
18840 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
18841 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
18842 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
18843 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
18844 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
18845 | |
18846 | /* Table lookup. Size 8. */ | |
18847 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18848 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18849 | ||
c921be7d NC |
18850 | #undef THUMB_VARIANT |
18851 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
18852 | #undef ARM_VARIANT | |
18853 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
18854 | ||
5287ad62 | 18855 | /* Neon element/structure load/store. */ |
21d799b5 NC |
18856 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
18857 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18858 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18859 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18860 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18861 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18862 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18863 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 18864 | |
c921be7d | 18865 | #undef THUMB_VARIANT |
62f3b8c8 PB |
18866 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
18867 | #undef ARM_VARIANT | |
18868 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
18869 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
18870 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18871 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18872 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18873 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18874 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18875 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18876 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18877 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18878 | ||
18879 | #undef THUMB_VARIANT | |
c921be7d NC |
18880 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
18881 | #undef ARM_VARIANT | |
18882 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
18883 | ||
21d799b5 | 18884 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 18885 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18886 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18887 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18888 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18889 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18890 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18891 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18892 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 18893 | |
62f3b8c8 PB |
18894 | #undef ARM_VARIANT |
18895 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
18896 | #undef THUMB_VARIANT | |
18897 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
18898 | /* Mnemonics shared by Neon and VFP. These are included in the | |
18899 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
18900 | FMA instructions. */ | |
18901 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18902 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18903 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
18904 | the v form should always be used. */ | |
18905 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18906 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18907 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18908 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18909 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18910 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18911 | ||
5287ad62 | 18912 | #undef THUMB_VARIANT |
c921be7d NC |
18913 | #undef ARM_VARIANT |
18914 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
18915 | ||
21d799b5 NC |
18916 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
18917 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18918 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18919 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18920 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18921 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18922 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
18923 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 18924 | |
c921be7d NC |
18925 | #undef ARM_VARIANT |
18926 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
18927 | ||
21d799b5 NC |
18928 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
18929 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
18930 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
18931 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
18932 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
18933 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
18934 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
18935 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
18936 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
18937 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18938 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18939 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18940 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18941 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18942 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18943 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18944 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18945 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18946 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
18947 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
18948 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18949 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18950 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18951 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18952 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18953 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18954 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
18955 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
18956 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
18957 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
18958 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
18959 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
18960 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
18961 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
18962 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
18963 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
18964 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
18965 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18966 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18967 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18968 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18969 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18970 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18971 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18972 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18973 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18974 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
18975 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18976 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18977 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18978 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18979 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18980 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18981 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18982 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18983 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18984 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18985 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18986 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18987 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18988 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18989 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18990 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18991 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18992 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18993 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18994 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18995 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18996 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18997 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18998 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18999 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19000 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19001 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19002 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19003 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19004 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19005 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19006 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19007 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19008 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19009 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19010 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19011 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19012 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19013 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19014 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19015 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19016 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
19017 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19018 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19019 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19020 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19021 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19022 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19023 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19024 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19025 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19026 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19027 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19028 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19029 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19030 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19031 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19032 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19033 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19034 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19035 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19036 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19037 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19038 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
19039 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19040 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19041 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19042 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19043 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19044 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19045 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19046 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19047 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19048 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19049 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19050 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19051 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19052 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19053 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19054 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19055 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
19056 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
19057 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
19058 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
19059 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
19060 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
19061 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19062 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19063 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19064 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19065 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19066 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19067 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19068 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19069 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19070 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
19071 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
19072 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
19073 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
19074 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
19075 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
19076 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19077 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19078 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19079 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
19080 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
19081 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
19082 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
19083 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
19084 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
19085 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19086 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19087 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19088 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19089 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 19090 | |
c921be7d NC |
19091 | #undef ARM_VARIANT |
19092 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
19093 | ||
21d799b5 NC |
19094 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
19095 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
19096 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
19097 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
19098 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
19099 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
19100 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19101 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19102 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19103 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19104 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19105 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19106 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19107 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19108 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19109 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19110 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19111 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19112 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19113 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19114 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
19115 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19116 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19117 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19118 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19119 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19120 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19121 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19122 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19123 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19124 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19125 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19126 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19127 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19128 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19129 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19130 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19131 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19132 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19133 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19134 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19135 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19136 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19137 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19138 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19139 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19140 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19141 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19142 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19143 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19144 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19145 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19146 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19147 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19148 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19149 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19150 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 19151 | |
c921be7d NC |
19152 | #undef ARM_VARIANT |
19153 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
19154 | ||
21d799b5 NC |
19155 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
19156 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
19157 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
19158 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
19159 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
19160 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
19161 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
19162 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
19163 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
19164 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
19165 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
19166 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
19167 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
19168 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
19169 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
19170 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
19171 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
19172 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
19173 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
19174 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
19175 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
19176 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
19177 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
19178 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
19179 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
19180 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
19181 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
19182 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
19183 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
19184 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
19185 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
19186 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
19187 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
19188 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
19189 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
19190 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
19191 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
19192 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
19193 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
19194 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
19195 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
19196 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
19197 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
19198 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
19199 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
19200 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
19201 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
19202 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
19203 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
19204 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
19205 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
19206 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
19207 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
19208 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
19209 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
19210 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
19211 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
19212 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
19213 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
19214 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
19215 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
19216 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
19217 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
19218 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
19219 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19220 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
19221 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19222 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
19223 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19224 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
19225 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19226 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19227 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
19228 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
19229 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
19230 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
19231 | }; |
19232 | #undef ARM_VARIANT | |
19233 | #undef THUMB_VARIANT | |
19234 | #undef TCE | |
19235 | #undef TCM | |
19236 | #undef TUE | |
19237 | #undef TUF | |
19238 | #undef TCC | |
8f06b2d8 | 19239 | #undef cCE |
e3cb604e PB |
19240 | #undef cCL |
19241 | #undef C3E | |
c19d1205 ZW |
19242 | #undef CE |
19243 | #undef CM | |
19244 | #undef UE | |
19245 | #undef UF | |
19246 | #undef UT | |
5287ad62 JB |
19247 | #undef NUF |
19248 | #undef nUF | |
19249 | #undef NCE | |
19250 | #undef nCE | |
c19d1205 ZW |
19251 | #undef OPS0 |
19252 | #undef OPS1 | |
19253 | #undef OPS2 | |
19254 | #undef OPS3 | |
19255 | #undef OPS4 | |
19256 | #undef OPS5 | |
19257 | #undef OPS6 | |
19258 | #undef do_0 | |
19259 | \f | |
19260 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 19261 | |
c19d1205 ZW |
19262 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
19263 | for use in the a.out file, and stores them in the array pointed to by buf. | |
19264 | This knows about the endian-ness of the target machine and does | |
19265 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
19266 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
19267 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 19268 | |
c19d1205 ZW |
19269 | void |
19270 | md_number_to_chars (char * buf, valueT val, int n) | |
19271 | { | |
19272 | if (target_big_endian) | |
19273 | number_to_chars_bigendian (buf, val, n); | |
19274 | else | |
19275 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
19276 | } |
19277 | ||
c19d1205 ZW |
19278 | static valueT |
19279 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 19280 | { |
c19d1205 ZW |
19281 | valueT result = 0; |
19282 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 19283 | |
c19d1205 | 19284 | if (target_big_endian) |
b99bd4ef | 19285 | { |
c19d1205 ZW |
19286 | while (n--) |
19287 | { | |
19288 | result <<= 8; | |
19289 | result |= (*where++ & 255); | |
19290 | } | |
b99bd4ef | 19291 | } |
c19d1205 | 19292 | else |
b99bd4ef | 19293 | { |
c19d1205 ZW |
19294 | while (n--) |
19295 | { | |
19296 | result <<= 8; | |
19297 | result |= (where[n] & 255); | |
19298 | } | |
bfae80f2 | 19299 | } |
b99bd4ef | 19300 | |
c19d1205 | 19301 | return result; |
bfae80f2 | 19302 | } |
b99bd4ef | 19303 | |
c19d1205 | 19304 | /* MD interface: Sections. */ |
b99bd4ef | 19305 | |
fa94de6b RM |
19306 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
19307 | that an rs_machine_dependent frag may reach. */ | |
19308 | ||
19309 | unsigned int | |
19310 | arm_frag_max_var (fragS *fragp) | |
19311 | { | |
19312 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
19313 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
19314 | ||
19315 | Note that we generate relaxable instructions even for cases that don't | |
19316 | really need it, like an immediate that's a trivial constant. So we're | |
19317 | overestimating the instruction size for some of those cases. Rather | |
19318 | than putting more intelligence here, it would probably be better to | |
19319 | avoid generating a relaxation frag in the first place when it can be | |
19320 | determined up front that a short instruction will suffice. */ | |
19321 | ||
19322 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
19323 | return INSN_SIZE; | |
19324 | } | |
19325 | ||
0110f2b8 PB |
19326 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
19327 | 2 bytes. */ | |
19328 | ||
c19d1205 | 19329 | int |
0110f2b8 | 19330 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
19331 | segT segtype ATTRIBUTE_UNUSED) |
19332 | { | |
0110f2b8 PB |
19333 | fragp->fr_var = 2; |
19334 | return 2; | |
19335 | } | |
19336 | ||
19337 | /* Convert a machine dependent frag. */ | |
19338 | ||
19339 | void | |
19340 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
19341 | { | |
19342 | unsigned long insn; | |
19343 | unsigned long old_op; | |
19344 | char *buf; | |
19345 | expressionS exp; | |
19346 | fixS *fixp; | |
19347 | int reloc_type; | |
19348 | int pc_rel; | |
19349 | int opcode; | |
19350 | ||
19351 | buf = fragp->fr_literal + fragp->fr_fix; | |
19352 | ||
19353 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
19354 | if (fragp->fr_symbol) |
19355 | { | |
0110f2b8 PB |
19356 | exp.X_op = O_symbol; |
19357 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
19358 | } |
19359 | else | |
19360 | { | |
0110f2b8 | 19361 | exp.X_op = O_constant; |
5f4273c7 | 19362 | } |
0110f2b8 PB |
19363 | exp.X_add_number = fragp->fr_offset; |
19364 | opcode = fragp->fr_subtype; | |
19365 | switch (opcode) | |
19366 | { | |
19367 | case T_MNEM_ldr_pc: | |
19368 | case T_MNEM_ldr_pc2: | |
19369 | case T_MNEM_ldr_sp: | |
19370 | case T_MNEM_str_sp: | |
19371 | case T_MNEM_ldr: | |
19372 | case T_MNEM_ldrb: | |
19373 | case T_MNEM_ldrh: | |
19374 | case T_MNEM_str: | |
19375 | case T_MNEM_strb: | |
19376 | case T_MNEM_strh: | |
19377 | if (fragp->fr_var == 4) | |
19378 | { | |
5f4273c7 | 19379 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
19380 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
19381 | { | |
19382 | insn |= (old_op & 0x700) << 4; | |
19383 | } | |
19384 | else | |
19385 | { | |
19386 | insn |= (old_op & 7) << 12; | |
19387 | insn |= (old_op & 0x38) << 13; | |
19388 | } | |
19389 | insn |= 0x00000c00; | |
19390 | put_thumb32_insn (buf, insn); | |
19391 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
19392 | } | |
19393 | else | |
19394 | { | |
19395 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
19396 | } | |
19397 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
19398 | break; | |
19399 | case T_MNEM_adr: | |
19400 | if (fragp->fr_var == 4) | |
19401 | { | |
19402 | insn = THUMB_OP32 (opcode); | |
19403 | insn |= (old_op & 0xf0) << 4; | |
19404 | put_thumb32_insn (buf, insn); | |
19405 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
19406 | } | |
19407 | else | |
19408 | { | |
19409 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19410 | exp.X_add_number -= 4; | |
19411 | } | |
19412 | pc_rel = 1; | |
19413 | break; | |
19414 | case T_MNEM_mov: | |
19415 | case T_MNEM_movs: | |
19416 | case T_MNEM_cmp: | |
19417 | case T_MNEM_cmn: | |
19418 | if (fragp->fr_var == 4) | |
19419 | { | |
19420 | int r0off = (opcode == T_MNEM_mov | |
19421 | || opcode == T_MNEM_movs) ? 0 : 8; | |
19422 | insn = THUMB_OP32 (opcode); | |
19423 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
19424 | insn |= (old_op & 0x700) << r0off; | |
19425 | put_thumb32_insn (buf, insn); | |
19426 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
19427 | } | |
19428 | else | |
19429 | { | |
19430 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
19431 | } | |
19432 | pc_rel = 0; | |
19433 | break; | |
19434 | case T_MNEM_b: | |
19435 | if (fragp->fr_var == 4) | |
19436 | { | |
19437 | insn = THUMB_OP32(opcode); | |
19438 | put_thumb32_insn (buf, insn); | |
19439 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
19440 | } | |
19441 | else | |
19442 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
19443 | pc_rel = 1; | |
19444 | break; | |
19445 | case T_MNEM_bcond: | |
19446 | if (fragp->fr_var == 4) | |
19447 | { | |
19448 | insn = THUMB_OP32(opcode); | |
19449 | insn |= (old_op & 0xf00) << 14; | |
19450 | put_thumb32_insn (buf, insn); | |
19451 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
19452 | } | |
19453 | else | |
19454 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
19455 | pc_rel = 1; | |
19456 | break; | |
19457 | case T_MNEM_add_sp: | |
19458 | case T_MNEM_add_pc: | |
19459 | case T_MNEM_inc_sp: | |
19460 | case T_MNEM_dec_sp: | |
19461 | if (fragp->fr_var == 4) | |
19462 | { | |
19463 | /* ??? Choose between add and addw. */ | |
19464 | insn = THUMB_OP32 (opcode); | |
19465 | insn |= (old_op & 0xf0) << 4; | |
19466 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19467 | if (opcode == T_MNEM_add_pc) |
19468 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
19469 | else | |
19470 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
19471 | } |
19472 | else | |
19473 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19474 | pc_rel = 0; | |
19475 | break; | |
19476 | ||
19477 | case T_MNEM_addi: | |
19478 | case T_MNEM_addis: | |
19479 | case T_MNEM_subi: | |
19480 | case T_MNEM_subis: | |
19481 | if (fragp->fr_var == 4) | |
19482 | { | |
19483 | insn = THUMB_OP32 (opcode); | |
19484 | insn |= (old_op & 0xf0) << 4; | |
19485 | insn |= (old_op & 0xf) << 16; | |
19486 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19487 | if (insn & (1 << 20)) |
19488 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
19489 | else | |
19490 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
19491 | } |
19492 | else | |
19493 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19494 | pc_rel = 0; | |
19495 | break; | |
19496 | default: | |
5f4273c7 | 19497 | abort (); |
0110f2b8 PB |
19498 | } |
19499 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 19500 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
19501 | fixp->fx_file = fragp->fr_file; |
19502 | fixp->fx_line = fragp->fr_line; | |
19503 | fragp->fr_fix += fragp->fr_var; | |
19504 | } | |
19505 | ||
19506 | /* Return the size of a relaxable immediate operand instruction. | |
19507 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
19508 | static int | |
19509 | relax_immediate (fragS *fragp, int size, int shift) | |
19510 | { | |
19511 | offsetT offset; | |
19512 | offsetT mask; | |
19513 | offsetT low; | |
19514 | ||
19515 | /* ??? Should be able to do better than this. */ | |
19516 | if (fragp->fr_symbol) | |
19517 | return 4; | |
19518 | ||
19519 | low = (1 << shift) - 1; | |
19520 | mask = (1 << (shift + size)) - (1 << shift); | |
19521 | offset = fragp->fr_offset; | |
19522 | /* Force misaligned offsets to 32-bit variant. */ | |
19523 | if (offset & low) | |
5e77afaa | 19524 | return 4; |
0110f2b8 PB |
19525 | if (offset & ~mask) |
19526 | return 4; | |
19527 | return 2; | |
19528 | } | |
19529 | ||
5e77afaa PB |
19530 | /* Get the address of a symbol during relaxation. */ |
19531 | static addressT | |
5f4273c7 | 19532 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
19533 | { |
19534 | fragS *sym_frag; | |
19535 | addressT addr; | |
19536 | symbolS *sym; | |
19537 | ||
19538 | sym = fragp->fr_symbol; | |
19539 | sym_frag = symbol_get_frag (sym); | |
19540 | know (S_GET_SEGMENT (sym) != absolute_section | |
19541 | || sym_frag == &zero_address_frag); | |
19542 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
19543 | ||
19544 | /* If frag has yet to be reached on this pass, assume it will | |
19545 | move by STRETCH just as we did. If this is not so, it will | |
19546 | be because some frag between grows, and that will force | |
19547 | another pass. */ | |
19548 | ||
19549 | if (stretch != 0 | |
19550 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
19551 | { |
19552 | fragS *f; | |
19553 | ||
19554 | /* Adjust stretch for any alignment frag. Note that if have | |
19555 | been expanding the earlier code, the symbol may be | |
19556 | defined in what appears to be an earlier frag. FIXME: | |
19557 | This doesn't handle the fr_subtype field, which specifies | |
19558 | a maximum number of bytes to skip when doing an | |
19559 | alignment. */ | |
19560 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
19561 | { | |
19562 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
19563 | { | |
19564 | if (stretch < 0) | |
19565 | stretch = - ((- stretch) | |
19566 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
19567 | else | |
19568 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
19569 | if (stretch == 0) | |
19570 | break; | |
19571 | } | |
19572 | } | |
19573 | if (f != NULL) | |
19574 | addr += stretch; | |
19575 | } | |
5e77afaa PB |
19576 | |
19577 | return addr; | |
19578 | } | |
19579 | ||
0110f2b8 PB |
19580 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
19581 | load. */ | |
19582 | static int | |
5e77afaa | 19583 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
19584 | { |
19585 | addressT addr; | |
19586 | offsetT val; | |
19587 | ||
19588 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
19589 | if (fragp->fr_symbol == NULL |
19590 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
19591 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19592 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19593 | return 4; |
19594 | ||
5f4273c7 | 19595 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19596 | addr = fragp->fr_address + fragp->fr_fix; |
19597 | addr = (addr + 4) & ~3; | |
5e77afaa | 19598 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 19599 | if (val & 3) |
5e77afaa | 19600 | return 4; |
0110f2b8 PB |
19601 | val -= addr; |
19602 | if (val < 0 || val > 1020) | |
19603 | return 4; | |
19604 | return 2; | |
19605 | } | |
19606 | ||
19607 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
19608 | static int | |
19609 | relax_addsub (fragS *fragp, asection *sec) | |
19610 | { | |
19611 | char *buf; | |
19612 | int op; | |
19613 | ||
19614 | buf = fragp->fr_literal + fragp->fr_fix; | |
19615 | op = bfd_get_16(sec->owner, buf); | |
19616 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
19617 | return relax_immediate (fragp, 8, 0); | |
19618 | else | |
19619 | return relax_immediate (fragp, 3, 0); | |
19620 | } | |
19621 | ||
19622 | ||
19623 | /* Return the size of a relaxable branch instruction. BITS is the | |
19624 | size of the offset field in the narrow instruction. */ | |
19625 | ||
19626 | static int | |
5e77afaa | 19627 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
19628 | { |
19629 | addressT addr; | |
19630 | offsetT val; | |
19631 | offsetT limit; | |
19632 | ||
19633 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 19634 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
19635 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19636 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19637 | return 4; |
19638 | ||
267bf995 RR |
19639 | #ifdef OBJ_ELF |
19640 | if (S_IS_DEFINED (fragp->fr_symbol) | |
19641 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
19642 | return 4; | |
0d9b4b55 NC |
19643 | |
19644 | /* PR 12532. Global symbols with default visibility might | |
19645 | be preempted, so do not relax relocations to them. */ | |
19646 | if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT) | |
19647 | && (! S_IS_LOCAL (fragp->fr_symbol))) | |
19648 | return 4; | |
267bf995 RR |
19649 | #endif |
19650 | ||
5f4273c7 | 19651 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19652 | addr = fragp->fr_address + fragp->fr_fix + 4; |
19653 | val -= addr; | |
19654 | ||
19655 | /* Offset is a signed value *2 */ | |
19656 | limit = 1 << bits; | |
19657 | if (val >= limit || val < -limit) | |
19658 | return 4; | |
19659 | return 2; | |
19660 | } | |
19661 | ||
19662 | ||
19663 | /* Relax a machine dependent frag. This returns the amount by which | |
19664 | the current size of the frag should change. */ | |
19665 | ||
19666 | int | |
5e77afaa | 19667 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
19668 | { |
19669 | int oldsize; | |
19670 | int newsize; | |
19671 | ||
19672 | oldsize = fragp->fr_var; | |
19673 | switch (fragp->fr_subtype) | |
19674 | { | |
19675 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 19676 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19677 | break; |
19678 | case T_MNEM_ldr_pc: | |
19679 | case T_MNEM_ldr_sp: | |
19680 | case T_MNEM_str_sp: | |
5f4273c7 | 19681 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
19682 | break; |
19683 | case T_MNEM_ldr: | |
19684 | case T_MNEM_str: | |
5f4273c7 | 19685 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
19686 | break; |
19687 | case T_MNEM_ldrh: | |
19688 | case T_MNEM_strh: | |
5f4273c7 | 19689 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
19690 | break; |
19691 | case T_MNEM_ldrb: | |
19692 | case T_MNEM_strb: | |
5f4273c7 | 19693 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
19694 | break; |
19695 | case T_MNEM_adr: | |
5f4273c7 | 19696 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19697 | break; |
19698 | case T_MNEM_mov: | |
19699 | case T_MNEM_movs: | |
19700 | case T_MNEM_cmp: | |
19701 | case T_MNEM_cmn: | |
5f4273c7 | 19702 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
19703 | break; |
19704 | case T_MNEM_b: | |
5f4273c7 | 19705 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
19706 | break; |
19707 | case T_MNEM_bcond: | |
5f4273c7 | 19708 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
19709 | break; |
19710 | case T_MNEM_add_sp: | |
19711 | case T_MNEM_add_pc: | |
19712 | newsize = relax_immediate (fragp, 8, 2); | |
19713 | break; | |
19714 | case T_MNEM_inc_sp: | |
19715 | case T_MNEM_dec_sp: | |
19716 | newsize = relax_immediate (fragp, 7, 2); | |
19717 | break; | |
19718 | case T_MNEM_addi: | |
19719 | case T_MNEM_addis: | |
19720 | case T_MNEM_subi: | |
19721 | case T_MNEM_subis: | |
19722 | newsize = relax_addsub (fragp, sec); | |
19723 | break; | |
19724 | default: | |
5f4273c7 | 19725 | abort (); |
0110f2b8 | 19726 | } |
5e77afaa PB |
19727 | |
19728 | fragp->fr_var = newsize; | |
19729 | /* Freeze wide instructions that are at or before the same location as | |
19730 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
19731 | Don't freeze them unconditionally because targets may be artificially |
19732 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 19733 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 19734 | { |
0110f2b8 | 19735 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 19736 | frag_wane (fragp); |
0110f2b8 | 19737 | } |
5e77afaa | 19738 | |
0110f2b8 | 19739 | return newsize - oldsize; |
c19d1205 | 19740 | } |
b99bd4ef | 19741 | |
c19d1205 | 19742 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 19743 | |
c19d1205 ZW |
19744 | valueT |
19745 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
19746 | valueT size) | |
19747 | { | |
f0927246 NC |
19748 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
19749 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
19750 | { | |
19751 | /* For a.out, force the section size to be aligned. If we don't do | |
19752 | this, BFD will align it for us, but it will not write out the | |
19753 | final bytes of the section. This may be a bug in BFD, but it is | |
19754 | easier to fix it here since that is how the other a.out targets | |
19755 | work. */ | |
19756 | int align; | |
19757 | ||
19758 | align = bfd_get_section_alignment (stdoutput, segment); | |
19759 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
19760 | } | |
c19d1205 | 19761 | #endif |
f0927246 NC |
19762 | |
19763 | return size; | |
bfae80f2 | 19764 | } |
b99bd4ef | 19765 | |
c19d1205 ZW |
19766 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
19767 | of an rs_align_code fragment. */ | |
19768 | ||
19769 | void | |
19770 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 19771 | { |
e7495e45 NS |
19772 | static char const arm_noop[2][2][4] = |
19773 | { | |
19774 | { /* ARMv1 */ | |
19775 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
19776 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
19777 | }, | |
19778 | { /* ARMv6k */ | |
19779 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
19780 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
19781 | }, | |
19782 | }; | |
19783 | static char const thumb_noop[2][2][2] = | |
19784 | { | |
19785 | { /* Thumb-1 */ | |
19786 | {0xc0, 0x46}, /* LE */ | |
19787 | {0x46, 0xc0}, /* BE */ | |
19788 | }, | |
19789 | { /* Thumb-2 */ | |
19790 | {0x00, 0xbf}, /* LE */ | |
19791 | {0xbf, 0x00} /* BE */ | |
19792 | } | |
19793 | }; | |
19794 | static char const wide_thumb_noop[2][4] = | |
19795 | { /* Wide Thumb-2 */ | |
19796 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
19797 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
19798 | }; | |
c921be7d | 19799 | |
e7495e45 | 19800 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
19801 | char * p; |
19802 | const char * noop; | |
e7495e45 | 19803 | const char *narrow_noop = NULL; |
cd000bff DJ |
19804 | #ifdef OBJ_ELF |
19805 | enum mstate state; | |
19806 | #endif | |
bfae80f2 | 19807 | |
c19d1205 | 19808 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
19809 | return; |
19810 | ||
c19d1205 ZW |
19811 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
19812 | p = fragP->fr_literal + fragP->fr_fix; | |
19813 | fix = 0; | |
bfae80f2 | 19814 | |
c19d1205 ZW |
19815 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
19816 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 19817 | |
cd000bff | 19818 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 19819 | |
cd000bff | 19820 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 19821 | { |
e7495e45 NS |
19822 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
19823 | { | |
19824 | narrow_noop = thumb_noop[1][target_big_endian]; | |
19825 | noop = wide_thumb_noop[target_big_endian]; | |
19826 | } | |
c19d1205 | 19827 | else |
e7495e45 NS |
19828 | noop = thumb_noop[0][target_big_endian]; |
19829 | noop_size = 2; | |
cd000bff DJ |
19830 | #ifdef OBJ_ELF |
19831 | state = MAP_THUMB; | |
19832 | #endif | |
7ed4c4c5 NC |
19833 | } |
19834 | else | |
19835 | { | |
e7495e45 NS |
19836 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
19837 | [target_big_endian]; | |
19838 | noop_size = 4; | |
cd000bff DJ |
19839 | #ifdef OBJ_ELF |
19840 | state = MAP_ARM; | |
19841 | #endif | |
7ed4c4c5 | 19842 | } |
c921be7d | 19843 | |
e7495e45 | 19844 | fragP->fr_var = noop_size; |
c921be7d | 19845 | |
c19d1205 | 19846 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 19847 | { |
c19d1205 | 19848 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
19849 | #ifdef OBJ_ELF |
19850 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
19851 | #endif | |
c19d1205 ZW |
19852 | memset (p, 0, fix); |
19853 | p += fix; | |
19854 | bytes -= fix; | |
a737bd4d | 19855 | } |
a737bd4d | 19856 | |
e7495e45 NS |
19857 | if (narrow_noop) |
19858 | { | |
19859 | if (bytes & noop_size) | |
19860 | { | |
19861 | /* Insert a narrow noop. */ | |
19862 | memcpy (p, narrow_noop, noop_size); | |
19863 | p += noop_size; | |
19864 | bytes -= noop_size; | |
19865 | fix += noop_size; | |
19866 | } | |
19867 | ||
19868 | /* Use wide noops for the remainder */ | |
19869 | noop_size = 4; | |
19870 | } | |
19871 | ||
c19d1205 | 19872 | while (bytes >= noop_size) |
a737bd4d | 19873 | { |
c19d1205 ZW |
19874 | memcpy (p, noop, noop_size); |
19875 | p += noop_size; | |
19876 | bytes -= noop_size; | |
19877 | fix += noop_size; | |
a737bd4d NC |
19878 | } |
19879 | ||
c19d1205 | 19880 | fragP->fr_fix += fix; |
a737bd4d NC |
19881 | } |
19882 | ||
c19d1205 ZW |
19883 | /* Called from md_do_align. Used to create an alignment |
19884 | frag in a code section. */ | |
19885 | ||
19886 | void | |
19887 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 19888 | { |
c19d1205 | 19889 | char * p; |
7ed4c4c5 | 19890 | |
c19d1205 | 19891 | /* We assume that there will never be a requirement |
6ec8e702 | 19892 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 19893 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
19894 | { |
19895 | char err_msg[128]; | |
19896 | ||
fa94de6b | 19897 | sprintf (err_msg, |
6ec8e702 NC |
19898 | _("alignments greater than %d bytes not supported in .text sections."), |
19899 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 19900 | as_fatal ("%s", err_msg); |
6ec8e702 | 19901 | } |
bfae80f2 | 19902 | |
c19d1205 ZW |
19903 | p = frag_var (rs_align_code, |
19904 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
19905 | 1, | |
19906 | (relax_substateT) max, | |
19907 | (symbolS *) NULL, | |
19908 | (offsetT) n, | |
19909 | (char *) NULL); | |
19910 | *p = 0; | |
19911 | } | |
bfae80f2 | 19912 | |
8dc2430f NC |
19913 | /* Perform target specific initialisation of a frag. |
19914 | Note - despite the name this initialisation is not done when the frag | |
19915 | is created, but only when its type is assigned. A frag can be created | |
19916 | and used a long time before its type is set, so beware of assuming that | |
19917 | this initialisationis performed first. */ | |
bfae80f2 | 19918 | |
cd000bff DJ |
19919 | #ifndef OBJ_ELF |
19920 | void | |
19921 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
19922 | { | |
19923 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 19924 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
19925 | } |
19926 | ||
19927 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 19928 | void |
cd000bff | 19929 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 19930 | { |
8dc2430f NC |
19931 | /* If the current ARM vs THUMB mode has not already |
19932 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
19933 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
19934 | { | |
19935 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
19936 | ||
19937 | /* Record a mapping symbol for alignment frags. We will delete this | |
19938 | later if the alignment ends up empty. */ | |
19939 | switch (fragP->fr_type) | |
19940 | { | |
19941 | case rs_align: | |
19942 | case rs_align_test: | |
19943 | case rs_fill: | |
19944 | mapping_state_2 (MAP_DATA, max_chars); | |
19945 | break; | |
19946 | case rs_align_code: | |
19947 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
19948 | break; | |
19949 | default: | |
19950 | break; | |
19951 | } | |
19952 | } | |
bfae80f2 RE |
19953 | } |
19954 | ||
c19d1205 ZW |
19955 | /* When we change sections we need to issue a new mapping symbol. */ |
19956 | ||
19957 | void | |
19958 | arm_elf_change_section (void) | |
bfae80f2 | 19959 | { |
c19d1205 ZW |
19960 | /* Link an unlinked unwind index table section to the .text section. */ |
19961 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
19962 | && elf_linked_to_section (now_seg) == NULL) | |
19963 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
19964 | } |
19965 | ||
c19d1205 ZW |
19966 | int |
19967 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 19968 | { |
c19d1205 ZW |
19969 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
19970 | return SHT_ARM_EXIDX; | |
e45d0630 | 19971 | |
c19d1205 ZW |
19972 | return -1; |
19973 | } | |
19974 | \f | |
19975 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 19976 | |
c19d1205 | 19977 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 19978 | |
5f4273c7 | 19979 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 19980 | |
bfae80f2 | 19981 | static void |
c19d1205 | 19982 | flush_pending_unwind (void) |
bfae80f2 | 19983 | { |
c19d1205 | 19984 | offsetT offset; |
bfae80f2 | 19985 | |
c19d1205 ZW |
19986 | offset = unwind.pending_offset; |
19987 | unwind.pending_offset = 0; | |
19988 | if (offset != 0) | |
19989 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
19990 | } |
19991 | ||
c19d1205 ZW |
19992 | /* Add an opcode to this list for this function. Two-byte opcodes should |
19993 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
19994 | order. */ | |
19995 | ||
bfae80f2 | 19996 | static void |
c19d1205 | 19997 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 19998 | { |
c19d1205 ZW |
19999 | /* Add any deferred stack adjustment. */ |
20000 | if (unwind.pending_offset) | |
20001 | flush_pending_unwind (); | |
bfae80f2 | 20002 | |
c19d1205 | 20003 | unwind.sp_restored = 0; |
bfae80f2 | 20004 | |
c19d1205 | 20005 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 20006 | { |
c19d1205 ZW |
20007 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
20008 | if (unwind.opcodes) | |
21d799b5 NC |
20009 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
20010 | unwind.opcode_alloc); | |
c19d1205 | 20011 | else |
21d799b5 | 20012 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 20013 | } |
c19d1205 | 20014 | while (length > 0) |
bfae80f2 | 20015 | { |
c19d1205 ZW |
20016 | length--; |
20017 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
20018 | op >>= 8; | |
20019 | unwind.opcode_count++; | |
bfae80f2 | 20020 | } |
bfae80f2 RE |
20021 | } |
20022 | ||
c19d1205 ZW |
20023 | /* Add unwind opcodes to adjust the stack pointer. */ |
20024 | ||
bfae80f2 | 20025 | static void |
c19d1205 | 20026 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 20027 | { |
c19d1205 | 20028 | valueT op; |
bfae80f2 | 20029 | |
c19d1205 | 20030 | if (offset > 0x200) |
bfae80f2 | 20031 | { |
c19d1205 ZW |
20032 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
20033 | char bytes[5]; | |
20034 | int n; | |
20035 | valueT o; | |
bfae80f2 | 20036 | |
c19d1205 ZW |
20037 | /* Long form: 0xb2, uleb128. */ |
20038 | /* This might not fit in a word so add the individual bytes, | |
20039 | remembering the list is built in reverse order. */ | |
20040 | o = (valueT) ((offset - 0x204) >> 2); | |
20041 | if (o == 0) | |
20042 | add_unwind_opcode (0, 1); | |
bfae80f2 | 20043 | |
c19d1205 ZW |
20044 | /* Calculate the uleb128 encoding of the offset. */ |
20045 | n = 0; | |
20046 | while (o) | |
20047 | { | |
20048 | bytes[n] = o & 0x7f; | |
20049 | o >>= 7; | |
20050 | if (o) | |
20051 | bytes[n] |= 0x80; | |
20052 | n++; | |
20053 | } | |
20054 | /* Add the insn. */ | |
20055 | for (; n; n--) | |
20056 | add_unwind_opcode (bytes[n - 1], 1); | |
20057 | add_unwind_opcode (0xb2, 1); | |
20058 | } | |
20059 | else if (offset > 0x100) | |
bfae80f2 | 20060 | { |
c19d1205 ZW |
20061 | /* Two short opcodes. */ |
20062 | add_unwind_opcode (0x3f, 1); | |
20063 | op = (offset - 0x104) >> 2; | |
20064 | add_unwind_opcode (op, 1); | |
bfae80f2 | 20065 | } |
c19d1205 ZW |
20066 | else if (offset > 0) |
20067 | { | |
20068 | /* Short opcode. */ | |
20069 | op = (offset - 4) >> 2; | |
20070 | add_unwind_opcode (op, 1); | |
20071 | } | |
20072 | else if (offset < 0) | |
bfae80f2 | 20073 | { |
c19d1205 ZW |
20074 | offset = -offset; |
20075 | while (offset > 0x100) | |
bfae80f2 | 20076 | { |
c19d1205 ZW |
20077 | add_unwind_opcode (0x7f, 1); |
20078 | offset -= 0x100; | |
bfae80f2 | 20079 | } |
c19d1205 ZW |
20080 | op = ((offset - 4) >> 2) | 0x40; |
20081 | add_unwind_opcode (op, 1); | |
bfae80f2 | 20082 | } |
bfae80f2 RE |
20083 | } |
20084 | ||
c19d1205 ZW |
20085 | /* Finish the list of unwind opcodes for this function. */ |
20086 | static void | |
20087 | finish_unwind_opcodes (void) | |
bfae80f2 | 20088 | { |
c19d1205 | 20089 | valueT op; |
bfae80f2 | 20090 | |
c19d1205 | 20091 | if (unwind.fp_used) |
bfae80f2 | 20092 | { |
708587a4 | 20093 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
20094 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
20095 | flush_pending_unwind (); | |
bfae80f2 | 20096 | |
c19d1205 ZW |
20097 | /* After restoring sp from the frame pointer. */ |
20098 | op = 0x90 | unwind.fp_reg; | |
20099 | add_unwind_opcode (op, 1); | |
20100 | } | |
20101 | else | |
20102 | flush_pending_unwind (); | |
bfae80f2 RE |
20103 | } |
20104 | ||
bfae80f2 | 20105 | |
c19d1205 ZW |
20106 | /* Start an exception table entry. If idx is nonzero this is an index table |
20107 | entry. */ | |
bfae80f2 RE |
20108 | |
20109 | static void | |
c19d1205 | 20110 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 20111 | { |
c19d1205 ZW |
20112 | const char * text_name; |
20113 | const char * prefix; | |
20114 | const char * prefix_once; | |
20115 | const char * group_name; | |
20116 | size_t prefix_len; | |
20117 | size_t text_len; | |
20118 | char * sec_name; | |
20119 | size_t sec_name_len; | |
20120 | int type; | |
20121 | int flags; | |
20122 | int linkonce; | |
bfae80f2 | 20123 | |
c19d1205 | 20124 | if (idx) |
bfae80f2 | 20125 | { |
c19d1205 ZW |
20126 | prefix = ELF_STRING_ARM_unwind; |
20127 | prefix_once = ELF_STRING_ARM_unwind_once; | |
20128 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 20129 | } |
c19d1205 | 20130 | else |
bfae80f2 | 20131 | { |
c19d1205 ZW |
20132 | prefix = ELF_STRING_ARM_unwind_info; |
20133 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
20134 | type = SHT_PROGBITS; | |
bfae80f2 RE |
20135 | } |
20136 | ||
c19d1205 ZW |
20137 | text_name = segment_name (text_seg); |
20138 | if (streq (text_name, ".text")) | |
20139 | text_name = ""; | |
20140 | ||
20141 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
20142 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 20143 | { |
c19d1205 ZW |
20144 | prefix = prefix_once; |
20145 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
20146 | } |
20147 | ||
c19d1205 ZW |
20148 | prefix_len = strlen (prefix); |
20149 | text_len = strlen (text_name); | |
20150 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 20151 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
20152 | memcpy (sec_name, prefix, prefix_len); |
20153 | memcpy (sec_name + prefix_len, text_name, text_len); | |
20154 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 20155 | |
c19d1205 ZW |
20156 | flags = SHF_ALLOC; |
20157 | linkonce = 0; | |
20158 | group_name = 0; | |
bfae80f2 | 20159 | |
c19d1205 ZW |
20160 | /* Handle COMDAT group. */ |
20161 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 20162 | { |
c19d1205 ZW |
20163 | group_name = elf_group_name (text_seg); |
20164 | if (group_name == NULL) | |
20165 | { | |
bd3ba5d1 | 20166 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
20167 | segment_name (text_seg)); |
20168 | ignore_rest_of_line (); | |
20169 | return; | |
20170 | } | |
20171 | flags |= SHF_GROUP; | |
20172 | linkonce = 1; | |
bfae80f2 RE |
20173 | } |
20174 | ||
c19d1205 | 20175 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 20176 | |
5f4273c7 | 20177 | /* Set the section link for index tables. */ |
c19d1205 ZW |
20178 | if (idx) |
20179 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
20180 | } |
20181 | ||
bfae80f2 | 20182 | |
c19d1205 ZW |
20183 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
20184 | personality routine data. Returns zero, or the index table value for | |
20185 | and inline entry. */ | |
20186 | ||
20187 | static valueT | |
20188 | create_unwind_entry (int have_data) | |
bfae80f2 | 20189 | { |
c19d1205 ZW |
20190 | int size; |
20191 | addressT where; | |
20192 | char *ptr; | |
20193 | /* The current word of data. */ | |
20194 | valueT data; | |
20195 | /* The number of bytes left in this word. */ | |
20196 | int n; | |
bfae80f2 | 20197 | |
c19d1205 | 20198 | finish_unwind_opcodes (); |
bfae80f2 | 20199 | |
c19d1205 ZW |
20200 | /* Remember the current text section. */ |
20201 | unwind.saved_seg = now_seg; | |
20202 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 20203 | |
c19d1205 | 20204 | start_unwind_section (now_seg, 0); |
bfae80f2 | 20205 | |
c19d1205 | 20206 | if (unwind.personality_routine == NULL) |
bfae80f2 | 20207 | { |
c19d1205 ZW |
20208 | if (unwind.personality_index == -2) |
20209 | { | |
20210 | if (have_data) | |
5f4273c7 | 20211 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
20212 | return 1; /* EXIDX_CANTUNWIND. */ |
20213 | } | |
bfae80f2 | 20214 | |
c19d1205 ZW |
20215 | /* Use a default personality routine if none is specified. */ |
20216 | if (unwind.personality_index == -1) | |
20217 | { | |
20218 | if (unwind.opcode_count > 3) | |
20219 | unwind.personality_index = 1; | |
20220 | else | |
20221 | unwind.personality_index = 0; | |
20222 | } | |
bfae80f2 | 20223 | |
c19d1205 ZW |
20224 | /* Space for the personality routine entry. */ |
20225 | if (unwind.personality_index == 0) | |
20226 | { | |
20227 | if (unwind.opcode_count > 3) | |
20228 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 20229 | |
c19d1205 ZW |
20230 | if (!have_data) |
20231 | { | |
20232 | /* All the data is inline in the index table. */ | |
20233 | data = 0x80; | |
20234 | n = 3; | |
20235 | while (unwind.opcode_count > 0) | |
20236 | { | |
20237 | unwind.opcode_count--; | |
20238 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
20239 | n--; | |
20240 | } | |
bfae80f2 | 20241 | |
c19d1205 ZW |
20242 | /* Pad with "finish" opcodes. */ |
20243 | while (n--) | |
20244 | data = (data << 8) | 0xb0; | |
bfae80f2 | 20245 | |
c19d1205 ZW |
20246 | return data; |
20247 | } | |
20248 | size = 0; | |
20249 | } | |
20250 | else | |
20251 | /* We get two opcodes "free" in the first word. */ | |
20252 | size = unwind.opcode_count - 2; | |
20253 | } | |
20254 | else | |
5011093d NC |
20255 | { |
20256 | gas_assert (unwind.personality_index == -1); | |
20257 | ||
20258 | /* An extra byte is required for the opcode count. */ | |
20259 | size = unwind.opcode_count + 1; | |
20260 | } | |
bfae80f2 | 20261 | |
c19d1205 ZW |
20262 | size = (size + 3) >> 2; |
20263 | if (size > 0xff) | |
20264 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 20265 | |
c19d1205 ZW |
20266 | frag_align (2, 0, 0); |
20267 | record_alignment (now_seg, 2); | |
20268 | unwind.table_entry = expr_build_dot (); | |
20269 | ||
20270 | /* Allocate the table entry. */ | |
20271 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
20272 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
20273 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 20274 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 20275 | |
c19d1205 | 20276 | switch (unwind.personality_index) |
bfae80f2 | 20277 | { |
c19d1205 ZW |
20278 | case -1: |
20279 | /* ??? Should this be a PLT generating relocation? */ | |
20280 | /* Custom personality routine. */ | |
20281 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
20282 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 20283 | |
c19d1205 ZW |
20284 | where += 4; |
20285 | ptr += 4; | |
bfae80f2 | 20286 | |
c19d1205 | 20287 | /* Set the first byte to the number of additional words. */ |
5011093d | 20288 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
20289 | n = 3; |
20290 | break; | |
bfae80f2 | 20291 | |
c19d1205 ZW |
20292 | /* ABI defined personality routines. */ |
20293 | case 0: | |
20294 | /* Three opcodes bytes are packed into the first word. */ | |
20295 | data = 0x80; | |
20296 | n = 3; | |
20297 | break; | |
bfae80f2 | 20298 | |
c19d1205 ZW |
20299 | case 1: |
20300 | case 2: | |
20301 | /* The size and first two opcode bytes go in the first word. */ | |
20302 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
20303 | n = 2; | |
20304 | break; | |
bfae80f2 | 20305 | |
c19d1205 ZW |
20306 | default: |
20307 | /* Should never happen. */ | |
20308 | abort (); | |
20309 | } | |
bfae80f2 | 20310 | |
c19d1205 ZW |
20311 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
20312 | time. */ | |
20313 | while (unwind.opcode_count > 0) | |
20314 | { | |
20315 | if (n == 0) | |
20316 | { | |
20317 | md_number_to_chars (ptr, data, 4); | |
20318 | ptr += 4; | |
20319 | n = 4; | |
20320 | data = 0; | |
20321 | } | |
20322 | unwind.opcode_count--; | |
20323 | n--; | |
20324 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
20325 | } | |
20326 | ||
20327 | /* Finish off the last word. */ | |
20328 | if (n < 4) | |
20329 | { | |
20330 | /* Pad with "finish" opcodes. */ | |
20331 | while (n--) | |
20332 | data = (data << 8) | 0xb0; | |
20333 | ||
20334 | md_number_to_chars (ptr, data, 4); | |
20335 | } | |
20336 | ||
20337 | if (!have_data) | |
20338 | { | |
20339 | /* Add an empty descriptor if there is no user-specified data. */ | |
20340 | ptr = frag_more (4); | |
20341 | md_number_to_chars (ptr, 0, 4); | |
20342 | } | |
20343 | ||
20344 | return 0; | |
bfae80f2 RE |
20345 | } |
20346 | ||
f0927246 NC |
20347 | |
20348 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
20349 | ||
20350 | void | |
20351 | tc_arm_frame_initial_instructions (void) | |
20352 | { | |
20353 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
20354 | } | |
20355 | #endif /* OBJ_ELF */ | |
20356 | ||
c19d1205 ZW |
20357 | /* Convert REGNAME to a DWARF-2 register number. */ |
20358 | ||
20359 | int | |
1df69f4f | 20360 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 20361 | { |
1df69f4f | 20362 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
20363 | |
20364 | if (reg == FAIL) | |
20365 | return -1; | |
20366 | ||
20367 | return reg; | |
bfae80f2 RE |
20368 | } |
20369 | ||
f0927246 | 20370 | #ifdef TE_PE |
c19d1205 | 20371 | void |
f0927246 | 20372 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 20373 | { |
91d6fa6a | 20374 | expressionS exp; |
bfae80f2 | 20375 | |
91d6fa6a NC |
20376 | exp.X_op = O_secrel; |
20377 | exp.X_add_symbol = symbol; | |
20378 | exp.X_add_number = 0; | |
20379 | emit_expr (&exp, size); | |
f0927246 NC |
20380 | } |
20381 | #endif | |
bfae80f2 | 20382 | |
c19d1205 | 20383 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 20384 | |
2fc8bdac ZW |
20385 | /* Return the address within the segment that a PC-relative fixup is |
20386 | relative to. For ARM, PC-relative fixups applied to instructions | |
20387 | are generally relative to the location of the fixup plus 8 bytes. | |
20388 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
20389 | require special handling. */ | |
bfae80f2 | 20390 | |
c19d1205 | 20391 | long |
2fc8bdac | 20392 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 20393 | { |
2fc8bdac ZW |
20394 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
20395 | ||
20396 | /* If this is pc-relative and we are going to emit a relocation | |
20397 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
20398 | will need. Otherwise we want to use the calculated base. |
20399 | For WinCE we skip the bias for externals as well, since this | |
20400 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 20401 | if (fixP->fx_pcrel |
2fc8bdac | 20402 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
20403 | || (arm_force_relocation (fixP) |
20404 | #ifdef TE_WINCE | |
20405 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20406 | #endif | |
20407 | ))) | |
2fc8bdac | 20408 | base = 0; |
bfae80f2 | 20409 | |
267bf995 | 20410 | |
c19d1205 | 20411 | switch (fixP->fx_r_type) |
bfae80f2 | 20412 | { |
2fc8bdac ZW |
20413 | /* PC relative addressing on the Thumb is slightly odd as the |
20414 | bottom two bits of the PC are forced to zero for the | |
20415 | calculation. This happens *after* application of the | |
20416 | pipeline offset. However, Thumb adrl already adjusts for | |
20417 | this, so we need not do it again. */ | |
c19d1205 | 20418 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 20419 | return base & ~3; |
c19d1205 ZW |
20420 | |
20421 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
20422 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 20423 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 20424 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 20425 | return (base + 4) & ~3; |
c19d1205 | 20426 | |
2fc8bdac ZW |
20427 | /* Thumb branches are simply offset by +4. */ |
20428 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
20429 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
20430 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
20431 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 20432 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 20433 | return base + 4; |
bfae80f2 | 20434 | |
267bf995 | 20435 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
20436 | if (fixP->fx_addsy |
20437 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20438 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20439 | && ARM_IS_FUNC (fixP->fx_addsy) |
20440 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20441 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
20442 | return base + 4; | |
20443 | ||
00adf2d4 JB |
20444 | /* BLX is like branches above, but forces the low two bits of PC to |
20445 | zero. */ | |
486499d0 CL |
20446 | case BFD_RELOC_THUMB_PCREL_BLX: |
20447 | if (fixP->fx_addsy | |
20448 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20449 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20450 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20451 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20452 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
20453 | return (base + 4) & ~3; |
20454 | ||
2fc8bdac ZW |
20455 | /* ARM mode branches are offset by +8. However, the Windows CE |
20456 | loader expects the relocation not to take this into account. */ | |
267bf995 | 20457 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
20458 | if (fixP->fx_addsy |
20459 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20460 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20461 | && ARM_IS_FUNC (fixP->fx_addsy) |
20462 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20463 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20464 | return base + 8; |
267bf995 | 20465 | |
486499d0 CL |
20466 | case BFD_RELOC_ARM_PCREL_CALL: |
20467 | if (fixP->fx_addsy | |
20468 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20469 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20470 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20471 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20472 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20473 | return base + 8; |
267bf995 | 20474 | |
2fc8bdac | 20475 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 20476 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 20477 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20478 | #ifdef TE_WINCE |
5f4273c7 | 20479 | /* When handling fixups immediately, because we have already |
53baae48 NC |
20480 | discovered the value of a symbol, or the address of the frag involved |
20481 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
20482 | see fixup_segment() in write.c | |
20483 | The S_IS_EXTERNAL test handles the case of global symbols. | |
20484 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
20485 | if (fixP->fx_pcrel | |
20486 | && fixP->fx_addsy != NULL | |
20487 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20488 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
20489 | return base + 8; | |
2fc8bdac | 20490 | return base; |
c19d1205 | 20491 | #else |
2fc8bdac | 20492 | return base + 8; |
c19d1205 | 20493 | #endif |
2fc8bdac | 20494 | |
267bf995 | 20495 | |
2fc8bdac ZW |
20496 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
20497 | branches, the Windows CE loader *does* expect the relocation | |
20498 | to take this into account. */ | |
20499 | case BFD_RELOC_ARM_OFFSET_IMM: | |
20500 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
20501 | case BFD_RELOC_ARM_HWLITERAL: | |
20502 | case BFD_RELOC_ARM_LITERAL: | |
20503 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
20504 | return base + 8; | |
20505 | ||
20506 | ||
20507 | /* Other PC-relative relocations are un-offset. */ | |
20508 | default: | |
20509 | return base; | |
20510 | } | |
bfae80f2 RE |
20511 | } |
20512 | ||
c19d1205 ZW |
20513 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
20514 | Otherwise we have no need to default values of symbols. */ | |
20515 | ||
20516 | symbolS * | |
20517 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 20518 | { |
c19d1205 ZW |
20519 | #ifdef OBJ_ELF |
20520 | if (name[0] == '_' && name[1] == 'G' | |
20521 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
20522 | { | |
20523 | if (!GOT_symbol) | |
20524 | { | |
20525 | if (symbol_find (name)) | |
bd3ba5d1 | 20526 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 20527 | |
c19d1205 ZW |
20528 | GOT_symbol = symbol_new (name, undefined_section, |
20529 | (valueT) 0, & zero_address_frag); | |
20530 | } | |
bfae80f2 | 20531 | |
c19d1205 | 20532 | return GOT_symbol; |
bfae80f2 | 20533 | } |
c19d1205 | 20534 | #endif |
bfae80f2 | 20535 | |
c921be7d | 20536 | return NULL; |
bfae80f2 RE |
20537 | } |
20538 | ||
55cf6793 | 20539 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
20540 | computed as two separate immediate values, added together. We |
20541 | already know that this value cannot be computed by just one ARM | |
20542 | instruction. */ | |
20543 | ||
20544 | static unsigned int | |
20545 | validate_immediate_twopart (unsigned int val, | |
20546 | unsigned int * highpart) | |
bfae80f2 | 20547 | { |
c19d1205 ZW |
20548 | unsigned int a; |
20549 | unsigned int i; | |
bfae80f2 | 20550 | |
c19d1205 ZW |
20551 | for (i = 0; i < 32; i += 2) |
20552 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
20553 | { | |
20554 | if (a & 0xff00) | |
20555 | { | |
20556 | if (a & ~ 0xffff) | |
20557 | continue; | |
20558 | * highpart = (a >> 8) | ((i + 24) << 7); | |
20559 | } | |
20560 | else if (a & 0xff0000) | |
20561 | { | |
20562 | if (a & 0xff000000) | |
20563 | continue; | |
20564 | * highpart = (a >> 16) | ((i + 16) << 7); | |
20565 | } | |
20566 | else | |
20567 | { | |
9c2799c2 | 20568 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
20569 | * highpart = (a >> 24) | ((i + 8) << 7); |
20570 | } | |
bfae80f2 | 20571 | |
c19d1205 ZW |
20572 | return (a & 0xff) | (i << 7); |
20573 | } | |
bfae80f2 | 20574 | |
c19d1205 | 20575 | return FAIL; |
bfae80f2 RE |
20576 | } |
20577 | ||
c19d1205 ZW |
20578 | static int |
20579 | validate_offset_imm (unsigned int val, int hwse) | |
20580 | { | |
20581 | if ((hwse && val > 255) || val > 4095) | |
20582 | return FAIL; | |
20583 | return val; | |
20584 | } | |
bfae80f2 | 20585 | |
55cf6793 | 20586 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
20587 | negative immediate constant by altering the instruction. A bit of |
20588 | a hack really. | |
20589 | MOV <-> MVN | |
20590 | AND <-> BIC | |
20591 | ADC <-> SBC | |
20592 | by inverting the second operand, and | |
20593 | ADD <-> SUB | |
20594 | CMP <-> CMN | |
20595 | by negating the second operand. */ | |
bfae80f2 | 20596 | |
c19d1205 ZW |
20597 | static int |
20598 | negate_data_op (unsigned long * instruction, | |
20599 | unsigned long value) | |
bfae80f2 | 20600 | { |
c19d1205 ZW |
20601 | int op, new_inst; |
20602 | unsigned long negated, inverted; | |
bfae80f2 | 20603 | |
c19d1205 ZW |
20604 | negated = encode_arm_immediate (-value); |
20605 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 20606 | |
c19d1205 ZW |
20607 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
20608 | switch (op) | |
bfae80f2 | 20609 | { |
c19d1205 ZW |
20610 | /* First negates. */ |
20611 | case OPCODE_SUB: /* ADD <-> SUB */ | |
20612 | new_inst = OPCODE_ADD; | |
20613 | value = negated; | |
20614 | break; | |
bfae80f2 | 20615 | |
c19d1205 ZW |
20616 | case OPCODE_ADD: |
20617 | new_inst = OPCODE_SUB; | |
20618 | value = negated; | |
20619 | break; | |
bfae80f2 | 20620 | |
c19d1205 ZW |
20621 | case OPCODE_CMP: /* CMP <-> CMN */ |
20622 | new_inst = OPCODE_CMN; | |
20623 | value = negated; | |
20624 | break; | |
bfae80f2 | 20625 | |
c19d1205 ZW |
20626 | case OPCODE_CMN: |
20627 | new_inst = OPCODE_CMP; | |
20628 | value = negated; | |
20629 | break; | |
bfae80f2 | 20630 | |
c19d1205 ZW |
20631 | /* Now Inverted ops. */ |
20632 | case OPCODE_MOV: /* MOV <-> MVN */ | |
20633 | new_inst = OPCODE_MVN; | |
20634 | value = inverted; | |
20635 | break; | |
bfae80f2 | 20636 | |
c19d1205 ZW |
20637 | case OPCODE_MVN: |
20638 | new_inst = OPCODE_MOV; | |
20639 | value = inverted; | |
20640 | break; | |
bfae80f2 | 20641 | |
c19d1205 ZW |
20642 | case OPCODE_AND: /* AND <-> BIC */ |
20643 | new_inst = OPCODE_BIC; | |
20644 | value = inverted; | |
20645 | break; | |
bfae80f2 | 20646 | |
c19d1205 ZW |
20647 | case OPCODE_BIC: |
20648 | new_inst = OPCODE_AND; | |
20649 | value = inverted; | |
20650 | break; | |
bfae80f2 | 20651 | |
c19d1205 ZW |
20652 | case OPCODE_ADC: /* ADC <-> SBC */ |
20653 | new_inst = OPCODE_SBC; | |
20654 | value = inverted; | |
20655 | break; | |
bfae80f2 | 20656 | |
c19d1205 ZW |
20657 | case OPCODE_SBC: |
20658 | new_inst = OPCODE_ADC; | |
20659 | value = inverted; | |
20660 | break; | |
bfae80f2 | 20661 | |
c19d1205 ZW |
20662 | /* We cannot do anything. */ |
20663 | default: | |
20664 | return FAIL; | |
b99bd4ef NC |
20665 | } |
20666 | ||
c19d1205 ZW |
20667 | if (value == (unsigned) FAIL) |
20668 | return FAIL; | |
20669 | ||
20670 | *instruction &= OPCODE_MASK; | |
20671 | *instruction |= new_inst << DATA_OP_SHIFT; | |
20672 | return value; | |
b99bd4ef NC |
20673 | } |
20674 | ||
ef8d22e6 PB |
20675 | /* Like negate_data_op, but for Thumb-2. */ |
20676 | ||
20677 | static unsigned int | |
16dd5e42 | 20678 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
20679 | { |
20680 | int op, new_inst; | |
20681 | int rd; | |
16dd5e42 | 20682 | unsigned int negated, inverted; |
ef8d22e6 PB |
20683 | |
20684 | negated = encode_thumb32_immediate (-value); | |
20685 | inverted = encode_thumb32_immediate (~value); | |
20686 | ||
20687 | rd = (*instruction >> 8) & 0xf; | |
20688 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
20689 | switch (op) | |
20690 | { | |
20691 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
20692 | case T2_OPCODE_SUB: | |
20693 | new_inst = T2_OPCODE_ADD; | |
20694 | value = negated; | |
20695 | break; | |
20696 | ||
20697 | case T2_OPCODE_ADD: | |
20698 | new_inst = T2_OPCODE_SUB; | |
20699 | value = negated; | |
20700 | break; | |
20701 | ||
20702 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
20703 | case T2_OPCODE_ORR: | |
20704 | new_inst = T2_OPCODE_ORN; | |
20705 | value = inverted; | |
20706 | break; | |
20707 | ||
20708 | case T2_OPCODE_ORN: | |
20709 | new_inst = T2_OPCODE_ORR; | |
20710 | value = inverted; | |
20711 | break; | |
20712 | ||
20713 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
20714 | case T2_OPCODE_AND: | |
20715 | new_inst = T2_OPCODE_BIC; | |
20716 | if (rd == 15) | |
20717 | value = FAIL; | |
20718 | else | |
20719 | value = inverted; | |
20720 | break; | |
20721 | ||
20722 | case T2_OPCODE_BIC: | |
20723 | new_inst = T2_OPCODE_AND; | |
20724 | value = inverted; | |
20725 | break; | |
20726 | ||
20727 | /* ADC <-> SBC */ | |
20728 | case T2_OPCODE_ADC: | |
20729 | new_inst = T2_OPCODE_SBC; | |
20730 | value = inverted; | |
20731 | break; | |
20732 | ||
20733 | case T2_OPCODE_SBC: | |
20734 | new_inst = T2_OPCODE_ADC; | |
20735 | value = inverted; | |
20736 | break; | |
20737 | ||
20738 | /* We cannot do anything. */ | |
20739 | default: | |
20740 | return FAIL; | |
20741 | } | |
20742 | ||
16dd5e42 | 20743 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
20744 | return FAIL; |
20745 | ||
20746 | *instruction &= T2_OPCODE_MASK; | |
20747 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
20748 | return value; | |
20749 | } | |
20750 | ||
8f06b2d8 PB |
20751 | /* Read a 32-bit thumb instruction from buf. */ |
20752 | static unsigned long | |
20753 | get_thumb32_insn (char * buf) | |
20754 | { | |
20755 | unsigned long insn; | |
20756 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
20757 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20758 | ||
20759 | return insn; | |
20760 | } | |
20761 | ||
a8bc6c78 PB |
20762 | |
20763 | /* We usually want to set the low bit on the address of thumb function | |
20764 | symbols. In particular .word foo - . should have the low bit set. | |
20765 | Generic code tries to fold the difference of two symbols to | |
20766 | a constant. Prevent this and force a relocation when the first symbols | |
20767 | is a thumb function. */ | |
c921be7d NC |
20768 | |
20769 | bfd_boolean | |
a8bc6c78 PB |
20770 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
20771 | { | |
20772 | if (op == O_subtract | |
20773 | && l->X_op == O_symbol | |
20774 | && r->X_op == O_symbol | |
20775 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
20776 | { | |
20777 | l->X_op = O_subtract; | |
20778 | l->X_op_symbol = r->X_add_symbol; | |
20779 | l->X_add_number -= r->X_add_number; | |
c921be7d | 20780 | return TRUE; |
a8bc6c78 | 20781 | } |
c921be7d | 20782 | |
a8bc6c78 | 20783 | /* Process as normal. */ |
c921be7d | 20784 | return FALSE; |
a8bc6c78 PB |
20785 | } |
20786 | ||
4a42ebbc RR |
20787 | /* Encode Thumb2 unconditional branches and calls. The encoding |
20788 | for the 2 are identical for the immediate values. */ | |
20789 | ||
20790 | static void | |
20791 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
20792 | { | |
20793 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
20794 | offsetT newval; | |
20795 | offsetT newval2; | |
20796 | addressT S, I1, I2, lo, hi; | |
20797 | ||
20798 | S = (value >> 24) & 0x01; | |
20799 | I1 = (value >> 23) & 0x01; | |
20800 | I2 = (value >> 22) & 0x01; | |
20801 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 20802 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
20803 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20804 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20805 | newval |= (S << 10) | hi; | |
20806 | newval2 &= ~T2I1I2MASK; | |
20807 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
20808 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20809 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20810 | } | |
20811 | ||
c19d1205 | 20812 | void |
55cf6793 | 20813 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
20814 | valueT * valP, |
20815 | segT seg) | |
20816 | { | |
20817 | offsetT value = * valP; | |
20818 | offsetT newval; | |
20819 | unsigned int newimm; | |
20820 | unsigned long temp; | |
20821 | int sign; | |
20822 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 20823 | |
9c2799c2 | 20824 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 20825 | |
c19d1205 | 20826 | /* Note whether this will delete the relocation. */ |
4962c51a | 20827 | |
c19d1205 ZW |
20828 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
20829 | fixP->fx_done = 1; | |
b99bd4ef | 20830 | |
adbaf948 | 20831 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 20832 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
20833 | for emit_reloc. */ |
20834 | value &= 0xffffffff; | |
20835 | value ^= 0x80000000; | |
5f4273c7 | 20836 | value -= 0x80000000; |
adbaf948 ZW |
20837 | |
20838 | *valP = value; | |
c19d1205 | 20839 | fixP->fx_addnumber = value; |
b99bd4ef | 20840 | |
adbaf948 ZW |
20841 | /* Same treatment for fixP->fx_offset. */ |
20842 | fixP->fx_offset &= 0xffffffff; | |
20843 | fixP->fx_offset ^= 0x80000000; | |
20844 | fixP->fx_offset -= 0x80000000; | |
20845 | ||
c19d1205 | 20846 | switch (fixP->fx_r_type) |
b99bd4ef | 20847 | { |
c19d1205 ZW |
20848 | case BFD_RELOC_NONE: |
20849 | /* This will need to go in the object file. */ | |
20850 | fixP->fx_done = 0; | |
20851 | break; | |
b99bd4ef | 20852 | |
c19d1205 ZW |
20853 | case BFD_RELOC_ARM_IMMEDIATE: |
20854 | /* We claim that this fixup has been processed here, | |
20855 | even if in fact we generate an error because we do | |
20856 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20857 | fixP->fx_done = 1; | |
b99bd4ef | 20858 | |
77db8e2e | 20859 | if (fixP->fx_addsy) |
b99bd4ef | 20860 | { |
77db8e2e | 20861 | const char *msg = 0; |
b99bd4ef | 20862 | |
77db8e2e NC |
20863 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20864 | msg = _("undefined symbol %s used as an immediate value"); | |
20865 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20866 | msg = _("symbol %s is in a different section"); | |
20867 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20868 | msg = _("symbol %s is weak and may be overridden later"); | |
20869 | ||
20870 | if (msg) | |
20871 | { | |
20872 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20873 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20874 | break; | |
20875 | } | |
42e5fcbf AS |
20876 | } |
20877 | ||
c19d1205 ZW |
20878 | temp = md_chars_to_number (buf, INSN_SIZE); |
20879 | ||
5e73442d SL |
20880 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
20881 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
20882 | newimm = negate_data_op (&temp, value); | |
20883 | else | |
20884 | { | |
20885 | newimm = encode_arm_immediate (value); | |
20886 | ||
20887 | /* If the instruction will fail, see if we can fix things up by | |
20888 | changing the opcode. */ | |
20889 | if (newimm == (unsigned int) FAIL) | |
20890 | newimm = negate_data_op (&temp, value); | |
20891 | } | |
20892 | ||
20893 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 20894 | { |
c19d1205 ZW |
20895 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20896 | _("invalid constant (%lx) after fixup"), | |
20897 | (unsigned long) value); | |
20898 | break; | |
b99bd4ef | 20899 | } |
b99bd4ef | 20900 | |
c19d1205 ZW |
20901 | newimm |= (temp & 0xfffff000); |
20902 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
20903 | break; | |
b99bd4ef | 20904 | |
c19d1205 ZW |
20905 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
20906 | { | |
20907 | unsigned int highpart = 0; | |
20908 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 20909 | |
77db8e2e | 20910 | if (fixP->fx_addsy) |
42e5fcbf | 20911 | { |
77db8e2e | 20912 | const char *msg = 0; |
42e5fcbf | 20913 | |
77db8e2e NC |
20914 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20915 | msg = _("undefined symbol %s used as an immediate value"); | |
20916 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20917 | msg = _("symbol %s is in a different section"); | |
20918 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20919 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 20920 | |
77db8e2e NC |
20921 | if (msg) |
20922 | { | |
20923 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20924 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20925 | break; | |
20926 | } | |
20927 | } | |
fa94de6b | 20928 | |
c19d1205 ZW |
20929 | newimm = encode_arm_immediate (value); |
20930 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 20931 | |
c19d1205 ZW |
20932 | /* If the instruction will fail, see if we can fix things up by |
20933 | changing the opcode. */ | |
20934 | if (newimm == (unsigned int) FAIL | |
20935 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
20936 | { | |
20937 | /* No ? OK - try using two ADD instructions to generate | |
20938 | the value. */ | |
20939 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 20940 | |
c19d1205 ZW |
20941 | /* Yes - then make sure that the second instruction is |
20942 | also an add. */ | |
20943 | if (newimm != (unsigned int) FAIL) | |
20944 | newinsn = temp; | |
20945 | /* Still No ? Try using a negated value. */ | |
20946 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
20947 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
20948 | /* Otherwise - give up. */ | |
20949 | else | |
20950 | { | |
20951 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20952 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
20953 | (long) value); | |
20954 | break; | |
20955 | } | |
b99bd4ef | 20956 | |
c19d1205 ZW |
20957 | /* Replace the first operand in the 2nd instruction (which |
20958 | is the PC) with the destination register. We have | |
20959 | already added in the PC in the first instruction and we | |
20960 | do not want to do it again. */ | |
20961 | newinsn &= ~ 0xf0000; | |
20962 | newinsn |= ((newinsn & 0x0f000) << 4); | |
20963 | } | |
b99bd4ef | 20964 | |
c19d1205 ZW |
20965 | newimm |= (temp & 0xfffff000); |
20966 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 20967 | |
c19d1205 ZW |
20968 | highpart |= (newinsn & 0xfffff000); |
20969 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
20970 | } | |
20971 | break; | |
b99bd4ef | 20972 | |
c19d1205 | 20973 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20974 | if (!fixP->fx_done && seg->use_rela_p) |
20975 | value = 0; | |
20976 | ||
c19d1205 | 20977 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 20978 | sign = value > 0; |
b99bd4ef | 20979 | |
c19d1205 ZW |
20980 | if (value < 0) |
20981 | value = - value; | |
b99bd4ef | 20982 | |
c19d1205 | 20983 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 20984 | { |
c19d1205 ZW |
20985 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
20986 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20987 | _("invalid literal constant: pool needs to be closer")); | |
20988 | else | |
20989 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20990 | _("bad immediate value for offset (%ld)"), | |
20991 | (long) value); | |
20992 | break; | |
f03698e6 RE |
20993 | } |
20994 | ||
c19d1205 | 20995 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20996 | if (value == 0) |
20997 | newval &= 0xfffff000; | |
20998 | else | |
20999 | { | |
21000 | newval &= 0xff7ff000; | |
21001 | newval |= value | (sign ? INDEX_UP : 0); | |
21002 | } | |
c19d1205 ZW |
21003 | md_number_to_chars (buf, newval, INSN_SIZE); |
21004 | break; | |
b99bd4ef | 21005 | |
c19d1205 ZW |
21006 | case BFD_RELOC_ARM_OFFSET_IMM8: |
21007 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 21008 | sign = value > 0; |
b99bd4ef | 21009 | |
c19d1205 ZW |
21010 | if (value < 0) |
21011 | value = - value; | |
b99bd4ef | 21012 | |
c19d1205 | 21013 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 21014 | { |
c19d1205 ZW |
21015 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
21016 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21017 | _("invalid literal constant: pool needs to be closer")); | |
21018 | else | |
f9d4405b | 21019 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
21020 | (long) value); |
21021 | break; | |
b99bd4ef NC |
21022 | } |
21023 | ||
c19d1205 | 21024 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
21025 | if (value == 0) |
21026 | newval &= 0xfffff0f0; | |
21027 | else | |
21028 | { | |
21029 | newval &= 0xff7ff0f0; | |
21030 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
21031 | } | |
c19d1205 ZW |
21032 | md_number_to_chars (buf, newval, INSN_SIZE); |
21033 | break; | |
b99bd4ef | 21034 | |
c19d1205 ZW |
21035 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
21036 | if (value < 0 || value > 1020 || value % 4 != 0) | |
21037 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21038 | _("bad immediate value for offset (%ld)"), (long) value); | |
21039 | value /= 4; | |
b99bd4ef | 21040 | |
c19d1205 | 21041 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
21042 | newval |= value; |
21043 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
21044 | break; | |
b99bd4ef | 21045 | |
c19d1205 ZW |
21046 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
21047 | /* This is a complicated relocation used for all varieties of Thumb32 | |
21048 | load/store instruction with immediate offset: | |
21049 | ||
21050 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
21051 | *4, optional writeback(W) | |
21052 | (doubleword load/store) | |
21053 | ||
21054 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
21055 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
21056 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
21057 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
21058 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
21059 | ||
21060 | Uppercase letters indicate bits that are already encoded at | |
21061 | this point. Lowercase letters are our problem. For the | |
21062 | second block of instructions, the secondary opcode nybble | |
21063 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
21064 | a PC-relative operation. */ | |
21065 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21066 | newval <<= 16; | |
21067 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 21068 | |
c19d1205 | 21069 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 21070 | { |
c19d1205 ZW |
21071 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
21072 | if (value >= 0) | |
21073 | newval |= (1 << 23); | |
21074 | else | |
21075 | value = -value; | |
21076 | if (value % 4 != 0) | |
21077 | { | |
21078 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21079 | _("offset not a multiple of 4")); | |
21080 | break; | |
21081 | } | |
21082 | value /= 4; | |
216d22bc | 21083 | if (value > 0xff) |
c19d1205 ZW |
21084 | { |
21085 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21086 | _("offset out of range")); | |
21087 | break; | |
21088 | } | |
21089 | newval &= ~0xff; | |
b99bd4ef | 21090 | } |
c19d1205 | 21091 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 21092 | { |
c19d1205 ZW |
21093 | /* PC-relative, 12-bit offset. */ |
21094 | if (value >= 0) | |
21095 | newval |= (1 << 23); | |
21096 | else | |
21097 | value = -value; | |
216d22bc | 21098 | if (value > 0xfff) |
c19d1205 ZW |
21099 | { |
21100 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21101 | _("offset out of range")); | |
21102 | break; | |
21103 | } | |
21104 | newval &= ~0xfff; | |
b99bd4ef | 21105 | } |
c19d1205 | 21106 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 21107 | { |
c19d1205 ZW |
21108 | /* Writeback: 8-bit, +/- offset. */ |
21109 | if (value >= 0) | |
21110 | newval |= (1 << 9); | |
21111 | else | |
21112 | value = -value; | |
216d22bc | 21113 | if (value > 0xff) |
c19d1205 ZW |
21114 | { |
21115 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21116 | _("offset out of range")); | |
21117 | break; | |
21118 | } | |
21119 | newval &= ~0xff; | |
b99bd4ef | 21120 | } |
c19d1205 | 21121 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 21122 | { |
c19d1205 | 21123 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 21124 | if (value < 0 || value > 0xff) |
b99bd4ef | 21125 | { |
c19d1205 ZW |
21126 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21127 | _("offset out of range")); | |
21128 | break; | |
b99bd4ef | 21129 | } |
c19d1205 ZW |
21130 | newval &= ~0xff; |
21131 | newval |= value; | |
b99bd4ef NC |
21132 | } |
21133 | else | |
b99bd4ef | 21134 | { |
c19d1205 ZW |
21135 | /* Positive 12-bit or negative 8-bit offset. */ |
21136 | int limit; | |
21137 | if (value >= 0) | |
b99bd4ef | 21138 | { |
c19d1205 ZW |
21139 | newval |= (1 << 23); |
21140 | limit = 0xfff; | |
21141 | } | |
21142 | else | |
21143 | { | |
21144 | value = -value; | |
21145 | limit = 0xff; | |
21146 | } | |
21147 | if (value > limit) | |
21148 | { | |
21149 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21150 | _("offset out of range")); | |
21151 | break; | |
b99bd4ef | 21152 | } |
c19d1205 | 21153 | newval &= ~limit; |
b99bd4ef | 21154 | } |
b99bd4ef | 21155 | |
c19d1205 ZW |
21156 | newval |= value; |
21157 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
21158 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
21159 | break; | |
404ff6b5 | 21160 | |
c19d1205 ZW |
21161 | case BFD_RELOC_ARM_SHIFT_IMM: |
21162 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21163 | if (((unsigned long) value) > 32 | |
21164 | || (value == 32 | |
21165 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
21166 | { | |
21167 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21168 | _("shift expression is too large")); | |
21169 | break; | |
21170 | } | |
404ff6b5 | 21171 | |
c19d1205 ZW |
21172 | if (value == 0) |
21173 | /* Shifts of zero must be done as lsl. */ | |
21174 | newval &= ~0x60; | |
21175 | else if (value == 32) | |
21176 | value = 0; | |
21177 | newval &= 0xfffff07f; | |
21178 | newval |= (value & 0x1f) << 7; | |
21179 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21180 | break; | |
404ff6b5 | 21181 | |
c19d1205 | 21182 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 21183 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 21184 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 21185 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
21186 | /* We claim that this fixup has been processed here, |
21187 | even if in fact we generate an error because we do | |
21188 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
21189 | fixP->fx_done = 1; | |
404ff6b5 | 21190 | |
c19d1205 ZW |
21191 | if (fixP->fx_addsy |
21192 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
21193 | { | |
21194 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21195 | _("undefined symbol %s used as an immediate value"), | |
21196 | S_GET_NAME (fixP->fx_addsy)); | |
21197 | break; | |
21198 | } | |
404ff6b5 | 21199 | |
c19d1205 ZW |
21200 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21201 | newval <<= 16; | |
21202 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 21203 | |
16805f35 PB |
21204 | newimm = FAIL; |
21205 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
21206 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
21207 | { |
21208 | newimm = encode_thumb32_immediate (value); | |
21209 | if (newimm == (unsigned int) FAIL) | |
21210 | newimm = thumb32_negate_data_op (&newval, value); | |
21211 | } | |
16805f35 PB |
21212 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
21213 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 21214 | { |
16805f35 PB |
21215 | /* Turn add/sum into addw/subw. */ |
21216 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
21217 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
21218 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
21219 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 21220 | { |
40f246e3 NC |
21221 | /* 12 bit immediate for addw/subw. */ |
21222 | if (value < 0) | |
21223 | { | |
21224 | value = -value; | |
21225 | newval ^= 0x00a00000; | |
21226 | } | |
21227 | if (value > 0xfff) | |
21228 | newimm = (unsigned int) FAIL; | |
21229 | else | |
21230 | newimm = value; | |
e9f89963 | 21231 | } |
92e90b6e | 21232 | } |
cc8a6dd0 | 21233 | |
c19d1205 | 21234 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 21235 | { |
c19d1205 ZW |
21236 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21237 | _("invalid constant (%lx) after fixup"), | |
21238 | (unsigned long) value); | |
21239 | break; | |
3631a3c8 NC |
21240 | } |
21241 | ||
c19d1205 ZW |
21242 | newval |= (newimm & 0x800) << 15; |
21243 | newval |= (newimm & 0x700) << 4; | |
21244 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 21245 | |
c19d1205 ZW |
21246 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
21247 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
21248 | break; | |
a737bd4d | 21249 | |
3eb17e6b | 21250 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
21251 | if (((unsigned long) value) > 0xffff) |
21252 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 21253 | _("invalid smc expression")); |
2fc8bdac | 21254 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
21255 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
21256 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21257 | break; | |
a737bd4d | 21258 | |
90ec0d68 MGD |
21259 | case BFD_RELOC_ARM_HVC: |
21260 | if (((unsigned long) value) > 0xffff) | |
21261 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21262 | _("invalid hvc expression")); | |
21263 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21264 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
21265 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21266 | break; | |
21267 | ||
c19d1205 | 21268 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 21269 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
21270 | { |
21271 | if (((unsigned long) value) > 0xff) | |
21272 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21273 | _("invalid swi expression")); | |
2fc8bdac | 21274 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
21275 | newval |= value; |
21276 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21277 | } | |
21278 | else | |
21279 | { | |
21280 | if (((unsigned long) value) > 0x00ffffff) | |
21281 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21282 | _("invalid swi expression")); | |
2fc8bdac | 21283 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
21284 | newval |= value; |
21285 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21286 | } | |
21287 | break; | |
a737bd4d | 21288 | |
c19d1205 ZW |
21289 | case BFD_RELOC_ARM_MULTI: |
21290 | if (((unsigned long) value) > 0xffff) | |
21291 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21292 | _("invalid expression in load/store multiple")); | |
21293 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
21294 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21295 | break; | |
a737bd4d | 21296 | |
c19d1205 | 21297 | #ifdef OBJ_ELF |
39b41c9c | 21298 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
21299 | |
21300 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
21301 | && fixP->fx_addsy | |
34e77a92 | 21302 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21303 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21304 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21305 | /* Flip the bl to blx. This is a simple flip | |
21306 | bit here because we generate PCREL_CALL for | |
21307 | unconditional bls. */ | |
21308 | { | |
21309 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21310 | newval = newval | 0x10000000; | |
21311 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21312 | temp = 1; | |
21313 | fixP->fx_done = 1; | |
21314 | } | |
39b41c9c PB |
21315 | else |
21316 | temp = 3; | |
21317 | goto arm_branch_common; | |
21318 | ||
21319 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
21320 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
21321 | && fixP->fx_addsy | |
34e77a92 | 21322 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21323 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21324 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21325 | { | |
21326 | /* This would map to a bl<cond>, b<cond>, | |
21327 | b<always> to a Thumb function. We | |
21328 | need to force a relocation for this particular | |
21329 | case. */ | |
21330 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21331 | fixP->fx_done = 0; | |
21332 | } | |
21333 | ||
2fc8bdac | 21334 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 21335 | #endif |
39b41c9c PB |
21336 | case BFD_RELOC_ARM_PCREL_BRANCH: |
21337 | temp = 3; | |
21338 | goto arm_branch_common; | |
a737bd4d | 21339 | |
39b41c9c | 21340 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 21341 | |
39b41c9c | 21342 | temp = 1; |
267bf995 RR |
21343 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
21344 | && fixP->fx_addsy | |
34e77a92 | 21345 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21346 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21347 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
21348 | { | |
21349 | /* Flip the blx to a bl and warn. */ | |
21350 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21351 | newval = 0xeb000000; | |
21352 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21353 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
21354 | name); | |
21355 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21356 | temp = 3; | |
21357 | fixP->fx_done = 1; | |
21358 | } | |
21359 | ||
21360 | #ifdef OBJ_ELF | |
21361 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21362 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
21363 | #endif | |
21364 | ||
39b41c9c | 21365 | arm_branch_common: |
c19d1205 | 21366 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
21367 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
21368 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
21369 | also be be clear. */ | |
21370 | if (value & temp) | |
c19d1205 | 21371 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
21372 | _("misaligned branch destination")); |
21373 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
21374 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 21375 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21376 | |
2fc8bdac | 21377 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21378 | { |
2fc8bdac ZW |
21379 | newval = md_chars_to_number (buf, INSN_SIZE); |
21380 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
21381 | /* Set the H bit on BLX instructions. */ |
21382 | if (temp == 1) | |
21383 | { | |
21384 | if (value & 2) | |
21385 | newval |= 0x01000000; | |
21386 | else | |
21387 | newval &= ~0x01000000; | |
21388 | } | |
2fc8bdac | 21389 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 21390 | } |
c19d1205 | 21391 | break; |
a737bd4d | 21392 | |
25fe350b MS |
21393 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
21394 | /* CBZ can only branch forward. */ | |
a737bd4d | 21395 | |
738755b0 MS |
21396 | /* Attempts to use CBZ to branch to the next instruction |
21397 | (which, strictly speaking, are prohibited) will be turned into | |
21398 | no-ops. | |
21399 | ||
21400 | FIXME: It may be better to remove the instruction completely and | |
21401 | perform relaxation. */ | |
21402 | if (value == -2) | |
2fc8bdac ZW |
21403 | { |
21404 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 21405 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
21406 | md_number_to_chars (buf, newval, THUMB_SIZE); |
21407 | } | |
738755b0 MS |
21408 | else |
21409 | { | |
21410 | if (value & ~0x7e) | |
08f10d51 | 21411 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 MS |
21412 | |
21413 | if (fixP->fx_done || !seg->use_rela_p) | |
21414 | { | |
21415 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21416 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
21417 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21418 | } | |
21419 | } | |
c19d1205 | 21420 | break; |
a737bd4d | 21421 | |
c19d1205 | 21422 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 21423 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 21424 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21425 | |
2fc8bdac ZW |
21426 | if (fixP->fx_done || !seg->use_rela_p) |
21427 | { | |
21428 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21429 | newval |= (value & 0x1ff) >> 1; | |
21430 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21431 | } | |
c19d1205 | 21432 | break; |
a737bd4d | 21433 | |
c19d1205 | 21434 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 21435 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 21436 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21437 | |
2fc8bdac ZW |
21438 | if (fixP->fx_done || !seg->use_rela_p) |
21439 | { | |
21440 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21441 | newval |= (value & 0xfff) >> 1; | |
21442 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21443 | } | |
c19d1205 | 21444 | break; |
a737bd4d | 21445 | |
c19d1205 | 21446 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
21447 | if (fixP->fx_addsy |
21448 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21449 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21450 | && ARM_IS_FUNC (fixP->fx_addsy) |
21451 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21452 | { | |
21453 | /* Force a relocation for a branch 20 bits wide. */ | |
21454 | fixP->fx_done = 0; | |
21455 | } | |
08f10d51 | 21456 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
21457 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21458 | _("conditional branch out of range")); | |
404ff6b5 | 21459 | |
2fc8bdac ZW |
21460 | if (fixP->fx_done || !seg->use_rela_p) |
21461 | { | |
21462 | offsetT newval2; | |
21463 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 21464 | |
2fc8bdac ZW |
21465 | S = (value & 0x00100000) >> 20; |
21466 | J2 = (value & 0x00080000) >> 19; | |
21467 | J1 = (value & 0x00040000) >> 18; | |
21468 | hi = (value & 0x0003f000) >> 12; | |
21469 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 21470 | |
2fc8bdac ZW |
21471 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21472 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21473 | newval |= (S << 10) | hi; | |
21474 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
21475 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21476 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
21477 | } | |
c19d1205 | 21478 | break; |
6c43fab6 | 21479 | |
c19d1205 | 21480 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
21481 | /* If there is a blx from a thumb state function to |
21482 | another thumb function flip this to a bl and warn | |
21483 | about it. */ | |
21484 | ||
21485 | if (fixP->fx_addsy | |
34e77a92 | 21486 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21487 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21488 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21489 | { | |
21490 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21491 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21492 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
21493 | name); | |
21494 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21495 | newval = newval | 0x1000; | |
21496 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21497 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21498 | fixP->fx_done = 1; | |
21499 | } | |
21500 | ||
21501 | ||
21502 | goto thumb_bl_common; | |
21503 | ||
c19d1205 | 21504 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
21505 | /* A bl from Thumb state ISA to an internal ARM state function |
21506 | is converted to a blx. */ | |
21507 | if (fixP->fx_addsy | |
21508 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21509 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21510 | && ARM_IS_FUNC (fixP->fx_addsy) |
21511 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21512 | { | |
21513 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21514 | newval = newval & ~0x1000; | |
21515 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21516 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
21517 | fixP->fx_done = 1; | |
21518 | } | |
21519 | ||
21520 | thumb_bl_common: | |
21521 | ||
21522 | #ifdef OBJ_ELF | |
2b2f5df9 NC |
21523 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 |
21524 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
267bf995 RR |
21525 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
21526 | #endif | |
21527 | ||
2fc8bdac ZW |
21528 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
21529 | /* For a BLX instruction, make sure that the relocation is rounded up | |
21530 | to a word boundary. This follows the semantics of the instruction | |
21531 | which specifies that bit 1 of the target address will come from bit | |
21532 | 1 of the base address. */ | |
21533 | value = (value + 1) & ~ 1; | |
404ff6b5 | 21534 | |
2b2f5df9 NC |
21535 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
21536 | { | |
21537 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
21538 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
21539 | else if ((value & ~0x1ffffff) | |
21540 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
21541 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21542 | _("Thumb2 branch out of range")); | |
21543 | } | |
4a42ebbc RR |
21544 | |
21545 | if (fixP->fx_done || !seg->use_rela_p) | |
21546 | encode_thumb2_b_bl_offset (buf, value); | |
21547 | ||
c19d1205 | 21548 | break; |
404ff6b5 | 21549 | |
c19d1205 | 21550 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
21551 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
21552 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 21553 | |
2fc8bdac | 21554 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 21555 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 21556 | |
2fc8bdac | 21557 | break; |
a737bd4d | 21558 | |
2fc8bdac ZW |
21559 | case BFD_RELOC_8: |
21560 | if (fixP->fx_done || !seg->use_rela_p) | |
21561 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 21562 | break; |
a737bd4d | 21563 | |
c19d1205 | 21564 | case BFD_RELOC_16: |
2fc8bdac | 21565 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21566 | md_number_to_chars (buf, value, 2); |
c19d1205 | 21567 | break; |
a737bd4d | 21568 | |
c19d1205 | 21569 | #ifdef OBJ_ELF |
0855e32b NS |
21570 | case BFD_RELOC_ARM_TLS_CALL: |
21571 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21572 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21573 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
21574 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21575 | break; | |
21576 | ||
21577 | case BFD_RELOC_ARM_TLS_GOTDESC: | |
c19d1205 ZW |
21578 | case BFD_RELOC_ARM_TLS_GD32: |
21579 | case BFD_RELOC_ARM_TLS_LE32: | |
21580 | case BFD_RELOC_ARM_TLS_IE32: | |
21581 | case BFD_RELOC_ARM_TLS_LDM32: | |
21582 | case BFD_RELOC_ARM_TLS_LDO32: | |
21583 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21584 | /* fall through */ | |
6c43fab6 | 21585 | |
c19d1205 ZW |
21586 | case BFD_RELOC_ARM_GOT32: |
21587 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
21588 | if (fixP->fx_done || !seg->use_rela_p) |
21589 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 21590 | break; |
b43420e6 NC |
21591 | |
21592 | case BFD_RELOC_ARM_GOT_PREL: | |
21593 | if (fixP->fx_done || !seg->use_rela_p) | |
21594 | md_number_to_chars (buf, value, 4); | |
21595 | break; | |
21596 | ||
9a6f4e97 NS |
21597 | case BFD_RELOC_ARM_TARGET2: |
21598 | /* TARGET2 is not partial-inplace, so we need to write the | |
21599 | addend here for REL targets, because it won't be written out | |
21600 | during reloc processing later. */ | |
21601 | if (fixP->fx_done || !seg->use_rela_p) | |
21602 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
21603 | break; | |
c19d1205 | 21604 | #endif |
6c43fab6 | 21605 | |
c19d1205 ZW |
21606 | case BFD_RELOC_RVA: |
21607 | case BFD_RELOC_32: | |
21608 | case BFD_RELOC_ARM_TARGET1: | |
21609 | case BFD_RELOC_ARM_ROSEGREL32: | |
21610 | case BFD_RELOC_ARM_SBREL32: | |
21611 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
21612 | #ifdef TE_PE |
21613 | case BFD_RELOC_32_SECREL: | |
21614 | #endif | |
2fc8bdac | 21615 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
21616 | #ifdef TE_WINCE |
21617 | /* For WinCE we only do this for pcrel fixups. */ | |
21618 | if (fixP->fx_done || fixP->fx_pcrel) | |
21619 | #endif | |
21620 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 21621 | break; |
6c43fab6 | 21622 | |
c19d1205 ZW |
21623 | #ifdef OBJ_ELF |
21624 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 21625 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
21626 | { |
21627 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
21628 | if ((value ^ (value >> 1)) & 0x40000000) | |
21629 | { | |
21630 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21631 | _("rel31 relocation overflow")); | |
21632 | } | |
21633 | newval |= value & 0x7fffffff; | |
21634 | md_number_to_chars (buf, newval, 4); | |
21635 | } | |
21636 | break; | |
c19d1205 | 21637 | #endif |
a737bd4d | 21638 | |
c19d1205 | 21639 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 21640 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
21641 | if (value < -1023 || value > 1023 || (value & 3)) |
21642 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21643 | _("co-processor offset out of range")); | |
21644 | cp_off_common: | |
26d97720 | 21645 | sign = value > 0; |
c19d1205 ZW |
21646 | if (value < 0) |
21647 | value = -value; | |
8f06b2d8 PB |
21648 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21649 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21650 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21651 | else | |
21652 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
21653 | if (value == 0) |
21654 | newval &= 0xffffff00; | |
21655 | else | |
21656 | { | |
21657 | newval &= 0xff7fff00; | |
21658 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
21659 | } | |
8f06b2d8 PB |
21660 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21661 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21662 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21663 | else | |
21664 | put_thumb32_insn (buf, newval); | |
c19d1205 | 21665 | break; |
a737bd4d | 21666 | |
c19d1205 | 21667 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 21668 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
21669 | if (value < -255 || value > 255) |
21670 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21671 | _("co-processor offset out of range")); | |
df7849c5 | 21672 | value *= 4; |
c19d1205 | 21673 | goto cp_off_common; |
6c43fab6 | 21674 | |
c19d1205 ZW |
21675 | case BFD_RELOC_ARM_THUMB_OFFSET: |
21676 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21677 | /* Exactly what ranges, and where the offset is inserted depends | |
21678 | on the type of instruction, we can establish this from the | |
21679 | top 4 bits. */ | |
21680 | switch (newval >> 12) | |
21681 | { | |
21682 | case 4: /* PC load. */ | |
21683 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
21684 | forced to zero for these loads; md_pcrel_from has already | |
21685 | compensated for this. */ | |
21686 | if (value & 3) | |
21687 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21688 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
21689 | (((unsigned long) fixP->fx_frag->fr_address |
21690 | + (unsigned long) fixP->fx_where) & ~3) | |
21691 | + (unsigned long) value); | |
a737bd4d | 21692 | |
c19d1205 ZW |
21693 | if (value & ~0x3fc) |
21694 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21695 | _("invalid offset, value too big (0x%08lX)"), | |
21696 | (long) value); | |
a737bd4d | 21697 | |
c19d1205 ZW |
21698 | newval |= value >> 2; |
21699 | break; | |
a737bd4d | 21700 | |
c19d1205 ZW |
21701 | case 9: /* SP load/store. */ |
21702 | if (value & ~0x3fc) | |
21703 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21704 | _("invalid offset, value too big (0x%08lX)"), | |
21705 | (long) value); | |
21706 | newval |= value >> 2; | |
21707 | break; | |
6c43fab6 | 21708 | |
c19d1205 ZW |
21709 | case 6: /* Word load/store. */ |
21710 | if (value & ~0x7c) | |
21711 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21712 | _("invalid offset, value too big (0x%08lX)"), | |
21713 | (long) value); | |
21714 | newval |= value << 4; /* 6 - 2. */ | |
21715 | break; | |
a737bd4d | 21716 | |
c19d1205 ZW |
21717 | case 7: /* Byte load/store. */ |
21718 | if (value & ~0x1f) | |
21719 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21720 | _("invalid offset, value too big (0x%08lX)"), | |
21721 | (long) value); | |
21722 | newval |= value << 6; | |
21723 | break; | |
a737bd4d | 21724 | |
c19d1205 ZW |
21725 | case 8: /* Halfword load/store. */ |
21726 | if (value & ~0x3e) | |
21727 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21728 | _("invalid offset, value too big (0x%08lX)"), | |
21729 | (long) value); | |
21730 | newval |= value << 5; /* 6 - 1. */ | |
21731 | break; | |
a737bd4d | 21732 | |
c19d1205 ZW |
21733 | default: |
21734 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21735 | "Unable to process relocation for thumb opcode: %lx", | |
21736 | (unsigned long) newval); | |
21737 | break; | |
21738 | } | |
21739 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21740 | break; | |
a737bd4d | 21741 | |
c19d1205 ZW |
21742 | case BFD_RELOC_ARM_THUMB_ADD: |
21743 | /* This is a complicated relocation, since we use it for all of | |
21744 | the following immediate relocations: | |
a737bd4d | 21745 | |
c19d1205 ZW |
21746 | 3bit ADD/SUB |
21747 | 8bit ADD/SUB | |
21748 | 9bit ADD/SUB SP word-aligned | |
21749 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 21750 | |
c19d1205 ZW |
21751 | The type of instruction being processed is encoded in the |
21752 | instruction field: | |
a737bd4d | 21753 | |
c19d1205 ZW |
21754 | 0x8000 SUB |
21755 | 0x00F0 Rd | |
21756 | 0x000F Rs | |
21757 | */ | |
21758 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21759 | { | |
21760 | int rd = (newval >> 4) & 0xf; | |
21761 | int rs = newval & 0xf; | |
21762 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 21763 | |
c19d1205 ZW |
21764 | /* Check for HI regs, only very restricted cases allowed: |
21765 | Adjusting SP, and using PC or SP to get an address. */ | |
21766 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
21767 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
21768 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21769 | _("invalid Hi register with immediate")); | |
a737bd4d | 21770 | |
c19d1205 ZW |
21771 | /* If value is negative, choose the opposite instruction. */ |
21772 | if (value < 0) | |
21773 | { | |
21774 | value = -value; | |
21775 | subtract = !subtract; | |
21776 | if (value < 0) | |
21777 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21778 | _("immediate value out of range")); | |
21779 | } | |
a737bd4d | 21780 | |
c19d1205 ZW |
21781 | if (rd == REG_SP) |
21782 | { | |
21783 | if (value & ~0x1fc) | |
21784 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21785 | _("invalid immediate for stack address calculation")); | |
21786 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
21787 | newval |= value >> 2; | |
21788 | } | |
21789 | else if (rs == REG_PC || rs == REG_SP) | |
21790 | { | |
21791 | if (subtract || value & ~0x3fc) | |
21792 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21793 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
21794 | (unsigned long) value); | |
21795 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
21796 | newval |= rd << 8; | |
21797 | newval |= value >> 2; | |
21798 | } | |
21799 | else if (rs == rd) | |
21800 | { | |
21801 | if (value & ~0xff) | |
21802 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21803 | _("immediate value out of range")); | |
21804 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
21805 | newval |= (rd << 8) | value; | |
21806 | } | |
21807 | else | |
21808 | { | |
21809 | if (value & ~0x7) | |
21810 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21811 | _("immediate value out of range")); | |
21812 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
21813 | newval |= rd | (rs << 3) | (value << 6); | |
21814 | } | |
21815 | } | |
21816 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21817 | break; | |
a737bd4d | 21818 | |
c19d1205 ZW |
21819 | case BFD_RELOC_ARM_THUMB_IMM: |
21820 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21821 | if (value < 0 || value > 255) | |
21822 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 21823 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
21824 | (long) value); |
21825 | newval |= value; | |
21826 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21827 | break; | |
a737bd4d | 21828 | |
c19d1205 ZW |
21829 | case BFD_RELOC_ARM_THUMB_SHIFT: |
21830 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
21831 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
21832 | temp = newval & 0xf800; | |
21833 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
21834 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21835 | _("invalid shift value: %ld"), (long) value); | |
21836 | /* Shifts of zero must be encoded as LSL. */ | |
21837 | if (value == 0) | |
21838 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
21839 | /* Shifts of 32 are encoded as zero. */ | |
21840 | else if (value == 32) | |
21841 | value = 0; | |
21842 | newval |= value << 6; | |
21843 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21844 | break; | |
a737bd4d | 21845 | |
c19d1205 ZW |
21846 | case BFD_RELOC_VTABLE_INHERIT: |
21847 | case BFD_RELOC_VTABLE_ENTRY: | |
21848 | fixP->fx_done = 0; | |
21849 | return; | |
6c43fab6 | 21850 | |
b6895b4f PB |
21851 | case BFD_RELOC_ARM_MOVW: |
21852 | case BFD_RELOC_ARM_MOVT: | |
21853 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21854 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21855 | if (fixP->fx_done || !seg->use_rela_p) | |
21856 | { | |
21857 | /* REL format relocations are limited to a 16-bit addend. */ | |
21858 | if (!fixP->fx_done) | |
21859 | { | |
39623e12 | 21860 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 21861 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 21862 | _("offset out of range")); |
b6895b4f PB |
21863 | } |
21864 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21865 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21866 | { | |
21867 | value >>= 16; | |
21868 | } | |
21869 | ||
21870 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21871 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21872 | { | |
21873 | newval = get_thumb32_insn (buf); | |
21874 | newval &= 0xfbf08f00; | |
21875 | newval |= (value & 0xf000) << 4; | |
21876 | newval |= (value & 0x0800) << 15; | |
21877 | newval |= (value & 0x0700) << 4; | |
21878 | newval |= (value & 0x00ff); | |
21879 | put_thumb32_insn (buf, newval); | |
21880 | } | |
21881 | else | |
21882 | { | |
21883 | newval = md_chars_to_number (buf, 4); | |
21884 | newval &= 0xfff0f000; | |
21885 | newval |= value & 0x0fff; | |
21886 | newval |= (value & 0xf000) << 4; | |
21887 | md_number_to_chars (buf, newval, 4); | |
21888 | } | |
21889 | } | |
21890 | return; | |
21891 | ||
4962c51a MS |
21892 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21893 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21894 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21895 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21896 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21897 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21898 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21899 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21900 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21901 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 21902 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21903 | if (!seg->use_rela_p) |
21904 | { | |
21905 | bfd_vma insn; | |
21906 | bfd_vma encoded_addend; | |
21907 | bfd_vma addend_abs = abs (value); | |
21908 | ||
21909 | /* Check that the absolute value of the addend can be | |
21910 | expressed as an 8-bit constant plus a rotation. */ | |
21911 | encoded_addend = encode_arm_immediate (addend_abs); | |
21912 | if (encoded_addend == (unsigned int) FAIL) | |
21913 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21914 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 21915 | (unsigned long) addend_abs); |
4962c51a MS |
21916 | |
21917 | /* Extract the instruction. */ | |
21918 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21919 | ||
21920 | /* If the addend is positive, use an ADD instruction. | |
21921 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
21922 | insn &= 0xff1fffff; | |
21923 | if (value < 0) | |
21924 | insn |= 1 << 22; | |
21925 | else | |
21926 | insn |= 1 << 23; | |
21927 | ||
21928 | /* Place the encoded addend into the first 12 bits of the | |
21929 | instruction. */ | |
21930 | insn &= 0xfffff000; | |
21931 | insn |= encoded_addend; | |
5f4273c7 NC |
21932 | |
21933 | /* Update the instruction. */ | |
4962c51a MS |
21934 | md_number_to_chars (buf, insn, INSN_SIZE); |
21935 | } | |
21936 | break; | |
21937 | ||
21938 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21939 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21940 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21941 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21942 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21943 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 21944 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21945 | if (!seg->use_rela_p) |
21946 | { | |
21947 | bfd_vma insn; | |
21948 | bfd_vma addend_abs = abs (value); | |
21949 | ||
21950 | /* Check that the absolute value of the addend can be | |
21951 | encoded in 12 bits. */ | |
21952 | if (addend_abs >= 0x1000) | |
21953 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21954 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 21955 | (unsigned long) addend_abs); |
4962c51a MS |
21956 | |
21957 | /* Extract the instruction. */ | |
21958 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21959 | ||
21960 | /* If the addend is negative, clear bit 23 of the instruction. | |
21961 | Otherwise set it. */ | |
21962 | if (value < 0) | |
21963 | insn &= ~(1 << 23); | |
21964 | else | |
21965 | insn |= 1 << 23; | |
21966 | ||
21967 | /* Place the absolute value of the addend into the first 12 bits | |
21968 | of the instruction. */ | |
21969 | insn &= 0xfffff000; | |
21970 | insn |= addend_abs; | |
5f4273c7 NC |
21971 | |
21972 | /* Update the instruction. */ | |
4962c51a MS |
21973 | md_number_to_chars (buf, insn, INSN_SIZE); |
21974 | } | |
21975 | break; | |
21976 | ||
21977 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21978 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21979 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21980 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21981 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21982 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 21983 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21984 | if (!seg->use_rela_p) |
21985 | { | |
21986 | bfd_vma insn; | |
21987 | bfd_vma addend_abs = abs (value); | |
21988 | ||
21989 | /* Check that the absolute value of the addend can be | |
21990 | encoded in 8 bits. */ | |
21991 | if (addend_abs >= 0x100) | |
21992 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21993 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 21994 | (unsigned long) addend_abs); |
4962c51a MS |
21995 | |
21996 | /* Extract the instruction. */ | |
21997 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21998 | ||
21999 | /* If the addend is negative, clear bit 23 of the instruction. | |
22000 | Otherwise set it. */ | |
22001 | if (value < 0) | |
22002 | insn &= ~(1 << 23); | |
22003 | else | |
22004 | insn |= 1 << 23; | |
22005 | ||
22006 | /* Place the first four bits of the absolute value of the addend | |
22007 | into the first 4 bits of the instruction, and the remaining | |
22008 | four into bits 8 .. 11. */ | |
22009 | insn &= 0xfffff0f0; | |
22010 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
22011 | |
22012 | /* Update the instruction. */ | |
4962c51a MS |
22013 | md_number_to_chars (buf, insn, INSN_SIZE); |
22014 | } | |
22015 | break; | |
22016 | ||
22017 | case BFD_RELOC_ARM_LDC_PC_G0: | |
22018 | case BFD_RELOC_ARM_LDC_PC_G1: | |
22019 | case BFD_RELOC_ARM_LDC_PC_G2: | |
22020 | case BFD_RELOC_ARM_LDC_SB_G0: | |
22021 | case BFD_RELOC_ARM_LDC_SB_G1: | |
22022 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 22023 | gas_assert (!fixP->fx_done); |
4962c51a MS |
22024 | if (!seg->use_rela_p) |
22025 | { | |
22026 | bfd_vma insn; | |
22027 | bfd_vma addend_abs = abs (value); | |
22028 | ||
22029 | /* Check that the absolute value of the addend is a multiple of | |
22030 | four and, when divided by four, fits in 8 bits. */ | |
22031 | if (addend_abs & 0x3) | |
22032 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22033 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 22034 | (unsigned long) addend_abs); |
4962c51a MS |
22035 | |
22036 | if ((addend_abs >> 2) > 0xff) | |
22037 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22038 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 22039 | (unsigned long) addend_abs); |
4962c51a MS |
22040 | |
22041 | /* Extract the instruction. */ | |
22042 | insn = md_chars_to_number (buf, INSN_SIZE); | |
22043 | ||
22044 | /* If the addend is negative, clear bit 23 of the instruction. | |
22045 | Otherwise set it. */ | |
22046 | if (value < 0) | |
22047 | insn &= ~(1 << 23); | |
22048 | else | |
22049 | insn |= 1 << 23; | |
22050 | ||
22051 | /* Place the addend (divided by four) into the first eight | |
22052 | bits of the instruction. */ | |
22053 | insn &= 0xfffffff0; | |
22054 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
22055 | |
22056 | /* Update the instruction. */ | |
4962c51a MS |
22057 | md_number_to_chars (buf, insn, INSN_SIZE); |
22058 | } | |
22059 | break; | |
22060 | ||
845b51d6 PB |
22061 | case BFD_RELOC_ARM_V4BX: |
22062 | /* This will need to go in the object file. */ | |
22063 | fixP->fx_done = 0; | |
22064 | break; | |
22065 | ||
c19d1205 ZW |
22066 | case BFD_RELOC_UNUSED: |
22067 | default: | |
22068 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22069 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
22070 | } | |
6c43fab6 RE |
22071 | } |
22072 | ||
c19d1205 ZW |
22073 | /* Translate internal representation of relocation info to BFD target |
22074 | format. */ | |
a737bd4d | 22075 | |
c19d1205 | 22076 | arelent * |
00a97672 | 22077 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 22078 | { |
c19d1205 ZW |
22079 | arelent * reloc; |
22080 | bfd_reloc_code_real_type code; | |
a737bd4d | 22081 | |
21d799b5 | 22082 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 22083 | |
21d799b5 | 22084 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
22085 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
22086 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 22087 | |
2fc8bdac | 22088 | if (fixp->fx_pcrel) |
00a97672 RS |
22089 | { |
22090 | if (section->use_rela_p) | |
22091 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
22092 | else | |
22093 | fixp->fx_offset = reloc->address; | |
22094 | } | |
c19d1205 | 22095 | reloc->addend = fixp->fx_offset; |
a737bd4d | 22096 | |
c19d1205 | 22097 | switch (fixp->fx_r_type) |
a737bd4d | 22098 | { |
c19d1205 ZW |
22099 | case BFD_RELOC_8: |
22100 | if (fixp->fx_pcrel) | |
22101 | { | |
22102 | code = BFD_RELOC_8_PCREL; | |
22103 | break; | |
22104 | } | |
a737bd4d | 22105 | |
c19d1205 ZW |
22106 | case BFD_RELOC_16: |
22107 | if (fixp->fx_pcrel) | |
22108 | { | |
22109 | code = BFD_RELOC_16_PCREL; | |
22110 | break; | |
22111 | } | |
6c43fab6 | 22112 | |
c19d1205 ZW |
22113 | case BFD_RELOC_32: |
22114 | if (fixp->fx_pcrel) | |
22115 | { | |
22116 | code = BFD_RELOC_32_PCREL; | |
22117 | break; | |
22118 | } | |
a737bd4d | 22119 | |
b6895b4f PB |
22120 | case BFD_RELOC_ARM_MOVW: |
22121 | if (fixp->fx_pcrel) | |
22122 | { | |
22123 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
22124 | break; | |
22125 | } | |
22126 | ||
22127 | case BFD_RELOC_ARM_MOVT: | |
22128 | if (fixp->fx_pcrel) | |
22129 | { | |
22130 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
22131 | break; | |
22132 | } | |
22133 | ||
22134 | case BFD_RELOC_ARM_THUMB_MOVW: | |
22135 | if (fixp->fx_pcrel) | |
22136 | { | |
22137 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
22138 | break; | |
22139 | } | |
22140 | ||
22141 | case BFD_RELOC_ARM_THUMB_MOVT: | |
22142 | if (fixp->fx_pcrel) | |
22143 | { | |
22144 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
22145 | break; | |
22146 | } | |
22147 | ||
c19d1205 ZW |
22148 | case BFD_RELOC_NONE: |
22149 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
22150 | case BFD_RELOC_ARM_PCREL_BLX: | |
22151 | case BFD_RELOC_RVA: | |
22152 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
22153 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
22154 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
22155 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
22156 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
22157 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
22158 | case BFD_RELOC_VTABLE_ENTRY: |
22159 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
22160 | #ifdef TE_PE |
22161 | case BFD_RELOC_32_SECREL: | |
22162 | #endif | |
c19d1205 ZW |
22163 | code = fixp->fx_r_type; |
22164 | break; | |
a737bd4d | 22165 | |
00adf2d4 JB |
22166 | case BFD_RELOC_THUMB_PCREL_BLX: |
22167 | #ifdef OBJ_ELF | |
22168 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
22169 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22170 | else | |
22171 | #endif | |
22172 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
22173 | break; | |
22174 | ||
c19d1205 ZW |
22175 | case BFD_RELOC_ARM_LITERAL: |
22176 | case BFD_RELOC_ARM_HWLITERAL: | |
22177 | /* If this is called then the a literal has | |
22178 | been referenced across a section boundary. */ | |
22179 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22180 | _("literal referenced across section boundary")); | |
22181 | return NULL; | |
a737bd4d | 22182 | |
c19d1205 | 22183 | #ifdef OBJ_ELF |
0855e32b NS |
22184 | case BFD_RELOC_ARM_TLS_CALL: |
22185 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
22186 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
22187 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
22188 | case BFD_RELOC_ARM_GOT32: |
22189 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 22190 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
22191 | case BFD_RELOC_ARM_PLT32: |
22192 | case BFD_RELOC_ARM_TARGET1: | |
22193 | case BFD_RELOC_ARM_ROSEGREL32: | |
22194 | case BFD_RELOC_ARM_SBREL32: | |
22195 | case BFD_RELOC_ARM_PREL31: | |
22196 | case BFD_RELOC_ARM_TARGET2: | |
22197 | case BFD_RELOC_ARM_TLS_LE32: | |
22198 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
22199 | case BFD_RELOC_ARM_PCREL_CALL: |
22200 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
22201 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
22202 | case BFD_RELOC_ARM_ALU_PC_G0: | |
22203 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
22204 | case BFD_RELOC_ARM_ALU_PC_G1: | |
22205 | case BFD_RELOC_ARM_ALU_PC_G2: | |
22206 | case BFD_RELOC_ARM_LDR_PC_G0: | |
22207 | case BFD_RELOC_ARM_LDR_PC_G1: | |
22208 | case BFD_RELOC_ARM_LDR_PC_G2: | |
22209 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
22210 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
22211 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
22212 | case BFD_RELOC_ARM_LDC_PC_G0: | |
22213 | case BFD_RELOC_ARM_LDC_PC_G1: | |
22214 | case BFD_RELOC_ARM_LDC_PC_G2: | |
22215 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
22216 | case BFD_RELOC_ARM_ALU_SB_G0: | |
22217 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
22218 | case BFD_RELOC_ARM_ALU_SB_G1: | |
22219 | case BFD_RELOC_ARM_ALU_SB_G2: | |
22220 | case BFD_RELOC_ARM_LDR_SB_G0: | |
22221 | case BFD_RELOC_ARM_LDR_SB_G1: | |
22222 | case BFD_RELOC_ARM_LDR_SB_G2: | |
22223 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
22224 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
22225 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
22226 | case BFD_RELOC_ARM_LDC_SB_G0: | |
22227 | case BFD_RELOC_ARM_LDC_SB_G1: | |
22228 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 22229 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
22230 | code = fixp->fx_r_type; |
22231 | break; | |
a737bd4d | 22232 | |
0855e32b | 22233 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
22234 | case BFD_RELOC_ARM_TLS_GD32: |
22235 | case BFD_RELOC_ARM_TLS_IE32: | |
22236 | case BFD_RELOC_ARM_TLS_LDM32: | |
22237 | /* BFD will include the symbol's address in the addend. | |
22238 | But we don't want that, so subtract it out again here. */ | |
22239 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
22240 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
22241 | code = fixp->fx_r_type; | |
22242 | break; | |
22243 | #endif | |
a737bd4d | 22244 | |
c19d1205 ZW |
22245 | case BFD_RELOC_ARM_IMMEDIATE: |
22246 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22247 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
22248 | return NULL; | |
a737bd4d | 22249 | |
c19d1205 ZW |
22250 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
22251 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22252 | _("ADRL used for a symbol not defined in the same file")); | |
22253 | return NULL; | |
a737bd4d | 22254 | |
c19d1205 | 22255 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
22256 | if (section->use_rela_p) |
22257 | { | |
22258 | code = fixp->fx_r_type; | |
22259 | break; | |
22260 | } | |
22261 | ||
c19d1205 ZW |
22262 | if (fixp->fx_addsy != NULL |
22263 | && !S_IS_DEFINED (fixp->fx_addsy) | |
22264 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 22265 | { |
c19d1205 ZW |
22266 | as_bad_where (fixp->fx_file, fixp->fx_line, |
22267 | _("undefined local label `%s'"), | |
22268 | S_GET_NAME (fixp->fx_addsy)); | |
22269 | return NULL; | |
a737bd4d NC |
22270 | } |
22271 | ||
c19d1205 ZW |
22272 | as_bad_where (fixp->fx_file, fixp->fx_line, |
22273 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
22274 | return NULL; | |
a737bd4d | 22275 | |
c19d1205 ZW |
22276 | default: |
22277 | { | |
22278 | char * type; | |
6c43fab6 | 22279 | |
c19d1205 ZW |
22280 | switch (fixp->fx_r_type) |
22281 | { | |
22282 | case BFD_RELOC_NONE: type = "NONE"; break; | |
22283 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
22284 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 22285 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
22286 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
22287 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
22288 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 22289 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 22290 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
22291 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
22292 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
22293 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
22294 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
22295 | default: type = _("<unknown>"); break; | |
22296 | } | |
22297 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22298 | _("cannot represent %s relocation in this object file format"), | |
22299 | type); | |
22300 | return NULL; | |
22301 | } | |
a737bd4d | 22302 | } |
6c43fab6 | 22303 | |
c19d1205 ZW |
22304 | #ifdef OBJ_ELF |
22305 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
22306 | && GOT_symbol | |
22307 | && fixp->fx_addsy == GOT_symbol) | |
22308 | { | |
22309 | code = BFD_RELOC_ARM_GOTPC; | |
22310 | reloc->addend = fixp->fx_offset = reloc->address; | |
22311 | } | |
22312 | #endif | |
6c43fab6 | 22313 | |
c19d1205 | 22314 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 22315 | |
c19d1205 ZW |
22316 | if (reloc->howto == NULL) |
22317 | { | |
22318 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22319 | _("cannot represent %s relocation in this object file format"), | |
22320 | bfd_get_reloc_code_name (code)); | |
22321 | return NULL; | |
22322 | } | |
6c43fab6 | 22323 | |
c19d1205 ZW |
22324 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
22325 | vtable entry to be used in the relocation's section offset. */ | |
22326 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
22327 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 22328 | |
c19d1205 | 22329 | return reloc; |
6c43fab6 RE |
22330 | } |
22331 | ||
c19d1205 | 22332 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 22333 | |
c19d1205 ZW |
22334 | void |
22335 | cons_fix_new_arm (fragS * frag, | |
22336 | int where, | |
22337 | int size, | |
22338 | expressionS * exp) | |
6c43fab6 | 22339 | { |
c19d1205 ZW |
22340 | bfd_reloc_code_real_type type; |
22341 | int pcrel = 0; | |
6c43fab6 | 22342 | |
c19d1205 ZW |
22343 | /* Pick a reloc. |
22344 | FIXME: @@ Should look at CPU word size. */ | |
22345 | switch (size) | |
22346 | { | |
22347 | case 1: | |
22348 | type = BFD_RELOC_8; | |
22349 | break; | |
22350 | case 2: | |
22351 | type = BFD_RELOC_16; | |
22352 | break; | |
22353 | case 4: | |
22354 | default: | |
22355 | type = BFD_RELOC_32; | |
22356 | break; | |
22357 | case 8: | |
22358 | type = BFD_RELOC_64; | |
22359 | break; | |
22360 | } | |
6c43fab6 | 22361 | |
f0927246 NC |
22362 | #ifdef TE_PE |
22363 | if (exp->X_op == O_secrel) | |
22364 | { | |
22365 | exp->X_op = O_symbol; | |
22366 | type = BFD_RELOC_32_SECREL; | |
22367 | } | |
22368 | #endif | |
22369 | ||
c19d1205 ZW |
22370 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
22371 | } | |
6c43fab6 | 22372 | |
4343666d | 22373 | #if defined (OBJ_COFF) |
c19d1205 ZW |
22374 | void |
22375 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 22376 | { |
c19d1205 ZW |
22377 | /* If the destination of the branch is a defined symbol which does not have |
22378 | the THUMB_FUNC attribute, then we must be calling a function which has | |
22379 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
22380 | function and change the branch to refer to that function instead. */ | |
22381 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
22382 | && fixP->fx_addsy != NULL | |
22383 | && S_IS_DEFINED (fixP->fx_addsy) | |
22384 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 22385 | { |
c19d1205 | 22386 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 22387 | } |
c19d1205 ZW |
22388 | } |
22389 | #endif | |
6c43fab6 | 22390 | |
267bf995 | 22391 | |
c19d1205 ZW |
22392 | int |
22393 | arm_force_relocation (struct fix * fixp) | |
22394 | { | |
22395 | #if defined (OBJ_COFF) && defined (TE_PE) | |
22396 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
22397 | return 1; | |
22398 | #endif | |
6c43fab6 | 22399 | |
267bf995 RR |
22400 | /* In case we have a call or a branch to a function in ARM ISA mode from |
22401 | a thumb function or vice-versa force the relocation. These relocations | |
22402 | are cleared off for some cores that might have blx and simple transformations | |
22403 | are possible. */ | |
22404 | ||
22405 | #ifdef OBJ_ELF | |
22406 | switch (fixp->fx_r_type) | |
22407 | { | |
22408 | case BFD_RELOC_ARM_PCREL_JUMP: | |
22409 | case BFD_RELOC_ARM_PCREL_CALL: | |
22410 | case BFD_RELOC_THUMB_PCREL_BLX: | |
22411 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
22412 | return 1; | |
22413 | break; | |
22414 | ||
22415 | case BFD_RELOC_ARM_PCREL_BLX: | |
22416 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
22417 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
22418 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
22419 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
22420 | return 1; | |
22421 | break; | |
22422 | ||
22423 | default: | |
22424 | break; | |
22425 | } | |
22426 | #endif | |
22427 | ||
b5884301 PB |
22428 | /* Resolve these relocations even if the symbol is extern or weak. |
22429 | Technically this is probably wrong due to symbol preemption. | |
22430 | In practice these relocations do not have enough range to be useful | |
22431 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
22432 | expects these references to be resolved. */ | |
c19d1205 ZW |
22433 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
22434 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 22435 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 22436 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
22437 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22438 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
22439 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 22440 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
22441 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
22442 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
22443 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
22444 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
22445 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
22446 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 22447 | return 0; |
a737bd4d | 22448 | |
4962c51a MS |
22449 | /* Always leave these relocations for the linker. */ |
22450 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22451 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22452 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
22453 | return 1; | |
22454 | ||
f0291e4c PB |
22455 | /* Always generate relocations against function symbols. */ |
22456 | if (fixp->fx_r_type == BFD_RELOC_32 | |
22457 | && fixp->fx_addsy | |
22458 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
22459 | return 1; | |
22460 | ||
c19d1205 | 22461 | return generic_force_reloc (fixp); |
404ff6b5 AH |
22462 | } |
22463 | ||
0ffdc86c | 22464 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
22465 | /* Relocations against function names must be left unadjusted, |
22466 | so that the linker can use this information to generate interworking | |
22467 | stubs. The MIPS version of this function | |
c19d1205 ZW |
22468 | also prevents relocations that are mips-16 specific, but I do not |
22469 | know why it does this. | |
404ff6b5 | 22470 | |
c19d1205 ZW |
22471 | FIXME: |
22472 | There is one other problem that ought to be addressed here, but | |
22473 | which currently is not: Taking the address of a label (rather | |
22474 | than a function) and then later jumping to that address. Such | |
22475 | addresses also ought to have their bottom bit set (assuming that | |
22476 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 22477 | |
c19d1205 ZW |
22478 | bfd_boolean |
22479 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 22480 | { |
c19d1205 ZW |
22481 | if (fixP->fx_addsy == NULL) |
22482 | return 1; | |
404ff6b5 | 22483 | |
e28387c3 PB |
22484 | /* Preserve relocations against symbols with function type. */ |
22485 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 22486 | return FALSE; |
e28387c3 | 22487 | |
c19d1205 ZW |
22488 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
22489 | && fixP->fx_subsy == NULL) | |
c921be7d | 22490 | return FALSE; |
a737bd4d | 22491 | |
c19d1205 ZW |
22492 | /* We need the symbol name for the VTABLE entries. */ |
22493 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
22494 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 22495 | return FALSE; |
404ff6b5 | 22496 | |
c19d1205 ZW |
22497 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
22498 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
22499 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
22500 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
22501 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
22502 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
22503 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
22504 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
22505 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
22506 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
22507 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
22508 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
22509 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
22510 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 22511 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 22512 | return FALSE; |
a737bd4d | 22513 | |
4962c51a MS |
22514 | /* Similarly for group relocations. */ |
22515 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22516 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22517 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 22518 | return FALSE; |
4962c51a | 22519 | |
79947c54 CD |
22520 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
22521 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
22522 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
22523 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
22524 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
22525 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
22526 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
22527 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
22528 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 22529 | return FALSE; |
79947c54 | 22530 | |
c921be7d | 22531 | return TRUE; |
a737bd4d | 22532 | } |
0ffdc86c NC |
22533 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
22534 | ||
22535 | #ifdef OBJ_ELF | |
404ff6b5 | 22536 | |
c19d1205 ZW |
22537 | const char * |
22538 | elf32_arm_target_format (void) | |
404ff6b5 | 22539 | { |
c19d1205 ZW |
22540 | #ifdef TE_SYMBIAN |
22541 | return (target_big_endian | |
22542 | ? "elf32-bigarm-symbian" | |
22543 | : "elf32-littlearm-symbian"); | |
22544 | #elif defined (TE_VXWORKS) | |
22545 | return (target_big_endian | |
22546 | ? "elf32-bigarm-vxworks" | |
22547 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
22548 | #elif defined (TE_NACL) |
22549 | return (target_big_endian | |
22550 | ? "elf32-bigarm-nacl" | |
22551 | : "elf32-littlearm-nacl"); | |
c19d1205 ZW |
22552 | #else |
22553 | if (target_big_endian) | |
22554 | return "elf32-bigarm"; | |
22555 | else | |
22556 | return "elf32-littlearm"; | |
22557 | #endif | |
404ff6b5 AH |
22558 | } |
22559 | ||
c19d1205 ZW |
22560 | void |
22561 | armelf_frob_symbol (symbolS * symp, | |
22562 | int * puntp) | |
404ff6b5 | 22563 | { |
c19d1205 ZW |
22564 | elf_frob_symbol (symp, puntp); |
22565 | } | |
22566 | #endif | |
404ff6b5 | 22567 | |
c19d1205 | 22568 | /* MD interface: Finalization. */ |
a737bd4d | 22569 | |
c19d1205 ZW |
22570 | void |
22571 | arm_cleanup (void) | |
22572 | { | |
22573 | literal_pool * pool; | |
a737bd4d | 22574 | |
e07e6e58 NC |
22575 | /* Ensure that all the IT blocks are properly closed. */ |
22576 | check_it_blocks_finished (); | |
22577 | ||
c19d1205 ZW |
22578 | for (pool = list_of_pools; pool; pool = pool->next) |
22579 | { | |
5f4273c7 | 22580 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
22581 | subseg_set (pool->section, pool->sub_section); |
22582 | #ifdef OBJ_ELF | |
22583 | arm_elf_change_section (); | |
22584 | #endif | |
22585 | s_ltorg (0); | |
22586 | } | |
404ff6b5 AH |
22587 | } |
22588 | ||
cd000bff DJ |
22589 | #ifdef OBJ_ELF |
22590 | /* Remove any excess mapping symbols generated for alignment frags in | |
22591 | SEC. We may have created a mapping symbol before a zero byte | |
22592 | alignment; remove it if there's a mapping symbol after the | |
22593 | alignment. */ | |
22594 | static void | |
22595 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
22596 | void *dummy ATTRIBUTE_UNUSED) | |
22597 | { | |
22598 | segment_info_type *seginfo = seg_info (sec); | |
22599 | fragS *fragp; | |
22600 | ||
22601 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
22602 | return; | |
22603 | ||
22604 | for (fragp = seginfo->frchainP->frch_root; | |
22605 | fragp != NULL; | |
22606 | fragp = fragp->fr_next) | |
22607 | { | |
22608 | symbolS *sym = fragp->tc_frag_data.last_map; | |
22609 | fragS *next = fragp->fr_next; | |
22610 | ||
22611 | /* Variable-sized frags have been converted to fixed size by | |
22612 | this point. But if this was variable-sized to start with, | |
22613 | there will be a fixed-size frag after it. So don't handle | |
22614 | next == NULL. */ | |
22615 | if (sym == NULL || next == NULL) | |
22616 | continue; | |
22617 | ||
22618 | if (S_GET_VALUE (sym) < next->fr_address) | |
22619 | /* Not at the end of this frag. */ | |
22620 | continue; | |
22621 | know (S_GET_VALUE (sym) == next->fr_address); | |
22622 | ||
22623 | do | |
22624 | { | |
22625 | if (next->tc_frag_data.first_map != NULL) | |
22626 | { | |
22627 | /* Next frag starts with a mapping symbol. Discard this | |
22628 | one. */ | |
22629 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22630 | break; | |
22631 | } | |
22632 | ||
22633 | if (next->fr_next == NULL) | |
22634 | { | |
22635 | /* This mapping symbol is at the end of the section. Discard | |
22636 | it. */ | |
22637 | know (next->fr_fix == 0 && next->fr_var == 0); | |
22638 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22639 | break; | |
22640 | } | |
22641 | ||
22642 | /* As long as we have empty frags without any mapping symbols, | |
22643 | keep looking. */ | |
22644 | /* If the next frag is non-empty and does not start with a | |
22645 | mapping symbol, then this mapping symbol is required. */ | |
22646 | if (next->fr_address != next->fr_next->fr_address) | |
22647 | break; | |
22648 | ||
22649 | next = next->fr_next; | |
22650 | } | |
22651 | while (next != NULL); | |
22652 | } | |
22653 | } | |
22654 | #endif | |
22655 | ||
c19d1205 ZW |
22656 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
22657 | ARM ones. */ | |
404ff6b5 | 22658 | |
c19d1205 ZW |
22659 | void |
22660 | arm_adjust_symtab (void) | |
404ff6b5 | 22661 | { |
c19d1205 ZW |
22662 | #ifdef OBJ_COFF |
22663 | symbolS * sym; | |
404ff6b5 | 22664 | |
c19d1205 ZW |
22665 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
22666 | { | |
22667 | if (ARM_IS_THUMB (sym)) | |
22668 | { | |
22669 | if (THUMB_IS_FUNC (sym)) | |
22670 | { | |
22671 | /* Mark the symbol as a Thumb function. */ | |
22672 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
22673 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
22674 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 22675 | |
c19d1205 ZW |
22676 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
22677 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
22678 | else | |
22679 | as_bad (_("%s: unexpected function type: %d"), | |
22680 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
22681 | } | |
22682 | else switch (S_GET_STORAGE_CLASS (sym)) | |
22683 | { | |
22684 | case C_EXT: | |
22685 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
22686 | break; | |
22687 | case C_STAT: | |
22688 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
22689 | break; | |
22690 | case C_LABEL: | |
22691 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
22692 | break; | |
22693 | default: | |
22694 | /* Do nothing. */ | |
22695 | break; | |
22696 | } | |
22697 | } | |
a737bd4d | 22698 | |
c19d1205 ZW |
22699 | if (ARM_IS_INTERWORK (sym)) |
22700 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 22701 | } |
c19d1205 ZW |
22702 | #endif |
22703 | #ifdef OBJ_ELF | |
22704 | symbolS * sym; | |
22705 | char bind; | |
404ff6b5 | 22706 | |
c19d1205 | 22707 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 22708 | { |
c19d1205 ZW |
22709 | if (ARM_IS_THUMB (sym)) |
22710 | { | |
22711 | elf_symbol_type * elf_sym; | |
404ff6b5 | 22712 | |
c19d1205 ZW |
22713 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
22714 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 22715 | |
b0796911 PB |
22716 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
22717 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
22718 | { |
22719 | /* If it's a .thumb_func, declare it as so, | |
22720 | otherwise tag label as .code 16. */ | |
22721 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
22722 | elf_sym->internal_elf_sym.st_target_internal |
22723 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 22724 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
22725 | elf_sym->internal_elf_sym.st_info = |
22726 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
22727 | } | |
22728 | } | |
22729 | } | |
cd000bff DJ |
22730 | |
22731 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
22732 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
22733 | /* Now do generic ELF adjustments. */ |
22734 | elf_adjust_symtab (); | |
c19d1205 | 22735 | #endif |
404ff6b5 AH |
22736 | } |
22737 | ||
c19d1205 | 22738 | /* MD interface: Initialization. */ |
404ff6b5 | 22739 | |
a737bd4d | 22740 | static void |
c19d1205 | 22741 | set_constant_flonums (void) |
a737bd4d | 22742 | { |
c19d1205 | 22743 | int i; |
404ff6b5 | 22744 | |
c19d1205 ZW |
22745 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
22746 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
22747 | abort (); | |
a737bd4d | 22748 | } |
404ff6b5 | 22749 | |
3e9e4fcf JB |
22750 | /* Auto-select Thumb mode if it's the only available instruction set for the |
22751 | given architecture. */ | |
22752 | ||
22753 | static void | |
22754 | autoselect_thumb_from_cpu_variant (void) | |
22755 | { | |
22756 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
22757 | opcode_select (16); | |
22758 | } | |
22759 | ||
c19d1205 ZW |
22760 | void |
22761 | md_begin (void) | |
a737bd4d | 22762 | { |
c19d1205 ZW |
22763 | unsigned mach; |
22764 | unsigned int i; | |
404ff6b5 | 22765 | |
c19d1205 ZW |
22766 | if ( (arm_ops_hsh = hash_new ()) == NULL |
22767 | || (arm_cond_hsh = hash_new ()) == NULL | |
22768 | || (arm_shift_hsh = hash_new ()) == NULL | |
22769 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 22770 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 22771 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
22772 | || (arm_reloc_hsh = hash_new ()) == NULL |
22773 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
22774 | as_fatal (_("virtual memory exhausted")); |
22775 | ||
22776 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 22777 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 22778 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 22779 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 22780 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 22781 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 22782 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 22783 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 22784 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
22785 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
22786 | (void *) (v7m_psrs + i)); | |
c19d1205 | 22787 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 22788 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
22789 | for (i = 0; |
22790 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
22791 | i++) | |
d3ce72d0 | 22792 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 22793 | (void *) (barrier_opt_names + i)); |
c19d1205 | 22794 | #ifdef OBJ_ELF |
3da1d841 NC |
22795 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
22796 | { | |
22797 | struct reloc_entry * entry = reloc_names + i; | |
22798 | ||
22799 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
22800 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
22801 | entry->reloc = BFD_RELOC_UNUSED; | |
22802 | ||
22803 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
22804 | } | |
c19d1205 ZW |
22805 | #endif |
22806 | ||
22807 | set_constant_flonums (); | |
404ff6b5 | 22808 | |
c19d1205 ZW |
22809 | /* Set the cpu variant based on the command-line options. We prefer |
22810 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
22811 | -mfpu= over any other way of setting the floating point unit. | |
22812 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 22813 | if (legacy_cpu) |
404ff6b5 | 22814 | { |
e74cfd16 | 22815 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
22816 | as_bad (_("use of old and new-style options to set CPU type")); |
22817 | ||
22818 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 22819 | } |
e74cfd16 | 22820 | else if (!mcpu_cpu_opt) |
c19d1205 | 22821 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 22822 | |
e74cfd16 | 22823 | if (legacy_fpu) |
c19d1205 | 22824 | { |
e74cfd16 | 22825 | if (mfpu_opt) |
c19d1205 | 22826 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
22827 | |
22828 | mfpu_opt = legacy_fpu; | |
22829 | } | |
e74cfd16 | 22830 | else if (!mfpu_opt) |
03b1477f | 22831 | { |
45eb4c1b NS |
22832 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
22833 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
22834 | /* Some environments specify a default FPU. If they don't, infer it |
22835 | from the processor. */ | |
e74cfd16 | 22836 | if (mcpu_fpu_opt) |
03b1477f RE |
22837 | mfpu_opt = mcpu_fpu_opt; |
22838 | else | |
22839 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 22840 | #else |
e74cfd16 | 22841 | mfpu_opt = &fpu_default; |
39c2da32 | 22842 | #endif |
03b1477f RE |
22843 | } |
22844 | ||
e74cfd16 | 22845 | if (!mfpu_opt) |
03b1477f | 22846 | { |
493cb6ef | 22847 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 22848 | mfpu_opt = &fpu_default; |
493cb6ef | 22849 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 22850 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 22851 | else |
e74cfd16 | 22852 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
22853 | } |
22854 | ||
ee065d83 | 22855 | #ifdef CPU_DEFAULT |
e74cfd16 | 22856 | if (!mcpu_cpu_opt) |
ee065d83 | 22857 | { |
e74cfd16 PB |
22858 | mcpu_cpu_opt = &cpu_default; |
22859 | selected_cpu = cpu_default; | |
ee065d83 | 22860 | } |
e74cfd16 PB |
22861 | #else |
22862 | if (mcpu_cpu_opt) | |
22863 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 22864 | else |
e74cfd16 | 22865 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 22866 | #endif |
03b1477f | 22867 | |
e74cfd16 | 22868 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 22869 | |
3e9e4fcf JB |
22870 | autoselect_thumb_from_cpu_variant (); |
22871 | ||
e74cfd16 | 22872 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 22873 | |
f17c130b | 22874 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 22875 | { |
7cc69913 NC |
22876 | unsigned int flags = 0; |
22877 | ||
22878 | #if defined OBJ_ELF | |
22879 | flags = meabi_flags; | |
d507cf36 PB |
22880 | |
22881 | switch (meabi_flags) | |
33a392fb | 22882 | { |
d507cf36 | 22883 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 22884 | #endif |
d507cf36 PB |
22885 | /* Set the flags in the private structure. */ |
22886 | if (uses_apcs_26) flags |= F_APCS26; | |
22887 | if (support_interwork) flags |= F_INTERWORK; | |
22888 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 22889 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 22890 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
22891 | flags |= F_SOFT_FLOAT; |
22892 | ||
d507cf36 PB |
22893 | switch (mfloat_abi_opt) |
22894 | { | |
22895 | case ARM_FLOAT_ABI_SOFT: | |
22896 | case ARM_FLOAT_ABI_SOFTFP: | |
22897 | flags |= F_SOFT_FLOAT; | |
22898 | break; | |
33a392fb | 22899 | |
d507cf36 PB |
22900 | case ARM_FLOAT_ABI_HARD: |
22901 | if (flags & F_SOFT_FLOAT) | |
22902 | as_bad (_("hard-float conflicts with specified fpu")); | |
22903 | break; | |
22904 | } | |
03b1477f | 22905 | |
e74cfd16 PB |
22906 | /* Using pure-endian doubles (even if soft-float). */ |
22907 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 22908 | flags |= F_VFP_FLOAT; |
f17c130b | 22909 | |
fde78edd | 22910 | #if defined OBJ_ELF |
e74cfd16 | 22911 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 22912 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
22913 | break; |
22914 | ||
8cb51566 | 22915 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 22916 | case EF_ARM_EABI_VER5: |
c19d1205 | 22917 | /* No additional flags to set. */ |
d507cf36 PB |
22918 | break; |
22919 | ||
22920 | default: | |
22921 | abort (); | |
22922 | } | |
7cc69913 | 22923 | #endif |
b99bd4ef NC |
22924 | bfd_set_private_flags (stdoutput, flags); |
22925 | ||
22926 | /* We have run out flags in the COFF header to encode the | |
22927 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 22928 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
22929 | if (atpcs) |
22930 | { | |
22931 | asection * sec; | |
22932 | ||
22933 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
22934 | ||
22935 | if (sec != NULL) | |
22936 | { | |
22937 | bfd_set_section_flags | |
22938 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
22939 | bfd_set_section_size (stdoutput, sec, 0); | |
22940 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
22941 | } | |
22942 | } | |
7cc69913 | 22943 | } |
f17c130b | 22944 | #endif |
b99bd4ef NC |
22945 | |
22946 | /* Record the CPU type as well. */ | |
2d447fca JM |
22947 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
22948 | mach = bfd_mach_arm_iWMMXt2; | |
22949 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 22950 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 22951 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 22952 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 22953 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 22954 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 22955 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 22956 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 22957 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 22958 | { |
e74cfd16 | 22959 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22960 | mach = bfd_mach_arm_5T; |
22961 | else | |
22962 | mach = bfd_mach_arm_5; | |
22963 | } | |
e74cfd16 | 22964 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 22965 | { |
e74cfd16 | 22966 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22967 | mach = bfd_mach_arm_4T; |
22968 | else | |
22969 | mach = bfd_mach_arm_4; | |
22970 | } | |
e74cfd16 | 22971 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 22972 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
22973 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
22974 | mach = bfd_mach_arm_3; | |
22975 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
22976 | mach = bfd_mach_arm_2a; | |
22977 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
22978 | mach = bfd_mach_arm_2; | |
22979 | else | |
22980 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
22981 | |
22982 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
22983 | } | |
22984 | ||
c19d1205 | 22985 | /* Command line processing. */ |
b99bd4ef | 22986 | |
c19d1205 ZW |
22987 | /* md_parse_option |
22988 | Invocation line includes a switch not recognized by the base assembler. | |
22989 | See if it's a processor-specific option. | |
b99bd4ef | 22990 | |
c19d1205 ZW |
22991 | This routine is somewhat complicated by the need for backwards |
22992 | compatibility (since older releases of gcc can't be changed). | |
22993 | The new options try to make the interface as compatible as | |
22994 | possible with GCC. | |
b99bd4ef | 22995 | |
c19d1205 | 22996 | New options (supported) are: |
b99bd4ef | 22997 | |
c19d1205 ZW |
22998 | -mcpu=<cpu name> Assemble for selected processor |
22999 | -march=<architecture name> Assemble for selected architecture | |
23000 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
23001 | -EB/-mbig-endian Big-endian | |
23002 | -EL/-mlittle-endian Little-endian | |
23003 | -k Generate PIC code | |
23004 | -mthumb Start in Thumb mode | |
23005 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 23006 | |
278df34e | 23007 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 23008 | |
c19d1205 | 23009 | For now we will also provide support for: |
b99bd4ef | 23010 | |
c19d1205 ZW |
23011 | -mapcs-32 32-bit Program counter |
23012 | -mapcs-26 26-bit Program counter | |
23013 | -macps-float Floats passed in FP registers | |
23014 | -mapcs-reentrant Reentrant code | |
23015 | -matpcs | |
23016 | (sometime these will probably be replaced with -mapcs=<list of options> | |
23017 | and -matpcs=<list of options>) | |
b99bd4ef | 23018 | |
c19d1205 ZW |
23019 | The remaining options are only supported for back-wards compatibility. |
23020 | Cpu variants, the arm part is optional: | |
23021 | -m[arm]1 Currently not supported. | |
23022 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
23023 | -m[arm]3 Arm 3 processor | |
23024 | -m[arm]6[xx], Arm 6 processors | |
23025 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
23026 | -m[arm]8[10] Arm 8 processors | |
23027 | -m[arm]9[20][tdmi] Arm 9 processors | |
23028 | -mstrongarm[110[0]] StrongARM processors | |
23029 | -mxscale XScale processors | |
23030 | -m[arm]v[2345[t[e]]] Arm architectures | |
23031 | -mall All (except the ARM1) | |
23032 | FP variants: | |
23033 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
23034 | -mfpe-old (No float load/store multiples) | |
23035 | -mvfpxd VFP Single precision | |
23036 | -mvfp All VFP | |
23037 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 23038 | |
c19d1205 ZW |
23039 | The following CPU names are recognized: |
23040 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
23041 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
23042 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
23043 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
23044 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
23045 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
23046 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 23047 | |
c19d1205 | 23048 | */ |
b99bd4ef | 23049 | |
c19d1205 | 23050 | const char * md_shortopts = "m:k"; |
b99bd4ef | 23051 | |
c19d1205 ZW |
23052 | #ifdef ARM_BI_ENDIAN |
23053 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
23054 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 23055 | #else |
c19d1205 ZW |
23056 | #if TARGET_BYTES_BIG_ENDIAN |
23057 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 23058 | #else |
c19d1205 ZW |
23059 | #define OPTION_EL (OPTION_MD_BASE + 1) |
23060 | #endif | |
b99bd4ef | 23061 | #endif |
845b51d6 | 23062 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 23063 | |
c19d1205 | 23064 | struct option md_longopts[] = |
b99bd4ef | 23065 | { |
c19d1205 ZW |
23066 | #ifdef OPTION_EB |
23067 | {"EB", no_argument, NULL, OPTION_EB}, | |
23068 | #endif | |
23069 | #ifdef OPTION_EL | |
23070 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 23071 | #endif |
845b51d6 | 23072 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
23073 | {NULL, no_argument, NULL, 0} |
23074 | }; | |
b99bd4ef | 23075 | |
c19d1205 | 23076 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 23077 | |
c19d1205 | 23078 | struct arm_option_table |
b99bd4ef | 23079 | { |
c19d1205 ZW |
23080 | char *option; /* Option name to match. */ |
23081 | char *help; /* Help information. */ | |
23082 | int *var; /* Variable to change. */ | |
23083 | int value; /* What to change it to. */ | |
23084 | char *deprecated; /* If non-null, print this message. */ | |
23085 | }; | |
b99bd4ef | 23086 | |
c19d1205 ZW |
23087 | struct arm_option_table arm_opts[] = |
23088 | { | |
23089 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
23090 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
23091 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
23092 | &support_interwork, 1, NULL}, | |
23093 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
23094 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
23095 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
23096 | 1, NULL}, | |
23097 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
23098 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
23099 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
23100 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
23101 | NULL}, | |
b99bd4ef | 23102 | |
c19d1205 ZW |
23103 | /* These are recognized by the assembler, but have no affect on code. */ |
23104 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
23105 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
23106 | |
23107 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
23108 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
23109 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
23110 | {NULL, NULL, NULL, 0, NULL} |
23111 | }; | |
23112 | ||
23113 | struct arm_legacy_option_table | |
23114 | { | |
23115 | char *option; /* Option name to match. */ | |
23116 | const arm_feature_set **var; /* Variable to change. */ | |
23117 | const arm_feature_set value; /* What to change it to. */ | |
23118 | char *deprecated; /* If non-null, print this message. */ | |
23119 | }; | |
b99bd4ef | 23120 | |
e74cfd16 PB |
23121 | const struct arm_legacy_option_table arm_legacy_opts[] = |
23122 | { | |
c19d1205 ZW |
23123 | /* DON'T add any new processors to this list -- we want the whole list |
23124 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
23125 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
23126 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
23127 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
23128 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
23129 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
23130 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
23131 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
23132 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
23133 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
23134 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
23135 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
23136 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
23137 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
23138 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
23139 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
23140 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
23141 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
23142 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
23143 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
23144 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
23145 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
23146 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
23147 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
23148 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
23149 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
23150 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
23151 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
23152 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
23153 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
23154 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
23155 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
23156 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
23157 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
23158 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
23159 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
23160 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
23161 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
23162 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
23163 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
23164 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
23165 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
23166 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
23167 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
23168 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
23169 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
23170 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
23171 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23172 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23173 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23174 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23175 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
23176 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
23177 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
23178 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
23179 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
23180 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
23181 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
23182 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
23183 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
23184 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
23185 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
23186 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
23187 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
23188 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
23189 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
23190 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
23191 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
23192 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
23193 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
23194 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 23195 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 23196 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 23197 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 23198 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 23199 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
23200 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
23201 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
23202 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 23203 | |
c19d1205 | 23204 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
23205 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
23206 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
23207 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
23208 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
23209 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
23210 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
23211 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
23212 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
23213 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
23214 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
23215 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
23216 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
23217 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
23218 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
23219 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
23220 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
23221 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
23222 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 23223 | |
c19d1205 | 23224 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
23225 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
23226 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
23227 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
23228 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 23229 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 23230 | |
e74cfd16 | 23231 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 23232 | }; |
7ed4c4c5 | 23233 | |
c19d1205 | 23234 | struct arm_cpu_option_table |
7ed4c4c5 | 23235 | { |
c19d1205 | 23236 | char *name; |
f3bad469 | 23237 | size_t name_len; |
e74cfd16 | 23238 | const arm_feature_set value; |
c19d1205 ZW |
23239 | /* For some CPUs we assume an FPU unless the user explicitly sets |
23240 | -mfpu=... */ | |
e74cfd16 | 23241 | const arm_feature_set default_fpu; |
ee065d83 PB |
23242 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
23243 | case. */ | |
23244 | const char *canonical_name; | |
c19d1205 | 23245 | }; |
7ed4c4c5 | 23246 | |
c19d1205 ZW |
23247 | /* This list should, at a minimum, contain all the cpu names |
23248 | recognized by GCC. */ | |
f3bad469 | 23249 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 23250 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 23251 | { |
f3bad469 MGD |
23252 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
23253 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
23254 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
23255 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
23256 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
23257 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23258 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23259 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23260 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23261 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23262 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23263 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
23264 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23265 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
23266 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23267 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
23268 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23269 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23270 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23271 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23272 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23273 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23274 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23275 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23276 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23277 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23278 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23279 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23280 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23281 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23282 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23283 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23284 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23285 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23286 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23287 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23288 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23289 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23290 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23291 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
23292 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23293 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23294 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23295 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23296 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23297 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
23298 | /* For V5 or later processors we default to using VFP; but the user |
23299 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
23300 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
23301 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23302 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
23303 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
23304 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
23305 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
23306 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
23307 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23308 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
23309 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
23310 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23311 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23312 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
23313 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
23314 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23315 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
23316 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
23317 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23318 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23319 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
23320 | "ARM1026EJ-S"), | |
23321 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
23322 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23323 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23324 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23325 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23326 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23327 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
23328 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
23329 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
23330 | "ARM1136JF-S"), | |
23331 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
23332 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
23333 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
23334 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
23335 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
23336 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL), | |
23337 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL), | |
23338 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, | |
23339 | FPU_NONE, "Cortex-A5"), | |
23340 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, | |
23341 | FPU_ARCH_NEON_VFP_V4, | |
23342 | "Cortex-A7"), | |
23343 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
23344 | ARM_FEATURE (0, FPU_VFP_V3 | |
5287ad62 | 23345 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
23346 | "Cortex-A8"), |
23347 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
23348 | ARM_FEATURE (0, FPU_VFP_V3 | |
15290f0a | 23349 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
23350 | "Cortex-A9"), |
23351 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, | |
23352 | FPU_ARCH_NEON_VFP_V4, | |
23353 | "Cortex-A15"), | |
23354 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), | |
23355 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
23356 | "Cortex-R4F"), | |
23357 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
23358 | FPU_NONE, "Cortex-R5"), | |
23359 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), | |
23360 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
23361 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
23362 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
ce32bd10 | 23363 | ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), |
c19d1205 | 23364 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 23365 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 23366 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
23367 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
23368 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
23369 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 23370 | /* Maverick */ |
f3bad469 MGD |
23371 | ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
23372 | FPU_ARCH_MAVERICK, | |
23373 | "ARM920T"), | |
23374 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } | |
c19d1205 | 23375 | }; |
f3bad469 | 23376 | #undef ARM_CPU_OPT |
7ed4c4c5 | 23377 | |
c19d1205 | 23378 | struct arm_arch_option_table |
7ed4c4c5 | 23379 | { |
c19d1205 | 23380 | char *name; |
f3bad469 | 23381 | size_t name_len; |
e74cfd16 PB |
23382 | const arm_feature_set value; |
23383 | const arm_feature_set default_fpu; | |
c19d1205 | 23384 | }; |
7ed4c4c5 | 23385 | |
c19d1205 ZW |
23386 | /* This list should, at a minimum, contain all the architecture names |
23387 | recognized by GCC. */ | |
f3bad469 | 23388 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 23389 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 23390 | { |
f3bad469 MGD |
23391 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
23392 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
23393 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
23394 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
23395 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
23396 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
23397 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
23398 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
23399 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
23400 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
23401 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
23402 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
23403 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
23404 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
23405 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
23406 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
23407 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
23408 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
23409 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
23410 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
23411 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
23412 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP), | |
23413 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
23414 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
23415 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
23416 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP), | |
23417 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
23418 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
23419 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
23420 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
23421 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 MGD |
23422 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
23423 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
23424 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
23425 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
23426 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
23427 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
23428 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
bca38921 | 23429 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), |
f3bad469 MGD |
23430 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
23431 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
23432 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
23433 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 23434 | }; |
f3bad469 | 23435 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 23436 | |
69133863 MGD |
23437 | /* ISA extensions in the co-processor and main instruction set space. */ |
23438 | struct arm_option_extension_value_table | |
c19d1205 ZW |
23439 | { |
23440 | char *name; | |
f3bad469 | 23441 | size_t name_len; |
e74cfd16 | 23442 | const arm_feature_set value; |
69133863 | 23443 | const arm_feature_set allowed_archs; |
c19d1205 | 23444 | }; |
7ed4c4c5 | 23445 | |
69133863 MGD |
23446 | /* The following table must be in alphabetical order with a NULL last entry. |
23447 | */ | |
f3bad469 | 23448 | #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA } |
69133863 | 23449 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 23450 | { |
bca38921 MGD |
23451 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
23452 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
23453 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, | |
23454 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
f3bad469 MGD |
23455 | ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
23456 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
23457 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), | |
23458 | ARM_EXT_OPT ("iwmmxt2", | |
23459 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY), | |
23460 | ARM_EXT_OPT ("maverick", | |
23461 | ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), | |
23462 | ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), | |
23463 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
bca38921 MGD |
23464 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
23465 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
f3bad469 MGD |
23466 | ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), |
23467 | ARM_FEATURE (ARM_EXT_V6M, 0)), | |
23468 | ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), | |
23469 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)), | |
23470 | ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | |
23471 | | ARM_EXT_DIV, 0), | |
23472 | ARM_FEATURE (ARM_EXT_V7A, 0)), | |
23473 | ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY), | |
23474 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
69133863 | 23475 | }; |
f3bad469 | 23476 | #undef ARM_EXT_OPT |
69133863 MGD |
23477 | |
23478 | /* ISA floating-point and Advanced SIMD extensions. */ | |
23479 | struct arm_option_fpu_value_table | |
23480 | { | |
23481 | char *name; | |
23482 | const arm_feature_set value; | |
c19d1205 | 23483 | }; |
7ed4c4c5 | 23484 | |
c19d1205 ZW |
23485 | /* This list should, at a minimum, contain all the fpu names |
23486 | recognized by GCC. */ | |
69133863 | 23487 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
23488 | { |
23489 | {"softfpa", FPU_NONE}, | |
23490 | {"fpe", FPU_ARCH_FPE}, | |
23491 | {"fpe2", FPU_ARCH_FPE}, | |
23492 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
23493 | {"fpa", FPU_ARCH_FPA}, | |
23494 | {"fpa10", FPU_ARCH_FPA}, | |
23495 | {"fpa11", FPU_ARCH_FPA}, | |
23496 | {"arm7500fe", FPU_ARCH_FPA}, | |
23497 | {"softvfp", FPU_ARCH_VFP}, | |
23498 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
23499 | {"vfp", FPU_ARCH_VFP_V2}, | |
23500 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 23501 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
23502 | {"vfp10", FPU_ARCH_VFP_V2}, |
23503 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
23504 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
23505 | {"vfpv2", FPU_ARCH_VFP_V2}, |
23506 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 23507 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 23508 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
23509 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
23510 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
23511 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
23512 | {"arm1020t", FPU_ARCH_VFP_V1}, |
23513 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
23514 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
23515 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
23516 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 23517 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 23518 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
23519 | {"vfpv4", FPU_ARCH_VFP_V4}, |
23520 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 23521 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 23522 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
23523 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
23524 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
23525 | {"crypto-neon-fp-armv8", | |
23526 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
e74cfd16 PB |
23527 | {NULL, ARM_ARCH_NONE} |
23528 | }; | |
23529 | ||
23530 | struct arm_option_value_table | |
23531 | { | |
23532 | char *name; | |
23533 | long value; | |
c19d1205 | 23534 | }; |
7ed4c4c5 | 23535 | |
e74cfd16 | 23536 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
23537 | { |
23538 | {"hard", ARM_FLOAT_ABI_HARD}, | |
23539 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
23540 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 23541 | {NULL, 0} |
c19d1205 | 23542 | }; |
7ed4c4c5 | 23543 | |
c19d1205 | 23544 | #ifdef OBJ_ELF |
3a4a14e9 | 23545 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 23546 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
23547 | { |
23548 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
23549 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 23550 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 23551 | {NULL, 0} |
c19d1205 ZW |
23552 | }; |
23553 | #endif | |
7ed4c4c5 | 23554 | |
c19d1205 ZW |
23555 | struct arm_long_option_table |
23556 | { | |
23557 | char * option; /* Substring to match. */ | |
23558 | char * help; /* Help information. */ | |
23559 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
23560 | char * deprecated; /* If non-null, print this message. */ | |
23561 | }; | |
7ed4c4c5 | 23562 | |
c921be7d | 23563 | static bfd_boolean |
f3bad469 | 23564 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 23565 | { |
21d799b5 NC |
23566 | arm_feature_set *ext_set = (arm_feature_set *) |
23567 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 23568 | |
69133863 | 23569 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
23570 | extensions being added before being removed. We achieve this by having |
23571 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 23572 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 23573 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
23574 | -1 -> 1 -> 0. */ |
23575 | const struct arm_option_extension_value_table * opt = NULL; | |
23576 | int adding_value = -1; | |
23577 | ||
e74cfd16 PB |
23578 | /* Copy the feature set, so that we can modify it. */ |
23579 | *ext_set = **opt_p; | |
23580 | *opt_p = ext_set; | |
23581 | ||
c19d1205 | 23582 | while (str != NULL && *str != 0) |
7ed4c4c5 | 23583 | { |
f3bad469 MGD |
23584 | char *ext; |
23585 | size_t len; | |
7ed4c4c5 | 23586 | |
c19d1205 ZW |
23587 | if (*str != '+') |
23588 | { | |
23589 | as_bad (_("invalid architectural extension")); | |
c921be7d | 23590 | return FALSE; |
c19d1205 | 23591 | } |
7ed4c4c5 | 23592 | |
c19d1205 ZW |
23593 | str++; |
23594 | ext = strchr (str, '+'); | |
7ed4c4c5 | 23595 | |
c19d1205 | 23596 | if (ext != NULL) |
f3bad469 | 23597 | len = ext - str; |
c19d1205 | 23598 | else |
f3bad469 | 23599 | len = strlen (str); |
7ed4c4c5 | 23600 | |
f3bad469 | 23601 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
23602 | { |
23603 | if (adding_value != 0) | |
23604 | { | |
23605 | adding_value = 0; | |
23606 | opt = arm_extensions; | |
23607 | } | |
23608 | ||
f3bad469 | 23609 | len -= 2; |
69133863 MGD |
23610 | str += 2; |
23611 | } | |
f3bad469 | 23612 | else if (len > 0) |
69133863 MGD |
23613 | { |
23614 | if (adding_value == -1) | |
23615 | { | |
23616 | adding_value = 1; | |
23617 | opt = arm_extensions; | |
23618 | } | |
23619 | else if (adding_value != 1) | |
23620 | { | |
23621 | as_bad (_("must specify extensions to add before specifying " | |
23622 | "those to remove")); | |
23623 | return FALSE; | |
23624 | } | |
23625 | } | |
23626 | ||
f3bad469 | 23627 | if (len == 0) |
c19d1205 ZW |
23628 | { |
23629 | as_bad (_("missing architectural extension")); | |
c921be7d | 23630 | return FALSE; |
c19d1205 | 23631 | } |
7ed4c4c5 | 23632 | |
69133863 MGD |
23633 | gas_assert (adding_value != -1); |
23634 | gas_assert (opt != NULL); | |
23635 | ||
23636 | /* Scan over the options table trying to find an exact match. */ | |
23637 | for (; opt->name != NULL; opt++) | |
f3bad469 | 23638 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23639 | { |
69133863 MGD |
23640 | /* Check we can apply the extension to this architecture. */ |
23641 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
23642 | { | |
23643 | as_bad (_("extension does not apply to the base architecture")); | |
23644 | return FALSE; | |
23645 | } | |
23646 | ||
23647 | /* Add or remove the extension. */ | |
23648 | if (adding_value) | |
23649 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); | |
23650 | else | |
23651 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); | |
23652 | ||
c19d1205 ZW |
23653 | break; |
23654 | } | |
7ed4c4c5 | 23655 | |
c19d1205 ZW |
23656 | if (opt->name == NULL) |
23657 | { | |
69133863 MGD |
23658 | /* Did we fail to find an extension because it wasn't specified in |
23659 | alphabetical order, or because it does not exist? */ | |
23660 | ||
23661 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 23662 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
23663 | break; |
23664 | ||
23665 | if (opt->name == NULL) | |
23666 | as_bad (_("unknown architectural extension `%s'"), str); | |
23667 | else | |
23668 | as_bad (_("architectural extensions must be specified in " | |
23669 | "alphabetical order")); | |
23670 | ||
c921be7d | 23671 | return FALSE; |
c19d1205 | 23672 | } |
69133863 MGD |
23673 | else |
23674 | { | |
23675 | /* We should skip the extension we've just matched the next time | |
23676 | round. */ | |
23677 | opt++; | |
23678 | } | |
7ed4c4c5 | 23679 | |
c19d1205 ZW |
23680 | str = ext; |
23681 | }; | |
7ed4c4c5 | 23682 | |
c921be7d | 23683 | return TRUE; |
c19d1205 | 23684 | } |
7ed4c4c5 | 23685 | |
c921be7d | 23686 | static bfd_boolean |
f3bad469 | 23687 | arm_parse_cpu (char *str) |
7ed4c4c5 | 23688 | { |
f3bad469 MGD |
23689 | const struct arm_cpu_option_table *opt; |
23690 | char *ext = strchr (str, '+'); | |
23691 | size_t len; | |
7ed4c4c5 | 23692 | |
c19d1205 | 23693 | if (ext != NULL) |
f3bad469 | 23694 | len = ext - str; |
7ed4c4c5 | 23695 | else |
f3bad469 | 23696 | len = strlen (str); |
7ed4c4c5 | 23697 | |
f3bad469 | 23698 | if (len == 0) |
7ed4c4c5 | 23699 | { |
c19d1205 | 23700 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 23701 | return FALSE; |
7ed4c4c5 NC |
23702 | } |
23703 | ||
c19d1205 | 23704 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 23705 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23706 | { |
e74cfd16 PB |
23707 | mcpu_cpu_opt = &opt->value; |
23708 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 23709 | if (opt->canonical_name) |
5f4273c7 | 23710 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23711 | else |
23712 | { | |
f3bad469 | 23713 | size_t i; |
c921be7d | 23714 | |
f3bad469 | 23715 | for (i = 0; i < len; i++) |
ee065d83 PB |
23716 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
23717 | selected_cpu_name[i] = 0; | |
23718 | } | |
7ed4c4c5 | 23719 | |
c19d1205 ZW |
23720 | if (ext != NULL) |
23721 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 23722 | |
c921be7d | 23723 | return TRUE; |
c19d1205 | 23724 | } |
7ed4c4c5 | 23725 | |
c19d1205 | 23726 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 23727 | return FALSE; |
7ed4c4c5 NC |
23728 | } |
23729 | ||
c921be7d | 23730 | static bfd_boolean |
f3bad469 | 23731 | arm_parse_arch (char *str) |
7ed4c4c5 | 23732 | { |
e74cfd16 | 23733 | const struct arm_arch_option_table *opt; |
c19d1205 | 23734 | char *ext = strchr (str, '+'); |
f3bad469 | 23735 | size_t len; |
7ed4c4c5 | 23736 | |
c19d1205 | 23737 | if (ext != NULL) |
f3bad469 | 23738 | len = ext - str; |
7ed4c4c5 | 23739 | else |
f3bad469 | 23740 | len = strlen (str); |
7ed4c4c5 | 23741 | |
f3bad469 | 23742 | if (len == 0) |
7ed4c4c5 | 23743 | { |
c19d1205 | 23744 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 23745 | return FALSE; |
7ed4c4c5 NC |
23746 | } |
23747 | ||
c19d1205 | 23748 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 23749 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23750 | { |
e74cfd16 PB |
23751 | march_cpu_opt = &opt->value; |
23752 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 23753 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 23754 | |
c19d1205 ZW |
23755 | if (ext != NULL) |
23756 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 23757 | |
c921be7d | 23758 | return TRUE; |
c19d1205 ZW |
23759 | } |
23760 | ||
23761 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 23762 | return FALSE; |
7ed4c4c5 | 23763 | } |
eb043451 | 23764 | |
c921be7d | 23765 | static bfd_boolean |
c19d1205 ZW |
23766 | arm_parse_fpu (char * str) |
23767 | { | |
69133863 | 23768 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 23769 | |
c19d1205 ZW |
23770 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23771 | if (streq (opt->name, str)) | |
23772 | { | |
e74cfd16 | 23773 | mfpu_opt = &opt->value; |
c921be7d | 23774 | return TRUE; |
c19d1205 | 23775 | } |
b99bd4ef | 23776 | |
c19d1205 | 23777 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 23778 | return FALSE; |
c19d1205 ZW |
23779 | } |
23780 | ||
c921be7d | 23781 | static bfd_boolean |
c19d1205 | 23782 | arm_parse_float_abi (char * str) |
b99bd4ef | 23783 | { |
e74cfd16 | 23784 | const struct arm_option_value_table * opt; |
b99bd4ef | 23785 | |
c19d1205 ZW |
23786 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
23787 | if (streq (opt->name, str)) | |
23788 | { | |
23789 | mfloat_abi_opt = opt->value; | |
c921be7d | 23790 | return TRUE; |
c19d1205 | 23791 | } |
cc8a6dd0 | 23792 | |
c19d1205 | 23793 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 23794 | return FALSE; |
c19d1205 | 23795 | } |
b99bd4ef | 23796 | |
c19d1205 | 23797 | #ifdef OBJ_ELF |
c921be7d | 23798 | static bfd_boolean |
c19d1205 ZW |
23799 | arm_parse_eabi (char * str) |
23800 | { | |
e74cfd16 | 23801 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 23802 | |
c19d1205 ZW |
23803 | for (opt = arm_eabis; opt->name != NULL; opt++) |
23804 | if (streq (opt->name, str)) | |
23805 | { | |
23806 | meabi_flags = opt->value; | |
c921be7d | 23807 | return TRUE; |
c19d1205 ZW |
23808 | } |
23809 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 23810 | return FALSE; |
c19d1205 ZW |
23811 | } |
23812 | #endif | |
cc8a6dd0 | 23813 | |
c921be7d | 23814 | static bfd_boolean |
e07e6e58 NC |
23815 | arm_parse_it_mode (char * str) |
23816 | { | |
c921be7d | 23817 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
23818 | |
23819 | if (streq ("arm", str)) | |
23820 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
23821 | else if (streq ("thumb", str)) | |
23822 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
23823 | else if (streq ("always", str)) | |
23824 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
23825 | else if (streq ("never", str)) | |
23826 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
23827 | else | |
23828 | { | |
23829 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
23830 | "arm, thumb, always, or never."), str); | |
c921be7d | 23831 | ret = FALSE; |
e07e6e58 NC |
23832 | } |
23833 | ||
23834 | return ret; | |
23835 | } | |
23836 | ||
c19d1205 ZW |
23837 | struct arm_long_option_table arm_long_opts[] = |
23838 | { | |
23839 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
23840 | arm_parse_cpu, NULL}, | |
23841 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
23842 | arm_parse_arch, NULL}, | |
23843 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
23844 | arm_parse_fpu, NULL}, | |
23845 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
23846 | arm_parse_float_abi, NULL}, | |
23847 | #ifdef OBJ_ELF | |
7fac0536 | 23848 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
23849 | arm_parse_eabi, NULL}, |
23850 | #endif | |
e07e6e58 NC |
23851 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
23852 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
23853 | {NULL, NULL, 0, NULL} |
23854 | }; | |
cc8a6dd0 | 23855 | |
c19d1205 ZW |
23856 | int |
23857 | md_parse_option (int c, char * arg) | |
23858 | { | |
23859 | struct arm_option_table *opt; | |
e74cfd16 | 23860 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 23861 | struct arm_long_option_table *lopt; |
b99bd4ef | 23862 | |
c19d1205 | 23863 | switch (c) |
b99bd4ef | 23864 | { |
c19d1205 ZW |
23865 | #ifdef OPTION_EB |
23866 | case OPTION_EB: | |
23867 | target_big_endian = 1; | |
23868 | break; | |
23869 | #endif | |
cc8a6dd0 | 23870 | |
c19d1205 ZW |
23871 | #ifdef OPTION_EL |
23872 | case OPTION_EL: | |
23873 | target_big_endian = 0; | |
23874 | break; | |
23875 | #endif | |
b99bd4ef | 23876 | |
845b51d6 PB |
23877 | case OPTION_FIX_V4BX: |
23878 | fix_v4bx = TRUE; | |
23879 | break; | |
23880 | ||
c19d1205 ZW |
23881 | case 'a': |
23882 | /* Listing option. Just ignore these, we don't support additional | |
23883 | ones. */ | |
23884 | return 0; | |
b99bd4ef | 23885 | |
c19d1205 ZW |
23886 | default: |
23887 | for (opt = arm_opts; opt->option != NULL; opt++) | |
23888 | { | |
23889 | if (c == opt->option[0] | |
23890 | && ((arg == NULL && opt->option[1] == 0) | |
23891 | || streq (arg, opt->option + 1))) | |
23892 | { | |
c19d1205 | 23893 | /* If the option is deprecated, tell the user. */ |
278df34e | 23894 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
23895 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23896 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 23897 | |
c19d1205 ZW |
23898 | if (opt->var != NULL) |
23899 | *opt->var = opt->value; | |
cc8a6dd0 | 23900 | |
c19d1205 ZW |
23901 | return 1; |
23902 | } | |
23903 | } | |
b99bd4ef | 23904 | |
e74cfd16 PB |
23905 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
23906 | { | |
23907 | if (c == fopt->option[0] | |
23908 | && ((arg == NULL && fopt->option[1] == 0) | |
23909 | || streq (arg, fopt->option + 1))) | |
23910 | { | |
e74cfd16 | 23911 | /* If the option is deprecated, tell the user. */ |
278df34e | 23912 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
23913 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23914 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
23915 | |
23916 | if (fopt->var != NULL) | |
23917 | *fopt->var = &fopt->value; | |
23918 | ||
23919 | return 1; | |
23920 | } | |
23921 | } | |
23922 | ||
c19d1205 ZW |
23923 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23924 | { | |
23925 | /* These options are expected to have an argument. */ | |
23926 | if (c == lopt->option[0] | |
23927 | && arg != NULL | |
23928 | && strncmp (arg, lopt->option + 1, | |
23929 | strlen (lopt->option + 1)) == 0) | |
23930 | { | |
c19d1205 | 23931 | /* If the option is deprecated, tell the user. */ |
278df34e | 23932 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
23933 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
23934 | _(lopt->deprecated)); | |
b99bd4ef | 23935 | |
c19d1205 ZW |
23936 | /* Call the sup-option parser. */ |
23937 | return lopt->func (arg + strlen (lopt->option) - 1); | |
23938 | } | |
23939 | } | |
a737bd4d | 23940 | |
c19d1205 ZW |
23941 | return 0; |
23942 | } | |
a394c00f | 23943 | |
c19d1205 ZW |
23944 | return 1; |
23945 | } | |
a394c00f | 23946 | |
c19d1205 ZW |
23947 | void |
23948 | md_show_usage (FILE * fp) | |
a394c00f | 23949 | { |
c19d1205 ZW |
23950 | struct arm_option_table *opt; |
23951 | struct arm_long_option_table *lopt; | |
a394c00f | 23952 | |
c19d1205 | 23953 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 23954 | |
c19d1205 ZW |
23955 | for (opt = arm_opts; opt->option != NULL; opt++) |
23956 | if (opt->help != NULL) | |
23957 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 23958 | |
c19d1205 ZW |
23959 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23960 | if (lopt->help != NULL) | |
23961 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 23962 | |
c19d1205 ZW |
23963 | #ifdef OPTION_EB |
23964 | fprintf (fp, _("\ | |
23965 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
23966 | #endif |
23967 | ||
c19d1205 ZW |
23968 | #ifdef OPTION_EL |
23969 | fprintf (fp, _("\ | |
23970 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 23971 | #endif |
845b51d6 PB |
23972 | |
23973 | fprintf (fp, _("\ | |
23974 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 23975 | } |
ee065d83 PB |
23976 | |
23977 | ||
23978 | #ifdef OBJ_ELF | |
62b3e311 PB |
23979 | typedef struct |
23980 | { | |
23981 | int val; | |
23982 | arm_feature_set flags; | |
23983 | } cpu_arch_ver_table; | |
23984 | ||
23985 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
23986 | least features first. */ | |
23987 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
23988 | { | |
23989 | {1, ARM_ARCH_V4}, | |
23990 | {2, ARM_ARCH_V4T}, | |
23991 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 23992 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
23993 | {4, ARM_ARCH_V5TE}, |
23994 | {5, ARM_ARCH_V5TEJ}, | |
23995 | {6, ARM_ARCH_V6}, | |
7e806470 | 23996 | {9, ARM_ARCH_V6K}, |
f4c65163 | 23997 | {7, ARM_ARCH_V6Z}, |
91e22acd | 23998 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 23999 | {12, ARM_ARCH_V6SM}, |
7e806470 | 24000 | {8, ARM_ARCH_V6T2}, |
bca38921 | 24001 | {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT}, |
62b3e311 PB |
24002 | {10, ARM_ARCH_V7R}, |
24003 | {10, ARM_ARCH_V7M}, | |
bca38921 | 24004 | {14, ARM_ARCH_V8A}, |
62b3e311 PB |
24005 | {0, ARM_ARCH_NONE} |
24006 | }; | |
24007 | ||
ee3c0378 AS |
24008 | /* Set an attribute if it has not already been set by the user. */ |
24009 | static void | |
24010 | aeabi_set_attribute_int (int tag, int value) | |
24011 | { | |
24012 | if (tag < 1 | |
24013 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
24014 | || !attributes_set_explicitly[tag]) | |
24015 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
24016 | } | |
24017 | ||
24018 | static void | |
24019 | aeabi_set_attribute_string (int tag, const char *value) | |
24020 | { | |
24021 | if (tag < 1 | |
24022 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
24023 | || !attributes_set_explicitly[tag]) | |
24024 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
24025 | } | |
24026 | ||
ee065d83 PB |
24027 | /* Set the public EABI object attributes. */ |
24028 | static void | |
24029 | aeabi_set_public_attributes (void) | |
24030 | { | |
24031 | int arch; | |
69239280 | 24032 | char profile; |
90ec0d68 | 24033 | int virt_sec = 0; |
bca38921 | 24034 | int fp16_optional = 0; |
e74cfd16 | 24035 | arm_feature_set flags; |
62b3e311 PB |
24036 | arm_feature_set tmp; |
24037 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
24038 | |
24039 | /* Choose the architecture based on the capabilities of the requested cpu | |
24040 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
24041 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
24042 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
24043 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
24044 | |
24045 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
24046 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
24047 | ||
24048 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
24049 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
24050 | ||
24051 | /* Allow the user to override the reported architecture. */ | |
7a1d4c38 PB |
24052 | if (object_arch) |
24053 | { | |
24054 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
24055 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
24056 | } | |
24057 | ||
251665fc MGD |
24058 | /* We need to make sure that the attributes do not identify us as v6S-M |
24059 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
24060 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
24061 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
24062 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); | |
24063 | ||
62b3e311 PB |
24064 | tmp = flags; |
24065 | arch = 0; | |
24066 | for (p = cpu_arch_ver; p->val; p++) | |
24067 | { | |
24068 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
24069 | { | |
24070 | arch = p->val; | |
24071 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
24072 | } | |
24073 | } | |
ee065d83 | 24074 | |
9e3c6df6 PB |
24075 | /* The table lookup above finds the last architecture to contribute |
24076 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
24077 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
24078 | We can not search for the last entry which is entirely used, | |
24079 | because if no CPU is specified we build up only those flags | |
24080 | actually used. Perhaps we should separate out the specified | |
24081 | and implicit cases. Avoid taking this path for -march=all by | |
24082 | checking for contradictory v7-A / v7-M features. */ | |
24083 | if (arch == 10 | |
24084 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
24085 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
24086 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
24087 | arch = 13; | |
24088 | ||
ee065d83 PB |
24089 | /* Tag_CPU_name. */ |
24090 | if (selected_cpu_name[0]) | |
24091 | { | |
91d6fa6a | 24092 | char *q; |
ee065d83 | 24093 | |
91d6fa6a NC |
24094 | q = selected_cpu_name; |
24095 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
24096 | { |
24097 | int i; | |
5f4273c7 | 24098 | |
91d6fa6a NC |
24099 | q += 4; |
24100 | for (i = 0; q[i]; i++) | |
24101 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 24102 | } |
91d6fa6a | 24103 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 24104 | } |
62f3b8c8 | 24105 | |
ee065d83 | 24106 | /* Tag_CPU_arch. */ |
ee3c0378 | 24107 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 24108 | |
62b3e311 PB |
24109 | /* Tag_CPU_arch_profile. */ |
24110 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
69239280 | 24111 | profile = 'A'; |
62b3e311 | 24112 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
69239280 | 24113 | profile = 'R'; |
7e806470 | 24114 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
69239280 MGD |
24115 | profile = 'M'; |
24116 | else | |
24117 | profile = '\0'; | |
24118 | ||
24119 | if (profile != '\0') | |
24120 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 24121 | |
ee065d83 | 24122 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
24123 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
24124 | || arch == 0) | |
24125 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 24126 | |
ee065d83 | 24127 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
24128 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
24129 | || arch == 0) | |
24130 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
24131 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 24132 | |
ee065d83 | 24133 | /* Tag_VFP_arch. */ |
bca38921 MGD |
24134 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8)) |
24135 | aeabi_set_attribute_int (Tag_VFP_arch, 7); | |
24136 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) | |
62f3b8c8 PB |
24137 | aeabi_set_attribute_int (Tag_VFP_arch, |
24138 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
24139 | ? 5 : 6); | |
24140 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
24141 | { |
24142 | fp16_optional = 1; | |
24143 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
24144 | } | |
ada65aa3 | 24145 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
24146 | { |
24147 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
24148 | fp16_optional = 1; | |
24149 | } | |
ee3c0378 AS |
24150 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
24151 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
24152 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
24153 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
24154 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 24155 | |
4547cb56 NC |
24156 | /* Tag_ABI_HardFP_use. */ |
24157 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
24158 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
24159 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
24160 | ||
ee065d83 | 24161 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
24162 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
24163 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
24164 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
24165 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 24166 | |
ee3c0378 | 24167 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
bca38921 MGD |
24168 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
24169 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); | |
24170 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
24171 | { | |
24172 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
24173 | { | |
24174 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
24175 | } | |
24176 | else | |
24177 | { | |
24178 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
24179 | fp16_optional = 1; | |
24180 | } | |
24181 | } | |
fa94de6b | 24182 | |
ee3c0378 | 24183 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 24184 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 24185 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 24186 | |
69239280 MGD |
24187 | /* Tag_DIV_use. |
24188 | ||
24189 | We set Tag_DIV_use to two when integer divide instructions have been used | |
24190 | in ARM state, or when Thumb integer divide instructions have been used, | |
24191 | but we have no architecture profile set, nor have we any ARM instructions. | |
24192 | ||
bca38921 MGD |
24193 | For ARMv8 we set the tag to 0 as integer divide is implied by the base |
24194 | architecture. | |
24195 | ||
69239280 | 24196 | For new architectures we will have to check these tests. */ |
bca38921 MGD |
24197 | gas_assert (arch <= TAG_CPU_ARCH_V8); |
24198 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) | |
24199 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
24200 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
24201 | || (profile == '\0' | |
24202 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
24203 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 24204 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
24205 | |
24206 | /* Tag_MP_extension_use. */ | |
24207 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
24208 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
24209 | |
24210 | /* Tag Virtualization_use. */ | |
24211 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
24212 | virt_sec |= 1; |
24213 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
24214 | virt_sec |= 2; | |
24215 | if (virt_sec != 0) | |
24216 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
24217 | } |
24218 | ||
104d59d1 | 24219 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
24220 | void |
24221 | arm_md_end (void) | |
24222 | { | |
ee065d83 PB |
24223 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
24224 | return; | |
24225 | ||
24226 | aeabi_set_public_attributes (); | |
ee065d83 | 24227 | } |
8463be01 | 24228 | #endif /* OBJ_ELF */ |
ee065d83 PB |
24229 | |
24230 | ||
24231 | /* Parse a .cpu directive. */ | |
24232 | ||
24233 | static void | |
24234 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
24235 | { | |
e74cfd16 | 24236 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
24237 | char *name; |
24238 | char saved_char; | |
24239 | ||
24240 | name = input_line_pointer; | |
5f4273c7 | 24241 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24242 | input_line_pointer++; |
24243 | saved_char = *input_line_pointer; | |
24244 | *input_line_pointer = 0; | |
24245 | ||
24246 | /* Skip the first "all" entry. */ | |
24247 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
24248 | if (streq (opt->name, name)) | |
24249 | { | |
e74cfd16 PB |
24250 | mcpu_cpu_opt = &opt->value; |
24251 | selected_cpu = opt->value; | |
ee065d83 | 24252 | if (opt->canonical_name) |
5f4273c7 | 24253 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
24254 | else |
24255 | { | |
24256 | int i; | |
24257 | for (i = 0; opt->name[i]; i++) | |
24258 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 24259 | |
ee065d83 PB |
24260 | selected_cpu_name[i] = 0; |
24261 | } | |
e74cfd16 | 24262 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
24263 | *input_line_pointer = saved_char; |
24264 | demand_empty_rest_of_line (); | |
24265 | return; | |
24266 | } | |
24267 | as_bad (_("unknown cpu `%s'"), name); | |
24268 | *input_line_pointer = saved_char; | |
24269 | ignore_rest_of_line (); | |
24270 | } | |
24271 | ||
24272 | ||
24273 | /* Parse a .arch directive. */ | |
24274 | ||
24275 | static void | |
24276 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
24277 | { | |
e74cfd16 | 24278 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
24279 | char saved_char; |
24280 | char *name; | |
24281 | ||
24282 | name = input_line_pointer; | |
5f4273c7 | 24283 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24284 | input_line_pointer++; |
24285 | saved_char = *input_line_pointer; | |
24286 | *input_line_pointer = 0; | |
24287 | ||
24288 | /* Skip the first "all" entry. */ | |
24289 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
24290 | if (streq (opt->name, name)) | |
24291 | { | |
e74cfd16 PB |
24292 | mcpu_cpu_opt = &opt->value; |
24293 | selected_cpu = opt->value; | |
5f4273c7 | 24294 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 24295 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
24296 | *input_line_pointer = saved_char; |
24297 | demand_empty_rest_of_line (); | |
24298 | return; | |
24299 | } | |
24300 | ||
24301 | as_bad (_("unknown architecture `%s'\n"), name); | |
24302 | *input_line_pointer = saved_char; | |
24303 | ignore_rest_of_line (); | |
24304 | } | |
24305 | ||
24306 | ||
7a1d4c38 PB |
24307 | /* Parse a .object_arch directive. */ |
24308 | ||
24309 | static void | |
24310 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
24311 | { | |
24312 | const struct arm_arch_option_table *opt; | |
24313 | char saved_char; | |
24314 | char *name; | |
24315 | ||
24316 | name = input_line_pointer; | |
5f4273c7 | 24317 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
24318 | input_line_pointer++; |
24319 | saved_char = *input_line_pointer; | |
24320 | *input_line_pointer = 0; | |
24321 | ||
24322 | /* Skip the first "all" entry. */ | |
24323 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
24324 | if (streq (opt->name, name)) | |
24325 | { | |
24326 | object_arch = &opt->value; | |
24327 | *input_line_pointer = saved_char; | |
24328 | demand_empty_rest_of_line (); | |
24329 | return; | |
24330 | } | |
24331 | ||
24332 | as_bad (_("unknown architecture `%s'\n"), name); | |
24333 | *input_line_pointer = saved_char; | |
24334 | ignore_rest_of_line (); | |
24335 | } | |
24336 | ||
69133863 MGD |
24337 | /* Parse a .arch_extension directive. */ |
24338 | ||
24339 | static void | |
24340 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
24341 | { | |
24342 | const struct arm_option_extension_value_table *opt; | |
24343 | char saved_char; | |
24344 | char *name; | |
24345 | int adding_value = 1; | |
24346 | ||
24347 | name = input_line_pointer; | |
24348 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
24349 | input_line_pointer++; | |
24350 | saved_char = *input_line_pointer; | |
24351 | *input_line_pointer = 0; | |
24352 | ||
24353 | if (strlen (name) >= 2 | |
24354 | && strncmp (name, "no", 2) == 0) | |
24355 | { | |
24356 | adding_value = 0; | |
24357 | name += 2; | |
24358 | } | |
24359 | ||
24360 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
24361 | if (streq (opt->name, name)) | |
24362 | { | |
24363 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
24364 | { | |
24365 | as_bad (_("architectural extension `%s' is not allowed for the " | |
24366 | "current base architecture"), name); | |
24367 | break; | |
24368 | } | |
24369 | ||
24370 | if (adding_value) | |
24371 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); | |
24372 | else | |
24373 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); | |
24374 | ||
24375 | mcpu_cpu_opt = &selected_cpu; | |
24376 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
24377 | *input_line_pointer = saved_char; | |
24378 | demand_empty_rest_of_line (); | |
24379 | return; | |
24380 | } | |
24381 | ||
24382 | if (opt->name == NULL) | |
24383 | as_bad (_("unknown architecture `%s'\n"), name); | |
24384 | ||
24385 | *input_line_pointer = saved_char; | |
24386 | ignore_rest_of_line (); | |
24387 | } | |
24388 | ||
ee065d83 PB |
24389 | /* Parse a .fpu directive. */ |
24390 | ||
24391 | static void | |
24392 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
24393 | { | |
69133863 | 24394 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
24395 | char saved_char; |
24396 | char *name; | |
24397 | ||
24398 | name = input_line_pointer; | |
5f4273c7 | 24399 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24400 | input_line_pointer++; |
24401 | saved_char = *input_line_pointer; | |
24402 | *input_line_pointer = 0; | |
5f4273c7 | 24403 | |
ee065d83 PB |
24404 | for (opt = arm_fpus; opt->name != NULL; opt++) |
24405 | if (streq (opt->name, name)) | |
24406 | { | |
e74cfd16 PB |
24407 | mfpu_opt = &opt->value; |
24408 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
24409 | *input_line_pointer = saved_char; |
24410 | demand_empty_rest_of_line (); | |
24411 | return; | |
24412 | } | |
24413 | ||
24414 | as_bad (_("unknown floating point format `%s'\n"), name); | |
24415 | *input_line_pointer = saved_char; | |
24416 | ignore_rest_of_line (); | |
24417 | } | |
ee065d83 | 24418 | |
794ba86a | 24419 | /* Copy symbol information. */ |
f31fef98 | 24420 | |
794ba86a DJ |
24421 | void |
24422 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
24423 | { | |
24424 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
24425 | } | |
e04befd0 | 24426 | |
f31fef98 | 24427 | #ifdef OBJ_ELF |
e04befd0 AS |
24428 | /* Given a symbolic attribute NAME, return the proper integer value. |
24429 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 24430 | |
e04befd0 AS |
24431 | int |
24432 | arm_convert_symbolic_attribute (const char *name) | |
24433 | { | |
f31fef98 NC |
24434 | static const struct |
24435 | { | |
24436 | const char * name; | |
24437 | const int tag; | |
24438 | } | |
24439 | attribute_table[] = | |
24440 | { | |
24441 | /* When you modify this table you should | |
24442 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 24443 | #define T(tag) {#tag, tag} |
f31fef98 NC |
24444 | T (Tag_CPU_raw_name), |
24445 | T (Tag_CPU_name), | |
24446 | T (Tag_CPU_arch), | |
24447 | T (Tag_CPU_arch_profile), | |
24448 | T (Tag_ARM_ISA_use), | |
24449 | T (Tag_THUMB_ISA_use), | |
75375b3e | 24450 | T (Tag_FP_arch), |
f31fef98 NC |
24451 | T (Tag_VFP_arch), |
24452 | T (Tag_WMMX_arch), | |
24453 | T (Tag_Advanced_SIMD_arch), | |
24454 | T (Tag_PCS_config), | |
24455 | T (Tag_ABI_PCS_R9_use), | |
24456 | T (Tag_ABI_PCS_RW_data), | |
24457 | T (Tag_ABI_PCS_RO_data), | |
24458 | T (Tag_ABI_PCS_GOT_use), | |
24459 | T (Tag_ABI_PCS_wchar_t), | |
24460 | T (Tag_ABI_FP_rounding), | |
24461 | T (Tag_ABI_FP_denormal), | |
24462 | T (Tag_ABI_FP_exceptions), | |
24463 | T (Tag_ABI_FP_user_exceptions), | |
24464 | T (Tag_ABI_FP_number_model), | |
75375b3e | 24465 | T (Tag_ABI_align_needed), |
f31fef98 | 24466 | T (Tag_ABI_align8_needed), |
75375b3e | 24467 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
24468 | T (Tag_ABI_align8_preserved), |
24469 | T (Tag_ABI_enum_size), | |
24470 | T (Tag_ABI_HardFP_use), | |
24471 | T (Tag_ABI_VFP_args), | |
24472 | T (Tag_ABI_WMMX_args), | |
24473 | T (Tag_ABI_optimization_goals), | |
24474 | T (Tag_ABI_FP_optimization_goals), | |
24475 | T (Tag_compatibility), | |
24476 | T (Tag_CPU_unaligned_access), | |
75375b3e | 24477 | T (Tag_FP_HP_extension), |
f31fef98 NC |
24478 | T (Tag_VFP_HP_extension), |
24479 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
24480 | T (Tag_MPextension_use), |
24481 | T (Tag_DIV_use), | |
f31fef98 NC |
24482 | T (Tag_nodefaults), |
24483 | T (Tag_also_compatible_with), | |
24484 | T (Tag_conformance), | |
24485 | T (Tag_T2EE_use), | |
24486 | T (Tag_Virtualization_use), | |
cd21e546 | 24487 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 24488 | #undef T |
f31fef98 | 24489 | }; |
e04befd0 AS |
24490 | unsigned int i; |
24491 | ||
24492 | if (name == NULL) | |
24493 | return -1; | |
24494 | ||
f31fef98 | 24495 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 24496 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
24497 | return attribute_table[i].tag; |
24498 | ||
24499 | return -1; | |
24500 | } | |
267bf995 RR |
24501 | |
24502 | ||
24503 | /* Apply sym value for relocations only in the case that | |
24504 | they are for local symbols and you have the respective | |
24505 | architectural feature for blx and simple switches. */ | |
24506 | int | |
24507 | arm_apply_sym_value (struct fix * fixP) | |
24508 | { | |
24509 | if (fixP->fx_addsy | |
24510 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 24511 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
24512 | { |
24513 | switch (fixP->fx_r_type) | |
24514 | { | |
24515 | case BFD_RELOC_ARM_PCREL_BLX: | |
24516 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
24517 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
24518 | return 1; | |
24519 | break; | |
24520 | ||
24521 | case BFD_RELOC_ARM_PCREL_CALL: | |
24522 | case BFD_RELOC_THUMB_PCREL_BLX: | |
24523 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
24524 | return 1; | |
24525 | break; | |
24526 | ||
24527 | default: | |
24528 | break; | |
24529 | } | |
24530 | ||
24531 | } | |
24532 | return 0; | |
24533 | } | |
f31fef98 | 24534 | #endif /* OBJ_ELF */ |