Commit | Line | Data |
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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
b90efa5b | 2 | Copyright (C) 1994-2015 Free Software Foundation, Inc. |
b99bd4ef NC |
3 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
4 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 5 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
6 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
7 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
8 | |
9 | This file is part of GAS, the GNU Assembler. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
19 | GNU General Public License for more details. |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
b99bd4ef | 25 | |
42a68e18 | 26 | #include "as.h" |
5287ad62 | 27 | #include <limits.h> |
037e8744 | 28 | #include <stdarg.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
3882b010 | 30 | #include "safe-ctype.h" |
b99bd4ef NC |
31 | #include "subsegs.h" |
32 | #include "obstack.h" | |
3da1d841 | 33 | #include "libiberty.h" |
f263249b RE |
34 | #include "opcode/arm.h" |
35 | ||
b99bd4ef NC |
36 | #ifdef OBJ_ELF |
37 | #include "elf/arm.h" | |
a394c00f | 38 | #include "dw2gencfi.h" |
b99bd4ef NC |
39 | #endif |
40 | ||
f0927246 NC |
41 | #include "dwarf2dbg.h" |
42 | ||
7ed4c4c5 NC |
43 | #ifdef OBJ_ELF |
44 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
45 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
46 | ||
47 | /* This structure holds the unwinding state. */ | |
48 | ||
49 | static struct | |
50 | { | |
c19d1205 ZW |
51 | symbolS * proc_start; |
52 | symbolS * table_entry; | |
53 | symbolS * personality_routine; | |
54 | int personality_index; | |
7ed4c4c5 | 55 | /* The segment containing the function. */ |
c19d1205 ZW |
56 | segT saved_seg; |
57 | subsegT saved_subseg; | |
7ed4c4c5 NC |
58 | /* Opcodes generated from this function. */ |
59 | unsigned char * opcodes; | |
c19d1205 ZW |
60 | int opcode_count; |
61 | int opcode_alloc; | |
7ed4c4c5 | 62 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 63 | offsetT frame_size; |
7ed4c4c5 NC |
64 | /* We don't add stack adjustment opcodes immediately so that we can merge |
65 | multiple adjustments. We can also omit the final adjustment | |
66 | when using a frame pointer. */ | |
c19d1205 | 67 | offsetT pending_offset; |
7ed4c4c5 | 68 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
69 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
70 | offsetT fp_offset; | |
71 | int fp_reg; | |
7ed4c4c5 | 72 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 73 | unsigned fp_used:1; |
7ed4c4c5 | 74 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 75 | unsigned sp_restored:1; |
7ed4c4c5 NC |
76 | } unwind; |
77 | ||
8b1ad454 NC |
78 | #endif /* OBJ_ELF */ |
79 | ||
4962c51a MS |
80 | /* Results from operand parsing worker functions. */ |
81 | ||
82 | typedef enum | |
83 | { | |
84 | PARSE_OPERAND_SUCCESS, | |
85 | PARSE_OPERAND_FAIL, | |
86 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
87 | } parse_operand_result; | |
88 | ||
33a392fb PB |
89 | enum arm_float_abi |
90 | { | |
91 | ARM_FLOAT_ABI_HARD, | |
92 | ARM_FLOAT_ABI_SOFTFP, | |
93 | ARM_FLOAT_ABI_SOFT | |
94 | }; | |
95 | ||
c19d1205 | 96 | /* Types of processor to assemble for. */ |
b99bd4ef | 97 | #ifndef CPU_DEFAULT |
8a59fff3 | 98 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 99 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
100 | changing gas' default behaviour depending upon the build host. |
101 | ||
102 | If you have a target that requires a default CPU option then the you | |
103 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
104 | #endif |
105 | ||
106 | #ifndef FPU_DEFAULT | |
c820d418 MM |
107 | # ifdef TE_LINUX |
108 | # define FPU_DEFAULT FPU_ARCH_FPA | |
109 | # elif defined (TE_NetBSD) | |
110 | # ifdef OBJ_ELF | |
111 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
112 | # else | |
113 | /* Legacy a.out format. */ | |
114 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
115 | # endif | |
4e7fd91e PB |
116 | # elif defined (TE_VXWORKS) |
117 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
118 | # else |
119 | /* For backwards compatibility, default to FPA. */ | |
120 | # define FPU_DEFAULT FPU_ARCH_FPA | |
121 | # endif | |
122 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 123 | |
c19d1205 | 124 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 125 | |
e74cfd16 PB |
126 | static arm_feature_set cpu_variant; |
127 | static arm_feature_set arm_arch_used; | |
128 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 129 | |
b99bd4ef | 130 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
131 | static int uses_apcs_26 = FALSE; |
132 | static int atpcs = FALSE; | |
b34976b6 AM |
133 | static int support_interwork = FALSE; |
134 | static int uses_apcs_float = FALSE; | |
c19d1205 | 135 | static int pic_code = FALSE; |
845b51d6 | 136 | static int fix_v4bx = FALSE; |
278df34e NS |
137 | /* Warn on using deprecated features. */ |
138 | static int warn_on_deprecated = TRUE; | |
139 | ||
2e6976a8 DG |
140 | /* Understand CodeComposer Studio assembly syntax. */ |
141 | bfd_boolean codecomposer_syntax = FALSE; | |
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
823d2571 TG |
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5); | |
e74cfd16 | 179 | static const arm_feature_set arm_ext_v4t_5 = |
823d2571 TG |
180 | ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5); |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); | |
187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); | |
188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M); | |
189 | static const arm_feature_set arm_ext_v6_notm = | |
190 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); | |
191 | static const arm_feature_set arm_ext_v6_dsp = | |
192 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP); | |
193 | static const arm_feature_set arm_ext_barrier = | |
194 | ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER); | |
195 | static const arm_feature_set arm_ext_msr = | |
196 | ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR); | |
197 | static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV); | |
198 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7); | |
199 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A); | |
200 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R); | |
201 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M); | |
202 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8); | |
7e806470 | 203 | static const arm_feature_set arm_ext_m = |
823d2571 TG |
204 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M); |
205 | static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP); | |
206 | static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC); | |
207 | static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS); | |
208 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); | |
209 | static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); | |
ddfded2f | 210 | static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); |
e74cfd16 PB |
211 | |
212 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
823d2571 | 213 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1); |
e74cfd16 PB |
214 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; |
215 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 216 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 217 | |
2d447fca | 218 | static const arm_feature_set arm_cext_iwmmxt2 = |
823d2571 | 219 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2); |
e74cfd16 | 220 | static const arm_feature_set arm_cext_iwmmxt = |
823d2571 | 221 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT); |
e74cfd16 | 222 | static const arm_feature_set arm_cext_xscale = |
823d2571 | 223 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE); |
e74cfd16 | 224 | static const arm_feature_set arm_cext_maverick = |
823d2571 TG |
225 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK); |
226 | static const arm_feature_set fpu_fpa_ext_v1 = | |
227 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V1); | |
228 | static const arm_feature_set fpu_fpa_ext_v2 = | |
229 | ARM_FEATURE_COPROC (FPU_FPA_EXT_V2); | |
e74cfd16 | 230 | static const arm_feature_set fpu_vfp_ext_v1xd = |
823d2571 TG |
231 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD); |
232 | static const arm_feature_set fpu_vfp_ext_v1 = | |
233 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V1); | |
234 | static const arm_feature_set fpu_vfp_ext_v2 = | |
235 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V2); | |
236 | static const arm_feature_set fpu_vfp_ext_v3xd = | |
237 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD); | |
238 | static const arm_feature_set fpu_vfp_ext_v3 = | |
239 | ARM_FEATURE_COPROC (FPU_VFP_EXT_V3); | |
b1cc4aeb | 240 | static const arm_feature_set fpu_vfp_ext_d32 = |
823d2571 TG |
241 | ARM_FEATURE_COPROC (FPU_VFP_EXT_D32); |
242 | static const arm_feature_set fpu_neon_ext_v1 = | |
243 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1); | |
5287ad62 | 244 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
823d2571 TG |
245 | ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
246 | static const arm_feature_set fpu_vfp_fp16 = | |
247 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16); | |
248 | static const arm_feature_set fpu_neon_ext_fma = | |
249 | ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA); | |
250 | static const arm_feature_set fpu_vfp_ext_fma = | |
251 | ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA); | |
bca38921 | 252 | static const arm_feature_set fpu_vfp_ext_armv8 = |
823d2571 | 253 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8); |
a715796b | 254 | static const arm_feature_set fpu_vfp_ext_armv8xd = |
823d2571 | 255 | ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD); |
bca38921 | 256 | static const arm_feature_set fpu_neon_ext_armv8 = |
823d2571 | 257 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8); |
bca38921 | 258 | static const arm_feature_set fpu_crypto_ext_armv8 = |
823d2571 | 259 | ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8); |
dd5181d5 | 260 | static const arm_feature_set crc_ext_armv8 = |
823d2571 | 261 | ARM_FEATURE_COPROC (CRC_EXT_ARMV8); |
d6b4b13e MW |
262 | static const arm_feature_set fpu_neon_ext_v8_1 = |
263 | ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA); | |
e74cfd16 | 264 | |
33a392fb | 265 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
266 | /* Record user cpu selection for object attributes. */ |
267 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
268 | /* Must be long enough to hold any of the names in arm_cpus. */ |
269 | static char selected_cpu_name[16]; | |
8d67f500 | 270 | |
aacf0b33 KT |
271 | extern FLONUM_TYPE generic_floating_point_number; |
272 | ||
8d67f500 NC |
273 | /* Return if no cpu was selected on command-line. */ |
274 | static bfd_boolean | |
275 | no_cpu_selected (void) | |
276 | { | |
823d2571 | 277 | return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none); |
8d67f500 NC |
278 | } |
279 | ||
7cc69913 | 280 | #ifdef OBJ_ELF |
deeaaff8 DJ |
281 | # ifdef EABI_DEFAULT |
282 | static int meabi_flags = EABI_DEFAULT; | |
283 | # else | |
d507cf36 | 284 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 285 | # endif |
e1da3f5b | 286 | |
ee3c0378 AS |
287 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
288 | ||
e1da3f5b | 289 | bfd_boolean |
5f4273c7 | 290 | arm_is_eabi (void) |
e1da3f5b PB |
291 | { |
292 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
293 | } | |
7cc69913 | 294 | #endif |
b99bd4ef | 295 | |
b99bd4ef | 296 | #ifdef OBJ_ELF |
c19d1205 | 297 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
298 | symbolS * GOT_symbol; |
299 | #endif | |
300 | ||
b99bd4ef NC |
301 | /* 0: assemble for ARM, |
302 | 1: assemble for Thumb, | |
303 | 2: assemble for Thumb even though target CPU does not support thumb | |
304 | instructions. */ | |
305 | static int thumb_mode = 0; | |
8dc2430f NC |
306 | /* A value distinct from the possible values for thumb_mode that we |
307 | can use to record whether thumb_mode has been copied into the | |
308 | tc_frag_data field of a frag. */ | |
309 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 310 | |
e07e6e58 NC |
311 | /* Specifies the intrinsic IT insn behavior mode. */ |
312 | enum implicit_it_mode | |
313 | { | |
314 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
315 | IMPLICIT_IT_MODE_ARM = 0x01, | |
316 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
317 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
318 | }; | |
319 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
320 | ||
c19d1205 ZW |
321 | /* If unified_syntax is true, we are processing the new unified |
322 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
323 | ||
324 | - Immediate operands do not require a # prefix. | |
325 | - Conditional affixes always appear at the end of the | |
326 | instruction. (For backward compatibility, those instructions | |
327 | that formerly had them in the middle, continue to accept them | |
328 | there.) | |
329 | - The IT instruction may appear, and if it does is validated | |
330 | against subsequent conditional affixes. It does not generate | |
331 | machine code. | |
332 | ||
333 | Important differences from the old Thumb mode: | |
334 | ||
335 | - Immediate operands do not require a # prefix. | |
336 | - Most of the V6T2 instructions are only available in unified mode. | |
337 | - The .N and .W suffixes are recognized and honored (it is an error | |
338 | if they cannot be honored). | |
339 | - All instructions set the flags if and only if they have an 's' affix. | |
340 | - Conditional affixes may be used. They are validated against | |
341 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
342 | conditional affix except in the scope of an IT instruction. */ | |
343 | ||
344 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 345 | |
bacebabc RM |
346 | /* An immediate operand can start with #, and ld*, st*, pld operands |
347 | can contain [ and ]. We need to tell APP not to elide whitespace | |
477330fc RM |
348 | before a [, which can appear as the first operand for pld. |
349 | Likewise, a { can appear as the first operand for push, pop, vld*, etc. */ | |
350 | const char arm_symbol_chars[] = "#[]{}"; | |
bacebabc | 351 | |
5287ad62 JB |
352 | enum neon_el_type |
353 | { | |
dcbf9037 | 354 | NT_invtype, |
5287ad62 JB |
355 | NT_untyped, |
356 | NT_integer, | |
357 | NT_float, | |
358 | NT_poly, | |
359 | NT_signed, | |
dcbf9037 | 360 | NT_unsigned |
5287ad62 JB |
361 | }; |
362 | ||
363 | struct neon_type_el | |
364 | { | |
365 | enum neon_el_type type; | |
366 | unsigned size; | |
367 | }; | |
368 | ||
369 | #define NEON_MAX_TYPE_ELS 4 | |
370 | ||
371 | struct neon_type | |
372 | { | |
373 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
374 | unsigned elems; | |
375 | }; | |
376 | ||
e07e6e58 NC |
377 | enum it_instruction_type |
378 | { | |
379 | OUTSIDE_IT_INSN, | |
380 | INSIDE_IT_INSN, | |
381 | INSIDE_IT_LAST_INSN, | |
382 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
477330fc | 383 | if inside, should be the last one. */ |
e07e6e58 | 384 | NEUTRAL_IT_INSN, /* This could be either inside or outside, |
477330fc | 385 | i.e. BKPT and NOP. */ |
e07e6e58 NC |
386 | IT_INSN /* The IT insn has been parsed. */ |
387 | }; | |
388 | ||
ad6cec43 MGD |
389 | /* The maximum number of operands we need. */ |
390 | #define ARM_IT_MAX_OPERANDS 6 | |
391 | ||
b99bd4ef NC |
392 | struct arm_it |
393 | { | |
c19d1205 | 394 | const char * error; |
b99bd4ef | 395 | unsigned long instruction; |
c19d1205 ZW |
396 | int size; |
397 | int size_req; | |
398 | int cond; | |
037e8744 JB |
399 | /* "uncond_value" is set to the value in place of the conditional field in |
400 | unconditional versions of the instruction, or -1 if nothing is | |
401 | appropriate. */ | |
402 | int uncond_value; | |
5287ad62 | 403 | struct neon_type vectype; |
88714cb8 DG |
404 | /* This does not indicate an actual NEON instruction, only that |
405 | the mnemonic accepts neon-style type suffixes. */ | |
406 | int is_neon; | |
0110f2b8 PB |
407 | /* Set to the opcode if the instruction needs relaxation. |
408 | Zero if the instruction is not relaxed. */ | |
409 | unsigned long relax; | |
b99bd4ef NC |
410 | struct |
411 | { | |
412 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
413 | expressionS exp; |
414 | int pc_rel; | |
b99bd4ef | 415 | } reloc; |
b99bd4ef | 416 | |
e07e6e58 NC |
417 | enum it_instruction_type it_insn_type; |
418 | ||
c19d1205 ZW |
419 | struct |
420 | { | |
421 | unsigned reg; | |
ca3f61f7 | 422 | signed int imm; |
dcbf9037 | 423 | struct neon_type_el vectype; |
ca3f61f7 NC |
424 | unsigned present : 1; /* Operand present. */ |
425 | unsigned isreg : 1; /* Operand was a register. */ | |
426 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
427 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
428 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 429 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
430 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
431 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
432 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 433 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 434 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 435 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
436 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
437 | unsigned writeback : 1; /* Operand has trailing ! */ | |
438 | unsigned preind : 1; /* Preindexed address. */ | |
439 | unsigned postind : 1; /* Postindexed address. */ | |
440 | unsigned negative : 1; /* Index register was negated. */ | |
441 | unsigned shifted : 1; /* Shift applied to operation. */ | |
442 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 443 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
444 | }; |
445 | ||
c19d1205 | 446 | static struct arm_it inst; |
b99bd4ef NC |
447 | |
448 | #define NUM_FLOAT_VALS 8 | |
449 | ||
05d2d07e | 450 | const char * fp_const[] = |
b99bd4ef NC |
451 | { |
452 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
453 | }; | |
454 | ||
c19d1205 | 455 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
456 | #define MAX_LITTLENUMS 6 |
457 | ||
458 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
459 | ||
460 | #define FAIL (-1) | |
461 | #define SUCCESS (0) | |
462 | ||
463 | #define SUFF_S 1 | |
464 | #define SUFF_D 2 | |
465 | #define SUFF_E 3 | |
466 | #define SUFF_P 4 | |
467 | ||
c19d1205 ZW |
468 | #define CP_T_X 0x00008000 |
469 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 470 | |
c19d1205 ZW |
471 | #define CONDS_BIT 0x00100000 |
472 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
473 | |
474 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
475 | ||
476 | struct asm_cond | |
477 | { | |
d3ce72d0 | 478 | const char * template_name; |
c921be7d | 479 | unsigned long value; |
b99bd4ef NC |
480 | }; |
481 | ||
c19d1205 | 482 | #define COND_ALWAYS 0xE |
b99bd4ef | 483 | |
b99bd4ef NC |
484 | struct asm_psr |
485 | { | |
d3ce72d0 | 486 | const char * template_name; |
c921be7d | 487 | unsigned long field; |
b99bd4ef NC |
488 | }; |
489 | ||
62b3e311 PB |
490 | struct asm_barrier_opt |
491 | { | |
e797f7e0 MGD |
492 | const char * template_name; |
493 | unsigned long value; | |
494 | const arm_feature_set arch; | |
62b3e311 PB |
495 | }; |
496 | ||
2d2255b5 | 497 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
498 | #define SPSR_BIT (1 << 22) |
499 | ||
c19d1205 ZW |
500 | /* The individual PSR flag bits. */ |
501 | #define PSR_c (1 << 16) | |
502 | #define PSR_x (1 << 17) | |
503 | #define PSR_s (1 << 18) | |
504 | #define PSR_f (1 << 19) | |
b99bd4ef | 505 | |
c19d1205 | 506 | struct reloc_entry |
bfae80f2 | 507 | { |
c921be7d NC |
508 | char * name; |
509 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
510 | }; |
511 | ||
5287ad62 | 512 | enum vfp_reg_pos |
bfae80f2 | 513 | { |
5287ad62 JB |
514 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
515 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
516 | }; |
517 | ||
518 | enum vfp_ldstm_type | |
519 | { | |
520 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
521 | }; | |
522 | ||
dcbf9037 JB |
523 | /* Bits for DEFINED field in neon_typed_alias. */ |
524 | #define NTA_HASTYPE 1 | |
525 | #define NTA_HASINDEX 2 | |
526 | ||
527 | struct neon_typed_alias | |
528 | { | |
c921be7d NC |
529 | unsigned char defined; |
530 | unsigned char index; | |
531 | struct neon_type_el eltype; | |
dcbf9037 JB |
532 | }; |
533 | ||
c19d1205 ZW |
534 | /* ARM register categories. This includes coprocessor numbers and various |
535 | architecture extensions' registers. */ | |
536 | enum arm_reg_type | |
bfae80f2 | 537 | { |
c19d1205 ZW |
538 | REG_TYPE_RN, |
539 | REG_TYPE_CP, | |
540 | REG_TYPE_CN, | |
541 | REG_TYPE_FN, | |
542 | REG_TYPE_VFS, | |
543 | REG_TYPE_VFD, | |
5287ad62 | 544 | REG_TYPE_NQ, |
037e8744 | 545 | REG_TYPE_VFSD, |
5287ad62 | 546 | REG_TYPE_NDQ, |
037e8744 | 547 | REG_TYPE_NSDQ, |
c19d1205 ZW |
548 | REG_TYPE_VFC, |
549 | REG_TYPE_MVF, | |
550 | REG_TYPE_MVD, | |
551 | REG_TYPE_MVFX, | |
552 | REG_TYPE_MVDX, | |
553 | REG_TYPE_MVAX, | |
554 | REG_TYPE_DSPSC, | |
555 | REG_TYPE_MMXWR, | |
556 | REG_TYPE_MMXWC, | |
557 | REG_TYPE_MMXWCG, | |
558 | REG_TYPE_XSCALE, | |
90ec0d68 | 559 | REG_TYPE_RNB |
bfae80f2 RE |
560 | }; |
561 | ||
dcbf9037 JB |
562 | /* Structure for a hash table entry for a register. |
563 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
564 | information which states whether a vector type or index is specified (for a | |
565 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
566 | struct reg_entry |
567 | { | |
c921be7d | 568 | const char * name; |
90ec0d68 | 569 | unsigned int number; |
c921be7d NC |
570 | unsigned char type; |
571 | unsigned char builtin; | |
572 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
573 | }; |
574 | ||
c19d1205 | 575 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 576 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
577 | { |
578 | N_("ARM register expected"), | |
579 | N_("bad or missing co-processor number"), | |
580 | N_("co-processor register expected"), | |
581 | N_("FPA register expected"), | |
582 | N_("VFP single precision register expected"), | |
5287ad62 JB |
583 | N_("VFP/Neon double precision register expected"), |
584 | N_("Neon quad precision register expected"), | |
037e8744 | 585 | N_("VFP single or double precision register expected"), |
5287ad62 | 586 | N_("Neon double or quad precision register expected"), |
037e8744 | 587 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
588 | N_("VFP system register expected"), |
589 | N_("Maverick MVF register expected"), | |
590 | N_("Maverick MVD register expected"), | |
591 | N_("Maverick MVFX register expected"), | |
592 | N_("Maverick MVDX register expected"), | |
593 | N_("Maverick MVAX register expected"), | |
594 | N_("Maverick DSPSC register expected"), | |
595 | N_("iWMMXt data register expected"), | |
596 | N_("iWMMXt control register expected"), | |
597 | N_("iWMMXt scalar register expected"), | |
598 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
599 | }; |
600 | ||
c19d1205 | 601 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 602 | #define REG_R12 12 |
c19d1205 ZW |
603 | #define REG_SP 13 |
604 | #define REG_LR 14 | |
605 | #define REG_PC 15 | |
404ff6b5 | 606 | |
b99bd4ef NC |
607 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
608 | take 2: */ | |
c19d1205 | 609 | #define INSN_SIZE 4 |
b99bd4ef NC |
610 | |
611 | struct asm_opcode | |
612 | { | |
613 | /* Basic string to match. */ | |
d3ce72d0 | 614 | const char * template_name; |
c19d1205 ZW |
615 | |
616 | /* Parameters to instruction. */ | |
5be8be5d | 617 | unsigned int operands[8]; |
c19d1205 ZW |
618 | |
619 | /* Conditional tag - see opcode_lookup. */ | |
620 | unsigned int tag : 4; | |
b99bd4ef NC |
621 | |
622 | /* Basic instruction code. */ | |
c19d1205 | 623 | unsigned int avalue : 28; |
b99bd4ef | 624 | |
c19d1205 ZW |
625 | /* Thumb-format instruction code. */ |
626 | unsigned int tvalue; | |
b99bd4ef | 627 | |
90e4755a | 628 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
629 | const arm_feature_set * avariant; |
630 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
631 | |
632 | /* Function to call to encode instruction in ARM format. */ | |
633 | void (* aencode) (void); | |
b99bd4ef | 634 | |
c19d1205 ZW |
635 | /* Function to call to encode instruction in Thumb format. */ |
636 | void (* tencode) (void); | |
b99bd4ef NC |
637 | }; |
638 | ||
a737bd4d NC |
639 | /* Defines for various bits that we will want to toggle. */ |
640 | #define INST_IMMEDIATE 0x02000000 | |
641 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 642 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
643 | #define SHIFT_BY_REG 0x00000010 |
644 | #define PRE_INDEX 0x01000000 | |
645 | #define INDEX_UP 0x00800000 | |
646 | #define WRITE_BACK 0x00200000 | |
647 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 648 | #define CPSI_MMOD 0x00020000 |
90e4755a | 649 | |
a737bd4d NC |
650 | #define LITERAL_MASK 0xf000f000 |
651 | #define OPCODE_MASK 0xfe1fffff | |
652 | #define V4_STR_BIT 0x00000020 | |
8335d6aa | 653 | #define VLDR_VMOV_SAME 0x0040f000 |
90e4755a | 654 | |
efd81785 PB |
655 | #define T2_SUBS_PC_LR 0xf3de8f00 |
656 | ||
a737bd4d | 657 | #define DATA_OP_SHIFT 21 |
90e4755a | 658 | |
ef8d22e6 PB |
659 | #define T2_OPCODE_MASK 0xfe1fffff |
660 | #define T2_DATA_OP_SHIFT 21 | |
661 | ||
6530b175 NC |
662 | #define A_COND_MASK 0xf0000000 |
663 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
664 | ||
665 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
666 | #define A1_OPCODE_PUSH 0x092d0000 | |
667 | #define A2_OPCODE_PUSH 0x052d0004 | |
668 | #define A2_OPCODE_POP 0x049d0004 | |
669 | ||
a737bd4d NC |
670 | /* Codes to distinguish the arithmetic instructions. */ |
671 | #define OPCODE_AND 0 | |
672 | #define OPCODE_EOR 1 | |
673 | #define OPCODE_SUB 2 | |
674 | #define OPCODE_RSB 3 | |
675 | #define OPCODE_ADD 4 | |
676 | #define OPCODE_ADC 5 | |
677 | #define OPCODE_SBC 6 | |
678 | #define OPCODE_RSC 7 | |
679 | #define OPCODE_TST 8 | |
680 | #define OPCODE_TEQ 9 | |
681 | #define OPCODE_CMP 10 | |
682 | #define OPCODE_CMN 11 | |
683 | #define OPCODE_ORR 12 | |
684 | #define OPCODE_MOV 13 | |
685 | #define OPCODE_BIC 14 | |
686 | #define OPCODE_MVN 15 | |
90e4755a | 687 | |
ef8d22e6 PB |
688 | #define T2_OPCODE_AND 0 |
689 | #define T2_OPCODE_BIC 1 | |
690 | #define T2_OPCODE_ORR 2 | |
691 | #define T2_OPCODE_ORN 3 | |
692 | #define T2_OPCODE_EOR 4 | |
693 | #define T2_OPCODE_ADD 8 | |
694 | #define T2_OPCODE_ADC 10 | |
695 | #define T2_OPCODE_SBC 11 | |
696 | #define T2_OPCODE_SUB 13 | |
697 | #define T2_OPCODE_RSB 14 | |
698 | ||
a737bd4d NC |
699 | #define T_OPCODE_MUL 0x4340 |
700 | #define T_OPCODE_TST 0x4200 | |
701 | #define T_OPCODE_CMN 0x42c0 | |
702 | #define T_OPCODE_NEG 0x4240 | |
703 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 704 | |
a737bd4d NC |
705 | #define T_OPCODE_ADD_R3 0x1800 |
706 | #define T_OPCODE_SUB_R3 0x1a00 | |
707 | #define T_OPCODE_ADD_HI 0x4400 | |
708 | #define T_OPCODE_ADD_ST 0xb000 | |
709 | #define T_OPCODE_SUB_ST 0xb080 | |
710 | #define T_OPCODE_ADD_SP 0xa800 | |
711 | #define T_OPCODE_ADD_PC 0xa000 | |
712 | #define T_OPCODE_ADD_I8 0x3000 | |
713 | #define T_OPCODE_SUB_I8 0x3800 | |
714 | #define T_OPCODE_ADD_I3 0x1c00 | |
715 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 716 | |
a737bd4d NC |
717 | #define T_OPCODE_ASR_R 0x4100 |
718 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
719 | #define T_OPCODE_LSR_R 0x40c0 |
720 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
721 | #define T_OPCODE_ASR_I 0x1000 |
722 | #define T_OPCODE_LSL_I 0x0000 | |
723 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 724 | |
a737bd4d NC |
725 | #define T_OPCODE_MOV_I8 0x2000 |
726 | #define T_OPCODE_CMP_I8 0x2800 | |
727 | #define T_OPCODE_CMP_LR 0x4280 | |
728 | #define T_OPCODE_MOV_HR 0x4600 | |
729 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 730 | |
a737bd4d NC |
731 | #define T_OPCODE_LDR_PC 0x4800 |
732 | #define T_OPCODE_LDR_SP 0x9800 | |
733 | #define T_OPCODE_STR_SP 0x9000 | |
734 | #define T_OPCODE_LDR_IW 0x6800 | |
735 | #define T_OPCODE_STR_IW 0x6000 | |
736 | #define T_OPCODE_LDR_IH 0x8800 | |
737 | #define T_OPCODE_STR_IH 0x8000 | |
738 | #define T_OPCODE_LDR_IB 0x7800 | |
739 | #define T_OPCODE_STR_IB 0x7000 | |
740 | #define T_OPCODE_LDR_RW 0x5800 | |
741 | #define T_OPCODE_STR_RW 0x5000 | |
742 | #define T_OPCODE_LDR_RH 0x5a00 | |
743 | #define T_OPCODE_STR_RH 0x5200 | |
744 | #define T_OPCODE_LDR_RB 0x5c00 | |
745 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 746 | |
a737bd4d NC |
747 | #define T_OPCODE_PUSH 0xb400 |
748 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 749 | |
2fc8bdac | 750 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 751 | |
a737bd4d | 752 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 753 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 754 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 755 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
756 | |
757 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 758 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
759 | #define BAD_PC _("r15 not allowed here") |
760 | #define BAD_COND _("instruction cannot be conditional") | |
761 | #define BAD_OVERLAP _("registers may not be the same") | |
762 | #define BAD_HIREG _("lo register required") | |
763 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 764 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
765 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
766 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 767 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
768 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
769 | #define BAD_IT_COND _("incorrect condition in IT block") | |
770 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 771 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
772 | #define BAD_PC_ADDRESSING \ |
773 | _("cannot use register index with PC-relative addressing") | |
774 | #define BAD_PC_WRITEBACK \ | |
775 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 776 | #define BAD_RANGE _("branch out of range") |
dd5181d5 | 777 | #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour") |
c19d1205 | 778 | |
c921be7d NC |
779 | static struct hash_control * arm_ops_hsh; |
780 | static struct hash_control * arm_cond_hsh; | |
781 | static struct hash_control * arm_shift_hsh; | |
782 | static struct hash_control * arm_psr_hsh; | |
783 | static struct hash_control * arm_v7m_psr_hsh; | |
784 | static struct hash_control * arm_reg_hsh; | |
785 | static struct hash_control * arm_reloc_hsh; | |
786 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 787 | |
b99bd4ef NC |
788 | /* Stuff needed to resolve the label ambiguity |
789 | As: | |
790 | ... | |
791 | label: <insn> | |
792 | may differ from: | |
793 | ... | |
794 | label: | |
5f4273c7 | 795 | <insn> */ |
b99bd4ef NC |
796 | |
797 | symbolS * last_label_seen; | |
b34976b6 | 798 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 799 | |
3d0c9500 NC |
800 | /* Literal pool structure. Held on a per-section |
801 | and per-sub-section basis. */ | |
a737bd4d | 802 | |
c19d1205 | 803 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 804 | typedef struct literal_pool |
b99bd4ef | 805 | { |
c921be7d NC |
806 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
807 | unsigned int next_free_entry; | |
808 | unsigned int id; | |
809 | symbolS * symbol; | |
810 | segT section; | |
811 | subsegT sub_section; | |
a8040cf2 NC |
812 | #ifdef OBJ_ELF |
813 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
814 | #endif | |
c921be7d | 815 | struct literal_pool * next; |
8335d6aa | 816 | unsigned int alignment; |
3d0c9500 | 817 | } literal_pool; |
b99bd4ef | 818 | |
3d0c9500 NC |
819 | /* Pointer to a linked list of literal pools. */ |
820 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 821 | |
2e6976a8 DG |
822 | typedef enum asmfunc_states |
823 | { | |
824 | OUTSIDE_ASMFUNC, | |
825 | WAITING_ASMFUNC_NAME, | |
826 | WAITING_ENDASMFUNC | |
827 | } asmfunc_states; | |
828 | ||
829 | static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; | |
830 | ||
e07e6e58 NC |
831 | #ifdef OBJ_ELF |
832 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
833 | #else | |
834 | static struct current_it now_it; | |
835 | #endif | |
836 | ||
837 | static inline int | |
838 | now_it_compatible (int cond) | |
839 | { | |
840 | return (cond & ~1) == (now_it.cc & ~1); | |
841 | } | |
842 | ||
843 | static inline int | |
844 | conditional_insn (void) | |
845 | { | |
846 | return inst.cond != COND_ALWAYS; | |
847 | } | |
848 | ||
849 | static int in_it_block (void); | |
850 | ||
851 | static int handle_it_state (void); | |
852 | ||
853 | static void force_automatic_it_block_close (void); | |
854 | ||
c921be7d NC |
855 | static void it_fsm_post_encode (void); |
856 | ||
e07e6e58 NC |
857 | #define set_it_insn_type(type) \ |
858 | do \ | |
859 | { \ | |
860 | inst.it_insn_type = type; \ | |
861 | if (handle_it_state () == FAIL) \ | |
477330fc | 862 | return; \ |
e07e6e58 NC |
863 | } \ |
864 | while (0) | |
865 | ||
c921be7d NC |
866 | #define set_it_insn_type_nonvoid(type, failret) \ |
867 | do \ | |
868 | { \ | |
869 | inst.it_insn_type = type; \ | |
870 | if (handle_it_state () == FAIL) \ | |
477330fc | 871 | return failret; \ |
c921be7d NC |
872 | } \ |
873 | while(0) | |
874 | ||
e07e6e58 NC |
875 | #define set_it_insn_type_last() \ |
876 | do \ | |
877 | { \ | |
878 | if (inst.cond == COND_ALWAYS) \ | |
477330fc | 879 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ |
e07e6e58 | 880 | else \ |
477330fc | 881 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ |
e07e6e58 NC |
882 | } \ |
883 | while (0) | |
884 | ||
c19d1205 | 885 | /* Pure syntax. */ |
b99bd4ef | 886 | |
c19d1205 ZW |
887 | /* This array holds the chars that always start a comment. If the |
888 | pre-processor is disabled, these aren't very useful. */ | |
2e6976a8 | 889 | char arm_comment_chars[] = "@"; |
3d0c9500 | 890 | |
c19d1205 ZW |
891 | /* This array holds the chars that only start a comment at the beginning of |
892 | a line. If the line seems to have the form '# 123 filename' | |
893 | .line and .file directives will appear in the pre-processed output. */ | |
894 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
895 | first line of the input file. This is because the compiler outputs | |
896 | #NO_APP at the beginning of its output. */ | |
897 | /* Also note that comments like this one will always work. */ | |
898 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 899 | |
2e6976a8 | 900 | char arm_line_separator_chars[] = ";"; |
b99bd4ef | 901 | |
c19d1205 ZW |
902 | /* Chars that can be used to separate mant |
903 | from exp in floating point numbers. */ | |
904 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 905 | |
c19d1205 ZW |
906 | /* Chars that mean this number is a floating point constant. */ |
907 | /* As in 0f12.456 */ | |
908 | /* or 0d1.2345e12 */ | |
b99bd4ef | 909 | |
c19d1205 | 910 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 911 | |
c19d1205 ZW |
912 | /* Prefix characters that indicate the start of an immediate |
913 | value. */ | |
914 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 915 | |
c19d1205 ZW |
916 | /* Separator character handling. */ |
917 | ||
918 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
919 | ||
920 | static inline int | |
921 | skip_past_char (char ** str, char c) | |
922 | { | |
8ab8155f NC |
923 | /* PR gas/14987: Allow for whitespace before the expected character. */ |
924 | skip_whitespace (*str); | |
427d0db6 | 925 | |
c19d1205 ZW |
926 | if (**str == c) |
927 | { | |
928 | (*str)++; | |
929 | return SUCCESS; | |
3d0c9500 | 930 | } |
c19d1205 ZW |
931 | else |
932 | return FAIL; | |
933 | } | |
c921be7d | 934 | |
c19d1205 | 935 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 936 | |
c19d1205 ZW |
937 | /* Arithmetic expressions (possibly involving symbols). */ |
938 | ||
939 | /* Return TRUE if anything in the expression is a bignum. */ | |
940 | ||
941 | static int | |
942 | walk_no_bignums (symbolS * sp) | |
943 | { | |
944 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
945 | return 1; | |
946 | ||
947 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 948 | { |
c19d1205 ZW |
949 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
950 | || (symbol_get_value_expression (sp)->X_op_symbol | |
951 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
952 | } |
953 | ||
c19d1205 | 954 | return 0; |
3d0c9500 NC |
955 | } |
956 | ||
c19d1205 ZW |
957 | static int in_my_get_expression = 0; |
958 | ||
959 | /* Third argument to my_get_expression. */ | |
960 | #define GE_NO_PREFIX 0 | |
961 | #define GE_IMM_PREFIX 1 | |
962 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
963 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
964 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
965 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 966 | |
b99bd4ef | 967 | static int |
c19d1205 | 968 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 969 | { |
c19d1205 ZW |
970 | char * save_in; |
971 | segT seg; | |
b99bd4ef | 972 | |
c19d1205 ZW |
973 | /* In unified syntax, all prefixes are optional. */ |
974 | if (unified_syntax) | |
5287ad62 | 975 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
477330fc | 976 | : GE_OPT_PREFIX; |
b99bd4ef | 977 | |
c19d1205 | 978 | switch (prefix_mode) |
b99bd4ef | 979 | { |
c19d1205 ZW |
980 | case GE_NO_PREFIX: break; |
981 | case GE_IMM_PREFIX: | |
982 | if (!is_immediate_prefix (**str)) | |
983 | { | |
984 | inst.error = _("immediate expression requires a # prefix"); | |
985 | return FAIL; | |
986 | } | |
987 | (*str)++; | |
988 | break; | |
989 | case GE_OPT_PREFIX: | |
5287ad62 | 990 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
991 | if (is_immediate_prefix (**str)) |
992 | (*str)++; | |
993 | break; | |
994 | default: abort (); | |
995 | } | |
b99bd4ef | 996 | |
c19d1205 | 997 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 998 | |
c19d1205 ZW |
999 | save_in = input_line_pointer; |
1000 | input_line_pointer = *str; | |
1001 | in_my_get_expression = 1; | |
1002 | seg = expression (ep); | |
1003 | in_my_get_expression = 0; | |
1004 | ||
f86adc07 | 1005 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 1006 | { |
f86adc07 | 1007 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
1008 | *str = input_line_pointer; |
1009 | input_line_pointer = save_in; | |
1010 | if (inst.error == NULL) | |
f86adc07 NS |
1011 | inst.error = (ep->X_op == O_absent |
1012 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
1013 | return 1; |
1014 | } | |
b99bd4ef | 1015 | |
c19d1205 ZW |
1016 | #ifdef OBJ_AOUT |
1017 | if (seg != absolute_section | |
1018 | && seg != text_section | |
1019 | && seg != data_section | |
1020 | && seg != bss_section | |
1021 | && seg != undefined_section) | |
1022 | { | |
1023 | inst.error = _("bad segment"); | |
1024 | *str = input_line_pointer; | |
1025 | input_line_pointer = save_in; | |
1026 | return 1; | |
b99bd4ef | 1027 | } |
87975d2a AM |
1028 | #else |
1029 | (void) seg; | |
c19d1205 | 1030 | #endif |
b99bd4ef | 1031 | |
c19d1205 ZW |
1032 | /* Get rid of any bignums now, so that we don't generate an error for which |
1033 | we can't establish a line number later on. Big numbers are never valid | |
1034 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
1035 | if (prefix_mode != GE_OPT_PREFIX_BIG |
1036 | && (ep->X_op == O_big | |
477330fc | 1037 | || (ep->X_add_symbol |
5287ad62 | 1038 | && (walk_no_bignums (ep->X_add_symbol) |
477330fc | 1039 | || (ep->X_op_symbol |
5287ad62 | 1040 | && walk_no_bignums (ep->X_op_symbol)))))) |
c19d1205 ZW |
1041 | { |
1042 | inst.error = _("invalid constant"); | |
1043 | *str = input_line_pointer; | |
1044 | input_line_pointer = save_in; | |
1045 | return 1; | |
1046 | } | |
b99bd4ef | 1047 | |
c19d1205 ZW |
1048 | *str = input_line_pointer; |
1049 | input_line_pointer = save_in; | |
1050 | return 0; | |
b99bd4ef NC |
1051 | } |
1052 | ||
c19d1205 ZW |
1053 | /* Turn a string in input_line_pointer into a floating point constant |
1054 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1055 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1056 | returned, or NULL on OK. | |
b99bd4ef | 1057 | |
c19d1205 ZW |
1058 | Note that fp constants aren't represent in the normal way on the ARM. |
1059 | In big endian mode, things are as expected. However, in little endian | |
1060 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1061 | within the words. For example, (double) 1.1 in big endian mode is | |
1062 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1063 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1064 | |
c19d1205 | 1065 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1066 | |
c19d1205 ZW |
1067 | char * |
1068 | md_atof (int type, char * litP, int * sizeP) | |
1069 | { | |
1070 | int prec; | |
1071 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1072 | char *t; | |
1073 | int i; | |
b99bd4ef | 1074 | |
c19d1205 ZW |
1075 | switch (type) |
1076 | { | |
1077 | case 'f': | |
1078 | case 'F': | |
1079 | case 's': | |
1080 | case 'S': | |
1081 | prec = 2; | |
1082 | break; | |
b99bd4ef | 1083 | |
c19d1205 ZW |
1084 | case 'd': |
1085 | case 'D': | |
1086 | case 'r': | |
1087 | case 'R': | |
1088 | prec = 4; | |
1089 | break; | |
b99bd4ef | 1090 | |
c19d1205 ZW |
1091 | case 'x': |
1092 | case 'X': | |
499ac353 | 1093 | prec = 5; |
c19d1205 | 1094 | break; |
b99bd4ef | 1095 | |
c19d1205 ZW |
1096 | case 'p': |
1097 | case 'P': | |
499ac353 | 1098 | prec = 5; |
c19d1205 | 1099 | break; |
a737bd4d | 1100 | |
c19d1205 ZW |
1101 | default: |
1102 | *sizeP = 0; | |
499ac353 | 1103 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1104 | } |
b99bd4ef | 1105 | |
c19d1205 ZW |
1106 | t = atof_ieee (input_line_pointer, type, words); |
1107 | if (t) | |
1108 | input_line_pointer = t; | |
499ac353 | 1109 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1110 | |
c19d1205 ZW |
1111 | if (target_big_endian) |
1112 | { | |
1113 | for (i = 0; i < prec; i++) | |
1114 | { | |
499ac353 NC |
1115 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1116 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1117 | } |
1118 | } | |
1119 | else | |
1120 | { | |
e74cfd16 | 1121 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1122 | for (i = prec - 1; i >= 0; i--) |
1123 | { | |
499ac353 NC |
1124 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1125 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1126 | } |
1127 | else | |
1128 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1129 | For an 8 byte float the order is 1 0 3 2. */ | |
1130 | for (i = 0; i < prec; i += 2) | |
1131 | { | |
499ac353 NC |
1132 | md_number_to_chars (litP, (valueT) words[i + 1], |
1133 | sizeof (LITTLENUM_TYPE)); | |
1134 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1135 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1136 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1137 | } |
1138 | } | |
b99bd4ef | 1139 | |
499ac353 | 1140 | return NULL; |
c19d1205 | 1141 | } |
b99bd4ef | 1142 | |
c19d1205 ZW |
1143 | /* We handle all bad expressions here, so that we can report the faulty |
1144 | instruction in the error message. */ | |
1145 | void | |
91d6fa6a | 1146 | md_operand (expressionS * exp) |
c19d1205 ZW |
1147 | { |
1148 | if (in_my_get_expression) | |
91d6fa6a | 1149 | exp->X_op = O_illegal; |
b99bd4ef NC |
1150 | } |
1151 | ||
c19d1205 | 1152 | /* Immediate values. */ |
b99bd4ef | 1153 | |
c19d1205 ZW |
1154 | /* Generic immediate-value read function for use in directives. |
1155 | Accepts anything that 'expression' can fold to a constant. | |
1156 | *val receives the number. */ | |
1157 | #ifdef OBJ_ELF | |
1158 | static int | |
1159 | immediate_for_directive (int *val) | |
b99bd4ef | 1160 | { |
c19d1205 ZW |
1161 | expressionS exp; |
1162 | exp.X_op = O_illegal; | |
b99bd4ef | 1163 | |
c19d1205 ZW |
1164 | if (is_immediate_prefix (*input_line_pointer)) |
1165 | { | |
1166 | input_line_pointer++; | |
1167 | expression (&exp); | |
1168 | } | |
b99bd4ef | 1169 | |
c19d1205 ZW |
1170 | if (exp.X_op != O_constant) |
1171 | { | |
1172 | as_bad (_("expected #constant")); | |
1173 | ignore_rest_of_line (); | |
1174 | return FAIL; | |
1175 | } | |
1176 | *val = exp.X_add_number; | |
1177 | return SUCCESS; | |
b99bd4ef | 1178 | } |
c19d1205 | 1179 | #endif |
b99bd4ef | 1180 | |
c19d1205 | 1181 | /* Register parsing. */ |
b99bd4ef | 1182 | |
c19d1205 ZW |
1183 | /* Generic register parser. CCP points to what should be the |
1184 | beginning of a register name. If it is indeed a valid register | |
1185 | name, advance CCP over it and return the reg_entry structure; | |
1186 | otherwise return NULL. Does not issue diagnostics. */ | |
1187 | ||
1188 | static struct reg_entry * | |
1189 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1190 | { |
c19d1205 ZW |
1191 | char *start = *ccp; |
1192 | char *p; | |
1193 | struct reg_entry *reg; | |
b99bd4ef | 1194 | |
477330fc RM |
1195 | skip_whitespace (start); |
1196 | ||
c19d1205 ZW |
1197 | #ifdef REGISTER_PREFIX |
1198 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1199 | return NULL; |
c19d1205 ZW |
1200 | start++; |
1201 | #endif | |
1202 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1203 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1204 | start++; | |
1205 | #endif | |
b99bd4ef | 1206 | |
c19d1205 ZW |
1207 | p = start; |
1208 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1209 | return NULL; | |
b99bd4ef | 1210 | |
c19d1205 ZW |
1211 | do |
1212 | p++; | |
1213 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1214 | ||
1215 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1216 | ||
1217 | if (!reg) | |
1218 | return NULL; | |
1219 | ||
1220 | *ccp = p; | |
1221 | return reg; | |
b99bd4ef NC |
1222 | } |
1223 | ||
1224 | static int | |
dcbf9037 | 1225 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
477330fc | 1226 | enum arm_reg_type type) |
b99bd4ef | 1227 | { |
c19d1205 ZW |
1228 | /* Alternative syntaxes are accepted for a few register classes. */ |
1229 | switch (type) | |
1230 | { | |
1231 | case REG_TYPE_MVF: | |
1232 | case REG_TYPE_MVD: | |
1233 | case REG_TYPE_MVFX: | |
1234 | case REG_TYPE_MVDX: | |
1235 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1236 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1237 | return reg->number; |
1238 | break; | |
69b97547 | 1239 | |
c19d1205 ZW |
1240 | case REG_TYPE_CP: |
1241 | /* For backward compatibility, a bare number is valid here. */ | |
1242 | { | |
1243 | unsigned long processor = strtoul (start, ccp, 10); | |
1244 | if (*ccp != start && processor <= 15) | |
1245 | return processor; | |
1246 | } | |
6057a28f | 1247 | |
c19d1205 ZW |
1248 | case REG_TYPE_MMXWC: |
1249 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1250 | instructions that take WC registers. */ | |
79134647 | 1251 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1252 | return reg->number; |
6057a28f | 1253 | break; |
c19d1205 | 1254 | |
6057a28f | 1255 | default: |
c19d1205 | 1256 | break; |
6057a28f NC |
1257 | } |
1258 | ||
dcbf9037 JB |
1259 | return FAIL; |
1260 | } | |
1261 | ||
1262 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1263 | return value is the register number or FAIL. */ | |
1264 | ||
1265 | static int | |
1266 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1267 | { | |
1268 | char *start = *ccp; | |
1269 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1270 | int ret; | |
1271 | ||
1272 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1273 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1274 | return FAIL; | |
1275 | ||
1276 | if (reg && reg->type == type) | |
1277 | return reg->number; | |
1278 | ||
1279 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1280 | return ret; | |
1281 | ||
c19d1205 ZW |
1282 | *ccp = start; |
1283 | return FAIL; | |
1284 | } | |
69b97547 | 1285 | |
dcbf9037 JB |
1286 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1287 | character. Does no verification at this stage that the type fits the opcode | |
1288 | properly. E.g., | |
1289 | ||
1290 | .i32.i32.s16 | |
1291 | .s32.f32 | |
1292 | .u16 | |
1293 | ||
1294 | Can all be legally parsed by this function. | |
1295 | ||
1296 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1297 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1298 | type, FAIL if not. */ | |
1299 | ||
1300 | static int | |
1301 | parse_neon_type (struct neon_type *type, char **str) | |
1302 | { | |
1303 | char *ptr = *str; | |
1304 | ||
1305 | if (type) | |
1306 | type->elems = 0; | |
1307 | ||
1308 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1309 | { | |
1310 | enum neon_el_type thistype = NT_untyped; | |
1311 | unsigned thissize = -1u; | |
1312 | ||
1313 | if (*ptr != '.') | |
1314 | break; | |
1315 | ||
1316 | ptr++; | |
1317 | ||
1318 | /* Just a size without an explicit type. */ | |
1319 | if (ISDIGIT (*ptr)) | |
1320 | goto parsesize; | |
1321 | ||
1322 | switch (TOLOWER (*ptr)) | |
1323 | { | |
1324 | case 'i': thistype = NT_integer; break; | |
1325 | case 'f': thistype = NT_float; break; | |
1326 | case 'p': thistype = NT_poly; break; | |
1327 | case 's': thistype = NT_signed; break; | |
1328 | case 'u': thistype = NT_unsigned; break; | |
477330fc RM |
1329 | case 'd': |
1330 | thistype = NT_float; | |
1331 | thissize = 64; | |
1332 | ptr++; | |
1333 | goto done; | |
dcbf9037 JB |
1334 | default: |
1335 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1336 | return FAIL; | |
1337 | } | |
1338 | ||
1339 | ptr++; | |
1340 | ||
1341 | /* .f is an abbreviation for .f32. */ | |
1342 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1343 | thissize = 32; | |
1344 | else | |
1345 | { | |
1346 | parsesize: | |
1347 | thissize = strtoul (ptr, &ptr, 10); | |
1348 | ||
1349 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
477330fc RM |
1350 | && thissize != 64) |
1351 | { | |
1352 | as_bad (_("bad size %d in type specifier"), thissize); | |
dcbf9037 JB |
1353 | return FAIL; |
1354 | } | |
1355 | } | |
1356 | ||
037e8744 | 1357 | done: |
dcbf9037 | 1358 | if (type) |
477330fc RM |
1359 | { |
1360 | type->el[type->elems].type = thistype; | |
dcbf9037 JB |
1361 | type->el[type->elems].size = thissize; |
1362 | type->elems++; | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | /* Empty/missing type is not a successful parse. */ | |
1367 | if (type->elems == 0) | |
1368 | return FAIL; | |
1369 | ||
1370 | *str = ptr; | |
1371 | ||
1372 | return SUCCESS; | |
1373 | } | |
1374 | ||
1375 | /* Errors may be set multiple times during parsing or bit encoding | |
1376 | (particularly in the Neon bits), but usually the earliest error which is set | |
1377 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1378 | errors by calling this function. */ | |
1379 | ||
1380 | static void | |
1381 | first_error (const char *err) | |
1382 | { | |
1383 | if (!inst.error) | |
1384 | inst.error = err; | |
1385 | } | |
1386 | ||
1387 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1388 | static int | |
1389 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1390 | { | |
1391 | char *str = *ccp; | |
1392 | struct neon_type optype; | |
1393 | ||
1394 | if (*str == '.') | |
1395 | { | |
1396 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
477330fc RM |
1397 | { |
1398 | if (optype.elems == 1) | |
1399 | *vectype = optype.el[0]; | |
1400 | else | |
1401 | { | |
1402 | first_error (_("only one type should be specified for operand")); | |
1403 | return FAIL; | |
1404 | } | |
1405 | } | |
dcbf9037 | 1406 | else |
477330fc RM |
1407 | { |
1408 | first_error (_("vector type expected")); | |
1409 | return FAIL; | |
1410 | } | |
dcbf9037 JB |
1411 | } |
1412 | else | |
1413 | return FAIL; | |
5f4273c7 | 1414 | |
dcbf9037 | 1415 | *ccp = str; |
5f4273c7 | 1416 | |
dcbf9037 JB |
1417 | return SUCCESS; |
1418 | } | |
1419 | ||
1420 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1421 | a 4-bit integer. */ | |
1422 | ||
1423 | #define NEON_ALL_LANES 15 | |
1424 | #define NEON_INTERLEAVE_LANES 14 | |
1425 | ||
1426 | /* Parse either a register or a scalar, with an optional type. Return the | |
1427 | register number, and optionally fill in the actual type of the register | |
1428 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1429 | type/index information in *TYPEINFO. */ | |
1430 | ||
1431 | static int | |
1432 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
477330fc RM |
1433 | enum arm_reg_type *rtype, |
1434 | struct neon_typed_alias *typeinfo) | |
dcbf9037 JB |
1435 | { |
1436 | char *str = *ccp; | |
1437 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1438 | struct neon_typed_alias atype; | |
1439 | struct neon_type_el parsetype; | |
1440 | ||
1441 | atype.defined = 0; | |
1442 | atype.index = -1; | |
1443 | atype.eltype.type = NT_invtype; | |
1444 | atype.eltype.size = -1; | |
1445 | ||
1446 | /* Try alternate syntax for some types of register. Note these are mutually | |
1447 | exclusive with the Neon syntax extensions. */ | |
1448 | if (reg == NULL) | |
1449 | { | |
1450 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1451 | if (altreg != FAIL) | |
477330fc | 1452 | *ccp = str; |
dcbf9037 | 1453 | if (typeinfo) |
477330fc | 1454 | *typeinfo = atype; |
dcbf9037 JB |
1455 | return altreg; |
1456 | } | |
1457 | ||
037e8744 JB |
1458 | /* Undo polymorphism when a set of register types may be accepted. */ |
1459 | if ((type == REG_TYPE_NDQ | |
1460 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1461 | || (type == REG_TYPE_VFSD | |
477330fc | 1462 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) |
037e8744 | 1463 | || (type == REG_TYPE_NSDQ |
477330fc RM |
1464 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD |
1465 | || reg->type == REG_TYPE_NQ)) | |
f512f76f NC |
1466 | || (type == REG_TYPE_MMXWC |
1467 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1468 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1469 | |
1470 | if (type != reg->type) | |
1471 | return FAIL; | |
1472 | ||
1473 | if (reg->neon) | |
1474 | atype = *reg->neon; | |
5f4273c7 | 1475 | |
dcbf9037 JB |
1476 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1477 | { | |
1478 | if ((atype.defined & NTA_HASTYPE) != 0) | |
477330fc RM |
1479 | { |
1480 | first_error (_("can't redefine type for operand")); | |
1481 | return FAIL; | |
1482 | } | |
dcbf9037 JB |
1483 | atype.defined |= NTA_HASTYPE; |
1484 | atype.eltype = parsetype; | |
1485 | } | |
5f4273c7 | 1486 | |
dcbf9037 JB |
1487 | if (skip_past_char (&str, '[') == SUCCESS) |
1488 | { | |
1489 | if (type != REG_TYPE_VFD) | |
477330fc RM |
1490 | { |
1491 | first_error (_("only D registers may be indexed")); | |
1492 | return FAIL; | |
1493 | } | |
5f4273c7 | 1494 | |
dcbf9037 | 1495 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
1496 | { |
1497 | first_error (_("can't change index for operand")); | |
1498 | return FAIL; | |
1499 | } | |
dcbf9037 JB |
1500 | |
1501 | atype.defined |= NTA_HASINDEX; | |
1502 | ||
1503 | if (skip_past_char (&str, ']') == SUCCESS) | |
477330fc | 1504 | atype.index = NEON_ALL_LANES; |
dcbf9037 | 1505 | else |
477330fc RM |
1506 | { |
1507 | expressionS exp; | |
dcbf9037 | 1508 | |
477330fc | 1509 | my_get_expression (&exp, &str, GE_NO_PREFIX); |
dcbf9037 | 1510 | |
477330fc RM |
1511 | if (exp.X_op != O_constant) |
1512 | { | |
1513 | first_error (_("constant expression required")); | |
1514 | return FAIL; | |
1515 | } | |
dcbf9037 | 1516 | |
477330fc RM |
1517 | if (skip_past_char (&str, ']') == FAIL) |
1518 | return FAIL; | |
dcbf9037 | 1519 | |
477330fc RM |
1520 | atype.index = exp.X_add_number; |
1521 | } | |
dcbf9037 | 1522 | } |
5f4273c7 | 1523 | |
dcbf9037 JB |
1524 | if (typeinfo) |
1525 | *typeinfo = atype; | |
5f4273c7 | 1526 | |
dcbf9037 JB |
1527 | if (rtype) |
1528 | *rtype = type; | |
5f4273c7 | 1529 | |
dcbf9037 | 1530 | *ccp = str; |
5f4273c7 | 1531 | |
dcbf9037 JB |
1532 | return reg->number; |
1533 | } | |
1534 | ||
1535 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1536 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1537 | register (e.g. Neon double or quad reg when either has been requested). | |
1538 | - If this is a Neon vector type with additional type information, fill | |
1539 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1540 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1541 | |
1542 | static int | |
1543 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
477330fc | 1544 | enum arm_reg_type *rtype, struct neon_type_el *vectype) |
dcbf9037 JB |
1545 | { |
1546 | struct neon_typed_alias atype; | |
1547 | char *str = *ccp; | |
1548 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1549 | ||
1550 | if (reg == FAIL) | |
1551 | return FAIL; | |
1552 | ||
0855e32b NS |
1553 | /* Do not allow regname(... to parse as a register. */ |
1554 | if (*str == '(') | |
1555 | return FAIL; | |
1556 | ||
dcbf9037 JB |
1557 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1558 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1559 | { | |
1560 | first_error (_("register operand expected, but got scalar")); | |
1561 | return FAIL; | |
1562 | } | |
1563 | ||
1564 | if (vectype) | |
1565 | *vectype = atype.eltype; | |
1566 | ||
1567 | *ccp = str; | |
1568 | ||
1569 | return reg; | |
1570 | } | |
1571 | ||
1572 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1573 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1574 | ||
5287ad62 JB |
1575 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1576 | have enough information to be able to do a good job bounds-checking. So, we | |
1577 | just do easy checks here, and do further checks later. */ | |
1578 | ||
1579 | static int | |
dcbf9037 | 1580 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1581 | { |
dcbf9037 | 1582 | int reg; |
5287ad62 | 1583 | char *str = *ccp; |
dcbf9037 | 1584 | struct neon_typed_alias atype; |
5f4273c7 | 1585 | |
dcbf9037 | 1586 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1587 | |
dcbf9037 | 1588 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1589 | return FAIL; |
5f4273c7 | 1590 | |
dcbf9037 | 1591 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1592 | { |
dcbf9037 | 1593 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1594 | return FAIL; |
1595 | } | |
dcbf9037 | 1596 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1597 | { |
dcbf9037 | 1598 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1599 | return FAIL; |
1600 | } | |
5f4273c7 | 1601 | |
dcbf9037 JB |
1602 | if (type) |
1603 | *type = atype.eltype; | |
5f4273c7 | 1604 | |
5287ad62 | 1605 | *ccp = str; |
5f4273c7 | 1606 | |
dcbf9037 | 1607 | return reg * 16 + atype.index; |
5287ad62 JB |
1608 | } |
1609 | ||
c19d1205 | 1610 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1611 | |
c19d1205 ZW |
1612 | static long |
1613 | parse_reg_list (char ** strp) | |
1614 | { | |
1615 | char * str = * strp; | |
1616 | long range = 0; | |
1617 | int another_range; | |
a737bd4d | 1618 | |
c19d1205 ZW |
1619 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1620 | do | |
6057a28f | 1621 | { |
477330fc RM |
1622 | skip_whitespace (str); |
1623 | ||
c19d1205 | 1624 | another_range = 0; |
a737bd4d | 1625 | |
c19d1205 ZW |
1626 | if (*str == '{') |
1627 | { | |
1628 | int in_range = 0; | |
1629 | int cur_reg = -1; | |
a737bd4d | 1630 | |
c19d1205 ZW |
1631 | str++; |
1632 | do | |
1633 | { | |
1634 | int reg; | |
6057a28f | 1635 | |
dcbf9037 | 1636 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1637 | { |
dcbf9037 | 1638 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1639 | return FAIL; |
1640 | } | |
a737bd4d | 1641 | |
c19d1205 ZW |
1642 | if (in_range) |
1643 | { | |
1644 | int i; | |
a737bd4d | 1645 | |
c19d1205 ZW |
1646 | if (reg <= cur_reg) |
1647 | { | |
dcbf9037 | 1648 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1649 | return FAIL; |
1650 | } | |
40a18ebd | 1651 | |
c19d1205 ZW |
1652 | for (i = cur_reg + 1; i < reg; i++) |
1653 | { | |
1654 | if (range & (1 << i)) | |
1655 | as_tsktsk | |
1656 | (_("Warning: duplicated register (r%d) in register list"), | |
1657 | i); | |
1658 | else | |
1659 | range |= 1 << i; | |
1660 | } | |
1661 | in_range = 0; | |
1662 | } | |
a737bd4d | 1663 | |
c19d1205 ZW |
1664 | if (range & (1 << reg)) |
1665 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1666 | reg); | |
1667 | else if (reg <= cur_reg) | |
1668 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1669 | |
c19d1205 ZW |
1670 | range |= 1 << reg; |
1671 | cur_reg = reg; | |
1672 | } | |
1673 | while (skip_past_comma (&str) != FAIL | |
1674 | || (in_range = 1, *str++ == '-')); | |
1675 | str--; | |
a737bd4d | 1676 | |
d996d970 | 1677 | if (skip_past_char (&str, '}') == FAIL) |
c19d1205 | 1678 | { |
dcbf9037 | 1679 | first_error (_("missing `}'")); |
c19d1205 ZW |
1680 | return FAIL; |
1681 | } | |
1682 | } | |
1683 | else | |
1684 | { | |
91d6fa6a | 1685 | expressionS exp; |
40a18ebd | 1686 | |
91d6fa6a | 1687 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1688 | return FAIL; |
40a18ebd | 1689 | |
91d6fa6a | 1690 | if (exp.X_op == O_constant) |
c19d1205 | 1691 | { |
91d6fa6a NC |
1692 | if (exp.X_add_number |
1693 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1694 | { |
1695 | inst.error = _("invalid register mask"); | |
1696 | return FAIL; | |
1697 | } | |
a737bd4d | 1698 | |
91d6fa6a | 1699 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1700 | { |
91d6fa6a | 1701 | int regno = range & exp.X_add_number; |
a737bd4d | 1702 | |
c19d1205 ZW |
1703 | regno &= -regno; |
1704 | regno = (1 << regno) - 1; | |
1705 | as_tsktsk | |
1706 | (_("Warning: duplicated register (r%d) in register list"), | |
1707 | regno); | |
1708 | } | |
a737bd4d | 1709 | |
91d6fa6a | 1710 | range |= exp.X_add_number; |
c19d1205 ZW |
1711 | } |
1712 | else | |
1713 | { | |
1714 | if (inst.reloc.type != 0) | |
1715 | { | |
1716 | inst.error = _("expression too complex"); | |
1717 | return FAIL; | |
1718 | } | |
a737bd4d | 1719 | |
91d6fa6a | 1720 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1721 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1722 | inst.reloc.pc_rel = 0; | |
1723 | } | |
1724 | } | |
a737bd4d | 1725 | |
c19d1205 ZW |
1726 | if (*str == '|' || *str == '+') |
1727 | { | |
1728 | str++; | |
1729 | another_range = 1; | |
1730 | } | |
a737bd4d | 1731 | } |
c19d1205 | 1732 | while (another_range); |
a737bd4d | 1733 | |
c19d1205 ZW |
1734 | *strp = str; |
1735 | return range; | |
a737bd4d NC |
1736 | } |
1737 | ||
5287ad62 JB |
1738 | /* Types of registers in a list. */ |
1739 | ||
1740 | enum reg_list_els | |
1741 | { | |
1742 | REGLIST_VFP_S, | |
1743 | REGLIST_VFP_D, | |
1744 | REGLIST_NEON_D | |
1745 | }; | |
1746 | ||
c19d1205 ZW |
1747 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1748 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1749 | register. Parses registers of type ETYPE. |
1750 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1751 | - Q registers can be used to specify pairs of D registers | |
1752 | - { } can be omitted from around a singleton register list | |
477330fc RM |
1753 | FIXME: This is not implemented, as it would require backtracking in |
1754 | some cases, e.g.: | |
1755 | vtbl.8 d3,d4,d5 | |
1756 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1757 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1758 | - 32 D registers may be used (also true for VFPv3). |
1759 | FIXME: Types are ignored in these register lists, which is probably a | |
1760 | bug. */ | |
6057a28f | 1761 | |
c19d1205 | 1762 | static int |
037e8744 | 1763 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1764 | { |
037e8744 | 1765 | char *str = *ccp; |
c19d1205 ZW |
1766 | int base_reg; |
1767 | int new_base; | |
21d799b5 | 1768 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1769 | int max_regs = 0; |
c19d1205 ZW |
1770 | int count = 0; |
1771 | int warned = 0; | |
1772 | unsigned long mask = 0; | |
a737bd4d | 1773 | int i; |
6057a28f | 1774 | |
477330fc | 1775 | if (skip_past_char (&str, '{') == FAIL) |
5287ad62 JB |
1776 | { |
1777 | inst.error = _("expecting {"); | |
1778 | return FAIL; | |
1779 | } | |
6057a28f | 1780 | |
5287ad62 | 1781 | switch (etype) |
c19d1205 | 1782 | { |
5287ad62 | 1783 | case REGLIST_VFP_S: |
c19d1205 ZW |
1784 | regtype = REG_TYPE_VFS; |
1785 | max_regs = 32; | |
5287ad62 | 1786 | break; |
5f4273c7 | 1787 | |
5287ad62 JB |
1788 | case REGLIST_VFP_D: |
1789 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1790 | break; |
5f4273c7 | 1791 | |
b7fc2769 JB |
1792 | case REGLIST_NEON_D: |
1793 | regtype = REG_TYPE_NDQ; | |
1794 | break; | |
1795 | } | |
1796 | ||
1797 | if (etype != REGLIST_VFP_S) | |
1798 | { | |
b1cc4aeb PB |
1799 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1800 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
477330fc RM |
1801 | { |
1802 | max_regs = 32; | |
1803 | if (thumb_mode) | |
1804 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
1805 | fpu_vfp_ext_d32); | |
1806 | else | |
1807 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
1808 | fpu_vfp_ext_d32); | |
1809 | } | |
5287ad62 | 1810 | else |
477330fc | 1811 | max_regs = 16; |
c19d1205 | 1812 | } |
6057a28f | 1813 | |
c19d1205 | 1814 | base_reg = max_regs; |
a737bd4d | 1815 | |
c19d1205 ZW |
1816 | do |
1817 | { | |
5287ad62 | 1818 | int setmask = 1, addregs = 1; |
dcbf9037 | 1819 | |
037e8744 | 1820 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1821 | |
c19d1205 | 1822 | if (new_base == FAIL) |
a737bd4d | 1823 | { |
dcbf9037 | 1824 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1825 | return FAIL; |
1826 | } | |
5f4273c7 | 1827 | |
b7fc2769 | 1828 | if (new_base >= max_regs) |
477330fc RM |
1829 | { |
1830 | first_error (_("register out of range in list")); | |
1831 | return FAIL; | |
1832 | } | |
5f4273c7 | 1833 | |
5287ad62 JB |
1834 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1835 | if (regtype == REG_TYPE_NQ) | |
477330fc RM |
1836 | { |
1837 | setmask = 3; | |
1838 | addregs = 2; | |
1839 | } | |
5287ad62 | 1840 | |
c19d1205 ZW |
1841 | if (new_base < base_reg) |
1842 | base_reg = new_base; | |
a737bd4d | 1843 | |
5287ad62 | 1844 | if (mask & (setmask << new_base)) |
c19d1205 | 1845 | { |
dcbf9037 | 1846 | first_error (_("invalid register list")); |
c19d1205 | 1847 | return FAIL; |
a737bd4d | 1848 | } |
a737bd4d | 1849 | |
c19d1205 ZW |
1850 | if ((mask >> new_base) != 0 && ! warned) |
1851 | { | |
1852 | as_tsktsk (_("register list not in ascending order")); | |
1853 | warned = 1; | |
1854 | } | |
0bbf2aa4 | 1855 | |
5287ad62 JB |
1856 | mask |= setmask << new_base; |
1857 | count += addregs; | |
0bbf2aa4 | 1858 | |
037e8744 | 1859 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1860 | { |
1861 | int high_range; | |
0bbf2aa4 | 1862 | |
037e8744 | 1863 | str++; |
0bbf2aa4 | 1864 | |
037e8744 | 1865 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
477330fc | 1866 | == FAIL) |
c19d1205 ZW |
1867 | { |
1868 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1869 | return FAIL; | |
1870 | } | |
0bbf2aa4 | 1871 | |
477330fc RM |
1872 | if (high_range >= max_regs) |
1873 | { | |
1874 | first_error (_("register out of range in list")); | |
1875 | return FAIL; | |
1876 | } | |
b7fc2769 | 1877 | |
477330fc RM |
1878 | if (regtype == REG_TYPE_NQ) |
1879 | high_range = high_range + 1; | |
5287ad62 | 1880 | |
c19d1205 ZW |
1881 | if (high_range <= new_base) |
1882 | { | |
1883 | inst.error = _("register range not in ascending order"); | |
1884 | return FAIL; | |
1885 | } | |
0bbf2aa4 | 1886 | |
5287ad62 | 1887 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1888 | { |
5287ad62 | 1889 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1890 | { |
c19d1205 ZW |
1891 | inst.error = _("invalid register list"); |
1892 | return FAIL; | |
0bbf2aa4 | 1893 | } |
c19d1205 | 1894 | |
5287ad62 JB |
1895 | mask |= setmask << new_base; |
1896 | count += addregs; | |
0bbf2aa4 | 1897 | } |
0bbf2aa4 | 1898 | } |
0bbf2aa4 | 1899 | } |
037e8744 | 1900 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1901 | |
037e8744 | 1902 | str++; |
0bbf2aa4 | 1903 | |
c19d1205 ZW |
1904 | /* Sanity check -- should have raised a parse error above. */ |
1905 | if (count == 0 || count > max_regs) | |
1906 | abort (); | |
1907 | ||
1908 | *pbase = base_reg; | |
1909 | ||
1910 | /* Final test -- the registers must be consecutive. */ | |
1911 | mask >>= base_reg; | |
1912 | for (i = 0; i < count; i++) | |
1913 | { | |
1914 | if ((mask & (1u << i)) == 0) | |
1915 | { | |
1916 | inst.error = _("non-contiguous register range"); | |
1917 | return FAIL; | |
1918 | } | |
1919 | } | |
1920 | ||
037e8744 JB |
1921 | *ccp = str; |
1922 | ||
c19d1205 | 1923 | return count; |
b99bd4ef NC |
1924 | } |
1925 | ||
dcbf9037 JB |
1926 | /* True if two alias types are the same. */ |
1927 | ||
c921be7d | 1928 | static bfd_boolean |
dcbf9037 JB |
1929 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1930 | { | |
1931 | if (!a && !b) | |
c921be7d | 1932 | return TRUE; |
5f4273c7 | 1933 | |
dcbf9037 | 1934 | if (!a || !b) |
c921be7d | 1935 | return FALSE; |
dcbf9037 JB |
1936 | |
1937 | if (a->defined != b->defined) | |
c921be7d | 1938 | return FALSE; |
5f4273c7 | 1939 | |
dcbf9037 JB |
1940 | if ((a->defined & NTA_HASTYPE) != 0 |
1941 | && (a->eltype.type != b->eltype.type | |
477330fc | 1942 | || a->eltype.size != b->eltype.size)) |
c921be7d | 1943 | return FALSE; |
dcbf9037 JB |
1944 | |
1945 | if ((a->defined & NTA_HASINDEX) != 0 | |
1946 | && (a->index != b->index)) | |
c921be7d | 1947 | return FALSE; |
5f4273c7 | 1948 | |
c921be7d | 1949 | return TRUE; |
dcbf9037 JB |
1950 | } |
1951 | ||
5287ad62 JB |
1952 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1953 | The base register is put in *PBASE. | |
dcbf9037 | 1954 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1955 | the return value. |
1956 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1957 | Bits [6:5] encode the list length (minus one). |
1958 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1959 | |
5287ad62 | 1960 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1961 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1962 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1963 | ||
1964 | static int | |
dcbf9037 | 1965 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
477330fc | 1966 | struct neon_type_el *eltype) |
5287ad62 JB |
1967 | { |
1968 | char *ptr = *str; | |
1969 | int base_reg = -1; | |
1970 | int reg_incr = -1; | |
1971 | int count = 0; | |
1972 | int lane = -1; | |
1973 | int leading_brace = 0; | |
1974 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1975 | const char *const incr_error = _("register stride must be 1 or 2"); |
1976 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1977 | struct neon_typed_alias firsttype; |
5f4273c7 | 1978 | |
5287ad62 JB |
1979 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1980 | leading_brace = 1; | |
5f4273c7 | 1981 | |
5287ad62 JB |
1982 | do |
1983 | { | |
dcbf9037 JB |
1984 | struct neon_typed_alias atype; |
1985 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1986 | ||
5287ad62 | 1987 | if (getreg == FAIL) |
477330fc RM |
1988 | { |
1989 | first_error (_(reg_expected_msgs[rtype])); | |
1990 | return FAIL; | |
1991 | } | |
5f4273c7 | 1992 | |
5287ad62 | 1993 | if (base_reg == -1) |
477330fc RM |
1994 | { |
1995 | base_reg = getreg; | |
1996 | if (rtype == REG_TYPE_NQ) | |
1997 | { | |
1998 | reg_incr = 1; | |
1999 | } | |
2000 | firsttype = atype; | |
2001 | } | |
5287ad62 | 2002 | else if (reg_incr == -1) |
477330fc RM |
2003 | { |
2004 | reg_incr = getreg - base_reg; | |
2005 | if (reg_incr < 1 || reg_incr > 2) | |
2006 | { | |
2007 | first_error (_(incr_error)); | |
2008 | return FAIL; | |
2009 | } | |
2010 | } | |
5287ad62 | 2011 | else if (getreg != base_reg + reg_incr * count) |
477330fc RM |
2012 | { |
2013 | first_error (_(incr_error)); | |
2014 | return FAIL; | |
2015 | } | |
dcbf9037 | 2016 | |
c921be7d | 2017 | if (! neon_alias_types_same (&atype, &firsttype)) |
477330fc RM |
2018 | { |
2019 | first_error (_(type_error)); | |
2020 | return FAIL; | |
2021 | } | |
5f4273c7 | 2022 | |
5287ad62 | 2023 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
477330fc | 2024 | modes. */ |
5287ad62 | 2025 | if (ptr[0] == '-') |
477330fc RM |
2026 | { |
2027 | struct neon_typed_alias htype; | |
2028 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; | |
2029 | if (lane == -1) | |
2030 | lane = NEON_INTERLEAVE_LANES; | |
2031 | else if (lane != NEON_INTERLEAVE_LANES) | |
2032 | { | |
2033 | first_error (_(type_error)); | |
2034 | return FAIL; | |
2035 | } | |
2036 | if (reg_incr == -1) | |
2037 | reg_incr = 1; | |
2038 | else if (reg_incr != 1) | |
2039 | { | |
2040 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); | |
2041 | return FAIL; | |
2042 | } | |
2043 | ptr++; | |
2044 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); | |
2045 | if (hireg == FAIL) | |
2046 | { | |
2047 | first_error (_(reg_expected_msgs[rtype])); | |
2048 | return FAIL; | |
2049 | } | |
2050 | if (! neon_alias_types_same (&htype, &firsttype)) | |
2051 | { | |
2052 | first_error (_(type_error)); | |
2053 | return FAIL; | |
2054 | } | |
2055 | count += hireg + dregs - getreg; | |
2056 | continue; | |
2057 | } | |
5f4273c7 | 2058 | |
5287ad62 JB |
2059 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2060 | if (rtype == REG_TYPE_NQ) | |
477330fc RM |
2061 | { |
2062 | count += 2; | |
2063 | continue; | |
2064 | } | |
5f4273c7 | 2065 | |
dcbf9037 | 2066 | if ((atype.defined & NTA_HASINDEX) != 0) |
477330fc RM |
2067 | { |
2068 | if (lane == -1) | |
2069 | lane = atype.index; | |
2070 | else if (lane != atype.index) | |
2071 | { | |
2072 | first_error (_(type_error)); | |
2073 | return FAIL; | |
2074 | } | |
2075 | } | |
5287ad62 | 2076 | else if (lane == -1) |
477330fc | 2077 | lane = NEON_INTERLEAVE_LANES; |
5287ad62 | 2078 | else if (lane != NEON_INTERLEAVE_LANES) |
477330fc RM |
2079 | { |
2080 | first_error (_(type_error)); | |
2081 | return FAIL; | |
2082 | } | |
5287ad62 JB |
2083 | count++; |
2084 | } | |
2085 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2086 | |
5287ad62 JB |
2087 | /* No lane set by [x]. We must be interleaving structures. */ |
2088 | if (lane == -1) | |
2089 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2090 | |
5287ad62 JB |
2091 | /* Sanity check. */ |
2092 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2093 | || (count > 1 && reg_incr == -1)) | |
2094 | { | |
dcbf9037 | 2095 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2096 | return FAIL; |
2097 | } | |
2098 | ||
2099 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2100 | { | |
dcbf9037 | 2101 | first_error (_("expected }")); |
5287ad62 JB |
2102 | return FAIL; |
2103 | } | |
5f4273c7 | 2104 | |
5287ad62 JB |
2105 | if (reg_incr == -1) |
2106 | reg_incr = 1; | |
2107 | ||
dcbf9037 JB |
2108 | if (eltype) |
2109 | *eltype = firsttype.eltype; | |
2110 | ||
5287ad62 JB |
2111 | *pbase = base_reg; |
2112 | *str = ptr; | |
5f4273c7 | 2113 | |
5287ad62 JB |
2114 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2115 | } | |
2116 | ||
c19d1205 ZW |
2117 | /* Parse an explicit relocation suffix on an expression. This is |
2118 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2119 | arm_reloc_hsh contains no entries, so this function can only | |
2120 | succeed if there is no () after the word. Returns -1 on error, | |
2121 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2122 | |
c19d1205 ZW |
2123 | static int |
2124 | parse_reloc (char **str) | |
b99bd4ef | 2125 | { |
c19d1205 ZW |
2126 | struct reloc_entry *r; |
2127 | char *p, *q; | |
b99bd4ef | 2128 | |
c19d1205 ZW |
2129 | if (**str != '(') |
2130 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2131 | |
c19d1205 ZW |
2132 | p = *str + 1; |
2133 | q = p; | |
2134 | ||
2135 | while (*q && *q != ')' && *q != ',') | |
2136 | q++; | |
2137 | if (*q != ')') | |
2138 | return -1; | |
2139 | ||
21d799b5 NC |
2140 | if ((r = (struct reloc_entry *) |
2141 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2142 | return -1; |
2143 | ||
2144 | *str = q + 1; | |
2145 | return r->reloc; | |
b99bd4ef NC |
2146 | } |
2147 | ||
c19d1205 ZW |
2148 | /* Directives: register aliases. */ |
2149 | ||
dcbf9037 | 2150 | static struct reg_entry * |
90ec0d68 | 2151 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2152 | { |
d3ce72d0 | 2153 | struct reg_entry *new_reg; |
c19d1205 | 2154 | const char *name; |
b99bd4ef | 2155 | |
d3ce72d0 | 2156 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2157 | { |
d3ce72d0 | 2158 | if (new_reg->builtin) |
c19d1205 | 2159 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2160 | |
c19d1205 ZW |
2161 | /* Only warn about a redefinition if it's not defined as the |
2162 | same register. */ | |
d3ce72d0 | 2163 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2164 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2165 | |
d929913e | 2166 | return NULL; |
c19d1205 | 2167 | } |
b99bd4ef | 2168 | |
c19d1205 | 2169 | name = xstrdup (str); |
d3ce72d0 | 2170 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2171 | |
d3ce72d0 NC |
2172 | new_reg->name = name; |
2173 | new_reg->number = number; | |
2174 | new_reg->type = type; | |
2175 | new_reg->builtin = FALSE; | |
2176 | new_reg->neon = NULL; | |
b99bd4ef | 2177 | |
d3ce72d0 | 2178 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2179 | abort (); |
5f4273c7 | 2180 | |
d3ce72d0 | 2181 | return new_reg; |
dcbf9037 JB |
2182 | } |
2183 | ||
2184 | static void | |
2185 | insert_neon_reg_alias (char *str, int number, int type, | |
477330fc | 2186 | struct neon_typed_alias *atype) |
dcbf9037 JB |
2187 | { |
2188 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2189 | |
dcbf9037 JB |
2190 | if (!reg) |
2191 | { | |
2192 | first_error (_("attempt to redefine typed alias")); | |
2193 | return; | |
2194 | } | |
5f4273c7 | 2195 | |
dcbf9037 JB |
2196 | if (atype) |
2197 | { | |
21d799b5 | 2198 | reg->neon = (struct neon_typed_alias *) |
477330fc | 2199 | xmalloc (sizeof (struct neon_typed_alias)); |
dcbf9037 JB |
2200 | *reg->neon = *atype; |
2201 | } | |
c19d1205 | 2202 | } |
b99bd4ef | 2203 | |
c19d1205 | 2204 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2205 | |
c19d1205 | 2206 | new_register_name .req existing_register_name |
b99bd4ef | 2207 | |
c19d1205 | 2208 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2209 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2210 | |
d929913e | 2211 | static bfd_boolean |
c19d1205 ZW |
2212 | create_register_alias (char * newname, char *p) |
2213 | { | |
2214 | struct reg_entry *old; | |
2215 | char *oldname, *nbuf; | |
2216 | size_t nlen; | |
b99bd4ef | 2217 | |
c19d1205 ZW |
2218 | /* The input scrubber ensures that whitespace after the mnemonic is |
2219 | collapsed to single spaces. */ | |
2220 | oldname = p; | |
2221 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2222 | return FALSE; |
b99bd4ef | 2223 | |
c19d1205 ZW |
2224 | oldname += 6; |
2225 | if (*oldname == '\0') | |
d929913e | 2226 | return FALSE; |
b99bd4ef | 2227 | |
21d799b5 | 2228 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2229 | if (!old) |
b99bd4ef | 2230 | { |
c19d1205 | 2231 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2232 | return TRUE; |
b99bd4ef NC |
2233 | } |
2234 | ||
c19d1205 ZW |
2235 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2236 | the desired alias name, and p points to its end. If not, then | |
2237 | the desired alias name is in the global original_case_string. */ | |
2238 | #ifdef TC_CASE_SENSITIVE | |
2239 | nlen = p - newname; | |
2240 | #else | |
2241 | newname = original_case_string; | |
2242 | nlen = strlen (newname); | |
2243 | #endif | |
b99bd4ef | 2244 | |
21d799b5 | 2245 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2246 | memcpy (nbuf, newname, nlen); |
2247 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2248 | |
c19d1205 ZW |
2249 | /* Create aliases under the new name as stated; an all-lowercase |
2250 | version of the new name; and an all-uppercase version of the new | |
2251 | name. */ | |
d929913e NC |
2252 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2253 | { | |
2254 | for (p = nbuf; *p; p++) | |
2255 | *p = TOUPPER (*p); | |
c19d1205 | 2256 | |
d929913e NC |
2257 | if (strncmp (nbuf, newname, nlen)) |
2258 | { | |
2259 | /* If this attempt to create an additional alias fails, do not bother | |
2260 | trying to create the all-lower case alias. We will fail and issue | |
2261 | a second, duplicate error message. This situation arises when the | |
2262 | programmer does something like: | |
2263 | foo .req r0 | |
2264 | Foo .req r1 | |
2265 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2266 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2267 | first .req. */ |
2268 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2269 | return TRUE; | |
2270 | } | |
c19d1205 | 2271 | |
d929913e NC |
2272 | for (p = nbuf; *p; p++) |
2273 | *p = TOLOWER (*p); | |
c19d1205 | 2274 | |
d929913e NC |
2275 | if (strncmp (nbuf, newname, nlen)) |
2276 | insert_reg_alias (nbuf, old->number, old->type); | |
2277 | } | |
c19d1205 | 2278 | |
d929913e | 2279 | return TRUE; |
b99bd4ef NC |
2280 | } |
2281 | ||
dcbf9037 JB |
2282 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2283 | X .dn d5.s32[1] | |
2284 | Y .qn 6.s16 | |
2285 | Z .dn d7 | |
2286 | T .dn Z[0] | |
2287 | These typed registers can be used instead of the types specified after the | |
2288 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2289 | specified directly, e.g.: | |
5f4273c7 | 2290 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2291 | |
c921be7d | 2292 | static bfd_boolean |
dcbf9037 JB |
2293 | create_neon_reg_alias (char *newname, char *p) |
2294 | { | |
2295 | enum arm_reg_type basetype; | |
2296 | struct reg_entry *basereg; | |
2297 | struct reg_entry mybasereg; | |
2298 | struct neon_type ntype; | |
2299 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2300 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2301 | int namelen; |
5f4273c7 | 2302 | |
dcbf9037 JB |
2303 | typeinfo.defined = 0; |
2304 | typeinfo.eltype.type = NT_invtype; | |
2305 | typeinfo.eltype.size = -1; | |
2306 | typeinfo.index = -1; | |
5f4273c7 | 2307 | |
dcbf9037 | 2308 | nameend = p; |
5f4273c7 | 2309 | |
dcbf9037 JB |
2310 | if (strncmp (p, " .dn ", 5) == 0) |
2311 | basetype = REG_TYPE_VFD; | |
2312 | else if (strncmp (p, " .qn ", 5) == 0) | |
2313 | basetype = REG_TYPE_NQ; | |
2314 | else | |
c921be7d | 2315 | return FALSE; |
5f4273c7 | 2316 | |
dcbf9037 | 2317 | p += 5; |
5f4273c7 | 2318 | |
dcbf9037 | 2319 | if (*p == '\0') |
c921be7d | 2320 | return FALSE; |
5f4273c7 | 2321 | |
dcbf9037 JB |
2322 | basereg = arm_reg_parse_multi (&p); |
2323 | ||
2324 | if (basereg && basereg->type != basetype) | |
2325 | { | |
2326 | as_bad (_("bad type for register")); | |
c921be7d | 2327 | return FALSE; |
dcbf9037 JB |
2328 | } |
2329 | ||
2330 | if (basereg == NULL) | |
2331 | { | |
2332 | expressionS exp; | |
2333 | /* Try parsing as an integer. */ | |
2334 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2335 | if (exp.X_op != O_constant) | |
477330fc RM |
2336 | { |
2337 | as_bad (_("expression must be constant")); | |
2338 | return FALSE; | |
2339 | } | |
dcbf9037 JB |
2340 | basereg = &mybasereg; |
2341 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
477330fc | 2342 | : exp.X_add_number; |
dcbf9037 JB |
2343 | basereg->neon = 0; |
2344 | } | |
2345 | ||
2346 | if (basereg->neon) | |
2347 | typeinfo = *basereg->neon; | |
2348 | ||
2349 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2350 | { | |
2351 | /* We got a type. */ | |
2352 | if (typeinfo.defined & NTA_HASTYPE) | |
477330fc RM |
2353 | { |
2354 | as_bad (_("can't redefine the type of a register alias")); | |
2355 | return FALSE; | |
2356 | } | |
5f4273c7 | 2357 | |
dcbf9037 JB |
2358 | typeinfo.defined |= NTA_HASTYPE; |
2359 | if (ntype.elems != 1) | |
477330fc RM |
2360 | { |
2361 | as_bad (_("you must specify a single type only")); | |
2362 | return FALSE; | |
2363 | } | |
dcbf9037 JB |
2364 | typeinfo.eltype = ntype.el[0]; |
2365 | } | |
5f4273c7 | 2366 | |
dcbf9037 JB |
2367 | if (skip_past_char (&p, '[') == SUCCESS) |
2368 | { | |
2369 | expressionS exp; | |
2370 | /* We got a scalar index. */ | |
5f4273c7 | 2371 | |
dcbf9037 | 2372 | if (typeinfo.defined & NTA_HASINDEX) |
477330fc RM |
2373 | { |
2374 | as_bad (_("can't redefine the index of a scalar alias")); | |
2375 | return FALSE; | |
2376 | } | |
5f4273c7 | 2377 | |
dcbf9037 | 2378 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2379 | |
dcbf9037 | 2380 | if (exp.X_op != O_constant) |
477330fc RM |
2381 | { |
2382 | as_bad (_("scalar index must be constant")); | |
2383 | return FALSE; | |
2384 | } | |
5f4273c7 | 2385 | |
dcbf9037 JB |
2386 | typeinfo.defined |= NTA_HASINDEX; |
2387 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2388 | |
dcbf9037 | 2389 | if (skip_past_char (&p, ']') == FAIL) |
477330fc RM |
2390 | { |
2391 | as_bad (_("expecting ]")); | |
2392 | return FALSE; | |
2393 | } | |
dcbf9037 JB |
2394 | } |
2395 | ||
15735687 NS |
2396 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2397 | the desired alias name, and p points to its end. If not, then | |
2398 | the desired alias name is in the global original_case_string. */ | |
2399 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2400 | namelen = nameend - newname; |
15735687 NS |
2401 | #else |
2402 | newname = original_case_string; | |
2403 | namelen = strlen (newname); | |
2404 | #endif | |
2405 | ||
21d799b5 | 2406 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2407 | strncpy (namebuf, newname, namelen); |
2408 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2409 | |
dcbf9037 | 2410 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
477330fc | 2411 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2412 | |
dcbf9037 JB |
2413 | /* Insert name in all uppercase. */ |
2414 | for (p = namebuf; *p; p++) | |
2415 | *p = TOUPPER (*p); | |
5f4273c7 | 2416 | |
dcbf9037 JB |
2417 | if (strncmp (namebuf, newname, namelen)) |
2418 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2419 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2420 | |
dcbf9037 JB |
2421 | /* Insert name in all lowercase. */ |
2422 | for (p = namebuf; *p; p++) | |
2423 | *p = TOLOWER (*p); | |
5f4273c7 | 2424 | |
dcbf9037 JB |
2425 | if (strncmp (namebuf, newname, namelen)) |
2426 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
477330fc | 2427 | typeinfo.defined != 0 ? &typeinfo : NULL); |
5f4273c7 | 2428 | |
c921be7d | 2429 | return TRUE; |
dcbf9037 JB |
2430 | } |
2431 | ||
c19d1205 ZW |
2432 | /* Should never be called, as .req goes between the alias and the |
2433 | register name, not at the beginning of the line. */ | |
c921be7d | 2434 | |
b99bd4ef | 2435 | static void |
c19d1205 | 2436 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2437 | { |
c19d1205 ZW |
2438 | as_bad (_("invalid syntax for .req directive")); |
2439 | } | |
b99bd4ef | 2440 | |
dcbf9037 JB |
2441 | static void |
2442 | s_dn (int a ATTRIBUTE_UNUSED) | |
2443 | { | |
2444 | as_bad (_("invalid syntax for .dn directive")); | |
2445 | } | |
2446 | ||
2447 | static void | |
2448 | s_qn (int a ATTRIBUTE_UNUSED) | |
2449 | { | |
2450 | as_bad (_("invalid syntax for .qn directive")); | |
2451 | } | |
2452 | ||
c19d1205 ZW |
2453 | /* The .unreq directive deletes an alias which was previously defined |
2454 | by .req. For example: | |
b99bd4ef | 2455 | |
c19d1205 ZW |
2456 | my_alias .req r11 |
2457 | .unreq my_alias */ | |
b99bd4ef NC |
2458 | |
2459 | static void | |
c19d1205 | 2460 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2461 | { |
c19d1205 ZW |
2462 | char * name; |
2463 | char saved_char; | |
b99bd4ef | 2464 | |
c19d1205 ZW |
2465 | name = input_line_pointer; |
2466 | ||
2467 | while (*input_line_pointer != 0 | |
2468 | && *input_line_pointer != ' ' | |
2469 | && *input_line_pointer != '\n') | |
2470 | ++input_line_pointer; | |
2471 | ||
2472 | saved_char = *input_line_pointer; | |
2473 | *input_line_pointer = 0; | |
2474 | ||
2475 | if (!*name) | |
2476 | as_bad (_("invalid syntax for .unreq directive")); | |
2477 | else | |
2478 | { | |
21d799b5 | 2479 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
477330fc | 2480 | name); |
c19d1205 ZW |
2481 | |
2482 | if (!reg) | |
2483 | as_bad (_("unknown register alias '%s'"), name); | |
2484 | else if (reg->builtin) | |
a1727c1a | 2485 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2486 | name); |
2487 | else | |
2488 | { | |
d929913e NC |
2489 | char * p; |
2490 | char * nbuf; | |
2491 | ||
db0bc284 | 2492 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2493 | free ((char *) reg->name); |
477330fc RM |
2494 | if (reg->neon) |
2495 | free (reg->neon); | |
c19d1205 | 2496 | free (reg); |
d929913e NC |
2497 | |
2498 | /* Also locate the all upper case and all lower case versions. | |
2499 | Do not complain if we cannot find one or the other as it | |
2500 | was probably deleted above. */ | |
5f4273c7 | 2501 | |
d929913e NC |
2502 | nbuf = strdup (name); |
2503 | for (p = nbuf; *p; p++) | |
2504 | *p = TOUPPER (*p); | |
21d799b5 | 2505 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2506 | if (reg) |
2507 | { | |
db0bc284 | 2508 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2509 | free ((char *) reg->name); |
2510 | if (reg->neon) | |
2511 | free (reg->neon); | |
2512 | free (reg); | |
2513 | } | |
2514 | ||
2515 | for (p = nbuf; *p; p++) | |
2516 | *p = TOLOWER (*p); | |
21d799b5 | 2517 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2518 | if (reg) |
2519 | { | |
db0bc284 | 2520 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2521 | free ((char *) reg->name); |
2522 | if (reg->neon) | |
2523 | free (reg->neon); | |
2524 | free (reg); | |
2525 | } | |
2526 | ||
2527 | free (nbuf); | |
c19d1205 ZW |
2528 | } |
2529 | } | |
b99bd4ef | 2530 | |
c19d1205 | 2531 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2532 | demand_empty_rest_of_line (); |
2533 | } | |
2534 | ||
c19d1205 ZW |
2535 | /* Directives: Instruction set selection. */ |
2536 | ||
2537 | #ifdef OBJ_ELF | |
2538 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2539 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2540 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2541 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2542 | ||
cd000bff DJ |
2543 | /* Create a new mapping symbol for the transition to STATE. */ |
2544 | ||
2545 | static void | |
2546 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2547 | { |
a737bd4d | 2548 | symbolS * symbolP; |
c19d1205 ZW |
2549 | const char * symname; |
2550 | int type; | |
b99bd4ef | 2551 | |
c19d1205 | 2552 | switch (state) |
b99bd4ef | 2553 | { |
c19d1205 ZW |
2554 | case MAP_DATA: |
2555 | symname = "$d"; | |
2556 | type = BSF_NO_FLAGS; | |
2557 | break; | |
2558 | case MAP_ARM: | |
2559 | symname = "$a"; | |
2560 | type = BSF_NO_FLAGS; | |
2561 | break; | |
2562 | case MAP_THUMB: | |
2563 | symname = "$t"; | |
2564 | type = BSF_NO_FLAGS; | |
2565 | break; | |
c19d1205 ZW |
2566 | default: |
2567 | abort (); | |
2568 | } | |
2569 | ||
cd000bff | 2570 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2571 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2572 | ||
2573 | switch (state) | |
2574 | { | |
2575 | case MAP_ARM: | |
2576 | THUMB_SET_FUNC (symbolP, 0); | |
2577 | ARM_SET_THUMB (symbolP, 0); | |
2578 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2579 | break; | |
2580 | ||
2581 | case MAP_THUMB: | |
2582 | THUMB_SET_FUNC (symbolP, 1); | |
2583 | ARM_SET_THUMB (symbolP, 1); | |
2584 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2585 | break; | |
2586 | ||
2587 | case MAP_DATA: | |
2588 | default: | |
cd000bff DJ |
2589 | break; |
2590 | } | |
2591 | ||
2592 | /* Save the mapping symbols for future reference. Also check that | |
2593 | we do not place two mapping symbols at the same offset within a | |
2594 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2595 | check_mapping_symbols. |
2596 | ||
2597 | If .fill or other data filling directive generates zero sized data, | |
2598 | the mapping symbol for the following code will have the same value | |
2599 | as the one generated for the data filling directive. In this case, | |
2600 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2601 | if (value == 0) |
2602 | { | |
2de7820f JZ |
2603 | if (frag->tc_frag_data.first_map != NULL) |
2604 | { | |
2605 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2606 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2607 | } | |
cd000bff DJ |
2608 | frag->tc_frag_data.first_map = symbolP; |
2609 | } | |
2610 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2611 | { |
2612 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2613 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2614 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2615 | } | |
cd000bff DJ |
2616 | frag->tc_frag_data.last_map = symbolP; |
2617 | } | |
2618 | ||
2619 | /* We must sometimes convert a region marked as code to data during | |
2620 | code alignment, if an odd number of bytes have to be padded. The | |
2621 | code mapping symbol is pushed to an aligned address. */ | |
2622 | ||
2623 | static void | |
2624 | insert_data_mapping_symbol (enum mstate state, | |
2625 | valueT value, fragS *frag, offsetT bytes) | |
2626 | { | |
2627 | /* If there was already a mapping symbol, remove it. */ | |
2628 | if (frag->tc_frag_data.last_map != NULL | |
2629 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2630 | { | |
2631 | symbolS *symp = frag->tc_frag_data.last_map; | |
2632 | ||
2633 | if (value == 0) | |
2634 | { | |
2635 | know (frag->tc_frag_data.first_map == symp); | |
2636 | frag->tc_frag_data.first_map = NULL; | |
2637 | } | |
2638 | frag->tc_frag_data.last_map = NULL; | |
2639 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2640 | } |
cd000bff DJ |
2641 | |
2642 | make_mapping_symbol (MAP_DATA, value, frag); | |
2643 | make_mapping_symbol (state, value + bytes, frag); | |
2644 | } | |
2645 | ||
2646 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2647 | ||
2648 | /* Set the mapping state to STATE. Only call this when about to | |
2649 | emit some STATE bytes to the file. */ | |
2650 | ||
4e9aaefb | 2651 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
cd000bff DJ |
2652 | void |
2653 | mapping_state (enum mstate state) | |
2654 | { | |
940b5ce0 DJ |
2655 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2656 | ||
cd000bff DJ |
2657 | if (mapstate == state) |
2658 | /* The mapping symbol has already been emitted. | |
2659 | There is nothing else to do. */ | |
2660 | return; | |
49c62a33 NC |
2661 | |
2662 | if (state == MAP_ARM || state == MAP_THUMB) | |
2663 | /* PR gas/12931 | |
2664 | All ARM instructions require 4-byte alignment. | |
2665 | (Almost) all Thumb instructions require 2-byte alignment. | |
2666 | ||
2667 | When emitting instructions into any section, mark the section | |
2668 | appropriately. | |
2669 | ||
2670 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2671 | but themselves require 2-byte alignment; this applies to some | |
2672 | PC- relative forms. However, these cases will invovle implicit | |
2673 | literal pool generation or an explicit .align >=2, both of | |
2674 | which will cause the section to me marked with sufficient | |
2675 | alignment. Thus, we don't handle those cases here. */ | |
2676 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2677 | ||
2678 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
4e9aaefb | 2679 | /* This case will be evaluated later. */ |
cd000bff | 2680 | return; |
cd000bff DJ |
2681 | |
2682 | mapping_state_2 (state, 0); | |
cd000bff DJ |
2683 | } |
2684 | ||
2685 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2686 | allocated. Put the mapping symbol that far back. */ | |
2687 | ||
2688 | static void | |
2689 | mapping_state_2 (enum mstate state, int max_chars) | |
2690 | { | |
940b5ce0 DJ |
2691 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2692 | ||
2693 | if (!SEG_NORMAL (now_seg)) | |
2694 | return; | |
2695 | ||
cd000bff DJ |
2696 | if (mapstate == state) |
2697 | /* The mapping symbol has already been emitted. | |
2698 | There is nothing else to do. */ | |
2699 | return; | |
2700 | ||
4e9aaefb SA |
2701 | if (TRANSITION (MAP_UNDEFINED, MAP_ARM) |
2702 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2703 | { | |
2704 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2705 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2706 | ||
2707 | if (add_symbol) | |
2708 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2709 | } | |
2710 | ||
cd000bff DJ |
2711 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2712 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 | 2713 | } |
4e9aaefb | 2714 | #undef TRANSITION |
c19d1205 | 2715 | #else |
d3106081 NS |
2716 | #define mapping_state(x) ((void)0) |
2717 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2718 | #endif |
2719 | ||
2720 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2721 | ||
4343666d | 2722 | #ifdef OBJ_COFF |
c19d1205 ZW |
2723 | static symbolS * |
2724 | find_real_start (symbolS * symbolP) | |
2725 | { | |
2726 | char * real_start; | |
2727 | const char * name = S_GET_NAME (symbolP); | |
2728 | symbolS * new_target; | |
2729 | ||
2730 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2731 | #define STUB_NAME ".real_start_of" | |
2732 | ||
2733 | if (name == NULL) | |
2734 | abort (); | |
2735 | ||
37f6032b ZW |
2736 | /* The compiler may generate BL instructions to local labels because |
2737 | it needs to perform a branch to a far away location. These labels | |
2738 | do not have a corresponding ".real_start_of" label. We check | |
2739 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2740 | the ".real_start_of" convention for nonlocal branches. */ | |
2741 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2742 | return symbolP; |
2743 | ||
37f6032b | 2744 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2745 | new_target = symbol_find (real_start); |
2746 | ||
2747 | if (new_target == NULL) | |
2748 | { | |
bd3ba5d1 | 2749 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2750 | new_target = symbolP; |
2751 | } | |
2752 | ||
c19d1205 ZW |
2753 | return new_target; |
2754 | } | |
4343666d | 2755 | #endif |
c19d1205 ZW |
2756 | |
2757 | static void | |
2758 | opcode_select (int width) | |
2759 | { | |
2760 | switch (width) | |
2761 | { | |
2762 | case 16: | |
2763 | if (! thumb_mode) | |
2764 | { | |
e74cfd16 | 2765 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2766 | as_bad (_("selected processor does not support THUMB opcodes")); |
2767 | ||
2768 | thumb_mode = 1; | |
2769 | /* No need to force the alignment, since we will have been | |
2770 | coming from ARM mode, which is word-aligned. */ | |
2771 | record_alignment (now_seg, 1); | |
2772 | } | |
c19d1205 ZW |
2773 | break; |
2774 | ||
2775 | case 32: | |
2776 | if (thumb_mode) | |
2777 | { | |
e74cfd16 | 2778 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2779 | as_bad (_("selected processor does not support ARM opcodes")); |
2780 | ||
2781 | thumb_mode = 0; | |
2782 | ||
2783 | if (!need_pass_2) | |
2784 | frag_align (2, 0, 0); | |
2785 | ||
2786 | record_alignment (now_seg, 1); | |
2787 | } | |
c19d1205 ZW |
2788 | break; |
2789 | ||
2790 | default: | |
2791 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2792 | } | |
2793 | } | |
2794 | ||
2795 | static void | |
2796 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2797 | { | |
2798 | opcode_select (32); | |
2799 | demand_empty_rest_of_line (); | |
2800 | } | |
2801 | ||
2802 | static void | |
2803 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2804 | { | |
2805 | opcode_select (16); | |
2806 | demand_empty_rest_of_line (); | |
2807 | } | |
2808 | ||
2809 | static void | |
2810 | s_code (int unused ATTRIBUTE_UNUSED) | |
2811 | { | |
2812 | int temp; | |
2813 | ||
2814 | temp = get_absolute_expression (); | |
2815 | switch (temp) | |
2816 | { | |
2817 | case 16: | |
2818 | case 32: | |
2819 | opcode_select (temp); | |
2820 | break; | |
2821 | ||
2822 | default: | |
2823 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2824 | } | |
2825 | } | |
2826 | ||
2827 | static void | |
2828 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2829 | { | |
2830 | /* If we are not already in thumb mode go into it, EVEN if | |
2831 | the target processor does not support thumb instructions. | |
2832 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2833 | to compile interworking support functions even if the | |
2834 | target processor should not support interworking. */ | |
2835 | if (! thumb_mode) | |
2836 | { | |
2837 | thumb_mode = 2; | |
2838 | record_alignment (now_seg, 1); | |
2839 | } | |
2840 | ||
2841 | demand_empty_rest_of_line (); | |
2842 | } | |
2843 | ||
2844 | static void | |
2845 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2846 | { | |
2847 | s_thumb (0); | |
2848 | ||
2849 | /* The following label is the name/address of the start of a Thumb function. | |
2850 | We need to know this for the interworking support. */ | |
2851 | label_is_thumb_function_name = TRUE; | |
2852 | } | |
2853 | ||
2854 | /* Perform a .set directive, but also mark the alias as | |
2855 | being a thumb function. */ | |
2856 | ||
2857 | static void | |
2858 | s_thumb_set (int equiv) | |
2859 | { | |
2860 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2861 | We cannot just call that code as we need to get at the symbol that | |
2862 | is created. */ | |
2863 | char * name; | |
2864 | char delim; | |
2865 | char * end_name; | |
2866 | symbolS * symbolP; | |
2867 | ||
2868 | /* Especial apologies for the random logic: | |
2869 | This just grew, and could be parsed much more simply! | |
2870 | Dean - in haste. */ | |
d02603dc | 2871 | delim = get_symbol_name (& name); |
c19d1205 | 2872 | end_name = input_line_pointer; |
d02603dc | 2873 | (void) restore_line_pointer (delim); |
c19d1205 ZW |
2874 | |
2875 | if (*input_line_pointer != ',') | |
2876 | { | |
2877 | *end_name = 0; | |
2878 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2879 | *end_name = delim; |
2880 | ignore_rest_of_line (); | |
2881 | return; | |
2882 | } | |
2883 | ||
2884 | input_line_pointer++; | |
2885 | *end_name = 0; | |
2886 | ||
2887 | if (name[0] == '.' && name[1] == '\0') | |
2888 | { | |
2889 | /* XXX - this should not happen to .thumb_set. */ | |
2890 | abort (); | |
2891 | } | |
2892 | ||
2893 | if ((symbolP = symbol_find (name)) == NULL | |
2894 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2895 | { | |
2896 | #ifndef NO_LISTING | |
2897 | /* When doing symbol listings, play games with dummy fragments living | |
2898 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2899 | for this symbol. */ |
b99bd4ef NC |
2900 | if (listing & LISTING_SYMBOLS) |
2901 | { | |
2902 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2903 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2904 | |
2905 | memset (dummy_frag, 0, sizeof (fragS)); | |
2906 | dummy_frag->fr_type = rs_fill; | |
2907 | dummy_frag->line = listing_tail; | |
2908 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2909 | dummy_frag->fr_symbol = symbolP; | |
2910 | } | |
2911 | else | |
2912 | #endif | |
2913 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2914 | ||
2915 | #ifdef OBJ_COFF | |
2916 | /* "set" symbols are local unless otherwise specified. */ | |
2917 | SF_SET_LOCAL (symbolP); | |
2918 | #endif /* OBJ_COFF */ | |
2919 | } /* Make a new symbol. */ | |
2920 | ||
2921 | symbol_table_insert (symbolP); | |
2922 | ||
2923 | * end_name = delim; | |
2924 | ||
2925 | if (equiv | |
2926 | && S_IS_DEFINED (symbolP) | |
2927 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2928 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2929 | ||
2930 | pseudo_set (symbolP); | |
2931 | ||
2932 | demand_empty_rest_of_line (); | |
2933 | ||
c19d1205 | 2934 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2935 | |
2936 | THUMB_SET_FUNC (symbolP, 1); | |
2937 | ARM_SET_THUMB (symbolP, 1); | |
2938 | #if defined OBJ_ELF || defined OBJ_COFF | |
2939 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2940 | #endif | |
2941 | } | |
2942 | ||
c19d1205 | 2943 | /* Directives: Mode selection. */ |
b99bd4ef | 2944 | |
c19d1205 ZW |
2945 | /* .syntax [unified|divided] - choose the new unified syntax |
2946 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2947 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2948 | static void |
c19d1205 | 2949 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2950 | { |
c19d1205 ZW |
2951 | char *name, delim; |
2952 | ||
d02603dc | 2953 | delim = get_symbol_name (& name); |
c19d1205 ZW |
2954 | |
2955 | if (!strcasecmp (name, "unified")) | |
2956 | unified_syntax = TRUE; | |
2957 | else if (!strcasecmp (name, "divided")) | |
2958 | unified_syntax = FALSE; | |
2959 | else | |
2960 | { | |
2961 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2962 | return; | |
2963 | } | |
d02603dc | 2964 | (void) restore_line_pointer (delim); |
b99bd4ef NC |
2965 | demand_empty_rest_of_line (); |
2966 | } | |
2967 | ||
c19d1205 ZW |
2968 | /* Directives: sectioning and alignment. */ |
2969 | ||
c19d1205 ZW |
2970 | static void |
2971 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2972 | { |
c19d1205 ZW |
2973 | /* We don't support putting frags in the BSS segment, we fake it by |
2974 | marking in_bss, then looking at s_skip for clues. */ | |
2975 | subseg_set (bss_section, 0); | |
2976 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2977 | |
2978 | #ifdef md_elf_section_change_hook | |
2979 | md_elf_section_change_hook (); | |
2980 | #endif | |
c19d1205 | 2981 | } |
b99bd4ef | 2982 | |
c19d1205 ZW |
2983 | static void |
2984 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2985 | { | |
2986 | /* Never make frag if expect extra pass. */ | |
2987 | if (!need_pass_2) | |
2988 | frag_align (1, 0, 0); | |
b99bd4ef | 2989 | |
c19d1205 | 2990 | record_alignment (now_seg, 1); |
b99bd4ef | 2991 | |
c19d1205 | 2992 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2993 | } |
2994 | ||
2e6976a8 DG |
2995 | /* Directives: CodeComposer Studio. */ |
2996 | ||
2997 | /* .ref (for CodeComposer Studio syntax only). */ | |
2998 | static void | |
2999 | s_ccs_ref (int unused ATTRIBUTE_UNUSED) | |
3000 | { | |
3001 | if (codecomposer_syntax) | |
3002 | ignore_rest_of_line (); | |
3003 | else | |
3004 | as_bad (_(".ref pseudo-op only available with -mccs flag.")); | |
3005 | } | |
3006 | ||
3007 | /* If name is not NULL, then it is used for marking the beginning of a | |
3008 | function, wherease if it is NULL then it means the function end. */ | |
3009 | static void | |
3010 | asmfunc_debug (const char * name) | |
3011 | { | |
3012 | static const char * last_name = NULL; | |
3013 | ||
3014 | if (name != NULL) | |
3015 | { | |
3016 | gas_assert (last_name == NULL); | |
3017 | last_name = name; | |
3018 | ||
3019 | if (debug_type == DEBUG_STABS) | |
3020 | stabs_generate_asm_func (name, name); | |
3021 | } | |
3022 | else | |
3023 | { | |
3024 | gas_assert (last_name != NULL); | |
3025 | ||
3026 | if (debug_type == DEBUG_STABS) | |
3027 | stabs_generate_asm_endfunc (last_name, last_name); | |
3028 | ||
3029 | last_name = NULL; | |
3030 | } | |
3031 | } | |
3032 | ||
3033 | static void | |
3034 | s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) | |
3035 | { | |
3036 | if (codecomposer_syntax) | |
3037 | { | |
3038 | switch (asmfunc_state) | |
3039 | { | |
3040 | case OUTSIDE_ASMFUNC: | |
3041 | asmfunc_state = WAITING_ASMFUNC_NAME; | |
3042 | break; | |
3043 | ||
3044 | case WAITING_ASMFUNC_NAME: | |
3045 | as_bad (_(".asmfunc repeated.")); | |
3046 | break; | |
3047 | ||
3048 | case WAITING_ENDASMFUNC: | |
3049 | as_bad (_(".asmfunc without function.")); | |
3050 | break; | |
3051 | } | |
3052 | demand_empty_rest_of_line (); | |
3053 | } | |
3054 | else | |
3055 | as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); | |
3056 | } | |
3057 | ||
3058 | static void | |
3059 | s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) | |
3060 | { | |
3061 | if (codecomposer_syntax) | |
3062 | { | |
3063 | switch (asmfunc_state) | |
3064 | { | |
3065 | case OUTSIDE_ASMFUNC: | |
3066 | as_bad (_(".endasmfunc without a .asmfunc.")); | |
3067 | break; | |
3068 | ||
3069 | case WAITING_ASMFUNC_NAME: | |
3070 | as_bad (_(".endasmfunc without function.")); | |
3071 | break; | |
3072 | ||
3073 | case WAITING_ENDASMFUNC: | |
3074 | asmfunc_state = OUTSIDE_ASMFUNC; | |
3075 | asmfunc_debug (NULL); | |
3076 | break; | |
3077 | } | |
3078 | demand_empty_rest_of_line (); | |
3079 | } | |
3080 | else | |
3081 | as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); | |
3082 | } | |
3083 | ||
3084 | static void | |
3085 | s_ccs_def (int name) | |
3086 | { | |
3087 | if (codecomposer_syntax) | |
3088 | s_globl (name); | |
3089 | else | |
3090 | as_bad (_(".def pseudo-op only available with -mccs flag.")); | |
3091 | } | |
3092 | ||
c19d1205 | 3093 | /* Directives: Literal pools. */ |
a737bd4d | 3094 | |
c19d1205 ZW |
3095 | static literal_pool * |
3096 | find_literal_pool (void) | |
a737bd4d | 3097 | { |
c19d1205 | 3098 | literal_pool * pool; |
a737bd4d | 3099 | |
c19d1205 | 3100 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3101 | { |
c19d1205 ZW |
3102 | if (pool->section == now_seg |
3103 | && pool->sub_section == now_subseg) | |
3104 | break; | |
a737bd4d NC |
3105 | } |
3106 | ||
c19d1205 | 3107 | return pool; |
a737bd4d NC |
3108 | } |
3109 | ||
c19d1205 ZW |
3110 | static literal_pool * |
3111 | find_or_make_literal_pool (void) | |
a737bd4d | 3112 | { |
c19d1205 ZW |
3113 | /* Next literal pool ID number. */ |
3114 | static unsigned int latest_pool_num = 1; | |
3115 | literal_pool * pool; | |
a737bd4d | 3116 | |
c19d1205 | 3117 | pool = find_literal_pool (); |
a737bd4d | 3118 | |
c19d1205 | 3119 | if (pool == NULL) |
a737bd4d | 3120 | { |
c19d1205 | 3121 | /* Create a new pool. */ |
21d799b5 | 3122 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3123 | if (! pool) |
3124 | return NULL; | |
a737bd4d | 3125 | |
c19d1205 ZW |
3126 | pool->next_free_entry = 0; |
3127 | pool->section = now_seg; | |
3128 | pool->sub_section = now_subseg; | |
3129 | pool->next = list_of_pools; | |
3130 | pool->symbol = NULL; | |
8335d6aa | 3131 | pool->alignment = 2; |
c19d1205 ZW |
3132 | |
3133 | /* Add it to the list. */ | |
3134 | list_of_pools = pool; | |
a737bd4d | 3135 | } |
a737bd4d | 3136 | |
c19d1205 ZW |
3137 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3138 | if (pool->symbol == NULL) | |
a737bd4d | 3139 | { |
c19d1205 ZW |
3140 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3141 | (valueT) 0, &zero_address_frag); | |
3142 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3143 | } |
3144 | ||
c19d1205 ZW |
3145 | /* Done. */ |
3146 | return pool; | |
a737bd4d NC |
3147 | } |
3148 | ||
c19d1205 | 3149 | /* Add the literal in the global 'inst' |
5f4273c7 | 3150 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3151 | |
3152 | static int | |
8335d6aa | 3153 | add_to_lit_pool (unsigned int nbytes) |
b99bd4ef | 3154 | { |
8335d6aa JW |
3155 | #define PADDING_SLOT 0x1 |
3156 | #define LIT_ENTRY_SIZE_MASK 0xFF | |
c19d1205 | 3157 | literal_pool * pool; |
8335d6aa JW |
3158 | unsigned int entry, pool_size = 0; |
3159 | bfd_boolean padding_slot_p = FALSE; | |
e56c722b | 3160 | unsigned imm1 = 0; |
8335d6aa JW |
3161 | unsigned imm2 = 0; |
3162 | ||
3163 | if (nbytes == 8) | |
3164 | { | |
3165 | imm1 = inst.operands[1].imm; | |
3166 | imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg | |
3167 | : inst.reloc.exp.X_unsigned ? 0 | |
2569ceb0 | 3168 | : ((bfd_int64_t) inst.operands[1].imm) >> 32); |
8335d6aa JW |
3169 | if (target_big_endian) |
3170 | { | |
3171 | imm1 = imm2; | |
3172 | imm2 = inst.operands[1].imm; | |
3173 | } | |
3174 | } | |
b99bd4ef | 3175 | |
c19d1205 ZW |
3176 | pool = find_or_make_literal_pool (); |
3177 | ||
3178 | /* Check if this literal value is already in the pool. */ | |
3179 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3180 | { |
8335d6aa JW |
3181 | if (nbytes == 4) |
3182 | { | |
3183 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3184 | && (inst.reloc.exp.X_op == O_constant) | |
3185 | && (pool->literals[entry].X_add_number | |
3186 | == inst.reloc.exp.X_add_number) | |
3187 | && (pool->literals[entry].X_md == nbytes) | |
3188 | && (pool->literals[entry].X_unsigned | |
3189 | == inst.reloc.exp.X_unsigned)) | |
3190 | break; | |
3191 | ||
3192 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3193 | && (inst.reloc.exp.X_op == O_symbol) | |
3194 | && (pool->literals[entry].X_add_number | |
3195 | == inst.reloc.exp.X_add_number) | |
3196 | && (pool->literals[entry].X_add_symbol | |
3197 | == inst.reloc.exp.X_add_symbol) | |
3198 | && (pool->literals[entry].X_op_symbol | |
3199 | == inst.reloc.exp.X_op_symbol) | |
3200 | && (pool->literals[entry].X_md == nbytes)) | |
3201 | break; | |
3202 | } | |
3203 | else if ((nbytes == 8) | |
3204 | && !(pool_size & 0x7) | |
3205 | && ((entry + 1) != pool->next_free_entry) | |
3206 | && (pool->literals[entry].X_op == O_constant) | |
19f2f6a9 | 3207 | && (pool->literals[entry].X_add_number == (offsetT) imm1) |
8335d6aa JW |
3208 | && (pool->literals[entry].X_unsigned |
3209 | == inst.reloc.exp.X_unsigned) | |
3210 | && (pool->literals[entry + 1].X_op == O_constant) | |
19f2f6a9 | 3211 | && (pool->literals[entry + 1].X_add_number == (offsetT) imm2) |
8335d6aa JW |
3212 | && (pool->literals[entry + 1].X_unsigned |
3213 | == inst.reloc.exp.X_unsigned)) | |
c19d1205 ZW |
3214 | break; |
3215 | ||
8335d6aa JW |
3216 | padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); |
3217 | if (padding_slot_p && (nbytes == 4)) | |
c19d1205 | 3218 | break; |
8335d6aa JW |
3219 | |
3220 | pool_size += 4; | |
b99bd4ef NC |
3221 | } |
3222 | ||
c19d1205 ZW |
3223 | /* Do we need to create a new entry? */ |
3224 | if (entry == pool->next_free_entry) | |
3225 | { | |
3226 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3227 | { | |
3228 | inst.error = _("literal pool overflow"); | |
3229 | return FAIL; | |
3230 | } | |
3231 | ||
8335d6aa JW |
3232 | if (nbytes == 8) |
3233 | { | |
3234 | /* For 8-byte entries, we align to an 8-byte boundary, | |
3235 | and split it into two 4-byte entries, because on 32-bit | |
3236 | host, 8-byte constants are treated as big num, thus | |
3237 | saved in "generic_bignum" which will be overwritten | |
3238 | by later assignments. | |
3239 | ||
3240 | We also need to make sure there is enough space for | |
3241 | the split. | |
3242 | ||
3243 | We also check to make sure the literal operand is a | |
3244 | constant number. */ | |
19f2f6a9 JW |
3245 | if (!(inst.reloc.exp.X_op == O_constant |
3246 | || inst.reloc.exp.X_op == O_big)) | |
8335d6aa JW |
3247 | { |
3248 | inst.error = _("invalid type for literal pool"); | |
3249 | return FAIL; | |
3250 | } | |
3251 | else if (pool_size & 0x7) | |
3252 | { | |
3253 | if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) | |
3254 | { | |
3255 | inst.error = _("literal pool overflow"); | |
3256 | return FAIL; | |
3257 | } | |
3258 | ||
3259 | pool->literals[entry] = inst.reloc.exp; | |
3260 | pool->literals[entry].X_add_number = 0; | |
3261 | pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; | |
3262 | pool->next_free_entry += 1; | |
3263 | pool_size += 4; | |
3264 | } | |
3265 | else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) | |
3266 | { | |
3267 | inst.error = _("literal pool overflow"); | |
3268 | return FAIL; | |
3269 | } | |
3270 | ||
3271 | pool->literals[entry] = inst.reloc.exp; | |
3272 | pool->literals[entry].X_op = O_constant; | |
3273 | pool->literals[entry].X_add_number = imm1; | |
3274 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3275 | pool->literals[entry++].X_md = 4; | |
3276 | pool->literals[entry] = inst.reloc.exp; | |
3277 | pool->literals[entry].X_op = O_constant; | |
3278 | pool->literals[entry].X_add_number = imm2; | |
3279 | pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; | |
3280 | pool->literals[entry].X_md = 4; | |
3281 | pool->alignment = 3; | |
3282 | pool->next_free_entry += 1; | |
3283 | } | |
3284 | else | |
3285 | { | |
3286 | pool->literals[entry] = inst.reloc.exp; | |
3287 | pool->literals[entry].X_md = 4; | |
3288 | } | |
3289 | ||
a8040cf2 NC |
3290 | #ifdef OBJ_ELF |
3291 | /* PR ld/12974: Record the location of the first source line to reference | |
3292 | this entry in the literal pool. If it turns out during linking that the | |
3293 | symbol does not exist we will be able to give an accurate line number for | |
3294 | the (first use of the) missing reference. */ | |
3295 | if (debug_type == DEBUG_DWARF2) | |
3296 | dwarf2_where (pool->locs + entry); | |
3297 | #endif | |
c19d1205 ZW |
3298 | pool->next_free_entry += 1; |
3299 | } | |
8335d6aa JW |
3300 | else if (padding_slot_p) |
3301 | { | |
3302 | pool->literals[entry] = inst.reloc.exp; | |
3303 | pool->literals[entry].X_md = nbytes; | |
3304 | } | |
b99bd4ef | 3305 | |
c19d1205 | 3306 | inst.reloc.exp.X_op = O_symbol; |
8335d6aa | 3307 | inst.reloc.exp.X_add_number = pool_size; |
c19d1205 | 3308 | inst.reloc.exp.X_add_symbol = pool->symbol; |
b99bd4ef | 3309 | |
c19d1205 | 3310 | return SUCCESS; |
b99bd4ef NC |
3311 | } |
3312 | ||
2e6976a8 | 3313 | bfd_boolean |
2e57ce7b | 3314 | tc_start_label_without_colon (void) |
2e6976a8 DG |
3315 | { |
3316 | bfd_boolean ret = TRUE; | |
3317 | ||
3318 | if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) | |
3319 | { | |
2e57ce7b | 3320 | const char *label = input_line_pointer; |
2e6976a8 DG |
3321 | |
3322 | while (!is_end_of_line[(int) label[-1]]) | |
3323 | --label; | |
3324 | ||
3325 | if (*label == '.') | |
3326 | { | |
3327 | as_bad (_("Invalid label '%s'"), label); | |
3328 | ret = FALSE; | |
3329 | } | |
3330 | ||
3331 | asmfunc_debug (label); | |
3332 | ||
3333 | asmfunc_state = WAITING_ENDASMFUNC; | |
3334 | } | |
3335 | ||
3336 | return ret; | |
3337 | } | |
3338 | ||
c19d1205 ZW |
3339 | /* Can't use symbol_new here, so have to create a symbol and then at |
3340 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3341 | |
c19d1205 ZW |
3342 | static void |
3343 | symbol_locate (symbolS * symbolP, | |
3344 | const char * name, /* It is copied, the caller can modify. */ | |
3345 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3346 | valueT valu, /* Symbol value. */ | |
3347 | fragS * frag) /* Associated fragment. */ | |
3348 | { | |
e57e6ddc | 3349 | size_t name_length; |
c19d1205 | 3350 | char * preserved_copy_of_name; |
e16bb312 | 3351 | |
c19d1205 ZW |
3352 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3353 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3354 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3355 | |
c19d1205 ZW |
3356 | #ifdef tc_canonicalize_symbol_name |
3357 | preserved_copy_of_name = | |
3358 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3359 | #endif | |
b99bd4ef | 3360 | |
c19d1205 | 3361 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3362 | |
c19d1205 ZW |
3363 | S_SET_SEGMENT (symbolP, segment); |
3364 | S_SET_VALUE (symbolP, valu); | |
3365 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3366 | |
c19d1205 | 3367 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3368 | |
c19d1205 ZW |
3369 | /* Link to end of symbol chain. */ |
3370 | { | |
3371 | extern int symbol_table_frozen; | |
b99bd4ef | 3372 | |
c19d1205 ZW |
3373 | if (symbol_table_frozen) |
3374 | abort (); | |
3375 | } | |
b99bd4ef | 3376 | |
c19d1205 | 3377 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3378 | |
c19d1205 | 3379 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3380 | |
c19d1205 ZW |
3381 | #ifdef tc_symbol_new_hook |
3382 | tc_symbol_new_hook (symbolP); | |
3383 | #endif | |
3384 | ||
3385 | #ifdef DEBUG_SYMS | |
3386 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3387 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3388 | } |
3389 | ||
c19d1205 ZW |
3390 | static void |
3391 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3392 | { |
c19d1205 ZW |
3393 | unsigned int entry; |
3394 | literal_pool * pool; | |
3395 | char sym_name[20]; | |
b99bd4ef | 3396 | |
c19d1205 ZW |
3397 | pool = find_literal_pool (); |
3398 | if (pool == NULL | |
3399 | || pool->symbol == NULL | |
3400 | || pool->next_free_entry == 0) | |
3401 | return; | |
b99bd4ef | 3402 | |
c19d1205 ZW |
3403 | /* Align pool as you have word accesses. |
3404 | Only make a frag if we have to. */ | |
3405 | if (!need_pass_2) | |
8335d6aa | 3406 | frag_align (pool->alignment, 0, 0); |
b99bd4ef | 3407 | |
c19d1205 | 3408 | record_alignment (now_seg, 2); |
b99bd4ef | 3409 | |
aaca88ef | 3410 | #ifdef OBJ_ELF |
47fc6e36 WN |
3411 | seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; |
3412 | make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); | |
aaca88ef | 3413 | #endif |
c19d1205 | 3414 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3415 | |
c19d1205 ZW |
3416 | symbol_locate (pool->symbol, sym_name, now_seg, |
3417 | (valueT) frag_now_fix (), frag_now); | |
3418 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3419 | |
c19d1205 | 3420 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3421 | |
c19d1205 ZW |
3422 | #if defined OBJ_COFF || defined OBJ_ELF |
3423 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3424 | #endif | |
6c43fab6 | 3425 | |
c19d1205 | 3426 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3427 | { |
3428 | #ifdef OBJ_ELF | |
3429 | if (debug_type == DEBUG_DWARF2) | |
3430 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3431 | #endif | |
3432 | /* First output the expression in the instruction to the pool. */ | |
8335d6aa JW |
3433 | emit_expr (&(pool->literals[entry]), |
3434 | pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); | |
a8040cf2 | 3435 | } |
b99bd4ef | 3436 | |
c19d1205 ZW |
3437 | /* Mark the pool as empty. */ |
3438 | pool->next_free_entry = 0; | |
3439 | pool->symbol = NULL; | |
b99bd4ef NC |
3440 | } |
3441 | ||
c19d1205 ZW |
3442 | #ifdef OBJ_ELF |
3443 | /* Forward declarations for functions below, in the MD interface | |
3444 | section. */ | |
3445 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3446 | static valueT create_unwind_entry (int); | |
3447 | static void start_unwind_section (const segT, int); | |
3448 | static void add_unwind_opcode (valueT, int); | |
3449 | static void flush_pending_unwind (void); | |
b99bd4ef | 3450 | |
c19d1205 | 3451 | /* Directives: Data. */ |
b99bd4ef | 3452 | |
c19d1205 ZW |
3453 | static void |
3454 | s_arm_elf_cons (int nbytes) | |
3455 | { | |
3456 | expressionS exp; | |
b99bd4ef | 3457 | |
c19d1205 ZW |
3458 | #ifdef md_flush_pending_output |
3459 | md_flush_pending_output (); | |
3460 | #endif | |
b99bd4ef | 3461 | |
c19d1205 | 3462 | if (is_it_end_of_statement ()) |
b99bd4ef | 3463 | { |
c19d1205 ZW |
3464 | demand_empty_rest_of_line (); |
3465 | return; | |
b99bd4ef NC |
3466 | } |
3467 | ||
c19d1205 ZW |
3468 | #ifdef md_cons_align |
3469 | md_cons_align (nbytes); | |
3470 | #endif | |
b99bd4ef | 3471 | |
c19d1205 ZW |
3472 | mapping_state (MAP_DATA); |
3473 | do | |
b99bd4ef | 3474 | { |
c19d1205 ZW |
3475 | int reloc; |
3476 | char *base = input_line_pointer; | |
b99bd4ef | 3477 | |
c19d1205 | 3478 | expression (& exp); |
b99bd4ef | 3479 | |
c19d1205 ZW |
3480 | if (exp.X_op != O_symbol) |
3481 | emit_expr (&exp, (unsigned int) nbytes); | |
3482 | else | |
3483 | { | |
3484 | char *before_reloc = input_line_pointer; | |
3485 | reloc = parse_reloc (&input_line_pointer); | |
3486 | if (reloc == -1) | |
3487 | { | |
3488 | as_bad (_("unrecognized relocation suffix")); | |
3489 | ignore_rest_of_line (); | |
3490 | return; | |
3491 | } | |
3492 | else if (reloc == BFD_RELOC_UNUSED) | |
3493 | emit_expr (&exp, (unsigned int) nbytes); | |
3494 | else | |
3495 | { | |
21d799b5 | 3496 | reloc_howto_type *howto = (reloc_howto_type *) |
477330fc RM |
3497 | bfd_reloc_type_lookup (stdoutput, |
3498 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3499 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3500 | |
2fc8bdac ZW |
3501 | if (reloc == BFD_RELOC_ARM_PLT32) |
3502 | { | |
3503 | as_bad (_("(plt) is only valid on branch targets")); | |
3504 | reloc = BFD_RELOC_UNUSED; | |
3505 | size = 0; | |
3506 | } | |
3507 | ||
c19d1205 | 3508 | if (size > nbytes) |
2fc8bdac | 3509 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3510 | howto->name, nbytes); |
3511 | else | |
3512 | { | |
3513 | /* We've parsed an expression stopping at O_symbol. | |
3514 | But there may be more expression left now that we | |
3515 | have parsed the relocation marker. Parse it again. | |
3516 | XXX Surely there is a cleaner way to do this. */ | |
3517 | char *p = input_line_pointer; | |
3518 | int offset; | |
21d799b5 | 3519 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3520 | memcpy (save_buf, base, input_line_pointer - base); |
3521 | memmove (base + (input_line_pointer - before_reloc), | |
3522 | base, before_reloc - base); | |
3523 | ||
3524 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3525 | expression (&exp); | |
3526 | memcpy (base, save_buf, p - base); | |
3527 | ||
3528 | offset = nbytes - size; | |
4b1a927e AM |
3529 | p = frag_more (nbytes); |
3530 | memset (p, 0, nbytes); | |
c19d1205 | 3531 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, |
21d799b5 | 3532 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3533 | } |
3534 | } | |
3535 | } | |
b99bd4ef | 3536 | } |
c19d1205 | 3537 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3538 | |
c19d1205 ZW |
3539 | /* Put terminator back into stream. */ |
3540 | input_line_pointer --; | |
3541 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3542 | } |
3543 | ||
c921be7d NC |
3544 | /* Emit an expression containing a 32-bit thumb instruction. |
3545 | Implementation based on put_thumb32_insn. */ | |
3546 | ||
3547 | static void | |
3548 | emit_thumb32_expr (expressionS * exp) | |
3549 | { | |
3550 | expressionS exp_high = *exp; | |
3551 | ||
3552 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3553 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3554 | exp->X_add_number &= 0xffff; | |
3555 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3556 | } | |
3557 | ||
3558 | /* Guess the instruction size based on the opcode. */ | |
3559 | ||
3560 | static int | |
3561 | thumb_insn_size (int opcode) | |
3562 | { | |
3563 | if ((unsigned int) opcode < 0xe800u) | |
3564 | return 2; | |
3565 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3566 | return 4; | |
3567 | else | |
3568 | return 0; | |
3569 | } | |
3570 | ||
3571 | static bfd_boolean | |
3572 | emit_insn (expressionS *exp, int nbytes) | |
3573 | { | |
3574 | int size = 0; | |
3575 | ||
3576 | if (exp->X_op == O_constant) | |
3577 | { | |
3578 | size = nbytes; | |
3579 | ||
3580 | if (size == 0) | |
3581 | size = thumb_insn_size (exp->X_add_number); | |
3582 | ||
3583 | if (size != 0) | |
3584 | { | |
3585 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3586 | { | |
3587 | as_bad (_(".inst.n operand too big. "\ | |
3588 | "Use .inst.w instead")); | |
3589 | size = 0; | |
3590 | } | |
3591 | else | |
3592 | { | |
3593 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3594 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3595 | else | |
3596 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3597 | ||
3598 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3599 | emit_thumb32_expr (exp); | |
3600 | else | |
3601 | emit_expr (exp, (unsigned int) size); | |
3602 | ||
3603 | it_fsm_post_encode (); | |
3604 | } | |
3605 | } | |
3606 | else | |
3607 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3608 | "Use .inst.n/.inst.w instead")); | |
3609 | } | |
3610 | else | |
3611 | as_bad (_("constant expression required")); | |
3612 | ||
3613 | return (size != 0); | |
3614 | } | |
3615 | ||
3616 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3617 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3618 | ||
3619 | static void | |
3620 | s_arm_elf_inst (int nbytes) | |
3621 | { | |
3622 | if (is_it_end_of_statement ()) | |
3623 | { | |
3624 | demand_empty_rest_of_line (); | |
3625 | return; | |
3626 | } | |
3627 | ||
3628 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3629 | but will ensure not to be in DATA state. */ | |
3630 | ||
3631 | if (thumb_mode) | |
3632 | mapping_state (MAP_THUMB); | |
3633 | else | |
3634 | { | |
3635 | if (nbytes != 0) | |
3636 | { | |
3637 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3638 | ignore_rest_of_line (); | |
3639 | return; | |
3640 | } | |
3641 | ||
3642 | nbytes = 4; | |
3643 | ||
3644 | mapping_state (MAP_ARM); | |
3645 | } | |
3646 | ||
3647 | do | |
3648 | { | |
3649 | expressionS exp; | |
3650 | ||
3651 | expression (& exp); | |
3652 | ||
3653 | if (! emit_insn (& exp, nbytes)) | |
3654 | { | |
3655 | ignore_rest_of_line (); | |
3656 | return; | |
3657 | } | |
3658 | } | |
3659 | while (*input_line_pointer++ == ','); | |
3660 | ||
3661 | /* Put terminator back into stream. */ | |
3662 | input_line_pointer --; | |
3663 | demand_empty_rest_of_line (); | |
3664 | } | |
b99bd4ef | 3665 | |
c19d1205 | 3666 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3667 | |
c19d1205 ZW |
3668 | static void |
3669 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3670 | { | |
3671 | expressionS exp; | |
3672 | char *p; | |
3673 | valueT highbit; | |
b99bd4ef | 3674 | |
c19d1205 ZW |
3675 | highbit = 0; |
3676 | if (*input_line_pointer == '1') | |
3677 | highbit = 0x80000000; | |
3678 | else if (*input_line_pointer != '0') | |
3679 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3680 | |
c19d1205 ZW |
3681 | input_line_pointer++; |
3682 | if (*input_line_pointer != ',') | |
3683 | as_bad (_("missing comma")); | |
3684 | input_line_pointer++; | |
b99bd4ef | 3685 | |
c19d1205 ZW |
3686 | #ifdef md_flush_pending_output |
3687 | md_flush_pending_output (); | |
3688 | #endif | |
b99bd4ef | 3689 | |
c19d1205 ZW |
3690 | #ifdef md_cons_align |
3691 | md_cons_align (4); | |
3692 | #endif | |
b99bd4ef | 3693 | |
c19d1205 | 3694 | mapping_state (MAP_DATA); |
b99bd4ef | 3695 | |
c19d1205 | 3696 | expression (&exp); |
b99bd4ef | 3697 | |
c19d1205 ZW |
3698 | p = frag_more (4); |
3699 | md_number_to_chars (p, highbit, 4); | |
3700 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3701 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3702 | |
c19d1205 | 3703 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3704 | } |
3705 | ||
c19d1205 | 3706 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3707 | |
c19d1205 | 3708 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3709 | |
c19d1205 ZW |
3710 | static void |
3711 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3712 | { | |
3713 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3714 | if (unwind.proc_start) |
3715 | { | |
c921be7d | 3716 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3717 | return; |
3718 | } | |
3719 | ||
c19d1205 ZW |
3720 | /* Mark the start of the function. */ |
3721 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3722 | |
c19d1205 ZW |
3723 | /* Reset the rest of the unwind info. */ |
3724 | unwind.opcode_count = 0; | |
3725 | unwind.table_entry = NULL; | |
3726 | unwind.personality_routine = NULL; | |
3727 | unwind.personality_index = -1; | |
3728 | unwind.frame_size = 0; | |
3729 | unwind.fp_offset = 0; | |
fdfde340 | 3730 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3731 | unwind.fp_used = 0; |
3732 | unwind.sp_restored = 0; | |
3733 | } | |
b99bd4ef | 3734 | |
b99bd4ef | 3735 | |
c19d1205 ZW |
3736 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3737 | for the function. */ | |
b99bd4ef | 3738 | |
c19d1205 ZW |
3739 | static void |
3740 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3741 | { | |
3742 | demand_empty_rest_of_line (); | |
921e5f0a | 3743 | if (!unwind.proc_start) |
c921be7d | 3744 | as_bad (MISSING_FNSTART); |
921e5f0a | 3745 | |
c19d1205 | 3746 | if (unwind.table_entry) |
6decc662 | 3747 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3748 | |
c19d1205 ZW |
3749 | create_unwind_entry (1); |
3750 | } | |
a737bd4d | 3751 | |
c19d1205 | 3752 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3753 | |
c19d1205 ZW |
3754 | static void |
3755 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3756 | { | |
3757 | long where; | |
3758 | char *ptr; | |
3759 | valueT val; | |
940b5ce0 | 3760 | unsigned int marked_pr_dependency; |
f02232aa | 3761 | |
c19d1205 | 3762 | demand_empty_rest_of_line (); |
f02232aa | 3763 | |
921e5f0a PB |
3764 | if (!unwind.proc_start) |
3765 | { | |
c921be7d | 3766 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3767 | return; |
3768 | } | |
3769 | ||
c19d1205 ZW |
3770 | /* Add eh table entry. */ |
3771 | if (unwind.table_entry == NULL) | |
3772 | val = create_unwind_entry (0); | |
3773 | else | |
3774 | val = 0; | |
f02232aa | 3775 | |
c19d1205 ZW |
3776 | /* Add index table entry. This is two words. */ |
3777 | start_unwind_section (unwind.saved_seg, 1); | |
3778 | frag_align (2, 0, 0); | |
3779 | record_alignment (now_seg, 2); | |
b99bd4ef | 3780 | |
c19d1205 | 3781 | ptr = frag_more (8); |
5011093d | 3782 | memset (ptr, 0, 8); |
c19d1205 | 3783 | where = frag_now_fix () - 8; |
f02232aa | 3784 | |
c19d1205 ZW |
3785 | /* Self relative offset of the function start. */ |
3786 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3787 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3788 | |
c19d1205 ZW |
3789 | /* Indicate dependency on EHABI-defined personality routines to the |
3790 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3791 | marked_pr_dependency |
3792 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3793 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3794 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3795 | { | |
5f4273c7 NC |
3796 | static const char *const name[] = |
3797 | { | |
3798 | "__aeabi_unwind_cpp_pr0", | |
3799 | "__aeabi_unwind_cpp_pr1", | |
3800 | "__aeabi_unwind_cpp_pr2" | |
3801 | }; | |
c19d1205 ZW |
3802 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3803 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3804 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3805 | |= 1 << unwind.personality_index; |
c19d1205 | 3806 | } |
f02232aa | 3807 | |
c19d1205 ZW |
3808 | if (val) |
3809 | /* Inline exception table entry. */ | |
3810 | md_number_to_chars (ptr + 4, val, 4); | |
3811 | else | |
3812 | /* Self relative offset of the table entry. */ | |
3813 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3814 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3815 | |
c19d1205 ZW |
3816 | /* Restore the original section. */ |
3817 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3818 | |
3819 | unwind.proc_start = NULL; | |
c19d1205 | 3820 | } |
f02232aa | 3821 | |
f02232aa | 3822 | |
c19d1205 | 3823 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3824 | |
c19d1205 ZW |
3825 | static void |
3826 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3827 | { | |
3828 | demand_empty_rest_of_line (); | |
921e5f0a | 3829 | if (!unwind.proc_start) |
c921be7d | 3830 | as_bad (MISSING_FNSTART); |
921e5f0a | 3831 | |
c19d1205 ZW |
3832 | if (unwind.personality_routine || unwind.personality_index != -1) |
3833 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3834 | |
c19d1205 ZW |
3835 | unwind.personality_index = -2; |
3836 | } | |
b99bd4ef | 3837 | |
b99bd4ef | 3838 | |
c19d1205 | 3839 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3840 | |
c19d1205 ZW |
3841 | static void |
3842 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3843 | { | |
3844 | expressionS exp; | |
b99bd4ef | 3845 | |
921e5f0a | 3846 | if (!unwind.proc_start) |
c921be7d | 3847 | as_bad (MISSING_FNSTART); |
921e5f0a | 3848 | |
c19d1205 ZW |
3849 | if (unwind.personality_routine || unwind.personality_index != -1) |
3850 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3851 | |
c19d1205 | 3852 | expression (&exp); |
b99bd4ef | 3853 | |
c19d1205 ZW |
3854 | if (exp.X_op != O_constant |
3855 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3856 | { |
c19d1205 ZW |
3857 | as_bad (_("bad personality routine number")); |
3858 | ignore_rest_of_line (); | |
3859 | return; | |
b99bd4ef NC |
3860 | } |
3861 | ||
c19d1205 | 3862 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3863 | |
c19d1205 ZW |
3864 | demand_empty_rest_of_line (); |
3865 | } | |
e16bb312 | 3866 | |
e16bb312 | 3867 | |
c19d1205 | 3868 | /* Parse a personality directive. */ |
e16bb312 | 3869 | |
c19d1205 ZW |
3870 | static void |
3871 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3872 | { | |
3873 | char *name, *p, c; | |
a737bd4d | 3874 | |
921e5f0a | 3875 | if (!unwind.proc_start) |
c921be7d | 3876 | as_bad (MISSING_FNSTART); |
921e5f0a | 3877 | |
c19d1205 ZW |
3878 | if (unwind.personality_routine || unwind.personality_index != -1) |
3879 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3880 | |
d02603dc | 3881 | c = get_symbol_name (& name); |
c19d1205 | 3882 | p = input_line_pointer; |
d02603dc NC |
3883 | if (c == '"') |
3884 | ++ input_line_pointer; | |
c19d1205 ZW |
3885 | unwind.personality_routine = symbol_find_or_make (name); |
3886 | *p = c; | |
3887 | demand_empty_rest_of_line (); | |
3888 | } | |
e16bb312 | 3889 | |
e16bb312 | 3890 | |
c19d1205 | 3891 | /* Parse a directive saving core registers. */ |
e16bb312 | 3892 | |
c19d1205 ZW |
3893 | static void |
3894 | s_arm_unwind_save_core (void) | |
e16bb312 | 3895 | { |
c19d1205 ZW |
3896 | valueT op; |
3897 | long range; | |
3898 | int n; | |
e16bb312 | 3899 | |
c19d1205 ZW |
3900 | range = parse_reg_list (&input_line_pointer); |
3901 | if (range == FAIL) | |
e16bb312 | 3902 | { |
c19d1205 ZW |
3903 | as_bad (_("expected register list")); |
3904 | ignore_rest_of_line (); | |
3905 | return; | |
3906 | } | |
e16bb312 | 3907 | |
c19d1205 | 3908 | demand_empty_rest_of_line (); |
e16bb312 | 3909 | |
c19d1205 ZW |
3910 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3911 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3912 | ip because it is clobbered by calls. */ | |
3913 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3914 | && (range & 0x3000) == 0x1000) | |
3915 | { | |
3916 | unwind.opcode_count--; | |
3917 | unwind.sp_restored = 0; | |
3918 | range = (range | 0x2000) & ~0x1000; | |
3919 | unwind.pending_offset = 0; | |
3920 | } | |
e16bb312 | 3921 | |
01ae4198 DJ |
3922 | /* Pop r4-r15. */ |
3923 | if (range & 0xfff0) | |
c19d1205 | 3924 | { |
01ae4198 DJ |
3925 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3926 | registers starting with r4, plus maybe r14. */ | |
3927 | for (n = 0; n < 8; n++) | |
3928 | { | |
3929 | /* Break at the first non-saved register. */ | |
3930 | if ((range & (1 << (n + 4))) == 0) | |
3931 | break; | |
3932 | } | |
3933 | /* See if there are any other bits set. */ | |
3934 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3935 | { | |
3936 | /* Use the long form. */ | |
3937 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3938 | add_unwind_opcode (op, 2); | |
3939 | } | |
0dd132b6 | 3940 | else |
01ae4198 DJ |
3941 | { |
3942 | /* Use the short form. */ | |
3943 | if (range & 0x4000) | |
3944 | op = 0xa8; /* Pop r14. */ | |
3945 | else | |
3946 | op = 0xa0; /* Do not pop r14. */ | |
3947 | op |= (n - 1); | |
3948 | add_unwind_opcode (op, 1); | |
3949 | } | |
c19d1205 | 3950 | } |
0dd132b6 | 3951 | |
c19d1205 ZW |
3952 | /* Pop r0-r3. */ |
3953 | if (range & 0xf) | |
3954 | { | |
3955 | op = 0xb100 | (range & 0xf); | |
3956 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3957 | } |
3958 | ||
c19d1205 ZW |
3959 | /* Record the number of bytes pushed. */ |
3960 | for (n = 0; n < 16; n++) | |
3961 | { | |
3962 | if (range & (1 << n)) | |
3963 | unwind.frame_size += 4; | |
3964 | } | |
0dd132b6 NC |
3965 | } |
3966 | ||
c19d1205 ZW |
3967 | |
3968 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3969 | |
3970 | static void | |
c19d1205 | 3971 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3972 | { |
c19d1205 ZW |
3973 | expressionS exp; |
3974 | int num_regs; | |
3975 | valueT op; | |
b99bd4ef | 3976 | |
c19d1205 ZW |
3977 | /* Get Number of registers to transfer. */ |
3978 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3979 | expression (&exp); | |
3980 | else | |
3981 | exp.X_op = O_illegal; | |
b99bd4ef | 3982 | |
c19d1205 | 3983 | if (exp.X_op != O_constant) |
b99bd4ef | 3984 | { |
c19d1205 ZW |
3985 | as_bad (_("expected , <constant>")); |
3986 | ignore_rest_of_line (); | |
b99bd4ef NC |
3987 | return; |
3988 | } | |
3989 | ||
c19d1205 ZW |
3990 | num_regs = exp.X_add_number; |
3991 | ||
3992 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3993 | { |
c19d1205 ZW |
3994 | as_bad (_("number of registers must be in the range [1:4]")); |
3995 | ignore_rest_of_line (); | |
b99bd4ef NC |
3996 | return; |
3997 | } | |
3998 | ||
c19d1205 | 3999 | demand_empty_rest_of_line (); |
b99bd4ef | 4000 | |
c19d1205 ZW |
4001 | if (reg == 4) |
4002 | { | |
4003 | /* Short form. */ | |
4004 | op = 0xb4 | (num_regs - 1); | |
4005 | add_unwind_opcode (op, 1); | |
4006 | } | |
b99bd4ef NC |
4007 | else |
4008 | { | |
c19d1205 ZW |
4009 | /* Long form. */ |
4010 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
4011 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4012 | } |
c19d1205 | 4013 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
4014 | } |
4015 | ||
c19d1205 | 4016 | |
fa073d69 MS |
4017 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
4018 | ||
4019 | static void | |
4020 | s_arm_unwind_save_vfp_armv6 (void) | |
4021 | { | |
4022 | int count; | |
4023 | unsigned int start; | |
4024 | valueT op; | |
4025 | int num_vfpv3_regs = 0; | |
4026 | int num_regs_below_16; | |
4027 | ||
4028 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
4029 | if (count == FAIL) | |
4030 | { | |
4031 | as_bad (_("expected register list")); | |
4032 | ignore_rest_of_line (); | |
4033 | return; | |
4034 | } | |
4035 | ||
4036 | demand_empty_rest_of_line (); | |
4037 | ||
4038 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
4039 | than FSTMX/FLDMX-style ones). */ | |
4040 | ||
4041 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
4042 | if (start >= 16) | |
4043 | num_vfpv3_regs = count; | |
4044 | else if (start + count > 16) | |
4045 | num_vfpv3_regs = start + count - 16; | |
4046 | ||
4047 | if (num_vfpv3_regs > 0) | |
4048 | { | |
4049 | int start_offset = start > 16 ? start - 16 : 0; | |
4050 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
4051 | add_unwind_opcode (op, 2); | |
4052 | } | |
4053 | ||
4054 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
4055 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 4056 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
4057 | if (num_regs_below_16 > 0) |
4058 | { | |
4059 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
4060 | add_unwind_opcode (op, 2); | |
4061 | } | |
4062 | ||
4063 | unwind.frame_size += count * 8; | |
4064 | } | |
4065 | ||
4066 | ||
4067 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
4068 | |
4069 | static void | |
c19d1205 | 4070 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 4071 | { |
c19d1205 | 4072 | int count; |
ca3f61f7 | 4073 | unsigned int reg; |
c19d1205 | 4074 | valueT op; |
b99bd4ef | 4075 | |
5287ad62 | 4076 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 4077 | if (count == FAIL) |
b99bd4ef | 4078 | { |
c19d1205 ZW |
4079 | as_bad (_("expected register list")); |
4080 | ignore_rest_of_line (); | |
b99bd4ef NC |
4081 | return; |
4082 | } | |
4083 | ||
c19d1205 | 4084 | demand_empty_rest_of_line (); |
b99bd4ef | 4085 | |
c19d1205 | 4086 | if (reg == 8) |
b99bd4ef | 4087 | { |
c19d1205 ZW |
4088 | /* Short form. */ |
4089 | op = 0xb8 | (count - 1); | |
4090 | add_unwind_opcode (op, 1); | |
b99bd4ef | 4091 | } |
c19d1205 | 4092 | else |
b99bd4ef | 4093 | { |
c19d1205 ZW |
4094 | /* Long form. */ |
4095 | op = 0xb300 | (reg << 4) | (count - 1); | |
4096 | add_unwind_opcode (op, 2); | |
b99bd4ef | 4097 | } |
c19d1205 ZW |
4098 | unwind.frame_size += count * 8 + 4; |
4099 | } | |
b99bd4ef | 4100 | |
b99bd4ef | 4101 | |
c19d1205 ZW |
4102 | /* Parse a directive saving iWMMXt data registers. */ |
4103 | ||
4104 | static void | |
4105 | s_arm_unwind_save_mmxwr (void) | |
4106 | { | |
4107 | int reg; | |
4108 | int hi_reg; | |
4109 | int i; | |
4110 | unsigned mask = 0; | |
4111 | valueT op; | |
b99bd4ef | 4112 | |
c19d1205 ZW |
4113 | if (*input_line_pointer == '{') |
4114 | input_line_pointer++; | |
b99bd4ef | 4115 | |
c19d1205 | 4116 | do |
b99bd4ef | 4117 | { |
dcbf9037 | 4118 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 4119 | |
c19d1205 | 4120 | if (reg == FAIL) |
b99bd4ef | 4121 | { |
9b7132d3 | 4122 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 4123 | goto error; |
b99bd4ef NC |
4124 | } |
4125 | ||
c19d1205 ZW |
4126 | if (mask >> reg) |
4127 | as_tsktsk (_("register list not in ascending order")); | |
4128 | mask |= 1 << reg; | |
b99bd4ef | 4129 | |
c19d1205 ZW |
4130 | if (*input_line_pointer == '-') |
4131 | { | |
4132 | input_line_pointer++; | |
dcbf9037 | 4133 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
4134 | if (hi_reg == FAIL) |
4135 | { | |
9b7132d3 | 4136 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
4137 | goto error; |
4138 | } | |
4139 | else if (reg >= hi_reg) | |
4140 | { | |
4141 | as_bad (_("bad register range")); | |
4142 | goto error; | |
4143 | } | |
4144 | for (; reg < hi_reg; reg++) | |
4145 | mask |= 1 << reg; | |
4146 | } | |
4147 | } | |
4148 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 4149 | |
d996d970 | 4150 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4151 | |
c19d1205 | 4152 | demand_empty_rest_of_line (); |
b99bd4ef | 4153 | |
708587a4 | 4154 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4155 | the list. */ |
4156 | flush_pending_unwind (); | |
b99bd4ef | 4157 | |
c19d1205 | 4158 | for (i = 0; i < 16; i++) |
b99bd4ef | 4159 | { |
c19d1205 ZW |
4160 | if (mask & (1 << i)) |
4161 | unwind.frame_size += 8; | |
b99bd4ef NC |
4162 | } |
4163 | ||
c19d1205 ZW |
4164 | /* Attempt to combine with a previous opcode. We do this because gcc |
4165 | likes to output separate unwind directives for a single block of | |
4166 | registers. */ | |
4167 | if (unwind.opcode_count > 0) | |
b99bd4ef | 4168 | { |
c19d1205 ZW |
4169 | i = unwind.opcodes[unwind.opcode_count - 1]; |
4170 | if ((i & 0xf8) == 0xc0) | |
4171 | { | |
4172 | i &= 7; | |
4173 | /* Only merge if the blocks are contiguous. */ | |
4174 | if (i < 6) | |
4175 | { | |
4176 | if ((mask & 0xfe00) == (1 << 9)) | |
4177 | { | |
4178 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
4179 | unwind.opcode_count--; | |
4180 | } | |
4181 | } | |
4182 | else if (i == 6 && unwind.opcode_count >= 2) | |
4183 | { | |
4184 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
4185 | reg = i >> 4; | |
4186 | i &= 0xf; | |
b99bd4ef | 4187 | |
c19d1205 ZW |
4188 | op = 0xffff << (reg - 1); |
4189 | if (reg > 0 | |
87a1fd79 | 4190 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
4191 | { |
4192 | op = (1 << (reg + i + 1)) - 1; | |
4193 | op &= ~((1 << reg) - 1); | |
4194 | mask |= op; | |
4195 | unwind.opcode_count -= 2; | |
4196 | } | |
4197 | } | |
4198 | } | |
b99bd4ef NC |
4199 | } |
4200 | ||
c19d1205 ZW |
4201 | hi_reg = 15; |
4202 | /* We want to generate opcodes in the order the registers have been | |
4203 | saved, ie. descending order. */ | |
4204 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 4205 | { |
c19d1205 ZW |
4206 | /* Save registers in blocks. */ |
4207 | if (reg < 0 | |
4208 | || !(mask & (1 << reg))) | |
4209 | { | |
4210 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 4211 | preceding block. */ |
c19d1205 ZW |
4212 | if (reg != hi_reg) |
4213 | { | |
4214 | if (reg == 9) | |
4215 | { | |
4216 | /* Short form. */ | |
4217 | op = 0xc0 | (hi_reg - 10); | |
4218 | add_unwind_opcode (op, 1); | |
4219 | } | |
4220 | else | |
4221 | { | |
4222 | /* Long form. */ | |
4223 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4224 | add_unwind_opcode (op, 2); | |
4225 | } | |
4226 | } | |
4227 | hi_reg = reg - 1; | |
4228 | } | |
b99bd4ef NC |
4229 | } |
4230 | ||
c19d1205 ZW |
4231 | return; |
4232 | error: | |
4233 | ignore_rest_of_line (); | |
b99bd4ef NC |
4234 | } |
4235 | ||
4236 | static void | |
c19d1205 | 4237 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4238 | { |
c19d1205 ZW |
4239 | int reg; |
4240 | int hi_reg; | |
4241 | unsigned mask = 0; | |
4242 | valueT op; | |
b99bd4ef | 4243 | |
c19d1205 ZW |
4244 | if (*input_line_pointer == '{') |
4245 | input_line_pointer++; | |
b99bd4ef | 4246 | |
477330fc RM |
4247 | skip_whitespace (input_line_pointer); |
4248 | ||
c19d1205 | 4249 | do |
b99bd4ef | 4250 | { |
dcbf9037 | 4251 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4252 | |
c19d1205 ZW |
4253 | if (reg == FAIL) |
4254 | { | |
9b7132d3 | 4255 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4256 | goto error; |
4257 | } | |
b99bd4ef | 4258 | |
c19d1205 ZW |
4259 | reg -= 8; |
4260 | if (mask >> reg) | |
4261 | as_tsktsk (_("register list not in ascending order")); | |
4262 | mask |= 1 << reg; | |
b99bd4ef | 4263 | |
c19d1205 ZW |
4264 | if (*input_line_pointer == '-') |
4265 | { | |
4266 | input_line_pointer++; | |
dcbf9037 | 4267 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4268 | if (hi_reg == FAIL) |
4269 | { | |
9b7132d3 | 4270 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4271 | goto error; |
4272 | } | |
4273 | else if (reg >= hi_reg) | |
4274 | { | |
4275 | as_bad (_("bad register range")); | |
4276 | goto error; | |
4277 | } | |
4278 | for (; reg < hi_reg; reg++) | |
4279 | mask |= 1 << reg; | |
4280 | } | |
b99bd4ef | 4281 | } |
c19d1205 | 4282 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4283 | |
d996d970 | 4284 | skip_past_char (&input_line_pointer, '}'); |
b99bd4ef | 4285 | |
c19d1205 ZW |
4286 | demand_empty_rest_of_line (); |
4287 | ||
708587a4 | 4288 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4289 | the list. */ |
4290 | flush_pending_unwind (); | |
b99bd4ef | 4291 | |
c19d1205 | 4292 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4293 | { |
c19d1205 ZW |
4294 | if (mask & (1 << reg)) |
4295 | unwind.frame_size += 4; | |
b99bd4ef | 4296 | } |
c19d1205 ZW |
4297 | op = 0xc700 | mask; |
4298 | add_unwind_opcode (op, 2); | |
4299 | return; | |
4300 | error: | |
4301 | ignore_rest_of_line (); | |
b99bd4ef NC |
4302 | } |
4303 | ||
c19d1205 | 4304 | |
fa073d69 MS |
4305 | /* Parse an unwind_save directive. |
4306 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4307 | |
b99bd4ef | 4308 | static void |
fa073d69 | 4309 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4310 | { |
c19d1205 ZW |
4311 | char *peek; |
4312 | struct reg_entry *reg; | |
4313 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4314 | |
921e5f0a | 4315 | if (!unwind.proc_start) |
c921be7d | 4316 | as_bad (MISSING_FNSTART); |
921e5f0a | 4317 | |
c19d1205 ZW |
4318 | /* Figure out what sort of save we have. */ |
4319 | peek = input_line_pointer; | |
b99bd4ef | 4320 | |
c19d1205 | 4321 | if (*peek == '{') |
b99bd4ef | 4322 | { |
c19d1205 ZW |
4323 | had_brace = TRUE; |
4324 | peek++; | |
b99bd4ef NC |
4325 | } |
4326 | ||
c19d1205 | 4327 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4328 | |
c19d1205 | 4329 | if (!reg) |
b99bd4ef | 4330 | { |
c19d1205 ZW |
4331 | as_bad (_("register expected")); |
4332 | ignore_rest_of_line (); | |
b99bd4ef NC |
4333 | return; |
4334 | } | |
4335 | ||
c19d1205 | 4336 | switch (reg->type) |
b99bd4ef | 4337 | { |
c19d1205 ZW |
4338 | case REG_TYPE_FN: |
4339 | if (had_brace) | |
4340 | { | |
4341 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4342 | ignore_rest_of_line (); | |
4343 | return; | |
4344 | } | |
93ac2687 | 4345 | input_line_pointer = peek; |
c19d1205 | 4346 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4347 | return; |
c19d1205 | 4348 | |
1f5afe1c NC |
4349 | case REG_TYPE_RN: |
4350 | s_arm_unwind_save_core (); | |
4351 | return; | |
4352 | ||
fa073d69 MS |
4353 | case REG_TYPE_VFD: |
4354 | if (arch_v6) | |
477330fc | 4355 | s_arm_unwind_save_vfp_armv6 (); |
fa073d69 | 4356 | else |
477330fc | 4357 | s_arm_unwind_save_vfp (); |
fa073d69 | 4358 | return; |
1f5afe1c NC |
4359 | |
4360 | case REG_TYPE_MMXWR: | |
4361 | s_arm_unwind_save_mmxwr (); | |
4362 | return; | |
4363 | ||
4364 | case REG_TYPE_MMXWCG: | |
4365 | s_arm_unwind_save_mmxwcg (); | |
4366 | return; | |
c19d1205 ZW |
4367 | |
4368 | default: | |
4369 | as_bad (_(".unwind_save does not support this kind of register")); | |
4370 | ignore_rest_of_line (); | |
b99bd4ef | 4371 | } |
c19d1205 | 4372 | } |
b99bd4ef | 4373 | |
b99bd4ef | 4374 | |
c19d1205 ZW |
4375 | /* Parse an unwind_movsp directive. */ |
4376 | ||
4377 | static void | |
4378 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4379 | { | |
4380 | int reg; | |
4381 | valueT op; | |
4fa3602b | 4382 | int offset; |
c19d1205 | 4383 | |
921e5f0a | 4384 | if (!unwind.proc_start) |
c921be7d | 4385 | as_bad (MISSING_FNSTART); |
921e5f0a | 4386 | |
dcbf9037 | 4387 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4388 | if (reg == FAIL) |
b99bd4ef | 4389 | { |
9b7132d3 | 4390 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4391 | ignore_rest_of_line (); |
b99bd4ef NC |
4392 | return; |
4393 | } | |
4fa3602b PB |
4394 | |
4395 | /* Optional constant. */ | |
4396 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4397 | { | |
4398 | if (immediate_for_directive (&offset) == FAIL) | |
4399 | return; | |
4400 | } | |
4401 | else | |
4402 | offset = 0; | |
4403 | ||
c19d1205 | 4404 | demand_empty_rest_of_line (); |
b99bd4ef | 4405 | |
c19d1205 | 4406 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4407 | { |
c19d1205 | 4408 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4409 | return; |
4410 | } | |
4411 | ||
c19d1205 ZW |
4412 | if (unwind.fp_reg != REG_SP) |
4413 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4414 | |
c19d1205 ZW |
4415 | /* Generate opcode to restore the value. */ |
4416 | op = 0x90 | reg; | |
4417 | add_unwind_opcode (op, 1); | |
4418 | ||
4419 | /* Record the information for later. */ | |
4420 | unwind.fp_reg = reg; | |
4fa3602b | 4421 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4422 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4423 | } |
4424 | ||
c19d1205 ZW |
4425 | /* Parse an unwind_pad directive. */ |
4426 | ||
b05fe5cf | 4427 | static void |
c19d1205 | 4428 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4429 | { |
c19d1205 | 4430 | int offset; |
b05fe5cf | 4431 | |
921e5f0a | 4432 | if (!unwind.proc_start) |
c921be7d | 4433 | as_bad (MISSING_FNSTART); |
921e5f0a | 4434 | |
c19d1205 ZW |
4435 | if (immediate_for_directive (&offset) == FAIL) |
4436 | return; | |
b99bd4ef | 4437 | |
c19d1205 ZW |
4438 | if (offset & 3) |
4439 | { | |
4440 | as_bad (_("stack increment must be multiple of 4")); | |
4441 | ignore_rest_of_line (); | |
4442 | return; | |
4443 | } | |
b99bd4ef | 4444 | |
c19d1205 ZW |
4445 | /* Don't generate any opcodes, just record the details for later. */ |
4446 | unwind.frame_size += offset; | |
4447 | unwind.pending_offset += offset; | |
4448 | ||
4449 | demand_empty_rest_of_line (); | |
4450 | } | |
4451 | ||
4452 | /* Parse an unwind_setfp directive. */ | |
4453 | ||
4454 | static void | |
4455 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4456 | { |
c19d1205 ZW |
4457 | int sp_reg; |
4458 | int fp_reg; | |
4459 | int offset; | |
4460 | ||
921e5f0a | 4461 | if (!unwind.proc_start) |
c921be7d | 4462 | as_bad (MISSING_FNSTART); |
921e5f0a | 4463 | |
dcbf9037 | 4464 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4465 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4466 | sp_reg = FAIL; | |
4467 | else | |
dcbf9037 | 4468 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4469 | |
c19d1205 ZW |
4470 | if (fp_reg == FAIL || sp_reg == FAIL) |
4471 | { | |
4472 | as_bad (_("expected <reg>, <reg>")); | |
4473 | ignore_rest_of_line (); | |
4474 | return; | |
4475 | } | |
b99bd4ef | 4476 | |
c19d1205 ZW |
4477 | /* Optional constant. */ |
4478 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4479 | { | |
4480 | if (immediate_for_directive (&offset) == FAIL) | |
4481 | return; | |
4482 | } | |
4483 | else | |
4484 | offset = 0; | |
a737bd4d | 4485 | |
c19d1205 | 4486 | demand_empty_rest_of_line (); |
a737bd4d | 4487 | |
fdfde340 | 4488 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4489 | { |
c19d1205 ZW |
4490 | as_bad (_("register must be either sp or set by a previous" |
4491 | "unwind_movsp directive")); | |
4492 | return; | |
a737bd4d NC |
4493 | } |
4494 | ||
c19d1205 ZW |
4495 | /* Don't generate any opcodes, just record the information for later. */ |
4496 | unwind.fp_reg = fp_reg; | |
4497 | unwind.fp_used = 1; | |
fdfde340 | 4498 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4499 | unwind.fp_offset = unwind.frame_size - offset; |
4500 | else | |
4501 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4502 | } |
4503 | ||
c19d1205 ZW |
4504 | /* Parse an unwind_raw directive. */ |
4505 | ||
4506 | static void | |
4507 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4508 | { |
c19d1205 | 4509 | expressionS exp; |
708587a4 | 4510 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4511 | unsigned char op[16]; |
4512 | int count; | |
a737bd4d | 4513 | |
921e5f0a | 4514 | if (!unwind.proc_start) |
c921be7d | 4515 | as_bad (MISSING_FNSTART); |
921e5f0a | 4516 | |
c19d1205 ZW |
4517 | expression (&exp); |
4518 | if (exp.X_op == O_constant | |
4519 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4520 | { |
c19d1205 ZW |
4521 | unwind.frame_size += exp.X_add_number; |
4522 | expression (&exp); | |
4523 | } | |
4524 | else | |
4525 | exp.X_op = O_illegal; | |
a737bd4d | 4526 | |
c19d1205 ZW |
4527 | if (exp.X_op != O_constant) |
4528 | { | |
4529 | as_bad (_("expected <offset>, <opcode>")); | |
4530 | ignore_rest_of_line (); | |
4531 | return; | |
4532 | } | |
a737bd4d | 4533 | |
c19d1205 | 4534 | count = 0; |
a737bd4d | 4535 | |
c19d1205 ZW |
4536 | /* Parse the opcode. */ |
4537 | for (;;) | |
4538 | { | |
4539 | if (count >= 16) | |
4540 | { | |
4541 | as_bad (_("unwind opcode too long")); | |
4542 | ignore_rest_of_line (); | |
a737bd4d | 4543 | } |
c19d1205 | 4544 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4545 | { |
c19d1205 ZW |
4546 | as_bad (_("invalid unwind opcode")); |
4547 | ignore_rest_of_line (); | |
4548 | return; | |
a737bd4d | 4549 | } |
c19d1205 | 4550 | op[count++] = exp.X_add_number; |
a737bd4d | 4551 | |
c19d1205 ZW |
4552 | /* Parse the next byte. */ |
4553 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4554 | break; | |
a737bd4d | 4555 | |
c19d1205 ZW |
4556 | expression (&exp); |
4557 | } | |
b99bd4ef | 4558 | |
c19d1205 ZW |
4559 | /* Add the opcode bytes in reverse order. */ |
4560 | while (count--) | |
4561 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4562 | |
c19d1205 | 4563 | demand_empty_rest_of_line (); |
b99bd4ef | 4564 | } |
ee065d83 PB |
4565 | |
4566 | ||
4567 | /* Parse a .eabi_attribute directive. */ | |
4568 | ||
4569 | static void | |
4570 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4571 | { | |
0420f52b | 4572 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); |
ee3c0378 AS |
4573 | |
4574 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4575 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4576 | } |
4577 | ||
0855e32b NS |
4578 | /* Emit a tls fix for the symbol. */ |
4579 | ||
4580 | static void | |
4581 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4582 | { | |
4583 | char *p; | |
4584 | expressionS exp; | |
4585 | #ifdef md_flush_pending_output | |
4586 | md_flush_pending_output (); | |
4587 | #endif | |
4588 | ||
4589 | #ifdef md_cons_align | |
4590 | md_cons_align (4); | |
4591 | #endif | |
4592 | ||
4593 | /* Since we're just labelling the code, there's no need to define a | |
4594 | mapping symbol. */ | |
4595 | expression (&exp); | |
4596 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4597 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4598 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4599 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4600 | } | |
cdf9ccec | 4601 | #endif /* OBJ_ELF */ |
0855e32b | 4602 | |
ee065d83 | 4603 | static void s_arm_arch (int); |
7a1d4c38 | 4604 | static void s_arm_object_arch (int); |
ee065d83 PB |
4605 | static void s_arm_cpu (int); |
4606 | static void s_arm_fpu (int); | |
69133863 | 4607 | static void s_arm_arch_extension (int); |
b99bd4ef | 4608 | |
f0927246 NC |
4609 | #ifdef TE_PE |
4610 | ||
4611 | static void | |
5f4273c7 | 4612 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4613 | { |
4614 | expressionS exp; | |
4615 | ||
4616 | do | |
4617 | { | |
4618 | expression (&exp); | |
4619 | if (exp.X_op == O_symbol) | |
4620 | exp.X_op = O_secrel; | |
4621 | ||
4622 | emit_expr (&exp, 4); | |
4623 | } | |
4624 | while (*input_line_pointer++ == ','); | |
4625 | ||
4626 | input_line_pointer--; | |
4627 | demand_empty_rest_of_line (); | |
4628 | } | |
4629 | #endif /* TE_PE */ | |
4630 | ||
c19d1205 ZW |
4631 | /* This table describes all the machine specific pseudo-ops the assembler |
4632 | has to support. The fields are: | |
4633 | pseudo-op name without dot | |
4634 | function to call to execute this pseudo-op | |
4635 | Integer arg to pass to the function. */ | |
b99bd4ef | 4636 | |
c19d1205 | 4637 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4638 | { |
c19d1205 ZW |
4639 | /* Never called because '.req' does not start a line. */ |
4640 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4641 | /* Following two are likewise never called. */ |
4642 | { "dn", s_dn, 0 }, | |
4643 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4644 | { "unreq", s_unreq, 0 }, |
4645 | { "bss", s_bss, 0 }, | |
db2ed2e0 | 4646 | { "align", s_align_ptwo, 2 }, |
c19d1205 ZW |
4647 | { "arm", s_arm, 0 }, |
4648 | { "thumb", s_thumb, 0 }, | |
4649 | { "code", s_code, 0 }, | |
4650 | { "force_thumb", s_force_thumb, 0 }, | |
4651 | { "thumb_func", s_thumb_func, 0 }, | |
4652 | { "thumb_set", s_thumb_set, 0 }, | |
4653 | { "even", s_even, 0 }, | |
4654 | { "ltorg", s_ltorg, 0 }, | |
4655 | { "pool", s_ltorg, 0 }, | |
4656 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4657 | { "cpu", s_arm_cpu, 0 }, |
4658 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4659 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4660 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4661 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4662 | #ifdef OBJ_ELF |
c921be7d NC |
4663 | { "word", s_arm_elf_cons, 4 }, |
4664 | { "long", s_arm_elf_cons, 4 }, | |
4665 | { "inst.n", s_arm_elf_inst, 2 }, | |
4666 | { "inst.w", s_arm_elf_inst, 4 }, | |
4667 | { "inst", s_arm_elf_inst, 0 }, | |
4668 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4669 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4670 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4671 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4672 | { "personality", s_arm_unwind_personality, 0 }, | |
4673 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4674 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4675 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4676 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4677 | { "movsp", s_arm_unwind_movsp, 0 }, |
4678 | { "pad", s_arm_unwind_pad, 0 }, | |
4679 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4680 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4681 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4682 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4683 | #else |
4684 | { "word", cons, 4}, | |
f0927246 NC |
4685 | |
4686 | /* These are used for dwarf. */ | |
4687 | {"2byte", cons, 2}, | |
4688 | {"4byte", cons, 4}, | |
4689 | {"8byte", cons, 8}, | |
4690 | /* These are used for dwarf2. */ | |
4691 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4692 | { "loc", dwarf2_directive_loc, 0 }, | |
4693 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4694 | #endif |
4695 | { "extend", float_cons, 'x' }, | |
4696 | { "ldouble", float_cons, 'x' }, | |
4697 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4698 | #ifdef TE_PE |
4699 | {"secrel32", pe_directive_secrel, 0}, | |
4700 | #endif | |
2e6976a8 DG |
4701 | |
4702 | /* These are for compatibility with CodeComposer Studio. */ | |
4703 | {"ref", s_ccs_ref, 0}, | |
4704 | {"def", s_ccs_def, 0}, | |
4705 | {"asmfunc", s_ccs_asmfunc, 0}, | |
4706 | {"endasmfunc", s_ccs_endasmfunc, 0}, | |
4707 | ||
c19d1205 ZW |
4708 | { 0, 0, 0 } |
4709 | }; | |
4710 | \f | |
4711 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4712 | |
c19d1205 ZW |
4713 | /* Generic immediate-value read function for use in insn parsing. |
4714 | STR points to the beginning of the immediate (the leading #); | |
4715 | VAL receives the value; if the value is outside [MIN, MAX] | |
4716 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4717 | optional. */ | |
b99bd4ef | 4718 | |
c19d1205 ZW |
4719 | static int |
4720 | parse_immediate (char **str, int *val, int min, int max, | |
4721 | bfd_boolean prefix_opt) | |
4722 | { | |
4723 | expressionS exp; | |
4724 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4725 | if (exp.X_op != O_constant) | |
b99bd4ef | 4726 | { |
c19d1205 ZW |
4727 | inst.error = _("constant expression required"); |
4728 | return FAIL; | |
4729 | } | |
b99bd4ef | 4730 | |
c19d1205 ZW |
4731 | if (exp.X_add_number < min || exp.X_add_number > max) |
4732 | { | |
4733 | inst.error = _("immediate value out of range"); | |
4734 | return FAIL; | |
4735 | } | |
b99bd4ef | 4736 | |
c19d1205 ZW |
4737 | *val = exp.X_add_number; |
4738 | return SUCCESS; | |
4739 | } | |
b99bd4ef | 4740 | |
5287ad62 | 4741 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4742 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4743 | instructions. Puts the result directly in inst.operands[i]. */ |
4744 | ||
4745 | static int | |
8335d6aa JW |
4746 | parse_big_immediate (char **str, int i, expressionS *in_exp, |
4747 | bfd_boolean allow_symbol_p) | |
5287ad62 JB |
4748 | { |
4749 | expressionS exp; | |
8335d6aa | 4750 | expressionS *exp_p = in_exp ? in_exp : &exp; |
5287ad62 JB |
4751 | char *ptr = *str; |
4752 | ||
8335d6aa | 4753 | my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); |
5287ad62 | 4754 | |
8335d6aa | 4755 | if (exp_p->X_op == O_constant) |
036dc3f7 | 4756 | { |
8335d6aa | 4757 | inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; |
036dc3f7 PB |
4758 | /* If we're on a 64-bit host, then a 64-bit number can be returned using |
4759 | O_constant. We have to be careful not to break compilation for | |
4760 | 32-bit X_add_number, though. */ | |
8335d6aa | 4761 | if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 | 4762 | { |
8335d6aa JW |
4763 | /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ |
4764 | inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) | |
4765 | & 0xffffffff); | |
036dc3f7 PB |
4766 | inst.operands[i].regisimm = 1; |
4767 | } | |
4768 | } | |
8335d6aa JW |
4769 | else if (exp_p->X_op == O_big |
4770 | && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) | |
5287ad62 JB |
4771 | { |
4772 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4773 | |
5287ad62 | 4774 | /* Bignums have their least significant bits in |
477330fc RM |
4775 | generic_bignum[0]. Make sure we put 32 bits in imm and |
4776 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4777 | gas_assert (parts != 0); |
95b75c01 NC |
4778 | |
4779 | /* Make sure that the number is not too big. | |
4780 | PR 11972: Bignums can now be sign-extended to the | |
4781 | size of a .octa so check that the out of range bits | |
4782 | are all zero or all one. */ | |
8335d6aa | 4783 | if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) |
95b75c01 NC |
4784 | { |
4785 | LITTLENUM_TYPE m = -1; | |
4786 | ||
4787 | if (generic_bignum[parts * 2] != 0 | |
4788 | && generic_bignum[parts * 2] != m) | |
4789 | return FAIL; | |
4790 | ||
8335d6aa | 4791 | for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) |
95b75c01 NC |
4792 | if (generic_bignum[j] != generic_bignum[j-1]) |
4793 | return FAIL; | |
4794 | } | |
4795 | ||
5287ad62 JB |
4796 | inst.operands[i].imm = 0; |
4797 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4798 | inst.operands[i].imm |= generic_bignum[idx] |
4799 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4800 | inst.operands[i].reg = 0; |
4801 | for (j = 0; j < parts; j++, idx++) | |
477330fc RM |
4802 | inst.operands[i].reg |= generic_bignum[idx] |
4803 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
5287ad62 JB |
4804 | inst.operands[i].regisimm = 1; |
4805 | } | |
8335d6aa | 4806 | else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) |
5287ad62 | 4807 | return FAIL; |
5f4273c7 | 4808 | |
5287ad62 JB |
4809 | *str = ptr; |
4810 | ||
4811 | return SUCCESS; | |
4812 | } | |
4813 | ||
c19d1205 ZW |
4814 | /* Returns the pseudo-register number of an FPA immediate constant, |
4815 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4816 | |
c19d1205 ZW |
4817 | static int |
4818 | parse_fpa_immediate (char ** str) | |
4819 | { | |
4820 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4821 | char * save_in; | |
4822 | expressionS exp; | |
4823 | int i; | |
4824 | int j; | |
b99bd4ef | 4825 | |
c19d1205 ZW |
4826 | /* First try and match exact strings, this is to guarantee |
4827 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4828 | |
c19d1205 ZW |
4829 | for (i = 0; fp_const[i]; i++) |
4830 | { | |
4831 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4832 | { |
c19d1205 | 4833 | char *start = *str; |
b99bd4ef | 4834 | |
c19d1205 ZW |
4835 | *str += strlen (fp_const[i]); |
4836 | if (is_end_of_line[(unsigned char) **str]) | |
4837 | return i + 8; | |
4838 | *str = start; | |
4839 | } | |
4840 | } | |
b99bd4ef | 4841 | |
c19d1205 ZW |
4842 | /* Just because we didn't get a match doesn't mean that the constant |
4843 | isn't valid, just that it is in a format that we don't | |
4844 | automatically recognize. Try parsing it with the standard | |
4845 | expression routines. */ | |
b99bd4ef | 4846 | |
c19d1205 | 4847 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4848 | |
c19d1205 ZW |
4849 | /* Look for a raw floating point number. */ |
4850 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4851 | && is_end_of_line[(unsigned char) *save_in]) | |
4852 | { | |
4853 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4854 | { | |
4855 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4856 | { |
c19d1205 ZW |
4857 | if (words[j] != fp_values[i][j]) |
4858 | break; | |
b99bd4ef NC |
4859 | } |
4860 | ||
c19d1205 | 4861 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4862 | { |
c19d1205 ZW |
4863 | *str = save_in; |
4864 | return i + 8; | |
b99bd4ef NC |
4865 | } |
4866 | } | |
4867 | } | |
b99bd4ef | 4868 | |
c19d1205 ZW |
4869 | /* Try and parse a more complex expression, this will probably fail |
4870 | unless the code uses a floating point prefix (eg "0f"). */ | |
4871 | save_in = input_line_pointer; | |
4872 | input_line_pointer = *str; | |
4873 | if (expression (&exp) == absolute_section | |
4874 | && exp.X_op == O_big | |
4875 | && exp.X_add_number < 0) | |
4876 | { | |
4877 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4878 | Ditto for 15. */ | |
ba592044 AM |
4879 | #define X_PRECISION 5 |
4880 | #define E_PRECISION 15L | |
4881 | if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0) | |
c19d1205 ZW |
4882 | { |
4883 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4884 | { | |
4885 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4886 | { | |
4887 | if (words[j] != fp_values[i][j]) | |
4888 | break; | |
4889 | } | |
b99bd4ef | 4890 | |
c19d1205 ZW |
4891 | if (j == MAX_LITTLENUMS) |
4892 | { | |
4893 | *str = input_line_pointer; | |
4894 | input_line_pointer = save_in; | |
4895 | return i + 8; | |
4896 | } | |
4897 | } | |
4898 | } | |
b99bd4ef NC |
4899 | } |
4900 | ||
c19d1205 ZW |
4901 | *str = input_line_pointer; |
4902 | input_line_pointer = save_in; | |
4903 | inst.error = _("invalid FPA immediate expression"); | |
4904 | return FAIL; | |
b99bd4ef NC |
4905 | } |
4906 | ||
136da414 JB |
4907 | /* Returns 1 if a number has "quarter-precision" float format |
4908 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4909 | ||
4910 | static int | |
4911 | is_quarter_float (unsigned imm) | |
4912 | { | |
4913 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4914 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4915 | } | |
4916 | ||
aacf0b33 KT |
4917 | |
4918 | /* Detect the presence of a floating point or integer zero constant, | |
4919 | i.e. #0.0 or #0. */ | |
4920 | ||
4921 | static bfd_boolean | |
4922 | parse_ifimm_zero (char **in) | |
4923 | { | |
4924 | int error_code; | |
4925 | ||
4926 | if (!is_immediate_prefix (**in)) | |
4927 | return FALSE; | |
4928 | ||
4929 | ++*in; | |
0900a05b JW |
4930 | |
4931 | /* Accept #0x0 as a synonym for #0. */ | |
4932 | if (strncmp (*in, "0x", 2) == 0) | |
4933 | { | |
4934 | int val; | |
4935 | if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL) | |
4936 | return FALSE; | |
4937 | return TRUE; | |
4938 | } | |
4939 | ||
aacf0b33 KT |
4940 | error_code = atof_generic (in, ".", EXP_CHARS, |
4941 | &generic_floating_point_number); | |
4942 | ||
4943 | if (!error_code | |
4944 | && generic_floating_point_number.sign == '+' | |
4945 | && (generic_floating_point_number.low | |
4946 | > generic_floating_point_number.leader)) | |
4947 | return TRUE; | |
4948 | ||
4949 | return FALSE; | |
4950 | } | |
4951 | ||
136da414 JB |
4952 | /* Parse an 8-bit "quarter-precision" floating point number of the form: |
4953 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4954 | The zero and minus-zero cases need special handling, since they can't be |
4955 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4956 | loaded as integer constants. */ | |
136da414 JB |
4957 | |
4958 | static unsigned | |
4959 | parse_qfloat_immediate (char **ccp, int *immed) | |
4960 | { | |
4961 | char *str = *ccp; | |
c96612cc | 4962 | char *fpnum; |
136da414 | 4963 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4964 | int found_fpchar = 0; |
5f4273c7 | 4965 | |
136da414 | 4966 | skip_past_char (&str, '#'); |
5f4273c7 | 4967 | |
c96612cc JB |
4968 | /* We must not accidentally parse an integer as a floating-point number. Make |
4969 | sure that the value we parse is not an integer by checking for special | |
4970 | characters '.' or 'e'. | |
4971 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4972 | information isn't in a very usable state at parse time. */ | |
4973 | fpnum = str; | |
4974 | skip_whitespace (fpnum); | |
4975 | ||
4976 | if (strncmp (fpnum, "0x", 2) == 0) | |
4977 | return FAIL; | |
4978 | else | |
4979 | { | |
4980 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
477330fc RM |
4981 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') |
4982 | { | |
4983 | found_fpchar = 1; | |
4984 | break; | |
4985 | } | |
c96612cc JB |
4986 | |
4987 | if (!found_fpchar) | |
477330fc | 4988 | return FAIL; |
c96612cc | 4989 | } |
5f4273c7 | 4990 | |
136da414 JB |
4991 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4992 | { | |
4993 | unsigned fpword = 0; | |
4994 | int i; | |
5f4273c7 | 4995 | |
136da414 JB |
4996 | /* Our FP word must be 32 bits (single-precision FP). */ |
4997 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
477330fc RM |
4998 | { |
4999 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
5000 | fpword |= words[i]; | |
5001 | } | |
5f4273c7 | 5002 | |
c96612cc | 5003 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
477330fc | 5004 | *immed = fpword; |
136da414 | 5005 | else |
477330fc | 5006 | return FAIL; |
136da414 JB |
5007 | |
5008 | *ccp = str; | |
5f4273c7 | 5009 | |
136da414 JB |
5010 | return SUCCESS; |
5011 | } | |
5f4273c7 | 5012 | |
136da414 JB |
5013 | return FAIL; |
5014 | } | |
5015 | ||
c19d1205 ZW |
5016 | /* Shift operands. */ |
5017 | enum shift_kind | |
b99bd4ef | 5018 | { |
c19d1205 ZW |
5019 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
5020 | }; | |
b99bd4ef | 5021 | |
c19d1205 ZW |
5022 | struct asm_shift_name |
5023 | { | |
5024 | const char *name; | |
5025 | enum shift_kind kind; | |
5026 | }; | |
b99bd4ef | 5027 | |
c19d1205 ZW |
5028 | /* Third argument to parse_shift. */ |
5029 | enum parse_shift_mode | |
5030 | { | |
5031 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
5032 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
5033 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
5034 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
5035 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
5036 | }; | |
b99bd4ef | 5037 | |
c19d1205 ZW |
5038 | /* Parse a <shift> specifier on an ARM data processing instruction. |
5039 | This has three forms: | |
b99bd4ef | 5040 | |
c19d1205 ZW |
5041 | (LSL|LSR|ASL|ASR|ROR) Rs |
5042 | (LSL|LSR|ASL|ASR|ROR) #imm | |
5043 | RRX | |
b99bd4ef | 5044 | |
c19d1205 ZW |
5045 | Note that ASL is assimilated to LSL in the instruction encoding, and |
5046 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 5047 | |
c19d1205 ZW |
5048 | static int |
5049 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 5050 | { |
c19d1205 ZW |
5051 | const struct asm_shift_name *shift_name; |
5052 | enum shift_kind shift; | |
5053 | char *s = *str; | |
5054 | char *p = s; | |
5055 | int reg; | |
b99bd4ef | 5056 | |
c19d1205 ZW |
5057 | for (p = *str; ISALPHA (*p); p++) |
5058 | ; | |
b99bd4ef | 5059 | |
c19d1205 | 5060 | if (p == *str) |
b99bd4ef | 5061 | { |
c19d1205 ZW |
5062 | inst.error = _("shift expression expected"); |
5063 | return FAIL; | |
b99bd4ef NC |
5064 | } |
5065 | ||
21d799b5 | 5066 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
477330fc | 5067 | p - *str); |
c19d1205 ZW |
5068 | |
5069 | if (shift_name == NULL) | |
b99bd4ef | 5070 | { |
c19d1205 ZW |
5071 | inst.error = _("shift expression expected"); |
5072 | return FAIL; | |
b99bd4ef NC |
5073 | } |
5074 | ||
c19d1205 | 5075 | shift = shift_name->kind; |
b99bd4ef | 5076 | |
c19d1205 ZW |
5077 | switch (mode) |
5078 | { | |
5079 | case NO_SHIFT_RESTRICT: | |
5080 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 5081 | |
c19d1205 ZW |
5082 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
5083 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
5084 | { | |
5085 | inst.error = _("'LSL' or 'ASR' required"); | |
5086 | return FAIL; | |
5087 | } | |
5088 | break; | |
b99bd4ef | 5089 | |
c19d1205 ZW |
5090 | case SHIFT_LSL_IMMEDIATE: |
5091 | if (shift != SHIFT_LSL) | |
5092 | { | |
5093 | inst.error = _("'LSL' required"); | |
5094 | return FAIL; | |
5095 | } | |
5096 | break; | |
b99bd4ef | 5097 | |
c19d1205 ZW |
5098 | case SHIFT_ASR_IMMEDIATE: |
5099 | if (shift != SHIFT_ASR) | |
5100 | { | |
5101 | inst.error = _("'ASR' required"); | |
5102 | return FAIL; | |
5103 | } | |
5104 | break; | |
b99bd4ef | 5105 | |
c19d1205 ZW |
5106 | default: abort (); |
5107 | } | |
b99bd4ef | 5108 | |
c19d1205 ZW |
5109 | if (shift != SHIFT_RRX) |
5110 | { | |
5111 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
5112 | skip_whitespace (p); | |
b99bd4ef | 5113 | |
c19d1205 | 5114 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 5115 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5116 | { |
5117 | inst.operands[i].imm = reg; | |
5118 | inst.operands[i].immisreg = 1; | |
5119 | } | |
5120 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5121 | return FAIL; | |
5122 | } | |
5123 | inst.operands[i].shift_kind = shift; | |
5124 | inst.operands[i].shifted = 1; | |
5125 | *str = p; | |
5126 | return SUCCESS; | |
b99bd4ef NC |
5127 | } |
5128 | ||
c19d1205 | 5129 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 5130 | |
c19d1205 ZW |
5131 | #<immediate> |
5132 | #<immediate>, <rotate> | |
5133 | <Rm> | |
5134 | <Rm>, <shift> | |
b99bd4ef | 5135 | |
c19d1205 ZW |
5136 | where <shift> is defined by parse_shift above, and <rotate> is a |
5137 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 5138 | is deferred to md_apply_fix. */ |
b99bd4ef | 5139 | |
c19d1205 ZW |
5140 | static int |
5141 | parse_shifter_operand (char **str, int i) | |
5142 | { | |
5143 | int value; | |
91d6fa6a | 5144 | expressionS exp; |
b99bd4ef | 5145 | |
dcbf9037 | 5146 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
5147 | { |
5148 | inst.operands[i].reg = value; | |
5149 | inst.operands[i].isreg = 1; | |
b99bd4ef | 5150 | |
c19d1205 ZW |
5151 | /* parse_shift will override this if appropriate */ |
5152 | inst.reloc.exp.X_op = O_constant; | |
5153 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 5154 | |
c19d1205 ZW |
5155 | if (skip_past_comma (str) == FAIL) |
5156 | return SUCCESS; | |
b99bd4ef | 5157 | |
c19d1205 ZW |
5158 | /* Shift operation on register. */ |
5159 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
5160 | } |
5161 | ||
c19d1205 ZW |
5162 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
5163 | return FAIL; | |
b99bd4ef | 5164 | |
c19d1205 | 5165 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 5166 | { |
c19d1205 | 5167 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 5168 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 5169 | return FAIL; |
b99bd4ef | 5170 | |
91d6fa6a | 5171 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
5172 | { |
5173 | inst.error = _("constant expression expected"); | |
5174 | return FAIL; | |
5175 | } | |
b99bd4ef | 5176 | |
91d6fa6a | 5177 | value = exp.X_add_number; |
c19d1205 ZW |
5178 | if (value < 0 || value > 30 || value % 2 != 0) |
5179 | { | |
5180 | inst.error = _("invalid rotation"); | |
5181 | return FAIL; | |
5182 | } | |
5183 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
5184 | { | |
5185 | inst.error = _("invalid constant"); | |
5186 | return FAIL; | |
5187 | } | |
09d92015 | 5188 | |
a415b1cd JB |
5189 | /* Encode as specified. */ |
5190 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
5191 | return SUCCESS; | |
09d92015 MM |
5192 | } |
5193 | ||
c19d1205 ZW |
5194 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
5195 | inst.reloc.pc_rel = 0; | |
5196 | return SUCCESS; | |
09d92015 MM |
5197 | } |
5198 | ||
4962c51a MS |
5199 | /* Group relocation information. Each entry in the table contains the |
5200 | textual name of the relocation as may appear in assembler source | |
5201 | and must end with a colon. | |
5202 | Along with this textual name are the relocation codes to be used if | |
5203 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
5204 | an LDR, an LDRS, or an LDC. */ | |
5205 | ||
5206 | struct group_reloc_table_entry | |
5207 | { | |
5208 | const char *name; | |
5209 | int alu_code; | |
5210 | int ldr_code; | |
5211 | int ldrs_code; | |
5212 | int ldc_code; | |
5213 | }; | |
5214 | ||
5215 | typedef enum | |
5216 | { | |
5217 | /* Varieties of non-ALU group relocation. */ | |
5218 | ||
5219 | GROUP_LDR, | |
5220 | GROUP_LDRS, | |
5221 | GROUP_LDC | |
5222 | } group_reloc_type; | |
5223 | ||
5224 | static struct group_reloc_table_entry group_reloc_table[] = | |
5225 | { /* Program counter relative: */ | |
5226 | { "pc_g0_nc", | |
5227 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
5228 | 0, /* LDR */ | |
5229 | 0, /* LDRS */ | |
5230 | 0 }, /* LDC */ | |
5231 | { "pc_g0", | |
5232 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
5233 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
5234 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
5235 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
5236 | { "pc_g1_nc", | |
5237 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
5238 | 0, /* LDR */ | |
5239 | 0, /* LDRS */ | |
5240 | 0 }, /* LDC */ | |
5241 | { "pc_g1", | |
5242 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
5243 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
5244 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
5245 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
5246 | { "pc_g2", | |
5247 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
5248 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
5249 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
5250 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
5251 | /* Section base relative */ | |
5252 | { "sb_g0_nc", | |
5253 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
5254 | 0, /* LDR */ | |
5255 | 0, /* LDRS */ | |
5256 | 0 }, /* LDC */ | |
5257 | { "sb_g0", | |
5258 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
5259 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
5260 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
5261 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
5262 | { "sb_g1_nc", | |
5263 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
5264 | 0, /* LDR */ | |
5265 | 0, /* LDRS */ | |
5266 | 0 }, /* LDC */ | |
5267 | { "sb_g1", | |
5268 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
5269 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
5270 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
5271 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
5272 | { "sb_g2", | |
5273 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
5274 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
5275 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
5276 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
5277 | ||
5278 | /* Given the address of a pointer pointing to the textual name of a group | |
5279 | relocation as may appear in assembler source, attempt to find its details | |
5280 | in group_reloc_table. The pointer will be updated to the character after | |
5281 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5282 | otherwise. On success, *entry will be updated to point at the relevant | |
5283 | group_reloc_table entry. */ | |
5284 | ||
5285 | static int | |
5286 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5287 | { | |
5288 | unsigned int i; | |
5289 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5290 | { | |
5291 | int length = strlen (group_reloc_table[i].name); | |
5292 | ||
5f4273c7 NC |
5293 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5294 | && (*str)[length] == ':') | |
477330fc RM |
5295 | { |
5296 | *out = &group_reloc_table[i]; | |
5297 | *str += (length + 1); | |
5298 | return SUCCESS; | |
5299 | } | |
4962c51a MS |
5300 | } |
5301 | ||
5302 | return FAIL; | |
5303 | } | |
5304 | ||
5305 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5306 | (as for parse_shifter_operand) where group relocations are allowed: | |
5307 | ||
5308 | #<immediate> | |
5309 | #<immediate>, <rotate> | |
5310 | #:<group_reloc>:<expression> | |
5311 | <Rm> | |
5312 | <Rm>, <shift> | |
5313 | ||
5314 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5315 | The hashes are optional. | |
5316 | ||
5317 | Everything else is as for parse_shifter_operand. */ | |
5318 | ||
5319 | static parse_operand_result | |
5320 | parse_shifter_operand_group_reloc (char **str, int i) | |
5321 | { | |
5322 | /* Determine if we have the sequence of characters #: or just : | |
5323 | coming next. If we do, then we check for a group relocation. | |
5324 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5325 | ||
5326 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5327 | || (*str)[0] == ':') | |
5328 | { | |
5329 | struct group_reloc_table_entry *entry; | |
5330 | ||
5331 | if ((*str)[0] == '#') | |
477330fc | 5332 | (*str) += 2; |
4962c51a | 5333 | else |
477330fc | 5334 | (*str)++; |
4962c51a MS |
5335 | |
5336 | /* Try to parse a group relocation. Anything else is an error. */ | |
5337 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
477330fc RM |
5338 | { |
5339 | inst.error = _("unknown group relocation"); | |
5340 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5341 | } | |
4962c51a MS |
5342 | |
5343 | /* We now have the group relocation table entry corresponding to | |
477330fc | 5344 | the name in the assembler source. Next, we parse the expression. */ |
4962c51a | 5345 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) |
477330fc | 5346 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; |
4962c51a MS |
5347 | |
5348 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5349 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5350 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5351 | |
5352 | return PARSE_OPERAND_SUCCESS; | |
5353 | } | |
5354 | else | |
5355 | return parse_shifter_operand (str, i) == SUCCESS | |
477330fc | 5356 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; |
4962c51a MS |
5357 | |
5358 | /* Never reached. */ | |
5359 | } | |
5360 | ||
8e560766 MGD |
5361 | /* Parse a Neon alignment expression. Information is written to |
5362 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5363 | |
8e560766 MGD |
5364 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5365 | static parse_operand_result | |
5366 | parse_neon_alignment (char **str, int i) | |
5367 | { | |
5368 | char *p = *str; | |
5369 | expressionS exp; | |
5370 | ||
5371 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5372 | ||
5373 | if (exp.X_op != O_constant) | |
5374 | { | |
5375 | inst.error = _("alignment must be constant"); | |
5376 | return PARSE_OPERAND_FAIL; | |
5377 | } | |
5378 | ||
5379 | inst.operands[i].imm = exp.X_add_number << 8; | |
5380 | inst.operands[i].immisalign = 1; | |
5381 | /* Alignments are not pre-indexes. */ | |
5382 | inst.operands[i].preind = 0; | |
5383 | ||
5384 | *str = p; | |
5385 | return PARSE_OPERAND_SUCCESS; | |
5386 | } | |
5387 | ||
c19d1205 ZW |
5388 | /* Parse all forms of an ARM address expression. Information is written |
5389 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5390 | |
c19d1205 | 5391 | Preindexed addressing (.preind=1): |
09d92015 | 5392 | |
c19d1205 ZW |
5393 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5394 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5395 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5396 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5397 | |
c19d1205 | 5398 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5399 | |
c19d1205 | 5400 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5401 | |
c19d1205 ZW |
5402 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5403 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5404 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5405 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5406 | |
c19d1205 | 5407 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5408 | |
c19d1205 | 5409 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5410 | |
c19d1205 | 5411 | Other: |
09d92015 | 5412 | |
c19d1205 ZW |
5413 | [Rn]{!} shorthand for [Rn,#0]{!} |
5414 | =immediate .isreg=0 .reloc.exp=immediate | |
5415 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5416 | |
c19d1205 ZW |
5417 | It is the caller's responsibility to check for addressing modes not |
5418 | supported by the instruction, and to set inst.reloc.type. */ | |
5419 | ||
4962c51a MS |
5420 | static parse_operand_result |
5421 | parse_address_main (char **str, int i, int group_relocations, | |
477330fc | 5422 | group_reloc_type group_type) |
09d92015 | 5423 | { |
c19d1205 ZW |
5424 | char *p = *str; |
5425 | int reg; | |
09d92015 | 5426 | |
c19d1205 | 5427 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5428 | { |
c19d1205 ZW |
5429 | if (skip_past_char (&p, '=') == FAIL) |
5430 | { | |
974da60d | 5431 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5432 | inst.reloc.pc_rel = 1; |
5433 | inst.operands[i].reg = REG_PC; | |
5434 | inst.operands[i].isreg = 1; | |
5435 | inst.operands[i].preind = 1; | |
09d92015 | 5436 | |
8335d6aa JW |
5437 | if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG)) |
5438 | return PARSE_OPERAND_FAIL; | |
5439 | } | |
5440 | else if (parse_big_immediate (&p, i, &inst.reloc.exp, | |
5441 | /*allow_symbol_p=*/TRUE)) | |
4962c51a | 5442 | return PARSE_OPERAND_FAIL; |
09d92015 | 5443 | |
c19d1205 | 5444 | *str = p; |
4962c51a | 5445 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5446 | } |
5447 | ||
8ab8155f NC |
5448 | /* PR gas/14887: Allow for whitespace after the opening bracket. */ |
5449 | skip_whitespace (p); | |
5450 | ||
dcbf9037 | 5451 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5452 | { |
c19d1205 | 5453 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5454 | return PARSE_OPERAND_FAIL; |
09d92015 | 5455 | } |
c19d1205 ZW |
5456 | inst.operands[i].reg = reg; |
5457 | inst.operands[i].isreg = 1; | |
09d92015 | 5458 | |
c19d1205 | 5459 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5460 | { |
c19d1205 | 5461 | inst.operands[i].preind = 1; |
09d92015 | 5462 | |
c19d1205 ZW |
5463 | if (*p == '+') p++; |
5464 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5465 | ||
dcbf9037 | 5466 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5467 | { |
c19d1205 ZW |
5468 | inst.operands[i].imm = reg; |
5469 | inst.operands[i].immisreg = 1; | |
5470 | ||
5471 | if (skip_past_comma (&p) == SUCCESS) | |
5472 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5473 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5474 | } |
5287ad62 | 5475 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5476 | { |
5477 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5478 | code before we get to see it here. This may be subject to | |
5479 | change. */ | |
5480 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5481 | |
8e560766 MGD |
5482 | if (result != PARSE_OPERAND_SUCCESS) |
5483 | return result; | |
5484 | } | |
c19d1205 ZW |
5485 | else |
5486 | { | |
5487 | if (inst.operands[i].negative) | |
5488 | { | |
5489 | inst.operands[i].negative = 0; | |
5490 | p--; | |
5491 | } | |
4962c51a | 5492 | |
5f4273c7 NC |
5493 | if (group_relocations |
5494 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5495 | { |
5496 | struct group_reloc_table_entry *entry; | |
5497 | ||
477330fc RM |
5498 | /* Skip over the #: or : sequence. */ |
5499 | if (*p == '#') | |
5500 | p += 2; | |
5501 | else | |
5502 | p++; | |
4962c51a MS |
5503 | |
5504 | /* Try to parse a group relocation. Anything else is an | |
477330fc | 5505 | error. */ |
4962c51a MS |
5506 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) |
5507 | { | |
5508 | inst.error = _("unknown group relocation"); | |
5509 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5510 | } | |
5511 | ||
5512 | /* We now have the group relocation table entry corresponding to | |
5513 | the name in the assembler source. Next, we parse the | |
477330fc | 5514 | expression. */ |
4962c51a MS |
5515 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
5516 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5517 | ||
5518 | /* Record the relocation type. */ | |
477330fc RM |
5519 | switch (group_type) |
5520 | { | |
5521 | case GROUP_LDR: | |
5522 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; | |
5523 | break; | |
4962c51a | 5524 | |
477330fc RM |
5525 | case GROUP_LDRS: |
5526 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; | |
5527 | break; | |
4962c51a | 5528 | |
477330fc RM |
5529 | case GROUP_LDC: |
5530 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; | |
5531 | break; | |
4962c51a | 5532 | |
477330fc RM |
5533 | default: |
5534 | gas_assert (0); | |
5535 | } | |
4962c51a | 5536 | |
477330fc | 5537 | if (inst.reloc.type == 0) |
4962c51a MS |
5538 | { |
5539 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5540 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5541 | } | |
477330fc RM |
5542 | } |
5543 | else | |
26d97720 NS |
5544 | { |
5545 | char *q = p; | |
5546 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5547 | return PARSE_OPERAND_FAIL; | |
5548 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5549 | if (inst.reloc.exp.X_op == O_constant | |
5550 | && inst.reloc.exp.X_add_number == 0) | |
5551 | { | |
5552 | skip_whitespace (q); | |
5553 | if (*q == '#') | |
5554 | { | |
5555 | q++; | |
5556 | skip_whitespace (q); | |
5557 | } | |
5558 | if (*q == '-') | |
5559 | inst.operands[i].negative = 1; | |
5560 | } | |
5561 | } | |
09d92015 MM |
5562 | } |
5563 | } | |
8e560766 MGD |
5564 | else if (skip_past_char (&p, ':') == SUCCESS) |
5565 | { | |
5566 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5567 | before we get to see it here. This may be subject to change. */ | |
5568 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5569 | |
8e560766 MGD |
5570 | if (result != PARSE_OPERAND_SUCCESS) |
5571 | return result; | |
5572 | } | |
09d92015 | 5573 | |
c19d1205 | 5574 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5575 | { |
c19d1205 | 5576 | inst.error = _("']' expected"); |
4962c51a | 5577 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5578 | } |
5579 | ||
c19d1205 ZW |
5580 | if (skip_past_char (&p, '!') == SUCCESS) |
5581 | inst.operands[i].writeback = 1; | |
09d92015 | 5582 | |
c19d1205 | 5583 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5584 | { |
c19d1205 ZW |
5585 | if (skip_past_char (&p, '{') == SUCCESS) |
5586 | { | |
5587 | /* [Rn], {expr} - unindexed, with option */ | |
5588 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5589 | 0, 255, TRUE) == FAIL) |
4962c51a | 5590 | return PARSE_OPERAND_FAIL; |
09d92015 | 5591 | |
c19d1205 ZW |
5592 | if (skip_past_char (&p, '}') == FAIL) |
5593 | { | |
5594 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5595 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5596 | } |
5597 | if (inst.operands[i].preind) | |
5598 | { | |
5599 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5600 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5601 | } |
5602 | *str = p; | |
4962c51a | 5603 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5604 | } |
c19d1205 ZW |
5605 | else |
5606 | { | |
5607 | inst.operands[i].postind = 1; | |
5608 | inst.operands[i].writeback = 1; | |
09d92015 | 5609 | |
c19d1205 ZW |
5610 | if (inst.operands[i].preind) |
5611 | { | |
5612 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5613 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5614 | } |
09d92015 | 5615 | |
c19d1205 ZW |
5616 | if (*p == '+') p++; |
5617 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5618 | |
dcbf9037 | 5619 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5620 | { |
477330fc RM |
5621 | /* We might be using the immediate for alignment already. If we |
5622 | are, OR the register number into the low-order bits. */ | |
5623 | if (inst.operands[i].immisalign) | |
5624 | inst.operands[i].imm |= reg; | |
5625 | else | |
5626 | inst.operands[i].imm = reg; | |
c19d1205 | 5627 | inst.operands[i].immisreg = 1; |
a737bd4d | 5628 | |
c19d1205 ZW |
5629 | if (skip_past_comma (&p) == SUCCESS) |
5630 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5631 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5632 | } |
5633 | else | |
5634 | { | |
26d97720 | 5635 | char *q = p; |
c19d1205 ZW |
5636 | if (inst.operands[i].negative) |
5637 | { | |
5638 | inst.operands[i].negative = 0; | |
5639 | p--; | |
5640 | } | |
5641 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5642 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5643 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5644 | if (inst.reloc.exp.X_op == O_constant | |
5645 | && inst.reloc.exp.X_add_number == 0) | |
5646 | { | |
5647 | skip_whitespace (q); | |
5648 | if (*q == '#') | |
5649 | { | |
5650 | q++; | |
5651 | skip_whitespace (q); | |
5652 | } | |
5653 | if (*q == '-') | |
5654 | inst.operands[i].negative = 1; | |
5655 | } | |
c19d1205 ZW |
5656 | } |
5657 | } | |
a737bd4d NC |
5658 | } |
5659 | ||
c19d1205 ZW |
5660 | /* If at this point neither .preind nor .postind is set, we have a |
5661 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5662 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5663 | { | |
5664 | inst.operands[i].preind = 1; | |
5665 | inst.reloc.exp.X_op = O_constant; | |
5666 | inst.reloc.exp.X_add_number = 0; | |
5667 | } | |
5668 | *str = p; | |
4962c51a MS |
5669 | return PARSE_OPERAND_SUCCESS; |
5670 | } | |
5671 | ||
5672 | static int | |
5673 | parse_address (char **str, int i) | |
5674 | { | |
21d799b5 | 5675 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
477330fc | 5676 | ? SUCCESS : FAIL; |
4962c51a MS |
5677 | } |
5678 | ||
5679 | static parse_operand_result | |
5680 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5681 | { | |
5682 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5683 | } |
5684 | ||
b6895b4f PB |
5685 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5686 | static int | |
5687 | parse_half (char **str) | |
5688 | { | |
5689 | char * p; | |
5f4273c7 | 5690 | |
b6895b4f PB |
5691 | p = *str; |
5692 | skip_past_char (&p, '#'); | |
5f4273c7 | 5693 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5694 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5695 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5696 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5697 | ||
5698 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5699 | { | |
5700 | p += 9; | |
5f4273c7 | 5701 | skip_whitespace (p); |
b6895b4f PB |
5702 | } |
5703 | ||
5704 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5705 | return FAIL; | |
5706 | ||
5707 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5708 | { | |
5709 | if (inst.reloc.exp.X_op != O_constant) | |
5710 | { | |
5711 | inst.error = _("constant expression expected"); | |
5712 | return FAIL; | |
5713 | } | |
5714 | if (inst.reloc.exp.X_add_number < 0 | |
5715 | || inst.reloc.exp.X_add_number > 0xffff) | |
5716 | { | |
5717 | inst.error = _("immediate value out of range"); | |
5718 | return FAIL; | |
5719 | } | |
5720 | } | |
5721 | *str = p; | |
5722 | return SUCCESS; | |
5723 | } | |
5724 | ||
c19d1205 | 5725 | /* Miscellaneous. */ |
a737bd4d | 5726 | |
c19d1205 ZW |
5727 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5728 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5729 | static int | |
d2cd1205 | 5730 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5731 | { |
c19d1205 ZW |
5732 | char *p; |
5733 | unsigned long psr_field; | |
62b3e311 PB |
5734 | const struct asm_psr *psr; |
5735 | char *start; | |
d2cd1205 | 5736 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5737 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5738 | |
a4482bb6 NC |
5739 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5740 | be TRUE, but we want to ignore it in this case as we are building for any | |
5741 | CPU type, including non-m variants. */ | |
823d2571 | 5742 | if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any)) |
a4482bb6 NC |
5743 | m_profile = FALSE; |
5744 | ||
c19d1205 ZW |
5745 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5746 | feature for ease of use and backwards compatibility. */ | |
5747 | p = *str; | |
62b3e311 | 5748 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5749 | { |
5750 | if (m_profile) | |
5751 | goto unsupported_psr; | |
fa94de6b | 5752 | |
d2cd1205 JB |
5753 | psr_field = SPSR_BIT; |
5754 | } | |
5755 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5756 | { | |
5757 | if (m_profile) | |
5758 | goto unsupported_psr; | |
5759 | ||
5760 | psr_field = 0; | |
5761 | } | |
5762 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5763 | { | |
5764 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5765 | and ARMv7-R architecture CPUs. */ | |
5766 | is_apsr = TRUE; | |
5767 | psr_field = 0; | |
5768 | } | |
5769 | else if (m_profile) | |
62b3e311 PB |
5770 | { |
5771 | start = p; | |
5772 | do | |
5773 | p++; | |
5774 | while (ISALNUM (*p) || *p == '_'); | |
5775 | ||
d2cd1205 JB |
5776 | if (strncasecmp (start, "iapsr", 5) == 0 |
5777 | || strncasecmp (start, "eapsr", 5) == 0 | |
5778 | || strncasecmp (start, "xpsr", 4) == 0 | |
5779 | || strncasecmp (start, "psr", 3) == 0) | |
5780 | p = start + strcspn (start, "rR") + 1; | |
5781 | ||
21d799b5 | 5782 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
477330fc | 5783 | p - start); |
d2cd1205 | 5784 | |
62b3e311 PB |
5785 | if (!psr) |
5786 | return FAIL; | |
09d92015 | 5787 | |
d2cd1205 JB |
5788 | /* If APSR is being written, a bitfield may be specified. Note that |
5789 | APSR itself is handled above. */ | |
5790 | if (psr->field <= 3) | |
5791 | { | |
5792 | psr_field = psr->field; | |
5793 | is_apsr = TRUE; | |
5794 | goto check_suffix; | |
5795 | } | |
5796 | ||
62b3e311 | 5797 | *str = p; |
d2cd1205 JB |
5798 | /* M-profile MSR instructions have the mask field set to "10", except |
5799 | *PSR variants which modify APSR, which may use a different mask (and | |
5800 | have been handled already). Do that by setting the PSR_f field | |
5801 | here. */ | |
5802 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5803 | } |
d2cd1205 JB |
5804 | else |
5805 | goto unsupported_psr; | |
09d92015 | 5806 | |
62b3e311 | 5807 | p += 4; |
d2cd1205 | 5808 | check_suffix: |
c19d1205 ZW |
5809 | if (*p == '_') |
5810 | { | |
5811 | /* A suffix follows. */ | |
c19d1205 ZW |
5812 | p++; |
5813 | start = p; | |
a737bd4d | 5814 | |
c19d1205 ZW |
5815 | do |
5816 | p++; | |
5817 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5818 | |
d2cd1205 JB |
5819 | if (is_apsr) |
5820 | { | |
5821 | /* APSR uses a notation for bits, rather than fields. */ | |
5822 | unsigned int nzcvq_bits = 0; | |
5823 | unsigned int g_bit = 0; | |
5824 | char *bit; | |
fa94de6b | 5825 | |
d2cd1205 JB |
5826 | for (bit = start; bit != p; bit++) |
5827 | { | |
5828 | switch (TOLOWER (*bit)) | |
477330fc | 5829 | { |
d2cd1205 JB |
5830 | case 'n': |
5831 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5832 | break; | |
5833 | ||
5834 | case 'z': | |
5835 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5836 | break; | |
5837 | ||
5838 | case 'c': | |
5839 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5840 | break; | |
5841 | ||
5842 | case 'v': | |
5843 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5844 | break; | |
fa94de6b | 5845 | |
d2cd1205 JB |
5846 | case 'q': |
5847 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5848 | break; | |
fa94de6b | 5849 | |
d2cd1205 JB |
5850 | case 'g': |
5851 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5852 | break; | |
fa94de6b | 5853 | |
d2cd1205 JB |
5854 | default: |
5855 | inst.error = _("unexpected bit specified after APSR"); | |
5856 | return FAIL; | |
5857 | } | |
5858 | } | |
fa94de6b | 5859 | |
d2cd1205 JB |
5860 | if (nzcvq_bits == 0x1f) |
5861 | psr_field |= PSR_f; | |
fa94de6b | 5862 | |
d2cd1205 JB |
5863 | if (g_bit == 0x1) |
5864 | { | |
5865 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
477330fc | 5866 | { |
d2cd1205 JB |
5867 | inst.error = _("selected processor does not " |
5868 | "support DSP extension"); | |
5869 | return FAIL; | |
5870 | } | |
5871 | ||
5872 | psr_field |= PSR_s; | |
5873 | } | |
fa94de6b | 5874 | |
d2cd1205 JB |
5875 | if ((nzcvq_bits & 0x20) != 0 |
5876 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5877 | || (g_bit & 0x2) != 0) | |
5878 | { | |
5879 | inst.error = _("bad bitmask specified after APSR"); | |
5880 | return FAIL; | |
5881 | } | |
5882 | } | |
5883 | else | |
477330fc | 5884 | { |
d2cd1205 | 5885 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, |
477330fc | 5886 | p - start); |
d2cd1205 | 5887 | if (!psr) |
477330fc | 5888 | goto error; |
a737bd4d | 5889 | |
d2cd1205 JB |
5890 | psr_field |= psr->field; |
5891 | } | |
a737bd4d | 5892 | } |
c19d1205 | 5893 | else |
a737bd4d | 5894 | { |
c19d1205 ZW |
5895 | if (ISALNUM (*p)) |
5896 | goto error; /* Garbage after "[CS]PSR". */ | |
5897 | ||
d2cd1205 | 5898 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
477330fc | 5899 | is deprecated, but allow it anyway. */ |
d2cd1205 JB |
5900 | if (is_apsr && lhs) |
5901 | { | |
5902 | psr_field |= PSR_f; | |
5903 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5904 | "deprecated")); | |
5905 | } | |
5906 | else if (!m_profile) | |
5907 | /* These bits are never right for M-profile devices: don't set them | |
5908 | (only code paths which read/write APSR reach here). */ | |
5909 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5910 | } |
c19d1205 ZW |
5911 | *str = p; |
5912 | return psr_field; | |
a737bd4d | 5913 | |
d2cd1205 JB |
5914 | unsupported_psr: |
5915 | inst.error = _("selected processor does not support requested special " | |
5916 | "purpose register"); | |
5917 | return FAIL; | |
5918 | ||
c19d1205 ZW |
5919 | error: |
5920 | inst.error = _("flag for {c}psr instruction expected"); | |
5921 | return FAIL; | |
a737bd4d NC |
5922 | } |
5923 | ||
c19d1205 ZW |
5924 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5925 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5926 | |
c19d1205 ZW |
5927 | static int |
5928 | parse_cps_flags (char **str) | |
a737bd4d | 5929 | { |
c19d1205 ZW |
5930 | int val = 0; |
5931 | int saw_a_flag = 0; | |
5932 | char *s = *str; | |
a737bd4d | 5933 | |
c19d1205 ZW |
5934 | for (;;) |
5935 | switch (*s++) | |
5936 | { | |
5937 | case '\0': case ',': | |
5938 | goto done; | |
a737bd4d | 5939 | |
c19d1205 ZW |
5940 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5941 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5942 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5943 | |
c19d1205 ZW |
5944 | default: |
5945 | inst.error = _("unrecognized CPS flag"); | |
5946 | return FAIL; | |
5947 | } | |
a737bd4d | 5948 | |
c19d1205 ZW |
5949 | done: |
5950 | if (saw_a_flag == 0) | |
a737bd4d | 5951 | { |
c19d1205 ZW |
5952 | inst.error = _("missing CPS flags"); |
5953 | return FAIL; | |
a737bd4d | 5954 | } |
a737bd4d | 5955 | |
c19d1205 ZW |
5956 | *str = s - 1; |
5957 | return val; | |
a737bd4d NC |
5958 | } |
5959 | ||
c19d1205 ZW |
5960 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5961 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5962 | |
5963 | static int | |
c19d1205 | 5964 | parse_endian_specifier (char **str) |
a737bd4d | 5965 | { |
c19d1205 ZW |
5966 | int little_endian; |
5967 | char *s = *str; | |
a737bd4d | 5968 | |
c19d1205 ZW |
5969 | if (strncasecmp (s, "BE", 2)) |
5970 | little_endian = 0; | |
5971 | else if (strncasecmp (s, "LE", 2)) | |
5972 | little_endian = 1; | |
5973 | else | |
a737bd4d | 5974 | { |
c19d1205 | 5975 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5976 | return FAIL; |
5977 | } | |
5978 | ||
c19d1205 | 5979 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5980 | { |
c19d1205 | 5981 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5982 | return FAIL; |
5983 | } | |
5984 | ||
c19d1205 ZW |
5985 | *str = s + 2; |
5986 | return little_endian; | |
5987 | } | |
a737bd4d | 5988 | |
c19d1205 ZW |
5989 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5990 | value suitable for poking into the rotate field of an sxt or sxta | |
5991 | instruction, or FAIL on error. */ | |
5992 | ||
5993 | static int | |
5994 | parse_ror (char **str) | |
5995 | { | |
5996 | int rot; | |
5997 | char *s = *str; | |
5998 | ||
5999 | if (strncasecmp (s, "ROR", 3) == 0) | |
6000 | s += 3; | |
6001 | else | |
a737bd4d | 6002 | { |
c19d1205 | 6003 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
6004 | return FAIL; |
6005 | } | |
c19d1205 ZW |
6006 | |
6007 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
6008 | return FAIL; | |
6009 | ||
6010 | switch (rot) | |
a737bd4d | 6011 | { |
c19d1205 ZW |
6012 | case 0: *str = s; return 0x0; |
6013 | case 8: *str = s; return 0x1; | |
6014 | case 16: *str = s; return 0x2; | |
6015 | case 24: *str = s; return 0x3; | |
6016 | ||
6017 | default: | |
6018 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
6019 | return FAIL; |
6020 | } | |
c19d1205 | 6021 | } |
a737bd4d | 6022 | |
c19d1205 ZW |
6023 | /* Parse a conditional code (from conds[] below). The value returned is in the |
6024 | range 0 .. 14, or FAIL. */ | |
6025 | static int | |
6026 | parse_cond (char **str) | |
6027 | { | |
c462b453 | 6028 | char *q; |
c19d1205 | 6029 | const struct asm_cond *c; |
c462b453 PB |
6030 | int n; |
6031 | /* Condition codes are always 2 characters, so matching up to | |
6032 | 3 characters is sufficient. */ | |
6033 | char cond[3]; | |
a737bd4d | 6034 | |
c462b453 PB |
6035 | q = *str; |
6036 | n = 0; | |
6037 | while (ISALPHA (*q) && n < 3) | |
6038 | { | |
e07e6e58 | 6039 | cond[n] = TOLOWER (*q); |
c462b453 PB |
6040 | q++; |
6041 | n++; | |
6042 | } | |
a737bd4d | 6043 | |
21d799b5 | 6044 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 6045 | if (!c) |
a737bd4d | 6046 | { |
c19d1205 | 6047 | inst.error = _("condition required"); |
a737bd4d NC |
6048 | return FAIL; |
6049 | } | |
6050 | ||
c19d1205 ZW |
6051 | *str = q; |
6052 | return c->value; | |
6053 | } | |
6054 | ||
e797f7e0 MGD |
6055 | /* If the given feature available in the selected CPU, mark it as used. |
6056 | Returns TRUE iff feature is available. */ | |
6057 | static bfd_boolean | |
6058 | mark_feature_used (const arm_feature_set *feature) | |
6059 | { | |
6060 | /* Ensure the option is valid on the current architecture. */ | |
6061 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
6062 | return FALSE; | |
6063 | ||
6064 | /* Add the appropriate architecture feature for the barrier option used. | |
6065 | */ | |
6066 | if (thumb_mode) | |
6067 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature); | |
6068 | else | |
6069 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature); | |
6070 | ||
6071 | return TRUE; | |
6072 | } | |
6073 | ||
62b3e311 PB |
6074 | /* Parse an option for a barrier instruction. Returns the encoding for the |
6075 | option, or FAIL. */ | |
6076 | static int | |
6077 | parse_barrier (char **str) | |
6078 | { | |
6079 | char *p, *q; | |
6080 | const struct asm_barrier_opt *o; | |
6081 | ||
6082 | p = q = *str; | |
6083 | while (ISALPHA (*q)) | |
6084 | q++; | |
6085 | ||
21d799b5 | 6086 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
477330fc | 6087 | q - p); |
62b3e311 PB |
6088 | if (!o) |
6089 | return FAIL; | |
6090 | ||
e797f7e0 MGD |
6091 | if (!mark_feature_used (&o->arch)) |
6092 | return FAIL; | |
6093 | ||
62b3e311 PB |
6094 | *str = q; |
6095 | return o->value; | |
6096 | } | |
6097 | ||
92e90b6e PB |
6098 | /* Parse the operands of a table branch instruction. Similar to a memory |
6099 | operand. */ | |
6100 | static int | |
6101 | parse_tb (char **str) | |
6102 | { | |
6103 | char * p = *str; | |
6104 | int reg; | |
6105 | ||
6106 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
6107 | { |
6108 | inst.error = _("'[' expected"); | |
6109 | return FAIL; | |
6110 | } | |
92e90b6e | 6111 | |
dcbf9037 | 6112 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6113 | { |
6114 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6115 | return FAIL; | |
6116 | } | |
6117 | inst.operands[0].reg = reg; | |
6118 | ||
6119 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
6120 | { |
6121 | inst.error = _("',' expected"); | |
6122 | return FAIL; | |
6123 | } | |
5f4273c7 | 6124 | |
dcbf9037 | 6125 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
6126 | { |
6127 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
6128 | return FAIL; | |
6129 | } | |
6130 | inst.operands[0].imm = reg; | |
6131 | ||
6132 | if (skip_past_comma (&p) == SUCCESS) | |
6133 | { | |
6134 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
6135 | return FAIL; | |
6136 | if (inst.reloc.exp.X_add_number != 1) | |
6137 | { | |
6138 | inst.error = _("invalid shift"); | |
6139 | return FAIL; | |
6140 | } | |
6141 | inst.operands[0].shifted = 1; | |
6142 | } | |
6143 | ||
6144 | if (skip_past_char (&p, ']') == FAIL) | |
6145 | { | |
6146 | inst.error = _("']' expected"); | |
6147 | return FAIL; | |
6148 | } | |
6149 | *str = p; | |
6150 | return SUCCESS; | |
6151 | } | |
6152 | ||
5287ad62 JB |
6153 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
6154 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
6155 | Up to four operands may be read; this function handles setting the |
6156 | ".present" field for each read operand itself. | |
5287ad62 JB |
6157 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
6158 | else returns FAIL. */ | |
6159 | ||
6160 | static int | |
6161 | parse_neon_mov (char **str, int *which_operand) | |
6162 | { | |
6163 | int i = *which_operand, val; | |
6164 | enum arm_reg_type rtype; | |
6165 | char *ptr = *str; | |
dcbf9037 | 6166 | struct neon_type_el optype; |
5f4273c7 | 6167 | |
dcbf9037 | 6168 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
6169 | { |
6170 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
6171 | inst.operands[i].reg = val; | |
6172 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 6173 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6174 | inst.operands[i++].present = 1; |
6175 | ||
6176 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6177 | goto wanted_comma; |
5f4273c7 | 6178 | |
dcbf9037 | 6179 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
477330fc | 6180 | goto wanted_arm; |
5f4273c7 | 6181 | |
5287ad62 JB |
6182 | inst.operands[i].reg = val; |
6183 | inst.operands[i].isreg = 1; | |
6184 | inst.operands[i].present = 1; | |
6185 | } | |
037e8744 | 6186 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
477330fc | 6187 | != FAIL) |
5287ad62 JB |
6188 | { |
6189 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
6190 | if (skip_past_comma (&ptr) == FAIL) | |
477330fc | 6191 | goto wanted_comma; |
5f4273c7 | 6192 | |
5287ad62 JB |
6193 | inst.operands[i].reg = val; |
6194 | inst.operands[i].isreg = 1; | |
6195 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
6196 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
6197 | inst.operands[i].isvec = 1; | |
dcbf9037 | 6198 | inst.operands[i].vectype = optype; |
5287ad62 JB |
6199 | inst.operands[i++].present = 1; |
6200 | ||
dcbf9037 | 6201 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6202 | { |
6203 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. | |
6204 | Case 13: VMOV <Sd>, <Rm> */ | |
6205 | inst.operands[i].reg = val; | |
6206 | inst.operands[i].isreg = 1; | |
6207 | inst.operands[i].present = 1; | |
6208 | ||
6209 | if (rtype == REG_TYPE_NQ) | |
6210 | { | |
6211 | first_error (_("can't use Neon quad register here")); | |
6212 | return FAIL; | |
6213 | } | |
6214 | else if (rtype != REG_TYPE_VFS) | |
6215 | { | |
6216 | i++; | |
6217 | if (skip_past_comma (&ptr) == FAIL) | |
6218 | goto wanted_comma; | |
6219 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6220 | goto wanted_arm; | |
6221 | inst.operands[i].reg = val; | |
6222 | inst.operands[i].isreg = 1; | |
6223 | inst.operands[i].present = 1; | |
6224 | } | |
6225 | } | |
037e8744 | 6226 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
477330fc RM |
6227 | &optype)) != FAIL) |
6228 | { | |
6229 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
6230 | Case 1: VMOV<c><q> <Dd>, <Dm> | |
6231 | Case 8: VMOV.F32 <Sd>, <Sm> | |
6232 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
6233 | ||
6234 | inst.operands[i].reg = val; | |
6235 | inst.operands[i].isreg = 1; | |
6236 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
6237 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6238 | inst.operands[i].isvec = 1; | |
6239 | inst.operands[i].vectype = optype; | |
6240 | inst.operands[i].present = 1; | |
6241 | ||
6242 | if (skip_past_comma (&ptr) == SUCCESS) | |
6243 | { | |
6244 | /* Case 15. */ | |
6245 | i++; | |
6246 | ||
6247 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6248 | goto wanted_arm; | |
6249 | ||
6250 | inst.operands[i].reg = val; | |
6251 | inst.operands[i].isreg = 1; | |
6252 | inst.operands[i++].present = 1; | |
6253 | ||
6254 | if (skip_past_comma (&ptr) == FAIL) | |
6255 | goto wanted_comma; | |
6256 | ||
6257 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
6258 | goto wanted_arm; | |
6259 | ||
6260 | inst.operands[i].reg = val; | |
6261 | inst.operands[i].isreg = 1; | |
6262 | inst.operands[i].present = 1; | |
6263 | } | |
6264 | } | |
4641781c | 6265 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
477330fc RM |
6266 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> |
6267 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
6268 | Case 10: VMOV.F32 <Sd>, #<imm> | |
6269 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
6270 | inst.operands[i].immisfloat = 1; | |
8335d6aa JW |
6271 | else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) |
6272 | == SUCCESS) | |
477330fc RM |
6273 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> |
6274 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
6275 | ; | |
5287ad62 | 6276 | else |
477330fc RM |
6277 | { |
6278 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); | |
6279 | return FAIL; | |
6280 | } | |
5287ad62 | 6281 | } |
dcbf9037 | 6282 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
6283 | { |
6284 | /* Cases 6, 7. */ | |
6285 | inst.operands[i].reg = val; | |
6286 | inst.operands[i].isreg = 1; | |
6287 | inst.operands[i++].present = 1; | |
5f4273c7 | 6288 | |
5287ad62 | 6289 | if (skip_past_comma (&ptr) == FAIL) |
477330fc | 6290 | goto wanted_comma; |
5f4273c7 | 6291 | |
dcbf9037 | 6292 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
477330fc RM |
6293 | { |
6294 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
6295 | inst.operands[i].reg = val; | |
6296 | inst.operands[i].isscalar = 1; | |
6297 | inst.operands[i].present = 1; | |
6298 | inst.operands[i].vectype = optype; | |
6299 | } | |
dcbf9037 | 6300 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
477330fc RM |
6301 | { |
6302 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
6303 | inst.operands[i].reg = val; | |
6304 | inst.operands[i].isreg = 1; | |
6305 | inst.operands[i++].present = 1; | |
6306 | ||
6307 | if (skip_past_comma (&ptr) == FAIL) | |
6308 | goto wanted_comma; | |
6309 | ||
6310 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) | |
6311 | == FAIL) | |
6312 | { | |
6313 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); | |
6314 | return FAIL; | |
6315 | } | |
6316 | ||
6317 | inst.operands[i].reg = val; | |
6318 | inst.operands[i].isreg = 1; | |
6319 | inst.operands[i].isvec = 1; | |
6320 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
6321 | inst.operands[i].vectype = optype; | |
6322 | inst.operands[i].present = 1; | |
6323 | ||
6324 | if (rtype == REG_TYPE_VFS) | |
6325 | { | |
6326 | /* Case 14. */ | |
6327 | i++; | |
6328 | if (skip_past_comma (&ptr) == FAIL) | |
6329 | goto wanted_comma; | |
6330 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6331 | &optype)) == FAIL) | |
6332 | { | |
6333 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6334 | return FAIL; | |
6335 | } | |
6336 | inst.operands[i].reg = val; | |
6337 | inst.operands[i].isreg = 1; | |
6338 | inst.operands[i].isvec = 1; | |
6339 | inst.operands[i].issingle = 1; | |
6340 | inst.operands[i].vectype = optype; | |
6341 | inst.operands[i].present = 1; | |
6342 | } | |
6343 | } | |
037e8744 | 6344 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) |
477330fc RM |
6345 | != FAIL) |
6346 | { | |
6347 | /* Case 13. */ | |
6348 | inst.operands[i].reg = val; | |
6349 | inst.operands[i].isreg = 1; | |
6350 | inst.operands[i].isvec = 1; | |
6351 | inst.operands[i].issingle = 1; | |
6352 | inst.operands[i].vectype = optype; | |
6353 | inst.operands[i].present = 1; | |
6354 | } | |
5287ad62 JB |
6355 | } |
6356 | else | |
6357 | { | |
dcbf9037 | 6358 | first_error (_("parse error")); |
5287ad62 JB |
6359 | return FAIL; |
6360 | } | |
6361 | ||
6362 | /* Successfully parsed the operands. Update args. */ | |
6363 | *which_operand = i; | |
6364 | *str = ptr; | |
6365 | return SUCCESS; | |
6366 | ||
5f4273c7 | 6367 | wanted_comma: |
dcbf9037 | 6368 | first_error (_("expected comma")); |
5287ad62 | 6369 | return FAIL; |
5f4273c7 NC |
6370 | |
6371 | wanted_arm: | |
dcbf9037 | 6372 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6373 | return FAIL; |
5287ad62 JB |
6374 | } |
6375 | ||
5be8be5d DG |
6376 | /* Use this macro when the operand constraints are different |
6377 | for ARM and THUMB (e.g. ldrd). */ | |
6378 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6379 | ((arm_operand) | ((thumb_operand) << 16)) | |
6380 | ||
c19d1205 ZW |
6381 | /* Matcher codes for parse_operands. */ |
6382 | enum operand_parse_code | |
6383 | { | |
6384 | OP_stop, /* end of line */ | |
6385 | ||
6386 | OP_RR, /* ARM register */ | |
6387 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6388 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6389 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6390 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6391 | optional trailing ! */ |
c19d1205 ZW |
6392 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6393 | OP_RCP, /* Coprocessor number */ | |
6394 | OP_RCN, /* Coprocessor register */ | |
6395 | OP_RF, /* FPA register */ | |
6396 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6397 | OP_RVD, /* VFP double precision register (0..15) */ |
6398 | OP_RND, /* Neon double precision register (0..31) */ | |
6399 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6400 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6401 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6402 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6403 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6404 | OP_RVC, /* VFP control register */ |
6405 | OP_RMF, /* Maverick F register */ | |
6406 | OP_RMD, /* Maverick D register */ | |
6407 | OP_RMFX, /* Maverick FX register */ | |
6408 | OP_RMDX, /* Maverick DX register */ | |
6409 | OP_RMAX, /* Maverick AX register */ | |
6410 | OP_RMDS, /* Maverick DSPSC register */ | |
6411 | OP_RIWR, /* iWMMXt wR register */ | |
6412 | OP_RIWC, /* iWMMXt wC register */ | |
6413 | OP_RIWG, /* iWMMXt wCG register */ | |
6414 | OP_RXA, /* XScale accumulator register */ | |
6415 | ||
6416 | OP_REGLST, /* ARM register list */ | |
6417 | OP_VRSLST, /* VFP single-precision register list */ | |
6418 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6419 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6420 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6421 | OP_NSTRLST, /* Neon element/structure list */ | |
6422 | ||
5287ad62 | 6423 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6424 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
aacf0b33 | 6425 | OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */ |
5287ad62 | 6426 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6427 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6428 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6429 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6430 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6431 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6432 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6433 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6434 | |
6435 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6436 | OP_I7, /* immediate value 0 .. 7 */ |
6437 | OP_I15, /* 0 .. 15 */ | |
6438 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6439 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6440 | OP_I31, /* 0 .. 31 */ |
6441 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6442 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6443 | OP_I32z, /* 0 .. 32 */ |
6444 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6445 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6446 | OP_I64, /* 1 .. 64 */ |
6447 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6448 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6449 | |
6450 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6451 | OP_I7b, /* 0 .. 7 */ | |
6452 | OP_I15b, /* 0 .. 15 */ | |
6453 | OP_I31b, /* 0 .. 31 */ | |
6454 | ||
6455 | OP_SH, /* shifter operand */ | |
4962c51a | 6456 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6457 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6458 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6459 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6460 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6461 | OP_EXP, /* arbitrary expression */ |
6462 | OP_EXPi, /* same, with optional immediate prefix */ | |
6463 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6464 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6465 | |
6466 | OP_CPSF, /* CPS flags */ | |
6467 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6468 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6469 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6470 | OP_COND, /* conditional code */ |
92e90b6e | 6471 | OP_TB, /* Table branch. */ |
c19d1205 | 6472 | |
037e8744 JB |
6473 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6474 | ||
c19d1205 ZW |
6475 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6476 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6477 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6478 | OP_RF_IF, /* FPA register or immediate */ | |
6479 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6480 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6481 | |
6482 | /* Optional operands. */ | |
6483 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6484 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6485 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6486 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6487 | OP_oIffffb, /* 0 .. 65535 */ |
6488 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6489 | ||
6490 | OP_oRR, /* ARM register */ | |
6491 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6492 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6493 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6494 | OP_oRND, /* Optional Neon double precision register */ |
6495 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6496 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6497 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6498 | OP_oSHll, /* LSL immediate */ |
6499 | OP_oSHar, /* ASR immediate */ | |
6500 | OP_oSHllar, /* LSL or ASR immediate */ | |
6501 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6502 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6503 | |
5be8be5d DG |
6504 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6505 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6506 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6507 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6508 | ||
c19d1205 ZW |
6509 | OP_FIRST_OPTIONAL = OP_oI7b |
6510 | }; | |
a737bd4d | 6511 | |
c19d1205 ZW |
6512 | /* Generic instruction operand parser. This does no encoding and no |
6513 | semantic validation; it merely squirrels values away in the inst | |
6514 | structure. Returns SUCCESS or FAIL depending on whether the | |
6515 | specified grammar matched. */ | |
6516 | static int | |
5be8be5d | 6517 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6518 | { |
5be8be5d | 6519 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6520 | char *backtrack_pos = 0; |
6521 | const char *backtrack_error = 0; | |
99aad254 | 6522 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6523 | enum arm_reg_type rtype; |
4962c51a | 6524 | parse_operand_result result; |
5be8be5d | 6525 | unsigned int op_parse_code; |
c19d1205 | 6526 | |
e07e6e58 NC |
6527 | #define po_char_or_fail(chr) \ |
6528 | do \ | |
6529 | { \ | |
6530 | if (skip_past_char (&str, chr) == FAIL) \ | |
477330fc | 6531 | goto bad_args; \ |
e07e6e58 NC |
6532 | } \ |
6533 | while (0) | |
c19d1205 | 6534 | |
e07e6e58 NC |
6535 | #define po_reg_or_fail(regtype) \ |
6536 | do \ | |
dcbf9037 | 6537 | { \ |
e07e6e58 | 6538 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
477330fc | 6539 | & inst.operands[i].vectype); \ |
e07e6e58 | 6540 | if (val == FAIL) \ |
477330fc RM |
6541 | { \ |
6542 | first_error (_(reg_expected_msgs[regtype])); \ | |
6543 | goto failure; \ | |
6544 | } \ | |
e07e6e58 NC |
6545 | inst.operands[i].reg = val; \ |
6546 | inst.operands[i].isreg = 1; \ | |
6547 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6548 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6549 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc RM |
6550 | || rtype == REG_TYPE_VFD \ |
6551 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6552 | } \ |
e07e6e58 NC |
6553 | while (0) |
6554 | ||
6555 | #define po_reg_or_goto(regtype, label) \ | |
6556 | do \ | |
6557 | { \ | |
6558 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6559 | & inst.operands[i].vectype); \ | |
6560 | if (val == FAIL) \ | |
6561 | goto label; \ | |
dcbf9037 | 6562 | \ |
e07e6e58 NC |
6563 | inst.operands[i].reg = val; \ |
6564 | inst.operands[i].isreg = 1; \ | |
6565 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6566 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6567 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
477330fc | 6568 | || rtype == REG_TYPE_VFD \ |
e07e6e58 NC |
6569 | || rtype == REG_TYPE_NQ); \ |
6570 | } \ | |
6571 | while (0) | |
6572 | ||
6573 | #define po_imm_or_fail(min, max, popt) \ | |
6574 | do \ | |
6575 | { \ | |
6576 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6577 | goto failure; \ | |
6578 | inst.operands[i].imm = val; \ | |
6579 | } \ | |
6580 | while (0) | |
6581 | ||
6582 | #define po_scalar_or_goto(elsz, label) \ | |
6583 | do \ | |
6584 | { \ | |
6585 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6586 | if (val == FAIL) \ | |
6587 | goto label; \ | |
6588 | inst.operands[i].reg = val; \ | |
6589 | inst.operands[i].isscalar = 1; \ | |
6590 | } \ | |
6591 | while (0) | |
6592 | ||
6593 | #define po_misc_or_fail(expr) \ | |
6594 | do \ | |
6595 | { \ | |
6596 | if (expr) \ | |
6597 | goto failure; \ | |
6598 | } \ | |
6599 | while (0) | |
6600 | ||
6601 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6602 | do \ | |
6603 | { \ | |
6604 | result = expr; \ | |
6605 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6606 | backtrack_pos = 0; \ | |
6607 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6608 | goto failure; \ | |
6609 | } \ | |
6610 | while (0) | |
4962c51a | 6611 | |
52e7f43d RE |
6612 | #define po_barrier_or_imm(str) \ |
6613 | do \ | |
6614 | { \ | |
6615 | val = parse_barrier (&str); \ | |
ccb84d65 JB |
6616 | if (val == FAIL && ! ISALPHA (*str)) \ |
6617 | goto immediate; \ | |
6618 | if (val == FAIL \ | |
6619 | /* ISB can only take SY as an option. */ \ | |
6620 | || ((inst.instruction & 0xf0) == 0x60 \ | |
6621 | && val != 0xf)) \ | |
52e7f43d | 6622 | { \ |
ccb84d65 JB |
6623 | inst.error = _("invalid barrier type"); \ |
6624 | backtrack_pos = 0; \ | |
6625 | goto failure; \ | |
52e7f43d RE |
6626 | } \ |
6627 | } \ | |
6628 | while (0) | |
6629 | ||
c19d1205 ZW |
6630 | skip_whitespace (str); |
6631 | ||
6632 | for (i = 0; upat[i] != OP_stop; i++) | |
6633 | { | |
5be8be5d DG |
6634 | op_parse_code = upat[i]; |
6635 | if (op_parse_code >= 1<<16) | |
6636 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6637 | : (op_parse_code & ((1<<16)-1)); | |
6638 | ||
6639 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6640 | { |
6641 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6642 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6643 | backtrack_pos = str; |
6644 | backtrack_error = inst.error; | |
6645 | backtrack_index = i; | |
6646 | } | |
6647 | ||
b6702015 | 6648 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6649 | po_char_or_fail (','); |
6650 | ||
5be8be5d | 6651 | switch (op_parse_code) |
c19d1205 ZW |
6652 | { |
6653 | /* Registers */ | |
6654 | case OP_oRRnpc: | |
5be8be5d | 6655 | case OP_oRRnpcsp: |
c19d1205 | 6656 | case OP_RRnpc: |
5be8be5d | 6657 | case OP_RRnpcsp: |
c19d1205 ZW |
6658 | case OP_oRR: |
6659 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6660 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6661 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6662 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6663 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6664 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
477330fc | 6665 | case OP_oRND: |
5287ad62 | 6666 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; |
cd2cf30b PB |
6667 | case OP_RVC: |
6668 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6669 | break; | |
6670 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6671 | coproc_reg: | |
6672 | po_reg_or_fail (REG_TYPE_CN); | |
6673 | break; | |
c19d1205 ZW |
6674 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6675 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6676 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6677 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6678 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6679 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6680 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6681 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6682 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6683 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
477330fc | 6684 | case OP_oRNQ: |
5287ad62 | 6685 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; |
477330fc | 6686 | case OP_oRNDQ: |
5287ad62 | 6687 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; |
477330fc RM |
6688 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6689 | case OP_oRNSDQ: | |
6690 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
6691 | ||
6692 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6693 | scalars are accepted here, so deal with those in later code. */ | |
6694 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6695 | ||
6696 | case OP_RNDQ_I0: | |
6697 | { | |
6698 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6699 | break; | |
6700 | try_imm0: | |
6701 | po_imm_or_fail (0, 0, TRUE); | |
6702 | } | |
6703 | break; | |
6704 | ||
6705 | case OP_RVSD_I0: | |
6706 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6707 | break; | |
6708 | ||
aacf0b33 KT |
6709 | case OP_RSVD_FI0: |
6710 | { | |
6711 | po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0); | |
6712 | break; | |
6713 | try_ifimm0: | |
6714 | if (parse_ifimm_zero (&str)) | |
6715 | inst.operands[i].imm = 0; | |
6716 | else | |
6717 | { | |
6718 | inst.error | |
6719 | = _("only floating point zero is allowed as immediate value"); | |
6720 | goto failure; | |
6721 | } | |
6722 | } | |
6723 | break; | |
6724 | ||
477330fc RM |
6725 | case OP_RR_RNSC: |
6726 | { | |
6727 | po_scalar_or_goto (8, try_rr); | |
6728 | break; | |
6729 | try_rr: | |
6730 | po_reg_or_fail (REG_TYPE_RN); | |
6731 | } | |
6732 | break; | |
6733 | ||
6734 | case OP_RNSDQ_RNSC: | |
6735 | { | |
6736 | po_scalar_or_goto (8, try_nsdq); | |
6737 | break; | |
6738 | try_nsdq: | |
6739 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6740 | } | |
6741 | break; | |
6742 | ||
6743 | case OP_RNDQ_RNSC: | |
6744 | { | |
6745 | po_scalar_or_goto (8, try_ndq); | |
6746 | break; | |
6747 | try_ndq: | |
6748 | po_reg_or_fail (REG_TYPE_NDQ); | |
6749 | } | |
6750 | break; | |
6751 | ||
6752 | case OP_RND_RNSC: | |
6753 | { | |
6754 | po_scalar_or_goto (8, try_vfd); | |
6755 | break; | |
6756 | try_vfd: | |
6757 | po_reg_or_fail (REG_TYPE_VFD); | |
6758 | } | |
6759 | break; | |
6760 | ||
6761 | case OP_VMOV: | |
6762 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6763 | not careful then bad things might happen. */ | |
6764 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6765 | break; | |
6766 | ||
6767 | case OP_RNDQ_Ibig: | |
6768 | { | |
6769 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); | |
6770 | break; | |
6771 | try_immbig: | |
6772 | /* There's a possibility of getting a 64-bit immediate here, so | |
6773 | we need special handling. */ | |
8335d6aa JW |
6774 | if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) |
6775 | == FAIL) | |
477330fc RM |
6776 | { |
6777 | inst.error = _("immediate value is out of range"); | |
6778 | goto failure; | |
6779 | } | |
6780 | } | |
6781 | break; | |
6782 | ||
6783 | case OP_RNDQ_I63b: | |
6784 | { | |
6785 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6786 | break; | |
6787 | try_shimm: | |
6788 | po_imm_or_fail (0, 63, TRUE); | |
6789 | } | |
6790 | break; | |
c19d1205 ZW |
6791 | |
6792 | case OP_RRnpcb: | |
6793 | po_char_or_fail ('['); | |
6794 | po_reg_or_fail (REG_TYPE_RN); | |
6795 | po_char_or_fail (']'); | |
6796 | break; | |
a737bd4d | 6797 | |
55881a11 | 6798 | case OP_RRnpctw: |
c19d1205 | 6799 | case OP_RRw: |
b6702015 | 6800 | case OP_oRRw: |
c19d1205 ZW |
6801 | po_reg_or_fail (REG_TYPE_RN); |
6802 | if (skip_past_char (&str, '!') == SUCCESS) | |
6803 | inst.operands[i].writeback = 1; | |
6804 | break; | |
6805 | ||
6806 | /* Immediates */ | |
6807 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6808 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6809 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
477330fc | 6810 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6811 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6812 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
477330fc | 6813 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6814 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
477330fc RM |
6815 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6816 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6817 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6818 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6819 | |
6820 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6821 | case OP_oI7b: | |
6822 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6823 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6824 | case OP_oI31b: | |
6825 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
477330fc RM |
6826 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
6827 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; | |
c19d1205 ZW |
6828 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6829 | ||
6830 | /* Immediate variants */ | |
6831 | case OP_oI255c: | |
6832 | po_char_or_fail ('{'); | |
6833 | po_imm_or_fail (0, 255, TRUE); | |
6834 | po_char_or_fail ('}'); | |
6835 | break; | |
6836 | ||
6837 | case OP_I31w: | |
6838 | /* The expression parser chokes on a trailing !, so we have | |
6839 | to find it first and zap it. */ | |
6840 | { | |
6841 | char *s = str; | |
6842 | while (*s && *s != ',') | |
6843 | s++; | |
6844 | if (s[-1] == '!') | |
6845 | { | |
6846 | s[-1] = '\0'; | |
6847 | inst.operands[i].writeback = 1; | |
6848 | } | |
6849 | po_imm_or_fail (0, 31, TRUE); | |
6850 | if (str == s - 1) | |
6851 | str = s; | |
6852 | } | |
6853 | break; | |
6854 | ||
6855 | /* Expressions */ | |
6856 | case OP_EXPi: EXPi: | |
6857 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6858 | GE_OPT_PREFIX)); | |
6859 | break; | |
6860 | ||
6861 | case OP_EXP: | |
6862 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6863 | GE_NO_PREFIX)); | |
6864 | break; | |
6865 | ||
6866 | case OP_EXPr: EXPr: | |
6867 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6868 | GE_NO_PREFIX)); | |
6869 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6870 | { |
c19d1205 ZW |
6871 | val = parse_reloc (&str); |
6872 | if (val == -1) | |
6873 | { | |
6874 | inst.error = _("unrecognized relocation suffix"); | |
6875 | goto failure; | |
6876 | } | |
6877 | else if (val != BFD_RELOC_UNUSED) | |
6878 | { | |
6879 | inst.operands[i].imm = val; | |
6880 | inst.operands[i].hasreloc = 1; | |
6881 | } | |
a737bd4d | 6882 | } |
c19d1205 | 6883 | break; |
a737bd4d | 6884 | |
b6895b4f PB |
6885 | /* Operand for MOVW or MOVT. */ |
6886 | case OP_HALF: | |
6887 | po_misc_or_fail (parse_half (&str)); | |
6888 | break; | |
6889 | ||
e07e6e58 | 6890 | /* Register or expression. */ |
c19d1205 ZW |
6891 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6892 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6893 | |
e07e6e58 | 6894 | /* Register or immediate. */ |
c19d1205 ZW |
6895 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6896 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6897 | |
c19d1205 ZW |
6898 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6899 | IF: | |
6900 | if (!is_immediate_prefix (*str)) | |
6901 | goto bad_args; | |
6902 | str++; | |
6903 | val = parse_fpa_immediate (&str); | |
6904 | if (val == FAIL) | |
6905 | goto failure; | |
6906 | /* FPA immediates are encoded as registers 8-15. | |
6907 | parse_fpa_immediate has already applied the offset. */ | |
6908 | inst.operands[i].reg = val; | |
6909 | inst.operands[i].isreg = 1; | |
6910 | break; | |
09d92015 | 6911 | |
2d447fca JM |
6912 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6913 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6914 | ||
e07e6e58 | 6915 | /* Two kinds of register. */ |
c19d1205 ZW |
6916 | case OP_RIWR_RIWC: |
6917 | { | |
6918 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6919 | if (!rege |
6920 | || (rege->type != REG_TYPE_MMXWR | |
6921 | && rege->type != REG_TYPE_MMXWC | |
6922 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6923 | { |
6924 | inst.error = _("iWMMXt data or control register expected"); | |
6925 | goto failure; | |
6926 | } | |
6927 | inst.operands[i].reg = rege->number; | |
6928 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6929 | } | |
6930 | break; | |
09d92015 | 6931 | |
41adaa5c JM |
6932 | case OP_RIWC_RIWG: |
6933 | { | |
6934 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6935 | if (!rege | |
6936 | || (rege->type != REG_TYPE_MMXWC | |
6937 | && rege->type != REG_TYPE_MMXWCG)) | |
6938 | { | |
6939 | inst.error = _("iWMMXt control register expected"); | |
6940 | goto failure; | |
6941 | } | |
6942 | inst.operands[i].reg = rege->number; | |
6943 | inst.operands[i].isreg = 1; | |
6944 | } | |
6945 | break; | |
6946 | ||
c19d1205 ZW |
6947 | /* Misc */ |
6948 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6949 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6950 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6951 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6952 | case OP_oBARRIER_I15: |
6953 | po_barrier_or_imm (str); break; | |
6954 | immediate: | |
6955 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
477330fc | 6956 | goto failure; |
52e7f43d | 6957 | break; |
c19d1205 | 6958 | |
fa94de6b | 6959 | case OP_wPSR: |
d2cd1205 | 6960 | case OP_rPSR: |
90ec0d68 MGD |
6961 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6962 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6963 | { | |
6964 | inst.error = _("Banked registers are not available with this " | |
6965 | "architecture."); | |
6966 | goto failure; | |
6967 | } | |
6968 | break; | |
d2cd1205 JB |
6969 | try_psr: |
6970 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6971 | break; | |
037e8744 | 6972 | |
477330fc RM |
6973 | case OP_APSR_RR: |
6974 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6975 | break; | |
6976 | try_apsr: | |
6977 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6978 | instruction). */ | |
6979 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6980 | { | |
6981 | unsigned found = 0; | |
6982 | str += 5; | |
6983 | while (found < 15) | |
6984 | switch (*str++) | |
6985 | { | |
6986 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6987 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6988 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6989 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6990 | default: found = 16; | |
6991 | } | |
6992 | if (found != 15) | |
6993 | goto failure; | |
6994 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6995 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6996 | inst.operands[i].reg = REG_PC; | |
477330fc RM |
6997 | } |
6998 | else | |
6999 | goto failure; | |
7000 | break; | |
037e8744 | 7001 | |
92e90b6e PB |
7002 | case OP_TB: |
7003 | po_misc_or_fail (parse_tb (&str)); | |
7004 | break; | |
7005 | ||
e07e6e58 | 7006 | /* Register lists. */ |
c19d1205 ZW |
7007 | case OP_REGLST: |
7008 | val = parse_reg_list (&str); | |
7009 | if (*str == '^') | |
7010 | { | |
5e0d7f77 | 7011 | inst.operands[i].writeback = 1; |
c19d1205 ZW |
7012 | str++; |
7013 | } | |
7014 | break; | |
09d92015 | 7015 | |
c19d1205 | 7016 | case OP_VRSLST: |
5287ad62 | 7017 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 7018 | break; |
09d92015 | 7019 | |
c19d1205 | 7020 | case OP_VRDLST: |
5287ad62 | 7021 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 7022 | break; |
a737bd4d | 7023 | |
477330fc RM |
7024 | case OP_VRSDLST: |
7025 | /* Allow Q registers too. */ | |
7026 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7027 | REGLIST_NEON_D); | |
7028 | if (val == FAIL) | |
7029 | { | |
7030 | inst.error = NULL; | |
7031 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7032 | REGLIST_VFP_S); | |
7033 | inst.operands[i].issingle = 1; | |
7034 | } | |
7035 | break; | |
7036 | ||
7037 | case OP_NRDLST: | |
7038 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
7039 | REGLIST_NEON_D); | |
7040 | break; | |
5287ad62 JB |
7041 | |
7042 | case OP_NSTRLST: | |
477330fc RM |
7043 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
7044 | &inst.operands[i].vectype); | |
7045 | break; | |
5287ad62 | 7046 | |
c19d1205 ZW |
7047 | /* Addressing modes */ |
7048 | case OP_ADDR: | |
7049 | po_misc_or_fail (parse_address (&str, i)); | |
7050 | break; | |
09d92015 | 7051 | |
4962c51a MS |
7052 | case OP_ADDRGLDR: |
7053 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7054 | parse_address_group_reloc (&str, i, GROUP_LDR)); |
4962c51a MS |
7055 | break; |
7056 | ||
7057 | case OP_ADDRGLDRS: | |
7058 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7059 | parse_address_group_reloc (&str, i, GROUP_LDRS)); |
4962c51a MS |
7060 | break; |
7061 | ||
7062 | case OP_ADDRGLDC: | |
7063 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7064 | parse_address_group_reloc (&str, i, GROUP_LDC)); |
4962c51a MS |
7065 | break; |
7066 | ||
c19d1205 ZW |
7067 | case OP_SH: |
7068 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
7069 | break; | |
09d92015 | 7070 | |
4962c51a MS |
7071 | case OP_SHG: |
7072 | po_misc_or_fail_no_backtrack ( | |
477330fc | 7073 | parse_shifter_operand_group_reloc (&str, i)); |
4962c51a MS |
7074 | break; |
7075 | ||
c19d1205 ZW |
7076 | case OP_oSHll: |
7077 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
7078 | break; | |
09d92015 | 7079 | |
c19d1205 ZW |
7080 | case OP_oSHar: |
7081 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
7082 | break; | |
09d92015 | 7083 | |
c19d1205 ZW |
7084 | case OP_oSHllar: |
7085 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
7086 | break; | |
09d92015 | 7087 | |
c19d1205 | 7088 | default: |
5be8be5d | 7089 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 7090 | } |
09d92015 | 7091 | |
c19d1205 ZW |
7092 | /* Various value-based sanity checks and shared operations. We |
7093 | do not signal immediate failures for the register constraints; | |
7094 | this allows a syntax error to take precedence. */ | |
5be8be5d | 7095 | switch (op_parse_code) |
c19d1205 ZW |
7096 | { |
7097 | case OP_oRRnpc: | |
7098 | case OP_RRnpc: | |
7099 | case OP_RRnpcb: | |
7100 | case OP_RRw: | |
b6702015 | 7101 | case OP_oRRw: |
c19d1205 ZW |
7102 | case OP_RRnpc_I0: |
7103 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
7104 | inst.error = BAD_PC; | |
7105 | break; | |
09d92015 | 7106 | |
5be8be5d DG |
7107 | case OP_oRRnpcsp: |
7108 | case OP_RRnpcsp: | |
7109 | if (inst.operands[i].isreg) | |
7110 | { | |
7111 | if (inst.operands[i].reg == REG_PC) | |
7112 | inst.error = BAD_PC; | |
7113 | else if (inst.operands[i].reg == REG_SP) | |
7114 | inst.error = BAD_SP; | |
7115 | } | |
7116 | break; | |
7117 | ||
55881a11 | 7118 | case OP_RRnpctw: |
fa94de6b RM |
7119 | if (inst.operands[i].isreg |
7120 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
7121 | && (inst.operands[i].writeback || thumb)) |
7122 | inst.error = BAD_PC; | |
7123 | break; | |
7124 | ||
c19d1205 ZW |
7125 | case OP_CPSF: |
7126 | case OP_ENDI: | |
7127 | case OP_oROR: | |
d2cd1205 JB |
7128 | case OP_wPSR: |
7129 | case OP_rPSR: | |
c19d1205 | 7130 | case OP_COND: |
52e7f43d | 7131 | case OP_oBARRIER_I15: |
c19d1205 ZW |
7132 | case OP_REGLST: |
7133 | case OP_VRSLST: | |
7134 | case OP_VRDLST: | |
477330fc RM |
7135 | case OP_VRSDLST: |
7136 | case OP_NRDLST: | |
7137 | case OP_NSTRLST: | |
c19d1205 ZW |
7138 | if (val == FAIL) |
7139 | goto failure; | |
7140 | inst.operands[i].imm = val; | |
7141 | break; | |
a737bd4d | 7142 | |
c19d1205 ZW |
7143 | default: |
7144 | break; | |
7145 | } | |
09d92015 | 7146 | |
c19d1205 ZW |
7147 | /* If we get here, this operand was successfully parsed. */ |
7148 | inst.operands[i].present = 1; | |
7149 | continue; | |
09d92015 | 7150 | |
c19d1205 | 7151 | bad_args: |
09d92015 | 7152 | inst.error = BAD_ARGS; |
c19d1205 ZW |
7153 | |
7154 | failure: | |
7155 | if (!backtrack_pos) | |
d252fdde PB |
7156 | { |
7157 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 7158 | default here just in case. */ |
d252fdde PB |
7159 | if (!inst.error) |
7160 | inst.error = _("syntax error"); | |
7161 | return FAIL; | |
7162 | } | |
c19d1205 ZW |
7163 | |
7164 | /* Do not backtrack over a trailing optional argument that | |
7165 | absorbed some text. We will only fail again, with the | |
7166 | 'garbage following instruction' error message, which is | |
7167 | probably less helpful than the current one. */ | |
7168 | if (backtrack_index == i && backtrack_pos != str | |
7169 | && upat[i+1] == OP_stop) | |
d252fdde PB |
7170 | { |
7171 | if (!inst.error) | |
7172 | inst.error = _("syntax error"); | |
7173 | return FAIL; | |
7174 | } | |
c19d1205 ZW |
7175 | |
7176 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
7177 | str = backtrack_pos; | |
7178 | inst.error = backtrack_error; | |
7179 | inst.operands[backtrack_index].present = 0; | |
7180 | i = backtrack_index; | |
7181 | backtrack_pos = 0; | |
09d92015 | 7182 | } |
09d92015 | 7183 | |
c19d1205 ZW |
7184 | /* Check that we have parsed all the arguments. */ |
7185 | if (*str != '\0' && !inst.error) | |
7186 | inst.error = _("garbage following instruction"); | |
09d92015 | 7187 | |
c19d1205 | 7188 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
7189 | } |
7190 | ||
c19d1205 ZW |
7191 | #undef po_char_or_fail |
7192 | #undef po_reg_or_fail | |
7193 | #undef po_reg_or_goto | |
7194 | #undef po_imm_or_fail | |
5287ad62 | 7195 | #undef po_scalar_or_fail |
52e7f43d | 7196 | #undef po_barrier_or_imm |
e07e6e58 | 7197 | |
c19d1205 | 7198 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
7199 | #define constraint(expr, err) \ |
7200 | do \ | |
c19d1205 | 7201 | { \ |
e07e6e58 NC |
7202 | if (expr) \ |
7203 | { \ | |
7204 | inst.error = err; \ | |
7205 | return; \ | |
7206 | } \ | |
c19d1205 | 7207 | } \ |
e07e6e58 | 7208 | while (0) |
c19d1205 | 7209 | |
fdfde340 JM |
7210 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
7211 | instructions are unpredictable if these registers are used. This | |
7212 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
7213 | #define reject_bad_reg(reg) \ | |
7214 | do \ | |
7215 | if (reg == REG_SP || reg == REG_PC) \ | |
7216 | { \ | |
7217 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
7218 | return; \ | |
7219 | } \ | |
7220 | while (0) | |
7221 | ||
94206790 MM |
7222 | /* If REG is R13 (the stack pointer), warn that its use is |
7223 | deprecated. */ | |
7224 | #define warn_deprecated_sp(reg) \ | |
7225 | do \ | |
7226 | if (warn_on_deprecated && reg == REG_SP) \ | |
5c3696f8 | 7227 | as_tsktsk (_("use of r13 is deprecated")); \ |
94206790 MM |
7228 | while (0) |
7229 | ||
c19d1205 ZW |
7230 | /* Functions for operand encoding. ARM, then Thumb. */ |
7231 | ||
d840c081 | 7232 | #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) |
c19d1205 ZW |
7233 | |
7234 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
7235 | return the encoded form. Otherwise, return FAIL. */ | |
7236 | ||
7237 | static unsigned int | |
7238 | encode_arm_immediate (unsigned int val) | |
09d92015 | 7239 | { |
c19d1205 ZW |
7240 | unsigned int a, i; |
7241 | ||
7242 | for (i = 0; i < 32; i += 2) | |
7243 | if ((a = rotate_left (val, i)) <= 0xff) | |
7244 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
7245 | ||
7246 | return FAIL; | |
09d92015 MM |
7247 | } |
7248 | ||
c19d1205 ZW |
7249 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
7250 | return the encoded form. Otherwise, return FAIL. */ | |
7251 | static unsigned int | |
7252 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 7253 | { |
c19d1205 | 7254 | unsigned int a, i; |
09d92015 | 7255 | |
9c3c69f2 | 7256 | if (val <= 0xff) |
c19d1205 | 7257 | return val; |
a737bd4d | 7258 | |
9c3c69f2 | 7259 | for (i = 1; i <= 24; i++) |
09d92015 | 7260 | { |
9c3c69f2 PB |
7261 | a = val >> i; |
7262 | if ((val & ~(0xff << i)) == 0) | |
7263 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 7264 | } |
a737bd4d | 7265 | |
c19d1205 ZW |
7266 | a = val & 0xff; |
7267 | if (val == ((a << 16) | a)) | |
7268 | return 0x100 | a; | |
7269 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
7270 | return 0x300 | a; | |
09d92015 | 7271 | |
c19d1205 ZW |
7272 | a = val & 0xff00; |
7273 | if (val == ((a << 16) | a)) | |
7274 | return 0x200 | (a >> 8); | |
a737bd4d | 7275 | |
c19d1205 | 7276 | return FAIL; |
09d92015 | 7277 | } |
5287ad62 | 7278 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
7279 | |
7280 | static void | |
5287ad62 JB |
7281 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
7282 | { | |
7283 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
7284 | && reg > 15) | |
7285 | { | |
b1cc4aeb | 7286 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
477330fc RM |
7287 | { |
7288 | if (thumb_mode) | |
7289 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
7290 | fpu_vfp_ext_d32); | |
7291 | else | |
7292 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
7293 | fpu_vfp_ext_d32); | |
7294 | } | |
5287ad62 | 7295 | else |
477330fc RM |
7296 | { |
7297 | first_error (_("D register out of range for selected VFP version")); | |
7298 | return; | |
7299 | } | |
5287ad62 JB |
7300 | } |
7301 | ||
c19d1205 | 7302 | switch (pos) |
09d92015 | 7303 | { |
c19d1205 ZW |
7304 | case VFP_REG_Sd: |
7305 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
7306 | break; | |
7307 | ||
7308 | case VFP_REG_Sn: | |
7309 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
7310 | break; | |
7311 | ||
7312 | case VFP_REG_Sm: | |
7313 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
7314 | break; | |
7315 | ||
5287ad62 JB |
7316 | case VFP_REG_Dd: |
7317 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
7318 | break; | |
5f4273c7 | 7319 | |
5287ad62 JB |
7320 | case VFP_REG_Dn: |
7321 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7322 | break; | |
5f4273c7 | 7323 | |
5287ad62 JB |
7324 | case VFP_REG_Dm: |
7325 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7326 | break; | |
7327 | ||
c19d1205 ZW |
7328 | default: |
7329 | abort (); | |
09d92015 | 7330 | } |
09d92015 MM |
7331 | } |
7332 | ||
c19d1205 | 7333 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7334 | if any, is handled by md_apply_fix. */ |
09d92015 | 7335 | static void |
c19d1205 | 7336 | encode_arm_shift (int i) |
09d92015 | 7337 | { |
c19d1205 ZW |
7338 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7339 | inst.instruction |= SHIFT_ROR << 5; | |
7340 | else | |
09d92015 | 7341 | { |
c19d1205 ZW |
7342 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7343 | if (inst.operands[i].immisreg) | |
7344 | { | |
7345 | inst.instruction |= SHIFT_BY_REG; | |
7346 | inst.instruction |= inst.operands[i].imm << 8; | |
7347 | } | |
7348 | else | |
7349 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7350 | } |
c19d1205 | 7351 | } |
09d92015 | 7352 | |
c19d1205 ZW |
7353 | static void |
7354 | encode_arm_shifter_operand (int i) | |
7355 | { | |
7356 | if (inst.operands[i].isreg) | |
09d92015 | 7357 | { |
c19d1205 ZW |
7358 | inst.instruction |= inst.operands[i].reg; |
7359 | encode_arm_shift (i); | |
09d92015 | 7360 | } |
c19d1205 | 7361 | else |
a415b1cd JB |
7362 | { |
7363 | inst.instruction |= INST_IMMEDIATE; | |
7364 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7365 | inst.instruction |= inst.operands[i].imm; | |
7366 | } | |
09d92015 MM |
7367 | } |
7368 | ||
c19d1205 | 7369 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7370 | static void |
c19d1205 | 7371 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7372 | { |
2b2f5df9 NC |
7373 | /* PR 14260: |
7374 | Generate an error if the operand is not a register. */ | |
7375 | constraint (!inst.operands[i].isreg, | |
7376 | _("Instruction does not support =N addresses")); | |
7377 | ||
c19d1205 | 7378 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7379 | |
c19d1205 | 7380 | if (inst.operands[i].preind) |
09d92015 | 7381 | { |
c19d1205 ZW |
7382 | if (is_t) |
7383 | { | |
7384 | inst.error = _("instruction does not accept preindexed addressing"); | |
7385 | return; | |
7386 | } | |
7387 | inst.instruction |= PRE_INDEX; | |
7388 | if (inst.operands[i].writeback) | |
7389 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7390 | |
c19d1205 ZW |
7391 | } |
7392 | else if (inst.operands[i].postind) | |
7393 | { | |
9c2799c2 | 7394 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7395 | if (is_t) |
7396 | inst.instruction |= WRITE_BACK; | |
7397 | } | |
7398 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7399 | { |
c19d1205 | 7400 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7401 | return; |
7402 | } | |
7403 | ||
c19d1205 ZW |
7404 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7405 | && (((inst.instruction & 0x000f0000) >> 16) | |
7406 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7407 | as_warn ((inst.instruction & LOAD_BIT) | |
7408 | ? _("destination register same as write-back base") | |
7409 | : _("source register same as write-back base")); | |
09d92015 MM |
7410 | } |
7411 | ||
c19d1205 ZW |
7412 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7413 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7414 | reject forms that cannot be used with a T instruction (i.e. not | |
7415 | post-indexed). */ | |
a737bd4d | 7416 | static void |
c19d1205 | 7417 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7418 | { |
5be8be5d DG |
7419 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7420 | ||
c19d1205 | 7421 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7422 | |
c19d1205 | 7423 | if (inst.operands[i].immisreg) |
09d92015 | 7424 | { |
5be8be5d DG |
7425 | constraint ((inst.operands[i].imm == REG_PC |
7426 | || (is_pc && inst.operands[i].writeback)), | |
7427 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7428 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7429 | inst.instruction |= inst.operands[i].imm; | |
7430 | if (!inst.operands[i].negative) | |
7431 | inst.instruction |= INDEX_UP; | |
7432 | if (inst.operands[i].shifted) | |
7433 | { | |
7434 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7435 | inst.instruction |= SHIFT_ROR << 5; | |
7436 | else | |
7437 | { | |
7438 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7439 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7440 | } | |
7441 | } | |
09d92015 | 7442 | } |
c19d1205 | 7443 | else /* immediate offset in inst.reloc */ |
09d92015 | 7444 | { |
5be8be5d DG |
7445 | if (is_pc && !inst.reloc.pc_rel) |
7446 | { | |
7447 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7448 | |
7449 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7450 | cannot use PC in addressing. | |
7451 | PC cannot be used in writeback addressing, either. */ | |
7452 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7453 | BAD_PC_ADDRESSING); |
23a10334 | 7454 | |
dc5ec521 | 7455 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7456 | if (warn_on_deprecated |
7457 | && !is_load | |
7458 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
5c3696f8 | 7459 | as_tsktsk (_("use of PC in this instruction is deprecated")); |
5be8be5d DG |
7460 | } |
7461 | ||
c19d1205 | 7462 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7463 | { |
7464 | /* Prefer + for zero encoded value. */ | |
7465 | if (!inst.operands[i].negative) | |
7466 | inst.instruction |= INDEX_UP; | |
7467 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7468 | } | |
09d92015 | 7469 | } |
09d92015 MM |
7470 | } |
7471 | ||
c19d1205 ZW |
7472 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7473 | ARM-format mode 3 load or store instruction. Reject forms that | |
7474 | cannot be used with such instructions. If is_t is true, reject | |
7475 | forms that cannot be used with a T instruction (i.e. not | |
7476 | post-indexed). */ | |
7477 | static void | |
7478 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7479 | { |
c19d1205 | 7480 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7481 | { |
c19d1205 ZW |
7482 | inst.error = _("instruction does not accept scaled register index"); |
7483 | return; | |
09d92015 | 7484 | } |
a737bd4d | 7485 | |
c19d1205 | 7486 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7487 | |
c19d1205 ZW |
7488 | if (inst.operands[i].immisreg) |
7489 | { | |
5be8be5d | 7490 | constraint ((inst.operands[i].imm == REG_PC |
eb9f3f00 | 7491 | || (is_t && inst.operands[i].reg == REG_PC)), |
5be8be5d | 7492 | BAD_PC_ADDRESSING); |
eb9f3f00 JB |
7493 | constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, |
7494 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7495 | inst.instruction |= inst.operands[i].imm; |
7496 | if (!inst.operands[i].negative) | |
7497 | inst.instruction |= INDEX_UP; | |
7498 | } | |
7499 | else /* immediate offset in inst.reloc */ | |
7500 | { | |
5be8be5d DG |
7501 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7502 | && inst.operands[i].writeback), | |
7503 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7504 | inst.instruction |= HWOFFSET_IMM; |
7505 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7506 | { |
7507 | /* Prefer + for zero encoded value. */ | |
7508 | if (!inst.operands[i].negative) | |
7509 | inst.instruction |= INDEX_UP; | |
7510 | ||
7511 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7512 | } | |
c19d1205 | 7513 | } |
a737bd4d NC |
7514 | } |
7515 | ||
8335d6aa JW |
7516 | /* Write immediate bits [7:0] to the following locations: |
7517 | ||
7518 | |28/24|23 19|18 16|15 4|3 0| | |
7519 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
7520 | ||
7521 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
7522 | ||
7523 | static void | |
7524 | neon_write_immbits (unsigned immbits) | |
7525 | { | |
7526 | inst.instruction |= immbits & 0xf; | |
7527 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
7528 | inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); | |
7529 | } | |
7530 | ||
7531 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
7532 | ||
7533 | static void | |
7534 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
7535 | { | |
7536 | unsigned immlo = xlo ? *xlo : 0; | |
7537 | unsigned immhi = xhi ? *xhi : 0; | |
7538 | ||
7539 | switch (size) | |
7540 | { | |
7541 | case 8: | |
7542 | immlo = (~immlo) & 0xff; | |
7543 | break; | |
7544 | ||
7545 | case 16: | |
7546 | immlo = (~immlo) & 0xffff; | |
7547 | break; | |
7548 | ||
7549 | case 64: | |
7550 | immhi = (~immhi) & 0xffffffff; | |
7551 | /* fall through. */ | |
7552 | ||
7553 | case 32: | |
7554 | immlo = (~immlo) & 0xffffffff; | |
7555 | break; | |
7556 | ||
7557 | default: | |
7558 | abort (); | |
7559 | } | |
7560 | ||
7561 | if (xlo) | |
7562 | *xlo = immlo; | |
7563 | ||
7564 | if (xhi) | |
7565 | *xhi = immhi; | |
7566 | } | |
7567 | ||
7568 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
7569 | A, B, C, D. */ | |
09d92015 | 7570 | |
c19d1205 | 7571 | static int |
8335d6aa | 7572 | neon_bits_same_in_bytes (unsigned imm) |
09d92015 | 7573 | { |
8335d6aa JW |
7574 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) |
7575 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
7576 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
7577 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
7578 | } | |
a737bd4d | 7579 | |
8335d6aa | 7580 | /* For immediate of above form, return 0bABCD. */ |
09d92015 | 7581 | |
8335d6aa JW |
7582 | static unsigned |
7583 | neon_squash_bits (unsigned imm) | |
7584 | { | |
7585 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
7586 | | ((imm & 0x01000000) >> 21); | |
7587 | } | |
7588 | ||
7589 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ | |
7590 | ||
7591 | static unsigned | |
7592 | neon_qfloat_bits (unsigned imm) | |
7593 | { | |
7594 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); | |
7595 | } | |
7596 | ||
7597 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
7598 | the instruction. *OP is passed as the initial value of the op field, and | |
7599 | may be set to a different value depending on the constant (i.e. | |
7600 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
7601 | MVN). If the immediate looks like a repeated pattern then also | |
7602 | try smaller element sizes. */ | |
7603 | ||
7604 | static int | |
7605 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, | |
7606 | unsigned *immbits, int *op, int size, | |
7607 | enum neon_el_type type) | |
7608 | { | |
7609 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is | |
7610 | float. */ | |
7611 | if (type == NT_float && !float_p) | |
7612 | return FAIL; | |
7613 | ||
7614 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) | |
09d92015 | 7615 | { |
8335d6aa JW |
7616 | if (size != 32 || *op == 1) |
7617 | return FAIL; | |
7618 | *immbits = neon_qfloat_bits (immlo); | |
7619 | return 0xf; | |
7620 | } | |
7621 | ||
7622 | if (size == 64) | |
7623 | { | |
7624 | if (neon_bits_same_in_bytes (immhi) | |
7625 | && neon_bits_same_in_bytes (immlo)) | |
c19d1205 | 7626 | { |
8335d6aa JW |
7627 | if (*op == 1) |
7628 | return FAIL; | |
7629 | *immbits = (neon_squash_bits (immhi) << 4) | |
7630 | | neon_squash_bits (immlo); | |
7631 | *op = 1; | |
7632 | return 0xe; | |
c19d1205 | 7633 | } |
a737bd4d | 7634 | |
8335d6aa JW |
7635 | if (immhi != immlo) |
7636 | return FAIL; | |
7637 | } | |
a737bd4d | 7638 | |
8335d6aa | 7639 | if (size >= 32) |
09d92015 | 7640 | { |
8335d6aa | 7641 | if (immlo == (immlo & 0x000000ff)) |
c19d1205 | 7642 | { |
8335d6aa JW |
7643 | *immbits = immlo; |
7644 | return 0x0; | |
c19d1205 | 7645 | } |
8335d6aa | 7646 | else if (immlo == (immlo & 0x0000ff00)) |
c19d1205 | 7647 | { |
8335d6aa JW |
7648 | *immbits = immlo >> 8; |
7649 | return 0x2; | |
c19d1205 | 7650 | } |
8335d6aa JW |
7651 | else if (immlo == (immlo & 0x00ff0000)) |
7652 | { | |
7653 | *immbits = immlo >> 16; | |
7654 | return 0x4; | |
7655 | } | |
7656 | else if (immlo == (immlo & 0xff000000)) | |
7657 | { | |
7658 | *immbits = immlo >> 24; | |
7659 | return 0x6; | |
7660 | } | |
7661 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
7662 | { | |
7663 | *immbits = (immlo >> 8) & 0xff; | |
7664 | return 0xc; | |
7665 | } | |
7666 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
7667 | { | |
7668 | *immbits = (immlo >> 16) & 0xff; | |
7669 | return 0xd; | |
7670 | } | |
7671 | ||
7672 | if ((immlo & 0xffff) != (immlo >> 16)) | |
7673 | return FAIL; | |
7674 | immlo &= 0xffff; | |
09d92015 | 7675 | } |
a737bd4d | 7676 | |
8335d6aa | 7677 | if (size >= 16) |
4962c51a | 7678 | { |
8335d6aa JW |
7679 | if (immlo == (immlo & 0x000000ff)) |
7680 | { | |
7681 | *immbits = immlo; | |
7682 | return 0x8; | |
7683 | } | |
7684 | else if (immlo == (immlo & 0x0000ff00)) | |
7685 | { | |
7686 | *immbits = immlo >> 8; | |
7687 | return 0xa; | |
7688 | } | |
7689 | ||
7690 | if ((immlo & 0xff) != (immlo >> 8)) | |
7691 | return FAIL; | |
7692 | immlo &= 0xff; | |
4962c51a MS |
7693 | } |
7694 | ||
8335d6aa JW |
7695 | if (immlo == (immlo & 0x000000ff)) |
7696 | { | |
7697 | /* Don't allow MVN with 8-bit immediate. */ | |
7698 | if (*op == 1) | |
7699 | return FAIL; | |
7700 | *immbits = immlo; | |
7701 | return 0xe; | |
7702 | } | |
26d97720 | 7703 | |
8335d6aa | 7704 | return FAIL; |
c19d1205 | 7705 | } |
a737bd4d | 7706 | |
5fc177c8 | 7707 | #if defined BFD_HOST_64_BIT |
ba592044 AM |
7708 | /* Returns TRUE if double precision value V may be cast |
7709 | to single precision without loss of accuracy. */ | |
7710 | ||
7711 | static bfd_boolean | |
5fc177c8 | 7712 | is_double_a_single (bfd_int64_t v) |
ba592044 | 7713 | { |
5fc177c8 | 7714 | int exp = (int)((v >> 52) & 0x7FF); |
8fe3f3d6 | 7715 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
7716 | |
7717 | return (exp == 0 || exp == 0x7FF | |
7718 | || (exp >= 1023 - 126 && exp <= 1023 + 127)) | |
7719 | && (mantissa & 0x1FFFFFFFl) == 0; | |
7720 | } | |
7721 | ||
3739860c | 7722 | /* Returns a double precision value casted to single precision |
ba592044 AM |
7723 | (ignoring the least significant bits in exponent and mantissa). */ |
7724 | ||
7725 | static int | |
5fc177c8 | 7726 | double_to_single (bfd_int64_t v) |
ba592044 AM |
7727 | { |
7728 | int sign = (int) ((v >> 63) & 1l); | |
5fc177c8 | 7729 | int exp = (int) ((v >> 52) & 0x7FF); |
8fe3f3d6 | 7730 | bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL); |
ba592044 AM |
7731 | |
7732 | if (exp == 0x7FF) | |
7733 | exp = 0xFF; | |
7734 | else | |
7735 | { | |
7736 | exp = exp - 1023 + 127; | |
7737 | if (exp >= 0xFF) | |
7738 | { | |
7739 | /* Infinity. */ | |
7740 | exp = 0x7F; | |
7741 | mantissa = 0; | |
7742 | } | |
7743 | else if (exp < 0) | |
7744 | { | |
7745 | /* No denormalized numbers. */ | |
7746 | exp = 0; | |
7747 | mantissa = 0; | |
7748 | } | |
7749 | } | |
7750 | mantissa >>= 29; | |
7751 | return (sign << 31) | (exp << 23) | mantissa; | |
7752 | } | |
5fc177c8 | 7753 | #endif /* BFD_HOST_64_BIT */ |
ba592044 | 7754 | |
8335d6aa JW |
7755 | enum lit_type |
7756 | { | |
7757 | CONST_THUMB, | |
7758 | CONST_ARM, | |
7759 | CONST_VEC | |
7760 | }; | |
7761 | ||
ba592044 AM |
7762 | static void do_vfp_nsyn_opcode (const char *); |
7763 | ||
c19d1205 ZW |
7764 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7765 | Determine whether it can be performed with a move instruction; if | |
7766 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7767 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7768 | load and return FALSE. If this is not a valid thing to do in the | |
7769 | current context, set inst.error and return TRUE. | |
a737bd4d | 7770 | |
c19d1205 ZW |
7771 | inst.operands[i] describes the destination register. */ |
7772 | ||
c921be7d | 7773 | static bfd_boolean |
8335d6aa | 7774 | move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) |
c19d1205 | 7775 | { |
53365c0d | 7776 | unsigned long tbit; |
8335d6aa JW |
7777 | bfd_boolean thumb_p = (t == CONST_THUMB); |
7778 | bfd_boolean arm_p = (t == CONST_ARM); | |
53365c0d PB |
7779 | |
7780 | if (thumb_p) | |
7781 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7782 | else | |
7783 | tbit = LOAD_BIT; | |
7784 | ||
7785 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7786 | { |
c19d1205 | 7787 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7788 | return TRUE; |
09d92015 | 7789 | } |
ba592044 | 7790 | |
8335d6aa JW |
7791 | if (inst.reloc.exp.X_op != O_constant |
7792 | && inst.reloc.exp.X_op != O_symbol | |
7793 | && inst.reloc.exp.X_op != O_big) | |
09d92015 MM |
7794 | { |
7795 | inst.error = _("constant expression expected"); | |
c921be7d | 7796 | return TRUE; |
09d92015 | 7797 | } |
ba592044 AM |
7798 | |
7799 | if (inst.reloc.exp.X_op == O_constant | |
7800 | || inst.reloc.exp.X_op == O_big) | |
8335d6aa | 7801 | { |
5fc177c8 NC |
7802 | #if defined BFD_HOST_64_BIT |
7803 | bfd_int64_t v; | |
7804 | #else | |
ba592044 | 7805 | offsetT v; |
5fc177c8 | 7806 | #endif |
ba592044 | 7807 | if (inst.reloc.exp.X_op == O_big) |
8335d6aa | 7808 | { |
ba592044 AM |
7809 | LITTLENUM_TYPE w[X_PRECISION]; |
7810 | LITTLENUM_TYPE * l; | |
7811 | ||
7812 | if (inst.reloc.exp.X_add_number == -1) | |
8335d6aa | 7813 | { |
ba592044 AM |
7814 | gen_to_words (w, X_PRECISION, E_PRECISION); |
7815 | l = w; | |
7816 | /* FIXME: Should we check words w[2..5] ? */ | |
8335d6aa | 7817 | } |
ba592044 AM |
7818 | else |
7819 | l = generic_bignum; | |
3739860c | 7820 | |
5fc177c8 NC |
7821 | #if defined BFD_HOST_64_BIT |
7822 | v = | |
7823 | ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK) | |
7824 | << LITTLENUM_NUMBER_OF_BITS) | |
7825 | | ((bfd_int64_t) l[2] & LITTLENUM_MASK)) | |
7826 | << LITTLENUM_NUMBER_OF_BITS) | |
7827 | | ((bfd_int64_t) l[1] & LITTLENUM_MASK)) | |
7828 | << LITTLENUM_NUMBER_OF_BITS) | |
7829 | | ((bfd_int64_t) l[0] & LITTLENUM_MASK)); | |
7830 | #else | |
ba592044 AM |
7831 | v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS) |
7832 | | (l[0] & LITTLENUM_MASK); | |
5fc177c8 | 7833 | #endif |
8335d6aa | 7834 | } |
ba592044 AM |
7835 | else |
7836 | v = inst.reloc.exp.X_add_number; | |
7837 | ||
7838 | if (!inst.operands[i].issingle) | |
8335d6aa | 7839 | { |
12569877 | 7840 | if (thumb_p) |
8335d6aa | 7841 | { |
12569877 | 7842 | if ((v & ~0xFF) == 0) |
ba592044 AM |
7843 | { |
7844 | /* This can be done with a mov(1) instruction. */ | |
7845 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7846 | inst.instruction |= v; | |
7847 | return TRUE; | |
7848 | } | |
12569877 AM |
7849 | |
7850 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2) | |
7851 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) | |
7852 | { | |
7853 | /* Check if on thumb2 it can be done with a mov.w or mvn.w instruction. */ | |
7854 | unsigned int newimm; | |
7855 | bfd_boolean isNegated; | |
7856 | ||
7857 | newimm = encode_thumb32_immediate (v); | |
7858 | if (newimm != (unsigned int) FAIL) | |
7859 | isNegated = FALSE; | |
7860 | else | |
7861 | { | |
7862 | newimm = encode_thumb32_immediate (~ v); | |
7863 | if (newimm != (unsigned int) FAIL) | |
7864 | isNegated = TRUE; | |
7865 | } | |
7866 | ||
7867 | if (newimm != (unsigned int) FAIL) | |
7868 | { | |
7869 | inst.instruction = 0xf04f0000 | (inst.operands[i].reg << 8); | |
7870 | inst.instruction |= (isNegated?0x200000:0); | |
7871 | inst.instruction |= (newimm & 0x800) << 15; | |
7872 | inst.instruction |= (newimm & 0x700) << 4; | |
7873 | inst.instruction |= (newimm & 0x0ff); | |
7874 | return TRUE; | |
7875 | } | |
7876 | else if ((v & ~0xFFFF) == 0 || (v & ~0xFFFF0000) == 0) | |
3739860c | 7877 | { |
12569877 AM |
7878 | /* The number may be loaded with a movw/movt instruction. */ |
7879 | int imm; | |
7880 | ||
7881 | if ((inst.reloc.exp.X_add_number & ~0xFFFF) == 0) | |
7882 | { | |
7883 | inst.instruction= 0xf2400000; | |
7884 | imm = v; | |
7885 | } | |
7886 | else | |
7887 | { | |
7888 | inst.instruction = 0xf2c00000; | |
7889 | imm = v >> 16; | |
7890 | } | |
7891 | ||
7892 | inst.instruction |= (inst.operands[i].reg << 8); | |
7893 | inst.instruction |= (imm & 0xf000) << 4; | |
7894 | inst.instruction |= (imm & 0x0800) << 15; | |
7895 | inst.instruction |= (imm & 0x0700) << 4; | |
7896 | inst.instruction |= (imm & 0x00ff); | |
7897 | return TRUE; | |
7898 | } | |
7899 | } | |
8335d6aa | 7900 | } |
12569877 | 7901 | else if (arm_p) |
ba592044 AM |
7902 | { |
7903 | int value = encode_arm_immediate (v); | |
12569877 | 7904 | |
ba592044 AM |
7905 | if (value != FAIL) |
7906 | { | |
7907 | /* This can be done with a mov instruction. */ | |
7908 | inst.instruction &= LITERAL_MASK; | |
7909 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7910 | inst.instruction |= value & 0xfff; | |
7911 | return TRUE; | |
7912 | } | |
8335d6aa | 7913 | |
ba592044 AM |
7914 | value = encode_arm_immediate (~ v); |
7915 | if (value != FAIL) | |
7916 | { | |
7917 | /* This can be done with a mvn instruction. */ | |
7918 | inst.instruction &= LITERAL_MASK; | |
7919 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7920 | inst.instruction |= value & 0xfff; | |
7921 | return TRUE; | |
7922 | } | |
7923 | } | |
7924 | else if (t == CONST_VEC) | |
8335d6aa | 7925 | { |
ba592044 AM |
7926 | int op = 0; |
7927 | unsigned immbits = 0; | |
7928 | unsigned immlo = inst.operands[1].imm; | |
7929 | unsigned immhi = inst.operands[1].regisimm | |
7930 | ? inst.operands[1].reg | |
7931 | : inst.reloc.exp.X_unsigned | |
7932 | ? 0 | |
7933 | : ((bfd_int64_t)((int) immlo)) >> 32; | |
7934 | int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
7935 | &op, 64, NT_invtype); | |
7936 | ||
7937 | if (cmode == FAIL) | |
7938 | { | |
7939 | neon_invert_size (&immlo, &immhi, 64); | |
7940 | op = !op; | |
7941 | cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, | |
7942 | &op, 64, NT_invtype); | |
7943 | } | |
7944 | ||
7945 | if (cmode != FAIL) | |
7946 | { | |
7947 | inst.instruction = (inst.instruction & VLDR_VMOV_SAME) | |
7948 | | (1 << 23) | |
7949 | | (cmode << 8) | |
7950 | | (op << 5) | |
7951 | | (1 << 4); | |
7952 | ||
7953 | /* Fill other bits in vmov encoding for both thumb and arm. */ | |
7954 | if (thumb_mode) | |
eff0bc54 | 7955 | inst.instruction |= (0x7U << 29) | (0xF << 24); |
ba592044 | 7956 | else |
eff0bc54 | 7957 | inst.instruction |= (0xFU << 28) | (0x1 << 25); |
ba592044 AM |
7958 | neon_write_immbits (immbits); |
7959 | return TRUE; | |
7960 | } | |
8335d6aa JW |
7961 | } |
7962 | } | |
8335d6aa | 7963 | |
ba592044 AM |
7964 | if (t == CONST_VEC) |
7965 | { | |
7966 | /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */ | |
7967 | if (inst.operands[i].issingle | |
7968 | && is_quarter_float (inst.operands[1].imm) | |
7969 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd)) | |
8335d6aa | 7970 | { |
ba592044 AM |
7971 | inst.operands[1].imm = |
7972 | neon_qfloat_bits (v); | |
7973 | do_vfp_nsyn_opcode ("fconsts"); | |
7974 | return TRUE; | |
8335d6aa | 7975 | } |
5fc177c8 NC |
7976 | |
7977 | /* If our host does not support a 64-bit type then we cannot perform | |
7978 | the following optimization. This mean that there will be a | |
7979 | discrepancy between the output produced by an assembler built for | |
7980 | a 32-bit-only host and the output produced from a 64-bit host, but | |
7981 | this cannot be helped. */ | |
7982 | #if defined BFD_HOST_64_BIT | |
ba592044 AM |
7983 | else if (!inst.operands[1].issingle |
7984 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) | |
8335d6aa | 7985 | { |
ba592044 AM |
7986 | if (is_double_a_single (v) |
7987 | && is_quarter_float (double_to_single (v))) | |
7988 | { | |
7989 | inst.operands[1].imm = | |
7990 | neon_qfloat_bits (double_to_single (v)); | |
7991 | do_vfp_nsyn_opcode ("fconstd"); | |
7992 | return TRUE; | |
7993 | } | |
8335d6aa | 7994 | } |
5fc177c8 | 7995 | #endif |
8335d6aa JW |
7996 | } |
7997 | } | |
7998 | ||
7999 | if (add_to_lit_pool ((!inst.operands[i].isvec | |
8000 | || inst.operands[i].issingle) ? 4 : 8) == FAIL) | |
8001 | return TRUE; | |
8002 | ||
8003 | inst.operands[1].reg = REG_PC; | |
8004 | inst.operands[1].isreg = 1; | |
8005 | inst.operands[1].preind = 1; | |
8006 | inst.reloc.pc_rel = 1; | |
8007 | inst.reloc.type = (thumb_p | |
8008 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
8009 | : (mode_3 | |
8010 | ? BFD_RELOC_ARM_HWLITERAL | |
8011 | : BFD_RELOC_ARM_LITERAL)); | |
8012 | return FALSE; | |
8013 | } | |
8014 | ||
8015 | /* inst.operands[i] was set up by parse_address. Encode it into an | |
8016 | ARM-format instruction. Reject all forms which cannot be encoded | |
8017 | into a coprocessor load/store instruction. If wb_ok is false, | |
8018 | reject use of writeback; if unind_ok is false, reject use of | |
8019 | unindexed addressing. If reloc_override is not 0, use it instead | |
8020 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one | |
8021 | (in which case it is preserved). */ | |
8022 | ||
8023 | static int | |
8024 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
8025 | { | |
8026 | if (!inst.operands[i].isreg) | |
8027 | { | |
99b2a2dd NC |
8028 | /* PR 18256 */ |
8029 | if (! inst.operands[0].isvec) | |
8030 | { | |
8031 | inst.error = _("invalid co-processor operand"); | |
8032 | return FAIL; | |
8033 | } | |
8335d6aa JW |
8034 | if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) |
8035 | return SUCCESS; | |
8036 | } | |
8037 | ||
8038 | inst.instruction |= inst.operands[i].reg << 16; | |
8039 | ||
8040 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); | |
8041 | ||
8042 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ | |
8043 | { | |
8044 | gas_assert (!inst.operands[i].writeback); | |
8045 | if (!unind_ok) | |
8046 | { | |
8047 | inst.error = _("instruction does not support unindexed addressing"); | |
8048 | return FAIL; | |
8049 | } | |
8050 | inst.instruction |= inst.operands[i].imm; | |
8051 | inst.instruction |= INDEX_UP; | |
8052 | return SUCCESS; | |
8053 | } | |
8054 | ||
8055 | if (inst.operands[i].preind) | |
8056 | inst.instruction |= PRE_INDEX; | |
8057 | ||
8058 | if (inst.operands[i].writeback) | |
09d92015 | 8059 | { |
8335d6aa | 8060 | if (inst.operands[i].reg == REG_PC) |
c19d1205 | 8061 | { |
8335d6aa JW |
8062 | inst.error = _("pc may not be used with write-back"); |
8063 | return FAIL; | |
c19d1205 | 8064 | } |
8335d6aa | 8065 | if (!wb_ok) |
c19d1205 | 8066 | { |
8335d6aa JW |
8067 | inst.error = _("instruction does not support writeback"); |
8068 | return FAIL; | |
c19d1205 | 8069 | } |
8335d6aa | 8070 | inst.instruction |= WRITE_BACK; |
09d92015 MM |
8071 | } |
8072 | ||
8335d6aa JW |
8073 | if (reloc_override) |
8074 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; | |
8075 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC | |
8076 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
8077 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
c19d1205 | 8078 | { |
8335d6aa JW |
8079 | if (thumb_mode) |
8080 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
8081 | else | |
8082 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
c19d1205 | 8083 | } |
8335d6aa JW |
8084 | |
8085 | /* Prefer + for zero encoded value. */ | |
8086 | if (!inst.operands[i].negative) | |
8087 | inst.instruction |= INDEX_UP; | |
8088 | ||
8089 | return SUCCESS; | |
09d92015 MM |
8090 | } |
8091 | ||
5f4273c7 | 8092 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
8093 | First some generics; their names are taken from the conventional |
8094 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 8095 | |
a737bd4d | 8096 | static void |
c19d1205 | 8097 | do_noargs (void) |
09d92015 | 8098 | { |
c19d1205 | 8099 | } |
a737bd4d | 8100 | |
c19d1205 ZW |
8101 | static void |
8102 | do_rd (void) | |
8103 | { | |
8104 | inst.instruction |= inst.operands[0].reg << 12; | |
8105 | } | |
a737bd4d | 8106 | |
c19d1205 ZW |
8107 | static void |
8108 | do_rd_rm (void) | |
8109 | { | |
8110 | inst.instruction |= inst.operands[0].reg << 12; | |
8111 | inst.instruction |= inst.operands[1].reg; | |
8112 | } | |
09d92015 | 8113 | |
9eb6c0f1 MGD |
8114 | static void |
8115 | do_rm_rn (void) | |
8116 | { | |
8117 | inst.instruction |= inst.operands[0].reg; | |
8118 | inst.instruction |= inst.operands[1].reg << 16; | |
8119 | } | |
8120 | ||
c19d1205 ZW |
8121 | static void |
8122 | do_rd_rn (void) | |
8123 | { | |
8124 | inst.instruction |= inst.operands[0].reg << 12; | |
8125 | inst.instruction |= inst.operands[1].reg << 16; | |
8126 | } | |
a737bd4d | 8127 | |
c19d1205 ZW |
8128 | static void |
8129 | do_rn_rd (void) | |
8130 | { | |
8131 | inst.instruction |= inst.operands[0].reg << 16; | |
8132 | inst.instruction |= inst.operands[1].reg << 12; | |
8133 | } | |
09d92015 | 8134 | |
59d09be6 MGD |
8135 | static bfd_boolean |
8136 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
8137 | { | |
8138 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
8139 | { | |
5c3696f8 | 8140 | as_tsktsk ("%s", msg); |
59d09be6 MGD |
8141 | return TRUE; |
8142 | } | |
8143 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
8144 | { | |
8145 | as_bad ("%s", msg); | |
8146 | return TRUE; | |
8147 | } | |
8148 | ||
8149 | return FALSE; | |
8150 | } | |
8151 | ||
c19d1205 ZW |
8152 | static void |
8153 | do_rd_rm_rn (void) | |
8154 | { | |
9a64e435 | 8155 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 8156 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 8157 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
8158 | { |
8159 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
8160 | _("Rn must not overlap other operands")); | |
8161 | ||
59d09be6 MGD |
8162 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
8163 | */ | |
8164 | if (!check_obsolete (&arm_ext_v8, | |
8165 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
8166 | && warn_on_deprecated | |
8167 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
5c3696f8 | 8168 | as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7")); |
56adecf4 | 8169 | } |
59d09be6 | 8170 | |
c19d1205 ZW |
8171 | inst.instruction |= inst.operands[0].reg << 12; |
8172 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 8173 | inst.instruction |= Rn << 16; |
c19d1205 | 8174 | } |
09d92015 | 8175 | |
c19d1205 ZW |
8176 | static void |
8177 | do_rd_rn_rm (void) | |
8178 | { | |
8179 | inst.instruction |= inst.operands[0].reg << 12; | |
8180 | inst.instruction |= inst.operands[1].reg << 16; | |
8181 | inst.instruction |= inst.operands[2].reg; | |
8182 | } | |
a737bd4d | 8183 | |
c19d1205 ZW |
8184 | static void |
8185 | do_rm_rd_rn (void) | |
8186 | { | |
5be8be5d DG |
8187 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
8188 | constraint (((inst.reloc.exp.X_op != O_constant | |
8189 | && inst.reloc.exp.X_op != O_illegal) | |
8190 | || inst.reloc.exp.X_add_number != 0), | |
8191 | BAD_ADDR_MODE); | |
c19d1205 ZW |
8192 | inst.instruction |= inst.operands[0].reg; |
8193 | inst.instruction |= inst.operands[1].reg << 12; | |
8194 | inst.instruction |= inst.operands[2].reg << 16; | |
8195 | } | |
09d92015 | 8196 | |
c19d1205 ZW |
8197 | static void |
8198 | do_imm0 (void) | |
8199 | { | |
8200 | inst.instruction |= inst.operands[0].imm; | |
8201 | } | |
09d92015 | 8202 | |
c19d1205 ZW |
8203 | static void |
8204 | do_rd_cpaddr (void) | |
8205 | { | |
8206 | inst.instruction |= inst.operands[0].reg << 12; | |
8207 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 8208 | } |
a737bd4d | 8209 | |
c19d1205 ZW |
8210 | /* ARM instructions, in alphabetical order by function name (except |
8211 | that wrapper functions appear immediately after the function they | |
8212 | wrap). */ | |
09d92015 | 8213 | |
c19d1205 ZW |
8214 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
8215 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
8216 | |
8217 | static void | |
c19d1205 | 8218 | do_adr (void) |
09d92015 | 8219 | { |
c19d1205 | 8220 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 8221 | |
c19d1205 ZW |
8222 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8223 | out to be negative. */ | |
8224 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 8225 | inst.reloc.pc_rel = 1; |
2fc8bdac | 8226 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 8227 | } |
b99bd4ef | 8228 | |
c19d1205 ZW |
8229 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
8230 | into a relative address of the form: | |
8231 | add rd, pc, #low(label-.-8)" | |
8232 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 8233 | |
c19d1205 ZW |
8234 | static void |
8235 | do_adrl (void) | |
8236 | { | |
8237 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 8238 | |
c19d1205 ZW |
8239 | /* Frag hacking will turn this into a sub instruction if the offset turns |
8240 | out to be negative. */ | |
8241 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
8242 | inst.reloc.pc_rel = 1; |
8243 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 8244 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
8245 | } |
8246 | ||
b99bd4ef | 8247 | static void |
c19d1205 | 8248 | do_arit (void) |
b99bd4ef | 8249 | { |
c19d1205 ZW |
8250 | if (!inst.operands[1].present) |
8251 | inst.operands[1].reg = inst.operands[0].reg; | |
8252 | inst.instruction |= inst.operands[0].reg << 12; | |
8253 | inst.instruction |= inst.operands[1].reg << 16; | |
8254 | encode_arm_shifter_operand (2); | |
8255 | } | |
b99bd4ef | 8256 | |
62b3e311 PB |
8257 | static void |
8258 | do_barrier (void) | |
8259 | { | |
8260 | if (inst.operands[0].present) | |
ccb84d65 | 8261 | inst.instruction |= inst.operands[0].imm; |
62b3e311 PB |
8262 | else |
8263 | inst.instruction |= 0xf; | |
8264 | } | |
8265 | ||
c19d1205 ZW |
8266 | static void |
8267 | do_bfc (void) | |
8268 | { | |
8269 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
8270 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8271 | /* The instruction encoding stores the LSB and MSB, | |
8272 | not the LSB and width. */ | |
8273 | inst.instruction |= inst.operands[0].reg << 12; | |
8274 | inst.instruction |= inst.operands[1].imm << 7; | |
8275 | inst.instruction |= (msb - 1) << 16; | |
8276 | } | |
b99bd4ef | 8277 | |
c19d1205 ZW |
8278 | static void |
8279 | do_bfi (void) | |
8280 | { | |
8281 | unsigned int msb; | |
b99bd4ef | 8282 | |
c19d1205 ZW |
8283 | /* #0 in second position is alternative syntax for bfc, which is |
8284 | the same instruction but with REG_PC in the Rm field. */ | |
8285 | if (!inst.operands[1].isreg) | |
8286 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 8287 | |
c19d1205 ZW |
8288 | msb = inst.operands[2].imm + inst.operands[3].imm; |
8289 | constraint (msb > 32, _("bit-field extends past end of register")); | |
8290 | /* The instruction encoding stores the LSB and MSB, | |
8291 | not the LSB and width. */ | |
8292 | inst.instruction |= inst.operands[0].reg << 12; | |
8293 | inst.instruction |= inst.operands[1].reg; | |
8294 | inst.instruction |= inst.operands[2].imm << 7; | |
8295 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
8296 | } |
8297 | ||
b99bd4ef | 8298 | static void |
c19d1205 | 8299 | do_bfx (void) |
b99bd4ef | 8300 | { |
c19d1205 ZW |
8301 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
8302 | _("bit-field extends past end of register")); | |
8303 | inst.instruction |= inst.operands[0].reg << 12; | |
8304 | inst.instruction |= inst.operands[1].reg; | |
8305 | inst.instruction |= inst.operands[2].imm << 7; | |
8306 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
8307 | } | |
09d92015 | 8308 | |
c19d1205 ZW |
8309 | /* ARM V5 breakpoint instruction (argument parse) |
8310 | BKPT <16 bit unsigned immediate> | |
8311 | Instruction is not conditional. | |
8312 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
8313 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 8314 | |
c19d1205 ZW |
8315 | static void |
8316 | do_bkpt (void) | |
8317 | { | |
8318 | /* Top 12 of 16 bits to bits 19:8. */ | |
8319 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 8320 | |
c19d1205 ZW |
8321 | /* Bottom 4 of 16 bits to bits 3:0. */ |
8322 | inst.instruction |= inst.operands[0].imm & 0xf; | |
8323 | } | |
09d92015 | 8324 | |
c19d1205 ZW |
8325 | static void |
8326 | encode_branch (int default_reloc) | |
8327 | { | |
8328 | if (inst.operands[0].hasreloc) | |
8329 | { | |
0855e32b NS |
8330 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
8331 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
8332 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
8333 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
8334 | ? BFD_RELOC_ARM_PLT32 | |
8335 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 8336 | } |
b99bd4ef | 8337 | else |
9ae92b05 | 8338 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 8339 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
8340 | } |
8341 | ||
b99bd4ef | 8342 | static void |
c19d1205 | 8343 | do_branch (void) |
b99bd4ef | 8344 | { |
39b41c9c PB |
8345 | #ifdef OBJ_ELF |
8346 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8347 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8348 | else | |
8349 | #endif | |
8350 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
8351 | } | |
8352 | ||
8353 | static void | |
8354 | do_bl (void) | |
8355 | { | |
8356 | #ifdef OBJ_ELF | |
8357 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
8358 | { | |
8359 | if (inst.cond == COND_ALWAYS) | |
8360 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
8361 | else | |
8362 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
8363 | } | |
8364 | else | |
8365 | #endif | |
8366 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 8367 | } |
b99bd4ef | 8368 | |
c19d1205 ZW |
8369 | /* ARM V5 branch-link-exchange instruction (argument parse) |
8370 | BLX <target_addr> ie BLX(1) | |
8371 | BLX{<condition>} <Rm> ie BLX(2) | |
8372 | Unfortunately, there are two different opcodes for this mnemonic. | |
8373 | So, the insns[].value is not used, and the code here zaps values | |
8374 | into inst.instruction. | |
8375 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 8376 | |
c19d1205 ZW |
8377 | static void |
8378 | do_blx (void) | |
8379 | { | |
8380 | if (inst.operands[0].isreg) | |
b99bd4ef | 8381 | { |
c19d1205 ZW |
8382 | /* Arg is a register; the opcode provided by insns[] is correct. |
8383 | It is not illegal to do "blx pc", just useless. */ | |
8384 | if (inst.operands[0].reg == REG_PC) | |
8385 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 8386 | |
c19d1205 ZW |
8387 | inst.instruction |= inst.operands[0].reg; |
8388 | } | |
8389 | else | |
b99bd4ef | 8390 | { |
c19d1205 | 8391 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
8392 | conditionally, and the opcode must be adjusted. |
8393 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
8394 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 8395 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 8396 | inst.instruction = 0xfa000000; |
267bf995 | 8397 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 8398 | } |
c19d1205 ZW |
8399 | } |
8400 | ||
8401 | static void | |
8402 | do_bx (void) | |
8403 | { | |
845b51d6 PB |
8404 | bfd_boolean want_reloc; |
8405 | ||
c19d1205 ZW |
8406 | if (inst.operands[0].reg == REG_PC) |
8407 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 8408 | |
c19d1205 | 8409 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
8410 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
8411 | it is for ARMv4t or earlier. */ | |
8412 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
8413 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
8414 | want_reloc = TRUE; | |
8415 | ||
5ad34203 | 8416 | #ifdef OBJ_ELF |
845b51d6 | 8417 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 8418 | #endif |
584206db | 8419 | want_reloc = FALSE; |
845b51d6 PB |
8420 | |
8421 | if (want_reloc) | |
8422 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
8423 | } |
8424 | ||
c19d1205 ZW |
8425 | |
8426 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
8427 | |
8428 | static void | |
c19d1205 | 8429 | do_bxj (void) |
a737bd4d | 8430 | { |
c19d1205 ZW |
8431 | if (inst.operands[0].reg == REG_PC) |
8432 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
8433 | ||
8434 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
8435 | } |
8436 | ||
c19d1205 ZW |
8437 | /* Co-processor data operation: |
8438 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
8439 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
8440 | static void | |
8441 | do_cdp (void) | |
8442 | { | |
8443 | inst.instruction |= inst.operands[0].reg << 8; | |
8444 | inst.instruction |= inst.operands[1].imm << 20; | |
8445 | inst.instruction |= inst.operands[2].reg << 12; | |
8446 | inst.instruction |= inst.operands[3].reg << 16; | |
8447 | inst.instruction |= inst.operands[4].reg; | |
8448 | inst.instruction |= inst.operands[5].imm << 5; | |
8449 | } | |
a737bd4d NC |
8450 | |
8451 | static void | |
c19d1205 | 8452 | do_cmp (void) |
a737bd4d | 8453 | { |
c19d1205 ZW |
8454 | inst.instruction |= inst.operands[0].reg << 16; |
8455 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
8456 | } |
8457 | ||
c19d1205 ZW |
8458 | /* Transfer between coprocessor and ARM registers. |
8459 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
8460 | MRC2 | |
8461 | MCR{cond} | |
8462 | MCR2 | |
8463 | ||
8464 | No special properties. */ | |
09d92015 | 8465 | |
dcbd0d71 MGD |
8466 | struct deprecated_coproc_regs_s |
8467 | { | |
8468 | unsigned cp; | |
8469 | int opc1; | |
8470 | unsigned crn; | |
8471 | unsigned crm; | |
8472 | int opc2; | |
8473 | arm_feature_set deprecated; | |
8474 | arm_feature_set obsoleted; | |
8475 | const char *dep_msg; | |
8476 | const char *obs_msg; | |
8477 | }; | |
8478 | ||
8479 | #define DEPR_ACCESS_V8 \ | |
8480 | N_("This coprocessor register access is deprecated in ARMv8") | |
8481 | ||
8482 | /* Table of all deprecated coprocessor registers. */ | |
8483 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
8484 | { | |
8485 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
823d2571 | 8486 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8487 | DEPR_ACCESS_V8, NULL}, |
8488 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
823d2571 | 8489 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8490 | DEPR_ACCESS_V8, NULL}, |
8491 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
823d2571 | 8492 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8493 | DEPR_ACCESS_V8, NULL}, |
8494 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
823d2571 | 8495 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8496 | DEPR_ACCESS_V8, NULL}, |
8497 | {14, 6, 0, 0, 0, /* TEECR. */ | |
823d2571 | 8498 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE, |
dcbd0d71 MGD |
8499 | DEPR_ACCESS_V8, NULL}, |
8500 | }; | |
8501 | ||
8502 | #undef DEPR_ACCESS_V8 | |
8503 | ||
8504 | static const size_t deprecated_coproc_reg_count = | |
8505 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
8506 | ||
09d92015 | 8507 | static void |
c19d1205 | 8508 | do_co_reg (void) |
09d92015 | 8509 | { |
fdfde340 | 8510 | unsigned Rd; |
dcbd0d71 | 8511 | size_t i; |
fdfde340 JM |
8512 | |
8513 | Rd = inst.operands[2].reg; | |
8514 | if (thumb_mode) | |
8515 | { | |
8516 | if (inst.instruction == 0xee000010 | |
8517 | || inst.instruction == 0xfe000010) | |
8518 | /* MCR, MCR2 */ | |
8519 | reject_bad_reg (Rd); | |
8520 | else | |
8521 | /* MRC, MRC2 */ | |
8522 | constraint (Rd == REG_SP, BAD_SP); | |
8523 | } | |
8524 | else | |
8525 | { | |
8526 | /* MCR */ | |
8527 | if (inst.instruction == 0xe000010) | |
8528 | constraint (Rd == REG_PC, BAD_PC); | |
8529 | } | |
8530 | ||
dcbd0d71 MGD |
8531 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
8532 | { | |
8533 | const struct deprecated_coproc_regs_s *r = | |
8534 | deprecated_coproc_regs + i; | |
8535 | ||
8536 | if (inst.operands[0].reg == r->cp | |
8537 | && inst.operands[1].imm == r->opc1 | |
8538 | && inst.operands[3].reg == r->crn | |
8539 | && inst.operands[4].reg == r->crm | |
8540 | && inst.operands[5].imm == r->opc2) | |
8541 | { | |
b10bf8c5 | 8542 | if (! ARM_CPU_IS_ANY (cpu_variant) |
477330fc | 8543 | && warn_on_deprecated |
dcbd0d71 | 8544 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) |
5c3696f8 | 8545 | as_tsktsk ("%s", r->dep_msg); |
dcbd0d71 MGD |
8546 | } |
8547 | } | |
fdfde340 | 8548 | |
c19d1205 ZW |
8549 | inst.instruction |= inst.operands[0].reg << 8; |
8550 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 8551 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
8552 | inst.instruction |= inst.operands[3].reg << 16; |
8553 | inst.instruction |= inst.operands[4].reg; | |
8554 | inst.instruction |= inst.operands[5].imm << 5; | |
8555 | } | |
09d92015 | 8556 | |
c19d1205 ZW |
8557 | /* Transfer between coprocessor register and pair of ARM registers. |
8558 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
8559 | MCRR2 | |
8560 | MRRC{cond} | |
8561 | MRRC2 | |
b99bd4ef | 8562 | |
c19d1205 | 8563 | Two XScale instructions are special cases of these: |
09d92015 | 8564 | |
c19d1205 ZW |
8565 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
8566 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 8567 | |
5f4273c7 | 8568 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 8569 | |
c19d1205 ZW |
8570 | static void |
8571 | do_co_reg2c (void) | |
8572 | { | |
fdfde340 JM |
8573 | unsigned Rd, Rn; |
8574 | ||
8575 | Rd = inst.operands[2].reg; | |
8576 | Rn = inst.operands[3].reg; | |
8577 | ||
8578 | if (thumb_mode) | |
8579 | { | |
8580 | reject_bad_reg (Rd); | |
8581 | reject_bad_reg (Rn); | |
8582 | } | |
8583 | else | |
8584 | { | |
8585 | constraint (Rd == REG_PC, BAD_PC); | |
8586 | constraint (Rn == REG_PC, BAD_PC); | |
8587 | } | |
8588 | ||
c19d1205 ZW |
8589 | inst.instruction |= inst.operands[0].reg << 8; |
8590 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
8591 | inst.instruction |= Rd << 12; |
8592 | inst.instruction |= Rn << 16; | |
c19d1205 | 8593 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
8594 | } |
8595 | ||
c19d1205 ZW |
8596 | static void |
8597 | do_cpsi (void) | |
8598 | { | |
8599 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
8600 | if (inst.operands[1].present) |
8601 | { | |
8602 | inst.instruction |= CPSI_MMOD; | |
8603 | inst.instruction |= inst.operands[1].imm; | |
8604 | } | |
c19d1205 | 8605 | } |
b99bd4ef | 8606 | |
62b3e311 PB |
8607 | static void |
8608 | do_dbg (void) | |
8609 | { | |
8610 | inst.instruction |= inst.operands[0].imm; | |
8611 | } | |
8612 | ||
eea54501 MGD |
8613 | static void |
8614 | do_div (void) | |
8615 | { | |
8616 | unsigned Rd, Rn, Rm; | |
8617 | ||
8618 | Rd = inst.operands[0].reg; | |
8619 | Rn = (inst.operands[1].present | |
8620 | ? inst.operands[1].reg : Rd); | |
8621 | Rm = inst.operands[2].reg; | |
8622 | ||
8623 | constraint ((Rd == REG_PC), BAD_PC); | |
8624 | constraint ((Rn == REG_PC), BAD_PC); | |
8625 | constraint ((Rm == REG_PC), BAD_PC); | |
8626 | ||
8627 | inst.instruction |= Rd << 16; | |
8628 | inst.instruction |= Rn << 0; | |
8629 | inst.instruction |= Rm << 8; | |
8630 | } | |
8631 | ||
b99bd4ef | 8632 | static void |
c19d1205 | 8633 | do_it (void) |
b99bd4ef | 8634 | { |
c19d1205 | 8635 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
8636 | process it to do the validation as if in |
8637 | thumb mode, just in case the code gets | |
8638 | assembled for thumb using the unified syntax. */ | |
8639 | ||
c19d1205 | 8640 | inst.size = 0; |
e07e6e58 NC |
8641 | if (unified_syntax) |
8642 | { | |
8643 | set_it_insn_type (IT_INSN); | |
8644 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
8645 | now_it.cc = inst.operands[0].imm; | |
8646 | } | |
09d92015 | 8647 | } |
b99bd4ef | 8648 | |
6530b175 NC |
8649 | /* If there is only one register in the register list, |
8650 | then return its register number. Otherwise return -1. */ | |
8651 | static int | |
8652 | only_one_reg_in_list (int range) | |
8653 | { | |
8654 | int i = ffs (range) - 1; | |
8655 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
8656 | } | |
8657 | ||
09d92015 | 8658 | static void |
6530b175 | 8659 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 8660 | { |
c19d1205 ZW |
8661 | int base_reg = inst.operands[0].reg; |
8662 | int range = inst.operands[1].imm; | |
6530b175 | 8663 | int one_reg; |
ea6ef066 | 8664 | |
c19d1205 ZW |
8665 | inst.instruction |= base_reg << 16; |
8666 | inst.instruction |= range; | |
ea6ef066 | 8667 | |
c19d1205 ZW |
8668 | if (inst.operands[1].writeback) |
8669 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 8670 | |
c19d1205 | 8671 | if (inst.operands[0].writeback) |
ea6ef066 | 8672 | { |
c19d1205 ZW |
8673 | inst.instruction |= WRITE_BACK; |
8674 | /* Check for unpredictable uses of writeback. */ | |
8675 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 8676 | { |
c19d1205 ZW |
8677 | /* Not allowed in LDM type 2. */ |
8678 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
8679 | && ((range & (1 << REG_PC)) == 0)) | |
8680 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8681 | /* Only allowed if base reg not in list for other types. */ | |
8682 | else if (range & (1 << base_reg)) | |
8683 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
8684 | } | |
8685 | else /* STM. */ | |
8686 | { | |
8687 | /* Not allowed for type 2. */ | |
8688 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
8689 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
8690 | /* Only allowed if base reg not in list, or first in list. */ | |
8691 | else if ((range & (1 << base_reg)) | |
8692 | && (range & ((1 << base_reg) - 1))) | |
8693 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 8694 | } |
ea6ef066 | 8695 | } |
6530b175 NC |
8696 | |
8697 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
8698 | one_reg = only_one_reg_in_list (range); | |
8699 | if (from_push_pop_mnem && one_reg >= 0) | |
8700 | { | |
8701 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
8702 | ||
8703 | inst.instruction &= A_COND_MASK; | |
8704 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
8705 | inst.instruction |= one_reg << 12; | |
8706 | } | |
8707 | } | |
8708 | ||
8709 | static void | |
8710 | do_ldmstm (void) | |
8711 | { | |
8712 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
8713 | } |
8714 | ||
c19d1205 ZW |
8715 | /* ARMv5TE load-consecutive (argument parse) |
8716 | Mode is like LDRH. | |
8717 | ||
8718 | LDRccD R, mode | |
8719 | STRccD R, mode. */ | |
8720 | ||
a737bd4d | 8721 | static void |
c19d1205 | 8722 | do_ldrd (void) |
a737bd4d | 8723 | { |
c19d1205 | 8724 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 8725 | _("first transfer register must be even")); |
c19d1205 ZW |
8726 | constraint (inst.operands[1].present |
8727 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 8728 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
8729 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
8730 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 8731 | |
c19d1205 ZW |
8732 | if (!inst.operands[1].present) |
8733 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 8734 | |
c56791bb RE |
8735 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
8736 | register and the first register written; we have to diagnose | |
8737 | overlap between the base and the second register written here. */ | |
ea6ef066 | 8738 | |
c56791bb RE |
8739 | if (inst.operands[2].reg == inst.operands[1].reg |
8740 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
8741 | as_warn (_("base register written back, and overlaps " | |
8742 | "second transfer register")); | |
b05fe5cf | 8743 | |
c56791bb RE |
8744 | if (!(inst.instruction & V4_STR_BIT)) |
8745 | { | |
c19d1205 | 8746 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
8747 | destination (even if not write-back). */ |
8748 | if (inst.operands[2].immisreg | |
8749 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
8750 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
8751 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 8752 | } |
c19d1205 ZW |
8753 | inst.instruction |= inst.operands[0].reg << 12; |
8754 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8755 | } |
8756 | ||
8757 | static void | |
c19d1205 | 8758 | do_ldrex (void) |
b05fe5cf | 8759 | { |
c19d1205 ZW |
8760 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8761 | || inst.operands[1].postind || inst.operands[1].writeback | |
8762 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8763 | || inst.operands[1].negative |
8764 | /* This can arise if the programmer has written | |
8765 | strex rN, rM, foo | |
8766 | or if they have mistakenly used a register name as the last | |
8767 | operand, eg: | |
8768 | strex rN, rM, rX | |
8769 | It is very difficult to distinguish between these two cases | |
8770 | because "rX" might actually be a label. ie the register | |
8771 | name has been occluded by a symbol of the same name. So we | |
8772 | just generate a general 'bad addressing mode' type error | |
8773 | message and leave it up to the programmer to discover the | |
8774 | true cause and fix their mistake. */ | |
8775 | || (inst.operands[1].reg == REG_PC), | |
8776 | BAD_ADDR_MODE); | |
b05fe5cf | 8777 | |
c19d1205 ZW |
8778 | constraint (inst.reloc.exp.X_op != O_constant |
8779 | || inst.reloc.exp.X_add_number != 0, | |
8780 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 8781 | |
5be8be5d DG |
8782 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
8783 | ||
c19d1205 ZW |
8784 | inst.instruction |= inst.operands[0].reg << 12; |
8785 | inst.instruction |= inst.operands[1].reg << 16; | |
8786 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
8787 | } |
8788 | ||
8789 | static void | |
c19d1205 | 8790 | do_ldrexd (void) |
b05fe5cf | 8791 | { |
c19d1205 ZW |
8792 | constraint (inst.operands[0].reg % 2 != 0, |
8793 | _("even register required")); | |
8794 | constraint (inst.operands[1].present | |
8795 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
8796 | _("can only load two consecutive registers")); | |
8797 | /* If op 1 were present and equal to PC, this function wouldn't | |
8798 | have been called in the first place. */ | |
8799 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 8800 | |
c19d1205 ZW |
8801 | inst.instruction |= inst.operands[0].reg << 12; |
8802 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
8803 | } |
8804 | ||
1be5fd2e NC |
8805 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
8806 | which is not a multiple of four is UNPREDICTABLE. */ | |
8807 | static void | |
8808 | check_ldr_r15_aligned (void) | |
8809 | { | |
8810 | constraint (!(inst.operands[1].immisreg) | |
8811 | && (inst.operands[0].reg == REG_PC | |
8812 | && inst.operands[1].reg == REG_PC | |
8813 | && (inst.reloc.exp.X_add_number & 0x3)), | |
8814 | _("ldr to register 15 must be 4-byte alligned")); | |
8815 | } | |
8816 | ||
b05fe5cf | 8817 | static void |
c19d1205 | 8818 | do_ldst (void) |
b05fe5cf | 8819 | { |
c19d1205 ZW |
8820 | inst.instruction |= inst.operands[0].reg << 12; |
8821 | if (!inst.operands[1].isreg) | |
8335d6aa | 8822 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) |
b05fe5cf | 8823 | return; |
c19d1205 | 8824 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 8825 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
8826 | } |
8827 | ||
8828 | static void | |
c19d1205 | 8829 | do_ldstt (void) |
b05fe5cf | 8830 | { |
c19d1205 ZW |
8831 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8832 | reject [Rn,...]. */ | |
8833 | if (inst.operands[1].preind) | |
b05fe5cf | 8834 | { |
bd3ba5d1 NC |
8835 | constraint (inst.reloc.exp.X_op != O_constant |
8836 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8837 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8838 | |
c19d1205 ZW |
8839 | inst.operands[1].preind = 0; |
8840 | inst.operands[1].postind = 1; | |
8841 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8842 | } |
c19d1205 ZW |
8843 | inst.instruction |= inst.operands[0].reg << 12; |
8844 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
8845 | } | |
b05fe5cf | 8846 | |
c19d1205 | 8847 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 8848 | |
c19d1205 ZW |
8849 | static void |
8850 | do_ldstv4 (void) | |
8851 | { | |
ff4a8d2b | 8852 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
8853 | inst.instruction |= inst.operands[0].reg << 12; |
8854 | if (!inst.operands[1].isreg) | |
8335d6aa | 8855 | if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) |
b05fe5cf | 8856 | return; |
c19d1205 | 8857 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
8858 | } |
8859 | ||
8860 | static void | |
c19d1205 | 8861 | do_ldsttv4 (void) |
b05fe5cf | 8862 | { |
c19d1205 ZW |
8863 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8864 | reject [Rn,...]. */ | |
8865 | if (inst.operands[1].preind) | |
b05fe5cf | 8866 | { |
bd3ba5d1 NC |
8867 | constraint (inst.reloc.exp.X_op != O_constant |
8868 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8869 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8870 | |
c19d1205 ZW |
8871 | inst.operands[1].preind = 0; |
8872 | inst.operands[1].postind = 1; | |
8873 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8874 | } |
c19d1205 ZW |
8875 | inst.instruction |= inst.operands[0].reg << 12; |
8876 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
8877 | } | |
b05fe5cf | 8878 | |
c19d1205 ZW |
8879 | /* Co-processor register load/store. |
8880 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8881 | static void | |
8882 | do_lstc (void) | |
8883 | { | |
8884 | inst.instruction |= inst.operands[0].reg << 8; | |
8885 | inst.instruction |= inst.operands[1].reg << 12; | |
8886 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8887 | } |
8888 | ||
b05fe5cf | 8889 | static void |
c19d1205 | 8890 | do_mlas (void) |
b05fe5cf | 8891 | { |
8fb9d7b9 | 8892 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8893 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8894 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8895 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8896 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8897 | |
c19d1205 ZW |
8898 | inst.instruction |= inst.operands[0].reg << 16; |
8899 | inst.instruction |= inst.operands[1].reg; | |
8900 | inst.instruction |= inst.operands[2].reg << 8; | |
8901 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8902 | } |
b05fe5cf | 8903 | |
c19d1205 ZW |
8904 | static void |
8905 | do_mov (void) | |
8906 | { | |
8907 | inst.instruction |= inst.operands[0].reg << 12; | |
8908 | encode_arm_shifter_operand (1); | |
8909 | } | |
b05fe5cf | 8910 | |
c19d1205 ZW |
8911 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8912 | static void | |
8913 | do_mov16 (void) | |
8914 | { | |
b6895b4f PB |
8915 | bfd_vma imm; |
8916 | bfd_boolean top; | |
8917 | ||
8918 | top = (inst.instruction & 0x00400000) != 0; | |
8919 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8920 | _(":lower16: not allowed this instruction")); | |
8921 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8922 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8923 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8924 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8925 | { | |
8926 | imm = inst.reloc.exp.X_add_number; | |
8927 | /* The value is in two pieces: 0:11, 16:19. */ | |
8928 | inst.instruction |= (imm & 0x00000fff); | |
8929 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8930 | } | |
b05fe5cf | 8931 | } |
b99bd4ef | 8932 | |
037e8744 JB |
8933 | static int |
8934 | do_vfp_nsyn_mrs (void) | |
8935 | { | |
8936 | if (inst.operands[0].isvec) | |
8937 | { | |
8938 | if (inst.operands[1].reg != 1) | |
477330fc | 8939 | first_error (_("operand 1 must be FPSCR")); |
037e8744 JB |
8940 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); |
8941 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8942 | do_vfp_nsyn_opcode ("fmstat"); | |
8943 | } | |
8944 | else if (inst.operands[1].isvec) | |
8945 | do_vfp_nsyn_opcode ("fmrx"); | |
8946 | else | |
8947 | return FAIL; | |
5f4273c7 | 8948 | |
037e8744 JB |
8949 | return SUCCESS; |
8950 | } | |
8951 | ||
8952 | static int | |
8953 | do_vfp_nsyn_msr (void) | |
8954 | { | |
8955 | if (inst.operands[0].isvec) | |
8956 | do_vfp_nsyn_opcode ("fmxr"); | |
8957 | else | |
8958 | return FAIL; | |
8959 | ||
8960 | return SUCCESS; | |
8961 | } | |
8962 | ||
f7c21dc7 NC |
8963 | static void |
8964 | do_vmrs (void) | |
8965 | { | |
8966 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 8967 | |
16d02dc9 | 8968 | if (thumb_mode && Rt == REG_SP) |
f7c21dc7 NC |
8969 | { |
8970 | inst.error = BAD_SP; | |
8971 | return; | |
8972 | } | |
8973 | ||
8974 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
16d02dc9 | 8975 | if (!inst.operands[0].isvec && Rt == REG_PC) |
f7c21dc7 NC |
8976 | { |
8977 | inst.error = BAD_PC; | |
8978 | return; | |
8979 | } | |
8980 | ||
16d02dc9 JB |
8981 | /* If we get through parsing the register name, we just insert the number |
8982 | generated into the instruction without further validation. */ | |
8983 | inst.instruction |= (inst.operands[1].reg << 16); | |
f7c21dc7 NC |
8984 | inst.instruction |= (Rt << 12); |
8985 | } | |
8986 | ||
8987 | static void | |
8988 | do_vmsr (void) | |
8989 | { | |
8990 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 8991 | |
f7c21dc7 NC |
8992 | if (thumb_mode) |
8993 | reject_bad_reg (Rt); | |
8994 | else if (Rt == REG_PC) | |
8995 | { | |
8996 | inst.error = BAD_PC; | |
8997 | return; | |
8998 | } | |
8999 | ||
16d02dc9 JB |
9000 | /* If we get through parsing the register name, we just insert the number |
9001 | generated into the instruction without further validation. */ | |
9002 | inst.instruction |= (inst.operands[0].reg << 16); | |
f7c21dc7 NC |
9003 | inst.instruction |= (Rt << 12); |
9004 | } | |
9005 | ||
b99bd4ef | 9006 | static void |
c19d1205 | 9007 | do_mrs (void) |
b99bd4ef | 9008 | { |
90ec0d68 MGD |
9009 | unsigned br; |
9010 | ||
037e8744 JB |
9011 | if (do_vfp_nsyn_mrs () == SUCCESS) |
9012 | return; | |
9013 | ||
ff4a8d2b | 9014 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 9015 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
9016 | |
9017 | if (inst.operands[1].isreg) | |
9018 | { | |
9019 | br = inst.operands[1].reg; | |
9020 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
9021 | as_bad (_("bad register for mrs")); | |
9022 | } | |
9023 | else | |
9024 | { | |
9025 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
9026 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
9027 | != (PSR_c|PSR_f), | |
d2cd1205 | 9028 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
9029 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
9030 | } | |
9031 | ||
9032 | inst.instruction |= br; | |
c19d1205 | 9033 | } |
b99bd4ef | 9034 | |
c19d1205 ZW |
9035 | /* Two possible forms: |
9036 | "{C|S}PSR_<field>, Rm", | |
9037 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 9038 | |
c19d1205 ZW |
9039 | static void |
9040 | do_msr (void) | |
9041 | { | |
037e8744 JB |
9042 | if (do_vfp_nsyn_msr () == SUCCESS) |
9043 | return; | |
9044 | ||
c19d1205 ZW |
9045 | inst.instruction |= inst.operands[0].imm; |
9046 | if (inst.operands[1].isreg) | |
9047 | inst.instruction |= inst.operands[1].reg; | |
9048 | else | |
b99bd4ef | 9049 | { |
c19d1205 ZW |
9050 | inst.instruction |= INST_IMMEDIATE; |
9051 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
9052 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 9053 | } |
b99bd4ef NC |
9054 | } |
9055 | ||
c19d1205 ZW |
9056 | static void |
9057 | do_mul (void) | |
a737bd4d | 9058 | { |
ff4a8d2b NC |
9059 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
9060 | ||
c19d1205 ZW |
9061 | if (!inst.operands[2].present) |
9062 | inst.operands[2].reg = inst.operands[0].reg; | |
9063 | inst.instruction |= inst.operands[0].reg << 16; | |
9064 | inst.instruction |= inst.operands[1].reg; | |
9065 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 9066 | |
8fb9d7b9 MS |
9067 | if (inst.operands[0].reg == inst.operands[1].reg |
9068 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
9069 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
9070 | } |
9071 | ||
c19d1205 ZW |
9072 | /* Long Multiply Parser |
9073 | UMULL RdLo, RdHi, Rm, Rs | |
9074 | SMULL RdLo, RdHi, Rm, Rs | |
9075 | UMLAL RdLo, RdHi, Rm, Rs | |
9076 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
9077 | |
9078 | static void | |
c19d1205 | 9079 | do_mull (void) |
b99bd4ef | 9080 | { |
c19d1205 ZW |
9081 | inst.instruction |= inst.operands[0].reg << 12; |
9082 | inst.instruction |= inst.operands[1].reg << 16; | |
9083 | inst.instruction |= inst.operands[2].reg; | |
9084 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 9085 | |
682b27ad PB |
9086 | /* rdhi and rdlo must be different. */ |
9087 | if (inst.operands[0].reg == inst.operands[1].reg) | |
9088 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9089 | ||
9090 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
9091 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 9092 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 9093 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
9094 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
9095 | } | |
b99bd4ef | 9096 | |
c19d1205 ZW |
9097 | static void |
9098 | do_nop (void) | |
9099 | { | |
e7495e45 NS |
9100 | if (inst.operands[0].present |
9101 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
9102 | { |
9103 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
9104 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
9105 | inst.instruction |= 0x0320f000; |
9106 | if (inst.operands[0].present) | |
9107 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 9108 | } |
b99bd4ef NC |
9109 | } |
9110 | ||
c19d1205 ZW |
9111 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
9112 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
9113 | Condition defaults to COND_ALWAYS. | |
9114 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
9115 | |
9116 | static void | |
c19d1205 | 9117 | do_pkhbt (void) |
b99bd4ef | 9118 | { |
c19d1205 ZW |
9119 | inst.instruction |= inst.operands[0].reg << 12; |
9120 | inst.instruction |= inst.operands[1].reg << 16; | |
9121 | inst.instruction |= inst.operands[2].reg; | |
9122 | if (inst.operands[3].present) | |
9123 | encode_arm_shift (3); | |
9124 | } | |
b99bd4ef | 9125 | |
c19d1205 | 9126 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 9127 | |
c19d1205 ZW |
9128 | static void |
9129 | do_pkhtb (void) | |
9130 | { | |
9131 | if (!inst.operands[3].present) | |
b99bd4ef | 9132 | { |
c19d1205 ZW |
9133 | /* If the shift specifier is omitted, turn the instruction |
9134 | into pkhbt rd, rm, rn. */ | |
9135 | inst.instruction &= 0xfff00010; | |
9136 | inst.instruction |= inst.operands[0].reg << 12; | |
9137 | inst.instruction |= inst.operands[1].reg; | |
9138 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9139 | } |
9140 | else | |
9141 | { | |
c19d1205 ZW |
9142 | inst.instruction |= inst.operands[0].reg << 12; |
9143 | inst.instruction |= inst.operands[1].reg << 16; | |
9144 | inst.instruction |= inst.operands[2].reg; | |
9145 | encode_arm_shift (3); | |
b99bd4ef NC |
9146 | } |
9147 | } | |
9148 | ||
c19d1205 | 9149 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 9150 | MP Extensions: Preload for write |
c19d1205 | 9151 | |
60e5ef9f | 9152 | PLD(W) <addr_mode> |
c19d1205 ZW |
9153 | |
9154 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
9155 | |
9156 | static void | |
c19d1205 | 9157 | do_pld (void) |
b99bd4ef | 9158 | { |
c19d1205 ZW |
9159 | constraint (!inst.operands[0].isreg, |
9160 | _("'[' expected after PLD mnemonic")); | |
9161 | constraint (inst.operands[0].postind, | |
9162 | _("post-indexed expression used in preload instruction")); | |
9163 | constraint (inst.operands[0].writeback, | |
9164 | _("writeback used in preload instruction")); | |
9165 | constraint (!inst.operands[0].preind, | |
9166 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
9167 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
9168 | } | |
b99bd4ef | 9169 | |
62b3e311 PB |
9170 | /* ARMv7: PLI <addr_mode> */ |
9171 | static void | |
9172 | do_pli (void) | |
9173 | { | |
9174 | constraint (!inst.operands[0].isreg, | |
9175 | _("'[' expected after PLI mnemonic")); | |
9176 | constraint (inst.operands[0].postind, | |
9177 | _("post-indexed expression used in preload instruction")); | |
9178 | constraint (inst.operands[0].writeback, | |
9179 | _("writeback used in preload instruction")); | |
9180 | constraint (!inst.operands[0].preind, | |
9181 | _("unindexed addressing used in preload instruction")); | |
9182 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
9183 | inst.instruction &= ~PRE_INDEX; | |
9184 | } | |
9185 | ||
c19d1205 ZW |
9186 | static void |
9187 | do_push_pop (void) | |
9188 | { | |
5e0d7f77 MP |
9189 | constraint (inst.operands[0].writeback, |
9190 | _("push/pop do not support {reglist}^")); | |
c19d1205 ZW |
9191 | inst.operands[1] = inst.operands[0]; |
9192 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
9193 | inst.operands[0].isreg = 1; | |
9194 | inst.operands[0].writeback = 1; | |
9195 | inst.operands[0].reg = REG_SP; | |
6530b175 | 9196 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 9197 | } |
b99bd4ef | 9198 | |
c19d1205 ZW |
9199 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
9200 | word at the specified address and the following word | |
9201 | respectively. | |
9202 | Unconditionally executed. | |
9203 | Error if Rn is R15. */ | |
b99bd4ef | 9204 | |
c19d1205 ZW |
9205 | static void |
9206 | do_rfe (void) | |
9207 | { | |
9208 | inst.instruction |= inst.operands[0].reg << 16; | |
9209 | if (inst.operands[0].writeback) | |
9210 | inst.instruction |= WRITE_BACK; | |
9211 | } | |
b99bd4ef | 9212 | |
c19d1205 | 9213 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 9214 | |
c19d1205 ZW |
9215 | static void |
9216 | do_ssat (void) | |
9217 | { | |
9218 | inst.instruction |= inst.operands[0].reg << 12; | |
9219 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
9220 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9221 | |
c19d1205 ZW |
9222 | if (inst.operands[3].present) |
9223 | encode_arm_shift (3); | |
b99bd4ef NC |
9224 | } |
9225 | ||
c19d1205 | 9226 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
9227 | |
9228 | static void | |
c19d1205 | 9229 | do_usat (void) |
b99bd4ef | 9230 | { |
c19d1205 ZW |
9231 | inst.instruction |= inst.operands[0].reg << 12; |
9232 | inst.instruction |= inst.operands[1].imm << 16; | |
9233 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 9234 | |
c19d1205 ZW |
9235 | if (inst.operands[3].present) |
9236 | encode_arm_shift (3); | |
b99bd4ef NC |
9237 | } |
9238 | ||
c19d1205 | 9239 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
9240 | |
9241 | static void | |
c19d1205 | 9242 | do_ssat16 (void) |
09d92015 | 9243 | { |
c19d1205 ZW |
9244 | inst.instruction |= inst.operands[0].reg << 12; |
9245 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
9246 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
9247 | } |
9248 | ||
c19d1205 ZW |
9249 | static void |
9250 | do_usat16 (void) | |
a737bd4d | 9251 | { |
c19d1205 ZW |
9252 | inst.instruction |= inst.operands[0].reg << 12; |
9253 | inst.instruction |= inst.operands[1].imm << 16; | |
9254 | inst.instruction |= inst.operands[2].reg; | |
9255 | } | |
a737bd4d | 9256 | |
c19d1205 ZW |
9257 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
9258 | preserving the other bits. | |
a737bd4d | 9259 | |
c19d1205 ZW |
9260 | setend <endian_specifier>, where <endian_specifier> is either |
9261 | BE or LE. */ | |
a737bd4d | 9262 | |
c19d1205 ZW |
9263 | static void |
9264 | do_setend (void) | |
9265 | { | |
12e37cbc MGD |
9266 | if (warn_on_deprecated |
9267 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 9268 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 9269 | |
c19d1205 ZW |
9270 | if (inst.operands[0].imm) |
9271 | inst.instruction |= 0x200; | |
a737bd4d NC |
9272 | } |
9273 | ||
9274 | static void | |
c19d1205 | 9275 | do_shift (void) |
a737bd4d | 9276 | { |
c19d1205 ZW |
9277 | unsigned int Rm = (inst.operands[1].present |
9278 | ? inst.operands[1].reg | |
9279 | : inst.operands[0].reg); | |
a737bd4d | 9280 | |
c19d1205 ZW |
9281 | inst.instruction |= inst.operands[0].reg << 12; |
9282 | inst.instruction |= Rm; | |
9283 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 9284 | { |
c19d1205 ZW |
9285 | inst.instruction |= inst.operands[2].reg << 8; |
9286 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
9287 | /* PR 12854: Error on extraneous shifts. */ |
9288 | constraint (inst.operands[2].shifted, | |
9289 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
9290 | } |
9291 | else | |
c19d1205 | 9292 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
9293 | } |
9294 | ||
09d92015 | 9295 | static void |
3eb17e6b | 9296 | do_smc (void) |
09d92015 | 9297 | { |
3eb17e6b | 9298 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 9299 | inst.reloc.pc_rel = 0; |
09d92015 MM |
9300 | } |
9301 | ||
90ec0d68 MGD |
9302 | static void |
9303 | do_hvc (void) | |
9304 | { | |
9305 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
9306 | inst.reloc.pc_rel = 0; | |
9307 | } | |
9308 | ||
09d92015 | 9309 | static void |
c19d1205 | 9310 | do_swi (void) |
09d92015 | 9311 | { |
c19d1205 ZW |
9312 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
9313 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
9314 | } |
9315 | ||
ddfded2f MW |
9316 | static void |
9317 | do_setpan (void) | |
9318 | { | |
9319 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
9320 | _("selected processor does not support SETPAN instruction")); | |
9321 | ||
9322 | inst.instruction |= ((inst.operands[0].imm & 1) << 9); | |
9323 | } | |
9324 | ||
9325 | static void | |
9326 | do_t_setpan (void) | |
9327 | { | |
9328 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), | |
9329 | _("selected processor does not support SETPAN instruction")); | |
9330 | ||
9331 | inst.instruction |= (inst.operands[0].imm << 3); | |
9332 | } | |
9333 | ||
c19d1205 ZW |
9334 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
9335 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
9336 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
9337 | Error if any register is R15. */ | |
e16bb312 | 9338 | |
c19d1205 ZW |
9339 | static void |
9340 | do_smla (void) | |
e16bb312 | 9341 | { |
c19d1205 ZW |
9342 | inst.instruction |= inst.operands[0].reg << 16; |
9343 | inst.instruction |= inst.operands[1].reg; | |
9344 | inst.instruction |= inst.operands[2].reg << 8; | |
9345 | inst.instruction |= inst.operands[3].reg << 12; | |
9346 | } | |
a737bd4d | 9347 | |
c19d1205 ZW |
9348 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
9349 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
9350 | Error if any register is R15. | |
9351 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 9352 | |
c19d1205 ZW |
9353 | static void |
9354 | do_smlal (void) | |
9355 | { | |
9356 | inst.instruction |= inst.operands[0].reg << 12; | |
9357 | inst.instruction |= inst.operands[1].reg << 16; | |
9358 | inst.instruction |= inst.operands[2].reg; | |
9359 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 9360 | |
c19d1205 ZW |
9361 | if (inst.operands[0].reg == inst.operands[1].reg) |
9362 | as_tsktsk (_("rdhi and rdlo must be different")); | |
9363 | } | |
a737bd4d | 9364 | |
c19d1205 ZW |
9365 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
9366 | SMULxy{cond} Rd,Rm,Rs | |
9367 | Error if any register is R15. */ | |
a737bd4d | 9368 | |
c19d1205 ZW |
9369 | static void |
9370 | do_smul (void) | |
9371 | { | |
9372 | inst.instruction |= inst.operands[0].reg << 16; | |
9373 | inst.instruction |= inst.operands[1].reg; | |
9374 | inst.instruction |= inst.operands[2].reg << 8; | |
9375 | } | |
a737bd4d | 9376 | |
b6702015 PB |
9377 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
9378 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 9379 | |
c19d1205 ZW |
9380 | static void |
9381 | do_srs (void) | |
9382 | { | |
b6702015 PB |
9383 | int reg; |
9384 | ||
9385 | if (inst.operands[0].present) | |
9386 | { | |
9387 | reg = inst.operands[0].reg; | |
fdfde340 | 9388 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
9389 | } |
9390 | else | |
fdfde340 | 9391 | reg = REG_SP; |
b6702015 PB |
9392 | |
9393 | inst.instruction |= reg << 16; | |
9394 | inst.instruction |= inst.operands[1].imm; | |
9395 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
9396 | inst.instruction |= WRITE_BACK; |
9397 | } | |
a737bd4d | 9398 | |
c19d1205 | 9399 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 9400 | |
c19d1205 ZW |
9401 | static void |
9402 | do_strex (void) | |
9403 | { | |
9404 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9405 | || inst.operands[2].postind || inst.operands[2].writeback | |
9406 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
9407 | || inst.operands[2].negative |
9408 | /* See comment in do_ldrex(). */ | |
9409 | || (inst.operands[2].reg == REG_PC), | |
9410 | BAD_ADDR_MODE); | |
a737bd4d | 9411 | |
c19d1205 ZW |
9412 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9413 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 9414 | |
c19d1205 ZW |
9415 | constraint (inst.reloc.exp.X_op != O_constant |
9416 | || inst.reloc.exp.X_add_number != 0, | |
9417 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 9418 | |
c19d1205 ZW |
9419 | inst.instruction |= inst.operands[0].reg << 12; |
9420 | inst.instruction |= inst.operands[1].reg; | |
9421 | inst.instruction |= inst.operands[2].reg << 16; | |
9422 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
9423 | } |
9424 | ||
877807f8 NC |
9425 | static void |
9426 | do_t_strexbh (void) | |
9427 | { | |
9428 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
9429 | || inst.operands[2].postind || inst.operands[2].writeback | |
9430 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
9431 | || inst.operands[2].negative, | |
9432 | BAD_ADDR_MODE); | |
9433 | ||
9434 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9435 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9436 | ||
9437 | do_rm_rd_rn (); | |
9438 | } | |
9439 | ||
e16bb312 | 9440 | static void |
c19d1205 | 9441 | do_strexd (void) |
e16bb312 | 9442 | { |
c19d1205 ZW |
9443 | constraint (inst.operands[1].reg % 2 != 0, |
9444 | _("even register required")); | |
9445 | constraint (inst.operands[2].present | |
9446 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
9447 | _("can only store two consecutive registers")); | |
9448 | /* If op 2 were present and equal to PC, this function wouldn't | |
9449 | have been called in the first place. */ | |
9450 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 9451 | |
c19d1205 ZW |
9452 | constraint (inst.operands[0].reg == inst.operands[1].reg |
9453 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
9454 | || inst.operands[0].reg == inst.operands[3].reg, | |
9455 | BAD_OVERLAP); | |
e16bb312 | 9456 | |
c19d1205 ZW |
9457 | inst.instruction |= inst.operands[0].reg << 12; |
9458 | inst.instruction |= inst.operands[1].reg; | |
9459 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
9460 | } |
9461 | ||
9eb6c0f1 MGD |
9462 | /* ARM V8 STRL. */ |
9463 | static void | |
4b8c8c02 | 9464 | do_stlex (void) |
9eb6c0f1 MGD |
9465 | { |
9466 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9467 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9468 | ||
9469 | do_rd_rm_rn (); | |
9470 | } | |
9471 | ||
9472 | static void | |
4b8c8c02 | 9473 | do_t_stlex (void) |
9eb6c0f1 MGD |
9474 | { |
9475 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
9476 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
9477 | ||
9478 | do_rm_rd_rn (); | |
9479 | } | |
9480 | ||
c19d1205 ZW |
9481 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
9482 | extends it to 32-bits, and adds the result to a value in another | |
9483 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
9484 | before extracting the 16-bit value. | |
9485 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
9486 | Condition defaults to COND_ALWAYS. | |
9487 | Error if any register uses R15. */ | |
9488 | ||
e16bb312 | 9489 | static void |
c19d1205 | 9490 | do_sxtah (void) |
e16bb312 | 9491 | { |
c19d1205 ZW |
9492 | inst.instruction |= inst.operands[0].reg << 12; |
9493 | inst.instruction |= inst.operands[1].reg << 16; | |
9494 | inst.instruction |= inst.operands[2].reg; | |
9495 | inst.instruction |= inst.operands[3].imm << 10; | |
9496 | } | |
e16bb312 | 9497 | |
c19d1205 | 9498 | /* ARM V6 SXTH. |
e16bb312 | 9499 | |
c19d1205 ZW |
9500 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
9501 | Condition defaults to COND_ALWAYS. | |
9502 | Error if any register uses R15. */ | |
e16bb312 NC |
9503 | |
9504 | static void | |
c19d1205 | 9505 | do_sxth (void) |
e16bb312 | 9506 | { |
c19d1205 ZW |
9507 | inst.instruction |= inst.operands[0].reg << 12; |
9508 | inst.instruction |= inst.operands[1].reg; | |
9509 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 9510 | } |
c19d1205 ZW |
9511 | \f |
9512 | /* VFP instructions. In a logical order: SP variant first, monad | |
9513 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
9514 | |
9515 | static void | |
c19d1205 | 9516 | do_vfp_sp_monadic (void) |
e16bb312 | 9517 | { |
5287ad62 JB |
9518 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9519 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9520 | } |
9521 | ||
9522 | static void | |
c19d1205 | 9523 | do_vfp_sp_dyadic (void) |
e16bb312 | 9524 | { |
5287ad62 JB |
9525 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9526 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
9527 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
9528 | } |
9529 | ||
9530 | static void | |
c19d1205 | 9531 | do_vfp_sp_compare_z (void) |
e16bb312 | 9532 | { |
5287ad62 | 9533 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
9534 | } |
9535 | ||
9536 | static void | |
c19d1205 | 9537 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 9538 | { |
5287ad62 JB |
9539 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
9540 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
9541 | } |
9542 | ||
9543 | static void | |
c19d1205 | 9544 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 9545 | { |
5287ad62 JB |
9546 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
9547 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
9548 | } |
9549 | ||
9550 | static void | |
c19d1205 | 9551 | do_vfp_reg_from_sp (void) |
e16bb312 | 9552 | { |
c19d1205 | 9553 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 9554 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
9555 | } |
9556 | ||
9557 | static void | |
c19d1205 | 9558 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 9559 | { |
c19d1205 ZW |
9560 | constraint (inst.operands[2].imm != 2, |
9561 | _("only two consecutive VFP SP registers allowed here")); | |
9562 | inst.instruction |= inst.operands[0].reg << 12; | |
9563 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 9564 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
9565 | } |
9566 | ||
9567 | static void | |
c19d1205 | 9568 | do_vfp_sp_from_reg (void) |
e16bb312 | 9569 | { |
5287ad62 | 9570 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 9571 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
9572 | } |
9573 | ||
9574 | static void | |
c19d1205 | 9575 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 9576 | { |
c19d1205 ZW |
9577 | constraint (inst.operands[0].imm != 2, |
9578 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 9579 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
9580 | inst.instruction |= inst.operands[1].reg << 12; |
9581 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
9582 | } |
9583 | ||
9584 | static void | |
c19d1205 | 9585 | do_vfp_sp_ldst (void) |
e16bb312 | 9586 | { |
5287ad62 | 9587 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 9588 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9589 | } |
9590 | ||
9591 | static void | |
c19d1205 | 9592 | do_vfp_dp_ldst (void) |
e16bb312 | 9593 | { |
5287ad62 | 9594 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 9595 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
9596 | } |
9597 | ||
c19d1205 | 9598 | |
e16bb312 | 9599 | static void |
c19d1205 | 9600 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9601 | { |
c19d1205 ZW |
9602 | if (inst.operands[0].writeback) |
9603 | inst.instruction |= WRITE_BACK; | |
9604 | else | |
9605 | constraint (ldstm_type != VFP_LDSTMIA, | |
9606 | _("this addressing mode requires base-register writeback")); | |
9607 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 9608 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 9609 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
9610 | } |
9611 | ||
9612 | static void | |
c19d1205 | 9613 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 9614 | { |
c19d1205 | 9615 | int count; |
e16bb312 | 9616 | |
c19d1205 ZW |
9617 | if (inst.operands[0].writeback) |
9618 | inst.instruction |= WRITE_BACK; | |
9619 | else | |
9620 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
9621 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 9622 | |
c19d1205 | 9623 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 9624 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 9625 | |
c19d1205 ZW |
9626 | count = inst.operands[1].imm << 1; |
9627 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
9628 | count += 1; | |
e16bb312 | 9629 | |
c19d1205 | 9630 | inst.instruction |= count; |
e16bb312 NC |
9631 | } |
9632 | ||
9633 | static void | |
c19d1205 | 9634 | do_vfp_sp_ldstmia (void) |
e16bb312 | 9635 | { |
c19d1205 | 9636 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9637 | } |
9638 | ||
9639 | static void | |
c19d1205 | 9640 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 9641 | { |
c19d1205 | 9642 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9643 | } |
9644 | ||
9645 | static void | |
c19d1205 | 9646 | do_vfp_dp_ldstmia (void) |
e16bb312 | 9647 | { |
c19d1205 | 9648 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
9649 | } |
9650 | ||
9651 | static void | |
c19d1205 | 9652 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 9653 | { |
c19d1205 | 9654 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
9655 | } |
9656 | ||
9657 | static void | |
c19d1205 | 9658 | do_vfp_xp_ldstmia (void) |
e16bb312 | 9659 | { |
c19d1205 ZW |
9660 | vfp_dp_ldstm (VFP_LDSTMIAX); |
9661 | } | |
e16bb312 | 9662 | |
c19d1205 ZW |
9663 | static void |
9664 | do_vfp_xp_ldstmdb (void) | |
9665 | { | |
9666 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 9667 | } |
5287ad62 JB |
9668 | |
9669 | static void | |
9670 | do_vfp_dp_rd_rm (void) | |
9671 | { | |
9672 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9673 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
9674 | } | |
9675 | ||
9676 | static void | |
9677 | do_vfp_dp_rn_rd (void) | |
9678 | { | |
9679 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
9680 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9681 | } | |
9682 | ||
9683 | static void | |
9684 | do_vfp_dp_rd_rn (void) | |
9685 | { | |
9686 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9687 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9688 | } | |
9689 | ||
9690 | static void | |
9691 | do_vfp_dp_rd_rn_rm (void) | |
9692 | { | |
9693 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9694 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
9695 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
9696 | } | |
9697 | ||
9698 | static void | |
9699 | do_vfp_dp_rd (void) | |
9700 | { | |
9701 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9702 | } | |
9703 | ||
9704 | static void | |
9705 | do_vfp_dp_rm_rd_rn (void) | |
9706 | { | |
9707 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
9708 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
9709 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
9710 | } | |
9711 | ||
9712 | /* VFPv3 instructions. */ | |
9713 | static void | |
9714 | do_vfp_sp_const (void) | |
9715 | { | |
9716 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
9717 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9718 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9719 | } |
9720 | ||
9721 | static void | |
9722 | do_vfp_dp_const (void) | |
9723 | { | |
9724 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
9725 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
9726 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
9727 | } |
9728 | ||
9729 | static void | |
9730 | vfp_conv (int srcsize) | |
9731 | { | |
5f1af56b MGD |
9732 | int immbits = srcsize - inst.operands[1].imm; |
9733 | ||
fa94de6b RM |
9734 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
9735 | { | |
5f1af56b | 9736 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
477330fc | 9737 | i.e. immbits must be in range 0 - 16. */ |
5f1af56b MGD |
9738 | inst.error = _("immediate value out of range, expected range [0, 16]"); |
9739 | return; | |
9740 | } | |
fa94de6b | 9741 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
9742 | { |
9743 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
477330fc | 9744 | i.e. immbits must be in range 0 - 31. */ |
5f1af56b MGD |
9745 | inst.error = _("immediate value out of range, expected range [1, 32]"); |
9746 | return; | |
9747 | } | |
9748 | ||
5287ad62 JB |
9749 | inst.instruction |= (immbits & 1) << 5; |
9750 | inst.instruction |= (immbits >> 1); | |
9751 | } | |
9752 | ||
9753 | static void | |
9754 | do_vfp_sp_conv_16 (void) | |
9755 | { | |
9756 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9757 | vfp_conv (16); | |
9758 | } | |
9759 | ||
9760 | static void | |
9761 | do_vfp_dp_conv_16 (void) | |
9762 | { | |
9763 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9764 | vfp_conv (16); | |
9765 | } | |
9766 | ||
9767 | static void | |
9768 | do_vfp_sp_conv_32 (void) | |
9769 | { | |
9770 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
9771 | vfp_conv (32); | |
9772 | } | |
9773 | ||
9774 | static void | |
9775 | do_vfp_dp_conv_32 (void) | |
9776 | { | |
9777 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9778 | vfp_conv (32); | |
9779 | } | |
c19d1205 ZW |
9780 | \f |
9781 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 9782 | |
c19d1205 ZW |
9783 | static void |
9784 | do_fpa_cmp (void) | |
9785 | { | |
9786 | inst.instruction |= inst.operands[0].reg << 16; | |
9787 | inst.instruction |= inst.operands[1].reg; | |
9788 | } | |
b99bd4ef NC |
9789 | |
9790 | static void | |
c19d1205 | 9791 | do_fpa_ldmstm (void) |
b99bd4ef | 9792 | { |
c19d1205 ZW |
9793 | inst.instruction |= inst.operands[0].reg << 12; |
9794 | switch (inst.operands[1].imm) | |
9795 | { | |
9796 | case 1: inst.instruction |= CP_T_X; break; | |
9797 | case 2: inst.instruction |= CP_T_Y; break; | |
9798 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
9799 | case 4: break; | |
9800 | default: abort (); | |
9801 | } | |
b99bd4ef | 9802 | |
c19d1205 ZW |
9803 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
9804 | { | |
9805 | /* The instruction specified "ea" or "fd", so we can only accept | |
9806 | [Rn]{!}. The instruction does not really support stacking or | |
9807 | unstacking, so we have to emulate these by setting appropriate | |
9808 | bits and offsets. */ | |
9809 | constraint (inst.reloc.exp.X_op != O_constant | |
9810 | || inst.reloc.exp.X_add_number != 0, | |
9811 | _("this instruction does not support indexing")); | |
b99bd4ef | 9812 | |
c19d1205 ZW |
9813 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
9814 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 9815 | |
c19d1205 ZW |
9816 | if (!(inst.instruction & INDEX_UP)) |
9817 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 9818 | |
c19d1205 ZW |
9819 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
9820 | { | |
9821 | inst.operands[2].preind = 0; | |
9822 | inst.operands[2].postind = 1; | |
9823 | } | |
9824 | } | |
b99bd4ef | 9825 | |
c19d1205 | 9826 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 9827 | } |
c19d1205 ZW |
9828 | \f |
9829 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 9830 | |
c19d1205 ZW |
9831 | static void |
9832 | do_iwmmxt_tandorc (void) | |
9833 | { | |
9834 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
9835 | } | |
b99bd4ef | 9836 | |
c19d1205 ZW |
9837 | static void |
9838 | do_iwmmxt_textrc (void) | |
9839 | { | |
9840 | inst.instruction |= inst.operands[0].reg << 12; | |
9841 | inst.instruction |= inst.operands[1].imm; | |
9842 | } | |
b99bd4ef NC |
9843 | |
9844 | static void | |
c19d1205 | 9845 | do_iwmmxt_textrm (void) |
b99bd4ef | 9846 | { |
c19d1205 ZW |
9847 | inst.instruction |= inst.operands[0].reg << 12; |
9848 | inst.instruction |= inst.operands[1].reg << 16; | |
9849 | inst.instruction |= inst.operands[2].imm; | |
9850 | } | |
b99bd4ef | 9851 | |
c19d1205 ZW |
9852 | static void |
9853 | do_iwmmxt_tinsr (void) | |
9854 | { | |
9855 | inst.instruction |= inst.operands[0].reg << 16; | |
9856 | inst.instruction |= inst.operands[1].reg << 12; | |
9857 | inst.instruction |= inst.operands[2].imm; | |
9858 | } | |
b99bd4ef | 9859 | |
c19d1205 ZW |
9860 | static void |
9861 | do_iwmmxt_tmia (void) | |
9862 | { | |
9863 | inst.instruction |= inst.operands[0].reg << 5; | |
9864 | inst.instruction |= inst.operands[1].reg; | |
9865 | inst.instruction |= inst.operands[2].reg << 12; | |
9866 | } | |
b99bd4ef | 9867 | |
c19d1205 ZW |
9868 | static void |
9869 | do_iwmmxt_waligni (void) | |
9870 | { | |
9871 | inst.instruction |= inst.operands[0].reg << 12; | |
9872 | inst.instruction |= inst.operands[1].reg << 16; | |
9873 | inst.instruction |= inst.operands[2].reg; | |
9874 | inst.instruction |= inst.operands[3].imm << 20; | |
9875 | } | |
b99bd4ef | 9876 | |
2d447fca JM |
9877 | static void |
9878 | do_iwmmxt_wmerge (void) | |
9879 | { | |
9880 | inst.instruction |= inst.operands[0].reg << 12; | |
9881 | inst.instruction |= inst.operands[1].reg << 16; | |
9882 | inst.instruction |= inst.operands[2].reg; | |
9883 | inst.instruction |= inst.operands[3].imm << 21; | |
9884 | } | |
9885 | ||
c19d1205 ZW |
9886 | static void |
9887 | do_iwmmxt_wmov (void) | |
9888 | { | |
9889 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
9890 | inst.instruction |= inst.operands[0].reg << 12; | |
9891 | inst.instruction |= inst.operands[1].reg << 16; | |
9892 | inst.instruction |= inst.operands[1].reg; | |
9893 | } | |
b99bd4ef | 9894 | |
c19d1205 ZW |
9895 | static void |
9896 | do_iwmmxt_wldstbh (void) | |
9897 | { | |
8f06b2d8 | 9898 | int reloc; |
c19d1205 | 9899 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
9900 | if (thumb_mode) |
9901 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
9902 | else | |
9903 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
9904 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
9905 | } |
9906 | ||
c19d1205 ZW |
9907 | static void |
9908 | do_iwmmxt_wldstw (void) | |
9909 | { | |
9910 | /* RIWR_RIWC clears .isreg for a control register. */ | |
9911 | if (!inst.operands[0].isreg) | |
9912 | { | |
9913 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
9914 | inst.instruction |= 0xf0000000; | |
9915 | } | |
b99bd4ef | 9916 | |
c19d1205 ZW |
9917 | inst.instruction |= inst.operands[0].reg << 12; |
9918 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
9919 | } | |
b99bd4ef NC |
9920 | |
9921 | static void | |
c19d1205 | 9922 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9923 | { |
c19d1205 | 9924 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9925 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9926 | && inst.operands[1].immisreg) | |
9927 | { | |
9928 | inst.instruction &= ~0x1a000ff; | |
eff0bc54 | 9929 | inst.instruction |= (0xfU << 28); |
2d447fca JM |
9930 | if (inst.operands[1].preind) |
9931 | inst.instruction |= PRE_INDEX; | |
9932 | if (!inst.operands[1].negative) | |
9933 | inst.instruction |= INDEX_UP; | |
9934 | if (inst.operands[1].writeback) | |
9935 | inst.instruction |= WRITE_BACK; | |
9936 | inst.instruction |= inst.operands[1].reg << 16; | |
9937 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9938 | inst.instruction |= inst.operands[1].imm; | |
9939 | } | |
9940 | else | |
9941 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9942 | } |
b99bd4ef | 9943 | |
c19d1205 ZW |
9944 | static void |
9945 | do_iwmmxt_wshufh (void) | |
9946 | { | |
9947 | inst.instruction |= inst.operands[0].reg << 12; | |
9948 | inst.instruction |= inst.operands[1].reg << 16; | |
9949 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9950 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9951 | } | |
b99bd4ef | 9952 | |
c19d1205 ZW |
9953 | static void |
9954 | do_iwmmxt_wzero (void) | |
9955 | { | |
9956 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
9957 | inst.instruction |= inst.operands[0].reg; | |
9958 | inst.instruction |= inst.operands[0].reg << 12; | |
9959 | inst.instruction |= inst.operands[0].reg << 16; | |
9960 | } | |
2d447fca JM |
9961 | |
9962 | static void | |
9963 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
9964 | { | |
9965 | if (inst.operands[2].isreg) | |
9966 | do_rd_rn_rm (); | |
9967 | else { | |
9968 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
9969 | _("immediate operand requires iWMMXt2")); | |
9970 | do_rd_rn (); | |
9971 | if (inst.operands[2].imm == 0) | |
9972 | { | |
9973 | switch ((inst.instruction >> 20) & 0xf) | |
9974 | { | |
9975 | case 4: | |
9976 | case 5: | |
9977 | case 6: | |
5f4273c7 | 9978 | case 7: |
2d447fca JM |
9979 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
9980 | inst.operands[2].imm = 16; | |
9981 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
9982 | break; | |
9983 | case 8: | |
9984 | case 9: | |
9985 | case 10: | |
9986 | case 11: | |
9987 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
9988 | inst.operands[2].imm = 32; | |
9989 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
9990 | break; | |
9991 | case 12: | |
9992 | case 13: | |
9993 | case 14: | |
9994 | case 15: | |
9995 | { | |
9996 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
9997 | unsigned long wrn; | |
9998 | wrn = (inst.instruction >> 16) & 0xf; | |
9999 | inst.instruction &= 0xff0fff0f; | |
10000 | inst.instruction |= wrn; | |
10001 | /* Bail out here; the instruction is now assembled. */ | |
10002 | return; | |
10003 | } | |
10004 | } | |
10005 | } | |
10006 | /* Map 32 -> 0, etc. */ | |
10007 | inst.operands[2].imm &= 0x1f; | |
eff0bc54 | 10008 | inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); |
2d447fca JM |
10009 | } |
10010 | } | |
c19d1205 ZW |
10011 | \f |
10012 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
10013 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 10014 | |
c19d1205 | 10015 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 10016 | |
c19d1205 ZW |
10017 | static void |
10018 | do_mav_triple (void) | |
10019 | { | |
10020 | inst.instruction |= inst.operands[0].reg << 16; | |
10021 | inst.instruction |= inst.operands[1].reg; | |
10022 | inst.instruction |= inst.operands[2].reg << 12; | |
10023 | } | |
b99bd4ef | 10024 | |
c19d1205 ZW |
10025 | /* Insns like "foo W,X,Y,Z". |
10026 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 10027 | |
c19d1205 ZW |
10028 | static void |
10029 | do_mav_quad (void) | |
10030 | { | |
10031 | inst.instruction |= inst.operands[0].reg << 5; | |
10032 | inst.instruction |= inst.operands[1].reg << 12; | |
10033 | inst.instruction |= inst.operands[2].reg << 16; | |
10034 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
10035 | } |
10036 | ||
c19d1205 ZW |
10037 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
10038 | static void | |
10039 | do_mav_dspsc (void) | |
a737bd4d | 10040 | { |
c19d1205 ZW |
10041 | inst.instruction |= inst.operands[1].reg << 12; |
10042 | } | |
a737bd4d | 10043 | |
c19d1205 ZW |
10044 | /* Maverick shift immediate instructions. |
10045 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
10046 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 10047 | |
c19d1205 ZW |
10048 | static void |
10049 | do_mav_shift (void) | |
10050 | { | |
10051 | int imm = inst.operands[2].imm; | |
a737bd4d | 10052 | |
c19d1205 ZW |
10053 | inst.instruction |= inst.operands[0].reg << 12; |
10054 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 10055 | |
c19d1205 ZW |
10056 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
10057 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
10058 | Bit 4 should be 0. */ | |
10059 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 10060 | |
c19d1205 ZW |
10061 | inst.instruction |= imm; |
10062 | } | |
10063 | \f | |
10064 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 10065 | |
c19d1205 ZW |
10066 | /* Xscale multiply-accumulate (argument parse) |
10067 | MIAcc acc0,Rm,Rs | |
10068 | MIAPHcc acc0,Rm,Rs | |
10069 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 10070 | |
c19d1205 ZW |
10071 | static void |
10072 | do_xsc_mia (void) | |
10073 | { | |
10074 | inst.instruction |= inst.operands[1].reg; | |
10075 | inst.instruction |= inst.operands[2].reg << 12; | |
10076 | } | |
a737bd4d | 10077 | |
c19d1205 | 10078 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 10079 | |
c19d1205 | 10080 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 10081 | |
c19d1205 ZW |
10082 | static void |
10083 | do_xsc_mar (void) | |
10084 | { | |
10085 | inst.instruction |= inst.operands[1].reg << 12; | |
10086 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10087 | } |
10088 | ||
c19d1205 | 10089 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 10090 | |
c19d1205 | 10091 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
10092 | |
10093 | static void | |
c19d1205 | 10094 | do_xsc_mra (void) |
b99bd4ef | 10095 | { |
c19d1205 ZW |
10096 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
10097 | inst.instruction |= inst.operands[0].reg << 12; | |
10098 | inst.instruction |= inst.operands[1].reg << 16; | |
10099 | } | |
10100 | \f | |
10101 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 10102 | |
c19d1205 ZW |
10103 | /* inst.operands[i] is a shifted-register operand; encode |
10104 | it into inst.instruction in the format used by Thumb32. */ | |
10105 | ||
10106 | static void | |
10107 | encode_thumb32_shifted_operand (int i) | |
10108 | { | |
10109 | unsigned int value = inst.reloc.exp.X_add_number; | |
10110 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 10111 | |
9c3c69f2 PB |
10112 | constraint (inst.operands[i].immisreg, |
10113 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
10114 | inst.instruction |= inst.operands[i].reg; |
10115 | if (shift == SHIFT_RRX) | |
10116 | inst.instruction |= SHIFT_ROR << 4; | |
10117 | else | |
b99bd4ef | 10118 | { |
c19d1205 ZW |
10119 | constraint (inst.reloc.exp.X_op != O_constant, |
10120 | _("expression too complex")); | |
10121 | ||
10122 | constraint (value > 32 | |
10123 | || (value == 32 && (shift == SHIFT_LSL | |
10124 | || shift == SHIFT_ROR)), | |
10125 | _("shift expression is too large")); | |
10126 | ||
10127 | if (value == 0) | |
10128 | shift = SHIFT_LSL; | |
10129 | else if (value == 32) | |
10130 | value = 0; | |
10131 | ||
10132 | inst.instruction |= shift << 4; | |
10133 | inst.instruction |= (value & 0x1c) << 10; | |
10134 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 10135 | } |
c19d1205 | 10136 | } |
b99bd4ef | 10137 | |
b99bd4ef | 10138 | |
c19d1205 ZW |
10139 | /* inst.operands[i] was set up by parse_address. Encode it into a |
10140 | Thumb32 format load or store instruction. Reject forms that cannot | |
10141 | be used with such instructions. If is_t is true, reject forms that | |
10142 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
10143 | that cannot be used with a D instruction. If it is a store insn, |
10144 | reject PC in Rn. */ | |
b99bd4ef | 10145 | |
c19d1205 ZW |
10146 | static void |
10147 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
10148 | { | |
5be8be5d | 10149 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
10150 | |
10151 | constraint (!inst.operands[i].isreg, | |
53365c0d | 10152 | _("Instruction does not support =N addresses")); |
b99bd4ef | 10153 | |
c19d1205 ZW |
10154 | inst.instruction |= inst.operands[i].reg << 16; |
10155 | if (inst.operands[i].immisreg) | |
b99bd4ef | 10156 | { |
5be8be5d | 10157 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
10158 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
10159 | constraint (inst.operands[i].negative, | |
10160 | _("Thumb does not support negative register indexing")); | |
10161 | constraint (inst.operands[i].postind, | |
10162 | _("Thumb does not support register post-indexing")); | |
10163 | constraint (inst.operands[i].writeback, | |
10164 | _("Thumb does not support register indexing with writeback")); | |
10165 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
10166 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 10167 | |
f40d1643 | 10168 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 10169 | if (inst.operands[i].shifted) |
b99bd4ef | 10170 | { |
c19d1205 ZW |
10171 | constraint (inst.reloc.exp.X_op != O_constant, |
10172 | _("expression too complex")); | |
9c3c69f2 PB |
10173 | constraint (inst.reloc.exp.X_add_number < 0 |
10174 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 10175 | _("shift out of range")); |
9c3c69f2 | 10176 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
10177 | } |
10178 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10179 | } | |
10180 | else if (inst.operands[i].preind) | |
10181 | { | |
5be8be5d | 10182 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 10183 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 10184 | _("cannot use writeback with this instruction")); |
4755303e WN |
10185 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), |
10186 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
10187 | |
10188 | if (is_d) | |
10189 | { | |
10190 | inst.instruction |= 0x01000000; | |
10191 | if (inst.operands[i].writeback) | |
10192 | inst.instruction |= 0x00200000; | |
b99bd4ef | 10193 | } |
c19d1205 | 10194 | else |
b99bd4ef | 10195 | { |
c19d1205 ZW |
10196 | inst.instruction |= 0x00000c00; |
10197 | if (inst.operands[i].writeback) | |
10198 | inst.instruction |= 0x00000100; | |
b99bd4ef | 10199 | } |
c19d1205 | 10200 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 10201 | } |
c19d1205 | 10202 | else if (inst.operands[i].postind) |
b99bd4ef | 10203 | { |
9c2799c2 | 10204 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
10205 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
10206 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
10207 | ||
10208 | if (is_d) | |
10209 | inst.instruction |= 0x00200000; | |
10210 | else | |
10211 | inst.instruction |= 0x00000900; | |
10212 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10213 | } | |
10214 | else /* unindexed - only for coprocessor */ | |
10215 | inst.error = _("instruction does not accept unindexed addressing"); | |
10216 | } | |
10217 | ||
10218 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
10219 | encodings (the latter only in post-V6T2 cores). The index is the | |
10220 | value used in the insns table below. When there is more than one | |
10221 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
10222 | holds variant (1). |
10223 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 10224 | #define T16_32_TAB \ |
21d799b5 NC |
10225 | X(_adc, 4140, eb400000), \ |
10226 | X(_adcs, 4140, eb500000), \ | |
10227 | X(_add, 1c00, eb000000), \ | |
10228 | X(_adds, 1c00, eb100000), \ | |
10229 | X(_addi, 0000, f1000000), \ | |
10230 | X(_addis, 0000, f1100000), \ | |
10231 | X(_add_pc,000f, f20f0000), \ | |
10232 | X(_add_sp,000d, f10d0000), \ | |
10233 | X(_adr, 000f, f20f0000), \ | |
10234 | X(_and, 4000, ea000000), \ | |
10235 | X(_ands, 4000, ea100000), \ | |
10236 | X(_asr, 1000, fa40f000), \ | |
10237 | X(_asrs, 1000, fa50f000), \ | |
10238 | X(_b, e000, f000b000), \ | |
10239 | X(_bcond, d000, f0008000), \ | |
10240 | X(_bic, 4380, ea200000), \ | |
10241 | X(_bics, 4380, ea300000), \ | |
10242 | X(_cmn, 42c0, eb100f00), \ | |
10243 | X(_cmp, 2800, ebb00f00), \ | |
10244 | X(_cpsie, b660, f3af8400), \ | |
10245 | X(_cpsid, b670, f3af8600), \ | |
10246 | X(_cpy, 4600, ea4f0000), \ | |
10247 | X(_dec_sp,80dd, f1ad0d00), \ | |
10248 | X(_eor, 4040, ea800000), \ | |
10249 | X(_eors, 4040, ea900000), \ | |
10250 | X(_inc_sp,00dd, f10d0d00), \ | |
10251 | X(_ldmia, c800, e8900000), \ | |
10252 | X(_ldr, 6800, f8500000), \ | |
10253 | X(_ldrb, 7800, f8100000), \ | |
10254 | X(_ldrh, 8800, f8300000), \ | |
10255 | X(_ldrsb, 5600, f9100000), \ | |
10256 | X(_ldrsh, 5e00, f9300000), \ | |
10257 | X(_ldr_pc,4800, f85f0000), \ | |
10258 | X(_ldr_pc2,4800, f85f0000), \ | |
10259 | X(_ldr_sp,9800, f85d0000), \ | |
10260 | X(_lsl, 0000, fa00f000), \ | |
10261 | X(_lsls, 0000, fa10f000), \ | |
10262 | X(_lsr, 0800, fa20f000), \ | |
10263 | X(_lsrs, 0800, fa30f000), \ | |
10264 | X(_mov, 2000, ea4f0000), \ | |
10265 | X(_movs, 2000, ea5f0000), \ | |
10266 | X(_mul, 4340, fb00f000), \ | |
10267 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
10268 | X(_mvn, 43c0, ea6f0000), \ | |
10269 | X(_mvns, 43c0, ea7f0000), \ | |
10270 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
10271 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
10272 | X(_orr, 4300, ea400000), \ | |
10273 | X(_orrs, 4300, ea500000), \ | |
10274 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
10275 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
10276 | X(_rev, ba00, fa90f080), \ | |
10277 | X(_rev16, ba40, fa90f090), \ | |
10278 | X(_revsh, bac0, fa90f0b0), \ | |
10279 | X(_ror, 41c0, fa60f000), \ | |
10280 | X(_rors, 41c0, fa70f000), \ | |
10281 | X(_sbc, 4180, eb600000), \ | |
10282 | X(_sbcs, 4180, eb700000), \ | |
10283 | X(_stmia, c000, e8800000), \ | |
10284 | X(_str, 6000, f8400000), \ | |
10285 | X(_strb, 7000, f8000000), \ | |
10286 | X(_strh, 8000, f8200000), \ | |
10287 | X(_str_sp,9000, f84d0000), \ | |
10288 | X(_sub, 1e00, eba00000), \ | |
10289 | X(_subs, 1e00, ebb00000), \ | |
10290 | X(_subi, 8000, f1a00000), \ | |
10291 | X(_subis, 8000, f1b00000), \ | |
10292 | X(_sxtb, b240, fa4ff080), \ | |
10293 | X(_sxth, b200, fa0ff080), \ | |
10294 | X(_tst, 4200, ea100f00), \ | |
10295 | X(_uxtb, b2c0, fa5ff080), \ | |
10296 | X(_uxth, b280, fa1ff080), \ | |
10297 | X(_nop, bf00, f3af8000), \ | |
10298 | X(_yield, bf10, f3af8001), \ | |
10299 | X(_wfe, bf20, f3af8002), \ | |
10300 | X(_wfi, bf30, f3af8003), \ | |
53c4b28b | 10301 | X(_sev, bf40, f3af8004), \ |
74db7efb NC |
10302 | X(_sevl, bf50, f3af8005), \ |
10303 | X(_udf, de00, f7f0a000) | |
c19d1205 ZW |
10304 | |
10305 | /* To catch errors in encoding functions, the codes are all offset by | |
10306 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
10307 | as 16-bit instructions. */ | |
21d799b5 | 10308 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
10309 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
10310 | #undef X | |
10311 | ||
10312 | #define X(a,b,c) 0x##b | |
10313 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
10314 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
10315 | #undef X | |
10316 | ||
10317 | #define X(a,b,c) 0x##c | |
10318 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
10319 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
10320 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
10321 | #undef X |
10322 | #undef T16_32_TAB | |
10323 | ||
10324 | /* Thumb instruction encoders, in alphabetical order. */ | |
10325 | ||
92e90b6e | 10326 | /* ADDW or SUBW. */ |
c921be7d | 10327 | |
92e90b6e PB |
10328 | static void |
10329 | do_t_add_sub_w (void) | |
10330 | { | |
10331 | int Rd, Rn; | |
10332 | ||
10333 | Rd = inst.operands[0].reg; | |
10334 | Rn = inst.operands[1].reg; | |
10335 | ||
539d4391 NC |
10336 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
10337 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
10338 | if (Rn == REG_SP) | |
10339 | constraint (Rd == REG_PC, BAD_PC); | |
10340 | else | |
10341 | reject_bad_reg (Rd); | |
fdfde340 | 10342 | |
92e90b6e PB |
10343 | inst.instruction |= (Rn << 16) | (Rd << 8); |
10344 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10345 | } | |
10346 | ||
c19d1205 ZW |
10347 | /* Parse an add or subtract instruction. We get here with inst.instruction |
10348 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
10349 | ||
10350 | static void | |
10351 | do_t_add_sub (void) | |
10352 | { | |
10353 | int Rd, Rs, Rn; | |
10354 | ||
10355 | Rd = inst.operands[0].reg; | |
10356 | Rs = (inst.operands[1].present | |
10357 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10358 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10359 | ||
e07e6e58 NC |
10360 | if (Rd == REG_PC) |
10361 | set_it_insn_type_last (); | |
10362 | ||
c19d1205 ZW |
10363 | if (unified_syntax) |
10364 | { | |
0110f2b8 PB |
10365 | bfd_boolean flags; |
10366 | bfd_boolean narrow; | |
10367 | int opcode; | |
10368 | ||
10369 | flags = (inst.instruction == T_MNEM_adds | |
10370 | || inst.instruction == T_MNEM_subs); | |
10371 | if (flags) | |
e07e6e58 | 10372 | narrow = !in_it_block (); |
0110f2b8 | 10373 | else |
e07e6e58 | 10374 | narrow = in_it_block (); |
c19d1205 | 10375 | if (!inst.operands[2].isreg) |
b99bd4ef | 10376 | { |
16805f35 PB |
10377 | int add; |
10378 | ||
fdfde340 JM |
10379 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
10380 | ||
16805f35 PB |
10381 | add = (inst.instruction == T_MNEM_add |
10382 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
10383 | opcode = 0; |
10384 | if (inst.size_req != 4) | |
10385 | { | |
0110f2b8 | 10386 | /* Attempt to use a narrow opcode, with relaxation if |
477330fc | 10387 | appropriate. */ |
0110f2b8 PB |
10388 | if (Rd == REG_SP && Rs == REG_SP && !flags) |
10389 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
10390 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
10391 | opcode = T_MNEM_add_sp; | |
10392 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
10393 | opcode = T_MNEM_add_pc; | |
10394 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
10395 | { | |
10396 | if (flags) | |
10397 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
10398 | else | |
10399 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
10400 | } | |
10401 | if (opcode) | |
10402 | { | |
10403 | inst.instruction = THUMB_OP16(opcode); | |
10404 | inst.instruction |= (Rd << 4) | Rs; | |
10405 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10406 | if (inst.size_req != 2) | |
10407 | inst.relax = opcode; | |
10408 | } | |
10409 | else | |
10410 | constraint (inst.size_req == 2, BAD_HIREG); | |
10411 | } | |
10412 | if (inst.size_req == 4 | |
10413 | || (inst.size_req != 2 && !opcode)) | |
10414 | { | |
efd81785 PB |
10415 | if (Rd == REG_PC) |
10416 | { | |
fdfde340 | 10417 | constraint (add, BAD_PC); |
efd81785 PB |
10418 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
10419 | _("only SUBS PC, LR, #const allowed")); | |
10420 | constraint (inst.reloc.exp.X_op != O_constant, | |
10421 | _("expression too complex")); | |
10422 | constraint (inst.reloc.exp.X_add_number < 0 | |
10423 | || inst.reloc.exp.X_add_number > 0xff, | |
10424 | _("immediate value out of range")); | |
10425 | inst.instruction = T2_SUBS_PC_LR | |
10426 | | inst.reloc.exp.X_add_number; | |
10427 | inst.reloc.type = BFD_RELOC_UNUSED; | |
10428 | return; | |
10429 | } | |
10430 | else if (Rs == REG_PC) | |
16805f35 PB |
10431 | { |
10432 | /* Always use addw/subw. */ | |
10433 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
10434 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
10435 | } | |
10436 | else | |
10437 | { | |
10438 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10439 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
10440 | | 0x10000000; | |
10441 | if (flags) | |
10442 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10443 | else | |
10444 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
10445 | } | |
dc4503c6 PB |
10446 | inst.instruction |= Rd << 8; |
10447 | inst.instruction |= Rs << 16; | |
0110f2b8 | 10448 | } |
b99bd4ef | 10449 | } |
c19d1205 ZW |
10450 | else |
10451 | { | |
5f4cb198 NC |
10452 | unsigned int value = inst.reloc.exp.X_add_number; |
10453 | unsigned int shift = inst.operands[2].shift_kind; | |
10454 | ||
c19d1205 ZW |
10455 | Rn = inst.operands[2].reg; |
10456 | /* See if we can do this with a 16-bit instruction. */ | |
10457 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
10458 | { | |
e27ec89e PB |
10459 | if (Rd > 7 || Rs > 7 || Rn > 7) |
10460 | narrow = FALSE; | |
10461 | ||
10462 | if (narrow) | |
c19d1205 | 10463 | { |
e27ec89e PB |
10464 | inst.instruction = ((inst.instruction == T_MNEM_adds |
10465 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
10466 | ? T_OPCODE_ADD_R3 |
10467 | : T_OPCODE_SUB_R3); | |
10468 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
10469 | return; | |
10470 | } | |
b99bd4ef | 10471 | |
7e806470 | 10472 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 10473 | { |
7e806470 PB |
10474 | /* Thumb-1 cores (except v6-M) require at least one high |
10475 | register in a narrow non flag setting add. */ | |
10476 | if (Rd > 7 || Rn > 7 | |
10477 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
10478 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 10479 | { |
7e806470 PB |
10480 | if (Rd == Rn) |
10481 | { | |
10482 | Rn = Rs; | |
10483 | Rs = Rd; | |
10484 | } | |
c19d1205 ZW |
10485 | inst.instruction = T_OPCODE_ADD_HI; |
10486 | inst.instruction |= (Rd & 8) << 4; | |
10487 | inst.instruction |= (Rd & 7); | |
10488 | inst.instruction |= Rn << 3; | |
10489 | return; | |
10490 | } | |
c19d1205 ZW |
10491 | } |
10492 | } | |
c921be7d | 10493 | |
fdfde340 JM |
10494 | constraint (Rd == REG_PC, BAD_PC); |
10495 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
10496 | constraint (Rs == REG_PC, BAD_PC); | |
10497 | reject_bad_reg (Rn); | |
10498 | ||
c19d1205 ZW |
10499 | /* If we get here, it can't be done in 16 bits. */ |
10500 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
10501 | _("shift must be constant")); | |
10502 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10503 | inst.instruction |= Rd << 8; | |
10504 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
10505 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
10506 | _("shift value over 3 not allowed in thumb mode")); | |
10507 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
10508 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
10509 | encode_thumb32_shifted_operand (2); |
10510 | } | |
10511 | } | |
10512 | else | |
10513 | { | |
10514 | constraint (inst.instruction == T_MNEM_adds | |
10515 | || inst.instruction == T_MNEM_subs, | |
10516 | BAD_THUMB32); | |
b99bd4ef | 10517 | |
c19d1205 | 10518 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 10519 | { |
c19d1205 ZW |
10520 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
10521 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
10522 | BAD_HIREG); | |
10523 | ||
10524 | inst.instruction = (inst.instruction == T_MNEM_add | |
10525 | ? 0x0000 : 0x8000); | |
10526 | inst.instruction |= (Rd << 4) | Rs; | |
10527 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
10528 | return; |
10529 | } | |
10530 | ||
c19d1205 ZW |
10531 | Rn = inst.operands[2].reg; |
10532 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 10533 | |
c19d1205 ZW |
10534 | /* We now have Rd, Rs, and Rn set to registers. */ |
10535 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 10536 | { |
c19d1205 ZW |
10537 | /* Can't do this for SUB. */ |
10538 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
10539 | inst.instruction = T_OPCODE_ADD_HI; | |
10540 | inst.instruction |= (Rd & 8) << 4; | |
10541 | inst.instruction |= (Rd & 7); | |
10542 | if (Rs == Rd) | |
10543 | inst.instruction |= Rn << 3; | |
10544 | else if (Rn == Rd) | |
10545 | inst.instruction |= Rs << 3; | |
10546 | else | |
10547 | constraint (1, _("dest must overlap one source register")); | |
10548 | } | |
10549 | else | |
10550 | { | |
10551 | inst.instruction = (inst.instruction == T_MNEM_add | |
10552 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
10553 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 10554 | } |
b99bd4ef | 10555 | } |
b99bd4ef NC |
10556 | } |
10557 | ||
c19d1205 ZW |
10558 | static void |
10559 | do_t_adr (void) | |
10560 | { | |
fdfde340 JM |
10561 | unsigned Rd; |
10562 | ||
10563 | Rd = inst.operands[0].reg; | |
10564 | reject_bad_reg (Rd); | |
10565 | ||
10566 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
10567 | { |
10568 | /* Defer to section relaxation. */ | |
10569 | inst.relax = inst.instruction; | |
10570 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 10571 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
10572 | } |
10573 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 10574 | { |
0110f2b8 | 10575 | /* Generate a 32-bit opcode. */ |
e9f89963 | 10576 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 10577 | inst.instruction |= Rd << 8; |
e9f89963 PB |
10578 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
10579 | inst.reloc.pc_rel = 1; | |
10580 | } | |
10581 | else | |
10582 | { | |
0110f2b8 | 10583 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
10584 | inst.instruction = THUMB_OP16 (inst.instruction); |
10585 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
10586 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
10587 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 10588 | |
fdfde340 | 10589 | inst.instruction |= Rd << 4; |
e9f89963 | 10590 | } |
c19d1205 | 10591 | } |
b99bd4ef | 10592 | |
c19d1205 ZW |
10593 | /* Arithmetic instructions for which there is just one 16-bit |
10594 | instruction encoding, and it allows only two low registers. | |
10595 | For maximal compatibility with ARM syntax, we allow three register | |
10596 | operands even when Thumb-32 instructions are not available, as long | |
10597 | as the first two are identical. For instance, both "sbc r0,r1" and | |
10598 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 10599 | static void |
c19d1205 | 10600 | do_t_arit3 (void) |
b99bd4ef | 10601 | { |
c19d1205 | 10602 | int Rd, Rs, Rn; |
b99bd4ef | 10603 | |
c19d1205 ZW |
10604 | Rd = inst.operands[0].reg; |
10605 | Rs = (inst.operands[1].present | |
10606 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10607 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10608 | Rn = inst.operands[2].reg; | |
b99bd4ef | 10609 | |
fdfde340 JM |
10610 | reject_bad_reg (Rd); |
10611 | reject_bad_reg (Rs); | |
10612 | if (inst.operands[2].isreg) | |
10613 | reject_bad_reg (Rn); | |
10614 | ||
c19d1205 | 10615 | if (unified_syntax) |
b99bd4ef | 10616 | { |
c19d1205 ZW |
10617 | if (!inst.operands[2].isreg) |
10618 | { | |
10619 | /* For an immediate, we always generate a 32-bit opcode; | |
10620 | section relaxation will shrink it later if possible. */ | |
10621 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10622 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10623 | inst.instruction |= Rd << 8; | |
10624 | inst.instruction |= Rs << 16; | |
10625 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10626 | } | |
10627 | else | |
10628 | { | |
e27ec89e PB |
10629 | bfd_boolean narrow; |
10630 | ||
c19d1205 | 10631 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10632 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10633 | narrow = !in_it_block (); |
e27ec89e | 10634 | else |
e07e6e58 | 10635 | narrow = in_it_block (); |
e27ec89e PB |
10636 | |
10637 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10638 | narrow = FALSE; | |
10639 | if (inst.operands[2].shifted) | |
10640 | narrow = FALSE; | |
10641 | if (inst.size_req == 4) | |
10642 | narrow = FALSE; | |
10643 | ||
10644 | if (narrow | |
c19d1205 ZW |
10645 | && Rd == Rs) |
10646 | { | |
10647 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10648 | inst.instruction |= Rd; | |
10649 | inst.instruction |= Rn << 3; | |
10650 | return; | |
10651 | } | |
b99bd4ef | 10652 | |
c19d1205 ZW |
10653 | /* If we get here, it can't be done in 16 bits. */ |
10654 | constraint (inst.operands[2].shifted | |
10655 | && inst.operands[2].immisreg, | |
10656 | _("shift must be constant")); | |
10657 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10658 | inst.instruction |= Rd << 8; | |
10659 | inst.instruction |= Rs << 16; | |
10660 | encode_thumb32_shifted_operand (2); | |
10661 | } | |
a737bd4d | 10662 | } |
c19d1205 | 10663 | else |
b99bd4ef | 10664 | { |
c19d1205 ZW |
10665 | /* On its face this is a lie - the instruction does set the |
10666 | flags. However, the only supported mnemonic in this mode | |
10667 | says it doesn't. */ | |
10668 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10669 | |
c19d1205 ZW |
10670 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10671 | _("unshifted register required")); | |
10672 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10673 | constraint (Rd != Rs, | |
10674 | _("dest and source1 must be the same register")); | |
a737bd4d | 10675 | |
c19d1205 ZW |
10676 | inst.instruction = THUMB_OP16 (inst.instruction); |
10677 | inst.instruction |= Rd; | |
10678 | inst.instruction |= Rn << 3; | |
b99bd4ef | 10679 | } |
a737bd4d | 10680 | } |
b99bd4ef | 10681 | |
c19d1205 ZW |
10682 | /* Similarly, but for instructions where the arithmetic operation is |
10683 | commutative, so we can allow either of them to be different from | |
10684 | the destination operand in a 16-bit instruction. For instance, all | |
10685 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
10686 | accepted. */ | |
10687 | static void | |
10688 | do_t_arit3c (void) | |
a737bd4d | 10689 | { |
c19d1205 | 10690 | int Rd, Rs, Rn; |
b99bd4ef | 10691 | |
c19d1205 ZW |
10692 | Rd = inst.operands[0].reg; |
10693 | Rs = (inst.operands[1].present | |
10694 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
10695 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
10696 | Rn = inst.operands[2].reg; | |
c921be7d | 10697 | |
fdfde340 JM |
10698 | reject_bad_reg (Rd); |
10699 | reject_bad_reg (Rs); | |
10700 | if (inst.operands[2].isreg) | |
10701 | reject_bad_reg (Rn); | |
a737bd4d | 10702 | |
c19d1205 | 10703 | if (unified_syntax) |
a737bd4d | 10704 | { |
c19d1205 | 10705 | if (!inst.operands[2].isreg) |
b99bd4ef | 10706 | { |
c19d1205 ZW |
10707 | /* For an immediate, we always generate a 32-bit opcode; |
10708 | section relaxation will shrink it later if possible. */ | |
10709 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10710 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
10711 | inst.instruction |= Rd << 8; | |
10712 | inst.instruction |= Rs << 16; | |
10713 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 10714 | } |
c19d1205 | 10715 | else |
a737bd4d | 10716 | { |
e27ec89e PB |
10717 | bfd_boolean narrow; |
10718 | ||
c19d1205 | 10719 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 10720 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 10721 | narrow = !in_it_block (); |
e27ec89e | 10722 | else |
e07e6e58 | 10723 | narrow = in_it_block (); |
e27ec89e PB |
10724 | |
10725 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
10726 | narrow = FALSE; | |
10727 | if (inst.operands[2].shifted) | |
10728 | narrow = FALSE; | |
10729 | if (inst.size_req == 4) | |
10730 | narrow = FALSE; | |
10731 | ||
10732 | if (narrow) | |
a737bd4d | 10733 | { |
c19d1205 | 10734 | if (Rd == Rs) |
a737bd4d | 10735 | { |
c19d1205 ZW |
10736 | inst.instruction = THUMB_OP16 (inst.instruction); |
10737 | inst.instruction |= Rd; | |
10738 | inst.instruction |= Rn << 3; | |
10739 | return; | |
a737bd4d | 10740 | } |
c19d1205 | 10741 | if (Rd == Rn) |
a737bd4d | 10742 | { |
c19d1205 ZW |
10743 | inst.instruction = THUMB_OP16 (inst.instruction); |
10744 | inst.instruction |= Rd; | |
10745 | inst.instruction |= Rs << 3; | |
10746 | return; | |
a737bd4d NC |
10747 | } |
10748 | } | |
c19d1205 ZW |
10749 | |
10750 | /* If we get here, it can't be done in 16 bits. */ | |
10751 | constraint (inst.operands[2].shifted | |
10752 | && inst.operands[2].immisreg, | |
10753 | _("shift must be constant")); | |
10754 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10755 | inst.instruction |= Rd << 8; | |
10756 | inst.instruction |= Rs << 16; | |
10757 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 10758 | } |
b99bd4ef | 10759 | } |
c19d1205 ZW |
10760 | else |
10761 | { | |
10762 | /* On its face this is a lie - the instruction does set the | |
10763 | flags. However, the only supported mnemonic in this mode | |
10764 | says it doesn't. */ | |
10765 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 10766 | |
c19d1205 ZW |
10767 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
10768 | _("unshifted register required")); | |
10769 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
10770 | ||
10771 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10772 | inst.instruction |= Rd; | |
10773 | ||
10774 | if (Rd == Rs) | |
10775 | inst.instruction |= Rn << 3; | |
10776 | else if (Rd == Rn) | |
10777 | inst.instruction |= Rs << 3; | |
10778 | else | |
10779 | constraint (1, _("dest must overlap one source register")); | |
10780 | } | |
a737bd4d NC |
10781 | } |
10782 | ||
c19d1205 ZW |
10783 | static void |
10784 | do_t_bfc (void) | |
a737bd4d | 10785 | { |
fdfde340 | 10786 | unsigned Rd; |
c19d1205 ZW |
10787 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
10788 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10789 | /* The instruction encoding stores the LSB and MSB, | |
10790 | not the LSB and width. */ | |
fdfde340 JM |
10791 | Rd = inst.operands[0].reg; |
10792 | reject_bad_reg (Rd); | |
10793 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
10794 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
10795 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
10796 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10797 | } |
10798 | ||
c19d1205 ZW |
10799 | static void |
10800 | do_t_bfi (void) | |
b99bd4ef | 10801 | { |
fdfde340 | 10802 | int Rd, Rn; |
c19d1205 | 10803 | unsigned int msb; |
b99bd4ef | 10804 | |
fdfde340 JM |
10805 | Rd = inst.operands[0].reg; |
10806 | reject_bad_reg (Rd); | |
10807 | ||
c19d1205 ZW |
10808 | /* #0 in second position is alternative syntax for bfc, which is |
10809 | the same instruction but with REG_PC in the Rm field. */ | |
10810 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
10811 | Rn = REG_PC; |
10812 | else | |
10813 | { | |
10814 | Rn = inst.operands[1].reg; | |
10815 | reject_bad_reg (Rn); | |
10816 | } | |
b99bd4ef | 10817 | |
c19d1205 ZW |
10818 | msb = inst.operands[2].imm + inst.operands[3].imm; |
10819 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10820 | /* The instruction encoding stores the LSB and MSB, | |
10821 | not the LSB and width. */ | |
fdfde340 JM |
10822 | inst.instruction |= Rd << 8; |
10823 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10824 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10825 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10826 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10827 | } |
10828 | ||
c19d1205 ZW |
10829 | static void |
10830 | do_t_bfx (void) | |
b99bd4ef | 10831 | { |
fdfde340 JM |
10832 | unsigned Rd, Rn; |
10833 | ||
10834 | Rd = inst.operands[0].reg; | |
10835 | Rn = inst.operands[1].reg; | |
10836 | ||
10837 | reject_bad_reg (Rd); | |
10838 | reject_bad_reg (Rn); | |
10839 | ||
c19d1205 ZW |
10840 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
10841 | _("bit-field extends past end of register")); | |
fdfde340 JM |
10842 | inst.instruction |= Rd << 8; |
10843 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10844 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10845 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10846 | inst.instruction |= inst.operands[3].imm - 1; | |
10847 | } | |
b99bd4ef | 10848 | |
c19d1205 ZW |
10849 | /* ARM V5 Thumb BLX (argument parse) |
10850 | BLX <target_addr> which is BLX(1) | |
10851 | BLX <Rm> which is BLX(2) | |
10852 | Unfortunately, there are two different opcodes for this mnemonic. | |
10853 | So, the insns[].value is not used, and the code here zaps values | |
10854 | into inst.instruction. | |
b99bd4ef | 10855 | |
c19d1205 ZW |
10856 | ??? How to take advantage of the additional two bits of displacement |
10857 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 10858 | |
c19d1205 ZW |
10859 | static void |
10860 | do_t_blx (void) | |
10861 | { | |
e07e6e58 NC |
10862 | set_it_insn_type_last (); |
10863 | ||
c19d1205 | 10864 | if (inst.operands[0].isreg) |
fdfde340 JM |
10865 | { |
10866 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
10867 | /* We have a register, so this is BLX(2). */ | |
10868 | inst.instruction |= inst.operands[0].reg << 3; | |
10869 | } | |
b99bd4ef NC |
10870 | else |
10871 | { | |
c19d1205 | 10872 | /* No register. This must be BLX(1). */ |
2fc8bdac | 10873 | inst.instruction = 0xf000e800; |
0855e32b | 10874 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
10875 | } |
10876 | } | |
10877 | ||
c19d1205 ZW |
10878 | static void |
10879 | do_t_branch (void) | |
b99bd4ef | 10880 | { |
0110f2b8 | 10881 | int opcode; |
dfa9f0d5 | 10882 | int cond; |
9ae92b05 | 10883 | int reloc; |
dfa9f0d5 | 10884 | |
e07e6e58 NC |
10885 | cond = inst.cond; |
10886 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
10887 | ||
10888 | if (in_it_block ()) | |
dfa9f0d5 PB |
10889 | { |
10890 | /* Conditional branches inside IT blocks are encoded as unconditional | |
477330fc | 10891 | branches. */ |
dfa9f0d5 | 10892 | cond = COND_ALWAYS; |
dfa9f0d5 PB |
10893 | } |
10894 | else | |
10895 | cond = inst.cond; | |
10896 | ||
10897 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
10898 | opcode = T_MNEM_bcond; |
10899 | else | |
10900 | opcode = inst.instruction; | |
10901 | ||
12d6b0b7 RS |
10902 | if (unified_syntax |
10903 | && (inst.size_req == 4 | |
10960bfb PB |
10904 | || (inst.size_req != 2 |
10905 | && (inst.operands[0].hasreloc | |
10906 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10907 | { |
0110f2b8 | 10908 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10909 | if (cond == COND_ALWAYS) |
9ae92b05 | 10910 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10911 | else |
10912 | { | |
9c2799c2 | 10913 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10914 | inst.instruction |= cond << 22; |
9ae92b05 | 10915 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10916 | } |
10917 | } | |
b99bd4ef NC |
10918 | else |
10919 | { | |
0110f2b8 | 10920 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10921 | if (cond == COND_ALWAYS) |
9ae92b05 | 10922 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10923 | else |
b99bd4ef | 10924 | { |
dfa9f0d5 | 10925 | inst.instruction |= cond << 8; |
9ae92b05 | 10926 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10927 | } |
0110f2b8 PB |
10928 | /* Allow section relaxation. */ |
10929 | if (unified_syntax && inst.size_req != 2) | |
10930 | inst.relax = opcode; | |
b99bd4ef | 10931 | } |
9ae92b05 | 10932 | inst.reloc.type = reloc; |
c19d1205 | 10933 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10934 | } |
10935 | ||
8884b720 | 10936 | /* Actually do the work for Thumb state bkpt and hlt. The only difference |
bacebabc | 10937 | between the two is the maximum immediate allowed - which is passed in |
8884b720 | 10938 | RANGE. */ |
b99bd4ef | 10939 | static void |
8884b720 | 10940 | do_t_bkpt_hlt1 (int range) |
b99bd4ef | 10941 | { |
dfa9f0d5 PB |
10942 | constraint (inst.cond != COND_ALWAYS, |
10943 | _("instruction is always unconditional")); | |
c19d1205 | 10944 | if (inst.operands[0].present) |
b99bd4ef | 10945 | { |
8884b720 | 10946 | constraint (inst.operands[0].imm > range, |
c19d1205 ZW |
10947 | _("immediate value out of range")); |
10948 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 10949 | } |
8884b720 MGD |
10950 | |
10951 | set_it_insn_type (NEUTRAL_IT_INSN); | |
10952 | } | |
10953 | ||
10954 | static void | |
10955 | do_t_hlt (void) | |
10956 | { | |
10957 | do_t_bkpt_hlt1 (63); | |
10958 | } | |
10959 | ||
10960 | static void | |
10961 | do_t_bkpt (void) | |
10962 | { | |
10963 | do_t_bkpt_hlt1 (255); | |
b99bd4ef NC |
10964 | } |
10965 | ||
10966 | static void | |
c19d1205 | 10967 | do_t_branch23 (void) |
b99bd4ef | 10968 | { |
e07e6e58 | 10969 | set_it_insn_type_last (); |
0855e32b | 10970 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 10971 | |
0855e32b NS |
10972 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
10973 | this file. We used to simply ignore the PLT reloc type here -- | |
10974 | the branch encoding is now needed to deal with TLSCALL relocs. | |
10975 | So if we see a PLT reloc now, put it back to how it used to be to | |
10976 | keep the preexisting behaviour. */ | |
10977 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
10978 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 10979 | |
4343666d | 10980 | #if defined(OBJ_COFF) |
c19d1205 ZW |
10981 | /* If the destination of the branch is a defined symbol which does not have |
10982 | the THUMB_FUNC attribute, then we must be calling a function which has | |
10983 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
10984 | function and change the branch to refer to that function instead. */ | |
10985 | if ( inst.reloc.exp.X_op == O_symbol | |
10986 | && inst.reloc.exp.X_add_symbol != NULL | |
10987 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10988 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10989 | inst.reloc.exp.X_add_symbol = | |
10990 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 10991 | #endif |
90e4755a RE |
10992 | } |
10993 | ||
10994 | static void | |
c19d1205 | 10995 | do_t_bx (void) |
90e4755a | 10996 | { |
e07e6e58 | 10997 | set_it_insn_type_last (); |
c19d1205 ZW |
10998 | inst.instruction |= inst.operands[0].reg << 3; |
10999 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
11000 | should cause the alignment to be checked once it is known. This is | |
11001 | because BX PC only works if the instruction is word aligned. */ | |
11002 | } | |
90e4755a | 11003 | |
c19d1205 ZW |
11004 | static void |
11005 | do_t_bxj (void) | |
11006 | { | |
fdfde340 | 11007 | int Rm; |
90e4755a | 11008 | |
e07e6e58 | 11009 | set_it_insn_type_last (); |
fdfde340 JM |
11010 | Rm = inst.operands[0].reg; |
11011 | reject_bad_reg (Rm); | |
11012 | inst.instruction |= Rm << 16; | |
90e4755a RE |
11013 | } |
11014 | ||
11015 | static void | |
c19d1205 | 11016 | do_t_clz (void) |
90e4755a | 11017 | { |
fdfde340 JM |
11018 | unsigned Rd; |
11019 | unsigned Rm; | |
11020 | ||
11021 | Rd = inst.operands[0].reg; | |
11022 | Rm = inst.operands[1].reg; | |
11023 | ||
11024 | reject_bad_reg (Rd); | |
11025 | reject_bad_reg (Rm); | |
11026 | ||
11027 | inst.instruction |= Rd << 8; | |
11028 | inst.instruction |= Rm << 16; | |
11029 | inst.instruction |= Rm; | |
c19d1205 | 11030 | } |
90e4755a | 11031 | |
dfa9f0d5 PB |
11032 | static void |
11033 | do_t_cps (void) | |
11034 | { | |
e07e6e58 | 11035 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
11036 | inst.instruction |= inst.operands[0].imm; |
11037 | } | |
11038 | ||
c19d1205 ZW |
11039 | static void |
11040 | do_t_cpsi (void) | |
11041 | { | |
e07e6e58 | 11042 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 11043 | if (unified_syntax |
62b3e311 PB |
11044 | && (inst.operands[1].present || inst.size_req == 4) |
11045 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 11046 | { |
c19d1205 ZW |
11047 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
11048 | inst.instruction = 0xf3af8000; | |
11049 | inst.instruction |= imod << 9; | |
11050 | inst.instruction |= inst.operands[0].imm << 5; | |
11051 | if (inst.operands[1].present) | |
11052 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 11053 | } |
c19d1205 | 11054 | else |
90e4755a | 11055 | { |
62b3e311 PB |
11056 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
11057 | && (inst.operands[0].imm & 4), | |
11058 | _("selected processor does not support 'A' form " | |
11059 | "of this instruction")); | |
11060 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
11061 | _("Thumb does not support the 2-argument " |
11062 | "form of this instruction")); | |
11063 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 11064 | } |
90e4755a RE |
11065 | } |
11066 | ||
c19d1205 ZW |
11067 | /* THUMB CPY instruction (argument parse). */ |
11068 | ||
90e4755a | 11069 | static void |
c19d1205 | 11070 | do_t_cpy (void) |
90e4755a | 11071 | { |
c19d1205 | 11072 | if (inst.size_req == 4) |
90e4755a | 11073 | { |
c19d1205 ZW |
11074 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
11075 | inst.instruction |= inst.operands[0].reg << 8; | |
11076 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 11077 | } |
c19d1205 | 11078 | else |
90e4755a | 11079 | { |
c19d1205 ZW |
11080 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
11081 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
11082 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 11083 | } |
90e4755a RE |
11084 | } |
11085 | ||
90e4755a | 11086 | static void |
25fe350b | 11087 | do_t_cbz (void) |
90e4755a | 11088 | { |
e07e6e58 | 11089 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11090 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11091 | inst.instruction |= inst.operands[0].reg; | |
11092 | inst.reloc.pc_rel = 1; | |
11093 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
11094 | } | |
90e4755a | 11095 | |
62b3e311 PB |
11096 | static void |
11097 | do_t_dbg (void) | |
11098 | { | |
11099 | inst.instruction |= inst.operands[0].imm; | |
11100 | } | |
11101 | ||
11102 | static void | |
11103 | do_t_div (void) | |
11104 | { | |
fdfde340 JM |
11105 | unsigned Rd, Rn, Rm; |
11106 | ||
11107 | Rd = inst.operands[0].reg; | |
11108 | Rn = (inst.operands[1].present | |
11109 | ? inst.operands[1].reg : Rd); | |
11110 | Rm = inst.operands[2].reg; | |
11111 | ||
11112 | reject_bad_reg (Rd); | |
11113 | reject_bad_reg (Rn); | |
11114 | reject_bad_reg (Rm); | |
11115 | ||
11116 | inst.instruction |= Rd << 8; | |
11117 | inst.instruction |= Rn << 16; | |
11118 | inst.instruction |= Rm; | |
62b3e311 PB |
11119 | } |
11120 | ||
c19d1205 ZW |
11121 | static void |
11122 | do_t_hint (void) | |
11123 | { | |
11124 | if (unified_syntax && inst.size_req == 4) | |
11125 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11126 | else | |
11127 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11128 | } | |
90e4755a | 11129 | |
c19d1205 ZW |
11130 | static void |
11131 | do_t_it (void) | |
11132 | { | |
11133 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 11134 | |
e07e6e58 NC |
11135 | set_it_insn_type (IT_INSN); |
11136 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
11137 | now_it.cc = cond; | |
5a01bb1d | 11138 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
11139 | |
11140 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 11141 | if ((cond & 0x1) == 0x0) |
90e4755a | 11142 | { |
c19d1205 | 11143 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 11144 | |
c19d1205 | 11145 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
11146 | { |
11147 | /* No conversion needed. */ | |
11148 | now_it.block_length = 1; | |
11149 | } | |
c19d1205 | 11150 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
11151 | { |
11152 | mask ^= 0x8; | |
11153 | now_it.block_length = 2; | |
11154 | } | |
e27ec89e | 11155 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
11156 | { |
11157 | mask ^= 0xC; | |
11158 | now_it.block_length = 3; | |
11159 | } | |
c19d1205 | 11160 | else |
5a01bb1d MGD |
11161 | { |
11162 | mask ^= 0xE; | |
11163 | now_it.block_length = 4; | |
11164 | } | |
90e4755a | 11165 | |
e27ec89e PB |
11166 | inst.instruction &= 0xfff0; |
11167 | inst.instruction |= mask; | |
c19d1205 | 11168 | } |
90e4755a | 11169 | |
c19d1205 ZW |
11170 | inst.instruction |= cond << 4; |
11171 | } | |
90e4755a | 11172 | |
3c707909 PB |
11173 | /* Helper function used for both push/pop and ldm/stm. */ |
11174 | static void | |
11175 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
11176 | { | |
11177 | bfd_boolean load; | |
11178 | ||
11179 | load = (inst.instruction & (1 << 20)) != 0; | |
11180 | ||
11181 | if (mask & (1 << 13)) | |
11182 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
11183 | |
11184 | if ((mask & (1 << base)) != 0 | |
11185 | && writeback) | |
11186 | inst.error = _("having the base register in the register list when " | |
11187 | "using write back is UNPREDICTABLE"); | |
11188 | ||
3c707909 PB |
11189 | if (load) |
11190 | { | |
e07e6e58 | 11191 | if (mask & (1 << 15)) |
477330fc RM |
11192 | { |
11193 | if (mask & (1 << 14)) | |
11194 | inst.error = _("LR and PC should not both be in register list"); | |
11195 | else | |
11196 | set_it_insn_type_last (); | |
11197 | } | |
3c707909 PB |
11198 | } |
11199 | else | |
11200 | { | |
11201 | if (mask & (1 << 15)) | |
11202 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
11203 | } |
11204 | ||
11205 | if ((mask & (mask - 1)) == 0) | |
11206 | { | |
11207 | /* Single register transfers implemented as str/ldr. */ | |
11208 | if (writeback) | |
11209 | { | |
11210 | if (inst.instruction & (1 << 23)) | |
11211 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
11212 | else | |
11213 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
11214 | } | |
11215 | else | |
11216 | { | |
11217 | if (inst.instruction & (1 << 23)) | |
11218 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
11219 | else | |
11220 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
11221 | } | |
11222 | ||
11223 | inst.instruction |= 0xf8400000; | |
11224 | if (load) | |
11225 | inst.instruction |= 0x00100000; | |
11226 | ||
5f4273c7 | 11227 | mask = ffs (mask) - 1; |
3c707909 PB |
11228 | mask <<= 12; |
11229 | } | |
11230 | else if (writeback) | |
11231 | inst.instruction |= WRITE_BACK; | |
11232 | ||
11233 | inst.instruction |= mask; | |
11234 | inst.instruction |= base << 16; | |
11235 | } | |
11236 | ||
c19d1205 ZW |
11237 | static void |
11238 | do_t_ldmstm (void) | |
11239 | { | |
11240 | /* This really doesn't seem worth it. */ | |
11241 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11242 | _("expression too complex")); | |
11243 | constraint (inst.operands[1].writeback, | |
11244 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 11245 | |
c19d1205 ZW |
11246 | if (unified_syntax) |
11247 | { | |
3c707909 PB |
11248 | bfd_boolean narrow; |
11249 | unsigned mask; | |
11250 | ||
11251 | narrow = FALSE; | |
c19d1205 ZW |
11252 | /* See if we can use a 16-bit instruction. */ |
11253 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
11254 | && inst.size_req != 4 | |
3c707909 | 11255 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 11256 | { |
3c707909 | 11257 | mask = 1 << inst.operands[0].reg; |
90e4755a | 11258 | |
eab4f823 | 11259 | if (inst.operands[0].reg <= 7) |
90e4755a | 11260 | { |
3c707909 | 11261 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
11262 | ? inst.operands[0].writeback |
11263 | : (inst.operands[0].writeback | |
11264 | == !(inst.operands[1].imm & mask))) | |
477330fc | 11265 | { |
eab4f823 MGD |
11266 | if (inst.instruction == T_MNEM_stmia |
11267 | && (inst.operands[1].imm & mask) | |
11268 | && (inst.operands[1].imm & (mask - 1))) | |
11269 | as_warn (_("value stored for r%d is UNKNOWN"), | |
11270 | inst.operands[0].reg); | |
3c707909 | 11271 | |
eab4f823 MGD |
11272 | inst.instruction = THUMB_OP16 (inst.instruction); |
11273 | inst.instruction |= inst.operands[0].reg << 8; | |
11274 | inst.instruction |= inst.operands[1].imm; | |
11275 | narrow = TRUE; | |
11276 | } | |
11277 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11278 | { | |
11279 | /* This means 1 register in reg list one of 3 situations: | |
11280 | 1. Instruction is stmia, but without writeback. | |
11281 | 2. lmdia without writeback, but with Rn not in | |
477330fc | 11282 | reglist. |
eab4f823 MGD |
11283 | 3. ldmia with writeback, but with Rn in reglist. |
11284 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
11285 | case 1 and 2 which can be converted into a 16-bit | |
11286 | str or ldr. The SP cases are handled below. */ | |
11287 | unsigned long opcode; | |
11288 | /* First, record an error for Case 3. */ | |
11289 | if (inst.operands[1].imm & mask | |
11290 | && inst.operands[0].writeback) | |
fa94de6b | 11291 | inst.error = |
eab4f823 MGD |
11292 | _("having the base register in the register list when " |
11293 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
11294 | |
11295 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
11296 | : T_MNEM_ldr); |
11297 | inst.instruction = THUMB_OP16 (opcode); | |
11298 | inst.instruction |= inst.operands[0].reg << 3; | |
11299 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
11300 | narrow = TRUE; | |
11301 | } | |
90e4755a | 11302 | } |
eab4f823 | 11303 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 11304 | { |
eab4f823 MGD |
11305 | if (inst.operands[0].writeback) |
11306 | { | |
fa94de6b | 11307 | inst.instruction = |
eab4f823 | 11308 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11309 | ? T_MNEM_push : T_MNEM_pop); |
eab4f823 | 11310 | inst.instruction |= inst.operands[1].imm; |
477330fc | 11311 | narrow = TRUE; |
eab4f823 MGD |
11312 | } |
11313 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
11314 | { | |
fa94de6b | 11315 | inst.instruction = |
eab4f823 | 11316 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
477330fc | 11317 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); |
eab4f823 | 11318 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); |
477330fc | 11319 | narrow = TRUE; |
eab4f823 | 11320 | } |
90e4755a | 11321 | } |
3c707909 PB |
11322 | } |
11323 | ||
11324 | if (!narrow) | |
11325 | { | |
c19d1205 ZW |
11326 | if (inst.instruction < 0xffff) |
11327 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 11328 | |
5f4273c7 NC |
11329 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
11330 | inst.operands[0].writeback); | |
90e4755a RE |
11331 | } |
11332 | } | |
c19d1205 | 11333 | else |
90e4755a | 11334 | { |
c19d1205 ZW |
11335 | constraint (inst.operands[0].reg > 7 |
11336 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
11337 | constraint (inst.instruction != T_MNEM_ldmia |
11338 | && inst.instruction != T_MNEM_stmia, | |
11339 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 11340 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 11341 | { |
c19d1205 ZW |
11342 | if (!inst.operands[0].writeback) |
11343 | as_warn (_("this instruction will write back the base register")); | |
11344 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
11345 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 11346 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 11347 | inst.operands[0].reg); |
f03698e6 | 11348 | } |
c19d1205 | 11349 | else |
90e4755a | 11350 | { |
c19d1205 ZW |
11351 | if (!inst.operands[0].writeback |
11352 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11353 | as_warn (_("this instruction will write back the base register")); | |
11354 | else if (inst.operands[0].writeback | |
11355 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
11356 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
11357 | } |
11358 | ||
c19d1205 ZW |
11359 | inst.instruction = THUMB_OP16 (inst.instruction); |
11360 | inst.instruction |= inst.operands[0].reg << 8; | |
11361 | inst.instruction |= inst.operands[1].imm; | |
11362 | } | |
11363 | } | |
e28cd48c | 11364 | |
c19d1205 ZW |
11365 | static void |
11366 | do_t_ldrex (void) | |
11367 | { | |
11368 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
11369 | || inst.operands[1].postind || inst.operands[1].writeback | |
11370 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
11371 | || inst.operands[1].negative, | |
01cfc07f | 11372 | BAD_ADDR_MODE); |
e28cd48c | 11373 | |
5be8be5d DG |
11374 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
11375 | ||
c19d1205 ZW |
11376 | inst.instruction |= inst.operands[0].reg << 12; |
11377 | inst.instruction |= inst.operands[1].reg << 16; | |
11378 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
11379 | } | |
e28cd48c | 11380 | |
c19d1205 ZW |
11381 | static void |
11382 | do_t_ldrexd (void) | |
11383 | { | |
11384 | if (!inst.operands[1].present) | |
1cac9012 | 11385 | { |
c19d1205 ZW |
11386 | constraint (inst.operands[0].reg == REG_LR, |
11387 | _("r14 not allowed as first register " | |
11388 | "when second register is omitted")); | |
11389 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 11390 | } |
c19d1205 ZW |
11391 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
11392 | BAD_OVERLAP); | |
b99bd4ef | 11393 | |
c19d1205 ZW |
11394 | inst.instruction |= inst.operands[0].reg << 12; |
11395 | inst.instruction |= inst.operands[1].reg << 8; | |
11396 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
11397 | } |
11398 | ||
11399 | static void | |
c19d1205 | 11400 | do_t_ldst (void) |
b99bd4ef | 11401 | { |
0110f2b8 PB |
11402 | unsigned long opcode; |
11403 | int Rn; | |
11404 | ||
e07e6e58 NC |
11405 | if (inst.operands[0].isreg |
11406 | && !inst.operands[0].preind | |
11407 | && inst.operands[0].reg == REG_PC) | |
11408 | set_it_insn_type_last (); | |
11409 | ||
0110f2b8 | 11410 | opcode = inst.instruction; |
c19d1205 | 11411 | if (unified_syntax) |
b99bd4ef | 11412 | { |
53365c0d PB |
11413 | if (!inst.operands[1].isreg) |
11414 | { | |
11415 | if (opcode <= 0xffff) | |
11416 | inst.instruction = THUMB_OP32 (opcode); | |
8335d6aa | 11417 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
53365c0d PB |
11418 | return; |
11419 | } | |
0110f2b8 PB |
11420 | if (inst.operands[1].isreg |
11421 | && !inst.operands[1].writeback | |
c19d1205 ZW |
11422 | && !inst.operands[1].shifted && !inst.operands[1].postind |
11423 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
11424 | && opcode <= 0xffff |
11425 | && inst.size_req != 4) | |
c19d1205 | 11426 | { |
0110f2b8 PB |
11427 | /* Insn may have a 16-bit form. */ |
11428 | Rn = inst.operands[1].reg; | |
11429 | if (inst.operands[1].immisreg) | |
11430 | { | |
11431 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 11432 | /* [Rn, Rik] */ |
0110f2b8 PB |
11433 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
11434 | goto op16; | |
5be8be5d DG |
11435 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
11436 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
11437 | } |
11438 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
11439 | && opcode != T_MNEM_ldrsb) | |
11440 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
11441 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
11442 | { | |
11443 | /* [Rn, #const] */ | |
11444 | if (Rn > 7) | |
11445 | { | |
11446 | if (Rn == REG_PC) | |
11447 | { | |
11448 | if (inst.reloc.pc_rel) | |
11449 | opcode = T_MNEM_ldr_pc2; | |
11450 | else | |
11451 | opcode = T_MNEM_ldr_pc; | |
11452 | } | |
11453 | else | |
11454 | { | |
11455 | if (opcode == T_MNEM_ldr) | |
11456 | opcode = T_MNEM_ldr_sp; | |
11457 | else | |
11458 | opcode = T_MNEM_str_sp; | |
11459 | } | |
11460 | inst.instruction = inst.operands[0].reg << 8; | |
11461 | } | |
11462 | else | |
11463 | { | |
11464 | inst.instruction = inst.operands[0].reg; | |
11465 | inst.instruction |= inst.operands[1].reg << 3; | |
11466 | } | |
11467 | inst.instruction |= THUMB_OP16 (opcode); | |
11468 | if (inst.size_req == 2) | |
11469 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11470 | else | |
11471 | inst.relax = opcode; | |
11472 | return; | |
11473 | } | |
c19d1205 | 11474 | } |
0110f2b8 | 11475 | /* Definitely a 32-bit variant. */ |
5be8be5d | 11476 | |
8d67f500 NC |
11477 | /* Warning for Erratum 752419. */ |
11478 | if (opcode == T_MNEM_ldr | |
11479 | && inst.operands[0].reg == REG_SP | |
11480 | && inst.operands[1].writeback == 1 | |
11481 | && !inst.operands[1].immisreg) | |
11482 | { | |
11483 | if (no_cpu_selected () | |
11484 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
477330fc RM |
11485 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) |
11486 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
8d67f500 NC |
11487 | as_warn (_("This instruction may be unpredictable " |
11488 | "if executed on M-profile cores " | |
11489 | "with interrupts enabled.")); | |
11490 | } | |
11491 | ||
5be8be5d | 11492 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 11493 | if (inst.operands[1].immisreg) |
5be8be5d DG |
11494 | reject_bad_reg (inst.operands[1].imm); |
11495 | ||
1be5fd2e NC |
11496 | constraint (inst.operands[1].writeback == 1 |
11497 | && inst.operands[0].reg == inst.operands[1].reg, | |
11498 | BAD_OVERLAP); | |
11499 | ||
0110f2b8 | 11500 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
11501 | inst.instruction |= inst.operands[0].reg << 12; |
11502 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 11503 | check_ldr_r15_aligned (); |
b99bd4ef NC |
11504 | return; |
11505 | } | |
11506 | ||
c19d1205 ZW |
11507 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
11508 | ||
11509 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 11510 | { |
c19d1205 ZW |
11511 | /* Only [Rn,Rm] is acceptable. */ |
11512 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
11513 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
11514 | || inst.operands[1].postind || inst.operands[1].shifted | |
11515 | || inst.operands[1].negative, | |
11516 | _("Thumb does not support this addressing mode")); | |
11517 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11518 | goto op16; | |
b99bd4ef | 11519 | } |
5f4273c7 | 11520 | |
c19d1205 ZW |
11521 | inst.instruction = THUMB_OP16 (inst.instruction); |
11522 | if (!inst.operands[1].isreg) | |
8335d6aa | 11523 | if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) |
c19d1205 | 11524 | return; |
b99bd4ef | 11525 | |
c19d1205 ZW |
11526 | constraint (!inst.operands[1].preind |
11527 | || inst.operands[1].shifted | |
11528 | || inst.operands[1].writeback, | |
11529 | _("Thumb does not support this addressing mode")); | |
11530 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 11531 | { |
c19d1205 ZW |
11532 | constraint (inst.instruction & 0x0600, |
11533 | _("byte or halfword not valid for base register")); | |
11534 | constraint (inst.operands[1].reg == REG_PC | |
11535 | && !(inst.instruction & THUMB_LOAD_BIT), | |
11536 | _("r15 based store not allowed")); | |
11537 | constraint (inst.operands[1].immisreg, | |
11538 | _("invalid base register for register offset")); | |
b99bd4ef | 11539 | |
c19d1205 ZW |
11540 | if (inst.operands[1].reg == REG_PC) |
11541 | inst.instruction = T_OPCODE_LDR_PC; | |
11542 | else if (inst.instruction & THUMB_LOAD_BIT) | |
11543 | inst.instruction = T_OPCODE_LDR_SP; | |
11544 | else | |
11545 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 11546 | |
c19d1205 ZW |
11547 | inst.instruction |= inst.operands[0].reg << 8; |
11548 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11549 | return; | |
11550 | } | |
90e4755a | 11551 | |
c19d1205 ZW |
11552 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
11553 | if (!inst.operands[1].immisreg) | |
11554 | { | |
11555 | /* Immediate offset. */ | |
11556 | inst.instruction |= inst.operands[0].reg; | |
11557 | inst.instruction |= inst.operands[1].reg << 3; | |
11558 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
11559 | return; | |
11560 | } | |
90e4755a | 11561 | |
c19d1205 ZW |
11562 | /* Register offset. */ |
11563 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
11564 | constraint (inst.operands[1].negative, | |
11565 | _("Thumb does not support this addressing mode")); | |
90e4755a | 11566 | |
c19d1205 ZW |
11567 | op16: |
11568 | switch (inst.instruction) | |
11569 | { | |
11570 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
11571 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
11572 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
11573 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
11574 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
11575 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
11576 | case 0x5600 /* ldrsb */: | |
11577 | case 0x5e00 /* ldrsh */: break; | |
11578 | default: abort (); | |
11579 | } | |
90e4755a | 11580 | |
c19d1205 ZW |
11581 | inst.instruction |= inst.operands[0].reg; |
11582 | inst.instruction |= inst.operands[1].reg << 3; | |
11583 | inst.instruction |= inst.operands[1].imm << 6; | |
11584 | } | |
90e4755a | 11585 | |
c19d1205 ZW |
11586 | static void |
11587 | do_t_ldstd (void) | |
11588 | { | |
11589 | if (!inst.operands[1].present) | |
b99bd4ef | 11590 | { |
c19d1205 ZW |
11591 | inst.operands[1].reg = inst.operands[0].reg + 1; |
11592 | constraint (inst.operands[0].reg == REG_LR, | |
11593 | _("r14 not allowed here")); | |
bd340a04 | 11594 | constraint (inst.operands[0].reg == REG_R12, |
477330fc | 11595 | _("r12 not allowed here")); |
b99bd4ef | 11596 | } |
bd340a04 MGD |
11597 | |
11598 | if (inst.operands[2].writeback | |
11599 | && (inst.operands[0].reg == inst.operands[2].reg | |
11600 | || inst.operands[1].reg == inst.operands[2].reg)) | |
11601 | as_warn (_("base register written back, and overlaps " | |
477330fc | 11602 | "one of transfer registers")); |
bd340a04 | 11603 | |
c19d1205 ZW |
11604 | inst.instruction |= inst.operands[0].reg << 12; |
11605 | inst.instruction |= inst.operands[1].reg << 8; | |
11606 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
11607 | } |
11608 | ||
c19d1205 ZW |
11609 | static void |
11610 | do_t_ldstt (void) | |
11611 | { | |
11612 | inst.instruction |= inst.operands[0].reg << 12; | |
11613 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
11614 | } | |
a737bd4d | 11615 | |
b99bd4ef | 11616 | static void |
c19d1205 | 11617 | do_t_mla (void) |
b99bd4ef | 11618 | { |
fdfde340 | 11619 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 11620 | |
fdfde340 JM |
11621 | Rd = inst.operands[0].reg; |
11622 | Rn = inst.operands[1].reg; | |
11623 | Rm = inst.operands[2].reg; | |
11624 | Ra = inst.operands[3].reg; | |
11625 | ||
11626 | reject_bad_reg (Rd); | |
11627 | reject_bad_reg (Rn); | |
11628 | reject_bad_reg (Rm); | |
11629 | reject_bad_reg (Ra); | |
11630 | ||
11631 | inst.instruction |= Rd << 8; | |
11632 | inst.instruction |= Rn << 16; | |
11633 | inst.instruction |= Rm; | |
11634 | inst.instruction |= Ra << 12; | |
c19d1205 | 11635 | } |
b99bd4ef | 11636 | |
c19d1205 ZW |
11637 | static void |
11638 | do_t_mlal (void) | |
11639 | { | |
fdfde340 JM |
11640 | unsigned RdLo, RdHi, Rn, Rm; |
11641 | ||
11642 | RdLo = inst.operands[0].reg; | |
11643 | RdHi = inst.operands[1].reg; | |
11644 | Rn = inst.operands[2].reg; | |
11645 | Rm = inst.operands[3].reg; | |
11646 | ||
11647 | reject_bad_reg (RdLo); | |
11648 | reject_bad_reg (RdHi); | |
11649 | reject_bad_reg (Rn); | |
11650 | reject_bad_reg (Rm); | |
11651 | ||
11652 | inst.instruction |= RdLo << 12; | |
11653 | inst.instruction |= RdHi << 8; | |
11654 | inst.instruction |= Rn << 16; | |
11655 | inst.instruction |= Rm; | |
c19d1205 | 11656 | } |
b99bd4ef | 11657 | |
c19d1205 ZW |
11658 | static void |
11659 | do_t_mov_cmp (void) | |
11660 | { | |
fdfde340 JM |
11661 | unsigned Rn, Rm; |
11662 | ||
11663 | Rn = inst.operands[0].reg; | |
11664 | Rm = inst.operands[1].reg; | |
11665 | ||
e07e6e58 NC |
11666 | if (Rn == REG_PC) |
11667 | set_it_insn_type_last (); | |
11668 | ||
c19d1205 | 11669 | if (unified_syntax) |
b99bd4ef | 11670 | { |
c19d1205 ZW |
11671 | int r0off = (inst.instruction == T_MNEM_mov |
11672 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 11673 | unsigned long opcode; |
3d388997 PB |
11674 | bfd_boolean narrow; |
11675 | bfd_boolean low_regs; | |
11676 | ||
fdfde340 | 11677 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 11678 | opcode = inst.instruction; |
e07e6e58 | 11679 | if (in_it_block ()) |
0110f2b8 | 11680 | narrow = opcode != T_MNEM_movs; |
3d388997 | 11681 | else |
0110f2b8 | 11682 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
11683 | if (inst.size_req == 4 |
11684 | || inst.operands[1].shifted) | |
11685 | narrow = FALSE; | |
11686 | ||
efd81785 PB |
11687 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
11688 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
11689 | && !inst.operands[1].shifted | |
fdfde340 JM |
11690 | && Rn == REG_PC |
11691 | && Rm == REG_LR) | |
efd81785 PB |
11692 | { |
11693 | inst.instruction = T2_SUBS_PC_LR; | |
11694 | return; | |
11695 | } | |
11696 | ||
fdfde340 JM |
11697 | if (opcode == T_MNEM_cmp) |
11698 | { | |
11699 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
11700 | if (narrow) |
11701 | { | |
11702 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
11703 | but valid. */ | |
11704 | warn_deprecated_sp (Rm); | |
11705 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
11706 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
11707 | tools reject R15, so we do too. */ | |
11708 | constraint (Rm == REG_PC, BAD_PC); | |
11709 | } | |
11710 | else | |
11711 | reject_bad_reg (Rm); | |
fdfde340 JM |
11712 | } |
11713 | else if (opcode == T_MNEM_mov | |
11714 | || opcode == T_MNEM_movs) | |
11715 | { | |
11716 | if (inst.operands[1].isreg) | |
11717 | { | |
11718 | if (opcode == T_MNEM_movs) | |
11719 | { | |
11720 | reject_bad_reg (Rn); | |
11721 | reject_bad_reg (Rm); | |
11722 | } | |
76fa04a4 MGD |
11723 | else if (narrow) |
11724 | { | |
11725 | /* This is mov.n. */ | |
11726 | if ((Rn == REG_SP || Rn == REG_PC) | |
11727 | && (Rm == REG_SP || Rm == REG_PC)) | |
11728 | { | |
5c3696f8 | 11729 | as_tsktsk (_("Use of r%u as a source register is " |
76fa04a4 MGD |
11730 | "deprecated when r%u is the destination " |
11731 | "register."), Rm, Rn); | |
11732 | } | |
11733 | } | |
11734 | else | |
11735 | { | |
11736 | /* This is mov.w. */ | |
11737 | constraint (Rn == REG_PC, BAD_PC); | |
11738 | constraint (Rm == REG_PC, BAD_PC); | |
11739 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
11740 | } | |
fdfde340 JM |
11741 | } |
11742 | else | |
11743 | reject_bad_reg (Rn); | |
11744 | } | |
11745 | ||
c19d1205 ZW |
11746 | if (!inst.operands[1].isreg) |
11747 | { | |
0110f2b8 | 11748 | /* Immediate operand. */ |
e07e6e58 | 11749 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
11750 | narrow = 0; |
11751 | if (low_regs && narrow) | |
11752 | { | |
11753 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 11754 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
11755 | if (inst.size_req == 2) |
11756 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
11757 | else | |
11758 | inst.relax = opcode; | |
11759 | } | |
11760 | else | |
11761 | { | |
11762 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11763 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11764 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
11765 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
11766 | } | |
c19d1205 | 11767 | } |
728ca7c9 PB |
11768 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
11769 | && (inst.instruction == T_MNEM_mov | |
11770 | || inst.instruction == T_MNEM_movs)) | |
11771 | { | |
11772 | /* Register shifts are encoded as separate shift instructions. */ | |
11773 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
11774 | ||
e07e6e58 | 11775 | if (in_it_block ()) |
728ca7c9 PB |
11776 | narrow = !flags; |
11777 | else | |
11778 | narrow = flags; | |
11779 | ||
11780 | if (inst.size_req == 4) | |
11781 | narrow = FALSE; | |
11782 | ||
11783 | if (!low_regs || inst.operands[1].imm > 7) | |
11784 | narrow = FALSE; | |
11785 | ||
fdfde340 | 11786 | if (Rn != Rm) |
728ca7c9 PB |
11787 | narrow = FALSE; |
11788 | ||
11789 | switch (inst.operands[1].shift_kind) | |
11790 | { | |
11791 | case SHIFT_LSL: | |
11792 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
11793 | break; | |
11794 | case SHIFT_ASR: | |
11795 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
11796 | break; | |
11797 | case SHIFT_LSR: | |
11798 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
11799 | break; | |
11800 | case SHIFT_ROR: | |
11801 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
11802 | break; | |
11803 | default: | |
5f4273c7 | 11804 | abort (); |
728ca7c9 PB |
11805 | } |
11806 | ||
11807 | inst.instruction = opcode; | |
11808 | if (narrow) | |
11809 | { | |
fdfde340 | 11810 | inst.instruction |= Rn; |
728ca7c9 PB |
11811 | inst.instruction |= inst.operands[1].imm << 3; |
11812 | } | |
11813 | else | |
11814 | { | |
11815 | if (flags) | |
11816 | inst.instruction |= CONDS_BIT; | |
11817 | ||
fdfde340 JM |
11818 | inst.instruction |= Rn << 8; |
11819 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
11820 | inst.instruction |= inst.operands[1].imm; |
11821 | } | |
11822 | } | |
3d388997 | 11823 | else if (!narrow) |
c19d1205 | 11824 | { |
728ca7c9 PB |
11825 | /* Some mov with immediate shift have narrow variants. |
11826 | Register shifts are handled above. */ | |
11827 | if (low_regs && inst.operands[1].shifted | |
11828 | && (inst.instruction == T_MNEM_mov | |
11829 | || inst.instruction == T_MNEM_movs)) | |
11830 | { | |
e07e6e58 | 11831 | if (in_it_block ()) |
728ca7c9 PB |
11832 | narrow = (inst.instruction == T_MNEM_mov); |
11833 | else | |
11834 | narrow = (inst.instruction == T_MNEM_movs); | |
11835 | } | |
11836 | ||
11837 | if (narrow) | |
11838 | { | |
11839 | switch (inst.operands[1].shift_kind) | |
11840 | { | |
11841 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11842 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
11843 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
11844 | default: narrow = FALSE; break; | |
11845 | } | |
11846 | } | |
11847 | ||
11848 | if (narrow) | |
11849 | { | |
fdfde340 JM |
11850 | inst.instruction |= Rn; |
11851 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
11852 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11853 | } | |
11854 | else | |
11855 | { | |
11856 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11857 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
11858 | encode_thumb32_shifted_operand (1); |
11859 | } | |
c19d1205 ZW |
11860 | } |
11861 | else | |
11862 | switch (inst.instruction) | |
11863 | { | |
11864 | case T_MNEM_mov: | |
837b3435 | 11865 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
11866 | results. Don't allow this. */ |
11867 | if (low_regs) | |
11868 | { | |
11869 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
11870 | "MOV Rd, Rs with two low registers is not " | |
11871 | "permitted on this architecture"); | |
fa94de6b | 11872 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
11873 | arm_ext_v6); |
11874 | } | |
11875 | ||
c19d1205 | 11876 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
11877 | inst.instruction |= (Rn & 0x8) << 4; |
11878 | inst.instruction |= (Rn & 0x7); | |
11879 | inst.instruction |= Rm << 3; | |
c19d1205 | 11880 | break; |
b99bd4ef | 11881 | |
c19d1205 ZW |
11882 | case T_MNEM_movs: |
11883 | /* We know we have low registers at this point. | |
941a8a52 MGD |
11884 | Generate LSLS Rd, Rs, #0. */ |
11885 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
11886 | inst.instruction |= Rn; |
11887 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11888 | break; |
11889 | ||
11890 | case T_MNEM_cmp: | |
3d388997 | 11891 | if (low_regs) |
c19d1205 ZW |
11892 | { |
11893 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
11894 | inst.instruction |= Rn; |
11895 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11896 | } |
11897 | else | |
11898 | { | |
11899 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
11900 | inst.instruction |= (Rn & 0x8) << 4; |
11901 | inst.instruction |= (Rn & 0x7); | |
11902 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11903 | } |
11904 | break; | |
11905 | } | |
b99bd4ef NC |
11906 | return; |
11907 | } | |
11908 | ||
c19d1205 | 11909 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
11910 | |
11911 | /* PR 10443: Do not silently ignore shifted operands. */ | |
11912 | constraint (inst.operands[1].shifted, | |
11913 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
11914 | ||
c19d1205 | 11915 | if (inst.operands[1].isreg) |
b99bd4ef | 11916 | { |
fdfde340 | 11917 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 11918 | { |
c19d1205 ZW |
11919 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
11920 | since a MOV instruction produces unpredictable results. */ | |
11921 | if (inst.instruction == T_OPCODE_MOV_I8) | |
11922 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 11923 | else |
c19d1205 | 11924 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 11925 | |
fdfde340 JM |
11926 | inst.instruction |= Rn; |
11927 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
11928 | } |
11929 | else | |
11930 | { | |
c19d1205 ZW |
11931 | if (inst.instruction == T_OPCODE_MOV_I8) |
11932 | inst.instruction = T_OPCODE_MOV_HR; | |
11933 | else | |
11934 | inst.instruction = T_OPCODE_CMP_HR; | |
11935 | do_t_cpy (); | |
b99bd4ef NC |
11936 | } |
11937 | } | |
c19d1205 | 11938 | else |
b99bd4ef | 11939 | { |
fdfde340 | 11940 | constraint (Rn > 7, |
c19d1205 | 11941 | _("only lo regs allowed with immediate")); |
fdfde340 | 11942 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11943 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11944 | } | |
11945 | } | |
b99bd4ef | 11946 | |
c19d1205 ZW |
11947 | static void |
11948 | do_t_mov16 (void) | |
11949 | { | |
fdfde340 | 11950 | unsigned Rd; |
b6895b4f PB |
11951 | bfd_vma imm; |
11952 | bfd_boolean top; | |
11953 | ||
11954 | top = (inst.instruction & 0x00800000) != 0; | |
11955 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
11956 | { | |
11957 | constraint (top, _(":lower16: not allowed this instruction")); | |
11958 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
11959 | } | |
11960 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
11961 | { | |
11962 | constraint (!top, _(":upper16: not allowed this instruction")); | |
11963 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
11964 | } | |
11965 | ||
fdfde340 JM |
11966 | Rd = inst.operands[0].reg; |
11967 | reject_bad_reg (Rd); | |
11968 | ||
11969 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
11970 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
11971 | { | |
11972 | imm = inst.reloc.exp.X_add_number; | |
11973 | inst.instruction |= (imm & 0xf000) << 4; | |
11974 | inst.instruction |= (imm & 0x0800) << 15; | |
11975 | inst.instruction |= (imm & 0x0700) << 4; | |
11976 | inst.instruction |= (imm & 0x00ff); | |
11977 | } | |
c19d1205 | 11978 | } |
b99bd4ef | 11979 | |
c19d1205 ZW |
11980 | static void |
11981 | do_t_mvn_tst (void) | |
11982 | { | |
fdfde340 | 11983 | unsigned Rn, Rm; |
c921be7d | 11984 | |
fdfde340 JM |
11985 | Rn = inst.operands[0].reg; |
11986 | Rm = inst.operands[1].reg; | |
11987 | ||
11988 | if (inst.instruction == T_MNEM_cmp | |
11989 | || inst.instruction == T_MNEM_cmn) | |
11990 | constraint (Rn == REG_PC, BAD_PC); | |
11991 | else | |
11992 | reject_bad_reg (Rn); | |
11993 | reject_bad_reg (Rm); | |
11994 | ||
c19d1205 ZW |
11995 | if (unified_syntax) |
11996 | { | |
11997 | int r0off = (inst.instruction == T_MNEM_mvn | |
11998 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
11999 | bfd_boolean narrow; |
12000 | ||
12001 | if (inst.size_req == 4 | |
12002 | || inst.instruction > 0xffff | |
12003 | || inst.operands[1].shifted | |
fdfde340 | 12004 | || Rn > 7 || Rm > 7) |
3d388997 | 12005 | narrow = FALSE; |
fe8b4cc3 KT |
12006 | else if (inst.instruction == T_MNEM_cmn |
12007 | || inst.instruction == T_MNEM_tst) | |
3d388997 PB |
12008 | narrow = TRUE; |
12009 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12010 | narrow = !in_it_block (); |
3d388997 | 12011 | else |
e07e6e58 | 12012 | narrow = in_it_block (); |
3d388997 | 12013 | |
c19d1205 | 12014 | if (!inst.operands[1].isreg) |
b99bd4ef | 12015 | { |
c19d1205 ZW |
12016 | /* For an immediate, we always generate a 32-bit opcode; |
12017 | section relaxation will shrink it later if possible. */ | |
12018 | if (inst.instruction < 0xffff) | |
12019 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12020 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 12021 | inst.instruction |= Rn << r0off; |
c19d1205 | 12022 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 12023 | } |
c19d1205 | 12024 | else |
b99bd4ef | 12025 | { |
c19d1205 | 12026 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 12027 | if (narrow) |
b99bd4ef | 12028 | { |
c19d1205 | 12029 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12030 | inst.instruction |= Rn; |
12031 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12032 | } |
c19d1205 | 12033 | else |
b99bd4ef | 12034 | { |
c19d1205 ZW |
12035 | constraint (inst.operands[1].shifted |
12036 | && inst.operands[1].immisreg, | |
12037 | _("shift must be constant")); | |
12038 | if (inst.instruction < 0xffff) | |
12039 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 12040 | inst.instruction |= Rn << r0off; |
c19d1205 | 12041 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 12042 | } |
b99bd4ef NC |
12043 | } |
12044 | } | |
12045 | else | |
12046 | { | |
c19d1205 ZW |
12047 | constraint (inst.instruction > 0xffff |
12048 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
12049 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
12050 | _("unshifted register required")); | |
fdfde340 | 12051 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12052 | BAD_HIREG); |
b99bd4ef | 12053 | |
c19d1205 | 12054 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12055 | inst.instruction |= Rn; |
12056 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12057 | } |
b99bd4ef NC |
12058 | } |
12059 | ||
b05fe5cf | 12060 | static void |
c19d1205 | 12061 | do_t_mrs (void) |
b05fe5cf | 12062 | { |
fdfde340 | 12063 | unsigned Rd; |
037e8744 JB |
12064 | |
12065 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
12066 | return; | |
12067 | ||
90ec0d68 MGD |
12068 | Rd = inst.operands[0].reg; |
12069 | reject_bad_reg (Rd); | |
12070 | inst.instruction |= Rd << 8; | |
12071 | ||
12072 | if (inst.operands[1].isreg) | |
62b3e311 | 12073 | { |
90ec0d68 MGD |
12074 | unsigned br = inst.operands[1].reg; |
12075 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
12076 | as_bad (_("bad register for mrs")); | |
12077 | ||
12078 | inst.instruction |= br & (0xf << 16); | |
12079 | inst.instruction |= (br & 0x300) >> 4; | |
12080 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
12081 | } |
12082 | else | |
12083 | { | |
90ec0d68 | 12084 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 12085 | |
d2cd1205 | 12086 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
12087 | { |
12088 | /* PR gas/12698: The constraint is only applied for m_profile. | |
12089 | If the user has specified -march=all, we want to ignore it as | |
12090 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
12091 | bfd_boolean m_profile = |
12092 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf NC |
12093 | constraint ((flags != 0) && m_profile, _("selected processor does " |
12094 | "not support requested special purpose register")); | |
12095 | } | |
90ec0d68 | 12096 | else |
d2cd1205 JB |
12097 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
12098 | devices). */ | |
12099 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
12100 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 12101 | |
90ec0d68 MGD |
12102 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
12103 | inst.instruction |= inst.operands[1].imm & 0xff; | |
12104 | inst.instruction |= 0xf0000; | |
12105 | } | |
c19d1205 | 12106 | } |
b05fe5cf | 12107 | |
c19d1205 ZW |
12108 | static void |
12109 | do_t_msr (void) | |
12110 | { | |
62b3e311 | 12111 | int flags; |
fdfde340 | 12112 | unsigned Rn; |
62b3e311 | 12113 | |
037e8744 JB |
12114 | if (do_vfp_nsyn_msr () == SUCCESS) |
12115 | return; | |
12116 | ||
c19d1205 ZW |
12117 | constraint (!inst.operands[1].isreg, |
12118 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
12119 | |
12120 | if (inst.operands[0].isreg) | |
12121 | flags = (int)(inst.operands[0].reg); | |
12122 | else | |
12123 | flags = inst.operands[0].imm; | |
12124 | ||
d2cd1205 | 12125 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 12126 | { |
d2cd1205 JB |
12127 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
12128 | ||
1a43faaf | 12129 | /* PR gas/12698: The constraint is only applied for m_profile. |
477330fc RM |
12130 | If the user has specified -march=all, we want to ignore it as |
12131 | we are building for any CPU type, including non-m variants. */ | |
823d2571 TG |
12132 | bfd_boolean m_profile = |
12133 | !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any); | |
1a43faaf | 12134 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) |
477330fc RM |
12135 | && (bits & ~(PSR_s | PSR_f)) != 0) |
12136 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
12137 | && bits != PSR_f)) && m_profile, | |
12138 | _("selected processor does not support requested special " | |
12139 | "purpose register")); | |
62b3e311 PB |
12140 | } |
12141 | else | |
d2cd1205 JB |
12142 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
12143 | "requested special purpose register")); | |
c921be7d | 12144 | |
fdfde340 JM |
12145 | Rn = inst.operands[1].reg; |
12146 | reject_bad_reg (Rn); | |
12147 | ||
62b3e311 | 12148 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
12149 | inst.instruction |= (flags & 0xf0000) >> 8; |
12150 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 12151 | inst.instruction |= (flags & 0xff); |
fdfde340 | 12152 | inst.instruction |= Rn << 16; |
c19d1205 | 12153 | } |
b05fe5cf | 12154 | |
c19d1205 ZW |
12155 | static void |
12156 | do_t_mul (void) | |
12157 | { | |
17828f45 | 12158 | bfd_boolean narrow; |
fdfde340 | 12159 | unsigned Rd, Rn, Rm; |
17828f45 | 12160 | |
c19d1205 ZW |
12161 | if (!inst.operands[2].present) |
12162 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 12163 | |
fdfde340 JM |
12164 | Rd = inst.operands[0].reg; |
12165 | Rn = inst.operands[1].reg; | |
12166 | Rm = inst.operands[2].reg; | |
12167 | ||
17828f45 | 12168 | if (unified_syntax) |
b05fe5cf | 12169 | { |
17828f45 | 12170 | if (inst.size_req == 4 |
fdfde340 JM |
12171 | || (Rd != Rn |
12172 | && Rd != Rm) | |
12173 | || Rn > 7 | |
12174 | || Rm > 7) | |
17828f45 JM |
12175 | narrow = FALSE; |
12176 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 12177 | narrow = !in_it_block (); |
17828f45 | 12178 | else |
e07e6e58 | 12179 | narrow = in_it_block (); |
b05fe5cf | 12180 | } |
c19d1205 | 12181 | else |
b05fe5cf | 12182 | { |
17828f45 | 12183 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 12184 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 12185 | BAD_HIREG); |
17828f45 JM |
12186 | narrow = TRUE; |
12187 | } | |
b05fe5cf | 12188 | |
17828f45 JM |
12189 | if (narrow) |
12190 | { | |
12191 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 12192 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 12193 | inst.instruction |= Rd; |
b05fe5cf | 12194 | |
fdfde340 JM |
12195 | if (Rd == Rn) |
12196 | inst.instruction |= Rm << 3; | |
12197 | else if (Rd == Rm) | |
12198 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
12199 | else |
12200 | constraint (1, _("dest must overlap one source register")); | |
12201 | } | |
17828f45 JM |
12202 | else |
12203 | { | |
e07e6e58 NC |
12204 | constraint (inst.instruction != T_MNEM_mul, |
12205 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
12206 | /* 32-bit MUL. */ |
12207 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12208 | inst.instruction |= Rd << 8; |
12209 | inst.instruction |= Rn << 16; | |
12210 | inst.instruction |= Rm << 0; | |
12211 | ||
12212 | reject_bad_reg (Rd); | |
12213 | reject_bad_reg (Rn); | |
12214 | reject_bad_reg (Rm); | |
17828f45 | 12215 | } |
c19d1205 | 12216 | } |
b05fe5cf | 12217 | |
c19d1205 ZW |
12218 | static void |
12219 | do_t_mull (void) | |
12220 | { | |
fdfde340 | 12221 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 12222 | |
fdfde340 JM |
12223 | RdLo = inst.operands[0].reg; |
12224 | RdHi = inst.operands[1].reg; | |
12225 | Rn = inst.operands[2].reg; | |
12226 | Rm = inst.operands[3].reg; | |
12227 | ||
12228 | reject_bad_reg (RdLo); | |
12229 | reject_bad_reg (RdHi); | |
12230 | reject_bad_reg (Rn); | |
12231 | reject_bad_reg (Rm); | |
12232 | ||
12233 | inst.instruction |= RdLo << 12; | |
12234 | inst.instruction |= RdHi << 8; | |
12235 | inst.instruction |= Rn << 16; | |
12236 | inst.instruction |= Rm; | |
12237 | ||
12238 | if (RdLo == RdHi) | |
c19d1205 ZW |
12239 | as_tsktsk (_("rdhi and rdlo must be different")); |
12240 | } | |
b05fe5cf | 12241 | |
c19d1205 ZW |
12242 | static void |
12243 | do_t_nop (void) | |
12244 | { | |
e07e6e58 NC |
12245 | set_it_insn_type (NEUTRAL_IT_INSN); |
12246 | ||
c19d1205 ZW |
12247 | if (unified_syntax) |
12248 | { | |
12249 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 12250 | { |
c19d1205 ZW |
12251 | inst.instruction = THUMB_OP32 (inst.instruction); |
12252 | inst.instruction |= inst.operands[0].imm; | |
12253 | } | |
12254 | else | |
12255 | { | |
bc2d1808 NC |
12256 | /* PR9722: Check for Thumb2 availability before |
12257 | generating a thumb2 nop instruction. */ | |
afa62d5e | 12258 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
12259 | { |
12260 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12261 | inst.instruction |= inst.operands[0].imm << 4; | |
12262 | } | |
12263 | else | |
12264 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
12265 | } |
12266 | } | |
12267 | else | |
12268 | { | |
12269 | constraint (inst.operands[0].present, | |
12270 | _("Thumb does not support NOP with hints")); | |
12271 | inst.instruction = 0x46c0; | |
12272 | } | |
12273 | } | |
b05fe5cf | 12274 | |
c19d1205 ZW |
12275 | static void |
12276 | do_t_neg (void) | |
12277 | { | |
12278 | if (unified_syntax) | |
12279 | { | |
3d388997 PB |
12280 | bfd_boolean narrow; |
12281 | ||
12282 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12283 | narrow = !in_it_block (); |
3d388997 | 12284 | else |
e07e6e58 | 12285 | narrow = in_it_block (); |
3d388997 PB |
12286 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12287 | narrow = FALSE; | |
12288 | if (inst.size_req == 4) | |
12289 | narrow = FALSE; | |
12290 | ||
12291 | if (!narrow) | |
c19d1205 ZW |
12292 | { |
12293 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12294 | inst.instruction |= inst.operands[0].reg << 8; | |
12295 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
12296 | } |
12297 | else | |
12298 | { | |
c19d1205 ZW |
12299 | inst.instruction = THUMB_OP16 (inst.instruction); |
12300 | inst.instruction |= inst.operands[0].reg; | |
12301 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
12302 | } |
12303 | } | |
12304 | else | |
12305 | { | |
c19d1205 ZW |
12306 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
12307 | BAD_HIREG); | |
12308 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
12309 | ||
12310 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12311 | inst.instruction |= inst.operands[0].reg; | |
12312 | inst.instruction |= inst.operands[1].reg << 3; | |
12313 | } | |
12314 | } | |
12315 | ||
1c444d06 JM |
12316 | static void |
12317 | do_t_orn (void) | |
12318 | { | |
12319 | unsigned Rd, Rn; | |
12320 | ||
12321 | Rd = inst.operands[0].reg; | |
12322 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
12323 | ||
fdfde340 JM |
12324 | reject_bad_reg (Rd); |
12325 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
12326 | reject_bad_reg (Rn); | |
12327 | ||
1c444d06 JM |
12328 | inst.instruction |= Rd << 8; |
12329 | inst.instruction |= Rn << 16; | |
12330 | ||
12331 | if (!inst.operands[2].isreg) | |
12332 | { | |
12333 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12334 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12335 | } | |
12336 | else | |
12337 | { | |
12338 | unsigned Rm; | |
12339 | ||
12340 | Rm = inst.operands[2].reg; | |
fdfde340 | 12341 | reject_bad_reg (Rm); |
1c444d06 JM |
12342 | |
12343 | constraint (inst.operands[2].shifted | |
12344 | && inst.operands[2].immisreg, | |
12345 | _("shift must be constant")); | |
12346 | encode_thumb32_shifted_operand (2); | |
12347 | } | |
12348 | } | |
12349 | ||
c19d1205 ZW |
12350 | static void |
12351 | do_t_pkhbt (void) | |
12352 | { | |
fdfde340 JM |
12353 | unsigned Rd, Rn, Rm; |
12354 | ||
12355 | Rd = inst.operands[0].reg; | |
12356 | Rn = inst.operands[1].reg; | |
12357 | Rm = inst.operands[2].reg; | |
12358 | ||
12359 | reject_bad_reg (Rd); | |
12360 | reject_bad_reg (Rn); | |
12361 | reject_bad_reg (Rm); | |
12362 | ||
12363 | inst.instruction |= Rd << 8; | |
12364 | inst.instruction |= Rn << 16; | |
12365 | inst.instruction |= Rm; | |
c19d1205 ZW |
12366 | if (inst.operands[3].present) |
12367 | { | |
12368 | unsigned int val = inst.reloc.exp.X_add_number; | |
12369 | constraint (inst.reloc.exp.X_op != O_constant, | |
12370 | _("expression too complex")); | |
12371 | inst.instruction |= (val & 0x1c) << 10; | |
12372 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 12373 | } |
c19d1205 | 12374 | } |
b05fe5cf | 12375 | |
c19d1205 ZW |
12376 | static void |
12377 | do_t_pkhtb (void) | |
12378 | { | |
12379 | if (!inst.operands[3].present) | |
1ef52f49 NC |
12380 | { |
12381 | unsigned Rtmp; | |
12382 | ||
12383 | inst.instruction &= ~0x00000020; | |
12384 | ||
12385 | /* PR 10168. Swap the Rm and Rn registers. */ | |
12386 | Rtmp = inst.operands[1].reg; | |
12387 | inst.operands[1].reg = inst.operands[2].reg; | |
12388 | inst.operands[2].reg = Rtmp; | |
12389 | } | |
c19d1205 | 12390 | do_t_pkhbt (); |
b05fe5cf ZW |
12391 | } |
12392 | ||
c19d1205 ZW |
12393 | static void |
12394 | do_t_pld (void) | |
12395 | { | |
fdfde340 JM |
12396 | if (inst.operands[0].immisreg) |
12397 | reject_bad_reg (inst.operands[0].imm); | |
12398 | ||
c19d1205 ZW |
12399 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
12400 | } | |
b05fe5cf | 12401 | |
c19d1205 ZW |
12402 | static void |
12403 | do_t_push_pop (void) | |
b99bd4ef | 12404 | { |
e9f89963 | 12405 | unsigned mask; |
5f4273c7 | 12406 | |
c19d1205 ZW |
12407 | constraint (inst.operands[0].writeback, |
12408 | _("push/pop do not support {reglist}^")); | |
12409 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
12410 | _("expression too complex")); | |
b99bd4ef | 12411 | |
e9f89963 | 12412 | mask = inst.operands[0].imm; |
d3bfe16e | 12413 | if (inst.size_req != 4 && (mask & ~0xff) == 0) |
3c707909 | 12414 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
d3bfe16e JB |
12415 | else if (inst.size_req != 4 |
12416 | && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push | |
12417 | ? REG_LR : REG_PC))) | |
b99bd4ef | 12418 | { |
c19d1205 ZW |
12419 | inst.instruction = THUMB_OP16 (inst.instruction); |
12420 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 12421 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
12422 | } |
12423 | else if (unified_syntax) | |
12424 | { | |
3c707909 | 12425 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 12426 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
12427 | } |
12428 | else | |
12429 | { | |
12430 | inst.error = _("invalid register list to push/pop instruction"); | |
12431 | return; | |
12432 | } | |
c19d1205 | 12433 | } |
b99bd4ef | 12434 | |
c19d1205 ZW |
12435 | static void |
12436 | do_t_rbit (void) | |
12437 | { | |
fdfde340 JM |
12438 | unsigned Rd, Rm; |
12439 | ||
12440 | Rd = inst.operands[0].reg; | |
12441 | Rm = inst.operands[1].reg; | |
12442 | ||
12443 | reject_bad_reg (Rd); | |
12444 | reject_bad_reg (Rm); | |
12445 | ||
12446 | inst.instruction |= Rd << 8; | |
12447 | inst.instruction |= Rm << 16; | |
12448 | inst.instruction |= Rm; | |
c19d1205 | 12449 | } |
b99bd4ef | 12450 | |
c19d1205 ZW |
12451 | static void |
12452 | do_t_rev (void) | |
12453 | { | |
fdfde340 JM |
12454 | unsigned Rd, Rm; |
12455 | ||
12456 | Rd = inst.operands[0].reg; | |
12457 | Rm = inst.operands[1].reg; | |
12458 | ||
12459 | reject_bad_reg (Rd); | |
12460 | reject_bad_reg (Rm); | |
12461 | ||
12462 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
12463 | && inst.size_req != 4) |
12464 | { | |
12465 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
12466 | inst.instruction |= Rd; |
12467 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
12468 | } |
12469 | else if (unified_syntax) | |
12470 | { | |
12471 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12472 | inst.instruction |= Rd << 8; |
12473 | inst.instruction |= Rm << 16; | |
12474 | inst.instruction |= Rm; | |
c19d1205 ZW |
12475 | } |
12476 | else | |
12477 | inst.error = BAD_HIREG; | |
12478 | } | |
b99bd4ef | 12479 | |
1c444d06 JM |
12480 | static void |
12481 | do_t_rrx (void) | |
12482 | { | |
12483 | unsigned Rd, Rm; | |
12484 | ||
12485 | Rd = inst.operands[0].reg; | |
12486 | Rm = inst.operands[1].reg; | |
12487 | ||
fdfde340 JM |
12488 | reject_bad_reg (Rd); |
12489 | reject_bad_reg (Rm); | |
c921be7d | 12490 | |
1c444d06 JM |
12491 | inst.instruction |= Rd << 8; |
12492 | inst.instruction |= Rm; | |
12493 | } | |
12494 | ||
c19d1205 ZW |
12495 | static void |
12496 | do_t_rsb (void) | |
12497 | { | |
fdfde340 | 12498 | unsigned Rd, Rs; |
b99bd4ef | 12499 | |
c19d1205 ZW |
12500 | Rd = inst.operands[0].reg; |
12501 | Rs = (inst.operands[1].present | |
12502 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
12503 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 12504 | |
fdfde340 JM |
12505 | reject_bad_reg (Rd); |
12506 | reject_bad_reg (Rs); | |
12507 | if (inst.operands[2].isreg) | |
12508 | reject_bad_reg (inst.operands[2].reg); | |
12509 | ||
c19d1205 ZW |
12510 | inst.instruction |= Rd << 8; |
12511 | inst.instruction |= Rs << 16; | |
12512 | if (!inst.operands[2].isreg) | |
12513 | { | |
026d3abb PB |
12514 | bfd_boolean narrow; |
12515 | ||
12516 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 12517 | narrow = !in_it_block (); |
026d3abb | 12518 | else |
e07e6e58 | 12519 | narrow = in_it_block (); |
026d3abb PB |
12520 | |
12521 | if (Rd > 7 || Rs > 7) | |
12522 | narrow = FALSE; | |
12523 | ||
12524 | if (inst.size_req == 4 || !unified_syntax) | |
12525 | narrow = FALSE; | |
12526 | ||
12527 | if (inst.reloc.exp.X_op != O_constant | |
12528 | || inst.reloc.exp.X_add_number != 0) | |
12529 | narrow = FALSE; | |
12530 | ||
12531 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
477330fc | 12532 | relaxation, but it doesn't seem worth the hassle. */ |
026d3abb PB |
12533 | if (narrow) |
12534 | { | |
12535 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12536 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
12537 | inst.instruction |= Rs << 3; | |
12538 | inst.instruction |= Rd; | |
12539 | } | |
12540 | else | |
12541 | { | |
12542 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
12543 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
12544 | } | |
c19d1205 ZW |
12545 | } |
12546 | else | |
12547 | encode_thumb32_shifted_operand (2); | |
12548 | } | |
b99bd4ef | 12549 | |
c19d1205 ZW |
12550 | static void |
12551 | do_t_setend (void) | |
12552 | { | |
12e37cbc MGD |
12553 | if (warn_on_deprecated |
12554 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
5c3696f8 | 12555 | as_tsktsk (_("setend use is deprecated for ARMv8")); |
12e37cbc | 12556 | |
e07e6e58 | 12557 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
12558 | if (inst.operands[0].imm) |
12559 | inst.instruction |= 0x8; | |
12560 | } | |
b99bd4ef | 12561 | |
c19d1205 ZW |
12562 | static void |
12563 | do_t_shift (void) | |
12564 | { | |
12565 | if (!inst.operands[1].present) | |
12566 | inst.operands[1].reg = inst.operands[0].reg; | |
12567 | ||
12568 | if (unified_syntax) | |
12569 | { | |
3d388997 PB |
12570 | bfd_boolean narrow; |
12571 | int shift_kind; | |
12572 | ||
12573 | switch (inst.instruction) | |
12574 | { | |
12575 | case T_MNEM_asr: | |
12576 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
12577 | case T_MNEM_lsl: | |
12578 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
12579 | case T_MNEM_lsr: | |
12580 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
12581 | case T_MNEM_ror: | |
12582 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
12583 | default: abort (); | |
12584 | } | |
12585 | ||
12586 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 12587 | narrow = !in_it_block (); |
3d388997 | 12588 | else |
e07e6e58 | 12589 | narrow = in_it_block (); |
3d388997 PB |
12590 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
12591 | narrow = FALSE; | |
12592 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
12593 | narrow = FALSE; | |
12594 | if (inst.operands[2].isreg | |
12595 | && (inst.operands[1].reg != inst.operands[0].reg | |
12596 | || inst.operands[2].reg > 7)) | |
12597 | narrow = FALSE; | |
12598 | if (inst.size_req == 4) | |
12599 | narrow = FALSE; | |
12600 | ||
fdfde340 JM |
12601 | reject_bad_reg (inst.operands[0].reg); |
12602 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 12603 | |
3d388997 | 12604 | if (!narrow) |
c19d1205 ZW |
12605 | { |
12606 | if (inst.operands[2].isreg) | |
b99bd4ef | 12607 | { |
fdfde340 | 12608 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
12609 | inst.instruction = THUMB_OP32 (inst.instruction); |
12610 | inst.instruction |= inst.operands[0].reg << 8; | |
12611 | inst.instruction |= inst.operands[1].reg << 16; | |
12612 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
12613 | |
12614 | /* PR 12854: Error on extraneous shifts. */ | |
12615 | constraint (inst.operands[2].shifted, | |
12616 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12617 | } |
12618 | else | |
12619 | { | |
12620 | inst.operands[1].shifted = 1; | |
3d388997 | 12621 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
12622 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
12623 | ? T_MNEM_movs : T_MNEM_mov); | |
12624 | inst.instruction |= inst.operands[0].reg << 8; | |
12625 | encode_thumb32_shifted_operand (1); | |
12626 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
12627 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
12628 | } |
12629 | } | |
12630 | else | |
12631 | { | |
c19d1205 | 12632 | if (inst.operands[2].isreg) |
b99bd4ef | 12633 | { |
3d388997 | 12634 | switch (shift_kind) |
b99bd4ef | 12635 | { |
3d388997 PB |
12636 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
12637 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
12638 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
12639 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 12640 | default: abort (); |
b99bd4ef | 12641 | } |
5f4273c7 | 12642 | |
c19d1205 ZW |
12643 | inst.instruction |= inst.operands[0].reg; |
12644 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12645 | |
12646 | /* PR 12854: Error on extraneous shifts. */ | |
12647 | constraint (inst.operands[2].shifted, | |
12648 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
12649 | } |
12650 | else | |
12651 | { | |
3d388997 | 12652 | switch (shift_kind) |
b99bd4ef | 12653 | { |
3d388997 PB |
12654 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
12655 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
12656 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 12657 | default: abort (); |
b99bd4ef | 12658 | } |
c19d1205 ZW |
12659 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
12660 | inst.instruction |= inst.operands[0].reg; | |
12661 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12662 | } |
12663 | } | |
c19d1205 ZW |
12664 | } |
12665 | else | |
12666 | { | |
12667 | constraint (inst.operands[0].reg > 7 | |
12668 | || inst.operands[1].reg > 7, BAD_HIREG); | |
12669 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 12670 | |
c19d1205 ZW |
12671 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
12672 | { | |
12673 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
12674 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
12675 | _("source1 and dest must be same register")); | |
b99bd4ef | 12676 | |
c19d1205 ZW |
12677 | switch (inst.instruction) |
12678 | { | |
12679 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
12680 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
12681 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
12682 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
12683 | default: abort (); | |
12684 | } | |
5f4273c7 | 12685 | |
c19d1205 ZW |
12686 | inst.instruction |= inst.operands[0].reg; |
12687 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
12688 | |
12689 | /* PR 12854: Error on extraneous shifts. */ | |
12690 | constraint (inst.operands[2].shifted, | |
12691 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
12692 | } |
12693 | else | |
b99bd4ef | 12694 | { |
c19d1205 ZW |
12695 | switch (inst.instruction) |
12696 | { | |
12697 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
12698 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
12699 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
12700 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
12701 | default: abort (); | |
12702 | } | |
12703 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
12704 | inst.instruction |= inst.operands[0].reg; | |
12705 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
12706 | } |
12707 | } | |
b99bd4ef NC |
12708 | } |
12709 | ||
12710 | static void | |
c19d1205 | 12711 | do_t_simd (void) |
b99bd4ef | 12712 | { |
fdfde340 JM |
12713 | unsigned Rd, Rn, Rm; |
12714 | ||
12715 | Rd = inst.operands[0].reg; | |
12716 | Rn = inst.operands[1].reg; | |
12717 | Rm = inst.operands[2].reg; | |
12718 | ||
12719 | reject_bad_reg (Rd); | |
12720 | reject_bad_reg (Rn); | |
12721 | reject_bad_reg (Rm); | |
12722 | ||
12723 | inst.instruction |= Rd << 8; | |
12724 | inst.instruction |= Rn << 16; | |
12725 | inst.instruction |= Rm; | |
c19d1205 | 12726 | } |
b99bd4ef | 12727 | |
03ee1b7f NC |
12728 | static void |
12729 | do_t_simd2 (void) | |
12730 | { | |
12731 | unsigned Rd, Rn, Rm; | |
12732 | ||
12733 | Rd = inst.operands[0].reg; | |
12734 | Rm = inst.operands[1].reg; | |
12735 | Rn = inst.operands[2].reg; | |
12736 | ||
12737 | reject_bad_reg (Rd); | |
12738 | reject_bad_reg (Rn); | |
12739 | reject_bad_reg (Rm); | |
12740 | ||
12741 | inst.instruction |= Rd << 8; | |
12742 | inst.instruction |= Rn << 16; | |
12743 | inst.instruction |= Rm; | |
12744 | } | |
12745 | ||
c19d1205 | 12746 | static void |
3eb17e6b | 12747 | do_t_smc (void) |
c19d1205 ZW |
12748 | { |
12749 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
12750 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
12751 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
12752 | constraint (inst.reloc.exp.X_op != O_constant, |
12753 | _("expression too complex")); | |
12754 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12755 | inst.instruction |= (value & 0xf000) >> 12; | |
12756 | inst.instruction |= (value & 0x0ff0); | |
12757 | inst.instruction |= (value & 0x000f) << 16; | |
24382199 NC |
12758 | /* PR gas/15623: SMC instructions must be last in an IT block. */ |
12759 | set_it_insn_type_last (); | |
c19d1205 | 12760 | } |
b99bd4ef | 12761 | |
90ec0d68 MGD |
12762 | static void |
12763 | do_t_hvc (void) | |
12764 | { | |
12765 | unsigned int value = inst.reloc.exp.X_add_number; | |
12766 | ||
12767 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12768 | inst.instruction |= (value & 0x0fff); | |
12769 | inst.instruction |= (value & 0xf000) << 4; | |
12770 | } | |
12771 | ||
c19d1205 | 12772 | static void |
3a21c15a | 12773 | do_t_ssat_usat (int bias) |
c19d1205 | 12774 | { |
fdfde340 JM |
12775 | unsigned Rd, Rn; |
12776 | ||
12777 | Rd = inst.operands[0].reg; | |
12778 | Rn = inst.operands[2].reg; | |
12779 | ||
12780 | reject_bad_reg (Rd); | |
12781 | reject_bad_reg (Rn); | |
12782 | ||
12783 | inst.instruction |= Rd << 8; | |
3a21c15a | 12784 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 12785 | inst.instruction |= Rn << 16; |
b99bd4ef | 12786 | |
c19d1205 | 12787 | if (inst.operands[3].present) |
b99bd4ef | 12788 | { |
3a21c15a NC |
12789 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
12790 | ||
12791 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12792 | ||
c19d1205 ZW |
12793 | constraint (inst.reloc.exp.X_op != O_constant, |
12794 | _("expression too complex")); | |
b99bd4ef | 12795 | |
3a21c15a | 12796 | if (shift_amount != 0) |
6189168b | 12797 | { |
3a21c15a NC |
12798 | constraint (shift_amount > 31, |
12799 | _("shift expression is too large")); | |
12800 | ||
c19d1205 | 12801 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
12802 | inst.instruction |= 0x00200000; /* sh bit. */ |
12803 | ||
12804 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
12805 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
12806 | } |
12807 | } | |
b99bd4ef | 12808 | } |
c921be7d | 12809 | |
3a21c15a NC |
12810 | static void |
12811 | do_t_ssat (void) | |
12812 | { | |
12813 | do_t_ssat_usat (1); | |
12814 | } | |
b99bd4ef | 12815 | |
0dd132b6 | 12816 | static void |
c19d1205 | 12817 | do_t_ssat16 (void) |
0dd132b6 | 12818 | { |
fdfde340 JM |
12819 | unsigned Rd, Rn; |
12820 | ||
12821 | Rd = inst.operands[0].reg; | |
12822 | Rn = inst.operands[2].reg; | |
12823 | ||
12824 | reject_bad_reg (Rd); | |
12825 | reject_bad_reg (Rn); | |
12826 | ||
12827 | inst.instruction |= Rd << 8; | |
c19d1205 | 12828 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 12829 | inst.instruction |= Rn << 16; |
c19d1205 | 12830 | } |
0dd132b6 | 12831 | |
c19d1205 ZW |
12832 | static void |
12833 | do_t_strex (void) | |
12834 | { | |
12835 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
12836 | || inst.operands[2].postind || inst.operands[2].writeback | |
12837 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
12838 | || inst.operands[2].negative, | |
01cfc07f | 12839 | BAD_ADDR_MODE); |
0dd132b6 | 12840 | |
5be8be5d DG |
12841 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
12842 | ||
c19d1205 ZW |
12843 | inst.instruction |= inst.operands[0].reg << 8; |
12844 | inst.instruction |= inst.operands[1].reg << 12; | |
12845 | inst.instruction |= inst.operands[2].reg << 16; | |
12846 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
12847 | } |
12848 | ||
b99bd4ef | 12849 | static void |
c19d1205 | 12850 | do_t_strexd (void) |
b99bd4ef | 12851 | { |
c19d1205 ZW |
12852 | if (!inst.operands[2].present) |
12853 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 12854 | |
c19d1205 ZW |
12855 | constraint (inst.operands[0].reg == inst.operands[1].reg |
12856 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 12857 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 12858 | BAD_OVERLAP); |
b99bd4ef | 12859 | |
c19d1205 ZW |
12860 | inst.instruction |= inst.operands[0].reg; |
12861 | inst.instruction |= inst.operands[1].reg << 12; | |
12862 | inst.instruction |= inst.operands[2].reg << 8; | |
12863 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
12864 | } |
12865 | ||
12866 | static void | |
c19d1205 | 12867 | do_t_sxtah (void) |
b99bd4ef | 12868 | { |
fdfde340 JM |
12869 | unsigned Rd, Rn, Rm; |
12870 | ||
12871 | Rd = inst.operands[0].reg; | |
12872 | Rn = inst.operands[1].reg; | |
12873 | Rm = inst.operands[2].reg; | |
12874 | ||
12875 | reject_bad_reg (Rd); | |
12876 | reject_bad_reg (Rn); | |
12877 | reject_bad_reg (Rm); | |
12878 | ||
12879 | inst.instruction |= Rd << 8; | |
12880 | inst.instruction |= Rn << 16; | |
12881 | inst.instruction |= Rm; | |
c19d1205 ZW |
12882 | inst.instruction |= inst.operands[3].imm << 4; |
12883 | } | |
b99bd4ef | 12884 | |
c19d1205 ZW |
12885 | static void |
12886 | do_t_sxth (void) | |
12887 | { | |
fdfde340 JM |
12888 | unsigned Rd, Rm; |
12889 | ||
12890 | Rd = inst.operands[0].reg; | |
12891 | Rm = inst.operands[1].reg; | |
12892 | ||
12893 | reject_bad_reg (Rd); | |
12894 | reject_bad_reg (Rm); | |
c921be7d NC |
12895 | |
12896 | if (inst.instruction <= 0xffff | |
12897 | && inst.size_req != 4 | |
fdfde340 | 12898 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 12899 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 12900 | { |
c19d1205 | 12901 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12902 | inst.instruction |= Rd; |
12903 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12904 | } |
c19d1205 | 12905 | else if (unified_syntax) |
b99bd4ef | 12906 | { |
c19d1205 ZW |
12907 | if (inst.instruction <= 0xffff) |
12908 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12909 | inst.instruction |= Rd << 8; |
12910 | inst.instruction |= Rm; | |
c19d1205 | 12911 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 12912 | } |
c19d1205 | 12913 | else |
b99bd4ef | 12914 | { |
c19d1205 ZW |
12915 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
12916 | _("Thumb encoding does not support rotation")); | |
12917 | constraint (1, BAD_HIREG); | |
b99bd4ef | 12918 | } |
c19d1205 | 12919 | } |
b99bd4ef | 12920 | |
c19d1205 ZW |
12921 | static void |
12922 | do_t_swi (void) | |
12923 | { | |
b2a5fbdc MGD |
12924 | /* We have to do the following check manually as ARM_EXT_OS only applies |
12925 | to ARM_EXT_V6M. */ | |
12926 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
12927 | { | |
ac7f631b NC |
12928 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
12929 | /* This only applies to the v6m howver, not later architectures. */ | |
12930 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
12931 | as_bad (_("SVC is not permitted on this architecture")); |
12932 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
12933 | } | |
12934 | ||
c19d1205 ZW |
12935 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
12936 | } | |
b99bd4ef | 12937 | |
92e90b6e PB |
12938 | static void |
12939 | do_t_tb (void) | |
12940 | { | |
fdfde340 | 12941 | unsigned Rn, Rm; |
92e90b6e PB |
12942 | int half; |
12943 | ||
12944 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 12945 | set_it_insn_type_last (); |
dfa9f0d5 PB |
12946 | constraint (inst.operands[0].immisreg, |
12947 | _("instruction requires register index")); | |
fdfde340 JM |
12948 | |
12949 | Rn = inst.operands[0].reg; | |
12950 | Rm = inst.operands[0].imm; | |
c921be7d | 12951 | |
fdfde340 JM |
12952 | constraint (Rn == REG_SP, BAD_SP); |
12953 | reject_bad_reg (Rm); | |
12954 | ||
92e90b6e PB |
12955 | constraint (!half && inst.operands[0].shifted, |
12956 | _("instruction does not allow shifted index")); | |
fdfde340 | 12957 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
12958 | } |
12959 | ||
74db7efb NC |
12960 | static void |
12961 | do_t_udf (void) | |
12962 | { | |
12963 | if (!inst.operands[0].present) | |
12964 | inst.operands[0].imm = 0; | |
12965 | ||
12966 | if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4) | |
12967 | { | |
12968 | constraint (inst.size_req == 2, | |
12969 | _("immediate value out of range")); | |
12970 | inst.instruction = THUMB_OP32 (inst.instruction); | |
12971 | inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4; | |
12972 | inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0; | |
12973 | } | |
12974 | else | |
12975 | { | |
12976 | inst.instruction = THUMB_OP16 (inst.instruction); | |
12977 | inst.instruction |= inst.operands[0].imm; | |
12978 | } | |
12979 | ||
12980 | set_it_insn_type (NEUTRAL_IT_INSN); | |
12981 | } | |
12982 | ||
12983 | ||
c19d1205 ZW |
12984 | static void |
12985 | do_t_usat (void) | |
12986 | { | |
3a21c15a | 12987 | do_t_ssat_usat (0); |
b99bd4ef NC |
12988 | } |
12989 | ||
12990 | static void | |
c19d1205 | 12991 | do_t_usat16 (void) |
b99bd4ef | 12992 | { |
fdfde340 JM |
12993 | unsigned Rd, Rn; |
12994 | ||
12995 | Rd = inst.operands[0].reg; | |
12996 | Rn = inst.operands[2].reg; | |
12997 | ||
12998 | reject_bad_reg (Rd); | |
12999 | reject_bad_reg (Rn); | |
13000 | ||
13001 | inst.instruction |= Rd << 8; | |
c19d1205 | 13002 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 13003 | inst.instruction |= Rn << 16; |
b99bd4ef | 13004 | } |
c19d1205 | 13005 | |
5287ad62 | 13006 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 13007 | |
5287ad62 | 13008 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 13009 | |
5287ad62 JB |
13010 | /* An "invalid" code for the following tables. */ |
13011 | #define N_INV -1u | |
13012 | ||
13013 | struct neon_tab_entry | |
b99bd4ef | 13014 | { |
5287ad62 JB |
13015 | unsigned integer; |
13016 | unsigned float_or_poly; | |
13017 | unsigned scalar_or_imm; | |
13018 | }; | |
5f4273c7 | 13019 | |
5287ad62 JB |
13020 | /* Map overloaded Neon opcodes to their respective encodings. */ |
13021 | #define NEON_ENC_TAB \ | |
13022 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
13023 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
13024 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
13025 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
13026 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
13027 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
13028 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
13029 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
13030 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
13031 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
13032 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
13033 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 13034 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
13035 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
13036 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
13037 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
13038 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
13039 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
13040 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
13041 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
13042 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
13043 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
13044 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
13045 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
13046 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
13047 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
13048 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
13049 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
d6b4b13e MW |
13050 | X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \ |
13051 | X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \ | |
5287ad62 JB |
13052 | X(vshl, 0x0000400, N_INV, 0x0800510), \ |
13053 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
13054 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
13055 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
13056 | X(veor, 0x1000110, N_INV, N_INV), \ | |
13057 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
13058 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
13059 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
13060 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
13061 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
13062 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
13063 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
13064 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
13065 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
13066 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
13067 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
13068 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
13069 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
13070 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
13071 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
13072 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
13073 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
13074 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
13075 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
13076 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
13077 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
13078 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
13079 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
13080 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
13081 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
13082 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
33399f07 MGD |
13083 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ |
13084 | X(vseleq, 0xe000a00, N_INV, N_INV), \ | |
13085 | X(vselvs, 0xe100a00, N_INV, N_INV), \ | |
13086 | X(vselge, 0xe200a00, N_INV, N_INV), \ | |
73924fbc MGD |
13087 | X(vselgt, 0xe300a00, N_INV, N_INV), \ |
13088 | X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \ | |
7e8e6784 | 13089 | X(vminnm, 0xe800a40, 0x3200f10, N_INV), \ |
30bdf752 MGD |
13090 | X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \ |
13091 | X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \ | |
91ff7894 | 13092 | X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \ |
48adcd8e | 13093 | X(aes, 0x3b00300, N_INV, N_INV), \ |
3c9017d2 MGD |
13094 | X(sha3op, 0x2000c00, N_INV, N_INV), \ |
13095 | X(sha1h, 0x3b902c0, N_INV, N_INV), \ | |
13096 | X(sha2op, 0x3ba0380, N_INV, N_INV) | |
5287ad62 JB |
13097 | |
13098 | enum neon_opc | |
13099 | { | |
13100 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
13101 | NEON_ENC_TAB | |
13102 | #undef X | |
13103 | }; | |
b99bd4ef | 13104 | |
5287ad62 JB |
13105 | static const struct neon_tab_entry neon_enc_tab[] = |
13106 | { | |
13107 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
13108 | NEON_ENC_TAB | |
13109 | #undef X | |
13110 | }; | |
b99bd4ef | 13111 | |
88714cb8 DG |
13112 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
13113 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13114 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13115 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13116 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13117 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13118 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13119 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
13120 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
13121 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
13122 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 13123 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 13124 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 13125 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
33399f07 MGD |
13126 | #define NEON_ENC_FPV8_(X) \ |
13127 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) | |
5287ad62 | 13128 | |
88714cb8 DG |
13129 | #define NEON_ENCODE(type, inst) \ |
13130 | do \ | |
13131 | { \ | |
13132 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
13133 | inst.is_neon = 1; \ | |
13134 | } \ | |
13135 | while (0) | |
13136 | ||
13137 | #define check_neon_suffixes \ | |
13138 | do \ | |
13139 | { \ | |
13140 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
13141 | { \ | |
13142 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
13143 | return; \ | |
13144 | } \ | |
13145 | } \ | |
13146 | while (0) | |
13147 | ||
037e8744 JB |
13148 | /* Define shapes for instruction operands. The following mnemonic characters |
13149 | are used in this table: | |
5287ad62 | 13150 | |
037e8744 | 13151 | F - VFP S<n> register |
5287ad62 JB |
13152 | D - Neon D<n> register |
13153 | Q - Neon Q<n> register | |
13154 | I - Immediate | |
13155 | S - Scalar | |
13156 | R - ARM register | |
13157 | L - D<n> register list | |
5f4273c7 | 13158 | |
037e8744 JB |
13159 | This table is used to generate various data: |
13160 | - enumerations of the form NS_DDR to be used as arguments to | |
13161 | neon_select_shape. | |
13162 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 13163 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 13164 | |
037e8744 JB |
13165 | #define NEON_SHAPE_DEF \ |
13166 | X(3, (D, D, D), DOUBLE), \ | |
13167 | X(3, (Q, Q, Q), QUAD), \ | |
13168 | X(3, (D, D, I), DOUBLE), \ | |
13169 | X(3, (Q, Q, I), QUAD), \ | |
13170 | X(3, (D, D, S), DOUBLE), \ | |
13171 | X(3, (Q, Q, S), QUAD), \ | |
13172 | X(2, (D, D), DOUBLE), \ | |
13173 | X(2, (Q, Q), QUAD), \ | |
13174 | X(2, (D, S), DOUBLE), \ | |
13175 | X(2, (Q, S), QUAD), \ | |
13176 | X(2, (D, R), DOUBLE), \ | |
13177 | X(2, (Q, R), QUAD), \ | |
13178 | X(2, (D, I), DOUBLE), \ | |
13179 | X(2, (Q, I), QUAD), \ | |
13180 | X(3, (D, L, D), DOUBLE), \ | |
13181 | X(2, (D, Q), MIXED), \ | |
13182 | X(2, (Q, D), MIXED), \ | |
13183 | X(3, (D, Q, I), MIXED), \ | |
13184 | X(3, (Q, D, I), MIXED), \ | |
13185 | X(3, (Q, D, D), MIXED), \ | |
13186 | X(3, (D, Q, Q), MIXED), \ | |
13187 | X(3, (Q, Q, D), MIXED), \ | |
13188 | X(3, (Q, D, S), MIXED), \ | |
13189 | X(3, (D, Q, S), MIXED), \ | |
13190 | X(4, (D, D, D, I), DOUBLE), \ | |
13191 | X(4, (Q, Q, Q, I), QUAD), \ | |
13192 | X(2, (F, F), SINGLE), \ | |
13193 | X(3, (F, F, F), SINGLE), \ | |
13194 | X(2, (F, I), SINGLE), \ | |
13195 | X(2, (F, D), MIXED), \ | |
13196 | X(2, (D, F), MIXED), \ | |
13197 | X(3, (F, F, I), MIXED), \ | |
13198 | X(4, (R, R, F, F), SINGLE), \ | |
13199 | X(4, (F, F, R, R), SINGLE), \ | |
13200 | X(3, (D, R, R), DOUBLE), \ | |
13201 | X(3, (R, R, D), DOUBLE), \ | |
13202 | X(2, (S, R), SINGLE), \ | |
13203 | X(2, (R, S), SINGLE), \ | |
13204 | X(2, (F, R), SINGLE), \ | |
13205 | X(2, (R, F), SINGLE) | |
13206 | ||
13207 | #define S2(A,B) NS_##A##B | |
13208 | #define S3(A,B,C) NS_##A##B##C | |
13209 | #define S4(A,B,C,D) NS_##A##B##C##D | |
13210 | ||
13211 | #define X(N, L, C) S##N L | |
13212 | ||
5287ad62 JB |
13213 | enum neon_shape |
13214 | { | |
037e8744 JB |
13215 | NEON_SHAPE_DEF, |
13216 | NS_NULL | |
5287ad62 | 13217 | }; |
b99bd4ef | 13218 | |
037e8744 JB |
13219 | #undef X |
13220 | #undef S2 | |
13221 | #undef S3 | |
13222 | #undef S4 | |
13223 | ||
13224 | enum neon_shape_class | |
13225 | { | |
13226 | SC_SINGLE, | |
13227 | SC_DOUBLE, | |
13228 | SC_QUAD, | |
13229 | SC_MIXED | |
13230 | }; | |
13231 | ||
13232 | #define X(N, L, C) SC_##C | |
13233 | ||
13234 | static enum neon_shape_class neon_shape_class[] = | |
13235 | { | |
13236 | NEON_SHAPE_DEF | |
13237 | }; | |
13238 | ||
13239 | #undef X | |
13240 | ||
13241 | enum neon_shape_el | |
13242 | { | |
13243 | SE_F, | |
13244 | SE_D, | |
13245 | SE_Q, | |
13246 | SE_I, | |
13247 | SE_S, | |
13248 | SE_R, | |
13249 | SE_L | |
13250 | }; | |
13251 | ||
13252 | /* Register widths of above. */ | |
13253 | static unsigned neon_shape_el_size[] = | |
13254 | { | |
13255 | 32, | |
13256 | 64, | |
13257 | 128, | |
13258 | 0, | |
13259 | 32, | |
13260 | 32, | |
13261 | 0 | |
13262 | }; | |
13263 | ||
13264 | struct neon_shape_info | |
13265 | { | |
13266 | unsigned els; | |
13267 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
13268 | }; | |
13269 | ||
13270 | #define S2(A,B) { SE_##A, SE_##B } | |
13271 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
13272 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
13273 | ||
13274 | #define X(N, L, C) { N, S##N L } | |
13275 | ||
13276 | static struct neon_shape_info neon_shape_tab[] = | |
13277 | { | |
13278 | NEON_SHAPE_DEF | |
13279 | }; | |
13280 | ||
13281 | #undef X | |
13282 | #undef S2 | |
13283 | #undef S3 | |
13284 | #undef S4 | |
13285 | ||
5287ad62 JB |
13286 | /* Bit masks used in type checking given instructions. |
13287 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
13288 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
13289 | set, various other bits can be set as well in order to modify the meaning of | |
13290 | the type constraint. */ | |
13291 | ||
13292 | enum neon_type_mask | |
13293 | { | |
8e79c3df CM |
13294 | N_S8 = 0x0000001, |
13295 | N_S16 = 0x0000002, | |
13296 | N_S32 = 0x0000004, | |
13297 | N_S64 = 0x0000008, | |
13298 | N_U8 = 0x0000010, | |
13299 | N_U16 = 0x0000020, | |
13300 | N_U32 = 0x0000040, | |
13301 | N_U64 = 0x0000080, | |
13302 | N_I8 = 0x0000100, | |
13303 | N_I16 = 0x0000200, | |
13304 | N_I32 = 0x0000400, | |
13305 | N_I64 = 0x0000800, | |
13306 | N_8 = 0x0001000, | |
13307 | N_16 = 0x0002000, | |
13308 | N_32 = 0x0004000, | |
13309 | N_64 = 0x0008000, | |
13310 | N_P8 = 0x0010000, | |
13311 | N_P16 = 0x0020000, | |
13312 | N_F16 = 0x0040000, | |
13313 | N_F32 = 0x0080000, | |
13314 | N_F64 = 0x0100000, | |
4f51b4bd | 13315 | N_P64 = 0x0200000, |
c921be7d NC |
13316 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
13317 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 13318 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
91ff7894 | 13319 | N_UNT = 0x8000000, /* Must be explicitly untyped. */ |
c921be7d NC |
13320 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
13321 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
13322 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
13323 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
13324 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
13325 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
13326 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 13327 | N_UTYP = 0, |
4f51b4bd | 13328 | N_MAX_NONSPECIAL = N_P64 |
5287ad62 JB |
13329 | }; |
13330 | ||
dcbf9037 JB |
13331 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
13332 | ||
5287ad62 JB |
13333 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
13334 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
13335 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
13336 | #define N_SUF_32 (N_SU_32 | N_F32) | |
13337 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
13338 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
13339 | ||
13340 | /* Pass this as the first type argument to neon_check_type to ignore types | |
13341 | altogether. */ | |
13342 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
13343 | ||
037e8744 JB |
13344 | /* Select a "shape" for the current instruction (describing register types or |
13345 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
13346 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
13347 | function of operand parsing, so this function doesn't need to be called. | |
13348 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
13349 | |
13350 | static enum neon_shape | |
037e8744 | 13351 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 13352 | { |
037e8744 JB |
13353 | va_list ap; |
13354 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
13355 | |
13356 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
13357 | many arguments we should have, so this makes the assumption that we have | |
13358 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
13359 | true in the future. */ | |
13360 | if (!inst.operands[1].present) | |
13361 | inst.operands[1] = inst.operands[0]; | |
13362 | ||
037e8744 | 13363 | va_start (ap, shape); |
5f4273c7 | 13364 | |
21d799b5 | 13365 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
13366 | { |
13367 | unsigned j; | |
13368 | int matches = 1; | |
13369 | ||
13370 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
477330fc RM |
13371 | { |
13372 | if (!inst.operands[j].present) | |
13373 | { | |
13374 | matches = 0; | |
13375 | break; | |
13376 | } | |
13377 | ||
13378 | switch (neon_shape_tab[shape].el[j]) | |
13379 | { | |
13380 | case SE_F: | |
13381 | if (!(inst.operands[j].isreg | |
13382 | && inst.operands[j].isvec | |
13383 | && inst.operands[j].issingle | |
13384 | && !inst.operands[j].isquad)) | |
13385 | matches = 0; | |
13386 | break; | |
13387 | ||
13388 | case SE_D: | |
13389 | if (!(inst.operands[j].isreg | |
13390 | && inst.operands[j].isvec | |
13391 | && !inst.operands[j].isquad | |
13392 | && !inst.operands[j].issingle)) | |
13393 | matches = 0; | |
13394 | break; | |
13395 | ||
13396 | case SE_R: | |
13397 | if (!(inst.operands[j].isreg | |
13398 | && !inst.operands[j].isvec)) | |
13399 | matches = 0; | |
13400 | break; | |
13401 | ||
13402 | case SE_Q: | |
13403 | if (!(inst.operands[j].isreg | |
13404 | && inst.operands[j].isvec | |
13405 | && inst.operands[j].isquad | |
13406 | && !inst.operands[j].issingle)) | |
13407 | matches = 0; | |
13408 | break; | |
13409 | ||
13410 | case SE_I: | |
13411 | if (!(!inst.operands[j].isreg | |
13412 | && !inst.operands[j].isscalar)) | |
13413 | matches = 0; | |
13414 | break; | |
13415 | ||
13416 | case SE_S: | |
13417 | if (!(!inst.operands[j].isreg | |
13418 | && inst.operands[j].isscalar)) | |
13419 | matches = 0; | |
13420 | break; | |
13421 | ||
13422 | case SE_L: | |
13423 | break; | |
13424 | } | |
3fde54a2 JZ |
13425 | if (!matches) |
13426 | break; | |
477330fc | 13427 | } |
ad6cec43 MGD |
13428 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
13429 | /* We've matched all the entries in the shape table, and we don't | |
13430 | have any left over operands which have not been matched. */ | |
477330fc | 13431 | break; |
037e8744 | 13432 | } |
5f4273c7 | 13433 | |
037e8744 | 13434 | va_end (ap); |
5287ad62 | 13435 | |
037e8744 JB |
13436 | if (shape == NS_NULL && first_shape != NS_NULL) |
13437 | first_error (_("invalid instruction shape")); | |
5287ad62 | 13438 | |
037e8744 JB |
13439 | return shape; |
13440 | } | |
5287ad62 | 13441 | |
037e8744 JB |
13442 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
13443 | means the Q bit should be set). */ | |
13444 | ||
13445 | static int | |
13446 | neon_quad (enum neon_shape shape) | |
13447 | { | |
13448 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 13449 | } |
037e8744 | 13450 | |
5287ad62 JB |
13451 | static void |
13452 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
477330fc | 13453 | unsigned *g_size) |
5287ad62 JB |
13454 | { |
13455 | /* Allow modification to be made to types which are constrained to be | |
13456 | based on the key element, based on bits set alongside N_EQK. */ | |
13457 | if ((typebits & N_EQK) != 0) | |
13458 | { | |
13459 | if ((typebits & N_HLF) != 0) | |
13460 | *g_size /= 2; | |
13461 | else if ((typebits & N_DBL) != 0) | |
13462 | *g_size *= 2; | |
13463 | if ((typebits & N_SGN) != 0) | |
13464 | *g_type = NT_signed; | |
13465 | else if ((typebits & N_UNS) != 0) | |
477330fc | 13466 | *g_type = NT_unsigned; |
5287ad62 | 13467 | else if ((typebits & N_INT) != 0) |
477330fc | 13468 | *g_type = NT_integer; |
5287ad62 | 13469 | else if ((typebits & N_FLT) != 0) |
477330fc | 13470 | *g_type = NT_float; |
dcbf9037 | 13471 | else if ((typebits & N_SIZ) != 0) |
477330fc | 13472 | *g_type = NT_untyped; |
5287ad62 JB |
13473 | } |
13474 | } | |
5f4273c7 | 13475 | |
5287ad62 JB |
13476 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
13477 | operand type, i.e. the single type specified in a Neon instruction when it | |
13478 | is the only one given. */ | |
13479 | ||
13480 | static struct neon_type_el | |
13481 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
13482 | { | |
13483 | struct neon_type_el dest = *key; | |
5f4273c7 | 13484 | |
9c2799c2 | 13485 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 13486 | |
5287ad62 JB |
13487 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
13488 | ||
13489 | return dest; | |
13490 | } | |
13491 | ||
13492 | /* Convert Neon type and size into compact bitmask representation. */ | |
13493 | ||
13494 | static enum neon_type_mask | |
13495 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
13496 | { | |
13497 | switch (type) | |
13498 | { | |
13499 | case NT_untyped: | |
13500 | switch (size) | |
477330fc RM |
13501 | { |
13502 | case 8: return N_8; | |
13503 | case 16: return N_16; | |
13504 | case 32: return N_32; | |
13505 | case 64: return N_64; | |
13506 | default: ; | |
13507 | } | |
5287ad62 JB |
13508 | break; |
13509 | ||
13510 | case NT_integer: | |
13511 | switch (size) | |
477330fc RM |
13512 | { |
13513 | case 8: return N_I8; | |
13514 | case 16: return N_I16; | |
13515 | case 32: return N_I32; | |
13516 | case 64: return N_I64; | |
13517 | default: ; | |
13518 | } | |
5287ad62 JB |
13519 | break; |
13520 | ||
13521 | case NT_float: | |
037e8744 | 13522 | switch (size) |
477330fc | 13523 | { |
8e79c3df | 13524 | case 16: return N_F16; |
477330fc RM |
13525 | case 32: return N_F32; |
13526 | case 64: return N_F64; | |
13527 | default: ; | |
13528 | } | |
5287ad62 JB |
13529 | break; |
13530 | ||
13531 | case NT_poly: | |
13532 | switch (size) | |
477330fc RM |
13533 | { |
13534 | case 8: return N_P8; | |
13535 | case 16: return N_P16; | |
4f51b4bd | 13536 | case 64: return N_P64; |
477330fc RM |
13537 | default: ; |
13538 | } | |
5287ad62 JB |
13539 | break; |
13540 | ||
13541 | case NT_signed: | |
13542 | switch (size) | |
477330fc RM |
13543 | { |
13544 | case 8: return N_S8; | |
13545 | case 16: return N_S16; | |
13546 | case 32: return N_S32; | |
13547 | case 64: return N_S64; | |
13548 | default: ; | |
13549 | } | |
5287ad62 JB |
13550 | break; |
13551 | ||
13552 | case NT_unsigned: | |
13553 | switch (size) | |
477330fc RM |
13554 | { |
13555 | case 8: return N_U8; | |
13556 | case 16: return N_U16; | |
13557 | case 32: return N_U32; | |
13558 | case 64: return N_U64; | |
13559 | default: ; | |
13560 | } | |
5287ad62 JB |
13561 | break; |
13562 | ||
13563 | default: ; | |
13564 | } | |
5f4273c7 | 13565 | |
5287ad62 JB |
13566 | return N_UTYP; |
13567 | } | |
13568 | ||
13569 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
13570 | handles the case where a single bit is set in the mask. */ | |
13571 | ||
dcbf9037 | 13572 | static int |
5287ad62 | 13573 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
477330fc | 13574 | enum neon_type_mask mask) |
5287ad62 | 13575 | { |
dcbf9037 JB |
13576 | if ((mask & N_EQK) != 0) |
13577 | return FAIL; | |
13578 | ||
5287ad62 JB |
13579 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
13580 | *size = 8; | |
c70a8987 | 13581 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0) |
5287ad62 | 13582 | *size = 16; |
dcbf9037 | 13583 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 13584 | *size = 32; |
4f51b4bd | 13585 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0) |
5287ad62 | 13586 | *size = 64; |
dcbf9037 JB |
13587 | else |
13588 | return FAIL; | |
13589 | ||
5287ad62 JB |
13590 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
13591 | *type = NT_signed; | |
dcbf9037 | 13592 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 13593 | *type = NT_unsigned; |
dcbf9037 | 13594 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 13595 | *type = NT_integer; |
dcbf9037 | 13596 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 13597 | *type = NT_untyped; |
4f51b4bd | 13598 | else if ((mask & (N_P8 | N_P16 | N_P64)) != 0) |
5287ad62 | 13599 | *type = NT_poly; |
c70a8987 | 13600 | else if ((mask & (N_F16 | N_F32 | N_F64)) != 0) |
5287ad62 | 13601 | *type = NT_float; |
dcbf9037 JB |
13602 | else |
13603 | return FAIL; | |
5f4273c7 | 13604 | |
dcbf9037 | 13605 | return SUCCESS; |
5287ad62 JB |
13606 | } |
13607 | ||
13608 | /* Modify a bitmask of allowed types. This is only needed for type | |
13609 | relaxation. */ | |
13610 | ||
13611 | static unsigned | |
13612 | modify_types_allowed (unsigned allowed, unsigned mods) | |
13613 | { | |
13614 | unsigned size; | |
13615 | enum neon_el_type type; | |
13616 | unsigned destmask; | |
13617 | int i; | |
5f4273c7 | 13618 | |
5287ad62 | 13619 | destmask = 0; |
5f4273c7 | 13620 | |
5287ad62 JB |
13621 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
13622 | { | |
21d799b5 | 13623 | if (el_type_of_type_chk (&type, &size, |
477330fc RM |
13624 | (enum neon_type_mask) (allowed & i)) == SUCCESS) |
13625 | { | |
13626 | neon_modify_type_size (mods, &type, &size); | |
13627 | destmask |= type_chk_of_el_type (type, size); | |
13628 | } | |
5287ad62 | 13629 | } |
5f4273c7 | 13630 | |
5287ad62 JB |
13631 | return destmask; |
13632 | } | |
13633 | ||
13634 | /* Check type and return type classification. | |
13635 | The manual states (paraphrase): If one datatype is given, it indicates the | |
13636 | type given in: | |
13637 | - the second operand, if there is one | |
13638 | - the operand, if there is no second operand | |
13639 | - the result, if there are no operands. | |
13640 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
13641 | which is set on a per-instruction basis, which is the one which matters when | |
13642 | only one data type is written. | |
13643 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 13644 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
13645 | |
13646 | static struct neon_type_el | |
13647 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
13648 | { | |
13649 | va_list ap; | |
13650 | unsigned i, pass, key_el = 0; | |
13651 | unsigned types[NEON_MAX_TYPE_ELS]; | |
13652 | enum neon_el_type k_type = NT_invtype; | |
13653 | unsigned k_size = -1u; | |
13654 | struct neon_type_el badtype = {NT_invtype, -1}; | |
13655 | unsigned key_allowed = 0; | |
13656 | ||
13657 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
13658 | Fill in the missing operand here, if it was omitted. */ | |
13659 | if (els > 1 && !inst.operands[1].present) | |
13660 | inst.operands[1] = inst.operands[0]; | |
13661 | ||
13662 | /* Suck up all the varargs. */ | |
13663 | va_start (ap, ns); | |
13664 | for (i = 0; i < els; i++) | |
13665 | { | |
13666 | unsigned thisarg = va_arg (ap, unsigned); | |
13667 | if (thisarg == N_IGNORE_TYPE) | |
477330fc RM |
13668 | { |
13669 | va_end (ap); | |
13670 | return badtype; | |
13671 | } | |
5287ad62 JB |
13672 | types[i] = thisarg; |
13673 | if ((thisarg & N_KEY) != 0) | |
477330fc | 13674 | key_el = i; |
5287ad62 JB |
13675 | } |
13676 | va_end (ap); | |
13677 | ||
dcbf9037 JB |
13678 | if (inst.vectype.elems > 0) |
13679 | for (i = 0; i < els; i++) | |
13680 | if (inst.operands[i].vectype.type != NT_invtype) | |
477330fc RM |
13681 | { |
13682 | first_error (_("types specified in both the mnemonic and operands")); | |
13683 | return badtype; | |
13684 | } | |
dcbf9037 | 13685 | |
5287ad62 JB |
13686 | /* Duplicate inst.vectype elements here as necessary. |
13687 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
13688 | particularly when an insn takes one register and one non-register | |
13689 | operand. */ | |
13690 | if (inst.vectype.elems == 1 && els > 1) | |
13691 | { | |
13692 | unsigned j; | |
13693 | inst.vectype.elems = els; | |
13694 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
13695 | for (j = 0; j < els; j++) | |
477330fc RM |
13696 | if (j != key_el) |
13697 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13698 | types[j]); | |
dcbf9037 JB |
13699 | } |
13700 | else if (inst.vectype.elems == 0 && els > 0) | |
13701 | { | |
13702 | unsigned j; | |
13703 | /* No types were given after the mnemonic, so look for types specified | |
477330fc RM |
13704 | after each operand. We allow some flexibility here; as long as the |
13705 | "key" operand has a type, we can infer the others. */ | |
dcbf9037 | 13706 | for (j = 0; j < els; j++) |
477330fc RM |
13707 | if (inst.operands[j].vectype.type != NT_invtype) |
13708 | inst.vectype.el[j] = inst.operands[j].vectype; | |
dcbf9037 JB |
13709 | |
13710 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
477330fc RM |
13711 | { |
13712 | for (j = 0; j < els; j++) | |
13713 | if (inst.operands[j].vectype.type == NT_invtype) | |
13714 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
13715 | types[j]); | |
13716 | } | |
dcbf9037 | 13717 | else |
477330fc RM |
13718 | { |
13719 | first_error (_("operand types can't be inferred")); | |
13720 | return badtype; | |
13721 | } | |
5287ad62 JB |
13722 | } |
13723 | else if (inst.vectype.elems != els) | |
13724 | { | |
dcbf9037 | 13725 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
13726 | return badtype; |
13727 | } | |
13728 | ||
13729 | for (pass = 0; pass < 2; pass++) | |
13730 | { | |
13731 | for (i = 0; i < els; i++) | |
477330fc RM |
13732 | { |
13733 | unsigned thisarg = types[i]; | |
13734 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
13735 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
13736 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
13737 | unsigned g_size = inst.vectype.el[i].size; | |
13738 | ||
13739 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
5287ad62 | 13740 | integer types if sign-specific variants are unavailable. */ |
477330fc | 13741 | if ((g_type == NT_signed || g_type == NT_unsigned) |
5287ad62 JB |
13742 | && (types_allowed & N_SU_ALL) == 0) |
13743 | g_type = NT_integer; | |
13744 | ||
477330fc | 13745 | /* If only untyped args are allowed, decay any more specific types to |
5287ad62 JB |
13746 | them. Some instructions only care about signs for some element |
13747 | sizes, so handle that properly. */ | |
477330fc | 13748 | if (((types_allowed & N_UNT) == 0) |
91ff7894 MGD |
13749 | && ((g_size == 8 && (types_allowed & N_8) != 0) |
13750 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
13751 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
13752 | || (g_size == 64 && (types_allowed & N_64) != 0))) | |
5287ad62 JB |
13753 | g_type = NT_untyped; |
13754 | ||
477330fc RM |
13755 | if (pass == 0) |
13756 | { | |
13757 | if ((thisarg & N_KEY) != 0) | |
13758 | { | |
13759 | k_type = g_type; | |
13760 | k_size = g_size; | |
13761 | key_allowed = thisarg & ~N_KEY; | |
13762 | } | |
13763 | } | |
13764 | else | |
13765 | { | |
13766 | if ((thisarg & N_VFP) != 0) | |
13767 | { | |
13768 | enum neon_shape_el regshape; | |
13769 | unsigned regwidth, match; | |
99b253c5 NC |
13770 | |
13771 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
13772 | if (ns == NS_NULL) | |
13773 | { | |
13774 | first_error (_("invalid instruction shape")); | |
13775 | return badtype; | |
13776 | } | |
477330fc RM |
13777 | regshape = neon_shape_tab[ns].el[i]; |
13778 | regwidth = neon_shape_el_size[regshape]; | |
13779 | ||
13780 | /* In VFP mode, operands must match register widths. If we | |
13781 | have a key operand, use its width, else use the width of | |
13782 | the current operand. */ | |
13783 | if (k_size != -1u) | |
13784 | match = k_size; | |
13785 | else | |
13786 | match = g_size; | |
13787 | ||
13788 | if (regwidth != match) | |
13789 | { | |
13790 | first_error (_("operand size must match register width")); | |
13791 | return badtype; | |
13792 | } | |
13793 | } | |
13794 | ||
13795 | if ((thisarg & N_EQK) == 0) | |
13796 | { | |
13797 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
13798 | ||
13799 | if ((given_type & types_allowed) == 0) | |
13800 | { | |
13801 | first_error (_("bad type in Neon instruction")); | |
13802 | return badtype; | |
13803 | } | |
13804 | } | |
13805 | else | |
13806 | { | |
13807 | enum neon_el_type mod_k_type = k_type; | |
13808 | unsigned mod_k_size = k_size; | |
13809 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
13810 | if (g_type != mod_k_type || g_size != mod_k_size) | |
13811 | { | |
13812 | first_error (_("inconsistent types in Neon instruction")); | |
13813 | return badtype; | |
13814 | } | |
13815 | } | |
13816 | } | |
13817 | } | |
5287ad62 JB |
13818 | } |
13819 | ||
13820 | return inst.vectype.el[key_el]; | |
13821 | } | |
13822 | ||
037e8744 | 13823 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 13824 | |
037e8744 JB |
13825 | /* Thumb VFP instructions have 0xE in the condition field. */ |
13826 | ||
13827 | static void | |
13828 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 13829 | { |
88714cb8 DG |
13830 | inst.is_neon = 1; |
13831 | ||
5287ad62 | 13832 | if (thumb_mode) |
037e8744 | 13833 | inst.instruction |= 0xe0000000; |
5287ad62 | 13834 | else |
037e8744 | 13835 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
13836 | } |
13837 | ||
037e8744 JB |
13838 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
13839 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
13840 | etc. It is assumed that operand parsing has already been done, and that the | |
13841 | operands are in the form expected by the given opcode (this isn't necessarily | |
13842 | the same as the form in which they were parsed, hence some massaging must | |
13843 | take place before this function is called). | |
13844 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 13845 | |
037e8744 JB |
13846 | static void |
13847 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 13848 | { |
037e8744 | 13849 | const struct asm_opcode *opcode; |
5f4273c7 | 13850 | |
21d799b5 | 13851 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 13852 | |
037e8744 JB |
13853 | if (!opcode) |
13854 | abort (); | |
5287ad62 | 13855 | |
037e8744 | 13856 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
477330fc RM |
13857 | thumb_mode ? *opcode->tvariant : *opcode->avariant), |
13858 | _(BAD_FPU)); | |
5287ad62 | 13859 | |
88714cb8 DG |
13860 | inst.is_neon = 1; |
13861 | ||
037e8744 JB |
13862 | if (thumb_mode) |
13863 | { | |
13864 | inst.instruction = opcode->tvalue; | |
13865 | opcode->tencode (); | |
13866 | } | |
13867 | else | |
13868 | { | |
13869 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
13870 | opcode->aencode (); | |
13871 | } | |
13872 | } | |
5287ad62 JB |
13873 | |
13874 | static void | |
037e8744 | 13875 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 13876 | { |
037e8744 JB |
13877 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
13878 | ||
13879 | if (rs == NS_FFF) | |
13880 | { | |
13881 | if (is_add) | |
477330fc | 13882 | do_vfp_nsyn_opcode ("fadds"); |
037e8744 | 13883 | else |
477330fc | 13884 | do_vfp_nsyn_opcode ("fsubs"); |
037e8744 JB |
13885 | } |
13886 | else | |
13887 | { | |
13888 | if (is_add) | |
477330fc | 13889 | do_vfp_nsyn_opcode ("faddd"); |
037e8744 | 13890 | else |
477330fc | 13891 | do_vfp_nsyn_opcode ("fsubd"); |
037e8744 JB |
13892 | } |
13893 | } | |
13894 | ||
13895 | /* Check operand types to see if this is a VFP instruction, and if so call | |
13896 | PFN (). */ | |
13897 | ||
13898 | static int | |
13899 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
13900 | { | |
13901 | enum neon_shape rs; | |
13902 | struct neon_type_el et; | |
13903 | ||
13904 | switch (args) | |
13905 | { | |
13906 | case 2: | |
13907 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13908 | et = neon_check_type (2, rs, | |
477330fc | 13909 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 | 13910 | break; |
5f4273c7 | 13911 | |
037e8744 JB |
13912 | case 3: |
13913 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13914 | et = neon_check_type (3, rs, | |
477330fc | 13915 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
037e8744 JB |
13916 | break; |
13917 | ||
13918 | default: | |
13919 | abort (); | |
13920 | } | |
13921 | ||
13922 | if (et.type != NT_invtype) | |
13923 | { | |
13924 | pfn (rs); | |
13925 | return SUCCESS; | |
13926 | } | |
037e8744 | 13927 | |
99b253c5 | 13928 | inst.error = NULL; |
037e8744 JB |
13929 | return FAIL; |
13930 | } | |
13931 | ||
13932 | static void | |
13933 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
13934 | { | |
13935 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 13936 | |
037e8744 JB |
13937 | if (rs == NS_FFF) |
13938 | { | |
13939 | if (is_mla) | |
477330fc | 13940 | do_vfp_nsyn_opcode ("fmacs"); |
037e8744 | 13941 | else |
477330fc | 13942 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
13943 | } |
13944 | else | |
13945 | { | |
13946 | if (is_mla) | |
477330fc | 13947 | do_vfp_nsyn_opcode ("fmacd"); |
037e8744 | 13948 | else |
477330fc | 13949 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
13950 | } |
13951 | } | |
13952 | ||
62f3b8c8 PB |
13953 | static void |
13954 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
13955 | { | |
13956 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
13957 | ||
13958 | if (rs == NS_FFF) | |
13959 | { | |
13960 | if (is_fma) | |
477330fc | 13961 | do_vfp_nsyn_opcode ("ffmas"); |
62f3b8c8 | 13962 | else |
477330fc | 13963 | do_vfp_nsyn_opcode ("ffnmas"); |
62f3b8c8 PB |
13964 | } |
13965 | else | |
13966 | { | |
13967 | if (is_fma) | |
477330fc | 13968 | do_vfp_nsyn_opcode ("ffmad"); |
62f3b8c8 | 13969 | else |
477330fc | 13970 | do_vfp_nsyn_opcode ("ffnmad"); |
62f3b8c8 PB |
13971 | } |
13972 | } | |
13973 | ||
037e8744 JB |
13974 | static void |
13975 | do_vfp_nsyn_mul (enum neon_shape rs) | |
13976 | { | |
13977 | if (rs == NS_FFF) | |
13978 | do_vfp_nsyn_opcode ("fmuls"); | |
13979 | else | |
13980 | do_vfp_nsyn_opcode ("fmuld"); | |
13981 | } | |
13982 | ||
13983 | static void | |
13984 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
13985 | { | |
13986 | int is_neg = (inst.instruction & 0x80) != 0; | |
13987 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
13988 | ||
13989 | if (rs == NS_FF) | |
13990 | { | |
13991 | if (is_neg) | |
477330fc | 13992 | do_vfp_nsyn_opcode ("fnegs"); |
037e8744 | 13993 | else |
477330fc | 13994 | do_vfp_nsyn_opcode ("fabss"); |
037e8744 JB |
13995 | } |
13996 | else | |
13997 | { | |
13998 | if (is_neg) | |
477330fc | 13999 | do_vfp_nsyn_opcode ("fnegd"); |
037e8744 | 14000 | else |
477330fc | 14001 | do_vfp_nsyn_opcode ("fabsd"); |
037e8744 JB |
14002 | } |
14003 | } | |
14004 | ||
14005 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
14006 | insns belong to Neon, and are handled elsewhere. */ | |
14007 | ||
14008 | static void | |
14009 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
14010 | { | |
14011 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
14012 | if (is_ldm) | |
14013 | { | |
14014 | if (is_dbmode) | |
477330fc | 14015 | do_vfp_nsyn_opcode ("fldmdbs"); |
037e8744 | 14016 | else |
477330fc | 14017 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 JB |
14018 | } |
14019 | else | |
14020 | { | |
14021 | if (is_dbmode) | |
477330fc | 14022 | do_vfp_nsyn_opcode ("fstmdbs"); |
037e8744 | 14023 | else |
477330fc | 14024 | do_vfp_nsyn_opcode ("fstmias"); |
037e8744 JB |
14025 | } |
14026 | } | |
14027 | ||
037e8744 JB |
14028 | static void |
14029 | do_vfp_nsyn_sqrt (void) | |
14030 | { | |
14031 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
14032 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14033 | |
037e8744 JB |
14034 | if (rs == NS_FF) |
14035 | do_vfp_nsyn_opcode ("fsqrts"); | |
14036 | else | |
14037 | do_vfp_nsyn_opcode ("fsqrtd"); | |
14038 | } | |
14039 | ||
14040 | static void | |
14041 | do_vfp_nsyn_div (void) | |
14042 | { | |
14043 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
14044 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
14045 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14046 | |
037e8744 JB |
14047 | if (rs == NS_FFF) |
14048 | do_vfp_nsyn_opcode ("fdivs"); | |
14049 | else | |
14050 | do_vfp_nsyn_opcode ("fdivd"); | |
14051 | } | |
14052 | ||
14053 | static void | |
14054 | do_vfp_nsyn_nmul (void) | |
14055 | { | |
14056 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
14057 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
14058 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14059 | |
037e8744 JB |
14060 | if (rs == NS_FFF) |
14061 | { | |
88714cb8 | 14062 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
14063 | do_vfp_sp_dyadic (); |
14064 | } | |
14065 | else | |
14066 | { | |
88714cb8 | 14067 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
14068 | do_vfp_dp_rd_rn_rm (); |
14069 | } | |
14070 | do_vfp_cond_or_thumb (); | |
14071 | } | |
14072 | ||
14073 | static void | |
14074 | do_vfp_nsyn_cmp (void) | |
14075 | { | |
14076 | if (inst.operands[1].isreg) | |
14077 | { | |
14078 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
14079 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 14080 | |
037e8744 | 14081 | if (rs == NS_FF) |
477330fc RM |
14082 | { |
14083 | NEON_ENCODE (SINGLE, inst); | |
14084 | do_vfp_sp_monadic (); | |
14085 | } | |
037e8744 | 14086 | else |
477330fc RM |
14087 | { |
14088 | NEON_ENCODE (DOUBLE, inst); | |
14089 | do_vfp_dp_rd_rm (); | |
14090 | } | |
037e8744 JB |
14091 | } |
14092 | else | |
14093 | { | |
14094 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
14095 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
14096 | ||
14097 | switch (inst.instruction & 0x0fffffff) | |
477330fc RM |
14098 | { |
14099 | case N_MNEM_vcmp: | |
14100 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
14101 | break; | |
14102 | case N_MNEM_vcmpe: | |
14103 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
14104 | break; | |
14105 | default: | |
14106 | abort (); | |
14107 | } | |
5f4273c7 | 14108 | |
037e8744 | 14109 | if (rs == NS_FI) |
477330fc RM |
14110 | { |
14111 | NEON_ENCODE (SINGLE, inst); | |
14112 | do_vfp_sp_compare_z (); | |
14113 | } | |
037e8744 | 14114 | else |
477330fc RM |
14115 | { |
14116 | NEON_ENCODE (DOUBLE, inst); | |
14117 | do_vfp_dp_rd (); | |
14118 | } | |
037e8744 JB |
14119 | } |
14120 | do_vfp_cond_or_thumb (); | |
14121 | } | |
14122 | ||
14123 | static void | |
14124 | nsyn_insert_sp (void) | |
14125 | { | |
14126 | inst.operands[1] = inst.operands[0]; | |
14127 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 14128 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
14129 | inst.operands[0].isreg = 1; |
14130 | inst.operands[0].writeback = 1; | |
14131 | inst.operands[0].present = 1; | |
14132 | } | |
14133 | ||
14134 | static void | |
14135 | do_vfp_nsyn_push (void) | |
14136 | { | |
14137 | nsyn_insert_sp (); | |
14138 | if (inst.operands[1].issingle) | |
14139 | do_vfp_nsyn_opcode ("fstmdbs"); | |
14140 | else | |
14141 | do_vfp_nsyn_opcode ("fstmdbd"); | |
14142 | } | |
14143 | ||
14144 | static void | |
14145 | do_vfp_nsyn_pop (void) | |
14146 | { | |
14147 | nsyn_insert_sp (); | |
14148 | if (inst.operands[1].issingle) | |
22b5b651 | 14149 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 14150 | else |
22b5b651 | 14151 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
14152 | } |
14153 | ||
14154 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
14155 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
14156 | ||
88714cb8 DG |
14157 | static void |
14158 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 14159 | { |
88714cb8 DG |
14160 | unsigned int i = insn->instruction; |
14161 | insn->is_neon = 1; | |
14162 | ||
037e8744 JB |
14163 | if (thumb_mode) |
14164 | { | |
14165 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
14166 | if (i & (1 << 24)) | |
477330fc | 14167 | i |= 1 << 28; |
5f4273c7 | 14168 | |
037e8744 | 14169 | i &= ~(1 << 24); |
5f4273c7 | 14170 | |
037e8744 JB |
14171 | i |= 0xef000000; |
14172 | } | |
14173 | else | |
14174 | i |= 0xf2000000; | |
5f4273c7 | 14175 | |
88714cb8 | 14176 | insn->instruction = i; |
037e8744 JB |
14177 | } |
14178 | ||
14179 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
14180 | (0, 1, 2, 3). */ | |
14181 | ||
14182 | static unsigned | |
14183 | neon_logbits (unsigned x) | |
14184 | { | |
14185 | return ffs (x) - 4; | |
14186 | } | |
14187 | ||
14188 | #define LOW4(R) ((R) & 0xf) | |
14189 | #define HI1(R) (((R) >> 4) & 1) | |
14190 | ||
14191 | /* Encode insns with bit pattern: | |
14192 | ||
14193 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
14194 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 14195 | |
037e8744 JB |
14196 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
14197 | different meaning for some instruction. */ | |
14198 | ||
14199 | static void | |
14200 | neon_three_same (int isquad, int ubit, int size) | |
14201 | { | |
14202 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14203 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14204 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14205 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14206 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14207 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14208 | inst.instruction |= (isquad != 0) << 6; | |
14209 | inst.instruction |= (ubit != 0) << 24; | |
14210 | if (size != -1) | |
14211 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14212 | |
88714cb8 | 14213 | neon_dp_fixup (&inst); |
037e8744 JB |
14214 | } |
14215 | ||
14216 | /* Encode instructions of the form: | |
14217 | ||
14218 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
14219 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
14220 | |
14221 | Don't write size if SIZE == -1. */ | |
14222 | ||
14223 | static void | |
14224 | neon_two_same (int qbit, int ubit, int size) | |
14225 | { | |
14226 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14227 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14228 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14229 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14230 | inst.instruction |= (qbit != 0) << 6; | |
14231 | inst.instruction |= (ubit != 0) << 24; | |
14232 | ||
14233 | if (size != -1) | |
14234 | inst.instruction |= neon_logbits (size) << 18; | |
14235 | ||
88714cb8 | 14236 | neon_dp_fixup (&inst); |
5287ad62 JB |
14237 | } |
14238 | ||
14239 | /* Neon instruction encoders, in approximate order of appearance. */ | |
14240 | ||
14241 | static void | |
14242 | do_neon_dyadic_i_su (void) | |
14243 | { | |
037e8744 | 14244 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14245 | struct neon_type_el et = neon_check_type (3, rs, |
14246 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 14247 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14248 | } |
14249 | ||
14250 | static void | |
14251 | do_neon_dyadic_i64_su (void) | |
14252 | { | |
037e8744 | 14253 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14254 | struct neon_type_el et = neon_check_type (3, rs, |
14255 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 14256 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14257 | } |
14258 | ||
14259 | static void | |
14260 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
477330fc | 14261 | unsigned immbits) |
5287ad62 JB |
14262 | { |
14263 | unsigned size = et.size >> 3; | |
14264 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14265 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14266 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14267 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14268 | inst.instruction |= (isquad != 0) << 6; | |
14269 | inst.instruction |= immbits << 16; | |
14270 | inst.instruction |= (size >> 3) << 7; | |
14271 | inst.instruction |= (size & 0x7) << 19; | |
14272 | if (write_ubit) | |
14273 | inst.instruction |= (uval != 0) << 24; | |
14274 | ||
88714cb8 | 14275 | neon_dp_fixup (&inst); |
5287ad62 JB |
14276 | } |
14277 | ||
14278 | static void | |
14279 | do_neon_shl_imm (void) | |
14280 | { | |
14281 | if (!inst.operands[2].isreg) | |
14282 | { | |
037e8744 | 14283 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14284 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
cb3b1e65 JB |
14285 | int imm = inst.operands[2].imm; |
14286 | ||
14287 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14288 | _("immediate out of range for shift")); | |
88714cb8 | 14289 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14290 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14291 | } |
14292 | else | |
14293 | { | |
037e8744 | 14294 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14295 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14296 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14297 | unsigned int tmp; |
14298 | ||
14299 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
477330fc RM |
14300 | vshl.xx Dd, Dm, Dn |
14301 | whereas other 3-register operations encoded by neon_three_same have | |
14302 | syntax like: | |
14303 | vadd.xx Dd, Dn, Dm | |
14304 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
14305 | here. */ | |
627907b7 JB |
14306 | tmp = inst.operands[2].reg; |
14307 | inst.operands[2].reg = inst.operands[1].reg; | |
14308 | inst.operands[1].reg = tmp; | |
88714cb8 | 14309 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14310 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14311 | } |
14312 | } | |
14313 | ||
14314 | static void | |
14315 | do_neon_qshl_imm (void) | |
14316 | { | |
14317 | if (!inst.operands[2].isreg) | |
14318 | { | |
037e8744 | 14319 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 14320 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
cb3b1e65 | 14321 | int imm = inst.operands[2].imm; |
627907b7 | 14322 | |
cb3b1e65 JB |
14323 | constraint (imm < 0 || (unsigned)imm >= et.size, |
14324 | _("immediate out of range for shift")); | |
88714cb8 | 14325 | NEON_ENCODE (IMMED, inst); |
cb3b1e65 | 14326 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm); |
5287ad62 JB |
14327 | } |
14328 | else | |
14329 | { | |
037e8744 | 14330 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14331 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14332 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); |
627907b7 JB |
14333 | unsigned int tmp; |
14334 | ||
14335 | /* See note in do_neon_shl_imm. */ | |
14336 | tmp = inst.operands[2].reg; | |
14337 | inst.operands[2].reg = inst.operands[1].reg; | |
14338 | inst.operands[1].reg = tmp; | |
88714cb8 | 14339 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14340 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
14341 | } |
14342 | } | |
14343 | ||
627907b7 JB |
14344 | static void |
14345 | do_neon_rshl (void) | |
14346 | { | |
14347 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
14348 | struct neon_type_el et = neon_check_type (3, rs, | |
14349 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
14350 | unsigned int tmp; | |
14351 | ||
14352 | tmp = inst.operands[2].reg; | |
14353 | inst.operands[2].reg = inst.operands[1].reg; | |
14354 | inst.operands[1].reg = tmp; | |
14355 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
14356 | } | |
14357 | ||
5287ad62 JB |
14358 | static int |
14359 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
14360 | { | |
036dc3f7 PB |
14361 | /* Handle .I8 pseudo-instructions. */ |
14362 | if (size == 8) | |
5287ad62 | 14363 | { |
5287ad62 | 14364 | /* Unfortunately, this will make everything apart from zero out-of-range. |
477330fc RM |
14365 | FIXME is this the intended semantics? There doesn't seem much point in |
14366 | accepting .I8 if so. */ | |
5287ad62 JB |
14367 | immediate |= immediate << 8; |
14368 | size = 16; | |
036dc3f7 PB |
14369 | } |
14370 | ||
14371 | if (size >= 32) | |
14372 | { | |
14373 | if (immediate == (immediate & 0x000000ff)) | |
14374 | { | |
14375 | *immbits = immediate; | |
14376 | return 0x1; | |
14377 | } | |
14378 | else if (immediate == (immediate & 0x0000ff00)) | |
14379 | { | |
14380 | *immbits = immediate >> 8; | |
14381 | return 0x3; | |
14382 | } | |
14383 | else if (immediate == (immediate & 0x00ff0000)) | |
14384 | { | |
14385 | *immbits = immediate >> 16; | |
14386 | return 0x5; | |
14387 | } | |
14388 | else if (immediate == (immediate & 0xff000000)) | |
14389 | { | |
14390 | *immbits = immediate >> 24; | |
14391 | return 0x7; | |
14392 | } | |
14393 | if ((immediate & 0xffff) != (immediate >> 16)) | |
14394 | goto bad_immediate; | |
14395 | immediate &= 0xffff; | |
5287ad62 JB |
14396 | } |
14397 | ||
14398 | if (immediate == (immediate & 0x000000ff)) | |
14399 | { | |
14400 | *immbits = immediate; | |
036dc3f7 | 14401 | return 0x9; |
5287ad62 JB |
14402 | } |
14403 | else if (immediate == (immediate & 0x0000ff00)) | |
14404 | { | |
14405 | *immbits = immediate >> 8; | |
036dc3f7 | 14406 | return 0xb; |
5287ad62 JB |
14407 | } |
14408 | ||
14409 | bad_immediate: | |
dcbf9037 | 14410 | first_error (_("immediate value out of range")); |
5287ad62 JB |
14411 | return FAIL; |
14412 | } | |
14413 | ||
5287ad62 JB |
14414 | static void |
14415 | do_neon_logic (void) | |
14416 | { | |
14417 | if (inst.operands[2].present && inst.operands[2].isreg) | |
14418 | { | |
037e8744 | 14419 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14420 | neon_check_type (3, rs, N_IGNORE_TYPE); |
14421 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 14422 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14423 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14424 | } |
14425 | else | |
14426 | { | |
4316f0d2 DG |
14427 | const int three_ops_form = (inst.operands[2].present |
14428 | && !inst.operands[2].isreg); | |
14429 | const int immoperand = (three_ops_form ? 2 : 1); | |
14430 | enum neon_shape rs = (three_ops_form | |
14431 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
14432 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 | 14433 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14434 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); |
21d799b5 | 14435 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
14436 | unsigned immbits; |
14437 | int cmode; | |
5f4273c7 | 14438 | |
5287ad62 | 14439 | if (et.type == NT_invtype) |
477330fc | 14440 | return; |
5f4273c7 | 14441 | |
4316f0d2 DG |
14442 | if (three_ops_form) |
14443 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14444 | _("first and second operands shall be the same register")); | |
14445 | ||
88714cb8 | 14446 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 14447 | |
4316f0d2 | 14448 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
14449 | if (et.size == 64) |
14450 | { | |
14451 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
14452 | pattern. */ | |
4316f0d2 DG |
14453 | if (immbits != (inst.operands[immoperand].regisimm ? |
14454 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
14455 | { |
14456 | /* Set immbits to an invalid constant. */ | |
14457 | immbits = 0xdeadbeef; | |
14458 | } | |
14459 | } | |
14460 | ||
5287ad62 | 14461 | switch (opcode) |
477330fc RM |
14462 | { |
14463 | case N_MNEM_vbic: | |
14464 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14465 | break; | |
14466 | ||
14467 | case N_MNEM_vorr: | |
14468 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14469 | break; | |
14470 | ||
14471 | case N_MNEM_vand: | |
14472 | /* Pseudo-instruction for VBIC. */ | |
14473 | neon_invert_size (&immbits, 0, et.size); | |
14474 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14475 | break; | |
14476 | ||
14477 | case N_MNEM_vorn: | |
14478 | /* Pseudo-instruction for VORR. */ | |
14479 | neon_invert_size (&immbits, 0, et.size); | |
14480 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
14481 | break; | |
14482 | ||
14483 | default: | |
14484 | abort (); | |
14485 | } | |
5287ad62 JB |
14486 | |
14487 | if (cmode == FAIL) | |
477330fc | 14488 | return; |
5287ad62 | 14489 | |
037e8744 | 14490 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14491 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14492 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14493 | inst.instruction |= cmode << 8; | |
14494 | neon_write_immbits (immbits); | |
5f4273c7 | 14495 | |
88714cb8 | 14496 | neon_dp_fixup (&inst); |
5287ad62 JB |
14497 | } |
14498 | } | |
14499 | ||
14500 | static void | |
14501 | do_neon_bitfield (void) | |
14502 | { | |
037e8744 | 14503 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14504 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 14505 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14506 | } |
14507 | ||
14508 | static void | |
dcbf9037 | 14509 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
477330fc | 14510 | unsigned destbits) |
5287ad62 | 14511 | { |
037e8744 | 14512 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 14513 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
477330fc | 14514 | types | N_KEY); |
5287ad62 JB |
14515 | if (et.type == NT_float) |
14516 | { | |
88714cb8 | 14517 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 14518 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14519 | } |
14520 | else | |
14521 | { | |
88714cb8 | 14522 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14523 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
14524 | } |
14525 | } | |
14526 | ||
14527 | static void | |
14528 | do_neon_dyadic_if_su (void) | |
14529 | { | |
dcbf9037 | 14530 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14531 | } |
14532 | ||
14533 | static void | |
14534 | do_neon_dyadic_if_su_d (void) | |
14535 | { | |
14536 | /* This version only allow D registers, but that constraint is enforced during | |
14537 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 14538 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
14539 | } |
14540 | ||
5287ad62 JB |
14541 | static void |
14542 | do_neon_dyadic_if_i_d (void) | |
14543 | { | |
428e3f1f PB |
14544 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14545 | affected if we specify unsigned args. */ | |
14546 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
14547 | } |
14548 | ||
037e8744 JB |
14549 | enum vfp_or_neon_is_neon_bits |
14550 | { | |
14551 | NEON_CHECK_CC = 1, | |
73924fbc MGD |
14552 | NEON_CHECK_ARCH = 2, |
14553 | NEON_CHECK_ARCH8 = 4 | |
037e8744 JB |
14554 | }; |
14555 | ||
14556 | /* Call this function if an instruction which may have belonged to the VFP or | |
14557 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
14558 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
14559 | things: | |
14560 | ||
14561 | - Make sure the user hasn't attempted to make a Neon instruction | |
14562 | conditional. | |
14563 | - Alter the value in the condition code field if necessary. | |
14564 | - Make sure that the arch supports Neon instructions. | |
14565 | ||
14566 | Which of these operations take place depends on bits from enum | |
14567 | vfp_or_neon_is_neon_bits. | |
14568 | ||
14569 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
14570 | current instruction's condition is COND_ALWAYS, the condition field is | |
14571 | changed to inst.uncond_value. This is necessary because instructions shared | |
14572 | between VFP and Neon may be conditional for the VFP variants only, and the | |
14573 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
14574 | ||
14575 | static int | |
14576 | vfp_or_neon_is_neon (unsigned check) | |
14577 | { | |
14578 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
14579 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
14580 | { | |
14581 | if (inst.cond != COND_ALWAYS) | |
477330fc RM |
14582 | { |
14583 | first_error (_(BAD_COND)); | |
14584 | return FAIL; | |
14585 | } | |
037e8744 | 14586 | if (inst.uncond_value != -1) |
477330fc | 14587 | inst.instruction |= inst.uncond_value << 28; |
037e8744 | 14588 | } |
5f4273c7 | 14589 | |
037e8744 | 14590 | if ((check & NEON_CHECK_ARCH) |
73924fbc MGD |
14591 | && !mark_feature_used (&fpu_neon_ext_v1)) |
14592 | { | |
14593 | first_error (_(BAD_FPU)); | |
14594 | return FAIL; | |
14595 | } | |
14596 | ||
14597 | if ((check & NEON_CHECK_ARCH8) | |
14598 | && !mark_feature_used (&fpu_neon_ext_armv8)) | |
037e8744 JB |
14599 | { |
14600 | first_error (_(BAD_FPU)); | |
14601 | return FAIL; | |
14602 | } | |
5f4273c7 | 14603 | |
037e8744 JB |
14604 | return SUCCESS; |
14605 | } | |
14606 | ||
5287ad62 JB |
14607 | static void |
14608 | do_neon_addsub_if_i (void) | |
14609 | { | |
037e8744 JB |
14610 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
14611 | return; | |
14612 | ||
14613 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14614 | return; | |
14615 | ||
5287ad62 JB |
14616 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
14617 | affected if we specify unsigned args. */ | |
dcbf9037 | 14618 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
14619 | } |
14620 | ||
14621 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
14622 | result to be: | |
14623 | V<op> A,B (A is operand 0, B is operand 2) | |
14624 | to mean: | |
14625 | V<op> A,B,A | |
14626 | not: | |
14627 | V<op> A,B,B | |
14628 | so handle that case specially. */ | |
14629 | ||
14630 | static void | |
14631 | neon_exchange_operands (void) | |
14632 | { | |
14633 | void *scratch = alloca (sizeof (inst.operands[0])); | |
14634 | if (inst.operands[1].present) | |
14635 | { | |
14636 | /* Swap operands[1] and operands[2]. */ | |
14637 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
14638 | inst.operands[1] = inst.operands[2]; | |
14639 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
14640 | } | |
14641 | else | |
14642 | { | |
14643 | inst.operands[1] = inst.operands[2]; | |
14644 | inst.operands[2] = inst.operands[0]; | |
14645 | } | |
14646 | } | |
14647 | ||
14648 | static void | |
14649 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
14650 | { | |
14651 | if (inst.operands[2].isreg) | |
14652 | { | |
14653 | if (invert) | |
477330fc | 14654 | neon_exchange_operands (); |
dcbf9037 | 14655 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
14656 | } |
14657 | else | |
14658 | { | |
037e8744 | 14659 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 | 14660 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 14661 | N_EQK | N_SIZ, immtypes | N_KEY); |
5287ad62 | 14662 | |
88714cb8 | 14663 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14664 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14665 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14666 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14667 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14668 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14669 | inst.instruction |= (et.type == NT_float) << 10; |
14670 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14671 | |
88714cb8 | 14672 | neon_dp_fixup (&inst); |
5287ad62 JB |
14673 | } |
14674 | } | |
14675 | ||
14676 | static void | |
14677 | do_neon_cmp (void) | |
14678 | { | |
14679 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
14680 | } | |
14681 | ||
14682 | static void | |
14683 | do_neon_cmp_inv (void) | |
14684 | { | |
14685 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
14686 | } | |
14687 | ||
14688 | static void | |
14689 | do_neon_ceq (void) | |
14690 | { | |
14691 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
14692 | } | |
14693 | ||
14694 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
14695 | scalars, which are encoded in 5 bits, M : Rm. | |
14696 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
14697 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
14698 | index in M. */ | |
14699 | ||
14700 | static unsigned | |
14701 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
14702 | { | |
dcbf9037 JB |
14703 | unsigned regno = NEON_SCALAR_REG (scalar); |
14704 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
14705 | |
14706 | switch (elsize) | |
14707 | { | |
14708 | case 16: | |
14709 | if (regno > 7 || elno > 3) | |
477330fc | 14710 | goto bad_scalar; |
5287ad62 | 14711 | return regno | (elno << 3); |
5f4273c7 | 14712 | |
5287ad62 JB |
14713 | case 32: |
14714 | if (regno > 15 || elno > 1) | |
477330fc | 14715 | goto bad_scalar; |
5287ad62 JB |
14716 | return regno | (elno << 4); |
14717 | ||
14718 | default: | |
14719 | bad_scalar: | |
dcbf9037 | 14720 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
14721 | } |
14722 | ||
14723 | return 0; | |
14724 | } | |
14725 | ||
14726 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
14727 | ||
14728 | static void | |
14729 | neon_mul_mac (struct neon_type_el et, int ubit) | |
14730 | { | |
dcbf9037 JB |
14731 | unsigned scalar; |
14732 | ||
14733 | /* Give a more helpful error message if we have an invalid type. */ | |
14734 | if (et.type == NT_invtype) | |
14735 | return; | |
5f4273c7 | 14736 | |
dcbf9037 | 14737 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
14738 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14739 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14740 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14741 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14742 | inst.instruction |= LOW4 (scalar); | |
14743 | inst.instruction |= HI1 (scalar) << 5; | |
14744 | inst.instruction |= (et.type == NT_float) << 8; | |
14745 | inst.instruction |= neon_logbits (et.size) << 20; | |
14746 | inst.instruction |= (ubit != 0) << 24; | |
14747 | ||
88714cb8 | 14748 | neon_dp_fixup (&inst); |
5287ad62 JB |
14749 | } |
14750 | ||
14751 | static void | |
14752 | do_neon_mac_maybe_scalar (void) | |
14753 | { | |
037e8744 JB |
14754 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
14755 | return; | |
14756 | ||
14757 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14758 | return; | |
14759 | ||
5287ad62 JB |
14760 | if (inst.operands[2].isscalar) |
14761 | { | |
037e8744 | 14762 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14763 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14764 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); |
88714cb8 | 14765 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14766 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14767 | } |
14768 | else | |
428e3f1f PB |
14769 | { |
14770 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
14771 | affected if we specify unsigned args. */ | |
14772 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14773 | } | |
5287ad62 JB |
14774 | } |
14775 | ||
62f3b8c8 PB |
14776 | static void |
14777 | do_neon_fmac (void) | |
14778 | { | |
14779 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
14780 | return; | |
14781 | ||
14782 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14783 | return; | |
14784 | ||
14785 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14786 | } | |
14787 | ||
5287ad62 JB |
14788 | static void |
14789 | do_neon_tst (void) | |
14790 | { | |
037e8744 | 14791 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14792 | struct neon_type_el et = neon_check_type (3, rs, |
14793 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 14794 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14795 | } |
14796 | ||
14797 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
14798 | same types as the MAC equivalents. The polynomial type for this instruction | |
14799 | is encoded the same as the integer type. */ | |
14800 | ||
14801 | static void | |
14802 | do_neon_mul (void) | |
14803 | { | |
037e8744 JB |
14804 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
14805 | return; | |
14806 | ||
14807 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14808 | return; | |
14809 | ||
5287ad62 JB |
14810 | if (inst.operands[2].isscalar) |
14811 | do_neon_mac_maybe_scalar (); | |
14812 | else | |
dcbf9037 | 14813 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
14814 | } |
14815 | ||
14816 | static void | |
14817 | do_neon_qdmulh (void) | |
14818 | { | |
14819 | if (inst.operands[2].isscalar) | |
14820 | { | |
037e8744 | 14821 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 | 14822 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14823 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14824 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14825 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14826 | } |
14827 | else | |
14828 | { | |
037e8744 | 14829 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14830 | struct neon_type_el et = neon_check_type (3, rs, |
477330fc | 14831 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); |
88714cb8 | 14832 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14833 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14834 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14835 | } |
14836 | } | |
14837 | ||
14838 | static void | |
14839 | do_neon_fcmp_absolute (void) | |
14840 | { | |
037e8744 | 14841 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14842 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14843 | /* Size field comes from bit mask. */ | |
037e8744 | 14844 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14845 | } |
14846 | ||
14847 | static void | |
14848 | do_neon_fcmp_absolute_inv (void) | |
14849 | { | |
14850 | neon_exchange_operands (); | |
14851 | do_neon_fcmp_absolute (); | |
14852 | } | |
14853 | ||
14854 | static void | |
14855 | do_neon_step (void) | |
14856 | { | |
037e8744 | 14857 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14858 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14859 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14860 | } |
14861 | ||
14862 | static void | |
14863 | do_neon_abs_neg (void) | |
14864 | { | |
037e8744 JB |
14865 | enum neon_shape rs; |
14866 | struct neon_type_el et; | |
5f4273c7 | 14867 | |
037e8744 JB |
14868 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14869 | return; | |
14870 | ||
14871 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14872 | return; | |
14873 | ||
14874 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14875 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14876 | |
5287ad62 JB |
14877 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14878 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14879 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14880 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14881 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14882 | inst.instruction |= (et.type == NT_float) << 10; |
14883 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14884 | |
88714cb8 | 14885 | neon_dp_fixup (&inst); |
5287ad62 JB |
14886 | } |
14887 | ||
14888 | static void | |
14889 | do_neon_sli (void) | |
14890 | { | |
037e8744 | 14891 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14892 | struct neon_type_el et = neon_check_type (2, rs, |
14893 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14894 | int imm = inst.operands[2].imm; | |
14895 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14896 | _("immediate out of range for insert")); |
037e8744 | 14897 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14898 | } |
14899 | ||
14900 | static void | |
14901 | do_neon_sri (void) | |
14902 | { | |
037e8744 | 14903 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14904 | struct neon_type_el et = neon_check_type (2, rs, |
14905 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14906 | int imm = inst.operands[2].imm; | |
14907 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 14908 | _("immediate out of range for insert")); |
037e8744 | 14909 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14910 | } |
14911 | ||
14912 | static void | |
14913 | do_neon_qshlu_imm (void) | |
14914 | { | |
037e8744 | 14915 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14916 | struct neon_type_el et = neon_check_type (2, rs, |
14917 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14918 | int imm = inst.operands[2].imm; | |
14919 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
477330fc | 14920 | _("immediate out of range for shift")); |
5287ad62 JB |
14921 | /* Only encodes the 'U present' variant of the instruction. |
14922 | In this case, signed types have OP (bit 8) set to 0. | |
14923 | Unsigned types have OP set to 1. */ | |
14924 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14925 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14926 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14927 | } |
14928 | ||
14929 | static void | |
14930 | do_neon_qmovn (void) | |
14931 | { | |
14932 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14933 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14934 | /* Saturating move where operands can be signed or unsigned, and the | |
14935 | destination has the same signedness. */ | |
88714cb8 | 14936 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14937 | if (et.type == NT_unsigned) |
14938 | inst.instruction |= 0xc0; | |
14939 | else | |
14940 | inst.instruction |= 0x80; | |
14941 | neon_two_same (0, 1, et.size / 2); | |
14942 | } | |
14943 | ||
14944 | static void | |
14945 | do_neon_qmovun (void) | |
14946 | { | |
14947 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14948 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14949 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14950 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14951 | neon_two_same (0, 1, et.size / 2); |
14952 | } | |
14953 | ||
14954 | static void | |
14955 | do_neon_rshift_sat_narrow (void) | |
14956 | { | |
14957 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14958 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14959 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14960 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14961 | int imm = inst.operands[2].imm; | |
14962 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14963 | right. */ | |
14964 | et.size /= 2; | |
5f4273c7 | 14965 | |
5287ad62 JB |
14966 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14967 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14968 | if (imm == 0) | |
14969 | { | |
14970 | inst.operands[2].present = 0; | |
14971 | inst.instruction = N_MNEM_vqmovn; | |
14972 | do_neon_qmovn (); | |
14973 | return; | |
14974 | } | |
5f4273c7 | 14975 | |
5287ad62 | 14976 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 14977 | _("immediate out of range")); |
5287ad62 JB |
14978 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); |
14979 | } | |
14980 | ||
14981 | static void | |
14982 | do_neon_rshift_sat_narrow_u (void) | |
14983 | { | |
14984 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14985 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14986 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14987 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14988 | int imm = inst.operands[2].imm; | |
14989 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14990 | right. */ | |
14991 | et.size /= 2; | |
14992 | ||
14993 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14994 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14995 | if (imm == 0) | |
14996 | { | |
14997 | inst.operands[2].present = 0; | |
14998 | inst.instruction = N_MNEM_vqmovun; | |
14999 | do_neon_qmovun (); | |
15000 | return; | |
15001 | } | |
15002 | ||
15003 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 15004 | _("immediate out of range")); |
5287ad62 JB |
15005 | /* FIXME: The manual is kind of unclear about what value U should have in |
15006 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
15007 | must be 1. */ | |
15008 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
15009 | } | |
15010 | ||
15011 | static void | |
15012 | do_neon_movn (void) | |
15013 | { | |
15014 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
15015 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 15016 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15017 | neon_two_same (0, 1, et.size / 2); |
15018 | } | |
15019 | ||
15020 | static void | |
15021 | do_neon_rshift_narrow (void) | |
15022 | { | |
15023 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
15024 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
15025 | int imm = inst.operands[2].imm; | |
15026 | /* This gets the bounds check, size encoding and immediate bits calculation | |
15027 | right. */ | |
15028 | et.size /= 2; | |
5f4273c7 | 15029 | |
5287ad62 JB |
15030 | /* If immediate is zero then we are a pseudo-instruction for |
15031 | VMOVN.I<size> <Dd>, <Qm> */ | |
15032 | if (imm == 0) | |
15033 | { | |
15034 | inst.operands[2].present = 0; | |
15035 | inst.instruction = N_MNEM_vmovn; | |
15036 | do_neon_movn (); | |
15037 | return; | |
15038 | } | |
5f4273c7 | 15039 | |
5287ad62 | 15040 | constraint (imm < 1 || (unsigned)imm > et.size, |
477330fc | 15041 | _("immediate out of range for narrowing operation")); |
5287ad62 JB |
15042 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); |
15043 | } | |
15044 | ||
15045 | static void | |
15046 | do_neon_shll (void) | |
15047 | { | |
15048 | /* FIXME: Type checking when lengthening. */ | |
15049 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
15050 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
15051 | unsigned imm = inst.operands[2].imm; | |
15052 | ||
15053 | if (imm == et.size) | |
15054 | { | |
15055 | /* Maximum shift variant. */ | |
88714cb8 | 15056 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15057 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15058 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15059 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15060 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15061 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 15062 | |
88714cb8 | 15063 | neon_dp_fixup (&inst); |
5287ad62 JB |
15064 | } |
15065 | else | |
15066 | { | |
15067 | /* A more-specific type check for non-max versions. */ | |
15068 | et = neon_check_type (2, NS_QDI, | |
477330fc | 15069 | N_EQK | N_DBL, N_SU_32 | N_KEY); |
88714cb8 | 15070 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15071 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
15072 | } | |
15073 | } | |
15074 | ||
037e8744 | 15075 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
15076 | the current instruction is. */ |
15077 | ||
6b9a8b67 MGD |
15078 | #define CVT_FLAVOUR_VAR \ |
15079 | CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \ | |
15080 | CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \ | |
15081 | CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \ | |
15082 | CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \ | |
15083 | /* Half-precision conversions. */ \ | |
15084 | CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \ | |
15085 | CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \ | |
15086 | /* VFP instructions. */ \ | |
15087 | CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \ | |
15088 | CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \ | |
15089 | CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \ | |
15090 | CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \ | |
15091 | CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \ | |
15092 | CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \ | |
15093 | /* VFP instructions with bitshift. */ \ | |
15094 | CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \ | |
15095 | CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \ | |
15096 | CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \ | |
15097 | CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \ | |
15098 | CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \ | |
15099 | CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \ | |
15100 | CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \ | |
15101 | CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL) | |
15102 | ||
15103 | #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \ | |
15104 | neon_cvt_flavour_##C, | |
15105 | ||
15106 | /* The different types of conversions we can do. */ | |
15107 | enum neon_cvt_flavour | |
15108 | { | |
15109 | CVT_FLAVOUR_VAR | |
15110 | neon_cvt_flavour_invalid, | |
15111 | neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64 | |
15112 | }; | |
15113 | ||
15114 | #undef CVT_VAR | |
15115 | ||
15116 | static enum neon_cvt_flavour | |
15117 | get_neon_cvt_flavour (enum neon_shape rs) | |
5287ad62 | 15118 | { |
6b9a8b67 MGD |
15119 | #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \ |
15120 | et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \ | |
15121 | if (et.type != NT_invtype) \ | |
15122 | { \ | |
15123 | inst.error = NULL; \ | |
15124 | return (neon_cvt_flavour_##C); \ | |
5287ad62 | 15125 | } |
6b9a8b67 | 15126 | |
5287ad62 | 15127 | struct neon_type_el et; |
037e8744 | 15128 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
477330fc | 15129 | || rs == NS_FF) ? N_VFP : 0; |
037e8744 JB |
15130 | /* The instruction versions which take an immediate take one register |
15131 | argument, which is extended to the width of the full register. Thus the | |
15132 | "source" and "destination" registers must have the same width. Hack that | |
15133 | here by making the size equal to the key (wider, in this case) operand. */ | |
15134 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 15135 | |
6b9a8b67 MGD |
15136 | CVT_FLAVOUR_VAR; |
15137 | ||
15138 | return neon_cvt_flavour_invalid; | |
5287ad62 JB |
15139 | #undef CVT_VAR |
15140 | } | |
15141 | ||
7e8e6784 MGD |
15142 | enum neon_cvt_mode |
15143 | { | |
15144 | neon_cvt_mode_a, | |
15145 | neon_cvt_mode_n, | |
15146 | neon_cvt_mode_p, | |
15147 | neon_cvt_mode_m, | |
15148 | neon_cvt_mode_z, | |
30bdf752 MGD |
15149 | neon_cvt_mode_x, |
15150 | neon_cvt_mode_r | |
7e8e6784 MGD |
15151 | }; |
15152 | ||
037e8744 JB |
15153 | /* Neon-syntax VFP conversions. */ |
15154 | ||
5287ad62 | 15155 | static void |
6b9a8b67 | 15156 | do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour) |
5287ad62 | 15157 | { |
037e8744 | 15158 | const char *opname = 0; |
5f4273c7 | 15159 | |
037e8744 | 15160 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 15161 | { |
037e8744 JB |
15162 | /* Conversions with immediate bitshift. */ |
15163 | const char *enc[] = | |
477330fc | 15164 | { |
6b9a8b67 MGD |
15165 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN, |
15166 | CVT_FLAVOUR_VAR | |
15167 | NULL | |
15168 | #undef CVT_VAR | |
477330fc | 15169 | }; |
037e8744 | 15170 | |
6b9a8b67 | 15171 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc RM |
15172 | { |
15173 | opname = enc[flavour]; | |
15174 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
15175 | _("operands 0 and 1 must be the same register")); | |
15176 | inst.operands[1] = inst.operands[2]; | |
15177 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
15178 | } | |
5287ad62 JB |
15179 | } |
15180 | else | |
15181 | { | |
037e8744 JB |
15182 | /* Conversions without bitshift. */ |
15183 | const char *enc[] = | |
477330fc | 15184 | { |
6b9a8b67 MGD |
15185 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN, |
15186 | CVT_FLAVOUR_VAR | |
15187 | NULL | |
15188 | #undef CVT_VAR | |
477330fc | 15189 | }; |
037e8744 | 15190 | |
6b9a8b67 | 15191 | if (flavour < (int) ARRAY_SIZE (enc)) |
477330fc | 15192 | opname = enc[flavour]; |
037e8744 JB |
15193 | } |
15194 | ||
15195 | if (opname) | |
15196 | do_vfp_nsyn_opcode (opname); | |
15197 | } | |
15198 | ||
15199 | static void | |
15200 | do_vfp_nsyn_cvtz (void) | |
15201 | { | |
15202 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
6b9a8b67 | 15203 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 JB |
15204 | const char *enc[] = |
15205 | { | |
6b9a8b67 MGD |
15206 | #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN, |
15207 | CVT_FLAVOUR_VAR | |
15208 | NULL | |
15209 | #undef CVT_VAR | |
037e8744 JB |
15210 | }; |
15211 | ||
6b9a8b67 | 15212 | if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
037e8744 JB |
15213 | do_vfp_nsyn_opcode (enc[flavour]); |
15214 | } | |
f31fef98 | 15215 | |
037e8744 | 15216 | static void |
bacebabc | 15217 | do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour, |
7e8e6784 MGD |
15218 | enum neon_cvt_mode mode) |
15219 | { | |
15220 | int sz, op; | |
15221 | int rm; | |
15222 | ||
a715796b TG |
15223 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
15224 | D register operands. */ | |
15225 | if (flavour == neon_cvt_flavour_s32_f64 | |
15226 | || flavour == neon_cvt_flavour_u32_f64) | |
15227 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15228 | _(BAD_FPU)); | |
15229 | ||
7e8e6784 MGD |
15230 | set_it_insn_type (OUTSIDE_IT_INSN); |
15231 | ||
15232 | switch (flavour) | |
15233 | { | |
15234 | case neon_cvt_flavour_s32_f64: | |
15235 | sz = 1; | |
827f64ff | 15236 | op = 1; |
7e8e6784 MGD |
15237 | break; |
15238 | case neon_cvt_flavour_s32_f32: | |
15239 | sz = 0; | |
15240 | op = 1; | |
15241 | break; | |
15242 | case neon_cvt_flavour_u32_f64: | |
15243 | sz = 1; | |
15244 | op = 0; | |
15245 | break; | |
15246 | case neon_cvt_flavour_u32_f32: | |
15247 | sz = 0; | |
15248 | op = 0; | |
15249 | break; | |
15250 | default: | |
15251 | first_error (_("invalid instruction shape")); | |
15252 | return; | |
15253 | } | |
15254 | ||
15255 | switch (mode) | |
15256 | { | |
15257 | case neon_cvt_mode_a: rm = 0; break; | |
15258 | case neon_cvt_mode_n: rm = 1; break; | |
15259 | case neon_cvt_mode_p: rm = 2; break; | |
15260 | case neon_cvt_mode_m: rm = 3; break; | |
15261 | default: first_error (_("invalid rounding mode")); return; | |
15262 | } | |
15263 | ||
15264 | NEON_ENCODE (FPV8, inst); | |
15265 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
15266 | encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm); | |
15267 | inst.instruction |= sz << 8; | |
15268 | inst.instruction |= op << 7; | |
15269 | inst.instruction |= rm << 16; | |
15270 | inst.instruction |= 0xf0000000; | |
15271 | inst.is_neon = TRUE; | |
15272 | } | |
15273 | ||
15274 | static void | |
15275 | do_neon_cvt_1 (enum neon_cvt_mode mode) | |
037e8744 JB |
15276 | { |
15277 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 15278 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
6b9a8b67 | 15279 | enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs); |
037e8744 | 15280 | |
e3e535bc | 15281 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
7e8e6784 | 15282 | if (mode == neon_cvt_mode_z |
e3e535bc | 15283 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) |
bacebabc RM |
15284 | && (flavour == neon_cvt_flavour_s32_f32 |
15285 | || flavour == neon_cvt_flavour_u32_f32 | |
15286 | || flavour == neon_cvt_flavour_s32_f64 | |
6b9a8b67 | 15287 | || flavour == neon_cvt_flavour_u32_f64) |
e3e535bc NC |
15288 | && (rs == NS_FD || rs == NS_FF)) |
15289 | { | |
15290 | do_vfp_nsyn_cvtz (); | |
15291 | return; | |
15292 | } | |
15293 | ||
037e8744 | 15294 | /* VFP rather than Neon conversions. */ |
6b9a8b67 | 15295 | if (flavour >= neon_cvt_flavour_first_fp) |
037e8744 | 15296 | { |
7e8e6784 MGD |
15297 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15298 | do_vfp_nsyn_cvt (rs, flavour); | |
15299 | else | |
15300 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
15301 | ||
037e8744 JB |
15302 | return; |
15303 | } | |
15304 | ||
15305 | switch (rs) | |
15306 | { | |
15307 | case NS_DDI: | |
15308 | case NS_QQI: | |
15309 | { | |
477330fc RM |
15310 | unsigned immbits; |
15311 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
35997600 | 15312 | |
477330fc RM |
15313 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15314 | return; | |
037e8744 | 15315 | |
477330fc RM |
15316 | /* Fixed-point conversion with #0 immediate is encoded as an |
15317 | integer conversion. */ | |
15318 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
15319 | goto int_encode; | |
35997600 | 15320 | immbits = 32 - inst.operands[2].imm; |
477330fc RM |
15321 | NEON_ENCODE (IMMED, inst); |
15322 | if (flavour != neon_cvt_flavour_invalid) | |
15323 | inst.instruction |= enctab[flavour]; | |
15324 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15325 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15326 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15327 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15328 | inst.instruction |= neon_quad (rs) << 6; | |
15329 | inst.instruction |= 1 << 21; | |
15330 | inst.instruction |= immbits << 16; | |
15331 | ||
15332 | neon_dp_fixup (&inst); | |
037e8744 JB |
15333 | } |
15334 | break; | |
15335 | ||
15336 | case NS_DD: | |
15337 | case NS_QQ: | |
7e8e6784 MGD |
15338 | if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z) |
15339 | { | |
15340 | NEON_ENCODE (FLOAT, inst); | |
15341 | set_it_insn_type (OUTSIDE_IT_INSN); | |
15342 | ||
15343 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
15344 | return; | |
15345 | ||
15346 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15347 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15348 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15349 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15350 | inst.instruction |= neon_quad (rs) << 6; | |
15351 | inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7; | |
15352 | inst.instruction |= mode << 8; | |
15353 | if (thumb_mode) | |
15354 | inst.instruction |= 0xfc000000; | |
15355 | else | |
15356 | inst.instruction |= 0xf0000000; | |
15357 | } | |
15358 | else | |
15359 | { | |
037e8744 | 15360 | int_encode: |
7e8e6784 MGD |
15361 | { |
15362 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
037e8744 | 15363 | |
7e8e6784 | 15364 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15365 | |
7e8e6784 MGD |
15366 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15367 | return; | |
037e8744 | 15368 | |
7e8e6784 MGD |
15369 | if (flavour != neon_cvt_flavour_invalid) |
15370 | inst.instruction |= enctab[flavour]; | |
037e8744 | 15371 | |
7e8e6784 MGD |
15372 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15373 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15374 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15375 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15376 | inst.instruction |= neon_quad (rs) << 6; | |
15377 | inst.instruction |= 2 << 18; | |
037e8744 | 15378 | |
7e8e6784 MGD |
15379 | neon_dp_fixup (&inst); |
15380 | } | |
15381 | } | |
15382 | break; | |
037e8744 | 15383 | |
8e79c3df CM |
15384 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
15385 | case NS_QD: | |
15386 | case NS_DQ: | |
15387 | ||
15388 | if ((rs == NS_DQ) | |
15389 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
15390 | { | |
15391 | as_bad (_("operand size must match register width")); | |
15392 | break; | |
15393 | } | |
15394 | ||
15395 | if ((rs == NS_QD) | |
15396 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
15397 | { | |
15398 | as_bad (_("operand size must match register width")); | |
15399 | break; | |
15400 | } | |
15401 | ||
15402 | if (rs == NS_DQ) | |
477330fc | 15403 | inst.instruction = 0x3b60600; |
8e79c3df CM |
15404 | else |
15405 | inst.instruction = 0x3b60700; | |
15406 | ||
15407 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15408 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15409 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15410 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 15411 | neon_dp_fixup (&inst); |
8e79c3df CM |
15412 | break; |
15413 | ||
037e8744 JB |
15414 | default: |
15415 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
7e8e6784 MGD |
15416 | if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z) |
15417 | do_vfp_nsyn_cvt (rs, flavour); | |
15418 | else | |
15419 | do_vfp_nsyn_cvt_fpv8 (flavour, mode); | |
5287ad62 | 15420 | } |
5287ad62 JB |
15421 | } |
15422 | ||
e3e535bc NC |
15423 | static void |
15424 | do_neon_cvtr (void) | |
15425 | { | |
7e8e6784 | 15426 | do_neon_cvt_1 (neon_cvt_mode_x); |
e3e535bc NC |
15427 | } |
15428 | ||
15429 | static void | |
15430 | do_neon_cvt (void) | |
15431 | { | |
7e8e6784 MGD |
15432 | do_neon_cvt_1 (neon_cvt_mode_z); |
15433 | } | |
15434 | ||
15435 | static void | |
15436 | do_neon_cvta (void) | |
15437 | { | |
15438 | do_neon_cvt_1 (neon_cvt_mode_a); | |
15439 | } | |
15440 | ||
15441 | static void | |
15442 | do_neon_cvtn (void) | |
15443 | { | |
15444 | do_neon_cvt_1 (neon_cvt_mode_n); | |
15445 | } | |
15446 | ||
15447 | static void | |
15448 | do_neon_cvtp (void) | |
15449 | { | |
15450 | do_neon_cvt_1 (neon_cvt_mode_p); | |
15451 | } | |
15452 | ||
15453 | static void | |
15454 | do_neon_cvtm (void) | |
15455 | { | |
15456 | do_neon_cvt_1 (neon_cvt_mode_m); | |
e3e535bc NC |
15457 | } |
15458 | ||
8e79c3df | 15459 | static void |
c70a8987 | 15460 | do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double) |
8e79c3df | 15461 | { |
c70a8987 MGD |
15462 | if (is_double) |
15463 | mark_feature_used (&fpu_vfp_ext_armv8); | |
8e79c3df | 15464 | |
c70a8987 MGD |
15465 | encode_arm_vfp_reg (inst.operands[0].reg, |
15466 | (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd); | |
15467 | encode_arm_vfp_reg (inst.operands[1].reg, | |
15468 | (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm); | |
15469 | inst.instruction |= to ? 0x10000 : 0; | |
15470 | inst.instruction |= t ? 0x80 : 0; | |
15471 | inst.instruction |= is_double ? 0x100 : 0; | |
15472 | do_vfp_cond_or_thumb (); | |
15473 | } | |
8e79c3df | 15474 | |
c70a8987 MGD |
15475 | static void |
15476 | do_neon_cvttb_1 (bfd_boolean t) | |
15477 | { | |
15478 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL); | |
8e79c3df | 15479 | |
c70a8987 MGD |
15480 | if (rs == NS_NULL) |
15481 | return; | |
15482 | else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype) | |
15483 | { | |
15484 | inst.error = NULL; | |
15485 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE); | |
15486 | } | |
15487 | else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype) | |
15488 | { | |
15489 | inst.error = NULL; | |
15490 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE); | |
15491 | } | |
15492 | else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype) | |
15493 | { | |
a715796b TG |
15494 | /* The VCVTB and VCVTT instructions with D-register operands |
15495 | don't work for SP only targets. */ | |
15496 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15497 | _(BAD_FPU)); | |
15498 | ||
c70a8987 MGD |
15499 | inst.error = NULL; |
15500 | do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE); | |
15501 | } | |
15502 | else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype) | |
15503 | { | |
a715796b TG |
15504 | /* The VCVTB and VCVTT instructions with D-register operands |
15505 | don't work for SP only targets. */ | |
15506 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
15507 | _(BAD_FPU)); | |
15508 | ||
c70a8987 MGD |
15509 | inst.error = NULL; |
15510 | do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE); | |
15511 | } | |
15512 | else | |
15513 | return; | |
15514 | } | |
15515 | ||
15516 | static void | |
15517 | do_neon_cvtb (void) | |
15518 | { | |
15519 | do_neon_cvttb_1 (FALSE); | |
8e79c3df CM |
15520 | } |
15521 | ||
15522 | ||
15523 | static void | |
15524 | do_neon_cvtt (void) | |
15525 | { | |
c70a8987 | 15526 | do_neon_cvttb_1 (TRUE); |
8e79c3df CM |
15527 | } |
15528 | ||
5287ad62 JB |
15529 | static void |
15530 | neon_move_immediate (void) | |
15531 | { | |
037e8744 JB |
15532 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
15533 | struct neon_type_el et = neon_check_type (2, rs, | |
15534 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 15535 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 15536 | int op, cmode, float_p; |
5287ad62 | 15537 | |
037e8744 | 15538 | constraint (et.type == NT_invtype, |
477330fc | 15539 | _("operand size must be specified for immediate VMOV")); |
037e8744 | 15540 | |
5287ad62 JB |
15541 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
15542 | op = (inst.instruction & (1 << 5)) != 0; | |
15543 | ||
15544 | immlo = inst.operands[1].imm; | |
15545 | if (inst.operands[1].regisimm) | |
15546 | immhi = inst.operands[1].reg; | |
15547 | ||
15548 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
477330fc | 15549 | _("immediate has bits set outside the operand size")); |
5287ad62 | 15550 | |
c96612cc JB |
15551 | float_p = inst.operands[1].immisfloat; |
15552 | ||
15553 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
477330fc | 15554 | et.size, et.type)) == FAIL) |
5287ad62 JB |
15555 | { |
15556 | /* Invert relevant bits only. */ | |
15557 | neon_invert_size (&immlo, &immhi, et.size); | |
15558 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
477330fc RM |
15559 | with one or the other; those cases are caught by |
15560 | neon_cmode_for_move_imm. */ | |
5287ad62 | 15561 | op = !op; |
c96612cc JB |
15562 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
15563 | &op, et.size, et.type)) == FAIL) | |
477330fc RM |
15564 | { |
15565 | first_error (_("immediate out of range")); | |
15566 | return; | |
15567 | } | |
5287ad62 JB |
15568 | } |
15569 | ||
15570 | inst.instruction &= ~(1 << 5); | |
15571 | inst.instruction |= op << 5; | |
15572 | ||
15573 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15574 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 15575 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15576 | inst.instruction |= cmode << 8; |
15577 | ||
15578 | neon_write_immbits (immbits); | |
15579 | } | |
15580 | ||
15581 | static void | |
15582 | do_neon_mvn (void) | |
15583 | { | |
15584 | if (inst.operands[1].isreg) | |
15585 | { | |
037e8744 | 15586 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 15587 | |
88714cb8 | 15588 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15589 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15590 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15591 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15592 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 15593 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15594 | } |
15595 | else | |
15596 | { | |
88714cb8 | 15597 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
15598 | neon_move_immediate (); |
15599 | } | |
15600 | ||
88714cb8 | 15601 | neon_dp_fixup (&inst); |
5287ad62 JB |
15602 | } |
15603 | ||
15604 | /* Encode instructions of form: | |
15605 | ||
15606 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 15607 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
15608 | |
15609 | static void | |
15610 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
15611 | { | |
15612 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15613 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15614 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15615 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15616 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15617 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15618 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
15619 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 15620 | |
88714cb8 | 15621 | neon_dp_fixup (&inst); |
5287ad62 JB |
15622 | } |
15623 | ||
15624 | static void | |
15625 | do_neon_dyadic_long (void) | |
15626 | { | |
15627 | /* FIXME: Type checking for lengthening op. */ | |
15628 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15629 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15630 | neon_mixed_length (et, et.size); | |
15631 | } | |
15632 | ||
15633 | static void | |
15634 | do_neon_abal (void) | |
15635 | { | |
15636 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15637 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
15638 | neon_mixed_length (et, et.size); | |
15639 | } | |
15640 | ||
15641 | static void | |
15642 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
15643 | { | |
15644 | if (inst.operands[2].isscalar) | |
15645 | { | |
dcbf9037 | 15646 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
477330fc | 15647 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); |
88714cb8 | 15648 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15649 | neon_mul_mac (et, et.type == NT_unsigned); |
15650 | } | |
15651 | else | |
15652 | { | |
15653 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15654 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); |
88714cb8 | 15655 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
15656 | neon_mixed_length (et, et.size); |
15657 | } | |
15658 | } | |
15659 | ||
15660 | static void | |
15661 | do_neon_mac_maybe_scalar_long (void) | |
15662 | { | |
15663 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
15664 | } | |
15665 | ||
15666 | static void | |
15667 | do_neon_dyadic_wide (void) | |
15668 | { | |
15669 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
15670 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15671 | neon_mixed_length (et, et.size); | |
15672 | } | |
15673 | ||
15674 | static void | |
15675 | do_neon_dyadic_narrow (void) | |
15676 | { | |
15677 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
15678 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
15679 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
15680 | so force the operand type to integer. */ | |
15681 | et.type = NT_integer; | |
5287ad62 JB |
15682 | neon_mixed_length (et, et.size / 2); |
15683 | } | |
15684 | ||
15685 | static void | |
15686 | do_neon_mul_sat_scalar_long (void) | |
15687 | { | |
15688 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
15689 | } | |
15690 | ||
15691 | static void | |
15692 | do_neon_vmull (void) | |
15693 | { | |
15694 | if (inst.operands[2].isscalar) | |
15695 | do_neon_mac_maybe_scalar_long (); | |
15696 | else | |
15697 | { | |
15698 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
477330fc | 15699 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY); |
4f51b4bd | 15700 | |
5287ad62 | 15701 | if (et.type == NT_poly) |
477330fc | 15702 | NEON_ENCODE (POLY, inst); |
5287ad62 | 15703 | else |
477330fc | 15704 | NEON_ENCODE (INTEGER, inst); |
4f51b4bd MGD |
15705 | |
15706 | /* For polynomial encoding the U bit must be zero, and the size must | |
15707 | be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non | |
15708 | obviously, as 0b10). */ | |
15709 | if (et.size == 64) | |
15710 | { | |
15711 | /* Check we're on the correct architecture. */ | |
15712 | if (!mark_feature_used (&fpu_crypto_ext_armv8)) | |
15713 | inst.error = | |
15714 | _("Instruction form not available on this architecture."); | |
15715 | ||
15716 | et.size = 32; | |
15717 | } | |
15718 | ||
5287ad62 JB |
15719 | neon_mixed_length (et, et.size); |
15720 | } | |
15721 | } | |
15722 | ||
15723 | static void | |
15724 | do_neon_ext (void) | |
15725 | { | |
037e8744 | 15726 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
15727 | struct neon_type_el et = neon_check_type (3, rs, |
15728 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
15729 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
15730 | |
15731 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
15732 | _("shift out of range")); | |
5287ad62 JB |
15733 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15734 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15735 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15736 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15737 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15738 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 15739 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 15740 | inst.instruction |= imm << 8; |
5f4273c7 | 15741 | |
88714cb8 | 15742 | neon_dp_fixup (&inst); |
5287ad62 JB |
15743 | } |
15744 | ||
15745 | static void | |
15746 | do_neon_rev (void) | |
15747 | { | |
037e8744 | 15748 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15749 | struct neon_type_el et = neon_check_type (2, rs, |
15750 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15751 | unsigned op = (inst.instruction >> 7) & 3; | |
15752 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
15753 | extract it here to check the elements to be reversed are smaller. | |
15754 | Otherwise we'd get a reserved instruction. */ | |
15755 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 15756 | gas_assert (elsize != 0); |
5287ad62 | 15757 | constraint (et.size >= elsize, |
477330fc | 15758 | _("elements must be smaller than reversal region")); |
037e8744 | 15759 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15760 | } |
15761 | ||
15762 | static void | |
15763 | do_neon_dup (void) | |
15764 | { | |
15765 | if (inst.operands[1].isscalar) | |
15766 | { | |
037e8744 | 15767 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 | 15768 | struct neon_type_el et = neon_check_type (2, rs, |
477330fc | 15769 | N_EQK, N_8 | N_16 | N_32 | N_KEY); |
5287ad62 | 15770 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 15771 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 15772 | int logsize = neon_logbits (et.size); |
dcbf9037 | 15773 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
15774 | |
15775 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
477330fc | 15776 | return; |
037e8744 | 15777 | |
88714cb8 | 15778 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
15779 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
15780 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15781 | inst.instruction |= LOW4 (dm); | |
15782 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 15783 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
15784 | inst.instruction |= x << 17; |
15785 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 15786 | |
88714cb8 | 15787 | neon_dp_fixup (&inst); |
5287ad62 JB |
15788 | } |
15789 | else | |
15790 | { | |
037e8744 JB |
15791 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
15792 | struct neon_type_el et = neon_check_type (2, rs, | |
477330fc | 15793 | N_8 | N_16 | N_32 | N_KEY, N_EQK); |
5287ad62 | 15794 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 15795 | NEON_ENCODE (ARMREG, inst); |
5287ad62 | 15796 | switch (et.size) |
477330fc RM |
15797 | { |
15798 | case 8: inst.instruction |= 0x400000; break; | |
15799 | case 16: inst.instruction |= 0x000020; break; | |
15800 | case 32: inst.instruction |= 0x000000; break; | |
15801 | default: break; | |
15802 | } | |
5287ad62 JB |
15803 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; |
15804 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
15805 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 15806 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 | 15807 | /* The encoding for this instruction is identical for the ARM and Thumb |
477330fc | 15808 | variants, except for the condition field. */ |
037e8744 | 15809 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15810 | } |
15811 | } | |
15812 | ||
15813 | /* VMOV has particularly many variations. It can be one of: | |
15814 | 0. VMOV<c><q> <Qd>, <Qm> | |
15815 | 1. VMOV<c><q> <Dd>, <Dm> | |
15816 | (Register operations, which are VORR with Rm = Rn.) | |
15817 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
15818 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
15819 | (Immediate loads.) | |
15820 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
15821 | (ARM register to scalar.) | |
15822 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
15823 | (Two ARM registers to vector.) | |
15824 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
15825 | (Scalar to ARM register.) | |
15826 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
15827 | (Vector to two ARM registers.) | |
037e8744 JB |
15828 | 8. VMOV.F32 <Sd>, <Sm> |
15829 | 9. VMOV.F64 <Dd>, <Dm> | |
15830 | (VFP register moves.) | |
15831 | 10. VMOV.F32 <Sd>, #imm | |
15832 | 11. VMOV.F64 <Dd>, #imm | |
15833 | (VFP float immediate load.) | |
15834 | 12. VMOV <Rd>, <Sm> | |
15835 | (VFP single to ARM reg.) | |
15836 | 13. VMOV <Sd>, <Rm> | |
15837 | (ARM reg to VFP single.) | |
15838 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
15839 | (Two ARM regs to two VFP singles.) | |
15840 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
15841 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 15842 | |
037e8744 JB |
15843 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
15844 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 15845 | |
5287ad62 | 15846 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 15847 | |
b7fc2769 JB |
15848 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
15849 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 15850 | |
5287ad62 | 15851 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 15852 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
15853 | |
15854 | static void | |
15855 | do_neon_mov (void) | |
15856 | { | |
037e8744 JB |
15857 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
15858 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
15859 | NS_NULL); | |
15860 | struct neon_type_el et; | |
15861 | const char *ldconst = 0; | |
5287ad62 | 15862 | |
037e8744 | 15863 | switch (rs) |
5287ad62 | 15864 | { |
037e8744 JB |
15865 | case NS_DD: /* case 1/9. */ |
15866 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15867 | /* It is not an error here if no type is given. */ | |
15868 | inst.error = NULL; | |
15869 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15870 | { |
15871 | do_vfp_nsyn_opcode ("fcpyd"); | |
15872 | break; | |
15873 | } | |
037e8744 | 15874 | /* fall through. */ |
5287ad62 | 15875 | |
037e8744 JB |
15876 | case NS_QQ: /* case 0/1. */ |
15877 | { | |
477330fc RM |
15878 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
15879 | return; | |
15880 | /* The architecture manual I have doesn't explicitly state which | |
15881 | value the U bit should have for register->register moves, but | |
15882 | the equivalent VORR instruction has U = 0, so do that. */ | |
15883 | inst.instruction = 0x0200110; | |
15884 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15885 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15886 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15887 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15888 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15889 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15890 | inst.instruction |= neon_quad (rs) << 6; | |
15891 | ||
15892 | neon_dp_fixup (&inst); | |
037e8744 JB |
15893 | } |
15894 | break; | |
5f4273c7 | 15895 | |
037e8744 JB |
15896 | case NS_DI: /* case 3/11. */ |
15897 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15898 | inst.error = NULL; | |
15899 | if (et.type == NT_float && et.size == 64) | |
477330fc RM |
15900 | { |
15901 | /* case 11 (fconstd). */ | |
15902 | ldconst = "fconstd"; | |
15903 | goto encode_fconstd; | |
15904 | } | |
037e8744 JB |
15905 | /* fall through. */ |
15906 | ||
15907 | case NS_QI: /* case 2/3. */ | |
15908 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
477330fc | 15909 | return; |
037e8744 JB |
15910 | inst.instruction = 0x0800010; |
15911 | neon_move_immediate (); | |
88714cb8 | 15912 | neon_dp_fixup (&inst); |
5287ad62 | 15913 | break; |
5f4273c7 | 15914 | |
037e8744 JB |
15915 | case NS_SR: /* case 4. */ |
15916 | { | |
477330fc RM |
15917 | unsigned bcdebits = 0; |
15918 | int logsize; | |
15919 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); | |
15920 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
037e8744 | 15921 | |
05ac0ffb JB |
15922 | /* .<size> is optional here, defaulting to .32. */ |
15923 | if (inst.vectype.elems == 0 | |
15924 | && inst.operands[0].vectype.type == NT_invtype | |
15925 | && inst.operands[1].vectype.type == NT_invtype) | |
15926 | { | |
15927 | inst.vectype.el[0].type = NT_untyped; | |
15928 | inst.vectype.el[0].size = 32; | |
15929 | inst.vectype.elems = 1; | |
15930 | } | |
15931 | ||
477330fc RM |
15932 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
15933 | logsize = neon_logbits (et.size); | |
15934 | ||
15935 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15936 | _(BAD_FPU)); | |
15937 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15938 | && et.size != 32, _(BAD_FPU)); | |
15939 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15940 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15941 | ||
15942 | switch (et.size) | |
15943 | { | |
15944 | case 8: bcdebits = 0x8; break; | |
15945 | case 16: bcdebits = 0x1; break; | |
15946 | case 32: bcdebits = 0x0; break; | |
15947 | default: ; | |
15948 | } | |
15949 | ||
15950 | bcdebits |= x << logsize; | |
15951 | ||
15952 | inst.instruction = 0xe000b10; | |
15953 | do_vfp_cond_or_thumb (); | |
15954 | inst.instruction |= LOW4 (dn) << 16; | |
15955 | inst.instruction |= HI1 (dn) << 7; | |
15956 | inst.instruction |= inst.operands[1].reg << 12; | |
15957 | inst.instruction |= (bcdebits & 3) << 5; | |
15958 | inst.instruction |= (bcdebits >> 2) << 21; | |
037e8744 JB |
15959 | } |
15960 | break; | |
5f4273c7 | 15961 | |
037e8744 | 15962 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 15963 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
477330fc | 15964 | _(BAD_FPU)); |
b7fc2769 | 15965 | |
037e8744 JB |
15966 | inst.instruction = 0xc400b10; |
15967 | do_vfp_cond_or_thumb (); | |
15968 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
15969 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
15970 | inst.instruction |= inst.operands[1].reg << 12; | |
15971 | inst.instruction |= inst.operands[2].reg << 16; | |
15972 | break; | |
5f4273c7 | 15973 | |
037e8744 JB |
15974 | case NS_RS: /* case 6. */ |
15975 | { | |
477330fc RM |
15976 | unsigned logsize; |
15977 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); | |
15978 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
15979 | unsigned abcdebits = 0; | |
037e8744 | 15980 | |
05ac0ffb JB |
15981 | /* .<dt> is optional here, defaulting to .32. */ |
15982 | if (inst.vectype.elems == 0 | |
15983 | && inst.operands[0].vectype.type == NT_invtype | |
15984 | && inst.operands[1].vectype.type == NT_invtype) | |
15985 | { | |
15986 | inst.vectype.el[0].type = NT_untyped; | |
15987 | inst.vectype.el[0].size = 32; | |
15988 | inst.vectype.elems = 1; | |
15989 | } | |
15990 | ||
91d6fa6a NC |
15991 | et = neon_check_type (2, NS_NULL, |
15992 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
477330fc RM |
15993 | logsize = neon_logbits (et.size); |
15994 | ||
15995 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), | |
15996 | _(BAD_FPU)); | |
15997 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15998 | && et.size != 32, _(BAD_FPU)); | |
15999 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
16000 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
16001 | ||
16002 | switch (et.size) | |
16003 | { | |
16004 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
16005 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
16006 | case 32: abcdebits = 0x00; break; | |
16007 | default: ; | |
16008 | } | |
16009 | ||
16010 | abcdebits |= x << logsize; | |
16011 | inst.instruction = 0xe100b10; | |
16012 | do_vfp_cond_or_thumb (); | |
16013 | inst.instruction |= LOW4 (dn) << 16; | |
16014 | inst.instruction |= HI1 (dn) << 7; | |
16015 | inst.instruction |= inst.operands[0].reg << 12; | |
16016 | inst.instruction |= (abcdebits & 3) << 5; | |
16017 | inst.instruction |= (abcdebits >> 2) << 21; | |
037e8744 JB |
16018 | } |
16019 | break; | |
5f4273c7 | 16020 | |
037e8744 JB |
16021 | case NS_RRD: /* case 7 (fmrrd). */ |
16022 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
477330fc | 16023 | _(BAD_FPU)); |
037e8744 JB |
16024 | |
16025 | inst.instruction = 0xc500b10; | |
16026 | do_vfp_cond_or_thumb (); | |
16027 | inst.instruction |= inst.operands[0].reg << 12; | |
16028 | inst.instruction |= inst.operands[1].reg << 16; | |
16029 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16030 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16031 | break; | |
5f4273c7 | 16032 | |
037e8744 JB |
16033 | case NS_FF: /* case 8 (fcpys). */ |
16034 | do_vfp_nsyn_opcode ("fcpys"); | |
16035 | break; | |
5f4273c7 | 16036 | |
037e8744 JB |
16037 | case NS_FI: /* case 10 (fconsts). */ |
16038 | ldconst = "fconsts"; | |
16039 | encode_fconstd: | |
16040 | if (is_quarter_float (inst.operands[1].imm)) | |
477330fc RM |
16041 | { |
16042 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); | |
16043 | do_vfp_nsyn_opcode (ldconst); | |
16044 | } | |
5287ad62 | 16045 | else |
477330fc | 16046 | first_error (_("immediate out of range")); |
037e8744 | 16047 | break; |
5f4273c7 | 16048 | |
037e8744 JB |
16049 | case NS_RF: /* case 12 (fmrs). */ |
16050 | do_vfp_nsyn_opcode ("fmrs"); | |
16051 | break; | |
5f4273c7 | 16052 | |
037e8744 JB |
16053 | case NS_FR: /* case 13 (fmsr). */ |
16054 | do_vfp_nsyn_opcode ("fmsr"); | |
16055 | break; | |
5f4273c7 | 16056 | |
037e8744 JB |
16057 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
16058 | (one of which is a list), but we have parsed four. Do some fiddling to | |
16059 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
16060 | expect. */ | |
16061 | case NS_RRFF: /* case 14 (fmrrs). */ | |
16062 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
477330fc | 16063 | _("VFP registers must be adjacent")); |
037e8744 JB |
16064 | inst.operands[2].imm = 2; |
16065 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
16066 | do_vfp_nsyn_opcode ("fmrrs"); | |
16067 | break; | |
5f4273c7 | 16068 | |
037e8744 JB |
16069 | case NS_FFRR: /* case 15 (fmsrr). */ |
16070 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
477330fc | 16071 | _("VFP registers must be adjacent")); |
037e8744 JB |
16072 | inst.operands[1] = inst.operands[2]; |
16073 | inst.operands[2] = inst.operands[3]; | |
16074 | inst.operands[0].imm = 2; | |
16075 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
16076 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 16077 | break; |
5f4273c7 | 16078 | |
4c261dff NC |
16079 | case NS_NULL: |
16080 | /* neon_select_shape has determined that the instruction | |
16081 | shape is wrong and has already set the error message. */ | |
16082 | break; | |
16083 | ||
5287ad62 JB |
16084 | default: |
16085 | abort (); | |
16086 | } | |
16087 | } | |
16088 | ||
16089 | static void | |
16090 | do_neon_rshift_round_imm (void) | |
16091 | { | |
037e8744 | 16092 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
16093 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
16094 | int imm = inst.operands[2].imm; | |
16095 | ||
16096 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
16097 | if (imm == 0) | |
16098 | { | |
16099 | inst.operands[2].present = 0; | |
16100 | do_neon_mov (); | |
16101 | return; | |
16102 | } | |
16103 | ||
16104 | constraint (imm < 1 || (unsigned)imm > et.size, | |
477330fc | 16105 | _("immediate out of range for shift")); |
037e8744 | 16106 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
477330fc | 16107 | et.size - imm); |
5287ad62 JB |
16108 | } |
16109 | ||
16110 | static void | |
16111 | do_neon_movl (void) | |
16112 | { | |
16113 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
16114 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
16115 | unsigned sizebits = et.size >> 3; | |
16116 | inst.instruction |= sizebits << 19; | |
16117 | neon_two_same (0, et.type == NT_unsigned, -1); | |
16118 | } | |
16119 | ||
16120 | static void | |
16121 | do_neon_trn (void) | |
16122 | { | |
037e8744 | 16123 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16124 | struct neon_type_el et = neon_check_type (2, rs, |
16125 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 16126 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 16127 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16128 | } |
16129 | ||
16130 | static void | |
16131 | do_neon_zip_uzp (void) | |
16132 | { | |
037e8744 | 16133 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16134 | struct neon_type_el et = neon_check_type (2, rs, |
16135 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
16136 | if (rs == NS_DD && et.size == 32) | |
16137 | { | |
16138 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
16139 | inst.instruction = N_MNEM_vtrn; | |
16140 | do_neon_trn (); | |
16141 | return; | |
16142 | } | |
037e8744 | 16143 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16144 | } |
16145 | ||
16146 | static void | |
16147 | do_neon_sat_abs_neg (void) | |
16148 | { | |
037e8744 | 16149 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16150 | struct neon_type_el et = neon_check_type (2, rs, |
16151 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16152 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16153 | } |
16154 | ||
16155 | static void | |
16156 | do_neon_pair_long (void) | |
16157 | { | |
037e8744 | 16158 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16159 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
16160 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
16161 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 16162 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16163 | } |
16164 | ||
16165 | static void | |
16166 | do_neon_recip_est (void) | |
16167 | { | |
037e8744 | 16168 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16169 | struct neon_type_el et = neon_check_type (2, rs, |
16170 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
16171 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 16172 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16173 | } |
16174 | ||
16175 | static void | |
16176 | do_neon_cls (void) | |
16177 | { | |
037e8744 | 16178 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16179 | struct neon_type_el et = neon_check_type (2, rs, |
16180 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 16181 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16182 | } |
16183 | ||
16184 | static void | |
16185 | do_neon_clz (void) | |
16186 | { | |
037e8744 | 16187 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16188 | struct neon_type_el et = neon_check_type (2, rs, |
16189 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 16190 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16191 | } |
16192 | ||
16193 | static void | |
16194 | do_neon_cnt (void) | |
16195 | { | |
037e8744 | 16196 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
16197 | struct neon_type_el et = neon_check_type (2, rs, |
16198 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 16199 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
16200 | } |
16201 | ||
16202 | static void | |
16203 | do_neon_swp (void) | |
16204 | { | |
037e8744 JB |
16205 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
16206 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
16207 | } |
16208 | ||
16209 | static void | |
16210 | do_neon_tbl_tbx (void) | |
16211 | { | |
16212 | unsigned listlenbits; | |
dcbf9037 | 16213 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 16214 | |
5287ad62 JB |
16215 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
16216 | { | |
dcbf9037 | 16217 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
16218 | return; |
16219 | } | |
5f4273c7 | 16220 | |
5287ad62 JB |
16221 | listlenbits = inst.operands[1].imm - 1; |
16222 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16223 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16224 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
16225 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
16226 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
16227 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
16228 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 16229 | |
88714cb8 | 16230 | neon_dp_fixup (&inst); |
5287ad62 JB |
16231 | } |
16232 | ||
16233 | static void | |
16234 | do_neon_ldm_stm (void) | |
16235 | { | |
16236 | /* P, U and L bits are part of bitmask. */ | |
16237 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
16238 | unsigned offsetbits = inst.operands[1].imm * 2; | |
16239 | ||
037e8744 JB |
16240 | if (inst.operands[1].issingle) |
16241 | { | |
16242 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
16243 | return; | |
16244 | } | |
16245 | ||
5287ad62 | 16246 | constraint (is_dbmode && !inst.operands[0].writeback, |
477330fc | 16247 | _("writeback (!) must be used for VLDMDB and VSTMDB")); |
5287ad62 JB |
16248 | |
16249 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
477330fc RM |
16250 | _("register list must contain at least 1 and at most 16 " |
16251 | "registers")); | |
5287ad62 JB |
16252 | |
16253 | inst.instruction |= inst.operands[0].reg << 16; | |
16254 | inst.instruction |= inst.operands[0].writeback << 21; | |
16255 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
16256 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
16257 | ||
16258 | inst.instruction |= offsetbits; | |
5f4273c7 | 16259 | |
037e8744 | 16260 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
16261 | } |
16262 | ||
16263 | static void | |
16264 | do_neon_ldr_str (void) | |
16265 | { | |
5287ad62 | 16266 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 16267 | |
6844b2c2 MGD |
16268 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
16269 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 16270 | if (!is_ldr |
6844b2c2 | 16271 | && inst.operands[1].reg == REG_PC |
ba86b375 | 16272 | && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode)) |
6844b2c2 | 16273 | { |
94dcf8bf | 16274 | if (thumb_mode) |
6844b2c2 | 16275 | inst.error = _("Use of PC here is UNPREDICTABLE"); |
94dcf8bf | 16276 | else if (warn_on_deprecated) |
5c3696f8 | 16277 | as_tsktsk (_("Use of PC here is deprecated")); |
6844b2c2 MGD |
16278 | } |
16279 | ||
037e8744 JB |
16280 | if (inst.operands[0].issingle) |
16281 | { | |
cd2f129f | 16282 | if (is_ldr) |
477330fc | 16283 | do_vfp_nsyn_opcode ("flds"); |
cd2f129f | 16284 | else |
477330fc | 16285 | do_vfp_nsyn_opcode ("fsts"); |
5287ad62 JB |
16286 | } |
16287 | else | |
5287ad62 | 16288 | { |
cd2f129f | 16289 | if (is_ldr) |
477330fc | 16290 | do_vfp_nsyn_opcode ("fldd"); |
5287ad62 | 16291 | else |
477330fc | 16292 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 16293 | } |
5287ad62 JB |
16294 | } |
16295 | ||
16296 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
16297 | instructions. */ | |
16298 | ||
16299 | static void | |
16300 | do_neon_ld_st_interleave (void) | |
16301 | { | |
037e8744 | 16302 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
477330fc | 16303 | N_8 | N_16 | N_32 | N_64); |
5287ad62 JB |
16304 | unsigned alignbits = 0; |
16305 | unsigned idx; | |
16306 | /* The bits in this table go: | |
16307 | 0: register stride of one (0) or two (1) | |
16308 | 1,2: register list length, minus one (1, 2, 3, 4). | |
16309 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
16310 | We use -1 for invalid entries. */ | |
16311 | const int typetable[] = | |
16312 | { | |
16313 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
16314 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
16315 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
16316 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
16317 | }; | |
16318 | int typebits; | |
16319 | ||
dcbf9037 JB |
16320 | if (et.type == NT_invtype) |
16321 | return; | |
16322 | ||
5287ad62 JB |
16323 | if (inst.operands[1].immisalign) |
16324 | switch (inst.operands[1].imm >> 8) | |
16325 | { | |
16326 | case 64: alignbits = 1; break; | |
16327 | case 128: | |
477330fc | 16328 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
e23c0ad8 | 16329 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
477330fc RM |
16330 | goto bad_alignment; |
16331 | alignbits = 2; | |
16332 | break; | |
5287ad62 | 16333 | case 256: |
477330fc RM |
16334 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
16335 | goto bad_alignment; | |
16336 | alignbits = 3; | |
16337 | break; | |
5287ad62 JB |
16338 | default: |
16339 | bad_alignment: | |
477330fc RM |
16340 | first_error (_("bad alignment")); |
16341 | return; | |
5287ad62 JB |
16342 | } |
16343 | ||
16344 | inst.instruction |= alignbits << 4; | |
16345 | inst.instruction |= neon_logbits (et.size) << 6; | |
16346 | ||
16347 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
16348 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
16349 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
16350 | up the right value for "type" in a table based on this value and the given | |
16351 | list style, then stick it back. */ | |
16352 | idx = ((inst.operands[0].imm >> 4) & 7) | |
477330fc | 16353 | | (((inst.instruction >> 8) & 3) << 3); |
5287ad62 JB |
16354 | |
16355 | typebits = typetable[idx]; | |
5f4273c7 | 16356 | |
5287ad62 | 16357 | constraint (typebits == -1, _("bad list type for instruction")); |
1d50d57c WN |
16358 | constraint (((inst.instruction >> 8) & 3) && et.size == 64, |
16359 | _("bad element type for instruction")); | |
5287ad62 JB |
16360 | |
16361 | inst.instruction &= ~0xf00; | |
16362 | inst.instruction |= typebits << 8; | |
16363 | } | |
16364 | ||
16365 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
16366 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
16367 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
16368 | values, terminated with -1. */ | |
16369 | ||
16370 | static int | |
16371 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
16372 | { | |
16373 | va_list ap; | |
16374 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 16375 | |
5287ad62 JB |
16376 | if (!inst.operands[1].immisalign) |
16377 | { | |
16378 | *do_align = 0; | |
16379 | return SUCCESS; | |
16380 | } | |
5f4273c7 | 16381 | |
5287ad62 JB |
16382 | va_start (ap, do_align); |
16383 | ||
16384 | do | |
16385 | { | |
16386 | thissize = va_arg (ap, int); | |
16387 | if (thissize == -1) | |
477330fc | 16388 | break; |
5287ad62 JB |
16389 | thisalign = va_arg (ap, int); |
16390 | ||
16391 | if (size == thissize && align == thisalign) | |
477330fc | 16392 | result = SUCCESS; |
5287ad62 JB |
16393 | } |
16394 | while (result != SUCCESS); | |
16395 | ||
16396 | va_end (ap); | |
16397 | ||
16398 | if (result == SUCCESS) | |
16399 | *do_align = 1; | |
16400 | else | |
dcbf9037 | 16401 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 16402 | |
5287ad62 JB |
16403 | return result; |
16404 | } | |
16405 | ||
16406 | static void | |
16407 | do_neon_ld_st_lane (void) | |
16408 | { | |
037e8744 | 16409 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16410 | int align_good, do_align = 0; |
16411 | int logsize = neon_logbits (et.size); | |
16412 | int align = inst.operands[1].imm >> 8; | |
16413 | int n = (inst.instruction >> 8) & 3; | |
16414 | int max_el = 64 / et.size; | |
5f4273c7 | 16415 | |
dcbf9037 JB |
16416 | if (et.type == NT_invtype) |
16417 | return; | |
5f4273c7 | 16418 | |
5287ad62 | 16419 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
477330fc | 16420 | _("bad list length")); |
5287ad62 | 16421 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, |
477330fc | 16422 | _("scalar index out of range")); |
5287ad62 | 16423 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 |
477330fc RM |
16424 | && et.size == 8, |
16425 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 16426 | |
5287ad62 JB |
16427 | switch (n) |
16428 | { | |
16429 | case 0: /* VLD1 / VST1. */ | |
16430 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
477330fc | 16431 | 32, 32, -1); |
5287ad62 | 16432 | if (align_good == FAIL) |
477330fc | 16433 | return; |
5287ad62 | 16434 | if (do_align) |
477330fc RM |
16435 | { |
16436 | unsigned alignbits = 0; | |
16437 | switch (et.size) | |
16438 | { | |
16439 | case 16: alignbits = 0x1; break; | |
16440 | case 32: alignbits = 0x3; break; | |
16441 | default: ; | |
16442 | } | |
16443 | inst.instruction |= alignbits << 4; | |
16444 | } | |
5287ad62 JB |
16445 | break; |
16446 | ||
16447 | case 1: /* VLD2 / VST2. */ | |
16448 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
477330fc | 16449 | 32, 64, -1); |
5287ad62 | 16450 | if (align_good == FAIL) |
477330fc | 16451 | return; |
5287ad62 | 16452 | if (do_align) |
477330fc | 16453 | inst.instruction |= 1 << 4; |
5287ad62 JB |
16454 | break; |
16455 | ||
16456 | case 2: /* VLD3 / VST3. */ | |
16457 | constraint (inst.operands[1].immisalign, | |
477330fc | 16458 | _("can't use alignment with this instruction")); |
5287ad62 JB |
16459 | break; |
16460 | ||
16461 | case 3: /* VLD4 / VST4. */ | |
16462 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
477330fc | 16463 | 16, 64, 32, 64, 32, 128, -1); |
5287ad62 | 16464 | if (align_good == FAIL) |
477330fc | 16465 | return; |
5287ad62 | 16466 | if (do_align) |
477330fc RM |
16467 | { |
16468 | unsigned alignbits = 0; | |
16469 | switch (et.size) | |
16470 | { | |
16471 | case 8: alignbits = 0x1; break; | |
16472 | case 16: alignbits = 0x1; break; | |
16473 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
16474 | default: ; | |
16475 | } | |
16476 | inst.instruction |= alignbits << 4; | |
16477 | } | |
5287ad62 JB |
16478 | break; |
16479 | ||
16480 | default: ; | |
16481 | } | |
16482 | ||
16483 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
16484 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16485 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 16486 | |
5287ad62 JB |
16487 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
16488 | inst.instruction |= logsize << 10; | |
16489 | } | |
16490 | ||
16491 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
16492 | ||
16493 | static void | |
16494 | do_neon_ld_dup (void) | |
16495 | { | |
037e8744 | 16496 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
16497 | int align_good, do_align = 0; |
16498 | ||
dcbf9037 JB |
16499 | if (et.type == NT_invtype) |
16500 | return; | |
16501 | ||
5287ad62 JB |
16502 | switch ((inst.instruction >> 8) & 3) |
16503 | { | |
16504 | case 0: /* VLD1. */ | |
9c2799c2 | 16505 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 | 16506 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
477330fc | 16507 | &do_align, 16, 16, 32, 32, -1); |
5287ad62 | 16508 | if (align_good == FAIL) |
477330fc | 16509 | return; |
5287ad62 | 16510 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) |
477330fc RM |
16511 | { |
16512 | case 1: break; | |
16513 | case 2: inst.instruction |= 1 << 5; break; | |
16514 | default: first_error (_("bad list length")); return; | |
16515 | } | |
5287ad62 JB |
16516 | inst.instruction |= neon_logbits (et.size) << 6; |
16517 | break; | |
16518 | ||
16519 | case 1: /* VLD2. */ | |
16520 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
477330fc | 16521 | &do_align, 8, 16, 16, 32, 32, 64, -1); |
5287ad62 | 16522 | if (align_good == FAIL) |
477330fc | 16523 | return; |
5287ad62 | 16524 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, |
477330fc | 16525 | _("bad list length")); |
5287ad62 | 16526 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16527 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16528 | inst.instruction |= neon_logbits (et.size) << 6; |
16529 | break; | |
16530 | ||
16531 | case 2: /* VLD3. */ | |
16532 | constraint (inst.operands[1].immisalign, | |
477330fc | 16533 | _("can't use alignment with this instruction")); |
5287ad62 | 16534 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, |
477330fc | 16535 | _("bad list length")); |
5287ad62 | 16536 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) |
477330fc | 16537 | inst.instruction |= 1 << 5; |
5287ad62 JB |
16538 | inst.instruction |= neon_logbits (et.size) << 6; |
16539 | break; | |
16540 | ||
16541 | case 3: /* VLD4. */ | |
16542 | { | |
477330fc RM |
16543 | int align = inst.operands[1].imm >> 8; |
16544 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
16545 | 16, 64, 32, 64, 32, 128, -1); | |
16546 | if (align_good == FAIL) | |
16547 | return; | |
16548 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
16549 | _("bad list length")); | |
16550 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
16551 | inst.instruction |= 1 << 5; | |
16552 | if (et.size == 32 && align == 128) | |
16553 | inst.instruction |= 0x3 << 6; | |
16554 | else | |
16555 | inst.instruction |= neon_logbits (et.size) << 6; | |
5287ad62 JB |
16556 | } |
16557 | break; | |
16558 | ||
16559 | default: ; | |
16560 | } | |
16561 | ||
16562 | inst.instruction |= do_align << 4; | |
16563 | } | |
16564 | ||
16565 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
16566 | apart from bits [11:4]. */ | |
16567 | ||
16568 | static void | |
16569 | do_neon_ldx_stx (void) | |
16570 | { | |
b1a769ed DG |
16571 | if (inst.operands[1].isreg) |
16572 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
16573 | ||
5287ad62 JB |
16574 | switch (NEON_LANE (inst.operands[0].imm)) |
16575 | { | |
16576 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 16577 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
16578 | do_neon_ld_st_interleave (); |
16579 | break; | |
5f4273c7 | 16580 | |
5287ad62 | 16581 | case NEON_ALL_LANES: |
88714cb8 | 16582 | NEON_ENCODE (DUP, inst); |
2d51fb74 JB |
16583 | if (inst.instruction == N_INV) |
16584 | { | |
16585 | first_error ("only loads support such operands"); | |
16586 | break; | |
16587 | } | |
5287ad62 JB |
16588 | do_neon_ld_dup (); |
16589 | break; | |
5f4273c7 | 16590 | |
5287ad62 | 16591 | default: |
88714cb8 | 16592 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
16593 | do_neon_ld_st_lane (); |
16594 | } | |
16595 | ||
16596 | /* L bit comes from bit mask. */ | |
16597 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16598 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16599 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 16600 | |
5287ad62 JB |
16601 | if (inst.operands[1].postind) |
16602 | { | |
16603 | int postreg = inst.operands[1].imm & 0xf; | |
16604 | constraint (!inst.operands[1].immisreg, | |
477330fc | 16605 | _("post-index must be a register")); |
5287ad62 | 16606 | constraint (postreg == 0xd || postreg == 0xf, |
477330fc | 16607 | _("bad register for post-index")); |
5287ad62 JB |
16608 | inst.instruction |= postreg; |
16609 | } | |
4f2374c7 | 16610 | else |
5287ad62 | 16611 | { |
4f2374c7 WN |
16612 | constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); |
16613 | constraint (inst.reloc.exp.X_op != O_constant | |
16614 | || inst.reloc.exp.X_add_number != 0, | |
16615 | BAD_ADDR_MODE); | |
16616 | ||
16617 | if (inst.operands[1].writeback) | |
16618 | { | |
16619 | inst.instruction |= 0xd; | |
16620 | } | |
16621 | else | |
16622 | inst.instruction |= 0xf; | |
5287ad62 | 16623 | } |
5f4273c7 | 16624 | |
5287ad62 JB |
16625 | if (thumb_mode) |
16626 | inst.instruction |= 0xf9000000; | |
16627 | else | |
16628 | inst.instruction |= 0xf4000000; | |
16629 | } | |
33399f07 MGD |
16630 | |
16631 | /* FP v8. */ | |
16632 | static void | |
16633 | do_vfp_nsyn_fpv8 (enum neon_shape rs) | |
16634 | { | |
a715796b TG |
16635 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
16636 | D register operands. */ | |
16637 | if (neon_shape_class[rs] == SC_DOUBLE) | |
16638 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16639 | _(BAD_FPU)); | |
16640 | ||
33399f07 MGD |
16641 | NEON_ENCODE (FPV8, inst); |
16642 | ||
16643 | if (rs == NS_FFF) | |
16644 | do_vfp_sp_dyadic (); | |
16645 | else | |
16646 | do_vfp_dp_rd_rn_rm (); | |
16647 | ||
16648 | if (rs == NS_DDD) | |
16649 | inst.instruction |= 0x100; | |
16650 | ||
16651 | inst.instruction |= 0xf0000000; | |
16652 | } | |
16653 | ||
16654 | static void | |
16655 | do_vsel (void) | |
16656 | { | |
16657 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16658 | ||
16659 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) | |
16660 | first_error (_("invalid instruction shape")); | |
16661 | } | |
16662 | ||
73924fbc MGD |
16663 | static void |
16664 | do_vmaxnm (void) | |
16665 | { | |
16666 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16667 | ||
16668 | if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) | |
16669 | return; | |
16670 | ||
16671 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16672 | return; | |
16673 | ||
16674 | neon_dyadic_misc (NT_untyped, N_F32, 0); | |
16675 | } | |
16676 | ||
30bdf752 MGD |
16677 | static void |
16678 | do_vrint_1 (enum neon_cvt_mode mode) | |
16679 | { | |
16680 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL); | |
16681 | struct neon_type_el et; | |
16682 | ||
16683 | if (rs == NS_NULL) | |
16684 | return; | |
16685 | ||
a715796b TG |
16686 | /* Targets like FPv5-SP-D16 don't support FP v8 instructions with |
16687 | D register operands. */ | |
16688 | if (neon_shape_class[rs] == SC_DOUBLE) | |
16689 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), | |
16690 | _(BAD_FPU)); | |
16691 | ||
30bdf752 MGD |
16692 | et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); |
16693 | if (et.type != NT_invtype) | |
16694 | { | |
16695 | /* VFP encodings. */ | |
16696 | if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n | |
16697 | || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m) | |
16698 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16699 | ||
16700 | NEON_ENCODE (FPV8, inst); | |
16701 | if (rs == NS_FF) | |
16702 | do_vfp_sp_monadic (); | |
16703 | else | |
16704 | do_vfp_dp_rd_rm (); | |
16705 | ||
16706 | switch (mode) | |
16707 | { | |
16708 | case neon_cvt_mode_r: inst.instruction |= 0x00000000; break; | |
16709 | case neon_cvt_mode_z: inst.instruction |= 0x00000080; break; | |
16710 | case neon_cvt_mode_x: inst.instruction |= 0x00010000; break; | |
16711 | case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break; | |
16712 | case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break; | |
16713 | case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break; | |
16714 | case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break; | |
16715 | default: abort (); | |
16716 | } | |
16717 | ||
16718 | inst.instruction |= (rs == NS_DD) << 8; | |
16719 | do_vfp_cond_or_thumb (); | |
16720 | } | |
16721 | else | |
16722 | { | |
16723 | /* Neon encodings (or something broken...). */ | |
16724 | inst.error = NULL; | |
16725 | et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY); | |
16726 | ||
16727 | if (et.type == NT_invtype) | |
16728 | return; | |
16729 | ||
16730 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16731 | NEON_ENCODE (FLOAT, inst); | |
16732 | ||
16733 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) | |
16734 | return; | |
16735 | ||
16736 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16737 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16738 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16739 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16740 | inst.instruction |= neon_quad (rs) << 6; | |
16741 | switch (mode) | |
16742 | { | |
16743 | case neon_cvt_mode_z: inst.instruction |= 3 << 7; break; | |
16744 | case neon_cvt_mode_x: inst.instruction |= 1 << 7; break; | |
16745 | case neon_cvt_mode_a: inst.instruction |= 2 << 7; break; | |
16746 | case neon_cvt_mode_n: inst.instruction |= 0 << 7; break; | |
16747 | case neon_cvt_mode_p: inst.instruction |= 7 << 7; break; | |
16748 | case neon_cvt_mode_m: inst.instruction |= 5 << 7; break; | |
16749 | case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break; | |
16750 | default: abort (); | |
16751 | } | |
16752 | ||
16753 | if (thumb_mode) | |
16754 | inst.instruction |= 0xfc000000; | |
16755 | else | |
16756 | inst.instruction |= 0xf0000000; | |
16757 | } | |
16758 | } | |
16759 | ||
16760 | static void | |
16761 | do_vrintx (void) | |
16762 | { | |
16763 | do_vrint_1 (neon_cvt_mode_x); | |
16764 | } | |
16765 | ||
16766 | static void | |
16767 | do_vrintz (void) | |
16768 | { | |
16769 | do_vrint_1 (neon_cvt_mode_z); | |
16770 | } | |
16771 | ||
16772 | static void | |
16773 | do_vrintr (void) | |
16774 | { | |
16775 | do_vrint_1 (neon_cvt_mode_r); | |
16776 | } | |
16777 | ||
16778 | static void | |
16779 | do_vrinta (void) | |
16780 | { | |
16781 | do_vrint_1 (neon_cvt_mode_a); | |
16782 | } | |
16783 | ||
16784 | static void | |
16785 | do_vrintn (void) | |
16786 | { | |
16787 | do_vrint_1 (neon_cvt_mode_n); | |
16788 | } | |
16789 | ||
16790 | static void | |
16791 | do_vrintp (void) | |
16792 | { | |
16793 | do_vrint_1 (neon_cvt_mode_p); | |
16794 | } | |
16795 | ||
16796 | static void | |
16797 | do_vrintm (void) | |
16798 | { | |
16799 | do_vrint_1 (neon_cvt_mode_m); | |
16800 | } | |
16801 | ||
91ff7894 MGD |
16802 | /* Crypto v1 instructions. */ |
16803 | static void | |
16804 | do_crypto_2op_1 (unsigned elttype, int op) | |
16805 | { | |
16806 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16807 | ||
16808 | if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type | |
16809 | == NT_invtype) | |
16810 | return; | |
16811 | ||
16812 | inst.error = NULL; | |
16813 | ||
16814 | NEON_ENCODE (INTEGER, inst); | |
16815 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
16816 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
16817 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
16818 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
16819 | if (op != -1) | |
16820 | inst.instruction |= op << 6; | |
16821 | ||
16822 | if (thumb_mode) | |
16823 | inst.instruction |= 0xfc000000; | |
16824 | else | |
16825 | inst.instruction |= 0xf0000000; | |
16826 | } | |
16827 | ||
48adcd8e MGD |
16828 | static void |
16829 | do_crypto_3op_1 (int u, int op) | |
16830 | { | |
16831 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16832 | ||
16833 | if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT, | |
16834 | N_32 | N_UNT | N_KEY).type == NT_invtype) | |
16835 | return; | |
16836 | ||
16837 | inst.error = NULL; | |
16838 | ||
16839 | NEON_ENCODE (INTEGER, inst); | |
16840 | neon_three_same (1, u, 8 << op); | |
16841 | } | |
16842 | ||
91ff7894 MGD |
16843 | static void |
16844 | do_aese (void) | |
16845 | { | |
16846 | do_crypto_2op_1 (N_8, 0); | |
16847 | } | |
16848 | ||
16849 | static void | |
16850 | do_aesd (void) | |
16851 | { | |
16852 | do_crypto_2op_1 (N_8, 1); | |
16853 | } | |
16854 | ||
16855 | static void | |
16856 | do_aesmc (void) | |
16857 | { | |
16858 | do_crypto_2op_1 (N_8, 2); | |
16859 | } | |
16860 | ||
16861 | static void | |
16862 | do_aesimc (void) | |
16863 | { | |
16864 | do_crypto_2op_1 (N_8, 3); | |
16865 | } | |
16866 | ||
48adcd8e MGD |
16867 | static void |
16868 | do_sha1c (void) | |
16869 | { | |
16870 | do_crypto_3op_1 (0, 0); | |
16871 | } | |
16872 | ||
16873 | static void | |
16874 | do_sha1p (void) | |
16875 | { | |
16876 | do_crypto_3op_1 (0, 1); | |
16877 | } | |
16878 | ||
16879 | static void | |
16880 | do_sha1m (void) | |
16881 | { | |
16882 | do_crypto_3op_1 (0, 2); | |
16883 | } | |
16884 | ||
16885 | static void | |
16886 | do_sha1su0 (void) | |
16887 | { | |
16888 | do_crypto_3op_1 (0, 3); | |
16889 | } | |
91ff7894 | 16890 | |
48adcd8e MGD |
16891 | static void |
16892 | do_sha256h (void) | |
16893 | { | |
16894 | do_crypto_3op_1 (1, 0); | |
16895 | } | |
16896 | ||
16897 | static void | |
16898 | do_sha256h2 (void) | |
16899 | { | |
16900 | do_crypto_3op_1 (1, 1); | |
16901 | } | |
16902 | ||
16903 | static void | |
16904 | do_sha256su1 (void) | |
16905 | { | |
16906 | do_crypto_3op_1 (1, 2); | |
16907 | } | |
3c9017d2 MGD |
16908 | |
16909 | static void | |
16910 | do_sha1h (void) | |
16911 | { | |
16912 | do_crypto_2op_1 (N_32, -1); | |
16913 | } | |
16914 | ||
16915 | static void | |
16916 | do_sha1su1 (void) | |
16917 | { | |
16918 | do_crypto_2op_1 (N_32, 0); | |
16919 | } | |
16920 | ||
16921 | static void | |
16922 | do_sha256su0 (void) | |
16923 | { | |
16924 | do_crypto_2op_1 (N_32, 1); | |
16925 | } | |
dd5181d5 KT |
16926 | |
16927 | static void | |
16928 | do_crc32_1 (unsigned int poly, unsigned int sz) | |
16929 | { | |
16930 | unsigned int Rd = inst.operands[0].reg; | |
16931 | unsigned int Rn = inst.operands[1].reg; | |
16932 | unsigned int Rm = inst.operands[2].reg; | |
16933 | ||
16934 | set_it_insn_type (OUTSIDE_IT_INSN); | |
16935 | inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12); | |
16936 | inst.instruction |= LOW4 (Rn) << 16; | |
16937 | inst.instruction |= LOW4 (Rm); | |
16938 | inst.instruction |= sz << (thumb_mode ? 4 : 21); | |
16939 | inst.instruction |= poly << (thumb_mode ? 20 : 9); | |
16940 | ||
16941 | if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) | |
16942 | as_warn (UNPRED_REG ("r15")); | |
16943 | if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP)) | |
16944 | as_warn (UNPRED_REG ("r13")); | |
16945 | } | |
16946 | ||
16947 | static void | |
16948 | do_crc32b (void) | |
16949 | { | |
16950 | do_crc32_1 (0, 0); | |
16951 | } | |
16952 | ||
16953 | static void | |
16954 | do_crc32h (void) | |
16955 | { | |
16956 | do_crc32_1 (0, 1); | |
16957 | } | |
16958 | ||
16959 | static void | |
16960 | do_crc32w (void) | |
16961 | { | |
16962 | do_crc32_1 (0, 2); | |
16963 | } | |
16964 | ||
16965 | static void | |
16966 | do_crc32cb (void) | |
16967 | { | |
16968 | do_crc32_1 (1, 0); | |
16969 | } | |
16970 | ||
16971 | static void | |
16972 | do_crc32ch (void) | |
16973 | { | |
16974 | do_crc32_1 (1, 1); | |
16975 | } | |
16976 | ||
16977 | static void | |
16978 | do_crc32cw (void) | |
16979 | { | |
16980 | do_crc32_1 (1, 2); | |
16981 | } | |
16982 | ||
5287ad62 JB |
16983 | \f |
16984 | /* Overall per-instruction processing. */ | |
16985 | ||
16986 | /* We need to be able to fix up arbitrary expressions in some statements. | |
16987 | This is so that we can handle symbols that are an arbitrary distance from | |
16988 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
16989 | which returns part of an address in a form which will be valid for | |
16990 | a data instruction. We do this by pushing the expression into a symbol | |
16991 | in the expr_section, and creating a fix for that. */ | |
16992 | ||
16993 | static void | |
16994 | fix_new_arm (fragS * frag, | |
16995 | int where, | |
16996 | short int size, | |
16997 | expressionS * exp, | |
16998 | int pc_rel, | |
16999 | int reloc) | |
17000 | { | |
17001 | fixS * new_fix; | |
17002 | ||
17003 | switch (exp->X_op) | |
17004 | { | |
17005 | case O_constant: | |
6e7ce2cd PB |
17006 | if (pc_rel) |
17007 | { | |
17008 | /* Create an absolute valued symbol, so we have something to | |
477330fc RM |
17009 | refer to in the object file. Unfortunately for us, gas's |
17010 | generic expression parsing will already have folded out | |
17011 | any use of .set foo/.type foo %function that may have | |
17012 | been used to set type information of the target location, | |
17013 | that's being specified symbolically. We have to presume | |
17014 | the user knows what they are doing. */ | |
6e7ce2cd PB |
17015 | char name[16 + 8]; |
17016 | symbolS *symbol; | |
17017 | ||
17018 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
17019 | ||
17020 | symbol = symbol_find_or_make (name); | |
17021 | S_SET_SEGMENT (symbol, absolute_section); | |
17022 | symbol_set_frag (symbol, &zero_address_frag); | |
17023 | S_SET_VALUE (symbol, exp->X_add_number); | |
17024 | exp->X_op = O_symbol; | |
17025 | exp->X_add_symbol = symbol; | |
17026 | exp->X_add_number = 0; | |
17027 | } | |
17028 | /* FALLTHROUGH */ | |
5287ad62 JB |
17029 | case O_symbol: |
17030 | case O_add: | |
17031 | case O_subtract: | |
21d799b5 | 17032 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
477330fc | 17033 | (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
17034 | break; |
17035 | ||
17036 | default: | |
21d799b5 | 17037 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
477330fc | 17038 | pc_rel, (enum bfd_reloc_code_real) reloc); |
5287ad62 JB |
17039 | break; |
17040 | } | |
17041 | ||
17042 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
17043 | instruction. */ | |
17044 | new_fix->tc_fix_data = thumb_mode; | |
17045 | } | |
17046 | ||
17047 | /* Create a frg for an instruction requiring relaxation. */ | |
17048 | static void | |
17049 | output_relax_insn (void) | |
17050 | { | |
17051 | char * to; | |
17052 | symbolS *sym; | |
0110f2b8 PB |
17053 | int offset; |
17054 | ||
6e1cb1a6 PB |
17055 | /* The size of the instruction is unknown, so tie the debug info to the |
17056 | start of the instruction. */ | |
17057 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 17058 | |
0110f2b8 PB |
17059 | switch (inst.reloc.exp.X_op) |
17060 | { | |
17061 | case O_symbol: | |
17062 | sym = inst.reloc.exp.X_add_symbol; | |
17063 | offset = inst.reloc.exp.X_add_number; | |
17064 | break; | |
17065 | case O_constant: | |
17066 | sym = NULL; | |
17067 | offset = inst.reloc.exp.X_add_number; | |
17068 | break; | |
17069 | default: | |
17070 | sym = make_expr_symbol (&inst.reloc.exp); | |
17071 | offset = 0; | |
17072 | break; | |
17073 | } | |
17074 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
17075 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
17076 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
17077 | } |
17078 | ||
17079 | /* Write a 32-bit thumb instruction to buf. */ | |
17080 | static void | |
17081 | put_thumb32_insn (char * buf, unsigned long insn) | |
17082 | { | |
17083 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
17084 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
17085 | } | |
17086 | ||
b99bd4ef | 17087 | static void |
c19d1205 | 17088 | output_inst (const char * str) |
b99bd4ef | 17089 | { |
c19d1205 | 17090 | char * to = NULL; |
b99bd4ef | 17091 | |
c19d1205 | 17092 | if (inst.error) |
b99bd4ef | 17093 | { |
c19d1205 | 17094 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
17095 | return; |
17096 | } | |
5f4273c7 NC |
17097 | if (inst.relax) |
17098 | { | |
17099 | output_relax_insn (); | |
0110f2b8 | 17100 | return; |
5f4273c7 | 17101 | } |
c19d1205 ZW |
17102 | if (inst.size == 0) |
17103 | return; | |
b99bd4ef | 17104 | |
c19d1205 | 17105 | to = frag_more (inst.size); |
8dc2430f NC |
17106 | /* PR 9814: Record the thumb mode into the current frag so that we know |
17107 | what type of NOP padding to use, if necessary. We override any previous | |
17108 | setting so that if the mode has changed then the NOPS that we use will | |
17109 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 17110 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
17111 | |
17112 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 17113 | { |
9c2799c2 | 17114 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 17115 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 17116 | } |
c19d1205 | 17117 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 17118 | { |
9c2799c2 | 17119 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
17120 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
17121 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 17122 | } |
c19d1205 ZW |
17123 | else |
17124 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 17125 | |
c19d1205 ZW |
17126 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
17127 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
17128 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
17129 | inst.reloc.type); | |
b99bd4ef | 17130 | |
c19d1205 | 17131 | dwarf2_emit_insn (inst.size); |
c19d1205 | 17132 | } |
b99bd4ef | 17133 | |
e07e6e58 NC |
17134 | static char * |
17135 | output_it_inst (int cond, int mask, char * to) | |
17136 | { | |
17137 | unsigned long instruction = 0xbf00; | |
17138 | ||
17139 | mask &= 0xf; | |
17140 | instruction |= mask; | |
17141 | instruction |= cond << 4; | |
17142 | ||
17143 | if (to == NULL) | |
17144 | { | |
17145 | to = frag_more (2); | |
17146 | #ifdef OBJ_ELF | |
17147 | dwarf2_emit_insn (2); | |
17148 | #endif | |
17149 | } | |
17150 | ||
17151 | md_number_to_chars (to, instruction, 2); | |
17152 | ||
17153 | return to; | |
17154 | } | |
17155 | ||
c19d1205 ZW |
17156 | /* Tag values used in struct asm_opcode's tag field. */ |
17157 | enum opcode_tag | |
17158 | { | |
17159 | OT_unconditional, /* Instruction cannot be conditionalized. | |
17160 | The ARM condition field is still 0xE. */ | |
17161 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
17162 | and carries 0xF in its ARM condition field. */ | |
17163 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 | 17164 | OT_csuffixF, /* Some forms of the instruction take a conditional |
477330fc RM |
17165 | suffix, others place 0xF where the condition field |
17166 | would be. */ | |
c19d1205 ZW |
17167 | OT_cinfix3, /* Instruction takes a conditional infix, |
17168 | beginning at character index 3. (In | |
17169 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
17170 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
17171 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
17172 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
17173 | character index 3, even in unified mode. Used for | |
17174 | legacy instructions where suffix and infix forms | |
17175 | may be ambiguous. */ | |
c19d1205 | 17176 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 17177 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
17178 | OT_odd_infix_unc, /* This is the unconditional variant of an |
17179 | instruction that takes a conditional infix | |
17180 | at an unusual position. In unified mode, | |
17181 | this variant will accept a suffix. */ | |
17182 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
17183 | are the conditional variants of instructions that | |
17184 | take conditional infixes in unusual positions. | |
17185 | The infix appears at character index | |
17186 | (tag - OT_odd_infix_0). These are not accepted | |
17187 | in unified mode. */ | |
17188 | }; | |
b99bd4ef | 17189 | |
c19d1205 ZW |
17190 | /* Subroutine of md_assemble, responsible for looking up the primary |
17191 | opcode from the mnemonic the user wrote. STR points to the | |
17192 | beginning of the mnemonic. | |
17193 | ||
17194 | This is not simply a hash table lookup, because of conditional | |
17195 | variants. Most instructions have conditional variants, which are | |
17196 | expressed with a _conditional affix_ to the mnemonic. If we were | |
17197 | to encode each conditional variant as a literal string in the opcode | |
17198 | table, it would have approximately 20,000 entries. | |
17199 | ||
17200 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
17201 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
17202 | instructions take the affix as an infix, notably the s-variants of | |
17203 | the arithmetic instructions. Of those instructions, all but six | |
17204 | have the infix appear after the third character of the mnemonic. | |
17205 | ||
17206 | Accordingly, the algorithm for looking up primary opcodes given | |
17207 | an identifier is: | |
17208 | ||
17209 | 1. Look up the identifier in the opcode table. | |
17210 | If we find a match, go to step U. | |
17211 | ||
17212 | 2. Look up the last two characters of the identifier in the | |
17213 | conditions table. If we find a match, look up the first N-2 | |
17214 | characters of the identifier in the opcode table. If we | |
17215 | find a match, go to step CE. | |
17216 | ||
17217 | 3. Look up the fourth and fifth characters of the identifier in | |
17218 | the conditions table. If we find a match, extract those | |
17219 | characters from the identifier, and look up the remaining | |
17220 | characters in the opcode table. If we find a match, go | |
17221 | to step CM. | |
17222 | ||
17223 | 4. Fail. | |
17224 | ||
17225 | U. Examine the tag field of the opcode structure, in case this is | |
17226 | one of the six instructions with its conditional infix in an | |
17227 | unusual place. If it is, the tag tells us where to find the | |
17228 | infix; look it up in the conditions table and set inst.cond | |
17229 | accordingly. Otherwise, this is an unconditional instruction. | |
17230 | Again set inst.cond accordingly. Return the opcode structure. | |
17231 | ||
17232 | CE. Examine the tag field to make sure this is an instruction that | |
17233 | should receive a conditional suffix. If it is not, fail. | |
17234 | Otherwise, set inst.cond from the suffix we already looked up, | |
17235 | and return the opcode structure. | |
17236 | ||
17237 | CM. Examine the tag field to make sure this is an instruction that | |
17238 | should receive a conditional infix after the third character. | |
17239 | If it is not, fail. Otherwise, undo the edits to the current | |
17240 | line of input and proceed as for case CE. */ | |
17241 | ||
17242 | static const struct asm_opcode * | |
17243 | opcode_lookup (char **str) | |
17244 | { | |
17245 | char *end, *base; | |
17246 | char *affix; | |
17247 | const struct asm_opcode *opcode; | |
17248 | const struct asm_cond *cond; | |
e3cb604e | 17249 | char save[2]; |
c19d1205 ZW |
17250 | |
17251 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 17252 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 17253 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 17254 | if (*end == ' ' || *end == '.') |
c19d1205 | 17255 | break; |
b99bd4ef | 17256 | |
c19d1205 | 17257 | if (end == base) |
c921be7d | 17258 | return NULL; |
b99bd4ef | 17259 | |
5287ad62 | 17260 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 17261 | if (end[0] == '.') |
b99bd4ef | 17262 | { |
5287ad62 | 17263 | int offset = 2; |
5f4273c7 | 17264 | |
267d2029 | 17265 | /* The .w and .n suffixes are only valid if the unified syntax is in |
477330fc | 17266 | use. */ |
267d2029 | 17267 | if (unified_syntax && end[1] == 'w') |
c19d1205 | 17268 | inst.size_req = 4; |
267d2029 | 17269 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
17270 | inst.size_req = 2; |
17271 | else | |
477330fc | 17272 | offset = 0; |
5287ad62 JB |
17273 | |
17274 | inst.vectype.elems = 0; | |
17275 | ||
17276 | *str = end + offset; | |
b99bd4ef | 17277 | |
5f4273c7 | 17278 | if (end[offset] == '.') |
5287ad62 | 17279 | { |
267d2029 | 17280 | /* See if we have a Neon type suffix (possible in either unified or |
477330fc RM |
17281 | non-unified ARM syntax mode). */ |
17282 | if (parse_neon_type (&inst.vectype, str) == FAIL) | |
c921be7d | 17283 | return NULL; |
477330fc | 17284 | } |
5287ad62 | 17285 | else if (end[offset] != '\0' && end[offset] != ' ') |
477330fc | 17286 | return NULL; |
b99bd4ef | 17287 | } |
c19d1205 ZW |
17288 | else |
17289 | *str = end; | |
b99bd4ef | 17290 | |
c19d1205 | 17291 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 | 17292 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17293 | end - base); |
c19d1205 | 17294 | if (opcode) |
b99bd4ef | 17295 | { |
c19d1205 ZW |
17296 | /* step U */ |
17297 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 17298 | { |
c19d1205 ZW |
17299 | inst.cond = COND_ALWAYS; |
17300 | return opcode; | |
b99bd4ef | 17301 | } |
b99bd4ef | 17302 | |
278df34e | 17303 | if (warn_on_deprecated && unified_syntax) |
5c3696f8 | 17304 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 | 17305 | affix = base + (opcode->tag - OT_odd_infix_0); |
21d799b5 | 17306 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 17307 | gas_assert (cond); |
b99bd4ef | 17308 | |
c19d1205 ZW |
17309 | inst.cond = cond->value; |
17310 | return opcode; | |
17311 | } | |
b99bd4ef | 17312 | |
c19d1205 ZW |
17313 | /* Cannot have a conditional suffix on a mnemonic of less than two |
17314 | characters. */ | |
17315 | if (end - base < 3) | |
c921be7d | 17316 | return NULL; |
b99bd4ef | 17317 | |
c19d1205 ZW |
17318 | /* Look for suffixed mnemonic. */ |
17319 | affix = end - 2; | |
21d799b5 NC |
17320 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
17321 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
477330fc | 17322 | affix - base); |
c19d1205 ZW |
17323 | if (opcode && cond) |
17324 | { | |
17325 | /* step CE */ | |
17326 | switch (opcode->tag) | |
17327 | { | |
e3cb604e PB |
17328 | case OT_cinfix3_legacy: |
17329 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
17330 | break; | |
17331 | ||
c19d1205 | 17332 | case OT_cinfix3: |
088fa78e | 17333 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
17334 | case OT_odd_infix_unc: |
17335 | if (!unified_syntax) | |
e3cb604e | 17336 | return 0; |
c19d1205 ZW |
17337 | /* else fall through */ |
17338 | ||
17339 | case OT_csuffix: | |
477330fc | 17340 | case OT_csuffixF: |
c19d1205 ZW |
17341 | case OT_csuf_or_in3: |
17342 | inst.cond = cond->value; | |
17343 | return opcode; | |
17344 | ||
17345 | case OT_unconditional: | |
17346 | case OT_unconditionalF: | |
dfa9f0d5 | 17347 | if (thumb_mode) |
c921be7d | 17348 | inst.cond = cond->value; |
dfa9f0d5 PB |
17349 | else |
17350 | { | |
c921be7d | 17351 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
17352 | inst.error = BAD_COND; |
17353 | inst.cond = COND_ALWAYS; | |
17354 | } | |
c19d1205 | 17355 | return opcode; |
b99bd4ef | 17356 | |
c19d1205 | 17357 | default: |
c921be7d | 17358 | return NULL; |
c19d1205 ZW |
17359 | } |
17360 | } | |
b99bd4ef | 17361 | |
c19d1205 ZW |
17362 | /* Cannot have a usual-position infix on a mnemonic of less than |
17363 | six characters (five would be a suffix). */ | |
17364 | if (end - base < 6) | |
c921be7d | 17365 | return NULL; |
b99bd4ef | 17366 | |
c19d1205 ZW |
17367 | /* Look for infixed mnemonic in the usual position. */ |
17368 | affix = base + 3; | |
21d799b5 | 17369 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 17370 | if (!cond) |
c921be7d | 17371 | return NULL; |
e3cb604e PB |
17372 | |
17373 | memcpy (save, affix, 2); | |
17374 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 | 17375 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
477330fc | 17376 | (end - base) - 2); |
e3cb604e PB |
17377 | memmove (affix + 2, affix, (end - affix) - 2); |
17378 | memcpy (affix, save, 2); | |
17379 | ||
088fa78e KH |
17380 | if (opcode |
17381 | && (opcode->tag == OT_cinfix3 | |
17382 | || opcode->tag == OT_cinfix3_deprecated | |
17383 | || opcode->tag == OT_csuf_or_in3 | |
17384 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 17385 | { |
c921be7d | 17386 | /* Step CM. */ |
278df34e | 17387 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
17388 | && (opcode->tag == OT_cinfix3 |
17389 | || opcode->tag == OT_cinfix3_deprecated)) | |
5c3696f8 | 17390 | as_tsktsk (_("conditional infixes are deprecated in unified syntax")); |
c19d1205 ZW |
17391 | |
17392 | inst.cond = cond->value; | |
17393 | return opcode; | |
b99bd4ef NC |
17394 | } |
17395 | ||
c921be7d | 17396 | return NULL; |
b99bd4ef NC |
17397 | } |
17398 | ||
e07e6e58 NC |
17399 | /* This function generates an initial IT instruction, leaving its block |
17400 | virtually open for the new instructions. Eventually, | |
17401 | the mask will be updated by now_it_add_mask () each time | |
17402 | a new instruction needs to be included in the IT block. | |
17403 | Finally, the block is closed with close_automatic_it_block (). | |
17404 | The block closure can be requested either from md_assemble (), | |
17405 | a tencode (), or due to a label hook. */ | |
17406 | ||
17407 | static void | |
17408 | new_automatic_it_block (int cond) | |
17409 | { | |
17410 | now_it.state = AUTOMATIC_IT_BLOCK; | |
17411 | now_it.mask = 0x18; | |
17412 | now_it.cc = cond; | |
17413 | now_it.block_length = 1; | |
cd000bff | 17414 | mapping_state (MAP_THUMB); |
e07e6e58 | 17415 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
17416 | now_it.warn_deprecated = FALSE; |
17417 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
17418 | } |
17419 | ||
17420 | /* Close an automatic IT block. | |
17421 | See comments in new_automatic_it_block (). */ | |
17422 | ||
17423 | static void | |
17424 | close_automatic_it_block (void) | |
17425 | { | |
17426 | now_it.mask = 0x10; | |
17427 | now_it.block_length = 0; | |
17428 | } | |
17429 | ||
17430 | /* Update the mask of the current automatically-generated IT | |
17431 | instruction. See comments in new_automatic_it_block (). */ | |
17432 | ||
17433 | static void | |
17434 | now_it_add_mask (int cond) | |
17435 | { | |
17436 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
17437 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
477330fc | 17438 | | ((bitvalue) << (nbit))) |
e07e6e58 | 17439 | const int resulting_bit = (cond & 1); |
c921be7d | 17440 | |
e07e6e58 NC |
17441 | now_it.mask &= 0xf; |
17442 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
477330fc RM |
17443 | resulting_bit, |
17444 | (5 - now_it.block_length)); | |
e07e6e58 | 17445 | now_it.mask = SET_BIT_VALUE (now_it.mask, |
477330fc RM |
17446 | 1, |
17447 | ((5 - now_it.block_length) - 1) ); | |
e07e6e58 NC |
17448 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); |
17449 | ||
17450 | #undef CLEAR_BIT | |
17451 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
17452 | } |
17453 | ||
17454 | /* The IT blocks handling machinery is accessed through the these functions: | |
17455 | it_fsm_pre_encode () from md_assemble () | |
17456 | set_it_insn_type () optional, from the tencode functions | |
17457 | set_it_insn_type_last () ditto | |
17458 | in_it_block () ditto | |
17459 | it_fsm_post_encode () from md_assemble () | |
17460 | force_automatic_it_block_close () from label habdling functions | |
17461 | ||
17462 | Rationale: | |
17463 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
477330fc RM |
17464 | initializing the IT insn type with a generic initial value depending |
17465 | on the inst.condition. | |
e07e6e58 | 17466 | 2) During the tencode function, two things may happen: |
477330fc RM |
17467 | a) The tencode function overrides the IT insn type by |
17468 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
17469 | b) The tencode function queries the IT block state by | |
17470 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
17471 | ||
17472 | Both set_it_insn_type and in_it_block run the internal FSM state | |
17473 | handling function (handle_it_state), because: a) setting the IT insn | |
17474 | type may incur in an invalid state (exiting the function), | |
17475 | and b) querying the state requires the FSM to be updated. | |
17476 | Specifically we want to avoid creating an IT block for conditional | |
17477 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
17478 | determine whether an IT block is required until the tencode () routine | |
17479 | has decided what type of instruction this actually it. | |
17480 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
17481 | set_it_insn_type has to be called first. | |
17482 | ||
17483 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
17484 | determines the insn IT type depending on the inst.cond code. | |
17485 | When a tencode () routine encodes an instruction that can be | |
17486 | either outside an IT block, or, in the case of being inside, has to be | |
17487 | the last one, set_it_insn_type_last () will determine the proper | |
17488 | IT instruction type based on the inst.cond code. Otherwise, | |
17489 | set_it_insn_type can be called for overriding that logic or | |
17490 | for covering other cases. | |
17491 | ||
17492 | Calling handle_it_state () may not transition the IT block state to | |
17493 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
17494 | still queried. Instead, if the FSM determines that the state should | |
17495 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
17496 | after the tencode () function: that's what it_fsm_post_encode () does. | |
17497 | ||
17498 | Since in_it_block () calls the state handling function to get an | |
17499 | updated state, an error may occur (due to invalid insns combination). | |
17500 | In that case, inst.error is set. | |
17501 | Therefore, inst.error has to be checked after the execution of | |
17502 | the tencode () routine. | |
e07e6e58 NC |
17503 | |
17504 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
477330fc RM |
17505 | any pending state change (if any) that didn't take place in |
17506 | handle_it_state () as explained above. */ | |
e07e6e58 NC |
17507 | |
17508 | static void | |
17509 | it_fsm_pre_encode (void) | |
17510 | { | |
17511 | if (inst.cond != COND_ALWAYS) | |
17512 | inst.it_insn_type = INSIDE_IT_INSN; | |
17513 | else | |
17514 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
17515 | ||
17516 | now_it.state_handled = 0; | |
17517 | } | |
17518 | ||
17519 | /* IT state FSM handling function. */ | |
17520 | ||
17521 | static int | |
17522 | handle_it_state (void) | |
17523 | { | |
17524 | now_it.state_handled = 1; | |
5a01bb1d | 17525 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
17526 | |
17527 | switch (now_it.state) | |
17528 | { | |
17529 | case OUTSIDE_IT_BLOCK: | |
17530 | switch (inst.it_insn_type) | |
17531 | { | |
17532 | case OUTSIDE_IT_INSN: | |
17533 | break; | |
17534 | ||
17535 | case INSIDE_IT_INSN: | |
17536 | case INSIDE_IT_LAST_INSN: | |
17537 | if (thumb_mode == 0) | |
17538 | { | |
c921be7d | 17539 | if (unified_syntax |
e07e6e58 NC |
17540 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
17541 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
17542 | " for Thumb.")); | |
17543 | } | |
17544 | else | |
17545 | { | |
17546 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
17547 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
17548 | { | |
17549 | /* Automatically generate the IT instruction. */ | |
17550 | new_automatic_it_block (inst.cond); | |
17551 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
17552 | close_automatic_it_block (); | |
17553 | } | |
17554 | else | |
17555 | { | |
17556 | inst.error = BAD_OUT_IT; | |
17557 | return FAIL; | |
17558 | } | |
17559 | } | |
17560 | break; | |
17561 | ||
17562 | case IF_INSIDE_IT_LAST_INSN: | |
17563 | case NEUTRAL_IT_INSN: | |
17564 | break; | |
17565 | ||
17566 | case IT_INSN: | |
17567 | now_it.state = MANUAL_IT_BLOCK; | |
17568 | now_it.block_length = 0; | |
17569 | break; | |
17570 | } | |
17571 | break; | |
17572 | ||
17573 | case AUTOMATIC_IT_BLOCK: | |
17574 | /* Three things may happen now: | |
17575 | a) We should increment current it block size; | |
17576 | b) We should close current it block (closing insn or 4 insns); | |
17577 | c) We should close current it block and start a new one (due | |
17578 | to incompatible conditions or | |
17579 | 4 insns-length block reached). */ | |
17580 | ||
17581 | switch (inst.it_insn_type) | |
17582 | { | |
17583 | case OUTSIDE_IT_INSN: | |
17584 | /* The closure of the block shall happen immediatelly, | |
17585 | so any in_it_block () call reports the block as closed. */ | |
17586 | force_automatic_it_block_close (); | |
17587 | break; | |
17588 | ||
17589 | case INSIDE_IT_INSN: | |
17590 | case INSIDE_IT_LAST_INSN: | |
17591 | case IF_INSIDE_IT_LAST_INSN: | |
17592 | now_it.block_length++; | |
17593 | ||
17594 | if (now_it.block_length > 4 | |
17595 | || !now_it_compatible (inst.cond)) | |
17596 | { | |
17597 | force_automatic_it_block_close (); | |
17598 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
17599 | new_automatic_it_block (inst.cond); | |
17600 | } | |
17601 | else | |
17602 | { | |
5a01bb1d | 17603 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17604 | now_it_add_mask (inst.cond); |
17605 | } | |
17606 | ||
17607 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
17608 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
17609 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
17610 | close_automatic_it_block (); | |
17611 | break; | |
17612 | ||
17613 | case NEUTRAL_IT_INSN: | |
17614 | now_it.block_length++; | |
5a01bb1d | 17615 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17616 | |
17617 | if (now_it.block_length > 4) | |
17618 | force_automatic_it_block_close (); | |
17619 | else | |
17620 | now_it_add_mask (now_it.cc & 1); | |
17621 | break; | |
17622 | ||
17623 | case IT_INSN: | |
17624 | close_automatic_it_block (); | |
17625 | now_it.state = MANUAL_IT_BLOCK; | |
17626 | break; | |
17627 | } | |
17628 | break; | |
17629 | ||
17630 | case MANUAL_IT_BLOCK: | |
17631 | { | |
17632 | /* Check conditional suffixes. */ | |
17633 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
17634 | int is_last; | |
17635 | now_it.mask <<= 1; | |
17636 | now_it.mask &= 0x1f; | |
17637 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 17638 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
17639 | |
17640 | switch (inst.it_insn_type) | |
17641 | { | |
17642 | case OUTSIDE_IT_INSN: | |
17643 | inst.error = BAD_NOT_IT; | |
17644 | return FAIL; | |
17645 | ||
17646 | case INSIDE_IT_INSN: | |
17647 | if (cond != inst.cond) | |
17648 | { | |
17649 | inst.error = BAD_IT_COND; | |
17650 | return FAIL; | |
17651 | } | |
17652 | break; | |
17653 | ||
17654 | case INSIDE_IT_LAST_INSN: | |
17655 | case IF_INSIDE_IT_LAST_INSN: | |
17656 | if (cond != inst.cond) | |
17657 | { | |
17658 | inst.error = BAD_IT_COND; | |
17659 | return FAIL; | |
17660 | } | |
17661 | if (!is_last) | |
17662 | { | |
17663 | inst.error = BAD_BRANCH; | |
17664 | return FAIL; | |
17665 | } | |
17666 | break; | |
17667 | ||
17668 | case NEUTRAL_IT_INSN: | |
17669 | /* The BKPT instruction is unconditional even in an IT block. */ | |
17670 | break; | |
17671 | ||
17672 | case IT_INSN: | |
17673 | inst.error = BAD_IT_IT; | |
17674 | return FAIL; | |
17675 | } | |
17676 | } | |
17677 | break; | |
17678 | } | |
17679 | ||
17680 | return SUCCESS; | |
17681 | } | |
17682 | ||
5a01bb1d MGD |
17683 | struct depr_insn_mask |
17684 | { | |
17685 | unsigned long pattern; | |
17686 | unsigned long mask; | |
17687 | const char* description; | |
17688 | }; | |
17689 | ||
17690 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
17691 | ARMv8. */ | |
17692 | static const struct depr_insn_mask depr_it_insns[] = { | |
17693 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
17694 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
17695 | { 0xa000, 0xb800, N_("ADR") }, | |
17696 | { 0x4800, 0xf800, N_("Literal loads") }, | |
17697 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
17698 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
c8de034b JW |
17699 | /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue' |
17700 | field in asm_opcode. 'tvalue' is used at the stage this check happen. */ | |
17701 | { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") }, | |
5a01bb1d MGD |
17702 | { 0, 0, NULL } |
17703 | }; | |
17704 | ||
e07e6e58 NC |
17705 | static void |
17706 | it_fsm_post_encode (void) | |
17707 | { | |
17708 | int is_last; | |
17709 | ||
17710 | if (!now_it.state_handled) | |
17711 | handle_it_state (); | |
17712 | ||
5a01bb1d MGD |
17713 | if (now_it.insn_cond |
17714 | && !now_it.warn_deprecated | |
17715 | && warn_on_deprecated | |
17716 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
17717 | { | |
17718 | if (inst.instruction >= 0x10000) | |
17719 | { | |
5c3696f8 | 17720 | as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are " |
5a01bb1d MGD |
17721 | "deprecated in ARMv8")); |
17722 | now_it.warn_deprecated = TRUE; | |
17723 | } | |
17724 | else | |
17725 | { | |
17726 | const struct depr_insn_mask *p = depr_it_insns; | |
17727 | ||
17728 | while (p->mask != 0) | |
17729 | { | |
17730 | if ((inst.instruction & p->mask) == p->pattern) | |
17731 | { | |
5c3696f8 | 17732 | as_tsktsk (_("IT blocks containing 16-bit Thumb instructions " |
5a01bb1d MGD |
17733 | "of the following class are deprecated in ARMv8: " |
17734 | "%s"), p->description); | |
17735 | now_it.warn_deprecated = TRUE; | |
17736 | break; | |
17737 | } | |
17738 | ||
17739 | ++p; | |
17740 | } | |
17741 | } | |
17742 | ||
17743 | if (now_it.block_length > 1) | |
17744 | { | |
5c3696f8 | 17745 | as_tsktsk (_("IT blocks containing more than one conditional " |
0a8897c7 | 17746 | "instruction are deprecated in ARMv8")); |
5a01bb1d MGD |
17747 | now_it.warn_deprecated = TRUE; |
17748 | } | |
17749 | } | |
17750 | ||
e07e6e58 NC |
17751 | is_last = (now_it.mask == 0x10); |
17752 | if (is_last) | |
17753 | { | |
17754 | now_it.state = OUTSIDE_IT_BLOCK; | |
17755 | now_it.mask = 0; | |
17756 | } | |
17757 | } | |
17758 | ||
17759 | static void | |
17760 | force_automatic_it_block_close (void) | |
17761 | { | |
17762 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
17763 | { | |
17764 | close_automatic_it_block (); | |
17765 | now_it.state = OUTSIDE_IT_BLOCK; | |
17766 | now_it.mask = 0; | |
17767 | } | |
17768 | } | |
17769 | ||
17770 | static int | |
17771 | in_it_block (void) | |
17772 | { | |
17773 | if (!now_it.state_handled) | |
17774 | handle_it_state (); | |
17775 | ||
17776 | return now_it.state != OUTSIDE_IT_BLOCK; | |
17777 | } | |
17778 | ||
c19d1205 ZW |
17779 | void |
17780 | md_assemble (char *str) | |
b99bd4ef | 17781 | { |
c19d1205 ZW |
17782 | char *p = str; |
17783 | const struct asm_opcode * opcode; | |
b99bd4ef | 17784 | |
c19d1205 ZW |
17785 | /* Align the previous label if needed. */ |
17786 | if (last_label_seen != NULL) | |
b99bd4ef | 17787 | { |
c19d1205 ZW |
17788 | symbol_set_frag (last_label_seen, frag_now); |
17789 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
17790 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
17791 | } |
17792 | ||
c19d1205 ZW |
17793 | memset (&inst, '\0', sizeof (inst)); |
17794 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 17795 | |
c19d1205 ZW |
17796 | opcode = opcode_lookup (&p); |
17797 | if (!opcode) | |
b99bd4ef | 17798 | { |
c19d1205 | 17799 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 17800 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d | 17801 | if (! create_register_alias (str, p) |
477330fc | 17802 | && ! create_neon_reg_alias (str, p)) |
c19d1205 | 17803 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 17804 | |
b99bd4ef NC |
17805 | return; |
17806 | } | |
17807 | ||
278df34e | 17808 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
5c3696f8 | 17809 | as_tsktsk (_("s suffix on comparison instruction is deprecated")); |
088fa78e | 17810 | |
037e8744 JB |
17811 | /* The value which unconditional instructions should have in place of the |
17812 | condition field. */ | |
17813 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
17814 | ||
c19d1205 | 17815 | if (thumb_mode) |
b99bd4ef | 17816 | { |
e74cfd16 | 17817 | arm_feature_set variant; |
8f06b2d8 PB |
17818 | |
17819 | variant = cpu_variant; | |
17820 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
17821 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
17822 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 17823 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
17824 | if (!opcode->tvariant |
17825 | || (thumb_mode == 1 | |
17826 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 17827 | { |
84b52b66 | 17828 | as_bad (_("selected processor does not support `%s' in Thumb mode"), str); |
b99bd4ef NC |
17829 | return; |
17830 | } | |
c19d1205 ZW |
17831 | if (inst.cond != COND_ALWAYS && !unified_syntax |
17832 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 17833 | { |
c19d1205 | 17834 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
17835 | return; |
17836 | } | |
17837 | ||
752d5da4 | 17838 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 17839 | { |
7e806470 | 17840 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
17841 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
17842 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
17843 | { | |
17844 | /* Two things are addressed here. | |
17845 | 1) Implicit require narrow instructions on Thumb-1. | |
17846 | This avoids relaxation accidentally introducing Thumb-2 | |
17847 | instructions. | |
17848 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
17849 | if (inst.size_req == 0) | |
17850 | inst.size_req = 2; | |
17851 | else if (inst.size_req == 4) | |
17852 | { | |
84b52b66 | 17853 | as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str); |
752d5da4 NC |
17854 | return; |
17855 | } | |
17856 | } | |
076d447c PB |
17857 | } |
17858 | ||
c19d1205 ZW |
17859 | inst.instruction = opcode->tvalue; |
17860 | ||
5be8be5d | 17861 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
477330fc RM |
17862 | { |
17863 | /* Prepare the it_insn_type for those encodings that don't set | |
17864 | it. */ | |
17865 | it_fsm_pre_encode (); | |
c19d1205 | 17866 | |
477330fc | 17867 | opcode->tencode (); |
e07e6e58 | 17868 | |
477330fc RM |
17869 | it_fsm_post_encode (); |
17870 | } | |
e27ec89e | 17871 | |
0110f2b8 | 17872 | if (!(inst.error || inst.relax)) |
b99bd4ef | 17873 | { |
9c2799c2 | 17874 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
17875 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
17876 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 17877 | { |
c19d1205 | 17878 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
17879 | return; |
17880 | } | |
17881 | } | |
076d447c PB |
17882 | |
17883 | /* Something has gone badly wrong if we try to relax a fixed size | |
477330fc | 17884 | instruction. */ |
9c2799c2 | 17885 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 17886 | |
e74cfd16 PB |
17887 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17888 | *opcode->tvariant); | |
ee065d83 | 17889 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 17890 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 17891 | anything other than bl/blx and v6-M instructions. |
3cfdb781 TG |
17892 | The impact of relaxable instructions will be considered later after we |
17893 | finish all relaxation. */ | |
17894 | if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) | |
e07e6e58 NC |
17895 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
17896 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
17897 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
17898 | arm_ext_v6t2); | |
cd000bff | 17899 | |
88714cb8 DG |
17900 | check_neon_suffixes; |
17901 | ||
cd000bff | 17902 | if (!inst.error) |
c877a2f2 NC |
17903 | { |
17904 | mapping_state (MAP_THUMB); | |
17905 | } | |
c19d1205 | 17906 | } |
3e9e4fcf | 17907 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 17908 | { |
845b51d6 PB |
17909 | bfd_boolean is_bx; |
17910 | ||
17911 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
17912 | is_bx = (opcode->aencode == do_bx); | |
17913 | ||
c19d1205 | 17914 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
17915 | if (!(is_bx && fix_v4bx) |
17916 | && !(opcode->avariant && | |
17917 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 17918 | { |
84b52b66 | 17919 | as_bad (_("selected processor does not support `%s' in ARM mode"), str); |
c19d1205 | 17920 | return; |
b99bd4ef | 17921 | } |
c19d1205 | 17922 | if (inst.size_req) |
b99bd4ef | 17923 | { |
c19d1205 ZW |
17924 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
17925 | return; | |
b99bd4ef NC |
17926 | } |
17927 | ||
c19d1205 ZW |
17928 | inst.instruction = opcode->avalue; |
17929 | if (opcode->tag == OT_unconditionalF) | |
eff0bc54 | 17930 | inst.instruction |= 0xFU << 28; |
c19d1205 ZW |
17931 | else |
17932 | inst.instruction |= inst.cond << 28; | |
17933 | inst.size = INSN_SIZE; | |
5be8be5d | 17934 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
477330fc RM |
17935 | { |
17936 | it_fsm_pre_encode (); | |
17937 | opcode->aencode (); | |
17938 | it_fsm_post_encode (); | |
17939 | } | |
ee065d83 | 17940 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
477330fc | 17941 | on a hypothetical non-thumb v5 core. */ |
845b51d6 | 17942 | if (is_bx) |
e74cfd16 | 17943 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 17944 | else |
e74cfd16 PB |
17945 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
17946 | *opcode->avariant); | |
88714cb8 DG |
17947 | |
17948 | check_neon_suffixes; | |
17949 | ||
cd000bff | 17950 | if (!inst.error) |
c877a2f2 NC |
17951 | { |
17952 | mapping_state (MAP_ARM); | |
17953 | } | |
b99bd4ef | 17954 | } |
3e9e4fcf JB |
17955 | else |
17956 | { | |
17957 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
17958 | "-- `%s'"), str); | |
17959 | return; | |
17960 | } | |
c19d1205 ZW |
17961 | output_inst (str); |
17962 | } | |
b99bd4ef | 17963 | |
e07e6e58 NC |
17964 | static void |
17965 | check_it_blocks_finished (void) | |
17966 | { | |
17967 | #ifdef OBJ_ELF | |
17968 | asection *sect; | |
17969 | ||
17970 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
17971 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
17972 | == MANUAL_IT_BLOCK) | |
17973 | { | |
17974 | as_warn (_("section '%s' finished with an open IT block."), | |
17975 | sect->name); | |
17976 | } | |
17977 | #else | |
17978 | if (now_it.state == MANUAL_IT_BLOCK) | |
17979 | as_warn (_("file finished with an open IT block.")); | |
17980 | #endif | |
17981 | } | |
17982 | ||
c19d1205 ZW |
17983 | /* Various frobbings of labels and their addresses. */ |
17984 | ||
17985 | void | |
17986 | arm_start_line_hook (void) | |
17987 | { | |
17988 | last_label_seen = NULL; | |
b99bd4ef NC |
17989 | } |
17990 | ||
c19d1205 ZW |
17991 | void |
17992 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 17993 | { |
c19d1205 | 17994 | last_label_seen = sym; |
b99bd4ef | 17995 | |
c19d1205 | 17996 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 17997 | |
c19d1205 ZW |
17998 | #if defined OBJ_COFF || defined OBJ_ELF |
17999 | ARM_SET_INTERWORK (sym, support_interwork); | |
18000 | #endif | |
b99bd4ef | 18001 | |
e07e6e58 NC |
18002 | force_automatic_it_block_close (); |
18003 | ||
5f4273c7 | 18004 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
18005 | as Thumb functions. This is because these labels, whilst |
18006 | they exist inside Thumb code, are not the entry points for | |
18007 | possible ARM->Thumb calls. Also, these labels can be used | |
18008 | as part of a computed goto or switch statement. eg gcc | |
18009 | can generate code that looks like this: | |
b99bd4ef | 18010 | |
c19d1205 ZW |
18011 | ldr r2, [pc, .Laaa] |
18012 | lsl r3, r3, #2 | |
18013 | ldr r2, [r3, r2] | |
18014 | mov pc, r2 | |
b99bd4ef | 18015 | |
c19d1205 ZW |
18016 | .Lbbb: .word .Lxxx |
18017 | .Lccc: .word .Lyyy | |
18018 | ..etc... | |
18019 | .Laaa: .word Lbbb | |
b99bd4ef | 18020 | |
c19d1205 ZW |
18021 | The first instruction loads the address of the jump table. |
18022 | The second instruction converts a table index into a byte offset. | |
18023 | The third instruction gets the jump address out of the table. | |
18024 | The fourth instruction performs the jump. | |
b99bd4ef | 18025 | |
c19d1205 ZW |
18026 | If the address stored at .Laaa is that of a symbol which has the |
18027 | Thumb_Func bit set, then the linker will arrange for this address | |
18028 | to have the bottom bit set, which in turn would mean that the | |
18029 | address computation performed by the third instruction would end | |
18030 | up with the bottom bit set. Since the ARM is capable of unaligned | |
18031 | word loads, the instruction would then load the incorrect address | |
18032 | out of the jump table, and chaos would ensue. */ | |
18033 | if (label_is_thumb_function_name | |
18034 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
18035 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 18036 | { |
c19d1205 ZW |
18037 | /* When the address of a Thumb function is taken the bottom |
18038 | bit of that address should be set. This will allow | |
18039 | interworking between Arm and Thumb functions to work | |
18040 | correctly. */ | |
b99bd4ef | 18041 | |
c19d1205 | 18042 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 18043 | |
c19d1205 | 18044 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 18045 | } |
07a53e5c | 18046 | |
07a53e5c | 18047 | dwarf2_emit_label (sym); |
b99bd4ef NC |
18048 | } |
18049 | ||
c921be7d | 18050 | bfd_boolean |
c19d1205 | 18051 | arm_data_in_code (void) |
b99bd4ef | 18052 | { |
c19d1205 | 18053 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 18054 | { |
c19d1205 ZW |
18055 | *input_line_pointer = '/'; |
18056 | input_line_pointer += 5; | |
18057 | *input_line_pointer = 0; | |
c921be7d | 18058 | return TRUE; |
b99bd4ef NC |
18059 | } |
18060 | ||
c921be7d | 18061 | return FALSE; |
b99bd4ef NC |
18062 | } |
18063 | ||
c19d1205 ZW |
18064 | char * |
18065 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 18066 | { |
c19d1205 | 18067 | int len; |
b99bd4ef | 18068 | |
c19d1205 ZW |
18069 | if (thumb_mode && (len = strlen (name)) > 5 |
18070 | && streq (name + len - 5, "/data")) | |
18071 | *(name + len - 5) = 0; | |
b99bd4ef | 18072 | |
c19d1205 | 18073 | return name; |
b99bd4ef | 18074 | } |
c19d1205 ZW |
18075 | \f |
18076 | /* Table of all register names defined by default. The user can | |
18077 | define additional names with .req. Note that all register names | |
18078 | should appear in both upper and lowercase variants. Some registers | |
18079 | also have mixed-case names. */ | |
b99bd4ef | 18080 | |
dcbf9037 | 18081 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 18082 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 18083 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
18084 | #define REGSET(p,t) \ |
18085 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
18086 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
18087 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
18088 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
18089 | #define REGSETH(p,t) \ |
18090 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
18091 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
18092 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
18093 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
18094 | #define REGSET2(p,t) \ | |
18095 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
18096 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
18097 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
18098 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
18099 | #define SPLRBANK(base,bank,t) \ |
18100 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
18101 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
18102 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
18103 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
18104 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
18105 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 18106 | |
c19d1205 | 18107 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 18108 | { |
c19d1205 ZW |
18109 | /* ARM integer registers. */ |
18110 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 18111 | |
c19d1205 ZW |
18112 | /* ATPCS synonyms. */ |
18113 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
18114 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
18115 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 18116 | |
c19d1205 ZW |
18117 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
18118 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
18119 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 18120 | |
c19d1205 ZW |
18121 | /* Well-known aliases. */ |
18122 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
18123 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
18124 | ||
18125 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
18126 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
18127 | ||
18128 | /* Coprocessor numbers. */ | |
18129 | REGSET(p, CP), REGSET(P, CP), | |
18130 | ||
18131 | /* Coprocessor register numbers. The "cr" variants are for backward | |
18132 | compatibility. */ | |
18133 | REGSET(c, CN), REGSET(C, CN), | |
18134 | REGSET(cr, CN), REGSET(CR, CN), | |
18135 | ||
90ec0d68 MGD |
18136 | /* ARM banked registers. */ |
18137 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
18138 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
18139 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
18140 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
18141 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
18142 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
18143 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
18144 | ||
18145 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
18146 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
18147 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
18148 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
18149 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
1472d06f | 18150 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB), |
90ec0d68 MGD |
18151 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), |
18152 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
18153 | ||
18154 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
18155 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
18156 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
18157 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
18158 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
18159 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
18160 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 18161 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
18162 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
18163 | ||
c19d1205 ZW |
18164 | /* FPA registers. */ |
18165 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
18166 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
18167 | ||
18168 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
18169 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
18170 | ||
18171 | /* VFP SP registers. */ | |
5287ad62 JB |
18172 | REGSET(s,VFS), REGSET(S,VFS), |
18173 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
18174 | |
18175 | /* VFP DP Registers. */ | |
5287ad62 JB |
18176 | REGSET(d,VFD), REGSET(D,VFD), |
18177 | /* Extra Neon DP registers. */ | |
18178 | REGSETH(d,VFD), REGSETH(D,VFD), | |
18179 | ||
18180 | /* Neon QP registers. */ | |
18181 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
18182 | |
18183 | /* VFP control registers. */ | |
18184 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
18185 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
18186 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
18187 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
18188 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
18189 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
18190 | |
18191 | /* Maverick DSP coprocessor registers. */ | |
18192 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
18193 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
18194 | ||
18195 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
18196 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
18197 | REGDEF(dspsc,0,DSPSC), | |
18198 | ||
18199 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
18200 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
18201 | REGDEF(DSPSC,0,DSPSC), | |
18202 | ||
18203 | /* iWMMXt data registers - p0, c0-15. */ | |
18204 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
18205 | ||
18206 | /* iWMMXt control registers - p1, c0-3. */ | |
18207 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
18208 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
18209 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
18210 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
18211 | ||
18212 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
18213 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
18214 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
18215 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
18216 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
18217 | ||
18218 | /* XScale accumulator registers. */ | |
18219 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
18220 | }; | |
18221 | #undef REGDEF | |
18222 | #undef REGNUM | |
18223 | #undef REGSET | |
7ed4c4c5 | 18224 | |
c19d1205 ZW |
18225 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
18226 | within psr_required_here. */ | |
18227 | static const struct asm_psr psrs[] = | |
18228 | { | |
18229 | /* Backward compatibility notation. Note that "all" is no longer | |
18230 | truly all possible PSR bits. */ | |
18231 | {"all", PSR_c | PSR_f}, | |
18232 | {"flg", PSR_f}, | |
18233 | {"ctl", PSR_c}, | |
18234 | ||
18235 | /* Individual flags. */ | |
18236 | {"f", PSR_f}, | |
18237 | {"c", PSR_c}, | |
18238 | {"x", PSR_x}, | |
18239 | {"s", PSR_s}, | |
59b42a0d | 18240 | |
c19d1205 ZW |
18241 | /* Combinations of flags. */ |
18242 | {"fs", PSR_f | PSR_s}, | |
18243 | {"fx", PSR_f | PSR_x}, | |
18244 | {"fc", PSR_f | PSR_c}, | |
18245 | {"sf", PSR_s | PSR_f}, | |
18246 | {"sx", PSR_s | PSR_x}, | |
18247 | {"sc", PSR_s | PSR_c}, | |
18248 | {"xf", PSR_x | PSR_f}, | |
18249 | {"xs", PSR_x | PSR_s}, | |
18250 | {"xc", PSR_x | PSR_c}, | |
18251 | {"cf", PSR_c | PSR_f}, | |
18252 | {"cs", PSR_c | PSR_s}, | |
18253 | {"cx", PSR_c | PSR_x}, | |
18254 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
18255 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
18256 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
18257 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
18258 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
18259 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
18260 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
18261 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
18262 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
18263 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
18264 | {"scf", PSR_s | PSR_c | PSR_f}, | |
18265 | {"scx", PSR_s | PSR_c | PSR_x}, | |
18266 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
18267 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
18268 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
18269 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
18270 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
18271 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
18272 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
18273 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
18274 | {"csf", PSR_c | PSR_s | PSR_f}, | |
18275 | {"csx", PSR_c | PSR_s | PSR_x}, | |
18276 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
18277 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
18278 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
18279 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
18280 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
18281 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
18282 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
18283 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
18284 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
18285 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
18286 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
18287 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
18288 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
18289 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
18290 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
18291 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
18292 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
18293 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
18294 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
18295 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
18296 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
18297 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
18298 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
18299 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
18300 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
18301 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
18302 | }; | |
18303 | ||
62b3e311 PB |
18304 | /* Table of V7M psr names. */ |
18305 | static const struct asm_psr v7m_psrs[] = | |
18306 | { | |
2b744c99 PB |
18307 | {"apsr", 0 }, {"APSR", 0 }, |
18308 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
18309 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
18310 | {"psr", 3 }, {"PSR", 3 }, | |
18311 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
18312 | {"ipsr", 5 }, {"IPSR", 5 }, | |
18313 | {"epsr", 6 }, {"EPSR", 6 }, | |
18314 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
18315 | {"msp", 8 }, {"MSP", 8 }, | |
18316 | {"psp", 9 }, {"PSP", 9 }, | |
18317 | {"primask", 16}, {"PRIMASK", 16}, | |
18318 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
18319 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
18320 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
18321 | {"faultmask", 19}, {"FAULTMASK", 19}, |
18322 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
18323 | }; |
18324 | ||
c19d1205 ZW |
18325 | /* Table of all shift-in-operand names. */ |
18326 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 18327 | { |
c19d1205 ZW |
18328 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
18329 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
18330 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
18331 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
18332 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
18333 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
18334 | }; | |
b99bd4ef | 18335 | |
c19d1205 ZW |
18336 | /* Table of all explicit relocation names. */ |
18337 | #ifdef OBJ_ELF | |
18338 | static struct reloc_entry reloc_names[] = | |
18339 | { | |
18340 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
18341 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
18342 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
18343 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
18344 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
18345 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
18346 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
18347 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
18348 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
18349 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 18350 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
18351 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
18352 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
477330fc | 18353 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, |
0855e32b | 18354 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, |
477330fc | 18355 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, |
0855e32b | 18356 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, |
477330fc | 18357 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} |
c19d1205 ZW |
18358 | }; |
18359 | #endif | |
b99bd4ef | 18360 | |
c19d1205 ZW |
18361 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
18362 | static const struct asm_cond conds[] = | |
18363 | { | |
18364 | {"eq", 0x0}, | |
18365 | {"ne", 0x1}, | |
18366 | {"cs", 0x2}, {"hs", 0x2}, | |
18367 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
18368 | {"mi", 0x4}, | |
18369 | {"pl", 0x5}, | |
18370 | {"vs", 0x6}, | |
18371 | {"vc", 0x7}, | |
18372 | {"hi", 0x8}, | |
18373 | {"ls", 0x9}, | |
18374 | {"ge", 0xa}, | |
18375 | {"lt", 0xb}, | |
18376 | {"gt", 0xc}, | |
18377 | {"le", 0xd}, | |
18378 | {"al", 0xe} | |
18379 | }; | |
bfae80f2 | 18380 | |
e797f7e0 | 18381 | #define UL_BARRIER(L,U,CODE,FEAT) \ |
823d2571 TG |
18382 | { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \ |
18383 | { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) } | |
e797f7e0 | 18384 | |
62b3e311 PB |
18385 | static struct asm_barrier_opt barrier_opt_names[] = |
18386 | { | |
e797f7e0 MGD |
18387 | UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER), |
18388 | UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER), | |
18389 | UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8), | |
18390 | UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER), | |
18391 | UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER), | |
18392 | UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER), | |
18393 | UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER), | |
18394 | UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8), | |
18395 | UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER), | |
18396 | UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER), | |
18397 | UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER), | |
18398 | UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER), | |
18399 | UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8), | |
18400 | UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER), | |
18401 | UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER), | |
18402 | UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8) | |
62b3e311 PB |
18403 | }; |
18404 | ||
e797f7e0 MGD |
18405 | #undef UL_BARRIER |
18406 | ||
c19d1205 ZW |
18407 | /* Table of ARM-format instructions. */ |
18408 | ||
18409 | /* Macros for gluing together operand strings. N.B. In all cases | |
18410 | other than OPS0, the trailing OP_stop comes from default | |
18411 | zero-initialization of the unspecified elements of the array. */ | |
18412 | #define OPS0() { OP_stop, } | |
18413 | #define OPS1(a) { OP_##a, } | |
18414 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
18415 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
18416 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
18417 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
18418 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
18419 | ||
5be8be5d DG |
18420 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
18421 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
18422 | MIX_ARM_THUMB_OPERANDS macro. | |
18423 | In order to use these macros, prefix the number of operands with _ | |
18424 | e.g. _3. */ | |
18425 | #define OPS_1(a) { a, } | |
18426 | #define OPS_2(a,b) { a,b, } | |
18427 | #define OPS_3(a,b,c) { a,b,c, } | |
18428 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
18429 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
18430 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
18431 | ||
c19d1205 ZW |
18432 | /* These macros abstract out the exact format of the mnemonic table and |
18433 | save some repeated characters. */ | |
18434 | ||
18435 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
18436 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18437 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18438 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18439 | |
18440 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
18441 | a T_MNEM_xyz enumerator. */ | |
18442 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 18443 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18444 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18445 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
18446 | |
18447 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
18448 | infix after the third character. */ | |
18449 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18450 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 18451 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 18452 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18453 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 18454 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18455 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18456 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 18457 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 18458 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 18459 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18460 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 18461 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 18462 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 | 18463 | |
c19d1205 | 18464 | /* Mnemonic that cannot be conditionalized. The ARM condition-code |
dfa9f0d5 PB |
18465 | field is still 0xE. Many of the Thumb variants can be executed |
18466 | conditionally, so this is checked separately. */ | |
c19d1205 | 18467 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 18468 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18469 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 18470 | |
dd5181d5 KT |
18471 | /* Same as TUE but the encoding function for ARM and Thumb modes is the same. |
18472 | Used by mnemonics that have very minimal differences in the encoding for | |
18473 | ARM and Thumb variants and can be handled in a common function. */ | |
18474 | #define TUEc(mnem, op, top, nops, ops, en) \ | |
18475 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
18476 | THUMB_VARIANT, do_##en, do_##en } | |
18477 | ||
c19d1205 ZW |
18478 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM |
18479 | condition code field. */ | |
18480 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 18481 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 18482 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
18483 | |
18484 | /* ARM-only variants of all the above. */ | |
6a86118a | 18485 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 18486 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
18487 | |
18488 | #define C3(mnem, op, nops, ops, ae) \ | |
18489 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
18490 | ||
e3cb604e PB |
18491 | /* Legacy mnemonics that always have conditional infix after the third |
18492 | character. */ | |
18493 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18494 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18495 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18496 | ||
8f06b2d8 PB |
18497 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
18498 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18499 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18500 | |
e3cb604e PB |
18501 | /* Legacy coprocessor instructions where conditional infix and conditional |
18502 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
18503 | not just the potentially ambiguous ones. */ | |
18504 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18505 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
18506 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
18507 | ||
18508 | /* Coprocessor, takes either a suffix or a position-3 infix | |
18509 | (for an FPA corner case). */ | |
18510 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 18511 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 18512 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 18513 | |
6a86118a | 18514 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
18515 | { m1 #m2 m3, OPS##nops ops, \ |
18516 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
18517 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
18518 | ||
18519 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
18520 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
18521 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
18522 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
18523 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
18524 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
18525 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
18526 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
18527 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
18528 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
18529 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
18530 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
18531 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
18532 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
18533 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
18534 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
18535 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
18536 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
18537 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
18538 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
18539 | |
18540 | #define UE(mnem, op, nops, ops, ae) \ | |
18541 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18542 | ||
18543 | #define UF(mnem, op, nops, ops, ae) \ | |
18544 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
18545 | ||
5287ad62 JB |
18546 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
18547 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
18548 | use the same encoding function for each. */ | |
18549 | #define NUF(mnem, op, nops, ops, enc) \ | |
18550 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
18551 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
18552 | ||
18553 | /* Neon data processing, version which indirects through neon_enc_tab for | |
18554 | the various overloaded versions of opcodes. */ | |
18555 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 18556 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18557 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18558 | ||
18559 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
18560 | version. */ | |
037e8744 JB |
18561 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
18562 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
18563 | THUMB_VARIANT, do_##enc, do_##enc } |
18564 | ||
037e8744 | 18565 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18566 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18567 | |
18568 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18569 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18570 | |
5287ad62 | 18571 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 18572 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 18573 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
18574 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
18575 | ||
037e8744 | 18576 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 18577 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
18578 | |
18579 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 18580 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 18581 | |
c19d1205 ZW |
18582 | #define do_0 0 |
18583 | ||
c19d1205 | 18584 | static const struct asm_opcode insns[] = |
bfae80f2 | 18585 | { |
74db7efb NC |
18586 | #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */ |
18587 | #define THUMB_VARIANT & arm_ext_v4t | |
21d799b5 NC |
18588 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
18589 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
18590 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
18591 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
18592 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
18593 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
18594 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18595 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
18596 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
18597 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18598 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
18599 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
18600 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
18601 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
18602 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
18603 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
18604 | |
18605 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
18606 | for setting PSR flag bits. They are obsolete in V6 and do not | |
18607 | have Thumb equivalents. */ | |
21d799b5 NC |
18608 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
18609 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
18610 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
18611 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18612 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
18613 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
18614 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18615 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
18616 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
18617 | ||
18618 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
18619 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
18620 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
18621 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
18622 | ||
18623 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
18624 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
18625 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
18626 | OP_RRnpc), | |
18627 | OP_ADDRGLDR),ldst, t_ldst), | |
18628 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
18629 | |
18630 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18631 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18632 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18633 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18634 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18635 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
18636 | ||
18637 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
18638 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
18639 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
18640 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 18641 | |
c19d1205 | 18642 | /* Pseudo ops. */ |
21d799b5 | 18643 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 18644 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 18645 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
74db7efb | 18646 | tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf), |
c19d1205 ZW |
18647 | |
18648 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
18649 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
18650 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
18651 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
18652 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
18653 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
18654 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
18655 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
18656 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
18657 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
18658 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
18659 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
18660 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 18661 | |
16a4cf17 | 18662 | /* These may simplify to neg. */ |
21d799b5 NC |
18663 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
18664 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 18665 | |
c921be7d NC |
18666 | #undef THUMB_VARIANT |
18667 | #define THUMB_VARIANT & arm_ext_v6 | |
18668 | ||
21d799b5 | 18669 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
18670 | |
18671 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
18672 | #undef THUMB_VARIANT |
18673 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18674 | ||
21d799b5 NC |
18675 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
18676 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
18677 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 18678 | |
5be8be5d DG |
18679 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
18680 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
18681 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
18682 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 18683 | |
21d799b5 NC |
18684 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18685 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 18686 | |
21d799b5 NC |
18687 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
18688 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
18689 | |
18690 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 18691 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
18692 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
18693 | ||
18694 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
18695 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
18696 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
18697 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
18698 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
18699 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
18700 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
18701 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
18702 | ||
c921be7d NC |
18703 | #undef ARM_VARIANT |
18704 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
18705 | #undef THUMB_VARIANT | |
18706 | #define THUMB_VARIANT & arm_ext_v4t | |
18707 | ||
21d799b5 NC |
18708 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
18709 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 18710 | |
c921be7d NC |
18711 | #undef THUMB_VARIANT |
18712 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18713 | ||
21d799b5 | 18714 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
18715 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
18716 | ||
18717 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
18718 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
18719 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18720 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18721 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18722 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18723 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 18724 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 18725 | |
c921be7d NC |
18726 | #undef ARM_VARIANT |
18727 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
18728 | ||
21d799b5 | 18729 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
18730 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
18731 | ||
c921be7d NC |
18732 | #undef ARM_VARIANT |
18733 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
18734 | #undef THUMB_VARIANT | |
18735 | #define THUMB_VARIANT & arm_ext_msr | |
18736 | ||
d2cd1205 JB |
18737 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
18738 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 18739 | |
c921be7d NC |
18740 | #undef ARM_VARIANT |
18741 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
18742 | #undef THUMB_VARIANT | |
18743 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18744 | ||
21d799b5 NC |
18745 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
18746 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18747 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18748 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18749 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18750 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
18751 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
18752 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 18753 | |
c921be7d NC |
18754 | #undef ARM_VARIANT |
18755 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
18756 | #undef THUMB_VARIANT | |
18757 | #define THUMB_VARIANT & arm_ext_v4t | |
18758 | ||
5be8be5d DG |
18759 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18760 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18761 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
18762 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
56c0a61f RE |
18763 | tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
18764 | tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 18765 | |
c921be7d NC |
18766 | #undef ARM_VARIANT |
18767 | #define ARM_VARIANT & arm_ext_v4t_5 | |
18768 | ||
c19d1205 ZW |
18769 | /* ARM Architecture 4T. */ |
18770 | /* Note: bx (and blx) are required on V5, even if the processor does | |
18771 | not support Thumb. */ | |
21d799b5 | 18772 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 18773 | |
c921be7d NC |
18774 | #undef ARM_VARIANT |
18775 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
18776 | #undef THUMB_VARIANT | |
18777 | #define THUMB_VARIANT & arm_ext_v5t | |
18778 | ||
c19d1205 ZW |
18779 | /* Note: blx has 2 variants; the .value coded here is for |
18780 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
18781 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
18782 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 18783 | |
c921be7d NC |
18784 | #undef THUMB_VARIANT |
18785 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18786 | ||
21d799b5 NC |
18787 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
18788 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18789 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18790 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18791 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
18792 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
18793 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
18794 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 18795 | |
c921be7d | 18796 | #undef ARM_VARIANT |
74db7efb NC |
18797 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ |
18798 | #undef THUMB_VARIANT | |
18799 | #define THUMB_VARIANT & arm_ext_v5exp | |
c921be7d | 18800 | |
21d799b5 NC |
18801 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18802 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18803 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
18804 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18805 | |
21d799b5 NC |
18806 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
18807 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 18808 | |
21d799b5 NC |
18809 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
18810 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18811 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
18812 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 18813 | |
21d799b5 NC |
18814 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18815 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18816 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18817 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18818 | |
21d799b5 NC |
18819 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
18820 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 18821 | |
03ee1b7f NC |
18822 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
18823 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18824 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
18825 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 18826 | |
c921be7d | 18827 | #undef ARM_VARIANT |
74db7efb NC |
18828 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |
18829 | #undef THUMB_VARIANT | |
18830 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 18831 | |
21d799b5 | 18832 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
18833 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
18834 | ldrd, t_ldstd), | |
18835 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
18836 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 18837 | |
21d799b5 NC |
18838 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18839 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 18840 | |
c921be7d NC |
18841 | #undef ARM_VARIANT |
18842 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
18843 | ||
21d799b5 | 18844 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 18845 | |
c921be7d NC |
18846 | #undef ARM_VARIANT |
18847 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
18848 | #undef THUMB_VARIANT | |
18849 | #define THUMB_VARIANT & arm_ext_v6 | |
18850 | ||
21d799b5 NC |
18851 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
18852 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
18853 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18854 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18855 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
18856 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18857 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18858 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18859 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18860 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 18861 | |
c921be7d NC |
18862 | #undef THUMB_VARIANT |
18863 | #define THUMB_VARIANT & arm_ext_v6t2 | |
18864 | ||
5be8be5d DG |
18865 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
18866 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
18867 | strex, t_strex), | |
21d799b5 NC |
18868 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
18869 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 18870 | |
21d799b5 NC |
18871 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
18872 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 18873 | |
9e3c6df6 | 18874 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
18875 | #undef THUMB_VARIANT |
18876 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 | 18877 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
d709e4e6 | 18878 | TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
9e3c6df6 PB |
18879 | UF(rfeib, 9900a00, 1, (RRw), rfe), |
18880 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
18881 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18882 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
d709e4e6 RE |
18883 | UF(rfefa, 8100a00, 1, (RRw), rfe), |
18884 | TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
18885 | UF(rfeed, 9900a00, 1, (RRw), rfe), | |
9e3c6df6 | 18886 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 RE |
18887 | TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), |
18888 | TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
9e3c6df6 | 18889 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18890 | UF(srsfa, 9c00500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18891 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), |
d709e4e6 | 18892 | UF(srsed, 8400500, 2, (oRRw, I31w), srs), |
9e3c6df6 | 18893 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
d709e4e6 | 18894 | TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), |
c921be7d | 18895 | |
9e3c6df6 PB |
18896 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
18897 | #undef THUMB_VARIANT | |
18898 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
18899 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
18900 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
18901 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
18902 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18903 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18904 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18905 | /* Old name for QASX. */ |
74db7efb | 18906 | TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18907 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18908 | /* Old name for QSAX. */ |
74db7efb | 18909 | TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18910 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18911 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18912 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18913 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18914 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18915 | /* Old name for SASX. */ |
74db7efb | 18916 | TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18917 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18918 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18919 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18920 | /* Old name for SHASX. */ |
21d799b5 | 18921 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
74db7efb | 18922 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18923 | /* Old name for SHSAX. */ |
21d799b5 NC |
18924 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18925 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18926 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18927 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18928 | /* Old name for SSAX. */ |
74db7efb | 18929 | TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18930 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18931 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18932 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18933 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18934 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18935 | /* Old name for UASX. */ |
74db7efb | 18936 | TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18937 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18938 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18939 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18940 | /* Old name for UHASX. */ |
21d799b5 NC |
18941 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18942 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18943 | /* Old name for UHSAX. */ |
21d799b5 NC |
18944 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18945 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18946 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18947 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18948 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
74db7efb | 18949 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
4f80ef3e | 18950 | /* Old name for UQASX. */ |
21d799b5 NC |
18951 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18952 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18953 | /* Old name for UQSAX. */ |
21d799b5 NC |
18954 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
18955 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18956 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18957 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18958 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 18959 | /* Old name for USAX. */ |
74db7efb | 18960 | TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 | 18961 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
21d799b5 NC |
18962 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
18963 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18964 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18965 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18966 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18967 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18968 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
18969 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
18970 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
18971 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18972 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18973 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18974 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18975 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18976 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18977 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18978 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
18979 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18980 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18981 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18982 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18983 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18984 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18985 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18986 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18987 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18988 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
18989 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
18990 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
18991 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
18992 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
18993 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 18994 | |
c921be7d NC |
18995 | #undef ARM_VARIANT |
18996 | #define ARM_VARIANT & arm_ext_v6k | |
18997 | #undef THUMB_VARIANT | |
18998 | #define THUMB_VARIANT & arm_ext_v6k | |
18999 | ||
21d799b5 NC |
19000 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
19001 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
19002 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
19003 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 19004 | |
c921be7d NC |
19005 | #undef THUMB_VARIANT |
19006 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
19007 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
19008 | ldrexd, t_ldrexd), | |
19009 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
19010 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 19011 | |
c921be7d NC |
19012 | #undef THUMB_VARIANT |
19013 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
19014 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
19015 | rd_rn, rd_rn), | |
19016 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
19017 | rd_rn, rd_rn), | |
19018 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 19019 | strex, t_strexbh), |
5be8be5d | 19020 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 19021 | strex, t_strexbh), |
21d799b5 | 19022 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 19023 | |
c921be7d | 19024 | #undef ARM_VARIANT |
f4c65163 | 19025 | #define ARM_VARIANT & arm_ext_sec |
74db7efb | 19026 | #undef THUMB_VARIANT |
f4c65163 | 19027 | #define THUMB_VARIANT & arm_ext_sec |
c921be7d | 19028 | |
21d799b5 | 19029 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 19030 | |
90ec0d68 MGD |
19031 | #undef ARM_VARIANT |
19032 | #define ARM_VARIANT & arm_ext_virt | |
19033 | #undef THUMB_VARIANT | |
19034 | #define THUMB_VARIANT & arm_ext_virt | |
19035 | ||
19036 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
19037 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
19038 | ||
ddfded2f MW |
19039 | #undef ARM_VARIANT |
19040 | #define ARM_VARIANT & arm_ext_pan | |
19041 | #undef THUMB_VARIANT | |
19042 | #define THUMB_VARIANT & arm_ext_pan | |
19043 | ||
19044 | TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan), | |
19045 | ||
c921be7d | 19046 | #undef ARM_VARIANT |
74db7efb | 19047 | #define ARM_VARIANT & arm_ext_v6t2 |
f4c65163 MGD |
19048 | #undef THUMB_VARIANT |
19049 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 19050 | |
21d799b5 NC |
19051 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
19052 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
19053 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
19054 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 19055 | |
21d799b5 NC |
19056 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
19057 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
19058 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
19059 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 19060 | |
5be8be5d DG |
19061 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
19062 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
19063 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
19064 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 19065 | |
bf3eeda7 | 19066 | /* Thumb-only instructions. */ |
74db7efb | 19067 | #undef ARM_VARIANT |
bf3eeda7 NS |
19068 | #define ARM_VARIANT NULL |
19069 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
19070 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
19071 | |
19072 | /* ARM does not really have an IT instruction, so always allow it. | |
19073 | The opcode is copied from Thumb in order to allow warnings in | |
19074 | -mimplicit-it=[never | arm] modes. */ | |
19075 | #undef ARM_VARIANT | |
19076 | #define ARM_VARIANT & arm_ext_v1 | |
19077 | ||
21d799b5 NC |
19078 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
19079 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
19080 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
19081 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
19082 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
19083 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
19084 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
19085 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
19086 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
19087 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
19088 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
19089 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
19090 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
19091 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
19092 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 19093 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
19094 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
19095 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 19096 | |
92e90b6e | 19097 | /* Thumb2 only instructions. */ |
c921be7d NC |
19098 | #undef ARM_VARIANT |
19099 | #define ARM_VARIANT NULL | |
92e90b6e | 19100 | |
21d799b5 NC |
19101 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
19102 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
19103 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
19104 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
19105 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
19106 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 19107 | |
eea54501 MGD |
19108 | /* Hardware division instructions. */ |
19109 | #undef ARM_VARIANT | |
19110 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
19111 | #undef THUMB_VARIANT |
19112 | #define THUMB_VARIANT & arm_ext_div | |
19113 | ||
eea54501 MGD |
19114 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
19115 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 19116 | |
7e806470 | 19117 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
19118 | #undef ARM_VARIANT |
19119 | #define ARM_VARIANT & arm_ext_barrier | |
19120 | #undef THUMB_VARIANT | |
19121 | #define THUMB_VARIANT & arm_ext_barrier | |
19122 | ||
ccb84d65 JB |
19123 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier), |
19124 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier), | |
19125 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier), | |
7e806470 | 19126 | |
62b3e311 | 19127 | /* ARM V7 instructions. */ |
c921be7d NC |
19128 | #undef ARM_VARIANT |
19129 | #define ARM_VARIANT & arm_ext_v7 | |
19130 | #undef THUMB_VARIANT | |
19131 | #define THUMB_VARIANT & arm_ext_v7 | |
19132 | ||
21d799b5 NC |
19133 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
19134 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 19135 | |
74db7efb | 19136 | #undef ARM_VARIANT |
60e5ef9f | 19137 | #define ARM_VARIANT & arm_ext_mp |
74db7efb | 19138 | #undef THUMB_VARIANT |
60e5ef9f MGD |
19139 | #define THUMB_VARIANT & arm_ext_mp |
19140 | ||
19141 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
19142 | ||
53c4b28b MGD |
19143 | /* AArchv8 instructions. */ |
19144 | #undef ARM_VARIANT | |
19145 | #define ARM_VARIANT & arm_ext_v8 | |
19146 | #undef THUMB_VARIANT | |
19147 | #define THUMB_VARIANT & arm_ext_v8 | |
19148 | ||
19149 | tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), | |
8884b720 | 19150 | TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), |
4b8c8c02 RE |
19151 | TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
19152 | TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 19153 | ldrexd, t_ldrexd), |
4b8c8c02 RE |
19154 | TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), |
19155 | TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19156 | TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), | |
19157 | stlex, t_stlex), | |
19158 | TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), | |
9eb6c0f1 | 19159 | strexd, t_strexd), |
4b8c8c02 RE |
19160 | TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), |
19161 | stlex, t_stlex), | |
19162 | TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), | |
19163 | stlex, t_stlex), | |
19164 | TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19165 | TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19166 | TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
19167 | TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
19168 | TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
19169 | TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), | |
53c4b28b | 19170 | |
8884b720 | 19171 | /* ARMv8 T32 only. */ |
74db7efb | 19172 | #undef ARM_VARIANT |
b79f7053 MGD |
19173 | #define ARM_VARIANT NULL |
19174 | TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs), | |
19175 | TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), | |
19176 | TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), | |
19177 | ||
33399f07 MGD |
19178 | /* FP for ARMv8. */ |
19179 | #undef ARM_VARIANT | |
a715796b | 19180 | #define ARM_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 | 19181 | #undef THUMB_VARIANT |
a715796b | 19182 | #define THUMB_VARIANT & fpu_vfp_ext_armv8xd |
33399f07 MGD |
19183 | |
19184 | nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), | |
19185 | nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), | |
19186 | nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), | |
19187 | nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), | |
73924fbc MGD |
19188 | nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), |
19189 | nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), | |
7e8e6784 MGD |
19190 | nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta), |
19191 | nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn), | |
19192 | nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp), | |
19193 | nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm), | |
30bdf752 MGD |
19194 | nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), |
19195 | nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), | |
19196 | nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), | |
19197 | nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), | |
19198 | nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), | |
19199 | nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), | |
19200 | nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), | |
33399f07 | 19201 | |
91ff7894 MGD |
19202 | /* Crypto v1 extensions. */ |
19203 | #undef ARM_VARIANT | |
19204 | #define ARM_VARIANT & fpu_crypto_ext_armv8 | |
19205 | #undef THUMB_VARIANT | |
19206 | #define THUMB_VARIANT & fpu_crypto_ext_armv8 | |
19207 | ||
19208 | nUF(aese, _aes, 2, (RNQ, RNQ), aese), | |
19209 | nUF(aesd, _aes, 2, (RNQ, RNQ), aesd), | |
19210 | nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc), | |
19211 | nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc), | |
48adcd8e MGD |
19212 | nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c), |
19213 | nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p), | |
19214 | nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m), | |
19215 | nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0), | |
19216 | nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h), | |
19217 | nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2), | |
19218 | nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1), | |
3c9017d2 MGD |
19219 | nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h), |
19220 | nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1), | |
19221 | nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0), | |
91ff7894 | 19222 | |
dd5181d5 | 19223 | #undef ARM_VARIANT |
74db7efb | 19224 | #define ARM_VARIANT & crc_ext_armv8 |
dd5181d5 KT |
19225 | #undef THUMB_VARIANT |
19226 | #define THUMB_VARIANT & crc_ext_armv8 | |
19227 | TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b), | |
19228 | TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h), | |
19229 | TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w), | |
19230 | TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb), | |
19231 | TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), | |
19232 | TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), | |
19233 | ||
c921be7d NC |
19234 | #undef ARM_VARIANT |
19235 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
53c4b28b MGD |
19236 | #undef THUMB_VARIANT |
19237 | #define THUMB_VARIANT NULL | |
c921be7d | 19238 | |
21d799b5 NC |
19239 | cCE("wfs", e200110, 1, (RR), rd), |
19240 | cCE("rfs", e300110, 1, (RR), rd), | |
19241 | cCE("wfc", e400110, 1, (RR), rd), | |
19242 | cCE("rfc", e500110, 1, (RR), rd), | |
19243 | ||
19244 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19245 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19246 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19247 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19248 | ||
19249 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19250 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19251 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19252 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
19253 | ||
19254 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
19255 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
19256 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
19257 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
19258 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
19259 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
19260 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
19261 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
19262 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
19263 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
19264 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
19265 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
19266 | ||
19267 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
19268 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
19269 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
19270 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
19271 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
19272 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
19273 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
19274 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
19275 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
19276 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
19277 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
19278 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
19279 | ||
19280 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
19281 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
19282 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
19283 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
19284 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
19285 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
19286 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
19287 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
19288 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
19289 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
19290 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
19291 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
19292 | ||
19293 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
19294 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
19295 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
19296 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
19297 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
19298 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
19299 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
19300 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
19301 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
19302 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
19303 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
19304 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
19305 | ||
19306 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
19307 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
19308 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
19309 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
19310 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
19311 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
19312 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
19313 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
19314 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
19315 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
19316 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
19317 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
19318 | ||
19319 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
19320 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
19321 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
19322 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
19323 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
19324 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
19325 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
19326 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
19327 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
19328 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
19329 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
19330 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
19331 | ||
19332 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
19333 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
19334 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
19335 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
19336 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
19337 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
19338 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
19339 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
19340 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
19341 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
19342 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
19343 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
19344 | ||
19345 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
19346 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
19347 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
19348 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
19349 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
19350 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
19351 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
19352 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
19353 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
19354 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
19355 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
19356 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
19357 | ||
19358 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
19359 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
19360 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
19361 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
19362 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
19363 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
19364 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
19365 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
19366 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
19367 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
19368 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
19369 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
19370 | ||
19371 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
19372 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
19373 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
19374 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
19375 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
19376 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
19377 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
19378 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
19379 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
19380 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
19381 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
19382 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
19383 | ||
19384 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
19385 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
19386 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
19387 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
19388 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
19389 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
19390 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
19391 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
19392 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
19393 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
19394 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
19395 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
19396 | ||
19397 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
19398 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
19399 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
19400 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
19401 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
19402 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
19403 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
19404 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
19405 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
19406 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
19407 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
19408 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
19409 | ||
19410 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
19411 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
19412 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
19413 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
19414 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
19415 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
19416 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
19417 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
19418 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
19419 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
19420 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
19421 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
19422 | ||
19423 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
19424 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
19425 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
19426 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
19427 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
19428 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
19429 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
19430 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
19431 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
19432 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
19433 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
19434 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
19435 | ||
19436 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
19437 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
19438 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
19439 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
19440 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
19441 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
19442 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
19443 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
19444 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
19445 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
19446 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
19447 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
19448 | ||
19449 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
19450 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
19451 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
19452 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
19453 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
19454 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
19455 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
19456 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
19457 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
19458 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
19459 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
19460 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
19461 | ||
19462 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19463 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19464 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19465 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19466 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19467 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19468 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19469 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19470 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19471 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19472 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19473 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19474 | ||
19475 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19476 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19477 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19478 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19479 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19480 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19481 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19482 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19483 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19484 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19485 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19486 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19487 | ||
19488 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19489 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19490 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19491 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19492 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19493 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19494 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19495 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19496 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19497 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19498 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19499 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19500 | ||
19501 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19502 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19503 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19504 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19505 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19506 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19507 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19508 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19509 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19510 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19511 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19512 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19513 | ||
19514 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19515 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19516 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19517 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19518 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19519 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19520 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19521 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19522 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19523 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19524 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19525 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19526 | ||
19527 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19528 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19529 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19530 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19531 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19532 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19533 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19534 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19535 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19536 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19537 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19538 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19539 | ||
19540 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19541 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19542 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19543 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19544 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19545 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19546 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19547 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19548 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19549 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19550 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19551 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19552 | ||
19553 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19554 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19555 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19556 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19557 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19558 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19559 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19560 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19561 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19562 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19563 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19564 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19565 | ||
19566 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19567 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19568 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19569 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19570 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19571 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19572 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19573 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19574 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19575 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19576 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19577 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19578 | ||
19579 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19580 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19581 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19582 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19583 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19584 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19585 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19586 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19587 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19588 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19589 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19590 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19591 | ||
19592 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19593 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19594 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19595 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19596 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19597 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19598 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19599 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19600 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19601 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19602 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19603 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19604 | ||
19605 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19606 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19607 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19608 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19609 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19610 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19611 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19612 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19613 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19614 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19615 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19616 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19617 | ||
19618 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19619 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19620 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19621 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19622 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19623 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19624 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19625 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19626 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19627 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19628 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19629 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
19630 | ||
19631 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
19632 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
19633 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
19634 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
19635 | ||
19636 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
19637 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
19638 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
19639 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
19640 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
19641 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
19642 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
19643 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
19644 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
19645 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
19646 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
19647 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 19648 | |
c19d1205 ZW |
19649 | /* The implementation of the FIX instruction is broken on some |
19650 | assemblers, in that it accepts a precision specifier as well as a | |
19651 | rounding specifier, despite the fact that this is meaningless. | |
19652 | To be more compatible, we accept it as well, though of course it | |
19653 | does not set any bits. */ | |
21d799b5 NC |
19654 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
19655 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
19656 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
19657 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
19658 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
19659 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
19660 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
19661 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
19662 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
19663 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
19664 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
19665 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
19666 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 19667 | |
c19d1205 | 19668 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
19669 | #undef ARM_VARIANT |
19670 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
19671 | ||
21d799b5 NC |
19672 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
19673 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19674 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19675 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19676 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
19677 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 19678 | |
c921be7d NC |
19679 | #undef ARM_VARIANT |
19680 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
19681 | ||
c19d1205 | 19682 | /* Moves and type conversions. */ |
21d799b5 NC |
19683 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
19684 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
19685 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
19686 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
19687 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
19688 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
19689 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19690 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19691 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19692 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19693 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19694 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19695 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
19696 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
19697 | |
19698 | /* Memory operations. */ | |
21d799b5 NC |
19699 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
19700 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
19701 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
19702 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19703 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19704 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19705 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19706 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19707 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19708 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19709 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19710 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
19711 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19712 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
19713 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19714 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
19715 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
19716 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 19717 | |
c19d1205 | 19718 | /* Monadic operations. */ |
21d799b5 NC |
19719 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
19720 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
19721 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
19722 | |
19723 | /* Dyadic operations. */ | |
21d799b5 NC |
19724 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
19725 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19726 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19727 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19728 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19729 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19730 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19731 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
19732 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 19733 | |
c19d1205 | 19734 | /* Comparisons. */ |
21d799b5 NC |
19735 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
19736 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
19737 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
19738 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 19739 | |
62f3b8c8 PB |
19740 | /* Double precision load/store are still present on single precision |
19741 | implementations. */ | |
19742 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
19743 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
19744 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
19745 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19746 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19747 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19748 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19749 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
19750 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
19751 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 19752 | |
c921be7d NC |
19753 | #undef ARM_VARIANT |
19754 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
19755 | ||
c19d1205 | 19756 | /* Moves and type conversions. */ |
21d799b5 NC |
19757 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19758 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19759 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19760 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19761 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
19762 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19763 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
19764 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19765 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
19766 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19767 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19768 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
19769 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 19770 | |
c19d1205 | 19771 | /* Monadic operations. */ |
21d799b5 NC |
19772 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
19773 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19774 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
19775 | |
19776 | /* Dyadic operations. */ | |
21d799b5 NC |
19777 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
19778 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19779 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19780 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19781 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19782 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19783 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19784 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
19785 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 19786 | |
c19d1205 | 19787 | /* Comparisons. */ |
21d799b5 NC |
19788 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
19789 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
19790 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
19791 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 19792 | |
c921be7d NC |
19793 | #undef ARM_VARIANT |
19794 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
19795 | ||
21d799b5 NC |
19796 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
19797 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
19798 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
19799 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 19800 | |
037e8744 JB |
19801 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
19802 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
19803 | #undef ARM_VARIANT |
19804 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
19805 | #undef THUMB_VARIANT | |
19806 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
19807 | ||
037e8744 JB |
19808 | /* These mnemonics are unique to VFP. */ |
19809 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
19810 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
19811 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
19812 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
19813 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
aacf0b33 KT |
19814 | nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), |
19815 | nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp), | |
037e8744 JB |
19816 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
19817 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
19818 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
19819 | ||
19820 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
19821 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
19822 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
19823 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 19824 | |
21d799b5 NC |
19825 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
19826 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
19827 | |
19828 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19829 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
19830 | ||
55881a11 MGD |
19831 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
19832 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19833 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19834 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19835 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
19836 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
19837 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
19838 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 19839 | |
5f1af56b | 19840 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 19841 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
c70a8987 MGD |
19842 | NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb), |
19843 | NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt), | |
f31fef98 | 19844 | |
037e8744 JB |
19845 | |
19846 | /* NOTE: All VMOV encoding is special-cased! */ | |
19847 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
19848 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
19849 | ||
c921be7d NC |
19850 | #undef THUMB_VARIANT |
19851 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
19852 | #undef ARM_VARIANT | |
19853 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
19854 | ||
5287ad62 JB |
19855 | /* Data processing with three registers of the same length. */ |
19856 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
19857 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
19858 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
19859 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19860 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19861 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19862 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19863 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
19864 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
19865 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19866 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19867 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
19868 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
19869 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
19870 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
19871 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
19872 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
19873 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
19874 | /* If not immediate, fall back to neon_dyadic_i64_su. |
19875 | shl_imm should accept I8 I16 I32 I64, | |
19876 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
19877 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
19878 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
19879 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
19880 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 19881 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
19882 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
19883 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19884 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19885 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19886 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19887 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19888 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
19889 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
19890 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
19891 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
19892 | /* Bitfield ops, untyped. */ |
19893 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19894 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19895 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19896 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19897 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
19898 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
19899 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
19900 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
19901 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19902 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19903 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
19904 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
19905 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
19906 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
19907 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
19908 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
19909 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19910 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
19911 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
19912 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19913 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
19914 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
19915 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 19916 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
19917 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
19918 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 19919 | /* As above, D registers only. */ |
21d799b5 NC |
19920 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
19921 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 19922 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
19923 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
19924 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
19925 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 19926 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
19927 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
19928 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
19929 | /* vtst takes sizes 8, 16, 32. */ |
19930 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
19931 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
19932 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 19933 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 19934 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
19935 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
19936 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
19937 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
19938 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
19939 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
19940 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
19941 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
19942 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
19943 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
19944 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
19945 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
19946 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
19947 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
19948 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
19949 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
19950 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
d6b4b13e MW |
19951 | /* ARM v8.1 extension. */ |
19952 | nUF(vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
19953 | nUF(vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
19954 | nUF(vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
19955 | nUF(vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
19956 | |
19957 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 19958 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
19959 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
19960 | ||
19961 | /* Data processing with two registers and a shift amount. */ | |
19962 | /* Right shifts, and variants with rounding. | |
19963 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19964 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
19965 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
19966 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
19967 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
19968 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
19969 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
19970 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
19971 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
19972 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
19973 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
19974 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
19975 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
19976 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
19977 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
19978 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
19979 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
19980 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
19981 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
19982 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
19983 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
19984 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
19985 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
19986 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
19987 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
19988 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
19989 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
19990 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 19991 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 19992 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 19993 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 19994 | |
4316f0d2 DG |
19995 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
19996 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
19997 | |
19998 | /* Data processing, three registers of different lengths. */ | |
19999 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
20000 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
20001 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
20002 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
20003 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
20004 | /* If not scalar, fall back to neon_dyadic_long. | |
20005 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
20006 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
20007 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
20008 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
20009 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
20010 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
20011 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
20012 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20013 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20014 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20015 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
20016 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
20017 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
20018 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
20019 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
20020 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
20021 | S16 S32 U16 U32. */ | |
21d799b5 | 20022 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
20023 | |
20024 | /* Extract. Size 8. */ | |
3b8d421e PB |
20025 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
20026 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
20027 | |
20028 | /* Two registers, miscellaneous. */ | |
20029 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
20030 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
20031 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
20032 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
20033 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
20034 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
20035 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
20036 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
20037 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
20038 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
20039 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
20040 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
20041 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 20042 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 20043 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 20044 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 20045 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 20046 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
20047 | /* VZIP / VUZP. Sizes 8 16 32. */ |
20048 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
20049 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
20050 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
20051 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
20052 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
20053 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
20054 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
20055 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
20056 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
20057 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
20058 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
20059 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
20060 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
20061 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
20062 | /* Reciprocal estimates. Types U32 F32. */ | |
20063 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
20064 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
20065 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
20066 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
20067 | /* VCLS. Types S8 S16 S32. */ | |
20068 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
20069 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
20070 | /* VCLZ. Types I8 I16 I32. */ | |
20071 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
20072 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
20073 | /* VCNT. Size 8. */ | |
20074 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
20075 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
20076 | /* Two address, untyped. */ | |
20077 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
20078 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
20079 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
20080 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
20081 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
20082 | |
20083 | /* Table lookup. Size 8. */ | |
20084 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
20085 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
20086 | ||
c921be7d NC |
20087 | #undef THUMB_VARIANT |
20088 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
20089 | #undef ARM_VARIANT | |
20090 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
20091 | ||
5287ad62 | 20092 | /* Neon element/structure load/store. */ |
21d799b5 NC |
20093 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
20094 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20095 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20096 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20097 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20098 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20099 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
20100 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 20101 | |
c921be7d | 20102 | #undef THUMB_VARIANT |
74db7efb NC |
20103 | #define THUMB_VARIANT & fpu_vfp_ext_v3xd |
20104 | #undef ARM_VARIANT | |
20105 | #define ARM_VARIANT & fpu_vfp_ext_v3xd | |
62f3b8c8 PB |
20106 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), |
20107 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20108 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20109 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20110 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20111 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20112 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20113 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
20114 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
20115 | ||
74db7efb | 20116 | #undef THUMB_VARIANT |
c921be7d NC |
20117 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
20118 | #undef ARM_VARIANT | |
20119 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
20120 | ||
21d799b5 | 20121 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 20122 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20123 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 20124 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20125 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 20126 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20127 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 20128 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 20129 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 20130 | |
74db7efb NC |
20131 | #undef ARM_VARIANT |
20132 | #define ARM_VARIANT & fpu_vfp_ext_fma | |
20133 | #undef THUMB_VARIANT | |
20134 | #define THUMB_VARIANT & fpu_vfp_ext_fma | |
62f3b8c8 PB |
20135 | /* Mnemonics shared by Neon and VFP. These are included in the |
20136 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
20137 | FMA instructions. */ | |
20138 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
20139 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
20140 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
20141 | the v form should always be used. */ | |
20142 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20143 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
20144 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20145 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
20146 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
20147 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
20148 | ||
5287ad62 | 20149 | #undef THUMB_VARIANT |
c921be7d NC |
20150 | #undef ARM_VARIANT |
20151 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
20152 | ||
21d799b5 NC |
20153 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
20154 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20155 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20156 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20157 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20158 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
20159 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
20160 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 20161 | |
c921be7d NC |
20162 | #undef ARM_VARIANT |
20163 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
20164 | ||
21d799b5 NC |
20165 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
20166 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
20167 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
20168 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
20169 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
20170 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
20171 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
20172 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
20173 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
74db7efb NC |
20174 | cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), |
20175 | cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20176 | cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20177 | cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20178 | cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
20179 | cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
21d799b5 NC |
20180 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), |
20181 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
20182 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
20183 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
20184 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
20185 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20186 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20187 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20188 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20189 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
20190 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
74db7efb NC |
20191 | cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn), |
20192 | cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn), | |
20193 | cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn), | |
21d799b5 NC |
20194 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), |
20195 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
20196 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
20197 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
20198 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
20199 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
20200 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
20201 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
20202 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20203 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20204 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20205 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20206 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20207 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20208 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20209 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20210 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20211 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
74db7efb NC |
20212 | cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20213 | cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20214 | cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20215 | cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20216 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20217 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20218 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20219 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20220 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20221 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20222 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20223 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20224 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20225 | cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20226 | cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20227 | cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20228 | cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20229 | cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20230 | cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20231 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), |
20232 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20233 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20234 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20235 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20236 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20237 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20238 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20239 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20240 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20241 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20242 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20243 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20244 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20245 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20246 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20247 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20248 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20249 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20250 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20251 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20252 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20253 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
20254 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20255 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20256 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20257 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20258 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
74db7efb NC |
20259 | cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), |
20260 | cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20261 | cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20262 | cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20263 | cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20264 | cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
21d799b5 NC |
20265 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), |
20266 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20267 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20268 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20269 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20270 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20271 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20272 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20273 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20274 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20275 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
20276 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20277 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20278 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20279 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20280 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20281 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20282 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20283 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20284 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20285 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20286 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20287 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20288 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20289 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20290 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20291 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20292 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
20293 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
20294 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20295 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
20296 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
20297 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
20298 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20299 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20300 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20301 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20302 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20303 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20304 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20305 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20306 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20307 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
20308 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
20309 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
20310 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
20311 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
20312 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
20313 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20314 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20315 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20316 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
20317 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
20318 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
20319 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
20320 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
20321 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
20322 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20323 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20324 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20325 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20326 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 20327 | |
c921be7d NC |
20328 | #undef ARM_VARIANT |
20329 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
20330 | ||
21d799b5 NC |
20331 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
20332 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
20333 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
20334 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
20335 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
20336 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
20337 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20338 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20339 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20340 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20341 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20342 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20343 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20344 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20345 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20346 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20347 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20348 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20349 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20350 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20351 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
20352 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20353 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20354 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20355 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20356 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20357 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20358 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20359 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20360 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20361 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20362 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20363 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20364 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20365 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20366 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20367 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20368 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20369 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20370 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20371 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20372 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20373 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20374 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20375 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20376 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20377 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20378 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20379 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20380 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20381 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20382 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20383 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20384 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20385 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20386 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
20387 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 20388 | |
c921be7d NC |
20389 | #undef ARM_VARIANT |
20390 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
20391 | ||
21d799b5 NC |
20392 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
20393 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20394 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20395 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20396 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
20397 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
20398 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
20399 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
20400 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
20401 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
20402 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
20403 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
20404 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
20405 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
74db7efb NC |
20406 | cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd), |
20407 | cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn), | |
20408 | cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd), | |
20409 | cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn), | |
20410 | cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn), | |
20411 | cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn), | |
20412 | cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn), | |
20413 | cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn), | |
20414 | cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn), | |
20415 | cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn), | |
21d799b5 NC |
20416 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), |
20417 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
20418 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
20419 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
74db7efb NC |
20420 | cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc), |
20421 | cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd), | |
21d799b5 NC |
20422 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), |
20423 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
20424 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
20425 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
74db7efb NC |
20426 | cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn), |
20427 | cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn), | |
20428 | cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn), | |
20429 | cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn), | |
20430 | cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn), | |
20431 | cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn), | |
21d799b5 NC |
20432 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), |
20433 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
74db7efb NC |
20434 | cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple), |
20435 | cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
21d799b5 NC |
20436 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), |
20437 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
20438 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
20439 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
20440 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
20441 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
20442 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
20443 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
20444 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
20445 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
20446 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20447 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20448 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20449 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20450 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
20451 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
20452 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
20453 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
20454 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
20455 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
20456 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20457 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20458 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20459 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20460 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20461 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
20462 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
20463 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
74db7efb NC |
20464 | cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), |
20465 | cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
21d799b5 NC |
20466 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), |
20467 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
20468 | }; |
20469 | #undef ARM_VARIANT | |
20470 | #undef THUMB_VARIANT | |
20471 | #undef TCE | |
c19d1205 ZW |
20472 | #undef TUE |
20473 | #undef TUF | |
20474 | #undef TCC | |
8f06b2d8 | 20475 | #undef cCE |
e3cb604e PB |
20476 | #undef cCL |
20477 | #undef C3E | |
c19d1205 ZW |
20478 | #undef CE |
20479 | #undef CM | |
20480 | #undef UE | |
20481 | #undef UF | |
20482 | #undef UT | |
5287ad62 JB |
20483 | #undef NUF |
20484 | #undef nUF | |
20485 | #undef NCE | |
20486 | #undef nCE | |
c19d1205 ZW |
20487 | #undef OPS0 |
20488 | #undef OPS1 | |
20489 | #undef OPS2 | |
20490 | #undef OPS3 | |
20491 | #undef OPS4 | |
20492 | #undef OPS5 | |
20493 | #undef OPS6 | |
20494 | #undef do_0 | |
20495 | \f | |
20496 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 20497 | |
c19d1205 ZW |
20498 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
20499 | for use in the a.out file, and stores them in the array pointed to by buf. | |
20500 | This knows about the endian-ness of the target machine and does | |
20501 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
20502 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
20503 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 20504 | |
c19d1205 ZW |
20505 | void |
20506 | md_number_to_chars (char * buf, valueT val, int n) | |
20507 | { | |
20508 | if (target_big_endian) | |
20509 | number_to_chars_bigendian (buf, val, n); | |
20510 | else | |
20511 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
20512 | } |
20513 | ||
c19d1205 ZW |
20514 | static valueT |
20515 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 20516 | { |
c19d1205 ZW |
20517 | valueT result = 0; |
20518 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 20519 | |
c19d1205 | 20520 | if (target_big_endian) |
b99bd4ef | 20521 | { |
c19d1205 ZW |
20522 | while (n--) |
20523 | { | |
20524 | result <<= 8; | |
20525 | result |= (*where++ & 255); | |
20526 | } | |
b99bd4ef | 20527 | } |
c19d1205 | 20528 | else |
b99bd4ef | 20529 | { |
c19d1205 ZW |
20530 | while (n--) |
20531 | { | |
20532 | result <<= 8; | |
20533 | result |= (where[n] & 255); | |
20534 | } | |
bfae80f2 | 20535 | } |
b99bd4ef | 20536 | |
c19d1205 | 20537 | return result; |
bfae80f2 | 20538 | } |
b99bd4ef | 20539 | |
c19d1205 | 20540 | /* MD interface: Sections. */ |
b99bd4ef | 20541 | |
fa94de6b RM |
20542 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
20543 | that an rs_machine_dependent frag may reach. */ | |
20544 | ||
20545 | unsigned int | |
20546 | arm_frag_max_var (fragS *fragp) | |
20547 | { | |
20548 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
20549 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
20550 | ||
20551 | Note that we generate relaxable instructions even for cases that don't | |
20552 | really need it, like an immediate that's a trivial constant. So we're | |
20553 | overestimating the instruction size for some of those cases. Rather | |
20554 | than putting more intelligence here, it would probably be better to | |
20555 | avoid generating a relaxation frag in the first place when it can be | |
20556 | determined up front that a short instruction will suffice. */ | |
20557 | ||
20558 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
20559 | return INSN_SIZE; | |
20560 | } | |
20561 | ||
0110f2b8 PB |
20562 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
20563 | 2 bytes. */ | |
20564 | ||
c19d1205 | 20565 | int |
0110f2b8 | 20566 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
20567 | segT segtype ATTRIBUTE_UNUSED) |
20568 | { | |
0110f2b8 PB |
20569 | fragp->fr_var = 2; |
20570 | return 2; | |
20571 | } | |
20572 | ||
20573 | /* Convert a machine dependent frag. */ | |
20574 | ||
20575 | void | |
20576 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
20577 | { | |
20578 | unsigned long insn; | |
20579 | unsigned long old_op; | |
20580 | char *buf; | |
20581 | expressionS exp; | |
20582 | fixS *fixp; | |
20583 | int reloc_type; | |
20584 | int pc_rel; | |
20585 | int opcode; | |
20586 | ||
20587 | buf = fragp->fr_literal + fragp->fr_fix; | |
20588 | ||
20589 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
20590 | if (fragp->fr_symbol) |
20591 | { | |
0110f2b8 PB |
20592 | exp.X_op = O_symbol; |
20593 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
20594 | } |
20595 | else | |
20596 | { | |
0110f2b8 | 20597 | exp.X_op = O_constant; |
5f4273c7 | 20598 | } |
0110f2b8 PB |
20599 | exp.X_add_number = fragp->fr_offset; |
20600 | opcode = fragp->fr_subtype; | |
20601 | switch (opcode) | |
20602 | { | |
20603 | case T_MNEM_ldr_pc: | |
20604 | case T_MNEM_ldr_pc2: | |
20605 | case T_MNEM_ldr_sp: | |
20606 | case T_MNEM_str_sp: | |
20607 | case T_MNEM_ldr: | |
20608 | case T_MNEM_ldrb: | |
20609 | case T_MNEM_ldrh: | |
20610 | case T_MNEM_str: | |
20611 | case T_MNEM_strb: | |
20612 | case T_MNEM_strh: | |
20613 | if (fragp->fr_var == 4) | |
20614 | { | |
5f4273c7 | 20615 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
20616 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
20617 | { | |
20618 | insn |= (old_op & 0x700) << 4; | |
20619 | } | |
20620 | else | |
20621 | { | |
20622 | insn |= (old_op & 7) << 12; | |
20623 | insn |= (old_op & 0x38) << 13; | |
20624 | } | |
20625 | insn |= 0x00000c00; | |
20626 | put_thumb32_insn (buf, insn); | |
20627 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
20628 | } | |
20629 | else | |
20630 | { | |
20631 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
20632 | } | |
20633 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
20634 | break; | |
20635 | case T_MNEM_adr: | |
20636 | if (fragp->fr_var == 4) | |
20637 | { | |
20638 | insn = THUMB_OP32 (opcode); | |
20639 | insn |= (old_op & 0xf0) << 4; | |
20640 | put_thumb32_insn (buf, insn); | |
20641 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
20642 | } | |
20643 | else | |
20644 | { | |
20645 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20646 | exp.X_add_number -= 4; | |
20647 | } | |
20648 | pc_rel = 1; | |
20649 | break; | |
20650 | case T_MNEM_mov: | |
20651 | case T_MNEM_movs: | |
20652 | case T_MNEM_cmp: | |
20653 | case T_MNEM_cmn: | |
20654 | if (fragp->fr_var == 4) | |
20655 | { | |
20656 | int r0off = (opcode == T_MNEM_mov | |
20657 | || opcode == T_MNEM_movs) ? 0 : 8; | |
20658 | insn = THUMB_OP32 (opcode); | |
20659 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
20660 | insn |= (old_op & 0x700) << r0off; | |
20661 | put_thumb32_insn (buf, insn); | |
20662 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
20663 | } | |
20664 | else | |
20665 | { | |
20666 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
20667 | } | |
20668 | pc_rel = 0; | |
20669 | break; | |
20670 | case T_MNEM_b: | |
20671 | if (fragp->fr_var == 4) | |
20672 | { | |
20673 | insn = THUMB_OP32(opcode); | |
20674 | put_thumb32_insn (buf, insn); | |
20675 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
20676 | } | |
20677 | else | |
20678 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
20679 | pc_rel = 1; | |
20680 | break; | |
20681 | case T_MNEM_bcond: | |
20682 | if (fragp->fr_var == 4) | |
20683 | { | |
20684 | insn = THUMB_OP32(opcode); | |
20685 | insn |= (old_op & 0xf00) << 14; | |
20686 | put_thumb32_insn (buf, insn); | |
20687 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
20688 | } | |
20689 | else | |
20690 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
20691 | pc_rel = 1; | |
20692 | break; | |
20693 | case T_MNEM_add_sp: | |
20694 | case T_MNEM_add_pc: | |
20695 | case T_MNEM_inc_sp: | |
20696 | case T_MNEM_dec_sp: | |
20697 | if (fragp->fr_var == 4) | |
20698 | { | |
20699 | /* ??? Choose between add and addw. */ | |
20700 | insn = THUMB_OP32 (opcode); | |
20701 | insn |= (old_op & 0xf0) << 4; | |
20702 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20703 | if (opcode == T_MNEM_add_pc) |
20704 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
20705 | else | |
20706 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
20707 | } |
20708 | else | |
20709 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20710 | pc_rel = 0; | |
20711 | break; | |
20712 | ||
20713 | case T_MNEM_addi: | |
20714 | case T_MNEM_addis: | |
20715 | case T_MNEM_subi: | |
20716 | case T_MNEM_subis: | |
20717 | if (fragp->fr_var == 4) | |
20718 | { | |
20719 | insn = THUMB_OP32 (opcode); | |
20720 | insn |= (old_op & 0xf0) << 4; | |
20721 | insn |= (old_op & 0xf) << 16; | |
20722 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
20723 | if (insn & (1 << 20)) |
20724 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
20725 | else | |
20726 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
20727 | } |
20728 | else | |
20729 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
20730 | pc_rel = 0; | |
20731 | break; | |
20732 | default: | |
5f4273c7 | 20733 | abort (); |
0110f2b8 PB |
20734 | } |
20735 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 20736 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
20737 | fixp->fx_file = fragp->fr_file; |
20738 | fixp->fx_line = fragp->fr_line; | |
20739 | fragp->fr_fix += fragp->fr_var; | |
3cfdb781 TG |
20740 | |
20741 | /* Set whether we use thumb-2 ISA based on final relaxation results. */ | |
20742 | if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected () | |
20743 | && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2)) | |
20744 | ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2); | |
0110f2b8 PB |
20745 | } |
20746 | ||
20747 | /* Return the size of a relaxable immediate operand instruction. | |
20748 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
20749 | static int | |
20750 | relax_immediate (fragS *fragp, int size, int shift) | |
20751 | { | |
20752 | offsetT offset; | |
20753 | offsetT mask; | |
20754 | offsetT low; | |
20755 | ||
20756 | /* ??? Should be able to do better than this. */ | |
20757 | if (fragp->fr_symbol) | |
20758 | return 4; | |
20759 | ||
20760 | low = (1 << shift) - 1; | |
20761 | mask = (1 << (shift + size)) - (1 << shift); | |
20762 | offset = fragp->fr_offset; | |
20763 | /* Force misaligned offsets to 32-bit variant. */ | |
20764 | if (offset & low) | |
5e77afaa | 20765 | return 4; |
0110f2b8 PB |
20766 | if (offset & ~mask) |
20767 | return 4; | |
20768 | return 2; | |
20769 | } | |
20770 | ||
5e77afaa PB |
20771 | /* Get the address of a symbol during relaxation. */ |
20772 | static addressT | |
5f4273c7 | 20773 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
20774 | { |
20775 | fragS *sym_frag; | |
20776 | addressT addr; | |
20777 | symbolS *sym; | |
20778 | ||
20779 | sym = fragp->fr_symbol; | |
20780 | sym_frag = symbol_get_frag (sym); | |
20781 | know (S_GET_SEGMENT (sym) != absolute_section | |
20782 | || sym_frag == &zero_address_frag); | |
20783 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
20784 | ||
20785 | /* If frag has yet to be reached on this pass, assume it will | |
20786 | move by STRETCH just as we did. If this is not so, it will | |
20787 | be because some frag between grows, and that will force | |
20788 | another pass. */ | |
20789 | ||
20790 | if (stretch != 0 | |
20791 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
20792 | { |
20793 | fragS *f; | |
20794 | ||
20795 | /* Adjust stretch for any alignment frag. Note that if have | |
20796 | been expanding the earlier code, the symbol may be | |
20797 | defined in what appears to be an earlier frag. FIXME: | |
20798 | This doesn't handle the fr_subtype field, which specifies | |
20799 | a maximum number of bytes to skip when doing an | |
20800 | alignment. */ | |
20801 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
20802 | { | |
20803 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
20804 | { | |
20805 | if (stretch < 0) | |
20806 | stretch = - ((- stretch) | |
20807 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
20808 | else | |
20809 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
20810 | if (stretch == 0) | |
20811 | break; | |
20812 | } | |
20813 | } | |
20814 | if (f != NULL) | |
20815 | addr += stretch; | |
20816 | } | |
5e77afaa PB |
20817 | |
20818 | return addr; | |
20819 | } | |
20820 | ||
0110f2b8 PB |
20821 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
20822 | load. */ | |
20823 | static int | |
5e77afaa | 20824 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
20825 | { |
20826 | addressT addr; | |
20827 | offsetT val; | |
20828 | ||
20829 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
20830 | if (fragp->fr_symbol == NULL |
20831 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
20832 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20833 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20834 | return 4; |
20835 | ||
5f4273c7 | 20836 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20837 | addr = fragp->fr_address + fragp->fr_fix; |
20838 | addr = (addr + 4) & ~3; | |
5e77afaa | 20839 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 20840 | if (val & 3) |
5e77afaa | 20841 | return 4; |
0110f2b8 PB |
20842 | val -= addr; |
20843 | if (val < 0 || val > 1020) | |
20844 | return 4; | |
20845 | return 2; | |
20846 | } | |
20847 | ||
20848 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
20849 | static int | |
20850 | relax_addsub (fragS *fragp, asection *sec) | |
20851 | { | |
20852 | char *buf; | |
20853 | int op; | |
20854 | ||
20855 | buf = fragp->fr_literal + fragp->fr_fix; | |
20856 | op = bfd_get_16(sec->owner, buf); | |
20857 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
20858 | return relax_immediate (fragp, 8, 0); | |
20859 | else | |
20860 | return relax_immediate (fragp, 3, 0); | |
20861 | } | |
20862 | ||
e83a675f RE |
20863 | /* Return TRUE iff the definition of symbol S could be pre-empted |
20864 | (overridden) at link or load time. */ | |
20865 | static bfd_boolean | |
20866 | symbol_preemptible (symbolS *s) | |
20867 | { | |
20868 | /* Weak symbols can always be pre-empted. */ | |
20869 | if (S_IS_WEAK (s)) | |
20870 | return TRUE; | |
20871 | ||
20872 | /* Non-global symbols cannot be pre-empted. */ | |
20873 | if (! S_IS_EXTERNAL (s)) | |
20874 | return FALSE; | |
20875 | ||
20876 | #ifdef OBJ_ELF | |
20877 | /* In ELF, a global symbol can be marked protected, or private. In that | |
20878 | case it can't be pre-empted (other definitions in the same link unit | |
20879 | would violate the ODR). */ | |
20880 | if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT) | |
20881 | return FALSE; | |
20882 | #endif | |
20883 | ||
20884 | /* Other global symbols might be pre-empted. */ | |
20885 | return TRUE; | |
20886 | } | |
0110f2b8 PB |
20887 | |
20888 | /* Return the size of a relaxable branch instruction. BITS is the | |
20889 | size of the offset field in the narrow instruction. */ | |
20890 | ||
20891 | static int | |
5e77afaa | 20892 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
20893 | { |
20894 | addressT addr; | |
20895 | offsetT val; | |
20896 | offsetT limit; | |
20897 | ||
20898 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 20899 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
20900 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
20901 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
20902 | return 4; |
20903 | ||
267bf995 | 20904 | #ifdef OBJ_ELF |
e83a675f | 20905 | /* A branch to a function in ARM state will require interworking. */ |
267bf995 RR |
20906 | if (S_IS_DEFINED (fragp->fr_symbol) |
20907 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
20908 | return 4; | |
e83a675f | 20909 | #endif |
0d9b4b55 | 20910 | |
e83a675f | 20911 | if (symbol_preemptible (fragp->fr_symbol)) |
0d9b4b55 | 20912 | return 4; |
267bf995 | 20913 | |
5f4273c7 | 20914 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
20915 | addr = fragp->fr_address + fragp->fr_fix + 4; |
20916 | val -= addr; | |
20917 | ||
20918 | /* Offset is a signed value *2 */ | |
20919 | limit = 1 << bits; | |
20920 | if (val >= limit || val < -limit) | |
20921 | return 4; | |
20922 | return 2; | |
20923 | } | |
20924 | ||
20925 | ||
20926 | /* Relax a machine dependent frag. This returns the amount by which | |
20927 | the current size of the frag should change. */ | |
20928 | ||
20929 | int | |
5e77afaa | 20930 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
20931 | { |
20932 | int oldsize; | |
20933 | int newsize; | |
20934 | ||
20935 | oldsize = fragp->fr_var; | |
20936 | switch (fragp->fr_subtype) | |
20937 | { | |
20938 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 20939 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20940 | break; |
20941 | case T_MNEM_ldr_pc: | |
20942 | case T_MNEM_ldr_sp: | |
20943 | case T_MNEM_str_sp: | |
5f4273c7 | 20944 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
20945 | break; |
20946 | case T_MNEM_ldr: | |
20947 | case T_MNEM_str: | |
5f4273c7 | 20948 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
20949 | break; |
20950 | case T_MNEM_ldrh: | |
20951 | case T_MNEM_strh: | |
5f4273c7 | 20952 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
20953 | break; |
20954 | case T_MNEM_ldrb: | |
20955 | case T_MNEM_strb: | |
5f4273c7 | 20956 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
20957 | break; |
20958 | case T_MNEM_adr: | |
5f4273c7 | 20959 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
20960 | break; |
20961 | case T_MNEM_mov: | |
20962 | case T_MNEM_movs: | |
20963 | case T_MNEM_cmp: | |
20964 | case T_MNEM_cmn: | |
5f4273c7 | 20965 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
20966 | break; |
20967 | case T_MNEM_b: | |
5f4273c7 | 20968 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
20969 | break; |
20970 | case T_MNEM_bcond: | |
5f4273c7 | 20971 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
20972 | break; |
20973 | case T_MNEM_add_sp: | |
20974 | case T_MNEM_add_pc: | |
20975 | newsize = relax_immediate (fragp, 8, 2); | |
20976 | break; | |
20977 | case T_MNEM_inc_sp: | |
20978 | case T_MNEM_dec_sp: | |
20979 | newsize = relax_immediate (fragp, 7, 2); | |
20980 | break; | |
20981 | case T_MNEM_addi: | |
20982 | case T_MNEM_addis: | |
20983 | case T_MNEM_subi: | |
20984 | case T_MNEM_subis: | |
20985 | newsize = relax_addsub (fragp, sec); | |
20986 | break; | |
20987 | default: | |
5f4273c7 | 20988 | abort (); |
0110f2b8 | 20989 | } |
5e77afaa PB |
20990 | |
20991 | fragp->fr_var = newsize; | |
20992 | /* Freeze wide instructions that are at or before the same location as | |
20993 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
20994 | Don't freeze them unconditionally because targets may be artificially |
20995 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 20996 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 20997 | { |
0110f2b8 | 20998 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 20999 | frag_wane (fragp); |
0110f2b8 | 21000 | } |
5e77afaa | 21001 | |
0110f2b8 | 21002 | return newsize - oldsize; |
c19d1205 | 21003 | } |
b99bd4ef | 21004 | |
c19d1205 | 21005 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 21006 | |
c19d1205 ZW |
21007 | valueT |
21008 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
21009 | valueT size) | |
21010 | { | |
f0927246 NC |
21011 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
21012 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
21013 | { | |
21014 | /* For a.out, force the section size to be aligned. If we don't do | |
21015 | this, BFD will align it for us, but it will not write out the | |
21016 | final bytes of the section. This may be a bug in BFD, but it is | |
21017 | easier to fix it here since that is how the other a.out targets | |
21018 | work. */ | |
21019 | int align; | |
21020 | ||
21021 | align = bfd_get_section_alignment (stdoutput, segment); | |
21022 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
21023 | } | |
c19d1205 | 21024 | #endif |
f0927246 NC |
21025 | |
21026 | return size; | |
bfae80f2 | 21027 | } |
b99bd4ef | 21028 | |
c19d1205 ZW |
21029 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
21030 | of an rs_align_code fragment. */ | |
21031 | ||
21032 | void | |
21033 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 21034 | { |
e7495e45 NS |
21035 | static char const arm_noop[2][2][4] = |
21036 | { | |
21037 | { /* ARMv1 */ | |
21038 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
21039 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
21040 | }, | |
21041 | { /* ARMv6k */ | |
21042 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
21043 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
21044 | }, | |
21045 | }; | |
21046 | static char const thumb_noop[2][2][2] = | |
21047 | { | |
21048 | { /* Thumb-1 */ | |
21049 | {0xc0, 0x46}, /* LE */ | |
21050 | {0x46, 0xc0}, /* BE */ | |
21051 | }, | |
21052 | { /* Thumb-2 */ | |
21053 | {0x00, 0xbf}, /* LE */ | |
21054 | {0xbf, 0x00} /* BE */ | |
21055 | } | |
21056 | }; | |
21057 | static char const wide_thumb_noop[2][4] = | |
21058 | { /* Wide Thumb-2 */ | |
21059 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
21060 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
21061 | }; | |
c921be7d | 21062 | |
e7495e45 | 21063 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
21064 | char * p; |
21065 | const char * noop; | |
e7495e45 | 21066 | const char *narrow_noop = NULL; |
cd000bff DJ |
21067 | #ifdef OBJ_ELF |
21068 | enum mstate state; | |
21069 | #endif | |
bfae80f2 | 21070 | |
c19d1205 | 21071 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
21072 | return; |
21073 | ||
c19d1205 ZW |
21074 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
21075 | p = fragP->fr_literal + fragP->fr_fix; | |
21076 | fix = 0; | |
bfae80f2 | 21077 | |
c19d1205 ZW |
21078 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
21079 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 21080 | |
cd000bff | 21081 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 21082 | |
cd000bff | 21083 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 21084 | { |
7f78eb34 JW |
21085 | if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
21086 | ? selected_cpu : arm_arch_none, arm_ext_v6t2)) | |
e7495e45 NS |
21087 | { |
21088 | narrow_noop = thumb_noop[1][target_big_endian]; | |
21089 | noop = wide_thumb_noop[target_big_endian]; | |
21090 | } | |
c19d1205 | 21091 | else |
e7495e45 NS |
21092 | noop = thumb_noop[0][target_big_endian]; |
21093 | noop_size = 2; | |
cd000bff DJ |
21094 | #ifdef OBJ_ELF |
21095 | state = MAP_THUMB; | |
21096 | #endif | |
7ed4c4c5 NC |
21097 | } |
21098 | else | |
21099 | { | |
7f78eb34 JW |
21100 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0] |
21101 | ? selected_cpu : arm_arch_none, | |
21102 | arm_ext_v6k) != 0] | |
e7495e45 NS |
21103 | [target_big_endian]; |
21104 | noop_size = 4; | |
cd000bff DJ |
21105 | #ifdef OBJ_ELF |
21106 | state = MAP_ARM; | |
21107 | #endif | |
7ed4c4c5 | 21108 | } |
c921be7d | 21109 | |
e7495e45 | 21110 | fragP->fr_var = noop_size; |
c921be7d | 21111 | |
c19d1205 | 21112 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 21113 | { |
c19d1205 | 21114 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
21115 | #ifdef OBJ_ELF |
21116 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
21117 | #endif | |
c19d1205 ZW |
21118 | memset (p, 0, fix); |
21119 | p += fix; | |
21120 | bytes -= fix; | |
a737bd4d | 21121 | } |
a737bd4d | 21122 | |
e7495e45 NS |
21123 | if (narrow_noop) |
21124 | { | |
21125 | if (bytes & noop_size) | |
21126 | { | |
21127 | /* Insert a narrow noop. */ | |
21128 | memcpy (p, narrow_noop, noop_size); | |
21129 | p += noop_size; | |
21130 | bytes -= noop_size; | |
21131 | fix += noop_size; | |
21132 | } | |
21133 | ||
21134 | /* Use wide noops for the remainder */ | |
21135 | noop_size = 4; | |
21136 | } | |
21137 | ||
c19d1205 | 21138 | while (bytes >= noop_size) |
a737bd4d | 21139 | { |
c19d1205 ZW |
21140 | memcpy (p, noop, noop_size); |
21141 | p += noop_size; | |
21142 | bytes -= noop_size; | |
21143 | fix += noop_size; | |
a737bd4d NC |
21144 | } |
21145 | ||
c19d1205 | 21146 | fragP->fr_fix += fix; |
a737bd4d NC |
21147 | } |
21148 | ||
c19d1205 ZW |
21149 | /* Called from md_do_align. Used to create an alignment |
21150 | frag in a code section. */ | |
21151 | ||
21152 | void | |
21153 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 21154 | { |
c19d1205 | 21155 | char * p; |
7ed4c4c5 | 21156 | |
c19d1205 | 21157 | /* We assume that there will never be a requirement |
6ec8e702 | 21158 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 21159 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
21160 | { |
21161 | char err_msg[128]; | |
21162 | ||
fa94de6b | 21163 | sprintf (err_msg, |
477330fc RM |
21164 | _("alignments greater than %d bytes not supported in .text sections."), |
21165 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 21166 | as_fatal ("%s", err_msg); |
6ec8e702 | 21167 | } |
bfae80f2 | 21168 | |
c19d1205 ZW |
21169 | p = frag_var (rs_align_code, |
21170 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
21171 | 1, | |
21172 | (relax_substateT) max, | |
21173 | (symbolS *) NULL, | |
21174 | (offsetT) n, | |
21175 | (char *) NULL); | |
21176 | *p = 0; | |
21177 | } | |
bfae80f2 | 21178 | |
8dc2430f NC |
21179 | /* Perform target specific initialisation of a frag. |
21180 | Note - despite the name this initialisation is not done when the frag | |
21181 | is created, but only when its type is assigned. A frag can be created | |
21182 | and used a long time before its type is set, so beware of assuming that | |
21183 | this initialisationis performed first. */ | |
bfae80f2 | 21184 | |
cd000bff DJ |
21185 | #ifndef OBJ_ELF |
21186 | void | |
21187 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
21188 | { | |
21189 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 21190 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
21191 | } |
21192 | ||
21193 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 21194 | void |
cd000bff | 21195 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 21196 | { |
b968d18a JW |
21197 | int frag_thumb_mode; |
21198 | ||
8dc2430f NC |
21199 | /* If the current ARM vs THUMB mode has not already |
21200 | been recorded into this frag then do so now. */ | |
cd000bff | 21201 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
b968d18a JW |
21202 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
21203 | ||
21204 | frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED; | |
cd000bff | 21205 | |
f9c1b181 RL |
21206 | /* Record a mapping symbol for alignment frags. We will delete this |
21207 | later if the alignment ends up empty. */ | |
21208 | switch (fragP->fr_type) | |
21209 | { | |
21210 | case rs_align: | |
21211 | case rs_align_test: | |
21212 | case rs_fill: | |
21213 | mapping_state_2 (MAP_DATA, max_chars); | |
21214 | break; | |
21215 | case rs_align_code: | |
b968d18a | 21216 | mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); |
f9c1b181 RL |
21217 | break; |
21218 | default: | |
21219 | break; | |
cd000bff | 21220 | } |
bfae80f2 RE |
21221 | } |
21222 | ||
c19d1205 ZW |
21223 | /* When we change sections we need to issue a new mapping symbol. */ |
21224 | ||
21225 | void | |
21226 | arm_elf_change_section (void) | |
bfae80f2 | 21227 | { |
c19d1205 ZW |
21228 | /* Link an unlinked unwind index table section to the .text section. */ |
21229 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
21230 | && elf_linked_to_section (now_seg) == NULL) | |
21231 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
21232 | } |
21233 | ||
c19d1205 ZW |
21234 | int |
21235 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 21236 | { |
c19d1205 ZW |
21237 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
21238 | return SHT_ARM_EXIDX; | |
e45d0630 | 21239 | |
c19d1205 ZW |
21240 | return -1; |
21241 | } | |
21242 | \f | |
21243 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 21244 | |
c19d1205 | 21245 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 21246 | |
5f4273c7 | 21247 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 21248 | |
bfae80f2 | 21249 | static void |
c19d1205 | 21250 | flush_pending_unwind (void) |
bfae80f2 | 21251 | { |
c19d1205 | 21252 | offsetT offset; |
bfae80f2 | 21253 | |
c19d1205 ZW |
21254 | offset = unwind.pending_offset; |
21255 | unwind.pending_offset = 0; | |
21256 | if (offset != 0) | |
21257 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
21258 | } |
21259 | ||
c19d1205 ZW |
21260 | /* Add an opcode to this list for this function. Two-byte opcodes should |
21261 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
21262 | order. */ | |
21263 | ||
bfae80f2 | 21264 | static void |
c19d1205 | 21265 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 21266 | { |
c19d1205 ZW |
21267 | /* Add any deferred stack adjustment. */ |
21268 | if (unwind.pending_offset) | |
21269 | flush_pending_unwind (); | |
bfae80f2 | 21270 | |
c19d1205 | 21271 | unwind.sp_restored = 0; |
bfae80f2 | 21272 | |
c19d1205 | 21273 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 21274 | { |
c19d1205 ZW |
21275 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
21276 | if (unwind.opcodes) | |
21d799b5 | 21277 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
477330fc | 21278 | unwind.opcode_alloc); |
c19d1205 | 21279 | else |
21d799b5 | 21280 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 21281 | } |
c19d1205 | 21282 | while (length > 0) |
bfae80f2 | 21283 | { |
c19d1205 ZW |
21284 | length--; |
21285 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
21286 | op >>= 8; | |
21287 | unwind.opcode_count++; | |
bfae80f2 | 21288 | } |
bfae80f2 RE |
21289 | } |
21290 | ||
c19d1205 ZW |
21291 | /* Add unwind opcodes to adjust the stack pointer. */ |
21292 | ||
bfae80f2 | 21293 | static void |
c19d1205 | 21294 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 21295 | { |
c19d1205 | 21296 | valueT op; |
bfae80f2 | 21297 | |
c19d1205 | 21298 | if (offset > 0x200) |
bfae80f2 | 21299 | { |
c19d1205 ZW |
21300 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
21301 | char bytes[5]; | |
21302 | int n; | |
21303 | valueT o; | |
bfae80f2 | 21304 | |
c19d1205 ZW |
21305 | /* Long form: 0xb2, uleb128. */ |
21306 | /* This might not fit in a word so add the individual bytes, | |
21307 | remembering the list is built in reverse order. */ | |
21308 | o = (valueT) ((offset - 0x204) >> 2); | |
21309 | if (o == 0) | |
21310 | add_unwind_opcode (0, 1); | |
bfae80f2 | 21311 | |
c19d1205 ZW |
21312 | /* Calculate the uleb128 encoding of the offset. */ |
21313 | n = 0; | |
21314 | while (o) | |
21315 | { | |
21316 | bytes[n] = o & 0x7f; | |
21317 | o >>= 7; | |
21318 | if (o) | |
21319 | bytes[n] |= 0x80; | |
21320 | n++; | |
21321 | } | |
21322 | /* Add the insn. */ | |
21323 | for (; n; n--) | |
21324 | add_unwind_opcode (bytes[n - 1], 1); | |
21325 | add_unwind_opcode (0xb2, 1); | |
21326 | } | |
21327 | else if (offset > 0x100) | |
bfae80f2 | 21328 | { |
c19d1205 ZW |
21329 | /* Two short opcodes. */ |
21330 | add_unwind_opcode (0x3f, 1); | |
21331 | op = (offset - 0x104) >> 2; | |
21332 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21333 | } |
c19d1205 ZW |
21334 | else if (offset > 0) |
21335 | { | |
21336 | /* Short opcode. */ | |
21337 | op = (offset - 4) >> 2; | |
21338 | add_unwind_opcode (op, 1); | |
21339 | } | |
21340 | else if (offset < 0) | |
bfae80f2 | 21341 | { |
c19d1205 ZW |
21342 | offset = -offset; |
21343 | while (offset > 0x100) | |
bfae80f2 | 21344 | { |
c19d1205 ZW |
21345 | add_unwind_opcode (0x7f, 1); |
21346 | offset -= 0x100; | |
bfae80f2 | 21347 | } |
c19d1205 ZW |
21348 | op = ((offset - 4) >> 2) | 0x40; |
21349 | add_unwind_opcode (op, 1); | |
bfae80f2 | 21350 | } |
bfae80f2 RE |
21351 | } |
21352 | ||
c19d1205 ZW |
21353 | /* Finish the list of unwind opcodes for this function. */ |
21354 | static void | |
21355 | finish_unwind_opcodes (void) | |
bfae80f2 | 21356 | { |
c19d1205 | 21357 | valueT op; |
bfae80f2 | 21358 | |
c19d1205 | 21359 | if (unwind.fp_used) |
bfae80f2 | 21360 | { |
708587a4 | 21361 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
21362 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
21363 | flush_pending_unwind (); | |
bfae80f2 | 21364 | |
c19d1205 ZW |
21365 | /* After restoring sp from the frame pointer. */ |
21366 | op = 0x90 | unwind.fp_reg; | |
21367 | add_unwind_opcode (op, 1); | |
21368 | } | |
21369 | else | |
21370 | flush_pending_unwind (); | |
bfae80f2 RE |
21371 | } |
21372 | ||
bfae80f2 | 21373 | |
c19d1205 ZW |
21374 | /* Start an exception table entry. If idx is nonzero this is an index table |
21375 | entry. */ | |
bfae80f2 RE |
21376 | |
21377 | static void | |
c19d1205 | 21378 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 21379 | { |
c19d1205 ZW |
21380 | const char * text_name; |
21381 | const char * prefix; | |
21382 | const char * prefix_once; | |
21383 | const char * group_name; | |
21384 | size_t prefix_len; | |
21385 | size_t text_len; | |
21386 | char * sec_name; | |
21387 | size_t sec_name_len; | |
21388 | int type; | |
21389 | int flags; | |
21390 | int linkonce; | |
bfae80f2 | 21391 | |
c19d1205 | 21392 | if (idx) |
bfae80f2 | 21393 | { |
c19d1205 ZW |
21394 | prefix = ELF_STRING_ARM_unwind; |
21395 | prefix_once = ELF_STRING_ARM_unwind_once; | |
21396 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 21397 | } |
c19d1205 | 21398 | else |
bfae80f2 | 21399 | { |
c19d1205 ZW |
21400 | prefix = ELF_STRING_ARM_unwind_info; |
21401 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
21402 | type = SHT_PROGBITS; | |
bfae80f2 RE |
21403 | } |
21404 | ||
c19d1205 ZW |
21405 | text_name = segment_name (text_seg); |
21406 | if (streq (text_name, ".text")) | |
21407 | text_name = ""; | |
21408 | ||
21409 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
21410 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 21411 | { |
c19d1205 ZW |
21412 | prefix = prefix_once; |
21413 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
21414 | } |
21415 | ||
c19d1205 ZW |
21416 | prefix_len = strlen (prefix); |
21417 | text_len = strlen (text_name); | |
21418 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 21419 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
21420 | memcpy (sec_name, prefix, prefix_len); |
21421 | memcpy (sec_name + prefix_len, text_name, text_len); | |
21422 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 21423 | |
c19d1205 ZW |
21424 | flags = SHF_ALLOC; |
21425 | linkonce = 0; | |
21426 | group_name = 0; | |
bfae80f2 | 21427 | |
c19d1205 ZW |
21428 | /* Handle COMDAT group. */ |
21429 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 21430 | { |
c19d1205 ZW |
21431 | group_name = elf_group_name (text_seg); |
21432 | if (group_name == NULL) | |
21433 | { | |
bd3ba5d1 | 21434 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
21435 | segment_name (text_seg)); |
21436 | ignore_rest_of_line (); | |
21437 | return; | |
21438 | } | |
21439 | flags |= SHF_GROUP; | |
21440 | linkonce = 1; | |
bfae80f2 RE |
21441 | } |
21442 | ||
c19d1205 | 21443 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 21444 | |
5f4273c7 | 21445 | /* Set the section link for index tables. */ |
c19d1205 ZW |
21446 | if (idx) |
21447 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
21448 | } |
21449 | ||
bfae80f2 | 21450 | |
c19d1205 ZW |
21451 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
21452 | personality routine data. Returns zero, or the index table value for | |
cad0da33 | 21453 | an inline entry. */ |
c19d1205 ZW |
21454 | |
21455 | static valueT | |
21456 | create_unwind_entry (int have_data) | |
bfae80f2 | 21457 | { |
c19d1205 ZW |
21458 | int size; |
21459 | addressT where; | |
21460 | char *ptr; | |
21461 | /* The current word of data. */ | |
21462 | valueT data; | |
21463 | /* The number of bytes left in this word. */ | |
21464 | int n; | |
bfae80f2 | 21465 | |
c19d1205 | 21466 | finish_unwind_opcodes (); |
bfae80f2 | 21467 | |
c19d1205 ZW |
21468 | /* Remember the current text section. */ |
21469 | unwind.saved_seg = now_seg; | |
21470 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 21471 | |
c19d1205 | 21472 | start_unwind_section (now_seg, 0); |
bfae80f2 | 21473 | |
c19d1205 | 21474 | if (unwind.personality_routine == NULL) |
bfae80f2 | 21475 | { |
c19d1205 ZW |
21476 | if (unwind.personality_index == -2) |
21477 | { | |
21478 | if (have_data) | |
5f4273c7 | 21479 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
21480 | return 1; /* EXIDX_CANTUNWIND. */ |
21481 | } | |
bfae80f2 | 21482 | |
c19d1205 ZW |
21483 | /* Use a default personality routine if none is specified. */ |
21484 | if (unwind.personality_index == -1) | |
21485 | { | |
21486 | if (unwind.opcode_count > 3) | |
21487 | unwind.personality_index = 1; | |
21488 | else | |
21489 | unwind.personality_index = 0; | |
21490 | } | |
bfae80f2 | 21491 | |
c19d1205 ZW |
21492 | /* Space for the personality routine entry. */ |
21493 | if (unwind.personality_index == 0) | |
21494 | { | |
21495 | if (unwind.opcode_count > 3) | |
21496 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 21497 | |
c19d1205 ZW |
21498 | if (!have_data) |
21499 | { | |
21500 | /* All the data is inline in the index table. */ | |
21501 | data = 0x80; | |
21502 | n = 3; | |
21503 | while (unwind.opcode_count > 0) | |
21504 | { | |
21505 | unwind.opcode_count--; | |
21506 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21507 | n--; | |
21508 | } | |
bfae80f2 | 21509 | |
c19d1205 ZW |
21510 | /* Pad with "finish" opcodes. */ |
21511 | while (n--) | |
21512 | data = (data << 8) | 0xb0; | |
bfae80f2 | 21513 | |
c19d1205 ZW |
21514 | return data; |
21515 | } | |
21516 | size = 0; | |
21517 | } | |
21518 | else | |
21519 | /* We get two opcodes "free" in the first word. */ | |
21520 | size = unwind.opcode_count - 2; | |
21521 | } | |
21522 | else | |
5011093d | 21523 | { |
cad0da33 NC |
21524 | /* PR 16765: Missing or misplaced unwind directives can trigger this. */ |
21525 | if (unwind.personality_index != -1) | |
21526 | { | |
21527 | as_bad (_("attempt to recreate an unwind entry")); | |
21528 | return 1; | |
21529 | } | |
5011093d NC |
21530 | |
21531 | /* An extra byte is required for the opcode count. */ | |
21532 | size = unwind.opcode_count + 1; | |
21533 | } | |
bfae80f2 | 21534 | |
c19d1205 ZW |
21535 | size = (size + 3) >> 2; |
21536 | if (size > 0xff) | |
21537 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 21538 | |
c19d1205 ZW |
21539 | frag_align (2, 0, 0); |
21540 | record_alignment (now_seg, 2); | |
21541 | unwind.table_entry = expr_build_dot (); | |
21542 | ||
21543 | /* Allocate the table entry. */ | |
21544 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
21545 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
21546 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 21547 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 21548 | |
c19d1205 | 21549 | switch (unwind.personality_index) |
bfae80f2 | 21550 | { |
c19d1205 ZW |
21551 | case -1: |
21552 | /* ??? Should this be a PLT generating relocation? */ | |
21553 | /* Custom personality routine. */ | |
21554 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
21555 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 21556 | |
c19d1205 ZW |
21557 | where += 4; |
21558 | ptr += 4; | |
bfae80f2 | 21559 | |
c19d1205 | 21560 | /* Set the first byte to the number of additional words. */ |
5011093d | 21561 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
21562 | n = 3; |
21563 | break; | |
bfae80f2 | 21564 | |
c19d1205 ZW |
21565 | /* ABI defined personality routines. */ |
21566 | case 0: | |
21567 | /* Three opcodes bytes are packed into the first word. */ | |
21568 | data = 0x80; | |
21569 | n = 3; | |
21570 | break; | |
bfae80f2 | 21571 | |
c19d1205 ZW |
21572 | case 1: |
21573 | case 2: | |
21574 | /* The size and first two opcode bytes go in the first word. */ | |
21575 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
21576 | n = 2; | |
21577 | break; | |
bfae80f2 | 21578 | |
c19d1205 ZW |
21579 | default: |
21580 | /* Should never happen. */ | |
21581 | abort (); | |
21582 | } | |
bfae80f2 | 21583 | |
c19d1205 ZW |
21584 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
21585 | time. */ | |
21586 | while (unwind.opcode_count > 0) | |
21587 | { | |
21588 | if (n == 0) | |
21589 | { | |
21590 | md_number_to_chars (ptr, data, 4); | |
21591 | ptr += 4; | |
21592 | n = 4; | |
21593 | data = 0; | |
21594 | } | |
21595 | unwind.opcode_count--; | |
21596 | n--; | |
21597 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
21598 | } | |
21599 | ||
21600 | /* Finish off the last word. */ | |
21601 | if (n < 4) | |
21602 | { | |
21603 | /* Pad with "finish" opcodes. */ | |
21604 | while (n--) | |
21605 | data = (data << 8) | 0xb0; | |
21606 | ||
21607 | md_number_to_chars (ptr, data, 4); | |
21608 | } | |
21609 | ||
21610 | if (!have_data) | |
21611 | { | |
21612 | /* Add an empty descriptor if there is no user-specified data. */ | |
21613 | ptr = frag_more (4); | |
21614 | md_number_to_chars (ptr, 0, 4); | |
21615 | } | |
21616 | ||
21617 | return 0; | |
bfae80f2 RE |
21618 | } |
21619 | ||
f0927246 NC |
21620 | |
21621 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
21622 | ||
21623 | void | |
21624 | tc_arm_frame_initial_instructions (void) | |
21625 | { | |
21626 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
21627 | } | |
21628 | #endif /* OBJ_ELF */ | |
21629 | ||
c19d1205 ZW |
21630 | /* Convert REGNAME to a DWARF-2 register number. */ |
21631 | ||
21632 | int | |
1df69f4f | 21633 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 21634 | { |
1df69f4f | 21635 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
1f5afe1c NC |
21636 | if (reg != FAIL) |
21637 | return reg; | |
c19d1205 | 21638 | |
1f5afe1c NC |
21639 | /* PR 16694: Allow VFP registers as well. */ |
21640 | reg = arm_reg_parse (®name, REG_TYPE_VFS); | |
21641 | if (reg != FAIL) | |
21642 | return 64 + reg; | |
c19d1205 | 21643 | |
1f5afe1c NC |
21644 | reg = arm_reg_parse (®name, REG_TYPE_VFD); |
21645 | if (reg != FAIL) | |
21646 | return reg + 256; | |
21647 | ||
21648 | return -1; | |
bfae80f2 RE |
21649 | } |
21650 | ||
f0927246 | 21651 | #ifdef TE_PE |
c19d1205 | 21652 | void |
f0927246 | 21653 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 21654 | { |
91d6fa6a | 21655 | expressionS exp; |
bfae80f2 | 21656 | |
91d6fa6a NC |
21657 | exp.X_op = O_secrel; |
21658 | exp.X_add_symbol = symbol; | |
21659 | exp.X_add_number = 0; | |
21660 | emit_expr (&exp, size); | |
f0927246 NC |
21661 | } |
21662 | #endif | |
bfae80f2 | 21663 | |
c19d1205 | 21664 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 21665 | |
2fc8bdac ZW |
21666 | /* Return the address within the segment that a PC-relative fixup is |
21667 | relative to. For ARM, PC-relative fixups applied to instructions | |
21668 | are generally relative to the location of the fixup plus 8 bytes. | |
21669 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
21670 | require special handling. */ | |
bfae80f2 | 21671 | |
c19d1205 | 21672 | long |
2fc8bdac | 21673 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 21674 | { |
2fc8bdac ZW |
21675 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
21676 | ||
21677 | /* If this is pc-relative and we are going to emit a relocation | |
21678 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
21679 | will need. Otherwise we want to use the calculated base. |
21680 | For WinCE we skip the bias for externals as well, since this | |
21681 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 21682 | if (fixP->fx_pcrel |
2fc8bdac | 21683 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
21684 | || (arm_force_relocation (fixP) |
21685 | #ifdef TE_WINCE | |
21686 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
21687 | #endif | |
21688 | ))) | |
2fc8bdac | 21689 | base = 0; |
bfae80f2 | 21690 | |
267bf995 | 21691 | |
c19d1205 | 21692 | switch (fixP->fx_r_type) |
bfae80f2 | 21693 | { |
2fc8bdac ZW |
21694 | /* PC relative addressing on the Thumb is slightly odd as the |
21695 | bottom two bits of the PC are forced to zero for the | |
21696 | calculation. This happens *after* application of the | |
21697 | pipeline offset. However, Thumb adrl already adjusts for | |
21698 | this, so we need not do it again. */ | |
c19d1205 | 21699 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 21700 | return base & ~3; |
c19d1205 ZW |
21701 | |
21702 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
21703 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 21704 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 21705 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 21706 | return (base + 4) & ~3; |
c19d1205 | 21707 | |
2fc8bdac ZW |
21708 | /* Thumb branches are simply offset by +4. */ |
21709 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21710 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21711 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21712 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 21713 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 21714 | return base + 4; |
bfae80f2 | 21715 | |
267bf995 | 21716 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
21717 | if (fixP->fx_addsy |
21718 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21719 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 | 21720 | && ARM_IS_FUNC (fixP->fx_addsy) |
477330fc RM |
21721 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) |
21722 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
267bf995 RR |
21723 | return base + 4; |
21724 | ||
00adf2d4 JB |
21725 | /* BLX is like branches above, but forces the low two bits of PC to |
21726 | zero. */ | |
486499d0 CL |
21727 | case BFD_RELOC_THUMB_PCREL_BLX: |
21728 | if (fixP->fx_addsy | |
21729 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21730 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21731 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21732 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21733 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
21734 | return (base + 4) & ~3; |
21735 | ||
2fc8bdac ZW |
21736 | /* ARM mode branches are offset by +8. However, the Windows CE |
21737 | loader expects the relocation not to take this into account. */ | |
267bf995 | 21738 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
21739 | if (fixP->fx_addsy |
21740 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21741 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21742 | && ARM_IS_FUNC (fixP->fx_addsy) |
21743 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21744 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21745 | return base + 8; |
267bf995 | 21746 | |
486499d0 CL |
21747 | case BFD_RELOC_ARM_PCREL_CALL: |
21748 | if (fixP->fx_addsy | |
21749 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21750 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
477330fc RM |
21751 | && THUMB_IS_FUNC (fixP->fx_addsy) |
21752 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21753 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 21754 | return base + 8; |
267bf995 | 21755 | |
2fc8bdac | 21756 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 21757 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 21758 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 21759 | #ifdef TE_WINCE |
5f4273c7 | 21760 | /* When handling fixups immediately, because we have already |
477330fc | 21761 | discovered the value of a symbol, or the address of the frag involved |
53baae48 | 21762 | we must account for the offset by +8, as the OS loader will never see the reloc. |
477330fc RM |
21763 | see fixup_segment() in write.c |
21764 | The S_IS_EXTERNAL test handles the case of global symbols. | |
21765 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
53baae48 NC |
21766 | if (fixP->fx_pcrel |
21767 | && fixP->fx_addsy != NULL | |
21768 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
21769 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
21770 | return base + 8; | |
2fc8bdac | 21771 | return base; |
c19d1205 | 21772 | #else |
2fc8bdac | 21773 | return base + 8; |
c19d1205 | 21774 | #endif |
2fc8bdac | 21775 | |
267bf995 | 21776 | |
2fc8bdac ZW |
21777 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
21778 | branches, the Windows CE loader *does* expect the relocation | |
21779 | to take this into account. */ | |
21780 | case BFD_RELOC_ARM_OFFSET_IMM: | |
21781 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
21782 | case BFD_RELOC_ARM_HWLITERAL: | |
21783 | case BFD_RELOC_ARM_LITERAL: | |
21784 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
21785 | return base + 8; | |
21786 | ||
21787 | ||
21788 | /* Other PC-relative relocations are un-offset. */ | |
21789 | default: | |
21790 | return base; | |
21791 | } | |
bfae80f2 RE |
21792 | } |
21793 | ||
8b2d793c NC |
21794 | static bfd_boolean flag_warn_syms = TRUE; |
21795 | ||
ae8714c2 NC |
21796 | bfd_boolean |
21797 | arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name) | |
bfae80f2 | 21798 | { |
8b2d793c NC |
21799 | /* PR 18347 - Warn if the user attempts to create a symbol with the same |
21800 | name as an ARM instruction. Whilst strictly speaking it is allowed, it | |
21801 | does mean that the resulting code might be very confusing to the reader. | |
21802 | Also this warning can be triggered if the user omits an operand before | |
21803 | an immediate address, eg: | |
21804 | ||
21805 | LDR =foo | |
21806 | ||
21807 | GAS treats this as an assignment of the value of the symbol foo to a | |
21808 | symbol LDR, and so (without this code) it will not issue any kind of | |
21809 | warning or error message. | |
21810 | ||
21811 | Note - ARM instructions are case-insensitive but the strings in the hash | |
21812 | table are all stored in lower case, so we must first ensure that name is | |
ae8714c2 NC |
21813 | lower case too. */ |
21814 | if (flag_warn_syms && arm_ops_hsh) | |
8b2d793c NC |
21815 | { |
21816 | char * nbuf = strdup (name); | |
21817 | char * p; | |
21818 | ||
21819 | for (p = nbuf; *p; p++) | |
21820 | *p = TOLOWER (*p); | |
21821 | if (hash_find (arm_ops_hsh, nbuf) != NULL) | |
21822 | { | |
21823 | static struct hash_control * already_warned = NULL; | |
21824 | ||
21825 | if (already_warned == NULL) | |
21826 | already_warned = hash_new (); | |
21827 | /* Only warn about the symbol once. To keep the code | |
21828 | simple we let hash_insert do the lookup for us. */ | |
21829 | if (hash_insert (already_warned, name, NULL) == NULL) | |
ae8714c2 | 21830 | as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name); |
8b2d793c NC |
21831 | } |
21832 | else | |
21833 | free (nbuf); | |
21834 | } | |
3739860c | 21835 | |
ae8714c2 NC |
21836 | return FALSE; |
21837 | } | |
21838 | ||
21839 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
21840 | Otherwise we have no need to default values of symbols. */ | |
21841 | ||
21842 | symbolS * | |
21843 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
21844 | { | |
21845 | #ifdef OBJ_ELF | |
21846 | if (name[0] == '_' && name[1] == 'G' | |
21847 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
21848 | { | |
21849 | if (!GOT_symbol) | |
21850 | { | |
21851 | if (symbol_find (name)) | |
21852 | as_bad (_("GOT already in the symbol table")); | |
21853 | ||
21854 | GOT_symbol = symbol_new (name, undefined_section, | |
21855 | (valueT) 0, & zero_address_frag); | |
21856 | } | |
21857 | ||
21858 | return GOT_symbol; | |
21859 | } | |
21860 | #endif | |
21861 | ||
c921be7d | 21862 | return NULL; |
bfae80f2 RE |
21863 | } |
21864 | ||
55cf6793 | 21865 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
21866 | computed as two separate immediate values, added together. We |
21867 | already know that this value cannot be computed by just one ARM | |
21868 | instruction. */ | |
21869 | ||
21870 | static unsigned int | |
21871 | validate_immediate_twopart (unsigned int val, | |
21872 | unsigned int * highpart) | |
bfae80f2 | 21873 | { |
c19d1205 ZW |
21874 | unsigned int a; |
21875 | unsigned int i; | |
bfae80f2 | 21876 | |
c19d1205 ZW |
21877 | for (i = 0; i < 32; i += 2) |
21878 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
21879 | { | |
21880 | if (a & 0xff00) | |
21881 | { | |
21882 | if (a & ~ 0xffff) | |
21883 | continue; | |
21884 | * highpart = (a >> 8) | ((i + 24) << 7); | |
21885 | } | |
21886 | else if (a & 0xff0000) | |
21887 | { | |
21888 | if (a & 0xff000000) | |
21889 | continue; | |
21890 | * highpart = (a >> 16) | ((i + 16) << 7); | |
21891 | } | |
21892 | else | |
21893 | { | |
9c2799c2 | 21894 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
21895 | * highpart = (a >> 24) | ((i + 8) << 7); |
21896 | } | |
bfae80f2 | 21897 | |
c19d1205 ZW |
21898 | return (a & 0xff) | (i << 7); |
21899 | } | |
bfae80f2 | 21900 | |
c19d1205 | 21901 | return FAIL; |
bfae80f2 RE |
21902 | } |
21903 | ||
c19d1205 ZW |
21904 | static int |
21905 | validate_offset_imm (unsigned int val, int hwse) | |
21906 | { | |
21907 | if ((hwse && val > 255) || val > 4095) | |
21908 | return FAIL; | |
21909 | return val; | |
21910 | } | |
bfae80f2 | 21911 | |
55cf6793 | 21912 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
21913 | negative immediate constant by altering the instruction. A bit of |
21914 | a hack really. | |
21915 | MOV <-> MVN | |
21916 | AND <-> BIC | |
21917 | ADC <-> SBC | |
21918 | by inverting the second operand, and | |
21919 | ADD <-> SUB | |
21920 | CMP <-> CMN | |
21921 | by negating the second operand. */ | |
bfae80f2 | 21922 | |
c19d1205 ZW |
21923 | static int |
21924 | negate_data_op (unsigned long * instruction, | |
21925 | unsigned long value) | |
bfae80f2 | 21926 | { |
c19d1205 ZW |
21927 | int op, new_inst; |
21928 | unsigned long negated, inverted; | |
bfae80f2 | 21929 | |
c19d1205 ZW |
21930 | negated = encode_arm_immediate (-value); |
21931 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 21932 | |
c19d1205 ZW |
21933 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
21934 | switch (op) | |
bfae80f2 | 21935 | { |
c19d1205 ZW |
21936 | /* First negates. */ |
21937 | case OPCODE_SUB: /* ADD <-> SUB */ | |
21938 | new_inst = OPCODE_ADD; | |
21939 | value = negated; | |
21940 | break; | |
bfae80f2 | 21941 | |
c19d1205 ZW |
21942 | case OPCODE_ADD: |
21943 | new_inst = OPCODE_SUB; | |
21944 | value = negated; | |
21945 | break; | |
bfae80f2 | 21946 | |
c19d1205 ZW |
21947 | case OPCODE_CMP: /* CMP <-> CMN */ |
21948 | new_inst = OPCODE_CMN; | |
21949 | value = negated; | |
21950 | break; | |
bfae80f2 | 21951 | |
c19d1205 ZW |
21952 | case OPCODE_CMN: |
21953 | new_inst = OPCODE_CMP; | |
21954 | value = negated; | |
21955 | break; | |
bfae80f2 | 21956 | |
c19d1205 ZW |
21957 | /* Now Inverted ops. */ |
21958 | case OPCODE_MOV: /* MOV <-> MVN */ | |
21959 | new_inst = OPCODE_MVN; | |
21960 | value = inverted; | |
21961 | break; | |
bfae80f2 | 21962 | |
c19d1205 ZW |
21963 | case OPCODE_MVN: |
21964 | new_inst = OPCODE_MOV; | |
21965 | value = inverted; | |
21966 | break; | |
bfae80f2 | 21967 | |
c19d1205 ZW |
21968 | case OPCODE_AND: /* AND <-> BIC */ |
21969 | new_inst = OPCODE_BIC; | |
21970 | value = inverted; | |
21971 | break; | |
bfae80f2 | 21972 | |
c19d1205 ZW |
21973 | case OPCODE_BIC: |
21974 | new_inst = OPCODE_AND; | |
21975 | value = inverted; | |
21976 | break; | |
bfae80f2 | 21977 | |
c19d1205 ZW |
21978 | case OPCODE_ADC: /* ADC <-> SBC */ |
21979 | new_inst = OPCODE_SBC; | |
21980 | value = inverted; | |
21981 | break; | |
bfae80f2 | 21982 | |
c19d1205 ZW |
21983 | case OPCODE_SBC: |
21984 | new_inst = OPCODE_ADC; | |
21985 | value = inverted; | |
21986 | break; | |
bfae80f2 | 21987 | |
c19d1205 ZW |
21988 | /* We cannot do anything. */ |
21989 | default: | |
21990 | return FAIL; | |
b99bd4ef NC |
21991 | } |
21992 | ||
c19d1205 ZW |
21993 | if (value == (unsigned) FAIL) |
21994 | return FAIL; | |
21995 | ||
21996 | *instruction &= OPCODE_MASK; | |
21997 | *instruction |= new_inst << DATA_OP_SHIFT; | |
21998 | return value; | |
b99bd4ef NC |
21999 | } |
22000 | ||
ef8d22e6 PB |
22001 | /* Like negate_data_op, but for Thumb-2. */ |
22002 | ||
22003 | static unsigned int | |
16dd5e42 | 22004 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
22005 | { |
22006 | int op, new_inst; | |
22007 | int rd; | |
16dd5e42 | 22008 | unsigned int negated, inverted; |
ef8d22e6 PB |
22009 | |
22010 | negated = encode_thumb32_immediate (-value); | |
22011 | inverted = encode_thumb32_immediate (~value); | |
22012 | ||
22013 | rd = (*instruction >> 8) & 0xf; | |
22014 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
22015 | switch (op) | |
22016 | { | |
22017 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
22018 | case T2_OPCODE_SUB: | |
22019 | new_inst = T2_OPCODE_ADD; | |
22020 | value = negated; | |
22021 | break; | |
22022 | ||
22023 | case T2_OPCODE_ADD: | |
22024 | new_inst = T2_OPCODE_SUB; | |
22025 | value = negated; | |
22026 | break; | |
22027 | ||
22028 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
22029 | case T2_OPCODE_ORR: | |
22030 | new_inst = T2_OPCODE_ORN; | |
22031 | value = inverted; | |
22032 | break; | |
22033 | ||
22034 | case T2_OPCODE_ORN: | |
22035 | new_inst = T2_OPCODE_ORR; | |
22036 | value = inverted; | |
22037 | break; | |
22038 | ||
22039 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
22040 | case T2_OPCODE_AND: | |
22041 | new_inst = T2_OPCODE_BIC; | |
22042 | if (rd == 15) | |
22043 | value = FAIL; | |
22044 | else | |
22045 | value = inverted; | |
22046 | break; | |
22047 | ||
22048 | case T2_OPCODE_BIC: | |
22049 | new_inst = T2_OPCODE_AND; | |
22050 | value = inverted; | |
22051 | break; | |
22052 | ||
22053 | /* ADC <-> SBC */ | |
22054 | case T2_OPCODE_ADC: | |
22055 | new_inst = T2_OPCODE_SBC; | |
22056 | value = inverted; | |
22057 | break; | |
22058 | ||
22059 | case T2_OPCODE_SBC: | |
22060 | new_inst = T2_OPCODE_ADC; | |
22061 | value = inverted; | |
22062 | break; | |
22063 | ||
22064 | /* We cannot do anything. */ | |
22065 | default: | |
22066 | return FAIL; | |
22067 | } | |
22068 | ||
16dd5e42 | 22069 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
22070 | return FAIL; |
22071 | ||
22072 | *instruction &= T2_OPCODE_MASK; | |
22073 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
22074 | return value; | |
22075 | } | |
22076 | ||
8f06b2d8 PB |
22077 | /* Read a 32-bit thumb instruction from buf. */ |
22078 | static unsigned long | |
22079 | get_thumb32_insn (char * buf) | |
22080 | { | |
22081 | unsigned long insn; | |
22082 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
22083 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22084 | ||
22085 | return insn; | |
22086 | } | |
22087 | ||
a8bc6c78 PB |
22088 | |
22089 | /* We usually want to set the low bit on the address of thumb function | |
22090 | symbols. In particular .word foo - . should have the low bit set. | |
22091 | Generic code tries to fold the difference of two symbols to | |
22092 | a constant. Prevent this and force a relocation when the first symbols | |
22093 | is a thumb function. */ | |
c921be7d NC |
22094 | |
22095 | bfd_boolean | |
a8bc6c78 PB |
22096 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
22097 | { | |
22098 | if (op == O_subtract | |
22099 | && l->X_op == O_symbol | |
22100 | && r->X_op == O_symbol | |
22101 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
22102 | { | |
22103 | l->X_op = O_subtract; | |
22104 | l->X_op_symbol = r->X_add_symbol; | |
22105 | l->X_add_number -= r->X_add_number; | |
c921be7d | 22106 | return TRUE; |
a8bc6c78 | 22107 | } |
c921be7d | 22108 | |
a8bc6c78 | 22109 | /* Process as normal. */ |
c921be7d | 22110 | return FALSE; |
a8bc6c78 PB |
22111 | } |
22112 | ||
4a42ebbc RR |
22113 | /* Encode Thumb2 unconditional branches and calls. The encoding |
22114 | for the 2 are identical for the immediate values. */ | |
22115 | ||
22116 | static void | |
22117 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
22118 | { | |
22119 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
22120 | offsetT newval; | |
22121 | offsetT newval2; | |
22122 | addressT S, I1, I2, lo, hi; | |
22123 | ||
22124 | S = (value >> 24) & 0x01; | |
22125 | I1 = (value >> 23) & 0x01; | |
22126 | I2 = (value >> 22) & 0x01; | |
22127 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 22128 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
22129 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22130 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22131 | newval |= (S << 10) | hi; | |
22132 | newval2 &= ~T2I1I2MASK; | |
22133 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
22134 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22135 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
22136 | } | |
22137 | ||
c19d1205 | 22138 | void |
55cf6793 | 22139 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
22140 | valueT * valP, |
22141 | segT seg) | |
22142 | { | |
22143 | offsetT value = * valP; | |
22144 | offsetT newval; | |
22145 | unsigned int newimm; | |
22146 | unsigned long temp; | |
22147 | int sign; | |
22148 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 22149 | |
9c2799c2 | 22150 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 22151 | |
c19d1205 | 22152 | /* Note whether this will delete the relocation. */ |
4962c51a | 22153 | |
c19d1205 ZW |
22154 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
22155 | fixP->fx_done = 1; | |
b99bd4ef | 22156 | |
adbaf948 | 22157 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 22158 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
22159 | for emit_reloc. */ |
22160 | value &= 0xffffffff; | |
22161 | value ^= 0x80000000; | |
5f4273c7 | 22162 | value -= 0x80000000; |
adbaf948 ZW |
22163 | |
22164 | *valP = value; | |
c19d1205 | 22165 | fixP->fx_addnumber = value; |
b99bd4ef | 22166 | |
adbaf948 ZW |
22167 | /* Same treatment for fixP->fx_offset. */ |
22168 | fixP->fx_offset &= 0xffffffff; | |
22169 | fixP->fx_offset ^= 0x80000000; | |
22170 | fixP->fx_offset -= 0x80000000; | |
22171 | ||
c19d1205 | 22172 | switch (fixP->fx_r_type) |
b99bd4ef | 22173 | { |
c19d1205 ZW |
22174 | case BFD_RELOC_NONE: |
22175 | /* This will need to go in the object file. */ | |
22176 | fixP->fx_done = 0; | |
22177 | break; | |
b99bd4ef | 22178 | |
c19d1205 ZW |
22179 | case BFD_RELOC_ARM_IMMEDIATE: |
22180 | /* We claim that this fixup has been processed here, | |
22181 | even if in fact we generate an error because we do | |
22182 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
22183 | fixP->fx_done = 1; | |
b99bd4ef | 22184 | |
77db8e2e | 22185 | if (fixP->fx_addsy) |
b99bd4ef | 22186 | { |
77db8e2e | 22187 | const char *msg = 0; |
b99bd4ef | 22188 | |
77db8e2e NC |
22189 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
22190 | msg = _("undefined symbol %s used as an immediate value"); | |
22191 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
22192 | msg = _("symbol %s is in a different section"); | |
22193 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
22194 | msg = _("symbol %s is weak and may be overridden later"); | |
22195 | ||
22196 | if (msg) | |
22197 | { | |
22198 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22199 | msg, S_GET_NAME (fixP->fx_addsy)); | |
22200 | break; | |
22201 | } | |
42e5fcbf AS |
22202 | } |
22203 | ||
c19d1205 ZW |
22204 | temp = md_chars_to_number (buf, INSN_SIZE); |
22205 | ||
5e73442d SL |
22206 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
22207 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
22208 | newimm = negate_data_op (&temp, value); | |
22209 | else | |
22210 | { | |
22211 | newimm = encode_arm_immediate (value); | |
22212 | ||
22213 | /* If the instruction will fail, see if we can fix things up by | |
22214 | changing the opcode. */ | |
22215 | if (newimm == (unsigned int) FAIL) | |
22216 | newimm = negate_data_op (&temp, value); | |
22217 | } | |
22218 | ||
22219 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 22220 | { |
c19d1205 ZW |
22221 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22222 | _("invalid constant (%lx) after fixup"), | |
22223 | (unsigned long) value); | |
22224 | break; | |
b99bd4ef | 22225 | } |
b99bd4ef | 22226 | |
c19d1205 ZW |
22227 | newimm |= (temp & 0xfffff000); |
22228 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
22229 | break; | |
b99bd4ef | 22230 | |
c19d1205 ZW |
22231 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
22232 | { | |
22233 | unsigned int highpart = 0; | |
22234 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 22235 | |
77db8e2e | 22236 | if (fixP->fx_addsy) |
42e5fcbf | 22237 | { |
77db8e2e | 22238 | const char *msg = 0; |
42e5fcbf | 22239 | |
77db8e2e NC |
22240 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
22241 | msg = _("undefined symbol %s used as an immediate value"); | |
22242 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
22243 | msg = _("symbol %s is in a different section"); | |
22244 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
22245 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 22246 | |
77db8e2e NC |
22247 | if (msg) |
22248 | { | |
22249 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22250 | msg, S_GET_NAME (fixP->fx_addsy)); | |
22251 | break; | |
22252 | } | |
22253 | } | |
fa94de6b | 22254 | |
c19d1205 ZW |
22255 | newimm = encode_arm_immediate (value); |
22256 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 22257 | |
c19d1205 ZW |
22258 | /* If the instruction will fail, see if we can fix things up by |
22259 | changing the opcode. */ | |
22260 | if (newimm == (unsigned int) FAIL | |
22261 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
22262 | { | |
22263 | /* No ? OK - try using two ADD instructions to generate | |
22264 | the value. */ | |
22265 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 22266 | |
c19d1205 ZW |
22267 | /* Yes - then make sure that the second instruction is |
22268 | also an add. */ | |
22269 | if (newimm != (unsigned int) FAIL) | |
22270 | newinsn = temp; | |
22271 | /* Still No ? Try using a negated value. */ | |
22272 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
22273 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
22274 | /* Otherwise - give up. */ | |
22275 | else | |
22276 | { | |
22277 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22278 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
22279 | (long) value); | |
22280 | break; | |
22281 | } | |
b99bd4ef | 22282 | |
c19d1205 ZW |
22283 | /* Replace the first operand in the 2nd instruction (which |
22284 | is the PC) with the destination register. We have | |
22285 | already added in the PC in the first instruction and we | |
22286 | do not want to do it again. */ | |
22287 | newinsn &= ~ 0xf0000; | |
22288 | newinsn |= ((newinsn & 0x0f000) << 4); | |
22289 | } | |
b99bd4ef | 22290 | |
c19d1205 ZW |
22291 | newimm |= (temp & 0xfffff000); |
22292 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 22293 | |
c19d1205 ZW |
22294 | highpart |= (newinsn & 0xfffff000); |
22295 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
22296 | } | |
22297 | break; | |
b99bd4ef | 22298 | |
c19d1205 | 22299 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
22300 | if (!fixP->fx_done && seg->use_rela_p) |
22301 | value = 0; | |
22302 | ||
c19d1205 | 22303 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 22304 | sign = value > 0; |
b99bd4ef | 22305 | |
c19d1205 ZW |
22306 | if (value < 0) |
22307 | value = - value; | |
b99bd4ef | 22308 | |
c19d1205 | 22309 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 22310 | { |
c19d1205 ZW |
22311 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
22312 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22313 | _("invalid literal constant: pool needs to be closer")); | |
22314 | else | |
22315 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22316 | _("bad immediate value for offset (%ld)"), | |
22317 | (long) value); | |
22318 | break; | |
f03698e6 RE |
22319 | } |
22320 | ||
c19d1205 | 22321 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22322 | if (value == 0) |
22323 | newval &= 0xfffff000; | |
22324 | else | |
22325 | { | |
22326 | newval &= 0xff7ff000; | |
22327 | newval |= value | (sign ? INDEX_UP : 0); | |
22328 | } | |
c19d1205 ZW |
22329 | md_number_to_chars (buf, newval, INSN_SIZE); |
22330 | break; | |
b99bd4ef | 22331 | |
c19d1205 ZW |
22332 | case BFD_RELOC_ARM_OFFSET_IMM8: |
22333 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 22334 | sign = value > 0; |
b99bd4ef | 22335 | |
c19d1205 ZW |
22336 | if (value < 0) |
22337 | value = - value; | |
b99bd4ef | 22338 | |
c19d1205 | 22339 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 22340 | { |
c19d1205 ZW |
22341 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
22342 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22343 | _("invalid literal constant: pool needs to be closer")); | |
22344 | else | |
427d0db6 RM |
22345 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22346 | _("bad immediate value for 8-bit offset (%ld)"), | |
22347 | (long) value); | |
c19d1205 | 22348 | break; |
b99bd4ef NC |
22349 | } |
22350 | ||
c19d1205 | 22351 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
22352 | if (value == 0) |
22353 | newval &= 0xfffff0f0; | |
22354 | else | |
22355 | { | |
22356 | newval &= 0xff7ff0f0; | |
22357 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
22358 | } | |
c19d1205 ZW |
22359 | md_number_to_chars (buf, newval, INSN_SIZE); |
22360 | break; | |
b99bd4ef | 22361 | |
c19d1205 ZW |
22362 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
22363 | if (value < 0 || value > 1020 || value % 4 != 0) | |
22364 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22365 | _("bad immediate value for offset (%ld)"), (long) value); | |
22366 | value /= 4; | |
b99bd4ef | 22367 | |
c19d1205 | 22368 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
22369 | newval |= value; |
22370 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
22371 | break; | |
b99bd4ef | 22372 | |
c19d1205 ZW |
22373 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
22374 | /* This is a complicated relocation used for all varieties of Thumb32 | |
22375 | load/store instruction with immediate offset: | |
22376 | ||
22377 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
477330fc | 22378 | *4, optional writeback(W) |
c19d1205 ZW |
22379 | (doubleword load/store) |
22380 | ||
22381 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
22382 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
22383 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
22384 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
22385 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
22386 | ||
22387 | Uppercase letters indicate bits that are already encoded at | |
22388 | this point. Lowercase letters are our problem. For the | |
22389 | second block of instructions, the secondary opcode nybble | |
22390 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
22391 | a PC-relative operation. */ | |
22392 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22393 | newval <<= 16; | |
22394 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 22395 | |
c19d1205 | 22396 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 22397 | { |
c19d1205 ZW |
22398 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
22399 | if (value >= 0) | |
22400 | newval |= (1 << 23); | |
22401 | else | |
22402 | value = -value; | |
22403 | if (value % 4 != 0) | |
22404 | { | |
22405 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22406 | _("offset not a multiple of 4")); | |
22407 | break; | |
22408 | } | |
22409 | value /= 4; | |
216d22bc | 22410 | if (value > 0xff) |
c19d1205 ZW |
22411 | { |
22412 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22413 | _("offset out of range")); | |
22414 | break; | |
22415 | } | |
22416 | newval &= ~0xff; | |
b99bd4ef | 22417 | } |
c19d1205 | 22418 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 22419 | { |
c19d1205 ZW |
22420 | /* PC-relative, 12-bit offset. */ |
22421 | if (value >= 0) | |
22422 | newval |= (1 << 23); | |
22423 | else | |
22424 | value = -value; | |
216d22bc | 22425 | if (value > 0xfff) |
c19d1205 ZW |
22426 | { |
22427 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22428 | _("offset out of range")); | |
22429 | break; | |
22430 | } | |
22431 | newval &= ~0xfff; | |
b99bd4ef | 22432 | } |
c19d1205 | 22433 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 22434 | { |
c19d1205 ZW |
22435 | /* Writeback: 8-bit, +/- offset. */ |
22436 | if (value >= 0) | |
22437 | newval |= (1 << 9); | |
22438 | else | |
22439 | value = -value; | |
216d22bc | 22440 | if (value > 0xff) |
c19d1205 ZW |
22441 | { |
22442 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22443 | _("offset out of range")); | |
22444 | break; | |
22445 | } | |
22446 | newval &= ~0xff; | |
b99bd4ef | 22447 | } |
c19d1205 | 22448 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 22449 | { |
c19d1205 | 22450 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 22451 | if (value < 0 || value > 0xff) |
b99bd4ef | 22452 | { |
c19d1205 ZW |
22453 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22454 | _("offset out of range")); | |
22455 | break; | |
b99bd4ef | 22456 | } |
c19d1205 ZW |
22457 | newval &= ~0xff; |
22458 | newval |= value; | |
b99bd4ef NC |
22459 | } |
22460 | else | |
b99bd4ef | 22461 | { |
c19d1205 ZW |
22462 | /* Positive 12-bit or negative 8-bit offset. */ |
22463 | int limit; | |
22464 | if (value >= 0) | |
b99bd4ef | 22465 | { |
c19d1205 ZW |
22466 | newval |= (1 << 23); |
22467 | limit = 0xfff; | |
22468 | } | |
22469 | else | |
22470 | { | |
22471 | value = -value; | |
22472 | limit = 0xff; | |
22473 | } | |
22474 | if (value > limit) | |
22475 | { | |
22476 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22477 | _("offset out of range")); | |
22478 | break; | |
b99bd4ef | 22479 | } |
c19d1205 | 22480 | newval &= ~limit; |
b99bd4ef | 22481 | } |
b99bd4ef | 22482 | |
c19d1205 ZW |
22483 | newval |= value; |
22484 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
22485 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
22486 | break; | |
404ff6b5 | 22487 | |
c19d1205 ZW |
22488 | case BFD_RELOC_ARM_SHIFT_IMM: |
22489 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22490 | if (((unsigned long) value) > 32 | |
22491 | || (value == 32 | |
22492 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
22493 | { | |
22494 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22495 | _("shift expression is too large")); | |
22496 | break; | |
22497 | } | |
404ff6b5 | 22498 | |
c19d1205 ZW |
22499 | if (value == 0) |
22500 | /* Shifts of zero must be done as lsl. */ | |
22501 | newval &= ~0x60; | |
22502 | else if (value == 32) | |
22503 | value = 0; | |
22504 | newval &= 0xfffff07f; | |
22505 | newval |= (value & 0x1f) << 7; | |
22506 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22507 | break; | |
404ff6b5 | 22508 | |
c19d1205 | 22509 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 22510 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 22511 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 22512 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
22513 | /* We claim that this fixup has been processed here, |
22514 | even if in fact we generate an error because we do | |
22515 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
22516 | fixP->fx_done = 1; | |
404ff6b5 | 22517 | |
c19d1205 ZW |
22518 | if (fixP->fx_addsy |
22519 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
22520 | { | |
22521 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22522 | _("undefined symbol %s used as an immediate value"), | |
22523 | S_GET_NAME (fixP->fx_addsy)); | |
22524 | break; | |
22525 | } | |
404ff6b5 | 22526 | |
c19d1205 ZW |
22527 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22528 | newval <<= 16; | |
22529 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 22530 | |
16805f35 PB |
22531 | newimm = FAIL; |
22532 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
22533 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
22534 | { |
22535 | newimm = encode_thumb32_immediate (value); | |
22536 | if (newimm == (unsigned int) FAIL) | |
22537 | newimm = thumb32_negate_data_op (&newval, value); | |
22538 | } | |
16805f35 PB |
22539 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
22540 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 22541 | { |
16805f35 PB |
22542 | /* Turn add/sum into addw/subw. */ |
22543 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
22544 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
22545 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
22546 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 22547 | { |
40f246e3 NC |
22548 | /* 12 bit immediate for addw/subw. */ |
22549 | if (value < 0) | |
22550 | { | |
22551 | value = -value; | |
22552 | newval ^= 0x00a00000; | |
22553 | } | |
22554 | if (value > 0xfff) | |
22555 | newimm = (unsigned int) FAIL; | |
22556 | else | |
22557 | newimm = value; | |
e9f89963 | 22558 | } |
92e90b6e | 22559 | } |
cc8a6dd0 | 22560 | |
c19d1205 | 22561 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 22562 | { |
c19d1205 ZW |
22563 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22564 | _("invalid constant (%lx) after fixup"), | |
22565 | (unsigned long) value); | |
22566 | break; | |
3631a3c8 NC |
22567 | } |
22568 | ||
c19d1205 ZW |
22569 | newval |= (newimm & 0x800) << 15; |
22570 | newval |= (newimm & 0x700) << 4; | |
22571 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 22572 | |
c19d1205 ZW |
22573 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
22574 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
22575 | break; | |
a737bd4d | 22576 | |
3eb17e6b | 22577 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
22578 | if (((unsigned long) value) > 0xffff) |
22579 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 22580 | _("invalid smc expression")); |
2fc8bdac | 22581 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22582 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
22583 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22584 | break; | |
a737bd4d | 22585 | |
90ec0d68 MGD |
22586 | case BFD_RELOC_ARM_HVC: |
22587 | if (((unsigned long) value) > 0xffff) | |
22588 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22589 | _("invalid hvc expression")); | |
22590 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22591 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
22592 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22593 | break; | |
22594 | ||
c19d1205 | 22595 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 22596 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
22597 | { |
22598 | if (((unsigned long) value) > 0xff) | |
22599 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22600 | _("invalid swi expression")); | |
2fc8bdac | 22601 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
22602 | newval |= value; |
22603 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22604 | } | |
22605 | else | |
22606 | { | |
22607 | if (((unsigned long) value) > 0x00ffffff) | |
22608 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22609 | _("invalid swi expression")); | |
2fc8bdac | 22610 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
22611 | newval |= value; |
22612 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22613 | } | |
22614 | break; | |
a737bd4d | 22615 | |
c19d1205 ZW |
22616 | case BFD_RELOC_ARM_MULTI: |
22617 | if (((unsigned long) value) > 0xffff) | |
22618 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22619 | _("invalid expression in load/store multiple")); | |
22620 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
22621 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22622 | break; | |
a737bd4d | 22623 | |
c19d1205 | 22624 | #ifdef OBJ_ELF |
39b41c9c | 22625 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
22626 | |
22627 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
22628 | && fixP->fx_addsy | |
34e77a92 | 22629 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22630 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22631 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22632 | /* Flip the bl to blx. This is a simple flip | |
22633 | bit here because we generate PCREL_CALL for | |
22634 | unconditional bls. */ | |
22635 | { | |
22636 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22637 | newval = newval | 0x10000000; | |
22638 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22639 | temp = 1; | |
22640 | fixP->fx_done = 1; | |
22641 | } | |
39b41c9c PB |
22642 | else |
22643 | temp = 3; | |
22644 | goto arm_branch_common; | |
22645 | ||
22646 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
22647 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22648 | && fixP->fx_addsy | |
34e77a92 | 22649 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22650 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22651 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22652 | { | |
22653 | /* This would map to a bl<cond>, b<cond>, | |
22654 | b<always> to a Thumb function. We | |
22655 | need to force a relocation for this particular | |
22656 | case. */ | |
22657 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22658 | fixP->fx_done = 0; | |
22659 | } | |
22660 | ||
2fc8bdac | 22661 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 22662 | #endif |
39b41c9c PB |
22663 | case BFD_RELOC_ARM_PCREL_BRANCH: |
22664 | temp = 3; | |
22665 | goto arm_branch_common; | |
a737bd4d | 22666 | |
39b41c9c | 22667 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 22668 | |
39b41c9c | 22669 | temp = 1; |
267bf995 RR |
22670 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
22671 | && fixP->fx_addsy | |
34e77a92 | 22672 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22673 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22674 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
22675 | { | |
22676 | /* Flip the blx to a bl and warn. */ | |
22677 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22678 | newval = 0xeb000000; | |
22679 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22680 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
22681 | name); | |
22682 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22683 | temp = 3; | |
22684 | fixP->fx_done = 1; | |
22685 | } | |
22686 | ||
22687 | #ifdef OBJ_ELF | |
22688 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
477330fc | 22689 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; |
267bf995 RR |
22690 | #endif |
22691 | ||
39b41c9c | 22692 | arm_branch_common: |
c19d1205 | 22693 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
22694 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
22695 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
22696 | also be be clear. */ | |
22697 | if (value & temp) | |
c19d1205 | 22698 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
22699 | _("misaligned branch destination")); |
22700 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
22701 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 22702 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22703 | |
2fc8bdac | 22704 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22705 | { |
2fc8bdac ZW |
22706 | newval = md_chars_to_number (buf, INSN_SIZE); |
22707 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
22708 | /* Set the H bit on BLX instructions. */ |
22709 | if (temp == 1) | |
22710 | { | |
22711 | if (value & 2) | |
22712 | newval |= 0x01000000; | |
22713 | else | |
22714 | newval &= ~0x01000000; | |
22715 | } | |
2fc8bdac | 22716 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 22717 | } |
c19d1205 | 22718 | break; |
a737bd4d | 22719 | |
25fe350b MS |
22720 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
22721 | /* CBZ can only branch forward. */ | |
a737bd4d | 22722 | |
738755b0 | 22723 | /* Attempts to use CBZ to branch to the next instruction |
477330fc RM |
22724 | (which, strictly speaking, are prohibited) will be turned into |
22725 | no-ops. | |
738755b0 MS |
22726 | |
22727 | FIXME: It may be better to remove the instruction completely and | |
22728 | perform relaxation. */ | |
22729 | if (value == -2) | |
2fc8bdac ZW |
22730 | { |
22731 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 22732 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
22733 | md_number_to_chars (buf, newval, THUMB_SIZE); |
22734 | } | |
738755b0 MS |
22735 | else |
22736 | { | |
22737 | if (value & ~0x7e) | |
08f10d51 | 22738 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 | 22739 | |
477330fc | 22740 | if (fixP->fx_done || !seg->use_rela_p) |
738755b0 MS |
22741 | { |
22742 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22743 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
22744 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22745 | } | |
22746 | } | |
c19d1205 | 22747 | break; |
a737bd4d | 22748 | |
c19d1205 | 22749 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 22750 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 22751 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22752 | |
2fc8bdac ZW |
22753 | if (fixP->fx_done || !seg->use_rela_p) |
22754 | { | |
22755 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22756 | newval |= (value & 0x1ff) >> 1; | |
22757 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22758 | } | |
c19d1205 | 22759 | break; |
a737bd4d | 22760 | |
c19d1205 | 22761 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 22762 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 22763 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 22764 | |
2fc8bdac ZW |
22765 | if (fixP->fx_done || !seg->use_rela_p) |
22766 | { | |
22767 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22768 | newval |= (value & 0xfff) >> 1; | |
22769 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22770 | } | |
c19d1205 | 22771 | break; |
a737bd4d | 22772 | |
c19d1205 | 22773 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
22774 | if (fixP->fx_addsy |
22775 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22776 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22777 | && ARM_IS_FUNC (fixP->fx_addsy) |
22778 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22779 | { | |
22780 | /* Force a relocation for a branch 20 bits wide. */ | |
22781 | fixP->fx_done = 0; | |
22782 | } | |
08f10d51 | 22783 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
22784 | as_bad_where (fixP->fx_file, fixP->fx_line, |
22785 | _("conditional branch out of range")); | |
404ff6b5 | 22786 | |
2fc8bdac ZW |
22787 | if (fixP->fx_done || !seg->use_rela_p) |
22788 | { | |
22789 | offsetT newval2; | |
22790 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 22791 | |
2fc8bdac ZW |
22792 | S = (value & 0x00100000) >> 20; |
22793 | J2 = (value & 0x00080000) >> 19; | |
22794 | J1 = (value & 0x00040000) >> 18; | |
22795 | hi = (value & 0x0003f000) >> 12; | |
22796 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 22797 | |
2fc8bdac ZW |
22798 | newval = md_chars_to_number (buf, THUMB_SIZE); |
22799 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22800 | newval |= (S << 10) | hi; | |
22801 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
22802 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
22803 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
22804 | } | |
c19d1205 | 22805 | break; |
6c43fab6 | 22806 | |
c19d1205 | 22807 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
22808 | /* If there is a blx from a thumb state function to |
22809 | another thumb function flip this to a bl and warn | |
22810 | about it. */ | |
22811 | ||
22812 | if (fixP->fx_addsy | |
34e77a92 | 22813 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22814 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
22815 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
22816 | { | |
22817 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
22818 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
22819 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
22820 | name); | |
22821 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22822 | newval = newval | 0x1000; | |
22823 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22824 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22825 | fixP->fx_done = 1; | |
22826 | } | |
22827 | ||
22828 | ||
22829 | goto thumb_bl_common; | |
22830 | ||
c19d1205 | 22831 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
22832 | /* A bl from Thumb state ISA to an internal ARM state function |
22833 | is converted to a blx. */ | |
22834 | if (fixP->fx_addsy | |
22835 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 22836 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
22837 | && ARM_IS_FUNC (fixP->fx_addsy) |
22838 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
22839 | { | |
22840 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
22841 | newval = newval & ~0x1000; | |
22842 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
22843 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
22844 | fixP->fx_done = 1; | |
22845 | } | |
22846 | ||
22847 | thumb_bl_common: | |
22848 | ||
2fc8bdac ZW |
22849 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
22850 | /* For a BLX instruction, make sure that the relocation is rounded up | |
22851 | to a word boundary. This follows the semantics of the instruction | |
22852 | which specifies that bit 1 of the target address will come from bit | |
22853 | 1 of the base address. */ | |
d406f3e4 JB |
22854 | value = (value + 3) & ~ 3; |
22855 | ||
22856 | #ifdef OBJ_ELF | |
22857 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 | |
22858 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
22859 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22860 | #endif | |
404ff6b5 | 22861 | |
2b2f5df9 NC |
22862 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
22863 | { | |
22864 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
22865 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
22866 | else if ((value & ~0x1ffffff) | |
22867 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
22868 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22869 | _("Thumb2 branch out of range")); | |
22870 | } | |
4a42ebbc RR |
22871 | |
22872 | if (fixP->fx_done || !seg->use_rela_p) | |
22873 | encode_thumb2_b_bl_offset (buf, value); | |
22874 | ||
c19d1205 | 22875 | break; |
404ff6b5 | 22876 | |
c19d1205 | 22877 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
22878 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
22879 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 22880 | |
2fc8bdac | 22881 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 22882 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 22883 | |
2fc8bdac | 22884 | break; |
a737bd4d | 22885 | |
2fc8bdac ZW |
22886 | case BFD_RELOC_8: |
22887 | if (fixP->fx_done || !seg->use_rela_p) | |
4b1a927e | 22888 | *buf = value; |
c19d1205 | 22889 | break; |
a737bd4d | 22890 | |
c19d1205 | 22891 | case BFD_RELOC_16: |
2fc8bdac | 22892 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 22893 | md_number_to_chars (buf, value, 2); |
c19d1205 | 22894 | break; |
a737bd4d | 22895 | |
c19d1205 | 22896 | #ifdef OBJ_ELF |
0855e32b NS |
22897 | case BFD_RELOC_ARM_TLS_CALL: |
22898 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
22899 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
22900 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
0855e32b | 22901 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
22902 | case BFD_RELOC_ARM_TLS_GD32: |
22903 | case BFD_RELOC_ARM_TLS_LE32: | |
22904 | case BFD_RELOC_ARM_TLS_IE32: | |
22905 | case BFD_RELOC_ARM_TLS_LDM32: | |
22906 | case BFD_RELOC_ARM_TLS_LDO32: | |
22907 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4b1a927e | 22908 | break; |
6c43fab6 | 22909 | |
c19d1205 ZW |
22910 | case BFD_RELOC_ARM_GOT32: |
22911 | case BFD_RELOC_ARM_GOTOFF: | |
c19d1205 | 22912 | break; |
b43420e6 NC |
22913 | |
22914 | case BFD_RELOC_ARM_GOT_PREL: | |
22915 | if (fixP->fx_done || !seg->use_rela_p) | |
477330fc | 22916 | md_number_to_chars (buf, value, 4); |
b43420e6 NC |
22917 | break; |
22918 | ||
9a6f4e97 NS |
22919 | case BFD_RELOC_ARM_TARGET2: |
22920 | /* TARGET2 is not partial-inplace, so we need to write the | |
477330fc RM |
22921 | addend here for REL targets, because it won't be written out |
22922 | during reloc processing later. */ | |
9a6f4e97 NS |
22923 | if (fixP->fx_done || !seg->use_rela_p) |
22924 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
22925 | break; | |
c19d1205 | 22926 | #endif |
6c43fab6 | 22927 | |
c19d1205 ZW |
22928 | case BFD_RELOC_RVA: |
22929 | case BFD_RELOC_32: | |
22930 | case BFD_RELOC_ARM_TARGET1: | |
22931 | case BFD_RELOC_ARM_ROSEGREL32: | |
22932 | case BFD_RELOC_ARM_SBREL32: | |
22933 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
22934 | #ifdef TE_PE |
22935 | case BFD_RELOC_32_SECREL: | |
22936 | #endif | |
2fc8bdac | 22937 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
22938 | #ifdef TE_WINCE |
22939 | /* For WinCE we only do this for pcrel fixups. */ | |
22940 | if (fixP->fx_done || fixP->fx_pcrel) | |
22941 | #endif | |
22942 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 22943 | break; |
6c43fab6 | 22944 | |
c19d1205 ZW |
22945 | #ifdef OBJ_ELF |
22946 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 22947 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
22948 | { |
22949 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
22950 | if ((value ^ (value >> 1)) & 0x40000000) | |
22951 | { | |
22952 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22953 | _("rel31 relocation overflow")); | |
22954 | } | |
22955 | newval |= value & 0x7fffffff; | |
22956 | md_number_to_chars (buf, newval, 4); | |
22957 | } | |
22958 | break; | |
c19d1205 | 22959 | #endif |
a737bd4d | 22960 | |
c19d1205 | 22961 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 22962 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
22963 | if (value < -1023 || value > 1023 || (value & 3)) |
22964 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22965 | _("co-processor offset out of range")); | |
22966 | cp_off_common: | |
26d97720 | 22967 | sign = value > 0; |
c19d1205 ZW |
22968 | if (value < 0) |
22969 | value = -value; | |
8f06b2d8 PB |
22970 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22971 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
22972 | newval = md_chars_to_number (buf, INSN_SIZE); | |
22973 | else | |
22974 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
22975 | if (value == 0) |
22976 | newval &= 0xffffff00; | |
22977 | else | |
22978 | { | |
22979 | newval &= 0xff7fff00; | |
22980 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
22981 | } | |
8f06b2d8 PB |
22982 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22983 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
22984 | md_number_to_chars (buf, newval, INSN_SIZE); | |
22985 | else | |
22986 | put_thumb32_insn (buf, newval); | |
c19d1205 | 22987 | break; |
a737bd4d | 22988 | |
c19d1205 | 22989 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 22990 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
22991 | if (value < -255 || value > 255) |
22992 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
22993 | _("co-processor offset out of range")); | |
df7849c5 | 22994 | value *= 4; |
c19d1205 | 22995 | goto cp_off_common; |
6c43fab6 | 22996 | |
c19d1205 ZW |
22997 | case BFD_RELOC_ARM_THUMB_OFFSET: |
22998 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
22999 | /* Exactly what ranges, and where the offset is inserted depends | |
23000 | on the type of instruction, we can establish this from the | |
23001 | top 4 bits. */ | |
23002 | switch (newval >> 12) | |
23003 | { | |
23004 | case 4: /* PC load. */ | |
23005 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
23006 | forced to zero for these loads; md_pcrel_from has already | |
23007 | compensated for this. */ | |
23008 | if (value & 3) | |
23009 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23010 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
23011 | (((unsigned long) fixP->fx_frag->fr_address |
23012 | + (unsigned long) fixP->fx_where) & ~3) | |
23013 | + (unsigned long) value); | |
a737bd4d | 23014 | |
c19d1205 ZW |
23015 | if (value & ~0x3fc) |
23016 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23017 | _("invalid offset, value too big (0x%08lX)"), | |
23018 | (long) value); | |
a737bd4d | 23019 | |
c19d1205 ZW |
23020 | newval |= value >> 2; |
23021 | break; | |
a737bd4d | 23022 | |
c19d1205 ZW |
23023 | case 9: /* SP load/store. */ |
23024 | if (value & ~0x3fc) | |
23025 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23026 | _("invalid offset, value too big (0x%08lX)"), | |
23027 | (long) value); | |
23028 | newval |= value >> 2; | |
23029 | break; | |
6c43fab6 | 23030 | |
c19d1205 ZW |
23031 | case 6: /* Word load/store. */ |
23032 | if (value & ~0x7c) | |
23033 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23034 | _("invalid offset, value too big (0x%08lX)"), | |
23035 | (long) value); | |
23036 | newval |= value << 4; /* 6 - 2. */ | |
23037 | break; | |
a737bd4d | 23038 | |
c19d1205 ZW |
23039 | case 7: /* Byte load/store. */ |
23040 | if (value & ~0x1f) | |
23041 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23042 | _("invalid offset, value too big (0x%08lX)"), | |
23043 | (long) value); | |
23044 | newval |= value << 6; | |
23045 | break; | |
a737bd4d | 23046 | |
c19d1205 ZW |
23047 | case 8: /* Halfword load/store. */ |
23048 | if (value & ~0x3e) | |
23049 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23050 | _("invalid offset, value too big (0x%08lX)"), | |
23051 | (long) value); | |
23052 | newval |= value << 5; /* 6 - 1. */ | |
23053 | break; | |
a737bd4d | 23054 | |
c19d1205 ZW |
23055 | default: |
23056 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23057 | "Unable to process relocation for thumb opcode: %lx", | |
23058 | (unsigned long) newval); | |
23059 | break; | |
23060 | } | |
23061 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23062 | break; | |
a737bd4d | 23063 | |
c19d1205 ZW |
23064 | case BFD_RELOC_ARM_THUMB_ADD: |
23065 | /* This is a complicated relocation, since we use it for all of | |
23066 | the following immediate relocations: | |
a737bd4d | 23067 | |
c19d1205 ZW |
23068 | 3bit ADD/SUB |
23069 | 8bit ADD/SUB | |
23070 | 9bit ADD/SUB SP word-aligned | |
23071 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 23072 | |
c19d1205 ZW |
23073 | The type of instruction being processed is encoded in the |
23074 | instruction field: | |
a737bd4d | 23075 | |
c19d1205 ZW |
23076 | 0x8000 SUB |
23077 | 0x00F0 Rd | |
23078 | 0x000F Rs | |
23079 | */ | |
23080 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23081 | { | |
23082 | int rd = (newval >> 4) & 0xf; | |
23083 | int rs = newval & 0xf; | |
23084 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 23085 | |
c19d1205 ZW |
23086 | /* Check for HI regs, only very restricted cases allowed: |
23087 | Adjusting SP, and using PC or SP to get an address. */ | |
23088 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
23089 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
23090 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23091 | _("invalid Hi register with immediate")); | |
a737bd4d | 23092 | |
c19d1205 ZW |
23093 | /* If value is negative, choose the opposite instruction. */ |
23094 | if (value < 0) | |
23095 | { | |
23096 | value = -value; | |
23097 | subtract = !subtract; | |
23098 | if (value < 0) | |
23099 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23100 | _("immediate value out of range")); | |
23101 | } | |
a737bd4d | 23102 | |
c19d1205 ZW |
23103 | if (rd == REG_SP) |
23104 | { | |
75c11999 | 23105 | if (value & ~0x1fc) |
c19d1205 ZW |
23106 | as_bad_where (fixP->fx_file, fixP->fx_line, |
23107 | _("invalid immediate for stack address calculation")); | |
23108 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
23109 | newval |= value >> 2; | |
23110 | } | |
23111 | else if (rs == REG_PC || rs == REG_SP) | |
23112 | { | |
c12d2c9d NC |
23113 | /* PR gas/18541. If the addition is for a defined symbol |
23114 | within range of an ADR instruction then accept it. */ | |
23115 | if (subtract | |
23116 | && value == 4 | |
23117 | && fixP->fx_addsy != NULL) | |
23118 | { | |
23119 | subtract = 0; | |
23120 | ||
23121 | if (! S_IS_DEFINED (fixP->fx_addsy) | |
23122 | || S_GET_SEGMENT (fixP->fx_addsy) != seg | |
23123 | || S_IS_WEAK (fixP->fx_addsy)) | |
23124 | { | |
23125 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23126 | _("address calculation needs a strongly defined nearby symbol")); | |
23127 | } | |
23128 | else | |
23129 | { | |
23130 | offsetT v = fixP->fx_where + fixP->fx_frag->fr_address; | |
23131 | ||
23132 | /* Round up to the next 4-byte boundary. */ | |
23133 | if (v & 3) | |
23134 | v = (v + 3) & ~ 3; | |
23135 | else | |
23136 | v += 4; | |
23137 | v = S_GET_VALUE (fixP->fx_addsy) - v; | |
23138 | ||
23139 | if (v & ~0x3fc) | |
23140 | { | |
23141 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23142 | _("symbol too far away")); | |
23143 | } | |
23144 | else | |
23145 | { | |
23146 | fixP->fx_done = 1; | |
23147 | value = v; | |
23148 | } | |
23149 | } | |
23150 | } | |
23151 | ||
c19d1205 ZW |
23152 | if (subtract || value & ~0x3fc) |
23153 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23154 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
5fc177c8 | 23155 | (unsigned long) (subtract ? - value : value)); |
c19d1205 ZW |
23156 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); |
23157 | newval |= rd << 8; | |
23158 | newval |= value >> 2; | |
23159 | } | |
23160 | else if (rs == rd) | |
23161 | { | |
23162 | if (value & ~0xff) | |
23163 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23164 | _("immediate value out of range")); | |
23165 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
23166 | newval |= (rd << 8) | value; | |
23167 | } | |
23168 | else | |
23169 | { | |
23170 | if (value & ~0x7) | |
23171 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23172 | _("immediate value out of range")); | |
23173 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
23174 | newval |= rd | (rs << 3) | (value << 6); | |
23175 | } | |
23176 | } | |
23177 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23178 | break; | |
a737bd4d | 23179 | |
c19d1205 ZW |
23180 | case BFD_RELOC_ARM_THUMB_IMM: |
23181 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
23182 | if (value < 0 || value > 255) | |
23183 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 23184 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
23185 | (long) value); |
23186 | newval |= value; | |
23187 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23188 | break; | |
a737bd4d | 23189 | |
c19d1205 ZW |
23190 | case BFD_RELOC_ARM_THUMB_SHIFT: |
23191 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
23192 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
23193 | temp = newval & 0xf800; | |
23194 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
23195 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23196 | _("invalid shift value: %ld"), (long) value); | |
23197 | /* Shifts of zero must be encoded as LSL. */ | |
23198 | if (value == 0) | |
23199 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
23200 | /* Shifts of 32 are encoded as zero. */ | |
23201 | else if (value == 32) | |
23202 | value = 0; | |
23203 | newval |= value << 6; | |
23204 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
23205 | break; | |
a737bd4d | 23206 | |
c19d1205 ZW |
23207 | case BFD_RELOC_VTABLE_INHERIT: |
23208 | case BFD_RELOC_VTABLE_ENTRY: | |
23209 | fixP->fx_done = 0; | |
23210 | return; | |
6c43fab6 | 23211 | |
b6895b4f PB |
23212 | case BFD_RELOC_ARM_MOVW: |
23213 | case BFD_RELOC_ARM_MOVT: | |
23214 | case BFD_RELOC_ARM_THUMB_MOVW: | |
23215 | case BFD_RELOC_ARM_THUMB_MOVT: | |
23216 | if (fixP->fx_done || !seg->use_rela_p) | |
23217 | { | |
23218 | /* REL format relocations are limited to a 16-bit addend. */ | |
23219 | if (!fixP->fx_done) | |
23220 | { | |
39623e12 | 23221 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 23222 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 23223 | _("offset out of range")); |
b6895b4f PB |
23224 | } |
23225 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
23226 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
23227 | { | |
23228 | value >>= 16; | |
23229 | } | |
23230 | ||
23231 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
23232 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
23233 | { | |
23234 | newval = get_thumb32_insn (buf); | |
23235 | newval &= 0xfbf08f00; | |
23236 | newval |= (value & 0xf000) << 4; | |
23237 | newval |= (value & 0x0800) << 15; | |
23238 | newval |= (value & 0x0700) << 4; | |
23239 | newval |= (value & 0x00ff); | |
23240 | put_thumb32_insn (buf, newval); | |
23241 | } | |
23242 | else | |
23243 | { | |
23244 | newval = md_chars_to_number (buf, 4); | |
23245 | newval &= 0xfff0f000; | |
23246 | newval |= value & 0x0fff; | |
23247 | newval |= (value & 0xf000) << 4; | |
23248 | md_number_to_chars (buf, newval, 4); | |
23249 | } | |
23250 | } | |
23251 | return; | |
23252 | ||
4962c51a MS |
23253 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
23254 | case BFD_RELOC_ARM_ALU_PC_G0: | |
23255 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
23256 | case BFD_RELOC_ARM_ALU_PC_G1: | |
23257 | case BFD_RELOC_ARM_ALU_PC_G2: | |
23258 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
23259 | case BFD_RELOC_ARM_ALU_SB_G0: | |
23260 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
23261 | case BFD_RELOC_ARM_ALU_SB_G1: | |
23262 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 23263 | gas_assert (!fixP->fx_done); |
4962c51a MS |
23264 | if (!seg->use_rela_p) |
23265 | { | |
477330fc RM |
23266 | bfd_vma insn; |
23267 | bfd_vma encoded_addend; | |
23268 | bfd_vma addend_abs = abs (value); | |
23269 | ||
23270 | /* Check that the absolute value of the addend can be | |
23271 | expressed as an 8-bit constant plus a rotation. */ | |
23272 | encoded_addend = encode_arm_immediate (addend_abs); | |
23273 | if (encoded_addend == (unsigned int) FAIL) | |
4962c51a | 23274 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23275 | _("the offset 0x%08lX is not representable"), |
23276 | (unsigned long) addend_abs); | |
23277 | ||
23278 | /* Extract the instruction. */ | |
23279 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23280 | ||
23281 | /* If the addend is positive, use an ADD instruction. | |
23282 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
23283 | insn &= 0xff1fffff; | |
23284 | if (value < 0) | |
23285 | insn |= 1 << 22; | |
23286 | else | |
23287 | insn |= 1 << 23; | |
23288 | ||
23289 | /* Place the encoded addend into the first 12 bits of the | |
23290 | instruction. */ | |
23291 | insn &= 0xfffff000; | |
23292 | insn |= encoded_addend; | |
23293 | ||
23294 | /* Update the instruction. */ | |
23295 | md_number_to_chars (buf, insn, INSN_SIZE); | |
4962c51a MS |
23296 | } |
23297 | break; | |
23298 | ||
23299 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23300 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23301 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23302 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23303 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23304 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 23305 | gas_assert (!fixP->fx_done); |
4962c51a | 23306 | if (!seg->use_rela_p) |
477330fc RM |
23307 | { |
23308 | bfd_vma insn; | |
23309 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23310 | |
477330fc RM |
23311 | /* Check that the absolute value of the addend can be |
23312 | encoded in 12 bits. */ | |
23313 | if (addend_abs >= 0x1000) | |
4962c51a | 23314 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23315 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), |
23316 | (unsigned long) addend_abs); | |
23317 | ||
23318 | /* Extract the instruction. */ | |
23319 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23320 | ||
23321 | /* If the addend is negative, clear bit 23 of the instruction. | |
23322 | Otherwise set it. */ | |
23323 | if (value < 0) | |
23324 | insn &= ~(1 << 23); | |
23325 | else | |
23326 | insn |= 1 << 23; | |
23327 | ||
23328 | /* Place the absolute value of the addend into the first 12 bits | |
23329 | of the instruction. */ | |
23330 | insn &= 0xfffff000; | |
23331 | insn |= addend_abs; | |
23332 | ||
23333 | /* Update the instruction. */ | |
23334 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23335 | } | |
4962c51a MS |
23336 | break; |
23337 | ||
23338 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23339 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23340 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23341 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23342 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23343 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 23344 | gas_assert (!fixP->fx_done); |
4962c51a | 23345 | if (!seg->use_rela_p) |
477330fc RM |
23346 | { |
23347 | bfd_vma insn; | |
23348 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23349 | |
477330fc RM |
23350 | /* Check that the absolute value of the addend can be |
23351 | encoded in 8 bits. */ | |
23352 | if (addend_abs >= 0x100) | |
4962c51a | 23353 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23354 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), |
23355 | (unsigned long) addend_abs); | |
23356 | ||
23357 | /* Extract the instruction. */ | |
23358 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23359 | ||
23360 | /* If the addend is negative, clear bit 23 of the instruction. | |
23361 | Otherwise set it. */ | |
23362 | if (value < 0) | |
23363 | insn &= ~(1 << 23); | |
23364 | else | |
23365 | insn |= 1 << 23; | |
23366 | ||
23367 | /* Place the first four bits of the absolute value of the addend | |
23368 | into the first 4 bits of the instruction, and the remaining | |
23369 | four into bits 8 .. 11. */ | |
23370 | insn &= 0xfffff0f0; | |
23371 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
23372 | ||
23373 | /* Update the instruction. */ | |
23374 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23375 | } | |
4962c51a MS |
23376 | break; |
23377 | ||
23378 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23379 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23380 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23381 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23382 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23383 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 23384 | gas_assert (!fixP->fx_done); |
4962c51a | 23385 | if (!seg->use_rela_p) |
477330fc RM |
23386 | { |
23387 | bfd_vma insn; | |
23388 | bfd_vma addend_abs = abs (value); | |
4962c51a | 23389 | |
477330fc RM |
23390 | /* Check that the absolute value of the addend is a multiple of |
23391 | four and, when divided by four, fits in 8 bits. */ | |
23392 | if (addend_abs & 0x3) | |
4962c51a | 23393 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23394 | _("bad offset 0x%08lX (must be word-aligned)"), |
23395 | (unsigned long) addend_abs); | |
4962c51a | 23396 | |
477330fc | 23397 | if ((addend_abs >> 2) > 0xff) |
4962c51a | 23398 | as_bad_where (fixP->fx_file, fixP->fx_line, |
477330fc RM |
23399 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), |
23400 | (unsigned long) addend_abs); | |
23401 | ||
23402 | /* Extract the instruction. */ | |
23403 | insn = md_chars_to_number (buf, INSN_SIZE); | |
23404 | ||
23405 | /* If the addend is negative, clear bit 23 of the instruction. | |
23406 | Otherwise set it. */ | |
23407 | if (value < 0) | |
23408 | insn &= ~(1 << 23); | |
23409 | else | |
23410 | insn |= 1 << 23; | |
23411 | ||
23412 | /* Place the addend (divided by four) into the first eight | |
23413 | bits of the instruction. */ | |
23414 | insn &= 0xfffffff0; | |
23415 | insn |= addend_abs >> 2; | |
23416 | ||
23417 | /* Update the instruction. */ | |
23418 | md_number_to_chars (buf, insn, INSN_SIZE); | |
23419 | } | |
4962c51a MS |
23420 | break; |
23421 | ||
845b51d6 PB |
23422 | case BFD_RELOC_ARM_V4BX: |
23423 | /* This will need to go in the object file. */ | |
23424 | fixP->fx_done = 0; | |
23425 | break; | |
23426 | ||
c19d1205 ZW |
23427 | case BFD_RELOC_UNUSED: |
23428 | default: | |
23429 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
23430 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
23431 | } | |
6c43fab6 RE |
23432 | } |
23433 | ||
c19d1205 ZW |
23434 | /* Translate internal representation of relocation info to BFD target |
23435 | format. */ | |
a737bd4d | 23436 | |
c19d1205 | 23437 | arelent * |
00a97672 | 23438 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 23439 | { |
c19d1205 ZW |
23440 | arelent * reloc; |
23441 | bfd_reloc_code_real_type code; | |
a737bd4d | 23442 | |
21d799b5 | 23443 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 23444 | |
21d799b5 | 23445 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
23446 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
23447 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 23448 | |
2fc8bdac | 23449 | if (fixp->fx_pcrel) |
00a97672 RS |
23450 | { |
23451 | if (section->use_rela_p) | |
23452 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
23453 | else | |
23454 | fixp->fx_offset = reloc->address; | |
23455 | } | |
c19d1205 | 23456 | reloc->addend = fixp->fx_offset; |
a737bd4d | 23457 | |
c19d1205 | 23458 | switch (fixp->fx_r_type) |
a737bd4d | 23459 | { |
c19d1205 ZW |
23460 | case BFD_RELOC_8: |
23461 | if (fixp->fx_pcrel) | |
23462 | { | |
23463 | code = BFD_RELOC_8_PCREL; | |
23464 | break; | |
23465 | } | |
a737bd4d | 23466 | |
c19d1205 ZW |
23467 | case BFD_RELOC_16: |
23468 | if (fixp->fx_pcrel) | |
23469 | { | |
23470 | code = BFD_RELOC_16_PCREL; | |
23471 | break; | |
23472 | } | |
6c43fab6 | 23473 | |
c19d1205 ZW |
23474 | case BFD_RELOC_32: |
23475 | if (fixp->fx_pcrel) | |
23476 | { | |
23477 | code = BFD_RELOC_32_PCREL; | |
23478 | break; | |
23479 | } | |
a737bd4d | 23480 | |
b6895b4f PB |
23481 | case BFD_RELOC_ARM_MOVW: |
23482 | if (fixp->fx_pcrel) | |
23483 | { | |
23484 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
23485 | break; | |
23486 | } | |
23487 | ||
23488 | case BFD_RELOC_ARM_MOVT: | |
23489 | if (fixp->fx_pcrel) | |
23490 | { | |
23491 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
23492 | break; | |
23493 | } | |
23494 | ||
23495 | case BFD_RELOC_ARM_THUMB_MOVW: | |
23496 | if (fixp->fx_pcrel) | |
23497 | { | |
23498 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
23499 | break; | |
23500 | } | |
23501 | ||
23502 | case BFD_RELOC_ARM_THUMB_MOVT: | |
23503 | if (fixp->fx_pcrel) | |
23504 | { | |
23505 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
23506 | break; | |
23507 | } | |
23508 | ||
c19d1205 ZW |
23509 | case BFD_RELOC_NONE: |
23510 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
23511 | case BFD_RELOC_ARM_PCREL_BLX: | |
23512 | case BFD_RELOC_RVA: | |
23513 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
23514 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
23515 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
23516 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23517 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23518 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
23519 | case BFD_RELOC_VTABLE_ENTRY: |
23520 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
23521 | #ifdef TE_PE |
23522 | case BFD_RELOC_32_SECREL: | |
23523 | #endif | |
c19d1205 ZW |
23524 | code = fixp->fx_r_type; |
23525 | break; | |
a737bd4d | 23526 | |
00adf2d4 JB |
23527 | case BFD_RELOC_THUMB_PCREL_BLX: |
23528 | #ifdef OBJ_ELF | |
23529 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
23530 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
23531 | else | |
23532 | #endif | |
23533 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
23534 | break; | |
23535 | ||
c19d1205 ZW |
23536 | case BFD_RELOC_ARM_LITERAL: |
23537 | case BFD_RELOC_ARM_HWLITERAL: | |
23538 | /* If this is called then the a literal has | |
23539 | been referenced across a section boundary. */ | |
23540 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23541 | _("literal referenced across section boundary")); | |
23542 | return NULL; | |
a737bd4d | 23543 | |
c19d1205 | 23544 | #ifdef OBJ_ELF |
0855e32b NS |
23545 | case BFD_RELOC_ARM_TLS_CALL: |
23546 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
23547 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
23548 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
23549 | case BFD_RELOC_ARM_GOT32: |
23550 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 23551 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
23552 | case BFD_RELOC_ARM_PLT32: |
23553 | case BFD_RELOC_ARM_TARGET1: | |
23554 | case BFD_RELOC_ARM_ROSEGREL32: | |
23555 | case BFD_RELOC_ARM_SBREL32: | |
23556 | case BFD_RELOC_ARM_PREL31: | |
23557 | case BFD_RELOC_ARM_TARGET2: | |
c19d1205 | 23558 | case BFD_RELOC_ARM_TLS_LDO32: |
39b41c9c PB |
23559 | case BFD_RELOC_ARM_PCREL_CALL: |
23560 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
23561 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
23562 | case BFD_RELOC_ARM_ALU_PC_G0: | |
23563 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
23564 | case BFD_RELOC_ARM_ALU_PC_G1: | |
23565 | case BFD_RELOC_ARM_ALU_PC_G2: | |
23566 | case BFD_RELOC_ARM_LDR_PC_G0: | |
23567 | case BFD_RELOC_ARM_LDR_PC_G1: | |
23568 | case BFD_RELOC_ARM_LDR_PC_G2: | |
23569 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
23570 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
23571 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
23572 | case BFD_RELOC_ARM_LDC_PC_G0: | |
23573 | case BFD_RELOC_ARM_LDC_PC_G1: | |
23574 | case BFD_RELOC_ARM_LDC_PC_G2: | |
23575 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
23576 | case BFD_RELOC_ARM_ALU_SB_G0: | |
23577 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
23578 | case BFD_RELOC_ARM_ALU_SB_G1: | |
23579 | case BFD_RELOC_ARM_ALU_SB_G2: | |
23580 | case BFD_RELOC_ARM_LDR_SB_G0: | |
23581 | case BFD_RELOC_ARM_LDR_SB_G1: | |
23582 | case BFD_RELOC_ARM_LDR_SB_G2: | |
23583 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
23584 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
23585 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
23586 | case BFD_RELOC_ARM_LDC_SB_G0: | |
23587 | case BFD_RELOC_ARM_LDC_SB_G1: | |
23588 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 23589 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
23590 | code = fixp->fx_r_type; |
23591 | break; | |
a737bd4d | 23592 | |
0855e32b | 23593 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 | 23594 | case BFD_RELOC_ARM_TLS_GD32: |
75c11999 | 23595 | case BFD_RELOC_ARM_TLS_LE32: |
c19d1205 ZW |
23596 | case BFD_RELOC_ARM_TLS_IE32: |
23597 | case BFD_RELOC_ARM_TLS_LDM32: | |
23598 | /* BFD will include the symbol's address in the addend. | |
23599 | But we don't want that, so subtract it out again here. */ | |
23600 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
23601 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
23602 | code = fixp->fx_r_type; | |
23603 | break; | |
23604 | #endif | |
a737bd4d | 23605 | |
c19d1205 ZW |
23606 | case BFD_RELOC_ARM_IMMEDIATE: |
23607 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23608 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
23609 | return NULL; | |
a737bd4d | 23610 | |
c19d1205 ZW |
23611 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
23612 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23613 | _("ADRL used for a symbol not defined in the same file")); | |
23614 | return NULL; | |
a737bd4d | 23615 | |
c19d1205 | 23616 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
23617 | if (section->use_rela_p) |
23618 | { | |
23619 | code = fixp->fx_r_type; | |
23620 | break; | |
23621 | } | |
23622 | ||
c19d1205 ZW |
23623 | if (fixp->fx_addsy != NULL |
23624 | && !S_IS_DEFINED (fixp->fx_addsy) | |
23625 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 23626 | { |
c19d1205 ZW |
23627 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23628 | _("undefined local label `%s'"), | |
23629 | S_GET_NAME (fixp->fx_addsy)); | |
23630 | return NULL; | |
a737bd4d NC |
23631 | } |
23632 | ||
c19d1205 ZW |
23633 | as_bad_where (fixp->fx_file, fixp->fx_line, |
23634 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
23635 | return NULL; | |
a737bd4d | 23636 | |
c19d1205 ZW |
23637 | default: |
23638 | { | |
23639 | char * type; | |
6c43fab6 | 23640 | |
c19d1205 ZW |
23641 | switch (fixp->fx_r_type) |
23642 | { | |
23643 | case BFD_RELOC_NONE: type = "NONE"; break; | |
23644 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
23645 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 23646 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
23647 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
23648 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
23649 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 23650 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 23651 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
23652 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
23653 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
23654 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
23655 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
23656 | default: type = _("<unknown>"); break; | |
23657 | } | |
23658 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23659 | _("cannot represent %s relocation in this object file format"), | |
23660 | type); | |
23661 | return NULL; | |
23662 | } | |
a737bd4d | 23663 | } |
6c43fab6 | 23664 | |
c19d1205 ZW |
23665 | #ifdef OBJ_ELF |
23666 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
23667 | && GOT_symbol | |
23668 | && fixp->fx_addsy == GOT_symbol) | |
23669 | { | |
23670 | code = BFD_RELOC_ARM_GOTPC; | |
23671 | reloc->addend = fixp->fx_offset = reloc->address; | |
23672 | } | |
23673 | #endif | |
6c43fab6 | 23674 | |
c19d1205 | 23675 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 23676 | |
c19d1205 ZW |
23677 | if (reloc->howto == NULL) |
23678 | { | |
23679 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
23680 | _("cannot represent %s relocation in this object file format"), | |
23681 | bfd_get_reloc_code_name (code)); | |
23682 | return NULL; | |
23683 | } | |
6c43fab6 | 23684 | |
c19d1205 ZW |
23685 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
23686 | vtable entry to be used in the relocation's section offset. */ | |
23687 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
23688 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 23689 | |
c19d1205 | 23690 | return reloc; |
6c43fab6 RE |
23691 | } |
23692 | ||
c19d1205 | 23693 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 23694 | |
c19d1205 ZW |
23695 | void |
23696 | cons_fix_new_arm (fragS * frag, | |
23697 | int where, | |
23698 | int size, | |
62ebcb5c AM |
23699 | expressionS * exp, |
23700 | bfd_reloc_code_real_type reloc) | |
6c43fab6 | 23701 | { |
c19d1205 | 23702 | int pcrel = 0; |
6c43fab6 | 23703 | |
c19d1205 ZW |
23704 | /* Pick a reloc. |
23705 | FIXME: @@ Should look at CPU word size. */ | |
23706 | switch (size) | |
23707 | { | |
23708 | case 1: | |
62ebcb5c | 23709 | reloc = BFD_RELOC_8; |
c19d1205 ZW |
23710 | break; |
23711 | case 2: | |
62ebcb5c | 23712 | reloc = BFD_RELOC_16; |
c19d1205 ZW |
23713 | break; |
23714 | case 4: | |
23715 | default: | |
62ebcb5c | 23716 | reloc = BFD_RELOC_32; |
c19d1205 ZW |
23717 | break; |
23718 | case 8: | |
62ebcb5c | 23719 | reloc = BFD_RELOC_64; |
c19d1205 ZW |
23720 | break; |
23721 | } | |
6c43fab6 | 23722 | |
f0927246 NC |
23723 | #ifdef TE_PE |
23724 | if (exp->X_op == O_secrel) | |
23725 | { | |
23726 | exp->X_op = O_symbol; | |
62ebcb5c | 23727 | reloc = BFD_RELOC_32_SECREL; |
f0927246 NC |
23728 | } |
23729 | #endif | |
23730 | ||
62ebcb5c | 23731 | fix_new_exp (frag, where, size, exp, pcrel, reloc); |
c19d1205 | 23732 | } |
6c43fab6 | 23733 | |
4343666d | 23734 | #if defined (OBJ_COFF) |
c19d1205 ZW |
23735 | void |
23736 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 23737 | { |
c19d1205 ZW |
23738 | /* If the destination of the branch is a defined symbol which does not have |
23739 | the THUMB_FUNC attribute, then we must be calling a function which has | |
23740 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
23741 | function and change the branch to refer to that function instead. */ | |
23742 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
23743 | && fixP->fx_addsy != NULL | |
23744 | && S_IS_DEFINED (fixP->fx_addsy) | |
23745 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 23746 | { |
c19d1205 | 23747 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 23748 | } |
c19d1205 ZW |
23749 | } |
23750 | #endif | |
6c43fab6 | 23751 | |
267bf995 | 23752 | |
c19d1205 ZW |
23753 | int |
23754 | arm_force_relocation (struct fix * fixp) | |
23755 | { | |
23756 | #if defined (OBJ_COFF) && defined (TE_PE) | |
23757 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
23758 | return 1; | |
23759 | #endif | |
6c43fab6 | 23760 | |
267bf995 RR |
23761 | /* In case we have a call or a branch to a function in ARM ISA mode from |
23762 | a thumb function or vice-versa force the relocation. These relocations | |
23763 | are cleared off for some cores that might have blx and simple transformations | |
23764 | are possible. */ | |
23765 | ||
23766 | #ifdef OBJ_ELF | |
23767 | switch (fixp->fx_r_type) | |
23768 | { | |
23769 | case BFD_RELOC_ARM_PCREL_JUMP: | |
23770 | case BFD_RELOC_ARM_PCREL_CALL: | |
23771 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23772 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
23773 | return 1; | |
23774 | break; | |
23775 | ||
23776 | case BFD_RELOC_ARM_PCREL_BLX: | |
23777 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
23778 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
23779 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23780 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
23781 | return 1; | |
23782 | break; | |
23783 | ||
23784 | default: | |
23785 | break; | |
23786 | } | |
23787 | #endif | |
23788 | ||
b5884301 PB |
23789 | /* Resolve these relocations even if the symbol is extern or weak. |
23790 | Technically this is probably wrong due to symbol preemption. | |
23791 | In practice these relocations do not have enough range to be useful | |
23792 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
23793 | expects these references to be resolved. */ | |
c19d1205 ZW |
23794 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
23795 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 23796 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 23797 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
23798 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
23799 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
23800 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 23801 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
23802 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
23803 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
23804 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
23805 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
23806 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
23807 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 23808 | return 0; |
a737bd4d | 23809 | |
4962c51a MS |
23810 | /* Always leave these relocations for the linker. */ |
23811 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23812 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23813 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
23814 | return 1; | |
23815 | ||
f0291e4c PB |
23816 | /* Always generate relocations against function symbols. */ |
23817 | if (fixp->fx_r_type == BFD_RELOC_32 | |
23818 | && fixp->fx_addsy | |
23819 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
23820 | return 1; | |
23821 | ||
c19d1205 | 23822 | return generic_force_reloc (fixp); |
404ff6b5 AH |
23823 | } |
23824 | ||
0ffdc86c | 23825 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
23826 | /* Relocations against function names must be left unadjusted, |
23827 | so that the linker can use this information to generate interworking | |
23828 | stubs. The MIPS version of this function | |
c19d1205 ZW |
23829 | also prevents relocations that are mips-16 specific, but I do not |
23830 | know why it does this. | |
404ff6b5 | 23831 | |
c19d1205 ZW |
23832 | FIXME: |
23833 | There is one other problem that ought to be addressed here, but | |
23834 | which currently is not: Taking the address of a label (rather | |
23835 | than a function) and then later jumping to that address. Such | |
23836 | addresses also ought to have their bottom bit set (assuming that | |
23837 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 23838 | |
c19d1205 ZW |
23839 | bfd_boolean |
23840 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 23841 | { |
c19d1205 ZW |
23842 | if (fixP->fx_addsy == NULL) |
23843 | return 1; | |
404ff6b5 | 23844 | |
e28387c3 PB |
23845 | /* Preserve relocations against symbols with function type. */ |
23846 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 23847 | return FALSE; |
e28387c3 | 23848 | |
c19d1205 ZW |
23849 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
23850 | && fixP->fx_subsy == NULL) | |
c921be7d | 23851 | return FALSE; |
a737bd4d | 23852 | |
c19d1205 ZW |
23853 | /* We need the symbol name for the VTABLE entries. */ |
23854 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
23855 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 23856 | return FALSE; |
404ff6b5 | 23857 | |
c19d1205 ZW |
23858 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
23859 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
23860 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
23861 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
23862 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
23863 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
23864 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
23865 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
23866 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
23867 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
23868 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
23869 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
23870 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
23871 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 23872 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 23873 | return FALSE; |
a737bd4d | 23874 | |
4962c51a MS |
23875 | /* Similarly for group relocations. */ |
23876 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
23877 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
23878 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 23879 | return FALSE; |
4962c51a | 23880 | |
79947c54 CD |
23881 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
23882 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
23883 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
23884 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
23885 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
23886 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
23887 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
23888 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
23889 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 23890 | return FALSE; |
79947c54 | 23891 | |
c921be7d | 23892 | return TRUE; |
a737bd4d | 23893 | } |
0ffdc86c NC |
23894 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
23895 | ||
23896 | #ifdef OBJ_ELF | |
404ff6b5 | 23897 | |
c19d1205 ZW |
23898 | const char * |
23899 | elf32_arm_target_format (void) | |
404ff6b5 | 23900 | { |
c19d1205 ZW |
23901 | #ifdef TE_SYMBIAN |
23902 | return (target_big_endian | |
23903 | ? "elf32-bigarm-symbian" | |
23904 | : "elf32-littlearm-symbian"); | |
23905 | #elif defined (TE_VXWORKS) | |
23906 | return (target_big_endian | |
23907 | ? "elf32-bigarm-vxworks" | |
23908 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
23909 | #elif defined (TE_NACL) |
23910 | return (target_big_endian | |
23911 | ? "elf32-bigarm-nacl" | |
23912 | : "elf32-littlearm-nacl"); | |
c19d1205 ZW |
23913 | #else |
23914 | if (target_big_endian) | |
23915 | return "elf32-bigarm"; | |
23916 | else | |
23917 | return "elf32-littlearm"; | |
23918 | #endif | |
404ff6b5 AH |
23919 | } |
23920 | ||
c19d1205 ZW |
23921 | void |
23922 | armelf_frob_symbol (symbolS * symp, | |
23923 | int * puntp) | |
404ff6b5 | 23924 | { |
c19d1205 ZW |
23925 | elf_frob_symbol (symp, puntp); |
23926 | } | |
23927 | #endif | |
404ff6b5 | 23928 | |
c19d1205 | 23929 | /* MD interface: Finalization. */ |
a737bd4d | 23930 | |
c19d1205 ZW |
23931 | void |
23932 | arm_cleanup (void) | |
23933 | { | |
23934 | literal_pool * pool; | |
a737bd4d | 23935 | |
e07e6e58 NC |
23936 | /* Ensure that all the IT blocks are properly closed. */ |
23937 | check_it_blocks_finished (); | |
23938 | ||
c19d1205 ZW |
23939 | for (pool = list_of_pools; pool; pool = pool->next) |
23940 | { | |
5f4273c7 | 23941 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
23942 | subseg_set (pool->section, pool->sub_section); |
23943 | #ifdef OBJ_ELF | |
23944 | arm_elf_change_section (); | |
23945 | #endif | |
23946 | s_ltorg (0); | |
23947 | } | |
404ff6b5 AH |
23948 | } |
23949 | ||
cd000bff DJ |
23950 | #ifdef OBJ_ELF |
23951 | /* Remove any excess mapping symbols generated for alignment frags in | |
23952 | SEC. We may have created a mapping symbol before a zero byte | |
23953 | alignment; remove it if there's a mapping symbol after the | |
23954 | alignment. */ | |
23955 | static void | |
23956 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
23957 | void *dummy ATTRIBUTE_UNUSED) | |
23958 | { | |
23959 | segment_info_type *seginfo = seg_info (sec); | |
23960 | fragS *fragp; | |
23961 | ||
23962 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
23963 | return; | |
23964 | ||
23965 | for (fragp = seginfo->frchainP->frch_root; | |
23966 | fragp != NULL; | |
23967 | fragp = fragp->fr_next) | |
23968 | { | |
23969 | symbolS *sym = fragp->tc_frag_data.last_map; | |
23970 | fragS *next = fragp->fr_next; | |
23971 | ||
23972 | /* Variable-sized frags have been converted to fixed size by | |
23973 | this point. But if this was variable-sized to start with, | |
23974 | there will be a fixed-size frag after it. So don't handle | |
23975 | next == NULL. */ | |
23976 | if (sym == NULL || next == NULL) | |
23977 | continue; | |
23978 | ||
23979 | if (S_GET_VALUE (sym) < next->fr_address) | |
23980 | /* Not at the end of this frag. */ | |
23981 | continue; | |
23982 | know (S_GET_VALUE (sym) == next->fr_address); | |
23983 | ||
23984 | do | |
23985 | { | |
23986 | if (next->tc_frag_data.first_map != NULL) | |
23987 | { | |
23988 | /* Next frag starts with a mapping symbol. Discard this | |
23989 | one. */ | |
23990 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
23991 | break; | |
23992 | } | |
23993 | ||
23994 | if (next->fr_next == NULL) | |
23995 | { | |
23996 | /* This mapping symbol is at the end of the section. Discard | |
23997 | it. */ | |
23998 | know (next->fr_fix == 0 && next->fr_var == 0); | |
23999 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
24000 | break; | |
24001 | } | |
24002 | ||
24003 | /* As long as we have empty frags without any mapping symbols, | |
24004 | keep looking. */ | |
24005 | /* If the next frag is non-empty and does not start with a | |
24006 | mapping symbol, then this mapping symbol is required. */ | |
24007 | if (next->fr_address != next->fr_next->fr_address) | |
24008 | break; | |
24009 | ||
24010 | next = next->fr_next; | |
24011 | } | |
24012 | while (next != NULL); | |
24013 | } | |
24014 | } | |
24015 | #endif | |
24016 | ||
c19d1205 ZW |
24017 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
24018 | ARM ones. */ | |
404ff6b5 | 24019 | |
c19d1205 ZW |
24020 | void |
24021 | arm_adjust_symtab (void) | |
404ff6b5 | 24022 | { |
c19d1205 ZW |
24023 | #ifdef OBJ_COFF |
24024 | symbolS * sym; | |
404ff6b5 | 24025 | |
c19d1205 ZW |
24026 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
24027 | { | |
24028 | if (ARM_IS_THUMB (sym)) | |
24029 | { | |
24030 | if (THUMB_IS_FUNC (sym)) | |
24031 | { | |
24032 | /* Mark the symbol as a Thumb function. */ | |
24033 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
24034 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
24035 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 24036 | |
c19d1205 ZW |
24037 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
24038 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
24039 | else | |
24040 | as_bad (_("%s: unexpected function type: %d"), | |
24041 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
24042 | } | |
24043 | else switch (S_GET_STORAGE_CLASS (sym)) | |
24044 | { | |
24045 | case C_EXT: | |
24046 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
24047 | break; | |
24048 | case C_STAT: | |
24049 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
24050 | break; | |
24051 | case C_LABEL: | |
24052 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
24053 | break; | |
24054 | default: | |
24055 | /* Do nothing. */ | |
24056 | break; | |
24057 | } | |
24058 | } | |
a737bd4d | 24059 | |
c19d1205 ZW |
24060 | if (ARM_IS_INTERWORK (sym)) |
24061 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 24062 | } |
c19d1205 ZW |
24063 | #endif |
24064 | #ifdef OBJ_ELF | |
24065 | symbolS * sym; | |
24066 | char bind; | |
404ff6b5 | 24067 | |
c19d1205 | 24068 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 24069 | { |
c19d1205 ZW |
24070 | if (ARM_IS_THUMB (sym)) |
24071 | { | |
24072 | elf_symbol_type * elf_sym; | |
404ff6b5 | 24073 | |
c19d1205 ZW |
24074 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
24075 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 24076 | |
b0796911 PB |
24077 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
24078 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
24079 | { |
24080 | /* If it's a .thumb_func, declare it as so, | |
24081 | otherwise tag label as .code 16. */ | |
24082 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
24083 | elf_sym->internal_elf_sym.st_target_internal |
24084 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 24085 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
24086 | elf_sym->internal_elf_sym.st_info = |
24087 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
24088 | } | |
24089 | } | |
24090 | } | |
cd000bff DJ |
24091 | |
24092 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
24093 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
24094 | /* Now do generic ELF adjustments. */ |
24095 | elf_adjust_symtab (); | |
c19d1205 | 24096 | #endif |
404ff6b5 AH |
24097 | } |
24098 | ||
c19d1205 | 24099 | /* MD interface: Initialization. */ |
404ff6b5 | 24100 | |
a737bd4d | 24101 | static void |
c19d1205 | 24102 | set_constant_flonums (void) |
a737bd4d | 24103 | { |
c19d1205 | 24104 | int i; |
404ff6b5 | 24105 | |
c19d1205 ZW |
24106 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
24107 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
24108 | abort (); | |
a737bd4d | 24109 | } |
404ff6b5 | 24110 | |
3e9e4fcf JB |
24111 | /* Auto-select Thumb mode if it's the only available instruction set for the |
24112 | given architecture. */ | |
24113 | ||
24114 | static void | |
24115 | autoselect_thumb_from_cpu_variant (void) | |
24116 | { | |
24117 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
24118 | opcode_select (16); | |
24119 | } | |
24120 | ||
c19d1205 ZW |
24121 | void |
24122 | md_begin (void) | |
a737bd4d | 24123 | { |
c19d1205 ZW |
24124 | unsigned mach; |
24125 | unsigned int i; | |
404ff6b5 | 24126 | |
c19d1205 ZW |
24127 | if ( (arm_ops_hsh = hash_new ()) == NULL |
24128 | || (arm_cond_hsh = hash_new ()) == NULL | |
24129 | || (arm_shift_hsh = hash_new ()) == NULL | |
24130 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 24131 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 24132 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
24133 | || (arm_reloc_hsh = hash_new ()) == NULL |
24134 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
24135 | as_fatal (_("virtual memory exhausted")); |
24136 | ||
24137 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 24138 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 24139 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 24140 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 24141 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 24142 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 24143 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 24144 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 24145 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 24146 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
477330fc | 24147 | (void *) (v7m_psrs + i)); |
c19d1205 | 24148 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 24149 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
24150 | for (i = 0; |
24151 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
24152 | i++) | |
d3ce72d0 | 24153 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 24154 | (void *) (barrier_opt_names + i)); |
c19d1205 | 24155 | #ifdef OBJ_ELF |
3da1d841 NC |
24156 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
24157 | { | |
24158 | struct reloc_entry * entry = reloc_names + i; | |
24159 | ||
24160 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
24161 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
24162 | entry->reloc = BFD_RELOC_UNUSED; | |
24163 | ||
24164 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
24165 | } | |
c19d1205 ZW |
24166 | #endif |
24167 | ||
24168 | set_constant_flonums (); | |
404ff6b5 | 24169 | |
c19d1205 ZW |
24170 | /* Set the cpu variant based on the command-line options. We prefer |
24171 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
24172 | -mfpu= over any other way of setting the floating point unit. | |
24173 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 24174 | if (legacy_cpu) |
404ff6b5 | 24175 | { |
e74cfd16 | 24176 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
24177 | as_bad (_("use of old and new-style options to set CPU type")); |
24178 | ||
24179 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 24180 | } |
e74cfd16 | 24181 | else if (!mcpu_cpu_opt) |
c19d1205 | 24182 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 24183 | |
e74cfd16 | 24184 | if (legacy_fpu) |
c19d1205 | 24185 | { |
e74cfd16 | 24186 | if (mfpu_opt) |
c19d1205 | 24187 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
24188 | |
24189 | mfpu_opt = legacy_fpu; | |
24190 | } | |
e74cfd16 | 24191 | else if (!mfpu_opt) |
03b1477f | 24192 | { |
45eb4c1b NS |
24193 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
24194 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
24195 | /* Some environments specify a default FPU. If they don't, infer it |
24196 | from the processor. */ | |
e74cfd16 | 24197 | if (mcpu_fpu_opt) |
03b1477f RE |
24198 | mfpu_opt = mcpu_fpu_opt; |
24199 | else | |
24200 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 24201 | #else |
e74cfd16 | 24202 | mfpu_opt = &fpu_default; |
39c2da32 | 24203 | #endif |
03b1477f RE |
24204 | } |
24205 | ||
e74cfd16 | 24206 | if (!mfpu_opt) |
03b1477f | 24207 | { |
493cb6ef | 24208 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 24209 | mfpu_opt = &fpu_default; |
493cb6ef | 24210 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 24211 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 24212 | else |
e74cfd16 | 24213 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
24214 | } |
24215 | ||
ee065d83 | 24216 | #ifdef CPU_DEFAULT |
e74cfd16 | 24217 | if (!mcpu_cpu_opt) |
ee065d83 | 24218 | { |
e74cfd16 PB |
24219 | mcpu_cpu_opt = &cpu_default; |
24220 | selected_cpu = cpu_default; | |
ee065d83 | 24221 | } |
73f43896 NC |
24222 | else if (no_cpu_selected ()) |
24223 | selected_cpu = cpu_default; | |
e74cfd16 PB |
24224 | #else |
24225 | if (mcpu_cpu_opt) | |
24226 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 24227 | else |
e74cfd16 | 24228 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 24229 | #endif |
03b1477f | 24230 | |
e74cfd16 | 24231 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 24232 | |
3e9e4fcf JB |
24233 | autoselect_thumb_from_cpu_variant (); |
24234 | ||
e74cfd16 | 24235 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 24236 | |
f17c130b | 24237 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 24238 | { |
7cc69913 NC |
24239 | unsigned int flags = 0; |
24240 | ||
24241 | #if defined OBJ_ELF | |
24242 | flags = meabi_flags; | |
d507cf36 PB |
24243 | |
24244 | switch (meabi_flags) | |
33a392fb | 24245 | { |
d507cf36 | 24246 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 24247 | #endif |
d507cf36 PB |
24248 | /* Set the flags in the private structure. */ |
24249 | if (uses_apcs_26) flags |= F_APCS26; | |
24250 | if (support_interwork) flags |= F_INTERWORK; | |
24251 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 24252 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 24253 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
24254 | flags |= F_SOFT_FLOAT; |
24255 | ||
d507cf36 PB |
24256 | switch (mfloat_abi_opt) |
24257 | { | |
24258 | case ARM_FLOAT_ABI_SOFT: | |
24259 | case ARM_FLOAT_ABI_SOFTFP: | |
24260 | flags |= F_SOFT_FLOAT; | |
24261 | break; | |
33a392fb | 24262 | |
d507cf36 PB |
24263 | case ARM_FLOAT_ABI_HARD: |
24264 | if (flags & F_SOFT_FLOAT) | |
24265 | as_bad (_("hard-float conflicts with specified fpu")); | |
24266 | break; | |
24267 | } | |
03b1477f | 24268 | |
e74cfd16 PB |
24269 | /* Using pure-endian doubles (even if soft-float). */ |
24270 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 24271 | flags |= F_VFP_FLOAT; |
f17c130b | 24272 | |
fde78edd | 24273 | #if defined OBJ_ELF |
e74cfd16 | 24274 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 24275 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
24276 | break; |
24277 | ||
8cb51566 | 24278 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 24279 | case EF_ARM_EABI_VER5: |
c19d1205 | 24280 | /* No additional flags to set. */ |
d507cf36 PB |
24281 | break; |
24282 | ||
24283 | default: | |
24284 | abort (); | |
24285 | } | |
7cc69913 | 24286 | #endif |
b99bd4ef NC |
24287 | bfd_set_private_flags (stdoutput, flags); |
24288 | ||
24289 | /* We have run out flags in the COFF header to encode the | |
24290 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 24291 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
24292 | if (atpcs) |
24293 | { | |
24294 | asection * sec; | |
24295 | ||
24296 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
24297 | ||
24298 | if (sec != NULL) | |
24299 | { | |
24300 | bfd_set_section_flags | |
24301 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
24302 | bfd_set_section_size (stdoutput, sec, 0); | |
24303 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
24304 | } | |
24305 | } | |
7cc69913 | 24306 | } |
f17c130b | 24307 | #endif |
b99bd4ef NC |
24308 | |
24309 | /* Record the CPU type as well. */ | |
2d447fca JM |
24310 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
24311 | mach = bfd_mach_arm_iWMMXt2; | |
24312 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 24313 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 24314 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 24315 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 24316 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 24317 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 24318 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 24319 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 24320 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 24321 | { |
e74cfd16 | 24322 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24323 | mach = bfd_mach_arm_5T; |
24324 | else | |
24325 | mach = bfd_mach_arm_5; | |
24326 | } | |
e74cfd16 | 24327 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 24328 | { |
e74cfd16 | 24329 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
24330 | mach = bfd_mach_arm_4T; |
24331 | else | |
24332 | mach = bfd_mach_arm_4; | |
24333 | } | |
e74cfd16 | 24334 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 24335 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
24336 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
24337 | mach = bfd_mach_arm_3; | |
24338 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
24339 | mach = bfd_mach_arm_2a; | |
24340 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
24341 | mach = bfd_mach_arm_2; | |
24342 | else | |
24343 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
24344 | |
24345 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
24346 | } | |
24347 | ||
c19d1205 | 24348 | /* Command line processing. */ |
b99bd4ef | 24349 | |
c19d1205 ZW |
24350 | /* md_parse_option |
24351 | Invocation line includes a switch not recognized by the base assembler. | |
24352 | See if it's a processor-specific option. | |
b99bd4ef | 24353 | |
c19d1205 ZW |
24354 | This routine is somewhat complicated by the need for backwards |
24355 | compatibility (since older releases of gcc can't be changed). | |
24356 | The new options try to make the interface as compatible as | |
24357 | possible with GCC. | |
b99bd4ef | 24358 | |
c19d1205 | 24359 | New options (supported) are: |
b99bd4ef | 24360 | |
c19d1205 ZW |
24361 | -mcpu=<cpu name> Assemble for selected processor |
24362 | -march=<architecture name> Assemble for selected architecture | |
24363 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
24364 | -EB/-mbig-endian Big-endian | |
24365 | -EL/-mlittle-endian Little-endian | |
24366 | -k Generate PIC code | |
24367 | -mthumb Start in Thumb mode | |
24368 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 24369 | |
278df34e | 24370 | -m[no-]warn-deprecated Warn about deprecated features |
8b2d793c | 24371 | -m[no-]warn-syms Warn when symbols match instructions |
267bf995 | 24372 | |
c19d1205 | 24373 | For now we will also provide support for: |
b99bd4ef | 24374 | |
c19d1205 ZW |
24375 | -mapcs-32 32-bit Program counter |
24376 | -mapcs-26 26-bit Program counter | |
24377 | -macps-float Floats passed in FP registers | |
24378 | -mapcs-reentrant Reentrant code | |
24379 | -matpcs | |
24380 | (sometime these will probably be replaced with -mapcs=<list of options> | |
24381 | and -matpcs=<list of options>) | |
b99bd4ef | 24382 | |
c19d1205 ZW |
24383 | The remaining options are only supported for back-wards compatibility. |
24384 | Cpu variants, the arm part is optional: | |
24385 | -m[arm]1 Currently not supported. | |
24386 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
24387 | -m[arm]3 Arm 3 processor | |
24388 | -m[arm]6[xx], Arm 6 processors | |
24389 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
24390 | -m[arm]8[10] Arm 8 processors | |
24391 | -m[arm]9[20][tdmi] Arm 9 processors | |
24392 | -mstrongarm[110[0]] StrongARM processors | |
24393 | -mxscale XScale processors | |
24394 | -m[arm]v[2345[t[e]]] Arm architectures | |
24395 | -mall All (except the ARM1) | |
24396 | FP variants: | |
24397 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
24398 | -mfpe-old (No float load/store multiples) | |
24399 | -mvfpxd VFP Single precision | |
24400 | -mvfp All VFP | |
24401 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 24402 | |
c19d1205 ZW |
24403 | The following CPU names are recognized: |
24404 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
24405 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
24406 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
24407 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
24408 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
24409 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
24410 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 24411 | |
c19d1205 | 24412 | */ |
b99bd4ef | 24413 | |
c19d1205 | 24414 | const char * md_shortopts = "m:k"; |
b99bd4ef | 24415 | |
c19d1205 ZW |
24416 | #ifdef ARM_BI_ENDIAN |
24417 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
24418 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 24419 | #else |
c19d1205 ZW |
24420 | #if TARGET_BYTES_BIG_ENDIAN |
24421 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 24422 | #else |
c19d1205 ZW |
24423 | #define OPTION_EL (OPTION_MD_BASE + 1) |
24424 | #endif | |
b99bd4ef | 24425 | #endif |
845b51d6 | 24426 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 24427 | |
c19d1205 | 24428 | struct option md_longopts[] = |
b99bd4ef | 24429 | { |
c19d1205 ZW |
24430 | #ifdef OPTION_EB |
24431 | {"EB", no_argument, NULL, OPTION_EB}, | |
24432 | #endif | |
24433 | #ifdef OPTION_EL | |
24434 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 24435 | #endif |
845b51d6 | 24436 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
24437 | {NULL, no_argument, NULL, 0} |
24438 | }; | |
b99bd4ef | 24439 | |
8b2d793c | 24440 | |
c19d1205 | 24441 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 24442 | |
c19d1205 | 24443 | struct arm_option_table |
b99bd4ef | 24444 | { |
c19d1205 ZW |
24445 | char *option; /* Option name to match. */ |
24446 | char *help; /* Help information. */ | |
24447 | int *var; /* Variable to change. */ | |
24448 | int value; /* What to change it to. */ | |
24449 | char *deprecated; /* If non-null, print this message. */ | |
24450 | }; | |
b99bd4ef | 24451 | |
c19d1205 ZW |
24452 | struct arm_option_table arm_opts[] = |
24453 | { | |
24454 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
24455 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
24456 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
24457 | &support_interwork, 1, NULL}, | |
24458 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
24459 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
24460 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
24461 | 1, NULL}, | |
24462 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
24463 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
24464 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
24465 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
24466 | NULL}, | |
b99bd4ef | 24467 | |
c19d1205 ZW |
24468 | /* These are recognized by the assembler, but have no affect on code. */ |
24469 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
24470 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
24471 | |
24472 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
24473 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
24474 | &warn_on_deprecated, 0, NULL}, | |
8b2d793c NC |
24475 | {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL}, |
24476 | {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL}, | |
e74cfd16 PB |
24477 | {NULL, NULL, NULL, 0, NULL} |
24478 | }; | |
24479 | ||
24480 | struct arm_legacy_option_table | |
24481 | { | |
24482 | char *option; /* Option name to match. */ | |
24483 | const arm_feature_set **var; /* Variable to change. */ | |
24484 | const arm_feature_set value; /* What to change it to. */ | |
24485 | char *deprecated; /* If non-null, print this message. */ | |
24486 | }; | |
b99bd4ef | 24487 | |
e74cfd16 PB |
24488 | const struct arm_legacy_option_table arm_legacy_opts[] = |
24489 | { | |
c19d1205 ZW |
24490 | /* DON'T add any new processors to this list -- we want the whole list |
24491 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
24492 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
24493 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
24494 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24495 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
24496 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24497 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
24498 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24499 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
24500 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24501 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
24502 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24503 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
24504 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24505 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
24506 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24507 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
24508 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24509 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
24510 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24511 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
24512 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24513 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
24514 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24515 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
24516 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24517 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
24518 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24519 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
24520 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24521 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
24522 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24523 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
24524 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24525 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
24526 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24527 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
24528 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24529 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
24530 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24531 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
24532 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24533 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
24534 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24535 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
24536 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24537 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
24538 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24539 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24540 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24541 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
24542 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24543 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
24544 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24545 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
24546 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24547 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
24548 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24549 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
24550 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24551 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
24552 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24553 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
24554 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24555 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
24556 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24557 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
24558 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24559 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
24560 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
24561 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 24562 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 24563 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24564 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 24565 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 24566 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
24567 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
24568 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
24569 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 24570 | |
c19d1205 | 24571 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24572 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
24573 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
24574 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24575 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
24576 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24577 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
24578 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24579 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
24580 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24581 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
24582 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24583 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
24584 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24585 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
24586 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24587 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
24588 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
24589 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 24590 | |
c19d1205 | 24591 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
24592 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
24593 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
24594 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
24595 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 24596 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 24597 | |
e74cfd16 | 24598 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 24599 | }; |
7ed4c4c5 | 24600 | |
c19d1205 | 24601 | struct arm_cpu_option_table |
7ed4c4c5 | 24602 | { |
c19d1205 | 24603 | char *name; |
f3bad469 | 24604 | size_t name_len; |
e74cfd16 | 24605 | const arm_feature_set value; |
c19d1205 ZW |
24606 | /* For some CPUs we assume an FPU unless the user explicitly sets |
24607 | -mfpu=... */ | |
e74cfd16 | 24608 | const arm_feature_set default_fpu; |
ee065d83 PB |
24609 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
24610 | case. */ | |
24611 | const char *canonical_name; | |
c19d1205 | 24612 | }; |
7ed4c4c5 | 24613 | |
c19d1205 ZW |
24614 | /* This list should, at a minimum, contain all the cpu names |
24615 | recognized by GCC. */ | |
f3bad469 | 24616 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 24617 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 24618 | { |
f3bad469 MGD |
24619 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
24620 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
24621 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
24622 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24623 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
24624 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24625 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24626 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24627 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24628 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24629 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24630 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24631 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24632 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24633 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24634 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
24635 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24636 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24637 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24638 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24639 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24640 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24641 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24642 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24643 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24644 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24645 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24646 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
24647 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24648 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24649 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24650 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24651 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24652 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24653 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24654 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24655 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24656 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24657 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24658 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
24659 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24660 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24661 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24662 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
24663 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
24664 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
24665 | /* For V5 or later processors we default to using VFP; but the user |
24666 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
24667 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
24668 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24669 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24670 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
24671 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24672 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24673 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
24674 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24675 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
24676 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
24677 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24678 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24679 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24680 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24681 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24682 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
24683 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
24684 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24685 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24686 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
24687 | "ARM1026EJ-S"), | |
24688 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
24689 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24690 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24691 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24692 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24693 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
24694 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
24695 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
24696 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
24697 | "ARM1136JF-S"), | |
24698 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
24699 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
24700 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
24701 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
24702 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
f33026a9 MW |
24703 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ, FPU_NONE, NULL), |
24704 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ, FPU_ARCH_VFP_V2, NULL), | |
f3bad469 MGD |
24705 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, |
24706 | FPU_NONE, "Cortex-A5"), | |
c9fb6e58 | 24707 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 MGD |
24708 | "Cortex-A7"), |
24709 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
823d2571 | 24710 | ARM_FEATURE_COPROC (FPU_VFP_V3 |
477330fc | 24711 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
24712 | "Cortex-A8"), |
24713 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
823d2571 | 24714 | ARM_FEATURE_COPROC (FPU_VFP_V3 |
477330fc | 24715 | | FPU_NEON_EXT_V1), |
f3bad469 | 24716 | "Cortex-A9"), |
c9fb6e58 | 24717 | ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
63a4bc21 | 24718 | "Cortex-A12"), |
c9fb6e58 | 24719 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
f3bad469 | 24720 | "Cortex-A15"), |
d7adf960 KT |
24721 | ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, |
24722 | "Cortex-A17"), | |
92eb40d9 | 24723 | ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24724 | "Cortex-A53"), |
92eb40d9 | 24725 | ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
477330fc | 24726 | "Cortex-A57"), |
b19f47ad JW |
24727 | ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
24728 | "Cortex-A72"), | |
f3bad469 MGD |
24729 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), |
24730 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
24731 | "Cortex-R4F"), | |
24732 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
24733 | FPU_NONE, "Cortex-R5"), | |
70a8bc5b | 24734 | ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV, |
24735 | FPU_ARCH_VFP_V3D16, | |
24736 | "Cortex-R7"), | |
a715796b | 24737 | ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"), |
f3bad469 MGD |
24738 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), |
24739 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
24740 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
24741 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
ce32bd10 | 24742 | ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), |
246496bb EM |
24743 | ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
24744 | "Samsung " \ | |
24745 | "Exynos M1"), | |
c19d1205 | 24746 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 24747 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 24748 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
24749 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
24750 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
24751 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 24752 | /* Maverick */ |
823d2571 | 24753 | ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
da4339ed NC |
24754 | FPU_ARCH_MAVERICK, "ARM920T"), |
24755 | /* Marvell processors. */ | |
823d2571 TG |
24756 | ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP |
24757 | | ARM_EXT_SEC), | |
477330fc | 24758 | FPU_ARCH_VFP_V3D16, NULL), |
823d2571 TG |
24759 | ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP |
24760 | | ARM_EXT_SEC), | |
4347085a | 24761 | FPU_ARCH_NEON_VFP_V4, NULL), |
ea0d6bb9 PT |
24762 | /* APM X-Gene family. */ |
24763 | ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
24764 | "APM X-Gene 1"), | |
24765 | ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, | |
24766 | "APM X-Gene 2"), | |
da4339ed | 24767 | |
f3bad469 | 24768 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } |
c19d1205 | 24769 | }; |
f3bad469 | 24770 | #undef ARM_CPU_OPT |
7ed4c4c5 | 24771 | |
c19d1205 | 24772 | struct arm_arch_option_table |
7ed4c4c5 | 24773 | { |
c19d1205 | 24774 | char *name; |
f3bad469 | 24775 | size_t name_len; |
e74cfd16 PB |
24776 | const arm_feature_set value; |
24777 | const arm_feature_set default_fpu; | |
c19d1205 | 24778 | }; |
7ed4c4c5 | 24779 | |
c19d1205 ZW |
24780 | /* This list should, at a minimum, contain all the architecture names |
24781 | recognized by GCC. */ | |
f3bad469 | 24782 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 24783 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 24784 | { |
f3bad469 MGD |
24785 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
24786 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
24787 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
24788 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24789 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
24790 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
24791 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
24792 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
24793 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
24794 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
24795 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
24796 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
24797 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
24798 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
24799 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
24800 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
24801 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
24802 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24803 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
24804 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
24805 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
f33026a9 MW |
24806 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is |
24807 | kept to preserve existing behaviour. */ | |
24808 | ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP), | |
24809 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP), | |
f3bad469 MGD |
24810 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), |
24811 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
24812 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
f33026a9 MW |
24813 | /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is |
24814 | kept to preserve existing behaviour. */ | |
24815 | ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP), | |
24816 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP), | |
f3bad469 MGD |
24817 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), |
24818 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
24819 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
24820 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
24821 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 | 24822 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
c9fb6e58 | 24823 | ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP), |
f3bad469 MGD |
24824 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), |
24825 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24826 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
24827 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
24828 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
24829 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
bca38921 | 24830 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), |
a5932920 | 24831 | ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP), |
f3bad469 MGD |
24832 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
24833 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
24834 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
24835 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 24836 | }; |
f3bad469 | 24837 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 24838 | |
69133863 MGD |
24839 | /* ISA extensions in the co-processor and main instruction set space. */ |
24840 | struct arm_option_extension_value_table | |
c19d1205 ZW |
24841 | { |
24842 | char *name; | |
f3bad469 | 24843 | size_t name_len; |
5a70a223 JB |
24844 | const arm_feature_set merge_value; |
24845 | const arm_feature_set clear_value; | |
69133863 | 24846 | const arm_feature_set allowed_archs; |
c19d1205 | 24847 | }; |
7ed4c4c5 | 24848 | |
69133863 MGD |
24849 | /* The following table must be in alphabetical order with a NULL last entry. |
24850 | */ | |
5a70a223 | 24851 | #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA } |
69133863 | 24852 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 24853 | { |
823d2571 TG |
24854 | ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8), |
24855 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
bca38921 | 24856 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
823d2571 TG |
24857 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8), |
24858 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
24859 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8), | |
24860 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
24861 | ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), | |
24862 | ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV), | |
24863 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)), | |
24864 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), | |
24865 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ANY), | |
24866 | ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), | |
24867 | ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ANY), | |
24868 | ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), | |
24869 | ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ANY), | |
24870 | ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
24871 | ARM_FEATURE_CORE_LOW (ARM_EXT_MP), | |
24872 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)), | |
bca38921 | 24873 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
823d2571 TG |
24874 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8), |
24875 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
24876 | ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
24877 | ARM_FEATURE_CORE_LOW (ARM_EXT_OS), | |
24878 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)), | |
ddfded2f MW |
24879 | ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), |
24880 | ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), | |
24881 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
24882 | ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), |
24883 | ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), | |
24884 | ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V7A)), | |
24885 | ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV | |
24886 | | ARM_EXT_DIV), | |
24887 | ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), | |
24888 | ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)), | |
d6b4b13e MW |
24889 | ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8, |
24890 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), | |
24891 | ARM_FEATURE_CORE_LOW (ARM_EXT_V8)), | |
823d2571 TG |
24892 | ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
24893 | ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY), | |
5a70a223 | 24894 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE } |
69133863 | 24895 | }; |
f3bad469 | 24896 | #undef ARM_EXT_OPT |
69133863 MGD |
24897 | |
24898 | /* ISA floating-point and Advanced SIMD extensions. */ | |
24899 | struct arm_option_fpu_value_table | |
24900 | { | |
24901 | char *name; | |
24902 | const arm_feature_set value; | |
c19d1205 | 24903 | }; |
7ed4c4c5 | 24904 | |
c19d1205 ZW |
24905 | /* This list should, at a minimum, contain all the fpu names |
24906 | recognized by GCC. */ | |
69133863 | 24907 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
24908 | { |
24909 | {"softfpa", FPU_NONE}, | |
24910 | {"fpe", FPU_ARCH_FPE}, | |
24911 | {"fpe2", FPU_ARCH_FPE}, | |
24912 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
24913 | {"fpa", FPU_ARCH_FPA}, | |
24914 | {"fpa10", FPU_ARCH_FPA}, | |
24915 | {"fpa11", FPU_ARCH_FPA}, | |
24916 | {"arm7500fe", FPU_ARCH_FPA}, | |
24917 | {"softvfp", FPU_ARCH_VFP}, | |
24918 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
24919 | {"vfp", FPU_ARCH_VFP_V2}, | |
24920 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 24921 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
24922 | {"vfp10", FPU_ARCH_VFP_V2}, |
24923 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
24924 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
24925 | {"vfpv2", FPU_ARCH_VFP_V2}, |
24926 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 24927 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 24928 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
24929 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
24930 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
24931 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
24932 | {"arm1020t", FPU_ARCH_VFP_V1}, |
24933 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
24934 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
24935 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
24936 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 24937 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 24938 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
24939 | {"vfpv4", FPU_ARCH_VFP_V4}, |
24940 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 24941 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
a715796b TG |
24942 | {"fpv5-d16", FPU_ARCH_VFP_V5D16}, |
24943 | {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16}, | |
62f3b8c8 | 24944 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
24945 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
24946 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
24947 | {"crypto-neon-fp-armv8", | |
24948 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
d6b4b13e | 24949 | {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1}, |
081e4c7d MW |
24950 | {"crypto-neon-fp-armv8.1", |
24951 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1}, | |
e74cfd16 PB |
24952 | {NULL, ARM_ARCH_NONE} |
24953 | }; | |
24954 | ||
24955 | struct arm_option_value_table | |
24956 | { | |
24957 | char *name; | |
24958 | long value; | |
c19d1205 | 24959 | }; |
7ed4c4c5 | 24960 | |
e74cfd16 | 24961 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
24962 | { |
24963 | {"hard", ARM_FLOAT_ABI_HARD}, | |
24964 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
24965 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 24966 | {NULL, 0} |
c19d1205 | 24967 | }; |
7ed4c4c5 | 24968 | |
c19d1205 | 24969 | #ifdef OBJ_ELF |
3a4a14e9 | 24970 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 24971 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
24972 | { |
24973 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
24974 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 24975 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 24976 | {NULL, 0} |
c19d1205 ZW |
24977 | }; |
24978 | #endif | |
7ed4c4c5 | 24979 | |
c19d1205 ZW |
24980 | struct arm_long_option_table |
24981 | { | |
24982 | char * option; /* Substring to match. */ | |
24983 | char * help; /* Help information. */ | |
24984 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
24985 | char * deprecated; /* If non-null, print this message. */ | |
24986 | }; | |
7ed4c4c5 | 24987 | |
c921be7d | 24988 | static bfd_boolean |
f3bad469 | 24989 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 24990 | { |
21d799b5 NC |
24991 | arm_feature_set *ext_set = (arm_feature_set *) |
24992 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 24993 | |
69133863 | 24994 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
24995 | extensions being added before being removed. We achieve this by having |
24996 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 24997 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 24998 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
24999 | -1 -> 1 -> 0. */ |
25000 | const struct arm_option_extension_value_table * opt = NULL; | |
25001 | int adding_value = -1; | |
25002 | ||
e74cfd16 PB |
25003 | /* Copy the feature set, so that we can modify it. */ |
25004 | *ext_set = **opt_p; | |
25005 | *opt_p = ext_set; | |
25006 | ||
c19d1205 | 25007 | while (str != NULL && *str != 0) |
7ed4c4c5 | 25008 | { |
f3bad469 MGD |
25009 | char *ext; |
25010 | size_t len; | |
7ed4c4c5 | 25011 | |
c19d1205 ZW |
25012 | if (*str != '+') |
25013 | { | |
25014 | as_bad (_("invalid architectural extension")); | |
c921be7d | 25015 | return FALSE; |
c19d1205 | 25016 | } |
7ed4c4c5 | 25017 | |
c19d1205 ZW |
25018 | str++; |
25019 | ext = strchr (str, '+'); | |
7ed4c4c5 | 25020 | |
c19d1205 | 25021 | if (ext != NULL) |
f3bad469 | 25022 | len = ext - str; |
c19d1205 | 25023 | else |
f3bad469 | 25024 | len = strlen (str); |
7ed4c4c5 | 25025 | |
f3bad469 | 25026 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
25027 | { |
25028 | if (adding_value != 0) | |
25029 | { | |
25030 | adding_value = 0; | |
25031 | opt = arm_extensions; | |
25032 | } | |
25033 | ||
f3bad469 | 25034 | len -= 2; |
69133863 MGD |
25035 | str += 2; |
25036 | } | |
f3bad469 | 25037 | else if (len > 0) |
69133863 MGD |
25038 | { |
25039 | if (adding_value == -1) | |
25040 | { | |
25041 | adding_value = 1; | |
25042 | opt = arm_extensions; | |
25043 | } | |
25044 | else if (adding_value != 1) | |
25045 | { | |
25046 | as_bad (_("must specify extensions to add before specifying " | |
25047 | "those to remove")); | |
25048 | return FALSE; | |
25049 | } | |
25050 | } | |
25051 | ||
f3bad469 | 25052 | if (len == 0) |
c19d1205 ZW |
25053 | { |
25054 | as_bad (_("missing architectural extension")); | |
c921be7d | 25055 | return FALSE; |
c19d1205 | 25056 | } |
7ed4c4c5 | 25057 | |
69133863 MGD |
25058 | gas_assert (adding_value != -1); |
25059 | gas_assert (opt != NULL); | |
25060 | ||
25061 | /* Scan over the options table trying to find an exact match. */ | |
25062 | for (; opt->name != NULL; opt++) | |
f3bad469 | 25063 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 25064 | { |
69133863 MGD |
25065 | /* Check we can apply the extension to this architecture. */ |
25066 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
25067 | { | |
25068 | as_bad (_("extension does not apply to the base architecture")); | |
25069 | return FALSE; | |
25070 | } | |
25071 | ||
25072 | /* Add or remove the extension. */ | |
25073 | if (adding_value) | |
5a70a223 | 25074 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value); |
69133863 | 25075 | else |
5a70a223 | 25076 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value); |
69133863 | 25077 | |
c19d1205 ZW |
25078 | break; |
25079 | } | |
7ed4c4c5 | 25080 | |
c19d1205 ZW |
25081 | if (opt->name == NULL) |
25082 | { | |
69133863 MGD |
25083 | /* Did we fail to find an extension because it wasn't specified in |
25084 | alphabetical order, or because it does not exist? */ | |
25085 | ||
25086 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 25087 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
25088 | break; |
25089 | ||
25090 | if (opt->name == NULL) | |
25091 | as_bad (_("unknown architectural extension `%s'"), str); | |
25092 | else | |
25093 | as_bad (_("architectural extensions must be specified in " | |
25094 | "alphabetical order")); | |
25095 | ||
c921be7d | 25096 | return FALSE; |
c19d1205 | 25097 | } |
69133863 MGD |
25098 | else |
25099 | { | |
25100 | /* We should skip the extension we've just matched the next time | |
25101 | round. */ | |
25102 | opt++; | |
25103 | } | |
7ed4c4c5 | 25104 | |
c19d1205 ZW |
25105 | str = ext; |
25106 | }; | |
7ed4c4c5 | 25107 | |
c921be7d | 25108 | return TRUE; |
c19d1205 | 25109 | } |
7ed4c4c5 | 25110 | |
c921be7d | 25111 | static bfd_boolean |
f3bad469 | 25112 | arm_parse_cpu (char *str) |
7ed4c4c5 | 25113 | { |
f3bad469 MGD |
25114 | const struct arm_cpu_option_table *opt; |
25115 | char *ext = strchr (str, '+'); | |
25116 | size_t len; | |
7ed4c4c5 | 25117 | |
c19d1205 | 25118 | if (ext != NULL) |
f3bad469 | 25119 | len = ext - str; |
7ed4c4c5 | 25120 | else |
f3bad469 | 25121 | len = strlen (str); |
7ed4c4c5 | 25122 | |
f3bad469 | 25123 | if (len == 0) |
7ed4c4c5 | 25124 | { |
c19d1205 | 25125 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 25126 | return FALSE; |
7ed4c4c5 NC |
25127 | } |
25128 | ||
c19d1205 | 25129 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 25130 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 25131 | { |
e74cfd16 PB |
25132 | mcpu_cpu_opt = &opt->value; |
25133 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 25134 | if (opt->canonical_name) |
5f4273c7 | 25135 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
25136 | else |
25137 | { | |
f3bad469 | 25138 | size_t i; |
c921be7d | 25139 | |
f3bad469 | 25140 | for (i = 0; i < len; i++) |
ee065d83 PB |
25141 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
25142 | selected_cpu_name[i] = 0; | |
25143 | } | |
7ed4c4c5 | 25144 | |
c19d1205 ZW |
25145 | if (ext != NULL) |
25146 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 25147 | |
c921be7d | 25148 | return TRUE; |
c19d1205 | 25149 | } |
7ed4c4c5 | 25150 | |
c19d1205 | 25151 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 25152 | return FALSE; |
7ed4c4c5 NC |
25153 | } |
25154 | ||
c921be7d | 25155 | static bfd_boolean |
f3bad469 | 25156 | arm_parse_arch (char *str) |
7ed4c4c5 | 25157 | { |
e74cfd16 | 25158 | const struct arm_arch_option_table *opt; |
c19d1205 | 25159 | char *ext = strchr (str, '+'); |
f3bad469 | 25160 | size_t len; |
7ed4c4c5 | 25161 | |
c19d1205 | 25162 | if (ext != NULL) |
f3bad469 | 25163 | len = ext - str; |
7ed4c4c5 | 25164 | else |
f3bad469 | 25165 | len = strlen (str); |
7ed4c4c5 | 25166 | |
f3bad469 | 25167 | if (len == 0) |
7ed4c4c5 | 25168 | { |
c19d1205 | 25169 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 25170 | return FALSE; |
7ed4c4c5 NC |
25171 | } |
25172 | ||
c19d1205 | 25173 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 25174 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 25175 | { |
e74cfd16 PB |
25176 | march_cpu_opt = &opt->value; |
25177 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 25178 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 25179 | |
c19d1205 ZW |
25180 | if (ext != NULL) |
25181 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 25182 | |
c921be7d | 25183 | return TRUE; |
c19d1205 ZW |
25184 | } |
25185 | ||
25186 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 25187 | return FALSE; |
7ed4c4c5 | 25188 | } |
eb043451 | 25189 | |
c921be7d | 25190 | static bfd_boolean |
c19d1205 ZW |
25191 | arm_parse_fpu (char * str) |
25192 | { | |
69133863 | 25193 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 25194 | |
c19d1205 ZW |
25195 | for (opt = arm_fpus; opt->name != NULL; opt++) |
25196 | if (streq (opt->name, str)) | |
25197 | { | |
e74cfd16 | 25198 | mfpu_opt = &opt->value; |
c921be7d | 25199 | return TRUE; |
c19d1205 | 25200 | } |
b99bd4ef | 25201 | |
c19d1205 | 25202 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 25203 | return FALSE; |
c19d1205 ZW |
25204 | } |
25205 | ||
c921be7d | 25206 | static bfd_boolean |
c19d1205 | 25207 | arm_parse_float_abi (char * str) |
b99bd4ef | 25208 | { |
e74cfd16 | 25209 | const struct arm_option_value_table * opt; |
b99bd4ef | 25210 | |
c19d1205 ZW |
25211 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
25212 | if (streq (opt->name, str)) | |
25213 | { | |
25214 | mfloat_abi_opt = opt->value; | |
c921be7d | 25215 | return TRUE; |
c19d1205 | 25216 | } |
cc8a6dd0 | 25217 | |
c19d1205 | 25218 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 25219 | return FALSE; |
c19d1205 | 25220 | } |
b99bd4ef | 25221 | |
c19d1205 | 25222 | #ifdef OBJ_ELF |
c921be7d | 25223 | static bfd_boolean |
c19d1205 ZW |
25224 | arm_parse_eabi (char * str) |
25225 | { | |
e74cfd16 | 25226 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 25227 | |
c19d1205 ZW |
25228 | for (opt = arm_eabis; opt->name != NULL; opt++) |
25229 | if (streq (opt->name, str)) | |
25230 | { | |
25231 | meabi_flags = opt->value; | |
c921be7d | 25232 | return TRUE; |
c19d1205 ZW |
25233 | } |
25234 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 25235 | return FALSE; |
c19d1205 ZW |
25236 | } |
25237 | #endif | |
cc8a6dd0 | 25238 | |
c921be7d | 25239 | static bfd_boolean |
e07e6e58 NC |
25240 | arm_parse_it_mode (char * str) |
25241 | { | |
c921be7d | 25242 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
25243 | |
25244 | if (streq ("arm", str)) | |
25245 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
25246 | else if (streq ("thumb", str)) | |
25247 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
25248 | else if (streq ("always", str)) | |
25249 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
25250 | else if (streq ("never", str)) | |
25251 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
25252 | else | |
25253 | { | |
25254 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
477330fc | 25255 | "arm, thumb, always, or never."), str); |
c921be7d | 25256 | ret = FALSE; |
e07e6e58 NC |
25257 | } |
25258 | ||
25259 | return ret; | |
25260 | } | |
25261 | ||
2e6976a8 DG |
25262 | static bfd_boolean |
25263 | arm_ccs_mode (char * unused ATTRIBUTE_UNUSED) | |
25264 | { | |
25265 | codecomposer_syntax = TRUE; | |
25266 | arm_comment_chars[0] = ';'; | |
25267 | arm_line_separator_chars[0] = 0; | |
25268 | return TRUE; | |
25269 | } | |
25270 | ||
c19d1205 ZW |
25271 | struct arm_long_option_table arm_long_opts[] = |
25272 | { | |
25273 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
25274 | arm_parse_cpu, NULL}, | |
25275 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
25276 | arm_parse_arch, NULL}, | |
25277 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
25278 | arm_parse_fpu, NULL}, | |
25279 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
25280 | arm_parse_float_abi, NULL}, | |
25281 | #ifdef OBJ_ELF | |
7fac0536 | 25282 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
25283 | arm_parse_eabi, NULL}, |
25284 | #endif | |
e07e6e58 NC |
25285 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
25286 | arm_parse_it_mode, NULL}, | |
2e6976a8 DG |
25287 | {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), |
25288 | arm_ccs_mode, NULL}, | |
c19d1205 ZW |
25289 | {NULL, NULL, 0, NULL} |
25290 | }; | |
cc8a6dd0 | 25291 | |
c19d1205 ZW |
25292 | int |
25293 | md_parse_option (int c, char * arg) | |
25294 | { | |
25295 | struct arm_option_table *opt; | |
e74cfd16 | 25296 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 25297 | struct arm_long_option_table *lopt; |
b99bd4ef | 25298 | |
c19d1205 | 25299 | switch (c) |
b99bd4ef | 25300 | { |
c19d1205 ZW |
25301 | #ifdef OPTION_EB |
25302 | case OPTION_EB: | |
25303 | target_big_endian = 1; | |
25304 | break; | |
25305 | #endif | |
cc8a6dd0 | 25306 | |
c19d1205 ZW |
25307 | #ifdef OPTION_EL |
25308 | case OPTION_EL: | |
25309 | target_big_endian = 0; | |
25310 | break; | |
25311 | #endif | |
b99bd4ef | 25312 | |
845b51d6 PB |
25313 | case OPTION_FIX_V4BX: |
25314 | fix_v4bx = TRUE; | |
25315 | break; | |
25316 | ||
c19d1205 ZW |
25317 | case 'a': |
25318 | /* Listing option. Just ignore these, we don't support additional | |
25319 | ones. */ | |
25320 | return 0; | |
b99bd4ef | 25321 | |
c19d1205 ZW |
25322 | default: |
25323 | for (opt = arm_opts; opt->option != NULL; opt++) | |
25324 | { | |
25325 | if (c == opt->option[0] | |
25326 | && ((arg == NULL && opt->option[1] == 0) | |
25327 | || streq (arg, opt->option + 1))) | |
25328 | { | |
c19d1205 | 25329 | /* If the option is deprecated, tell the user. */ |
278df34e | 25330 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
25331 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
25332 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 25333 | |
c19d1205 ZW |
25334 | if (opt->var != NULL) |
25335 | *opt->var = opt->value; | |
cc8a6dd0 | 25336 | |
c19d1205 ZW |
25337 | return 1; |
25338 | } | |
25339 | } | |
b99bd4ef | 25340 | |
e74cfd16 PB |
25341 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
25342 | { | |
25343 | if (c == fopt->option[0] | |
25344 | && ((arg == NULL && fopt->option[1] == 0) | |
25345 | || streq (arg, fopt->option + 1))) | |
25346 | { | |
e74cfd16 | 25347 | /* If the option is deprecated, tell the user. */ |
278df34e | 25348 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
25349 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
25350 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
25351 | |
25352 | if (fopt->var != NULL) | |
25353 | *fopt->var = &fopt->value; | |
25354 | ||
25355 | return 1; | |
25356 | } | |
25357 | } | |
25358 | ||
c19d1205 ZW |
25359 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25360 | { | |
25361 | /* These options are expected to have an argument. */ | |
25362 | if (c == lopt->option[0] | |
25363 | && arg != NULL | |
25364 | && strncmp (arg, lopt->option + 1, | |
25365 | strlen (lopt->option + 1)) == 0) | |
25366 | { | |
c19d1205 | 25367 | /* If the option is deprecated, tell the user. */ |
278df34e | 25368 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
25369 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
25370 | _(lopt->deprecated)); | |
b99bd4ef | 25371 | |
c19d1205 ZW |
25372 | /* Call the sup-option parser. */ |
25373 | return lopt->func (arg + strlen (lopt->option) - 1); | |
25374 | } | |
25375 | } | |
a737bd4d | 25376 | |
c19d1205 ZW |
25377 | return 0; |
25378 | } | |
a394c00f | 25379 | |
c19d1205 ZW |
25380 | return 1; |
25381 | } | |
a394c00f | 25382 | |
c19d1205 ZW |
25383 | void |
25384 | md_show_usage (FILE * fp) | |
a394c00f | 25385 | { |
c19d1205 ZW |
25386 | struct arm_option_table *opt; |
25387 | struct arm_long_option_table *lopt; | |
a394c00f | 25388 | |
c19d1205 | 25389 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 25390 | |
c19d1205 ZW |
25391 | for (opt = arm_opts; opt->option != NULL; opt++) |
25392 | if (opt->help != NULL) | |
25393 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 25394 | |
c19d1205 ZW |
25395 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
25396 | if (lopt->help != NULL) | |
25397 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 25398 | |
c19d1205 ZW |
25399 | #ifdef OPTION_EB |
25400 | fprintf (fp, _("\ | |
25401 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
25402 | #endif |
25403 | ||
c19d1205 ZW |
25404 | #ifdef OPTION_EL |
25405 | fprintf (fp, _("\ | |
25406 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 25407 | #endif |
845b51d6 PB |
25408 | |
25409 | fprintf (fp, _("\ | |
25410 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 25411 | } |
ee065d83 PB |
25412 | |
25413 | ||
25414 | #ifdef OBJ_ELF | |
62b3e311 PB |
25415 | typedef struct |
25416 | { | |
25417 | int val; | |
25418 | arm_feature_set flags; | |
25419 | } cpu_arch_ver_table; | |
25420 | ||
25421 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
25422 | least features first. */ | |
25423 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
25424 | { | |
25425 | {1, ARM_ARCH_V4}, | |
25426 | {2, ARM_ARCH_V4T}, | |
25427 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 25428 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
25429 | {4, ARM_ARCH_V5TE}, |
25430 | {5, ARM_ARCH_V5TEJ}, | |
25431 | {6, ARM_ARCH_V6}, | |
7e806470 | 25432 | {9, ARM_ARCH_V6K}, |
f4c65163 | 25433 | {7, ARM_ARCH_V6Z}, |
91e22acd | 25434 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 25435 | {12, ARM_ARCH_V6SM}, |
7e806470 | 25436 | {8, ARM_ARCH_V6T2}, |
c9fb6e58 | 25437 | {10, ARM_ARCH_V7VE}, |
62b3e311 PB |
25438 | {10, ARM_ARCH_V7R}, |
25439 | {10, ARM_ARCH_V7M}, | |
bca38921 | 25440 | {14, ARM_ARCH_V8A}, |
62b3e311 PB |
25441 | {0, ARM_ARCH_NONE} |
25442 | }; | |
25443 | ||
ee3c0378 AS |
25444 | /* Set an attribute if it has not already been set by the user. */ |
25445 | static void | |
25446 | aeabi_set_attribute_int (int tag, int value) | |
25447 | { | |
25448 | if (tag < 1 | |
25449 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25450 | || !attributes_set_explicitly[tag]) | |
25451 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
25452 | } | |
25453 | ||
25454 | static void | |
25455 | aeabi_set_attribute_string (int tag, const char *value) | |
25456 | { | |
25457 | if (tag < 1 | |
25458 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
25459 | || !attributes_set_explicitly[tag]) | |
25460 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
25461 | } | |
25462 | ||
ee065d83 | 25463 | /* Set the public EABI object attributes. */ |
3cfdb781 | 25464 | void |
ee065d83 PB |
25465 | aeabi_set_public_attributes (void) |
25466 | { | |
25467 | int arch; | |
69239280 | 25468 | char profile; |
90ec0d68 | 25469 | int virt_sec = 0; |
bca38921 | 25470 | int fp16_optional = 0; |
e74cfd16 | 25471 | arm_feature_set flags; |
62b3e311 PB |
25472 | arm_feature_set tmp; |
25473 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
25474 | |
25475 | /* Choose the architecture based on the capabilities of the requested cpu | |
25476 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
25477 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
25478 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
25479 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
25480 | |
25481 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
25482 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
25483 | ||
25484 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
25485 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
25486 | ||
7f78eb34 JW |
25487 | selected_cpu = flags; |
25488 | ||
ddd7f988 | 25489 | /* Allow the user to override the reported architecture. */ |
7a1d4c38 PB |
25490 | if (object_arch) |
25491 | { | |
25492 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
25493 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
25494 | } | |
25495 | ||
251665fc MGD |
25496 | /* We need to make sure that the attributes do not identify us as v6S-M |
25497 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
25498 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
25499 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
477330fc | 25500 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); |
251665fc | 25501 | |
62b3e311 PB |
25502 | tmp = flags; |
25503 | arch = 0; | |
25504 | for (p = cpu_arch_ver; p->val; p++) | |
25505 | { | |
25506 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
25507 | { | |
25508 | arch = p->val; | |
25509 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
25510 | } | |
25511 | } | |
ee065d83 | 25512 | |
9e3c6df6 PB |
25513 | /* The table lookup above finds the last architecture to contribute |
25514 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
25515 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
25516 | We can not search for the last entry which is entirely used, | |
25517 | because if no CPU is specified we build up only those flags | |
25518 | actually used. Perhaps we should separate out the specified | |
25519 | and implicit cases. Avoid taking this path for -march=all by | |
25520 | checking for contradictory v7-A / v7-M features. */ | |
25521 | if (arch == 10 | |
25522 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
25523 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
25524 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
25525 | arch = 13; | |
25526 | ||
ee065d83 PB |
25527 | /* Tag_CPU_name. */ |
25528 | if (selected_cpu_name[0]) | |
25529 | { | |
91d6fa6a | 25530 | char *q; |
ee065d83 | 25531 | |
91d6fa6a NC |
25532 | q = selected_cpu_name; |
25533 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
25534 | { |
25535 | int i; | |
5f4273c7 | 25536 | |
91d6fa6a NC |
25537 | q += 4; |
25538 | for (i = 0; q[i]; i++) | |
25539 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 25540 | } |
91d6fa6a | 25541 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 25542 | } |
62f3b8c8 | 25543 | |
ee065d83 | 25544 | /* Tag_CPU_arch. */ |
ee3c0378 | 25545 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 25546 | |
62b3e311 PB |
25547 | /* Tag_CPU_arch_profile. */ |
25548 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
69239280 | 25549 | profile = 'A'; |
62b3e311 | 25550 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
69239280 | 25551 | profile = 'R'; |
7e806470 | 25552 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
69239280 MGD |
25553 | profile = 'M'; |
25554 | else | |
25555 | profile = '\0'; | |
25556 | ||
25557 | if (profile != '\0') | |
25558 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 25559 | |
ee065d83 | 25560 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
25561 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
25562 | || arch == 0) | |
25563 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 25564 | |
ee065d83 | 25565 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
25566 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
25567 | || arch == 0) | |
25568 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
25569 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 25570 | |
ee065d83 | 25571 | /* Tag_VFP_arch. */ |
a715796b TG |
25572 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd)) |
25573 | aeabi_set_attribute_int (Tag_VFP_arch, | |
25574 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25575 | ? 7 : 8); | |
bca38921 | 25576 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
62f3b8c8 PB |
25577 | aeabi_set_attribute_int (Tag_VFP_arch, |
25578 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
25579 | ? 5 : 6); | |
25580 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
25581 | { |
25582 | fp16_optional = 1; | |
25583 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
25584 | } | |
ada65aa3 | 25585 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
25586 | { |
25587 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
25588 | fp16_optional = 1; | |
25589 | } | |
ee3c0378 AS |
25590 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
25591 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
25592 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
477330fc | 25593 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) |
ee3c0378 | 25594 | aeabi_set_attribute_int (Tag_VFP_arch, 1); |
62f3b8c8 | 25595 | |
4547cb56 NC |
25596 | /* Tag_ABI_HardFP_use. */ |
25597 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
25598 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
25599 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
25600 | ||
ee065d83 | 25601 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
25602 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
25603 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
25604 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
25605 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 25606 | |
ee3c0378 | 25607 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
bca38921 MGD |
25608 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
25609 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); | |
25610 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
25611 | { | |
25612 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
25613 | { | |
25614 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
25615 | } | |
25616 | else | |
25617 | { | |
25618 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
25619 | fp16_optional = 1; | |
25620 | } | |
25621 | } | |
fa94de6b | 25622 | |
ee3c0378 | 25623 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 25624 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 25625 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 25626 | |
69239280 MGD |
25627 | /* Tag_DIV_use. |
25628 | ||
25629 | We set Tag_DIV_use to two when integer divide instructions have been used | |
25630 | in ARM state, or when Thumb integer divide instructions have been used, | |
25631 | but we have no architecture profile set, nor have we any ARM instructions. | |
25632 | ||
bca38921 MGD |
25633 | For ARMv8 we set the tag to 0 as integer divide is implied by the base |
25634 | architecture. | |
25635 | ||
69239280 | 25636 | For new architectures we will have to check these tests. */ |
bca38921 MGD |
25637 | gas_assert (arch <= TAG_CPU_ARCH_V8); |
25638 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) | |
25639 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
25640 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
25641 | || (profile == '\0' | |
25642 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
25643 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 25644 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
25645 | |
25646 | /* Tag_MP_extension_use. */ | |
25647 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
25648 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
25649 | |
25650 | /* Tag Virtualization_use. */ | |
25651 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
25652 | virt_sec |= 1; |
25653 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
25654 | virt_sec |= 2; | |
25655 | if (virt_sec != 0) | |
25656 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
25657 | } |
25658 | ||
104d59d1 | 25659 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
25660 | void |
25661 | arm_md_end (void) | |
25662 | { | |
ee065d83 PB |
25663 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
25664 | return; | |
25665 | ||
25666 | aeabi_set_public_attributes (); | |
ee065d83 | 25667 | } |
8463be01 | 25668 | #endif /* OBJ_ELF */ |
ee065d83 PB |
25669 | |
25670 | ||
25671 | /* Parse a .cpu directive. */ | |
25672 | ||
25673 | static void | |
25674 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
25675 | { | |
e74cfd16 | 25676 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
25677 | char *name; |
25678 | char saved_char; | |
25679 | ||
25680 | name = input_line_pointer; | |
5f4273c7 | 25681 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25682 | input_line_pointer++; |
25683 | saved_char = *input_line_pointer; | |
25684 | *input_line_pointer = 0; | |
25685 | ||
25686 | /* Skip the first "all" entry. */ | |
25687 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
25688 | if (streq (opt->name, name)) | |
25689 | { | |
e74cfd16 PB |
25690 | mcpu_cpu_opt = &opt->value; |
25691 | selected_cpu = opt->value; | |
ee065d83 | 25692 | if (opt->canonical_name) |
5f4273c7 | 25693 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
25694 | else |
25695 | { | |
25696 | int i; | |
25697 | for (i = 0; opt->name[i]; i++) | |
25698 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 25699 | |
ee065d83 PB |
25700 | selected_cpu_name[i] = 0; |
25701 | } | |
e74cfd16 | 25702 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25703 | *input_line_pointer = saved_char; |
25704 | demand_empty_rest_of_line (); | |
25705 | return; | |
25706 | } | |
25707 | as_bad (_("unknown cpu `%s'"), name); | |
25708 | *input_line_pointer = saved_char; | |
25709 | ignore_rest_of_line (); | |
25710 | } | |
25711 | ||
25712 | ||
25713 | /* Parse a .arch directive. */ | |
25714 | ||
25715 | static void | |
25716 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
25717 | { | |
e74cfd16 | 25718 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
25719 | char saved_char; |
25720 | char *name; | |
25721 | ||
25722 | name = input_line_pointer; | |
5f4273c7 | 25723 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25724 | input_line_pointer++; |
25725 | saved_char = *input_line_pointer; | |
25726 | *input_line_pointer = 0; | |
25727 | ||
25728 | /* Skip the first "all" entry. */ | |
25729 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25730 | if (streq (opt->name, name)) | |
25731 | { | |
e74cfd16 PB |
25732 | mcpu_cpu_opt = &opt->value; |
25733 | selected_cpu = opt->value; | |
5f4273c7 | 25734 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 25735 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
25736 | *input_line_pointer = saved_char; |
25737 | demand_empty_rest_of_line (); | |
25738 | return; | |
25739 | } | |
25740 | ||
25741 | as_bad (_("unknown architecture `%s'\n"), name); | |
25742 | *input_line_pointer = saved_char; | |
25743 | ignore_rest_of_line (); | |
25744 | } | |
25745 | ||
25746 | ||
7a1d4c38 PB |
25747 | /* Parse a .object_arch directive. */ |
25748 | ||
25749 | static void | |
25750 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
25751 | { | |
25752 | const struct arm_arch_option_table *opt; | |
25753 | char saved_char; | |
25754 | char *name; | |
25755 | ||
25756 | name = input_line_pointer; | |
5f4273c7 | 25757 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
25758 | input_line_pointer++; |
25759 | saved_char = *input_line_pointer; | |
25760 | *input_line_pointer = 0; | |
25761 | ||
25762 | /* Skip the first "all" entry. */ | |
25763 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
25764 | if (streq (opt->name, name)) | |
25765 | { | |
25766 | object_arch = &opt->value; | |
25767 | *input_line_pointer = saved_char; | |
25768 | demand_empty_rest_of_line (); | |
25769 | return; | |
25770 | } | |
25771 | ||
25772 | as_bad (_("unknown architecture `%s'\n"), name); | |
25773 | *input_line_pointer = saved_char; | |
25774 | ignore_rest_of_line (); | |
25775 | } | |
25776 | ||
69133863 MGD |
25777 | /* Parse a .arch_extension directive. */ |
25778 | ||
25779 | static void | |
25780 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
25781 | { | |
25782 | const struct arm_option_extension_value_table *opt; | |
25783 | char saved_char; | |
25784 | char *name; | |
25785 | int adding_value = 1; | |
25786 | ||
25787 | name = input_line_pointer; | |
25788 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
25789 | input_line_pointer++; | |
25790 | saved_char = *input_line_pointer; | |
25791 | *input_line_pointer = 0; | |
25792 | ||
25793 | if (strlen (name) >= 2 | |
25794 | && strncmp (name, "no", 2) == 0) | |
25795 | { | |
25796 | adding_value = 0; | |
25797 | name += 2; | |
25798 | } | |
25799 | ||
25800 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
25801 | if (streq (opt->name, name)) | |
25802 | { | |
25803 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
25804 | { | |
25805 | as_bad (_("architectural extension `%s' is not allowed for the " | |
25806 | "current base architecture"), name); | |
25807 | break; | |
25808 | } | |
25809 | ||
25810 | if (adding_value) | |
5a70a223 JB |
25811 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, |
25812 | opt->merge_value); | |
69133863 | 25813 | else |
5a70a223 | 25814 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value); |
69133863 MGD |
25815 | |
25816 | mcpu_cpu_opt = &selected_cpu; | |
25817 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
25818 | *input_line_pointer = saved_char; | |
25819 | demand_empty_rest_of_line (); | |
25820 | return; | |
25821 | } | |
25822 | ||
25823 | if (opt->name == NULL) | |
e673710a | 25824 | as_bad (_("unknown architecture extension `%s'\n"), name); |
69133863 MGD |
25825 | |
25826 | *input_line_pointer = saved_char; | |
25827 | ignore_rest_of_line (); | |
25828 | } | |
25829 | ||
ee065d83 PB |
25830 | /* Parse a .fpu directive. */ |
25831 | ||
25832 | static void | |
25833 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
25834 | { | |
69133863 | 25835 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
25836 | char saved_char; |
25837 | char *name; | |
25838 | ||
25839 | name = input_line_pointer; | |
5f4273c7 | 25840 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
25841 | input_line_pointer++; |
25842 | saved_char = *input_line_pointer; | |
25843 | *input_line_pointer = 0; | |
5f4273c7 | 25844 | |
ee065d83 PB |
25845 | for (opt = arm_fpus; opt->name != NULL; opt++) |
25846 | if (streq (opt->name, name)) | |
25847 | { | |
e74cfd16 PB |
25848 | mfpu_opt = &opt->value; |
25849 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
25850 | *input_line_pointer = saved_char; |
25851 | demand_empty_rest_of_line (); | |
25852 | return; | |
25853 | } | |
25854 | ||
25855 | as_bad (_("unknown floating point format `%s'\n"), name); | |
25856 | *input_line_pointer = saved_char; | |
25857 | ignore_rest_of_line (); | |
25858 | } | |
ee065d83 | 25859 | |
794ba86a | 25860 | /* Copy symbol information. */ |
f31fef98 | 25861 | |
794ba86a DJ |
25862 | void |
25863 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
25864 | { | |
25865 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
25866 | } | |
e04befd0 | 25867 | |
f31fef98 | 25868 | #ifdef OBJ_ELF |
e04befd0 AS |
25869 | /* Given a symbolic attribute NAME, return the proper integer value. |
25870 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 25871 | |
e04befd0 AS |
25872 | int |
25873 | arm_convert_symbolic_attribute (const char *name) | |
25874 | { | |
f31fef98 NC |
25875 | static const struct |
25876 | { | |
25877 | const char * name; | |
25878 | const int tag; | |
25879 | } | |
25880 | attribute_table[] = | |
25881 | { | |
25882 | /* When you modify this table you should | |
25883 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 25884 | #define T(tag) {#tag, tag} |
f31fef98 NC |
25885 | T (Tag_CPU_raw_name), |
25886 | T (Tag_CPU_name), | |
25887 | T (Tag_CPU_arch), | |
25888 | T (Tag_CPU_arch_profile), | |
25889 | T (Tag_ARM_ISA_use), | |
25890 | T (Tag_THUMB_ISA_use), | |
75375b3e | 25891 | T (Tag_FP_arch), |
f31fef98 NC |
25892 | T (Tag_VFP_arch), |
25893 | T (Tag_WMMX_arch), | |
25894 | T (Tag_Advanced_SIMD_arch), | |
25895 | T (Tag_PCS_config), | |
25896 | T (Tag_ABI_PCS_R9_use), | |
25897 | T (Tag_ABI_PCS_RW_data), | |
25898 | T (Tag_ABI_PCS_RO_data), | |
25899 | T (Tag_ABI_PCS_GOT_use), | |
25900 | T (Tag_ABI_PCS_wchar_t), | |
25901 | T (Tag_ABI_FP_rounding), | |
25902 | T (Tag_ABI_FP_denormal), | |
25903 | T (Tag_ABI_FP_exceptions), | |
25904 | T (Tag_ABI_FP_user_exceptions), | |
25905 | T (Tag_ABI_FP_number_model), | |
75375b3e | 25906 | T (Tag_ABI_align_needed), |
f31fef98 | 25907 | T (Tag_ABI_align8_needed), |
75375b3e | 25908 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
25909 | T (Tag_ABI_align8_preserved), |
25910 | T (Tag_ABI_enum_size), | |
25911 | T (Tag_ABI_HardFP_use), | |
25912 | T (Tag_ABI_VFP_args), | |
25913 | T (Tag_ABI_WMMX_args), | |
25914 | T (Tag_ABI_optimization_goals), | |
25915 | T (Tag_ABI_FP_optimization_goals), | |
25916 | T (Tag_compatibility), | |
25917 | T (Tag_CPU_unaligned_access), | |
75375b3e | 25918 | T (Tag_FP_HP_extension), |
f31fef98 NC |
25919 | T (Tag_VFP_HP_extension), |
25920 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
25921 | T (Tag_MPextension_use), |
25922 | T (Tag_DIV_use), | |
f31fef98 NC |
25923 | T (Tag_nodefaults), |
25924 | T (Tag_also_compatible_with), | |
25925 | T (Tag_conformance), | |
25926 | T (Tag_T2EE_use), | |
25927 | T (Tag_Virtualization_use), | |
cd21e546 | 25928 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 25929 | #undef T |
f31fef98 | 25930 | }; |
e04befd0 AS |
25931 | unsigned int i; |
25932 | ||
25933 | if (name == NULL) | |
25934 | return -1; | |
25935 | ||
f31fef98 | 25936 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 25937 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
25938 | return attribute_table[i].tag; |
25939 | ||
25940 | return -1; | |
25941 | } | |
267bf995 RR |
25942 | |
25943 | ||
93ef582d NC |
25944 | /* Apply sym value for relocations only in the case that they are for |
25945 | local symbols in the same segment as the fixup and you have the | |
25946 | respective architectural feature for blx and simple switches. */ | |
267bf995 | 25947 | int |
93ef582d | 25948 | arm_apply_sym_value (struct fix * fixP, segT this_seg) |
267bf995 RR |
25949 | { |
25950 | if (fixP->fx_addsy | |
25951 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
93ef582d NC |
25952 | /* PR 17444: If the local symbol is in a different section then a reloc |
25953 | will always be generated for it, so applying the symbol value now | |
25954 | will result in a double offset being stored in the relocation. */ | |
25955 | && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg) | |
34e77a92 | 25956 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
25957 | { |
25958 | switch (fixP->fx_r_type) | |
25959 | { | |
25960 | case BFD_RELOC_ARM_PCREL_BLX: | |
25961 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
25962 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
25963 | return 1; | |
25964 | break; | |
25965 | ||
25966 | case BFD_RELOC_ARM_PCREL_CALL: | |
25967 | case BFD_RELOC_THUMB_PCREL_BLX: | |
25968 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
93ef582d | 25969 | return 1; |
267bf995 RR |
25970 | break; |
25971 | ||
25972 | default: | |
25973 | break; | |
25974 | } | |
25975 | ||
25976 | } | |
25977 | return 0; | |
25978 | } | |
f31fef98 | 25979 | #endif /* OBJ_ELF */ |