Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
fa94de6b | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
3da1d841 | 35 | #include "libiberty.h" |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 | 100 | /* The code that was here used to select a default CPU depending on compiler |
fa94de6b | 101 | pre-defines which were only present when doing native builds, thus |
8a59fff3 MGD |
102 | changing gas' default behaviour depending upon the build host. |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
bca38921 | 198 | static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0); |
7e806470 | 199 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 200 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 201 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 202 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 203 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 204 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 205 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
206 | |
207 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
208 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
209 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
210 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 211 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 212 | |
2d447fca JM |
213 | static const arm_feature_set arm_cext_iwmmxt2 = |
214 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
215 | static const arm_feature_set arm_cext_iwmmxt = |
216 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
217 | static const arm_feature_set arm_cext_xscale = | |
218 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
219 | static const arm_feature_set arm_cext_maverick = | |
220 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
221 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
222 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
223 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
224 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
225 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
226 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 227 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 228 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
229 | static const arm_feature_set fpu_vfp_ext_d32 = |
230 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
231 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
232 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
233 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
234 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
235 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
236 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
bca38921 MGD |
237 | static const arm_feature_set fpu_vfp_ext_armv8 = |
238 | ARM_FEATURE (0, FPU_VFP_EXT_ARMV8); | |
239 | static const arm_feature_set fpu_neon_ext_armv8 = | |
240 | ARM_FEATURE (0, FPU_NEON_EXT_ARMV8); | |
241 | static const arm_feature_set fpu_crypto_ext_armv8 = | |
242 | ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8); | |
e74cfd16 | 243 | |
33a392fb | 244 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
245 | /* Record user cpu selection for object attributes. */ |
246 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
247 | /* Must be long enough to hold any of the names in arm_cpus. */ |
248 | static char selected_cpu_name[16]; | |
8d67f500 NC |
249 | |
250 | /* Return if no cpu was selected on command-line. */ | |
251 | static bfd_boolean | |
252 | no_cpu_selected (void) | |
253 | { | |
254 | return selected_cpu.core == arm_arch_none.core | |
255 | && selected_cpu.coproc == arm_arch_none.coproc; | |
256 | } | |
257 | ||
7cc69913 | 258 | #ifdef OBJ_ELF |
deeaaff8 DJ |
259 | # ifdef EABI_DEFAULT |
260 | static int meabi_flags = EABI_DEFAULT; | |
261 | # else | |
d507cf36 | 262 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 263 | # endif |
e1da3f5b | 264 | |
ee3c0378 AS |
265 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
266 | ||
e1da3f5b | 267 | bfd_boolean |
5f4273c7 | 268 | arm_is_eabi (void) |
e1da3f5b PB |
269 | { |
270 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
271 | } | |
7cc69913 | 272 | #endif |
b99bd4ef | 273 | |
b99bd4ef | 274 | #ifdef OBJ_ELF |
c19d1205 | 275 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
276 | symbolS * GOT_symbol; |
277 | #endif | |
278 | ||
b99bd4ef NC |
279 | /* 0: assemble for ARM, |
280 | 1: assemble for Thumb, | |
281 | 2: assemble for Thumb even though target CPU does not support thumb | |
282 | instructions. */ | |
283 | static int thumb_mode = 0; | |
8dc2430f NC |
284 | /* A value distinct from the possible values for thumb_mode that we |
285 | can use to record whether thumb_mode has been copied into the | |
286 | tc_frag_data field of a frag. */ | |
287 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 288 | |
e07e6e58 NC |
289 | /* Specifies the intrinsic IT insn behavior mode. */ |
290 | enum implicit_it_mode | |
291 | { | |
292 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
293 | IMPLICIT_IT_MODE_ARM = 0x01, | |
294 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
295 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
296 | }; | |
297 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
298 | ||
c19d1205 ZW |
299 | /* If unified_syntax is true, we are processing the new unified |
300 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
301 | ||
302 | - Immediate operands do not require a # prefix. | |
303 | - Conditional affixes always appear at the end of the | |
304 | instruction. (For backward compatibility, those instructions | |
305 | that formerly had them in the middle, continue to accept them | |
306 | there.) | |
307 | - The IT instruction may appear, and if it does is validated | |
308 | against subsequent conditional affixes. It does not generate | |
309 | machine code. | |
310 | ||
311 | Important differences from the old Thumb mode: | |
312 | ||
313 | - Immediate operands do not require a # prefix. | |
314 | - Most of the V6T2 instructions are only available in unified mode. | |
315 | - The .N and .W suffixes are recognized and honored (it is an error | |
316 | if they cannot be honored). | |
317 | - All instructions set the flags if and only if they have an 's' affix. | |
318 | - Conditional affixes may be used. They are validated against | |
319 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
320 | conditional affix except in the scope of an IT instruction. */ | |
321 | ||
322 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 323 | |
5287ad62 JB |
324 | enum neon_el_type |
325 | { | |
dcbf9037 | 326 | NT_invtype, |
5287ad62 JB |
327 | NT_untyped, |
328 | NT_integer, | |
329 | NT_float, | |
330 | NT_poly, | |
331 | NT_signed, | |
dcbf9037 | 332 | NT_unsigned |
5287ad62 JB |
333 | }; |
334 | ||
335 | struct neon_type_el | |
336 | { | |
337 | enum neon_el_type type; | |
338 | unsigned size; | |
339 | }; | |
340 | ||
341 | #define NEON_MAX_TYPE_ELS 4 | |
342 | ||
343 | struct neon_type | |
344 | { | |
345 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
346 | unsigned elems; | |
347 | }; | |
348 | ||
e07e6e58 NC |
349 | enum it_instruction_type |
350 | { | |
351 | OUTSIDE_IT_INSN, | |
352 | INSIDE_IT_INSN, | |
353 | INSIDE_IT_LAST_INSN, | |
354 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
355 | if inside, should be the last one. */ | |
356 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
357 | i.e. BKPT and NOP. */ | |
358 | IT_INSN /* The IT insn has been parsed. */ | |
359 | }; | |
360 | ||
ad6cec43 MGD |
361 | /* The maximum number of operands we need. */ |
362 | #define ARM_IT_MAX_OPERANDS 6 | |
363 | ||
b99bd4ef NC |
364 | struct arm_it |
365 | { | |
c19d1205 | 366 | const char * error; |
b99bd4ef | 367 | unsigned long instruction; |
c19d1205 ZW |
368 | int size; |
369 | int size_req; | |
370 | int cond; | |
037e8744 JB |
371 | /* "uncond_value" is set to the value in place of the conditional field in |
372 | unconditional versions of the instruction, or -1 if nothing is | |
373 | appropriate. */ | |
374 | int uncond_value; | |
5287ad62 | 375 | struct neon_type vectype; |
88714cb8 DG |
376 | /* This does not indicate an actual NEON instruction, only that |
377 | the mnemonic accepts neon-style type suffixes. */ | |
378 | int is_neon; | |
0110f2b8 PB |
379 | /* Set to the opcode if the instruction needs relaxation. |
380 | Zero if the instruction is not relaxed. */ | |
381 | unsigned long relax; | |
b99bd4ef NC |
382 | struct |
383 | { | |
384 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
385 | expressionS exp; |
386 | int pc_rel; | |
b99bd4ef | 387 | } reloc; |
b99bd4ef | 388 | |
e07e6e58 NC |
389 | enum it_instruction_type it_insn_type; |
390 | ||
c19d1205 ZW |
391 | struct |
392 | { | |
393 | unsigned reg; | |
ca3f61f7 | 394 | signed int imm; |
dcbf9037 | 395 | struct neon_type_el vectype; |
ca3f61f7 NC |
396 | unsigned present : 1; /* Operand present. */ |
397 | unsigned isreg : 1; /* Operand was a register. */ | |
398 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
399 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
400 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 401 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
402 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
403 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
404 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 405 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 406 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 407 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
408 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
409 | unsigned writeback : 1; /* Operand has trailing ! */ | |
410 | unsigned preind : 1; /* Preindexed address. */ | |
411 | unsigned postind : 1; /* Postindexed address. */ | |
412 | unsigned negative : 1; /* Index register was negated. */ | |
413 | unsigned shifted : 1; /* Shift applied to operation. */ | |
414 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 415 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
416 | }; |
417 | ||
c19d1205 | 418 | static struct arm_it inst; |
b99bd4ef NC |
419 | |
420 | #define NUM_FLOAT_VALS 8 | |
421 | ||
05d2d07e | 422 | const char * fp_const[] = |
b99bd4ef NC |
423 | { |
424 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
425 | }; | |
426 | ||
c19d1205 | 427 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
428 | #define MAX_LITTLENUMS 6 |
429 | ||
430 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
431 | ||
432 | #define FAIL (-1) | |
433 | #define SUCCESS (0) | |
434 | ||
435 | #define SUFF_S 1 | |
436 | #define SUFF_D 2 | |
437 | #define SUFF_E 3 | |
438 | #define SUFF_P 4 | |
439 | ||
c19d1205 ZW |
440 | #define CP_T_X 0x00008000 |
441 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 442 | |
c19d1205 ZW |
443 | #define CONDS_BIT 0x00100000 |
444 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
445 | |
446 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
447 | ||
448 | struct asm_cond | |
449 | { | |
d3ce72d0 | 450 | const char * template_name; |
c921be7d | 451 | unsigned long value; |
b99bd4ef NC |
452 | }; |
453 | ||
c19d1205 | 454 | #define COND_ALWAYS 0xE |
b99bd4ef | 455 | |
b99bd4ef NC |
456 | struct asm_psr |
457 | { | |
d3ce72d0 | 458 | const char * template_name; |
c921be7d | 459 | unsigned long field; |
b99bd4ef NC |
460 | }; |
461 | ||
62b3e311 PB |
462 | struct asm_barrier_opt |
463 | { | |
d3ce72d0 | 464 | const char * template_name; |
c921be7d | 465 | unsigned long value; |
62b3e311 PB |
466 | }; |
467 | ||
2d2255b5 | 468 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
469 | #define SPSR_BIT (1 << 22) |
470 | ||
c19d1205 ZW |
471 | /* The individual PSR flag bits. */ |
472 | #define PSR_c (1 << 16) | |
473 | #define PSR_x (1 << 17) | |
474 | #define PSR_s (1 << 18) | |
475 | #define PSR_f (1 << 19) | |
b99bd4ef | 476 | |
c19d1205 | 477 | struct reloc_entry |
bfae80f2 | 478 | { |
c921be7d NC |
479 | char * name; |
480 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
481 | }; |
482 | ||
5287ad62 | 483 | enum vfp_reg_pos |
bfae80f2 | 484 | { |
5287ad62 JB |
485 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
486 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
487 | }; |
488 | ||
489 | enum vfp_ldstm_type | |
490 | { | |
491 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
492 | }; | |
493 | ||
dcbf9037 JB |
494 | /* Bits for DEFINED field in neon_typed_alias. */ |
495 | #define NTA_HASTYPE 1 | |
496 | #define NTA_HASINDEX 2 | |
497 | ||
498 | struct neon_typed_alias | |
499 | { | |
c921be7d NC |
500 | unsigned char defined; |
501 | unsigned char index; | |
502 | struct neon_type_el eltype; | |
dcbf9037 JB |
503 | }; |
504 | ||
c19d1205 ZW |
505 | /* ARM register categories. This includes coprocessor numbers and various |
506 | architecture extensions' registers. */ | |
507 | enum arm_reg_type | |
bfae80f2 | 508 | { |
c19d1205 ZW |
509 | REG_TYPE_RN, |
510 | REG_TYPE_CP, | |
511 | REG_TYPE_CN, | |
512 | REG_TYPE_FN, | |
513 | REG_TYPE_VFS, | |
514 | REG_TYPE_VFD, | |
5287ad62 | 515 | REG_TYPE_NQ, |
037e8744 | 516 | REG_TYPE_VFSD, |
5287ad62 | 517 | REG_TYPE_NDQ, |
037e8744 | 518 | REG_TYPE_NSDQ, |
c19d1205 ZW |
519 | REG_TYPE_VFC, |
520 | REG_TYPE_MVF, | |
521 | REG_TYPE_MVD, | |
522 | REG_TYPE_MVFX, | |
523 | REG_TYPE_MVDX, | |
524 | REG_TYPE_MVAX, | |
525 | REG_TYPE_DSPSC, | |
526 | REG_TYPE_MMXWR, | |
527 | REG_TYPE_MMXWC, | |
528 | REG_TYPE_MMXWCG, | |
529 | REG_TYPE_XSCALE, | |
90ec0d68 | 530 | REG_TYPE_RNB |
bfae80f2 RE |
531 | }; |
532 | ||
dcbf9037 JB |
533 | /* Structure for a hash table entry for a register. |
534 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
535 | information which states whether a vector type or index is specified (for a | |
536 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
537 | struct reg_entry |
538 | { | |
c921be7d | 539 | const char * name; |
90ec0d68 | 540 | unsigned int number; |
c921be7d NC |
541 | unsigned char type; |
542 | unsigned char builtin; | |
543 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
544 | }; |
545 | ||
c19d1205 | 546 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 547 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
548 | { |
549 | N_("ARM register expected"), | |
550 | N_("bad or missing co-processor number"), | |
551 | N_("co-processor register expected"), | |
552 | N_("FPA register expected"), | |
553 | N_("VFP single precision register expected"), | |
5287ad62 JB |
554 | N_("VFP/Neon double precision register expected"), |
555 | N_("Neon quad precision register expected"), | |
037e8744 | 556 | N_("VFP single or double precision register expected"), |
5287ad62 | 557 | N_("Neon double or quad precision register expected"), |
037e8744 | 558 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
559 | N_("VFP system register expected"), |
560 | N_("Maverick MVF register expected"), | |
561 | N_("Maverick MVD register expected"), | |
562 | N_("Maverick MVFX register expected"), | |
563 | N_("Maverick MVDX register expected"), | |
564 | N_("Maverick MVAX register expected"), | |
565 | N_("Maverick DSPSC register expected"), | |
566 | N_("iWMMXt data register expected"), | |
567 | N_("iWMMXt control register expected"), | |
568 | N_("iWMMXt scalar register expected"), | |
569 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
570 | }; |
571 | ||
c19d1205 | 572 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 573 | #define REG_R12 12 |
c19d1205 ZW |
574 | #define REG_SP 13 |
575 | #define REG_LR 14 | |
576 | #define REG_PC 15 | |
404ff6b5 | 577 | |
b99bd4ef NC |
578 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
579 | take 2: */ | |
c19d1205 | 580 | #define INSN_SIZE 4 |
b99bd4ef NC |
581 | |
582 | struct asm_opcode | |
583 | { | |
584 | /* Basic string to match. */ | |
d3ce72d0 | 585 | const char * template_name; |
c19d1205 ZW |
586 | |
587 | /* Parameters to instruction. */ | |
5be8be5d | 588 | unsigned int operands[8]; |
c19d1205 ZW |
589 | |
590 | /* Conditional tag - see opcode_lookup. */ | |
591 | unsigned int tag : 4; | |
b99bd4ef NC |
592 | |
593 | /* Basic instruction code. */ | |
c19d1205 | 594 | unsigned int avalue : 28; |
b99bd4ef | 595 | |
c19d1205 ZW |
596 | /* Thumb-format instruction code. */ |
597 | unsigned int tvalue; | |
b99bd4ef | 598 | |
90e4755a | 599 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
600 | const arm_feature_set * avariant; |
601 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
602 | |
603 | /* Function to call to encode instruction in ARM format. */ | |
604 | void (* aencode) (void); | |
b99bd4ef | 605 | |
c19d1205 ZW |
606 | /* Function to call to encode instruction in Thumb format. */ |
607 | void (* tencode) (void); | |
b99bd4ef NC |
608 | }; |
609 | ||
a737bd4d NC |
610 | /* Defines for various bits that we will want to toggle. */ |
611 | #define INST_IMMEDIATE 0x02000000 | |
612 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 613 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
614 | #define SHIFT_BY_REG 0x00000010 |
615 | #define PRE_INDEX 0x01000000 | |
616 | #define INDEX_UP 0x00800000 | |
617 | #define WRITE_BACK 0x00200000 | |
618 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 619 | #define CPSI_MMOD 0x00020000 |
90e4755a | 620 | |
a737bd4d NC |
621 | #define LITERAL_MASK 0xf000f000 |
622 | #define OPCODE_MASK 0xfe1fffff | |
623 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 624 | |
efd81785 PB |
625 | #define T2_SUBS_PC_LR 0xf3de8f00 |
626 | ||
a737bd4d | 627 | #define DATA_OP_SHIFT 21 |
90e4755a | 628 | |
ef8d22e6 PB |
629 | #define T2_OPCODE_MASK 0xfe1fffff |
630 | #define T2_DATA_OP_SHIFT 21 | |
631 | ||
6530b175 NC |
632 | #define A_COND_MASK 0xf0000000 |
633 | #define A_PUSH_POP_OP_MASK 0x0fff0000 | |
634 | ||
635 | /* Opcodes for pushing/poping registers to/from the stack. */ | |
636 | #define A1_OPCODE_PUSH 0x092d0000 | |
637 | #define A2_OPCODE_PUSH 0x052d0004 | |
638 | #define A2_OPCODE_POP 0x049d0004 | |
639 | ||
a737bd4d NC |
640 | /* Codes to distinguish the arithmetic instructions. */ |
641 | #define OPCODE_AND 0 | |
642 | #define OPCODE_EOR 1 | |
643 | #define OPCODE_SUB 2 | |
644 | #define OPCODE_RSB 3 | |
645 | #define OPCODE_ADD 4 | |
646 | #define OPCODE_ADC 5 | |
647 | #define OPCODE_SBC 6 | |
648 | #define OPCODE_RSC 7 | |
649 | #define OPCODE_TST 8 | |
650 | #define OPCODE_TEQ 9 | |
651 | #define OPCODE_CMP 10 | |
652 | #define OPCODE_CMN 11 | |
653 | #define OPCODE_ORR 12 | |
654 | #define OPCODE_MOV 13 | |
655 | #define OPCODE_BIC 14 | |
656 | #define OPCODE_MVN 15 | |
90e4755a | 657 | |
ef8d22e6 PB |
658 | #define T2_OPCODE_AND 0 |
659 | #define T2_OPCODE_BIC 1 | |
660 | #define T2_OPCODE_ORR 2 | |
661 | #define T2_OPCODE_ORN 3 | |
662 | #define T2_OPCODE_EOR 4 | |
663 | #define T2_OPCODE_ADD 8 | |
664 | #define T2_OPCODE_ADC 10 | |
665 | #define T2_OPCODE_SBC 11 | |
666 | #define T2_OPCODE_SUB 13 | |
667 | #define T2_OPCODE_RSB 14 | |
668 | ||
a737bd4d NC |
669 | #define T_OPCODE_MUL 0x4340 |
670 | #define T_OPCODE_TST 0x4200 | |
671 | #define T_OPCODE_CMN 0x42c0 | |
672 | #define T_OPCODE_NEG 0x4240 | |
673 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 674 | |
a737bd4d NC |
675 | #define T_OPCODE_ADD_R3 0x1800 |
676 | #define T_OPCODE_SUB_R3 0x1a00 | |
677 | #define T_OPCODE_ADD_HI 0x4400 | |
678 | #define T_OPCODE_ADD_ST 0xb000 | |
679 | #define T_OPCODE_SUB_ST 0xb080 | |
680 | #define T_OPCODE_ADD_SP 0xa800 | |
681 | #define T_OPCODE_ADD_PC 0xa000 | |
682 | #define T_OPCODE_ADD_I8 0x3000 | |
683 | #define T_OPCODE_SUB_I8 0x3800 | |
684 | #define T_OPCODE_ADD_I3 0x1c00 | |
685 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 686 | |
a737bd4d NC |
687 | #define T_OPCODE_ASR_R 0x4100 |
688 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
689 | #define T_OPCODE_LSR_R 0x40c0 |
690 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
691 | #define T_OPCODE_ASR_I 0x1000 |
692 | #define T_OPCODE_LSL_I 0x0000 | |
693 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 694 | |
a737bd4d NC |
695 | #define T_OPCODE_MOV_I8 0x2000 |
696 | #define T_OPCODE_CMP_I8 0x2800 | |
697 | #define T_OPCODE_CMP_LR 0x4280 | |
698 | #define T_OPCODE_MOV_HR 0x4600 | |
699 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 700 | |
a737bd4d NC |
701 | #define T_OPCODE_LDR_PC 0x4800 |
702 | #define T_OPCODE_LDR_SP 0x9800 | |
703 | #define T_OPCODE_STR_SP 0x9000 | |
704 | #define T_OPCODE_LDR_IW 0x6800 | |
705 | #define T_OPCODE_STR_IW 0x6000 | |
706 | #define T_OPCODE_LDR_IH 0x8800 | |
707 | #define T_OPCODE_STR_IH 0x8000 | |
708 | #define T_OPCODE_LDR_IB 0x7800 | |
709 | #define T_OPCODE_STR_IB 0x7000 | |
710 | #define T_OPCODE_LDR_RW 0x5800 | |
711 | #define T_OPCODE_STR_RW 0x5000 | |
712 | #define T_OPCODE_LDR_RH 0x5a00 | |
713 | #define T_OPCODE_STR_RH 0x5200 | |
714 | #define T_OPCODE_LDR_RB 0x5c00 | |
715 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 716 | |
a737bd4d NC |
717 | #define T_OPCODE_PUSH 0xb400 |
718 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 719 | |
2fc8bdac | 720 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 721 | |
a737bd4d | 722 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 723 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 724 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 725 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
726 | |
727 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 728 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
729 | #define BAD_PC _("r15 not allowed here") |
730 | #define BAD_COND _("instruction cannot be conditional") | |
731 | #define BAD_OVERLAP _("registers may not be the same") | |
732 | #define BAD_HIREG _("lo register required") | |
733 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 734 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
735 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
736 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 737 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
738 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
739 | #define BAD_IT_COND _("incorrect condition in IT block") | |
740 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 741 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
742 | #define BAD_PC_ADDRESSING \ |
743 | _("cannot use register index with PC-relative addressing") | |
744 | #define BAD_PC_WRITEBACK \ | |
745 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 746 | #define BAD_RANGE _("branch out of range") |
c19d1205 | 747 | |
c921be7d NC |
748 | static struct hash_control * arm_ops_hsh; |
749 | static struct hash_control * arm_cond_hsh; | |
750 | static struct hash_control * arm_shift_hsh; | |
751 | static struct hash_control * arm_psr_hsh; | |
752 | static struct hash_control * arm_v7m_psr_hsh; | |
753 | static struct hash_control * arm_reg_hsh; | |
754 | static struct hash_control * arm_reloc_hsh; | |
755 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 756 | |
b99bd4ef NC |
757 | /* Stuff needed to resolve the label ambiguity |
758 | As: | |
759 | ... | |
760 | label: <insn> | |
761 | may differ from: | |
762 | ... | |
763 | label: | |
5f4273c7 | 764 | <insn> */ |
b99bd4ef NC |
765 | |
766 | symbolS * last_label_seen; | |
b34976b6 | 767 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 768 | |
3d0c9500 NC |
769 | /* Literal pool structure. Held on a per-section |
770 | and per-sub-section basis. */ | |
a737bd4d | 771 | |
c19d1205 | 772 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 773 | typedef struct literal_pool |
b99bd4ef | 774 | { |
c921be7d NC |
775 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
776 | unsigned int next_free_entry; | |
777 | unsigned int id; | |
778 | symbolS * symbol; | |
779 | segT section; | |
780 | subsegT sub_section; | |
a8040cf2 NC |
781 | #ifdef OBJ_ELF |
782 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
783 | #endif | |
c921be7d | 784 | struct literal_pool * next; |
3d0c9500 | 785 | } literal_pool; |
b99bd4ef | 786 | |
3d0c9500 NC |
787 | /* Pointer to a linked list of literal pools. */ |
788 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 789 | |
e07e6e58 NC |
790 | #ifdef OBJ_ELF |
791 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
792 | #else | |
793 | static struct current_it now_it; | |
794 | #endif | |
795 | ||
796 | static inline int | |
797 | now_it_compatible (int cond) | |
798 | { | |
799 | return (cond & ~1) == (now_it.cc & ~1); | |
800 | } | |
801 | ||
802 | static inline int | |
803 | conditional_insn (void) | |
804 | { | |
805 | return inst.cond != COND_ALWAYS; | |
806 | } | |
807 | ||
808 | static int in_it_block (void); | |
809 | ||
810 | static int handle_it_state (void); | |
811 | ||
812 | static void force_automatic_it_block_close (void); | |
813 | ||
c921be7d NC |
814 | static void it_fsm_post_encode (void); |
815 | ||
e07e6e58 NC |
816 | #define set_it_insn_type(type) \ |
817 | do \ | |
818 | { \ | |
819 | inst.it_insn_type = type; \ | |
820 | if (handle_it_state () == FAIL) \ | |
821 | return; \ | |
822 | } \ | |
823 | while (0) | |
824 | ||
c921be7d NC |
825 | #define set_it_insn_type_nonvoid(type, failret) \ |
826 | do \ | |
827 | { \ | |
828 | inst.it_insn_type = type; \ | |
829 | if (handle_it_state () == FAIL) \ | |
830 | return failret; \ | |
831 | } \ | |
832 | while(0) | |
833 | ||
e07e6e58 NC |
834 | #define set_it_insn_type_last() \ |
835 | do \ | |
836 | { \ | |
837 | if (inst.cond == COND_ALWAYS) \ | |
838 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
839 | else \ | |
840 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
841 | } \ | |
842 | while (0) | |
843 | ||
c19d1205 | 844 | /* Pure syntax. */ |
b99bd4ef | 845 | |
c19d1205 ZW |
846 | /* This array holds the chars that always start a comment. If the |
847 | pre-processor is disabled, these aren't very useful. */ | |
848 | const char comment_chars[] = "@"; | |
3d0c9500 | 849 | |
c19d1205 ZW |
850 | /* This array holds the chars that only start a comment at the beginning of |
851 | a line. If the line seems to have the form '# 123 filename' | |
852 | .line and .file directives will appear in the pre-processed output. */ | |
853 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
854 | first line of the input file. This is because the compiler outputs | |
855 | #NO_APP at the beginning of its output. */ | |
856 | /* Also note that comments like this one will always work. */ | |
857 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 858 | |
c19d1205 | 859 | const char line_separator_chars[] = ";"; |
b99bd4ef | 860 | |
c19d1205 ZW |
861 | /* Chars that can be used to separate mant |
862 | from exp in floating point numbers. */ | |
863 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 864 | |
c19d1205 ZW |
865 | /* Chars that mean this number is a floating point constant. */ |
866 | /* As in 0f12.456 */ | |
867 | /* or 0d1.2345e12 */ | |
b99bd4ef | 868 | |
c19d1205 | 869 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 870 | |
c19d1205 ZW |
871 | /* Prefix characters that indicate the start of an immediate |
872 | value. */ | |
873 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 874 | |
c19d1205 ZW |
875 | /* Separator character handling. */ |
876 | ||
877 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
878 | ||
879 | static inline int | |
880 | skip_past_char (char ** str, char c) | |
881 | { | |
882 | if (**str == c) | |
883 | { | |
884 | (*str)++; | |
885 | return SUCCESS; | |
3d0c9500 | 886 | } |
c19d1205 ZW |
887 | else |
888 | return FAIL; | |
889 | } | |
c921be7d | 890 | |
c19d1205 | 891 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 892 | |
c19d1205 ZW |
893 | /* Arithmetic expressions (possibly involving symbols). */ |
894 | ||
895 | /* Return TRUE if anything in the expression is a bignum. */ | |
896 | ||
897 | static int | |
898 | walk_no_bignums (symbolS * sp) | |
899 | { | |
900 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
901 | return 1; | |
902 | ||
903 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 904 | { |
c19d1205 ZW |
905 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
906 | || (symbol_get_value_expression (sp)->X_op_symbol | |
907 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
908 | } |
909 | ||
c19d1205 | 910 | return 0; |
3d0c9500 NC |
911 | } |
912 | ||
c19d1205 ZW |
913 | static int in_my_get_expression = 0; |
914 | ||
915 | /* Third argument to my_get_expression. */ | |
916 | #define GE_NO_PREFIX 0 | |
917 | #define GE_IMM_PREFIX 1 | |
918 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
919 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
920 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
921 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 922 | |
b99bd4ef | 923 | static int |
c19d1205 | 924 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 925 | { |
c19d1205 ZW |
926 | char * save_in; |
927 | segT seg; | |
b99bd4ef | 928 | |
c19d1205 ZW |
929 | /* In unified syntax, all prefixes are optional. */ |
930 | if (unified_syntax) | |
5287ad62 JB |
931 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
932 | : GE_OPT_PREFIX; | |
b99bd4ef | 933 | |
c19d1205 | 934 | switch (prefix_mode) |
b99bd4ef | 935 | { |
c19d1205 ZW |
936 | case GE_NO_PREFIX: break; |
937 | case GE_IMM_PREFIX: | |
938 | if (!is_immediate_prefix (**str)) | |
939 | { | |
940 | inst.error = _("immediate expression requires a # prefix"); | |
941 | return FAIL; | |
942 | } | |
943 | (*str)++; | |
944 | break; | |
945 | case GE_OPT_PREFIX: | |
5287ad62 | 946 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
947 | if (is_immediate_prefix (**str)) |
948 | (*str)++; | |
949 | break; | |
950 | default: abort (); | |
951 | } | |
b99bd4ef | 952 | |
c19d1205 | 953 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 954 | |
c19d1205 ZW |
955 | save_in = input_line_pointer; |
956 | input_line_pointer = *str; | |
957 | in_my_get_expression = 1; | |
958 | seg = expression (ep); | |
959 | in_my_get_expression = 0; | |
960 | ||
f86adc07 | 961 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 962 | { |
f86adc07 | 963 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
964 | *str = input_line_pointer; |
965 | input_line_pointer = save_in; | |
966 | if (inst.error == NULL) | |
f86adc07 NS |
967 | inst.error = (ep->X_op == O_absent |
968 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
969 | return 1; |
970 | } | |
b99bd4ef | 971 | |
c19d1205 ZW |
972 | #ifdef OBJ_AOUT |
973 | if (seg != absolute_section | |
974 | && seg != text_section | |
975 | && seg != data_section | |
976 | && seg != bss_section | |
977 | && seg != undefined_section) | |
978 | { | |
979 | inst.error = _("bad segment"); | |
980 | *str = input_line_pointer; | |
981 | input_line_pointer = save_in; | |
982 | return 1; | |
b99bd4ef | 983 | } |
87975d2a AM |
984 | #else |
985 | (void) seg; | |
c19d1205 | 986 | #endif |
b99bd4ef | 987 | |
c19d1205 ZW |
988 | /* Get rid of any bignums now, so that we don't generate an error for which |
989 | we can't establish a line number later on. Big numbers are never valid | |
990 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
991 | if (prefix_mode != GE_OPT_PREFIX_BIG |
992 | && (ep->X_op == O_big | |
993 | || (ep->X_add_symbol | |
994 | && (walk_no_bignums (ep->X_add_symbol) | |
995 | || (ep->X_op_symbol | |
996 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
997 | { |
998 | inst.error = _("invalid constant"); | |
999 | *str = input_line_pointer; | |
1000 | input_line_pointer = save_in; | |
1001 | return 1; | |
1002 | } | |
b99bd4ef | 1003 | |
c19d1205 ZW |
1004 | *str = input_line_pointer; |
1005 | input_line_pointer = save_in; | |
1006 | return 0; | |
b99bd4ef NC |
1007 | } |
1008 | ||
c19d1205 ZW |
1009 | /* Turn a string in input_line_pointer into a floating point constant |
1010 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1011 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1012 | returned, or NULL on OK. | |
b99bd4ef | 1013 | |
c19d1205 ZW |
1014 | Note that fp constants aren't represent in the normal way on the ARM. |
1015 | In big endian mode, things are as expected. However, in little endian | |
1016 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1017 | within the words. For example, (double) 1.1 in big endian mode is | |
1018 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1019 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1020 | |
c19d1205 | 1021 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1022 | |
c19d1205 ZW |
1023 | char * |
1024 | md_atof (int type, char * litP, int * sizeP) | |
1025 | { | |
1026 | int prec; | |
1027 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1028 | char *t; | |
1029 | int i; | |
b99bd4ef | 1030 | |
c19d1205 ZW |
1031 | switch (type) |
1032 | { | |
1033 | case 'f': | |
1034 | case 'F': | |
1035 | case 's': | |
1036 | case 'S': | |
1037 | prec = 2; | |
1038 | break; | |
b99bd4ef | 1039 | |
c19d1205 ZW |
1040 | case 'd': |
1041 | case 'D': | |
1042 | case 'r': | |
1043 | case 'R': | |
1044 | prec = 4; | |
1045 | break; | |
b99bd4ef | 1046 | |
c19d1205 ZW |
1047 | case 'x': |
1048 | case 'X': | |
499ac353 | 1049 | prec = 5; |
c19d1205 | 1050 | break; |
b99bd4ef | 1051 | |
c19d1205 ZW |
1052 | case 'p': |
1053 | case 'P': | |
499ac353 | 1054 | prec = 5; |
c19d1205 | 1055 | break; |
a737bd4d | 1056 | |
c19d1205 ZW |
1057 | default: |
1058 | *sizeP = 0; | |
499ac353 | 1059 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1060 | } |
b99bd4ef | 1061 | |
c19d1205 ZW |
1062 | t = atof_ieee (input_line_pointer, type, words); |
1063 | if (t) | |
1064 | input_line_pointer = t; | |
499ac353 | 1065 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1066 | |
c19d1205 ZW |
1067 | if (target_big_endian) |
1068 | { | |
1069 | for (i = 0; i < prec; i++) | |
1070 | { | |
499ac353 NC |
1071 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1072 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1073 | } |
1074 | } | |
1075 | else | |
1076 | { | |
e74cfd16 | 1077 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1078 | for (i = prec - 1; i >= 0; i--) |
1079 | { | |
499ac353 NC |
1080 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1081 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1082 | } |
1083 | else | |
1084 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1085 | For an 8 byte float the order is 1 0 3 2. */ | |
1086 | for (i = 0; i < prec; i += 2) | |
1087 | { | |
499ac353 NC |
1088 | md_number_to_chars (litP, (valueT) words[i + 1], |
1089 | sizeof (LITTLENUM_TYPE)); | |
1090 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1091 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1092 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1093 | } |
1094 | } | |
b99bd4ef | 1095 | |
499ac353 | 1096 | return NULL; |
c19d1205 | 1097 | } |
b99bd4ef | 1098 | |
c19d1205 ZW |
1099 | /* We handle all bad expressions here, so that we can report the faulty |
1100 | instruction in the error message. */ | |
1101 | void | |
91d6fa6a | 1102 | md_operand (expressionS * exp) |
c19d1205 ZW |
1103 | { |
1104 | if (in_my_get_expression) | |
91d6fa6a | 1105 | exp->X_op = O_illegal; |
b99bd4ef NC |
1106 | } |
1107 | ||
c19d1205 | 1108 | /* Immediate values. */ |
b99bd4ef | 1109 | |
c19d1205 ZW |
1110 | /* Generic immediate-value read function for use in directives. |
1111 | Accepts anything that 'expression' can fold to a constant. | |
1112 | *val receives the number. */ | |
1113 | #ifdef OBJ_ELF | |
1114 | static int | |
1115 | immediate_for_directive (int *val) | |
b99bd4ef | 1116 | { |
c19d1205 ZW |
1117 | expressionS exp; |
1118 | exp.X_op = O_illegal; | |
b99bd4ef | 1119 | |
c19d1205 ZW |
1120 | if (is_immediate_prefix (*input_line_pointer)) |
1121 | { | |
1122 | input_line_pointer++; | |
1123 | expression (&exp); | |
1124 | } | |
b99bd4ef | 1125 | |
c19d1205 ZW |
1126 | if (exp.X_op != O_constant) |
1127 | { | |
1128 | as_bad (_("expected #constant")); | |
1129 | ignore_rest_of_line (); | |
1130 | return FAIL; | |
1131 | } | |
1132 | *val = exp.X_add_number; | |
1133 | return SUCCESS; | |
b99bd4ef | 1134 | } |
c19d1205 | 1135 | #endif |
b99bd4ef | 1136 | |
c19d1205 | 1137 | /* Register parsing. */ |
b99bd4ef | 1138 | |
c19d1205 ZW |
1139 | /* Generic register parser. CCP points to what should be the |
1140 | beginning of a register name. If it is indeed a valid register | |
1141 | name, advance CCP over it and return the reg_entry structure; | |
1142 | otherwise return NULL. Does not issue diagnostics. */ | |
1143 | ||
1144 | static struct reg_entry * | |
1145 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1146 | { |
c19d1205 ZW |
1147 | char *start = *ccp; |
1148 | char *p; | |
1149 | struct reg_entry *reg; | |
b99bd4ef | 1150 | |
c19d1205 ZW |
1151 | #ifdef REGISTER_PREFIX |
1152 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1153 | return NULL; |
c19d1205 ZW |
1154 | start++; |
1155 | #endif | |
1156 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1157 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1158 | start++; | |
1159 | #endif | |
b99bd4ef | 1160 | |
c19d1205 ZW |
1161 | p = start; |
1162 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1163 | return NULL; | |
b99bd4ef | 1164 | |
c19d1205 ZW |
1165 | do |
1166 | p++; | |
1167 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1168 | ||
1169 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1170 | ||
1171 | if (!reg) | |
1172 | return NULL; | |
1173 | ||
1174 | *ccp = p; | |
1175 | return reg; | |
b99bd4ef NC |
1176 | } |
1177 | ||
1178 | static int | |
dcbf9037 JB |
1179 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1180 | enum arm_reg_type type) | |
b99bd4ef | 1181 | { |
c19d1205 ZW |
1182 | /* Alternative syntaxes are accepted for a few register classes. */ |
1183 | switch (type) | |
1184 | { | |
1185 | case REG_TYPE_MVF: | |
1186 | case REG_TYPE_MVD: | |
1187 | case REG_TYPE_MVFX: | |
1188 | case REG_TYPE_MVDX: | |
1189 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1190 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1191 | return reg->number; |
1192 | break; | |
69b97547 | 1193 | |
c19d1205 ZW |
1194 | case REG_TYPE_CP: |
1195 | /* For backward compatibility, a bare number is valid here. */ | |
1196 | { | |
1197 | unsigned long processor = strtoul (start, ccp, 10); | |
1198 | if (*ccp != start && processor <= 15) | |
1199 | return processor; | |
1200 | } | |
6057a28f | 1201 | |
c19d1205 ZW |
1202 | case REG_TYPE_MMXWC: |
1203 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1204 | instructions that take WC registers. */ | |
79134647 | 1205 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1206 | return reg->number; |
6057a28f | 1207 | break; |
c19d1205 | 1208 | |
6057a28f | 1209 | default: |
c19d1205 | 1210 | break; |
6057a28f NC |
1211 | } |
1212 | ||
dcbf9037 JB |
1213 | return FAIL; |
1214 | } | |
1215 | ||
1216 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1217 | return value is the register number or FAIL. */ | |
1218 | ||
1219 | static int | |
1220 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1221 | { | |
1222 | char *start = *ccp; | |
1223 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1224 | int ret; | |
1225 | ||
1226 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1227 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1228 | return FAIL; | |
1229 | ||
1230 | if (reg && reg->type == type) | |
1231 | return reg->number; | |
1232 | ||
1233 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1234 | return ret; | |
1235 | ||
c19d1205 ZW |
1236 | *ccp = start; |
1237 | return FAIL; | |
1238 | } | |
69b97547 | 1239 | |
dcbf9037 JB |
1240 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1241 | character. Does no verification at this stage that the type fits the opcode | |
1242 | properly. E.g., | |
1243 | ||
1244 | .i32.i32.s16 | |
1245 | .s32.f32 | |
1246 | .u16 | |
1247 | ||
1248 | Can all be legally parsed by this function. | |
1249 | ||
1250 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1251 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1252 | type, FAIL if not. */ | |
1253 | ||
1254 | static int | |
1255 | parse_neon_type (struct neon_type *type, char **str) | |
1256 | { | |
1257 | char *ptr = *str; | |
1258 | ||
1259 | if (type) | |
1260 | type->elems = 0; | |
1261 | ||
1262 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1263 | { | |
1264 | enum neon_el_type thistype = NT_untyped; | |
1265 | unsigned thissize = -1u; | |
1266 | ||
1267 | if (*ptr != '.') | |
1268 | break; | |
1269 | ||
1270 | ptr++; | |
1271 | ||
1272 | /* Just a size without an explicit type. */ | |
1273 | if (ISDIGIT (*ptr)) | |
1274 | goto parsesize; | |
1275 | ||
1276 | switch (TOLOWER (*ptr)) | |
1277 | { | |
1278 | case 'i': thistype = NT_integer; break; | |
1279 | case 'f': thistype = NT_float; break; | |
1280 | case 'p': thistype = NT_poly; break; | |
1281 | case 's': thistype = NT_signed; break; | |
1282 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1283 | case 'd': |
1284 | thistype = NT_float; | |
1285 | thissize = 64; | |
1286 | ptr++; | |
1287 | goto done; | |
dcbf9037 JB |
1288 | default: |
1289 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1290 | return FAIL; | |
1291 | } | |
1292 | ||
1293 | ptr++; | |
1294 | ||
1295 | /* .f is an abbreviation for .f32. */ | |
1296 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1297 | thissize = 32; | |
1298 | else | |
1299 | { | |
1300 | parsesize: | |
1301 | thissize = strtoul (ptr, &ptr, 10); | |
1302 | ||
1303 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1304 | && thissize != 64) | |
1305 | { | |
1306 | as_bad (_("bad size %d in type specifier"), thissize); | |
1307 | return FAIL; | |
1308 | } | |
1309 | } | |
1310 | ||
037e8744 | 1311 | done: |
dcbf9037 JB |
1312 | if (type) |
1313 | { | |
1314 | type->el[type->elems].type = thistype; | |
1315 | type->el[type->elems].size = thissize; | |
1316 | type->elems++; | |
1317 | } | |
1318 | } | |
1319 | ||
1320 | /* Empty/missing type is not a successful parse. */ | |
1321 | if (type->elems == 0) | |
1322 | return FAIL; | |
1323 | ||
1324 | *str = ptr; | |
1325 | ||
1326 | return SUCCESS; | |
1327 | } | |
1328 | ||
1329 | /* Errors may be set multiple times during parsing or bit encoding | |
1330 | (particularly in the Neon bits), but usually the earliest error which is set | |
1331 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1332 | errors by calling this function. */ | |
1333 | ||
1334 | static void | |
1335 | first_error (const char *err) | |
1336 | { | |
1337 | if (!inst.error) | |
1338 | inst.error = err; | |
1339 | } | |
1340 | ||
1341 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1342 | static int | |
1343 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1344 | { | |
1345 | char *str = *ccp; | |
1346 | struct neon_type optype; | |
1347 | ||
1348 | if (*str == '.') | |
1349 | { | |
1350 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1351 | { | |
1352 | if (optype.elems == 1) | |
1353 | *vectype = optype.el[0]; | |
1354 | else | |
1355 | { | |
1356 | first_error (_("only one type should be specified for operand")); | |
1357 | return FAIL; | |
1358 | } | |
1359 | } | |
1360 | else | |
1361 | { | |
1362 | first_error (_("vector type expected")); | |
1363 | return FAIL; | |
1364 | } | |
1365 | } | |
1366 | else | |
1367 | return FAIL; | |
5f4273c7 | 1368 | |
dcbf9037 | 1369 | *ccp = str; |
5f4273c7 | 1370 | |
dcbf9037 JB |
1371 | return SUCCESS; |
1372 | } | |
1373 | ||
1374 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1375 | a 4-bit integer. */ | |
1376 | ||
1377 | #define NEON_ALL_LANES 15 | |
1378 | #define NEON_INTERLEAVE_LANES 14 | |
1379 | ||
1380 | /* Parse either a register or a scalar, with an optional type. Return the | |
1381 | register number, and optionally fill in the actual type of the register | |
1382 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1383 | type/index information in *TYPEINFO. */ | |
1384 | ||
1385 | static int | |
1386 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1387 | enum arm_reg_type *rtype, | |
1388 | struct neon_typed_alias *typeinfo) | |
1389 | { | |
1390 | char *str = *ccp; | |
1391 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1392 | struct neon_typed_alias atype; | |
1393 | struct neon_type_el parsetype; | |
1394 | ||
1395 | atype.defined = 0; | |
1396 | atype.index = -1; | |
1397 | atype.eltype.type = NT_invtype; | |
1398 | atype.eltype.size = -1; | |
1399 | ||
1400 | /* Try alternate syntax for some types of register. Note these are mutually | |
1401 | exclusive with the Neon syntax extensions. */ | |
1402 | if (reg == NULL) | |
1403 | { | |
1404 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1405 | if (altreg != FAIL) | |
1406 | *ccp = str; | |
1407 | if (typeinfo) | |
1408 | *typeinfo = atype; | |
1409 | return altreg; | |
1410 | } | |
1411 | ||
037e8744 JB |
1412 | /* Undo polymorphism when a set of register types may be accepted. */ |
1413 | if ((type == REG_TYPE_NDQ | |
1414 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1415 | || (type == REG_TYPE_VFSD | |
1416 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1417 | || (type == REG_TYPE_NSDQ | |
1418 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1419 | || reg->type == REG_TYPE_NQ)) |
1420 | || (type == REG_TYPE_MMXWC | |
1421 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1422 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1423 | |
1424 | if (type != reg->type) | |
1425 | return FAIL; | |
1426 | ||
1427 | if (reg->neon) | |
1428 | atype = *reg->neon; | |
5f4273c7 | 1429 | |
dcbf9037 JB |
1430 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1431 | { | |
1432 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1433 | { | |
1434 | first_error (_("can't redefine type for operand")); | |
1435 | return FAIL; | |
1436 | } | |
1437 | atype.defined |= NTA_HASTYPE; | |
1438 | atype.eltype = parsetype; | |
1439 | } | |
5f4273c7 | 1440 | |
dcbf9037 JB |
1441 | if (skip_past_char (&str, '[') == SUCCESS) |
1442 | { | |
1443 | if (type != REG_TYPE_VFD) | |
1444 | { | |
1445 | first_error (_("only D registers may be indexed")); | |
1446 | return FAIL; | |
1447 | } | |
5f4273c7 | 1448 | |
dcbf9037 JB |
1449 | if ((atype.defined & NTA_HASINDEX) != 0) |
1450 | { | |
1451 | first_error (_("can't change index for operand")); | |
1452 | return FAIL; | |
1453 | } | |
1454 | ||
1455 | atype.defined |= NTA_HASINDEX; | |
1456 | ||
1457 | if (skip_past_char (&str, ']') == SUCCESS) | |
1458 | atype.index = NEON_ALL_LANES; | |
1459 | else | |
1460 | { | |
1461 | expressionS exp; | |
1462 | ||
1463 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1464 | ||
1465 | if (exp.X_op != O_constant) | |
1466 | { | |
1467 | first_error (_("constant expression required")); | |
1468 | return FAIL; | |
1469 | } | |
1470 | ||
1471 | if (skip_past_char (&str, ']') == FAIL) | |
1472 | return FAIL; | |
1473 | ||
1474 | atype.index = exp.X_add_number; | |
1475 | } | |
1476 | } | |
5f4273c7 | 1477 | |
dcbf9037 JB |
1478 | if (typeinfo) |
1479 | *typeinfo = atype; | |
5f4273c7 | 1480 | |
dcbf9037 JB |
1481 | if (rtype) |
1482 | *rtype = type; | |
5f4273c7 | 1483 | |
dcbf9037 | 1484 | *ccp = str; |
5f4273c7 | 1485 | |
dcbf9037 JB |
1486 | return reg->number; |
1487 | } | |
1488 | ||
1489 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1490 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1491 | register (e.g. Neon double or quad reg when either has been requested). | |
1492 | - If this is a Neon vector type with additional type information, fill | |
1493 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1494 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1495 | |
1496 | static int | |
1497 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1498 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1499 | { | |
1500 | struct neon_typed_alias atype; | |
1501 | char *str = *ccp; | |
1502 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1503 | ||
1504 | if (reg == FAIL) | |
1505 | return FAIL; | |
1506 | ||
0855e32b NS |
1507 | /* Do not allow regname(... to parse as a register. */ |
1508 | if (*str == '(') | |
1509 | return FAIL; | |
1510 | ||
dcbf9037 JB |
1511 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1512 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1513 | { | |
1514 | first_error (_("register operand expected, but got scalar")); | |
1515 | return FAIL; | |
1516 | } | |
1517 | ||
1518 | if (vectype) | |
1519 | *vectype = atype.eltype; | |
1520 | ||
1521 | *ccp = str; | |
1522 | ||
1523 | return reg; | |
1524 | } | |
1525 | ||
1526 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1527 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1528 | ||
5287ad62 JB |
1529 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1530 | have enough information to be able to do a good job bounds-checking. So, we | |
1531 | just do easy checks here, and do further checks later. */ | |
1532 | ||
1533 | static int | |
dcbf9037 | 1534 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1535 | { |
dcbf9037 | 1536 | int reg; |
5287ad62 | 1537 | char *str = *ccp; |
dcbf9037 | 1538 | struct neon_typed_alias atype; |
5f4273c7 | 1539 | |
dcbf9037 | 1540 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1541 | |
dcbf9037 | 1542 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1543 | return FAIL; |
5f4273c7 | 1544 | |
dcbf9037 | 1545 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1546 | { |
dcbf9037 | 1547 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1548 | return FAIL; |
1549 | } | |
dcbf9037 | 1550 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1551 | { |
dcbf9037 | 1552 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1553 | return FAIL; |
1554 | } | |
5f4273c7 | 1555 | |
dcbf9037 JB |
1556 | if (type) |
1557 | *type = atype.eltype; | |
5f4273c7 | 1558 | |
5287ad62 | 1559 | *ccp = str; |
5f4273c7 | 1560 | |
dcbf9037 | 1561 | return reg * 16 + atype.index; |
5287ad62 JB |
1562 | } |
1563 | ||
c19d1205 | 1564 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1565 | |
c19d1205 ZW |
1566 | static long |
1567 | parse_reg_list (char ** strp) | |
1568 | { | |
1569 | char * str = * strp; | |
1570 | long range = 0; | |
1571 | int another_range; | |
a737bd4d | 1572 | |
c19d1205 ZW |
1573 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1574 | do | |
6057a28f | 1575 | { |
c19d1205 | 1576 | another_range = 0; |
a737bd4d | 1577 | |
c19d1205 ZW |
1578 | if (*str == '{') |
1579 | { | |
1580 | int in_range = 0; | |
1581 | int cur_reg = -1; | |
a737bd4d | 1582 | |
c19d1205 ZW |
1583 | str++; |
1584 | do | |
1585 | { | |
1586 | int reg; | |
6057a28f | 1587 | |
dcbf9037 | 1588 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1589 | { |
dcbf9037 | 1590 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1591 | return FAIL; |
1592 | } | |
a737bd4d | 1593 | |
c19d1205 ZW |
1594 | if (in_range) |
1595 | { | |
1596 | int i; | |
a737bd4d | 1597 | |
c19d1205 ZW |
1598 | if (reg <= cur_reg) |
1599 | { | |
dcbf9037 | 1600 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1601 | return FAIL; |
1602 | } | |
40a18ebd | 1603 | |
c19d1205 ZW |
1604 | for (i = cur_reg + 1; i < reg; i++) |
1605 | { | |
1606 | if (range & (1 << i)) | |
1607 | as_tsktsk | |
1608 | (_("Warning: duplicated register (r%d) in register list"), | |
1609 | i); | |
1610 | else | |
1611 | range |= 1 << i; | |
1612 | } | |
1613 | in_range = 0; | |
1614 | } | |
a737bd4d | 1615 | |
c19d1205 ZW |
1616 | if (range & (1 << reg)) |
1617 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1618 | reg); | |
1619 | else if (reg <= cur_reg) | |
1620 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1621 | |
c19d1205 ZW |
1622 | range |= 1 << reg; |
1623 | cur_reg = reg; | |
1624 | } | |
1625 | while (skip_past_comma (&str) != FAIL | |
1626 | || (in_range = 1, *str++ == '-')); | |
1627 | str--; | |
a737bd4d | 1628 | |
c19d1205 ZW |
1629 | if (*str++ != '}') |
1630 | { | |
dcbf9037 | 1631 | first_error (_("missing `}'")); |
c19d1205 ZW |
1632 | return FAIL; |
1633 | } | |
1634 | } | |
1635 | else | |
1636 | { | |
91d6fa6a | 1637 | expressionS exp; |
40a18ebd | 1638 | |
91d6fa6a | 1639 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1640 | return FAIL; |
40a18ebd | 1641 | |
91d6fa6a | 1642 | if (exp.X_op == O_constant) |
c19d1205 | 1643 | { |
91d6fa6a NC |
1644 | if (exp.X_add_number |
1645 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1646 | { |
1647 | inst.error = _("invalid register mask"); | |
1648 | return FAIL; | |
1649 | } | |
a737bd4d | 1650 | |
91d6fa6a | 1651 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1652 | { |
91d6fa6a | 1653 | int regno = range & exp.X_add_number; |
a737bd4d | 1654 | |
c19d1205 ZW |
1655 | regno &= -regno; |
1656 | regno = (1 << regno) - 1; | |
1657 | as_tsktsk | |
1658 | (_("Warning: duplicated register (r%d) in register list"), | |
1659 | regno); | |
1660 | } | |
a737bd4d | 1661 | |
91d6fa6a | 1662 | range |= exp.X_add_number; |
c19d1205 ZW |
1663 | } |
1664 | else | |
1665 | { | |
1666 | if (inst.reloc.type != 0) | |
1667 | { | |
1668 | inst.error = _("expression too complex"); | |
1669 | return FAIL; | |
1670 | } | |
a737bd4d | 1671 | |
91d6fa6a | 1672 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1673 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1674 | inst.reloc.pc_rel = 0; | |
1675 | } | |
1676 | } | |
a737bd4d | 1677 | |
c19d1205 ZW |
1678 | if (*str == '|' || *str == '+') |
1679 | { | |
1680 | str++; | |
1681 | another_range = 1; | |
1682 | } | |
a737bd4d | 1683 | } |
c19d1205 | 1684 | while (another_range); |
a737bd4d | 1685 | |
c19d1205 ZW |
1686 | *strp = str; |
1687 | return range; | |
a737bd4d NC |
1688 | } |
1689 | ||
5287ad62 JB |
1690 | /* Types of registers in a list. */ |
1691 | ||
1692 | enum reg_list_els | |
1693 | { | |
1694 | REGLIST_VFP_S, | |
1695 | REGLIST_VFP_D, | |
1696 | REGLIST_NEON_D | |
1697 | }; | |
1698 | ||
c19d1205 ZW |
1699 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1700 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1701 | register. Parses registers of type ETYPE. |
1702 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1703 | - Q registers can be used to specify pairs of D registers | |
1704 | - { } can be omitted from around a singleton register list | |
1705 | FIXME: This is not implemented, as it would require backtracking in | |
1706 | some cases, e.g.: | |
1707 | vtbl.8 d3,d4,d5 | |
1708 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1709 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1710 | - 32 D registers may be used (also true for VFPv3). |
1711 | FIXME: Types are ignored in these register lists, which is probably a | |
1712 | bug. */ | |
6057a28f | 1713 | |
c19d1205 | 1714 | static int |
037e8744 | 1715 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1716 | { |
037e8744 | 1717 | char *str = *ccp; |
c19d1205 ZW |
1718 | int base_reg; |
1719 | int new_base; | |
21d799b5 | 1720 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1721 | int max_regs = 0; |
c19d1205 ZW |
1722 | int count = 0; |
1723 | int warned = 0; | |
1724 | unsigned long mask = 0; | |
a737bd4d | 1725 | int i; |
6057a28f | 1726 | |
037e8744 | 1727 | if (*str != '{') |
5287ad62 JB |
1728 | { |
1729 | inst.error = _("expecting {"); | |
1730 | return FAIL; | |
1731 | } | |
6057a28f | 1732 | |
037e8744 | 1733 | str++; |
6057a28f | 1734 | |
5287ad62 | 1735 | switch (etype) |
c19d1205 | 1736 | { |
5287ad62 | 1737 | case REGLIST_VFP_S: |
c19d1205 ZW |
1738 | regtype = REG_TYPE_VFS; |
1739 | max_regs = 32; | |
5287ad62 | 1740 | break; |
5f4273c7 | 1741 | |
5287ad62 JB |
1742 | case REGLIST_VFP_D: |
1743 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1744 | break; |
5f4273c7 | 1745 | |
b7fc2769 JB |
1746 | case REGLIST_NEON_D: |
1747 | regtype = REG_TYPE_NDQ; | |
1748 | break; | |
1749 | } | |
1750 | ||
1751 | if (etype != REGLIST_VFP_S) | |
1752 | { | |
b1cc4aeb PB |
1753 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1754 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1755 | { |
1756 | max_regs = 32; | |
1757 | if (thumb_mode) | |
1758 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1759 | fpu_vfp_ext_d32); |
5287ad62 JB |
1760 | else |
1761 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1762 | fpu_vfp_ext_d32); |
5287ad62 JB |
1763 | } |
1764 | else | |
1765 | max_regs = 16; | |
c19d1205 | 1766 | } |
6057a28f | 1767 | |
c19d1205 | 1768 | base_reg = max_regs; |
a737bd4d | 1769 | |
c19d1205 ZW |
1770 | do |
1771 | { | |
5287ad62 | 1772 | int setmask = 1, addregs = 1; |
dcbf9037 | 1773 | |
037e8744 | 1774 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1775 | |
c19d1205 | 1776 | if (new_base == FAIL) |
a737bd4d | 1777 | { |
dcbf9037 | 1778 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1779 | return FAIL; |
1780 | } | |
5f4273c7 | 1781 | |
b7fc2769 JB |
1782 | if (new_base >= max_regs) |
1783 | { | |
1784 | first_error (_("register out of range in list")); | |
1785 | return FAIL; | |
1786 | } | |
5f4273c7 | 1787 | |
5287ad62 JB |
1788 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1789 | if (regtype == REG_TYPE_NQ) | |
1790 | { | |
1791 | setmask = 3; | |
1792 | addregs = 2; | |
1793 | } | |
1794 | ||
c19d1205 ZW |
1795 | if (new_base < base_reg) |
1796 | base_reg = new_base; | |
a737bd4d | 1797 | |
5287ad62 | 1798 | if (mask & (setmask << new_base)) |
c19d1205 | 1799 | { |
dcbf9037 | 1800 | first_error (_("invalid register list")); |
c19d1205 | 1801 | return FAIL; |
a737bd4d | 1802 | } |
a737bd4d | 1803 | |
c19d1205 ZW |
1804 | if ((mask >> new_base) != 0 && ! warned) |
1805 | { | |
1806 | as_tsktsk (_("register list not in ascending order")); | |
1807 | warned = 1; | |
1808 | } | |
0bbf2aa4 | 1809 | |
5287ad62 JB |
1810 | mask |= setmask << new_base; |
1811 | count += addregs; | |
0bbf2aa4 | 1812 | |
037e8744 | 1813 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1814 | { |
1815 | int high_range; | |
0bbf2aa4 | 1816 | |
037e8744 | 1817 | str++; |
0bbf2aa4 | 1818 | |
037e8744 | 1819 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1820 | == FAIL) |
c19d1205 ZW |
1821 | { |
1822 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1823 | return FAIL; | |
1824 | } | |
0bbf2aa4 | 1825 | |
b7fc2769 JB |
1826 | if (high_range >= max_regs) |
1827 | { | |
1828 | first_error (_("register out of range in list")); | |
1829 | return FAIL; | |
1830 | } | |
1831 | ||
5287ad62 JB |
1832 | if (regtype == REG_TYPE_NQ) |
1833 | high_range = high_range + 1; | |
1834 | ||
c19d1205 ZW |
1835 | if (high_range <= new_base) |
1836 | { | |
1837 | inst.error = _("register range not in ascending order"); | |
1838 | return FAIL; | |
1839 | } | |
0bbf2aa4 | 1840 | |
5287ad62 | 1841 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1842 | { |
5287ad62 | 1843 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1844 | { |
c19d1205 ZW |
1845 | inst.error = _("invalid register list"); |
1846 | return FAIL; | |
0bbf2aa4 | 1847 | } |
c19d1205 | 1848 | |
5287ad62 JB |
1849 | mask |= setmask << new_base; |
1850 | count += addregs; | |
0bbf2aa4 | 1851 | } |
0bbf2aa4 | 1852 | } |
0bbf2aa4 | 1853 | } |
037e8744 | 1854 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1855 | |
037e8744 | 1856 | str++; |
0bbf2aa4 | 1857 | |
c19d1205 ZW |
1858 | /* Sanity check -- should have raised a parse error above. */ |
1859 | if (count == 0 || count > max_regs) | |
1860 | abort (); | |
1861 | ||
1862 | *pbase = base_reg; | |
1863 | ||
1864 | /* Final test -- the registers must be consecutive. */ | |
1865 | mask >>= base_reg; | |
1866 | for (i = 0; i < count; i++) | |
1867 | { | |
1868 | if ((mask & (1u << i)) == 0) | |
1869 | { | |
1870 | inst.error = _("non-contiguous register range"); | |
1871 | return FAIL; | |
1872 | } | |
1873 | } | |
1874 | ||
037e8744 JB |
1875 | *ccp = str; |
1876 | ||
c19d1205 | 1877 | return count; |
b99bd4ef NC |
1878 | } |
1879 | ||
dcbf9037 JB |
1880 | /* True if two alias types are the same. */ |
1881 | ||
c921be7d | 1882 | static bfd_boolean |
dcbf9037 JB |
1883 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1884 | { | |
1885 | if (!a && !b) | |
c921be7d | 1886 | return TRUE; |
5f4273c7 | 1887 | |
dcbf9037 | 1888 | if (!a || !b) |
c921be7d | 1889 | return FALSE; |
dcbf9037 JB |
1890 | |
1891 | if (a->defined != b->defined) | |
c921be7d | 1892 | return FALSE; |
5f4273c7 | 1893 | |
dcbf9037 JB |
1894 | if ((a->defined & NTA_HASTYPE) != 0 |
1895 | && (a->eltype.type != b->eltype.type | |
1896 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1897 | return FALSE; |
dcbf9037 JB |
1898 | |
1899 | if ((a->defined & NTA_HASINDEX) != 0 | |
1900 | && (a->index != b->index)) | |
c921be7d | 1901 | return FALSE; |
5f4273c7 | 1902 | |
c921be7d | 1903 | return TRUE; |
dcbf9037 JB |
1904 | } |
1905 | ||
5287ad62 JB |
1906 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1907 | The base register is put in *PBASE. | |
dcbf9037 | 1908 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1909 | the return value. |
1910 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1911 | Bits [6:5] encode the list length (minus one). |
1912 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1913 | |
5287ad62 | 1914 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1915 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1916 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1917 | ||
1918 | static int | |
dcbf9037 JB |
1919 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1920 | struct neon_type_el *eltype) | |
5287ad62 JB |
1921 | { |
1922 | char *ptr = *str; | |
1923 | int base_reg = -1; | |
1924 | int reg_incr = -1; | |
1925 | int count = 0; | |
1926 | int lane = -1; | |
1927 | int leading_brace = 0; | |
1928 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1929 | const char *const incr_error = _("register stride must be 1 or 2"); |
1930 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1931 | struct neon_typed_alias firsttype; |
5f4273c7 | 1932 | |
5287ad62 JB |
1933 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1934 | leading_brace = 1; | |
5f4273c7 | 1935 | |
5287ad62 JB |
1936 | do |
1937 | { | |
dcbf9037 JB |
1938 | struct neon_typed_alias atype; |
1939 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1940 | ||
5287ad62 JB |
1941 | if (getreg == FAIL) |
1942 | { | |
dcbf9037 | 1943 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1944 | return FAIL; |
1945 | } | |
5f4273c7 | 1946 | |
5287ad62 JB |
1947 | if (base_reg == -1) |
1948 | { | |
1949 | base_reg = getreg; | |
1950 | if (rtype == REG_TYPE_NQ) | |
1951 | { | |
1952 | reg_incr = 1; | |
5287ad62 | 1953 | } |
dcbf9037 | 1954 | firsttype = atype; |
5287ad62 JB |
1955 | } |
1956 | else if (reg_incr == -1) | |
1957 | { | |
1958 | reg_incr = getreg - base_reg; | |
1959 | if (reg_incr < 1 || reg_incr > 2) | |
1960 | { | |
dcbf9037 | 1961 | first_error (_(incr_error)); |
5287ad62 JB |
1962 | return FAIL; |
1963 | } | |
1964 | } | |
1965 | else if (getreg != base_reg + reg_incr * count) | |
1966 | { | |
dcbf9037 JB |
1967 | first_error (_(incr_error)); |
1968 | return FAIL; | |
1969 | } | |
1970 | ||
c921be7d | 1971 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1972 | { |
1973 | first_error (_(type_error)); | |
5287ad62 JB |
1974 | return FAIL; |
1975 | } | |
5f4273c7 | 1976 | |
5287ad62 JB |
1977 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1978 | modes. */ | |
1979 | if (ptr[0] == '-') | |
1980 | { | |
dcbf9037 | 1981 | struct neon_typed_alias htype; |
5287ad62 JB |
1982 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1983 | if (lane == -1) | |
1984 | lane = NEON_INTERLEAVE_LANES; | |
1985 | else if (lane != NEON_INTERLEAVE_LANES) | |
1986 | { | |
dcbf9037 | 1987 | first_error (_(type_error)); |
5287ad62 JB |
1988 | return FAIL; |
1989 | } | |
1990 | if (reg_incr == -1) | |
1991 | reg_incr = 1; | |
1992 | else if (reg_incr != 1) | |
1993 | { | |
dcbf9037 | 1994 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1995 | return FAIL; |
1996 | } | |
1997 | ptr++; | |
dcbf9037 | 1998 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1999 | if (hireg == FAIL) |
2000 | { | |
dcbf9037 JB |
2001 | first_error (_(reg_expected_msgs[rtype])); |
2002 | return FAIL; | |
2003 | } | |
c921be7d | 2004 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
2005 | { |
2006 | first_error (_(type_error)); | |
5287ad62 JB |
2007 | return FAIL; |
2008 | } | |
2009 | count += hireg + dregs - getreg; | |
2010 | continue; | |
2011 | } | |
5f4273c7 | 2012 | |
5287ad62 JB |
2013 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
2014 | if (rtype == REG_TYPE_NQ) | |
2015 | { | |
2016 | count += 2; | |
2017 | continue; | |
2018 | } | |
5f4273c7 | 2019 | |
dcbf9037 | 2020 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 2021 | { |
dcbf9037 JB |
2022 | if (lane == -1) |
2023 | lane = atype.index; | |
2024 | else if (lane != atype.index) | |
5287ad62 | 2025 | { |
dcbf9037 JB |
2026 | first_error (_(type_error)); |
2027 | return FAIL; | |
5287ad62 JB |
2028 | } |
2029 | } | |
2030 | else if (lane == -1) | |
2031 | lane = NEON_INTERLEAVE_LANES; | |
2032 | else if (lane != NEON_INTERLEAVE_LANES) | |
2033 | { | |
dcbf9037 | 2034 | first_error (_(type_error)); |
5287ad62 JB |
2035 | return FAIL; |
2036 | } | |
2037 | count++; | |
2038 | } | |
2039 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2040 | |
5287ad62 JB |
2041 | /* No lane set by [x]. We must be interleaving structures. */ |
2042 | if (lane == -1) | |
2043 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2044 | |
5287ad62 JB |
2045 | /* Sanity check. */ |
2046 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2047 | || (count > 1 && reg_incr == -1)) | |
2048 | { | |
dcbf9037 | 2049 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2050 | return FAIL; |
2051 | } | |
2052 | ||
2053 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2054 | { | |
dcbf9037 | 2055 | first_error (_("expected }")); |
5287ad62 JB |
2056 | return FAIL; |
2057 | } | |
5f4273c7 | 2058 | |
5287ad62 JB |
2059 | if (reg_incr == -1) |
2060 | reg_incr = 1; | |
2061 | ||
dcbf9037 JB |
2062 | if (eltype) |
2063 | *eltype = firsttype.eltype; | |
2064 | ||
5287ad62 JB |
2065 | *pbase = base_reg; |
2066 | *str = ptr; | |
5f4273c7 | 2067 | |
5287ad62 JB |
2068 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2069 | } | |
2070 | ||
c19d1205 ZW |
2071 | /* Parse an explicit relocation suffix on an expression. This is |
2072 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2073 | arm_reloc_hsh contains no entries, so this function can only | |
2074 | succeed if there is no () after the word. Returns -1 on error, | |
2075 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2076 | |
c19d1205 ZW |
2077 | static int |
2078 | parse_reloc (char **str) | |
b99bd4ef | 2079 | { |
c19d1205 ZW |
2080 | struct reloc_entry *r; |
2081 | char *p, *q; | |
b99bd4ef | 2082 | |
c19d1205 ZW |
2083 | if (**str != '(') |
2084 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2085 | |
c19d1205 ZW |
2086 | p = *str + 1; |
2087 | q = p; | |
2088 | ||
2089 | while (*q && *q != ')' && *q != ',') | |
2090 | q++; | |
2091 | if (*q != ')') | |
2092 | return -1; | |
2093 | ||
21d799b5 NC |
2094 | if ((r = (struct reloc_entry *) |
2095 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2096 | return -1; |
2097 | ||
2098 | *str = q + 1; | |
2099 | return r->reloc; | |
b99bd4ef NC |
2100 | } |
2101 | ||
c19d1205 ZW |
2102 | /* Directives: register aliases. */ |
2103 | ||
dcbf9037 | 2104 | static struct reg_entry * |
90ec0d68 | 2105 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2106 | { |
d3ce72d0 | 2107 | struct reg_entry *new_reg; |
c19d1205 | 2108 | const char *name; |
b99bd4ef | 2109 | |
d3ce72d0 | 2110 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2111 | { |
d3ce72d0 | 2112 | if (new_reg->builtin) |
c19d1205 | 2113 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2114 | |
c19d1205 ZW |
2115 | /* Only warn about a redefinition if it's not defined as the |
2116 | same register. */ | |
d3ce72d0 | 2117 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2118 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2119 | |
d929913e | 2120 | return NULL; |
c19d1205 | 2121 | } |
b99bd4ef | 2122 | |
c19d1205 | 2123 | name = xstrdup (str); |
d3ce72d0 | 2124 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2125 | |
d3ce72d0 NC |
2126 | new_reg->name = name; |
2127 | new_reg->number = number; | |
2128 | new_reg->type = type; | |
2129 | new_reg->builtin = FALSE; | |
2130 | new_reg->neon = NULL; | |
b99bd4ef | 2131 | |
d3ce72d0 | 2132 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2133 | abort (); |
5f4273c7 | 2134 | |
d3ce72d0 | 2135 | return new_reg; |
dcbf9037 JB |
2136 | } |
2137 | ||
2138 | static void | |
2139 | insert_neon_reg_alias (char *str, int number, int type, | |
2140 | struct neon_typed_alias *atype) | |
2141 | { | |
2142 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2143 | |
dcbf9037 JB |
2144 | if (!reg) |
2145 | { | |
2146 | first_error (_("attempt to redefine typed alias")); | |
2147 | return; | |
2148 | } | |
5f4273c7 | 2149 | |
dcbf9037 JB |
2150 | if (atype) |
2151 | { | |
21d799b5 NC |
2152 | reg->neon = (struct neon_typed_alias *) |
2153 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2154 | *reg->neon = *atype; |
2155 | } | |
c19d1205 | 2156 | } |
b99bd4ef | 2157 | |
c19d1205 | 2158 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2159 | |
c19d1205 | 2160 | new_register_name .req existing_register_name |
b99bd4ef | 2161 | |
c19d1205 | 2162 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2163 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2164 | |
d929913e | 2165 | static bfd_boolean |
c19d1205 ZW |
2166 | create_register_alias (char * newname, char *p) |
2167 | { | |
2168 | struct reg_entry *old; | |
2169 | char *oldname, *nbuf; | |
2170 | size_t nlen; | |
b99bd4ef | 2171 | |
c19d1205 ZW |
2172 | /* The input scrubber ensures that whitespace after the mnemonic is |
2173 | collapsed to single spaces. */ | |
2174 | oldname = p; | |
2175 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2176 | return FALSE; |
b99bd4ef | 2177 | |
c19d1205 ZW |
2178 | oldname += 6; |
2179 | if (*oldname == '\0') | |
d929913e | 2180 | return FALSE; |
b99bd4ef | 2181 | |
21d799b5 | 2182 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2183 | if (!old) |
b99bd4ef | 2184 | { |
c19d1205 | 2185 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2186 | return TRUE; |
b99bd4ef NC |
2187 | } |
2188 | ||
c19d1205 ZW |
2189 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2190 | the desired alias name, and p points to its end. If not, then | |
2191 | the desired alias name is in the global original_case_string. */ | |
2192 | #ifdef TC_CASE_SENSITIVE | |
2193 | nlen = p - newname; | |
2194 | #else | |
2195 | newname = original_case_string; | |
2196 | nlen = strlen (newname); | |
2197 | #endif | |
b99bd4ef | 2198 | |
21d799b5 | 2199 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2200 | memcpy (nbuf, newname, nlen); |
2201 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2202 | |
c19d1205 ZW |
2203 | /* Create aliases under the new name as stated; an all-lowercase |
2204 | version of the new name; and an all-uppercase version of the new | |
2205 | name. */ | |
d929913e NC |
2206 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2207 | { | |
2208 | for (p = nbuf; *p; p++) | |
2209 | *p = TOUPPER (*p); | |
c19d1205 | 2210 | |
d929913e NC |
2211 | if (strncmp (nbuf, newname, nlen)) |
2212 | { | |
2213 | /* If this attempt to create an additional alias fails, do not bother | |
2214 | trying to create the all-lower case alias. We will fail and issue | |
2215 | a second, duplicate error message. This situation arises when the | |
2216 | programmer does something like: | |
2217 | foo .req r0 | |
2218 | Foo .req r1 | |
2219 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2220 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2221 | first .req. */ |
2222 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2223 | return TRUE; | |
2224 | } | |
c19d1205 | 2225 | |
d929913e NC |
2226 | for (p = nbuf; *p; p++) |
2227 | *p = TOLOWER (*p); | |
c19d1205 | 2228 | |
d929913e NC |
2229 | if (strncmp (nbuf, newname, nlen)) |
2230 | insert_reg_alias (nbuf, old->number, old->type); | |
2231 | } | |
c19d1205 | 2232 | |
d929913e | 2233 | return TRUE; |
b99bd4ef NC |
2234 | } |
2235 | ||
dcbf9037 JB |
2236 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2237 | X .dn d5.s32[1] | |
2238 | Y .qn 6.s16 | |
2239 | Z .dn d7 | |
2240 | T .dn Z[0] | |
2241 | These typed registers can be used instead of the types specified after the | |
2242 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2243 | specified directly, e.g.: | |
5f4273c7 | 2244 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2245 | |
c921be7d | 2246 | static bfd_boolean |
dcbf9037 JB |
2247 | create_neon_reg_alias (char *newname, char *p) |
2248 | { | |
2249 | enum arm_reg_type basetype; | |
2250 | struct reg_entry *basereg; | |
2251 | struct reg_entry mybasereg; | |
2252 | struct neon_type ntype; | |
2253 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2254 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2255 | int namelen; |
5f4273c7 | 2256 | |
dcbf9037 JB |
2257 | typeinfo.defined = 0; |
2258 | typeinfo.eltype.type = NT_invtype; | |
2259 | typeinfo.eltype.size = -1; | |
2260 | typeinfo.index = -1; | |
5f4273c7 | 2261 | |
dcbf9037 | 2262 | nameend = p; |
5f4273c7 | 2263 | |
dcbf9037 JB |
2264 | if (strncmp (p, " .dn ", 5) == 0) |
2265 | basetype = REG_TYPE_VFD; | |
2266 | else if (strncmp (p, " .qn ", 5) == 0) | |
2267 | basetype = REG_TYPE_NQ; | |
2268 | else | |
c921be7d | 2269 | return FALSE; |
5f4273c7 | 2270 | |
dcbf9037 | 2271 | p += 5; |
5f4273c7 | 2272 | |
dcbf9037 | 2273 | if (*p == '\0') |
c921be7d | 2274 | return FALSE; |
5f4273c7 | 2275 | |
dcbf9037 JB |
2276 | basereg = arm_reg_parse_multi (&p); |
2277 | ||
2278 | if (basereg && basereg->type != basetype) | |
2279 | { | |
2280 | as_bad (_("bad type for register")); | |
c921be7d | 2281 | return FALSE; |
dcbf9037 JB |
2282 | } |
2283 | ||
2284 | if (basereg == NULL) | |
2285 | { | |
2286 | expressionS exp; | |
2287 | /* Try parsing as an integer. */ | |
2288 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2289 | if (exp.X_op != O_constant) | |
2290 | { | |
2291 | as_bad (_("expression must be constant")); | |
c921be7d | 2292 | return FALSE; |
dcbf9037 JB |
2293 | } |
2294 | basereg = &mybasereg; | |
2295 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2296 | : exp.X_add_number; | |
2297 | basereg->neon = 0; | |
2298 | } | |
2299 | ||
2300 | if (basereg->neon) | |
2301 | typeinfo = *basereg->neon; | |
2302 | ||
2303 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2304 | { | |
2305 | /* We got a type. */ | |
2306 | if (typeinfo.defined & NTA_HASTYPE) | |
2307 | { | |
2308 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2309 | return FALSE; |
dcbf9037 | 2310 | } |
5f4273c7 | 2311 | |
dcbf9037 JB |
2312 | typeinfo.defined |= NTA_HASTYPE; |
2313 | if (ntype.elems != 1) | |
2314 | { | |
2315 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2316 | return FALSE; |
dcbf9037 JB |
2317 | } |
2318 | typeinfo.eltype = ntype.el[0]; | |
2319 | } | |
5f4273c7 | 2320 | |
dcbf9037 JB |
2321 | if (skip_past_char (&p, '[') == SUCCESS) |
2322 | { | |
2323 | expressionS exp; | |
2324 | /* We got a scalar index. */ | |
5f4273c7 | 2325 | |
dcbf9037 JB |
2326 | if (typeinfo.defined & NTA_HASINDEX) |
2327 | { | |
2328 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2329 | return FALSE; |
dcbf9037 | 2330 | } |
5f4273c7 | 2331 | |
dcbf9037 | 2332 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2333 | |
dcbf9037 JB |
2334 | if (exp.X_op != O_constant) |
2335 | { | |
2336 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2337 | return FALSE; |
dcbf9037 | 2338 | } |
5f4273c7 | 2339 | |
dcbf9037 JB |
2340 | typeinfo.defined |= NTA_HASINDEX; |
2341 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2342 | |
dcbf9037 JB |
2343 | if (skip_past_char (&p, ']') == FAIL) |
2344 | { | |
2345 | as_bad (_("expecting ]")); | |
c921be7d | 2346 | return FALSE; |
dcbf9037 JB |
2347 | } |
2348 | } | |
2349 | ||
15735687 NS |
2350 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2351 | the desired alias name, and p points to its end. If not, then | |
2352 | the desired alias name is in the global original_case_string. */ | |
2353 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2354 | namelen = nameend - newname; |
15735687 NS |
2355 | #else |
2356 | newname = original_case_string; | |
2357 | namelen = strlen (newname); | |
2358 | #endif | |
2359 | ||
21d799b5 | 2360 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2361 | strncpy (namebuf, newname, namelen); |
2362 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2363 | |
dcbf9037 JB |
2364 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2365 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2366 | |
dcbf9037 JB |
2367 | /* Insert name in all uppercase. */ |
2368 | for (p = namebuf; *p; p++) | |
2369 | *p = TOUPPER (*p); | |
5f4273c7 | 2370 | |
dcbf9037 JB |
2371 | if (strncmp (namebuf, newname, namelen)) |
2372 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2373 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2374 | |
dcbf9037 JB |
2375 | /* Insert name in all lowercase. */ |
2376 | for (p = namebuf; *p; p++) | |
2377 | *p = TOLOWER (*p); | |
5f4273c7 | 2378 | |
dcbf9037 JB |
2379 | if (strncmp (namebuf, newname, namelen)) |
2380 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2381 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2382 | |
c921be7d | 2383 | return TRUE; |
dcbf9037 JB |
2384 | } |
2385 | ||
c19d1205 ZW |
2386 | /* Should never be called, as .req goes between the alias and the |
2387 | register name, not at the beginning of the line. */ | |
c921be7d | 2388 | |
b99bd4ef | 2389 | static void |
c19d1205 | 2390 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2391 | { |
c19d1205 ZW |
2392 | as_bad (_("invalid syntax for .req directive")); |
2393 | } | |
b99bd4ef | 2394 | |
dcbf9037 JB |
2395 | static void |
2396 | s_dn (int a ATTRIBUTE_UNUSED) | |
2397 | { | |
2398 | as_bad (_("invalid syntax for .dn directive")); | |
2399 | } | |
2400 | ||
2401 | static void | |
2402 | s_qn (int a ATTRIBUTE_UNUSED) | |
2403 | { | |
2404 | as_bad (_("invalid syntax for .qn directive")); | |
2405 | } | |
2406 | ||
c19d1205 ZW |
2407 | /* The .unreq directive deletes an alias which was previously defined |
2408 | by .req. For example: | |
b99bd4ef | 2409 | |
c19d1205 ZW |
2410 | my_alias .req r11 |
2411 | .unreq my_alias */ | |
b99bd4ef NC |
2412 | |
2413 | static void | |
c19d1205 | 2414 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2415 | { |
c19d1205 ZW |
2416 | char * name; |
2417 | char saved_char; | |
b99bd4ef | 2418 | |
c19d1205 ZW |
2419 | name = input_line_pointer; |
2420 | ||
2421 | while (*input_line_pointer != 0 | |
2422 | && *input_line_pointer != ' ' | |
2423 | && *input_line_pointer != '\n') | |
2424 | ++input_line_pointer; | |
2425 | ||
2426 | saved_char = *input_line_pointer; | |
2427 | *input_line_pointer = 0; | |
2428 | ||
2429 | if (!*name) | |
2430 | as_bad (_("invalid syntax for .unreq directive")); | |
2431 | else | |
2432 | { | |
21d799b5 NC |
2433 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2434 | name); | |
c19d1205 ZW |
2435 | |
2436 | if (!reg) | |
2437 | as_bad (_("unknown register alias '%s'"), name); | |
2438 | else if (reg->builtin) | |
a1727c1a | 2439 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2440 | name); |
2441 | else | |
2442 | { | |
d929913e NC |
2443 | char * p; |
2444 | char * nbuf; | |
2445 | ||
db0bc284 | 2446 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2447 | free ((char *) reg->name); |
dcbf9037 JB |
2448 | if (reg->neon) |
2449 | free (reg->neon); | |
c19d1205 | 2450 | free (reg); |
d929913e NC |
2451 | |
2452 | /* Also locate the all upper case and all lower case versions. | |
2453 | Do not complain if we cannot find one or the other as it | |
2454 | was probably deleted above. */ | |
5f4273c7 | 2455 | |
d929913e NC |
2456 | nbuf = strdup (name); |
2457 | for (p = nbuf; *p; p++) | |
2458 | *p = TOUPPER (*p); | |
21d799b5 | 2459 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2460 | if (reg) |
2461 | { | |
db0bc284 | 2462 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2463 | free ((char *) reg->name); |
2464 | if (reg->neon) | |
2465 | free (reg->neon); | |
2466 | free (reg); | |
2467 | } | |
2468 | ||
2469 | for (p = nbuf; *p; p++) | |
2470 | *p = TOLOWER (*p); | |
21d799b5 | 2471 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2472 | if (reg) |
2473 | { | |
db0bc284 | 2474 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2475 | free ((char *) reg->name); |
2476 | if (reg->neon) | |
2477 | free (reg->neon); | |
2478 | free (reg); | |
2479 | } | |
2480 | ||
2481 | free (nbuf); | |
c19d1205 ZW |
2482 | } |
2483 | } | |
b99bd4ef | 2484 | |
c19d1205 | 2485 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2486 | demand_empty_rest_of_line (); |
2487 | } | |
2488 | ||
c19d1205 ZW |
2489 | /* Directives: Instruction set selection. */ |
2490 | ||
2491 | #ifdef OBJ_ELF | |
2492 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2493 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2494 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2495 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2496 | ||
cd000bff DJ |
2497 | /* Create a new mapping symbol for the transition to STATE. */ |
2498 | ||
2499 | static void | |
2500 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2501 | { |
a737bd4d | 2502 | symbolS * symbolP; |
c19d1205 ZW |
2503 | const char * symname; |
2504 | int type; | |
b99bd4ef | 2505 | |
c19d1205 | 2506 | switch (state) |
b99bd4ef | 2507 | { |
c19d1205 ZW |
2508 | case MAP_DATA: |
2509 | symname = "$d"; | |
2510 | type = BSF_NO_FLAGS; | |
2511 | break; | |
2512 | case MAP_ARM: | |
2513 | symname = "$a"; | |
2514 | type = BSF_NO_FLAGS; | |
2515 | break; | |
2516 | case MAP_THUMB: | |
2517 | symname = "$t"; | |
2518 | type = BSF_NO_FLAGS; | |
2519 | break; | |
c19d1205 ZW |
2520 | default: |
2521 | abort (); | |
2522 | } | |
2523 | ||
cd000bff | 2524 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2525 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2526 | ||
2527 | switch (state) | |
2528 | { | |
2529 | case MAP_ARM: | |
2530 | THUMB_SET_FUNC (symbolP, 0); | |
2531 | ARM_SET_THUMB (symbolP, 0); | |
2532 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2533 | break; | |
2534 | ||
2535 | case MAP_THUMB: | |
2536 | THUMB_SET_FUNC (symbolP, 1); | |
2537 | ARM_SET_THUMB (symbolP, 1); | |
2538 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2539 | break; | |
2540 | ||
2541 | case MAP_DATA: | |
2542 | default: | |
cd000bff DJ |
2543 | break; |
2544 | } | |
2545 | ||
2546 | /* Save the mapping symbols for future reference. Also check that | |
2547 | we do not place two mapping symbols at the same offset within a | |
2548 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2549 | check_mapping_symbols. |
2550 | ||
2551 | If .fill or other data filling directive generates zero sized data, | |
2552 | the mapping symbol for the following code will have the same value | |
2553 | as the one generated for the data filling directive. In this case, | |
2554 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2555 | if (value == 0) |
2556 | { | |
2de7820f JZ |
2557 | if (frag->tc_frag_data.first_map != NULL) |
2558 | { | |
2559 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2560 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2561 | } | |
cd000bff DJ |
2562 | frag->tc_frag_data.first_map = symbolP; |
2563 | } | |
2564 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2565 | { |
2566 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2567 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2568 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2569 | } | |
cd000bff DJ |
2570 | frag->tc_frag_data.last_map = symbolP; |
2571 | } | |
2572 | ||
2573 | /* We must sometimes convert a region marked as code to data during | |
2574 | code alignment, if an odd number of bytes have to be padded. The | |
2575 | code mapping symbol is pushed to an aligned address. */ | |
2576 | ||
2577 | static void | |
2578 | insert_data_mapping_symbol (enum mstate state, | |
2579 | valueT value, fragS *frag, offsetT bytes) | |
2580 | { | |
2581 | /* If there was already a mapping symbol, remove it. */ | |
2582 | if (frag->tc_frag_data.last_map != NULL | |
2583 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2584 | { | |
2585 | symbolS *symp = frag->tc_frag_data.last_map; | |
2586 | ||
2587 | if (value == 0) | |
2588 | { | |
2589 | know (frag->tc_frag_data.first_map == symp); | |
2590 | frag->tc_frag_data.first_map = NULL; | |
2591 | } | |
2592 | frag->tc_frag_data.last_map = NULL; | |
2593 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2594 | } |
cd000bff DJ |
2595 | |
2596 | make_mapping_symbol (MAP_DATA, value, frag); | |
2597 | make_mapping_symbol (state, value + bytes, frag); | |
2598 | } | |
2599 | ||
2600 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2601 | ||
2602 | /* Set the mapping state to STATE. Only call this when about to | |
2603 | emit some STATE bytes to the file. */ | |
2604 | ||
2605 | void | |
2606 | mapping_state (enum mstate state) | |
2607 | { | |
940b5ce0 DJ |
2608 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2609 | ||
cd000bff DJ |
2610 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2611 | ||
2612 | if (mapstate == state) | |
2613 | /* The mapping symbol has already been emitted. | |
2614 | There is nothing else to do. */ | |
2615 | return; | |
49c62a33 NC |
2616 | |
2617 | if (state == MAP_ARM || state == MAP_THUMB) | |
2618 | /* PR gas/12931 | |
2619 | All ARM instructions require 4-byte alignment. | |
2620 | (Almost) all Thumb instructions require 2-byte alignment. | |
2621 | ||
2622 | When emitting instructions into any section, mark the section | |
2623 | appropriately. | |
2624 | ||
2625 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2626 | but themselves require 2-byte alignment; this applies to some | |
2627 | PC- relative forms. However, these cases will invovle implicit | |
2628 | literal pool generation or an explicit .align >=2, both of | |
2629 | which will cause the section to me marked with sufficient | |
2630 | alignment. Thus, we don't handle those cases here. */ | |
2631 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2632 | ||
2633 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
cd000bff DJ |
2634 | /* This case will be evaluated later in the next else. */ |
2635 | return; | |
2636 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2637 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2638 | { | |
2639 | /* Only add the symbol if the offset is > 0: | |
2640 | if we're at the first frag, check it's size > 0; | |
2641 | if we're not at the first frag, then for sure | |
2642 | the offset is > 0. */ | |
2643 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2644 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2645 | ||
2646 | if (add_symbol) | |
2647 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2648 | } | |
2649 | ||
2650 | mapping_state_2 (state, 0); | |
2651 | #undef TRANSITION | |
2652 | } | |
2653 | ||
2654 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2655 | allocated. Put the mapping symbol that far back. */ | |
2656 | ||
2657 | static void | |
2658 | mapping_state_2 (enum mstate state, int max_chars) | |
2659 | { | |
940b5ce0 DJ |
2660 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2661 | ||
2662 | if (!SEG_NORMAL (now_seg)) | |
2663 | return; | |
2664 | ||
cd000bff DJ |
2665 | if (mapstate == state) |
2666 | /* The mapping symbol has already been emitted. | |
2667 | There is nothing else to do. */ | |
2668 | return; | |
2669 | ||
cd000bff DJ |
2670 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2671 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2672 | } |
2673 | #else | |
d3106081 NS |
2674 | #define mapping_state(x) ((void)0) |
2675 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2676 | #endif |
2677 | ||
2678 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2679 | ||
4343666d | 2680 | #ifdef OBJ_COFF |
c19d1205 ZW |
2681 | static symbolS * |
2682 | find_real_start (symbolS * symbolP) | |
2683 | { | |
2684 | char * real_start; | |
2685 | const char * name = S_GET_NAME (symbolP); | |
2686 | symbolS * new_target; | |
2687 | ||
2688 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2689 | #define STUB_NAME ".real_start_of" | |
2690 | ||
2691 | if (name == NULL) | |
2692 | abort (); | |
2693 | ||
37f6032b ZW |
2694 | /* The compiler may generate BL instructions to local labels because |
2695 | it needs to perform a branch to a far away location. These labels | |
2696 | do not have a corresponding ".real_start_of" label. We check | |
2697 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2698 | the ".real_start_of" convention for nonlocal branches. */ | |
2699 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2700 | return symbolP; |
2701 | ||
37f6032b | 2702 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2703 | new_target = symbol_find (real_start); |
2704 | ||
2705 | if (new_target == NULL) | |
2706 | { | |
bd3ba5d1 | 2707 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2708 | new_target = symbolP; |
2709 | } | |
2710 | ||
c19d1205 ZW |
2711 | return new_target; |
2712 | } | |
4343666d | 2713 | #endif |
c19d1205 ZW |
2714 | |
2715 | static void | |
2716 | opcode_select (int width) | |
2717 | { | |
2718 | switch (width) | |
2719 | { | |
2720 | case 16: | |
2721 | if (! thumb_mode) | |
2722 | { | |
e74cfd16 | 2723 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2724 | as_bad (_("selected processor does not support THUMB opcodes")); |
2725 | ||
2726 | thumb_mode = 1; | |
2727 | /* No need to force the alignment, since we will have been | |
2728 | coming from ARM mode, which is word-aligned. */ | |
2729 | record_alignment (now_seg, 1); | |
2730 | } | |
c19d1205 ZW |
2731 | break; |
2732 | ||
2733 | case 32: | |
2734 | if (thumb_mode) | |
2735 | { | |
e74cfd16 | 2736 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2737 | as_bad (_("selected processor does not support ARM opcodes")); |
2738 | ||
2739 | thumb_mode = 0; | |
2740 | ||
2741 | if (!need_pass_2) | |
2742 | frag_align (2, 0, 0); | |
2743 | ||
2744 | record_alignment (now_seg, 1); | |
2745 | } | |
c19d1205 ZW |
2746 | break; |
2747 | ||
2748 | default: | |
2749 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2750 | } | |
2751 | } | |
2752 | ||
2753 | static void | |
2754 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2755 | { | |
2756 | opcode_select (32); | |
2757 | demand_empty_rest_of_line (); | |
2758 | } | |
2759 | ||
2760 | static void | |
2761 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2762 | { | |
2763 | opcode_select (16); | |
2764 | demand_empty_rest_of_line (); | |
2765 | } | |
2766 | ||
2767 | static void | |
2768 | s_code (int unused ATTRIBUTE_UNUSED) | |
2769 | { | |
2770 | int temp; | |
2771 | ||
2772 | temp = get_absolute_expression (); | |
2773 | switch (temp) | |
2774 | { | |
2775 | case 16: | |
2776 | case 32: | |
2777 | opcode_select (temp); | |
2778 | break; | |
2779 | ||
2780 | default: | |
2781 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2782 | } | |
2783 | } | |
2784 | ||
2785 | static void | |
2786 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2787 | { | |
2788 | /* If we are not already in thumb mode go into it, EVEN if | |
2789 | the target processor does not support thumb instructions. | |
2790 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2791 | to compile interworking support functions even if the | |
2792 | target processor should not support interworking. */ | |
2793 | if (! thumb_mode) | |
2794 | { | |
2795 | thumb_mode = 2; | |
2796 | record_alignment (now_seg, 1); | |
2797 | } | |
2798 | ||
2799 | demand_empty_rest_of_line (); | |
2800 | } | |
2801 | ||
2802 | static void | |
2803 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2804 | { | |
2805 | s_thumb (0); | |
2806 | ||
2807 | /* The following label is the name/address of the start of a Thumb function. | |
2808 | We need to know this for the interworking support. */ | |
2809 | label_is_thumb_function_name = TRUE; | |
2810 | } | |
2811 | ||
2812 | /* Perform a .set directive, but also mark the alias as | |
2813 | being a thumb function. */ | |
2814 | ||
2815 | static void | |
2816 | s_thumb_set (int equiv) | |
2817 | { | |
2818 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2819 | We cannot just call that code as we need to get at the symbol that | |
2820 | is created. */ | |
2821 | char * name; | |
2822 | char delim; | |
2823 | char * end_name; | |
2824 | symbolS * symbolP; | |
2825 | ||
2826 | /* Especial apologies for the random logic: | |
2827 | This just grew, and could be parsed much more simply! | |
2828 | Dean - in haste. */ | |
2829 | name = input_line_pointer; | |
2830 | delim = get_symbol_end (); | |
2831 | end_name = input_line_pointer; | |
2832 | *end_name = delim; | |
2833 | ||
2834 | if (*input_line_pointer != ',') | |
2835 | { | |
2836 | *end_name = 0; | |
2837 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2838 | *end_name = delim; |
2839 | ignore_rest_of_line (); | |
2840 | return; | |
2841 | } | |
2842 | ||
2843 | input_line_pointer++; | |
2844 | *end_name = 0; | |
2845 | ||
2846 | if (name[0] == '.' && name[1] == '\0') | |
2847 | { | |
2848 | /* XXX - this should not happen to .thumb_set. */ | |
2849 | abort (); | |
2850 | } | |
2851 | ||
2852 | if ((symbolP = symbol_find (name)) == NULL | |
2853 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2854 | { | |
2855 | #ifndef NO_LISTING | |
2856 | /* When doing symbol listings, play games with dummy fragments living | |
2857 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2858 | for this symbol. */ |
b99bd4ef NC |
2859 | if (listing & LISTING_SYMBOLS) |
2860 | { | |
2861 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2862 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2863 | |
2864 | memset (dummy_frag, 0, sizeof (fragS)); | |
2865 | dummy_frag->fr_type = rs_fill; | |
2866 | dummy_frag->line = listing_tail; | |
2867 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2868 | dummy_frag->fr_symbol = symbolP; | |
2869 | } | |
2870 | else | |
2871 | #endif | |
2872 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2873 | ||
2874 | #ifdef OBJ_COFF | |
2875 | /* "set" symbols are local unless otherwise specified. */ | |
2876 | SF_SET_LOCAL (symbolP); | |
2877 | #endif /* OBJ_COFF */ | |
2878 | } /* Make a new symbol. */ | |
2879 | ||
2880 | symbol_table_insert (symbolP); | |
2881 | ||
2882 | * end_name = delim; | |
2883 | ||
2884 | if (equiv | |
2885 | && S_IS_DEFINED (symbolP) | |
2886 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2887 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2888 | ||
2889 | pseudo_set (symbolP); | |
2890 | ||
2891 | demand_empty_rest_of_line (); | |
2892 | ||
c19d1205 | 2893 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2894 | |
2895 | THUMB_SET_FUNC (symbolP, 1); | |
2896 | ARM_SET_THUMB (symbolP, 1); | |
2897 | #if defined OBJ_ELF || defined OBJ_COFF | |
2898 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2899 | #endif | |
2900 | } | |
2901 | ||
c19d1205 | 2902 | /* Directives: Mode selection. */ |
b99bd4ef | 2903 | |
c19d1205 ZW |
2904 | /* .syntax [unified|divided] - choose the new unified syntax |
2905 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2906 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2907 | static void |
c19d1205 | 2908 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2909 | { |
c19d1205 ZW |
2910 | char *name, delim; |
2911 | ||
2912 | name = input_line_pointer; | |
2913 | delim = get_symbol_end (); | |
2914 | ||
2915 | if (!strcasecmp (name, "unified")) | |
2916 | unified_syntax = TRUE; | |
2917 | else if (!strcasecmp (name, "divided")) | |
2918 | unified_syntax = FALSE; | |
2919 | else | |
2920 | { | |
2921 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2922 | return; | |
2923 | } | |
2924 | *input_line_pointer = delim; | |
b99bd4ef NC |
2925 | demand_empty_rest_of_line (); |
2926 | } | |
2927 | ||
c19d1205 ZW |
2928 | /* Directives: sectioning and alignment. */ |
2929 | ||
2930 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2931 | ||
b99bd4ef | 2932 | static void |
c19d1205 | 2933 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2934 | { |
a737bd4d | 2935 | int temp; |
dce323d1 | 2936 | bfd_boolean fill_p; |
c19d1205 ZW |
2937 | long temp_fill; |
2938 | long max_alignment = 15; | |
b99bd4ef NC |
2939 | |
2940 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2941 | if (temp > max_alignment) |
2942 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2943 | else if (temp < 0) | |
b99bd4ef | 2944 | { |
c19d1205 ZW |
2945 | as_bad (_("alignment negative. 0 assumed.")); |
2946 | temp = 0; | |
2947 | } | |
b99bd4ef | 2948 | |
c19d1205 ZW |
2949 | if (*input_line_pointer == ',') |
2950 | { | |
2951 | input_line_pointer++; | |
2952 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2953 | fill_p = TRUE; |
b99bd4ef | 2954 | } |
c19d1205 | 2955 | else |
dce323d1 PB |
2956 | { |
2957 | fill_p = FALSE; | |
2958 | temp_fill = 0; | |
2959 | } | |
b99bd4ef | 2960 | |
c19d1205 ZW |
2961 | if (!temp) |
2962 | temp = 2; | |
b99bd4ef | 2963 | |
c19d1205 ZW |
2964 | /* Only make a frag if we HAVE to. */ |
2965 | if (temp && !need_pass_2) | |
dce323d1 PB |
2966 | { |
2967 | if (!fill_p && subseg_text_p (now_seg)) | |
2968 | frag_align_code (temp, 0); | |
2969 | else | |
2970 | frag_align (temp, (int) temp_fill, 0); | |
2971 | } | |
c19d1205 ZW |
2972 | demand_empty_rest_of_line (); |
2973 | ||
2974 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2975 | } |
2976 | ||
c19d1205 ZW |
2977 | static void |
2978 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2979 | { |
c19d1205 ZW |
2980 | /* We don't support putting frags in the BSS segment, we fake it by |
2981 | marking in_bss, then looking at s_skip for clues. */ | |
2982 | subseg_set (bss_section, 0); | |
2983 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2984 | |
2985 | #ifdef md_elf_section_change_hook | |
2986 | md_elf_section_change_hook (); | |
2987 | #endif | |
c19d1205 | 2988 | } |
b99bd4ef | 2989 | |
c19d1205 ZW |
2990 | static void |
2991 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2992 | { | |
2993 | /* Never make frag if expect extra pass. */ | |
2994 | if (!need_pass_2) | |
2995 | frag_align (1, 0, 0); | |
b99bd4ef | 2996 | |
c19d1205 | 2997 | record_alignment (now_seg, 1); |
b99bd4ef | 2998 | |
c19d1205 | 2999 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3000 | } |
3001 | ||
c19d1205 | 3002 | /* Directives: Literal pools. */ |
a737bd4d | 3003 | |
c19d1205 ZW |
3004 | static literal_pool * |
3005 | find_literal_pool (void) | |
a737bd4d | 3006 | { |
c19d1205 | 3007 | literal_pool * pool; |
a737bd4d | 3008 | |
c19d1205 | 3009 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 3010 | { |
c19d1205 ZW |
3011 | if (pool->section == now_seg |
3012 | && pool->sub_section == now_subseg) | |
3013 | break; | |
a737bd4d NC |
3014 | } |
3015 | ||
c19d1205 | 3016 | return pool; |
a737bd4d NC |
3017 | } |
3018 | ||
c19d1205 ZW |
3019 | static literal_pool * |
3020 | find_or_make_literal_pool (void) | |
a737bd4d | 3021 | { |
c19d1205 ZW |
3022 | /* Next literal pool ID number. */ |
3023 | static unsigned int latest_pool_num = 1; | |
3024 | literal_pool * pool; | |
a737bd4d | 3025 | |
c19d1205 | 3026 | pool = find_literal_pool (); |
a737bd4d | 3027 | |
c19d1205 | 3028 | if (pool == NULL) |
a737bd4d | 3029 | { |
c19d1205 | 3030 | /* Create a new pool. */ |
21d799b5 | 3031 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3032 | if (! pool) |
3033 | return NULL; | |
a737bd4d | 3034 | |
c19d1205 ZW |
3035 | pool->next_free_entry = 0; |
3036 | pool->section = now_seg; | |
3037 | pool->sub_section = now_subseg; | |
3038 | pool->next = list_of_pools; | |
3039 | pool->symbol = NULL; | |
3040 | ||
3041 | /* Add it to the list. */ | |
3042 | list_of_pools = pool; | |
a737bd4d | 3043 | } |
a737bd4d | 3044 | |
c19d1205 ZW |
3045 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3046 | if (pool->symbol == NULL) | |
a737bd4d | 3047 | { |
c19d1205 ZW |
3048 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3049 | (valueT) 0, &zero_address_frag); | |
3050 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3051 | } |
3052 | ||
c19d1205 ZW |
3053 | /* Done. */ |
3054 | return pool; | |
a737bd4d NC |
3055 | } |
3056 | ||
c19d1205 | 3057 | /* Add the literal in the global 'inst' |
5f4273c7 | 3058 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3059 | |
3060 | static int | |
c19d1205 | 3061 | add_to_lit_pool (void) |
b99bd4ef | 3062 | { |
c19d1205 ZW |
3063 | literal_pool * pool; |
3064 | unsigned int entry; | |
b99bd4ef | 3065 | |
c19d1205 ZW |
3066 | pool = find_or_make_literal_pool (); |
3067 | ||
3068 | /* Check if this literal value is already in the pool. */ | |
3069 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3070 | { |
c19d1205 ZW |
3071 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3072 | && (inst.reloc.exp.X_op == O_constant) | |
3073 | && (pool->literals[entry].X_add_number | |
3074 | == inst.reloc.exp.X_add_number) | |
3075 | && (pool->literals[entry].X_unsigned | |
3076 | == inst.reloc.exp.X_unsigned)) | |
3077 | break; | |
3078 | ||
3079 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3080 | && (inst.reloc.exp.X_op == O_symbol) | |
3081 | && (pool->literals[entry].X_add_number | |
3082 | == inst.reloc.exp.X_add_number) | |
3083 | && (pool->literals[entry].X_add_symbol | |
3084 | == inst.reloc.exp.X_add_symbol) | |
3085 | && (pool->literals[entry].X_op_symbol | |
3086 | == inst.reloc.exp.X_op_symbol)) | |
3087 | break; | |
b99bd4ef NC |
3088 | } |
3089 | ||
c19d1205 ZW |
3090 | /* Do we need to create a new entry? */ |
3091 | if (entry == pool->next_free_entry) | |
3092 | { | |
3093 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3094 | { | |
3095 | inst.error = _("literal pool overflow"); | |
3096 | return FAIL; | |
3097 | } | |
3098 | ||
3099 | pool->literals[entry] = inst.reloc.exp; | |
a8040cf2 NC |
3100 | #ifdef OBJ_ELF |
3101 | /* PR ld/12974: Record the location of the first source line to reference | |
3102 | this entry in the literal pool. If it turns out during linking that the | |
3103 | symbol does not exist we will be able to give an accurate line number for | |
3104 | the (first use of the) missing reference. */ | |
3105 | if (debug_type == DEBUG_DWARF2) | |
3106 | dwarf2_where (pool->locs + entry); | |
3107 | #endif | |
c19d1205 ZW |
3108 | pool->next_free_entry += 1; |
3109 | } | |
b99bd4ef | 3110 | |
c19d1205 ZW |
3111 | inst.reloc.exp.X_op = O_symbol; |
3112 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3113 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3114 | |
c19d1205 | 3115 | return SUCCESS; |
b99bd4ef NC |
3116 | } |
3117 | ||
c19d1205 ZW |
3118 | /* Can't use symbol_new here, so have to create a symbol and then at |
3119 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3120 | |
c19d1205 ZW |
3121 | static void |
3122 | symbol_locate (symbolS * symbolP, | |
3123 | const char * name, /* It is copied, the caller can modify. */ | |
3124 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3125 | valueT valu, /* Symbol value. */ | |
3126 | fragS * frag) /* Associated fragment. */ | |
3127 | { | |
3128 | unsigned int name_length; | |
3129 | char * preserved_copy_of_name; | |
e16bb312 | 3130 | |
c19d1205 ZW |
3131 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3132 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3133 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3134 | |
c19d1205 ZW |
3135 | #ifdef tc_canonicalize_symbol_name |
3136 | preserved_copy_of_name = | |
3137 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3138 | #endif | |
b99bd4ef | 3139 | |
c19d1205 | 3140 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3141 | |
c19d1205 ZW |
3142 | S_SET_SEGMENT (symbolP, segment); |
3143 | S_SET_VALUE (symbolP, valu); | |
3144 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3145 | |
c19d1205 | 3146 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3147 | |
c19d1205 ZW |
3148 | /* Link to end of symbol chain. */ |
3149 | { | |
3150 | extern int symbol_table_frozen; | |
b99bd4ef | 3151 | |
c19d1205 ZW |
3152 | if (symbol_table_frozen) |
3153 | abort (); | |
3154 | } | |
b99bd4ef | 3155 | |
c19d1205 | 3156 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3157 | |
c19d1205 | 3158 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3159 | |
c19d1205 ZW |
3160 | #ifdef tc_symbol_new_hook |
3161 | tc_symbol_new_hook (symbolP); | |
3162 | #endif | |
3163 | ||
3164 | #ifdef DEBUG_SYMS | |
3165 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3166 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3167 | } |
3168 | ||
b99bd4ef | 3169 | |
c19d1205 ZW |
3170 | static void |
3171 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3172 | { |
c19d1205 ZW |
3173 | unsigned int entry; |
3174 | literal_pool * pool; | |
3175 | char sym_name[20]; | |
b99bd4ef | 3176 | |
c19d1205 ZW |
3177 | pool = find_literal_pool (); |
3178 | if (pool == NULL | |
3179 | || pool->symbol == NULL | |
3180 | || pool->next_free_entry == 0) | |
3181 | return; | |
b99bd4ef | 3182 | |
c19d1205 | 3183 | mapping_state (MAP_DATA); |
b99bd4ef | 3184 | |
c19d1205 ZW |
3185 | /* Align pool as you have word accesses. |
3186 | Only make a frag if we have to. */ | |
3187 | if (!need_pass_2) | |
3188 | frag_align (2, 0, 0); | |
b99bd4ef | 3189 | |
c19d1205 | 3190 | record_alignment (now_seg, 2); |
b99bd4ef | 3191 | |
c19d1205 | 3192 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3193 | |
c19d1205 ZW |
3194 | symbol_locate (pool->symbol, sym_name, now_seg, |
3195 | (valueT) frag_now_fix (), frag_now); | |
3196 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3197 | |
c19d1205 | 3198 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3199 | |
c19d1205 ZW |
3200 | #if defined OBJ_COFF || defined OBJ_ELF |
3201 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3202 | #endif | |
6c43fab6 | 3203 | |
c19d1205 | 3204 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3205 | { |
3206 | #ifdef OBJ_ELF | |
3207 | if (debug_type == DEBUG_DWARF2) | |
3208 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3209 | #endif | |
3210 | /* First output the expression in the instruction to the pool. */ | |
3211 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
3212 | } | |
b99bd4ef | 3213 | |
c19d1205 ZW |
3214 | /* Mark the pool as empty. */ |
3215 | pool->next_free_entry = 0; | |
3216 | pool->symbol = NULL; | |
b99bd4ef NC |
3217 | } |
3218 | ||
c19d1205 ZW |
3219 | #ifdef OBJ_ELF |
3220 | /* Forward declarations for functions below, in the MD interface | |
3221 | section. */ | |
3222 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3223 | static valueT create_unwind_entry (int); | |
3224 | static void start_unwind_section (const segT, int); | |
3225 | static void add_unwind_opcode (valueT, int); | |
3226 | static void flush_pending_unwind (void); | |
b99bd4ef | 3227 | |
c19d1205 | 3228 | /* Directives: Data. */ |
b99bd4ef | 3229 | |
c19d1205 ZW |
3230 | static void |
3231 | s_arm_elf_cons (int nbytes) | |
3232 | { | |
3233 | expressionS exp; | |
b99bd4ef | 3234 | |
c19d1205 ZW |
3235 | #ifdef md_flush_pending_output |
3236 | md_flush_pending_output (); | |
3237 | #endif | |
b99bd4ef | 3238 | |
c19d1205 | 3239 | if (is_it_end_of_statement ()) |
b99bd4ef | 3240 | { |
c19d1205 ZW |
3241 | demand_empty_rest_of_line (); |
3242 | return; | |
b99bd4ef NC |
3243 | } |
3244 | ||
c19d1205 ZW |
3245 | #ifdef md_cons_align |
3246 | md_cons_align (nbytes); | |
3247 | #endif | |
b99bd4ef | 3248 | |
c19d1205 ZW |
3249 | mapping_state (MAP_DATA); |
3250 | do | |
b99bd4ef | 3251 | { |
c19d1205 ZW |
3252 | int reloc; |
3253 | char *base = input_line_pointer; | |
b99bd4ef | 3254 | |
c19d1205 | 3255 | expression (& exp); |
b99bd4ef | 3256 | |
c19d1205 ZW |
3257 | if (exp.X_op != O_symbol) |
3258 | emit_expr (&exp, (unsigned int) nbytes); | |
3259 | else | |
3260 | { | |
3261 | char *before_reloc = input_line_pointer; | |
3262 | reloc = parse_reloc (&input_line_pointer); | |
3263 | if (reloc == -1) | |
3264 | { | |
3265 | as_bad (_("unrecognized relocation suffix")); | |
3266 | ignore_rest_of_line (); | |
3267 | return; | |
3268 | } | |
3269 | else if (reloc == BFD_RELOC_UNUSED) | |
3270 | emit_expr (&exp, (unsigned int) nbytes); | |
3271 | else | |
3272 | { | |
21d799b5 NC |
3273 | reloc_howto_type *howto = (reloc_howto_type *) |
3274 | bfd_reloc_type_lookup (stdoutput, | |
3275 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3276 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3277 | |
2fc8bdac ZW |
3278 | if (reloc == BFD_RELOC_ARM_PLT32) |
3279 | { | |
3280 | as_bad (_("(plt) is only valid on branch targets")); | |
3281 | reloc = BFD_RELOC_UNUSED; | |
3282 | size = 0; | |
3283 | } | |
3284 | ||
c19d1205 | 3285 | if (size > nbytes) |
2fc8bdac | 3286 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3287 | howto->name, nbytes); |
3288 | else | |
3289 | { | |
3290 | /* We've parsed an expression stopping at O_symbol. | |
3291 | But there may be more expression left now that we | |
3292 | have parsed the relocation marker. Parse it again. | |
3293 | XXX Surely there is a cleaner way to do this. */ | |
3294 | char *p = input_line_pointer; | |
3295 | int offset; | |
21d799b5 | 3296 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3297 | memcpy (save_buf, base, input_line_pointer - base); |
3298 | memmove (base + (input_line_pointer - before_reloc), | |
3299 | base, before_reloc - base); | |
3300 | ||
3301 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3302 | expression (&exp); | |
3303 | memcpy (base, save_buf, p - base); | |
3304 | ||
3305 | offset = nbytes - size; | |
3306 | p = frag_more ((int) nbytes); | |
3307 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3308 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3309 | } |
3310 | } | |
3311 | } | |
b99bd4ef | 3312 | } |
c19d1205 | 3313 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3314 | |
c19d1205 ZW |
3315 | /* Put terminator back into stream. */ |
3316 | input_line_pointer --; | |
3317 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3318 | } |
3319 | ||
c921be7d NC |
3320 | /* Emit an expression containing a 32-bit thumb instruction. |
3321 | Implementation based on put_thumb32_insn. */ | |
3322 | ||
3323 | static void | |
3324 | emit_thumb32_expr (expressionS * exp) | |
3325 | { | |
3326 | expressionS exp_high = *exp; | |
3327 | ||
3328 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3329 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3330 | exp->X_add_number &= 0xffff; | |
3331 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3332 | } | |
3333 | ||
3334 | /* Guess the instruction size based on the opcode. */ | |
3335 | ||
3336 | static int | |
3337 | thumb_insn_size (int opcode) | |
3338 | { | |
3339 | if ((unsigned int) opcode < 0xe800u) | |
3340 | return 2; | |
3341 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3342 | return 4; | |
3343 | else | |
3344 | return 0; | |
3345 | } | |
3346 | ||
3347 | static bfd_boolean | |
3348 | emit_insn (expressionS *exp, int nbytes) | |
3349 | { | |
3350 | int size = 0; | |
3351 | ||
3352 | if (exp->X_op == O_constant) | |
3353 | { | |
3354 | size = nbytes; | |
3355 | ||
3356 | if (size == 0) | |
3357 | size = thumb_insn_size (exp->X_add_number); | |
3358 | ||
3359 | if (size != 0) | |
3360 | { | |
3361 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3362 | { | |
3363 | as_bad (_(".inst.n operand too big. "\ | |
3364 | "Use .inst.w instead")); | |
3365 | size = 0; | |
3366 | } | |
3367 | else | |
3368 | { | |
3369 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3370 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3371 | else | |
3372 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3373 | ||
3374 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3375 | emit_thumb32_expr (exp); | |
3376 | else | |
3377 | emit_expr (exp, (unsigned int) size); | |
3378 | ||
3379 | it_fsm_post_encode (); | |
3380 | } | |
3381 | } | |
3382 | else | |
3383 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3384 | "Use .inst.n/.inst.w instead")); | |
3385 | } | |
3386 | else | |
3387 | as_bad (_("constant expression required")); | |
3388 | ||
3389 | return (size != 0); | |
3390 | } | |
3391 | ||
3392 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3393 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3394 | ||
3395 | static void | |
3396 | s_arm_elf_inst (int nbytes) | |
3397 | { | |
3398 | if (is_it_end_of_statement ()) | |
3399 | { | |
3400 | demand_empty_rest_of_line (); | |
3401 | return; | |
3402 | } | |
3403 | ||
3404 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3405 | but will ensure not to be in DATA state. */ | |
3406 | ||
3407 | if (thumb_mode) | |
3408 | mapping_state (MAP_THUMB); | |
3409 | else | |
3410 | { | |
3411 | if (nbytes != 0) | |
3412 | { | |
3413 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3414 | ignore_rest_of_line (); | |
3415 | return; | |
3416 | } | |
3417 | ||
3418 | nbytes = 4; | |
3419 | ||
3420 | mapping_state (MAP_ARM); | |
3421 | } | |
3422 | ||
3423 | do | |
3424 | { | |
3425 | expressionS exp; | |
3426 | ||
3427 | expression (& exp); | |
3428 | ||
3429 | if (! emit_insn (& exp, nbytes)) | |
3430 | { | |
3431 | ignore_rest_of_line (); | |
3432 | return; | |
3433 | } | |
3434 | } | |
3435 | while (*input_line_pointer++ == ','); | |
3436 | ||
3437 | /* Put terminator back into stream. */ | |
3438 | input_line_pointer --; | |
3439 | demand_empty_rest_of_line (); | |
3440 | } | |
b99bd4ef | 3441 | |
c19d1205 | 3442 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3443 | |
c19d1205 ZW |
3444 | static void |
3445 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3446 | { | |
3447 | expressionS exp; | |
3448 | char *p; | |
3449 | valueT highbit; | |
b99bd4ef | 3450 | |
c19d1205 ZW |
3451 | highbit = 0; |
3452 | if (*input_line_pointer == '1') | |
3453 | highbit = 0x80000000; | |
3454 | else if (*input_line_pointer != '0') | |
3455 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3456 | |
c19d1205 ZW |
3457 | input_line_pointer++; |
3458 | if (*input_line_pointer != ',') | |
3459 | as_bad (_("missing comma")); | |
3460 | input_line_pointer++; | |
b99bd4ef | 3461 | |
c19d1205 ZW |
3462 | #ifdef md_flush_pending_output |
3463 | md_flush_pending_output (); | |
3464 | #endif | |
b99bd4ef | 3465 | |
c19d1205 ZW |
3466 | #ifdef md_cons_align |
3467 | md_cons_align (4); | |
3468 | #endif | |
b99bd4ef | 3469 | |
c19d1205 | 3470 | mapping_state (MAP_DATA); |
b99bd4ef | 3471 | |
c19d1205 | 3472 | expression (&exp); |
b99bd4ef | 3473 | |
c19d1205 ZW |
3474 | p = frag_more (4); |
3475 | md_number_to_chars (p, highbit, 4); | |
3476 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3477 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3478 | |
c19d1205 | 3479 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3480 | } |
3481 | ||
c19d1205 | 3482 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3483 | |
c19d1205 | 3484 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3485 | |
c19d1205 ZW |
3486 | static void |
3487 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3488 | { | |
3489 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3490 | if (unwind.proc_start) |
3491 | { | |
c921be7d | 3492 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3493 | return; |
3494 | } | |
3495 | ||
c19d1205 ZW |
3496 | /* Mark the start of the function. */ |
3497 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3498 | |
c19d1205 ZW |
3499 | /* Reset the rest of the unwind info. */ |
3500 | unwind.opcode_count = 0; | |
3501 | unwind.table_entry = NULL; | |
3502 | unwind.personality_routine = NULL; | |
3503 | unwind.personality_index = -1; | |
3504 | unwind.frame_size = 0; | |
3505 | unwind.fp_offset = 0; | |
fdfde340 | 3506 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3507 | unwind.fp_used = 0; |
3508 | unwind.sp_restored = 0; | |
3509 | } | |
b99bd4ef | 3510 | |
b99bd4ef | 3511 | |
c19d1205 ZW |
3512 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3513 | for the function. */ | |
b99bd4ef | 3514 | |
c19d1205 ZW |
3515 | static void |
3516 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3517 | { | |
3518 | demand_empty_rest_of_line (); | |
921e5f0a | 3519 | if (!unwind.proc_start) |
c921be7d | 3520 | as_bad (MISSING_FNSTART); |
921e5f0a | 3521 | |
c19d1205 | 3522 | if (unwind.table_entry) |
6decc662 | 3523 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3524 | |
c19d1205 ZW |
3525 | create_unwind_entry (1); |
3526 | } | |
a737bd4d | 3527 | |
c19d1205 | 3528 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3529 | |
c19d1205 ZW |
3530 | static void |
3531 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3532 | { | |
3533 | long where; | |
3534 | char *ptr; | |
3535 | valueT val; | |
940b5ce0 | 3536 | unsigned int marked_pr_dependency; |
f02232aa | 3537 | |
c19d1205 | 3538 | demand_empty_rest_of_line (); |
f02232aa | 3539 | |
921e5f0a PB |
3540 | if (!unwind.proc_start) |
3541 | { | |
c921be7d | 3542 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3543 | return; |
3544 | } | |
3545 | ||
c19d1205 ZW |
3546 | /* Add eh table entry. */ |
3547 | if (unwind.table_entry == NULL) | |
3548 | val = create_unwind_entry (0); | |
3549 | else | |
3550 | val = 0; | |
f02232aa | 3551 | |
c19d1205 ZW |
3552 | /* Add index table entry. This is two words. */ |
3553 | start_unwind_section (unwind.saved_seg, 1); | |
3554 | frag_align (2, 0, 0); | |
3555 | record_alignment (now_seg, 2); | |
b99bd4ef | 3556 | |
c19d1205 | 3557 | ptr = frag_more (8); |
5011093d | 3558 | memset (ptr, 0, 8); |
c19d1205 | 3559 | where = frag_now_fix () - 8; |
f02232aa | 3560 | |
c19d1205 ZW |
3561 | /* Self relative offset of the function start. */ |
3562 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3563 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3564 | |
c19d1205 ZW |
3565 | /* Indicate dependency on EHABI-defined personality routines to the |
3566 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3567 | marked_pr_dependency |
3568 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3569 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3570 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3571 | { | |
5f4273c7 NC |
3572 | static const char *const name[] = |
3573 | { | |
3574 | "__aeabi_unwind_cpp_pr0", | |
3575 | "__aeabi_unwind_cpp_pr1", | |
3576 | "__aeabi_unwind_cpp_pr2" | |
3577 | }; | |
c19d1205 ZW |
3578 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3579 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3580 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3581 | |= 1 << unwind.personality_index; |
c19d1205 | 3582 | } |
f02232aa | 3583 | |
c19d1205 ZW |
3584 | if (val) |
3585 | /* Inline exception table entry. */ | |
3586 | md_number_to_chars (ptr + 4, val, 4); | |
3587 | else | |
3588 | /* Self relative offset of the table entry. */ | |
3589 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3590 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3591 | |
c19d1205 ZW |
3592 | /* Restore the original section. */ |
3593 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3594 | |
3595 | unwind.proc_start = NULL; | |
c19d1205 | 3596 | } |
f02232aa | 3597 | |
f02232aa | 3598 | |
c19d1205 | 3599 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3600 | |
c19d1205 ZW |
3601 | static void |
3602 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3603 | { | |
3604 | demand_empty_rest_of_line (); | |
921e5f0a | 3605 | if (!unwind.proc_start) |
c921be7d | 3606 | as_bad (MISSING_FNSTART); |
921e5f0a | 3607 | |
c19d1205 ZW |
3608 | if (unwind.personality_routine || unwind.personality_index != -1) |
3609 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3610 | |
c19d1205 ZW |
3611 | unwind.personality_index = -2; |
3612 | } | |
b99bd4ef | 3613 | |
b99bd4ef | 3614 | |
c19d1205 | 3615 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3616 | |
c19d1205 ZW |
3617 | static void |
3618 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3619 | { | |
3620 | expressionS exp; | |
b99bd4ef | 3621 | |
921e5f0a | 3622 | if (!unwind.proc_start) |
c921be7d | 3623 | as_bad (MISSING_FNSTART); |
921e5f0a | 3624 | |
c19d1205 ZW |
3625 | if (unwind.personality_routine || unwind.personality_index != -1) |
3626 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3627 | |
c19d1205 | 3628 | expression (&exp); |
b99bd4ef | 3629 | |
c19d1205 ZW |
3630 | if (exp.X_op != O_constant |
3631 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3632 | { |
c19d1205 ZW |
3633 | as_bad (_("bad personality routine number")); |
3634 | ignore_rest_of_line (); | |
3635 | return; | |
b99bd4ef NC |
3636 | } |
3637 | ||
c19d1205 | 3638 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3639 | |
c19d1205 ZW |
3640 | demand_empty_rest_of_line (); |
3641 | } | |
e16bb312 | 3642 | |
e16bb312 | 3643 | |
c19d1205 | 3644 | /* Parse a personality directive. */ |
e16bb312 | 3645 | |
c19d1205 ZW |
3646 | static void |
3647 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3648 | { | |
3649 | char *name, *p, c; | |
a737bd4d | 3650 | |
921e5f0a | 3651 | if (!unwind.proc_start) |
c921be7d | 3652 | as_bad (MISSING_FNSTART); |
921e5f0a | 3653 | |
c19d1205 ZW |
3654 | if (unwind.personality_routine || unwind.personality_index != -1) |
3655 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3656 | |
c19d1205 ZW |
3657 | name = input_line_pointer; |
3658 | c = get_symbol_end (); | |
3659 | p = input_line_pointer; | |
3660 | unwind.personality_routine = symbol_find_or_make (name); | |
3661 | *p = c; | |
3662 | demand_empty_rest_of_line (); | |
3663 | } | |
e16bb312 | 3664 | |
e16bb312 | 3665 | |
c19d1205 | 3666 | /* Parse a directive saving core registers. */ |
e16bb312 | 3667 | |
c19d1205 ZW |
3668 | static void |
3669 | s_arm_unwind_save_core (void) | |
e16bb312 | 3670 | { |
c19d1205 ZW |
3671 | valueT op; |
3672 | long range; | |
3673 | int n; | |
e16bb312 | 3674 | |
c19d1205 ZW |
3675 | range = parse_reg_list (&input_line_pointer); |
3676 | if (range == FAIL) | |
e16bb312 | 3677 | { |
c19d1205 ZW |
3678 | as_bad (_("expected register list")); |
3679 | ignore_rest_of_line (); | |
3680 | return; | |
3681 | } | |
e16bb312 | 3682 | |
c19d1205 | 3683 | demand_empty_rest_of_line (); |
e16bb312 | 3684 | |
c19d1205 ZW |
3685 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3686 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3687 | ip because it is clobbered by calls. */ | |
3688 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3689 | && (range & 0x3000) == 0x1000) | |
3690 | { | |
3691 | unwind.opcode_count--; | |
3692 | unwind.sp_restored = 0; | |
3693 | range = (range | 0x2000) & ~0x1000; | |
3694 | unwind.pending_offset = 0; | |
3695 | } | |
e16bb312 | 3696 | |
01ae4198 DJ |
3697 | /* Pop r4-r15. */ |
3698 | if (range & 0xfff0) | |
c19d1205 | 3699 | { |
01ae4198 DJ |
3700 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3701 | registers starting with r4, plus maybe r14. */ | |
3702 | for (n = 0; n < 8; n++) | |
3703 | { | |
3704 | /* Break at the first non-saved register. */ | |
3705 | if ((range & (1 << (n + 4))) == 0) | |
3706 | break; | |
3707 | } | |
3708 | /* See if there are any other bits set. */ | |
3709 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3710 | { | |
3711 | /* Use the long form. */ | |
3712 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3713 | add_unwind_opcode (op, 2); | |
3714 | } | |
0dd132b6 | 3715 | else |
01ae4198 DJ |
3716 | { |
3717 | /* Use the short form. */ | |
3718 | if (range & 0x4000) | |
3719 | op = 0xa8; /* Pop r14. */ | |
3720 | else | |
3721 | op = 0xa0; /* Do not pop r14. */ | |
3722 | op |= (n - 1); | |
3723 | add_unwind_opcode (op, 1); | |
3724 | } | |
c19d1205 | 3725 | } |
0dd132b6 | 3726 | |
c19d1205 ZW |
3727 | /* Pop r0-r3. */ |
3728 | if (range & 0xf) | |
3729 | { | |
3730 | op = 0xb100 | (range & 0xf); | |
3731 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3732 | } |
3733 | ||
c19d1205 ZW |
3734 | /* Record the number of bytes pushed. */ |
3735 | for (n = 0; n < 16; n++) | |
3736 | { | |
3737 | if (range & (1 << n)) | |
3738 | unwind.frame_size += 4; | |
3739 | } | |
0dd132b6 NC |
3740 | } |
3741 | ||
c19d1205 ZW |
3742 | |
3743 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3744 | |
3745 | static void | |
c19d1205 | 3746 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3747 | { |
c19d1205 ZW |
3748 | expressionS exp; |
3749 | int num_regs; | |
3750 | valueT op; | |
b99bd4ef | 3751 | |
c19d1205 ZW |
3752 | /* Get Number of registers to transfer. */ |
3753 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3754 | expression (&exp); | |
3755 | else | |
3756 | exp.X_op = O_illegal; | |
b99bd4ef | 3757 | |
c19d1205 | 3758 | if (exp.X_op != O_constant) |
b99bd4ef | 3759 | { |
c19d1205 ZW |
3760 | as_bad (_("expected , <constant>")); |
3761 | ignore_rest_of_line (); | |
b99bd4ef NC |
3762 | return; |
3763 | } | |
3764 | ||
c19d1205 ZW |
3765 | num_regs = exp.X_add_number; |
3766 | ||
3767 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3768 | { |
c19d1205 ZW |
3769 | as_bad (_("number of registers must be in the range [1:4]")); |
3770 | ignore_rest_of_line (); | |
b99bd4ef NC |
3771 | return; |
3772 | } | |
3773 | ||
c19d1205 | 3774 | demand_empty_rest_of_line (); |
b99bd4ef | 3775 | |
c19d1205 ZW |
3776 | if (reg == 4) |
3777 | { | |
3778 | /* Short form. */ | |
3779 | op = 0xb4 | (num_regs - 1); | |
3780 | add_unwind_opcode (op, 1); | |
3781 | } | |
b99bd4ef NC |
3782 | else |
3783 | { | |
c19d1205 ZW |
3784 | /* Long form. */ |
3785 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3786 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3787 | } |
c19d1205 | 3788 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3789 | } |
3790 | ||
c19d1205 | 3791 | |
fa073d69 MS |
3792 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3793 | ||
3794 | static void | |
3795 | s_arm_unwind_save_vfp_armv6 (void) | |
3796 | { | |
3797 | int count; | |
3798 | unsigned int start; | |
3799 | valueT op; | |
3800 | int num_vfpv3_regs = 0; | |
3801 | int num_regs_below_16; | |
3802 | ||
3803 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3804 | if (count == FAIL) | |
3805 | { | |
3806 | as_bad (_("expected register list")); | |
3807 | ignore_rest_of_line (); | |
3808 | return; | |
3809 | } | |
3810 | ||
3811 | demand_empty_rest_of_line (); | |
3812 | ||
3813 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3814 | than FSTMX/FLDMX-style ones). */ | |
3815 | ||
3816 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3817 | if (start >= 16) | |
3818 | num_vfpv3_regs = count; | |
3819 | else if (start + count > 16) | |
3820 | num_vfpv3_regs = start + count - 16; | |
3821 | ||
3822 | if (num_vfpv3_regs > 0) | |
3823 | { | |
3824 | int start_offset = start > 16 ? start - 16 : 0; | |
3825 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3826 | add_unwind_opcode (op, 2); | |
3827 | } | |
3828 | ||
3829 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3830 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3831 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3832 | if (num_regs_below_16 > 0) |
3833 | { | |
3834 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3835 | add_unwind_opcode (op, 2); | |
3836 | } | |
3837 | ||
3838 | unwind.frame_size += count * 8; | |
3839 | } | |
3840 | ||
3841 | ||
3842 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3843 | |
3844 | static void | |
c19d1205 | 3845 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3846 | { |
c19d1205 | 3847 | int count; |
ca3f61f7 | 3848 | unsigned int reg; |
c19d1205 | 3849 | valueT op; |
b99bd4ef | 3850 | |
5287ad62 | 3851 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3852 | if (count == FAIL) |
b99bd4ef | 3853 | { |
c19d1205 ZW |
3854 | as_bad (_("expected register list")); |
3855 | ignore_rest_of_line (); | |
b99bd4ef NC |
3856 | return; |
3857 | } | |
3858 | ||
c19d1205 | 3859 | demand_empty_rest_of_line (); |
b99bd4ef | 3860 | |
c19d1205 | 3861 | if (reg == 8) |
b99bd4ef | 3862 | { |
c19d1205 ZW |
3863 | /* Short form. */ |
3864 | op = 0xb8 | (count - 1); | |
3865 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3866 | } |
c19d1205 | 3867 | else |
b99bd4ef | 3868 | { |
c19d1205 ZW |
3869 | /* Long form. */ |
3870 | op = 0xb300 | (reg << 4) | (count - 1); | |
3871 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3872 | } |
c19d1205 ZW |
3873 | unwind.frame_size += count * 8 + 4; |
3874 | } | |
b99bd4ef | 3875 | |
b99bd4ef | 3876 | |
c19d1205 ZW |
3877 | /* Parse a directive saving iWMMXt data registers. */ |
3878 | ||
3879 | static void | |
3880 | s_arm_unwind_save_mmxwr (void) | |
3881 | { | |
3882 | int reg; | |
3883 | int hi_reg; | |
3884 | int i; | |
3885 | unsigned mask = 0; | |
3886 | valueT op; | |
b99bd4ef | 3887 | |
c19d1205 ZW |
3888 | if (*input_line_pointer == '{') |
3889 | input_line_pointer++; | |
b99bd4ef | 3890 | |
c19d1205 | 3891 | do |
b99bd4ef | 3892 | { |
dcbf9037 | 3893 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3894 | |
c19d1205 | 3895 | if (reg == FAIL) |
b99bd4ef | 3896 | { |
9b7132d3 | 3897 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3898 | goto error; |
b99bd4ef NC |
3899 | } |
3900 | ||
c19d1205 ZW |
3901 | if (mask >> reg) |
3902 | as_tsktsk (_("register list not in ascending order")); | |
3903 | mask |= 1 << reg; | |
b99bd4ef | 3904 | |
c19d1205 ZW |
3905 | if (*input_line_pointer == '-') |
3906 | { | |
3907 | input_line_pointer++; | |
dcbf9037 | 3908 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3909 | if (hi_reg == FAIL) |
3910 | { | |
9b7132d3 | 3911 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3912 | goto error; |
3913 | } | |
3914 | else if (reg >= hi_reg) | |
3915 | { | |
3916 | as_bad (_("bad register range")); | |
3917 | goto error; | |
3918 | } | |
3919 | for (; reg < hi_reg; reg++) | |
3920 | mask |= 1 << reg; | |
3921 | } | |
3922 | } | |
3923 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3924 | |
c19d1205 ZW |
3925 | if (*input_line_pointer == '}') |
3926 | input_line_pointer++; | |
b99bd4ef | 3927 | |
c19d1205 | 3928 | demand_empty_rest_of_line (); |
b99bd4ef | 3929 | |
708587a4 | 3930 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3931 | the list. */ |
3932 | flush_pending_unwind (); | |
b99bd4ef | 3933 | |
c19d1205 | 3934 | for (i = 0; i < 16; i++) |
b99bd4ef | 3935 | { |
c19d1205 ZW |
3936 | if (mask & (1 << i)) |
3937 | unwind.frame_size += 8; | |
b99bd4ef NC |
3938 | } |
3939 | ||
c19d1205 ZW |
3940 | /* Attempt to combine with a previous opcode. We do this because gcc |
3941 | likes to output separate unwind directives for a single block of | |
3942 | registers. */ | |
3943 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3944 | { |
c19d1205 ZW |
3945 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3946 | if ((i & 0xf8) == 0xc0) | |
3947 | { | |
3948 | i &= 7; | |
3949 | /* Only merge if the blocks are contiguous. */ | |
3950 | if (i < 6) | |
3951 | { | |
3952 | if ((mask & 0xfe00) == (1 << 9)) | |
3953 | { | |
3954 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3955 | unwind.opcode_count--; | |
3956 | } | |
3957 | } | |
3958 | else if (i == 6 && unwind.opcode_count >= 2) | |
3959 | { | |
3960 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3961 | reg = i >> 4; | |
3962 | i &= 0xf; | |
b99bd4ef | 3963 | |
c19d1205 ZW |
3964 | op = 0xffff << (reg - 1); |
3965 | if (reg > 0 | |
87a1fd79 | 3966 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3967 | { |
3968 | op = (1 << (reg + i + 1)) - 1; | |
3969 | op &= ~((1 << reg) - 1); | |
3970 | mask |= op; | |
3971 | unwind.opcode_count -= 2; | |
3972 | } | |
3973 | } | |
3974 | } | |
b99bd4ef NC |
3975 | } |
3976 | ||
c19d1205 ZW |
3977 | hi_reg = 15; |
3978 | /* We want to generate opcodes in the order the registers have been | |
3979 | saved, ie. descending order. */ | |
3980 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3981 | { |
c19d1205 ZW |
3982 | /* Save registers in blocks. */ |
3983 | if (reg < 0 | |
3984 | || !(mask & (1 << reg))) | |
3985 | { | |
3986 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3987 | preceding block. */ |
c19d1205 ZW |
3988 | if (reg != hi_reg) |
3989 | { | |
3990 | if (reg == 9) | |
3991 | { | |
3992 | /* Short form. */ | |
3993 | op = 0xc0 | (hi_reg - 10); | |
3994 | add_unwind_opcode (op, 1); | |
3995 | } | |
3996 | else | |
3997 | { | |
3998 | /* Long form. */ | |
3999 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
4000 | add_unwind_opcode (op, 2); | |
4001 | } | |
4002 | } | |
4003 | hi_reg = reg - 1; | |
4004 | } | |
b99bd4ef NC |
4005 | } |
4006 | ||
c19d1205 ZW |
4007 | return; |
4008 | error: | |
4009 | ignore_rest_of_line (); | |
b99bd4ef NC |
4010 | } |
4011 | ||
4012 | static void | |
c19d1205 | 4013 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 4014 | { |
c19d1205 ZW |
4015 | int reg; |
4016 | int hi_reg; | |
4017 | unsigned mask = 0; | |
4018 | valueT op; | |
b99bd4ef | 4019 | |
c19d1205 ZW |
4020 | if (*input_line_pointer == '{') |
4021 | input_line_pointer++; | |
b99bd4ef | 4022 | |
c19d1205 | 4023 | do |
b99bd4ef | 4024 | { |
dcbf9037 | 4025 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4026 | |
c19d1205 ZW |
4027 | if (reg == FAIL) |
4028 | { | |
9b7132d3 | 4029 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4030 | goto error; |
4031 | } | |
b99bd4ef | 4032 | |
c19d1205 ZW |
4033 | reg -= 8; |
4034 | if (mask >> reg) | |
4035 | as_tsktsk (_("register list not in ascending order")); | |
4036 | mask |= 1 << reg; | |
b99bd4ef | 4037 | |
c19d1205 ZW |
4038 | if (*input_line_pointer == '-') |
4039 | { | |
4040 | input_line_pointer++; | |
dcbf9037 | 4041 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4042 | if (hi_reg == FAIL) |
4043 | { | |
9b7132d3 | 4044 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4045 | goto error; |
4046 | } | |
4047 | else if (reg >= hi_reg) | |
4048 | { | |
4049 | as_bad (_("bad register range")); | |
4050 | goto error; | |
4051 | } | |
4052 | for (; reg < hi_reg; reg++) | |
4053 | mask |= 1 << reg; | |
4054 | } | |
b99bd4ef | 4055 | } |
c19d1205 | 4056 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4057 | |
c19d1205 ZW |
4058 | if (*input_line_pointer == '}') |
4059 | input_line_pointer++; | |
b99bd4ef | 4060 | |
c19d1205 ZW |
4061 | demand_empty_rest_of_line (); |
4062 | ||
708587a4 | 4063 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4064 | the list. */ |
4065 | flush_pending_unwind (); | |
b99bd4ef | 4066 | |
c19d1205 | 4067 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4068 | { |
c19d1205 ZW |
4069 | if (mask & (1 << reg)) |
4070 | unwind.frame_size += 4; | |
b99bd4ef | 4071 | } |
c19d1205 ZW |
4072 | op = 0xc700 | mask; |
4073 | add_unwind_opcode (op, 2); | |
4074 | return; | |
4075 | error: | |
4076 | ignore_rest_of_line (); | |
b99bd4ef NC |
4077 | } |
4078 | ||
c19d1205 | 4079 | |
fa073d69 MS |
4080 | /* Parse an unwind_save directive. |
4081 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4082 | |
b99bd4ef | 4083 | static void |
fa073d69 | 4084 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4085 | { |
c19d1205 ZW |
4086 | char *peek; |
4087 | struct reg_entry *reg; | |
4088 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4089 | |
921e5f0a | 4090 | if (!unwind.proc_start) |
c921be7d | 4091 | as_bad (MISSING_FNSTART); |
921e5f0a | 4092 | |
c19d1205 ZW |
4093 | /* Figure out what sort of save we have. */ |
4094 | peek = input_line_pointer; | |
b99bd4ef | 4095 | |
c19d1205 | 4096 | if (*peek == '{') |
b99bd4ef | 4097 | { |
c19d1205 ZW |
4098 | had_brace = TRUE; |
4099 | peek++; | |
b99bd4ef NC |
4100 | } |
4101 | ||
c19d1205 | 4102 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4103 | |
c19d1205 | 4104 | if (!reg) |
b99bd4ef | 4105 | { |
c19d1205 ZW |
4106 | as_bad (_("register expected")); |
4107 | ignore_rest_of_line (); | |
b99bd4ef NC |
4108 | return; |
4109 | } | |
4110 | ||
c19d1205 | 4111 | switch (reg->type) |
b99bd4ef | 4112 | { |
c19d1205 ZW |
4113 | case REG_TYPE_FN: |
4114 | if (had_brace) | |
4115 | { | |
4116 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4117 | ignore_rest_of_line (); | |
4118 | return; | |
4119 | } | |
93ac2687 | 4120 | input_line_pointer = peek; |
c19d1205 | 4121 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4122 | return; |
c19d1205 ZW |
4123 | |
4124 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4125 | case REG_TYPE_VFD: |
4126 | if (arch_v6) | |
4127 | s_arm_unwind_save_vfp_armv6 (); | |
4128 | else | |
4129 | s_arm_unwind_save_vfp (); | |
4130 | return; | |
c19d1205 ZW |
4131 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4132 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4133 | ||
4134 | default: | |
4135 | as_bad (_(".unwind_save does not support this kind of register")); | |
4136 | ignore_rest_of_line (); | |
b99bd4ef | 4137 | } |
c19d1205 | 4138 | } |
b99bd4ef | 4139 | |
b99bd4ef | 4140 | |
c19d1205 ZW |
4141 | /* Parse an unwind_movsp directive. */ |
4142 | ||
4143 | static void | |
4144 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4145 | { | |
4146 | int reg; | |
4147 | valueT op; | |
4fa3602b | 4148 | int offset; |
c19d1205 | 4149 | |
921e5f0a | 4150 | if (!unwind.proc_start) |
c921be7d | 4151 | as_bad (MISSING_FNSTART); |
921e5f0a | 4152 | |
dcbf9037 | 4153 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4154 | if (reg == FAIL) |
b99bd4ef | 4155 | { |
9b7132d3 | 4156 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4157 | ignore_rest_of_line (); |
b99bd4ef NC |
4158 | return; |
4159 | } | |
4fa3602b PB |
4160 | |
4161 | /* Optional constant. */ | |
4162 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4163 | { | |
4164 | if (immediate_for_directive (&offset) == FAIL) | |
4165 | return; | |
4166 | } | |
4167 | else | |
4168 | offset = 0; | |
4169 | ||
c19d1205 | 4170 | demand_empty_rest_of_line (); |
b99bd4ef | 4171 | |
c19d1205 | 4172 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4173 | { |
c19d1205 | 4174 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4175 | return; |
4176 | } | |
4177 | ||
c19d1205 ZW |
4178 | if (unwind.fp_reg != REG_SP) |
4179 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4180 | |
c19d1205 ZW |
4181 | /* Generate opcode to restore the value. */ |
4182 | op = 0x90 | reg; | |
4183 | add_unwind_opcode (op, 1); | |
4184 | ||
4185 | /* Record the information for later. */ | |
4186 | unwind.fp_reg = reg; | |
4fa3602b | 4187 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4188 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4189 | } |
4190 | ||
c19d1205 ZW |
4191 | /* Parse an unwind_pad directive. */ |
4192 | ||
b05fe5cf | 4193 | static void |
c19d1205 | 4194 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4195 | { |
c19d1205 | 4196 | int offset; |
b05fe5cf | 4197 | |
921e5f0a | 4198 | if (!unwind.proc_start) |
c921be7d | 4199 | as_bad (MISSING_FNSTART); |
921e5f0a | 4200 | |
c19d1205 ZW |
4201 | if (immediate_for_directive (&offset) == FAIL) |
4202 | return; | |
b99bd4ef | 4203 | |
c19d1205 ZW |
4204 | if (offset & 3) |
4205 | { | |
4206 | as_bad (_("stack increment must be multiple of 4")); | |
4207 | ignore_rest_of_line (); | |
4208 | return; | |
4209 | } | |
b99bd4ef | 4210 | |
c19d1205 ZW |
4211 | /* Don't generate any opcodes, just record the details for later. */ |
4212 | unwind.frame_size += offset; | |
4213 | unwind.pending_offset += offset; | |
4214 | ||
4215 | demand_empty_rest_of_line (); | |
4216 | } | |
4217 | ||
4218 | /* Parse an unwind_setfp directive. */ | |
4219 | ||
4220 | static void | |
4221 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4222 | { |
c19d1205 ZW |
4223 | int sp_reg; |
4224 | int fp_reg; | |
4225 | int offset; | |
4226 | ||
921e5f0a | 4227 | if (!unwind.proc_start) |
c921be7d | 4228 | as_bad (MISSING_FNSTART); |
921e5f0a | 4229 | |
dcbf9037 | 4230 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4231 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4232 | sp_reg = FAIL; | |
4233 | else | |
dcbf9037 | 4234 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4235 | |
c19d1205 ZW |
4236 | if (fp_reg == FAIL || sp_reg == FAIL) |
4237 | { | |
4238 | as_bad (_("expected <reg>, <reg>")); | |
4239 | ignore_rest_of_line (); | |
4240 | return; | |
4241 | } | |
b99bd4ef | 4242 | |
c19d1205 ZW |
4243 | /* Optional constant. */ |
4244 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4245 | { | |
4246 | if (immediate_for_directive (&offset) == FAIL) | |
4247 | return; | |
4248 | } | |
4249 | else | |
4250 | offset = 0; | |
a737bd4d | 4251 | |
c19d1205 | 4252 | demand_empty_rest_of_line (); |
a737bd4d | 4253 | |
fdfde340 | 4254 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4255 | { |
c19d1205 ZW |
4256 | as_bad (_("register must be either sp or set by a previous" |
4257 | "unwind_movsp directive")); | |
4258 | return; | |
a737bd4d NC |
4259 | } |
4260 | ||
c19d1205 ZW |
4261 | /* Don't generate any opcodes, just record the information for later. */ |
4262 | unwind.fp_reg = fp_reg; | |
4263 | unwind.fp_used = 1; | |
fdfde340 | 4264 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4265 | unwind.fp_offset = unwind.frame_size - offset; |
4266 | else | |
4267 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4268 | } |
4269 | ||
c19d1205 ZW |
4270 | /* Parse an unwind_raw directive. */ |
4271 | ||
4272 | static void | |
4273 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4274 | { |
c19d1205 | 4275 | expressionS exp; |
708587a4 | 4276 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4277 | unsigned char op[16]; |
4278 | int count; | |
a737bd4d | 4279 | |
921e5f0a | 4280 | if (!unwind.proc_start) |
c921be7d | 4281 | as_bad (MISSING_FNSTART); |
921e5f0a | 4282 | |
c19d1205 ZW |
4283 | expression (&exp); |
4284 | if (exp.X_op == O_constant | |
4285 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4286 | { |
c19d1205 ZW |
4287 | unwind.frame_size += exp.X_add_number; |
4288 | expression (&exp); | |
4289 | } | |
4290 | else | |
4291 | exp.X_op = O_illegal; | |
a737bd4d | 4292 | |
c19d1205 ZW |
4293 | if (exp.X_op != O_constant) |
4294 | { | |
4295 | as_bad (_("expected <offset>, <opcode>")); | |
4296 | ignore_rest_of_line (); | |
4297 | return; | |
4298 | } | |
a737bd4d | 4299 | |
c19d1205 | 4300 | count = 0; |
a737bd4d | 4301 | |
c19d1205 ZW |
4302 | /* Parse the opcode. */ |
4303 | for (;;) | |
4304 | { | |
4305 | if (count >= 16) | |
4306 | { | |
4307 | as_bad (_("unwind opcode too long")); | |
4308 | ignore_rest_of_line (); | |
a737bd4d | 4309 | } |
c19d1205 | 4310 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4311 | { |
c19d1205 ZW |
4312 | as_bad (_("invalid unwind opcode")); |
4313 | ignore_rest_of_line (); | |
4314 | return; | |
a737bd4d | 4315 | } |
c19d1205 | 4316 | op[count++] = exp.X_add_number; |
a737bd4d | 4317 | |
c19d1205 ZW |
4318 | /* Parse the next byte. */ |
4319 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4320 | break; | |
a737bd4d | 4321 | |
c19d1205 ZW |
4322 | expression (&exp); |
4323 | } | |
b99bd4ef | 4324 | |
c19d1205 ZW |
4325 | /* Add the opcode bytes in reverse order. */ |
4326 | while (count--) | |
4327 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4328 | |
c19d1205 | 4329 | demand_empty_rest_of_line (); |
b99bd4ef | 4330 | } |
ee065d83 PB |
4331 | |
4332 | ||
4333 | /* Parse a .eabi_attribute directive. */ | |
4334 | ||
4335 | static void | |
4336 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4337 | { | |
ee3c0378 AS |
4338 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4339 | ||
4340 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4341 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4342 | } |
4343 | ||
0855e32b NS |
4344 | /* Emit a tls fix for the symbol. */ |
4345 | ||
4346 | static void | |
4347 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4348 | { | |
4349 | char *p; | |
4350 | expressionS exp; | |
4351 | #ifdef md_flush_pending_output | |
4352 | md_flush_pending_output (); | |
4353 | #endif | |
4354 | ||
4355 | #ifdef md_cons_align | |
4356 | md_cons_align (4); | |
4357 | #endif | |
4358 | ||
4359 | /* Since we're just labelling the code, there's no need to define a | |
4360 | mapping symbol. */ | |
4361 | expression (&exp); | |
4362 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4363 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4364 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4365 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4366 | } | |
cdf9ccec | 4367 | #endif /* OBJ_ELF */ |
0855e32b | 4368 | |
ee065d83 | 4369 | static void s_arm_arch (int); |
7a1d4c38 | 4370 | static void s_arm_object_arch (int); |
ee065d83 PB |
4371 | static void s_arm_cpu (int); |
4372 | static void s_arm_fpu (int); | |
69133863 | 4373 | static void s_arm_arch_extension (int); |
b99bd4ef | 4374 | |
f0927246 NC |
4375 | #ifdef TE_PE |
4376 | ||
4377 | static void | |
5f4273c7 | 4378 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4379 | { |
4380 | expressionS exp; | |
4381 | ||
4382 | do | |
4383 | { | |
4384 | expression (&exp); | |
4385 | if (exp.X_op == O_symbol) | |
4386 | exp.X_op = O_secrel; | |
4387 | ||
4388 | emit_expr (&exp, 4); | |
4389 | } | |
4390 | while (*input_line_pointer++ == ','); | |
4391 | ||
4392 | input_line_pointer--; | |
4393 | demand_empty_rest_of_line (); | |
4394 | } | |
4395 | #endif /* TE_PE */ | |
4396 | ||
c19d1205 ZW |
4397 | /* This table describes all the machine specific pseudo-ops the assembler |
4398 | has to support. The fields are: | |
4399 | pseudo-op name without dot | |
4400 | function to call to execute this pseudo-op | |
4401 | Integer arg to pass to the function. */ | |
b99bd4ef | 4402 | |
c19d1205 | 4403 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4404 | { |
c19d1205 ZW |
4405 | /* Never called because '.req' does not start a line. */ |
4406 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4407 | /* Following two are likewise never called. */ |
4408 | { "dn", s_dn, 0 }, | |
4409 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4410 | { "unreq", s_unreq, 0 }, |
4411 | { "bss", s_bss, 0 }, | |
4412 | { "align", s_align, 0 }, | |
4413 | { "arm", s_arm, 0 }, | |
4414 | { "thumb", s_thumb, 0 }, | |
4415 | { "code", s_code, 0 }, | |
4416 | { "force_thumb", s_force_thumb, 0 }, | |
4417 | { "thumb_func", s_thumb_func, 0 }, | |
4418 | { "thumb_set", s_thumb_set, 0 }, | |
4419 | { "even", s_even, 0 }, | |
4420 | { "ltorg", s_ltorg, 0 }, | |
4421 | { "pool", s_ltorg, 0 }, | |
4422 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4423 | { "cpu", s_arm_cpu, 0 }, |
4424 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4425 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4426 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4427 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4428 | #ifdef OBJ_ELF |
c921be7d NC |
4429 | { "word", s_arm_elf_cons, 4 }, |
4430 | { "long", s_arm_elf_cons, 4 }, | |
4431 | { "inst.n", s_arm_elf_inst, 2 }, | |
4432 | { "inst.w", s_arm_elf_inst, 4 }, | |
4433 | { "inst", s_arm_elf_inst, 0 }, | |
4434 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4435 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4436 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4437 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4438 | { "personality", s_arm_unwind_personality, 0 }, | |
4439 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4440 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4441 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4442 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4443 | { "movsp", s_arm_unwind_movsp, 0 }, |
4444 | { "pad", s_arm_unwind_pad, 0 }, | |
4445 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4446 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4447 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4448 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4449 | #else |
4450 | { "word", cons, 4}, | |
f0927246 NC |
4451 | |
4452 | /* These are used for dwarf. */ | |
4453 | {"2byte", cons, 2}, | |
4454 | {"4byte", cons, 4}, | |
4455 | {"8byte", cons, 8}, | |
4456 | /* These are used for dwarf2. */ | |
4457 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4458 | { "loc", dwarf2_directive_loc, 0 }, | |
4459 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4460 | #endif |
4461 | { "extend", float_cons, 'x' }, | |
4462 | { "ldouble", float_cons, 'x' }, | |
4463 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4464 | #ifdef TE_PE |
4465 | {"secrel32", pe_directive_secrel, 0}, | |
4466 | #endif | |
c19d1205 ZW |
4467 | { 0, 0, 0 } |
4468 | }; | |
4469 | \f | |
4470 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4471 | |
c19d1205 ZW |
4472 | /* Generic immediate-value read function for use in insn parsing. |
4473 | STR points to the beginning of the immediate (the leading #); | |
4474 | VAL receives the value; if the value is outside [MIN, MAX] | |
4475 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4476 | optional. */ | |
b99bd4ef | 4477 | |
c19d1205 ZW |
4478 | static int |
4479 | parse_immediate (char **str, int *val, int min, int max, | |
4480 | bfd_boolean prefix_opt) | |
4481 | { | |
4482 | expressionS exp; | |
4483 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4484 | if (exp.X_op != O_constant) | |
b99bd4ef | 4485 | { |
c19d1205 ZW |
4486 | inst.error = _("constant expression required"); |
4487 | return FAIL; | |
4488 | } | |
b99bd4ef | 4489 | |
c19d1205 ZW |
4490 | if (exp.X_add_number < min || exp.X_add_number > max) |
4491 | { | |
4492 | inst.error = _("immediate value out of range"); | |
4493 | return FAIL; | |
4494 | } | |
b99bd4ef | 4495 | |
c19d1205 ZW |
4496 | *val = exp.X_add_number; |
4497 | return SUCCESS; | |
4498 | } | |
b99bd4ef | 4499 | |
5287ad62 | 4500 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4501 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4502 | instructions. Puts the result directly in inst.operands[i]. */ |
4503 | ||
4504 | static int | |
4505 | parse_big_immediate (char **str, int i) | |
4506 | { | |
4507 | expressionS exp; | |
4508 | char *ptr = *str; | |
4509 | ||
4510 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4511 | ||
4512 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4513 | { |
4514 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4515 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4516 | O_constant. We have to be careful not to break compilation for | |
4517 | 32-bit X_add_number, though. */ | |
58ad575f | 4518 | if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 PB |
4519 | { |
4520 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4521 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4522 | inst.operands[i].regisimm = 1; | |
4523 | } | |
4524 | } | |
5287ad62 | 4525 | else if (exp.X_op == O_big |
95b75c01 | 4526 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) |
5287ad62 JB |
4527 | { |
4528 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4529 | |
5287ad62 JB |
4530 | /* Bignums have their least significant bits in |
4531 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4532 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4533 | gas_assert (parts != 0); |
95b75c01 NC |
4534 | |
4535 | /* Make sure that the number is not too big. | |
4536 | PR 11972: Bignums can now be sign-extended to the | |
4537 | size of a .octa so check that the out of range bits | |
4538 | are all zero or all one. */ | |
4539 | if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) | |
4540 | { | |
4541 | LITTLENUM_TYPE m = -1; | |
4542 | ||
4543 | if (generic_bignum[parts * 2] != 0 | |
4544 | && generic_bignum[parts * 2] != m) | |
4545 | return FAIL; | |
4546 | ||
4547 | for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) | |
4548 | if (generic_bignum[j] != generic_bignum[j-1]) | |
4549 | return FAIL; | |
4550 | } | |
4551 | ||
5287ad62 JB |
4552 | inst.operands[i].imm = 0; |
4553 | for (j = 0; j < parts; j++, idx++) | |
4554 | inst.operands[i].imm |= generic_bignum[idx] | |
4555 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4556 | inst.operands[i].reg = 0; | |
4557 | for (j = 0; j < parts; j++, idx++) | |
4558 | inst.operands[i].reg |= generic_bignum[idx] | |
4559 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4560 | inst.operands[i].regisimm = 1; | |
4561 | } | |
4562 | else | |
4563 | return FAIL; | |
5f4273c7 | 4564 | |
5287ad62 JB |
4565 | *str = ptr; |
4566 | ||
4567 | return SUCCESS; | |
4568 | } | |
4569 | ||
c19d1205 ZW |
4570 | /* Returns the pseudo-register number of an FPA immediate constant, |
4571 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4572 | |
c19d1205 ZW |
4573 | static int |
4574 | parse_fpa_immediate (char ** str) | |
4575 | { | |
4576 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4577 | char * save_in; | |
4578 | expressionS exp; | |
4579 | int i; | |
4580 | int j; | |
b99bd4ef | 4581 | |
c19d1205 ZW |
4582 | /* First try and match exact strings, this is to guarantee |
4583 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4584 | |
c19d1205 ZW |
4585 | for (i = 0; fp_const[i]; i++) |
4586 | { | |
4587 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4588 | { |
c19d1205 | 4589 | char *start = *str; |
b99bd4ef | 4590 | |
c19d1205 ZW |
4591 | *str += strlen (fp_const[i]); |
4592 | if (is_end_of_line[(unsigned char) **str]) | |
4593 | return i + 8; | |
4594 | *str = start; | |
4595 | } | |
4596 | } | |
b99bd4ef | 4597 | |
c19d1205 ZW |
4598 | /* Just because we didn't get a match doesn't mean that the constant |
4599 | isn't valid, just that it is in a format that we don't | |
4600 | automatically recognize. Try parsing it with the standard | |
4601 | expression routines. */ | |
b99bd4ef | 4602 | |
c19d1205 | 4603 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4604 | |
c19d1205 ZW |
4605 | /* Look for a raw floating point number. */ |
4606 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4607 | && is_end_of_line[(unsigned char) *save_in]) | |
4608 | { | |
4609 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4610 | { | |
4611 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4612 | { |
c19d1205 ZW |
4613 | if (words[j] != fp_values[i][j]) |
4614 | break; | |
b99bd4ef NC |
4615 | } |
4616 | ||
c19d1205 | 4617 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4618 | { |
c19d1205 ZW |
4619 | *str = save_in; |
4620 | return i + 8; | |
b99bd4ef NC |
4621 | } |
4622 | } | |
4623 | } | |
b99bd4ef | 4624 | |
c19d1205 ZW |
4625 | /* Try and parse a more complex expression, this will probably fail |
4626 | unless the code uses a floating point prefix (eg "0f"). */ | |
4627 | save_in = input_line_pointer; | |
4628 | input_line_pointer = *str; | |
4629 | if (expression (&exp) == absolute_section | |
4630 | && exp.X_op == O_big | |
4631 | && exp.X_add_number < 0) | |
4632 | { | |
4633 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4634 | Ditto for 15. */ | |
4635 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4636 | { | |
4637 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4638 | { | |
4639 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4640 | { | |
4641 | if (words[j] != fp_values[i][j]) | |
4642 | break; | |
4643 | } | |
b99bd4ef | 4644 | |
c19d1205 ZW |
4645 | if (j == MAX_LITTLENUMS) |
4646 | { | |
4647 | *str = input_line_pointer; | |
4648 | input_line_pointer = save_in; | |
4649 | return i + 8; | |
4650 | } | |
4651 | } | |
4652 | } | |
b99bd4ef NC |
4653 | } |
4654 | ||
c19d1205 ZW |
4655 | *str = input_line_pointer; |
4656 | input_line_pointer = save_in; | |
4657 | inst.error = _("invalid FPA immediate expression"); | |
4658 | return FAIL; | |
b99bd4ef NC |
4659 | } |
4660 | ||
136da414 JB |
4661 | /* Returns 1 if a number has "quarter-precision" float format |
4662 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4663 | ||
4664 | static int | |
4665 | is_quarter_float (unsigned imm) | |
4666 | { | |
4667 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4668 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4669 | } | |
4670 | ||
4671 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4672 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4673 | The zero and minus-zero cases need special handling, since they can't be |
4674 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4675 | loaded as integer constants. */ | |
136da414 JB |
4676 | |
4677 | static unsigned | |
4678 | parse_qfloat_immediate (char **ccp, int *immed) | |
4679 | { | |
4680 | char *str = *ccp; | |
c96612cc | 4681 | char *fpnum; |
136da414 | 4682 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4683 | int found_fpchar = 0; |
5f4273c7 | 4684 | |
136da414 | 4685 | skip_past_char (&str, '#'); |
5f4273c7 | 4686 | |
c96612cc JB |
4687 | /* We must not accidentally parse an integer as a floating-point number. Make |
4688 | sure that the value we parse is not an integer by checking for special | |
4689 | characters '.' or 'e'. | |
4690 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4691 | information isn't in a very usable state at parse time. */ | |
4692 | fpnum = str; | |
4693 | skip_whitespace (fpnum); | |
4694 | ||
4695 | if (strncmp (fpnum, "0x", 2) == 0) | |
4696 | return FAIL; | |
4697 | else | |
4698 | { | |
4699 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4700 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4701 | { | |
4702 | found_fpchar = 1; | |
4703 | break; | |
4704 | } | |
4705 | ||
4706 | if (!found_fpchar) | |
4707 | return FAIL; | |
4708 | } | |
5f4273c7 | 4709 | |
136da414 JB |
4710 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4711 | { | |
4712 | unsigned fpword = 0; | |
4713 | int i; | |
5f4273c7 | 4714 | |
136da414 JB |
4715 | /* Our FP word must be 32 bits (single-precision FP). */ |
4716 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4717 | { | |
4718 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4719 | fpword |= words[i]; | |
4720 | } | |
5f4273c7 | 4721 | |
c96612cc | 4722 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4723 | *immed = fpword; |
4724 | else | |
4725 | return FAIL; | |
4726 | ||
4727 | *ccp = str; | |
5f4273c7 | 4728 | |
136da414 JB |
4729 | return SUCCESS; |
4730 | } | |
5f4273c7 | 4731 | |
136da414 JB |
4732 | return FAIL; |
4733 | } | |
4734 | ||
c19d1205 ZW |
4735 | /* Shift operands. */ |
4736 | enum shift_kind | |
b99bd4ef | 4737 | { |
c19d1205 ZW |
4738 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4739 | }; | |
b99bd4ef | 4740 | |
c19d1205 ZW |
4741 | struct asm_shift_name |
4742 | { | |
4743 | const char *name; | |
4744 | enum shift_kind kind; | |
4745 | }; | |
b99bd4ef | 4746 | |
c19d1205 ZW |
4747 | /* Third argument to parse_shift. */ |
4748 | enum parse_shift_mode | |
4749 | { | |
4750 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4751 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4752 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4753 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4754 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4755 | }; | |
b99bd4ef | 4756 | |
c19d1205 ZW |
4757 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4758 | This has three forms: | |
b99bd4ef | 4759 | |
c19d1205 ZW |
4760 | (LSL|LSR|ASL|ASR|ROR) Rs |
4761 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4762 | RRX | |
b99bd4ef | 4763 | |
c19d1205 ZW |
4764 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4765 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4766 | |
c19d1205 ZW |
4767 | static int |
4768 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4769 | { |
c19d1205 ZW |
4770 | const struct asm_shift_name *shift_name; |
4771 | enum shift_kind shift; | |
4772 | char *s = *str; | |
4773 | char *p = s; | |
4774 | int reg; | |
b99bd4ef | 4775 | |
c19d1205 ZW |
4776 | for (p = *str; ISALPHA (*p); p++) |
4777 | ; | |
b99bd4ef | 4778 | |
c19d1205 | 4779 | if (p == *str) |
b99bd4ef | 4780 | { |
c19d1205 ZW |
4781 | inst.error = _("shift expression expected"); |
4782 | return FAIL; | |
b99bd4ef NC |
4783 | } |
4784 | ||
21d799b5 NC |
4785 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4786 | p - *str); | |
c19d1205 ZW |
4787 | |
4788 | if (shift_name == NULL) | |
b99bd4ef | 4789 | { |
c19d1205 ZW |
4790 | inst.error = _("shift expression expected"); |
4791 | return FAIL; | |
b99bd4ef NC |
4792 | } |
4793 | ||
c19d1205 | 4794 | shift = shift_name->kind; |
b99bd4ef | 4795 | |
c19d1205 ZW |
4796 | switch (mode) |
4797 | { | |
4798 | case NO_SHIFT_RESTRICT: | |
4799 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4800 | |
c19d1205 ZW |
4801 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4802 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4803 | { | |
4804 | inst.error = _("'LSL' or 'ASR' required"); | |
4805 | return FAIL; | |
4806 | } | |
4807 | break; | |
b99bd4ef | 4808 | |
c19d1205 ZW |
4809 | case SHIFT_LSL_IMMEDIATE: |
4810 | if (shift != SHIFT_LSL) | |
4811 | { | |
4812 | inst.error = _("'LSL' required"); | |
4813 | return FAIL; | |
4814 | } | |
4815 | break; | |
b99bd4ef | 4816 | |
c19d1205 ZW |
4817 | case SHIFT_ASR_IMMEDIATE: |
4818 | if (shift != SHIFT_ASR) | |
4819 | { | |
4820 | inst.error = _("'ASR' required"); | |
4821 | return FAIL; | |
4822 | } | |
4823 | break; | |
b99bd4ef | 4824 | |
c19d1205 ZW |
4825 | default: abort (); |
4826 | } | |
b99bd4ef | 4827 | |
c19d1205 ZW |
4828 | if (shift != SHIFT_RRX) |
4829 | { | |
4830 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4831 | skip_whitespace (p); | |
b99bd4ef | 4832 | |
c19d1205 | 4833 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4834 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4835 | { |
4836 | inst.operands[i].imm = reg; | |
4837 | inst.operands[i].immisreg = 1; | |
4838 | } | |
4839 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4840 | return FAIL; | |
4841 | } | |
4842 | inst.operands[i].shift_kind = shift; | |
4843 | inst.operands[i].shifted = 1; | |
4844 | *str = p; | |
4845 | return SUCCESS; | |
b99bd4ef NC |
4846 | } |
4847 | ||
c19d1205 | 4848 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4849 | |
c19d1205 ZW |
4850 | #<immediate> |
4851 | #<immediate>, <rotate> | |
4852 | <Rm> | |
4853 | <Rm>, <shift> | |
b99bd4ef | 4854 | |
c19d1205 ZW |
4855 | where <shift> is defined by parse_shift above, and <rotate> is a |
4856 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4857 | is deferred to md_apply_fix. */ |
b99bd4ef | 4858 | |
c19d1205 ZW |
4859 | static int |
4860 | parse_shifter_operand (char **str, int i) | |
4861 | { | |
4862 | int value; | |
91d6fa6a | 4863 | expressionS exp; |
b99bd4ef | 4864 | |
dcbf9037 | 4865 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4866 | { |
4867 | inst.operands[i].reg = value; | |
4868 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4869 | |
c19d1205 ZW |
4870 | /* parse_shift will override this if appropriate */ |
4871 | inst.reloc.exp.X_op = O_constant; | |
4872 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4873 | |
c19d1205 ZW |
4874 | if (skip_past_comma (str) == FAIL) |
4875 | return SUCCESS; | |
b99bd4ef | 4876 | |
c19d1205 ZW |
4877 | /* Shift operation on register. */ |
4878 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4879 | } |
4880 | ||
c19d1205 ZW |
4881 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4882 | return FAIL; | |
b99bd4ef | 4883 | |
c19d1205 | 4884 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4885 | { |
c19d1205 | 4886 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4887 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4888 | return FAIL; |
b99bd4ef | 4889 | |
91d6fa6a | 4890 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4891 | { |
4892 | inst.error = _("constant expression expected"); | |
4893 | return FAIL; | |
4894 | } | |
b99bd4ef | 4895 | |
91d6fa6a | 4896 | value = exp.X_add_number; |
c19d1205 ZW |
4897 | if (value < 0 || value > 30 || value % 2 != 0) |
4898 | { | |
4899 | inst.error = _("invalid rotation"); | |
4900 | return FAIL; | |
4901 | } | |
4902 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4903 | { | |
4904 | inst.error = _("invalid constant"); | |
4905 | return FAIL; | |
4906 | } | |
09d92015 | 4907 | |
a415b1cd JB |
4908 | /* Encode as specified. */ |
4909 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
4910 | return SUCCESS; | |
09d92015 MM |
4911 | } |
4912 | ||
c19d1205 ZW |
4913 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4914 | inst.reloc.pc_rel = 0; | |
4915 | return SUCCESS; | |
09d92015 MM |
4916 | } |
4917 | ||
4962c51a MS |
4918 | /* Group relocation information. Each entry in the table contains the |
4919 | textual name of the relocation as may appear in assembler source | |
4920 | and must end with a colon. | |
4921 | Along with this textual name are the relocation codes to be used if | |
4922 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4923 | an LDR, an LDRS, or an LDC. */ | |
4924 | ||
4925 | struct group_reloc_table_entry | |
4926 | { | |
4927 | const char *name; | |
4928 | int alu_code; | |
4929 | int ldr_code; | |
4930 | int ldrs_code; | |
4931 | int ldc_code; | |
4932 | }; | |
4933 | ||
4934 | typedef enum | |
4935 | { | |
4936 | /* Varieties of non-ALU group relocation. */ | |
4937 | ||
4938 | GROUP_LDR, | |
4939 | GROUP_LDRS, | |
4940 | GROUP_LDC | |
4941 | } group_reloc_type; | |
4942 | ||
4943 | static struct group_reloc_table_entry group_reloc_table[] = | |
4944 | { /* Program counter relative: */ | |
4945 | { "pc_g0_nc", | |
4946 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4947 | 0, /* LDR */ | |
4948 | 0, /* LDRS */ | |
4949 | 0 }, /* LDC */ | |
4950 | { "pc_g0", | |
4951 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4952 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4953 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4954 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4955 | { "pc_g1_nc", | |
4956 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4957 | 0, /* LDR */ | |
4958 | 0, /* LDRS */ | |
4959 | 0 }, /* LDC */ | |
4960 | { "pc_g1", | |
4961 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4962 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4963 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4964 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4965 | { "pc_g2", | |
4966 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4967 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4968 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4969 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4970 | /* Section base relative */ | |
4971 | { "sb_g0_nc", | |
4972 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4973 | 0, /* LDR */ | |
4974 | 0, /* LDRS */ | |
4975 | 0 }, /* LDC */ | |
4976 | { "sb_g0", | |
4977 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4978 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4979 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4980 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4981 | { "sb_g1_nc", | |
4982 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4983 | 0, /* LDR */ | |
4984 | 0, /* LDRS */ | |
4985 | 0 }, /* LDC */ | |
4986 | { "sb_g1", | |
4987 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4988 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4989 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4990 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4991 | { "sb_g2", | |
4992 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4993 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4994 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4995 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4996 | ||
4997 | /* Given the address of a pointer pointing to the textual name of a group | |
4998 | relocation as may appear in assembler source, attempt to find its details | |
4999 | in group_reloc_table. The pointer will be updated to the character after | |
5000 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
5001 | otherwise. On success, *entry will be updated to point at the relevant | |
5002 | group_reloc_table entry. */ | |
5003 | ||
5004 | static int | |
5005 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
5006 | { | |
5007 | unsigned int i; | |
5008 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
5009 | { | |
5010 | int length = strlen (group_reloc_table[i].name); | |
5011 | ||
5f4273c7 NC |
5012 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
5013 | && (*str)[length] == ':') | |
4962c51a MS |
5014 | { |
5015 | *out = &group_reloc_table[i]; | |
5016 | *str += (length + 1); | |
5017 | return SUCCESS; | |
5018 | } | |
5019 | } | |
5020 | ||
5021 | return FAIL; | |
5022 | } | |
5023 | ||
5024 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5025 | (as for parse_shifter_operand) where group relocations are allowed: | |
5026 | ||
5027 | #<immediate> | |
5028 | #<immediate>, <rotate> | |
5029 | #:<group_reloc>:<expression> | |
5030 | <Rm> | |
5031 | <Rm>, <shift> | |
5032 | ||
5033 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5034 | The hashes are optional. | |
5035 | ||
5036 | Everything else is as for parse_shifter_operand. */ | |
5037 | ||
5038 | static parse_operand_result | |
5039 | parse_shifter_operand_group_reloc (char **str, int i) | |
5040 | { | |
5041 | /* Determine if we have the sequence of characters #: or just : | |
5042 | coming next. If we do, then we check for a group relocation. | |
5043 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5044 | ||
5045 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5046 | || (*str)[0] == ':') | |
5047 | { | |
5048 | struct group_reloc_table_entry *entry; | |
5049 | ||
5050 | if ((*str)[0] == '#') | |
5051 | (*str) += 2; | |
5052 | else | |
5053 | (*str)++; | |
5054 | ||
5055 | /* Try to parse a group relocation. Anything else is an error. */ | |
5056 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
5057 | { | |
5058 | inst.error = _("unknown group relocation"); | |
5059 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5060 | } | |
5061 | ||
5062 | /* We now have the group relocation table entry corresponding to | |
5063 | the name in the assembler source. Next, we parse the expression. */ | |
5064 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
5065 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5066 | ||
5067 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5068 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5069 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5070 | |
5071 | return PARSE_OPERAND_SUCCESS; | |
5072 | } | |
5073 | else | |
5074 | return parse_shifter_operand (str, i) == SUCCESS | |
5075 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
5076 | ||
5077 | /* Never reached. */ | |
5078 | } | |
5079 | ||
8e560766 MGD |
5080 | /* Parse a Neon alignment expression. Information is written to |
5081 | inst.operands[i]. We assume the initial ':' has been skipped. | |
fa94de6b | 5082 | |
8e560766 MGD |
5083 | align .imm = align << 8, .immisalign=1, .preind=0 */ |
5084 | static parse_operand_result | |
5085 | parse_neon_alignment (char **str, int i) | |
5086 | { | |
5087 | char *p = *str; | |
5088 | expressionS exp; | |
5089 | ||
5090 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5091 | ||
5092 | if (exp.X_op != O_constant) | |
5093 | { | |
5094 | inst.error = _("alignment must be constant"); | |
5095 | return PARSE_OPERAND_FAIL; | |
5096 | } | |
5097 | ||
5098 | inst.operands[i].imm = exp.X_add_number << 8; | |
5099 | inst.operands[i].immisalign = 1; | |
5100 | /* Alignments are not pre-indexes. */ | |
5101 | inst.operands[i].preind = 0; | |
5102 | ||
5103 | *str = p; | |
5104 | return PARSE_OPERAND_SUCCESS; | |
5105 | } | |
5106 | ||
c19d1205 ZW |
5107 | /* Parse all forms of an ARM address expression. Information is written |
5108 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5109 | |
c19d1205 | 5110 | Preindexed addressing (.preind=1): |
09d92015 | 5111 | |
c19d1205 ZW |
5112 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5113 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5114 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5115 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5116 | |
c19d1205 | 5117 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5118 | |
c19d1205 | 5119 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5120 | |
c19d1205 ZW |
5121 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5122 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5123 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5124 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5125 | |
c19d1205 | 5126 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5127 | |
c19d1205 | 5128 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5129 | |
c19d1205 | 5130 | Other: |
09d92015 | 5131 | |
c19d1205 ZW |
5132 | [Rn]{!} shorthand for [Rn,#0]{!} |
5133 | =immediate .isreg=0 .reloc.exp=immediate | |
5134 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5135 | |
c19d1205 ZW |
5136 | It is the caller's responsibility to check for addressing modes not |
5137 | supported by the instruction, and to set inst.reloc.type. */ | |
5138 | ||
4962c51a MS |
5139 | static parse_operand_result |
5140 | parse_address_main (char **str, int i, int group_relocations, | |
5141 | group_reloc_type group_type) | |
09d92015 | 5142 | { |
c19d1205 ZW |
5143 | char *p = *str; |
5144 | int reg; | |
09d92015 | 5145 | |
c19d1205 | 5146 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5147 | { |
c19d1205 ZW |
5148 | if (skip_past_char (&p, '=') == FAIL) |
5149 | { | |
974da60d | 5150 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5151 | inst.reloc.pc_rel = 1; |
5152 | inst.operands[i].reg = REG_PC; | |
5153 | inst.operands[i].isreg = 1; | |
5154 | inst.operands[i].preind = 1; | |
5155 | } | |
974da60d | 5156 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5157 | |
c19d1205 | 5158 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5159 | return PARSE_OPERAND_FAIL; |
09d92015 | 5160 | |
c19d1205 | 5161 | *str = p; |
4962c51a | 5162 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5163 | } |
5164 | ||
dcbf9037 | 5165 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5166 | { |
c19d1205 | 5167 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5168 | return PARSE_OPERAND_FAIL; |
09d92015 | 5169 | } |
c19d1205 ZW |
5170 | inst.operands[i].reg = reg; |
5171 | inst.operands[i].isreg = 1; | |
09d92015 | 5172 | |
c19d1205 | 5173 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5174 | { |
c19d1205 | 5175 | inst.operands[i].preind = 1; |
09d92015 | 5176 | |
c19d1205 ZW |
5177 | if (*p == '+') p++; |
5178 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5179 | ||
dcbf9037 | 5180 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5181 | { |
c19d1205 ZW |
5182 | inst.operands[i].imm = reg; |
5183 | inst.operands[i].immisreg = 1; | |
5184 | ||
5185 | if (skip_past_comma (&p) == SUCCESS) | |
5186 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5187 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5188 | } |
5287ad62 | 5189 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5190 | { |
5191 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5192 | code before we get to see it here. This may be subject to | |
5193 | change. */ | |
5194 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5195 | |
8e560766 MGD |
5196 | if (result != PARSE_OPERAND_SUCCESS) |
5197 | return result; | |
5198 | } | |
c19d1205 ZW |
5199 | else |
5200 | { | |
5201 | if (inst.operands[i].negative) | |
5202 | { | |
5203 | inst.operands[i].negative = 0; | |
5204 | p--; | |
5205 | } | |
4962c51a | 5206 | |
5f4273c7 NC |
5207 | if (group_relocations |
5208 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5209 | { |
5210 | struct group_reloc_table_entry *entry; | |
5211 | ||
5212 | /* Skip over the #: or : sequence. */ | |
5213 | if (*p == '#') | |
5214 | p += 2; | |
5215 | else | |
5216 | p++; | |
5217 | ||
5218 | /* Try to parse a group relocation. Anything else is an | |
5219 | error. */ | |
5220 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5221 | { | |
5222 | inst.error = _("unknown group relocation"); | |
5223 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5224 | } | |
5225 | ||
5226 | /* We now have the group relocation table entry corresponding to | |
5227 | the name in the assembler source. Next, we parse the | |
5228 | expression. */ | |
5229 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5230 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5231 | ||
5232 | /* Record the relocation type. */ | |
5233 | switch (group_type) | |
5234 | { | |
5235 | case GROUP_LDR: | |
21d799b5 | 5236 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5237 | break; |
5238 | ||
5239 | case GROUP_LDRS: | |
21d799b5 | 5240 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5241 | break; |
5242 | ||
5243 | case GROUP_LDC: | |
21d799b5 | 5244 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5245 | break; |
5246 | ||
5247 | default: | |
9c2799c2 | 5248 | gas_assert (0); |
4962c51a MS |
5249 | } |
5250 | ||
5251 | if (inst.reloc.type == 0) | |
5252 | { | |
5253 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5254 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5255 | } | |
5256 | } | |
5257 | else | |
26d97720 NS |
5258 | { |
5259 | char *q = p; | |
5260 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5261 | return PARSE_OPERAND_FAIL; | |
5262 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5263 | if (inst.reloc.exp.X_op == O_constant | |
5264 | && inst.reloc.exp.X_add_number == 0) | |
5265 | { | |
5266 | skip_whitespace (q); | |
5267 | if (*q == '#') | |
5268 | { | |
5269 | q++; | |
5270 | skip_whitespace (q); | |
5271 | } | |
5272 | if (*q == '-') | |
5273 | inst.operands[i].negative = 1; | |
5274 | } | |
5275 | } | |
09d92015 MM |
5276 | } |
5277 | } | |
8e560766 MGD |
5278 | else if (skip_past_char (&p, ':') == SUCCESS) |
5279 | { | |
5280 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5281 | before we get to see it here. This may be subject to change. */ | |
5282 | parse_operand_result result = parse_neon_alignment (&p, i); | |
fa94de6b | 5283 | |
8e560766 MGD |
5284 | if (result != PARSE_OPERAND_SUCCESS) |
5285 | return result; | |
5286 | } | |
09d92015 | 5287 | |
c19d1205 | 5288 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5289 | { |
c19d1205 | 5290 | inst.error = _("']' expected"); |
4962c51a | 5291 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5292 | } |
5293 | ||
c19d1205 ZW |
5294 | if (skip_past_char (&p, '!') == SUCCESS) |
5295 | inst.operands[i].writeback = 1; | |
09d92015 | 5296 | |
c19d1205 | 5297 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5298 | { |
c19d1205 ZW |
5299 | if (skip_past_char (&p, '{') == SUCCESS) |
5300 | { | |
5301 | /* [Rn], {expr} - unindexed, with option */ | |
5302 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5303 | 0, 255, TRUE) == FAIL) |
4962c51a | 5304 | return PARSE_OPERAND_FAIL; |
09d92015 | 5305 | |
c19d1205 ZW |
5306 | if (skip_past_char (&p, '}') == FAIL) |
5307 | { | |
5308 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5309 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5310 | } |
5311 | if (inst.operands[i].preind) | |
5312 | { | |
5313 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5314 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5315 | } |
5316 | *str = p; | |
4962c51a | 5317 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5318 | } |
c19d1205 ZW |
5319 | else |
5320 | { | |
5321 | inst.operands[i].postind = 1; | |
5322 | inst.operands[i].writeback = 1; | |
09d92015 | 5323 | |
c19d1205 ZW |
5324 | if (inst.operands[i].preind) |
5325 | { | |
5326 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5327 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5328 | } |
09d92015 | 5329 | |
c19d1205 ZW |
5330 | if (*p == '+') p++; |
5331 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5332 | |
dcbf9037 | 5333 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5334 | { |
5287ad62 JB |
5335 | /* We might be using the immediate for alignment already. If we |
5336 | are, OR the register number into the low-order bits. */ | |
5337 | if (inst.operands[i].immisalign) | |
5338 | inst.operands[i].imm |= reg; | |
5339 | else | |
5340 | inst.operands[i].imm = reg; | |
c19d1205 | 5341 | inst.operands[i].immisreg = 1; |
a737bd4d | 5342 | |
c19d1205 ZW |
5343 | if (skip_past_comma (&p) == SUCCESS) |
5344 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5345 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5346 | } |
5347 | else | |
5348 | { | |
26d97720 | 5349 | char *q = p; |
c19d1205 ZW |
5350 | if (inst.operands[i].negative) |
5351 | { | |
5352 | inst.operands[i].negative = 0; | |
5353 | p--; | |
5354 | } | |
5355 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5356 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5357 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5358 | if (inst.reloc.exp.X_op == O_constant | |
5359 | && inst.reloc.exp.X_add_number == 0) | |
5360 | { | |
5361 | skip_whitespace (q); | |
5362 | if (*q == '#') | |
5363 | { | |
5364 | q++; | |
5365 | skip_whitespace (q); | |
5366 | } | |
5367 | if (*q == '-') | |
5368 | inst.operands[i].negative = 1; | |
5369 | } | |
c19d1205 ZW |
5370 | } |
5371 | } | |
a737bd4d NC |
5372 | } |
5373 | ||
c19d1205 ZW |
5374 | /* If at this point neither .preind nor .postind is set, we have a |
5375 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5376 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5377 | { | |
5378 | inst.operands[i].preind = 1; | |
5379 | inst.reloc.exp.X_op = O_constant; | |
5380 | inst.reloc.exp.X_add_number = 0; | |
5381 | } | |
5382 | *str = p; | |
4962c51a MS |
5383 | return PARSE_OPERAND_SUCCESS; |
5384 | } | |
5385 | ||
5386 | static int | |
5387 | parse_address (char **str, int i) | |
5388 | { | |
21d799b5 | 5389 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5390 | ? SUCCESS : FAIL; |
5391 | } | |
5392 | ||
5393 | static parse_operand_result | |
5394 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5395 | { | |
5396 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5397 | } |
5398 | ||
b6895b4f PB |
5399 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5400 | static int | |
5401 | parse_half (char **str) | |
5402 | { | |
5403 | char * p; | |
5f4273c7 | 5404 | |
b6895b4f PB |
5405 | p = *str; |
5406 | skip_past_char (&p, '#'); | |
5f4273c7 | 5407 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5408 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5409 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5410 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5411 | ||
5412 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5413 | { | |
5414 | p += 9; | |
5f4273c7 | 5415 | skip_whitespace (p); |
b6895b4f PB |
5416 | } |
5417 | ||
5418 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5419 | return FAIL; | |
5420 | ||
5421 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5422 | { | |
5423 | if (inst.reloc.exp.X_op != O_constant) | |
5424 | { | |
5425 | inst.error = _("constant expression expected"); | |
5426 | return FAIL; | |
5427 | } | |
5428 | if (inst.reloc.exp.X_add_number < 0 | |
5429 | || inst.reloc.exp.X_add_number > 0xffff) | |
5430 | { | |
5431 | inst.error = _("immediate value out of range"); | |
5432 | return FAIL; | |
5433 | } | |
5434 | } | |
5435 | *str = p; | |
5436 | return SUCCESS; | |
5437 | } | |
5438 | ||
c19d1205 | 5439 | /* Miscellaneous. */ |
a737bd4d | 5440 | |
c19d1205 ZW |
5441 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5442 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5443 | static int | |
d2cd1205 | 5444 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5445 | { |
c19d1205 ZW |
5446 | char *p; |
5447 | unsigned long psr_field; | |
62b3e311 PB |
5448 | const struct asm_psr *psr; |
5449 | char *start; | |
d2cd1205 | 5450 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5451 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5452 | |
a4482bb6 NC |
5453 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5454 | be TRUE, but we want to ignore it in this case as we are building for any | |
5455 | CPU type, including non-m variants. */ | |
5456 | if (selected_cpu.core == arm_arch_any.core) | |
5457 | m_profile = FALSE; | |
5458 | ||
c19d1205 ZW |
5459 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5460 | feature for ease of use and backwards compatibility. */ | |
5461 | p = *str; | |
62b3e311 | 5462 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5463 | { |
5464 | if (m_profile) | |
5465 | goto unsupported_psr; | |
fa94de6b | 5466 | |
d2cd1205 JB |
5467 | psr_field = SPSR_BIT; |
5468 | } | |
5469 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5470 | { | |
5471 | if (m_profile) | |
5472 | goto unsupported_psr; | |
5473 | ||
5474 | psr_field = 0; | |
5475 | } | |
5476 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5477 | { | |
5478 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5479 | and ARMv7-R architecture CPUs. */ | |
5480 | is_apsr = TRUE; | |
5481 | psr_field = 0; | |
5482 | } | |
5483 | else if (m_profile) | |
62b3e311 PB |
5484 | { |
5485 | start = p; | |
5486 | do | |
5487 | p++; | |
5488 | while (ISALNUM (*p) || *p == '_'); | |
5489 | ||
d2cd1205 JB |
5490 | if (strncasecmp (start, "iapsr", 5) == 0 |
5491 | || strncasecmp (start, "eapsr", 5) == 0 | |
5492 | || strncasecmp (start, "xpsr", 4) == 0 | |
5493 | || strncasecmp (start, "psr", 3) == 0) | |
5494 | p = start + strcspn (start, "rR") + 1; | |
5495 | ||
21d799b5 NC |
5496 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5497 | p - start); | |
d2cd1205 | 5498 | |
62b3e311 PB |
5499 | if (!psr) |
5500 | return FAIL; | |
09d92015 | 5501 | |
d2cd1205 JB |
5502 | /* If APSR is being written, a bitfield may be specified. Note that |
5503 | APSR itself is handled above. */ | |
5504 | if (psr->field <= 3) | |
5505 | { | |
5506 | psr_field = psr->field; | |
5507 | is_apsr = TRUE; | |
5508 | goto check_suffix; | |
5509 | } | |
5510 | ||
62b3e311 | 5511 | *str = p; |
d2cd1205 JB |
5512 | /* M-profile MSR instructions have the mask field set to "10", except |
5513 | *PSR variants which modify APSR, which may use a different mask (and | |
5514 | have been handled already). Do that by setting the PSR_f field | |
5515 | here. */ | |
5516 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5517 | } |
d2cd1205 JB |
5518 | else |
5519 | goto unsupported_psr; | |
09d92015 | 5520 | |
62b3e311 | 5521 | p += 4; |
d2cd1205 | 5522 | check_suffix: |
c19d1205 ZW |
5523 | if (*p == '_') |
5524 | { | |
5525 | /* A suffix follows. */ | |
c19d1205 ZW |
5526 | p++; |
5527 | start = p; | |
a737bd4d | 5528 | |
c19d1205 ZW |
5529 | do |
5530 | p++; | |
5531 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5532 | |
d2cd1205 JB |
5533 | if (is_apsr) |
5534 | { | |
5535 | /* APSR uses a notation for bits, rather than fields. */ | |
5536 | unsigned int nzcvq_bits = 0; | |
5537 | unsigned int g_bit = 0; | |
5538 | char *bit; | |
fa94de6b | 5539 | |
d2cd1205 JB |
5540 | for (bit = start; bit != p; bit++) |
5541 | { | |
5542 | switch (TOLOWER (*bit)) | |
5543 | { | |
5544 | case 'n': | |
5545 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5546 | break; | |
5547 | ||
5548 | case 'z': | |
5549 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5550 | break; | |
5551 | ||
5552 | case 'c': | |
5553 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5554 | break; | |
5555 | ||
5556 | case 'v': | |
5557 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5558 | break; | |
fa94de6b | 5559 | |
d2cd1205 JB |
5560 | case 'q': |
5561 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5562 | break; | |
fa94de6b | 5563 | |
d2cd1205 JB |
5564 | case 'g': |
5565 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5566 | break; | |
fa94de6b | 5567 | |
d2cd1205 JB |
5568 | default: |
5569 | inst.error = _("unexpected bit specified after APSR"); | |
5570 | return FAIL; | |
5571 | } | |
5572 | } | |
fa94de6b | 5573 | |
d2cd1205 JB |
5574 | if (nzcvq_bits == 0x1f) |
5575 | psr_field |= PSR_f; | |
fa94de6b | 5576 | |
d2cd1205 JB |
5577 | if (g_bit == 0x1) |
5578 | { | |
5579 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
5580 | { | |
5581 | inst.error = _("selected processor does not " | |
5582 | "support DSP extension"); | |
5583 | return FAIL; | |
5584 | } | |
5585 | ||
5586 | psr_field |= PSR_s; | |
5587 | } | |
fa94de6b | 5588 | |
d2cd1205 JB |
5589 | if ((nzcvq_bits & 0x20) != 0 |
5590 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5591 | || (g_bit & 0x2) != 0) | |
5592 | { | |
5593 | inst.error = _("bad bitmask specified after APSR"); | |
5594 | return FAIL; | |
5595 | } | |
5596 | } | |
5597 | else | |
5598 | { | |
5599 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, | |
5600 | p - start); | |
5601 | if (!psr) | |
5602 | goto error; | |
a737bd4d | 5603 | |
d2cd1205 JB |
5604 | psr_field |= psr->field; |
5605 | } | |
a737bd4d | 5606 | } |
c19d1205 | 5607 | else |
a737bd4d | 5608 | { |
c19d1205 ZW |
5609 | if (ISALNUM (*p)) |
5610 | goto error; /* Garbage after "[CS]PSR". */ | |
5611 | ||
d2cd1205 JB |
5612 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
5613 | is deprecated, but allow it anyway. */ | |
5614 | if (is_apsr && lhs) | |
5615 | { | |
5616 | psr_field |= PSR_f; | |
5617 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5618 | "deprecated")); | |
5619 | } | |
5620 | else if (!m_profile) | |
5621 | /* These bits are never right for M-profile devices: don't set them | |
5622 | (only code paths which read/write APSR reach here). */ | |
5623 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5624 | } |
c19d1205 ZW |
5625 | *str = p; |
5626 | return psr_field; | |
a737bd4d | 5627 | |
d2cd1205 JB |
5628 | unsupported_psr: |
5629 | inst.error = _("selected processor does not support requested special " | |
5630 | "purpose register"); | |
5631 | return FAIL; | |
5632 | ||
c19d1205 ZW |
5633 | error: |
5634 | inst.error = _("flag for {c}psr instruction expected"); | |
5635 | return FAIL; | |
a737bd4d NC |
5636 | } |
5637 | ||
c19d1205 ZW |
5638 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5639 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5640 | |
c19d1205 ZW |
5641 | static int |
5642 | parse_cps_flags (char **str) | |
a737bd4d | 5643 | { |
c19d1205 ZW |
5644 | int val = 0; |
5645 | int saw_a_flag = 0; | |
5646 | char *s = *str; | |
a737bd4d | 5647 | |
c19d1205 ZW |
5648 | for (;;) |
5649 | switch (*s++) | |
5650 | { | |
5651 | case '\0': case ',': | |
5652 | goto done; | |
a737bd4d | 5653 | |
c19d1205 ZW |
5654 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5655 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5656 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5657 | |
c19d1205 ZW |
5658 | default: |
5659 | inst.error = _("unrecognized CPS flag"); | |
5660 | return FAIL; | |
5661 | } | |
a737bd4d | 5662 | |
c19d1205 ZW |
5663 | done: |
5664 | if (saw_a_flag == 0) | |
a737bd4d | 5665 | { |
c19d1205 ZW |
5666 | inst.error = _("missing CPS flags"); |
5667 | return FAIL; | |
a737bd4d | 5668 | } |
a737bd4d | 5669 | |
c19d1205 ZW |
5670 | *str = s - 1; |
5671 | return val; | |
a737bd4d NC |
5672 | } |
5673 | ||
c19d1205 ZW |
5674 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5675 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5676 | |
5677 | static int | |
c19d1205 | 5678 | parse_endian_specifier (char **str) |
a737bd4d | 5679 | { |
c19d1205 ZW |
5680 | int little_endian; |
5681 | char *s = *str; | |
a737bd4d | 5682 | |
c19d1205 ZW |
5683 | if (strncasecmp (s, "BE", 2)) |
5684 | little_endian = 0; | |
5685 | else if (strncasecmp (s, "LE", 2)) | |
5686 | little_endian = 1; | |
5687 | else | |
a737bd4d | 5688 | { |
c19d1205 | 5689 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5690 | return FAIL; |
5691 | } | |
5692 | ||
c19d1205 | 5693 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5694 | { |
c19d1205 | 5695 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5696 | return FAIL; |
5697 | } | |
5698 | ||
c19d1205 ZW |
5699 | *str = s + 2; |
5700 | return little_endian; | |
5701 | } | |
a737bd4d | 5702 | |
c19d1205 ZW |
5703 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5704 | value suitable for poking into the rotate field of an sxt or sxta | |
5705 | instruction, or FAIL on error. */ | |
5706 | ||
5707 | static int | |
5708 | parse_ror (char **str) | |
5709 | { | |
5710 | int rot; | |
5711 | char *s = *str; | |
5712 | ||
5713 | if (strncasecmp (s, "ROR", 3) == 0) | |
5714 | s += 3; | |
5715 | else | |
a737bd4d | 5716 | { |
c19d1205 | 5717 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5718 | return FAIL; |
5719 | } | |
c19d1205 ZW |
5720 | |
5721 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5722 | return FAIL; | |
5723 | ||
5724 | switch (rot) | |
a737bd4d | 5725 | { |
c19d1205 ZW |
5726 | case 0: *str = s; return 0x0; |
5727 | case 8: *str = s; return 0x1; | |
5728 | case 16: *str = s; return 0x2; | |
5729 | case 24: *str = s; return 0x3; | |
5730 | ||
5731 | default: | |
5732 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5733 | return FAIL; |
5734 | } | |
c19d1205 | 5735 | } |
a737bd4d | 5736 | |
c19d1205 ZW |
5737 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5738 | range 0 .. 14, or FAIL. */ | |
5739 | static int | |
5740 | parse_cond (char **str) | |
5741 | { | |
c462b453 | 5742 | char *q; |
c19d1205 | 5743 | const struct asm_cond *c; |
c462b453 PB |
5744 | int n; |
5745 | /* Condition codes are always 2 characters, so matching up to | |
5746 | 3 characters is sufficient. */ | |
5747 | char cond[3]; | |
a737bd4d | 5748 | |
c462b453 PB |
5749 | q = *str; |
5750 | n = 0; | |
5751 | while (ISALPHA (*q) && n < 3) | |
5752 | { | |
e07e6e58 | 5753 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5754 | q++; |
5755 | n++; | |
5756 | } | |
a737bd4d | 5757 | |
21d799b5 | 5758 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5759 | if (!c) |
a737bd4d | 5760 | { |
c19d1205 | 5761 | inst.error = _("condition required"); |
a737bd4d NC |
5762 | return FAIL; |
5763 | } | |
5764 | ||
c19d1205 ZW |
5765 | *str = q; |
5766 | return c->value; | |
5767 | } | |
5768 | ||
62b3e311 PB |
5769 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5770 | option, or FAIL. */ | |
5771 | static int | |
5772 | parse_barrier (char **str) | |
5773 | { | |
5774 | char *p, *q; | |
5775 | const struct asm_barrier_opt *o; | |
5776 | ||
5777 | p = q = *str; | |
5778 | while (ISALPHA (*q)) | |
5779 | q++; | |
5780 | ||
21d799b5 NC |
5781 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5782 | q - p); | |
62b3e311 PB |
5783 | if (!o) |
5784 | return FAIL; | |
5785 | ||
5786 | *str = q; | |
5787 | return o->value; | |
5788 | } | |
5789 | ||
92e90b6e PB |
5790 | /* Parse the operands of a table branch instruction. Similar to a memory |
5791 | operand. */ | |
5792 | static int | |
5793 | parse_tb (char **str) | |
5794 | { | |
5795 | char * p = *str; | |
5796 | int reg; | |
5797 | ||
5798 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5799 | { |
5800 | inst.error = _("'[' expected"); | |
5801 | return FAIL; | |
5802 | } | |
92e90b6e | 5803 | |
dcbf9037 | 5804 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5805 | { |
5806 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5807 | return FAIL; | |
5808 | } | |
5809 | inst.operands[0].reg = reg; | |
5810 | ||
5811 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5812 | { |
5813 | inst.error = _("',' expected"); | |
5814 | return FAIL; | |
5815 | } | |
5f4273c7 | 5816 | |
dcbf9037 | 5817 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5818 | { |
5819 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5820 | return FAIL; | |
5821 | } | |
5822 | inst.operands[0].imm = reg; | |
5823 | ||
5824 | if (skip_past_comma (&p) == SUCCESS) | |
5825 | { | |
5826 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5827 | return FAIL; | |
5828 | if (inst.reloc.exp.X_add_number != 1) | |
5829 | { | |
5830 | inst.error = _("invalid shift"); | |
5831 | return FAIL; | |
5832 | } | |
5833 | inst.operands[0].shifted = 1; | |
5834 | } | |
5835 | ||
5836 | if (skip_past_char (&p, ']') == FAIL) | |
5837 | { | |
5838 | inst.error = _("']' expected"); | |
5839 | return FAIL; | |
5840 | } | |
5841 | *str = p; | |
5842 | return SUCCESS; | |
5843 | } | |
5844 | ||
5287ad62 JB |
5845 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5846 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5847 | Up to four operands may be read; this function handles setting the |
5848 | ".present" field for each read operand itself. | |
5287ad62 JB |
5849 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5850 | else returns FAIL. */ | |
5851 | ||
5852 | static int | |
5853 | parse_neon_mov (char **str, int *which_operand) | |
5854 | { | |
5855 | int i = *which_operand, val; | |
5856 | enum arm_reg_type rtype; | |
5857 | char *ptr = *str; | |
dcbf9037 | 5858 | struct neon_type_el optype; |
5f4273c7 | 5859 | |
dcbf9037 | 5860 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5861 | { |
5862 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5863 | inst.operands[i].reg = val; | |
5864 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5865 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5866 | inst.operands[i++].present = 1; |
5867 | ||
5868 | if (skip_past_comma (&ptr) == FAIL) | |
5869 | goto wanted_comma; | |
5f4273c7 | 5870 | |
dcbf9037 | 5871 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5872 | goto wanted_arm; |
5f4273c7 | 5873 | |
5287ad62 JB |
5874 | inst.operands[i].reg = val; |
5875 | inst.operands[i].isreg = 1; | |
5876 | inst.operands[i].present = 1; | |
5877 | } | |
037e8744 | 5878 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5879 | != FAIL) |
5287ad62 JB |
5880 | { |
5881 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5882 | if (skip_past_comma (&ptr) == FAIL) | |
5883 | goto wanted_comma; | |
5f4273c7 | 5884 | |
5287ad62 JB |
5885 | inst.operands[i].reg = val; |
5886 | inst.operands[i].isreg = 1; | |
5887 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5888 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5889 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5890 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5891 | inst.operands[i++].present = 1; |
5892 | ||
dcbf9037 | 5893 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5894 | { |
037e8744 JB |
5895 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5896 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5897 | inst.operands[i].reg = val; |
5898 | inst.operands[i].isreg = 1; | |
037e8744 | 5899 | inst.operands[i].present = 1; |
5287ad62 JB |
5900 | |
5901 | if (rtype == REG_TYPE_NQ) | |
5902 | { | |
dcbf9037 | 5903 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5904 | return FAIL; |
5905 | } | |
037e8744 JB |
5906 | else if (rtype != REG_TYPE_VFS) |
5907 | { | |
5908 | i++; | |
5909 | if (skip_past_comma (&ptr) == FAIL) | |
5910 | goto wanted_comma; | |
5911 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5912 | goto wanted_arm; | |
5913 | inst.operands[i].reg = val; | |
5914 | inst.operands[i].isreg = 1; | |
5915 | inst.operands[i].present = 1; | |
5916 | } | |
5287ad62 | 5917 | } |
037e8744 JB |
5918 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5919 | &optype)) != FAIL) | |
5287ad62 JB |
5920 | { |
5921 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5922 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5923 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5924 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5925 | |
5926 | inst.operands[i].reg = val; | |
5927 | inst.operands[i].isreg = 1; | |
5928 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5929 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5930 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5931 | inst.operands[i].vectype = optype; |
5287ad62 | 5932 | inst.operands[i].present = 1; |
5f4273c7 | 5933 | |
037e8744 JB |
5934 | if (skip_past_comma (&ptr) == SUCCESS) |
5935 | { | |
5936 | /* Case 15. */ | |
5937 | i++; | |
5938 | ||
5939 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5940 | goto wanted_arm; | |
5941 | ||
5942 | inst.operands[i].reg = val; | |
5943 | inst.operands[i].isreg = 1; | |
5944 | inst.operands[i++].present = 1; | |
5f4273c7 | 5945 | |
037e8744 JB |
5946 | if (skip_past_comma (&ptr) == FAIL) |
5947 | goto wanted_comma; | |
5f4273c7 | 5948 | |
037e8744 JB |
5949 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5950 | goto wanted_arm; | |
5f4273c7 | 5951 | |
037e8744 JB |
5952 | inst.operands[i].reg = val; |
5953 | inst.operands[i].isreg = 1; | |
1b11b49f | 5954 | inst.operands[i].present = 1; |
037e8744 | 5955 | } |
5287ad62 | 5956 | } |
4641781c PB |
5957 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5958 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5959 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5960 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5961 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5962 | inst.operands[i].immisfloat = 1; | |
5963 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5964 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5965 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5966 | ; | |
5287ad62 JB |
5967 | else |
5968 | { | |
dcbf9037 | 5969 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5970 | return FAIL; |
5971 | } | |
5972 | } | |
dcbf9037 | 5973 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5974 | { |
5975 | /* Cases 6, 7. */ | |
5976 | inst.operands[i].reg = val; | |
5977 | inst.operands[i].isreg = 1; | |
5978 | inst.operands[i++].present = 1; | |
5f4273c7 | 5979 | |
5287ad62 JB |
5980 | if (skip_past_comma (&ptr) == FAIL) |
5981 | goto wanted_comma; | |
5f4273c7 | 5982 | |
dcbf9037 | 5983 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5984 | { |
5985 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5986 | inst.operands[i].reg = val; | |
5987 | inst.operands[i].isscalar = 1; | |
5988 | inst.operands[i].present = 1; | |
dcbf9037 | 5989 | inst.operands[i].vectype = optype; |
5287ad62 | 5990 | } |
dcbf9037 | 5991 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5992 | { |
5993 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5994 | inst.operands[i].reg = val; | |
5995 | inst.operands[i].isreg = 1; | |
5996 | inst.operands[i++].present = 1; | |
5f4273c7 | 5997 | |
5287ad62 JB |
5998 | if (skip_past_comma (&ptr) == FAIL) |
5999 | goto wanted_comma; | |
5f4273c7 | 6000 | |
037e8744 | 6001 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 6002 | == FAIL) |
5287ad62 | 6003 | { |
037e8744 | 6004 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
6005 | return FAIL; |
6006 | } | |
6007 | ||
6008 | inst.operands[i].reg = val; | |
6009 | inst.operands[i].isreg = 1; | |
037e8744 JB |
6010 | inst.operands[i].isvec = 1; |
6011 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 6012 | inst.operands[i].vectype = optype; |
5287ad62 | 6013 | inst.operands[i].present = 1; |
5f4273c7 | 6014 | |
037e8744 JB |
6015 | if (rtype == REG_TYPE_VFS) |
6016 | { | |
6017 | /* Case 14. */ | |
6018 | i++; | |
6019 | if (skip_past_comma (&ptr) == FAIL) | |
6020 | goto wanted_comma; | |
6021 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6022 | &optype)) == FAIL) | |
6023 | { | |
6024 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6025 | return FAIL; | |
6026 | } | |
6027 | inst.operands[i].reg = val; | |
6028 | inst.operands[i].isreg = 1; | |
6029 | inst.operands[i].isvec = 1; | |
6030 | inst.operands[i].issingle = 1; | |
6031 | inst.operands[i].vectype = optype; | |
6032 | inst.operands[i].present = 1; | |
6033 | } | |
6034 | } | |
6035 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
6036 | != FAIL) | |
6037 | { | |
6038 | /* Case 13. */ | |
6039 | inst.operands[i].reg = val; | |
6040 | inst.operands[i].isreg = 1; | |
6041 | inst.operands[i].isvec = 1; | |
6042 | inst.operands[i].issingle = 1; | |
6043 | inst.operands[i].vectype = optype; | |
1b11b49f | 6044 | inst.operands[i].present = 1; |
5287ad62 JB |
6045 | } |
6046 | } | |
6047 | else | |
6048 | { | |
dcbf9037 | 6049 | first_error (_("parse error")); |
5287ad62 JB |
6050 | return FAIL; |
6051 | } | |
6052 | ||
6053 | /* Successfully parsed the operands. Update args. */ | |
6054 | *which_operand = i; | |
6055 | *str = ptr; | |
6056 | return SUCCESS; | |
6057 | ||
5f4273c7 | 6058 | wanted_comma: |
dcbf9037 | 6059 | first_error (_("expected comma")); |
5287ad62 | 6060 | return FAIL; |
5f4273c7 NC |
6061 | |
6062 | wanted_arm: | |
dcbf9037 | 6063 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6064 | return FAIL; |
5287ad62 JB |
6065 | } |
6066 | ||
5be8be5d DG |
6067 | /* Use this macro when the operand constraints are different |
6068 | for ARM and THUMB (e.g. ldrd). */ | |
6069 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6070 | ((arm_operand) | ((thumb_operand) << 16)) | |
6071 | ||
c19d1205 ZW |
6072 | /* Matcher codes for parse_operands. */ |
6073 | enum operand_parse_code | |
6074 | { | |
6075 | OP_stop, /* end of line */ | |
6076 | ||
6077 | OP_RR, /* ARM register */ | |
6078 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6079 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6080 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
fa94de6b | 6081 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
55881a11 | 6082 | optional trailing ! */ |
c19d1205 ZW |
6083 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6084 | OP_RCP, /* Coprocessor number */ | |
6085 | OP_RCN, /* Coprocessor register */ | |
6086 | OP_RF, /* FPA register */ | |
6087 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6088 | OP_RVD, /* VFP double precision register (0..15) */ |
6089 | OP_RND, /* Neon double precision register (0..31) */ | |
6090 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6091 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6092 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6093 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6094 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6095 | OP_RVC, /* VFP control register */ |
6096 | OP_RMF, /* Maverick F register */ | |
6097 | OP_RMD, /* Maverick D register */ | |
6098 | OP_RMFX, /* Maverick FX register */ | |
6099 | OP_RMDX, /* Maverick DX register */ | |
6100 | OP_RMAX, /* Maverick AX register */ | |
6101 | OP_RMDS, /* Maverick DSPSC register */ | |
6102 | OP_RIWR, /* iWMMXt wR register */ | |
6103 | OP_RIWC, /* iWMMXt wC register */ | |
6104 | OP_RIWG, /* iWMMXt wCG register */ | |
6105 | OP_RXA, /* XScale accumulator register */ | |
6106 | ||
6107 | OP_REGLST, /* ARM register list */ | |
6108 | OP_VRSLST, /* VFP single-precision register list */ | |
6109 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6110 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6111 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6112 | OP_NSTRLST, /* Neon element/structure list */ | |
6113 | ||
5287ad62 | 6114 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6115 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 6116 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6117 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6118 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6119 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6120 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6121 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6122 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6123 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6124 | |
6125 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6126 | OP_I7, /* immediate value 0 .. 7 */ |
6127 | OP_I15, /* 0 .. 15 */ | |
6128 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6129 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6130 | OP_I31, /* 0 .. 31 */ |
6131 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6132 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6133 | OP_I32z, /* 0 .. 32 */ |
6134 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6135 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6136 | OP_I64, /* 1 .. 64 */ |
6137 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6138 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6139 | |
6140 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6141 | OP_I7b, /* 0 .. 7 */ | |
6142 | OP_I15b, /* 0 .. 15 */ | |
6143 | OP_I31b, /* 0 .. 31 */ | |
6144 | ||
6145 | OP_SH, /* shifter operand */ | |
4962c51a | 6146 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6147 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6148 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6149 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6150 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6151 | OP_EXP, /* arbitrary expression */ |
6152 | OP_EXPi, /* same, with optional immediate prefix */ | |
6153 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6154 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6155 | |
6156 | OP_CPSF, /* CPS flags */ | |
6157 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6158 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6159 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6160 | OP_COND, /* conditional code */ |
92e90b6e | 6161 | OP_TB, /* Table branch. */ |
c19d1205 | 6162 | |
037e8744 JB |
6163 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6164 | ||
c19d1205 ZW |
6165 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6166 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6167 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6168 | OP_RF_IF, /* FPA register or immediate */ | |
6169 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6170 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6171 | |
6172 | /* Optional operands. */ | |
6173 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6174 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6175 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6176 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6177 | OP_oIffffb, /* 0 .. 65535 */ |
6178 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6179 | ||
6180 | OP_oRR, /* ARM register */ | |
6181 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6182 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6183 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6184 | OP_oRND, /* Optional Neon double precision register */ |
6185 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6186 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6187 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6188 | OP_oSHll, /* LSL immediate */ |
6189 | OP_oSHar, /* ASR immediate */ | |
6190 | OP_oSHllar, /* LSL or ASR immediate */ | |
6191 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6192 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6193 | |
5be8be5d DG |
6194 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6195 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6196 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6197 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6198 | ||
c19d1205 ZW |
6199 | OP_FIRST_OPTIONAL = OP_oI7b |
6200 | }; | |
a737bd4d | 6201 | |
c19d1205 ZW |
6202 | /* Generic instruction operand parser. This does no encoding and no |
6203 | semantic validation; it merely squirrels values away in the inst | |
6204 | structure. Returns SUCCESS or FAIL depending on whether the | |
6205 | specified grammar matched. */ | |
6206 | static int | |
5be8be5d | 6207 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6208 | { |
5be8be5d | 6209 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6210 | char *backtrack_pos = 0; |
6211 | const char *backtrack_error = 0; | |
99aad254 | 6212 | int i, val = 0, backtrack_index = 0; |
5287ad62 | 6213 | enum arm_reg_type rtype; |
4962c51a | 6214 | parse_operand_result result; |
5be8be5d | 6215 | unsigned int op_parse_code; |
c19d1205 | 6216 | |
e07e6e58 NC |
6217 | #define po_char_or_fail(chr) \ |
6218 | do \ | |
6219 | { \ | |
6220 | if (skip_past_char (&str, chr) == FAIL) \ | |
6221 | goto bad_args; \ | |
6222 | } \ | |
6223 | while (0) | |
c19d1205 | 6224 | |
e07e6e58 NC |
6225 | #define po_reg_or_fail(regtype) \ |
6226 | do \ | |
dcbf9037 | 6227 | { \ |
e07e6e58 NC |
6228 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
6229 | & inst.operands[i].vectype); \ | |
6230 | if (val == FAIL) \ | |
6231 | { \ | |
6232 | first_error (_(reg_expected_msgs[regtype])); \ | |
6233 | goto failure; \ | |
6234 | } \ | |
6235 | inst.operands[i].reg = val; \ | |
6236 | inst.operands[i].isreg = 1; \ | |
6237 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6238 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6239 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6240 | || rtype == REG_TYPE_VFD \ | |
6241 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6242 | } \ |
e07e6e58 NC |
6243 | while (0) |
6244 | ||
6245 | #define po_reg_or_goto(regtype, label) \ | |
6246 | do \ | |
6247 | { \ | |
6248 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6249 | & inst.operands[i].vectype); \ | |
6250 | if (val == FAIL) \ | |
6251 | goto label; \ | |
dcbf9037 | 6252 | \ |
e07e6e58 NC |
6253 | inst.operands[i].reg = val; \ |
6254 | inst.operands[i].isreg = 1; \ | |
6255 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6256 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6257 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6258 | || rtype == REG_TYPE_VFD \ | |
6259 | || rtype == REG_TYPE_NQ); \ | |
6260 | } \ | |
6261 | while (0) | |
6262 | ||
6263 | #define po_imm_or_fail(min, max, popt) \ | |
6264 | do \ | |
6265 | { \ | |
6266 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6267 | goto failure; \ | |
6268 | inst.operands[i].imm = val; \ | |
6269 | } \ | |
6270 | while (0) | |
6271 | ||
6272 | #define po_scalar_or_goto(elsz, label) \ | |
6273 | do \ | |
6274 | { \ | |
6275 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6276 | if (val == FAIL) \ | |
6277 | goto label; \ | |
6278 | inst.operands[i].reg = val; \ | |
6279 | inst.operands[i].isscalar = 1; \ | |
6280 | } \ | |
6281 | while (0) | |
6282 | ||
6283 | #define po_misc_or_fail(expr) \ | |
6284 | do \ | |
6285 | { \ | |
6286 | if (expr) \ | |
6287 | goto failure; \ | |
6288 | } \ | |
6289 | while (0) | |
6290 | ||
6291 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6292 | do \ | |
6293 | { \ | |
6294 | result = expr; \ | |
6295 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6296 | backtrack_pos = 0; \ | |
6297 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6298 | goto failure; \ | |
6299 | } \ | |
6300 | while (0) | |
4962c51a | 6301 | |
52e7f43d RE |
6302 | #define po_barrier_or_imm(str) \ |
6303 | do \ | |
6304 | { \ | |
6305 | val = parse_barrier (&str); \ | |
6306 | if (val == FAIL) \ | |
6307 | { \ | |
6308 | if (ISALPHA (*str)) \ | |
6309 | goto failure; \ | |
6310 | else \ | |
6311 | goto immediate; \ | |
6312 | } \ | |
6313 | else \ | |
6314 | { \ | |
6315 | if ((inst.instruction & 0xf0) == 0x60 \ | |
6316 | && val != 0xf) \ | |
6317 | { \ | |
6318 | /* ISB can only take SY as an option. */ \ | |
6319 | inst.error = _("invalid barrier type"); \ | |
6320 | goto failure; \ | |
6321 | } \ | |
6322 | } \ | |
6323 | } \ | |
6324 | while (0) | |
6325 | ||
c19d1205 ZW |
6326 | skip_whitespace (str); |
6327 | ||
6328 | for (i = 0; upat[i] != OP_stop; i++) | |
6329 | { | |
5be8be5d DG |
6330 | op_parse_code = upat[i]; |
6331 | if (op_parse_code >= 1<<16) | |
6332 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6333 | : (op_parse_code & ((1<<16)-1)); | |
6334 | ||
6335 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6336 | { |
6337 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6338 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6339 | backtrack_pos = str; |
6340 | backtrack_error = inst.error; | |
6341 | backtrack_index = i; | |
6342 | } | |
6343 | ||
b6702015 | 6344 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6345 | po_char_or_fail (','); |
6346 | ||
5be8be5d | 6347 | switch (op_parse_code) |
c19d1205 ZW |
6348 | { |
6349 | /* Registers */ | |
6350 | case OP_oRRnpc: | |
5be8be5d | 6351 | case OP_oRRnpcsp: |
c19d1205 | 6352 | case OP_RRnpc: |
5be8be5d | 6353 | case OP_RRnpcsp: |
c19d1205 ZW |
6354 | case OP_oRR: |
6355 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6356 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6357 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6358 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6359 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6360 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6361 | case OP_oRND: |
6362 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6363 | case OP_RVC: |
6364 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6365 | break; | |
6366 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6367 | coproc_reg: | |
6368 | po_reg_or_fail (REG_TYPE_CN); | |
6369 | break; | |
c19d1205 ZW |
6370 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6371 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6372 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6373 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6374 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6375 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6376 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6377 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6378 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6379 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6380 | case OP_oRNQ: |
6381 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6382 | case OP_oRNDQ: | |
6383 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6384 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6385 | case OP_oRNSDQ: | |
6386 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6387 | |
6388 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6389 | scalars are accepted here, so deal with those in later code. */ | |
6390 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6391 | ||
5287ad62 JB |
6392 | case OP_RNDQ_I0: |
6393 | { | |
6394 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6395 | break; | |
6396 | try_imm0: | |
6397 | po_imm_or_fail (0, 0, TRUE); | |
6398 | } | |
6399 | break; | |
6400 | ||
037e8744 JB |
6401 | case OP_RVSD_I0: |
6402 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6403 | break; | |
6404 | ||
5287ad62 JB |
6405 | case OP_RR_RNSC: |
6406 | { | |
6407 | po_scalar_or_goto (8, try_rr); | |
6408 | break; | |
6409 | try_rr: | |
6410 | po_reg_or_fail (REG_TYPE_RN); | |
6411 | } | |
6412 | break; | |
6413 | ||
037e8744 JB |
6414 | case OP_RNSDQ_RNSC: |
6415 | { | |
6416 | po_scalar_or_goto (8, try_nsdq); | |
6417 | break; | |
6418 | try_nsdq: | |
6419 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6420 | } | |
6421 | break; | |
6422 | ||
5287ad62 JB |
6423 | case OP_RNDQ_RNSC: |
6424 | { | |
6425 | po_scalar_or_goto (8, try_ndq); | |
6426 | break; | |
6427 | try_ndq: | |
6428 | po_reg_or_fail (REG_TYPE_NDQ); | |
6429 | } | |
6430 | break; | |
6431 | ||
6432 | case OP_RND_RNSC: | |
6433 | { | |
6434 | po_scalar_or_goto (8, try_vfd); | |
6435 | break; | |
6436 | try_vfd: | |
6437 | po_reg_or_fail (REG_TYPE_VFD); | |
6438 | } | |
6439 | break; | |
6440 | ||
6441 | case OP_VMOV: | |
6442 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6443 | not careful then bad things might happen. */ | |
6444 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6445 | break; | |
6446 | ||
4316f0d2 | 6447 | case OP_RNDQ_Ibig: |
5287ad62 | 6448 | { |
4316f0d2 | 6449 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6450 | break; |
4316f0d2 | 6451 | try_immbig: |
5287ad62 JB |
6452 | /* There's a possibility of getting a 64-bit immediate here, so |
6453 | we need special handling. */ | |
6454 | if (parse_big_immediate (&str, i) == FAIL) | |
6455 | { | |
6456 | inst.error = _("immediate value is out of range"); | |
6457 | goto failure; | |
6458 | } | |
6459 | } | |
6460 | break; | |
6461 | ||
6462 | case OP_RNDQ_I63b: | |
6463 | { | |
6464 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6465 | break; | |
6466 | try_shimm: | |
6467 | po_imm_or_fail (0, 63, TRUE); | |
6468 | } | |
6469 | break; | |
c19d1205 ZW |
6470 | |
6471 | case OP_RRnpcb: | |
6472 | po_char_or_fail ('['); | |
6473 | po_reg_or_fail (REG_TYPE_RN); | |
6474 | po_char_or_fail (']'); | |
6475 | break; | |
a737bd4d | 6476 | |
55881a11 | 6477 | case OP_RRnpctw: |
c19d1205 | 6478 | case OP_RRw: |
b6702015 | 6479 | case OP_oRRw: |
c19d1205 ZW |
6480 | po_reg_or_fail (REG_TYPE_RN); |
6481 | if (skip_past_char (&str, '!') == SUCCESS) | |
6482 | inst.operands[i].writeback = 1; | |
6483 | break; | |
6484 | ||
6485 | /* Immediates */ | |
6486 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6487 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6488 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6489 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6490 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6491 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6492 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6493 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6494 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6495 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6496 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6497 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6498 | |
6499 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6500 | case OP_oI7b: | |
6501 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6502 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6503 | case OP_oI31b: | |
6504 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6505 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
5f1af56b | 6506 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; |
c19d1205 ZW |
6507 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6508 | ||
6509 | /* Immediate variants */ | |
6510 | case OP_oI255c: | |
6511 | po_char_or_fail ('{'); | |
6512 | po_imm_or_fail (0, 255, TRUE); | |
6513 | po_char_or_fail ('}'); | |
6514 | break; | |
6515 | ||
6516 | case OP_I31w: | |
6517 | /* The expression parser chokes on a trailing !, so we have | |
6518 | to find it first and zap it. */ | |
6519 | { | |
6520 | char *s = str; | |
6521 | while (*s && *s != ',') | |
6522 | s++; | |
6523 | if (s[-1] == '!') | |
6524 | { | |
6525 | s[-1] = '\0'; | |
6526 | inst.operands[i].writeback = 1; | |
6527 | } | |
6528 | po_imm_or_fail (0, 31, TRUE); | |
6529 | if (str == s - 1) | |
6530 | str = s; | |
6531 | } | |
6532 | break; | |
6533 | ||
6534 | /* Expressions */ | |
6535 | case OP_EXPi: EXPi: | |
6536 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6537 | GE_OPT_PREFIX)); | |
6538 | break; | |
6539 | ||
6540 | case OP_EXP: | |
6541 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6542 | GE_NO_PREFIX)); | |
6543 | break; | |
6544 | ||
6545 | case OP_EXPr: EXPr: | |
6546 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6547 | GE_NO_PREFIX)); | |
6548 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6549 | { |
c19d1205 ZW |
6550 | val = parse_reloc (&str); |
6551 | if (val == -1) | |
6552 | { | |
6553 | inst.error = _("unrecognized relocation suffix"); | |
6554 | goto failure; | |
6555 | } | |
6556 | else if (val != BFD_RELOC_UNUSED) | |
6557 | { | |
6558 | inst.operands[i].imm = val; | |
6559 | inst.operands[i].hasreloc = 1; | |
6560 | } | |
a737bd4d | 6561 | } |
c19d1205 | 6562 | break; |
a737bd4d | 6563 | |
b6895b4f PB |
6564 | /* Operand for MOVW or MOVT. */ |
6565 | case OP_HALF: | |
6566 | po_misc_or_fail (parse_half (&str)); | |
6567 | break; | |
6568 | ||
e07e6e58 | 6569 | /* Register or expression. */ |
c19d1205 ZW |
6570 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6571 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6572 | |
e07e6e58 | 6573 | /* Register or immediate. */ |
c19d1205 ZW |
6574 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6575 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6576 | |
c19d1205 ZW |
6577 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6578 | IF: | |
6579 | if (!is_immediate_prefix (*str)) | |
6580 | goto bad_args; | |
6581 | str++; | |
6582 | val = parse_fpa_immediate (&str); | |
6583 | if (val == FAIL) | |
6584 | goto failure; | |
6585 | /* FPA immediates are encoded as registers 8-15. | |
6586 | parse_fpa_immediate has already applied the offset. */ | |
6587 | inst.operands[i].reg = val; | |
6588 | inst.operands[i].isreg = 1; | |
6589 | break; | |
09d92015 | 6590 | |
2d447fca JM |
6591 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6592 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6593 | ||
e07e6e58 | 6594 | /* Two kinds of register. */ |
c19d1205 ZW |
6595 | case OP_RIWR_RIWC: |
6596 | { | |
6597 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6598 | if (!rege |
6599 | || (rege->type != REG_TYPE_MMXWR | |
6600 | && rege->type != REG_TYPE_MMXWC | |
6601 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6602 | { |
6603 | inst.error = _("iWMMXt data or control register expected"); | |
6604 | goto failure; | |
6605 | } | |
6606 | inst.operands[i].reg = rege->number; | |
6607 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6608 | } | |
6609 | break; | |
09d92015 | 6610 | |
41adaa5c JM |
6611 | case OP_RIWC_RIWG: |
6612 | { | |
6613 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6614 | if (!rege | |
6615 | || (rege->type != REG_TYPE_MMXWC | |
6616 | && rege->type != REG_TYPE_MMXWCG)) | |
6617 | { | |
6618 | inst.error = _("iWMMXt control register expected"); | |
6619 | goto failure; | |
6620 | } | |
6621 | inst.operands[i].reg = rege->number; | |
6622 | inst.operands[i].isreg = 1; | |
6623 | } | |
6624 | break; | |
6625 | ||
c19d1205 ZW |
6626 | /* Misc */ |
6627 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6628 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6629 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6630 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6631 | case OP_oBARRIER_I15: |
6632 | po_barrier_or_imm (str); break; | |
6633 | immediate: | |
6634 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
6635 | goto failure; | |
6636 | break; | |
c19d1205 | 6637 | |
fa94de6b | 6638 | case OP_wPSR: |
d2cd1205 | 6639 | case OP_rPSR: |
90ec0d68 MGD |
6640 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6641 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6642 | { | |
6643 | inst.error = _("Banked registers are not available with this " | |
6644 | "architecture."); | |
6645 | goto failure; | |
6646 | } | |
6647 | break; | |
d2cd1205 JB |
6648 | try_psr: |
6649 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6650 | break; | |
037e8744 JB |
6651 | |
6652 | case OP_APSR_RR: | |
6653 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6654 | break; | |
6655 | try_apsr: | |
6656 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6657 | instruction). */ | |
6658 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6659 | { | |
6660 | unsigned found = 0; | |
6661 | str += 5; | |
6662 | while (found < 15) | |
6663 | switch (*str++) | |
6664 | { | |
6665 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6666 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6667 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6668 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6669 | default: found = 16; | |
6670 | } | |
6671 | if (found != 15) | |
6672 | goto failure; | |
6673 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6674 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6675 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6676 | } |
6677 | else | |
6678 | goto failure; | |
6679 | break; | |
6680 | ||
92e90b6e PB |
6681 | case OP_TB: |
6682 | po_misc_or_fail (parse_tb (&str)); | |
6683 | break; | |
6684 | ||
e07e6e58 | 6685 | /* Register lists. */ |
c19d1205 ZW |
6686 | case OP_REGLST: |
6687 | val = parse_reg_list (&str); | |
6688 | if (*str == '^') | |
6689 | { | |
6690 | inst.operands[1].writeback = 1; | |
6691 | str++; | |
6692 | } | |
6693 | break; | |
09d92015 | 6694 | |
c19d1205 | 6695 | case OP_VRSLST: |
5287ad62 | 6696 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6697 | break; |
09d92015 | 6698 | |
c19d1205 | 6699 | case OP_VRDLST: |
5287ad62 | 6700 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6701 | break; |
a737bd4d | 6702 | |
037e8744 JB |
6703 | case OP_VRSDLST: |
6704 | /* Allow Q registers too. */ | |
6705 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6706 | REGLIST_NEON_D); | |
6707 | if (val == FAIL) | |
6708 | { | |
6709 | inst.error = NULL; | |
6710 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6711 | REGLIST_VFP_S); | |
6712 | inst.operands[i].issingle = 1; | |
6713 | } | |
6714 | break; | |
6715 | ||
5287ad62 JB |
6716 | case OP_NRDLST: |
6717 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6718 | REGLIST_NEON_D); | |
6719 | break; | |
6720 | ||
6721 | case OP_NSTRLST: | |
dcbf9037 JB |
6722 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6723 | &inst.operands[i].vectype); | |
5287ad62 JB |
6724 | break; |
6725 | ||
c19d1205 ZW |
6726 | /* Addressing modes */ |
6727 | case OP_ADDR: | |
6728 | po_misc_or_fail (parse_address (&str, i)); | |
6729 | break; | |
09d92015 | 6730 | |
4962c51a MS |
6731 | case OP_ADDRGLDR: |
6732 | po_misc_or_fail_no_backtrack ( | |
6733 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6734 | break; | |
6735 | ||
6736 | case OP_ADDRGLDRS: | |
6737 | po_misc_or_fail_no_backtrack ( | |
6738 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6739 | break; | |
6740 | ||
6741 | case OP_ADDRGLDC: | |
6742 | po_misc_or_fail_no_backtrack ( | |
6743 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6744 | break; | |
6745 | ||
c19d1205 ZW |
6746 | case OP_SH: |
6747 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6748 | break; | |
09d92015 | 6749 | |
4962c51a MS |
6750 | case OP_SHG: |
6751 | po_misc_or_fail_no_backtrack ( | |
6752 | parse_shifter_operand_group_reloc (&str, i)); | |
6753 | break; | |
6754 | ||
c19d1205 ZW |
6755 | case OP_oSHll: |
6756 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6757 | break; | |
09d92015 | 6758 | |
c19d1205 ZW |
6759 | case OP_oSHar: |
6760 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6761 | break; | |
09d92015 | 6762 | |
c19d1205 ZW |
6763 | case OP_oSHllar: |
6764 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6765 | break; | |
09d92015 | 6766 | |
c19d1205 | 6767 | default: |
5be8be5d | 6768 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6769 | } |
09d92015 | 6770 | |
c19d1205 ZW |
6771 | /* Various value-based sanity checks and shared operations. We |
6772 | do not signal immediate failures for the register constraints; | |
6773 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6774 | switch (op_parse_code) |
c19d1205 ZW |
6775 | { |
6776 | case OP_oRRnpc: | |
6777 | case OP_RRnpc: | |
6778 | case OP_RRnpcb: | |
6779 | case OP_RRw: | |
b6702015 | 6780 | case OP_oRRw: |
c19d1205 ZW |
6781 | case OP_RRnpc_I0: |
6782 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6783 | inst.error = BAD_PC; | |
6784 | break; | |
09d92015 | 6785 | |
5be8be5d DG |
6786 | case OP_oRRnpcsp: |
6787 | case OP_RRnpcsp: | |
6788 | if (inst.operands[i].isreg) | |
6789 | { | |
6790 | if (inst.operands[i].reg == REG_PC) | |
6791 | inst.error = BAD_PC; | |
6792 | else if (inst.operands[i].reg == REG_SP) | |
6793 | inst.error = BAD_SP; | |
6794 | } | |
6795 | break; | |
6796 | ||
55881a11 | 6797 | case OP_RRnpctw: |
fa94de6b RM |
6798 | if (inst.operands[i].isreg |
6799 | && inst.operands[i].reg == REG_PC | |
55881a11 MGD |
6800 | && (inst.operands[i].writeback || thumb)) |
6801 | inst.error = BAD_PC; | |
6802 | break; | |
6803 | ||
c19d1205 ZW |
6804 | case OP_CPSF: |
6805 | case OP_ENDI: | |
6806 | case OP_oROR: | |
d2cd1205 JB |
6807 | case OP_wPSR: |
6808 | case OP_rPSR: | |
c19d1205 | 6809 | case OP_COND: |
52e7f43d | 6810 | case OP_oBARRIER_I15: |
c19d1205 ZW |
6811 | case OP_REGLST: |
6812 | case OP_VRSLST: | |
6813 | case OP_VRDLST: | |
037e8744 | 6814 | case OP_VRSDLST: |
5287ad62 JB |
6815 | case OP_NRDLST: |
6816 | case OP_NSTRLST: | |
c19d1205 ZW |
6817 | if (val == FAIL) |
6818 | goto failure; | |
6819 | inst.operands[i].imm = val; | |
6820 | break; | |
a737bd4d | 6821 | |
c19d1205 ZW |
6822 | default: |
6823 | break; | |
6824 | } | |
09d92015 | 6825 | |
c19d1205 ZW |
6826 | /* If we get here, this operand was successfully parsed. */ |
6827 | inst.operands[i].present = 1; | |
6828 | continue; | |
09d92015 | 6829 | |
c19d1205 | 6830 | bad_args: |
09d92015 | 6831 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6832 | |
6833 | failure: | |
6834 | if (!backtrack_pos) | |
d252fdde PB |
6835 | { |
6836 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6837 | default here just in case. */ |
d252fdde PB |
6838 | if (!inst.error) |
6839 | inst.error = _("syntax error"); | |
6840 | return FAIL; | |
6841 | } | |
c19d1205 ZW |
6842 | |
6843 | /* Do not backtrack over a trailing optional argument that | |
6844 | absorbed some text. We will only fail again, with the | |
6845 | 'garbage following instruction' error message, which is | |
6846 | probably less helpful than the current one. */ | |
6847 | if (backtrack_index == i && backtrack_pos != str | |
6848 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6849 | { |
6850 | if (!inst.error) | |
6851 | inst.error = _("syntax error"); | |
6852 | return FAIL; | |
6853 | } | |
c19d1205 ZW |
6854 | |
6855 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6856 | str = backtrack_pos; | |
6857 | inst.error = backtrack_error; | |
6858 | inst.operands[backtrack_index].present = 0; | |
6859 | i = backtrack_index; | |
6860 | backtrack_pos = 0; | |
09d92015 | 6861 | } |
09d92015 | 6862 | |
c19d1205 ZW |
6863 | /* Check that we have parsed all the arguments. */ |
6864 | if (*str != '\0' && !inst.error) | |
6865 | inst.error = _("garbage following instruction"); | |
09d92015 | 6866 | |
c19d1205 | 6867 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6868 | } |
6869 | ||
c19d1205 ZW |
6870 | #undef po_char_or_fail |
6871 | #undef po_reg_or_fail | |
6872 | #undef po_reg_or_goto | |
6873 | #undef po_imm_or_fail | |
5287ad62 | 6874 | #undef po_scalar_or_fail |
52e7f43d | 6875 | #undef po_barrier_or_imm |
e07e6e58 | 6876 | |
c19d1205 | 6877 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6878 | #define constraint(expr, err) \ |
6879 | do \ | |
c19d1205 | 6880 | { \ |
e07e6e58 NC |
6881 | if (expr) \ |
6882 | { \ | |
6883 | inst.error = err; \ | |
6884 | return; \ | |
6885 | } \ | |
c19d1205 | 6886 | } \ |
e07e6e58 | 6887 | while (0) |
c19d1205 | 6888 | |
fdfde340 JM |
6889 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6890 | instructions are unpredictable if these registers are used. This | |
6891 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6892 | #define reject_bad_reg(reg) \ | |
6893 | do \ | |
6894 | if (reg == REG_SP || reg == REG_PC) \ | |
6895 | { \ | |
6896 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6897 | return; \ | |
6898 | } \ | |
6899 | while (0) | |
6900 | ||
94206790 MM |
6901 | /* If REG is R13 (the stack pointer), warn that its use is |
6902 | deprecated. */ | |
6903 | #define warn_deprecated_sp(reg) \ | |
6904 | do \ | |
6905 | if (warn_on_deprecated && reg == REG_SP) \ | |
6906 | as_warn (_("use of r13 is deprecated")); \ | |
6907 | while (0) | |
6908 | ||
c19d1205 ZW |
6909 | /* Functions for operand encoding. ARM, then Thumb. */ |
6910 | ||
6911 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6912 | ||
6913 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6914 | return the encoded form. Otherwise, return FAIL. */ | |
6915 | ||
6916 | static unsigned int | |
6917 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6918 | { |
c19d1205 ZW |
6919 | unsigned int a, i; |
6920 | ||
6921 | for (i = 0; i < 32; i += 2) | |
6922 | if ((a = rotate_left (val, i)) <= 0xff) | |
6923 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6924 | ||
6925 | return FAIL; | |
09d92015 MM |
6926 | } |
6927 | ||
c19d1205 ZW |
6928 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6929 | return the encoded form. Otherwise, return FAIL. */ | |
6930 | static unsigned int | |
6931 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6932 | { |
c19d1205 | 6933 | unsigned int a, i; |
09d92015 | 6934 | |
9c3c69f2 | 6935 | if (val <= 0xff) |
c19d1205 | 6936 | return val; |
a737bd4d | 6937 | |
9c3c69f2 | 6938 | for (i = 1; i <= 24; i++) |
09d92015 | 6939 | { |
9c3c69f2 PB |
6940 | a = val >> i; |
6941 | if ((val & ~(0xff << i)) == 0) | |
6942 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6943 | } |
a737bd4d | 6944 | |
c19d1205 ZW |
6945 | a = val & 0xff; |
6946 | if (val == ((a << 16) | a)) | |
6947 | return 0x100 | a; | |
6948 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6949 | return 0x300 | a; | |
09d92015 | 6950 | |
c19d1205 ZW |
6951 | a = val & 0xff00; |
6952 | if (val == ((a << 16) | a)) | |
6953 | return 0x200 | (a >> 8); | |
a737bd4d | 6954 | |
c19d1205 | 6955 | return FAIL; |
09d92015 | 6956 | } |
5287ad62 | 6957 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6958 | |
6959 | static void | |
5287ad62 JB |
6960 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6961 | { | |
6962 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6963 | && reg > 15) | |
6964 | { | |
b1cc4aeb | 6965 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6966 | { |
6967 | if (thumb_mode) | |
6968 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6969 | fpu_vfp_ext_d32); |
5287ad62 JB |
6970 | else |
6971 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6972 | fpu_vfp_ext_d32); |
5287ad62 JB |
6973 | } |
6974 | else | |
6975 | { | |
dcbf9037 | 6976 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6977 | return; |
6978 | } | |
6979 | } | |
6980 | ||
c19d1205 | 6981 | switch (pos) |
09d92015 | 6982 | { |
c19d1205 ZW |
6983 | case VFP_REG_Sd: |
6984 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6985 | break; | |
6986 | ||
6987 | case VFP_REG_Sn: | |
6988 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6989 | break; | |
6990 | ||
6991 | case VFP_REG_Sm: | |
6992 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6993 | break; | |
6994 | ||
5287ad62 JB |
6995 | case VFP_REG_Dd: |
6996 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6997 | break; | |
5f4273c7 | 6998 | |
5287ad62 JB |
6999 | case VFP_REG_Dn: |
7000 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
7001 | break; | |
5f4273c7 | 7002 | |
5287ad62 JB |
7003 | case VFP_REG_Dm: |
7004 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
7005 | break; | |
7006 | ||
c19d1205 ZW |
7007 | default: |
7008 | abort (); | |
09d92015 | 7009 | } |
09d92015 MM |
7010 | } |
7011 | ||
c19d1205 | 7012 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 7013 | if any, is handled by md_apply_fix. */ |
09d92015 | 7014 | static void |
c19d1205 | 7015 | encode_arm_shift (int i) |
09d92015 | 7016 | { |
c19d1205 ZW |
7017 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7018 | inst.instruction |= SHIFT_ROR << 5; | |
7019 | else | |
09d92015 | 7020 | { |
c19d1205 ZW |
7021 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7022 | if (inst.operands[i].immisreg) | |
7023 | { | |
7024 | inst.instruction |= SHIFT_BY_REG; | |
7025 | inst.instruction |= inst.operands[i].imm << 8; | |
7026 | } | |
7027 | else | |
7028 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7029 | } |
c19d1205 | 7030 | } |
09d92015 | 7031 | |
c19d1205 ZW |
7032 | static void |
7033 | encode_arm_shifter_operand (int i) | |
7034 | { | |
7035 | if (inst.operands[i].isreg) | |
09d92015 | 7036 | { |
c19d1205 ZW |
7037 | inst.instruction |= inst.operands[i].reg; |
7038 | encode_arm_shift (i); | |
09d92015 | 7039 | } |
c19d1205 | 7040 | else |
a415b1cd JB |
7041 | { |
7042 | inst.instruction |= INST_IMMEDIATE; | |
7043 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7044 | inst.instruction |= inst.operands[i].imm; | |
7045 | } | |
09d92015 MM |
7046 | } |
7047 | ||
c19d1205 | 7048 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7049 | static void |
c19d1205 | 7050 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7051 | { |
2b2f5df9 NC |
7052 | /* PR 14260: |
7053 | Generate an error if the operand is not a register. */ | |
7054 | constraint (!inst.operands[i].isreg, | |
7055 | _("Instruction does not support =N addresses")); | |
7056 | ||
c19d1205 | 7057 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7058 | |
c19d1205 | 7059 | if (inst.operands[i].preind) |
09d92015 | 7060 | { |
c19d1205 ZW |
7061 | if (is_t) |
7062 | { | |
7063 | inst.error = _("instruction does not accept preindexed addressing"); | |
7064 | return; | |
7065 | } | |
7066 | inst.instruction |= PRE_INDEX; | |
7067 | if (inst.operands[i].writeback) | |
7068 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7069 | |
c19d1205 ZW |
7070 | } |
7071 | else if (inst.operands[i].postind) | |
7072 | { | |
9c2799c2 | 7073 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7074 | if (is_t) |
7075 | inst.instruction |= WRITE_BACK; | |
7076 | } | |
7077 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7078 | { |
c19d1205 | 7079 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7080 | return; |
7081 | } | |
7082 | ||
c19d1205 ZW |
7083 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7084 | && (((inst.instruction & 0x000f0000) >> 16) | |
7085 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7086 | as_warn ((inst.instruction & LOAD_BIT) | |
7087 | ? _("destination register same as write-back base") | |
7088 | : _("source register same as write-back base")); | |
09d92015 MM |
7089 | } |
7090 | ||
c19d1205 ZW |
7091 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7092 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7093 | reject forms that cannot be used with a T instruction (i.e. not | |
7094 | post-indexed). */ | |
a737bd4d | 7095 | static void |
c19d1205 | 7096 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7097 | { |
5be8be5d DG |
7098 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7099 | ||
c19d1205 | 7100 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7101 | |
c19d1205 | 7102 | if (inst.operands[i].immisreg) |
09d92015 | 7103 | { |
5be8be5d DG |
7104 | constraint ((inst.operands[i].imm == REG_PC |
7105 | || (is_pc && inst.operands[i].writeback)), | |
7106 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7107 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7108 | inst.instruction |= inst.operands[i].imm; | |
7109 | if (!inst.operands[i].negative) | |
7110 | inst.instruction |= INDEX_UP; | |
7111 | if (inst.operands[i].shifted) | |
7112 | { | |
7113 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7114 | inst.instruction |= SHIFT_ROR << 5; | |
7115 | else | |
7116 | { | |
7117 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7118 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7119 | } | |
7120 | } | |
09d92015 | 7121 | } |
c19d1205 | 7122 | else /* immediate offset in inst.reloc */ |
09d92015 | 7123 | { |
5be8be5d DG |
7124 | if (is_pc && !inst.reloc.pc_rel) |
7125 | { | |
7126 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7127 | |
7128 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7129 | cannot use PC in addressing. | |
7130 | PC cannot be used in writeback addressing, either. */ | |
7131 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7132 | BAD_PC_ADDRESSING); |
23a10334 | 7133 | |
dc5ec521 | 7134 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7135 | if (warn_on_deprecated |
7136 | && !is_load | |
7137 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
7138 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
7139 | } |
7140 | ||
c19d1205 | 7141 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7142 | { |
7143 | /* Prefer + for zero encoded value. */ | |
7144 | if (!inst.operands[i].negative) | |
7145 | inst.instruction |= INDEX_UP; | |
7146 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7147 | } | |
09d92015 | 7148 | } |
09d92015 MM |
7149 | } |
7150 | ||
c19d1205 ZW |
7151 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7152 | ARM-format mode 3 load or store instruction. Reject forms that | |
7153 | cannot be used with such instructions. If is_t is true, reject | |
7154 | forms that cannot be used with a T instruction (i.e. not | |
7155 | post-indexed). */ | |
7156 | static void | |
7157 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7158 | { |
c19d1205 | 7159 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7160 | { |
c19d1205 ZW |
7161 | inst.error = _("instruction does not accept scaled register index"); |
7162 | return; | |
09d92015 | 7163 | } |
a737bd4d | 7164 | |
c19d1205 | 7165 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7166 | |
c19d1205 ZW |
7167 | if (inst.operands[i].immisreg) |
7168 | { | |
5be8be5d DG |
7169 | constraint ((inst.operands[i].imm == REG_PC |
7170 | || inst.operands[i].reg == REG_PC), | |
7171 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7172 | inst.instruction |= inst.operands[i].imm; |
7173 | if (!inst.operands[i].negative) | |
7174 | inst.instruction |= INDEX_UP; | |
7175 | } | |
7176 | else /* immediate offset in inst.reloc */ | |
7177 | { | |
5be8be5d DG |
7178 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7179 | && inst.operands[i].writeback), | |
7180 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7181 | inst.instruction |= HWOFFSET_IMM; |
7182 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7183 | { |
7184 | /* Prefer + for zero encoded value. */ | |
7185 | if (!inst.operands[i].negative) | |
7186 | inst.instruction |= INDEX_UP; | |
7187 | ||
7188 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7189 | } | |
c19d1205 | 7190 | } |
a737bd4d NC |
7191 | } |
7192 | ||
c19d1205 ZW |
7193 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7194 | ARM-format instruction. Reject all forms which cannot be encoded | |
7195 | into a coprocessor load/store instruction. If wb_ok is false, | |
7196 | reject use of writeback; if unind_ok is false, reject use of | |
7197 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
7198 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
7199 | (in which case it is preserved). */ | |
09d92015 | 7200 | |
c19d1205 ZW |
7201 | static int |
7202 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 7203 | { |
c19d1205 | 7204 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7205 | |
9c2799c2 | 7206 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 7207 | |
c19d1205 | 7208 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 7209 | { |
9c2799c2 | 7210 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
7211 | if (!unind_ok) |
7212 | { | |
7213 | inst.error = _("instruction does not support unindexed addressing"); | |
7214 | return FAIL; | |
7215 | } | |
7216 | inst.instruction |= inst.operands[i].imm; | |
7217 | inst.instruction |= INDEX_UP; | |
7218 | return SUCCESS; | |
09d92015 | 7219 | } |
a737bd4d | 7220 | |
c19d1205 ZW |
7221 | if (inst.operands[i].preind) |
7222 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 7223 | |
c19d1205 | 7224 | if (inst.operands[i].writeback) |
09d92015 | 7225 | { |
c19d1205 ZW |
7226 | if (inst.operands[i].reg == REG_PC) |
7227 | { | |
7228 | inst.error = _("pc may not be used with write-back"); | |
7229 | return FAIL; | |
7230 | } | |
7231 | if (!wb_ok) | |
7232 | { | |
7233 | inst.error = _("instruction does not support writeback"); | |
7234 | return FAIL; | |
7235 | } | |
7236 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7237 | } |
a737bd4d | 7238 | |
c19d1205 | 7239 | if (reloc_override) |
21d799b5 | 7240 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
7241 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
7242 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7243 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
7244 | { | |
7245 | if (thumb_mode) | |
7246 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7247 | else | |
7248 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
7249 | } | |
7250 | ||
26d97720 NS |
7251 | /* Prefer + for zero encoded value. */ |
7252 | if (!inst.operands[i].negative) | |
7253 | inst.instruction |= INDEX_UP; | |
7254 | ||
c19d1205 ZW |
7255 | return SUCCESS; |
7256 | } | |
a737bd4d | 7257 | |
c19d1205 ZW |
7258 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7259 | Determine whether it can be performed with a move instruction; if | |
7260 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7261 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7262 | load and return FALSE. If this is not a valid thing to do in the | |
7263 | current context, set inst.error and return TRUE. | |
a737bd4d | 7264 | |
c19d1205 ZW |
7265 | inst.operands[i] describes the destination register. */ |
7266 | ||
c921be7d | 7267 | static bfd_boolean |
c19d1205 ZW |
7268 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
7269 | { | |
53365c0d PB |
7270 | unsigned long tbit; |
7271 | ||
7272 | if (thumb_p) | |
7273 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7274 | else | |
7275 | tbit = LOAD_BIT; | |
7276 | ||
7277 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7278 | { |
c19d1205 | 7279 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7280 | return TRUE; |
09d92015 | 7281 | } |
c19d1205 | 7282 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
7283 | { |
7284 | inst.error = _("constant expression expected"); | |
c921be7d | 7285 | return TRUE; |
09d92015 | 7286 | } |
c19d1205 | 7287 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 7288 | { |
c19d1205 ZW |
7289 | if (thumb_p) |
7290 | { | |
53365c0d | 7291 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
7292 | { |
7293 | /* This can be done with a mov(1) instruction. */ | |
7294 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7295 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 7296 | return TRUE; |
c19d1205 ZW |
7297 | } |
7298 | } | |
7299 | else | |
7300 | { | |
7301 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7302 | if (value != FAIL) | |
7303 | { | |
7304 | /* This can be done with a mov instruction. */ | |
7305 | inst.instruction &= LITERAL_MASK; | |
7306 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7307 | inst.instruction |= value & 0xfff; | |
c921be7d | 7308 | return TRUE; |
c19d1205 | 7309 | } |
09d92015 | 7310 | |
c19d1205 ZW |
7311 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
7312 | if (value != FAIL) | |
7313 | { | |
7314 | /* This can be done with a mvn instruction. */ | |
7315 | inst.instruction &= LITERAL_MASK; | |
7316 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7317 | inst.instruction |= value & 0xfff; | |
c921be7d | 7318 | return TRUE; |
c19d1205 ZW |
7319 | } |
7320 | } | |
09d92015 MM |
7321 | } |
7322 | ||
c19d1205 ZW |
7323 | if (add_to_lit_pool () == FAIL) |
7324 | { | |
7325 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 7326 | return TRUE; |
c19d1205 ZW |
7327 | } |
7328 | inst.operands[1].reg = REG_PC; | |
7329 | inst.operands[1].isreg = 1; | |
7330 | inst.operands[1].preind = 1; | |
7331 | inst.reloc.pc_rel = 1; | |
7332 | inst.reloc.type = (thumb_p | |
7333 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7334 | : (mode_3 | |
7335 | ? BFD_RELOC_ARM_HWLITERAL | |
7336 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 7337 | return FALSE; |
09d92015 MM |
7338 | } |
7339 | ||
5f4273c7 | 7340 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7341 | First some generics; their names are taken from the conventional |
7342 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7343 | |
a737bd4d | 7344 | static void |
c19d1205 | 7345 | do_noargs (void) |
09d92015 | 7346 | { |
c19d1205 | 7347 | } |
a737bd4d | 7348 | |
c19d1205 ZW |
7349 | static void |
7350 | do_rd (void) | |
7351 | { | |
7352 | inst.instruction |= inst.operands[0].reg << 12; | |
7353 | } | |
a737bd4d | 7354 | |
c19d1205 ZW |
7355 | static void |
7356 | do_rd_rm (void) | |
7357 | { | |
7358 | inst.instruction |= inst.operands[0].reg << 12; | |
7359 | inst.instruction |= inst.operands[1].reg; | |
7360 | } | |
09d92015 | 7361 | |
c19d1205 ZW |
7362 | static void |
7363 | do_rd_rn (void) | |
7364 | { | |
7365 | inst.instruction |= inst.operands[0].reg << 12; | |
7366 | inst.instruction |= inst.operands[1].reg << 16; | |
7367 | } | |
a737bd4d | 7368 | |
c19d1205 ZW |
7369 | static void |
7370 | do_rn_rd (void) | |
7371 | { | |
7372 | inst.instruction |= inst.operands[0].reg << 16; | |
7373 | inst.instruction |= inst.operands[1].reg << 12; | |
7374 | } | |
09d92015 | 7375 | |
59d09be6 MGD |
7376 | static bfd_boolean |
7377 | check_obsolete (const arm_feature_set *feature, const char *msg) | |
7378 | { | |
7379 | if (ARM_CPU_IS_ANY (cpu_variant)) | |
7380 | { | |
7381 | as_warn ("%s", msg); | |
7382 | return TRUE; | |
7383 | } | |
7384 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature)) | |
7385 | { | |
7386 | as_bad ("%s", msg); | |
7387 | return TRUE; | |
7388 | } | |
7389 | ||
7390 | return FALSE; | |
7391 | } | |
7392 | ||
c19d1205 ZW |
7393 | static void |
7394 | do_rd_rm_rn (void) | |
7395 | { | |
9a64e435 | 7396 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7397 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7398 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7399 | { |
7400 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7401 | _("Rn must not overlap other operands")); | |
7402 | ||
59d09be6 MGD |
7403 | /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7. |
7404 | */ | |
7405 | if (!check_obsolete (&arm_ext_v8, | |
7406 | _("swp{b} use is obsoleted for ARMv8 and later")) | |
7407 | && warn_on_deprecated | |
7408 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6)) | |
7409 | as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7")); | |
56adecf4 | 7410 | } |
59d09be6 | 7411 | |
c19d1205 ZW |
7412 | inst.instruction |= inst.operands[0].reg << 12; |
7413 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7414 | inst.instruction |= Rn << 16; |
c19d1205 | 7415 | } |
09d92015 | 7416 | |
c19d1205 ZW |
7417 | static void |
7418 | do_rd_rn_rm (void) | |
7419 | { | |
7420 | inst.instruction |= inst.operands[0].reg << 12; | |
7421 | inst.instruction |= inst.operands[1].reg << 16; | |
7422 | inst.instruction |= inst.operands[2].reg; | |
7423 | } | |
a737bd4d | 7424 | |
c19d1205 ZW |
7425 | static void |
7426 | do_rm_rd_rn (void) | |
7427 | { | |
5be8be5d DG |
7428 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7429 | constraint (((inst.reloc.exp.X_op != O_constant | |
7430 | && inst.reloc.exp.X_op != O_illegal) | |
7431 | || inst.reloc.exp.X_add_number != 0), | |
7432 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7433 | inst.instruction |= inst.operands[0].reg; |
7434 | inst.instruction |= inst.operands[1].reg << 12; | |
7435 | inst.instruction |= inst.operands[2].reg << 16; | |
7436 | } | |
09d92015 | 7437 | |
c19d1205 ZW |
7438 | static void |
7439 | do_imm0 (void) | |
7440 | { | |
7441 | inst.instruction |= inst.operands[0].imm; | |
7442 | } | |
09d92015 | 7443 | |
c19d1205 ZW |
7444 | static void |
7445 | do_rd_cpaddr (void) | |
7446 | { | |
7447 | inst.instruction |= inst.operands[0].reg << 12; | |
7448 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7449 | } |
a737bd4d | 7450 | |
c19d1205 ZW |
7451 | /* ARM instructions, in alphabetical order by function name (except |
7452 | that wrapper functions appear immediately after the function they | |
7453 | wrap). */ | |
09d92015 | 7454 | |
c19d1205 ZW |
7455 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7456 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7457 | |
7458 | static void | |
c19d1205 | 7459 | do_adr (void) |
09d92015 | 7460 | { |
c19d1205 | 7461 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7462 | |
c19d1205 ZW |
7463 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7464 | out to be negative. */ | |
7465 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7466 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7467 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7468 | } |
b99bd4ef | 7469 | |
c19d1205 ZW |
7470 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7471 | into a relative address of the form: | |
7472 | add rd, pc, #low(label-.-8)" | |
7473 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7474 | |
c19d1205 ZW |
7475 | static void |
7476 | do_adrl (void) | |
7477 | { | |
7478 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7479 | |
c19d1205 ZW |
7480 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7481 | out to be negative. */ | |
7482 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7483 | inst.reloc.pc_rel = 1; |
7484 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7485 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7486 | } |
7487 | ||
b99bd4ef | 7488 | static void |
c19d1205 | 7489 | do_arit (void) |
b99bd4ef | 7490 | { |
c19d1205 ZW |
7491 | if (!inst.operands[1].present) |
7492 | inst.operands[1].reg = inst.operands[0].reg; | |
7493 | inst.instruction |= inst.operands[0].reg << 12; | |
7494 | inst.instruction |= inst.operands[1].reg << 16; | |
7495 | encode_arm_shifter_operand (2); | |
7496 | } | |
b99bd4ef | 7497 | |
62b3e311 PB |
7498 | static void |
7499 | do_barrier (void) | |
7500 | { | |
7501 | if (inst.operands[0].present) | |
7502 | { | |
7503 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
7504 | && inst.operands[0].imm > 0xf |
7505 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 7506 | _("bad barrier type")); |
62b3e311 PB |
7507 | inst.instruction |= inst.operands[0].imm; |
7508 | } | |
7509 | else | |
7510 | inst.instruction |= 0xf; | |
7511 | } | |
7512 | ||
c19d1205 ZW |
7513 | static void |
7514 | do_bfc (void) | |
7515 | { | |
7516 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7517 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7518 | /* The instruction encoding stores the LSB and MSB, | |
7519 | not the LSB and width. */ | |
7520 | inst.instruction |= inst.operands[0].reg << 12; | |
7521 | inst.instruction |= inst.operands[1].imm << 7; | |
7522 | inst.instruction |= (msb - 1) << 16; | |
7523 | } | |
b99bd4ef | 7524 | |
c19d1205 ZW |
7525 | static void |
7526 | do_bfi (void) | |
7527 | { | |
7528 | unsigned int msb; | |
b99bd4ef | 7529 | |
c19d1205 ZW |
7530 | /* #0 in second position is alternative syntax for bfc, which is |
7531 | the same instruction but with REG_PC in the Rm field. */ | |
7532 | if (!inst.operands[1].isreg) | |
7533 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7534 | |
c19d1205 ZW |
7535 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7536 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7537 | /* The instruction encoding stores the LSB and MSB, | |
7538 | not the LSB and width. */ | |
7539 | inst.instruction |= inst.operands[0].reg << 12; | |
7540 | inst.instruction |= inst.operands[1].reg; | |
7541 | inst.instruction |= inst.operands[2].imm << 7; | |
7542 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7543 | } |
7544 | ||
b99bd4ef | 7545 | static void |
c19d1205 | 7546 | do_bfx (void) |
b99bd4ef | 7547 | { |
c19d1205 ZW |
7548 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7549 | _("bit-field extends past end of register")); | |
7550 | inst.instruction |= inst.operands[0].reg << 12; | |
7551 | inst.instruction |= inst.operands[1].reg; | |
7552 | inst.instruction |= inst.operands[2].imm << 7; | |
7553 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7554 | } | |
09d92015 | 7555 | |
c19d1205 ZW |
7556 | /* ARM V5 breakpoint instruction (argument parse) |
7557 | BKPT <16 bit unsigned immediate> | |
7558 | Instruction is not conditional. | |
7559 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7560 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7561 | |
c19d1205 ZW |
7562 | static void |
7563 | do_bkpt (void) | |
7564 | { | |
7565 | /* Top 12 of 16 bits to bits 19:8. */ | |
7566 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7567 | |
c19d1205 ZW |
7568 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7569 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7570 | } | |
09d92015 | 7571 | |
c19d1205 ZW |
7572 | static void |
7573 | encode_branch (int default_reloc) | |
7574 | { | |
7575 | if (inst.operands[0].hasreloc) | |
7576 | { | |
0855e32b NS |
7577 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
7578 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
7579 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
7580 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
7581 | ? BFD_RELOC_ARM_PLT32 | |
7582 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 7583 | } |
b99bd4ef | 7584 | else |
9ae92b05 | 7585 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 7586 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7587 | } |
7588 | ||
b99bd4ef | 7589 | static void |
c19d1205 | 7590 | do_branch (void) |
b99bd4ef | 7591 | { |
39b41c9c PB |
7592 | #ifdef OBJ_ELF |
7593 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7594 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7595 | else | |
7596 | #endif | |
7597 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7598 | } | |
7599 | ||
7600 | static void | |
7601 | do_bl (void) | |
7602 | { | |
7603 | #ifdef OBJ_ELF | |
7604 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7605 | { | |
7606 | if (inst.cond == COND_ALWAYS) | |
7607 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7608 | else | |
7609 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7610 | } | |
7611 | else | |
7612 | #endif | |
7613 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7614 | } |
b99bd4ef | 7615 | |
c19d1205 ZW |
7616 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7617 | BLX <target_addr> ie BLX(1) | |
7618 | BLX{<condition>} <Rm> ie BLX(2) | |
7619 | Unfortunately, there are two different opcodes for this mnemonic. | |
7620 | So, the insns[].value is not used, and the code here zaps values | |
7621 | into inst.instruction. | |
7622 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7623 | |
c19d1205 ZW |
7624 | static void |
7625 | do_blx (void) | |
7626 | { | |
7627 | if (inst.operands[0].isreg) | |
b99bd4ef | 7628 | { |
c19d1205 ZW |
7629 | /* Arg is a register; the opcode provided by insns[] is correct. |
7630 | It is not illegal to do "blx pc", just useless. */ | |
7631 | if (inst.operands[0].reg == REG_PC) | |
7632 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7633 | |
c19d1205 ZW |
7634 | inst.instruction |= inst.operands[0].reg; |
7635 | } | |
7636 | else | |
b99bd4ef | 7637 | { |
c19d1205 | 7638 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7639 | conditionally, and the opcode must be adjusted. |
7640 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7641 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7642 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7643 | inst.instruction = 0xfa000000; |
267bf995 | 7644 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7645 | } |
c19d1205 ZW |
7646 | } |
7647 | ||
7648 | static void | |
7649 | do_bx (void) | |
7650 | { | |
845b51d6 PB |
7651 | bfd_boolean want_reloc; |
7652 | ||
c19d1205 ZW |
7653 | if (inst.operands[0].reg == REG_PC) |
7654 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7655 | |
c19d1205 | 7656 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7657 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7658 | it is for ARMv4t or earlier. */ | |
7659 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7660 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7661 | want_reloc = TRUE; | |
7662 | ||
5ad34203 | 7663 | #ifdef OBJ_ELF |
845b51d6 | 7664 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7665 | #endif |
584206db | 7666 | want_reloc = FALSE; |
845b51d6 PB |
7667 | |
7668 | if (want_reloc) | |
7669 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7670 | } |
7671 | ||
c19d1205 ZW |
7672 | |
7673 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7674 | |
7675 | static void | |
c19d1205 | 7676 | do_bxj (void) |
a737bd4d | 7677 | { |
c19d1205 ZW |
7678 | if (inst.operands[0].reg == REG_PC) |
7679 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7680 | ||
7681 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7682 | } |
7683 | ||
c19d1205 ZW |
7684 | /* Co-processor data operation: |
7685 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7686 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7687 | static void | |
7688 | do_cdp (void) | |
7689 | { | |
7690 | inst.instruction |= inst.operands[0].reg << 8; | |
7691 | inst.instruction |= inst.operands[1].imm << 20; | |
7692 | inst.instruction |= inst.operands[2].reg << 12; | |
7693 | inst.instruction |= inst.operands[3].reg << 16; | |
7694 | inst.instruction |= inst.operands[4].reg; | |
7695 | inst.instruction |= inst.operands[5].imm << 5; | |
7696 | } | |
a737bd4d NC |
7697 | |
7698 | static void | |
c19d1205 | 7699 | do_cmp (void) |
a737bd4d | 7700 | { |
c19d1205 ZW |
7701 | inst.instruction |= inst.operands[0].reg << 16; |
7702 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7703 | } |
7704 | ||
c19d1205 ZW |
7705 | /* Transfer between coprocessor and ARM registers. |
7706 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7707 | MRC2 | |
7708 | MCR{cond} | |
7709 | MCR2 | |
7710 | ||
7711 | No special properties. */ | |
09d92015 | 7712 | |
dcbd0d71 MGD |
7713 | struct deprecated_coproc_regs_s |
7714 | { | |
7715 | unsigned cp; | |
7716 | int opc1; | |
7717 | unsigned crn; | |
7718 | unsigned crm; | |
7719 | int opc2; | |
7720 | arm_feature_set deprecated; | |
7721 | arm_feature_set obsoleted; | |
7722 | const char *dep_msg; | |
7723 | const char *obs_msg; | |
7724 | }; | |
7725 | ||
7726 | #define DEPR_ACCESS_V8 \ | |
7727 | N_("This coprocessor register access is deprecated in ARMv8") | |
7728 | ||
7729 | /* Table of all deprecated coprocessor registers. */ | |
7730 | static struct deprecated_coproc_regs_s deprecated_coproc_regs[] = | |
7731 | { | |
7732 | {15, 0, 7, 10, 5, /* CP15DMB. */ | |
7733 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7734 | DEPR_ACCESS_V8, NULL}, | |
7735 | {15, 0, 7, 10, 4, /* CP15DSB. */ | |
7736 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7737 | DEPR_ACCESS_V8, NULL}, | |
7738 | {15, 0, 7, 5, 4, /* CP15ISB. */ | |
7739 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7740 | DEPR_ACCESS_V8, NULL}, | |
7741 | {14, 6, 1, 0, 0, /* TEEHBR. */ | |
7742 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7743 | DEPR_ACCESS_V8, NULL}, | |
7744 | {14, 6, 0, 0, 0, /* TEECR. */ | |
7745 | ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0), | |
7746 | DEPR_ACCESS_V8, NULL}, | |
7747 | }; | |
7748 | ||
7749 | #undef DEPR_ACCESS_V8 | |
7750 | ||
7751 | static const size_t deprecated_coproc_reg_count = | |
7752 | sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]); | |
7753 | ||
09d92015 | 7754 | static void |
c19d1205 | 7755 | do_co_reg (void) |
09d92015 | 7756 | { |
fdfde340 | 7757 | unsigned Rd; |
dcbd0d71 | 7758 | size_t i; |
fdfde340 JM |
7759 | |
7760 | Rd = inst.operands[2].reg; | |
7761 | if (thumb_mode) | |
7762 | { | |
7763 | if (inst.instruction == 0xee000010 | |
7764 | || inst.instruction == 0xfe000010) | |
7765 | /* MCR, MCR2 */ | |
7766 | reject_bad_reg (Rd); | |
7767 | else | |
7768 | /* MRC, MRC2 */ | |
7769 | constraint (Rd == REG_SP, BAD_SP); | |
7770 | } | |
7771 | else | |
7772 | { | |
7773 | /* MCR */ | |
7774 | if (inst.instruction == 0xe000010) | |
7775 | constraint (Rd == REG_PC, BAD_PC); | |
7776 | } | |
7777 | ||
dcbd0d71 MGD |
7778 | for (i = 0; i < deprecated_coproc_reg_count; ++i) |
7779 | { | |
7780 | const struct deprecated_coproc_regs_s *r = | |
7781 | deprecated_coproc_regs + i; | |
7782 | ||
7783 | if (inst.operands[0].reg == r->cp | |
7784 | && inst.operands[1].imm == r->opc1 | |
7785 | && inst.operands[3].reg == r->crn | |
7786 | && inst.operands[4].reg == r->crm | |
7787 | && inst.operands[5].imm == r->opc2) | |
7788 | { | |
7789 | if (!check_obsolete (&r->obsoleted, r->obs_msg) | |
7790 | && warn_on_deprecated | |
7791 | && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated)) | |
7792 | as_warn ("%s", r->dep_msg); | |
7793 | } | |
7794 | } | |
fdfde340 | 7795 | |
c19d1205 ZW |
7796 | inst.instruction |= inst.operands[0].reg << 8; |
7797 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7798 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7799 | inst.instruction |= inst.operands[3].reg << 16; |
7800 | inst.instruction |= inst.operands[4].reg; | |
7801 | inst.instruction |= inst.operands[5].imm << 5; | |
7802 | } | |
09d92015 | 7803 | |
c19d1205 ZW |
7804 | /* Transfer between coprocessor register and pair of ARM registers. |
7805 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7806 | MCRR2 | |
7807 | MRRC{cond} | |
7808 | MRRC2 | |
b99bd4ef | 7809 | |
c19d1205 | 7810 | Two XScale instructions are special cases of these: |
09d92015 | 7811 | |
c19d1205 ZW |
7812 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7813 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7814 | |
5f4273c7 | 7815 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7816 | |
c19d1205 ZW |
7817 | static void |
7818 | do_co_reg2c (void) | |
7819 | { | |
fdfde340 JM |
7820 | unsigned Rd, Rn; |
7821 | ||
7822 | Rd = inst.operands[2].reg; | |
7823 | Rn = inst.operands[3].reg; | |
7824 | ||
7825 | if (thumb_mode) | |
7826 | { | |
7827 | reject_bad_reg (Rd); | |
7828 | reject_bad_reg (Rn); | |
7829 | } | |
7830 | else | |
7831 | { | |
7832 | constraint (Rd == REG_PC, BAD_PC); | |
7833 | constraint (Rn == REG_PC, BAD_PC); | |
7834 | } | |
7835 | ||
c19d1205 ZW |
7836 | inst.instruction |= inst.operands[0].reg << 8; |
7837 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7838 | inst.instruction |= Rd << 12; |
7839 | inst.instruction |= Rn << 16; | |
c19d1205 | 7840 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7841 | } |
7842 | ||
c19d1205 ZW |
7843 | static void |
7844 | do_cpsi (void) | |
7845 | { | |
7846 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7847 | if (inst.operands[1].present) |
7848 | { | |
7849 | inst.instruction |= CPSI_MMOD; | |
7850 | inst.instruction |= inst.operands[1].imm; | |
7851 | } | |
c19d1205 | 7852 | } |
b99bd4ef | 7853 | |
62b3e311 PB |
7854 | static void |
7855 | do_dbg (void) | |
7856 | { | |
7857 | inst.instruction |= inst.operands[0].imm; | |
7858 | } | |
7859 | ||
eea54501 MGD |
7860 | static void |
7861 | do_div (void) | |
7862 | { | |
7863 | unsigned Rd, Rn, Rm; | |
7864 | ||
7865 | Rd = inst.operands[0].reg; | |
7866 | Rn = (inst.operands[1].present | |
7867 | ? inst.operands[1].reg : Rd); | |
7868 | Rm = inst.operands[2].reg; | |
7869 | ||
7870 | constraint ((Rd == REG_PC), BAD_PC); | |
7871 | constraint ((Rn == REG_PC), BAD_PC); | |
7872 | constraint ((Rm == REG_PC), BAD_PC); | |
7873 | ||
7874 | inst.instruction |= Rd << 16; | |
7875 | inst.instruction |= Rn << 0; | |
7876 | inst.instruction |= Rm << 8; | |
7877 | } | |
7878 | ||
b99bd4ef | 7879 | static void |
c19d1205 | 7880 | do_it (void) |
b99bd4ef | 7881 | { |
c19d1205 | 7882 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7883 | process it to do the validation as if in |
7884 | thumb mode, just in case the code gets | |
7885 | assembled for thumb using the unified syntax. */ | |
7886 | ||
c19d1205 | 7887 | inst.size = 0; |
e07e6e58 NC |
7888 | if (unified_syntax) |
7889 | { | |
7890 | set_it_insn_type (IT_INSN); | |
7891 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7892 | now_it.cc = inst.operands[0].imm; | |
7893 | } | |
09d92015 | 7894 | } |
b99bd4ef | 7895 | |
6530b175 NC |
7896 | /* If there is only one register in the register list, |
7897 | then return its register number. Otherwise return -1. */ | |
7898 | static int | |
7899 | only_one_reg_in_list (int range) | |
7900 | { | |
7901 | int i = ffs (range) - 1; | |
7902 | return (i > 15 || range != (1 << i)) ? -1 : i; | |
7903 | } | |
7904 | ||
09d92015 | 7905 | static void |
6530b175 | 7906 | encode_ldmstm(int from_push_pop_mnem) |
ea6ef066 | 7907 | { |
c19d1205 ZW |
7908 | int base_reg = inst.operands[0].reg; |
7909 | int range = inst.operands[1].imm; | |
6530b175 | 7910 | int one_reg; |
ea6ef066 | 7911 | |
c19d1205 ZW |
7912 | inst.instruction |= base_reg << 16; |
7913 | inst.instruction |= range; | |
ea6ef066 | 7914 | |
c19d1205 ZW |
7915 | if (inst.operands[1].writeback) |
7916 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7917 | |
c19d1205 | 7918 | if (inst.operands[0].writeback) |
ea6ef066 | 7919 | { |
c19d1205 ZW |
7920 | inst.instruction |= WRITE_BACK; |
7921 | /* Check for unpredictable uses of writeback. */ | |
7922 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7923 | { |
c19d1205 ZW |
7924 | /* Not allowed in LDM type 2. */ |
7925 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7926 | && ((range & (1 << REG_PC)) == 0)) | |
7927 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7928 | /* Only allowed if base reg not in list for other types. */ | |
7929 | else if (range & (1 << base_reg)) | |
7930 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7931 | } | |
7932 | else /* STM. */ | |
7933 | { | |
7934 | /* Not allowed for type 2. */ | |
7935 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7936 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7937 | /* Only allowed if base reg not in list, or first in list. */ | |
7938 | else if ((range & (1 << base_reg)) | |
7939 | && (range & ((1 << base_reg) - 1))) | |
7940 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7941 | } |
ea6ef066 | 7942 | } |
6530b175 NC |
7943 | |
7944 | /* If PUSH/POP has only one register, then use the A2 encoding. */ | |
7945 | one_reg = only_one_reg_in_list (range); | |
7946 | if (from_push_pop_mnem && one_reg >= 0) | |
7947 | { | |
7948 | int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH; | |
7949 | ||
7950 | inst.instruction &= A_COND_MASK; | |
7951 | inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP; | |
7952 | inst.instruction |= one_reg << 12; | |
7953 | } | |
7954 | } | |
7955 | ||
7956 | static void | |
7957 | do_ldmstm (void) | |
7958 | { | |
7959 | encode_ldmstm (/*from_push_pop_mnem=*/FALSE); | |
a737bd4d NC |
7960 | } |
7961 | ||
c19d1205 ZW |
7962 | /* ARMv5TE load-consecutive (argument parse) |
7963 | Mode is like LDRH. | |
7964 | ||
7965 | LDRccD R, mode | |
7966 | STRccD R, mode. */ | |
7967 | ||
a737bd4d | 7968 | static void |
c19d1205 | 7969 | do_ldrd (void) |
a737bd4d | 7970 | { |
c19d1205 | 7971 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 7972 | _("first transfer register must be even")); |
c19d1205 ZW |
7973 | constraint (inst.operands[1].present |
7974 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 7975 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
7976 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
7977 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7978 | |
c19d1205 ZW |
7979 | if (!inst.operands[1].present) |
7980 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7981 | |
c56791bb RE |
7982 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7983 | register and the first register written; we have to diagnose | |
7984 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7985 | |
c56791bb RE |
7986 | if (inst.operands[2].reg == inst.operands[1].reg |
7987 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7988 | as_warn (_("base register written back, and overlaps " | |
7989 | "second transfer register")); | |
b05fe5cf | 7990 | |
c56791bb RE |
7991 | if (!(inst.instruction & V4_STR_BIT)) |
7992 | { | |
c19d1205 | 7993 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
7994 | destination (even if not write-back). */ |
7995 | if (inst.operands[2].immisreg | |
7996 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
7997 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
7998 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 7999 | } |
c19d1205 ZW |
8000 | inst.instruction |= inst.operands[0].reg << 12; |
8001 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
8002 | } |
8003 | ||
8004 | static void | |
c19d1205 | 8005 | do_ldrex (void) |
b05fe5cf | 8006 | { |
c19d1205 ZW |
8007 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
8008 | || inst.operands[1].postind || inst.operands[1].writeback | |
8009 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
8010 | || inst.operands[1].negative |
8011 | /* This can arise if the programmer has written | |
8012 | strex rN, rM, foo | |
8013 | or if they have mistakenly used a register name as the last | |
8014 | operand, eg: | |
8015 | strex rN, rM, rX | |
8016 | It is very difficult to distinguish between these two cases | |
8017 | because "rX" might actually be a label. ie the register | |
8018 | name has been occluded by a symbol of the same name. So we | |
8019 | just generate a general 'bad addressing mode' type error | |
8020 | message and leave it up to the programmer to discover the | |
8021 | true cause and fix their mistake. */ | |
8022 | || (inst.operands[1].reg == REG_PC), | |
8023 | BAD_ADDR_MODE); | |
b05fe5cf | 8024 | |
c19d1205 ZW |
8025 | constraint (inst.reloc.exp.X_op != O_constant |
8026 | || inst.reloc.exp.X_add_number != 0, | |
8027 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 8028 | |
5be8be5d DG |
8029 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
8030 | ||
c19d1205 ZW |
8031 | inst.instruction |= inst.operands[0].reg << 12; |
8032 | inst.instruction |= inst.operands[1].reg << 16; | |
8033 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
8034 | } |
8035 | ||
8036 | static void | |
c19d1205 | 8037 | do_ldrexd (void) |
b05fe5cf | 8038 | { |
c19d1205 ZW |
8039 | constraint (inst.operands[0].reg % 2 != 0, |
8040 | _("even register required")); | |
8041 | constraint (inst.operands[1].present | |
8042 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
8043 | _("can only load two consecutive registers")); | |
8044 | /* If op 1 were present and equal to PC, this function wouldn't | |
8045 | have been called in the first place. */ | |
8046 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 8047 | |
c19d1205 ZW |
8048 | inst.instruction |= inst.operands[0].reg << 12; |
8049 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
8050 | } |
8051 | ||
1be5fd2e NC |
8052 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
8053 | which is not a multiple of four is UNPREDICTABLE. */ | |
8054 | static void | |
8055 | check_ldr_r15_aligned (void) | |
8056 | { | |
8057 | constraint (!(inst.operands[1].immisreg) | |
8058 | && (inst.operands[0].reg == REG_PC | |
8059 | && inst.operands[1].reg == REG_PC | |
8060 | && (inst.reloc.exp.X_add_number & 0x3)), | |
8061 | _("ldr to register 15 must be 4-byte alligned")); | |
8062 | } | |
8063 | ||
b05fe5cf | 8064 | static void |
c19d1205 | 8065 | do_ldst (void) |
b05fe5cf | 8066 | { |
c19d1205 ZW |
8067 | inst.instruction |= inst.operands[0].reg << 12; |
8068 | if (!inst.operands[1].isreg) | |
8069 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 8070 | return; |
c19d1205 | 8071 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 8072 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
8073 | } |
8074 | ||
8075 | static void | |
c19d1205 | 8076 | do_ldstt (void) |
b05fe5cf | 8077 | { |
c19d1205 ZW |
8078 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8079 | reject [Rn,...]. */ | |
8080 | if (inst.operands[1].preind) | |
b05fe5cf | 8081 | { |
bd3ba5d1 NC |
8082 | constraint (inst.reloc.exp.X_op != O_constant |
8083 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8084 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8085 | |
c19d1205 ZW |
8086 | inst.operands[1].preind = 0; |
8087 | inst.operands[1].postind = 1; | |
8088 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8089 | } |
c19d1205 ZW |
8090 | inst.instruction |= inst.operands[0].reg << 12; |
8091 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
8092 | } | |
b05fe5cf | 8093 | |
c19d1205 | 8094 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 8095 | |
c19d1205 ZW |
8096 | static void |
8097 | do_ldstv4 (void) | |
8098 | { | |
ff4a8d2b | 8099 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
8100 | inst.instruction |= inst.operands[0].reg << 12; |
8101 | if (!inst.operands[1].isreg) | |
8102 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 8103 | return; |
c19d1205 | 8104 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
8105 | } |
8106 | ||
8107 | static void | |
c19d1205 | 8108 | do_ldsttv4 (void) |
b05fe5cf | 8109 | { |
c19d1205 ZW |
8110 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
8111 | reject [Rn,...]. */ | |
8112 | if (inst.operands[1].preind) | |
b05fe5cf | 8113 | { |
bd3ba5d1 NC |
8114 | constraint (inst.reloc.exp.X_op != O_constant |
8115 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 8116 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 8117 | |
c19d1205 ZW |
8118 | inst.operands[1].preind = 0; |
8119 | inst.operands[1].postind = 1; | |
8120 | inst.operands[1].writeback = 1; | |
b05fe5cf | 8121 | } |
c19d1205 ZW |
8122 | inst.instruction |= inst.operands[0].reg << 12; |
8123 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
8124 | } | |
b05fe5cf | 8125 | |
c19d1205 ZW |
8126 | /* Co-processor register load/store. |
8127 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8128 | static void | |
8129 | do_lstc (void) | |
8130 | { | |
8131 | inst.instruction |= inst.operands[0].reg << 8; | |
8132 | inst.instruction |= inst.operands[1].reg << 12; | |
8133 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8134 | } |
8135 | ||
b05fe5cf | 8136 | static void |
c19d1205 | 8137 | do_mlas (void) |
b05fe5cf | 8138 | { |
8fb9d7b9 | 8139 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8140 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8141 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8142 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8143 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8144 | |
c19d1205 ZW |
8145 | inst.instruction |= inst.operands[0].reg << 16; |
8146 | inst.instruction |= inst.operands[1].reg; | |
8147 | inst.instruction |= inst.operands[2].reg << 8; | |
8148 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8149 | } |
b05fe5cf | 8150 | |
c19d1205 ZW |
8151 | static void |
8152 | do_mov (void) | |
8153 | { | |
8154 | inst.instruction |= inst.operands[0].reg << 12; | |
8155 | encode_arm_shifter_operand (1); | |
8156 | } | |
b05fe5cf | 8157 | |
c19d1205 ZW |
8158 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8159 | static void | |
8160 | do_mov16 (void) | |
8161 | { | |
b6895b4f PB |
8162 | bfd_vma imm; |
8163 | bfd_boolean top; | |
8164 | ||
8165 | top = (inst.instruction & 0x00400000) != 0; | |
8166 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8167 | _(":lower16: not allowed this instruction")); | |
8168 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8169 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8170 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8171 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8172 | { | |
8173 | imm = inst.reloc.exp.X_add_number; | |
8174 | /* The value is in two pieces: 0:11, 16:19. */ | |
8175 | inst.instruction |= (imm & 0x00000fff); | |
8176 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8177 | } | |
b05fe5cf | 8178 | } |
b99bd4ef | 8179 | |
037e8744 JB |
8180 | static void do_vfp_nsyn_opcode (const char *); |
8181 | ||
8182 | static int | |
8183 | do_vfp_nsyn_mrs (void) | |
8184 | { | |
8185 | if (inst.operands[0].isvec) | |
8186 | { | |
8187 | if (inst.operands[1].reg != 1) | |
8188 | first_error (_("operand 1 must be FPSCR")); | |
8189 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
8190 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8191 | do_vfp_nsyn_opcode ("fmstat"); | |
8192 | } | |
8193 | else if (inst.operands[1].isvec) | |
8194 | do_vfp_nsyn_opcode ("fmrx"); | |
8195 | else | |
8196 | return FAIL; | |
5f4273c7 | 8197 | |
037e8744 JB |
8198 | return SUCCESS; |
8199 | } | |
8200 | ||
8201 | static int | |
8202 | do_vfp_nsyn_msr (void) | |
8203 | { | |
8204 | if (inst.operands[0].isvec) | |
8205 | do_vfp_nsyn_opcode ("fmxr"); | |
8206 | else | |
8207 | return FAIL; | |
8208 | ||
8209 | return SUCCESS; | |
8210 | } | |
8211 | ||
f7c21dc7 NC |
8212 | static void |
8213 | do_vmrs (void) | |
8214 | { | |
8215 | unsigned Rt = inst.operands[0].reg; | |
fa94de6b | 8216 | |
f7c21dc7 NC |
8217 | if (thumb_mode && inst.operands[0].reg == REG_SP) |
8218 | { | |
8219 | inst.error = BAD_SP; | |
8220 | return; | |
8221 | } | |
8222 | ||
8223 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
8224 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
8225 | { | |
8226 | inst.error = BAD_PC; | |
8227 | return; | |
8228 | } | |
8229 | ||
7465e07a NC |
8230 | switch (inst.operands[1].reg) |
8231 | { | |
8232 | case 0: /* FPSID */ | |
8233 | case 1: /* FPSCR */ | |
8234 | case 6: /* MVFR1 */ | |
8235 | case 7: /* MVFR0 */ | |
8236 | case 8: /* FPEXC */ | |
8237 | inst.instruction |= (inst.operands[1].reg << 16); | |
8238 | break; | |
8239 | default: | |
8240 | first_error (_("operand 1 must be a VFP extension System Register")); | |
8241 | } | |
f7c21dc7 NC |
8242 | |
8243 | inst.instruction |= (Rt << 12); | |
8244 | } | |
8245 | ||
8246 | static void | |
8247 | do_vmsr (void) | |
8248 | { | |
8249 | unsigned Rt = inst.operands[1].reg; | |
fa94de6b | 8250 | |
f7c21dc7 NC |
8251 | if (thumb_mode) |
8252 | reject_bad_reg (Rt); | |
8253 | else if (Rt == REG_PC) | |
8254 | { | |
8255 | inst.error = BAD_PC; | |
8256 | return; | |
8257 | } | |
8258 | ||
7465e07a NC |
8259 | switch (inst.operands[0].reg) |
8260 | { | |
8261 | case 0: /* FPSID */ | |
8262 | case 1: /* FPSCR */ | |
8263 | case 8: /* FPEXC */ | |
8264 | inst.instruction |= (inst.operands[0].reg << 16); | |
8265 | break; | |
8266 | default: | |
8267 | first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC")); | |
8268 | } | |
f7c21dc7 NC |
8269 | |
8270 | inst.instruction |= (Rt << 12); | |
8271 | } | |
8272 | ||
b99bd4ef | 8273 | static void |
c19d1205 | 8274 | do_mrs (void) |
b99bd4ef | 8275 | { |
90ec0d68 MGD |
8276 | unsigned br; |
8277 | ||
037e8744 JB |
8278 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8279 | return; | |
8280 | ||
ff4a8d2b | 8281 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8282 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8283 | |
8284 | if (inst.operands[1].isreg) | |
8285 | { | |
8286 | br = inst.operands[1].reg; | |
8287 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8288 | as_bad (_("bad register for mrs")); | |
8289 | } | |
8290 | else | |
8291 | { | |
8292 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8293 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8294 | != (PSR_c|PSR_f), | |
d2cd1205 | 8295 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8296 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8297 | } | |
8298 | ||
8299 | inst.instruction |= br; | |
c19d1205 | 8300 | } |
b99bd4ef | 8301 | |
c19d1205 ZW |
8302 | /* Two possible forms: |
8303 | "{C|S}PSR_<field>, Rm", | |
8304 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8305 | |
c19d1205 ZW |
8306 | static void |
8307 | do_msr (void) | |
8308 | { | |
037e8744 JB |
8309 | if (do_vfp_nsyn_msr () == SUCCESS) |
8310 | return; | |
8311 | ||
c19d1205 ZW |
8312 | inst.instruction |= inst.operands[0].imm; |
8313 | if (inst.operands[1].isreg) | |
8314 | inst.instruction |= inst.operands[1].reg; | |
8315 | else | |
b99bd4ef | 8316 | { |
c19d1205 ZW |
8317 | inst.instruction |= INST_IMMEDIATE; |
8318 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8319 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8320 | } |
b99bd4ef NC |
8321 | } |
8322 | ||
c19d1205 ZW |
8323 | static void |
8324 | do_mul (void) | |
a737bd4d | 8325 | { |
ff4a8d2b NC |
8326 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8327 | ||
c19d1205 ZW |
8328 | if (!inst.operands[2].present) |
8329 | inst.operands[2].reg = inst.operands[0].reg; | |
8330 | inst.instruction |= inst.operands[0].reg << 16; | |
8331 | inst.instruction |= inst.operands[1].reg; | |
8332 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8333 | |
8fb9d7b9 MS |
8334 | if (inst.operands[0].reg == inst.operands[1].reg |
8335 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8336 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8337 | } |
8338 | ||
c19d1205 ZW |
8339 | /* Long Multiply Parser |
8340 | UMULL RdLo, RdHi, Rm, Rs | |
8341 | SMULL RdLo, RdHi, Rm, Rs | |
8342 | UMLAL RdLo, RdHi, Rm, Rs | |
8343 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8344 | |
8345 | static void | |
c19d1205 | 8346 | do_mull (void) |
b99bd4ef | 8347 | { |
c19d1205 ZW |
8348 | inst.instruction |= inst.operands[0].reg << 12; |
8349 | inst.instruction |= inst.operands[1].reg << 16; | |
8350 | inst.instruction |= inst.operands[2].reg; | |
8351 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8352 | |
682b27ad PB |
8353 | /* rdhi and rdlo must be different. */ |
8354 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8355 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8356 | ||
8357 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8358 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8359 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8360 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8361 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8362 | } | |
b99bd4ef | 8363 | |
c19d1205 ZW |
8364 | static void |
8365 | do_nop (void) | |
8366 | { | |
e7495e45 NS |
8367 | if (inst.operands[0].present |
8368 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8369 | { |
8370 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8371 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8372 | inst.instruction |= 0x0320f000; |
8373 | if (inst.operands[0].present) | |
8374 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8375 | } |
b99bd4ef NC |
8376 | } |
8377 | ||
c19d1205 ZW |
8378 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8379 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8380 | Condition defaults to COND_ALWAYS. | |
8381 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8382 | |
8383 | static void | |
c19d1205 | 8384 | do_pkhbt (void) |
b99bd4ef | 8385 | { |
c19d1205 ZW |
8386 | inst.instruction |= inst.operands[0].reg << 12; |
8387 | inst.instruction |= inst.operands[1].reg << 16; | |
8388 | inst.instruction |= inst.operands[2].reg; | |
8389 | if (inst.operands[3].present) | |
8390 | encode_arm_shift (3); | |
8391 | } | |
b99bd4ef | 8392 | |
c19d1205 | 8393 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8394 | |
c19d1205 ZW |
8395 | static void |
8396 | do_pkhtb (void) | |
8397 | { | |
8398 | if (!inst.operands[3].present) | |
b99bd4ef | 8399 | { |
c19d1205 ZW |
8400 | /* If the shift specifier is omitted, turn the instruction |
8401 | into pkhbt rd, rm, rn. */ | |
8402 | inst.instruction &= 0xfff00010; | |
8403 | inst.instruction |= inst.operands[0].reg << 12; | |
8404 | inst.instruction |= inst.operands[1].reg; | |
8405 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8406 | } |
8407 | else | |
8408 | { | |
c19d1205 ZW |
8409 | inst.instruction |= inst.operands[0].reg << 12; |
8410 | inst.instruction |= inst.operands[1].reg << 16; | |
8411 | inst.instruction |= inst.operands[2].reg; | |
8412 | encode_arm_shift (3); | |
b99bd4ef NC |
8413 | } |
8414 | } | |
8415 | ||
c19d1205 | 8416 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 8417 | MP Extensions: Preload for write |
c19d1205 | 8418 | |
60e5ef9f | 8419 | PLD(W) <addr_mode> |
c19d1205 ZW |
8420 | |
8421 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
8422 | |
8423 | static void | |
c19d1205 | 8424 | do_pld (void) |
b99bd4ef | 8425 | { |
c19d1205 ZW |
8426 | constraint (!inst.operands[0].isreg, |
8427 | _("'[' expected after PLD mnemonic")); | |
8428 | constraint (inst.operands[0].postind, | |
8429 | _("post-indexed expression used in preload instruction")); | |
8430 | constraint (inst.operands[0].writeback, | |
8431 | _("writeback used in preload instruction")); | |
8432 | constraint (!inst.operands[0].preind, | |
8433 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
8434 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
8435 | } | |
b99bd4ef | 8436 | |
62b3e311 PB |
8437 | /* ARMv7: PLI <addr_mode> */ |
8438 | static void | |
8439 | do_pli (void) | |
8440 | { | |
8441 | constraint (!inst.operands[0].isreg, | |
8442 | _("'[' expected after PLI mnemonic")); | |
8443 | constraint (inst.operands[0].postind, | |
8444 | _("post-indexed expression used in preload instruction")); | |
8445 | constraint (inst.operands[0].writeback, | |
8446 | _("writeback used in preload instruction")); | |
8447 | constraint (!inst.operands[0].preind, | |
8448 | _("unindexed addressing used in preload instruction")); | |
8449 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
8450 | inst.instruction &= ~PRE_INDEX; | |
8451 | } | |
8452 | ||
c19d1205 ZW |
8453 | static void |
8454 | do_push_pop (void) | |
8455 | { | |
8456 | inst.operands[1] = inst.operands[0]; | |
8457 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
8458 | inst.operands[0].isreg = 1; | |
8459 | inst.operands[0].writeback = 1; | |
8460 | inst.operands[0].reg = REG_SP; | |
6530b175 | 8461 | encode_ldmstm (/*from_push_pop_mnem=*/TRUE); |
c19d1205 | 8462 | } |
b99bd4ef | 8463 | |
c19d1205 ZW |
8464 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
8465 | word at the specified address and the following word | |
8466 | respectively. | |
8467 | Unconditionally executed. | |
8468 | Error if Rn is R15. */ | |
b99bd4ef | 8469 | |
c19d1205 ZW |
8470 | static void |
8471 | do_rfe (void) | |
8472 | { | |
8473 | inst.instruction |= inst.operands[0].reg << 16; | |
8474 | if (inst.operands[0].writeback) | |
8475 | inst.instruction |= WRITE_BACK; | |
8476 | } | |
b99bd4ef | 8477 | |
c19d1205 | 8478 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 8479 | |
c19d1205 ZW |
8480 | static void |
8481 | do_ssat (void) | |
8482 | { | |
8483 | inst.instruction |= inst.operands[0].reg << 12; | |
8484 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
8485 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8486 | |
c19d1205 ZW |
8487 | if (inst.operands[3].present) |
8488 | encode_arm_shift (3); | |
b99bd4ef NC |
8489 | } |
8490 | ||
c19d1205 | 8491 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
8492 | |
8493 | static void | |
c19d1205 | 8494 | do_usat (void) |
b99bd4ef | 8495 | { |
c19d1205 ZW |
8496 | inst.instruction |= inst.operands[0].reg << 12; |
8497 | inst.instruction |= inst.operands[1].imm << 16; | |
8498 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8499 | |
c19d1205 ZW |
8500 | if (inst.operands[3].present) |
8501 | encode_arm_shift (3); | |
b99bd4ef NC |
8502 | } |
8503 | ||
c19d1205 | 8504 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
8505 | |
8506 | static void | |
c19d1205 | 8507 | do_ssat16 (void) |
09d92015 | 8508 | { |
c19d1205 ZW |
8509 | inst.instruction |= inst.operands[0].reg << 12; |
8510 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
8511 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
8512 | } |
8513 | ||
c19d1205 ZW |
8514 | static void |
8515 | do_usat16 (void) | |
a737bd4d | 8516 | { |
c19d1205 ZW |
8517 | inst.instruction |= inst.operands[0].reg << 12; |
8518 | inst.instruction |= inst.operands[1].imm << 16; | |
8519 | inst.instruction |= inst.operands[2].reg; | |
8520 | } | |
a737bd4d | 8521 | |
c19d1205 ZW |
8522 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
8523 | preserving the other bits. | |
a737bd4d | 8524 | |
c19d1205 ZW |
8525 | setend <endian_specifier>, where <endian_specifier> is either |
8526 | BE or LE. */ | |
a737bd4d | 8527 | |
c19d1205 ZW |
8528 | static void |
8529 | do_setend (void) | |
8530 | { | |
8531 | if (inst.operands[0].imm) | |
8532 | inst.instruction |= 0x200; | |
a737bd4d NC |
8533 | } |
8534 | ||
8535 | static void | |
c19d1205 | 8536 | do_shift (void) |
a737bd4d | 8537 | { |
c19d1205 ZW |
8538 | unsigned int Rm = (inst.operands[1].present |
8539 | ? inst.operands[1].reg | |
8540 | : inst.operands[0].reg); | |
a737bd4d | 8541 | |
c19d1205 ZW |
8542 | inst.instruction |= inst.operands[0].reg << 12; |
8543 | inst.instruction |= Rm; | |
8544 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8545 | { |
c19d1205 ZW |
8546 | inst.instruction |= inst.operands[2].reg << 8; |
8547 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
8548 | /* PR 12854: Error on extraneous shifts. */ |
8549 | constraint (inst.operands[2].shifted, | |
8550 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
8551 | } |
8552 | else | |
c19d1205 | 8553 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8554 | } |
8555 | ||
09d92015 | 8556 | static void |
3eb17e6b | 8557 | do_smc (void) |
09d92015 | 8558 | { |
3eb17e6b | 8559 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8560 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8561 | } |
8562 | ||
90ec0d68 MGD |
8563 | static void |
8564 | do_hvc (void) | |
8565 | { | |
8566 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
8567 | inst.reloc.pc_rel = 0; | |
8568 | } | |
8569 | ||
09d92015 | 8570 | static void |
c19d1205 | 8571 | do_swi (void) |
09d92015 | 8572 | { |
c19d1205 ZW |
8573 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8574 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8575 | } |
8576 | ||
c19d1205 ZW |
8577 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8578 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8579 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8580 | Error if any register is R15. */ | |
e16bb312 | 8581 | |
c19d1205 ZW |
8582 | static void |
8583 | do_smla (void) | |
e16bb312 | 8584 | { |
c19d1205 ZW |
8585 | inst.instruction |= inst.operands[0].reg << 16; |
8586 | inst.instruction |= inst.operands[1].reg; | |
8587 | inst.instruction |= inst.operands[2].reg << 8; | |
8588 | inst.instruction |= inst.operands[3].reg << 12; | |
8589 | } | |
a737bd4d | 8590 | |
c19d1205 ZW |
8591 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8592 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8593 | Error if any register is R15. | |
8594 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8595 | |
c19d1205 ZW |
8596 | static void |
8597 | do_smlal (void) | |
8598 | { | |
8599 | inst.instruction |= inst.operands[0].reg << 12; | |
8600 | inst.instruction |= inst.operands[1].reg << 16; | |
8601 | inst.instruction |= inst.operands[2].reg; | |
8602 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8603 | |
c19d1205 ZW |
8604 | if (inst.operands[0].reg == inst.operands[1].reg) |
8605 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8606 | } | |
a737bd4d | 8607 | |
c19d1205 ZW |
8608 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8609 | SMULxy{cond} Rd,Rm,Rs | |
8610 | Error if any register is R15. */ | |
a737bd4d | 8611 | |
c19d1205 ZW |
8612 | static void |
8613 | do_smul (void) | |
8614 | { | |
8615 | inst.instruction |= inst.operands[0].reg << 16; | |
8616 | inst.instruction |= inst.operands[1].reg; | |
8617 | inst.instruction |= inst.operands[2].reg << 8; | |
8618 | } | |
a737bd4d | 8619 | |
b6702015 PB |
8620 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8621 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8622 | |
c19d1205 ZW |
8623 | static void |
8624 | do_srs (void) | |
8625 | { | |
b6702015 PB |
8626 | int reg; |
8627 | ||
8628 | if (inst.operands[0].present) | |
8629 | { | |
8630 | reg = inst.operands[0].reg; | |
fdfde340 | 8631 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8632 | } |
8633 | else | |
fdfde340 | 8634 | reg = REG_SP; |
b6702015 PB |
8635 | |
8636 | inst.instruction |= reg << 16; | |
8637 | inst.instruction |= inst.operands[1].imm; | |
8638 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8639 | inst.instruction |= WRITE_BACK; |
8640 | } | |
a737bd4d | 8641 | |
c19d1205 | 8642 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8643 | |
c19d1205 ZW |
8644 | static void |
8645 | do_strex (void) | |
8646 | { | |
8647 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8648 | || inst.operands[2].postind || inst.operands[2].writeback | |
8649 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8650 | || inst.operands[2].negative |
8651 | /* See comment in do_ldrex(). */ | |
8652 | || (inst.operands[2].reg == REG_PC), | |
8653 | BAD_ADDR_MODE); | |
a737bd4d | 8654 | |
c19d1205 ZW |
8655 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8656 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8657 | |
c19d1205 ZW |
8658 | constraint (inst.reloc.exp.X_op != O_constant |
8659 | || inst.reloc.exp.X_add_number != 0, | |
8660 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8661 | |
c19d1205 ZW |
8662 | inst.instruction |= inst.operands[0].reg << 12; |
8663 | inst.instruction |= inst.operands[1].reg; | |
8664 | inst.instruction |= inst.operands[2].reg << 16; | |
8665 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8666 | } |
8667 | ||
877807f8 NC |
8668 | static void |
8669 | do_t_strexbh (void) | |
8670 | { | |
8671 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8672 | || inst.operands[2].postind || inst.operands[2].writeback | |
8673 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
8674 | || inst.operands[2].negative, | |
8675 | BAD_ADDR_MODE); | |
8676 | ||
8677 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
8678 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
8679 | ||
8680 | do_rm_rd_rn (); | |
8681 | } | |
8682 | ||
e16bb312 | 8683 | static void |
c19d1205 | 8684 | do_strexd (void) |
e16bb312 | 8685 | { |
c19d1205 ZW |
8686 | constraint (inst.operands[1].reg % 2 != 0, |
8687 | _("even register required")); | |
8688 | constraint (inst.operands[2].present | |
8689 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8690 | _("can only store two consecutive registers")); | |
8691 | /* If op 2 were present and equal to PC, this function wouldn't | |
8692 | have been called in the first place. */ | |
8693 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8694 | |
c19d1205 ZW |
8695 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8696 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8697 | || inst.operands[0].reg == inst.operands[3].reg, | |
8698 | BAD_OVERLAP); | |
e16bb312 | 8699 | |
c19d1205 ZW |
8700 | inst.instruction |= inst.operands[0].reg << 12; |
8701 | inst.instruction |= inst.operands[1].reg; | |
8702 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8703 | } |
8704 | ||
c19d1205 ZW |
8705 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8706 | extends it to 32-bits, and adds the result to a value in another | |
8707 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8708 | before extracting the 16-bit value. | |
8709 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8710 | Condition defaults to COND_ALWAYS. | |
8711 | Error if any register uses R15. */ | |
8712 | ||
e16bb312 | 8713 | static void |
c19d1205 | 8714 | do_sxtah (void) |
e16bb312 | 8715 | { |
c19d1205 ZW |
8716 | inst.instruction |= inst.operands[0].reg << 12; |
8717 | inst.instruction |= inst.operands[1].reg << 16; | |
8718 | inst.instruction |= inst.operands[2].reg; | |
8719 | inst.instruction |= inst.operands[3].imm << 10; | |
8720 | } | |
e16bb312 | 8721 | |
c19d1205 | 8722 | /* ARM V6 SXTH. |
e16bb312 | 8723 | |
c19d1205 ZW |
8724 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8725 | Condition defaults to COND_ALWAYS. | |
8726 | Error if any register uses R15. */ | |
e16bb312 NC |
8727 | |
8728 | static void | |
c19d1205 | 8729 | do_sxth (void) |
e16bb312 | 8730 | { |
c19d1205 ZW |
8731 | inst.instruction |= inst.operands[0].reg << 12; |
8732 | inst.instruction |= inst.operands[1].reg; | |
8733 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8734 | } |
c19d1205 ZW |
8735 | \f |
8736 | /* VFP instructions. In a logical order: SP variant first, monad | |
8737 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8738 | |
8739 | static void | |
c19d1205 | 8740 | do_vfp_sp_monadic (void) |
e16bb312 | 8741 | { |
5287ad62 JB |
8742 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8743 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8744 | } |
8745 | ||
8746 | static void | |
c19d1205 | 8747 | do_vfp_sp_dyadic (void) |
e16bb312 | 8748 | { |
5287ad62 JB |
8749 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8750 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8751 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8752 | } |
8753 | ||
8754 | static void | |
c19d1205 | 8755 | do_vfp_sp_compare_z (void) |
e16bb312 | 8756 | { |
5287ad62 | 8757 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8758 | } |
8759 | ||
8760 | static void | |
c19d1205 | 8761 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8762 | { |
5287ad62 JB |
8763 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8764 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8765 | } |
8766 | ||
8767 | static void | |
c19d1205 | 8768 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8769 | { |
5287ad62 JB |
8770 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8771 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8772 | } |
8773 | ||
8774 | static void | |
c19d1205 | 8775 | do_vfp_reg_from_sp (void) |
e16bb312 | 8776 | { |
c19d1205 | 8777 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8778 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8779 | } |
8780 | ||
8781 | static void | |
c19d1205 | 8782 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8783 | { |
c19d1205 ZW |
8784 | constraint (inst.operands[2].imm != 2, |
8785 | _("only two consecutive VFP SP registers allowed here")); | |
8786 | inst.instruction |= inst.operands[0].reg << 12; | |
8787 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8788 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8789 | } |
8790 | ||
8791 | static void | |
c19d1205 | 8792 | do_vfp_sp_from_reg (void) |
e16bb312 | 8793 | { |
5287ad62 | 8794 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8795 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8796 | } |
8797 | ||
8798 | static void | |
c19d1205 | 8799 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8800 | { |
c19d1205 ZW |
8801 | constraint (inst.operands[0].imm != 2, |
8802 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8803 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8804 | inst.instruction |= inst.operands[1].reg << 12; |
8805 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8806 | } |
8807 | ||
8808 | static void | |
c19d1205 | 8809 | do_vfp_sp_ldst (void) |
e16bb312 | 8810 | { |
5287ad62 | 8811 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8812 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8813 | } |
8814 | ||
8815 | static void | |
c19d1205 | 8816 | do_vfp_dp_ldst (void) |
e16bb312 | 8817 | { |
5287ad62 | 8818 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8819 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8820 | } |
8821 | ||
c19d1205 | 8822 | |
e16bb312 | 8823 | static void |
c19d1205 | 8824 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8825 | { |
c19d1205 ZW |
8826 | if (inst.operands[0].writeback) |
8827 | inst.instruction |= WRITE_BACK; | |
8828 | else | |
8829 | constraint (ldstm_type != VFP_LDSTMIA, | |
8830 | _("this addressing mode requires base-register writeback")); | |
8831 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8832 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8833 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8834 | } |
8835 | ||
8836 | static void | |
c19d1205 | 8837 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8838 | { |
c19d1205 | 8839 | int count; |
e16bb312 | 8840 | |
c19d1205 ZW |
8841 | if (inst.operands[0].writeback) |
8842 | inst.instruction |= WRITE_BACK; | |
8843 | else | |
8844 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8845 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8846 | |
c19d1205 | 8847 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8848 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8849 | |
c19d1205 ZW |
8850 | count = inst.operands[1].imm << 1; |
8851 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8852 | count += 1; | |
e16bb312 | 8853 | |
c19d1205 | 8854 | inst.instruction |= count; |
e16bb312 NC |
8855 | } |
8856 | ||
8857 | static void | |
c19d1205 | 8858 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8859 | { |
c19d1205 | 8860 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8861 | } |
8862 | ||
8863 | static void | |
c19d1205 | 8864 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8865 | { |
c19d1205 | 8866 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8867 | } |
8868 | ||
8869 | static void | |
c19d1205 | 8870 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8871 | { |
c19d1205 | 8872 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8873 | } |
8874 | ||
8875 | static void | |
c19d1205 | 8876 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8877 | { |
c19d1205 | 8878 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8879 | } |
8880 | ||
8881 | static void | |
c19d1205 | 8882 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8883 | { |
c19d1205 ZW |
8884 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8885 | } | |
e16bb312 | 8886 | |
c19d1205 ZW |
8887 | static void |
8888 | do_vfp_xp_ldstmdb (void) | |
8889 | { | |
8890 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8891 | } |
5287ad62 JB |
8892 | |
8893 | static void | |
8894 | do_vfp_dp_rd_rm (void) | |
8895 | { | |
8896 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8897 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8898 | } | |
8899 | ||
8900 | static void | |
8901 | do_vfp_dp_rn_rd (void) | |
8902 | { | |
8903 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8904 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8905 | } | |
8906 | ||
8907 | static void | |
8908 | do_vfp_dp_rd_rn (void) | |
8909 | { | |
8910 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8911 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8912 | } | |
8913 | ||
8914 | static void | |
8915 | do_vfp_dp_rd_rn_rm (void) | |
8916 | { | |
8917 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8918 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8919 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8920 | } | |
8921 | ||
8922 | static void | |
8923 | do_vfp_dp_rd (void) | |
8924 | { | |
8925 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8926 | } | |
8927 | ||
8928 | static void | |
8929 | do_vfp_dp_rm_rd_rn (void) | |
8930 | { | |
8931 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8932 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8933 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8934 | } | |
8935 | ||
8936 | /* VFPv3 instructions. */ | |
8937 | static void | |
8938 | do_vfp_sp_const (void) | |
8939 | { | |
8940 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8941 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8942 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8943 | } |
8944 | ||
8945 | static void | |
8946 | do_vfp_dp_const (void) | |
8947 | { | |
8948 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8949 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8950 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8951 | } |
8952 | ||
8953 | static void | |
8954 | vfp_conv (int srcsize) | |
8955 | { | |
5f1af56b MGD |
8956 | int immbits = srcsize - inst.operands[1].imm; |
8957 | ||
fa94de6b RM |
8958 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) |
8959 | { | |
5f1af56b MGD |
8960 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. |
8961 | i.e. immbits must be in range 0 - 16. */ | |
8962 | inst.error = _("immediate value out of range, expected range [0, 16]"); | |
8963 | return; | |
8964 | } | |
fa94de6b | 8965 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) |
5f1af56b MGD |
8966 | { |
8967 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
8968 | i.e. immbits must be in range 0 - 31. */ | |
8969 | inst.error = _("immediate value out of range, expected range [1, 32]"); | |
8970 | return; | |
8971 | } | |
8972 | ||
5287ad62 JB |
8973 | inst.instruction |= (immbits & 1) << 5; |
8974 | inst.instruction |= (immbits >> 1); | |
8975 | } | |
8976 | ||
8977 | static void | |
8978 | do_vfp_sp_conv_16 (void) | |
8979 | { | |
8980 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8981 | vfp_conv (16); | |
8982 | } | |
8983 | ||
8984 | static void | |
8985 | do_vfp_dp_conv_16 (void) | |
8986 | { | |
8987 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8988 | vfp_conv (16); | |
8989 | } | |
8990 | ||
8991 | static void | |
8992 | do_vfp_sp_conv_32 (void) | |
8993 | { | |
8994 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8995 | vfp_conv (32); | |
8996 | } | |
8997 | ||
8998 | static void | |
8999 | do_vfp_dp_conv_32 (void) | |
9000 | { | |
9001 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
9002 | vfp_conv (32); | |
9003 | } | |
c19d1205 ZW |
9004 | \f |
9005 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 9006 | |
c19d1205 ZW |
9007 | static void |
9008 | do_fpa_cmp (void) | |
9009 | { | |
9010 | inst.instruction |= inst.operands[0].reg << 16; | |
9011 | inst.instruction |= inst.operands[1].reg; | |
9012 | } | |
b99bd4ef NC |
9013 | |
9014 | static void | |
c19d1205 | 9015 | do_fpa_ldmstm (void) |
b99bd4ef | 9016 | { |
c19d1205 ZW |
9017 | inst.instruction |= inst.operands[0].reg << 12; |
9018 | switch (inst.operands[1].imm) | |
9019 | { | |
9020 | case 1: inst.instruction |= CP_T_X; break; | |
9021 | case 2: inst.instruction |= CP_T_Y; break; | |
9022 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
9023 | case 4: break; | |
9024 | default: abort (); | |
9025 | } | |
b99bd4ef | 9026 | |
c19d1205 ZW |
9027 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
9028 | { | |
9029 | /* The instruction specified "ea" or "fd", so we can only accept | |
9030 | [Rn]{!}. The instruction does not really support stacking or | |
9031 | unstacking, so we have to emulate these by setting appropriate | |
9032 | bits and offsets. */ | |
9033 | constraint (inst.reloc.exp.X_op != O_constant | |
9034 | || inst.reloc.exp.X_add_number != 0, | |
9035 | _("this instruction does not support indexing")); | |
b99bd4ef | 9036 | |
c19d1205 ZW |
9037 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
9038 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 9039 | |
c19d1205 ZW |
9040 | if (!(inst.instruction & INDEX_UP)) |
9041 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 9042 | |
c19d1205 ZW |
9043 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
9044 | { | |
9045 | inst.operands[2].preind = 0; | |
9046 | inst.operands[2].postind = 1; | |
9047 | } | |
9048 | } | |
b99bd4ef | 9049 | |
c19d1205 | 9050 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 9051 | } |
c19d1205 ZW |
9052 | \f |
9053 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 9054 | |
c19d1205 ZW |
9055 | static void |
9056 | do_iwmmxt_tandorc (void) | |
9057 | { | |
9058 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
9059 | } | |
b99bd4ef | 9060 | |
c19d1205 ZW |
9061 | static void |
9062 | do_iwmmxt_textrc (void) | |
9063 | { | |
9064 | inst.instruction |= inst.operands[0].reg << 12; | |
9065 | inst.instruction |= inst.operands[1].imm; | |
9066 | } | |
b99bd4ef NC |
9067 | |
9068 | static void | |
c19d1205 | 9069 | do_iwmmxt_textrm (void) |
b99bd4ef | 9070 | { |
c19d1205 ZW |
9071 | inst.instruction |= inst.operands[0].reg << 12; |
9072 | inst.instruction |= inst.operands[1].reg << 16; | |
9073 | inst.instruction |= inst.operands[2].imm; | |
9074 | } | |
b99bd4ef | 9075 | |
c19d1205 ZW |
9076 | static void |
9077 | do_iwmmxt_tinsr (void) | |
9078 | { | |
9079 | inst.instruction |= inst.operands[0].reg << 16; | |
9080 | inst.instruction |= inst.operands[1].reg << 12; | |
9081 | inst.instruction |= inst.operands[2].imm; | |
9082 | } | |
b99bd4ef | 9083 | |
c19d1205 ZW |
9084 | static void |
9085 | do_iwmmxt_tmia (void) | |
9086 | { | |
9087 | inst.instruction |= inst.operands[0].reg << 5; | |
9088 | inst.instruction |= inst.operands[1].reg; | |
9089 | inst.instruction |= inst.operands[2].reg << 12; | |
9090 | } | |
b99bd4ef | 9091 | |
c19d1205 ZW |
9092 | static void |
9093 | do_iwmmxt_waligni (void) | |
9094 | { | |
9095 | inst.instruction |= inst.operands[0].reg << 12; | |
9096 | inst.instruction |= inst.operands[1].reg << 16; | |
9097 | inst.instruction |= inst.operands[2].reg; | |
9098 | inst.instruction |= inst.operands[3].imm << 20; | |
9099 | } | |
b99bd4ef | 9100 | |
2d447fca JM |
9101 | static void |
9102 | do_iwmmxt_wmerge (void) | |
9103 | { | |
9104 | inst.instruction |= inst.operands[0].reg << 12; | |
9105 | inst.instruction |= inst.operands[1].reg << 16; | |
9106 | inst.instruction |= inst.operands[2].reg; | |
9107 | inst.instruction |= inst.operands[3].imm << 21; | |
9108 | } | |
9109 | ||
c19d1205 ZW |
9110 | static void |
9111 | do_iwmmxt_wmov (void) | |
9112 | { | |
9113 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
9114 | inst.instruction |= inst.operands[0].reg << 12; | |
9115 | inst.instruction |= inst.operands[1].reg << 16; | |
9116 | inst.instruction |= inst.operands[1].reg; | |
9117 | } | |
b99bd4ef | 9118 | |
c19d1205 ZW |
9119 | static void |
9120 | do_iwmmxt_wldstbh (void) | |
9121 | { | |
8f06b2d8 | 9122 | int reloc; |
c19d1205 | 9123 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
9124 | if (thumb_mode) |
9125 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
9126 | else | |
9127 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
9128 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
9129 | } |
9130 | ||
c19d1205 ZW |
9131 | static void |
9132 | do_iwmmxt_wldstw (void) | |
9133 | { | |
9134 | /* RIWR_RIWC clears .isreg for a control register. */ | |
9135 | if (!inst.operands[0].isreg) | |
9136 | { | |
9137 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
9138 | inst.instruction |= 0xf0000000; | |
9139 | } | |
b99bd4ef | 9140 | |
c19d1205 ZW |
9141 | inst.instruction |= inst.operands[0].reg << 12; |
9142 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
9143 | } | |
b99bd4ef NC |
9144 | |
9145 | static void | |
c19d1205 | 9146 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9147 | { |
c19d1205 | 9148 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9149 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9150 | && inst.operands[1].immisreg) | |
9151 | { | |
9152 | inst.instruction &= ~0x1a000ff; | |
9153 | inst.instruction |= (0xf << 28); | |
9154 | if (inst.operands[1].preind) | |
9155 | inst.instruction |= PRE_INDEX; | |
9156 | if (!inst.operands[1].negative) | |
9157 | inst.instruction |= INDEX_UP; | |
9158 | if (inst.operands[1].writeback) | |
9159 | inst.instruction |= WRITE_BACK; | |
9160 | inst.instruction |= inst.operands[1].reg << 16; | |
9161 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9162 | inst.instruction |= inst.operands[1].imm; | |
9163 | } | |
9164 | else | |
9165 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9166 | } |
b99bd4ef | 9167 | |
c19d1205 ZW |
9168 | static void |
9169 | do_iwmmxt_wshufh (void) | |
9170 | { | |
9171 | inst.instruction |= inst.operands[0].reg << 12; | |
9172 | inst.instruction |= inst.operands[1].reg << 16; | |
9173 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9174 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9175 | } | |
b99bd4ef | 9176 | |
c19d1205 ZW |
9177 | static void |
9178 | do_iwmmxt_wzero (void) | |
9179 | { | |
9180 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
9181 | inst.instruction |= inst.operands[0].reg; | |
9182 | inst.instruction |= inst.operands[0].reg << 12; | |
9183 | inst.instruction |= inst.operands[0].reg << 16; | |
9184 | } | |
2d447fca JM |
9185 | |
9186 | static void | |
9187 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
9188 | { | |
9189 | if (inst.operands[2].isreg) | |
9190 | do_rd_rn_rm (); | |
9191 | else { | |
9192 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
9193 | _("immediate operand requires iWMMXt2")); | |
9194 | do_rd_rn (); | |
9195 | if (inst.operands[2].imm == 0) | |
9196 | { | |
9197 | switch ((inst.instruction >> 20) & 0xf) | |
9198 | { | |
9199 | case 4: | |
9200 | case 5: | |
9201 | case 6: | |
5f4273c7 | 9202 | case 7: |
2d447fca JM |
9203 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
9204 | inst.operands[2].imm = 16; | |
9205 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
9206 | break; | |
9207 | case 8: | |
9208 | case 9: | |
9209 | case 10: | |
9210 | case 11: | |
9211 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
9212 | inst.operands[2].imm = 32; | |
9213 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
9214 | break; | |
9215 | case 12: | |
9216 | case 13: | |
9217 | case 14: | |
9218 | case 15: | |
9219 | { | |
9220 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
9221 | unsigned long wrn; | |
9222 | wrn = (inst.instruction >> 16) & 0xf; | |
9223 | inst.instruction &= 0xff0fff0f; | |
9224 | inst.instruction |= wrn; | |
9225 | /* Bail out here; the instruction is now assembled. */ | |
9226 | return; | |
9227 | } | |
9228 | } | |
9229 | } | |
9230 | /* Map 32 -> 0, etc. */ | |
9231 | inst.operands[2].imm &= 0x1f; | |
9232 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
9233 | } | |
9234 | } | |
c19d1205 ZW |
9235 | \f |
9236 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
9237 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 9238 | |
c19d1205 | 9239 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 9240 | |
c19d1205 ZW |
9241 | static void |
9242 | do_mav_triple (void) | |
9243 | { | |
9244 | inst.instruction |= inst.operands[0].reg << 16; | |
9245 | inst.instruction |= inst.operands[1].reg; | |
9246 | inst.instruction |= inst.operands[2].reg << 12; | |
9247 | } | |
b99bd4ef | 9248 | |
c19d1205 ZW |
9249 | /* Insns like "foo W,X,Y,Z". |
9250 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 9251 | |
c19d1205 ZW |
9252 | static void |
9253 | do_mav_quad (void) | |
9254 | { | |
9255 | inst.instruction |= inst.operands[0].reg << 5; | |
9256 | inst.instruction |= inst.operands[1].reg << 12; | |
9257 | inst.instruction |= inst.operands[2].reg << 16; | |
9258 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
9259 | } |
9260 | ||
c19d1205 ZW |
9261 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
9262 | static void | |
9263 | do_mav_dspsc (void) | |
a737bd4d | 9264 | { |
c19d1205 ZW |
9265 | inst.instruction |= inst.operands[1].reg << 12; |
9266 | } | |
a737bd4d | 9267 | |
c19d1205 ZW |
9268 | /* Maverick shift immediate instructions. |
9269 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
9270 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 9271 | |
c19d1205 ZW |
9272 | static void |
9273 | do_mav_shift (void) | |
9274 | { | |
9275 | int imm = inst.operands[2].imm; | |
a737bd4d | 9276 | |
c19d1205 ZW |
9277 | inst.instruction |= inst.operands[0].reg << 12; |
9278 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 9279 | |
c19d1205 ZW |
9280 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
9281 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
9282 | Bit 4 should be 0. */ | |
9283 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 9284 | |
c19d1205 ZW |
9285 | inst.instruction |= imm; |
9286 | } | |
9287 | \f | |
9288 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 9289 | |
c19d1205 ZW |
9290 | /* Xscale multiply-accumulate (argument parse) |
9291 | MIAcc acc0,Rm,Rs | |
9292 | MIAPHcc acc0,Rm,Rs | |
9293 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 9294 | |
c19d1205 ZW |
9295 | static void |
9296 | do_xsc_mia (void) | |
9297 | { | |
9298 | inst.instruction |= inst.operands[1].reg; | |
9299 | inst.instruction |= inst.operands[2].reg << 12; | |
9300 | } | |
a737bd4d | 9301 | |
c19d1205 | 9302 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9303 | |
c19d1205 | 9304 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9305 | |
c19d1205 ZW |
9306 | static void |
9307 | do_xsc_mar (void) | |
9308 | { | |
9309 | inst.instruction |= inst.operands[1].reg << 12; | |
9310 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9311 | } |
9312 | ||
c19d1205 | 9313 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9314 | |
c19d1205 | 9315 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9316 | |
9317 | static void | |
c19d1205 | 9318 | do_xsc_mra (void) |
b99bd4ef | 9319 | { |
c19d1205 ZW |
9320 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9321 | inst.instruction |= inst.operands[0].reg << 12; | |
9322 | inst.instruction |= inst.operands[1].reg << 16; | |
9323 | } | |
9324 | \f | |
9325 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9326 | |
c19d1205 ZW |
9327 | /* inst.operands[i] is a shifted-register operand; encode |
9328 | it into inst.instruction in the format used by Thumb32. */ | |
9329 | ||
9330 | static void | |
9331 | encode_thumb32_shifted_operand (int i) | |
9332 | { | |
9333 | unsigned int value = inst.reloc.exp.X_add_number; | |
9334 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9335 | |
9c3c69f2 PB |
9336 | constraint (inst.operands[i].immisreg, |
9337 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9338 | inst.instruction |= inst.operands[i].reg; |
9339 | if (shift == SHIFT_RRX) | |
9340 | inst.instruction |= SHIFT_ROR << 4; | |
9341 | else | |
b99bd4ef | 9342 | { |
c19d1205 ZW |
9343 | constraint (inst.reloc.exp.X_op != O_constant, |
9344 | _("expression too complex")); | |
9345 | ||
9346 | constraint (value > 32 | |
9347 | || (value == 32 && (shift == SHIFT_LSL | |
9348 | || shift == SHIFT_ROR)), | |
9349 | _("shift expression is too large")); | |
9350 | ||
9351 | if (value == 0) | |
9352 | shift = SHIFT_LSL; | |
9353 | else if (value == 32) | |
9354 | value = 0; | |
9355 | ||
9356 | inst.instruction |= shift << 4; | |
9357 | inst.instruction |= (value & 0x1c) << 10; | |
9358 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9359 | } |
c19d1205 | 9360 | } |
b99bd4ef | 9361 | |
b99bd4ef | 9362 | |
c19d1205 ZW |
9363 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9364 | Thumb32 format load or store instruction. Reject forms that cannot | |
9365 | be used with such instructions. If is_t is true, reject forms that | |
9366 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9367 | that cannot be used with a D instruction. If it is a store insn, |
9368 | reject PC in Rn. */ | |
b99bd4ef | 9369 | |
c19d1205 ZW |
9370 | static void |
9371 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9372 | { | |
5be8be5d | 9373 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9374 | |
9375 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9376 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9377 | |
c19d1205 ZW |
9378 | inst.instruction |= inst.operands[i].reg << 16; |
9379 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9380 | { |
5be8be5d | 9381 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9382 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9383 | constraint (inst.operands[i].negative, | |
9384 | _("Thumb does not support negative register indexing")); | |
9385 | constraint (inst.operands[i].postind, | |
9386 | _("Thumb does not support register post-indexing")); | |
9387 | constraint (inst.operands[i].writeback, | |
9388 | _("Thumb does not support register indexing with writeback")); | |
9389 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
9390 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 9391 | |
f40d1643 | 9392 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 9393 | if (inst.operands[i].shifted) |
b99bd4ef | 9394 | { |
c19d1205 ZW |
9395 | constraint (inst.reloc.exp.X_op != O_constant, |
9396 | _("expression too complex")); | |
9c3c69f2 PB |
9397 | constraint (inst.reloc.exp.X_add_number < 0 |
9398 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 9399 | _("shift out of range")); |
9c3c69f2 | 9400 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
9401 | } |
9402 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9403 | } | |
9404 | else if (inst.operands[i].preind) | |
9405 | { | |
5be8be5d | 9406 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 9407 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 9408 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
9409 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
9410 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
9411 | |
9412 | if (is_d) | |
9413 | { | |
9414 | inst.instruction |= 0x01000000; | |
9415 | if (inst.operands[i].writeback) | |
9416 | inst.instruction |= 0x00200000; | |
b99bd4ef | 9417 | } |
c19d1205 | 9418 | else |
b99bd4ef | 9419 | { |
c19d1205 ZW |
9420 | inst.instruction |= 0x00000c00; |
9421 | if (inst.operands[i].writeback) | |
9422 | inst.instruction |= 0x00000100; | |
b99bd4ef | 9423 | } |
c19d1205 | 9424 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 9425 | } |
c19d1205 | 9426 | else if (inst.operands[i].postind) |
b99bd4ef | 9427 | { |
9c2799c2 | 9428 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
9429 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
9430 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
9431 | ||
9432 | if (is_d) | |
9433 | inst.instruction |= 0x00200000; | |
9434 | else | |
9435 | inst.instruction |= 0x00000900; | |
9436 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
9437 | } | |
9438 | else /* unindexed - only for coprocessor */ | |
9439 | inst.error = _("instruction does not accept unindexed addressing"); | |
9440 | } | |
9441 | ||
9442 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
9443 | encodings (the latter only in post-V6T2 cores). The index is the | |
9444 | value used in the insns table below. When there is more than one | |
9445 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
9446 | holds variant (1). |
9447 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 9448 | #define T16_32_TAB \ |
21d799b5 NC |
9449 | X(_adc, 4140, eb400000), \ |
9450 | X(_adcs, 4140, eb500000), \ | |
9451 | X(_add, 1c00, eb000000), \ | |
9452 | X(_adds, 1c00, eb100000), \ | |
9453 | X(_addi, 0000, f1000000), \ | |
9454 | X(_addis, 0000, f1100000), \ | |
9455 | X(_add_pc,000f, f20f0000), \ | |
9456 | X(_add_sp,000d, f10d0000), \ | |
9457 | X(_adr, 000f, f20f0000), \ | |
9458 | X(_and, 4000, ea000000), \ | |
9459 | X(_ands, 4000, ea100000), \ | |
9460 | X(_asr, 1000, fa40f000), \ | |
9461 | X(_asrs, 1000, fa50f000), \ | |
9462 | X(_b, e000, f000b000), \ | |
9463 | X(_bcond, d000, f0008000), \ | |
9464 | X(_bic, 4380, ea200000), \ | |
9465 | X(_bics, 4380, ea300000), \ | |
9466 | X(_cmn, 42c0, eb100f00), \ | |
9467 | X(_cmp, 2800, ebb00f00), \ | |
9468 | X(_cpsie, b660, f3af8400), \ | |
9469 | X(_cpsid, b670, f3af8600), \ | |
9470 | X(_cpy, 4600, ea4f0000), \ | |
9471 | X(_dec_sp,80dd, f1ad0d00), \ | |
9472 | X(_eor, 4040, ea800000), \ | |
9473 | X(_eors, 4040, ea900000), \ | |
9474 | X(_inc_sp,00dd, f10d0d00), \ | |
9475 | X(_ldmia, c800, e8900000), \ | |
9476 | X(_ldr, 6800, f8500000), \ | |
9477 | X(_ldrb, 7800, f8100000), \ | |
9478 | X(_ldrh, 8800, f8300000), \ | |
9479 | X(_ldrsb, 5600, f9100000), \ | |
9480 | X(_ldrsh, 5e00, f9300000), \ | |
9481 | X(_ldr_pc,4800, f85f0000), \ | |
9482 | X(_ldr_pc2,4800, f85f0000), \ | |
9483 | X(_ldr_sp,9800, f85d0000), \ | |
9484 | X(_lsl, 0000, fa00f000), \ | |
9485 | X(_lsls, 0000, fa10f000), \ | |
9486 | X(_lsr, 0800, fa20f000), \ | |
9487 | X(_lsrs, 0800, fa30f000), \ | |
9488 | X(_mov, 2000, ea4f0000), \ | |
9489 | X(_movs, 2000, ea5f0000), \ | |
9490 | X(_mul, 4340, fb00f000), \ | |
9491 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
9492 | X(_mvn, 43c0, ea6f0000), \ | |
9493 | X(_mvns, 43c0, ea7f0000), \ | |
9494 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
9495 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
9496 | X(_orr, 4300, ea400000), \ | |
9497 | X(_orrs, 4300, ea500000), \ | |
9498 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
9499 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
9500 | X(_rev, ba00, fa90f080), \ | |
9501 | X(_rev16, ba40, fa90f090), \ | |
9502 | X(_revsh, bac0, fa90f0b0), \ | |
9503 | X(_ror, 41c0, fa60f000), \ | |
9504 | X(_rors, 41c0, fa70f000), \ | |
9505 | X(_sbc, 4180, eb600000), \ | |
9506 | X(_sbcs, 4180, eb700000), \ | |
9507 | X(_stmia, c000, e8800000), \ | |
9508 | X(_str, 6000, f8400000), \ | |
9509 | X(_strb, 7000, f8000000), \ | |
9510 | X(_strh, 8000, f8200000), \ | |
9511 | X(_str_sp,9000, f84d0000), \ | |
9512 | X(_sub, 1e00, eba00000), \ | |
9513 | X(_subs, 1e00, ebb00000), \ | |
9514 | X(_subi, 8000, f1a00000), \ | |
9515 | X(_subis, 8000, f1b00000), \ | |
9516 | X(_sxtb, b240, fa4ff080), \ | |
9517 | X(_sxth, b200, fa0ff080), \ | |
9518 | X(_tst, 4200, ea100f00), \ | |
9519 | X(_uxtb, b2c0, fa5ff080), \ | |
9520 | X(_uxth, b280, fa1ff080), \ | |
9521 | X(_nop, bf00, f3af8000), \ | |
9522 | X(_yield, bf10, f3af8001), \ | |
9523 | X(_wfe, bf20, f3af8002), \ | |
9524 | X(_wfi, bf30, f3af8003), \ | |
9525 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
9526 | |
9527 | /* To catch errors in encoding functions, the codes are all offset by | |
9528 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
9529 | as 16-bit instructions. */ | |
21d799b5 | 9530 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
9531 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
9532 | #undef X | |
9533 | ||
9534 | #define X(a,b,c) 0x##b | |
9535 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
9536 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
9537 | #undef X | |
9538 | ||
9539 | #define X(a,b,c) 0x##c | |
9540 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
9541 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
9542 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
9543 | #undef X |
9544 | #undef T16_32_TAB | |
9545 | ||
9546 | /* Thumb instruction encoders, in alphabetical order. */ | |
9547 | ||
92e90b6e | 9548 | /* ADDW or SUBW. */ |
c921be7d | 9549 | |
92e90b6e PB |
9550 | static void |
9551 | do_t_add_sub_w (void) | |
9552 | { | |
9553 | int Rd, Rn; | |
9554 | ||
9555 | Rd = inst.operands[0].reg; | |
9556 | Rn = inst.operands[1].reg; | |
9557 | ||
539d4391 NC |
9558 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
9559 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
9560 | if (Rn == REG_SP) | |
9561 | constraint (Rd == REG_PC, BAD_PC); | |
9562 | else | |
9563 | reject_bad_reg (Rd); | |
fdfde340 | 9564 | |
92e90b6e PB |
9565 | inst.instruction |= (Rn << 16) | (Rd << 8); |
9566 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9567 | } | |
9568 | ||
c19d1205 ZW |
9569 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9570 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9571 | ||
9572 | static void | |
9573 | do_t_add_sub (void) | |
9574 | { | |
9575 | int Rd, Rs, Rn; | |
9576 | ||
9577 | Rd = inst.operands[0].reg; | |
9578 | Rs = (inst.operands[1].present | |
9579 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9580 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9581 | ||
e07e6e58 NC |
9582 | if (Rd == REG_PC) |
9583 | set_it_insn_type_last (); | |
9584 | ||
c19d1205 ZW |
9585 | if (unified_syntax) |
9586 | { | |
0110f2b8 PB |
9587 | bfd_boolean flags; |
9588 | bfd_boolean narrow; | |
9589 | int opcode; | |
9590 | ||
9591 | flags = (inst.instruction == T_MNEM_adds | |
9592 | || inst.instruction == T_MNEM_subs); | |
9593 | if (flags) | |
e07e6e58 | 9594 | narrow = !in_it_block (); |
0110f2b8 | 9595 | else |
e07e6e58 | 9596 | narrow = in_it_block (); |
c19d1205 | 9597 | if (!inst.operands[2].isreg) |
b99bd4ef | 9598 | { |
16805f35 PB |
9599 | int add; |
9600 | ||
fdfde340 JM |
9601 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9602 | ||
16805f35 PB |
9603 | add = (inst.instruction == T_MNEM_add |
9604 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9605 | opcode = 0; |
9606 | if (inst.size_req != 4) | |
9607 | { | |
0110f2b8 PB |
9608 | /* Attempt to use a narrow opcode, with relaxation if |
9609 | appropriate. */ | |
9610 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9611 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9612 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9613 | opcode = T_MNEM_add_sp; | |
9614 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9615 | opcode = T_MNEM_add_pc; | |
9616 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9617 | { | |
9618 | if (flags) | |
9619 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9620 | else | |
9621 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9622 | } | |
9623 | if (opcode) | |
9624 | { | |
9625 | inst.instruction = THUMB_OP16(opcode); | |
9626 | inst.instruction |= (Rd << 4) | Rs; | |
9627 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9628 | if (inst.size_req != 2) | |
9629 | inst.relax = opcode; | |
9630 | } | |
9631 | else | |
9632 | constraint (inst.size_req == 2, BAD_HIREG); | |
9633 | } | |
9634 | if (inst.size_req == 4 | |
9635 | || (inst.size_req != 2 && !opcode)) | |
9636 | { | |
efd81785 PB |
9637 | if (Rd == REG_PC) |
9638 | { | |
fdfde340 | 9639 | constraint (add, BAD_PC); |
efd81785 PB |
9640 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9641 | _("only SUBS PC, LR, #const allowed")); | |
9642 | constraint (inst.reloc.exp.X_op != O_constant, | |
9643 | _("expression too complex")); | |
9644 | constraint (inst.reloc.exp.X_add_number < 0 | |
9645 | || inst.reloc.exp.X_add_number > 0xff, | |
9646 | _("immediate value out of range")); | |
9647 | inst.instruction = T2_SUBS_PC_LR | |
9648 | | inst.reloc.exp.X_add_number; | |
9649 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9650 | return; | |
9651 | } | |
9652 | else if (Rs == REG_PC) | |
16805f35 PB |
9653 | { |
9654 | /* Always use addw/subw. */ | |
9655 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9656 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9657 | } | |
9658 | else | |
9659 | { | |
9660 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9661 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9662 | | 0x10000000; | |
9663 | if (flags) | |
9664 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9665 | else | |
9666 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9667 | } | |
dc4503c6 PB |
9668 | inst.instruction |= Rd << 8; |
9669 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9670 | } |
b99bd4ef | 9671 | } |
c19d1205 ZW |
9672 | else |
9673 | { | |
5f4cb198 NC |
9674 | unsigned int value = inst.reloc.exp.X_add_number; |
9675 | unsigned int shift = inst.operands[2].shift_kind; | |
9676 | ||
c19d1205 ZW |
9677 | Rn = inst.operands[2].reg; |
9678 | /* See if we can do this with a 16-bit instruction. */ | |
9679 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9680 | { | |
e27ec89e PB |
9681 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9682 | narrow = FALSE; | |
9683 | ||
9684 | if (narrow) | |
c19d1205 | 9685 | { |
e27ec89e PB |
9686 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9687 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9688 | ? T_OPCODE_ADD_R3 |
9689 | : T_OPCODE_SUB_R3); | |
9690 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9691 | return; | |
9692 | } | |
b99bd4ef | 9693 | |
7e806470 | 9694 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9695 | { |
7e806470 PB |
9696 | /* Thumb-1 cores (except v6-M) require at least one high |
9697 | register in a narrow non flag setting add. */ | |
9698 | if (Rd > 7 || Rn > 7 | |
9699 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9700 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9701 | { |
7e806470 PB |
9702 | if (Rd == Rn) |
9703 | { | |
9704 | Rn = Rs; | |
9705 | Rs = Rd; | |
9706 | } | |
c19d1205 ZW |
9707 | inst.instruction = T_OPCODE_ADD_HI; |
9708 | inst.instruction |= (Rd & 8) << 4; | |
9709 | inst.instruction |= (Rd & 7); | |
9710 | inst.instruction |= Rn << 3; | |
9711 | return; | |
9712 | } | |
c19d1205 ZW |
9713 | } |
9714 | } | |
c921be7d | 9715 | |
fdfde340 JM |
9716 | constraint (Rd == REG_PC, BAD_PC); |
9717 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9718 | constraint (Rs == REG_PC, BAD_PC); | |
9719 | reject_bad_reg (Rn); | |
9720 | ||
c19d1205 ZW |
9721 | /* If we get here, it can't be done in 16 bits. */ |
9722 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9723 | _("shift must be constant")); | |
9724 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9725 | inst.instruction |= Rd << 8; | |
9726 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
9727 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
9728 | _("shift value over 3 not allowed in thumb mode")); | |
9729 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
9730 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
9731 | encode_thumb32_shifted_operand (2); |
9732 | } | |
9733 | } | |
9734 | else | |
9735 | { | |
9736 | constraint (inst.instruction == T_MNEM_adds | |
9737 | || inst.instruction == T_MNEM_subs, | |
9738 | BAD_THUMB32); | |
b99bd4ef | 9739 | |
c19d1205 | 9740 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9741 | { |
c19d1205 ZW |
9742 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9743 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9744 | BAD_HIREG); | |
9745 | ||
9746 | inst.instruction = (inst.instruction == T_MNEM_add | |
9747 | ? 0x0000 : 0x8000); | |
9748 | inst.instruction |= (Rd << 4) | Rs; | |
9749 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9750 | return; |
9751 | } | |
9752 | ||
c19d1205 ZW |
9753 | Rn = inst.operands[2].reg; |
9754 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9755 | |
c19d1205 ZW |
9756 | /* We now have Rd, Rs, and Rn set to registers. */ |
9757 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9758 | { |
c19d1205 ZW |
9759 | /* Can't do this for SUB. */ |
9760 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9761 | inst.instruction = T_OPCODE_ADD_HI; | |
9762 | inst.instruction |= (Rd & 8) << 4; | |
9763 | inst.instruction |= (Rd & 7); | |
9764 | if (Rs == Rd) | |
9765 | inst.instruction |= Rn << 3; | |
9766 | else if (Rn == Rd) | |
9767 | inst.instruction |= Rs << 3; | |
9768 | else | |
9769 | constraint (1, _("dest must overlap one source register")); | |
9770 | } | |
9771 | else | |
9772 | { | |
9773 | inst.instruction = (inst.instruction == T_MNEM_add | |
9774 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9775 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9776 | } |
b99bd4ef | 9777 | } |
b99bd4ef NC |
9778 | } |
9779 | ||
c19d1205 ZW |
9780 | static void |
9781 | do_t_adr (void) | |
9782 | { | |
fdfde340 JM |
9783 | unsigned Rd; |
9784 | ||
9785 | Rd = inst.operands[0].reg; | |
9786 | reject_bad_reg (Rd); | |
9787 | ||
9788 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9789 | { |
9790 | /* Defer to section relaxation. */ | |
9791 | inst.relax = inst.instruction; | |
9792 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9793 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9794 | } |
9795 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9796 | { |
0110f2b8 | 9797 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9798 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9799 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9800 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9801 | inst.reloc.pc_rel = 1; | |
9802 | } | |
9803 | else | |
9804 | { | |
0110f2b8 | 9805 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9806 | inst.instruction = THUMB_OP16 (inst.instruction); |
9807 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9808 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9809 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9810 | |
fdfde340 | 9811 | inst.instruction |= Rd << 4; |
e9f89963 | 9812 | } |
c19d1205 | 9813 | } |
b99bd4ef | 9814 | |
c19d1205 ZW |
9815 | /* Arithmetic instructions for which there is just one 16-bit |
9816 | instruction encoding, and it allows only two low registers. | |
9817 | For maximal compatibility with ARM syntax, we allow three register | |
9818 | operands even when Thumb-32 instructions are not available, as long | |
9819 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9820 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9821 | static void |
c19d1205 | 9822 | do_t_arit3 (void) |
b99bd4ef | 9823 | { |
c19d1205 | 9824 | int Rd, Rs, Rn; |
b99bd4ef | 9825 | |
c19d1205 ZW |
9826 | Rd = inst.operands[0].reg; |
9827 | Rs = (inst.operands[1].present | |
9828 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9829 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9830 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9831 | |
fdfde340 JM |
9832 | reject_bad_reg (Rd); |
9833 | reject_bad_reg (Rs); | |
9834 | if (inst.operands[2].isreg) | |
9835 | reject_bad_reg (Rn); | |
9836 | ||
c19d1205 | 9837 | if (unified_syntax) |
b99bd4ef | 9838 | { |
c19d1205 ZW |
9839 | if (!inst.operands[2].isreg) |
9840 | { | |
9841 | /* For an immediate, we always generate a 32-bit opcode; | |
9842 | section relaxation will shrink it later if possible. */ | |
9843 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9844 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9845 | inst.instruction |= Rd << 8; | |
9846 | inst.instruction |= Rs << 16; | |
9847 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9848 | } | |
9849 | else | |
9850 | { | |
e27ec89e PB |
9851 | bfd_boolean narrow; |
9852 | ||
c19d1205 | 9853 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9854 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9855 | narrow = !in_it_block (); |
e27ec89e | 9856 | else |
e07e6e58 | 9857 | narrow = in_it_block (); |
e27ec89e PB |
9858 | |
9859 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9860 | narrow = FALSE; | |
9861 | if (inst.operands[2].shifted) | |
9862 | narrow = FALSE; | |
9863 | if (inst.size_req == 4) | |
9864 | narrow = FALSE; | |
9865 | ||
9866 | if (narrow | |
c19d1205 ZW |
9867 | && Rd == Rs) |
9868 | { | |
9869 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9870 | inst.instruction |= Rd; | |
9871 | inst.instruction |= Rn << 3; | |
9872 | return; | |
9873 | } | |
b99bd4ef | 9874 | |
c19d1205 ZW |
9875 | /* If we get here, it can't be done in 16 bits. */ |
9876 | constraint (inst.operands[2].shifted | |
9877 | && inst.operands[2].immisreg, | |
9878 | _("shift must be constant")); | |
9879 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9880 | inst.instruction |= Rd << 8; | |
9881 | inst.instruction |= Rs << 16; | |
9882 | encode_thumb32_shifted_operand (2); | |
9883 | } | |
a737bd4d | 9884 | } |
c19d1205 | 9885 | else |
b99bd4ef | 9886 | { |
c19d1205 ZW |
9887 | /* On its face this is a lie - the instruction does set the |
9888 | flags. However, the only supported mnemonic in this mode | |
9889 | says it doesn't. */ | |
9890 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9891 | |
c19d1205 ZW |
9892 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9893 | _("unshifted register required")); | |
9894 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9895 | constraint (Rd != Rs, | |
9896 | _("dest and source1 must be the same register")); | |
a737bd4d | 9897 | |
c19d1205 ZW |
9898 | inst.instruction = THUMB_OP16 (inst.instruction); |
9899 | inst.instruction |= Rd; | |
9900 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9901 | } |
a737bd4d | 9902 | } |
b99bd4ef | 9903 | |
c19d1205 ZW |
9904 | /* Similarly, but for instructions where the arithmetic operation is |
9905 | commutative, so we can allow either of them to be different from | |
9906 | the destination operand in a 16-bit instruction. For instance, all | |
9907 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9908 | accepted. */ | |
9909 | static void | |
9910 | do_t_arit3c (void) | |
a737bd4d | 9911 | { |
c19d1205 | 9912 | int Rd, Rs, Rn; |
b99bd4ef | 9913 | |
c19d1205 ZW |
9914 | Rd = inst.operands[0].reg; |
9915 | Rs = (inst.operands[1].present | |
9916 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9917 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9918 | Rn = inst.operands[2].reg; | |
c921be7d | 9919 | |
fdfde340 JM |
9920 | reject_bad_reg (Rd); |
9921 | reject_bad_reg (Rs); | |
9922 | if (inst.operands[2].isreg) | |
9923 | reject_bad_reg (Rn); | |
a737bd4d | 9924 | |
c19d1205 | 9925 | if (unified_syntax) |
a737bd4d | 9926 | { |
c19d1205 | 9927 | if (!inst.operands[2].isreg) |
b99bd4ef | 9928 | { |
c19d1205 ZW |
9929 | /* For an immediate, we always generate a 32-bit opcode; |
9930 | section relaxation will shrink it later if possible. */ | |
9931 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9932 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9933 | inst.instruction |= Rd << 8; | |
9934 | inst.instruction |= Rs << 16; | |
9935 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9936 | } |
c19d1205 | 9937 | else |
a737bd4d | 9938 | { |
e27ec89e PB |
9939 | bfd_boolean narrow; |
9940 | ||
c19d1205 | 9941 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9942 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9943 | narrow = !in_it_block (); |
e27ec89e | 9944 | else |
e07e6e58 | 9945 | narrow = in_it_block (); |
e27ec89e PB |
9946 | |
9947 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9948 | narrow = FALSE; | |
9949 | if (inst.operands[2].shifted) | |
9950 | narrow = FALSE; | |
9951 | if (inst.size_req == 4) | |
9952 | narrow = FALSE; | |
9953 | ||
9954 | if (narrow) | |
a737bd4d | 9955 | { |
c19d1205 | 9956 | if (Rd == Rs) |
a737bd4d | 9957 | { |
c19d1205 ZW |
9958 | inst.instruction = THUMB_OP16 (inst.instruction); |
9959 | inst.instruction |= Rd; | |
9960 | inst.instruction |= Rn << 3; | |
9961 | return; | |
a737bd4d | 9962 | } |
c19d1205 | 9963 | if (Rd == Rn) |
a737bd4d | 9964 | { |
c19d1205 ZW |
9965 | inst.instruction = THUMB_OP16 (inst.instruction); |
9966 | inst.instruction |= Rd; | |
9967 | inst.instruction |= Rs << 3; | |
9968 | return; | |
a737bd4d NC |
9969 | } |
9970 | } | |
c19d1205 ZW |
9971 | |
9972 | /* If we get here, it can't be done in 16 bits. */ | |
9973 | constraint (inst.operands[2].shifted | |
9974 | && inst.operands[2].immisreg, | |
9975 | _("shift must be constant")); | |
9976 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9977 | inst.instruction |= Rd << 8; | |
9978 | inst.instruction |= Rs << 16; | |
9979 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9980 | } |
b99bd4ef | 9981 | } |
c19d1205 ZW |
9982 | else |
9983 | { | |
9984 | /* On its face this is a lie - the instruction does set the | |
9985 | flags. However, the only supported mnemonic in this mode | |
9986 | says it doesn't. */ | |
9987 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9988 | |
c19d1205 ZW |
9989 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9990 | _("unshifted register required")); | |
9991 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9992 | ||
9993 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9994 | inst.instruction |= Rd; | |
9995 | ||
9996 | if (Rd == Rs) | |
9997 | inst.instruction |= Rn << 3; | |
9998 | else if (Rd == Rn) | |
9999 | inst.instruction |= Rs << 3; | |
10000 | else | |
10001 | constraint (1, _("dest must overlap one source register")); | |
10002 | } | |
a737bd4d NC |
10003 | } |
10004 | ||
62b3e311 PB |
10005 | static void |
10006 | do_t_barrier (void) | |
10007 | { | |
10008 | if (inst.operands[0].present) | |
10009 | { | |
10010 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
10011 | && inst.operands[0].imm > 0xf |
10012 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 10013 | _("bad barrier type")); |
62b3e311 PB |
10014 | inst.instruction |= inst.operands[0].imm; |
10015 | } | |
10016 | else | |
10017 | inst.instruction |= 0xf; | |
10018 | } | |
10019 | ||
c19d1205 ZW |
10020 | static void |
10021 | do_t_bfc (void) | |
a737bd4d | 10022 | { |
fdfde340 | 10023 | unsigned Rd; |
c19d1205 ZW |
10024 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
10025 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10026 | /* The instruction encoding stores the LSB and MSB, | |
10027 | not the LSB and width. */ | |
fdfde340 JM |
10028 | Rd = inst.operands[0].reg; |
10029 | reject_bad_reg (Rd); | |
10030 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
10031 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
10032 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
10033 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10034 | } |
10035 | ||
c19d1205 ZW |
10036 | static void |
10037 | do_t_bfi (void) | |
b99bd4ef | 10038 | { |
fdfde340 | 10039 | int Rd, Rn; |
c19d1205 | 10040 | unsigned int msb; |
b99bd4ef | 10041 | |
fdfde340 JM |
10042 | Rd = inst.operands[0].reg; |
10043 | reject_bad_reg (Rd); | |
10044 | ||
c19d1205 ZW |
10045 | /* #0 in second position is alternative syntax for bfc, which is |
10046 | the same instruction but with REG_PC in the Rm field. */ | |
10047 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
10048 | Rn = REG_PC; |
10049 | else | |
10050 | { | |
10051 | Rn = inst.operands[1].reg; | |
10052 | reject_bad_reg (Rn); | |
10053 | } | |
b99bd4ef | 10054 | |
c19d1205 ZW |
10055 | msb = inst.operands[2].imm + inst.operands[3].imm; |
10056 | constraint (msb > 32, _("bit-field extends past end of register")); | |
10057 | /* The instruction encoding stores the LSB and MSB, | |
10058 | not the LSB and width. */ | |
fdfde340 JM |
10059 | inst.instruction |= Rd << 8; |
10060 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10061 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10062 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10063 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
10064 | } |
10065 | ||
c19d1205 ZW |
10066 | static void |
10067 | do_t_bfx (void) | |
b99bd4ef | 10068 | { |
fdfde340 JM |
10069 | unsigned Rd, Rn; |
10070 | ||
10071 | Rd = inst.operands[0].reg; | |
10072 | Rn = inst.operands[1].reg; | |
10073 | ||
10074 | reject_bad_reg (Rd); | |
10075 | reject_bad_reg (Rn); | |
10076 | ||
c19d1205 ZW |
10077 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
10078 | _("bit-field extends past end of register")); | |
fdfde340 JM |
10079 | inst.instruction |= Rd << 8; |
10080 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
10081 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
10082 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
10083 | inst.instruction |= inst.operands[3].imm - 1; | |
10084 | } | |
b99bd4ef | 10085 | |
c19d1205 ZW |
10086 | /* ARM V5 Thumb BLX (argument parse) |
10087 | BLX <target_addr> which is BLX(1) | |
10088 | BLX <Rm> which is BLX(2) | |
10089 | Unfortunately, there are two different opcodes for this mnemonic. | |
10090 | So, the insns[].value is not used, and the code here zaps values | |
10091 | into inst.instruction. | |
b99bd4ef | 10092 | |
c19d1205 ZW |
10093 | ??? How to take advantage of the additional two bits of displacement |
10094 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 10095 | |
c19d1205 ZW |
10096 | static void |
10097 | do_t_blx (void) | |
10098 | { | |
e07e6e58 NC |
10099 | set_it_insn_type_last (); |
10100 | ||
c19d1205 | 10101 | if (inst.operands[0].isreg) |
fdfde340 JM |
10102 | { |
10103 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
10104 | /* We have a register, so this is BLX(2). */ | |
10105 | inst.instruction |= inst.operands[0].reg << 3; | |
10106 | } | |
b99bd4ef NC |
10107 | else |
10108 | { | |
c19d1205 | 10109 | /* No register. This must be BLX(1). */ |
2fc8bdac | 10110 | inst.instruction = 0xf000e800; |
0855e32b | 10111 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
10112 | } |
10113 | } | |
10114 | ||
c19d1205 ZW |
10115 | static void |
10116 | do_t_branch (void) | |
b99bd4ef | 10117 | { |
0110f2b8 | 10118 | int opcode; |
dfa9f0d5 | 10119 | int cond; |
9ae92b05 | 10120 | int reloc; |
dfa9f0d5 | 10121 | |
e07e6e58 NC |
10122 | cond = inst.cond; |
10123 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
10124 | ||
10125 | if (in_it_block ()) | |
dfa9f0d5 PB |
10126 | { |
10127 | /* Conditional branches inside IT blocks are encoded as unconditional | |
10128 | branches. */ | |
10129 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
10130 | } |
10131 | else | |
10132 | cond = inst.cond; | |
10133 | ||
10134 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
10135 | opcode = T_MNEM_bcond; |
10136 | else | |
10137 | opcode = inst.instruction; | |
10138 | ||
12d6b0b7 RS |
10139 | if (unified_syntax |
10140 | && (inst.size_req == 4 | |
10960bfb PB |
10141 | || (inst.size_req != 2 |
10142 | && (inst.operands[0].hasreloc | |
10143 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10144 | { |
0110f2b8 | 10145 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10146 | if (cond == COND_ALWAYS) |
9ae92b05 | 10147 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10148 | else |
10149 | { | |
9c2799c2 | 10150 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10151 | inst.instruction |= cond << 22; |
9ae92b05 | 10152 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10153 | } |
10154 | } | |
b99bd4ef NC |
10155 | else |
10156 | { | |
0110f2b8 | 10157 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10158 | if (cond == COND_ALWAYS) |
9ae92b05 | 10159 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10160 | else |
b99bd4ef | 10161 | { |
dfa9f0d5 | 10162 | inst.instruction |= cond << 8; |
9ae92b05 | 10163 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10164 | } |
0110f2b8 PB |
10165 | /* Allow section relaxation. */ |
10166 | if (unified_syntax && inst.size_req != 2) | |
10167 | inst.relax = opcode; | |
b99bd4ef | 10168 | } |
9ae92b05 | 10169 | inst.reloc.type = reloc; |
c19d1205 | 10170 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10171 | } |
10172 | ||
10173 | static void | |
c19d1205 | 10174 | do_t_bkpt (void) |
b99bd4ef | 10175 | { |
dfa9f0d5 PB |
10176 | constraint (inst.cond != COND_ALWAYS, |
10177 | _("instruction is always unconditional")); | |
c19d1205 | 10178 | if (inst.operands[0].present) |
b99bd4ef | 10179 | { |
c19d1205 ZW |
10180 | constraint (inst.operands[0].imm > 255, |
10181 | _("immediate value out of range")); | |
10182 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 10183 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 10184 | } |
b99bd4ef NC |
10185 | } |
10186 | ||
10187 | static void | |
c19d1205 | 10188 | do_t_branch23 (void) |
b99bd4ef | 10189 | { |
e07e6e58 | 10190 | set_it_insn_type_last (); |
0855e32b | 10191 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
fa94de6b | 10192 | |
0855e32b NS |
10193 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in |
10194 | this file. We used to simply ignore the PLT reloc type here -- | |
10195 | the branch encoding is now needed to deal with TLSCALL relocs. | |
10196 | So if we see a PLT reloc now, put it back to how it used to be to | |
10197 | keep the preexisting behaviour. */ | |
10198 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
10199 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 10200 | |
4343666d | 10201 | #if defined(OBJ_COFF) |
c19d1205 ZW |
10202 | /* If the destination of the branch is a defined symbol which does not have |
10203 | the THUMB_FUNC attribute, then we must be calling a function which has | |
10204 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
10205 | function and change the branch to refer to that function instead. */ | |
10206 | if ( inst.reloc.exp.X_op == O_symbol | |
10207 | && inst.reloc.exp.X_add_symbol != NULL | |
10208 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10209 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10210 | inst.reloc.exp.X_add_symbol = | |
10211 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 10212 | #endif |
90e4755a RE |
10213 | } |
10214 | ||
10215 | static void | |
c19d1205 | 10216 | do_t_bx (void) |
90e4755a | 10217 | { |
e07e6e58 | 10218 | set_it_insn_type_last (); |
c19d1205 ZW |
10219 | inst.instruction |= inst.operands[0].reg << 3; |
10220 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
10221 | should cause the alignment to be checked once it is known. This is | |
10222 | because BX PC only works if the instruction is word aligned. */ | |
10223 | } | |
90e4755a | 10224 | |
c19d1205 ZW |
10225 | static void |
10226 | do_t_bxj (void) | |
10227 | { | |
fdfde340 | 10228 | int Rm; |
90e4755a | 10229 | |
e07e6e58 | 10230 | set_it_insn_type_last (); |
fdfde340 JM |
10231 | Rm = inst.operands[0].reg; |
10232 | reject_bad_reg (Rm); | |
10233 | inst.instruction |= Rm << 16; | |
90e4755a RE |
10234 | } |
10235 | ||
10236 | static void | |
c19d1205 | 10237 | do_t_clz (void) |
90e4755a | 10238 | { |
fdfde340 JM |
10239 | unsigned Rd; |
10240 | unsigned Rm; | |
10241 | ||
10242 | Rd = inst.operands[0].reg; | |
10243 | Rm = inst.operands[1].reg; | |
10244 | ||
10245 | reject_bad_reg (Rd); | |
10246 | reject_bad_reg (Rm); | |
10247 | ||
10248 | inst.instruction |= Rd << 8; | |
10249 | inst.instruction |= Rm << 16; | |
10250 | inst.instruction |= Rm; | |
c19d1205 | 10251 | } |
90e4755a | 10252 | |
dfa9f0d5 PB |
10253 | static void |
10254 | do_t_cps (void) | |
10255 | { | |
e07e6e58 | 10256 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
10257 | inst.instruction |= inst.operands[0].imm; |
10258 | } | |
10259 | ||
c19d1205 ZW |
10260 | static void |
10261 | do_t_cpsi (void) | |
10262 | { | |
e07e6e58 | 10263 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 10264 | if (unified_syntax |
62b3e311 PB |
10265 | && (inst.operands[1].present || inst.size_req == 4) |
10266 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 10267 | { |
c19d1205 ZW |
10268 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
10269 | inst.instruction = 0xf3af8000; | |
10270 | inst.instruction |= imod << 9; | |
10271 | inst.instruction |= inst.operands[0].imm << 5; | |
10272 | if (inst.operands[1].present) | |
10273 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 10274 | } |
c19d1205 | 10275 | else |
90e4755a | 10276 | { |
62b3e311 PB |
10277 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
10278 | && (inst.operands[0].imm & 4), | |
10279 | _("selected processor does not support 'A' form " | |
10280 | "of this instruction")); | |
10281 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
10282 | _("Thumb does not support the 2-argument " |
10283 | "form of this instruction")); | |
10284 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 10285 | } |
90e4755a RE |
10286 | } |
10287 | ||
c19d1205 ZW |
10288 | /* THUMB CPY instruction (argument parse). */ |
10289 | ||
90e4755a | 10290 | static void |
c19d1205 | 10291 | do_t_cpy (void) |
90e4755a | 10292 | { |
c19d1205 | 10293 | if (inst.size_req == 4) |
90e4755a | 10294 | { |
c19d1205 ZW |
10295 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
10296 | inst.instruction |= inst.operands[0].reg << 8; | |
10297 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 10298 | } |
c19d1205 | 10299 | else |
90e4755a | 10300 | { |
c19d1205 ZW |
10301 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
10302 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
10303 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10304 | } |
90e4755a RE |
10305 | } |
10306 | ||
90e4755a | 10307 | static void |
25fe350b | 10308 | do_t_cbz (void) |
90e4755a | 10309 | { |
e07e6e58 | 10310 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10311 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10312 | inst.instruction |= inst.operands[0].reg; | |
10313 | inst.reloc.pc_rel = 1; | |
10314 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10315 | } | |
90e4755a | 10316 | |
62b3e311 PB |
10317 | static void |
10318 | do_t_dbg (void) | |
10319 | { | |
10320 | inst.instruction |= inst.operands[0].imm; | |
10321 | } | |
10322 | ||
10323 | static void | |
10324 | do_t_div (void) | |
10325 | { | |
fdfde340 JM |
10326 | unsigned Rd, Rn, Rm; |
10327 | ||
10328 | Rd = inst.operands[0].reg; | |
10329 | Rn = (inst.operands[1].present | |
10330 | ? inst.operands[1].reg : Rd); | |
10331 | Rm = inst.operands[2].reg; | |
10332 | ||
10333 | reject_bad_reg (Rd); | |
10334 | reject_bad_reg (Rn); | |
10335 | reject_bad_reg (Rm); | |
10336 | ||
10337 | inst.instruction |= Rd << 8; | |
10338 | inst.instruction |= Rn << 16; | |
10339 | inst.instruction |= Rm; | |
62b3e311 PB |
10340 | } |
10341 | ||
c19d1205 ZW |
10342 | static void |
10343 | do_t_hint (void) | |
10344 | { | |
10345 | if (unified_syntax && inst.size_req == 4) | |
10346 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10347 | else | |
10348 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10349 | } | |
90e4755a | 10350 | |
c19d1205 ZW |
10351 | static void |
10352 | do_t_it (void) | |
10353 | { | |
10354 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10355 | |
e07e6e58 NC |
10356 | set_it_insn_type (IT_INSN); |
10357 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10358 | now_it.cc = cond; | |
5a01bb1d | 10359 | now_it.warn_deprecated = FALSE; |
e27ec89e PB |
10360 | |
10361 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10362 | if ((cond & 0x1) == 0x0) |
90e4755a | 10363 | { |
c19d1205 | 10364 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10365 | |
c19d1205 | 10366 | if ((mask & 0x7) == 0) |
5a01bb1d MGD |
10367 | { |
10368 | /* No conversion needed. */ | |
10369 | now_it.block_length = 1; | |
10370 | } | |
c19d1205 | 10371 | else if ((mask & 0x3) == 0) |
5a01bb1d MGD |
10372 | { |
10373 | mask ^= 0x8; | |
10374 | now_it.block_length = 2; | |
10375 | } | |
e27ec89e | 10376 | else if ((mask & 0x1) == 0) |
5a01bb1d MGD |
10377 | { |
10378 | mask ^= 0xC; | |
10379 | now_it.block_length = 3; | |
10380 | } | |
c19d1205 | 10381 | else |
5a01bb1d MGD |
10382 | { |
10383 | mask ^= 0xE; | |
10384 | now_it.block_length = 4; | |
10385 | } | |
90e4755a | 10386 | |
e27ec89e PB |
10387 | inst.instruction &= 0xfff0; |
10388 | inst.instruction |= mask; | |
c19d1205 | 10389 | } |
90e4755a | 10390 | |
c19d1205 ZW |
10391 | inst.instruction |= cond << 4; |
10392 | } | |
90e4755a | 10393 | |
3c707909 PB |
10394 | /* Helper function used for both push/pop and ldm/stm. */ |
10395 | static void | |
10396 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
10397 | { | |
10398 | bfd_boolean load; | |
10399 | ||
10400 | load = (inst.instruction & (1 << 20)) != 0; | |
10401 | ||
10402 | if (mask & (1 << 13)) | |
10403 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
10404 | |
10405 | if ((mask & (1 << base)) != 0 | |
10406 | && writeback) | |
10407 | inst.error = _("having the base register in the register list when " | |
10408 | "using write back is UNPREDICTABLE"); | |
10409 | ||
3c707909 PB |
10410 | if (load) |
10411 | { | |
e07e6e58 NC |
10412 | if (mask & (1 << 15)) |
10413 | { | |
10414 | if (mask & (1 << 14)) | |
10415 | inst.error = _("LR and PC should not both be in register list"); | |
10416 | else | |
10417 | set_it_insn_type_last (); | |
10418 | } | |
3c707909 PB |
10419 | } |
10420 | else | |
10421 | { | |
10422 | if (mask & (1 << 15)) | |
10423 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
10424 | } |
10425 | ||
10426 | if ((mask & (mask - 1)) == 0) | |
10427 | { | |
10428 | /* Single register transfers implemented as str/ldr. */ | |
10429 | if (writeback) | |
10430 | { | |
10431 | if (inst.instruction & (1 << 23)) | |
10432 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
10433 | else | |
10434 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
10435 | } | |
10436 | else | |
10437 | { | |
10438 | if (inst.instruction & (1 << 23)) | |
10439 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
10440 | else | |
10441 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
10442 | } | |
10443 | ||
10444 | inst.instruction |= 0xf8400000; | |
10445 | if (load) | |
10446 | inst.instruction |= 0x00100000; | |
10447 | ||
5f4273c7 | 10448 | mask = ffs (mask) - 1; |
3c707909 PB |
10449 | mask <<= 12; |
10450 | } | |
10451 | else if (writeback) | |
10452 | inst.instruction |= WRITE_BACK; | |
10453 | ||
10454 | inst.instruction |= mask; | |
10455 | inst.instruction |= base << 16; | |
10456 | } | |
10457 | ||
c19d1205 ZW |
10458 | static void |
10459 | do_t_ldmstm (void) | |
10460 | { | |
10461 | /* This really doesn't seem worth it. */ | |
10462 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10463 | _("expression too complex")); | |
10464 | constraint (inst.operands[1].writeback, | |
10465 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 10466 | |
c19d1205 ZW |
10467 | if (unified_syntax) |
10468 | { | |
3c707909 PB |
10469 | bfd_boolean narrow; |
10470 | unsigned mask; | |
10471 | ||
10472 | narrow = FALSE; | |
c19d1205 ZW |
10473 | /* See if we can use a 16-bit instruction. */ |
10474 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
10475 | && inst.size_req != 4 | |
3c707909 | 10476 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 10477 | { |
3c707909 | 10478 | mask = 1 << inst.operands[0].reg; |
90e4755a | 10479 | |
eab4f823 | 10480 | if (inst.operands[0].reg <= 7) |
90e4755a | 10481 | { |
3c707909 | 10482 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
10483 | ? inst.operands[0].writeback |
10484 | : (inst.operands[0].writeback | |
10485 | == !(inst.operands[1].imm & mask))) | |
10486 | { | |
10487 | if (inst.instruction == T_MNEM_stmia | |
10488 | && (inst.operands[1].imm & mask) | |
10489 | && (inst.operands[1].imm & (mask - 1))) | |
10490 | as_warn (_("value stored for r%d is UNKNOWN"), | |
10491 | inst.operands[0].reg); | |
3c707909 | 10492 | |
eab4f823 MGD |
10493 | inst.instruction = THUMB_OP16 (inst.instruction); |
10494 | inst.instruction |= inst.operands[0].reg << 8; | |
10495 | inst.instruction |= inst.operands[1].imm; | |
10496 | narrow = TRUE; | |
10497 | } | |
10498 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10499 | { | |
10500 | /* This means 1 register in reg list one of 3 situations: | |
10501 | 1. Instruction is stmia, but without writeback. | |
10502 | 2. lmdia without writeback, but with Rn not in | |
10503 | reglist. | |
10504 | 3. ldmia with writeback, but with Rn in reglist. | |
10505 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
10506 | case 1 and 2 which can be converted into a 16-bit | |
10507 | str or ldr. The SP cases are handled below. */ | |
10508 | unsigned long opcode; | |
10509 | /* First, record an error for Case 3. */ | |
10510 | if (inst.operands[1].imm & mask | |
10511 | && inst.operands[0].writeback) | |
fa94de6b | 10512 | inst.error = |
eab4f823 MGD |
10513 | _("having the base register in the register list when " |
10514 | "using write back is UNPREDICTABLE"); | |
fa94de6b RM |
10515 | |
10516 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
eab4f823 MGD |
10517 | : T_MNEM_ldr); |
10518 | inst.instruction = THUMB_OP16 (opcode); | |
10519 | inst.instruction |= inst.operands[0].reg << 3; | |
10520 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
10521 | narrow = TRUE; | |
10522 | } | |
90e4755a | 10523 | } |
eab4f823 | 10524 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 10525 | { |
eab4f823 MGD |
10526 | if (inst.operands[0].writeback) |
10527 | { | |
fa94de6b | 10528 | inst.instruction = |
eab4f823 MGD |
10529 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
10530 | ? T_MNEM_push : T_MNEM_pop); | |
10531 | inst.instruction |= inst.operands[1].imm; | |
10532 | narrow = TRUE; | |
10533 | } | |
10534 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10535 | { | |
fa94de6b | 10536 | inst.instruction = |
eab4f823 MGD |
10537 | THUMB_OP16 (inst.instruction == T_MNEM_stmia |
10538 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); | |
10539 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); | |
10540 | narrow = TRUE; | |
10541 | } | |
90e4755a | 10542 | } |
3c707909 PB |
10543 | } |
10544 | ||
10545 | if (!narrow) | |
10546 | { | |
c19d1205 ZW |
10547 | if (inst.instruction < 0xffff) |
10548 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 10549 | |
5f4273c7 NC |
10550 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
10551 | inst.operands[0].writeback); | |
90e4755a RE |
10552 | } |
10553 | } | |
c19d1205 | 10554 | else |
90e4755a | 10555 | { |
c19d1205 ZW |
10556 | constraint (inst.operands[0].reg > 7 |
10557 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
10558 | constraint (inst.instruction != T_MNEM_ldmia |
10559 | && inst.instruction != T_MNEM_stmia, | |
10560 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 10561 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 10562 | { |
c19d1205 ZW |
10563 | if (!inst.operands[0].writeback) |
10564 | as_warn (_("this instruction will write back the base register")); | |
10565 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
10566 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 10567 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 10568 | inst.operands[0].reg); |
f03698e6 | 10569 | } |
c19d1205 | 10570 | else |
90e4755a | 10571 | { |
c19d1205 ZW |
10572 | if (!inst.operands[0].writeback |
10573 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10574 | as_warn (_("this instruction will write back the base register")); | |
10575 | else if (inst.operands[0].writeback | |
10576 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10577 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
10578 | } |
10579 | ||
c19d1205 ZW |
10580 | inst.instruction = THUMB_OP16 (inst.instruction); |
10581 | inst.instruction |= inst.operands[0].reg << 8; | |
10582 | inst.instruction |= inst.operands[1].imm; | |
10583 | } | |
10584 | } | |
e28cd48c | 10585 | |
c19d1205 ZW |
10586 | static void |
10587 | do_t_ldrex (void) | |
10588 | { | |
10589 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
10590 | || inst.operands[1].postind || inst.operands[1].writeback | |
10591 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
10592 | || inst.operands[1].negative, | |
01cfc07f | 10593 | BAD_ADDR_MODE); |
e28cd48c | 10594 | |
5be8be5d DG |
10595 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
10596 | ||
c19d1205 ZW |
10597 | inst.instruction |= inst.operands[0].reg << 12; |
10598 | inst.instruction |= inst.operands[1].reg << 16; | |
10599 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
10600 | } | |
e28cd48c | 10601 | |
c19d1205 ZW |
10602 | static void |
10603 | do_t_ldrexd (void) | |
10604 | { | |
10605 | if (!inst.operands[1].present) | |
1cac9012 | 10606 | { |
c19d1205 ZW |
10607 | constraint (inst.operands[0].reg == REG_LR, |
10608 | _("r14 not allowed as first register " | |
10609 | "when second register is omitted")); | |
10610 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 10611 | } |
c19d1205 ZW |
10612 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
10613 | BAD_OVERLAP); | |
b99bd4ef | 10614 | |
c19d1205 ZW |
10615 | inst.instruction |= inst.operands[0].reg << 12; |
10616 | inst.instruction |= inst.operands[1].reg << 8; | |
10617 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10618 | } |
10619 | ||
10620 | static void | |
c19d1205 | 10621 | do_t_ldst (void) |
b99bd4ef | 10622 | { |
0110f2b8 PB |
10623 | unsigned long opcode; |
10624 | int Rn; | |
10625 | ||
e07e6e58 NC |
10626 | if (inst.operands[0].isreg |
10627 | && !inst.operands[0].preind | |
10628 | && inst.operands[0].reg == REG_PC) | |
10629 | set_it_insn_type_last (); | |
10630 | ||
0110f2b8 | 10631 | opcode = inst.instruction; |
c19d1205 | 10632 | if (unified_syntax) |
b99bd4ef | 10633 | { |
53365c0d PB |
10634 | if (!inst.operands[1].isreg) |
10635 | { | |
10636 | if (opcode <= 0xffff) | |
10637 | inst.instruction = THUMB_OP32 (opcode); | |
10638 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10639 | return; | |
10640 | } | |
0110f2b8 PB |
10641 | if (inst.operands[1].isreg |
10642 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10643 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10644 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10645 | && opcode <= 0xffff |
10646 | && inst.size_req != 4) | |
c19d1205 | 10647 | { |
0110f2b8 PB |
10648 | /* Insn may have a 16-bit form. */ |
10649 | Rn = inst.operands[1].reg; | |
10650 | if (inst.operands[1].immisreg) | |
10651 | { | |
10652 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10653 | /* [Rn, Rik] */ |
0110f2b8 PB |
10654 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10655 | goto op16; | |
5be8be5d DG |
10656 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10657 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10658 | } |
10659 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10660 | && opcode != T_MNEM_ldrsb) | |
10661 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10662 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10663 | { | |
10664 | /* [Rn, #const] */ | |
10665 | if (Rn > 7) | |
10666 | { | |
10667 | if (Rn == REG_PC) | |
10668 | { | |
10669 | if (inst.reloc.pc_rel) | |
10670 | opcode = T_MNEM_ldr_pc2; | |
10671 | else | |
10672 | opcode = T_MNEM_ldr_pc; | |
10673 | } | |
10674 | else | |
10675 | { | |
10676 | if (opcode == T_MNEM_ldr) | |
10677 | opcode = T_MNEM_ldr_sp; | |
10678 | else | |
10679 | opcode = T_MNEM_str_sp; | |
10680 | } | |
10681 | inst.instruction = inst.operands[0].reg << 8; | |
10682 | } | |
10683 | else | |
10684 | { | |
10685 | inst.instruction = inst.operands[0].reg; | |
10686 | inst.instruction |= inst.operands[1].reg << 3; | |
10687 | } | |
10688 | inst.instruction |= THUMB_OP16 (opcode); | |
10689 | if (inst.size_req == 2) | |
10690 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10691 | else | |
10692 | inst.relax = opcode; | |
10693 | return; | |
10694 | } | |
c19d1205 | 10695 | } |
0110f2b8 | 10696 | /* Definitely a 32-bit variant. */ |
5be8be5d | 10697 | |
8d67f500 NC |
10698 | /* Warning for Erratum 752419. */ |
10699 | if (opcode == T_MNEM_ldr | |
10700 | && inst.operands[0].reg == REG_SP | |
10701 | && inst.operands[1].writeback == 1 | |
10702 | && !inst.operands[1].immisreg) | |
10703 | { | |
10704 | if (no_cpu_selected () | |
10705 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
10706 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) | |
10707 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
10708 | as_warn (_("This instruction may be unpredictable " | |
10709 | "if executed on M-profile cores " | |
10710 | "with interrupts enabled.")); | |
10711 | } | |
10712 | ||
5be8be5d | 10713 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 10714 | if (inst.operands[1].immisreg) |
5be8be5d DG |
10715 | reject_bad_reg (inst.operands[1].imm); |
10716 | ||
1be5fd2e NC |
10717 | constraint (inst.operands[1].writeback == 1 |
10718 | && inst.operands[0].reg == inst.operands[1].reg, | |
10719 | BAD_OVERLAP); | |
10720 | ||
0110f2b8 | 10721 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10722 | inst.instruction |= inst.operands[0].reg << 12; |
10723 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 10724 | check_ldr_r15_aligned (); |
b99bd4ef NC |
10725 | return; |
10726 | } | |
10727 | ||
c19d1205 ZW |
10728 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10729 | ||
10730 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10731 | { |
c19d1205 ZW |
10732 | /* Only [Rn,Rm] is acceptable. */ |
10733 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10734 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10735 | || inst.operands[1].postind || inst.operands[1].shifted | |
10736 | || inst.operands[1].negative, | |
10737 | _("Thumb does not support this addressing mode")); | |
10738 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10739 | goto op16; | |
b99bd4ef | 10740 | } |
5f4273c7 | 10741 | |
c19d1205 ZW |
10742 | inst.instruction = THUMB_OP16 (inst.instruction); |
10743 | if (!inst.operands[1].isreg) | |
10744 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10745 | return; | |
b99bd4ef | 10746 | |
c19d1205 ZW |
10747 | constraint (!inst.operands[1].preind |
10748 | || inst.operands[1].shifted | |
10749 | || inst.operands[1].writeback, | |
10750 | _("Thumb does not support this addressing mode")); | |
10751 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10752 | { |
c19d1205 ZW |
10753 | constraint (inst.instruction & 0x0600, |
10754 | _("byte or halfword not valid for base register")); | |
10755 | constraint (inst.operands[1].reg == REG_PC | |
10756 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10757 | _("r15 based store not allowed")); | |
10758 | constraint (inst.operands[1].immisreg, | |
10759 | _("invalid base register for register offset")); | |
b99bd4ef | 10760 | |
c19d1205 ZW |
10761 | if (inst.operands[1].reg == REG_PC) |
10762 | inst.instruction = T_OPCODE_LDR_PC; | |
10763 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10764 | inst.instruction = T_OPCODE_LDR_SP; | |
10765 | else | |
10766 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10767 | |
c19d1205 ZW |
10768 | inst.instruction |= inst.operands[0].reg << 8; |
10769 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10770 | return; | |
10771 | } | |
90e4755a | 10772 | |
c19d1205 ZW |
10773 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10774 | if (!inst.operands[1].immisreg) | |
10775 | { | |
10776 | /* Immediate offset. */ | |
10777 | inst.instruction |= inst.operands[0].reg; | |
10778 | inst.instruction |= inst.operands[1].reg << 3; | |
10779 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10780 | return; | |
10781 | } | |
90e4755a | 10782 | |
c19d1205 ZW |
10783 | /* Register offset. */ |
10784 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10785 | constraint (inst.operands[1].negative, | |
10786 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10787 | |
c19d1205 ZW |
10788 | op16: |
10789 | switch (inst.instruction) | |
10790 | { | |
10791 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10792 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10793 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10794 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10795 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10796 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10797 | case 0x5600 /* ldrsb */: | |
10798 | case 0x5e00 /* ldrsh */: break; | |
10799 | default: abort (); | |
10800 | } | |
90e4755a | 10801 | |
c19d1205 ZW |
10802 | inst.instruction |= inst.operands[0].reg; |
10803 | inst.instruction |= inst.operands[1].reg << 3; | |
10804 | inst.instruction |= inst.operands[1].imm << 6; | |
10805 | } | |
90e4755a | 10806 | |
c19d1205 ZW |
10807 | static void |
10808 | do_t_ldstd (void) | |
10809 | { | |
10810 | if (!inst.operands[1].present) | |
b99bd4ef | 10811 | { |
c19d1205 ZW |
10812 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10813 | constraint (inst.operands[0].reg == REG_LR, | |
10814 | _("r14 not allowed here")); | |
bd340a04 MGD |
10815 | constraint (inst.operands[0].reg == REG_R12, |
10816 | _("r12 not allowed here")); | |
b99bd4ef | 10817 | } |
bd340a04 MGD |
10818 | |
10819 | if (inst.operands[2].writeback | |
10820 | && (inst.operands[0].reg == inst.operands[2].reg | |
10821 | || inst.operands[1].reg == inst.operands[2].reg)) | |
10822 | as_warn (_("base register written back, and overlaps " | |
10823 | "one of transfer registers")); | |
10824 | ||
c19d1205 ZW |
10825 | inst.instruction |= inst.operands[0].reg << 12; |
10826 | inst.instruction |= inst.operands[1].reg << 8; | |
10827 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10828 | } |
10829 | ||
c19d1205 ZW |
10830 | static void |
10831 | do_t_ldstt (void) | |
10832 | { | |
10833 | inst.instruction |= inst.operands[0].reg << 12; | |
10834 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10835 | } | |
a737bd4d | 10836 | |
b99bd4ef | 10837 | static void |
c19d1205 | 10838 | do_t_mla (void) |
b99bd4ef | 10839 | { |
fdfde340 | 10840 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10841 | |
fdfde340 JM |
10842 | Rd = inst.operands[0].reg; |
10843 | Rn = inst.operands[1].reg; | |
10844 | Rm = inst.operands[2].reg; | |
10845 | Ra = inst.operands[3].reg; | |
10846 | ||
10847 | reject_bad_reg (Rd); | |
10848 | reject_bad_reg (Rn); | |
10849 | reject_bad_reg (Rm); | |
10850 | reject_bad_reg (Ra); | |
10851 | ||
10852 | inst.instruction |= Rd << 8; | |
10853 | inst.instruction |= Rn << 16; | |
10854 | inst.instruction |= Rm; | |
10855 | inst.instruction |= Ra << 12; | |
c19d1205 | 10856 | } |
b99bd4ef | 10857 | |
c19d1205 ZW |
10858 | static void |
10859 | do_t_mlal (void) | |
10860 | { | |
fdfde340 JM |
10861 | unsigned RdLo, RdHi, Rn, Rm; |
10862 | ||
10863 | RdLo = inst.operands[0].reg; | |
10864 | RdHi = inst.operands[1].reg; | |
10865 | Rn = inst.operands[2].reg; | |
10866 | Rm = inst.operands[3].reg; | |
10867 | ||
10868 | reject_bad_reg (RdLo); | |
10869 | reject_bad_reg (RdHi); | |
10870 | reject_bad_reg (Rn); | |
10871 | reject_bad_reg (Rm); | |
10872 | ||
10873 | inst.instruction |= RdLo << 12; | |
10874 | inst.instruction |= RdHi << 8; | |
10875 | inst.instruction |= Rn << 16; | |
10876 | inst.instruction |= Rm; | |
c19d1205 | 10877 | } |
b99bd4ef | 10878 | |
c19d1205 ZW |
10879 | static void |
10880 | do_t_mov_cmp (void) | |
10881 | { | |
fdfde340 JM |
10882 | unsigned Rn, Rm; |
10883 | ||
10884 | Rn = inst.operands[0].reg; | |
10885 | Rm = inst.operands[1].reg; | |
10886 | ||
e07e6e58 NC |
10887 | if (Rn == REG_PC) |
10888 | set_it_insn_type_last (); | |
10889 | ||
c19d1205 | 10890 | if (unified_syntax) |
b99bd4ef | 10891 | { |
c19d1205 ZW |
10892 | int r0off = (inst.instruction == T_MNEM_mov |
10893 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10894 | unsigned long opcode; |
3d388997 PB |
10895 | bfd_boolean narrow; |
10896 | bfd_boolean low_regs; | |
10897 | ||
fdfde340 | 10898 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10899 | opcode = inst.instruction; |
e07e6e58 | 10900 | if (in_it_block ()) |
0110f2b8 | 10901 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10902 | else |
0110f2b8 | 10903 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10904 | if (inst.size_req == 4 |
10905 | || inst.operands[1].shifted) | |
10906 | narrow = FALSE; | |
10907 | ||
efd81785 PB |
10908 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10909 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10910 | && !inst.operands[1].shifted | |
fdfde340 JM |
10911 | && Rn == REG_PC |
10912 | && Rm == REG_LR) | |
efd81785 PB |
10913 | { |
10914 | inst.instruction = T2_SUBS_PC_LR; | |
10915 | return; | |
10916 | } | |
10917 | ||
fdfde340 JM |
10918 | if (opcode == T_MNEM_cmp) |
10919 | { | |
10920 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10921 | if (narrow) |
10922 | { | |
10923 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10924 | but valid. */ | |
10925 | warn_deprecated_sp (Rm); | |
10926 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10927 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10928 | tools reject R15, so we do too. */ | |
10929 | constraint (Rm == REG_PC, BAD_PC); | |
10930 | } | |
10931 | else | |
10932 | reject_bad_reg (Rm); | |
fdfde340 JM |
10933 | } |
10934 | else if (opcode == T_MNEM_mov | |
10935 | || opcode == T_MNEM_movs) | |
10936 | { | |
10937 | if (inst.operands[1].isreg) | |
10938 | { | |
10939 | if (opcode == T_MNEM_movs) | |
10940 | { | |
10941 | reject_bad_reg (Rn); | |
10942 | reject_bad_reg (Rm); | |
10943 | } | |
76fa04a4 MGD |
10944 | else if (narrow) |
10945 | { | |
10946 | /* This is mov.n. */ | |
10947 | if ((Rn == REG_SP || Rn == REG_PC) | |
10948 | && (Rm == REG_SP || Rm == REG_PC)) | |
10949 | { | |
10950 | as_warn (_("Use of r%u as a source register is " | |
10951 | "deprecated when r%u is the destination " | |
10952 | "register."), Rm, Rn); | |
10953 | } | |
10954 | } | |
10955 | else | |
10956 | { | |
10957 | /* This is mov.w. */ | |
10958 | constraint (Rn == REG_PC, BAD_PC); | |
10959 | constraint (Rm == REG_PC, BAD_PC); | |
10960 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
10961 | } | |
fdfde340 JM |
10962 | } |
10963 | else | |
10964 | reject_bad_reg (Rn); | |
10965 | } | |
10966 | ||
c19d1205 ZW |
10967 | if (!inst.operands[1].isreg) |
10968 | { | |
0110f2b8 | 10969 | /* Immediate operand. */ |
e07e6e58 | 10970 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10971 | narrow = 0; |
10972 | if (low_regs && narrow) | |
10973 | { | |
10974 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10975 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10976 | if (inst.size_req == 2) |
10977 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10978 | else | |
10979 | inst.relax = opcode; | |
10980 | } | |
10981 | else | |
10982 | { | |
10983 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10984 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10985 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10986 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10987 | } | |
c19d1205 | 10988 | } |
728ca7c9 PB |
10989 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10990 | && (inst.instruction == T_MNEM_mov | |
10991 | || inst.instruction == T_MNEM_movs)) | |
10992 | { | |
10993 | /* Register shifts are encoded as separate shift instructions. */ | |
10994 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10995 | ||
e07e6e58 | 10996 | if (in_it_block ()) |
728ca7c9 PB |
10997 | narrow = !flags; |
10998 | else | |
10999 | narrow = flags; | |
11000 | ||
11001 | if (inst.size_req == 4) | |
11002 | narrow = FALSE; | |
11003 | ||
11004 | if (!low_regs || inst.operands[1].imm > 7) | |
11005 | narrow = FALSE; | |
11006 | ||
fdfde340 | 11007 | if (Rn != Rm) |
728ca7c9 PB |
11008 | narrow = FALSE; |
11009 | ||
11010 | switch (inst.operands[1].shift_kind) | |
11011 | { | |
11012 | case SHIFT_LSL: | |
11013 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
11014 | break; | |
11015 | case SHIFT_ASR: | |
11016 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
11017 | break; | |
11018 | case SHIFT_LSR: | |
11019 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
11020 | break; | |
11021 | case SHIFT_ROR: | |
11022 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
11023 | break; | |
11024 | default: | |
5f4273c7 | 11025 | abort (); |
728ca7c9 PB |
11026 | } |
11027 | ||
11028 | inst.instruction = opcode; | |
11029 | if (narrow) | |
11030 | { | |
fdfde340 | 11031 | inst.instruction |= Rn; |
728ca7c9 PB |
11032 | inst.instruction |= inst.operands[1].imm << 3; |
11033 | } | |
11034 | else | |
11035 | { | |
11036 | if (flags) | |
11037 | inst.instruction |= CONDS_BIT; | |
11038 | ||
fdfde340 JM |
11039 | inst.instruction |= Rn << 8; |
11040 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
11041 | inst.instruction |= inst.operands[1].imm; |
11042 | } | |
11043 | } | |
3d388997 | 11044 | else if (!narrow) |
c19d1205 | 11045 | { |
728ca7c9 PB |
11046 | /* Some mov with immediate shift have narrow variants. |
11047 | Register shifts are handled above. */ | |
11048 | if (low_regs && inst.operands[1].shifted | |
11049 | && (inst.instruction == T_MNEM_mov | |
11050 | || inst.instruction == T_MNEM_movs)) | |
11051 | { | |
e07e6e58 | 11052 | if (in_it_block ()) |
728ca7c9 PB |
11053 | narrow = (inst.instruction == T_MNEM_mov); |
11054 | else | |
11055 | narrow = (inst.instruction == T_MNEM_movs); | |
11056 | } | |
11057 | ||
11058 | if (narrow) | |
11059 | { | |
11060 | switch (inst.operands[1].shift_kind) | |
11061 | { | |
11062 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11063 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
11064 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
11065 | default: narrow = FALSE; break; | |
11066 | } | |
11067 | } | |
11068 | ||
11069 | if (narrow) | |
11070 | { | |
fdfde340 JM |
11071 | inst.instruction |= Rn; |
11072 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
11073 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11074 | } | |
11075 | else | |
11076 | { | |
11077 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11078 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
11079 | encode_thumb32_shifted_operand (1); |
11080 | } | |
c19d1205 ZW |
11081 | } |
11082 | else | |
11083 | switch (inst.instruction) | |
11084 | { | |
11085 | case T_MNEM_mov: | |
837b3435 | 11086 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
11087 | results. Don't allow this. */ |
11088 | if (low_regs) | |
11089 | { | |
11090 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
11091 | "MOV Rd, Rs with two low registers is not " | |
11092 | "permitted on this architecture"); | |
fa94de6b | 11093 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
c6400f8a MGD |
11094 | arm_ext_v6); |
11095 | } | |
11096 | ||
c19d1205 | 11097 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
11098 | inst.instruction |= (Rn & 0x8) << 4; |
11099 | inst.instruction |= (Rn & 0x7); | |
11100 | inst.instruction |= Rm << 3; | |
c19d1205 | 11101 | break; |
b99bd4ef | 11102 | |
c19d1205 ZW |
11103 | case T_MNEM_movs: |
11104 | /* We know we have low registers at this point. | |
941a8a52 MGD |
11105 | Generate LSLS Rd, Rs, #0. */ |
11106 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
11107 | inst.instruction |= Rn; |
11108 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11109 | break; |
11110 | ||
11111 | case T_MNEM_cmp: | |
3d388997 | 11112 | if (low_regs) |
c19d1205 ZW |
11113 | { |
11114 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
11115 | inst.instruction |= Rn; |
11116 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11117 | } |
11118 | else | |
11119 | { | |
11120 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
11121 | inst.instruction |= (Rn & 0x8) << 4; |
11122 | inst.instruction |= (Rn & 0x7); | |
11123 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11124 | } |
11125 | break; | |
11126 | } | |
b99bd4ef NC |
11127 | return; |
11128 | } | |
11129 | ||
c19d1205 | 11130 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
11131 | |
11132 | /* PR 10443: Do not silently ignore shifted operands. */ | |
11133 | constraint (inst.operands[1].shifted, | |
11134 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
11135 | ||
c19d1205 | 11136 | if (inst.operands[1].isreg) |
b99bd4ef | 11137 | { |
fdfde340 | 11138 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 11139 | { |
c19d1205 ZW |
11140 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
11141 | since a MOV instruction produces unpredictable results. */ | |
11142 | if (inst.instruction == T_OPCODE_MOV_I8) | |
11143 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 11144 | else |
c19d1205 | 11145 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 11146 | |
fdfde340 JM |
11147 | inst.instruction |= Rn; |
11148 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
11149 | } |
11150 | else | |
11151 | { | |
c19d1205 ZW |
11152 | if (inst.instruction == T_OPCODE_MOV_I8) |
11153 | inst.instruction = T_OPCODE_MOV_HR; | |
11154 | else | |
11155 | inst.instruction = T_OPCODE_CMP_HR; | |
11156 | do_t_cpy (); | |
b99bd4ef NC |
11157 | } |
11158 | } | |
c19d1205 | 11159 | else |
b99bd4ef | 11160 | { |
fdfde340 | 11161 | constraint (Rn > 7, |
c19d1205 | 11162 | _("only lo regs allowed with immediate")); |
fdfde340 | 11163 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11164 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11165 | } | |
11166 | } | |
b99bd4ef | 11167 | |
c19d1205 ZW |
11168 | static void |
11169 | do_t_mov16 (void) | |
11170 | { | |
fdfde340 | 11171 | unsigned Rd; |
b6895b4f PB |
11172 | bfd_vma imm; |
11173 | bfd_boolean top; | |
11174 | ||
11175 | top = (inst.instruction & 0x00800000) != 0; | |
11176 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
11177 | { | |
11178 | constraint (top, _(":lower16: not allowed this instruction")); | |
11179 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
11180 | } | |
11181 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
11182 | { | |
11183 | constraint (!top, _(":upper16: not allowed this instruction")); | |
11184 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
11185 | } | |
11186 | ||
fdfde340 JM |
11187 | Rd = inst.operands[0].reg; |
11188 | reject_bad_reg (Rd); | |
11189 | ||
11190 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
11191 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
11192 | { | |
11193 | imm = inst.reloc.exp.X_add_number; | |
11194 | inst.instruction |= (imm & 0xf000) << 4; | |
11195 | inst.instruction |= (imm & 0x0800) << 15; | |
11196 | inst.instruction |= (imm & 0x0700) << 4; | |
11197 | inst.instruction |= (imm & 0x00ff); | |
11198 | } | |
c19d1205 | 11199 | } |
b99bd4ef | 11200 | |
c19d1205 ZW |
11201 | static void |
11202 | do_t_mvn_tst (void) | |
11203 | { | |
fdfde340 | 11204 | unsigned Rn, Rm; |
c921be7d | 11205 | |
fdfde340 JM |
11206 | Rn = inst.operands[0].reg; |
11207 | Rm = inst.operands[1].reg; | |
11208 | ||
11209 | if (inst.instruction == T_MNEM_cmp | |
11210 | || inst.instruction == T_MNEM_cmn) | |
11211 | constraint (Rn == REG_PC, BAD_PC); | |
11212 | else | |
11213 | reject_bad_reg (Rn); | |
11214 | reject_bad_reg (Rm); | |
11215 | ||
c19d1205 ZW |
11216 | if (unified_syntax) |
11217 | { | |
11218 | int r0off = (inst.instruction == T_MNEM_mvn | |
11219 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
11220 | bfd_boolean narrow; |
11221 | ||
11222 | if (inst.size_req == 4 | |
11223 | || inst.instruction > 0xffff | |
11224 | || inst.operands[1].shifted | |
fdfde340 | 11225 | || Rn > 7 || Rm > 7) |
3d388997 PB |
11226 | narrow = FALSE; |
11227 | else if (inst.instruction == T_MNEM_cmn) | |
11228 | narrow = TRUE; | |
11229 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11230 | narrow = !in_it_block (); |
3d388997 | 11231 | else |
e07e6e58 | 11232 | narrow = in_it_block (); |
3d388997 | 11233 | |
c19d1205 | 11234 | if (!inst.operands[1].isreg) |
b99bd4ef | 11235 | { |
c19d1205 ZW |
11236 | /* For an immediate, we always generate a 32-bit opcode; |
11237 | section relaxation will shrink it later if possible. */ | |
11238 | if (inst.instruction < 0xffff) | |
11239 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11240 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11241 | inst.instruction |= Rn << r0off; |
c19d1205 | 11242 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11243 | } |
c19d1205 | 11244 | else |
b99bd4ef | 11245 | { |
c19d1205 | 11246 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 11247 | if (narrow) |
b99bd4ef | 11248 | { |
c19d1205 | 11249 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11250 | inst.instruction |= Rn; |
11251 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11252 | } |
c19d1205 | 11253 | else |
b99bd4ef | 11254 | { |
c19d1205 ZW |
11255 | constraint (inst.operands[1].shifted |
11256 | && inst.operands[1].immisreg, | |
11257 | _("shift must be constant")); | |
11258 | if (inst.instruction < 0xffff) | |
11259 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11260 | inst.instruction |= Rn << r0off; |
c19d1205 | 11261 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 11262 | } |
b99bd4ef NC |
11263 | } |
11264 | } | |
11265 | else | |
11266 | { | |
c19d1205 ZW |
11267 | constraint (inst.instruction > 0xffff |
11268 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
11269 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
11270 | _("unshifted register required")); | |
fdfde340 | 11271 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11272 | BAD_HIREG); |
b99bd4ef | 11273 | |
c19d1205 | 11274 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11275 | inst.instruction |= Rn; |
11276 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11277 | } |
b99bd4ef NC |
11278 | } |
11279 | ||
b05fe5cf | 11280 | static void |
c19d1205 | 11281 | do_t_mrs (void) |
b05fe5cf | 11282 | { |
fdfde340 | 11283 | unsigned Rd; |
037e8744 JB |
11284 | |
11285 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
11286 | return; | |
11287 | ||
90ec0d68 MGD |
11288 | Rd = inst.operands[0].reg; |
11289 | reject_bad_reg (Rd); | |
11290 | inst.instruction |= Rd << 8; | |
11291 | ||
11292 | if (inst.operands[1].isreg) | |
62b3e311 | 11293 | { |
90ec0d68 MGD |
11294 | unsigned br = inst.operands[1].reg; |
11295 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
11296 | as_bad (_("bad register for mrs")); | |
11297 | ||
11298 | inst.instruction |= br & (0xf << 16); | |
11299 | inst.instruction |= (br & 0x300) >> 4; | |
11300 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
11301 | } |
11302 | else | |
11303 | { | |
90ec0d68 | 11304 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 11305 | |
d2cd1205 | 11306 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
1a43faaf NC |
11307 | { |
11308 | /* PR gas/12698: The constraint is only applied for m_profile. | |
11309 | If the user has specified -march=all, we want to ignore it as | |
11310 | we are building for any CPU type, including non-m variants. */ | |
11311 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; | |
11312 | constraint ((flags != 0) && m_profile, _("selected processor does " | |
11313 | "not support requested special purpose register")); | |
11314 | } | |
90ec0d68 | 11315 | else |
d2cd1205 JB |
11316 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
11317 | devices). */ | |
11318 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
11319 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 11320 | |
90ec0d68 MGD |
11321 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
11322 | inst.instruction |= inst.operands[1].imm & 0xff; | |
11323 | inst.instruction |= 0xf0000; | |
11324 | } | |
c19d1205 | 11325 | } |
b05fe5cf | 11326 | |
c19d1205 ZW |
11327 | static void |
11328 | do_t_msr (void) | |
11329 | { | |
62b3e311 | 11330 | int flags; |
fdfde340 | 11331 | unsigned Rn; |
62b3e311 | 11332 | |
037e8744 JB |
11333 | if (do_vfp_nsyn_msr () == SUCCESS) |
11334 | return; | |
11335 | ||
c19d1205 ZW |
11336 | constraint (!inst.operands[1].isreg, |
11337 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
11338 | |
11339 | if (inst.operands[0].isreg) | |
11340 | flags = (int)(inst.operands[0].reg); | |
11341 | else | |
11342 | flags = inst.operands[0].imm; | |
11343 | ||
d2cd1205 | 11344 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 11345 | { |
d2cd1205 JB |
11346 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
11347 | ||
1a43faaf NC |
11348 | /* PR gas/12698: The constraint is only applied for m_profile. |
11349 | If the user has specified -march=all, we want to ignore it as | |
11350 | we are building for any CPU type, including non-m variants. */ | |
11351 | bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core; | |
11352 | constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11353 | && (bits & ~(PSR_s | PSR_f)) != 0) | |
11354 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11355 | && bits != PSR_f)) && m_profile, | |
11356 | _("selected processor does not support requested special " | |
11357 | "purpose register")); | |
62b3e311 PB |
11358 | } |
11359 | else | |
d2cd1205 JB |
11360 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
11361 | "requested special purpose register")); | |
c921be7d | 11362 | |
fdfde340 JM |
11363 | Rn = inst.operands[1].reg; |
11364 | reject_bad_reg (Rn); | |
11365 | ||
62b3e311 | 11366 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11367 | inst.instruction |= (flags & 0xf0000) >> 8; |
11368 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11369 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11370 | inst.instruction |= Rn << 16; |
c19d1205 | 11371 | } |
b05fe5cf | 11372 | |
c19d1205 ZW |
11373 | static void |
11374 | do_t_mul (void) | |
11375 | { | |
17828f45 | 11376 | bfd_boolean narrow; |
fdfde340 | 11377 | unsigned Rd, Rn, Rm; |
17828f45 | 11378 | |
c19d1205 ZW |
11379 | if (!inst.operands[2].present) |
11380 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11381 | |
fdfde340 JM |
11382 | Rd = inst.operands[0].reg; |
11383 | Rn = inst.operands[1].reg; | |
11384 | Rm = inst.operands[2].reg; | |
11385 | ||
17828f45 | 11386 | if (unified_syntax) |
b05fe5cf | 11387 | { |
17828f45 | 11388 | if (inst.size_req == 4 |
fdfde340 JM |
11389 | || (Rd != Rn |
11390 | && Rd != Rm) | |
11391 | || Rn > 7 | |
11392 | || Rm > 7) | |
17828f45 JM |
11393 | narrow = FALSE; |
11394 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 11395 | narrow = !in_it_block (); |
17828f45 | 11396 | else |
e07e6e58 | 11397 | narrow = in_it_block (); |
b05fe5cf | 11398 | } |
c19d1205 | 11399 | else |
b05fe5cf | 11400 | { |
17828f45 | 11401 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 11402 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11403 | BAD_HIREG); |
17828f45 JM |
11404 | narrow = TRUE; |
11405 | } | |
b05fe5cf | 11406 | |
17828f45 JM |
11407 | if (narrow) |
11408 | { | |
11409 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 11410 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 11411 | inst.instruction |= Rd; |
b05fe5cf | 11412 | |
fdfde340 JM |
11413 | if (Rd == Rn) |
11414 | inst.instruction |= Rm << 3; | |
11415 | else if (Rd == Rm) | |
11416 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
11417 | else |
11418 | constraint (1, _("dest must overlap one source register")); | |
11419 | } | |
17828f45 JM |
11420 | else |
11421 | { | |
e07e6e58 NC |
11422 | constraint (inst.instruction != T_MNEM_mul, |
11423 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
11424 | /* 32-bit MUL. */ |
11425 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11426 | inst.instruction |= Rd << 8; |
11427 | inst.instruction |= Rn << 16; | |
11428 | inst.instruction |= Rm << 0; | |
11429 | ||
11430 | reject_bad_reg (Rd); | |
11431 | reject_bad_reg (Rn); | |
11432 | reject_bad_reg (Rm); | |
17828f45 | 11433 | } |
c19d1205 | 11434 | } |
b05fe5cf | 11435 | |
c19d1205 ZW |
11436 | static void |
11437 | do_t_mull (void) | |
11438 | { | |
fdfde340 | 11439 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 11440 | |
fdfde340 JM |
11441 | RdLo = inst.operands[0].reg; |
11442 | RdHi = inst.operands[1].reg; | |
11443 | Rn = inst.operands[2].reg; | |
11444 | Rm = inst.operands[3].reg; | |
11445 | ||
11446 | reject_bad_reg (RdLo); | |
11447 | reject_bad_reg (RdHi); | |
11448 | reject_bad_reg (Rn); | |
11449 | reject_bad_reg (Rm); | |
11450 | ||
11451 | inst.instruction |= RdLo << 12; | |
11452 | inst.instruction |= RdHi << 8; | |
11453 | inst.instruction |= Rn << 16; | |
11454 | inst.instruction |= Rm; | |
11455 | ||
11456 | if (RdLo == RdHi) | |
c19d1205 ZW |
11457 | as_tsktsk (_("rdhi and rdlo must be different")); |
11458 | } | |
b05fe5cf | 11459 | |
c19d1205 ZW |
11460 | static void |
11461 | do_t_nop (void) | |
11462 | { | |
e07e6e58 NC |
11463 | set_it_insn_type (NEUTRAL_IT_INSN); |
11464 | ||
c19d1205 ZW |
11465 | if (unified_syntax) |
11466 | { | |
11467 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 11468 | { |
c19d1205 ZW |
11469 | inst.instruction = THUMB_OP32 (inst.instruction); |
11470 | inst.instruction |= inst.operands[0].imm; | |
11471 | } | |
11472 | else | |
11473 | { | |
bc2d1808 NC |
11474 | /* PR9722: Check for Thumb2 availability before |
11475 | generating a thumb2 nop instruction. */ | |
afa62d5e | 11476 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
11477 | { |
11478 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11479 | inst.instruction |= inst.operands[0].imm << 4; | |
11480 | } | |
11481 | else | |
11482 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
11483 | } |
11484 | } | |
11485 | else | |
11486 | { | |
11487 | constraint (inst.operands[0].present, | |
11488 | _("Thumb does not support NOP with hints")); | |
11489 | inst.instruction = 0x46c0; | |
11490 | } | |
11491 | } | |
b05fe5cf | 11492 | |
c19d1205 ZW |
11493 | static void |
11494 | do_t_neg (void) | |
11495 | { | |
11496 | if (unified_syntax) | |
11497 | { | |
3d388997 PB |
11498 | bfd_boolean narrow; |
11499 | ||
11500 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11501 | narrow = !in_it_block (); |
3d388997 | 11502 | else |
e07e6e58 | 11503 | narrow = in_it_block (); |
3d388997 PB |
11504 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11505 | narrow = FALSE; | |
11506 | if (inst.size_req == 4) | |
11507 | narrow = FALSE; | |
11508 | ||
11509 | if (!narrow) | |
c19d1205 ZW |
11510 | { |
11511 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11512 | inst.instruction |= inst.operands[0].reg << 8; | |
11513 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
11514 | } |
11515 | else | |
11516 | { | |
c19d1205 ZW |
11517 | inst.instruction = THUMB_OP16 (inst.instruction); |
11518 | inst.instruction |= inst.operands[0].reg; | |
11519 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
11520 | } |
11521 | } | |
11522 | else | |
11523 | { | |
c19d1205 ZW |
11524 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
11525 | BAD_HIREG); | |
11526 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
11527 | ||
11528 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11529 | inst.instruction |= inst.operands[0].reg; | |
11530 | inst.instruction |= inst.operands[1].reg << 3; | |
11531 | } | |
11532 | } | |
11533 | ||
1c444d06 JM |
11534 | static void |
11535 | do_t_orn (void) | |
11536 | { | |
11537 | unsigned Rd, Rn; | |
11538 | ||
11539 | Rd = inst.operands[0].reg; | |
11540 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
11541 | ||
fdfde340 JM |
11542 | reject_bad_reg (Rd); |
11543 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
11544 | reject_bad_reg (Rn); | |
11545 | ||
1c444d06 JM |
11546 | inst.instruction |= Rd << 8; |
11547 | inst.instruction |= Rn << 16; | |
11548 | ||
11549 | if (!inst.operands[2].isreg) | |
11550 | { | |
11551 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11552 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11553 | } | |
11554 | else | |
11555 | { | |
11556 | unsigned Rm; | |
11557 | ||
11558 | Rm = inst.operands[2].reg; | |
fdfde340 | 11559 | reject_bad_reg (Rm); |
1c444d06 JM |
11560 | |
11561 | constraint (inst.operands[2].shifted | |
11562 | && inst.operands[2].immisreg, | |
11563 | _("shift must be constant")); | |
11564 | encode_thumb32_shifted_operand (2); | |
11565 | } | |
11566 | } | |
11567 | ||
c19d1205 ZW |
11568 | static void |
11569 | do_t_pkhbt (void) | |
11570 | { | |
fdfde340 JM |
11571 | unsigned Rd, Rn, Rm; |
11572 | ||
11573 | Rd = inst.operands[0].reg; | |
11574 | Rn = inst.operands[1].reg; | |
11575 | Rm = inst.operands[2].reg; | |
11576 | ||
11577 | reject_bad_reg (Rd); | |
11578 | reject_bad_reg (Rn); | |
11579 | reject_bad_reg (Rm); | |
11580 | ||
11581 | inst.instruction |= Rd << 8; | |
11582 | inst.instruction |= Rn << 16; | |
11583 | inst.instruction |= Rm; | |
c19d1205 ZW |
11584 | if (inst.operands[3].present) |
11585 | { | |
11586 | unsigned int val = inst.reloc.exp.X_add_number; | |
11587 | constraint (inst.reloc.exp.X_op != O_constant, | |
11588 | _("expression too complex")); | |
11589 | inst.instruction |= (val & 0x1c) << 10; | |
11590 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 11591 | } |
c19d1205 | 11592 | } |
b05fe5cf | 11593 | |
c19d1205 ZW |
11594 | static void |
11595 | do_t_pkhtb (void) | |
11596 | { | |
11597 | if (!inst.operands[3].present) | |
1ef52f49 NC |
11598 | { |
11599 | unsigned Rtmp; | |
11600 | ||
11601 | inst.instruction &= ~0x00000020; | |
11602 | ||
11603 | /* PR 10168. Swap the Rm and Rn registers. */ | |
11604 | Rtmp = inst.operands[1].reg; | |
11605 | inst.operands[1].reg = inst.operands[2].reg; | |
11606 | inst.operands[2].reg = Rtmp; | |
11607 | } | |
c19d1205 | 11608 | do_t_pkhbt (); |
b05fe5cf ZW |
11609 | } |
11610 | ||
c19d1205 ZW |
11611 | static void |
11612 | do_t_pld (void) | |
11613 | { | |
fdfde340 JM |
11614 | if (inst.operands[0].immisreg) |
11615 | reject_bad_reg (inst.operands[0].imm); | |
11616 | ||
c19d1205 ZW |
11617 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
11618 | } | |
b05fe5cf | 11619 | |
c19d1205 ZW |
11620 | static void |
11621 | do_t_push_pop (void) | |
b99bd4ef | 11622 | { |
e9f89963 | 11623 | unsigned mask; |
5f4273c7 | 11624 | |
c19d1205 ZW |
11625 | constraint (inst.operands[0].writeback, |
11626 | _("push/pop do not support {reglist}^")); | |
11627 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11628 | _("expression too complex")); | |
b99bd4ef | 11629 | |
e9f89963 PB |
11630 | mask = inst.operands[0].imm; |
11631 | if ((mask & ~0xff) == 0) | |
3c707909 | 11632 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 11633 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 11634 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 11635 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 11636 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 11637 | { |
c19d1205 ZW |
11638 | inst.instruction = THUMB_OP16 (inst.instruction); |
11639 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 11640 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
11641 | } |
11642 | else if (unified_syntax) | |
11643 | { | |
3c707909 | 11644 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 11645 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
11646 | } |
11647 | else | |
11648 | { | |
11649 | inst.error = _("invalid register list to push/pop instruction"); | |
11650 | return; | |
11651 | } | |
c19d1205 | 11652 | } |
b99bd4ef | 11653 | |
c19d1205 ZW |
11654 | static void |
11655 | do_t_rbit (void) | |
11656 | { | |
fdfde340 JM |
11657 | unsigned Rd, Rm; |
11658 | ||
11659 | Rd = inst.operands[0].reg; | |
11660 | Rm = inst.operands[1].reg; | |
11661 | ||
11662 | reject_bad_reg (Rd); | |
11663 | reject_bad_reg (Rm); | |
11664 | ||
11665 | inst.instruction |= Rd << 8; | |
11666 | inst.instruction |= Rm << 16; | |
11667 | inst.instruction |= Rm; | |
c19d1205 | 11668 | } |
b99bd4ef | 11669 | |
c19d1205 ZW |
11670 | static void |
11671 | do_t_rev (void) | |
11672 | { | |
fdfde340 JM |
11673 | unsigned Rd, Rm; |
11674 | ||
11675 | Rd = inst.operands[0].reg; | |
11676 | Rm = inst.operands[1].reg; | |
11677 | ||
11678 | reject_bad_reg (Rd); | |
11679 | reject_bad_reg (Rm); | |
11680 | ||
11681 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
11682 | && inst.size_req != 4) |
11683 | { | |
11684 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
11685 | inst.instruction |= Rd; |
11686 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11687 | } |
11688 | else if (unified_syntax) | |
11689 | { | |
11690 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11691 | inst.instruction |= Rd << 8; |
11692 | inst.instruction |= Rm << 16; | |
11693 | inst.instruction |= Rm; | |
c19d1205 ZW |
11694 | } |
11695 | else | |
11696 | inst.error = BAD_HIREG; | |
11697 | } | |
b99bd4ef | 11698 | |
1c444d06 JM |
11699 | static void |
11700 | do_t_rrx (void) | |
11701 | { | |
11702 | unsigned Rd, Rm; | |
11703 | ||
11704 | Rd = inst.operands[0].reg; | |
11705 | Rm = inst.operands[1].reg; | |
11706 | ||
fdfde340 JM |
11707 | reject_bad_reg (Rd); |
11708 | reject_bad_reg (Rm); | |
c921be7d | 11709 | |
1c444d06 JM |
11710 | inst.instruction |= Rd << 8; |
11711 | inst.instruction |= Rm; | |
11712 | } | |
11713 | ||
c19d1205 ZW |
11714 | static void |
11715 | do_t_rsb (void) | |
11716 | { | |
fdfde340 | 11717 | unsigned Rd, Rs; |
b99bd4ef | 11718 | |
c19d1205 ZW |
11719 | Rd = inst.operands[0].reg; |
11720 | Rs = (inst.operands[1].present | |
11721 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11722 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11723 | |
fdfde340 JM |
11724 | reject_bad_reg (Rd); |
11725 | reject_bad_reg (Rs); | |
11726 | if (inst.operands[2].isreg) | |
11727 | reject_bad_reg (inst.operands[2].reg); | |
11728 | ||
c19d1205 ZW |
11729 | inst.instruction |= Rd << 8; |
11730 | inst.instruction |= Rs << 16; | |
11731 | if (!inst.operands[2].isreg) | |
11732 | { | |
026d3abb PB |
11733 | bfd_boolean narrow; |
11734 | ||
11735 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11736 | narrow = !in_it_block (); |
026d3abb | 11737 | else |
e07e6e58 | 11738 | narrow = in_it_block (); |
026d3abb PB |
11739 | |
11740 | if (Rd > 7 || Rs > 7) | |
11741 | narrow = FALSE; | |
11742 | ||
11743 | if (inst.size_req == 4 || !unified_syntax) | |
11744 | narrow = FALSE; | |
11745 | ||
11746 | if (inst.reloc.exp.X_op != O_constant | |
11747 | || inst.reloc.exp.X_add_number != 0) | |
11748 | narrow = FALSE; | |
11749 | ||
11750 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11751 | relaxation, but it doesn't seem worth the hassle. */ | |
11752 | if (narrow) | |
11753 | { | |
11754 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11755 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11756 | inst.instruction |= Rs << 3; | |
11757 | inst.instruction |= Rd; | |
11758 | } | |
11759 | else | |
11760 | { | |
11761 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11762 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11763 | } | |
c19d1205 ZW |
11764 | } |
11765 | else | |
11766 | encode_thumb32_shifted_operand (2); | |
11767 | } | |
b99bd4ef | 11768 | |
c19d1205 ZW |
11769 | static void |
11770 | do_t_setend (void) | |
11771 | { | |
e07e6e58 | 11772 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11773 | if (inst.operands[0].imm) |
11774 | inst.instruction |= 0x8; | |
11775 | } | |
b99bd4ef | 11776 | |
c19d1205 ZW |
11777 | static void |
11778 | do_t_shift (void) | |
11779 | { | |
11780 | if (!inst.operands[1].present) | |
11781 | inst.operands[1].reg = inst.operands[0].reg; | |
11782 | ||
11783 | if (unified_syntax) | |
11784 | { | |
3d388997 PB |
11785 | bfd_boolean narrow; |
11786 | int shift_kind; | |
11787 | ||
11788 | switch (inst.instruction) | |
11789 | { | |
11790 | case T_MNEM_asr: | |
11791 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11792 | case T_MNEM_lsl: | |
11793 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11794 | case T_MNEM_lsr: | |
11795 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11796 | case T_MNEM_ror: | |
11797 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11798 | default: abort (); | |
11799 | } | |
11800 | ||
11801 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11802 | narrow = !in_it_block (); |
3d388997 | 11803 | else |
e07e6e58 | 11804 | narrow = in_it_block (); |
3d388997 PB |
11805 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11806 | narrow = FALSE; | |
11807 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11808 | narrow = FALSE; | |
11809 | if (inst.operands[2].isreg | |
11810 | && (inst.operands[1].reg != inst.operands[0].reg | |
11811 | || inst.operands[2].reg > 7)) | |
11812 | narrow = FALSE; | |
11813 | if (inst.size_req == 4) | |
11814 | narrow = FALSE; | |
11815 | ||
fdfde340 JM |
11816 | reject_bad_reg (inst.operands[0].reg); |
11817 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11818 | |
3d388997 | 11819 | if (!narrow) |
c19d1205 ZW |
11820 | { |
11821 | if (inst.operands[2].isreg) | |
b99bd4ef | 11822 | { |
fdfde340 | 11823 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11824 | inst.instruction = THUMB_OP32 (inst.instruction); |
11825 | inst.instruction |= inst.operands[0].reg << 8; | |
11826 | inst.instruction |= inst.operands[1].reg << 16; | |
11827 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
11828 | |
11829 | /* PR 12854: Error on extraneous shifts. */ | |
11830 | constraint (inst.operands[2].shifted, | |
11831 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
11832 | } |
11833 | else | |
11834 | { | |
11835 | inst.operands[1].shifted = 1; | |
3d388997 | 11836 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11837 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11838 | ? T_MNEM_movs : T_MNEM_mov); | |
11839 | inst.instruction |= inst.operands[0].reg << 8; | |
11840 | encode_thumb32_shifted_operand (1); | |
11841 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11842 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11843 | } |
11844 | } | |
11845 | else | |
11846 | { | |
c19d1205 | 11847 | if (inst.operands[2].isreg) |
b99bd4ef | 11848 | { |
3d388997 | 11849 | switch (shift_kind) |
b99bd4ef | 11850 | { |
3d388997 PB |
11851 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11852 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11853 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11854 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11855 | default: abort (); |
b99bd4ef | 11856 | } |
5f4273c7 | 11857 | |
c19d1205 ZW |
11858 | inst.instruction |= inst.operands[0].reg; |
11859 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
11860 | |
11861 | /* PR 12854: Error on extraneous shifts. */ | |
11862 | constraint (inst.operands[2].shifted, | |
11863 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
11864 | } |
11865 | else | |
11866 | { | |
3d388997 | 11867 | switch (shift_kind) |
b99bd4ef | 11868 | { |
3d388997 PB |
11869 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11870 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11871 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11872 | default: abort (); |
b99bd4ef | 11873 | } |
c19d1205 ZW |
11874 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11875 | inst.instruction |= inst.operands[0].reg; | |
11876 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11877 | } |
11878 | } | |
c19d1205 ZW |
11879 | } |
11880 | else | |
11881 | { | |
11882 | constraint (inst.operands[0].reg > 7 | |
11883 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11884 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11885 | |
c19d1205 ZW |
11886 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11887 | { | |
11888 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11889 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11890 | _("source1 and dest must be same register")); | |
b99bd4ef | 11891 | |
c19d1205 ZW |
11892 | switch (inst.instruction) |
11893 | { | |
11894 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11895 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11896 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11897 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11898 | default: abort (); | |
11899 | } | |
5f4273c7 | 11900 | |
c19d1205 ZW |
11901 | inst.instruction |= inst.operands[0].reg; |
11902 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
11903 | |
11904 | /* PR 12854: Error on extraneous shifts. */ | |
11905 | constraint (inst.operands[2].shifted, | |
11906 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
11907 | } |
11908 | else | |
b99bd4ef | 11909 | { |
c19d1205 ZW |
11910 | switch (inst.instruction) |
11911 | { | |
11912 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11913 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11914 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11915 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11916 | default: abort (); | |
11917 | } | |
11918 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11919 | inst.instruction |= inst.operands[0].reg; | |
11920 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11921 | } |
11922 | } | |
b99bd4ef NC |
11923 | } |
11924 | ||
11925 | static void | |
c19d1205 | 11926 | do_t_simd (void) |
b99bd4ef | 11927 | { |
fdfde340 JM |
11928 | unsigned Rd, Rn, Rm; |
11929 | ||
11930 | Rd = inst.operands[0].reg; | |
11931 | Rn = inst.operands[1].reg; | |
11932 | Rm = inst.operands[2].reg; | |
11933 | ||
11934 | reject_bad_reg (Rd); | |
11935 | reject_bad_reg (Rn); | |
11936 | reject_bad_reg (Rm); | |
11937 | ||
11938 | inst.instruction |= Rd << 8; | |
11939 | inst.instruction |= Rn << 16; | |
11940 | inst.instruction |= Rm; | |
c19d1205 | 11941 | } |
b99bd4ef | 11942 | |
03ee1b7f NC |
11943 | static void |
11944 | do_t_simd2 (void) | |
11945 | { | |
11946 | unsigned Rd, Rn, Rm; | |
11947 | ||
11948 | Rd = inst.operands[0].reg; | |
11949 | Rm = inst.operands[1].reg; | |
11950 | Rn = inst.operands[2].reg; | |
11951 | ||
11952 | reject_bad_reg (Rd); | |
11953 | reject_bad_reg (Rn); | |
11954 | reject_bad_reg (Rm); | |
11955 | ||
11956 | inst.instruction |= Rd << 8; | |
11957 | inst.instruction |= Rn << 16; | |
11958 | inst.instruction |= Rm; | |
11959 | } | |
11960 | ||
c19d1205 | 11961 | static void |
3eb17e6b | 11962 | do_t_smc (void) |
c19d1205 ZW |
11963 | { |
11964 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
11965 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
11966 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
11967 | constraint (inst.reloc.exp.X_op != O_constant, |
11968 | _("expression too complex")); | |
11969 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11970 | inst.instruction |= (value & 0xf000) >> 12; | |
11971 | inst.instruction |= (value & 0x0ff0); | |
11972 | inst.instruction |= (value & 0x000f) << 16; | |
11973 | } | |
b99bd4ef | 11974 | |
90ec0d68 MGD |
11975 | static void |
11976 | do_t_hvc (void) | |
11977 | { | |
11978 | unsigned int value = inst.reloc.exp.X_add_number; | |
11979 | ||
11980 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11981 | inst.instruction |= (value & 0x0fff); | |
11982 | inst.instruction |= (value & 0xf000) << 4; | |
11983 | } | |
11984 | ||
c19d1205 | 11985 | static void |
3a21c15a | 11986 | do_t_ssat_usat (int bias) |
c19d1205 | 11987 | { |
fdfde340 JM |
11988 | unsigned Rd, Rn; |
11989 | ||
11990 | Rd = inst.operands[0].reg; | |
11991 | Rn = inst.operands[2].reg; | |
11992 | ||
11993 | reject_bad_reg (Rd); | |
11994 | reject_bad_reg (Rn); | |
11995 | ||
11996 | inst.instruction |= Rd << 8; | |
3a21c15a | 11997 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11998 | inst.instruction |= Rn << 16; |
b99bd4ef | 11999 | |
c19d1205 | 12000 | if (inst.operands[3].present) |
b99bd4ef | 12001 | { |
3a21c15a NC |
12002 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
12003 | ||
12004 | inst.reloc.type = BFD_RELOC_UNUSED; | |
12005 | ||
c19d1205 ZW |
12006 | constraint (inst.reloc.exp.X_op != O_constant, |
12007 | _("expression too complex")); | |
b99bd4ef | 12008 | |
3a21c15a | 12009 | if (shift_amount != 0) |
6189168b | 12010 | { |
3a21c15a NC |
12011 | constraint (shift_amount > 31, |
12012 | _("shift expression is too large")); | |
12013 | ||
c19d1205 | 12014 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
12015 | inst.instruction |= 0x00200000; /* sh bit. */ |
12016 | ||
12017 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
12018 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
12019 | } |
12020 | } | |
b99bd4ef | 12021 | } |
c921be7d | 12022 | |
3a21c15a NC |
12023 | static void |
12024 | do_t_ssat (void) | |
12025 | { | |
12026 | do_t_ssat_usat (1); | |
12027 | } | |
b99bd4ef | 12028 | |
0dd132b6 | 12029 | static void |
c19d1205 | 12030 | do_t_ssat16 (void) |
0dd132b6 | 12031 | { |
fdfde340 JM |
12032 | unsigned Rd, Rn; |
12033 | ||
12034 | Rd = inst.operands[0].reg; | |
12035 | Rn = inst.operands[2].reg; | |
12036 | ||
12037 | reject_bad_reg (Rd); | |
12038 | reject_bad_reg (Rn); | |
12039 | ||
12040 | inst.instruction |= Rd << 8; | |
c19d1205 | 12041 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 12042 | inst.instruction |= Rn << 16; |
c19d1205 | 12043 | } |
0dd132b6 | 12044 | |
c19d1205 ZW |
12045 | static void |
12046 | do_t_strex (void) | |
12047 | { | |
12048 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
12049 | || inst.operands[2].postind || inst.operands[2].writeback | |
12050 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
12051 | || inst.operands[2].negative, | |
01cfc07f | 12052 | BAD_ADDR_MODE); |
0dd132b6 | 12053 | |
5be8be5d DG |
12054 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
12055 | ||
c19d1205 ZW |
12056 | inst.instruction |= inst.operands[0].reg << 8; |
12057 | inst.instruction |= inst.operands[1].reg << 12; | |
12058 | inst.instruction |= inst.operands[2].reg << 16; | |
12059 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
12060 | } |
12061 | ||
b99bd4ef | 12062 | static void |
c19d1205 | 12063 | do_t_strexd (void) |
b99bd4ef | 12064 | { |
c19d1205 ZW |
12065 | if (!inst.operands[2].present) |
12066 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 12067 | |
c19d1205 ZW |
12068 | constraint (inst.operands[0].reg == inst.operands[1].reg |
12069 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 12070 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 12071 | BAD_OVERLAP); |
b99bd4ef | 12072 | |
c19d1205 ZW |
12073 | inst.instruction |= inst.operands[0].reg; |
12074 | inst.instruction |= inst.operands[1].reg << 12; | |
12075 | inst.instruction |= inst.operands[2].reg << 8; | |
12076 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
12077 | } |
12078 | ||
12079 | static void | |
c19d1205 | 12080 | do_t_sxtah (void) |
b99bd4ef | 12081 | { |
fdfde340 JM |
12082 | unsigned Rd, Rn, Rm; |
12083 | ||
12084 | Rd = inst.operands[0].reg; | |
12085 | Rn = inst.operands[1].reg; | |
12086 | Rm = inst.operands[2].reg; | |
12087 | ||
12088 | reject_bad_reg (Rd); | |
12089 | reject_bad_reg (Rn); | |
12090 | reject_bad_reg (Rm); | |
12091 | ||
12092 | inst.instruction |= Rd << 8; | |
12093 | inst.instruction |= Rn << 16; | |
12094 | inst.instruction |= Rm; | |
c19d1205 ZW |
12095 | inst.instruction |= inst.operands[3].imm << 4; |
12096 | } | |
b99bd4ef | 12097 | |
c19d1205 ZW |
12098 | static void |
12099 | do_t_sxth (void) | |
12100 | { | |
fdfde340 JM |
12101 | unsigned Rd, Rm; |
12102 | ||
12103 | Rd = inst.operands[0].reg; | |
12104 | Rm = inst.operands[1].reg; | |
12105 | ||
12106 | reject_bad_reg (Rd); | |
12107 | reject_bad_reg (Rm); | |
c921be7d NC |
12108 | |
12109 | if (inst.instruction <= 0xffff | |
12110 | && inst.size_req != 4 | |
fdfde340 | 12111 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 12112 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 12113 | { |
c19d1205 | 12114 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
12115 | inst.instruction |= Rd; |
12116 | inst.instruction |= Rm << 3; | |
b99bd4ef | 12117 | } |
c19d1205 | 12118 | else if (unified_syntax) |
b99bd4ef | 12119 | { |
c19d1205 ZW |
12120 | if (inst.instruction <= 0xffff) |
12121 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
12122 | inst.instruction |= Rd << 8; |
12123 | inst.instruction |= Rm; | |
c19d1205 | 12124 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 12125 | } |
c19d1205 | 12126 | else |
b99bd4ef | 12127 | { |
c19d1205 ZW |
12128 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
12129 | _("Thumb encoding does not support rotation")); | |
12130 | constraint (1, BAD_HIREG); | |
b99bd4ef | 12131 | } |
c19d1205 | 12132 | } |
b99bd4ef | 12133 | |
c19d1205 ZW |
12134 | static void |
12135 | do_t_swi (void) | |
12136 | { | |
b2a5fbdc MGD |
12137 | /* We have to do the following check manually as ARM_EXT_OS only applies |
12138 | to ARM_EXT_V6M. */ | |
12139 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
12140 | { | |
ac7f631b NC |
12141 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
12142 | /* This only applies to the v6m howver, not later architectures. */ | |
12143 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
12144 | as_bad (_("SVC is not permitted on this architecture")); |
12145 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
12146 | } | |
12147 | ||
c19d1205 ZW |
12148 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
12149 | } | |
b99bd4ef | 12150 | |
92e90b6e PB |
12151 | static void |
12152 | do_t_tb (void) | |
12153 | { | |
fdfde340 | 12154 | unsigned Rn, Rm; |
92e90b6e PB |
12155 | int half; |
12156 | ||
12157 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 12158 | set_it_insn_type_last (); |
dfa9f0d5 PB |
12159 | constraint (inst.operands[0].immisreg, |
12160 | _("instruction requires register index")); | |
fdfde340 JM |
12161 | |
12162 | Rn = inst.operands[0].reg; | |
12163 | Rm = inst.operands[0].imm; | |
c921be7d | 12164 | |
fdfde340 JM |
12165 | constraint (Rn == REG_SP, BAD_SP); |
12166 | reject_bad_reg (Rm); | |
12167 | ||
92e90b6e PB |
12168 | constraint (!half && inst.operands[0].shifted, |
12169 | _("instruction does not allow shifted index")); | |
fdfde340 | 12170 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
12171 | } |
12172 | ||
c19d1205 ZW |
12173 | static void |
12174 | do_t_usat (void) | |
12175 | { | |
3a21c15a | 12176 | do_t_ssat_usat (0); |
b99bd4ef NC |
12177 | } |
12178 | ||
12179 | static void | |
c19d1205 | 12180 | do_t_usat16 (void) |
b99bd4ef | 12181 | { |
fdfde340 JM |
12182 | unsigned Rd, Rn; |
12183 | ||
12184 | Rd = inst.operands[0].reg; | |
12185 | Rn = inst.operands[2].reg; | |
12186 | ||
12187 | reject_bad_reg (Rd); | |
12188 | reject_bad_reg (Rn); | |
12189 | ||
12190 | inst.instruction |= Rd << 8; | |
c19d1205 | 12191 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 12192 | inst.instruction |= Rn << 16; |
b99bd4ef | 12193 | } |
c19d1205 | 12194 | |
5287ad62 | 12195 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 12196 | |
5287ad62 | 12197 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 12198 | |
5287ad62 JB |
12199 | /* An "invalid" code for the following tables. */ |
12200 | #define N_INV -1u | |
12201 | ||
12202 | struct neon_tab_entry | |
b99bd4ef | 12203 | { |
5287ad62 JB |
12204 | unsigned integer; |
12205 | unsigned float_or_poly; | |
12206 | unsigned scalar_or_imm; | |
12207 | }; | |
5f4273c7 | 12208 | |
5287ad62 JB |
12209 | /* Map overloaded Neon opcodes to their respective encodings. */ |
12210 | #define NEON_ENC_TAB \ | |
12211 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
12212 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
12213 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
12214 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
12215 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
12216 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
12217 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
12218 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
12219 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
12220 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
12221 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
12222 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 12223 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
12224 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
12225 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
12226 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
12227 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
12228 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
12229 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
12230 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
12231 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
12232 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
12233 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
12234 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
12235 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
12236 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
12237 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
12238 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
12239 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
12240 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
12241 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
12242 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
12243 | X(veor, 0x1000110, N_INV, N_INV), \ | |
12244 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
12245 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
12246 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
12247 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
12248 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
12249 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
12250 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
12251 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
12252 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
12253 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
12254 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
12255 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
12256 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
12257 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
12258 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
12259 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
12260 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
12261 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
12262 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
12263 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
12264 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
12265 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
12266 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
12267 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
12268 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
12269 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
12270 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
12271 | |
12272 | enum neon_opc | |
12273 | { | |
12274 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
12275 | NEON_ENC_TAB | |
12276 | #undef X | |
12277 | }; | |
b99bd4ef | 12278 | |
5287ad62 JB |
12279 | static const struct neon_tab_entry neon_enc_tab[] = |
12280 | { | |
12281 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
12282 | NEON_ENC_TAB | |
12283 | #undef X | |
12284 | }; | |
b99bd4ef | 12285 | |
88714cb8 DG |
12286 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
12287 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12288 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12289 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12290 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12291 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12292 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12293 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12294 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12295 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12296 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 12297 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 12298 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 12299 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 12300 | |
88714cb8 DG |
12301 | #define NEON_ENCODE(type, inst) \ |
12302 | do \ | |
12303 | { \ | |
12304 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
12305 | inst.is_neon = 1; \ | |
12306 | } \ | |
12307 | while (0) | |
12308 | ||
12309 | #define check_neon_suffixes \ | |
12310 | do \ | |
12311 | { \ | |
12312 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
12313 | { \ | |
12314 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
12315 | return; \ | |
12316 | } \ | |
12317 | } \ | |
12318 | while (0) | |
12319 | ||
037e8744 JB |
12320 | /* Define shapes for instruction operands. The following mnemonic characters |
12321 | are used in this table: | |
5287ad62 | 12322 | |
037e8744 | 12323 | F - VFP S<n> register |
5287ad62 JB |
12324 | D - Neon D<n> register |
12325 | Q - Neon Q<n> register | |
12326 | I - Immediate | |
12327 | S - Scalar | |
12328 | R - ARM register | |
12329 | L - D<n> register list | |
5f4273c7 | 12330 | |
037e8744 JB |
12331 | This table is used to generate various data: |
12332 | - enumerations of the form NS_DDR to be used as arguments to | |
12333 | neon_select_shape. | |
12334 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 12335 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 12336 | |
037e8744 JB |
12337 | #define NEON_SHAPE_DEF \ |
12338 | X(3, (D, D, D), DOUBLE), \ | |
12339 | X(3, (Q, Q, Q), QUAD), \ | |
12340 | X(3, (D, D, I), DOUBLE), \ | |
12341 | X(3, (Q, Q, I), QUAD), \ | |
12342 | X(3, (D, D, S), DOUBLE), \ | |
12343 | X(3, (Q, Q, S), QUAD), \ | |
12344 | X(2, (D, D), DOUBLE), \ | |
12345 | X(2, (Q, Q), QUAD), \ | |
12346 | X(2, (D, S), DOUBLE), \ | |
12347 | X(2, (Q, S), QUAD), \ | |
12348 | X(2, (D, R), DOUBLE), \ | |
12349 | X(2, (Q, R), QUAD), \ | |
12350 | X(2, (D, I), DOUBLE), \ | |
12351 | X(2, (Q, I), QUAD), \ | |
12352 | X(3, (D, L, D), DOUBLE), \ | |
12353 | X(2, (D, Q), MIXED), \ | |
12354 | X(2, (Q, D), MIXED), \ | |
12355 | X(3, (D, Q, I), MIXED), \ | |
12356 | X(3, (Q, D, I), MIXED), \ | |
12357 | X(3, (Q, D, D), MIXED), \ | |
12358 | X(3, (D, Q, Q), MIXED), \ | |
12359 | X(3, (Q, Q, D), MIXED), \ | |
12360 | X(3, (Q, D, S), MIXED), \ | |
12361 | X(3, (D, Q, S), MIXED), \ | |
12362 | X(4, (D, D, D, I), DOUBLE), \ | |
12363 | X(4, (Q, Q, Q, I), QUAD), \ | |
12364 | X(2, (F, F), SINGLE), \ | |
12365 | X(3, (F, F, F), SINGLE), \ | |
12366 | X(2, (F, I), SINGLE), \ | |
12367 | X(2, (F, D), MIXED), \ | |
12368 | X(2, (D, F), MIXED), \ | |
12369 | X(3, (F, F, I), MIXED), \ | |
12370 | X(4, (R, R, F, F), SINGLE), \ | |
12371 | X(4, (F, F, R, R), SINGLE), \ | |
12372 | X(3, (D, R, R), DOUBLE), \ | |
12373 | X(3, (R, R, D), DOUBLE), \ | |
12374 | X(2, (S, R), SINGLE), \ | |
12375 | X(2, (R, S), SINGLE), \ | |
12376 | X(2, (F, R), SINGLE), \ | |
12377 | X(2, (R, F), SINGLE) | |
12378 | ||
12379 | #define S2(A,B) NS_##A##B | |
12380 | #define S3(A,B,C) NS_##A##B##C | |
12381 | #define S4(A,B,C,D) NS_##A##B##C##D | |
12382 | ||
12383 | #define X(N, L, C) S##N L | |
12384 | ||
5287ad62 JB |
12385 | enum neon_shape |
12386 | { | |
037e8744 JB |
12387 | NEON_SHAPE_DEF, |
12388 | NS_NULL | |
5287ad62 | 12389 | }; |
b99bd4ef | 12390 | |
037e8744 JB |
12391 | #undef X |
12392 | #undef S2 | |
12393 | #undef S3 | |
12394 | #undef S4 | |
12395 | ||
12396 | enum neon_shape_class | |
12397 | { | |
12398 | SC_SINGLE, | |
12399 | SC_DOUBLE, | |
12400 | SC_QUAD, | |
12401 | SC_MIXED | |
12402 | }; | |
12403 | ||
12404 | #define X(N, L, C) SC_##C | |
12405 | ||
12406 | static enum neon_shape_class neon_shape_class[] = | |
12407 | { | |
12408 | NEON_SHAPE_DEF | |
12409 | }; | |
12410 | ||
12411 | #undef X | |
12412 | ||
12413 | enum neon_shape_el | |
12414 | { | |
12415 | SE_F, | |
12416 | SE_D, | |
12417 | SE_Q, | |
12418 | SE_I, | |
12419 | SE_S, | |
12420 | SE_R, | |
12421 | SE_L | |
12422 | }; | |
12423 | ||
12424 | /* Register widths of above. */ | |
12425 | static unsigned neon_shape_el_size[] = | |
12426 | { | |
12427 | 32, | |
12428 | 64, | |
12429 | 128, | |
12430 | 0, | |
12431 | 32, | |
12432 | 32, | |
12433 | 0 | |
12434 | }; | |
12435 | ||
12436 | struct neon_shape_info | |
12437 | { | |
12438 | unsigned els; | |
12439 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
12440 | }; | |
12441 | ||
12442 | #define S2(A,B) { SE_##A, SE_##B } | |
12443 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
12444 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
12445 | ||
12446 | #define X(N, L, C) { N, S##N L } | |
12447 | ||
12448 | static struct neon_shape_info neon_shape_tab[] = | |
12449 | { | |
12450 | NEON_SHAPE_DEF | |
12451 | }; | |
12452 | ||
12453 | #undef X | |
12454 | #undef S2 | |
12455 | #undef S3 | |
12456 | #undef S4 | |
12457 | ||
5287ad62 JB |
12458 | /* Bit masks used in type checking given instructions. |
12459 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
12460 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
12461 | set, various other bits can be set as well in order to modify the meaning of | |
12462 | the type constraint. */ | |
12463 | ||
12464 | enum neon_type_mask | |
12465 | { | |
8e79c3df CM |
12466 | N_S8 = 0x0000001, |
12467 | N_S16 = 0x0000002, | |
12468 | N_S32 = 0x0000004, | |
12469 | N_S64 = 0x0000008, | |
12470 | N_U8 = 0x0000010, | |
12471 | N_U16 = 0x0000020, | |
12472 | N_U32 = 0x0000040, | |
12473 | N_U64 = 0x0000080, | |
12474 | N_I8 = 0x0000100, | |
12475 | N_I16 = 0x0000200, | |
12476 | N_I32 = 0x0000400, | |
12477 | N_I64 = 0x0000800, | |
12478 | N_8 = 0x0001000, | |
12479 | N_16 = 0x0002000, | |
12480 | N_32 = 0x0004000, | |
12481 | N_64 = 0x0008000, | |
12482 | N_P8 = 0x0010000, | |
12483 | N_P16 = 0x0020000, | |
12484 | N_F16 = 0x0040000, | |
12485 | N_F32 = 0x0080000, | |
12486 | N_F64 = 0x0100000, | |
c921be7d NC |
12487 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
12488 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 12489 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
12490 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
12491 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
12492 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
12493 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
12494 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
12495 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
12496 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 12497 | N_UTYP = 0, |
037e8744 | 12498 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
12499 | }; |
12500 | ||
dcbf9037 JB |
12501 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
12502 | ||
5287ad62 JB |
12503 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
12504 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
12505 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
12506 | #define N_SUF_32 (N_SU_32 | N_F32) | |
12507 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
12508 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
12509 | ||
12510 | /* Pass this as the first type argument to neon_check_type to ignore types | |
12511 | altogether. */ | |
12512 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
12513 | ||
037e8744 JB |
12514 | /* Select a "shape" for the current instruction (describing register types or |
12515 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
12516 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
12517 | function of operand parsing, so this function doesn't need to be called. | |
12518 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
12519 | |
12520 | static enum neon_shape | |
037e8744 | 12521 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 12522 | { |
037e8744 JB |
12523 | va_list ap; |
12524 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
12525 | |
12526 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
12527 | many arguments we should have, so this makes the assumption that we have | |
12528 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
12529 | true in the future. */ | |
12530 | if (!inst.operands[1].present) | |
12531 | inst.operands[1] = inst.operands[0]; | |
12532 | ||
037e8744 | 12533 | va_start (ap, shape); |
5f4273c7 | 12534 | |
21d799b5 | 12535 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
12536 | { |
12537 | unsigned j; | |
12538 | int matches = 1; | |
12539 | ||
12540 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
12541 | { | |
12542 | if (!inst.operands[j].present) | |
12543 | { | |
12544 | matches = 0; | |
12545 | break; | |
12546 | } | |
12547 | ||
12548 | switch (neon_shape_tab[shape].el[j]) | |
12549 | { | |
12550 | case SE_F: | |
12551 | if (!(inst.operands[j].isreg | |
12552 | && inst.operands[j].isvec | |
12553 | && inst.operands[j].issingle | |
12554 | && !inst.operands[j].isquad)) | |
12555 | matches = 0; | |
12556 | break; | |
12557 | ||
12558 | case SE_D: | |
12559 | if (!(inst.operands[j].isreg | |
12560 | && inst.operands[j].isvec | |
12561 | && !inst.operands[j].isquad | |
12562 | && !inst.operands[j].issingle)) | |
12563 | matches = 0; | |
12564 | break; | |
12565 | ||
12566 | case SE_R: | |
12567 | if (!(inst.operands[j].isreg | |
12568 | && !inst.operands[j].isvec)) | |
12569 | matches = 0; | |
12570 | break; | |
12571 | ||
12572 | case SE_Q: | |
12573 | if (!(inst.operands[j].isreg | |
12574 | && inst.operands[j].isvec | |
12575 | && inst.operands[j].isquad | |
12576 | && !inst.operands[j].issingle)) | |
12577 | matches = 0; | |
12578 | break; | |
12579 | ||
12580 | case SE_I: | |
12581 | if (!(!inst.operands[j].isreg | |
12582 | && !inst.operands[j].isscalar)) | |
12583 | matches = 0; | |
12584 | break; | |
12585 | ||
12586 | case SE_S: | |
12587 | if (!(!inst.operands[j].isreg | |
12588 | && inst.operands[j].isscalar)) | |
12589 | matches = 0; | |
12590 | break; | |
12591 | ||
12592 | case SE_L: | |
12593 | break; | |
12594 | } | |
3fde54a2 JZ |
12595 | if (!matches) |
12596 | break; | |
037e8744 | 12597 | } |
ad6cec43 MGD |
12598 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
12599 | /* We've matched all the entries in the shape table, and we don't | |
12600 | have any left over operands which have not been matched. */ | |
5287ad62 | 12601 | break; |
037e8744 | 12602 | } |
5f4273c7 | 12603 | |
037e8744 | 12604 | va_end (ap); |
5287ad62 | 12605 | |
037e8744 JB |
12606 | if (shape == NS_NULL && first_shape != NS_NULL) |
12607 | first_error (_("invalid instruction shape")); | |
5287ad62 | 12608 | |
037e8744 JB |
12609 | return shape; |
12610 | } | |
5287ad62 | 12611 | |
037e8744 JB |
12612 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
12613 | means the Q bit should be set). */ | |
12614 | ||
12615 | static int | |
12616 | neon_quad (enum neon_shape shape) | |
12617 | { | |
12618 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 12619 | } |
037e8744 | 12620 | |
5287ad62 JB |
12621 | static void |
12622 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
12623 | unsigned *g_size) | |
12624 | { | |
12625 | /* Allow modification to be made to types which are constrained to be | |
12626 | based on the key element, based on bits set alongside N_EQK. */ | |
12627 | if ((typebits & N_EQK) != 0) | |
12628 | { | |
12629 | if ((typebits & N_HLF) != 0) | |
12630 | *g_size /= 2; | |
12631 | else if ((typebits & N_DBL) != 0) | |
12632 | *g_size *= 2; | |
12633 | if ((typebits & N_SGN) != 0) | |
12634 | *g_type = NT_signed; | |
12635 | else if ((typebits & N_UNS) != 0) | |
12636 | *g_type = NT_unsigned; | |
12637 | else if ((typebits & N_INT) != 0) | |
12638 | *g_type = NT_integer; | |
12639 | else if ((typebits & N_FLT) != 0) | |
12640 | *g_type = NT_float; | |
dcbf9037 JB |
12641 | else if ((typebits & N_SIZ) != 0) |
12642 | *g_type = NT_untyped; | |
5287ad62 JB |
12643 | } |
12644 | } | |
5f4273c7 | 12645 | |
5287ad62 JB |
12646 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
12647 | operand type, i.e. the single type specified in a Neon instruction when it | |
12648 | is the only one given. */ | |
12649 | ||
12650 | static struct neon_type_el | |
12651 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
12652 | { | |
12653 | struct neon_type_el dest = *key; | |
5f4273c7 | 12654 | |
9c2799c2 | 12655 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 12656 | |
5287ad62 JB |
12657 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
12658 | ||
12659 | return dest; | |
12660 | } | |
12661 | ||
12662 | /* Convert Neon type and size into compact bitmask representation. */ | |
12663 | ||
12664 | static enum neon_type_mask | |
12665 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
12666 | { | |
12667 | switch (type) | |
12668 | { | |
12669 | case NT_untyped: | |
12670 | switch (size) | |
12671 | { | |
12672 | case 8: return N_8; | |
12673 | case 16: return N_16; | |
12674 | case 32: return N_32; | |
12675 | case 64: return N_64; | |
12676 | default: ; | |
12677 | } | |
12678 | break; | |
12679 | ||
12680 | case NT_integer: | |
12681 | switch (size) | |
12682 | { | |
12683 | case 8: return N_I8; | |
12684 | case 16: return N_I16; | |
12685 | case 32: return N_I32; | |
12686 | case 64: return N_I64; | |
12687 | default: ; | |
12688 | } | |
12689 | break; | |
12690 | ||
12691 | case NT_float: | |
037e8744 JB |
12692 | switch (size) |
12693 | { | |
8e79c3df | 12694 | case 16: return N_F16; |
037e8744 JB |
12695 | case 32: return N_F32; |
12696 | case 64: return N_F64; | |
12697 | default: ; | |
12698 | } | |
5287ad62 JB |
12699 | break; |
12700 | ||
12701 | case NT_poly: | |
12702 | switch (size) | |
12703 | { | |
12704 | case 8: return N_P8; | |
12705 | case 16: return N_P16; | |
12706 | default: ; | |
12707 | } | |
12708 | break; | |
12709 | ||
12710 | case NT_signed: | |
12711 | switch (size) | |
12712 | { | |
12713 | case 8: return N_S8; | |
12714 | case 16: return N_S16; | |
12715 | case 32: return N_S32; | |
12716 | case 64: return N_S64; | |
12717 | default: ; | |
12718 | } | |
12719 | break; | |
12720 | ||
12721 | case NT_unsigned: | |
12722 | switch (size) | |
12723 | { | |
12724 | case 8: return N_U8; | |
12725 | case 16: return N_U16; | |
12726 | case 32: return N_U32; | |
12727 | case 64: return N_U64; | |
12728 | default: ; | |
12729 | } | |
12730 | break; | |
12731 | ||
12732 | default: ; | |
12733 | } | |
5f4273c7 | 12734 | |
5287ad62 JB |
12735 | return N_UTYP; |
12736 | } | |
12737 | ||
12738 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
12739 | handles the case where a single bit is set in the mask. */ | |
12740 | ||
dcbf9037 | 12741 | static int |
5287ad62 JB |
12742 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12743 | enum neon_type_mask mask) | |
12744 | { | |
dcbf9037 JB |
12745 | if ((mask & N_EQK) != 0) |
12746 | return FAIL; | |
12747 | ||
5287ad62 JB |
12748 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12749 | *size = 8; | |
dcbf9037 | 12750 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12751 | *size = 16; |
dcbf9037 | 12752 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12753 | *size = 32; |
037e8744 | 12754 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12755 | *size = 64; |
dcbf9037 JB |
12756 | else |
12757 | return FAIL; | |
12758 | ||
5287ad62 JB |
12759 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12760 | *type = NT_signed; | |
dcbf9037 | 12761 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12762 | *type = NT_unsigned; |
dcbf9037 | 12763 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12764 | *type = NT_integer; |
dcbf9037 | 12765 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12766 | *type = NT_untyped; |
dcbf9037 | 12767 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12768 | *type = NT_poly; |
037e8744 | 12769 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12770 | *type = NT_float; |
dcbf9037 JB |
12771 | else |
12772 | return FAIL; | |
5f4273c7 | 12773 | |
dcbf9037 | 12774 | return SUCCESS; |
5287ad62 JB |
12775 | } |
12776 | ||
12777 | /* Modify a bitmask of allowed types. This is only needed for type | |
12778 | relaxation. */ | |
12779 | ||
12780 | static unsigned | |
12781 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12782 | { | |
12783 | unsigned size; | |
12784 | enum neon_el_type type; | |
12785 | unsigned destmask; | |
12786 | int i; | |
5f4273c7 | 12787 | |
5287ad62 | 12788 | destmask = 0; |
5f4273c7 | 12789 | |
5287ad62 JB |
12790 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12791 | { | |
21d799b5 NC |
12792 | if (el_type_of_type_chk (&type, &size, |
12793 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12794 | { |
12795 | neon_modify_type_size (mods, &type, &size); | |
12796 | destmask |= type_chk_of_el_type (type, size); | |
12797 | } | |
5287ad62 | 12798 | } |
5f4273c7 | 12799 | |
5287ad62 JB |
12800 | return destmask; |
12801 | } | |
12802 | ||
12803 | /* Check type and return type classification. | |
12804 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12805 | type given in: | |
12806 | - the second operand, if there is one | |
12807 | - the operand, if there is no second operand | |
12808 | - the result, if there are no operands. | |
12809 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12810 | which is set on a per-instruction basis, which is the one which matters when | |
12811 | only one data type is written. | |
12812 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12813 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12814 | |
12815 | static struct neon_type_el | |
12816 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12817 | { | |
12818 | va_list ap; | |
12819 | unsigned i, pass, key_el = 0; | |
12820 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12821 | enum neon_el_type k_type = NT_invtype; | |
12822 | unsigned k_size = -1u; | |
12823 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12824 | unsigned key_allowed = 0; | |
12825 | ||
12826 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12827 | Fill in the missing operand here, if it was omitted. */ | |
12828 | if (els > 1 && !inst.operands[1].present) | |
12829 | inst.operands[1] = inst.operands[0]; | |
12830 | ||
12831 | /* Suck up all the varargs. */ | |
12832 | va_start (ap, ns); | |
12833 | for (i = 0; i < els; i++) | |
12834 | { | |
12835 | unsigned thisarg = va_arg (ap, unsigned); | |
12836 | if (thisarg == N_IGNORE_TYPE) | |
12837 | { | |
12838 | va_end (ap); | |
12839 | return badtype; | |
12840 | } | |
12841 | types[i] = thisarg; | |
12842 | if ((thisarg & N_KEY) != 0) | |
12843 | key_el = i; | |
12844 | } | |
12845 | va_end (ap); | |
12846 | ||
dcbf9037 JB |
12847 | if (inst.vectype.elems > 0) |
12848 | for (i = 0; i < els; i++) | |
12849 | if (inst.operands[i].vectype.type != NT_invtype) | |
12850 | { | |
12851 | first_error (_("types specified in both the mnemonic and operands")); | |
12852 | return badtype; | |
12853 | } | |
12854 | ||
5287ad62 JB |
12855 | /* Duplicate inst.vectype elements here as necessary. |
12856 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12857 | particularly when an insn takes one register and one non-register | |
12858 | operand. */ | |
12859 | if (inst.vectype.elems == 1 && els > 1) | |
12860 | { | |
12861 | unsigned j; | |
12862 | inst.vectype.elems = els; | |
12863 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12864 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12865 | if (j != key_el) |
12866 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12867 | types[j]); | |
12868 | } | |
12869 | else if (inst.vectype.elems == 0 && els > 0) | |
12870 | { | |
12871 | unsigned j; | |
12872 | /* No types were given after the mnemonic, so look for types specified | |
12873 | after each operand. We allow some flexibility here; as long as the | |
12874 | "key" operand has a type, we can infer the others. */ | |
12875 | for (j = 0; j < els; j++) | |
12876 | if (inst.operands[j].vectype.type != NT_invtype) | |
12877 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12878 | ||
12879 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12880 | { |
dcbf9037 JB |
12881 | for (j = 0; j < els; j++) |
12882 | if (inst.operands[j].vectype.type == NT_invtype) | |
12883 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12884 | types[j]); | |
12885 | } | |
12886 | else | |
12887 | { | |
12888 | first_error (_("operand types can't be inferred")); | |
12889 | return badtype; | |
5287ad62 JB |
12890 | } |
12891 | } | |
12892 | else if (inst.vectype.elems != els) | |
12893 | { | |
dcbf9037 | 12894 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12895 | return badtype; |
12896 | } | |
12897 | ||
12898 | for (pass = 0; pass < 2; pass++) | |
12899 | { | |
12900 | for (i = 0; i < els; i++) | |
12901 | { | |
12902 | unsigned thisarg = types[i]; | |
12903 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12904 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12905 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12906 | unsigned g_size = inst.vectype.el[i].size; | |
12907 | ||
12908 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12909 | integer types if sign-specific variants are unavailable. */ | |
12910 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12911 | && (types_allowed & N_SU_ALL) == 0) | |
12912 | g_type = NT_integer; | |
12913 | ||
12914 | /* If only untyped args are allowed, decay any more specific types to | |
12915 | them. Some instructions only care about signs for some element | |
12916 | sizes, so handle that properly. */ | |
12917 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12918 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12919 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12920 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12921 | g_type = NT_untyped; | |
12922 | ||
12923 | if (pass == 0) | |
12924 | { | |
12925 | if ((thisarg & N_KEY) != 0) | |
12926 | { | |
12927 | k_type = g_type; | |
12928 | k_size = g_size; | |
12929 | key_allowed = thisarg & ~N_KEY; | |
12930 | } | |
12931 | } | |
12932 | else | |
12933 | { | |
037e8744 JB |
12934 | if ((thisarg & N_VFP) != 0) |
12935 | { | |
99b253c5 NC |
12936 | enum neon_shape_el regshape; |
12937 | unsigned regwidth, match; | |
12938 | ||
12939 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12940 | if (ns == NS_NULL) | |
12941 | { | |
12942 | first_error (_("invalid instruction shape")); | |
12943 | return badtype; | |
12944 | } | |
12945 | regshape = neon_shape_tab[ns].el[i]; | |
12946 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12947 | |
12948 | /* In VFP mode, operands must match register widths. If we | |
12949 | have a key operand, use its width, else use the width of | |
12950 | the current operand. */ | |
12951 | if (k_size != -1u) | |
12952 | match = k_size; | |
12953 | else | |
12954 | match = g_size; | |
12955 | ||
12956 | if (regwidth != match) | |
12957 | { | |
12958 | first_error (_("operand size must match register width")); | |
12959 | return badtype; | |
12960 | } | |
12961 | } | |
5f4273c7 | 12962 | |
5287ad62 JB |
12963 | if ((thisarg & N_EQK) == 0) |
12964 | { | |
12965 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12966 | ||
12967 | if ((given_type & types_allowed) == 0) | |
12968 | { | |
dcbf9037 | 12969 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12970 | return badtype; |
12971 | } | |
12972 | } | |
12973 | else | |
12974 | { | |
12975 | enum neon_el_type mod_k_type = k_type; | |
12976 | unsigned mod_k_size = k_size; | |
12977 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12978 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12979 | { | |
dcbf9037 | 12980 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12981 | return badtype; |
12982 | } | |
12983 | } | |
12984 | } | |
12985 | } | |
12986 | } | |
12987 | ||
12988 | return inst.vectype.el[key_el]; | |
12989 | } | |
12990 | ||
037e8744 | 12991 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12992 | |
037e8744 JB |
12993 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12994 | ||
12995 | static void | |
12996 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12997 | { |
88714cb8 DG |
12998 | inst.is_neon = 1; |
12999 | ||
5287ad62 | 13000 | if (thumb_mode) |
037e8744 | 13001 | inst.instruction |= 0xe0000000; |
5287ad62 | 13002 | else |
037e8744 | 13003 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
13004 | } |
13005 | ||
037e8744 JB |
13006 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
13007 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
13008 | etc. It is assumed that operand parsing has already been done, and that the | |
13009 | operands are in the form expected by the given opcode (this isn't necessarily | |
13010 | the same as the form in which they were parsed, hence some massaging must | |
13011 | take place before this function is called). | |
13012 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 13013 | |
037e8744 JB |
13014 | static void |
13015 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 13016 | { |
037e8744 | 13017 | const struct asm_opcode *opcode; |
5f4273c7 | 13018 | |
21d799b5 | 13019 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 13020 | |
037e8744 JB |
13021 | if (!opcode) |
13022 | abort (); | |
5287ad62 | 13023 | |
037e8744 JB |
13024 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
13025 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
13026 | _(BAD_FPU)); | |
5287ad62 | 13027 | |
88714cb8 DG |
13028 | inst.is_neon = 1; |
13029 | ||
037e8744 JB |
13030 | if (thumb_mode) |
13031 | { | |
13032 | inst.instruction = opcode->tvalue; | |
13033 | opcode->tencode (); | |
13034 | } | |
13035 | else | |
13036 | { | |
13037 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
13038 | opcode->aencode (); | |
13039 | } | |
13040 | } | |
5287ad62 JB |
13041 | |
13042 | static void | |
037e8744 | 13043 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 13044 | { |
037e8744 JB |
13045 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
13046 | ||
13047 | if (rs == NS_FFF) | |
13048 | { | |
13049 | if (is_add) | |
13050 | do_vfp_nsyn_opcode ("fadds"); | |
13051 | else | |
13052 | do_vfp_nsyn_opcode ("fsubs"); | |
13053 | } | |
13054 | else | |
13055 | { | |
13056 | if (is_add) | |
13057 | do_vfp_nsyn_opcode ("faddd"); | |
13058 | else | |
13059 | do_vfp_nsyn_opcode ("fsubd"); | |
13060 | } | |
13061 | } | |
13062 | ||
13063 | /* Check operand types to see if this is a VFP instruction, and if so call | |
13064 | PFN (). */ | |
13065 | ||
13066 | static int | |
13067 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
13068 | { | |
13069 | enum neon_shape rs; | |
13070 | struct neon_type_el et; | |
13071 | ||
13072 | switch (args) | |
13073 | { | |
13074 | case 2: | |
13075 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13076 | et = neon_check_type (2, rs, | |
13077 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
13078 | break; | |
5f4273c7 | 13079 | |
037e8744 JB |
13080 | case 3: |
13081 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13082 | et = neon_check_type (3, rs, | |
13083 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
13084 | break; | |
13085 | ||
13086 | default: | |
13087 | abort (); | |
13088 | } | |
13089 | ||
13090 | if (et.type != NT_invtype) | |
13091 | { | |
13092 | pfn (rs); | |
13093 | return SUCCESS; | |
13094 | } | |
037e8744 | 13095 | |
99b253c5 | 13096 | inst.error = NULL; |
037e8744 JB |
13097 | return FAIL; |
13098 | } | |
13099 | ||
13100 | static void | |
13101 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
13102 | { | |
13103 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 13104 | |
037e8744 JB |
13105 | if (rs == NS_FFF) |
13106 | { | |
13107 | if (is_mla) | |
13108 | do_vfp_nsyn_opcode ("fmacs"); | |
13109 | else | |
1ee69515 | 13110 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
13111 | } |
13112 | else | |
13113 | { | |
13114 | if (is_mla) | |
13115 | do_vfp_nsyn_opcode ("fmacd"); | |
13116 | else | |
1ee69515 | 13117 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
13118 | } |
13119 | } | |
13120 | ||
62f3b8c8 PB |
13121 | static void |
13122 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
13123 | { | |
13124 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
13125 | ||
13126 | if (rs == NS_FFF) | |
13127 | { | |
13128 | if (is_fma) | |
13129 | do_vfp_nsyn_opcode ("ffmas"); | |
13130 | else | |
13131 | do_vfp_nsyn_opcode ("ffnmas"); | |
13132 | } | |
13133 | else | |
13134 | { | |
13135 | if (is_fma) | |
13136 | do_vfp_nsyn_opcode ("ffmad"); | |
13137 | else | |
13138 | do_vfp_nsyn_opcode ("ffnmad"); | |
13139 | } | |
13140 | } | |
13141 | ||
037e8744 JB |
13142 | static void |
13143 | do_vfp_nsyn_mul (enum neon_shape rs) | |
13144 | { | |
13145 | if (rs == NS_FFF) | |
13146 | do_vfp_nsyn_opcode ("fmuls"); | |
13147 | else | |
13148 | do_vfp_nsyn_opcode ("fmuld"); | |
13149 | } | |
13150 | ||
13151 | static void | |
13152 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
13153 | { | |
13154 | int is_neg = (inst.instruction & 0x80) != 0; | |
13155 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
13156 | ||
13157 | if (rs == NS_FF) | |
13158 | { | |
13159 | if (is_neg) | |
13160 | do_vfp_nsyn_opcode ("fnegs"); | |
13161 | else | |
13162 | do_vfp_nsyn_opcode ("fabss"); | |
13163 | } | |
13164 | else | |
13165 | { | |
13166 | if (is_neg) | |
13167 | do_vfp_nsyn_opcode ("fnegd"); | |
13168 | else | |
13169 | do_vfp_nsyn_opcode ("fabsd"); | |
13170 | } | |
13171 | } | |
13172 | ||
13173 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
13174 | insns belong to Neon, and are handled elsewhere. */ | |
13175 | ||
13176 | static void | |
13177 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
13178 | { | |
13179 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
13180 | if (is_ldm) | |
13181 | { | |
13182 | if (is_dbmode) | |
13183 | do_vfp_nsyn_opcode ("fldmdbs"); | |
13184 | else | |
13185 | do_vfp_nsyn_opcode ("fldmias"); | |
13186 | } | |
13187 | else | |
13188 | { | |
13189 | if (is_dbmode) | |
13190 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13191 | else | |
13192 | do_vfp_nsyn_opcode ("fstmias"); | |
13193 | } | |
13194 | } | |
13195 | ||
037e8744 JB |
13196 | static void |
13197 | do_vfp_nsyn_sqrt (void) | |
13198 | { | |
13199 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13200 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13201 | |
037e8744 JB |
13202 | if (rs == NS_FF) |
13203 | do_vfp_nsyn_opcode ("fsqrts"); | |
13204 | else | |
13205 | do_vfp_nsyn_opcode ("fsqrtd"); | |
13206 | } | |
13207 | ||
13208 | static void | |
13209 | do_vfp_nsyn_div (void) | |
13210 | { | |
13211 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13212 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13213 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13214 | |
037e8744 JB |
13215 | if (rs == NS_FFF) |
13216 | do_vfp_nsyn_opcode ("fdivs"); | |
13217 | else | |
13218 | do_vfp_nsyn_opcode ("fdivd"); | |
13219 | } | |
13220 | ||
13221 | static void | |
13222 | do_vfp_nsyn_nmul (void) | |
13223 | { | |
13224 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13225 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13226 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13227 | |
037e8744 JB |
13228 | if (rs == NS_FFF) |
13229 | { | |
88714cb8 | 13230 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13231 | do_vfp_sp_dyadic (); |
13232 | } | |
13233 | else | |
13234 | { | |
88714cb8 | 13235 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13236 | do_vfp_dp_rd_rn_rm (); |
13237 | } | |
13238 | do_vfp_cond_or_thumb (); | |
13239 | } | |
13240 | ||
13241 | static void | |
13242 | do_vfp_nsyn_cmp (void) | |
13243 | { | |
13244 | if (inst.operands[1].isreg) | |
13245 | { | |
13246 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13247 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13248 | |
037e8744 JB |
13249 | if (rs == NS_FF) |
13250 | { | |
88714cb8 | 13251 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13252 | do_vfp_sp_monadic (); |
13253 | } | |
13254 | else | |
13255 | { | |
88714cb8 | 13256 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13257 | do_vfp_dp_rd_rm (); |
13258 | } | |
13259 | } | |
13260 | else | |
13261 | { | |
13262 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
13263 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
13264 | ||
13265 | switch (inst.instruction & 0x0fffffff) | |
13266 | { | |
13267 | case N_MNEM_vcmp: | |
13268 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
13269 | break; | |
13270 | case N_MNEM_vcmpe: | |
13271 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
13272 | break; | |
13273 | default: | |
13274 | abort (); | |
13275 | } | |
5f4273c7 | 13276 | |
037e8744 JB |
13277 | if (rs == NS_FI) |
13278 | { | |
88714cb8 | 13279 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13280 | do_vfp_sp_compare_z (); |
13281 | } | |
13282 | else | |
13283 | { | |
88714cb8 | 13284 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13285 | do_vfp_dp_rd (); |
13286 | } | |
13287 | } | |
13288 | do_vfp_cond_or_thumb (); | |
13289 | } | |
13290 | ||
13291 | static void | |
13292 | nsyn_insert_sp (void) | |
13293 | { | |
13294 | inst.operands[1] = inst.operands[0]; | |
13295 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 13296 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
13297 | inst.operands[0].isreg = 1; |
13298 | inst.operands[0].writeback = 1; | |
13299 | inst.operands[0].present = 1; | |
13300 | } | |
13301 | ||
13302 | static void | |
13303 | do_vfp_nsyn_push (void) | |
13304 | { | |
13305 | nsyn_insert_sp (); | |
13306 | if (inst.operands[1].issingle) | |
13307 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13308 | else | |
13309 | do_vfp_nsyn_opcode ("fstmdbd"); | |
13310 | } | |
13311 | ||
13312 | static void | |
13313 | do_vfp_nsyn_pop (void) | |
13314 | { | |
13315 | nsyn_insert_sp (); | |
13316 | if (inst.operands[1].issingle) | |
22b5b651 | 13317 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 13318 | else |
22b5b651 | 13319 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
13320 | } |
13321 | ||
13322 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
13323 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
13324 | ||
88714cb8 DG |
13325 | static void |
13326 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 13327 | { |
88714cb8 DG |
13328 | unsigned int i = insn->instruction; |
13329 | insn->is_neon = 1; | |
13330 | ||
037e8744 JB |
13331 | if (thumb_mode) |
13332 | { | |
13333 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
13334 | if (i & (1 << 24)) | |
13335 | i |= 1 << 28; | |
5f4273c7 | 13336 | |
037e8744 | 13337 | i &= ~(1 << 24); |
5f4273c7 | 13338 | |
037e8744 JB |
13339 | i |= 0xef000000; |
13340 | } | |
13341 | else | |
13342 | i |= 0xf2000000; | |
5f4273c7 | 13343 | |
88714cb8 | 13344 | insn->instruction = i; |
037e8744 JB |
13345 | } |
13346 | ||
13347 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
13348 | (0, 1, 2, 3). */ | |
13349 | ||
13350 | static unsigned | |
13351 | neon_logbits (unsigned x) | |
13352 | { | |
13353 | return ffs (x) - 4; | |
13354 | } | |
13355 | ||
13356 | #define LOW4(R) ((R) & 0xf) | |
13357 | #define HI1(R) (((R) >> 4) & 1) | |
13358 | ||
13359 | /* Encode insns with bit pattern: | |
13360 | ||
13361 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
13362 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 13363 | |
037e8744 JB |
13364 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
13365 | different meaning for some instruction. */ | |
13366 | ||
13367 | static void | |
13368 | neon_three_same (int isquad, int ubit, int size) | |
13369 | { | |
13370 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13371 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13372 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13373 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13374 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13375 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
13376 | inst.instruction |= (isquad != 0) << 6; | |
13377 | inst.instruction |= (ubit != 0) << 24; | |
13378 | if (size != -1) | |
13379 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 13380 | |
88714cb8 | 13381 | neon_dp_fixup (&inst); |
037e8744 JB |
13382 | } |
13383 | ||
13384 | /* Encode instructions of the form: | |
13385 | ||
13386 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
13387 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
13388 | |
13389 | Don't write size if SIZE == -1. */ | |
13390 | ||
13391 | static void | |
13392 | neon_two_same (int qbit, int ubit, int size) | |
13393 | { | |
13394 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13395 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13396 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13397 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13398 | inst.instruction |= (qbit != 0) << 6; | |
13399 | inst.instruction |= (ubit != 0) << 24; | |
13400 | ||
13401 | if (size != -1) | |
13402 | inst.instruction |= neon_logbits (size) << 18; | |
13403 | ||
88714cb8 | 13404 | neon_dp_fixup (&inst); |
5287ad62 JB |
13405 | } |
13406 | ||
13407 | /* Neon instruction encoders, in approximate order of appearance. */ | |
13408 | ||
13409 | static void | |
13410 | do_neon_dyadic_i_su (void) | |
13411 | { | |
037e8744 | 13412 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13413 | struct neon_type_el et = neon_check_type (3, rs, |
13414 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 13415 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13416 | } |
13417 | ||
13418 | static void | |
13419 | do_neon_dyadic_i64_su (void) | |
13420 | { | |
037e8744 | 13421 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13422 | struct neon_type_el et = neon_check_type (3, rs, |
13423 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 13424 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13425 | } |
13426 | ||
13427 | static void | |
13428 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
13429 | unsigned immbits) | |
13430 | { | |
13431 | unsigned size = et.size >> 3; | |
13432 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13433 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13434 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13435 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13436 | inst.instruction |= (isquad != 0) << 6; | |
13437 | inst.instruction |= immbits << 16; | |
13438 | inst.instruction |= (size >> 3) << 7; | |
13439 | inst.instruction |= (size & 0x7) << 19; | |
13440 | if (write_ubit) | |
13441 | inst.instruction |= (uval != 0) << 24; | |
13442 | ||
88714cb8 | 13443 | neon_dp_fixup (&inst); |
5287ad62 JB |
13444 | } |
13445 | ||
13446 | static void | |
13447 | do_neon_shl_imm (void) | |
13448 | { | |
13449 | if (!inst.operands[2].isreg) | |
13450 | { | |
037e8744 | 13451 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13452 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 13453 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13454 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
13455 | } |
13456 | else | |
13457 | { | |
037e8744 | 13458 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13459 | struct neon_type_el et = neon_check_type (3, rs, |
13460 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13461 | unsigned int tmp; |
13462 | ||
13463 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
13464 | vshl.xx Dd, Dm, Dn | |
13465 | whereas other 3-register operations encoded by neon_three_same have | |
13466 | syntax like: | |
13467 | vadd.xx Dd, Dn, Dm | |
13468 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
13469 | here. */ | |
13470 | tmp = inst.operands[2].reg; | |
13471 | inst.operands[2].reg = inst.operands[1].reg; | |
13472 | inst.operands[1].reg = tmp; | |
88714cb8 | 13473 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13474 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13475 | } |
13476 | } | |
13477 | ||
13478 | static void | |
13479 | do_neon_qshl_imm (void) | |
13480 | { | |
13481 | if (!inst.operands[2].isreg) | |
13482 | { | |
037e8744 | 13483 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13484 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 13485 | |
88714cb8 | 13486 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13487 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
13488 | inst.operands[2].imm); |
13489 | } | |
13490 | else | |
13491 | { | |
037e8744 | 13492 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13493 | struct neon_type_el et = neon_check_type (3, rs, |
13494 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13495 | unsigned int tmp; |
13496 | ||
13497 | /* See note in do_neon_shl_imm. */ | |
13498 | tmp = inst.operands[2].reg; | |
13499 | inst.operands[2].reg = inst.operands[1].reg; | |
13500 | inst.operands[1].reg = tmp; | |
88714cb8 | 13501 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13502 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13503 | } |
13504 | } | |
13505 | ||
627907b7 JB |
13506 | static void |
13507 | do_neon_rshl (void) | |
13508 | { | |
13509 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
13510 | struct neon_type_el et = neon_check_type (3, rs, | |
13511 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
13512 | unsigned int tmp; | |
13513 | ||
13514 | tmp = inst.operands[2].reg; | |
13515 | inst.operands[2].reg = inst.operands[1].reg; | |
13516 | inst.operands[1].reg = tmp; | |
13517 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
13518 | } | |
13519 | ||
5287ad62 JB |
13520 | static int |
13521 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
13522 | { | |
036dc3f7 PB |
13523 | /* Handle .I8 pseudo-instructions. */ |
13524 | if (size == 8) | |
5287ad62 | 13525 | { |
5287ad62 JB |
13526 | /* Unfortunately, this will make everything apart from zero out-of-range. |
13527 | FIXME is this the intended semantics? There doesn't seem much point in | |
13528 | accepting .I8 if so. */ | |
13529 | immediate |= immediate << 8; | |
13530 | size = 16; | |
036dc3f7 PB |
13531 | } |
13532 | ||
13533 | if (size >= 32) | |
13534 | { | |
13535 | if (immediate == (immediate & 0x000000ff)) | |
13536 | { | |
13537 | *immbits = immediate; | |
13538 | return 0x1; | |
13539 | } | |
13540 | else if (immediate == (immediate & 0x0000ff00)) | |
13541 | { | |
13542 | *immbits = immediate >> 8; | |
13543 | return 0x3; | |
13544 | } | |
13545 | else if (immediate == (immediate & 0x00ff0000)) | |
13546 | { | |
13547 | *immbits = immediate >> 16; | |
13548 | return 0x5; | |
13549 | } | |
13550 | else if (immediate == (immediate & 0xff000000)) | |
13551 | { | |
13552 | *immbits = immediate >> 24; | |
13553 | return 0x7; | |
13554 | } | |
13555 | if ((immediate & 0xffff) != (immediate >> 16)) | |
13556 | goto bad_immediate; | |
13557 | immediate &= 0xffff; | |
5287ad62 JB |
13558 | } |
13559 | ||
13560 | if (immediate == (immediate & 0x000000ff)) | |
13561 | { | |
13562 | *immbits = immediate; | |
036dc3f7 | 13563 | return 0x9; |
5287ad62 JB |
13564 | } |
13565 | else if (immediate == (immediate & 0x0000ff00)) | |
13566 | { | |
13567 | *immbits = immediate >> 8; | |
036dc3f7 | 13568 | return 0xb; |
5287ad62 JB |
13569 | } |
13570 | ||
13571 | bad_immediate: | |
dcbf9037 | 13572 | first_error (_("immediate value out of range")); |
5287ad62 JB |
13573 | return FAIL; |
13574 | } | |
13575 | ||
13576 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
13577 | A, B, C, D. */ | |
13578 | ||
13579 | static int | |
13580 | neon_bits_same_in_bytes (unsigned imm) | |
13581 | { | |
13582 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
13583 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
13584 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
13585 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
13586 | } | |
13587 | ||
13588 | /* For immediate of above form, return 0bABCD. */ | |
13589 | ||
13590 | static unsigned | |
13591 | neon_squash_bits (unsigned imm) | |
13592 | { | |
13593 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
13594 | | ((imm & 0x01000000) >> 21); | |
13595 | } | |
13596 | ||
136da414 | 13597 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
13598 | |
13599 | static unsigned | |
13600 | neon_qfloat_bits (unsigned imm) | |
13601 | { | |
136da414 | 13602 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
13603 | } |
13604 | ||
13605 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
13606 | the instruction. *OP is passed as the initial value of the op field, and | |
13607 | may be set to a different value depending on the constant (i.e. | |
13608 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 13609 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 13610 | try smaller element sizes. */ |
5287ad62 JB |
13611 | |
13612 | static int | |
c96612cc JB |
13613 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
13614 | unsigned *immbits, int *op, int size, | |
13615 | enum neon_el_type type) | |
5287ad62 | 13616 | { |
c96612cc JB |
13617 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
13618 | float. */ | |
13619 | if (type == NT_float && !float_p) | |
13620 | return FAIL; | |
13621 | ||
136da414 JB |
13622 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
13623 | { | |
13624 | if (size != 32 || *op == 1) | |
13625 | return FAIL; | |
13626 | *immbits = neon_qfloat_bits (immlo); | |
13627 | return 0xf; | |
13628 | } | |
036dc3f7 PB |
13629 | |
13630 | if (size == 64) | |
5287ad62 | 13631 | { |
036dc3f7 PB |
13632 | if (neon_bits_same_in_bytes (immhi) |
13633 | && neon_bits_same_in_bytes (immlo)) | |
13634 | { | |
13635 | if (*op == 1) | |
13636 | return FAIL; | |
13637 | *immbits = (neon_squash_bits (immhi) << 4) | |
13638 | | neon_squash_bits (immlo); | |
13639 | *op = 1; | |
13640 | return 0xe; | |
13641 | } | |
13642 | ||
13643 | if (immhi != immlo) | |
13644 | return FAIL; | |
5287ad62 | 13645 | } |
036dc3f7 PB |
13646 | |
13647 | if (size >= 32) | |
5287ad62 | 13648 | { |
036dc3f7 PB |
13649 | if (immlo == (immlo & 0x000000ff)) |
13650 | { | |
13651 | *immbits = immlo; | |
13652 | return 0x0; | |
13653 | } | |
13654 | else if (immlo == (immlo & 0x0000ff00)) | |
13655 | { | |
13656 | *immbits = immlo >> 8; | |
13657 | return 0x2; | |
13658 | } | |
13659 | else if (immlo == (immlo & 0x00ff0000)) | |
13660 | { | |
13661 | *immbits = immlo >> 16; | |
13662 | return 0x4; | |
13663 | } | |
13664 | else if (immlo == (immlo & 0xff000000)) | |
13665 | { | |
13666 | *immbits = immlo >> 24; | |
13667 | return 0x6; | |
13668 | } | |
13669 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
13670 | { | |
13671 | *immbits = (immlo >> 8) & 0xff; | |
13672 | return 0xc; | |
13673 | } | |
13674 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
13675 | { | |
13676 | *immbits = (immlo >> 16) & 0xff; | |
13677 | return 0xd; | |
13678 | } | |
13679 | ||
13680 | if ((immlo & 0xffff) != (immlo >> 16)) | |
13681 | return FAIL; | |
13682 | immlo &= 0xffff; | |
5287ad62 | 13683 | } |
036dc3f7 PB |
13684 | |
13685 | if (size >= 16) | |
5287ad62 | 13686 | { |
036dc3f7 PB |
13687 | if (immlo == (immlo & 0x000000ff)) |
13688 | { | |
13689 | *immbits = immlo; | |
13690 | return 0x8; | |
13691 | } | |
13692 | else if (immlo == (immlo & 0x0000ff00)) | |
13693 | { | |
13694 | *immbits = immlo >> 8; | |
13695 | return 0xa; | |
13696 | } | |
13697 | ||
13698 | if ((immlo & 0xff) != (immlo >> 8)) | |
13699 | return FAIL; | |
13700 | immlo &= 0xff; | |
5287ad62 | 13701 | } |
036dc3f7 PB |
13702 | |
13703 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 13704 | { |
036dc3f7 PB |
13705 | /* Don't allow MVN with 8-bit immediate. */ |
13706 | if (*op == 1) | |
13707 | return FAIL; | |
13708 | *immbits = immlo; | |
13709 | return 0xe; | |
5287ad62 | 13710 | } |
5287ad62 JB |
13711 | |
13712 | return FAIL; | |
13713 | } | |
13714 | ||
13715 | /* Write immediate bits [7:0] to the following locations: | |
13716 | ||
13717 | |28/24|23 19|18 16|15 4|3 0| | |
13718 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
13719 | ||
13720 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
13721 | ||
13722 | static void | |
13723 | neon_write_immbits (unsigned immbits) | |
13724 | { | |
13725 | inst.instruction |= immbits & 0xf; | |
13726 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
13727 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
13728 | } | |
13729 | ||
13730 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
13731 | ||
13732 | static void | |
13733 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
13734 | { | |
13735 | unsigned immlo = xlo ? *xlo : 0; | |
13736 | unsigned immhi = xhi ? *xhi : 0; | |
13737 | ||
13738 | switch (size) | |
13739 | { | |
13740 | case 8: | |
13741 | immlo = (~immlo) & 0xff; | |
13742 | break; | |
13743 | ||
13744 | case 16: | |
13745 | immlo = (~immlo) & 0xffff; | |
13746 | break; | |
13747 | ||
13748 | case 64: | |
13749 | immhi = (~immhi) & 0xffffffff; | |
13750 | /* fall through. */ | |
13751 | ||
13752 | case 32: | |
13753 | immlo = (~immlo) & 0xffffffff; | |
13754 | break; | |
13755 | ||
13756 | default: | |
13757 | abort (); | |
13758 | } | |
13759 | ||
13760 | if (xlo) | |
13761 | *xlo = immlo; | |
13762 | ||
13763 | if (xhi) | |
13764 | *xhi = immhi; | |
13765 | } | |
13766 | ||
13767 | static void | |
13768 | do_neon_logic (void) | |
13769 | { | |
13770 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13771 | { | |
037e8744 | 13772 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13773 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13774 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13775 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13776 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13777 | } |
13778 | else | |
13779 | { | |
4316f0d2 DG |
13780 | const int three_ops_form = (inst.operands[2].present |
13781 | && !inst.operands[2].isreg); | |
13782 | const int immoperand = (three_ops_form ? 2 : 1); | |
13783 | enum neon_shape rs = (three_ops_form | |
13784 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13785 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13786 | struct neon_type_el et = neon_check_type (2, rs, |
13787 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13788 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13789 | unsigned immbits; |
13790 | int cmode; | |
5f4273c7 | 13791 | |
5287ad62 JB |
13792 | if (et.type == NT_invtype) |
13793 | return; | |
5f4273c7 | 13794 | |
4316f0d2 DG |
13795 | if (three_ops_form) |
13796 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13797 | _("first and second operands shall be the same register")); | |
13798 | ||
88714cb8 | 13799 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13800 | |
4316f0d2 | 13801 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13802 | if (et.size == 64) |
13803 | { | |
13804 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13805 | pattern. */ | |
4316f0d2 DG |
13806 | if (immbits != (inst.operands[immoperand].regisimm ? |
13807 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13808 | { |
13809 | /* Set immbits to an invalid constant. */ | |
13810 | immbits = 0xdeadbeef; | |
13811 | } | |
13812 | } | |
13813 | ||
5287ad62 JB |
13814 | switch (opcode) |
13815 | { | |
13816 | case N_MNEM_vbic: | |
036dc3f7 | 13817 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13818 | break; |
5f4273c7 | 13819 | |
5287ad62 | 13820 | case N_MNEM_vorr: |
036dc3f7 | 13821 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13822 | break; |
5f4273c7 | 13823 | |
5287ad62 JB |
13824 | case N_MNEM_vand: |
13825 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13826 | neon_invert_size (&immbits, 0, et.size); |
13827 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13828 | break; | |
5f4273c7 | 13829 | |
5287ad62 JB |
13830 | case N_MNEM_vorn: |
13831 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13832 | neon_invert_size (&immbits, 0, et.size); |
13833 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13834 | break; | |
5f4273c7 | 13835 | |
5287ad62 JB |
13836 | default: |
13837 | abort (); | |
13838 | } | |
13839 | ||
13840 | if (cmode == FAIL) | |
13841 | return; | |
13842 | ||
037e8744 | 13843 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13844 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13845 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13846 | inst.instruction |= cmode << 8; | |
13847 | neon_write_immbits (immbits); | |
5f4273c7 | 13848 | |
88714cb8 | 13849 | neon_dp_fixup (&inst); |
5287ad62 JB |
13850 | } |
13851 | } | |
13852 | ||
13853 | static void | |
13854 | do_neon_bitfield (void) | |
13855 | { | |
037e8744 | 13856 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13857 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13858 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13859 | } |
13860 | ||
13861 | static void | |
dcbf9037 JB |
13862 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13863 | unsigned destbits) | |
5287ad62 | 13864 | { |
037e8744 | 13865 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13866 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13867 | types | N_KEY); | |
5287ad62 JB |
13868 | if (et.type == NT_float) |
13869 | { | |
88714cb8 | 13870 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13871 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13872 | } |
13873 | else | |
13874 | { | |
88714cb8 | 13875 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13876 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13877 | } |
13878 | } | |
13879 | ||
13880 | static void | |
13881 | do_neon_dyadic_if_su (void) | |
13882 | { | |
dcbf9037 | 13883 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13884 | } |
13885 | ||
13886 | static void | |
13887 | do_neon_dyadic_if_su_d (void) | |
13888 | { | |
13889 | /* This version only allow D registers, but that constraint is enforced during | |
13890 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13891 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13892 | } |
13893 | ||
5287ad62 JB |
13894 | static void |
13895 | do_neon_dyadic_if_i_d (void) | |
13896 | { | |
428e3f1f PB |
13897 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13898 | affected if we specify unsigned args. */ | |
13899 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13900 | } |
13901 | ||
037e8744 JB |
13902 | enum vfp_or_neon_is_neon_bits |
13903 | { | |
13904 | NEON_CHECK_CC = 1, | |
13905 | NEON_CHECK_ARCH = 2 | |
13906 | }; | |
13907 | ||
13908 | /* Call this function if an instruction which may have belonged to the VFP or | |
13909 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13910 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13911 | things: | |
13912 | ||
13913 | - Make sure the user hasn't attempted to make a Neon instruction | |
13914 | conditional. | |
13915 | - Alter the value in the condition code field if necessary. | |
13916 | - Make sure that the arch supports Neon instructions. | |
13917 | ||
13918 | Which of these operations take place depends on bits from enum | |
13919 | vfp_or_neon_is_neon_bits. | |
13920 | ||
13921 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13922 | current instruction's condition is COND_ALWAYS, the condition field is | |
13923 | changed to inst.uncond_value. This is necessary because instructions shared | |
13924 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13925 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13926 | ||
13927 | static int | |
13928 | vfp_or_neon_is_neon (unsigned check) | |
13929 | { | |
13930 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13931 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13932 | { | |
13933 | if (inst.cond != COND_ALWAYS) | |
13934 | { | |
13935 | first_error (_(BAD_COND)); | |
13936 | return FAIL; | |
13937 | } | |
13938 | if (inst.uncond_value != -1) | |
13939 | inst.instruction |= inst.uncond_value << 28; | |
13940 | } | |
5f4273c7 | 13941 | |
037e8744 JB |
13942 | if ((check & NEON_CHECK_ARCH) |
13943 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13944 | { | |
13945 | first_error (_(BAD_FPU)); | |
13946 | return FAIL; | |
13947 | } | |
5f4273c7 | 13948 | |
037e8744 JB |
13949 | return SUCCESS; |
13950 | } | |
13951 | ||
5287ad62 JB |
13952 | static void |
13953 | do_neon_addsub_if_i (void) | |
13954 | { | |
037e8744 JB |
13955 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13956 | return; | |
13957 | ||
13958 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13959 | return; | |
13960 | ||
5287ad62 JB |
13961 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13962 | affected if we specify unsigned args. */ | |
dcbf9037 | 13963 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13964 | } |
13965 | ||
13966 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13967 | result to be: | |
13968 | V<op> A,B (A is operand 0, B is operand 2) | |
13969 | to mean: | |
13970 | V<op> A,B,A | |
13971 | not: | |
13972 | V<op> A,B,B | |
13973 | so handle that case specially. */ | |
13974 | ||
13975 | static void | |
13976 | neon_exchange_operands (void) | |
13977 | { | |
13978 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13979 | if (inst.operands[1].present) | |
13980 | { | |
13981 | /* Swap operands[1] and operands[2]. */ | |
13982 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13983 | inst.operands[1] = inst.operands[2]; | |
13984 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13985 | } | |
13986 | else | |
13987 | { | |
13988 | inst.operands[1] = inst.operands[2]; | |
13989 | inst.operands[2] = inst.operands[0]; | |
13990 | } | |
13991 | } | |
13992 | ||
13993 | static void | |
13994 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13995 | { | |
13996 | if (inst.operands[2].isreg) | |
13997 | { | |
13998 | if (invert) | |
13999 | neon_exchange_operands (); | |
dcbf9037 | 14000 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
14001 | } |
14002 | else | |
14003 | { | |
037e8744 | 14004 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
14005 | struct neon_type_el et = neon_check_type (2, rs, |
14006 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 14007 | |
88714cb8 | 14008 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14009 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14010 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14011 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14012 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14013 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14014 | inst.instruction |= (et.type == NT_float) << 10; |
14015 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14016 | |
88714cb8 | 14017 | neon_dp_fixup (&inst); |
5287ad62 JB |
14018 | } |
14019 | } | |
14020 | ||
14021 | static void | |
14022 | do_neon_cmp (void) | |
14023 | { | |
14024 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
14025 | } | |
14026 | ||
14027 | static void | |
14028 | do_neon_cmp_inv (void) | |
14029 | { | |
14030 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
14031 | } | |
14032 | ||
14033 | static void | |
14034 | do_neon_ceq (void) | |
14035 | { | |
14036 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
14037 | } | |
14038 | ||
14039 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
14040 | scalars, which are encoded in 5 bits, M : Rm. | |
14041 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
14042 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
14043 | index in M. */ | |
14044 | ||
14045 | static unsigned | |
14046 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
14047 | { | |
dcbf9037 JB |
14048 | unsigned regno = NEON_SCALAR_REG (scalar); |
14049 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
14050 | |
14051 | switch (elsize) | |
14052 | { | |
14053 | case 16: | |
14054 | if (regno > 7 || elno > 3) | |
14055 | goto bad_scalar; | |
14056 | return regno | (elno << 3); | |
5f4273c7 | 14057 | |
5287ad62 JB |
14058 | case 32: |
14059 | if (regno > 15 || elno > 1) | |
14060 | goto bad_scalar; | |
14061 | return regno | (elno << 4); | |
14062 | ||
14063 | default: | |
14064 | bad_scalar: | |
dcbf9037 | 14065 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
14066 | } |
14067 | ||
14068 | return 0; | |
14069 | } | |
14070 | ||
14071 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
14072 | ||
14073 | static void | |
14074 | neon_mul_mac (struct neon_type_el et, int ubit) | |
14075 | { | |
dcbf9037 JB |
14076 | unsigned scalar; |
14077 | ||
14078 | /* Give a more helpful error message if we have an invalid type. */ | |
14079 | if (et.type == NT_invtype) | |
14080 | return; | |
5f4273c7 | 14081 | |
dcbf9037 | 14082 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
14083 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14084 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14085 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14086 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14087 | inst.instruction |= LOW4 (scalar); | |
14088 | inst.instruction |= HI1 (scalar) << 5; | |
14089 | inst.instruction |= (et.type == NT_float) << 8; | |
14090 | inst.instruction |= neon_logbits (et.size) << 20; | |
14091 | inst.instruction |= (ubit != 0) << 24; | |
14092 | ||
88714cb8 | 14093 | neon_dp_fixup (&inst); |
5287ad62 JB |
14094 | } |
14095 | ||
14096 | static void | |
14097 | do_neon_mac_maybe_scalar (void) | |
14098 | { | |
037e8744 JB |
14099 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
14100 | return; | |
14101 | ||
14102 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14103 | return; | |
14104 | ||
5287ad62 JB |
14105 | if (inst.operands[2].isscalar) |
14106 | { | |
037e8744 | 14107 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
14108 | struct neon_type_el et = neon_check_type (3, rs, |
14109 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 14110 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14111 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14112 | } |
14113 | else | |
428e3f1f PB |
14114 | { |
14115 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
14116 | affected if we specify unsigned args. */ | |
14117 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14118 | } | |
5287ad62 JB |
14119 | } |
14120 | ||
62f3b8c8 PB |
14121 | static void |
14122 | do_neon_fmac (void) | |
14123 | { | |
14124 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
14125 | return; | |
14126 | ||
14127 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14128 | return; | |
14129 | ||
14130 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
14131 | } | |
14132 | ||
5287ad62 JB |
14133 | static void |
14134 | do_neon_tst (void) | |
14135 | { | |
037e8744 | 14136 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14137 | struct neon_type_el et = neon_check_type (3, rs, |
14138 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 14139 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14140 | } |
14141 | ||
14142 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
14143 | same types as the MAC equivalents. The polynomial type for this instruction | |
14144 | is encoded the same as the integer type. */ | |
14145 | ||
14146 | static void | |
14147 | do_neon_mul (void) | |
14148 | { | |
037e8744 JB |
14149 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
14150 | return; | |
14151 | ||
14152 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14153 | return; | |
14154 | ||
5287ad62 JB |
14155 | if (inst.operands[2].isscalar) |
14156 | do_neon_mac_maybe_scalar (); | |
14157 | else | |
dcbf9037 | 14158 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
14159 | } |
14160 | ||
14161 | static void | |
14162 | do_neon_qdmulh (void) | |
14163 | { | |
14164 | if (inst.operands[2].isscalar) | |
14165 | { | |
037e8744 | 14166 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
14167 | struct neon_type_el et = neon_check_type (3, rs, |
14168 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 14169 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14170 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14171 | } |
14172 | else | |
14173 | { | |
037e8744 | 14174 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14175 | struct neon_type_el et = neon_check_type (3, rs, |
14176 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 14177 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14178 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14179 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14180 | } |
14181 | } | |
14182 | ||
14183 | static void | |
14184 | do_neon_fcmp_absolute (void) | |
14185 | { | |
037e8744 | 14186 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14187 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14188 | /* Size field comes from bit mask. */ | |
037e8744 | 14189 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14190 | } |
14191 | ||
14192 | static void | |
14193 | do_neon_fcmp_absolute_inv (void) | |
14194 | { | |
14195 | neon_exchange_operands (); | |
14196 | do_neon_fcmp_absolute (); | |
14197 | } | |
14198 | ||
14199 | static void | |
14200 | do_neon_step (void) | |
14201 | { | |
037e8744 | 14202 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14203 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14204 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14205 | } |
14206 | ||
14207 | static void | |
14208 | do_neon_abs_neg (void) | |
14209 | { | |
037e8744 JB |
14210 | enum neon_shape rs; |
14211 | struct neon_type_el et; | |
5f4273c7 | 14212 | |
037e8744 JB |
14213 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14214 | return; | |
14215 | ||
14216 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14217 | return; | |
14218 | ||
14219 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14220 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14221 | |
5287ad62 JB |
14222 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14223 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14224 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14225 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14226 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14227 | inst.instruction |= (et.type == NT_float) << 10; |
14228 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14229 | |
88714cb8 | 14230 | neon_dp_fixup (&inst); |
5287ad62 JB |
14231 | } |
14232 | ||
14233 | static void | |
14234 | do_neon_sli (void) | |
14235 | { | |
037e8744 | 14236 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14237 | struct neon_type_el et = neon_check_type (2, rs, |
14238 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14239 | int imm = inst.operands[2].imm; | |
14240 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14241 | _("immediate out of range for insert")); | |
037e8744 | 14242 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14243 | } |
14244 | ||
14245 | static void | |
14246 | do_neon_sri (void) | |
14247 | { | |
037e8744 | 14248 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14249 | struct neon_type_el et = neon_check_type (2, rs, |
14250 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14251 | int imm = inst.operands[2].imm; | |
14252 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14253 | _("immediate out of range for insert")); | |
037e8744 | 14254 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14255 | } |
14256 | ||
14257 | static void | |
14258 | do_neon_qshlu_imm (void) | |
14259 | { | |
037e8744 | 14260 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14261 | struct neon_type_el et = neon_check_type (2, rs, |
14262 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14263 | int imm = inst.operands[2].imm; | |
14264 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14265 | _("immediate out of range for shift")); | |
14266 | /* Only encodes the 'U present' variant of the instruction. | |
14267 | In this case, signed types have OP (bit 8) set to 0. | |
14268 | Unsigned types have OP set to 1. */ | |
14269 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14270 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14271 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14272 | } |
14273 | ||
14274 | static void | |
14275 | do_neon_qmovn (void) | |
14276 | { | |
14277 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14278 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14279 | /* Saturating move where operands can be signed or unsigned, and the | |
14280 | destination has the same signedness. */ | |
88714cb8 | 14281 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14282 | if (et.type == NT_unsigned) |
14283 | inst.instruction |= 0xc0; | |
14284 | else | |
14285 | inst.instruction |= 0x80; | |
14286 | neon_two_same (0, 1, et.size / 2); | |
14287 | } | |
14288 | ||
14289 | static void | |
14290 | do_neon_qmovun (void) | |
14291 | { | |
14292 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14293 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14294 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14295 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14296 | neon_two_same (0, 1, et.size / 2); |
14297 | } | |
14298 | ||
14299 | static void | |
14300 | do_neon_rshift_sat_narrow (void) | |
14301 | { | |
14302 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14303 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14304 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14305 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14306 | int imm = inst.operands[2].imm; | |
14307 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14308 | right. */ | |
14309 | et.size /= 2; | |
5f4273c7 | 14310 | |
5287ad62 JB |
14311 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14312 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14313 | if (imm == 0) | |
14314 | { | |
14315 | inst.operands[2].present = 0; | |
14316 | inst.instruction = N_MNEM_vqmovn; | |
14317 | do_neon_qmovn (); | |
14318 | return; | |
14319 | } | |
5f4273c7 | 14320 | |
5287ad62 JB |
14321 | constraint (imm < 1 || (unsigned)imm > et.size, |
14322 | _("immediate out of range")); | |
14323 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
14324 | } | |
14325 | ||
14326 | static void | |
14327 | do_neon_rshift_sat_narrow_u (void) | |
14328 | { | |
14329 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14330 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14331 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14332 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14333 | int imm = inst.operands[2].imm; | |
14334 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14335 | right. */ | |
14336 | et.size /= 2; | |
14337 | ||
14338 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14339 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14340 | if (imm == 0) | |
14341 | { | |
14342 | inst.operands[2].present = 0; | |
14343 | inst.instruction = N_MNEM_vqmovun; | |
14344 | do_neon_qmovun (); | |
14345 | return; | |
14346 | } | |
14347 | ||
14348 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14349 | _("immediate out of range")); | |
14350 | /* FIXME: The manual is kind of unclear about what value U should have in | |
14351 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
14352 | must be 1. */ | |
14353 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
14354 | } | |
14355 | ||
14356 | static void | |
14357 | do_neon_movn (void) | |
14358 | { | |
14359 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14360 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 14361 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14362 | neon_two_same (0, 1, et.size / 2); |
14363 | } | |
14364 | ||
14365 | static void | |
14366 | do_neon_rshift_narrow (void) | |
14367 | { | |
14368 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14369 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
14370 | int imm = inst.operands[2].imm; | |
14371 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14372 | right. */ | |
14373 | et.size /= 2; | |
5f4273c7 | 14374 | |
5287ad62 JB |
14375 | /* If immediate is zero then we are a pseudo-instruction for |
14376 | VMOVN.I<size> <Dd>, <Qm> */ | |
14377 | if (imm == 0) | |
14378 | { | |
14379 | inst.operands[2].present = 0; | |
14380 | inst.instruction = N_MNEM_vmovn; | |
14381 | do_neon_movn (); | |
14382 | return; | |
14383 | } | |
5f4273c7 | 14384 | |
5287ad62 JB |
14385 | constraint (imm < 1 || (unsigned)imm > et.size, |
14386 | _("immediate out of range for narrowing operation")); | |
14387 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
14388 | } | |
14389 | ||
14390 | static void | |
14391 | do_neon_shll (void) | |
14392 | { | |
14393 | /* FIXME: Type checking when lengthening. */ | |
14394 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14395 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14396 | unsigned imm = inst.operands[2].imm; | |
14397 | ||
14398 | if (imm == et.size) | |
14399 | { | |
14400 | /* Maximum shift variant. */ | |
88714cb8 | 14401 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14402 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14403 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14404 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14405 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14406 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14407 | |
88714cb8 | 14408 | neon_dp_fixup (&inst); |
5287ad62 JB |
14409 | } |
14410 | else | |
14411 | { | |
14412 | /* A more-specific type check for non-max versions. */ | |
14413 | et = neon_check_type (2, NS_QDI, | |
14414 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 14415 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14416 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14417 | } | |
14418 | } | |
14419 | ||
037e8744 | 14420 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14421 | the current instruction is. */ |
14422 | ||
14423 | static int | |
14424 | neon_cvt_flavour (enum neon_shape rs) | |
14425 | { | |
037e8744 JB |
14426 | #define CVT_VAR(C,X,Y) \ |
14427 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
14428 | if (et.type != NT_invtype) \ | |
14429 | { \ | |
14430 | inst.error = NULL; \ | |
14431 | return (C); \ | |
5287ad62 JB |
14432 | } |
14433 | struct neon_type_el et; | |
037e8744 JB |
14434 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
14435 | || rs == NS_FF) ? N_VFP : 0; | |
14436 | /* The instruction versions which take an immediate take one register | |
14437 | argument, which is extended to the width of the full register. Thus the | |
14438 | "source" and "destination" registers must have the same width. Hack that | |
14439 | here by making the size equal to the key (wider, in this case) operand. */ | |
14440 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14441 | |
5287ad62 JB |
14442 | CVT_VAR (0, N_S32, N_F32); |
14443 | CVT_VAR (1, N_U32, N_F32); | |
14444 | CVT_VAR (2, N_F32, N_S32); | |
14445 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
14446 | /* Half-precision conversions. */ |
14447 | CVT_VAR (4, N_F32, N_F16); | |
14448 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 14449 | |
037e8744 | 14450 | whole_reg = N_VFP; |
5f4273c7 | 14451 | |
037e8744 | 14452 | /* VFP instructions. */ |
8e79c3df CM |
14453 | CVT_VAR (6, N_F32, N_F64); |
14454 | CVT_VAR (7, N_F64, N_F32); | |
14455 | CVT_VAR (8, N_S32, N_F64 | key); | |
14456 | CVT_VAR (9, N_U32, N_F64 | key); | |
14457 | CVT_VAR (10, N_F64 | key, N_S32); | |
14458 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 14459 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
14460 | CVT_VAR (12, N_F32 | key, N_S16); |
14461 | CVT_VAR (13, N_F32 | key, N_U16); | |
14462 | CVT_VAR (14, N_F64 | key, N_S16); | |
14463 | CVT_VAR (15, N_F64 | key, N_U16); | |
14464 | CVT_VAR (16, N_S16, N_F32 | key); | |
14465 | CVT_VAR (17, N_U16, N_F32 | key); | |
14466 | CVT_VAR (18, N_S16, N_F64 | key); | |
14467 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 14468 | |
5287ad62 JB |
14469 | return -1; |
14470 | #undef CVT_VAR | |
14471 | } | |
14472 | ||
037e8744 JB |
14473 | /* Neon-syntax VFP conversions. */ |
14474 | ||
5287ad62 | 14475 | static void |
037e8744 | 14476 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 14477 | { |
037e8744 | 14478 | const char *opname = 0; |
5f4273c7 | 14479 | |
037e8744 | 14480 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14481 | { |
037e8744 JB |
14482 | /* Conversions with immediate bitshift. */ |
14483 | const char *enc[] = | |
14484 | { | |
14485 | "ftosls", | |
14486 | "ftouls", | |
14487 | "fsltos", | |
14488 | "fultos", | |
14489 | NULL, | |
14490 | NULL, | |
8e79c3df CM |
14491 | NULL, |
14492 | NULL, | |
037e8744 JB |
14493 | "ftosld", |
14494 | "ftould", | |
14495 | "fsltod", | |
14496 | "fultod", | |
14497 | "fshtos", | |
14498 | "fuhtos", | |
14499 | "fshtod", | |
14500 | "fuhtod", | |
14501 | "ftoshs", | |
14502 | "ftouhs", | |
14503 | "ftoshd", | |
14504 | "ftouhd" | |
14505 | }; | |
14506 | ||
14507 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14508 | { | |
14509 | opname = enc[flavour]; | |
14510 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14511 | _("operands 0 and 1 must be the same register")); | |
14512 | inst.operands[1] = inst.operands[2]; | |
14513 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
14514 | } | |
5287ad62 JB |
14515 | } |
14516 | else | |
14517 | { | |
037e8744 JB |
14518 | /* Conversions without bitshift. */ |
14519 | const char *enc[] = | |
14520 | { | |
14521 | "ftosis", | |
14522 | "ftouis", | |
14523 | "fsitos", | |
14524 | "fuitos", | |
8e79c3df CM |
14525 | "NULL", |
14526 | "NULL", | |
037e8744 JB |
14527 | "fcvtsd", |
14528 | "fcvtds", | |
14529 | "ftosid", | |
14530 | "ftouid", | |
14531 | "fsitod", | |
14532 | "fuitod" | |
14533 | }; | |
14534 | ||
14535 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14536 | opname = enc[flavour]; | |
14537 | } | |
14538 | ||
14539 | if (opname) | |
14540 | do_vfp_nsyn_opcode (opname); | |
14541 | } | |
14542 | ||
14543 | static void | |
14544 | do_vfp_nsyn_cvtz (void) | |
14545 | { | |
14546 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
14547 | int flavour = neon_cvt_flavour (rs); | |
14548 | const char *enc[] = | |
14549 | { | |
14550 | "ftosizs", | |
14551 | "ftouizs", | |
14552 | NULL, | |
14553 | NULL, | |
14554 | NULL, | |
14555 | NULL, | |
8e79c3df CM |
14556 | NULL, |
14557 | NULL, | |
037e8744 JB |
14558 | "ftosizd", |
14559 | "ftouizd" | |
14560 | }; | |
14561 | ||
14562 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
14563 | do_vfp_nsyn_opcode (enc[flavour]); | |
14564 | } | |
f31fef98 | 14565 | |
037e8744 | 14566 | static void |
e3e535bc | 14567 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
14568 | { |
14569 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 14570 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
14571 | int flavour = neon_cvt_flavour (rs); |
14572 | ||
e3e535bc NC |
14573 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
14574 | if (round_to_zero | |
14575 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
14576 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
14577 | && (rs == NS_FD || rs == NS_FF)) | |
14578 | { | |
14579 | do_vfp_nsyn_cvtz (); | |
14580 | return; | |
14581 | } | |
14582 | ||
037e8744 | 14583 | /* VFP rather than Neon conversions. */ |
8e79c3df | 14584 | if (flavour >= 6) |
037e8744 JB |
14585 | { |
14586 | do_vfp_nsyn_cvt (rs, flavour); | |
14587 | return; | |
14588 | } | |
14589 | ||
14590 | switch (rs) | |
14591 | { | |
14592 | case NS_DDI: | |
14593 | case NS_QQI: | |
14594 | { | |
35997600 NC |
14595 | unsigned immbits; |
14596 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
14597 | ||
037e8744 JB |
14598 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
14599 | return; | |
14600 | ||
14601 | /* Fixed-point conversion with #0 immediate is encoded as an | |
14602 | integer conversion. */ | |
14603 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
14604 | goto int_encode; | |
35997600 | 14605 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 14606 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
14607 | if (flavour != -1) |
14608 | inst.instruction |= enctab[flavour]; | |
14609 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14610 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14611 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14612 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14613 | inst.instruction |= neon_quad (rs) << 6; | |
14614 | inst.instruction |= 1 << 21; | |
14615 | inst.instruction |= immbits << 16; | |
14616 | ||
88714cb8 | 14617 | neon_dp_fixup (&inst); |
037e8744 JB |
14618 | } |
14619 | break; | |
14620 | ||
14621 | case NS_DD: | |
14622 | case NS_QQ: | |
14623 | int_encode: | |
14624 | { | |
14625 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
14626 | ||
88714cb8 | 14627 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
14628 | |
14629 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14630 | return; | |
14631 | ||
14632 | if (flavour != -1) | |
14633 | inst.instruction |= enctab[flavour]; | |
14634 | ||
14635 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14636 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14637 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14638 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14639 | inst.instruction |= neon_quad (rs) << 6; | |
14640 | inst.instruction |= 2 << 18; | |
14641 | ||
88714cb8 | 14642 | neon_dp_fixup (&inst); |
037e8744 JB |
14643 | } |
14644 | break; | |
14645 | ||
8e79c3df CM |
14646 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
14647 | case NS_QD: | |
14648 | case NS_DQ: | |
14649 | ||
14650 | if ((rs == NS_DQ) | |
14651 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
14652 | { | |
14653 | as_bad (_("operand size must match register width")); | |
14654 | break; | |
14655 | } | |
14656 | ||
14657 | if ((rs == NS_QD) | |
14658 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
14659 | { | |
14660 | as_bad (_("operand size must match register width")); | |
14661 | break; | |
14662 | } | |
14663 | ||
14664 | if (rs == NS_DQ) | |
14665 | inst.instruction = 0x3b60600; | |
14666 | else | |
14667 | inst.instruction = 0x3b60700; | |
14668 | ||
14669 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14670 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14671 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14672 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 14673 | neon_dp_fixup (&inst); |
8e79c3df CM |
14674 | break; |
14675 | ||
037e8744 JB |
14676 | default: |
14677 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
14678 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 14679 | } |
5287ad62 JB |
14680 | } |
14681 | ||
e3e535bc NC |
14682 | static void |
14683 | do_neon_cvtr (void) | |
14684 | { | |
14685 | do_neon_cvt_1 (FALSE); | |
14686 | } | |
14687 | ||
14688 | static void | |
14689 | do_neon_cvt (void) | |
14690 | { | |
14691 | do_neon_cvt_1 (TRUE); | |
14692 | } | |
14693 | ||
8e79c3df CM |
14694 | static void |
14695 | do_neon_cvtb (void) | |
14696 | { | |
14697 | inst.instruction = 0xeb20a40; | |
14698 | ||
14699 | /* The sizes are attached to the mnemonic. */ | |
14700 | if (inst.vectype.el[0].type != NT_invtype | |
14701 | && inst.vectype.el[0].size == 16) | |
14702 | inst.instruction |= 0x00010000; | |
14703 | ||
14704 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
14705 | else if (inst.operands[0].vectype.type != NT_invtype | |
14706 | && inst.operands[0].vectype.size == 16) | |
14707 | inst.instruction |= 0x00010000; | |
14708 | ||
14709 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
14710 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
14711 | do_vfp_cond_or_thumb (); | |
14712 | } | |
14713 | ||
14714 | ||
14715 | static void | |
14716 | do_neon_cvtt (void) | |
14717 | { | |
14718 | do_neon_cvtb (); | |
14719 | inst.instruction |= 0x80; | |
14720 | } | |
14721 | ||
5287ad62 JB |
14722 | static void |
14723 | neon_move_immediate (void) | |
14724 | { | |
037e8744 JB |
14725 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
14726 | struct neon_type_el et = neon_check_type (2, rs, | |
14727 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 14728 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 14729 | int op, cmode, float_p; |
5287ad62 | 14730 | |
037e8744 JB |
14731 | constraint (et.type == NT_invtype, |
14732 | _("operand size must be specified for immediate VMOV")); | |
14733 | ||
5287ad62 JB |
14734 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
14735 | op = (inst.instruction & (1 << 5)) != 0; | |
14736 | ||
14737 | immlo = inst.operands[1].imm; | |
14738 | if (inst.operands[1].regisimm) | |
14739 | immhi = inst.operands[1].reg; | |
14740 | ||
14741 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14742 | _("immediate has bits set outside the operand size")); | |
14743 | ||
c96612cc JB |
14744 | float_p = inst.operands[1].immisfloat; |
14745 | ||
14746 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14747 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14748 | { |
14749 | /* Invert relevant bits only. */ | |
14750 | neon_invert_size (&immlo, &immhi, et.size); | |
14751 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14752 | with one or the other; those cases are caught by | |
14753 | neon_cmode_for_move_imm. */ | |
14754 | op = !op; | |
c96612cc JB |
14755 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14756 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14757 | { |
dcbf9037 | 14758 | first_error (_("immediate out of range")); |
5287ad62 JB |
14759 | return; |
14760 | } | |
14761 | } | |
14762 | ||
14763 | inst.instruction &= ~(1 << 5); | |
14764 | inst.instruction |= op << 5; | |
14765 | ||
14766 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14767 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14768 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14769 | inst.instruction |= cmode << 8; |
14770 | ||
14771 | neon_write_immbits (immbits); | |
14772 | } | |
14773 | ||
14774 | static void | |
14775 | do_neon_mvn (void) | |
14776 | { | |
14777 | if (inst.operands[1].isreg) | |
14778 | { | |
037e8744 | 14779 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14780 | |
88714cb8 | 14781 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14782 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14783 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14784 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14785 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14786 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14787 | } |
14788 | else | |
14789 | { | |
88714cb8 | 14790 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14791 | neon_move_immediate (); |
14792 | } | |
14793 | ||
88714cb8 | 14794 | neon_dp_fixup (&inst); |
5287ad62 JB |
14795 | } |
14796 | ||
14797 | /* Encode instructions of form: | |
14798 | ||
14799 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14800 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14801 | |
14802 | static void | |
14803 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14804 | { | |
14805 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14806 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14807 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14808 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14809 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14810 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14811 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14812 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14813 | |
88714cb8 | 14814 | neon_dp_fixup (&inst); |
5287ad62 JB |
14815 | } |
14816 | ||
14817 | static void | |
14818 | do_neon_dyadic_long (void) | |
14819 | { | |
14820 | /* FIXME: Type checking for lengthening op. */ | |
14821 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14822 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14823 | neon_mixed_length (et, et.size); | |
14824 | } | |
14825 | ||
14826 | static void | |
14827 | do_neon_abal (void) | |
14828 | { | |
14829 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14830 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14831 | neon_mixed_length (et, et.size); | |
14832 | } | |
14833 | ||
14834 | static void | |
14835 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14836 | { | |
14837 | if (inst.operands[2].isscalar) | |
14838 | { | |
dcbf9037 JB |
14839 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14840 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14841 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14842 | neon_mul_mac (et, et.type == NT_unsigned); |
14843 | } | |
14844 | else | |
14845 | { | |
14846 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14847 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14848 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14849 | neon_mixed_length (et, et.size); |
14850 | } | |
14851 | } | |
14852 | ||
14853 | static void | |
14854 | do_neon_mac_maybe_scalar_long (void) | |
14855 | { | |
14856 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14857 | } | |
14858 | ||
14859 | static void | |
14860 | do_neon_dyadic_wide (void) | |
14861 | { | |
14862 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14863 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14864 | neon_mixed_length (et, et.size); | |
14865 | } | |
14866 | ||
14867 | static void | |
14868 | do_neon_dyadic_narrow (void) | |
14869 | { | |
14870 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14871 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14872 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14873 | so force the operand type to integer. */ | |
14874 | et.type = NT_integer; | |
5287ad62 JB |
14875 | neon_mixed_length (et, et.size / 2); |
14876 | } | |
14877 | ||
14878 | static void | |
14879 | do_neon_mul_sat_scalar_long (void) | |
14880 | { | |
14881 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14882 | } | |
14883 | ||
14884 | static void | |
14885 | do_neon_vmull (void) | |
14886 | { | |
14887 | if (inst.operands[2].isscalar) | |
14888 | do_neon_mac_maybe_scalar_long (); | |
14889 | else | |
14890 | { | |
14891 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14892 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14893 | if (et.type == NT_poly) | |
88714cb8 | 14894 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14895 | else |
88714cb8 | 14896 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14897 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14898 | zero. Should be OK as-is. */ | |
14899 | neon_mixed_length (et, et.size); | |
14900 | } | |
14901 | } | |
14902 | ||
14903 | static void | |
14904 | do_neon_ext (void) | |
14905 | { | |
037e8744 | 14906 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14907 | struct neon_type_el et = neon_check_type (3, rs, |
14908 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14909 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14910 | |
14911 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14912 | _("shift out of range")); | |
5287ad62 JB |
14913 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14914 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14915 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14916 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14917 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14918 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14919 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14920 | inst.instruction |= imm << 8; |
5f4273c7 | 14921 | |
88714cb8 | 14922 | neon_dp_fixup (&inst); |
5287ad62 JB |
14923 | } |
14924 | ||
14925 | static void | |
14926 | do_neon_rev (void) | |
14927 | { | |
037e8744 | 14928 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14929 | struct neon_type_el et = neon_check_type (2, rs, |
14930 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14931 | unsigned op = (inst.instruction >> 7) & 3; | |
14932 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14933 | extract it here to check the elements to be reversed are smaller. | |
14934 | Otherwise we'd get a reserved instruction. */ | |
14935 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14936 | gas_assert (elsize != 0); |
5287ad62 JB |
14937 | constraint (et.size >= elsize, |
14938 | _("elements must be smaller than reversal region")); | |
037e8744 | 14939 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14940 | } |
14941 | ||
14942 | static void | |
14943 | do_neon_dup (void) | |
14944 | { | |
14945 | if (inst.operands[1].isscalar) | |
14946 | { | |
037e8744 | 14947 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14948 | struct neon_type_el et = neon_check_type (2, rs, |
14949 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14950 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14951 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14952 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14953 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14954 | |
14955 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14956 | return; | |
14957 | ||
88714cb8 | 14958 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14959 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14960 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14961 | inst.instruction |= LOW4 (dm); | |
14962 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14963 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14964 | inst.instruction |= x << 17; |
14965 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14966 | |
88714cb8 | 14967 | neon_dp_fixup (&inst); |
5287ad62 JB |
14968 | } |
14969 | else | |
14970 | { | |
037e8744 JB |
14971 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14972 | struct neon_type_el et = neon_check_type (2, rs, | |
14973 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14974 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14975 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14976 | switch (et.size) |
14977 | { | |
14978 | case 8: inst.instruction |= 0x400000; break; | |
14979 | case 16: inst.instruction |= 0x000020; break; | |
14980 | case 32: inst.instruction |= 0x000000; break; | |
14981 | default: break; | |
14982 | } | |
14983 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14984 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14985 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14986 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14987 | /* The encoding for this instruction is identical for the ARM and Thumb |
14988 | variants, except for the condition field. */ | |
037e8744 | 14989 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14990 | } |
14991 | } | |
14992 | ||
14993 | /* VMOV has particularly many variations. It can be one of: | |
14994 | 0. VMOV<c><q> <Qd>, <Qm> | |
14995 | 1. VMOV<c><q> <Dd>, <Dm> | |
14996 | (Register operations, which are VORR with Rm = Rn.) | |
14997 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14998 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14999 | (Immediate loads.) | |
15000 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
15001 | (ARM register to scalar.) | |
15002 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
15003 | (Two ARM registers to vector.) | |
15004 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
15005 | (Scalar to ARM register.) | |
15006 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
15007 | (Vector to two ARM registers.) | |
037e8744 JB |
15008 | 8. VMOV.F32 <Sd>, <Sm> |
15009 | 9. VMOV.F64 <Dd>, <Dm> | |
15010 | (VFP register moves.) | |
15011 | 10. VMOV.F32 <Sd>, #imm | |
15012 | 11. VMOV.F64 <Dd>, #imm | |
15013 | (VFP float immediate load.) | |
15014 | 12. VMOV <Rd>, <Sm> | |
15015 | (VFP single to ARM reg.) | |
15016 | 13. VMOV <Sd>, <Rm> | |
15017 | (ARM reg to VFP single.) | |
15018 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
15019 | (Two ARM regs to two VFP singles.) | |
15020 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
15021 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 15022 | |
037e8744 JB |
15023 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
15024 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 15025 | |
5287ad62 | 15026 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 15027 | |
b7fc2769 JB |
15028 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
15029 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 15030 | |
5287ad62 | 15031 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 15032 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
15033 | |
15034 | static void | |
15035 | do_neon_mov (void) | |
15036 | { | |
037e8744 JB |
15037 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
15038 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
15039 | NS_NULL); | |
15040 | struct neon_type_el et; | |
15041 | const char *ldconst = 0; | |
5287ad62 | 15042 | |
037e8744 | 15043 | switch (rs) |
5287ad62 | 15044 | { |
037e8744 JB |
15045 | case NS_DD: /* case 1/9. */ |
15046 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15047 | /* It is not an error here if no type is given. */ | |
15048 | inst.error = NULL; | |
15049 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 15050 | { |
037e8744 JB |
15051 | do_vfp_nsyn_opcode ("fcpyd"); |
15052 | break; | |
5287ad62 | 15053 | } |
037e8744 | 15054 | /* fall through. */ |
5287ad62 | 15055 | |
037e8744 JB |
15056 | case NS_QQ: /* case 0/1. */ |
15057 | { | |
15058 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15059 | return; | |
15060 | /* The architecture manual I have doesn't explicitly state which | |
15061 | value the U bit should have for register->register moves, but | |
15062 | the equivalent VORR instruction has U = 0, so do that. */ | |
15063 | inst.instruction = 0x0200110; | |
15064 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15065 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15066 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
15067 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
15068 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15069 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15070 | inst.instruction |= neon_quad (rs) << 6; | |
15071 | ||
88714cb8 | 15072 | neon_dp_fixup (&inst); |
037e8744 JB |
15073 | } |
15074 | break; | |
5f4273c7 | 15075 | |
037e8744 JB |
15076 | case NS_DI: /* case 3/11. */ |
15077 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
15078 | inst.error = NULL; | |
15079 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 15080 | { |
037e8744 JB |
15081 | /* case 11 (fconstd). */ |
15082 | ldconst = "fconstd"; | |
15083 | goto encode_fconstd; | |
5287ad62 | 15084 | } |
037e8744 JB |
15085 | /* fall through. */ |
15086 | ||
15087 | case NS_QI: /* case 2/3. */ | |
15088 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
15089 | return; | |
15090 | inst.instruction = 0x0800010; | |
15091 | neon_move_immediate (); | |
88714cb8 | 15092 | neon_dp_fixup (&inst); |
5287ad62 | 15093 | break; |
5f4273c7 | 15094 | |
037e8744 JB |
15095 | case NS_SR: /* case 4. */ |
15096 | { | |
15097 | unsigned bcdebits = 0; | |
91d6fa6a | 15098 | int logsize; |
037e8744 JB |
15099 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
15100 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
15101 | ||
91d6fa6a NC |
15102 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
15103 | logsize = neon_logbits (et.size); | |
15104 | ||
037e8744 JB |
15105 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
15106 | _(BAD_FPU)); | |
15107 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15108 | && et.size != 32, _(BAD_FPU)); | |
15109 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15110 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15111 | ||
15112 | switch (et.size) | |
15113 | { | |
15114 | case 8: bcdebits = 0x8; break; | |
15115 | case 16: bcdebits = 0x1; break; | |
15116 | case 32: bcdebits = 0x0; break; | |
15117 | default: ; | |
15118 | } | |
15119 | ||
15120 | bcdebits |= x << logsize; | |
15121 | ||
15122 | inst.instruction = 0xe000b10; | |
15123 | do_vfp_cond_or_thumb (); | |
15124 | inst.instruction |= LOW4 (dn) << 16; | |
15125 | inst.instruction |= HI1 (dn) << 7; | |
15126 | inst.instruction |= inst.operands[1].reg << 12; | |
15127 | inst.instruction |= (bcdebits & 3) << 5; | |
15128 | inst.instruction |= (bcdebits >> 2) << 21; | |
15129 | } | |
15130 | break; | |
5f4273c7 | 15131 | |
037e8744 | 15132 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 15133 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 15134 | _(BAD_FPU)); |
b7fc2769 | 15135 | |
037e8744 JB |
15136 | inst.instruction = 0xc400b10; |
15137 | do_vfp_cond_or_thumb (); | |
15138 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
15139 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
15140 | inst.instruction |= inst.operands[1].reg << 12; | |
15141 | inst.instruction |= inst.operands[2].reg << 16; | |
15142 | break; | |
5f4273c7 | 15143 | |
037e8744 JB |
15144 | case NS_RS: /* case 6. */ |
15145 | { | |
91d6fa6a | 15146 | unsigned logsize; |
037e8744 JB |
15147 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
15148 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
15149 | unsigned abcdebits = 0; | |
15150 | ||
91d6fa6a NC |
15151 | et = neon_check_type (2, NS_NULL, |
15152 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
15153 | logsize = neon_logbits (et.size); | |
15154 | ||
037e8744 JB |
15155 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
15156 | _(BAD_FPU)); | |
15157 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
15158 | && et.size != 32, _(BAD_FPU)); | |
15159 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
15160 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
15161 | ||
15162 | switch (et.size) | |
15163 | { | |
15164 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
15165 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
15166 | case 32: abcdebits = 0x00; break; | |
15167 | default: ; | |
15168 | } | |
15169 | ||
15170 | abcdebits |= x << logsize; | |
15171 | inst.instruction = 0xe100b10; | |
15172 | do_vfp_cond_or_thumb (); | |
15173 | inst.instruction |= LOW4 (dn) << 16; | |
15174 | inst.instruction |= HI1 (dn) << 7; | |
15175 | inst.instruction |= inst.operands[0].reg << 12; | |
15176 | inst.instruction |= (abcdebits & 3) << 5; | |
15177 | inst.instruction |= (abcdebits >> 2) << 21; | |
15178 | } | |
15179 | break; | |
5f4273c7 | 15180 | |
037e8744 JB |
15181 | case NS_RRD: /* case 7 (fmrrd). */ |
15182 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
15183 | _(BAD_FPU)); | |
15184 | ||
15185 | inst.instruction = 0xc500b10; | |
15186 | do_vfp_cond_or_thumb (); | |
15187 | inst.instruction |= inst.operands[0].reg << 12; | |
15188 | inst.instruction |= inst.operands[1].reg << 16; | |
15189 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15190 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15191 | break; | |
5f4273c7 | 15192 | |
037e8744 JB |
15193 | case NS_FF: /* case 8 (fcpys). */ |
15194 | do_vfp_nsyn_opcode ("fcpys"); | |
15195 | break; | |
5f4273c7 | 15196 | |
037e8744 JB |
15197 | case NS_FI: /* case 10 (fconsts). */ |
15198 | ldconst = "fconsts"; | |
15199 | encode_fconstd: | |
15200 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 15201 | { |
037e8744 JB |
15202 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
15203 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
15204 | } |
15205 | else | |
037e8744 JB |
15206 | first_error (_("immediate out of range")); |
15207 | break; | |
5f4273c7 | 15208 | |
037e8744 JB |
15209 | case NS_RF: /* case 12 (fmrs). */ |
15210 | do_vfp_nsyn_opcode ("fmrs"); | |
15211 | break; | |
5f4273c7 | 15212 | |
037e8744 JB |
15213 | case NS_FR: /* case 13 (fmsr). */ |
15214 | do_vfp_nsyn_opcode ("fmsr"); | |
15215 | break; | |
5f4273c7 | 15216 | |
037e8744 JB |
15217 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
15218 | (one of which is a list), but we have parsed four. Do some fiddling to | |
15219 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
15220 | expect. */ | |
15221 | case NS_RRFF: /* case 14 (fmrrs). */ | |
15222 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
15223 | _("VFP registers must be adjacent")); | |
15224 | inst.operands[2].imm = 2; | |
15225 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15226 | do_vfp_nsyn_opcode ("fmrrs"); | |
15227 | break; | |
5f4273c7 | 15228 | |
037e8744 JB |
15229 | case NS_FFRR: /* case 15 (fmsrr). */ |
15230 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
15231 | _("VFP registers must be adjacent")); | |
15232 | inst.operands[1] = inst.operands[2]; | |
15233 | inst.operands[2] = inst.operands[3]; | |
15234 | inst.operands[0].imm = 2; | |
15235 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15236 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 15237 | break; |
5f4273c7 | 15238 | |
5287ad62 JB |
15239 | default: |
15240 | abort (); | |
15241 | } | |
15242 | } | |
15243 | ||
15244 | static void | |
15245 | do_neon_rshift_round_imm (void) | |
15246 | { | |
037e8744 | 15247 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15248 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
15249 | int imm = inst.operands[2].imm; | |
15250 | ||
15251 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
15252 | if (imm == 0) | |
15253 | { | |
15254 | inst.operands[2].present = 0; | |
15255 | do_neon_mov (); | |
15256 | return; | |
15257 | } | |
15258 | ||
15259 | constraint (imm < 1 || (unsigned)imm > et.size, | |
15260 | _("immediate out of range for shift")); | |
037e8744 | 15261 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
15262 | et.size - imm); |
15263 | } | |
15264 | ||
15265 | static void | |
15266 | do_neon_movl (void) | |
15267 | { | |
15268 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
15269 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15270 | unsigned sizebits = et.size >> 3; | |
15271 | inst.instruction |= sizebits << 19; | |
15272 | neon_two_same (0, et.type == NT_unsigned, -1); | |
15273 | } | |
15274 | ||
15275 | static void | |
15276 | do_neon_trn (void) | |
15277 | { | |
037e8744 | 15278 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15279 | struct neon_type_el et = neon_check_type (2, rs, |
15280 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 15281 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15282 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15283 | } |
15284 | ||
15285 | static void | |
15286 | do_neon_zip_uzp (void) | |
15287 | { | |
037e8744 | 15288 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15289 | struct neon_type_el et = neon_check_type (2, rs, |
15290 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15291 | if (rs == NS_DD && et.size == 32) | |
15292 | { | |
15293 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
15294 | inst.instruction = N_MNEM_vtrn; | |
15295 | do_neon_trn (); | |
15296 | return; | |
15297 | } | |
037e8744 | 15298 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15299 | } |
15300 | ||
15301 | static void | |
15302 | do_neon_sat_abs_neg (void) | |
15303 | { | |
037e8744 | 15304 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15305 | struct neon_type_el et = neon_check_type (2, rs, |
15306 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15307 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15308 | } |
15309 | ||
15310 | static void | |
15311 | do_neon_pair_long (void) | |
15312 | { | |
037e8744 | 15313 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15314 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
15315 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
15316 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 15317 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15318 | } |
15319 | ||
15320 | static void | |
15321 | do_neon_recip_est (void) | |
15322 | { | |
037e8744 | 15323 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15324 | struct neon_type_el et = neon_check_type (2, rs, |
15325 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
15326 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 15327 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15328 | } |
15329 | ||
15330 | static void | |
15331 | do_neon_cls (void) | |
15332 | { | |
037e8744 | 15333 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15334 | struct neon_type_el et = neon_check_type (2, rs, |
15335 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15336 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15337 | } |
15338 | ||
15339 | static void | |
15340 | do_neon_clz (void) | |
15341 | { | |
037e8744 | 15342 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15343 | struct neon_type_el et = neon_check_type (2, rs, |
15344 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 15345 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15346 | } |
15347 | ||
15348 | static void | |
15349 | do_neon_cnt (void) | |
15350 | { | |
037e8744 | 15351 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15352 | struct neon_type_el et = neon_check_type (2, rs, |
15353 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 15354 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15355 | } |
15356 | ||
15357 | static void | |
15358 | do_neon_swp (void) | |
15359 | { | |
037e8744 JB |
15360 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
15361 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
15362 | } |
15363 | ||
15364 | static void | |
15365 | do_neon_tbl_tbx (void) | |
15366 | { | |
15367 | unsigned listlenbits; | |
dcbf9037 | 15368 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 15369 | |
5287ad62 JB |
15370 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
15371 | { | |
dcbf9037 | 15372 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
15373 | return; |
15374 | } | |
5f4273c7 | 15375 | |
5287ad62 JB |
15376 | listlenbits = inst.operands[1].imm - 1; |
15377 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15378 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15379 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15380 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15381 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15382 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15383 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 15384 | |
88714cb8 | 15385 | neon_dp_fixup (&inst); |
5287ad62 JB |
15386 | } |
15387 | ||
15388 | static void | |
15389 | do_neon_ldm_stm (void) | |
15390 | { | |
15391 | /* P, U and L bits are part of bitmask. */ | |
15392 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
15393 | unsigned offsetbits = inst.operands[1].imm * 2; | |
15394 | ||
037e8744 JB |
15395 | if (inst.operands[1].issingle) |
15396 | { | |
15397 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
15398 | return; | |
15399 | } | |
15400 | ||
5287ad62 JB |
15401 | constraint (is_dbmode && !inst.operands[0].writeback, |
15402 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
15403 | ||
15404 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
15405 | _("register list must contain at least 1 and at most 16 " | |
15406 | "registers")); | |
15407 | ||
15408 | inst.instruction |= inst.operands[0].reg << 16; | |
15409 | inst.instruction |= inst.operands[0].writeback << 21; | |
15410 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
15411 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
15412 | ||
15413 | inst.instruction |= offsetbits; | |
5f4273c7 | 15414 | |
037e8744 | 15415 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15416 | } |
15417 | ||
15418 | static void | |
15419 | do_neon_ldr_str (void) | |
15420 | { | |
5287ad62 | 15421 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 15422 | |
6844b2c2 MGD |
15423 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
15424 | And is UNPREDICTABLE in thumb mode. */ | |
fa94de6b | 15425 | if (!is_ldr |
6844b2c2 MGD |
15426 | && inst.operands[1].reg == REG_PC |
15427 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
15428 | { | |
15429 | if (!thumb_mode && warn_on_deprecated) | |
15430 | as_warn (_("Use of PC here is deprecated")); | |
15431 | else | |
15432 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
15433 | } | |
15434 | ||
037e8744 JB |
15435 | if (inst.operands[0].issingle) |
15436 | { | |
cd2f129f JB |
15437 | if (is_ldr) |
15438 | do_vfp_nsyn_opcode ("flds"); | |
15439 | else | |
15440 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
15441 | } |
15442 | else | |
5287ad62 | 15443 | { |
cd2f129f JB |
15444 | if (is_ldr) |
15445 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 15446 | else |
cd2f129f | 15447 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 15448 | } |
5287ad62 JB |
15449 | } |
15450 | ||
15451 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
15452 | instructions. */ | |
15453 | ||
15454 | static void | |
15455 | do_neon_ld_st_interleave (void) | |
15456 | { | |
037e8744 | 15457 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
15458 | N_8 | N_16 | N_32 | N_64); |
15459 | unsigned alignbits = 0; | |
15460 | unsigned idx; | |
15461 | /* The bits in this table go: | |
15462 | 0: register stride of one (0) or two (1) | |
15463 | 1,2: register list length, minus one (1, 2, 3, 4). | |
15464 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
15465 | We use -1 for invalid entries. */ | |
15466 | const int typetable[] = | |
15467 | { | |
15468 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
15469 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
15470 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
15471 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
15472 | }; | |
15473 | int typebits; | |
15474 | ||
dcbf9037 JB |
15475 | if (et.type == NT_invtype) |
15476 | return; | |
15477 | ||
5287ad62 JB |
15478 | if (inst.operands[1].immisalign) |
15479 | switch (inst.operands[1].imm >> 8) | |
15480 | { | |
15481 | case 64: alignbits = 1; break; | |
15482 | case 128: | |
e23c0ad8 JZ |
15483 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
15484 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
15485 | goto bad_alignment; |
15486 | alignbits = 2; | |
15487 | break; | |
15488 | case 256: | |
e23c0ad8 | 15489 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
15490 | goto bad_alignment; |
15491 | alignbits = 3; | |
15492 | break; | |
15493 | default: | |
15494 | bad_alignment: | |
dcbf9037 | 15495 | first_error (_("bad alignment")); |
5287ad62 JB |
15496 | return; |
15497 | } | |
15498 | ||
15499 | inst.instruction |= alignbits << 4; | |
15500 | inst.instruction |= neon_logbits (et.size) << 6; | |
15501 | ||
15502 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
15503 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
15504 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
15505 | up the right value for "type" in a table based on this value and the given | |
15506 | list style, then stick it back. */ | |
15507 | idx = ((inst.operands[0].imm >> 4) & 7) | |
15508 | | (((inst.instruction >> 8) & 3) << 3); | |
15509 | ||
15510 | typebits = typetable[idx]; | |
5f4273c7 | 15511 | |
5287ad62 JB |
15512 | constraint (typebits == -1, _("bad list type for instruction")); |
15513 | ||
15514 | inst.instruction &= ~0xf00; | |
15515 | inst.instruction |= typebits << 8; | |
15516 | } | |
15517 | ||
15518 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
15519 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
15520 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
15521 | values, terminated with -1. */ | |
15522 | ||
15523 | static int | |
15524 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
15525 | { | |
15526 | va_list ap; | |
15527 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 15528 | |
5287ad62 JB |
15529 | if (!inst.operands[1].immisalign) |
15530 | { | |
15531 | *do_align = 0; | |
15532 | return SUCCESS; | |
15533 | } | |
5f4273c7 | 15534 | |
5287ad62 JB |
15535 | va_start (ap, do_align); |
15536 | ||
15537 | do | |
15538 | { | |
15539 | thissize = va_arg (ap, int); | |
15540 | if (thissize == -1) | |
15541 | break; | |
15542 | thisalign = va_arg (ap, int); | |
15543 | ||
15544 | if (size == thissize && align == thisalign) | |
15545 | result = SUCCESS; | |
15546 | } | |
15547 | while (result != SUCCESS); | |
15548 | ||
15549 | va_end (ap); | |
15550 | ||
15551 | if (result == SUCCESS) | |
15552 | *do_align = 1; | |
15553 | else | |
dcbf9037 | 15554 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 15555 | |
5287ad62 JB |
15556 | return result; |
15557 | } | |
15558 | ||
15559 | static void | |
15560 | do_neon_ld_st_lane (void) | |
15561 | { | |
037e8744 | 15562 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15563 | int align_good, do_align = 0; |
15564 | int logsize = neon_logbits (et.size); | |
15565 | int align = inst.operands[1].imm >> 8; | |
15566 | int n = (inst.instruction >> 8) & 3; | |
15567 | int max_el = 64 / et.size; | |
5f4273c7 | 15568 | |
dcbf9037 JB |
15569 | if (et.type == NT_invtype) |
15570 | return; | |
5f4273c7 | 15571 | |
5287ad62 JB |
15572 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
15573 | _("bad list length")); | |
15574 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
15575 | _("scalar index out of range")); | |
15576 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
15577 | && et.size == 8, | |
15578 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 15579 | |
5287ad62 JB |
15580 | switch (n) |
15581 | { | |
15582 | case 0: /* VLD1 / VST1. */ | |
15583 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
15584 | 32, 32, -1); | |
15585 | if (align_good == FAIL) | |
15586 | return; | |
15587 | if (do_align) | |
15588 | { | |
15589 | unsigned alignbits = 0; | |
15590 | switch (et.size) | |
15591 | { | |
15592 | case 16: alignbits = 0x1; break; | |
15593 | case 32: alignbits = 0x3; break; | |
15594 | default: ; | |
15595 | } | |
15596 | inst.instruction |= alignbits << 4; | |
15597 | } | |
15598 | break; | |
15599 | ||
15600 | case 1: /* VLD2 / VST2. */ | |
15601 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
15602 | 32, 64, -1); | |
15603 | if (align_good == FAIL) | |
15604 | return; | |
15605 | if (do_align) | |
15606 | inst.instruction |= 1 << 4; | |
15607 | break; | |
15608 | ||
15609 | case 2: /* VLD3 / VST3. */ | |
15610 | constraint (inst.operands[1].immisalign, | |
15611 | _("can't use alignment with this instruction")); | |
15612 | break; | |
15613 | ||
15614 | case 3: /* VLD4 / VST4. */ | |
15615 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15616 | 16, 64, 32, 64, 32, 128, -1); | |
15617 | if (align_good == FAIL) | |
15618 | return; | |
15619 | if (do_align) | |
15620 | { | |
15621 | unsigned alignbits = 0; | |
15622 | switch (et.size) | |
15623 | { | |
15624 | case 8: alignbits = 0x1; break; | |
15625 | case 16: alignbits = 0x1; break; | |
15626 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
15627 | default: ; | |
15628 | } | |
15629 | inst.instruction |= alignbits << 4; | |
15630 | } | |
15631 | break; | |
15632 | ||
15633 | default: ; | |
15634 | } | |
15635 | ||
15636 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
15637 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15638 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 15639 | |
5287ad62 JB |
15640 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
15641 | inst.instruction |= logsize << 10; | |
15642 | } | |
15643 | ||
15644 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
15645 | ||
15646 | static void | |
15647 | do_neon_ld_dup (void) | |
15648 | { | |
037e8744 | 15649 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15650 | int align_good, do_align = 0; |
15651 | ||
dcbf9037 JB |
15652 | if (et.type == NT_invtype) |
15653 | return; | |
15654 | ||
5287ad62 JB |
15655 | switch ((inst.instruction >> 8) & 3) |
15656 | { | |
15657 | case 0: /* VLD1. */ | |
9c2799c2 | 15658 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
15659 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
15660 | &do_align, 16, 16, 32, 32, -1); | |
15661 | if (align_good == FAIL) | |
15662 | return; | |
15663 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
15664 | { | |
15665 | case 1: break; | |
15666 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 15667 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
15668 | } |
15669 | inst.instruction |= neon_logbits (et.size) << 6; | |
15670 | break; | |
15671 | ||
15672 | case 1: /* VLD2. */ | |
15673 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
15674 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
15675 | if (align_good == FAIL) | |
15676 | return; | |
15677 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
15678 | _("bad list length")); | |
15679 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15680 | inst.instruction |= 1 << 5; | |
15681 | inst.instruction |= neon_logbits (et.size) << 6; | |
15682 | break; | |
15683 | ||
15684 | case 2: /* VLD3. */ | |
15685 | constraint (inst.operands[1].immisalign, | |
15686 | _("can't use alignment with this instruction")); | |
15687 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
15688 | _("bad list length")); | |
15689 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15690 | inst.instruction |= 1 << 5; | |
15691 | inst.instruction |= neon_logbits (et.size) << 6; | |
15692 | break; | |
15693 | ||
15694 | case 3: /* VLD4. */ | |
15695 | { | |
15696 | int align = inst.operands[1].imm >> 8; | |
15697 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15698 | 16, 64, 32, 64, 32, 128, -1); | |
15699 | if (align_good == FAIL) | |
15700 | return; | |
15701 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
15702 | _("bad list length")); | |
15703 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15704 | inst.instruction |= 1 << 5; | |
15705 | if (et.size == 32 && align == 128) | |
15706 | inst.instruction |= 0x3 << 6; | |
15707 | else | |
15708 | inst.instruction |= neon_logbits (et.size) << 6; | |
15709 | } | |
15710 | break; | |
15711 | ||
15712 | default: ; | |
15713 | } | |
15714 | ||
15715 | inst.instruction |= do_align << 4; | |
15716 | } | |
15717 | ||
15718 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
15719 | apart from bits [11:4]. */ | |
15720 | ||
15721 | static void | |
15722 | do_neon_ldx_stx (void) | |
15723 | { | |
b1a769ed DG |
15724 | if (inst.operands[1].isreg) |
15725 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
15726 | ||
5287ad62 JB |
15727 | switch (NEON_LANE (inst.operands[0].imm)) |
15728 | { | |
15729 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 15730 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
15731 | do_neon_ld_st_interleave (); |
15732 | break; | |
5f4273c7 | 15733 | |
5287ad62 | 15734 | case NEON_ALL_LANES: |
88714cb8 | 15735 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
15736 | do_neon_ld_dup (); |
15737 | break; | |
5f4273c7 | 15738 | |
5287ad62 | 15739 | default: |
88714cb8 | 15740 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
15741 | do_neon_ld_st_lane (); |
15742 | } | |
15743 | ||
15744 | /* L bit comes from bit mask. */ | |
15745 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15746 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15747 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 15748 | |
5287ad62 JB |
15749 | if (inst.operands[1].postind) |
15750 | { | |
15751 | int postreg = inst.operands[1].imm & 0xf; | |
15752 | constraint (!inst.operands[1].immisreg, | |
15753 | _("post-index must be a register")); | |
15754 | constraint (postreg == 0xd || postreg == 0xf, | |
15755 | _("bad register for post-index")); | |
15756 | inst.instruction |= postreg; | |
15757 | } | |
15758 | else if (inst.operands[1].writeback) | |
15759 | { | |
15760 | inst.instruction |= 0xd; | |
15761 | } | |
15762 | else | |
5f4273c7 NC |
15763 | inst.instruction |= 0xf; |
15764 | ||
5287ad62 JB |
15765 | if (thumb_mode) |
15766 | inst.instruction |= 0xf9000000; | |
15767 | else | |
15768 | inst.instruction |= 0xf4000000; | |
15769 | } | |
5287ad62 JB |
15770 | \f |
15771 | /* Overall per-instruction processing. */ | |
15772 | ||
15773 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15774 | This is so that we can handle symbols that are an arbitrary distance from | |
15775 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15776 | which returns part of an address in a form which will be valid for | |
15777 | a data instruction. We do this by pushing the expression into a symbol | |
15778 | in the expr_section, and creating a fix for that. */ | |
15779 | ||
15780 | static void | |
15781 | fix_new_arm (fragS * frag, | |
15782 | int where, | |
15783 | short int size, | |
15784 | expressionS * exp, | |
15785 | int pc_rel, | |
15786 | int reloc) | |
15787 | { | |
15788 | fixS * new_fix; | |
15789 | ||
15790 | switch (exp->X_op) | |
15791 | { | |
15792 | case O_constant: | |
6e7ce2cd PB |
15793 | if (pc_rel) |
15794 | { | |
15795 | /* Create an absolute valued symbol, so we have something to | |
15796 | refer to in the object file. Unfortunately for us, gas's | |
15797 | generic expression parsing will already have folded out | |
15798 | any use of .set foo/.type foo %function that may have | |
15799 | been used to set type information of the target location, | |
15800 | that's being specified symbolically. We have to presume | |
15801 | the user knows what they are doing. */ | |
15802 | char name[16 + 8]; | |
15803 | symbolS *symbol; | |
15804 | ||
15805 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
15806 | ||
15807 | symbol = symbol_find_or_make (name); | |
15808 | S_SET_SEGMENT (symbol, absolute_section); | |
15809 | symbol_set_frag (symbol, &zero_address_frag); | |
15810 | S_SET_VALUE (symbol, exp->X_add_number); | |
15811 | exp->X_op = O_symbol; | |
15812 | exp->X_add_symbol = symbol; | |
15813 | exp->X_add_number = 0; | |
15814 | } | |
15815 | /* FALLTHROUGH */ | |
5287ad62 JB |
15816 | case O_symbol: |
15817 | case O_add: | |
15818 | case O_subtract: | |
21d799b5 NC |
15819 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15820 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15821 | break; |
15822 | ||
15823 | default: | |
21d799b5 NC |
15824 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15825 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15826 | break; |
15827 | } | |
15828 | ||
15829 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15830 | instruction. */ | |
15831 | new_fix->tc_fix_data = thumb_mode; | |
15832 | } | |
15833 | ||
15834 | /* Create a frg for an instruction requiring relaxation. */ | |
15835 | static void | |
15836 | output_relax_insn (void) | |
15837 | { | |
15838 | char * to; | |
15839 | symbolS *sym; | |
0110f2b8 PB |
15840 | int offset; |
15841 | ||
6e1cb1a6 PB |
15842 | /* The size of the instruction is unknown, so tie the debug info to the |
15843 | start of the instruction. */ | |
15844 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15845 | |
0110f2b8 PB |
15846 | switch (inst.reloc.exp.X_op) |
15847 | { | |
15848 | case O_symbol: | |
15849 | sym = inst.reloc.exp.X_add_symbol; | |
15850 | offset = inst.reloc.exp.X_add_number; | |
15851 | break; | |
15852 | case O_constant: | |
15853 | sym = NULL; | |
15854 | offset = inst.reloc.exp.X_add_number; | |
15855 | break; | |
15856 | default: | |
15857 | sym = make_expr_symbol (&inst.reloc.exp); | |
15858 | offset = 0; | |
15859 | break; | |
15860 | } | |
15861 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15862 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15863 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15864 | } |
15865 | ||
15866 | /* Write a 32-bit thumb instruction to buf. */ | |
15867 | static void | |
15868 | put_thumb32_insn (char * buf, unsigned long insn) | |
15869 | { | |
15870 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15871 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15872 | } | |
15873 | ||
b99bd4ef | 15874 | static void |
c19d1205 | 15875 | output_inst (const char * str) |
b99bd4ef | 15876 | { |
c19d1205 | 15877 | char * to = NULL; |
b99bd4ef | 15878 | |
c19d1205 | 15879 | if (inst.error) |
b99bd4ef | 15880 | { |
c19d1205 | 15881 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15882 | return; |
15883 | } | |
5f4273c7 NC |
15884 | if (inst.relax) |
15885 | { | |
15886 | output_relax_insn (); | |
0110f2b8 | 15887 | return; |
5f4273c7 | 15888 | } |
c19d1205 ZW |
15889 | if (inst.size == 0) |
15890 | return; | |
b99bd4ef | 15891 | |
c19d1205 | 15892 | to = frag_more (inst.size); |
8dc2430f NC |
15893 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15894 | what type of NOP padding to use, if necessary. We override any previous | |
15895 | setting so that if the mode has changed then the NOPS that we use will | |
15896 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15897 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15898 | |
15899 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15900 | { |
9c2799c2 | 15901 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15902 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15903 | } |
c19d1205 | 15904 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15905 | { |
9c2799c2 | 15906 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15907 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15908 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15909 | } |
c19d1205 ZW |
15910 | else |
15911 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15912 | |
c19d1205 ZW |
15913 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15914 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15915 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15916 | inst.reloc.type); | |
b99bd4ef | 15917 | |
c19d1205 | 15918 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15919 | } |
b99bd4ef | 15920 | |
e07e6e58 NC |
15921 | static char * |
15922 | output_it_inst (int cond, int mask, char * to) | |
15923 | { | |
15924 | unsigned long instruction = 0xbf00; | |
15925 | ||
15926 | mask &= 0xf; | |
15927 | instruction |= mask; | |
15928 | instruction |= cond << 4; | |
15929 | ||
15930 | if (to == NULL) | |
15931 | { | |
15932 | to = frag_more (2); | |
15933 | #ifdef OBJ_ELF | |
15934 | dwarf2_emit_insn (2); | |
15935 | #endif | |
15936 | } | |
15937 | ||
15938 | md_number_to_chars (to, instruction, 2); | |
15939 | ||
15940 | return to; | |
15941 | } | |
15942 | ||
c19d1205 ZW |
15943 | /* Tag values used in struct asm_opcode's tag field. */ |
15944 | enum opcode_tag | |
15945 | { | |
15946 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15947 | The ARM condition field is still 0xE. */ | |
15948 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15949 | and carries 0xF in its ARM condition field. */ | |
15950 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15951 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15952 | suffix, others place 0xF where the condition field | |
15953 | would be. */ | |
c19d1205 ZW |
15954 | OT_cinfix3, /* Instruction takes a conditional infix, |
15955 | beginning at character index 3. (In | |
15956 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15957 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15958 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15959 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15960 | character index 3, even in unified mode. Used for | |
15961 | legacy instructions where suffix and infix forms | |
15962 | may be ambiguous. */ | |
c19d1205 | 15963 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15964 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15965 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15966 | instruction that takes a conditional infix | |
15967 | at an unusual position. In unified mode, | |
15968 | this variant will accept a suffix. */ | |
15969 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15970 | are the conditional variants of instructions that | |
15971 | take conditional infixes in unusual positions. | |
15972 | The infix appears at character index | |
15973 | (tag - OT_odd_infix_0). These are not accepted | |
15974 | in unified mode. */ | |
15975 | }; | |
b99bd4ef | 15976 | |
c19d1205 ZW |
15977 | /* Subroutine of md_assemble, responsible for looking up the primary |
15978 | opcode from the mnemonic the user wrote. STR points to the | |
15979 | beginning of the mnemonic. | |
15980 | ||
15981 | This is not simply a hash table lookup, because of conditional | |
15982 | variants. Most instructions have conditional variants, which are | |
15983 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15984 | to encode each conditional variant as a literal string in the opcode | |
15985 | table, it would have approximately 20,000 entries. | |
15986 | ||
15987 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15988 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15989 | instructions take the affix as an infix, notably the s-variants of | |
15990 | the arithmetic instructions. Of those instructions, all but six | |
15991 | have the infix appear after the third character of the mnemonic. | |
15992 | ||
15993 | Accordingly, the algorithm for looking up primary opcodes given | |
15994 | an identifier is: | |
15995 | ||
15996 | 1. Look up the identifier in the opcode table. | |
15997 | If we find a match, go to step U. | |
15998 | ||
15999 | 2. Look up the last two characters of the identifier in the | |
16000 | conditions table. If we find a match, look up the first N-2 | |
16001 | characters of the identifier in the opcode table. If we | |
16002 | find a match, go to step CE. | |
16003 | ||
16004 | 3. Look up the fourth and fifth characters of the identifier in | |
16005 | the conditions table. If we find a match, extract those | |
16006 | characters from the identifier, and look up the remaining | |
16007 | characters in the opcode table. If we find a match, go | |
16008 | to step CM. | |
16009 | ||
16010 | 4. Fail. | |
16011 | ||
16012 | U. Examine the tag field of the opcode structure, in case this is | |
16013 | one of the six instructions with its conditional infix in an | |
16014 | unusual place. If it is, the tag tells us where to find the | |
16015 | infix; look it up in the conditions table and set inst.cond | |
16016 | accordingly. Otherwise, this is an unconditional instruction. | |
16017 | Again set inst.cond accordingly. Return the opcode structure. | |
16018 | ||
16019 | CE. Examine the tag field to make sure this is an instruction that | |
16020 | should receive a conditional suffix. If it is not, fail. | |
16021 | Otherwise, set inst.cond from the suffix we already looked up, | |
16022 | and return the opcode structure. | |
16023 | ||
16024 | CM. Examine the tag field to make sure this is an instruction that | |
16025 | should receive a conditional infix after the third character. | |
16026 | If it is not, fail. Otherwise, undo the edits to the current | |
16027 | line of input and proceed as for case CE. */ | |
16028 | ||
16029 | static const struct asm_opcode * | |
16030 | opcode_lookup (char **str) | |
16031 | { | |
16032 | char *end, *base; | |
16033 | char *affix; | |
16034 | const struct asm_opcode *opcode; | |
16035 | const struct asm_cond *cond; | |
e3cb604e | 16036 | char save[2]; |
c19d1205 ZW |
16037 | |
16038 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 16039 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 16040 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 16041 | if (*end == ' ' || *end == '.') |
c19d1205 | 16042 | break; |
b99bd4ef | 16043 | |
c19d1205 | 16044 | if (end == base) |
c921be7d | 16045 | return NULL; |
b99bd4ef | 16046 | |
5287ad62 | 16047 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 16048 | if (end[0] == '.') |
b99bd4ef | 16049 | { |
5287ad62 | 16050 | int offset = 2; |
5f4273c7 | 16051 | |
267d2029 JB |
16052 | /* The .w and .n suffixes are only valid if the unified syntax is in |
16053 | use. */ | |
16054 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 16055 | inst.size_req = 4; |
267d2029 | 16056 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
16057 | inst.size_req = 2; |
16058 | else | |
5287ad62 JB |
16059 | offset = 0; |
16060 | ||
16061 | inst.vectype.elems = 0; | |
16062 | ||
16063 | *str = end + offset; | |
b99bd4ef | 16064 | |
5f4273c7 | 16065 | if (end[offset] == '.') |
5287ad62 | 16066 | { |
267d2029 JB |
16067 | /* See if we have a Neon type suffix (possible in either unified or |
16068 | non-unified ARM syntax mode). */ | |
dcbf9037 | 16069 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 16070 | return NULL; |
5287ad62 JB |
16071 | } |
16072 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 16073 | return NULL; |
b99bd4ef | 16074 | } |
c19d1205 ZW |
16075 | else |
16076 | *str = end; | |
b99bd4ef | 16077 | |
c19d1205 | 16078 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
16079 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
16080 | end - base); | |
c19d1205 | 16081 | if (opcode) |
b99bd4ef | 16082 | { |
c19d1205 ZW |
16083 | /* step U */ |
16084 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 16085 | { |
c19d1205 ZW |
16086 | inst.cond = COND_ALWAYS; |
16087 | return opcode; | |
b99bd4ef | 16088 | } |
b99bd4ef | 16089 | |
278df34e | 16090 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
16091 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
16092 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 16093 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 16094 | gas_assert (cond); |
b99bd4ef | 16095 | |
c19d1205 ZW |
16096 | inst.cond = cond->value; |
16097 | return opcode; | |
16098 | } | |
b99bd4ef | 16099 | |
c19d1205 ZW |
16100 | /* Cannot have a conditional suffix on a mnemonic of less than two |
16101 | characters. */ | |
16102 | if (end - base < 3) | |
c921be7d | 16103 | return NULL; |
b99bd4ef | 16104 | |
c19d1205 ZW |
16105 | /* Look for suffixed mnemonic. */ |
16106 | affix = end - 2; | |
21d799b5 NC |
16107 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
16108 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
16109 | affix - base); | |
c19d1205 ZW |
16110 | if (opcode && cond) |
16111 | { | |
16112 | /* step CE */ | |
16113 | switch (opcode->tag) | |
16114 | { | |
e3cb604e PB |
16115 | case OT_cinfix3_legacy: |
16116 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
16117 | break; | |
16118 | ||
c19d1205 | 16119 | case OT_cinfix3: |
088fa78e | 16120 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
16121 | case OT_odd_infix_unc: |
16122 | if (!unified_syntax) | |
e3cb604e | 16123 | return 0; |
c19d1205 ZW |
16124 | /* else fall through */ |
16125 | ||
16126 | case OT_csuffix: | |
037e8744 | 16127 | case OT_csuffixF: |
c19d1205 ZW |
16128 | case OT_csuf_or_in3: |
16129 | inst.cond = cond->value; | |
16130 | return opcode; | |
16131 | ||
16132 | case OT_unconditional: | |
16133 | case OT_unconditionalF: | |
dfa9f0d5 | 16134 | if (thumb_mode) |
c921be7d | 16135 | inst.cond = cond->value; |
dfa9f0d5 PB |
16136 | else |
16137 | { | |
c921be7d | 16138 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
16139 | inst.error = BAD_COND; |
16140 | inst.cond = COND_ALWAYS; | |
16141 | } | |
c19d1205 | 16142 | return opcode; |
b99bd4ef | 16143 | |
c19d1205 | 16144 | default: |
c921be7d | 16145 | return NULL; |
c19d1205 ZW |
16146 | } |
16147 | } | |
b99bd4ef | 16148 | |
c19d1205 ZW |
16149 | /* Cannot have a usual-position infix on a mnemonic of less than |
16150 | six characters (five would be a suffix). */ | |
16151 | if (end - base < 6) | |
c921be7d | 16152 | return NULL; |
b99bd4ef | 16153 | |
c19d1205 ZW |
16154 | /* Look for infixed mnemonic in the usual position. */ |
16155 | affix = base + 3; | |
21d799b5 | 16156 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 16157 | if (!cond) |
c921be7d | 16158 | return NULL; |
e3cb604e PB |
16159 | |
16160 | memcpy (save, affix, 2); | |
16161 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
16162 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
16163 | (end - base) - 2); | |
e3cb604e PB |
16164 | memmove (affix + 2, affix, (end - affix) - 2); |
16165 | memcpy (affix, save, 2); | |
16166 | ||
088fa78e KH |
16167 | if (opcode |
16168 | && (opcode->tag == OT_cinfix3 | |
16169 | || opcode->tag == OT_cinfix3_deprecated | |
16170 | || opcode->tag == OT_csuf_or_in3 | |
16171 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 16172 | { |
c921be7d | 16173 | /* Step CM. */ |
278df34e | 16174 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
16175 | && (opcode->tag == OT_cinfix3 |
16176 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
16177 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
16178 | ||
16179 | inst.cond = cond->value; | |
16180 | return opcode; | |
b99bd4ef NC |
16181 | } |
16182 | ||
c921be7d | 16183 | return NULL; |
b99bd4ef NC |
16184 | } |
16185 | ||
e07e6e58 NC |
16186 | /* This function generates an initial IT instruction, leaving its block |
16187 | virtually open for the new instructions. Eventually, | |
16188 | the mask will be updated by now_it_add_mask () each time | |
16189 | a new instruction needs to be included in the IT block. | |
16190 | Finally, the block is closed with close_automatic_it_block (). | |
16191 | The block closure can be requested either from md_assemble (), | |
16192 | a tencode (), or due to a label hook. */ | |
16193 | ||
16194 | static void | |
16195 | new_automatic_it_block (int cond) | |
16196 | { | |
16197 | now_it.state = AUTOMATIC_IT_BLOCK; | |
16198 | now_it.mask = 0x18; | |
16199 | now_it.cc = cond; | |
16200 | now_it.block_length = 1; | |
cd000bff | 16201 | mapping_state (MAP_THUMB); |
e07e6e58 | 16202 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
5a01bb1d MGD |
16203 | now_it.warn_deprecated = FALSE; |
16204 | now_it.insn_cond = TRUE; | |
e07e6e58 NC |
16205 | } |
16206 | ||
16207 | /* Close an automatic IT block. | |
16208 | See comments in new_automatic_it_block (). */ | |
16209 | ||
16210 | static void | |
16211 | close_automatic_it_block (void) | |
16212 | { | |
16213 | now_it.mask = 0x10; | |
16214 | now_it.block_length = 0; | |
16215 | } | |
16216 | ||
16217 | /* Update the mask of the current automatically-generated IT | |
16218 | instruction. See comments in new_automatic_it_block (). */ | |
16219 | ||
16220 | static void | |
16221 | now_it_add_mask (int cond) | |
16222 | { | |
16223 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
16224 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
16225 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 16226 | const int resulting_bit = (cond & 1); |
c921be7d | 16227 | |
e07e6e58 NC |
16228 | now_it.mask &= 0xf; |
16229 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
16230 | resulting_bit, | |
16231 | (5 - now_it.block_length)); | |
16232 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
16233 | 1, | |
16234 | ((5 - now_it.block_length) - 1) ); | |
16235 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
16236 | ||
16237 | #undef CLEAR_BIT | |
16238 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
16239 | } |
16240 | ||
16241 | /* The IT blocks handling machinery is accessed through the these functions: | |
16242 | it_fsm_pre_encode () from md_assemble () | |
16243 | set_it_insn_type () optional, from the tencode functions | |
16244 | set_it_insn_type_last () ditto | |
16245 | in_it_block () ditto | |
16246 | it_fsm_post_encode () from md_assemble () | |
16247 | force_automatic_it_block_close () from label habdling functions | |
16248 | ||
16249 | Rationale: | |
16250 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
16251 | initializing the IT insn type with a generic initial value depending | |
16252 | on the inst.condition. | |
16253 | 2) During the tencode function, two things may happen: | |
16254 | a) The tencode function overrides the IT insn type by | |
16255 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
16256 | b) The tencode function queries the IT block state by | |
16257 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
16258 | ||
16259 | Both set_it_insn_type and in_it_block run the internal FSM state | |
16260 | handling function (handle_it_state), because: a) setting the IT insn | |
16261 | type may incur in an invalid state (exiting the function), | |
16262 | and b) querying the state requires the FSM to be updated. | |
16263 | Specifically we want to avoid creating an IT block for conditional | |
16264 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
16265 | determine whether an IT block is required until the tencode () routine | |
16266 | has decided what type of instruction this actually it. | |
16267 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
16268 | set_it_insn_type has to be called first. | |
16269 | ||
16270 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
16271 | determines the insn IT type depending on the inst.cond code. | |
16272 | When a tencode () routine encodes an instruction that can be | |
16273 | either outside an IT block, or, in the case of being inside, has to be | |
16274 | the last one, set_it_insn_type_last () will determine the proper | |
16275 | IT instruction type based on the inst.cond code. Otherwise, | |
16276 | set_it_insn_type can be called for overriding that logic or | |
16277 | for covering other cases. | |
16278 | ||
16279 | Calling handle_it_state () may not transition the IT block state to | |
16280 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
16281 | still queried. Instead, if the FSM determines that the state should | |
16282 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
16283 | after the tencode () function: that's what it_fsm_post_encode () does. | |
16284 | ||
16285 | Since in_it_block () calls the state handling function to get an | |
16286 | updated state, an error may occur (due to invalid insns combination). | |
16287 | In that case, inst.error is set. | |
16288 | Therefore, inst.error has to be checked after the execution of | |
16289 | the tencode () routine. | |
16290 | ||
16291 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
16292 | any pending state change (if any) that didn't take place in | |
16293 | handle_it_state () as explained above. */ | |
16294 | ||
16295 | static void | |
16296 | it_fsm_pre_encode (void) | |
16297 | { | |
16298 | if (inst.cond != COND_ALWAYS) | |
16299 | inst.it_insn_type = INSIDE_IT_INSN; | |
16300 | else | |
16301 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
16302 | ||
16303 | now_it.state_handled = 0; | |
16304 | } | |
16305 | ||
16306 | /* IT state FSM handling function. */ | |
16307 | ||
16308 | static int | |
16309 | handle_it_state (void) | |
16310 | { | |
16311 | now_it.state_handled = 1; | |
5a01bb1d | 16312 | now_it.insn_cond = FALSE; |
e07e6e58 NC |
16313 | |
16314 | switch (now_it.state) | |
16315 | { | |
16316 | case OUTSIDE_IT_BLOCK: | |
16317 | switch (inst.it_insn_type) | |
16318 | { | |
16319 | case OUTSIDE_IT_INSN: | |
16320 | break; | |
16321 | ||
16322 | case INSIDE_IT_INSN: | |
16323 | case INSIDE_IT_LAST_INSN: | |
16324 | if (thumb_mode == 0) | |
16325 | { | |
c921be7d | 16326 | if (unified_syntax |
e07e6e58 NC |
16327 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
16328 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
16329 | " for Thumb.")); | |
16330 | } | |
16331 | else | |
16332 | { | |
16333 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
16334 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
16335 | { | |
16336 | /* Automatically generate the IT instruction. */ | |
16337 | new_automatic_it_block (inst.cond); | |
16338 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
16339 | close_automatic_it_block (); | |
16340 | } | |
16341 | else | |
16342 | { | |
16343 | inst.error = BAD_OUT_IT; | |
16344 | return FAIL; | |
16345 | } | |
16346 | } | |
16347 | break; | |
16348 | ||
16349 | case IF_INSIDE_IT_LAST_INSN: | |
16350 | case NEUTRAL_IT_INSN: | |
16351 | break; | |
16352 | ||
16353 | case IT_INSN: | |
16354 | now_it.state = MANUAL_IT_BLOCK; | |
16355 | now_it.block_length = 0; | |
16356 | break; | |
16357 | } | |
16358 | break; | |
16359 | ||
16360 | case AUTOMATIC_IT_BLOCK: | |
16361 | /* Three things may happen now: | |
16362 | a) We should increment current it block size; | |
16363 | b) We should close current it block (closing insn or 4 insns); | |
16364 | c) We should close current it block and start a new one (due | |
16365 | to incompatible conditions or | |
16366 | 4 insns-length block reached). */ | |
16367 | ||
16368 | switch (inst.it_insn_type) | |
16369 | { | |
16370 | case OUTSIDE_IT_INSN: | |
16371 | /* The closure of the block shall happen immediatelly, | |
16372 | so any in_it_block () call reports the block as closed. */ | |
16373 | force_automatic_it_block_close (); | |
16374 | break; | |
16375 | ||
16376 | case INSIDE_IT_INSN: | |
16377 | case INSIDE_IT_LAST_INSN: | |
16378 | case IF_INSIDE_IT_LAST_INSN: | |
16379 | now_it.block_length++; | |
16380 | ||
16381 | if (now_it.block_length > 4 | |
16382 | || !now_it_compatible (inst.cond)) | |
16383 | { | |
16384 | force_automatic_it_block_close (); | |
16385 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
16386 | new_automatic_it_block (inst.cond); | |
16387 | } | |
16388 | else | |
16389 | { | |
5a01bb1d | 16390 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
16391 | now_it_add_mask (inst.cond); |
16392 | } | |
16393 | ||
16394 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
16395 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
16396 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
16397 | close_automatic_it_block (); | |
16398 | break; | |
16399 | ||
16400 | case NEUTRAL_IT_INSN: | |
16401 | now_it.block_length++; | |
5a01bb1d | 16402 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
16403 | |
16404 | if (now_it.block_length > 4) | |
16405 | force_automatic_it_block_close (); | |
16406 | else | |
16407 | now_it_add_mask (now_it.cc & 1); | |
16408 | break; | |
16409 | ||
16410 | case IT_INSN: | |
16411 | close_automatic_it_block (); | |
16412 | now_it.state = MANUAL_IT_BLOCK; | |
16413 | break; | |
16414 | } | |
16415 | break; | |
16416 | ||
16417 | case MANUAL_IT_BLOCK: | |
16418 | { | |
16419 | /* Check conditional suffixes. */ | |
16420 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
16421 | int is_last; | |
16422 | now_it.mask <<= 1; | |
16423 | now_it.mask &= 0x1f; | |
16424 | is_last = (now_it.mask == 0x10); | |
5a01bb1d | 16425 | now_it.insn_cond = TRUE; |
e07e6e58 NC |
16426 | |
16427 | switch (inst.it_insn_type) | |
16428 | { | |
16429 | case OUTSIDE_IT_INSN: | |
16430 | inst.error = BAD_NOT_IT; | |
16431 | return FAIL; | |
16432 | ||
16433 | case INSIDE_IT_INSN: | |
16434 | if (cond != inst.cond) | |
16435 | { | |
16436 | inst.error = BAD_IT_COND; | |
16437 | return FAIL; | |
16438 | } | |
16439 | break; | |
16440 | ||
16441 | case INSIDE_IT_LAST_INSN: | |
16442 | case IF_INSIDE_IT_LAST_INSN: | |
16443 | if (cond != inst.cond) | |
16444 | { | |
16445 | inst.error = BAD_IT_COND; | |
16446 | return FAIL; | |
16447 | } | |
16448 | if (!is_last) | |
16449 | { | |
16450 | inst.error = BAD_BRANCH; | |
16451 | return FAIL; | |
16452 | } | |
16453 | break; | |
16454 | ||
16455 | case NEUTRAL_IT_INSN: | |
16456 | /* The BKPT instruction is unconditional even in an IT block. */ | |
16457 | break; | |
16458 | ||
16459 | case IT_INSN: | |
16460 | inst.error = BAD_IT_IT; | |
16461 | return FAIL; | |
16462 | } | |
16463 | } | |
16464 | break; | |
16465 | } | |
16466 | ||
16467 | return SUCCESS; | |
16468 | } | |
16469 | ||
5a01bb1d MGD |
16470 | struct depr_insn_mask |
16471 | { | |
16472 | unsigned long pattern; | |
16473 | unsigned long mask; | |
16474 | const char* description; | |
16475 | }; | |
16476 | ||
16477 | /* List of 16-bit instruction patterns deprecated in an IT block in | |
16478 | ARMv8. */ | |
16479 | static const struct depr_insn_mask depr_it_insns[] = { | |
16480 | { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") }, | |
16481 | { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") }, | |
16482 | { 0xa000, 0xb800, N_("ADR") }, | |
16483 | { 0x4800, 0xf800, N_("Literal loads") }, | |
16484 | { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") }, | |
16485 | { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") }, | |
16486 | { 0, 0, NULL } | |
16487 | }; | |
16488 | ||
e07e6e58 NC |
16489 | static void |
16490 | it_fsm_post_encode (void) | |
16491 | { | |
16492 | int is_last; | |
16493 | ||
16494 | if (!now_it.state_handled) | |
16495 | handle_it_state (); | |
16496 | ||
5a01bb1d MGD |
16497 | if (now_it.insn_cond |
16498 | && !now_it.warn_deprecated | |
16499 | && warn_on_deprecated | |
16500 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) | |
16501 | { | |
16502 | if (inst.instruction >= 0x10000) | |
16503 | { | |
16504 | as_warn (_("it blocks containing wide Thumb instructions are " | |
16505 | "deprecated in ARMv8")); | |
16506 | now_it.warn_deprecated = TRUE; | |
16507 | } | |
16508 | else | |
16509 | { | |
16510 | const struct depr_insn_mask *p = depr_it_insns; | |
16511 | ||
16512 | while (p->mask != 0) | |
16513 | { | |
16514 | if ((inst.instruction & p->mask) == p->pattern) | |
16515 | { | |
16516 | as_warn (_("it blocks containing 16-bit Thumb intsructions " | |
16517 | "of the following class are deprecated in ARMv8: " | |
16518 | "%s"), p->description); | |
16519 | now_it.warn_deprecated = TRUE; | |
16520 | break; | |
16521 | } | |
16522 | ||
16523 | ++p; | |
16524 | } | |
16525 | } | |
16526 | ||
16527 | if (now_it.block_length > 1) | |
16528 | { | |
16529 | as_warn (_("it blocks of more than one conditional instruction are " | |
16530 | "deprecated in ARMv8")); | |
16531 | now_it.warn_deprecated = TRUE; | |
16532 | } | |
16533 | } | |
16534 | ||
e07e6e58 NC |
16535 | is_last = (now_it.mask == 0x10); |
16536 | if (is_last) | |
16537 | { | |
16538 | now_it.state = OUTSIDE_IT_BLOCK; | |
16539 | now_it.mask = 0; | |
16540 | } | |
16541 | } | |
16542 | ||
16543 | static void | |
16544 | force_automatic_it_block_close (void) | |
16545 | { | |
16546 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
16547 | { | |
16548 | close_automatic_it_block (); | |
16549 | now_it.state = OUTSIDE_IT_BLOCK; | |
16550 | now_it.mask = 0; | |
16551 | } | |
16552 | } | |
16553 | ||
16554 | static int | |
16555 | in_it_block (void) | |
16556 | { | |
16557 | if (!now_it.state_handled) | |
16558 | handle_it_state (); | |
16559 | ||
16560 | return now_it.state != OUTSIDE_IT_BLOCK; | |
16561 | } | |
16562 | ||
c19d1205 ZW |
16563 | void |
16564 | md_assemble (char *str) | |
b99bd4ef | 16565 | { |
c19d1205 ZW |
16566 | char *p = str; |
16567 | const struct asm_opcode * opcode; | |
b99bd4ef | 16568 | |
c19d1205 ZW |
16569 | /* Align the previous label if needed. */ |
16570 | if (last_label_seen != NULL) | |
b99bd4ef | 16571 | { |
c19d1205 ZW |
16572 | symbol_set_frag (last_label_seen, frag_now); |
16573 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
16574 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
16575 | } |
16576 | ||
c19d1205 ZW |
16577 | memset (&inst, '\0', sizeof (inst)); |
16578 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 16579 | |
c19d1205 ZW |
16580 | opcode = opcode_lookup (&p); |
16581 | if (!opcode) | |
b99bd4ef | 16582 | { |
c19d1205 | 16583 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 16584 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
16585 | if (! create_register_alias (str, p) |
16586 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 16587 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 16588 | |
b99bd4ef NC |
16589 | return; |
16590 | } | |
16591 | ||
278df34e | 16592 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
16593 | as_warn (_("s suffix on comparison instruction is deprecated")); |
16594 | ||
037e8744 JB |
16595 | /* The value which unconditional instructions should have in place of the |
16596 | condition field. */ | |
16597 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
16598 | ||
c19d1205 | 16599 | if (thumb_mode) |
b99bd4ef | 16600 | { |
e74cfd16 | 16601 | arm_feature_set variant; |
8f06b2d8 PB |
16602 | |
16603 | variant = cpu_variant; | |
16604 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
16605 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
16606 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 16607 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
16608 | if (!opcode->tvariant |
16609 | || (thumb_mode == 1 | |
16610 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 16611 | { |
bf3eeda7 | 16612 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
16613 | return; |
16614 | } | |
c19d1205 ZW |
16615 | if (inst.cond != COND_ALWAYS && !unified_syntax |
16616 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 16617 | { |
c19d1205 | 16618 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
16619 | return; |
16620 | } | |
16621 | ||
752d5da4 | 16622 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 16623 | { |
7e806470 | 16624 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
16625 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
16626 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
16627 | { | |
16628 | /* Two things are addressed here. | |
16629 | 1) Implicit require narrow instructions on Thumb-1. | |
16630 | This avoids relaxation accidentally introducing Thumb-2 | |
16631 | instructions. | |
16632 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
16633 | if (inst.size_req == 0) | |
16634 | inst.size_req = 2; | |
16635 | else if (inst.size_req == 4) | |
16636 | { | |
bf3eeda7 | 16637 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
16638 | return; |
16639 | } | |
16640 | } | |
076d447c PB |
16641 | } |
16642 | ||
c19d1205 ZW |
16643 | inst.instruction = opcode->tvalue; |
16644 | ||
5be8be5d | 16645 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
16646 | { |
16647 | /* Prepare the it_insn_type for those encodings that don't set | |
16648 | it. */ | |
16649 | it_fsm_pre_encode (); | |
c19d1205 | 16650 | |
e07e6e58 NC |
16651 | opcode->tencode (); |
16652 | ||
16653 | it_fsm_post_encode (); | |
16654 | } | |
e27ec89e | 16655 | |
0110f2b8 | 16656 | if (!(inst.error || inst.relax)) |
b99bd4ef | 16657 | { |
9c2799c2 | 16658 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
16659 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
16660 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 16661 | { |
c19d1205 | 16662 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
16663 | return; |
16664 | } | |
16665 | } | |
076d447c PB |
16666 | |
16667 | /* Something has gone badly wrong if we try to relax a fixed size | |
16668 | instruction. */ | |
9c2799c2 | 16669 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 16670 | |
e74cfd16 PB |
16671 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16672 | *opcode->tvariant); | |
ee065d83 | 16673 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 16674 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 16675 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 16676 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
16677 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
16678 | || inst.relax) | |
e07e6e58 NC |
16679 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
16680 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
16681 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16682 | arm_ext_v6t2); | |
cd000bff | 16683 | |
88714cb8 DG |
16684 | check_neon_suffixes; |
16685 | ||
cd000bff | 16686 | if (!inst.error) |
c877a2f2 NC |
16687 | { |
16688 | mapping_state (MAP_THUMB); | |
16689 | } | |
c19d1205 | 16690 | } |
3e9e4fcf | 16691 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 16692 | { |
845b51d6 PB |
16693 | bfd_boolean is_bx; |
16694 | ||
16695 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
16696 | is_bx = (opcode->aencode == do_bx); | |
16697 | ||
c19d1205 | 16698 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
16699 | if (!(is_bx && fix_v4bx) |
16700 | && !(opcode->avariant && | |
16701 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 16702 | { |
bf3eeda7 | 16703 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 16704 | return; |
b99bd4ef | 16705 | } |
c19d1205 | 16706 | if (inst.size_req) |
b99bd4ef | 16707 | { |
c19d1205 ZW |
16708 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
16709 | return; | |
b99bd4ef NC |
16710 | } |
16711 | ||
c19d1205 ZW |
16712 | inst.instruction = opcode->avalue; |
16713 | if (opcode->tag == OT_unconditionalF) | |
16714 | inst.instruction |= 0xF << 28; | |
16715 | else | |
16716 | inst.instruction |= inst.cond << 28; | |
16717 | inst.size = INSN_SIZE; | |
5be8be5d | 16718 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
16719 | { |
16720 | it_fsm_pre_encode (); | |
16721 | opcode->aencode (); | |
16722 | it_fsm_post_encode (); | |
16723 | } | |
ee065d83 PB |
16724 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
16725 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 16726 | if (is_bx) |
e74cfd16 | 16727 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 16728 | else |
e74cfd16 PB |
16729 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
16730 | *opcode->avariant); | |
88714cb8 DG |
16731 | |
16732 | check_neon_suffixes; | |
16733 | ||
cd000bff | 16734 | if (!inst.error) |
c877a2f2 NC |
16735 | { |
16736 | mapping_state (MAP_ARM); | |
16737 | } | |
b99bd4ef | 16738 | } |
3e9e4fcf JB |
16739 | else |
16740 | { | |
16741 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
16742 | "-- `%s'"), str); | |
16743 | return; | |
16744 | } | |
c19d1205 ZW |
16745 | output_inst (str); |
16746 | } | |
b99bd4ef | 16747 | |
e07e6e58 NC |
16748 | static void |
16749 | check_it_blocks_finished (void) | |
16750 | { | |
16751 | #ifdef OBJ_ELF | |
16752 | asection *sect; | |
16753 | ||
16754 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
16755 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
16756 | == MANUAL_IT_BLOCK) | |
16757 | { | |
16758 | as_warn (_("section '%s' finished with an open IT block."), | |
16759 | sect->name); | |
16760 | } | |
16761 | #else | |
16762 | if (now_it.state == MANUAL_IT_BLOCK) | |
16763 | as_warn (_("file finished with an open IT block.")); | |
16764 | #endif | |
16765 | } | |
16766 | ||
c19d1205 ZW |
16767 | /* Various frobbings of labels and their addresses. */ |
16768 | ||
16769 | void | |
16770 | arm_start_line_hook (void) | |
16771 | { | |
16772 | last_label_seen = NULL; | |
b99bd4ef NC |
16773 | } |
16774 | ||
c19d1205 ZW |
16775 | void |
16776 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 16777 | { |
c19d1205 | 16778 | last_label_seen = sym; |
b99bd4ef | 16779 | |
c19d1205 | 16780 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 16781 | |
c19d1205 ZW |
16782 | #if defined OBJ_COFF || defined OBJ_ELF |
16783 | ARM_SET_INTERWORK (sym, support_interwork); | |
16784 | #endif | |
b99bd4ef | 16785 | |
e07e6e58 NC |
16786 | force_automatic_it_block_close (); |
16787 | ||
5f4273c7 | 16788 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
16789 | as Thumb functions. This is because these labels, whilst |
16790 | they exist inside Thumb code, are not the entry points for | |
16791 | possible ARM->Thumb calls. Also, these labels can be used | |
16792 | as part of a computed goto or switch statement. eg gcc | |
16793 | can generate code that looks like this: | |
b99bd4ef | 16794 | |
c19d1205 ZW |
16795 | ldr r2, [pc, .Laaa] |
16796 | lsl r3, r3, #2 | |
16797 | ldr r2, [r3, r2] | |
16798 | mov pc, r2 | |
b99bd4ef | 16799 | |
c19d1205 ZW |
16800 | .Lbbb: .word .Lxxx |
16801 | .Lccc: .word .Lyyy | |
16802 | ..etc... | |
16803 | .Laaa: .word Lbbb | |
b99bd4ef | 16804 | |
c19d1205 ZW |
16805 | The first instruction loads the address of the jump table. |
16806 | The second instruction converts a table index into a byte offset. | |
16807 | The third instruction gets the jump address out of the table. | |
16808 | The fourth instruction performs the jump. | |
b99bd4ef | 16809 | |
c19d1205 ZW |
16810 | If the address stored at .Laaa is that of a symbol which has the |
16811 | Thumb_Func bit set, then the linker will arrange for this address | |
16812 | to have the bottom bit set, which in turn would mean that the | |
16813 | address computation performed by the third instruction would end | |
16814 | up with the bottom bit set. Since the ARM is capable of unaligned | |
16815 | word loads, the instruction would then load the incorrect address | |
16816 | out of the jump table, and chaos would ensue. */ | |
16817 | if (label_is_thumb_function_name | |
16818 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
16819 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 16820 | { |
c19d1205 ZW |
16821 | /* When the address of a Thumb function is taken the bottom |
16822 | bit of that address should be set. This will allow | |
16823 | interworking between Arm and Thumb functions to work | |
16824 | correctly. */ | |
b99bd4ef | 16825 | |
c19d1205 | 16826 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 16827 | |
c19d1205 | 16828 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 16829 | } |
07a53e5c | 16830 | |
07a53e5c | 16831 | dwarf2_emit_label (sym); |
b99bd4ef NC |
16832 | } |
16833 | ||
c921be7d | 16834 | bfd_boolean |
c19d1205 | 16835 | arm_data_in_code (void) |
b99bd4ef | 16836 | { |
c19d1205 | 16837 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16838 | { |
c19d1205 ZW |
16839 | *input_line_pointer = '/'; |
16840 | input_line_pointer += 5; | |
16841 | *input_line_pointer = 0; | |
c921be7d | 16842 | return TRUE; |
b99bd4ef NC |
16843 | } |
16844 | ||
c921be7d | 16845 | return FALSE; |
b99bd4ef NC |
16846 | } |
16847 | ||
c19d1205 ZW |
16848 | char * |
16849 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16850 | { |
c19d1205 | 16851 | int len; |
b99bd4ef | 16852 | |
c19d1205 ZW |
16853 | if (thumb_mode && (len = strlen (name)) > 5 |
16854 | && streq (name + len - 5, "/data")) | |
16855 | *(name + len - 5) = 0; | |
b99bd4ef | 16856 | |
c19d1205 | 16857 | return name; |
b99bd4ef | 16858 | } |
c19d1205 ZW |
16859 | \f |
16860 | /* Table of all register names defined by default. The user can | |
16861 | define additional names with .req. Note that all register names | |
16862 | should appear in both upper and lowercase variants. Some registers | |
16863 | also have mixed-case names. */ | |
b99bd4ef | 16864 | |
dcbf9037 | 16865 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16866 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16867 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16868 | #define REGSET(p,t) \ |
16869 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16870 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16871 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16872 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16873 | #define REGSETH(p,t) \ |
16874 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16875 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16876 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16877 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16878 | #define REGSET2(p,t) \ | |
16879 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16880 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16881 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16882 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
16883 | #define SPLRBANK(base,bank,t) \ |
16884 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
16885 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
16886 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
16887 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
16888 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
16889 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 16890 | |
c19d1205 | 16891 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16892 | { |
c19d1205 ZW |
16893 | /* ARM integer registers. */ |
16894 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16895 | |
c19d1205 ZW |
16896 | /* ATPCS synonyms. */ |
16897 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16898 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16899 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16900 | |
c19d1205 ZW |
16901 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16902 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16903 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16904 | |
c19d1205 ZW |
16905 | /* Well-known aliases. */ |
16906 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16907 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16908 | ||
16909 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16910 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16911 | ||
16912 | /* Coprocessor numbers. */ | |
16913 | REGSET(p, CP), REGSET(P, CP), | |
16914 | ||
16915 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16916 | compatibility. */ | |
16917 | REGSET(c, CN), REGSET(C, CN), | |
16918 | REGSET(cr, CN), REGSET(CR, CN), | |
16919 | ||
90ec0d68 MGD |
16920 | /* ARM banked registers. */ |
16921 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
16922 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
16923 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
16924 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
16925 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
16926 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
16927 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
16928 | ||
16929 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
16930 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
16931 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
16932 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
16933 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
16934 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB), | |
16935 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), | |
16936 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
16937 | ||
16938 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
16939 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
16940 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
16941 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
16942 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
16943 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
16944 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
fa94de6b | 16945 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), |
90ec0d68 MGD |
16946 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), |
16947 | ||
c19d1205 ZW |
16948 | /* FPA registers. */ |
16949 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16950 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16951 | ||
16952 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16953 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16954 | ||
16955 | /* VFP SP registers. */ | |
5287ad62 JB |
16956 | REGSET(s,VFS), REGSET(S,VFS), |
16957 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16958 | |
16959 | /* VFP DP Registers. */ | |
5287ad62 JB |
16960 | REGSET(d,VFD), REGSET(D,VFD), |
16961 | /* Extra Neon DP registers. */ | |
16962 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16963 | ||
16964 | /* Neon QP registers. */ | |
16965 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16966 | |
16967 | /* VFP control registers. */ | |
16968 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16969 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16970 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16971 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16972 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16973 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16974 | |
16975 | /* Maverick DSP coprocessor registers. */ | |
16976 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16977 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16978 | ||
16979 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16980 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16981 | REGDEF(dspsc,0,DSPSC), | |
16982 | ||
16983 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16984 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16985 | REGDEF(DSPSC,0,DSPSC), | |
16986 | ||
16987 | /* iWMMXt data registers - p0, c0-15. */ | |
16988 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16989 | ||
16990 | /* iWMMXt control registers - p1, c0-3. */ | |
16991 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16992 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16993 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16994 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16995 | ||
16996 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16997 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16998 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16999 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
17000 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
17001 | ||
17002 | /* XScale accumulator registers. */ | |
17003 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
17004 | }; | |
17005 | #undef REGDEF | |
17006 | #undef REGNUM | |
17007 | #undef REGSET | |
7ed4c4c5 | 17008 | |
c19d1205 ZW |
17009 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
17010 | within psr_required_here. */ | |
17011 | static const struct asm_psr psrs[] = | |
17012 | { | |
17013 | /* Backward compatibility notation. Note that "all" is no longer | |
17014 | truly all possible PSR bits. */ | |
17015 | {"all", PSR_c | PSR_f}, | |
17016 | {"flg", PSR_f}, | |
17017 | {"ctl", PSR_c}, | |
17018 | ||
17019 | /* Individual flags. */ | |
17020 | {"f", PSR_f}, | |
17021 | {"c", PSR_c}, | |
17022 | {"x", PSR_x}, | |
17023 | {"s", PSR_s}, | |
59b42a0d | 17024 | |
c19d1205 ZW |
17025 | /* Combinations of flags. */ |
17026 | {"fs", PSR_f | PSR_s}, | |
17027 | {"fx", PSR_f | PSR_x}, | |
17028 | {"fc", PSR_f | PSR_c}, | |
17029 | {"sf", PSR_s | PSR_f}, | |
17030 | {"sx", PSR_s | PSR_x}, | |
17031 | {"sc", PSR_s | PSR_c}, | |
17032 | {"xf", PSR_x | PSR_f}, | |
17033 | {"xs", PSR_x | PSR_s}, | |
17034 | {"xc", PSR_x | PSR_c}, | |
17035 | {"cf", PSR_c | PSR_f}, | |
17036 | {"cs", PSR_c | PSR_s}, | |
17037 | {"cx", PSR_c | PSR_x}, | |
17038 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
17039 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
17040 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
17041 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
17042 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
17043 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
17044 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
17045 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
17046 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
17047 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
17048 | {"scf", PSR_s | PSR_c | PSR_f}, | |
17049 | {"scx", PSR_s | PSR_c | PSR_x}, | |
17050 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
17051 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
17052 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
17053 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
17054 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
17055 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
17056 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
17057 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
17058 | {"csf", PSR_c | PSR_s | PSR_f}, | |
17059 | {"csx", PSR_c | PSR_s | PSR_x}, | |
17060 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
17061 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
17062 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
17063 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
17064 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
17065 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
17066 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
17067 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
17068 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
17069 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
17070 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
17071 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
17072 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
17073 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
17074 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
17075 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
17076 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
17077 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
17078 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
17079 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
17080 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
17081 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
17082 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
17083 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
17084 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
17085 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
17086 | }; | |
17087 | ||
62b3e311 PB |
17088 | /* Table of V7M psr names. */ |
17089 | static const struct asm_psr v7m_psrs[] = | |
17090 | { | |
2b744c99 PB |
17091 | {"apsr", 0 }, {"APSR", 0 }, |
17092 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
17093 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
17094 | {"psr", 3 }, {"PSR", 3 }, | |
17095 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
17096 | {"ipsr", 5 }, {"IPSR", 5 }, | |
17097 | {"epsr", 6 }, {"EPSR", 6 }, | |
17098 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
17099 | {"msp", 8 }, {"MSP", 8 }, | |
17100 | {"psp", 9 }, {"PSP", 9 }, | |
17101 | {"primask", 16}, {"PRIMASK", 16}, | |
17102 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
17103 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
17104 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
17105 | {"faultmask", 19}, {"FAULTMASK", 19}, |
17106 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
17107 | }; |
17108 | ||
c19d1205 ZW |
17109 | /* Table of all shift-in-operand names. */ |
17110 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 17111 | { |
c19d1205 ZW |
17112 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
17113 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
17114 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
17115 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
17116 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
17117 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
17118 | }; | |
b99bd4ef | 17119 | |
c19d1205 ZW |
17120 | /* Table of all explicit relocation names. */ |
17121 | #ifdef OBJ_ELF | |
17122 | static struct reloc_entry reloc_names[] = | |
17123 | { | |
17124 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
17125 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
17126 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
17127 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
17128 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
17129 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
17130 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
17131 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
17132 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
17133 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 17134 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
17135 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
17136 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
17137 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, | |
17138 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, | |
17139 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, | |
17140 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, | |
17141 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} | |
c19d1205 ZW |
17142 | }; |
17143 | #endif | |
b99bd4ef | 17144 | |
c19d1205 ZW |
17145 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
17146 | static const struct asm_cond conds[] = | |
17147 | { | |
17148 | {"eq", 0x0}, | |
17149 | {"ne", 0x1}, | |
17150 | {"cs", 0x2}, {"hs", 0x2}, | |
17151 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
17152 | {"mi", 0x4}, | |
17153 | {"pl", 0x5}, | |
17154 | {"vs", 0x6}, | |
17155 | {"vc", 0x7}, | |
17156 | {"hi", 0x8}, | |
17157 | {"ls", 0x9}, | |
17158 | {"ge", 0xa}, | |
17159 | {"lt", 0xb}, | |
17160 | {"gt", 0xc}, | |
17161 | {"le", 0xd}, | |
17162 | {"al", 0xe} | |
17163 | }; | |
bfae80f2 | 17164 | |
62b3e311 PB |
17165 | static struct asm_barrier_opt barrier_opt_names[] = |
17166 | { | |
52e7f43d RE |
17167 | { "sy", 0xf }, { "SY", 0xf }, |
17168 | { "un", 0x7 }, { "UN", 0x7 }, | |
17169 | { "st", 0xe }, { "ST", 0xe }, | |
17170 | { "unst", 0x6 }, { "UNST", 0x6 }, | |
17171 | { "ish", 0xb }, { "ISH", 0xb }, | |
17172 | { "sh", 0xb }, { "SH", 0xb }, | |
17173 | { "ishst", 0xa }, { "ISHST", 0xa }, | |
17174 | { "shst", 0xa }, { "SHST", 0xa }, | |
17175 | { "nsh", 0x7 }, { "NSH", 0x7 }, | |
17176 | { "nshst", 0x6 }, { "NSHST", 0x6 }, | |
17177 | { "osh", 0x3 }, { "OSH", 0x3 }, | |
17178 | { "oshst", 0x2 }, { "OSHST", 0x2 } | |
62b3e311 PB |
17179 | }; |
17180 | ||
c19d1205 ZW |
17181 | /* Table of ARM-format instructions. */ |
17182 | ||
17183 | /* Macros for gluing together operand strings. N.B. In all cases | |
17184 | other than OPS0, the trailing OP_stop comes from default | |
17185 | zero-initialization of the unspecified elements of the array. */ | |
17186 | #define OPS0() { OP_stop, } | |
17187 | #define OPS1(a) { OP_##a, } | |
17188 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
17189 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
17190 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
17191 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
17192 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
17193 | ||
5be8be5d DG |
17194 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
17195 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
17196 | MIX_ARM_THUMB_OPERANDS macro. | |
17197 | In order to use these macros, prefix the number of operands with _ | |
17198 | e.g. _3. */ | |
17199 | #define OPS_1(a) { a, } | |
17200 | #define OPS_2(a,b) { a,b, } | |
17201 | #define OPS_3(a,b,c) { a,b,c, } | |
17202 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
17203 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
17204 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
17205 | ||
c19d1205 ZW |
17206 | /* These macros abstract out the exact format of the mnemonic table and |
17207 | save some repeated characters. */ | |
17208 | ||
17209 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
17210 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17211 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 17212 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17213 | |
17214 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
17215 | a T_MNEM_xyz enumerator. */ | |
17216 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 17217 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 17218 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17219 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17220 | |
17221 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
17222 | infix after the third character. */ | |
17223 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17224 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 17225 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 17226 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 17227 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 17228 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 17229 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 17230 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 17231 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 17232 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 17233 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17234 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 17235 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17236 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17237 | |
17238 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
17239 | appear in the condition table. */ | |
17240 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17241 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 17242 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17243 | |
17244 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
17245 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
17246 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
17247 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
17248 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
17249 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
17250 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
17251 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
17252 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
17253 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
17254 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
17255 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
17256 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
17257 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
17258 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
17259 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
17260 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
17261 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
17262 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
17263 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
17264 | |
17265 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
17266 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
17267 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 17268 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17269 | |
17270 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
17271 | field is still 0xE. Many of the Thumb variants can be executed |
17272 | conditionally, so this is checked separately. */ | |
c19d1205 | 17273 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 17274 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 17275 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17276 | |
17277 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
17278 | condition code field. */ | |
17279 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17280 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 17281 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17282 | |
17283 | /* ARM-only variants of all the above. */ | |
6a86118a | 17284 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 17285 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
17286 | |
17287 | #define C3(mnem, op, nops, ops, ae) \ | |
17288 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
17289 | ||
e3cb604e PB |
17290 | /* Legacy mnemonics that always have conditional infix after the third |
17291 | character. */ | |
17292 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17293 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
17294 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
17295 | ||
8f06b2d8 PB |
17296 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
17297 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17298 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 17299 | |
e3cb604e PB |
17300 | /* Legacy coprocessor instructions where conditional infix and conditional |
17301 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
17302 | not just the potentially ambiguous ones. */ | |
17303 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17304 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
17305 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
17306 | ||
17307 | /* Coprocessor, takes either a suffix or a position-3 infix | |
17308 | (for an FPA corner case). */ | |
17309 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17310 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 17311 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 17312 | |
6a86118a | 17313 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
17314 | { m1 #m2 m3, OPS##nops ops, \ |
17315 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
17316 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
17317 | ||
17318 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
17319 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
17320 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
17321 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
17322 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
17323 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
17324 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
17325 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
17326 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
17327 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
17328 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
17329 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
17330 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
17331 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
17332 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
17333 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
17334 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
17335 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
17336 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
17337 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
17338 | |
17339 | #define UE(mnem, op, nops, ops, ae) \ | |
17340 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
17341 | ||
17342 | #define UF(mnem, op, nops, ops, ae) \ | |
17343 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
17344 | ||
5287ad62 JB |
17345 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
17346 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
17347 | use the same encoding function for each. */ | |
17348 | #define NUF(mnem, op, nops, ops, enc) \ | |
17349 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
17350 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
17351 | ||
17352 | /* Neon data processing, version which indirects through neon_enc_tab for | |
17353 | the various overloaded versions of opcodes. */ | |
17354 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 17355 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17356 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17357 | ||
17358 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
17359 | version. */ | |
037e8744 JB |
17360 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
17361 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
17362 | THUMB_VARIANT, do_##enc, do_##enc } |
17363 | ||
037e8744 | 17364 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17365 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17366 | |
17367 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17368 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17369 | |
5287ad62 | 17370 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 17371 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 17372 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17373 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17374 | ||
037e8744 | 17375 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17376 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17377 | |
17378 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17379 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17380 | |
c19d1205 ZW |
17381 | #define do_0 0 |
17382 | ||
c19d1205 | 17383 | static const struct asm_opcode insns[] = |
bfae80f2 | 17384 | { |
e74cfd16 PB |
17385 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
17386 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
17387 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
17388 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
17389 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
17390 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
17391 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
17392 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
17393 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17394 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17395 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
17396 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17397 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
17398 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
17399 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
17400 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17401 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
17402 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
17403 | |
17404 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
17405 | for setting PSR flag bits. They are obsolete in V6 and do not | |
17406 | have Thumb equivalents. */ | |
21d799b5 NC |
17407 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
17408 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
17409 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
17410 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17411 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17412 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
17413 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17414 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17415 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
17416 | ||
17417 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
17418 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
17419 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
17420 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
17421 | ||
17422 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
17423 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
17424 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
17425 | OP_RRnpc), | |
17426 | OP_ADDRGLDR),ldst, t_ldst), | |
17427 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
17428 | |
17429 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17430 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17431 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17432 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17433 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17434 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17435 | ||
17436 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
17437 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
17438 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
17439 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 17440 | |
c19d1205 | 17441 | /* Pseudo ops. */ |
21d799b5 | 17442 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 17443 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 17444 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
17445 | |
17446 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
17447 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
17448 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
17449 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
17450 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
17451 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
17452 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
17453 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
17454 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
17455 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
17456 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
17457 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
17458 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 17459 | |
16a4cf17 | 17460 | /* These may simplify to neg. */ |
21d799b5 NC |
17461 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
17462 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 17463 | |
c921be7d NC |
17464 | #undef THUMB_VARIANT |
17465 | #define THUMB_VARIANT & arm_ext_v6 | |
17466 | ||
21d799b5 | 17467 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
17468 | |
17469 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
17470 | #undef THUMB_VARIANT |
17471 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17472 | ||
21d799b5 NC |
17473 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
17474 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
17475 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 17476 | |
5be8be5d DG |
17477 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
17478 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
17479 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
17480 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 17481 | |
21d799b5 NC |
17482 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17483 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 17484 | |
21d799b5 NC |
17485 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17486 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
17487 | |
17488 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 17489 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
17490 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
17491 | ||
17492 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
17493 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
17494 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
17495 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
17496 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
17497 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
17498 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
17499 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
17500 | ||
c921be7d NC |
17501 | #undef ARM_VARIANT |
17502 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
17503 | #undef THUMB_VARIANT | |
17504 | #define THUMB_VARIANT & arm_ext_v4t | |
17505 | ||
21d799b5 NC |
17506 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
17507 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 17508 | |
c921be7d NC |
17509 | #undef THUMB_VARIANT |
17510 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17511 | ||
21d799b5 | 17512 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
17513 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
17514 | ||
17515 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
17516 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
17517 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17518 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17519 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17520 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17521 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 17522 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 17523 | |
c921be7d NC |
17524 | #undef ARM_VARIANT |
17525 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
17526 | ||
21d799b5 | 17527 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
17528 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
17529 | ||
c921be7d NC |
17530 | #undef ARM_VARIANT |
17531 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
17532 | #undef THUMB_VARIANT | |
17533 | #define THUMB_VARIANT & arm_ext_msr | |
17534 | ||
d2cd1205 JB |
17535 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
17536 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 17537 | |
c921be7d NC |
17538 | #undef ARM_VARIANT |
17539 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
17540 | #undef THUMB_VARIANT | |
17541 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17542 | ||
21d799b5 NC |
17543 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
17544 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17545 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17546 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17547 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17548 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17549 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17550 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 17551 | |
c921be7d NC |
17552 | #undef ARM_VARIANT |
17553 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
17554 | #undef THUMB_VARIANT | |
17555 | #define THUMB_VARIANT & arm_ext_v4t | |
17556 | ||
5be8be5d DG |
17557 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
17558 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17559 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17560 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17561 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17562 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 17563 | |
c921be7d NC |
17564 | #undef ARM_VARIANT |
17565 | #define ARM_VARIANT & arm_ext_v4t_5 | |
17566 | ||
c19d1205 ZW |
17567 | /* ARM Architecture 4T. */ |
17568 | /* Note: bx (and blx) are required on V5, even if the processor does | |
17569 | not support Thumb. */ | |
21d799b5 | 17570 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 17571 | |
c921be7d NC |
17572 | #undef ARM_VARIANT |
17573 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
17574 | #undef THUMB_VARIANT | |
17575 | #define THUMB_VARIANT & arm_ext_v5t | |
17576 | ||
c19d1205 ZW |
17577 | /* Note: blx has 2 variants; the .value coded here is for |
17578 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
17579 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
17580 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 17581 | |
c921be7d NC |
17582 | #undef THUMB_VARIANT |
17583 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17584 | ||
21d799b5 NC |
17585 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
17586 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17587 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17588 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17589 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17590 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
17591 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
17592 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 17593 | |
c921be7d NC |
17594 | #undef ARM_VARIANT |
17595 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
17596 | #undef THUMB_VARIANT |
17597 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 17598 | |
21d799b5 NC |
17599 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17600 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17601 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17602 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17603 | |
21d799b5 NC |
17604 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17605 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17606 | |
21d799b5 NC |
17607 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
17608 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17609 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17610 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 17611 | |
21d799b5 NC |
17612 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17613 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17614 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17615 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17616 | |
21d799b5 NC |
17617 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17618 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17619 | |
03ee1b7f NC |
17620 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
17621 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17622 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17623 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 17624 | |
c921be7d NC |
17625 | #undef ARM_VARIANT |
17626 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
17627 | #undef THUMB_VARIANT |
17628 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 17629 | |
21d799b5 | 17630 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
17631 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
17632 | ldrd, t_ldstd), | |
17633 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
17634 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 17635 | |
21d799b5 NC |
17636 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17637 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 17638 | |
c921be7d NC |
17639 | #undef ARM_VARIANT |
17640 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
17641 | ||
21d799b5 | 17642 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 17643 | |
c921be7d NC |
17644 | #undef ARM_VARIANT |
17645 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
17646 | #undef THUMB_VARIANT | |
17647 | #define THUMB_VARIANT & arm_ext_v6 | |
17648 | ||
21d799b5 NC |
17649 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
17650 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
17651 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17652 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17653 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17654 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17655 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17656 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17657 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17658 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 17659 | |
c921be7d NC |
17660 | #undef THUMB_VARIANT |
17661 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17662 | ||
5be8be5d DG |
17663 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
17664 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17665 | strex, t_strex), | |
21d799b5 NC |
17666 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17667 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 17668 | |
21d799b5 NC |
17669 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
17670 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 17671 | |
9e3c6df6 | 17672 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
17673 | #undef THUMB_VARIANT |
17674 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
17675 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
17676 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
17677 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
17678 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17679 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
17680 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
17681 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
17682 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17683 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
17684 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
17685 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
17686 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 17687 | |
9e3c6df6 PB |
17688 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
17689 | #undef THUMB_VARIANT | |
17690 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
17691 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
17692 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
17693 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
17694 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17695 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17696 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17697 | /* Old name for QASX. */ |
21d799b5 NC |
17698 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17699 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17700 | /* Old name for QSAX. */ |
21d799b5 NC |
17701 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17702 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17703 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17704 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17705 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17706 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17707 | /* Old name for SASX. */ |
21d799b5 NC |
17708 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17709 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17710 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17711 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17712 | /* Old name for SHASX. */ |
21d799b5 NC |
17713 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17714 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17715 | /* Old name for SHSAX. */ |
21d799b5 NC |
17716 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17717 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17718 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17719 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17720 | /* Old name for SSAX. */ |
21d799b5 NC |
17721 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17722 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17723 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17724 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17725 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17726 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17727 | /* Old name for UASX. */ |
21d799b5 NC |
17728 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17729 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17730 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17731 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17732 | /* Old name for UHASX. */ |
21d799b5 NC |
17733 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17734 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17735 | /* Old name for UHSAX. */ |
21d799b5 NC |
17736 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17737 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17738 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17739 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17740 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17741 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17742 | /* Old name for UQASX. */ |
21d799b5 NC |
17743 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17744 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17745 | /* Old name for UQSAX. */ |
21d799b5 NC |
17746 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17747 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17748 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17749 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17750 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17751 | /* Old name for USAX. */ |
21d799b5 NC |
17752 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17753 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
17754 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
17755 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17756 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17757 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17758 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17759 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17760 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17761 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17762 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17763 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17764 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17765 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17766 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17767 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17768 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17769 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17770 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17771 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17772 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17773 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17774 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17775 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17776 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17777 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17778 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17779 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17780 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
17781 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
17782 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
17783 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17784 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17785 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 17786 | |
c921be7d NC |
17787 | #undef ARM_VARIANT |
17788 | #define ARM_VARIANT & arm_ext_v6k | |
17789 | #undef THUMB_VARIANT | |
17790 | #define THUMB_VARIANT & arm_ext_v6k | |
17791 | ||
21d799b5 NC |
17792 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
17793 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
17794 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
17795 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 17796 | |
c921be7d NC |
17797 | #undef THUMB_VARIANT |
17798 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
17799 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
17800 | ldrexd, t_ldrexd), | |
17801 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
17802 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 17803 | |
c921be7d NC |
17804 | #undef THUMB_VARIANT |
17805 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
17806 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
17807 | rd_rn, rd_rn), | |
17808 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
17809 | rd_rn, rd_rn), | |
17810 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 17811 | strex, t_strexbh), |
5be8be5d | 17812 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 17813 | strex, t_strexbh), |
21d799b5 | 17814 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 17815 | |
c921be7d | 17816 | #undef ARM_VARIANT |
f4c65163 MGD |
17817 | #define ARM_VARIANT & arm_ext_sec |
17818 | #undef THUMB_VARIANT | |
17819 | #define THUMB_VARIANT & arm_ext_sec | |
c921be7d | 17820 | |
21d799b5 | 17821 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 17822 | |
90ec0d68 MGD |
17823 | #undef ARM_VARIANT |
17824 | #define ARM_VARIANT & arm_ext_virt | |
17825 | #undef THUMB_VARIANT | |
17826 | #define THUMB_VARIANT & arm_ext_virt | |
17827 | ||
17828 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
17829 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
17830 | ||
c921be7d NC |
17831 | #undef ARM_VARIANT |
17832 | #define ARM_VARIANT & arm_ext_v6t2 | |
f4c65163 MGD |
17833 | #undef THUMB_VARIANT |
17834 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 17835 | |
21d799b5 NC |
17836 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
17837 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
17838 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
17839 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 17840 | |
21d799b5 NC |
17841 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
17842 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17843 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17844 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 17845 | |
5be8be5d DG |
17846 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
17847 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17848 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17849 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 17850 | |
bf3eeda7 NS |
17851 | /* Thumb-only instructions. */ |
17852 | #undef ARM_VARIANT | |
17853 | #define ARM_VARIANT NULL | |
17854 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
17855 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
17856 | |
17857 | /* ARM does not really have an IT instruction, so always allow it. | |
17858 | The opcode is copied from Thumb in order to allow warnings in | |
17859 | -mimplicit-it=[never | arm] modes. */ | |
17860 | #undef ARM_VARIANT | |
17861 | #define ARM_VARIANT & arm_ext_v1 | |
17862 | ||
21d799b5 NC |
17863 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
17864 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
17865 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
17866 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
17867 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
17868 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
17869 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
17870 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
17871 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
17872 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
17873 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
17874 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
17875 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
17876 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
17877 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 17878 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
17879 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
17880 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 17881 | |
92e90b6e | 17882 | /* Thumb2 only instructions. */ |
c921be7d NC |
17883 | #undef ARM_VARIANT |
17884 | #define ARM_VARIANT NULL | |
92e90b6e | 17885 | |
21d799b5 NC |
17886 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
17887 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
17888 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
17889 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
17890 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
17891 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 17892 | |
eea54501 MGD |
17893 | /* Hardware division instructions. */ |
17894 | #undef ARM_VARIANT | |
17895 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
17896 | #undef THUMB_VARIANT |
17897 | #define THUMB_VARIANT & arm_ext_div | |
17898 | ||
eea54501 MGD |
17899 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
17900 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 17901 | |
7e806470 | 17902 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17903 | #undef ARM_VARIANT |
17904 | #define ARM_VARIANT & arm_ext_barrier | |
17905 | #undef THUMB_VARIANT | |
17906 | #define THUMB_VARIANT & arm_ext_barrier | |
17907 | ||
52e7f43d RE |
17908 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), |
17909 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), | |
17910 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), | |
7e806470 | 17911 | |
62b3e311 | 17912 | /* ARM V7 instructions. */ |
c921be7d NC |
17913 | #undef ARM_VARIANT |
17914 | #define ARM_VARIANT & arm_ext_v7 | |
17915 | #undef THUMB_VARIANT | |
17916 | #define THUMB_VARIANT & arm_ext_v7 | |
17917 | ||
21d799b5 NC |
17918 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17919 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17920 | |
60e5ef9f MGD |
17921 | #undef ARM_VARIANT |
17922 | #define ARM_VARIANT & arm_ext_mp | |
17923 | #undef THUMB_VARIANT | |
17924 | #define THUMB_VARIANT & arm_ext_mp | |
17925 | ||
17926 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
17927 | ||
c921be7d NC |
17928 | #undef ARM_VARIANT |
17929 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
17930 | ||
21d799b5 NC |
17931 | cCE("wfs", e200110, 1, (RR), rd), |
17932 | cCE("rfs", e300110, 1, (RR), rd), | |
17933 | cCE("wfc", e400110, 1, (RR), rd), | |
17934 | cCE("rfc", e500110, 1, (RR), rd), | |
17935 | ||
17936 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17937 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17938 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17939 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17940 | ||
17941 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17942 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17943 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17944 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17945 | ||
17946 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
17947 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
17948 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
17949 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
17950 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
17951 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
17952 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
17953 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
17954 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
17955 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
17956 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
17957 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
17958 | ||
17959 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
17960 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
17961 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17962 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17963 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17964 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17965 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17966 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17967 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17968 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17969 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17970 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17971 | ||
17972 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17973 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17974 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17975 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17976 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17977 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17978 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17979 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17980 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17981 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17982 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17983 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17984 | ||
17985 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17986 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17987 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17988 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17989 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17990 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17991 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17992 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17993 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17994 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17995 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17996 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17997 | ||
17998 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17999 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
18000 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
18001 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
18002 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
18003 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
18004 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
18005 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
18006 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
18007 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
18008 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
18009 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
18010 | ||
18011 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
18012 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
18013 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
18014 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
18015 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
18016 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
18017 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
18018 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
18019 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
18020 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
18021 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
18022 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
18023 | ||
18024 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
18025 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
18026 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
18027 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
18028 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
18029 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
18030 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
18031 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
18032 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
18033 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
18034 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
18035 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
18036 | ||
18037 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
18038 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
18039 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
18040 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
18041 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
18042 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
18043 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
18044 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
18045 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
18046 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
18047 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
18048 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
18049 | ||
18050 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
18051 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
18052 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
18053 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
18054 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
18055 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
18056 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
18057 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
18058 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
18059 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
18060 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
18061 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
18062 | ||
18063 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
18064 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
18065 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
18066 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
18067 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
18068 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
18069 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
18070 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
18071 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
18072 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
18073 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
18074 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
18075 | ||
18076 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
18077 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
18078 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
18079 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
18080 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
18081 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
18082 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
18083 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
18084 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
18085 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
18086 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
18087 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
18088 | ||
18089 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
18090 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
18091 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
18092 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
18093 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
18094 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
18095 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
18096 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
18097 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
18098 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
18099 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
18100 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
18101 | ||
18102 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
18103 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
18104 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
18105 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
18106 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
18107 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
18108 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
18109 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
18110 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
18111 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
18112 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
18113 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
18114 | ||
18115 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
18116 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
18117 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
18118 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
18119 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
18120 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
18121 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
18122 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
18123 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
18124 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
18125 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
18126 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
18127 | ||
18128 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
18129 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
18130 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
18131 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
18132 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
18133 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
18134 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
18135 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
18136 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
18137 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
18138 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
18139 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
18140 | ||
18141 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
18142 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
18143 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
18144 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
18145 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
18146 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
18147 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
18148 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
18149 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
18150 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
18151 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
18152 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
18153 | ||
18154 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18155 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18156 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18157 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18158 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18159 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18160 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18161 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18162 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18163 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18164 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18165 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18166 | ||
18167 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18168 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18169 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18170 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18171 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18172 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18173 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18174 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18175 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18176 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18177 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18178 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18179 | ||
18180 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18181 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18182 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18183 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18184 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18185 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18186 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18187 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18188 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18189 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18190 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18191 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18192 | ||
18193 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18194 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18195 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18196 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18197 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18198 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18199 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18200 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18201 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18202 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18203 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18204 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18205 | ||
18206 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18207 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18208 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18209 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18210 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18211 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18212 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18213 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18214 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18215 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18216 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18217 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18218 | ||
18219 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18220 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18221 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18222 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18223 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18224 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18225 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18226 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18227 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18228 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18229 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18230 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18231 | ||
18232 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18233 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18234 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18235 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18236 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18237 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18238 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18239 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18240 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18241 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18242 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18243 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18244 | ||
18245 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18246 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18247 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18248 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18249 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18250 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18251 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18252 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18253 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18254 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18255 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18256 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18257 | ||
18258 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18259 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18260 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18261 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18262 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18263 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18264 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18265 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18266 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18267 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18268 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18269 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18270 | ||
18271 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18272 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18273 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18274 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18275 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18276 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18277 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18278 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18279 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18280 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18281 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18282 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18283 | ||
18284 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18285 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18286 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18287 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18288 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18289 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18290 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18291 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18292 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18293 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18294 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18295 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18296 | ||
18297 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18298 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18299 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18300 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18301 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18302 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18303 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18304 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18305 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18306 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18307 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18308 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18309 | ||
18310 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18311 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18312 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18313 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18314 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18315 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18316 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18317 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18318 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18319 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18320 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18321 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18322 | ||
18323 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
18324 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
18325 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
18326 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
18327 | ||
18328 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
18329 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
18330 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
18331 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
18332 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
18333 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
18334 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
18335 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
18336 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
18337 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
18338 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
18339 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 18340 | |
c19d1205 ZW |
18341 | /* The implementation of the FIX instruction is broken on some |
18342 | assemblers, in that it accepts a precision specifier as well as a | |
18343 | rounding specifier, despite the fact that this is meaningless. | |
18344 | To be more compatible, we accept it as well, though of course it | |
18345 | does not set any bits. */ | |
21d799b5 NC |
18346 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
18347 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
18348 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
18349 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
18350 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
18351 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
18352 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
18353 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
18354 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
18355 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
18356 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
18357 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
18358 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 18359 | |
c19d1205 | 18360 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
18361 | #undef ARM_VARIANT |
18362 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
18363 | ||
21d799b5 NC |
18364 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
18365 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18366 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18367 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18368 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18369 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 18370 | |
c921be7d NC |
18371 | #undef ARM_VARIANT |
18372 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
18373 | ||
c19d1205 | 18374 | /* Moves and type conversions. */ |
21d799b5 NC |
18375 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
18376 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
18377 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
18378 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
7465e07a NC |
18379 | cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs), |
18380 | cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
18381 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18382 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18383 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18384 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18385 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18386 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18387 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
18388 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
18389 | |
18390 | /* Memory operations. */ | |
21d799b5 NC |
18391 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
18392 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
18393 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
18394 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18395 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18396 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18397 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18398 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18399 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18400 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18401 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18402 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18403 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18404 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18405 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18406 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18407 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18408 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 18409 | |
c19d1205 | 18410 | /* Monadic operations. */ |
21d799b5 NC |
18411 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18412 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18413 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
18414 | |
18415 | /* Dyadic operations. */ | |
21d799b5 NC |
18416 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
18417 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18418 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18419 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18420 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18421 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18422 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18423 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18424 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 18425 | |
c19d1205 | 18426 | /* Comparisons. */ |
21d799b5 NC |
18427 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
18428 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
18429 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18430 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 18431 | |
62f3b8c8 PB |
18432 | /* Double precision load/store are still present on single precision |
18433 | implementations. */ | |
18434 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
18435 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
18436 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
18437 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18438 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18439 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18440 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18441 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18442 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18443 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 18444 | |
c921be7d NC |
18445 | #undef ARM_VARIANT |
18446 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
18447 | ||
c19d1205 | 18448 | /* Moves and type conversions. */ |
21d799b5 NC |
18449 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18450 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18451 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18452 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18453 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18454 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18455 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18456 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18457 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18458 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18459 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18460 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18461 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 18462 | |
c19d1205 | 18463 | /* Monadic operations. */ |
21d799b5 NC |
18464 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
18465 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18466 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
18467 | |
18468 | /* Dyadic operations. */ | |
21d799b5 NC |
18469 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
18470 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18471 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18472 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18473 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18474 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18475 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18476 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18477 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 18478 | |
c19d1205 | 18479 | /* Comparisons. */ |
21d799b5 NC |
18480 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18481 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
18482 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18483 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 18484 | |
c921be7d NC |
18485 | #undef ARM_VARIANT |
18486 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
18487 | ||
21d799b5 NC |
18488 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
18489 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
18490 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
18491 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 18492 | |
037e8744 JB |
18493 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
18494 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
18495 | #undef ARM_VARIANT |
18496 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
18497 | #undef THUMB_VARIANT | |
18498 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
18499 | ||
037e8744 JB |
18500 | /* These mnemonics are unique to VFP. */ |
18501 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
18502 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
18503 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
18504 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18505 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18506 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
18507 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
18508 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
18509 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
18510 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
18511 | ||
18512 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
18513 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
18514 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
18515 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 18516 | |
21d799b5 NC |
18517 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
18518 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
18519 | |
18520 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18521 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18522 | ||
55881a11 MGD |
18523 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
18524 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18525 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18526 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18527 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18528 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
18529 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
18530 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 18531 | |
5f1af56b | 18532 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 18533 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
21d799b5 NC |
18534 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
18535 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 18536 | |
037e8744 JB |
18537 | |
18538 | /* NOTE: All VMOV encoding is special-cased! */ | |
18539 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
18540 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
18541 | ||
c921be7d NC |
18542 | #undef THUMB_VARIANT |
18543 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
18544 | #undef ARM_VARIANT | |
18545 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
18546 | ||
5287ad62 JB |
18547 | /* Data processing with three registers of the same length. */ |
18548 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
18549 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
18550 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
18551 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18552 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18553 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18554 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18555 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18556 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18557 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18558 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18559 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
18560 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18561 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
18562 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
18563 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
18564 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
18565 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
18566 | /* If not immediate, fall back to neon_dyadic_i64_su. |
18567 | shl_imm should accept I8 I16 I32 I64, | |
18568 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
18569 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
18570 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
18571 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
18572 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 18573 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
18574 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
18575 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18576 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18577 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18578 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18579 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18580 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18581 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18582 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
18583 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
18584 | /* Bitfield ops, untyped. */ |
18585 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18586 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18587 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18588 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18589 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18590 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18591 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
18592 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
18593 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18594 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18595 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18596 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18597 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
18598 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
18599 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
18600 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
18601 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18602 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
18603 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18604 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18605 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
18606 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18607 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 18608 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
18609 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
18610 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 18611 | /* As above, D registers only. */ |
21d799b5 NC |
18612 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
18613 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 18614 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
18615 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
18616 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
18617 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 18618 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
18619 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
18620 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
18621 | /* vtst takes sizes 8, 16, 32. */ |
18622 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
18623 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
18624 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 18625 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 18626 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
18627 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
18628 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
18629 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
18630 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
18631 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
18632 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
18633 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
18634 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
18635 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
18636 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
18637 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
18638 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
18639 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
18640 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18641 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
18642 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18643 | ||
18644 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 18645 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
18646 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
18647 | ||
18648 | /* Data processing with two registers and a shift amount. */ | |
18649 | /* Right shifts, and variants with rounding. | |
18650 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18651 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18652 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18653 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18654 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18655 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18656 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18657 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18658 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18659 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
18660 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
18661 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
18662 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
18663 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
18664 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18665 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
18666 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
18667 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
18668 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
18669 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18670 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18671 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
18672 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18673 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18674 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
18675 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18676 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18677 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 18678 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 18679 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 18680 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 18681 | |
4316f0d2 DG |
18682 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
18683 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
18684 | |
18685 | /* Data processing, three registers of different lengths. */ | |
18686 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
18687 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
18688 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18689 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18690 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18691 | /* If not scalar, fall back to neon_dyadic_long. | |
18692 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
18693 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
18694 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
18695 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
18696 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18697 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18698 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
18699 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18700 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18701 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18702 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18703 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
18704 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
18705 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
18706 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
18707 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
18708 | S16 S32 U16 U32. */ | |
21d799b5 | 18709 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
18710 | |
18711 | /* Extract. Size 8. */ | |
3b8d421e PB |
18712 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
18713 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
18714 | |
18715 | /* Two registers, miscellaneous. */ | |
18716 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
18717 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
18718 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
18719 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
18720 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
18721 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
18722 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
18723 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
18724 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
18725 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
18726 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
18727 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
18728 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 18729 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 18730 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 18731 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 18732 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 18733 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
18734 | /* VZIP / VUZP. Sizes 8 16 32. */ |
18735 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18736 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
18737 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18738 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
18739 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
18740 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18741 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18742 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18743 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18744 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
18745 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
18746 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
18747 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
18748 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
18749 | /* Reciprocal estimates. Types U32 F32. */ | |
18750 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
18751 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
18752 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
18753 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
18754 | /* VCLS. Types S8 S16 S32. */ | |
18755 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
18756 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
18757 | /* VCLZ. Types I8 I16 I32. */ | |
18758 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
18759 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
18760 | /* VCNT. Size 8. */ | |
18761 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
18762 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
18763 | /* Two address, untyped. */ | |
18764 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
18765 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
18766 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
18767 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
18768 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
18769 | |
18770 | /* Table lookup. Size 8. */ | |
18771 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18772 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18773 | ||
c921be7d NC |
18774 | #undef THUMB_VARIANT |
18775 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
18776 | #undef ARM_VARIANT | |
18777 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
18778 | ||
5287ad62 | 18779 | /* Neon element/structure load/store. */ |
21d799b5 NC |
18780 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
18781 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18782 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18783 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18784 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18785 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18786 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18787 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 18788 | |
c921be7d | 18789 | #undef THUMB_VARIANT |
62f3b8c8 PB |
18790 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
18791 | #undef ARM_VARIANT | |
18792 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
18793 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
18794 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18795 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18796 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18797 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18798 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18799 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18800 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18801 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18802 | ||
18803 | #undef THUMB_VARIANT | |
c921be7d NC |
18804 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
18805 | #undef ARM_VARIANT | |
18806 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
18807 | ||
21d799b5 | 18808 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 18809 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18810 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18811 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18812 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18813 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18814 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18815 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18816 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 18817 | |
62f3b8c8 PB |
18818 | #undef ARM_VARIANT |
18819 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
18820 | #undef THUMB_VARIANT | |
18821 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
18822 | /* Mnemonics shared by Neon and VFP. These are included in the | |
18823 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
18824 | FMA instructions. */ | |
18825 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18826 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18827 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
18828 | the v form should always be used. */ | |
18829 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18830 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18831 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18832 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18833 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18834 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18835 | ||
5287ad62 | 18836 | #undef THUMB_VARIANT |
c921be7d NC |
18837 | #undef ARM_VARIANT |
18838 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
18839 | ||
21d799b5 NC |
18840 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
18841 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18842 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18843 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18844 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18845 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18846 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
18847 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 18848 | |
c921be7d NC |
18849 | #undef ARM_VARIANT |
18850 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
18851 | ||
21d799b5 NC |
18852 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
18853 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
18854 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
18855 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
18856 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
18857 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
18858 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
18859 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
18860 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
18861 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18862 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18863 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18864 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18865 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18866 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18867 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18868 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18869 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18870 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
18871 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
18872 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18873 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18874 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18875 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18876 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18877 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18878 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
18879 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
18880 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
18881 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
18882 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
18883 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
18884 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
18885 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
18886 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
18887 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
18888 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
18889 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18890 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18891 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18892 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18893 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18894 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18895 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18896 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18897 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18898 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
18899 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18900 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18901 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18902 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18903 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18904 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18905 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18906 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18907 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18908 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18909 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18910 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18911 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18912 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18913 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18914 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18915 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18916 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18917 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18918 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18919 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18920 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18921 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18922 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18923 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18924 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18925 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18926 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18927 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18928 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18929 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18930 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18931 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18932 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18933 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18934 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18935 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18936 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18937 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18938 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18939 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18940 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
18941 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18942 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18943 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18944 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18945 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18946 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18947 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18948 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18949 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18950 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18951 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18952 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18953 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18954 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18955 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18956 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18957 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18958 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18959 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18960 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18961 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18962 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18963 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18964 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18965 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18966 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18967 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18968 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18969 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18970 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18971 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18972 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18973 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18974 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18975 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18976 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18977 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18978 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18979 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18980 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18981 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18982 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18983 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18984 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18985 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18986 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18987 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18988 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18989 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18990 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18991 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18992 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18993 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18994 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18995 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18996 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18997 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18998 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18999 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
19000 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19001 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19002 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19003 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
19004 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
19005 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
19006 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
19007 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
19008 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
19009 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19010 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19011 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19012 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19013 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 19014 | |
c921be7d NC |
19015 | #undef ARM_VARIANT |
19016 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
19017 | ||
21d799b5 NC |
19018 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
19019 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
19020 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
19021 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
19022 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
19023 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
19024 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19025 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19026 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19027 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19028 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19029 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19030 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19031 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19032 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19033 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19034 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19035 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19036 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19037 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19038 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
19039 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19040 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19041 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19042 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19043 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19044 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19045 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19046 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19047 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19048 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19049 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19050 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19051 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19052 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19053 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19054 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19055 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19056 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19057 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19058 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19059 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19060 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19061 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19062 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19063 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19064 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19065 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19066 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19067 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19068 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19069 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19070 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19071 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19072 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19073 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
19074 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 19075 | |
c921be7d NC |
19076 | #undef ARM_VARIANT |
19077 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
19078 | ||
21d799b5 NC |
19079 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
19080 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
19081 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
19082 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
19083 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
19084 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
19085 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
19086 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
19087 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
19088 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
19089 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
19090 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
19091 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
19092 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
19093 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
19094 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
19095 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
19096 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
19097 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
19098 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
19099 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
19100 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
19101 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
19102 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
19103 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
19104 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
19105 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
19106 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
19107 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
19108 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
19109 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
19110 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
19111 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
19112 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
19113 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
19114 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
19115 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
19116 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
19117 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
19118 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
19119 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
19120 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
19121 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
19122 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
19123 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
19124 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
19125 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
19126 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
19127 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
19128 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
19129 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
19130 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
19131 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
19132 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
19133 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
19134 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
19135 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
19136 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
19137 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
19138 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
19139 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
19140 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
19141 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
19142 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
19143 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19144 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
19145 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19146 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
19147 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19148 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
19149 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19150 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
19151 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
19152 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
19153 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
19154 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
19155 | }; |
19156 | #undef ARM_VARIANT | |
19157 | #undef THUMB_VARIANT | |
19158 | #undef TCE | |
19159 | #undef TCM | |
19160 | #undef TUE | |
19161 | #undef TUF | |
19162 | #undef TCC | |
8f06b2d8 | 19163 | #undef cCE |
e3cb604e PB |
19164 | #undef cCL |
19165 | #undef C3E | |
c19d1205 ZW |
19166 | #undef CE |
19167 | #undef CM | |
19168 | #undef UE | |
19169 | #undef UF | |
19170 | #undef UT | |
5287ad62 JB |
19171 | #undef NUF |
19172 | #undef nUF | |
19173 | #undef NCE | |
19174 | #undef nCE | |
c19d1205 ZW |
19175 | #undef OPS0 |
19176 | #undef OPS1 | |
19177 | #undef OPS2 | |
19178 | #undef OPS3 | |
19179 | #undef OPS4 | |
19180 | #undef OPS5 | |
19181 | #undef OPS6 | |
19182 | #undef do_0 | |
19183 | \f | |
19184 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 19185 | |
c19d1205 ZW |
19186 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
19187 | for use in the a.out file, and stores them in the array pointed to by buf. | |
19188 | This knows about the endian-ness of the target machine and does | |
19189 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
19190 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
19191 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 19192 | |
c19d1205 ZW |
19193 | void |
19194 | md_number_to_chars (char * buf, valueT val, int n) | |
19195 | { | |
19196 | if (target_big_endian) | |
19197 | number_to_chars_bigendian (buf, val, n); | |
19198 | else | |
19199 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
19200 | } |
19201 | ||
c19d1205 ZW |
19202 | static valueT |
19203 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 19204 | { |
c19d1205 ZW |
19205 | valueT result = 0; |
19206 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 19207 | |
c19d1205 | 19208 | if (target_big_endian) |
b99bd4ef | 19209 | { |
c19d1205 ZW |
19210 | while (n--) |
19211 | { | |
19212 | result <<= 8; | |
19213 | result |= (*where++ & 255); | |
19214 | } | |
b99bd4ef | 19215 | } |
c19d1205 | 19216 | else |
b99bd4ef | 19217 | { |
c19d1205 ZW |
19218 | while (n--) |
19219 | { | |
19220 | result <<= 8; | |
19221 | result |= (where[n] & 255); | |
19222 | } | |
bfae80f2 | 19223 | } |
b99bd4ef | 19224 | |
c19d1205 | 19225 | return result; |
bfae80f2 | 19226 | } |
b99bd4ef | 19227 | |
c19d1205 | 19228 | /* MD interface: Sections. */ |
b99bd4ef | 19229 | |
fa94de6b RM |
19230 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
19231 | that an rs_machine_dependent frag may reach. */ | |
19232 | ||
19233 | unsigned int | |
19234 | arm_frag_max_var (fragS *fragp) | |
19235 | { | |
19236 | /* We only use rs_machine_dependent for variable-size Thumb instructions, | |
19237 | which are either THUMB_SIZE (2) or INSN_SIZE (4). | |
19238 | ||
19239 | Note that we generate relaxable instructions even for cases that don't | |
19240 | really need it, like an immediate that's a trivial constant. So we're | |
19241 | overestimating the instruction size for some of those cases. Rather | |
19242 | than putting more intelligence here, it would probably be better to | |
19243 | avoid generating a relaxation frag in the first place when it can be | |
19244 | determined up front that a short instruction will suffice. */ | |
19245 | ||
19246 | gas_assert (fragp->fr_type == rs_machine_dependent); | |
19247 | return INSN_SIZE; | |
19248 | } | |
19249 | ||
0110f2b8 PB |
19250 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
19251 | 2 bytes. */ | |
19252 | ||
c19d1205 | 19253 | int |
0110f2b8 | 19254 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
19255 | segT segtype ATTRIBUTE_UNUSED) |
19256 | { | |
0110f2b8 PB |
19257 | fragp->fr_var = 2; |
19258 | return 2; | |
19259 | } | |
19260 | ||
19261 | /* Convert a machine dependent frag. */ | |
19262 | ||
19263 | void | |
19264 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
19265 | { | |
19266 | unsigned long insn; | |
19267 | unsigned long old_op; | |
19268 | char *buf; | |
19269 | expressionS exp; | |
19270 | fixS *fixp; | |
19271 | int reloc_type; | |
19272 | int pc_rel; | |
19273 | int opcode; | |
19274 | ||
19275 | buf = fragp->fr_literal + fragp->fr_fix; | |
19276 | ||
19277 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
19278 | if (fragp->fr_symbol) |
19279 | { | |
0110f2b8 PB |
19280 | exp.X_op = O_symbol; |
19281 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
19282 | } |
19283 | else | |
19284 | { | |
0110f2b8 | 19285 | exp.X_op = O_constant; |
5f4273c7 | 19286 | } |
0110f2b8 PB |
19287 | exp.X_add_number = fragp->fr_offset; |
19288 | opcode = fragp->fr_subtype; | |
19289 | switch (opcode) | |
19290 | { | |
19291 | case T_MNEM_ldr_pc: | |
19292 | case T_MNEM_ldr_pc2: | |
19293 | case T_MNEM_ldr_sp: | |
19294 | case T_MNEM_str_sp: | |
19295 | case T_MNEM_ldr: | |
19296 | case T_MNEM_ldrb: | |
19297 | case T_MNEM_ldrh: | |
19298 | case T_MNEM_str: | |
19299 | case T_MNEM_strb: | |
19300 | case T_MNEM_strh: | |
19301 | if (fragp->fr_var == 4) | |
19302 | { | |
5f4273c7 | 19303 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
19304 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
19305 | { | |
19306 | insn |= (old_op & 0x700) << 4; | |
19307 | } | |
19308 | else | |
19309 | { | |
19310 | insn |= (old_op & 7) << 12; | |
19311 | insn |= (old_op & 0x38) << 13; | |
19312 | } | |
19313 | insn |= 0x00000c00; | |
19314 | put_thumb32_insn (buf, insn); | |
19315 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
19316 | } | |
19317 | else | |
19318 | { | |
19319 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
19320 | } | |
19321 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
19322 | break; | |
19323 | case T_MNEM_adr: | |
19324 | if (fragp->fr_var == 4) | |
19325 | { | |
19326 | insn = THUMB_OP32 (opcode); | |
19327 | insn |= (old_op & 0xf0) << 4; | |
19328 | put_thumb32_insn (buf, insn); | |
19329 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
19330 | } | |
19331 | else | |
19332 | { | |
19333 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19334 | exp.X_add_number -= 4; | |
19335 | } | |
19336 | pc_rel = 1; | |
19337 | break; | |
19338 | case T_MNEM_mov: | |
19339 | case T_MNEM_movs: | |
19340 | case T_MNEM_cmp: | |
19341 | case T_MNEM_cmn: | |
19342 | if (fragp->fr_var == 4) | |
19343 | { | |
19344 | int r0off = (opcode == T_MNEM_mov | |
19345 | || opcode == T_MNEM_movs) ? 0 : 8; | |
19346 | insn = THUMB_OP32 (opcode); | |
19347 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
19348 | insn |= (old_op & 0x700) << r0off; | |
19349 | put_thumb32_insn (buf, insn); | |
19350 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
19351 | } | |
19352 | else | |
19353 | { | |
19354 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
19355 | } | |
19356 | pc_rel = 0; | |
19357 | break; | |
19358 | case T_MNEM_b: | |
19359 | if (fragp->fr_var == 4) | |
19360 | { | |
19361 | insn = THUMB_OP32(opcode); | |
19362 | put_thumb32_insn (buf, insn); | |
19363 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
19364 | } | |
19365 | else | |
19366 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
19367 | pc_rel = 1; | |
19368 | break; | |
19369 | case T_MNEM_bcond: | |
19370 | if (fragp->fr_var == 4) | |
19371 | { | |
19372 | insn = THUMB_OP32(opcode); | |
19373 | insn |= (old_op & 0xf00) << 14; | |
19374 | put_thumb32_insn (buf, insn); | |
19375 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
19376 | } | |
19377 | else | |
19378 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
19379 | pc_rel = 1; | |
19380 | break; | |
19381 | case T_MNEM_add_sp: | |
19382 | case T_MNEM_add_pc: | |
19383 | case T_MNEM_inc_sp: | |
19384 | case T_MNEM_dec_sp: | |
19385 | if (fragp->fr_var == 4) | |
19386 | { | |
19387 | /* ??? Choose between add and addw. */ | |
19388 | insn = THUMB_OP32 (opcode); | |
19389 | insn |= (old_op & 0xf0) << 4; | |
19390 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19391 | if (opcode == T_MNEM_add_pc) |
19392 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
19393 | else | |
19394 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
19395 | } |
19396 | else | |
19397 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19398 | pc_rel = 0; | |
19399 | break; | |
19400 | ||
19401 | case T_MNEM_addi: | |
19402 | case T_MNEM_addis: | |
19403 | case T_MNEM_subi: | |
19404 | case T_MNEM_subis: | |
19405 | if (fragp->fr_var == 4) | |
19406 | { | |
19407 | insn = THUMB_OP32 (opcode); | |
19408 | insn |= (old_op & 0xf0) << 4; | |
19409 | insn |= (old_op & 0xf) << 16; | |
19410 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19411 | if (insn & (1 << 20)) |
19412 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
19413 | else | |
19414 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
19415 | } |
19416 | else | |
19417 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19418 | pc_rel = 0; | |
19419 | break; | |
19420 | default: | |
5f4273c7 | 19421 | abort (); |
0110f2b8 PB |
19422 | } |
19423 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 19424 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
19425 | fixp->fx_file = fragp->fr_file; |
19426 | fixp->fx_line = fragp->fr_line; | |
19427 | fragp->fr_fix += fragp->fr_var; | |
19428 | } | |
19429 | ||
19430 | /* Return the size of a relaxable immediate operand instruction. | |
19431 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
19432 | static int | |
19433 | relax_immediate (fragS *fragp, int size, int shift) | |
19434 | { | |
19435 | offsetT offset; | |
19436 | offsetT mask; | |
19437 | offsetT low; | |
19438 | ||
19439 | /* ??? Should be able to do better than this. */ | |
19440 | if (fragp->fr_symbol) | |
19441 | return 4; | |
19442 | ||
19443 | low = (1 << shift) - 1; | |
19444 | mask = (1 << (shift + size)) - (1 << shift); | |
19445 | offset = fragp->fr_offset; | |
19446 | /* Force misaligned offsets to 32-bit variant. */ | |
19447 | if (offset & low) | |
5e77afaa | 19448 | return 4; |
0110f2b8 PB |
19449 | if (offset & ~mask) |
19450 | return 4; | |
19451 | return 2; | |
19452 | } | |
19453 | ||
5e77afaa PB |
19454 | /* Get the address of a symbol during relaxation. */ |
19455 | static addressT | |
5f4273c7 | 19456 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
19457 | { |
19458 | fragS *sym_frag; | |
19459 | addressT addr; | |
19460 | symbolS *sym; | |
19461 | ||
19462 | sym = fragp->fr_symbol; | |
19463 | sym_frag = symbol_get_frag (sym); | |
19464 | know (S_GET_SEGMENT (sym) != absolute_section | |
19465 | || sym_frag == &zero_address_frag); | |
19466 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
19467 | ||
19468 | /* If frag has yet to be reached on this pass, assume it will | |
19469 | move by STRETCH just as we did. If this is not so, it will | |
19470 | be because some frag between grows, and that will force | |
19471 | another pass. */ | |
19472 | ||
19473 | if (stretch != 0 | |
19474 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
19475 | { |
19476 | fragS *f; | |
19477 | ||
19478 | /* Adjust stretch for any alignment frag. Note that if have | |
19479 | been expanding the earlier code, the symbol may be | |
19480 | defined in what appears to be an earlier frag. FIXME: | |
19481 | This doesn't handle the fr_subtype field, which specifies | |
19482 | a maximum number of bytes to skip when doing an | |
19483 | alignment. */ | |
19484 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
19485 | { | |
19486 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
19487 | { | |
19488 | if (stretch < 0) | |
19489 | stretch = - ((- stretch) | |
19490 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
19491 | else | |
19492 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
19493 | if (stretch == 0) | |
19494 | break; | |
19495 | } | |
19496 | } | |
19497 | if (f != NULL) | |
19498 | addr += stretch; | |
19499 | } | |
5e77afaa PB |
19500 | |
19501 | return addr; | |
19502 | } | |
19503 | ||
0110f2b8 PB |
19504 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
19505 | load. */ | |
19506 | static int | |
5e77afaa | 19507 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
19508 | { |
19509 | addressT addr; | |
19510 | offsetT val; | |
19511 | ||
19512 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
19513 | if (fragp->fr_symbol == NULL |
19514 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
19515 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19516 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19517 | return 4; |
19518 | ||
5f4273c7 | 19519 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19520 | addr = fragp->fr_address + fragp->fr_fix; |
19521 | addr = (addr + 4) & ~3; | |
5e77afaa | 19522 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 19523 | if (val & 3) |
5e77afaa | 19524 | return 4; |
0110f2b8 PB |
19525 | val -= addr; |
19526 | if (val < 0 || val > 1020) | |
19527 | return 4; | |
19528 | return 2; | |
19529 | } | |
19530 | ||
19531 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
19532 | static int | |
19533 | relax_addsub (fragS *fragp, asection *sec) | |
19534 | { | |
19535 | char *buf; | |
19536 | int op; | |
19537 | ||
19538 | buf = fragp->fr_literal + fragp->fr_fix; | |
19539 | op = bfd_get_16(sec->owner, buf); | |
19540 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
19541 | return relax_immediate (fragp, 8, 0); | |
19542 | else | |
19543 | return relax_immediate (fragp, 3, 0); | |
19544 | } | |
19545 | ||
19546 | ||
19547 | /* Return the size of a relaxable branch instruction. BITS is the | |
19548 | size of the offset field in the narrow instruction. */ | |
19549 | ||
19550 | static int | |
5e77afaa | 19551 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
19552 | { |
19553 | addressT addr; | |
19554 | offsetT val; | |
19555 | offsetT limit; | |
19556 | ||
19557 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 19558 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
19559 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19560 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19561 | return 4; |
19562 | ||
267bf995 RR |
19563 | #ifdef OBJ_ELF |
19564 | if (S_IS_DEFINED (fragp->fr_symbol) | |
19565 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
19566 | return 4; | |
0d9b4b55 NC |
19567 | |
19568 | /* PR 12532. Global symbols with default visibility might | |
19569 | be preempted, so do not relax relocations to them. */ | |
19570 | if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT) | |
19571 | && (! S_IS_LOCAL (fragp->fr_symbol))) | |
19572 | return 4; | |
267bf995 RR |
19573 | #endif |
19574 | ||
5f4273c7 | 19575 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19576 | addr = fragp->fr_address + fragp->fr_fix + 4; |
19577 | val -= addr; | |
19578 | ||
19579 | /* Offset is a signed value *2 */ | |
19580 | limit = 1 << bits; | |
19581 | if (val >= limit || val < -limit) | |
19582 | return 4; | |
19583 | return 2; | |
19584 | } | |
19585 | ||
19586 | ||
19587 | /* Relax a machine dependent frag. This returns the amount by which | |
19588 | the current size of the frag should change. */ | |
19589 | ||
19590 | int | |
5e77afaa | 19591 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
19592 | { |
19593 | int oldsize; | |
19594 | int newsize; | |
19595 | ||
19596 | oldsize = fragp->fr_var; | |
19597 | switch (fragp->fr_subtype) | |
19598 | { | |
19599 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 19600 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19601 | break; |
19602 | case T_MNEM_ldr_pc: | |
19603 | case T_MNEM_ldr_sp: | |
19604 | case T_MNEM_str_sp: | |
5f4273c7 | 19605 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
19606 | break; |
19607 | case T_MNEM_ldr: | |
19608 | case T_MNEM_str: | |
5f4273c7 | 19609 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
19610 | break; |
19611 | case T_MNEM_ldrh: | |
19612 | case T_MNEM_strh: | |
5f4273c7 | 19613 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
19614 | break; |
19615 | case T_MNEM_ldrb: | |
19616 | case T_MNEM_strb: | |
5f4273c7 | 19617 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
19618 | break; |
19619 | case T_MNEM_adr: | |
5f4273c7 | 19620 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19621 | break; |
19622 | case T_MNEM_mov: | |
19623 | case T_MNEM_movs: | |
19624 | case T_MNEM_cmp: | |
19625 | case T_MNEM_cmn: | |
5f4273c7 | 19626 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
19627 | break; |
19628 | case T_MNEM_b: | |
5f4273c7 | 19629 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
19630 | break; |
19631 | case T_MNEM_bcond: | |
5f4273c7 | 19632 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
19633 | break; |
19634 | case T_MNEM_add_sp: | |
19635 | case T_MNEM_add_pc: | |
19636 | newsize = relax_immediate (fragp, 8, 2); | |
19637 | break; | |
19638 | case T_MNEM_inc_sp: | |
19639 | case T_MNEM_dec_sp: | |
19640 | newsize = relax_immediate (fragp, 7, 2); | |
19641 | break; | |
19642 | case T_MNEM_addi: | |
19643 | case T_MNEM_addis: | |
19644 | case T_MNEM_subi: | |
19645 | case T_MNEM_subis: | |
19646 | newsize = relax_addsub (fragp, sec); | |
19647 | break; | |
19648 | default: | |
5f4273c7 | 19649 | abort (); |
0110f2b8 | 19650 | } |
5e77afaa PB |
19651 | |
19652 | fragp->fr_var = newsize; | |
19653 | /* Freeze wide instructions that are at or before the same location as | |
19654 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
19655 | Don't freeze them unconditionally because targets may be artificially |
19656 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 19657 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 19658 | { |
0110f2b8 | 19659 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 19660 | frag_wane (fragp); |
0110f2b8 | 19661 | } |
5e77afaa | 19662 | |
0110f2b8 | 19663 | return newsize - oldsize; |
c19d1205 | 19664 | } |
b99bd4ef | 19665 | |
c19d1205 | 19666 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 19667 | |
c19d1205 ZW |
19668 | valueT |
19669 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
19670 | valueT size) | |
19671 | { | |
f0927246 NC |
19672 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
19673 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
19674 | { | |
19675 | /* For a.out, force the section size to be aligned. If we don't do | |
19676 | this, BFD will align it for us, but it will not write out the | |
19677 | final bytes of the section. This may be a bug in BFD, but it is | |
19678 | easier to fix it here since that is how the other a.out targets | |
19679 | work. */ | |
19680 | int align; | |
19681 | ||
19682 | align = bfd_get_section_alignment (stdoutput, segment); | |
19683 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
19684 | } | |
c19d1205 | 19685 | #endif |
f0927246 NC |
19686 | |
19687 | return size; | |
bfae80f2 | 19688 | } |
b99bd4ef | 19689 | |
c19d1205 ZW |
19690 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
19691 | of an rs_align_code fragment. */ | |
19692 | ||
19693 | void | |
19694 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 19695 | { |
e7495e45 NS |
19696 | static char const arm_noop[2][2][4] = |
19697 | { | |
19698 | { /* ARMv1 */ | |
19699 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
19700 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
19701 | }, | |
19702 | { /* ARMv6k */ | |
19703 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
19704 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
19705 | }, | |
19706 | }; | |
19707 | static char const thumb_noop[2][2][2] = | |
19708 | { | |
19709 | { /* Thumb-1 */ | |
19710 | {0xc0, 0x46}, /* LE */ | |
19711 | {0x46, 0xc0}, /* BE */ | |
19712 | }, | |
19713 | { /* Thumb-2 */ | |
19714 | {0x00, 0xbf}, /* LE */ | |
19715 | {0xbf, 0x00} /* BE */ | |
19716 | } | |
19717 | }; | |
19718 | static char const wide_thumb_noop[2][4] = | |
19719 | { /* Wide Thumb-2 */ | |
19720 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
19721 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
19722 | }; | |
c921be7d | 19723 | |
e7495e45 | 19724 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
19725 | char * p; |
19726 | const char * noop; | |
e7495e45 | 19727 | const char *narrow_noop = NULL; |
cd000bff DJ |
19728 | #ifdef OBJ_ELF |
19729 | enum mstate state; | |
19730 | #endif | |
bfae80f2 | 19731 | |
c19d1205 | 19732 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
19733 | return; |
19734 | ||
c19d1205 ZW |
19735 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
19736 | p = fragP->fr_literal + fragP->fr_fix; | |
19737 | fix = 0; | |
bfae80f2 | 19738 | |
c19d1205 ZW |
19739 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
19740 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 19741 | |
cd000bff | 19742 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 19743 | |
cd000bff | 19744 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 19745 | { |
e7495e45 NS |
19746 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
19747 | { | |
19748 | narrow_noop = thumb_noop[1][target_big_endian]; | |
19749 | noop = wide_thumb_noop[target_big_endian]; | |
19750 | } | |
c19d1205 | 19751 | else |
e7495e45 NS |
19752 | noop = thumb_noop[0][target_big_endian]; |
19753 | noop_size = 2; | |
cd000bff DJ |
19754 | #ifdef OBJ_ELF |
19755 | state = MAP_THUMB; | |
19756 | #endif | |
7ed4c4c5 NC |
19757 | } |
19758 | else | |
19759 | { | |
e7495e45 NS |
19760 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
19761 | [target_big_endian]; | |
19762 | noop_size = 4; | |
cd000bff DJ |
19763 | #ifdef OBJ_ELF |
19764 | state = MAP_ARM; | |
19765 | #endif | |
7ed4c4c5 | 19766 | } |
c921be7d | 19767 | |
e7495e45 | 19768 | fragP->fr_var = noop_size; |
c921be7d | 19769 | |
c19d1205 | 19770 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 19771 | { |
c19d1205 | 19772 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
19773 | #ifdef OBJ_ELF |
19774 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
19775 | #endif | |
c19d1205 ZW |
19776 | memset (p, 0, fix); |
19777 | p += fix; | |
19778 | bytes -= fix; | |
a737bd4d | 19779 | } |
a737bd4d | 19780 | |
e7495e45 NS |
19781 | if (narrow_noop) |
19782 | { | |
19783 | if (bytes & noop_size) | |
19784 | { | |
19785 | /* Insert a narrow noop. */ | |
19786 | memcpy (p, narrow_noop, noop_size); | |
19787 | p += noop_size; | |
19788 | bytes -= noop_size; | |
19789 | fix += noop_size; | |
19790 | } | |
19791 | ||
19792 | /* Use wide noops for the remainder */ | |
19793 | noop_size = 4; | |
19794 | } | |
19795 | ||
c19d1205 | 19796 | while (bytes >= noop_size) |
a737bd4d | 19797 | { |
c19d1205 ZW |
19798 | memcpy (p, noop, noop_size); |
19799 | p += noop_size; | |
19800 | bytes -= noop_size; | |
19801 | fix += noop_size; | |
a737bd4d NC |
19802 | } |
19803 | ||
c19d1205 | 19804 | fragP->fr_fix += fix; |
a737bd4d NC |
19805 | } |
19806 | ||
c19d1205 ZW |
19807 | /* Called from md_do_align. Used to create an alignment |
19808 | frag in a code section. */ | |
19809 | ||
19810 | void | |
19811 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 19812 | { |
c19d1205 | 19813 | char * p; |
7ed4c4c5 | 19814 | |
c19d1205 | 19815 | /* We assume that there will never be a requirement |
6ec8e702 | 19816 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 19817 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
19818 | { |
19819 | char err_msg[128]; | |
19820 | ||
fa94de6b | 19821 | sprintf (err_msg, |
6ec8e702 NC |
19822 | _("alignments greater than %d bytes not supported in .text sections."), |
19823 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 19824 | as_fatal ("%s", err_msg); |
6ec8e702 | 19825 | } |
bfae80f2 | 19826 | |
c19d1205 ZW |
19827 | p = frag_var (rs_align_code, |
19828 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
19829 | 1, | |
19830 | (relax_substateT) max, | |
19831 | (symbolS *) NULL, | |
19832 | (offsetT) n, | |
19833 | (char *) NULL); | |
19834 | *p = 0; | |
19835 | } | |
bfae80f2 | 19836 | |
8dc2430f NC |
19837 | /* Perform target specific initialisation of a frag. |
19838 | Note - despite the name this initialisation is not done when the frag | |
19839 | is created, but only when its type is assigned. A frag can be created | |
19840 | and used a long time before its type is set, so beware of assuming that | |
19841 | this initialisationis performed first. */ | |
bfae80f2 | 19842 | |
cd000bff DJ |
19843 | #ifndef OBJ_ELF |
19844 | void | |
19845 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
19846 | { | |
19847 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 19848 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
19849 | } |
19850 | ||
19851 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 19852 | void |
cd000bff | 19853 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 19854 | { |
8dc2430f NC |
19855 | /* If the current ARM vs THUMB mode has not already |
19856 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
19857 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
19858 | { | |
19859 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
19860 | ||
19861 | /* Record a mapping symbol for alignment frags. We will delete this | |
19862 | later if the alignment ends up empty. */ | |
19863 | switch (fragP->fr_type) | |
19864 | { | |
19865 | case rs_align: | |
19866 | case rs_align_test: | |
19867 | case rs_fill: | |
19868 | mapping_state_2 (MAP_DATA, max_chars); | |
19869 | break; | |
19870 | case rs_align_code: | |
19871 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
19872 | break; | |
19873 | default: | |
19874 | break; | |
19875 | } | |
19876 | } | |
bfae80f2 RE |
19877 | } |
19878 | ||
c19d1205 ZW |
19879 | /* When we change sections we need to issue a new mapping symbol. */ |
19880 | ||
19881 | void | |
19882 | arm_elf_change_section (void) | |
bfae80f2 | 19883 | { |
c19d1205 ZW |
19884 | /* Link an unlinked unwind index table section to the .text section. */ |
19885 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
19886 | && elf_linked_to_section (now_seg) == NULL) | |
19887 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
19888 | } |
19889 | ||
c19d1205 ZW |
19890 | int |
19891 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 19892 | { |
c19d1205 ZW |
19893 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
19894 | return SHT_ARM_EXIDX; | |
e45d0630 | 19895 | |
c19d1205 ZW |
19896 | return -1; |
19897 | } | |
19898 | \f | |
19899 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 19900 | |
c19d1205 | 19901 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 19902 | |
5f4273c7 | 19903 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 19904 | |
bfae80f2 | 19905 | static void |
c19d1205 | 19906 | flush_pending_unwind (void) |
bfae80f2 | 19907 | { |
c19d1205 | 19908 | offsetT offset; |
bfae80f2 | 19909 | |
c19d1205 ZW |
19910 | offset = unwind.pending_offset; |
19911 | unwind.pending_offset = 0; | |
19912 | if (offset != 0) | |
19913 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
19914 | } |
19915 | ||
c19d1205 ZW |
19916 | /* Add an opcode to this list for this function. Two-byte opcodes should |
19917 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
19918 | order. */ | |
19919 | ||
bfae80f2 | 19920 | static void |
c19d1205 | 19921 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 19922 | { |
c19d1205 ZW |
19923 | /* Add any deferred stack adjustment. */ |
19924 | if (unwind.pending_offset) | |
19925 | flush_pending_unwind (); | |
bfae80f2 | 19926 | |
c19d1205 | 19927 | unwind.sp_restored = 0; |
bfae80f2 | 19928 | |
c19d1205 | 19929 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 19930 | { |
c19d1205 ZW |
19931 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
19932 | if (unwind.opcodes) | |
21d799b5 NC |
19933 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
19934 | unwind.opcode_alloc); | |
c19d1205 | 19935 | else |
21d799b5 | 19936 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 19937 | } |
c19d1205 | 19938 | while (length > 0) |
bfae80f2 | 19939 | { |
c19d1205 ZW |
19940 | length--; |
19941 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
19942 | op >>= 8; | |
19943 | unwind.opcode_count++; | |
bfae80f2 | 19944 | } |
bfae80f2 RE |
19945 | } |
19946 | ||
c19d1205 ZW |
19947 | /* Add unwind opcodes to adjust the stack pointer. */ |
19948 | ||
bfae80f2 | 19949 | static void |
c19d1205 | 19950 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 19951 | { |
c19d1205 | 19952 | valueT op; |
bfae80f2 | 19953 | |
c19d1205 | 19954 | if (offset > 0x200) |
bfae80f2 | 19955 | { |
c19d1205 ZW |
19956 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
19957 | char bytes[5]; | |
19958 | int n; | |
19959 | valueT o; | |
bfae80f2 | 19960 | |
c19d1205 ZW |
19961 | /* Long form: 0xb2, uleb128. */ |
19962 | /* This might not fit in a word so add the individual bytes, | |
19963 | remembering the list is built in reverse order. */ | |
19964 | o = (valueT) ((offset - 0x204) >> 2); | |
19965 | if (o == 0) | |
19966 | add_unwind_opcode (0, 1); | |
bfae80f2 | 19967 | |
c19d1205 ZW |
19968 | /* Calculate the uleb128 encoding of the offset. */ |
19969 | n = 0; | |
19970 | while (o) | |
19971 | { | |
19972 | bytes[n] = o & 0x7f; | |
19973 | o >>= 7; | |
19974 | if (o) | |
19975 | bytes[n] |= 0x80; | |
19976 | n++; | |
19977 | } | |
19978 | /* Add the insn. */ | |
19979 | for (; n; n--) | |
19980 | add_unwind_opcode (bytes[n - 1], 1); | |
19981 | add_unwind_opcode (0xb2, 1); | |
19982 | } | |
19983 | else if (offset > 0x100) | |
bfae80f2 | 19984 | { |
c19d1205 ZW |
19985 | /* Two short opcodes. */ |
19986 | add_unwind_opcode (0x3f, 1); | |
19987 | op = (offset - 0x104) >> 2; | |
19988 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19989 | } |
c19d1205 ZW |
19990 | else if (offset > 0) |
19991 | { | |
19992 | /* Short opcode. */ | |
19993 | op = (offset - 4) >> 2; | |
19994 | add_unwind_opcode (op, 1); | |
19995 | } | |
19996 | else if (offset < 0) | |
bfae80f2 | 19997 | { |
c19d1205 ZW |
19998 | offset = -offset; |
19999 | while (offset > 0x100) | |
bfae80f2 | 20000 | { |
c19d1205 ZW |
20001 | add_unwind_opcode (0x7f, 1); |
20002 | offset -= 0x100; | |
bfae80f2 | 20003 | } |
c19d1205 ZW |
20004 | op = ((offset - 4) >> 2) | 0x40; |
20005 | add_unwind_opcode (op, 1); | |
bfae80f2 | 20006 | } |
bfae80f2 RE |
20007 | } |
20008 | ||
c19d1205 ZW |
20009 | /* Finish the list of unwind opcodes for this function. */ |
20010 | static void | |
20011 | finish_unwind_opcodes (void) | |
bfae80f2 | 20012 | { |
c19d1205 | 20013 | valueT op; |
bfae80f2 | 20014 | |
c19d1205 | 20015 | if (unwind.fp_used) |
bfae80f2 | 20016 | { |
708587a4 | 20017 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
20018 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
20019 | flush_pending_unwind (); | |
bfae80f2 | 20020 | |
c19d1205 ZW |
20021 | /* After restoring sp from the frame pointer. */ |
20022 | op = 0x90 | unwind.fp_reg; | |
20023 | add_unwind_opcode (op, 1); | |
20024 | } | |
20025 | else | |
20026 | flush_pending_unwind (); | |
bfae80f2 RE |
20027 | } |
20028 | ||
bfae80f2 | 20029 | |
c19d1205 ZW |
20030 | /* Start an exception table entry. If idx is nonzero this is an index table |
20031 | entry. */ | |
bfae80f2 RE |
20032 | |
20033 | static void | |
c19d1205 | 20034 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 20035 | { |
c19d1205 ZW |
20036 | const char * text_name; |
20037 | const char * prefix; | |
20038 | const char * prefix_once; | |
20039 | const char * group_name; | |
20040 | size_t prefix_len; | |
20041 | size_t text_len; | |
20042 | char * sec_name; | |
20043 | size_t sec_name_len; | |
20044 | int type; | |
20045 | int flags; | |
20046 | int linkonce; | |
bfae80f2 | 20047 | |
c19d1205 | 20048 | if (idx) |
bfae80f2 | 20049 | { |
c19d1205 ZW |
20050 | prefix = ELF_STRING_ARM_unwind; |
20051 | prefix_once = ELF_STRING_ARM_unwind_once; | |
20052 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 20053 | } |
c19d1205 | 20054 | else |
bfae80f2 | 20055 | { |
c19d1205 ZW |
20056 | prefix = ELF_STRING_ARM_unwind_info; |
20057 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
20058 | type = SHT_PROGBITS; | |
bfae80f2 RE |
20059 | } |
20060 | ||
c19d1205 ZW |
20061 | text_name = segment_name (text_seg); |
20062 | if (streq (text_name, ".text")) | |
20063 | text_name = ""; | |
20064 | ||
20065 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
20066 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 20067 | { |
c19d1205 ZW |
20068 | prefix = prefix_once; |
20069 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
20070 | } |
20071 | ||
c19d1205 ZW |
20072 | prefix_len = strlen (prefix); |
20073 | text_len = strlen (text_name); | |
20074 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 20075 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
20076 | memcpy (sec_name, prefix, prefix_len); |
20077 | memcpy (sec_name + prefix_len, text_name, text_len); | |
20078 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 20079 | |
c19d1205 ZW |
20080 | flags = SHF_ALLOC; |
20081 | linkonce = 0; | |
20082 | group_name = 0; | |
bfae80f2 | 20083 | |
c19d1205 ZW |
20084 | /* Handle COMDAT group. */ |
20085 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 20086 | { |
c19d1205 ZW |
20087 | group_name = elf_group_name (text_seg); |
20088 | if (group_name == NULL) | |
20089 | { | |
bd3ba5d1 | 20090 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
20091 | segment_name (text_seg)); |
20092 | ignore_rest_of_line (); | |
20093 | return; | |
20094 | } | |
20095 | flags |= SHF_GROUP; | |
20096 | linkonce = 1; | |
bfae80f2 RE |
20097 | } |
20098 | ||
c19d1205 | 20099 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 20100 | |
5f4273c7 | 20101 | /* Set the section link for index tables. */ |
c19d1205 ZW |
20102 | if (idx) |
20103 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
20104 | } |
20105 | ||
bfae80f2 | 20106 | |
c19d1205 ZW |
20107 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
20108 | personality routine data. Returns zero, or the index table value for | |
20109 | and inline entry. */ | |
20110 | ||
20111 | static valueT | |
20112 | create_unwind_entry (int have_data) | |
bfae80f2 | 20113 | { |
c19d1205 ZW |
20114 | int size; |
20115 | addressT where; | |
20116 | char *ptr; | |
20117 | /* The current word of data. */ | |
20118 | valueT data; | |
20119 | /* The number of bytes left in this word. */ | |
20120 | int n; | |
bfae80f2 | 20121 | |
c19d1205 | 20122 | finish_unwind_opcodes (); |
bfae80f2 | 20123 | |
c19d1205 ZW |
20124 | /* Remember the current text section. */ |
20125 | unwind.saved_seg = now_seg; | |
20126 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 20127 | |
c19d1205 | 20128 | start_unwind_section (now_seg, 0); |
bfae80f2 | 20129 | |
c19d1205 | 20130 | if (unwind.personality_routine == NULL) |
bfae80f2 | 20131 | { |
c19d1205 ZW |
20132 | if (unwind.personality_index == -2) |
20133 | { | |
20134 | if (have_data) | |
5f4273c7 | 20135 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
20136 | return 1; /* EXIDX_CANTUNWIND. */ |
20137 | } | |
bfae80f2 | 20138 | |
c19d1205 ZW |
20139 | /* Use a default personality routine if none is specified. */ |
20140 | if (unwind.personality_index == -1) | |
20141 | { | |
20142 | if (unwind.opcode_count > 3) | |
20143 | unwind.personality_index = 1; | |
20144 | else | |
20145 | unwind.personality_index = 0; | |
20146 | } | |
bfae80f2 | 20147 | |
c19d1205 ZW |
20148 | /* Space for the personality routine entry. */ |
20149 | if (unwind.personality_index == 0) | |
20150 | { | |
20151 | if (unwind.opcode_count > 3) | |
20152 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 20153 | |
c19d1205 ZW |
20154 | if (!have_data) |
20155 | { | |
20156 | /* All the data is inline in the index table. */ | |
20157 | data = 0x80; | |
20158 | n = 3; | |
20159 | while (unwind.opcode_count > 0) | |
20160 | { | |
20161 | unwind.opcode_count--; | |
20162 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
20163 | n--; | |
20164 | } | |
bfae80f2 | 20165 | |
c19d1205 ZW |
20166 | /* Pad with "finish" opcodes. */ |
20167 | while (n--) | |
20168 | data = (data << 8) | 0xb0; | |
bfae80f2 | 20169 | |
c19d1205 ZW |
20170 | return data; |
20171 | } | |
20172 | size = 0; | |
20173 | } | |
20174 | else | |
20175 | /* We get two opcodes "free" in the first word. */ | |
20176 | size = unwind.opcode_count - 2; | |
20177 | } | |
20178 | else | |
5011093d NC |
20179 | { |
20180 | gas_assert (unwind.personality_index == -1); | |
20181 | ||
20182 | /* An extra byte is required for the opcode count. */ | |
20183 | size = unwind.opcode_count + 1; | |
20184 | } | |
bfae80f2 | 20185 | |
c19d1205 ZW |
20186 | size = (size + 3) >> 2; |
20187 | if (size > 0xff) | |
20188 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 20189 | |
c19d1205 ZW |
20190 | frag_align (2, 0, 0); |
20191 | record_alignment (now_seg, 2); | |
20192 | unwind.table_entry = expr_build_dot (); | |
20193 | ||
20194 | /* Allocate the table entry. */ | |
20195 | ptr = frag_more ((size << 2) + 4); | |
74929e7b NC |
20196 | /* PR 13449: Zero the table entries in case some of them are not used. */ |
20197 | memset (ptr, 0, (size << 2) + 4); | |
c19d1205 | 20198 | where = frag_now_fix () - ((size << 2) + 4); |
bfae80f2 | 20199 | |
c19d1205 | 20200 | switch (unwind.personality_index) |
bfae80f2 | 20201 | { |
c19d1205 ZW |
20202 | case -1: |
20203 | /* ??? Should this be a PLT generating relocation? */ | |
20204 | /* Custom personality routine. */ | |
20205 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
20206 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 20207 | |
c19d1205 ZW |
20208 | where += 4; |
20209 | ptr += 4; | |
bfae80f2 | 20210 | |
c19d1205 | 20211 | /* Set the first byte to the number of additional words. */ |
5011093d | 20212 | data = size > 0 ? size - 1 : 0; |
c19d1205 ZW |
20213 | n = 3; |
20214 | break; | |
bfae80f2 | 20215 | |
c19d1205 ZW |
20216 | /* ABI defined personality routines. */ |
20217 | case 0: | |
20218 | /* Three opcodes bytes are packed into the first word. */ | |
20219 | data = 0x80; | |
20220 | n = 3; | |
20221 | break; | |
bfae80f2 | 20222 | |
c19d1205 ZW |
20223 | case 1: |
20224 | case 2: | |
20225 | /* The size and first two opcode bytes go in the first word. */ | |
20226 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
20227 | n = 2; | |
20228 | break; | |
bfae80f2 | 20229 | |
c19d1205 ZW |
20230 | default: |
20231 | /* Should never happen. */ | |
20232 | abort (); | |
20233 | } | |
bfae80f2 | 20234 | |
c19d1205 ZW |
20235 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
20236 | time. */ | |
20237 | while (unwind.opcode_count > 0) | |
20238 | { | |
20239 | if (n == 0) | |
20240 | { | |
20241 | md_number_to_chars (ptr, data, 4); | |
20242 | ptr += 4; | |
20243 | n = 4; | |
20244 | data = 0; | |
20245 | } | |
20246 | unwind.opcode_count--; | |
20247 | n--; | |
20248 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
20249 | } | |
20250 | ||
20251 | /* Finish off the last word. */ | |
20252 | if (n < 4) | |
20253 | { | |
20254 | /* Pad with "finish" opcodes. */ | |
20255 | while (n--) | |
20256 | data = (data << 8) | 0xb0; | |
20257 | ||
20258 | md_number_to_chars (ptr, data, 4); | |
20259 | } | |
20260 | ||
20261 | if (!have_data) | |
20262 | { | |
20263 | /* Add an empty descriptor if there is no user-specified data. */ | |
20264 | ptr = frag_more (4); | |
20265 | md_number_to_chars (ptr, 0, 4); | |
20266 | } | |
20267 | ||
20268 | return 0; | |
bfae80f2 RE |
20269 | } |
20270 | ||
f0927246 NC |
20271 | |
20272 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
20273 | ||
20274 | void | |
20275 | tc_arm_frame_initial_instructions (void) | |
20276 | { | |
20277 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
20278 | } | |
20279 | #endif /* OBJ_ELF */ | |
20280 | ||
c19d1205 ZW |
20281 | /* Convert REGNAME to a DWARF-2 register number. */ |
20282 | ||
20283 | int | |
1df69f4f | 20284 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 20285 | { |
1df69f4f | 20286 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
20287 | |
20288 | if (reg == FAIL) | |
20289 | return -1; | |
20290 | ||
20291 | return reg; | |
bfae80f2 RE |
20292 | } |
20293 | ||
f0927246 | 20294 | #ifdef TE_PE |
c19d1205 | 20295 | void |
f0927246 | 20296 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 20297 | { |
91d6fa6a | 20298 | expressionS exp; |
bfae80f2 | 20299 | |
91d6fa6a NC |
20300 | exp.X_op = O_secrel; |
20301 | exp.X_add_symbol = symbol; | |
20302 | exp.X_add_number = 0; | |
20303 | emit_expr (&exp, size); | |
f0927246 NC |
20304 | } |
20305 | #endif | |
bfae80f2 | 20306 | |
c19d1205 | 20307 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 20308 | |
2fc8bdac ZW |
20309 | /* Return the address within the segment that a PC-relative fixup is |
20310 | relative to. For ARM, PC-relative fixups applied to instructions | |
20311 | are generally relative to the location of the fixup plus 8 bytes. | |
20312 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
20313 | require special handling. */ | |
bfae80f2 | 20314 | |
c19d1205 | 20315 | long |
2fc8bdac | 20316 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 20317 | { |
2fc8bdac ZW |
20318 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
20319 | ||
20320 | /* If this is pc-relative and we are going to emit a relocation | |
20321 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
20322 | will need. Otherwise we want to use the calculated base. |
20323 | For WinCE we skip the bias for externals as well, since this | |
20324 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 20325 | if (fixP->fx_pcrel |
2fc8bdac | 20326 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
20327 | || (arm_force_relocation (fixP) |
20328 | #ifdef TE_WINCE | |
20329 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20330 | #endif | |
20331 | ))) | |
2fc8bdac | 20332 | base = 0; |
bfae80f2 | 20333 | |
267bf995 | 20334 | |
c19d1205 | 20335 | switch (fixP->fx_r_type) |
bfae80f2 | 20336 | { |
2fc8bdac ZW |
20337 | /* PC relative addressing on the Thumb is slightly odd as the |
20338 | bottom two bits of the PC are forced to zero for the | |
20339 | calculation. This happens *after* application of the | |
20340 | pipeline offset. However, Thumb adrl already adjusts for | |
20341 | this, so we need not do it again. */ | |
c19d1205 | 20342 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 20343 | return base & ~3; |
c19d1205 ZW |
20344 | |
20345 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
20346 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 20347 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 20348 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 20349 | return (base + 4) & ~3; |
c19d1205 | 20350 | |
2fc8bdac ZW |
20351 | /* Thumb branches are simply offset by +4. */ |
20352 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
20353 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
20354 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
20355 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 20356 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 20357 | return base + 4; |
bfae80f2 | 20358 | |
267bf995 | 20359 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
20360 | if (fixP->fx_addsy |
20361 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20362 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20363 | && ARM_IS_FUNC (fixP->fx_addsy) |
20364 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20365 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
20366 | return base + 4; | |
20367 | ||
00adf2d4 JB |
20368 | /* BLX is like branches above, but forces the low two bits of PC to |
20369 | zero. */ | |
486499d0 CL |
20370 | case BFD_RELOC_THUMB_PCREL_BLX: |
20371 | if (fixP->fx_addsy | |
20372 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20373 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20374 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20375 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20376 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
20377 | return (base + 4) & ~3; |
20378 | ||
2fc8bdac ZW |
20379 | /* ARM mode branches are offset by +8. However, the Windows CE |
20380 | loader expects the relocation not to take this into account. */ | |
267bf995 | 20381 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
20382 | if (fixP->fx_addsy |
20383 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20384 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20385 | && ARM_IS_FUNC (fixP->fx_addsy) |
20386 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20387 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20388 | return base + 8; |
267bf995 | 20389 | |
486499d0 CL |
20390 | case BFD_RELOC_ARM_PCREL_CALL: |
20391 | if (fixP->fx_addsy | |
20392 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20393 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20394 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20395 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20396 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20397 | return base + 8; |
267bf995 | 20398 | |
2fc8bdac | 20399 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 20400 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 20401 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20402 | #ifdef TE_WINCE |
5f4273c7 | 20403 | /* When handling fixups immediately, because we have already |
53baae48 NC |
20404 | discovered the value of a symbol, or the address of the frag involved |
20405 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
20406 | see fixup_segment() in write.c | |
20407 | The S_IS_EXTERNAL test handles the case of global symbols. | |
20408 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
20409 | if (fixP->fx_pcrel | |
20410 | && fixP->fx_addsy != NULL | |
20411 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20412 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
20413 | return base + 8; | |
2fc8bdac | 20414 | return base; |
c19d1205 | 20415 | #else |
2fc8bdac | 20416 | return base + 8; |
c19d1205 | 20417 | #endif |
2fc8bdac | 20418 | |
267bf995 | 20419 | |
2fc8bdac ZW |
20420 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
20421 | branches, the Windows CE loader *does* expect the relocation | |
20422 | to take this into account. */ | |
20423 | case BFD_RELOC_ARM_OFFSET_IMM: | |
20424 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
20425 | case BFD_RELOC_ARM_HWLITERAL: | |
20426 | case BFD_RELOC_ARM_LITERAL: | |
20427 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
20428 | return base + 8; | |
20429 | ||
20430 | ||
20431 | /* Other PC-relative relocations are un-offset. */ | |
20432 | default: | |
20433 | return base; | |
20434 | } | |
bfae80f2 RE |
20435 | } |
20436 | ||
c19d1205 ZW |
20437 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
20438 | Otherwise we have no need to default values of symbols. */ | |
20439 | ||
20440 | symbolS * | |
20441 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 20442 | { |
c19d1205 ZW |
20443 | #ifdef OBJ_ELF |
20444 | if (name[0] == '_' && name[1] == 'G' | |
20445 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
20446 | { | |
20447 | if (!GOT_symbol) | |
20448 | { | |
20449 | if (symbol_find (name)) | |
bd3ba5d1 | 20450 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 20451 | |
c19d1205 ZW |
20452 | GOT_symbol = symbol_new (name, undefined_section, |
20453 | (valueT) 0, & zero_address_frag); | |
20454 | } | |
bfae80f2 | 20455 | |
c19d1205 | 20456 | return GOT_symbol; |
bfae80f2 | 20457 | } |
c19d1205 | 20458 | #endif |
bfae80f2 | 20459 | |
c921be7d | 20460 | return NULL; |
bfae80f2 RE |
20461 | } |
20462 | ||
55cf6793 | 20463 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
20464 | computed as two separate immediate values, added together. We |
20465 | already know that this value cannot be computed by just one ARM | |
20466 | instruction. */ | |
20467 | ||
20468 | static unsigned int | |
20469 | validate_immediate_twopart (unsigned int val, | |
20470 | unsigned int * highpart) | |
bfae80f2 | 20471 | { |
c19d1205 ZW |
20472 | unsigned int a; |
20473 | unsigned int i; | |
bfae80f2 | 20474 | |
c19d1205 ZW |
20475 | for (i = 0; i < 32; i += 2) |
20476 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
20477 | { | |
20478 | if (a & 0xff00) | |
20479 | { | |
20480 | if (a & ~ 0xffff) | |
20481 | continue; | |
20482 | * highpart = (a >> 8) | ((i + 24) << 7); | |
20483 | } | |
20484 | else if (a & 0xff0000) | |
20485 | { | |
20486 | if (a & 0xff000000) | |
20487 | continue; | |
20488 | * highpart = (a >> 16) | ((i + 16) << 7); | |
20489 | } | |
20490 | else | |
20491 | { | |
9c2799c2 | 20492 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
20493 | * highpart = (a >> 24) | ((i + 8) << 7); |
20494 | } | |
bfae80f2 | 20495 | |
c19d1205 ZW |
20496 | return (a & 0xff) | (i << 7); |
20497 | } | |
bfae80f2 | 20498 | |
c19d1205 | 20499 | return FAIL; |
bfae80f2 RE |
20500 | } |
20501 | ||
c19d1205 ZW |
20502 | static int |
20503 | validate_offset_imm (unsigned int val, int hwse) | |
20504 | { | |
20505 | if ((hwse && val > 255) || val > 4095) | |
20506 | return FAIL; | |
20507 | return val; | |
20508 | } | |
bfae80f2 | 20509 | |
55cf6793 | 20510 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
20511 | negative immediate constant by altering the instruction. A bit of |
20512 | a hack really. | |
20513 | MOV <-> MVN | |
20514 | AND <-> BIC | |
20515 | ADC <-> SBC | |
20516 | by inverting the second operand, and | |
20517 | ADD <-> SUB | |
20518 | CMP <-> CMN | |
20519 | by negating the second operand. */ | |
bfae80f2 | 20520 | |
c19d1205 ZW |
20521 | static int |
20522 | negate_data_op (unsigned long * instruction, | |
20523 | unsigned long value) | |
bfae80f2 | 20524 | { |
c19d1205 ZW |
20525 | int op, new_inst; |
20526 | unsigned long negated, inverted; | |
bfae80f2 | 20527 | |
c19d1205 ZW |
20528 | negated = encode_arm_immediate (-value); |
20529 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 20530 | |
c19d1205 ZW |
20531 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
20532 | switch (op) | |
bfae80f2 | 20533 | { |
c19d1205 ZW |
20534 | /* First negates. */ |
20535 | case OPCODE_SUB: /* ADD <-> SUB */ | |
20536 | new_inst = OPCODE_ADD; | |
20537 | value = negated; | |
20538 | break; | |
bfae80f2 | 20539 | |
c19d1205 ZW |
20540 | case OPCODE_ADD: |
20541 | new_inst = OPCODE_SUB; | |
20542 | value = negated; | |
20543 | break; | |
bfae80f2 | 20544 | |
c19d1205 ZW |
20545 | case OPCODE_CMP: /* CMP <-> CMN */ |
20546 | new_inst = OPCODE_CMN; | |
20547 | value = negated; | |
20548 | break; | |
bfae80f2 | 20549 | |
c19d1205 ZW |
20550 | case OPCODE_CMN: |
20551 | new_inst = OPCODE_CMP; | |
20552 | value = negated; | |
20553 | break; | |
bfae80f2 | 20554 | |
c19d1205 ZW |
20555 | /* Now Inverted ops. */ |
20556 | case OPCODE_MOV: /* MOV <-> MVN */ | |
20557 | new_inst = OPCODE_MVN; | |
20558 | value = inverted; | |
20559 | break; | |
bfae80f2 | 20560 | |
c19d1205 ZW |
20561 | case OPCODE_MVN: |
20562 | new_inst = OPCODE_MOV; | |
20563 | value = inverted; | |
20564 | break; | |
bfae80f2 | 20565 | |
c19d1205 ZW |
20566 | case OPCODE_AND: /* AND <-> BIC */ |
20567 | new_inst = OPCODE_BIC; | |
20568 | value = inverted; | |
20569 | break; | |
bfae80f2 | 20570 | |
c19d1205 ZW |
20571 | case OPCODE_BIC: |
20572 | new_inst = OPCODE_AND; | |
20573 | value = inverted; | |
20574 | break; | |
bfae80f2 | 20575 | |
c19d1205 ZW |
20576 | case OPCODE_ADC: /* ADC <-> SBC */ |
20577 | new_inst = OPCODE_SBC; | |
20578 | value = inverted; | |
20579 | break; | |
bfae80f2 | 20580 | |
c19d1205 ZW |
20581 | case OPCODE_SBC: |
20582 | new_inst = OPCODE_ADC; | |
20583 | value = inverted; | |
20584 | break; | |
bfae80f2 | 20585 | |
c19d1205 ZW |
20586 | /* We cannot do anything. */ |
20587 | default: | |
20588 | return FAIL; | |
b99bd4ef NC |
20589 | } |
20590 | ||
c19d1205 ZW |
20591 | if (value == (unsigned) FAIL) |
20592 | return FAIL; | |
20593 | ||
20594 | *instruction &= OPCODE_MASK; | |
20595 | *instruction |= new_inst << DATA_OP_SHIFT; | |
20596 | return value; | |
b99bd4ef NC |
20597 | } |
20598 | ||
ef8d22e6 PB |
20599 | /* Like negate_data_op, but for Thumb-2. */ |
20600 | ||
20601 | static unsigned int | |
16dd5e42 | 20602 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
20603 | { |
20604 | int op, new_inst; | |
20605 | int rd; | |
16dd5e42 | 20606 | unsigned int negated, inverted; |
ef8d22e6 PB |
20607 | |
20608 | negated = encode_thumb32_immediate (-value); | |
20609 | inverted = encode_thumb32_immediate (~value); | |
20610 | ||
20611 | rd = (*instruction >> 8) & 0xf; | |
20612 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
20613 | switch (op) | |
20614 | { | |
20615 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
20616 | case T2_OPCODE_SUB: | |
20617 | new_inst = T2_OPCODE_ADD; | |
20618 | value = negated; | |
20619 | break; | |
20620 | ||
20621 | case T2_OPCODE_ADD: | |
20622 | new_inst = T2_OPCODE_SUB; | |
20623 | value = negated; | |
20624 | break; | |
20625 | ||
20626 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
20627 | case T2_OPCODE_ORR: | |
20628 | new_inst = T2_OPCODE_ORN; | |
20629 | value = inverted; | |
20630 | break; | |
20631 | ||
20632 | case T2_OPCODE_ORN: | |
20633 | new_inst = T2_OPCODE_ORR; | |
20634 | value = inverted; | |
20635 | break; | |
20636 | ||
20637 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
20638 | case T2_OPCODE_AND: | |
20639 | new_inst = T2_OPCODE_BIC; | |
20640 | if (rd == 15) | |
20641 | value = FAIL; | |
20642 | else | |
20643 | value = inverted; | |
20644 | break; | |
20645 | ||
20646 | case T2_OPCODE_BIC: | |
20647 | new_inst = T2_OPCODE_AND; | |
20648 | value = inverted; | |
20649 | break; | |
20650 | ||
20651 | /* ADC <-> SBC */ | |
20652 | case T2_OPCODE_ADC: | |
20653 | new_inst = T2_OPCODE_SBC; | |
20654 | value = inverted; | |
20655 | break; | |
20656 | ||
20657 | case T2_OPCODE_SBC: | |
20658 | new_inst = T2_OPCODE_ADC; | |
20659 | value = inverted; | |
20660 | break; | |
20661 | ||
20662 | /* We cannot do anything. */ | |
20663 | default: | |
20664 | return FAIL; | |
20665 | } | |
20666 | ||
16dd5e42 | 20667 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
20668 | return FAIL; |
20669 | ||
20670 | *instruction &= T2_OPCODE_MASK; | |
20671 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
20672 | return value; | |
20673 | } | |
20674 | ||
8f06b2d8 PB |
20675 | /* Read a 32-bit thumb instruction from buf. */ |
20676 | static unsigned long | |
20677 | get_thumb32_insn (char * buf) | |
20678 | { | |
20679 | unsigned long insn; | |
20680 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
20681 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20682 | ||
20683 | return insn; | |
20684 | } | |
20685 | ||
a8bc6c78 PB |
20686 | |
20687 | /* We usually want to set the low bit on the address of thumb function | |
20688 | symbols. In particular .word foo - . should have the low bit set. | |
20689 | Generic code tries to fold the difference of two symbols to | |
20690 | a constant. Prevent this and force a relocation when the first symbols | |
20691 | is a thumb function. */ | |
c921be7d NC |
20692 | |
20693 | bfd_boolean | |
a8bc6c78 PB |
20694 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
20695 | { | |
20696 | if (op == O_subtract | |
20697 | && l->X_op == O_symbol | |
20698 | && r->X_op == O_symbol | |
20699 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
20700 | { | |
20701 | l->X_op = O_subtract; | |
20702 | l->X_op_symbol = r->X_add_symbol; | |
20703 | l->X_add_number -= r->X_add_number; | |
c921be7d | 20704 | return TRUE; |
a8bc6c78 | 20705 | } |
c921be7d | 20706 | |
a8bc6c78 | 20707 | /* Process as normal. */ |
c921be7d | 20708 | return FALSE; |
a8bc6c78 PB |
20709 | } |
20710 | ||
4a42ebbc RR |
20711 | /* Encode Thumb2 unconditional branches and calls. The encoding |
20712 | for the 2 are identical for the immediate values. */ | |
20713 | ||
20714 | static void | |
20715 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
20716 | { | |
20717 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
20718 | offsetT newval; | |
20719 | offsetT newval2; | |
20720 | addressT S, I1, I2, lo, hi; | |
20721 | ||
20722 | S = (value >> 24) & 0x01; | |
20723 | I1 = (value >> 23) & 0x01; | |
20724 | I2 = (value >> 22) & 0x01; | |
20725 | hi = (value >> 12) & 0x3ff; | |
fa94de6b | 20726 | lo = (value >> 1) & 0x7ff; |
4a42ebbc RR |
20727 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20728 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20729 | newval |= (S << 10) | hi; | |
20730 | newval2 &= ~T2I1I2MASK; | |
20731 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
20732 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20733 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20734 | } | |
20735 | ||
c19d1205 | 20736 | void |
55cf6793 | 20737 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
20738 | valueT * valP, |
20739 | segT seg) | |
20740 | { | |
20741 | offsetT value = * valP; | |
20742 | offsetT newval; | |
20743 | unsigned int newimm; | |
20744 | unsigned long temp; | |
20745 | int sign; | |
20746 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 20747 | |
9c2799c2 | 20748 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 20749 | |
c19d1205 | 20750 | /* Note whether this will delete the relocation. */ |
4962c51a | 20751 | |
c19d1205 ZW |
20752 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
20753 | fixP->fx_done = 1; | |
b99bd4ef | 20754 | |
adbaf948 | 20755 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 20756 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
20757 | for emit_reloc. */ |
20758 | value &= 0xffffffff; | |
20759 | value ^= 0x80000000; | |
5f4273c7 | 20760 | value -= 0x80000000; |
adbaf948 ZW |
20761 | |
20762 | *valP = value; | |
c19d1205 | 20763 | fixP->fx_addnumber = value; |
b99bd4ef | 20764 | |
adbaf948 ZW |
20765 | /* Same treatment for fixP->fx_offset. */ |
20766 | fixP->fx_offset &= 0xffffffff; | |
20767 | fixP->fx_offset ^= 0x80000000; | |
20768 | fixP->fx_offset -= 0x80000000; | |
20769 | ||
c19d1205 | 20770 | switch (fixP->fx_r_type) |
b99bd4ef | 20771 | { |
c19d1205 ZW |
20772 | case BFD_RELOC_NONE: |
20773 | /* This will need to go in the object file. */ | |
20774 | fixP->fx_done = 0; | |
20775 | break; | |
b99bd4ef | 20776 | |
c19d1205 ZW |
20777 | case BFD_RELOC_ARM_IMMEDIATE: |
20778 | /* We claim that this fixup has been processed here, | |
20779 | even if in fact we generate an error because we do | |
20780 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20781 | fixP->fx_done = 1; | |
b99bd4ef | 20782 | |
77db8e2e | 20783 | if (fixP->fx_addsy) |
b99bd4ef | 20784 | { |
77db8e2e | 20785 | const char *msg = 0; |
b99bd4ef | 20786 | |
77db8e2e NC |
20787 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20788 | msg = _("undefined symbol %s used as an immediate value"); | |
20789 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20790 | msg = _("symbol %s is in a different section"); | |
20791 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20792 | msg = _("symbol %s is weak and may be overridden later"); | |
20793 | ||
20794 | if (msg) | |
20795 | { | |
20796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20797 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20798 | break; | |
20799 | } | |
42e5fcbf AS |
20800 | } |
20801 | ||
c19d1205 ZW |
20802 | temp = md_chars_to_number (buf, INSN_SIZE); |
20803 | ||
5e73442d SL |
20804 | /* If the offset is negative, we should use encoding A2 for ADR. */ |
20805 | if ((temp & 0xfff0000) == 0x28f0000 && value < 0) | |
20806 | newimm = negate_data_op (&temp, value); | |
20807 | else | |
20808 | { | |
20809 | newimm = encode_arm_immediate (value); | |
20810 | ||
20811 | /* If the instruction will fail, see if we can fix things up by | |
20812 | changing the opcode. */ | |
20813 | if (newimm == (unsigned int) FAIL) | |
20814 | newimm = negate_data_op (&temp, value); | |
20815 | } | |
20816 | ||
20817 | if (newimm == (unsigned int) FAIL) | |
b99bd4ef | 20818 | { |
c19d1205 ZW |
20819 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20820 | _("invalid constant (%lx) after fixup"), | |
20821 | (unsigned long) value); | |
20822 | break; | |
b99bd4ef | 20823 | } |
b99bd4ef | 20824 | |
c19d1205 ZW |
20825 | newimm |= (temp & 0xfffff000); |
20826 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
20827 | break; | |
b99bd4ef | 20828 | |
c19d1205 ZW |
20829 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
20830 | { | |
20831 | unsigned int highpart = 0; | |
20832 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 20833 | |
77db8e2e | 20834 | if (fixP->fx_addsy) |
42e5fcbf | 20835 | { |
77db8e2e | 20836 | const char *msg = 0; |
42e5fcbf | 20837 | |
77db8e2e NC |
20838 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20839 | msg = _("undefined symbol %s used as an immediate value"); | |
20840 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20841 | msg = _("symbol %s is in a different section"); | |
20842 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20843 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 20844 | |
77db8e2e NC |
20845 | if (msg) |
20846 | { | |
20847 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20848 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20849 | break; | |
20850 | } | |
20851 | } | |
fa94de6b | 20852 | |
c19d1205 ZW |
20853 | newimm = encode_arm_immediate (value); |
20854 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 20855 | |
c19d1205 ZW |
20856 | /* If the instruction will fail, see if we can fix things up by |
20857 | changing the opcode. */ | |
20858 | if (newimm == (unsigned int) FAIL | |
20859 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
20860 | { | |
20861 | /* No ? OK - try using two ADD instructions to generate | |
20862 | the value. */ | |
20863 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 20864 | |
c19d1205 ZW |
20865 | /* Yes - then make sure that the second instruction is |
20866 | also an add. */ | |
20867 | if (newimm != (unsigned int) FAIL) | |
20868 | newinsn = temp; | |
20869 | /* Still No ? Try using a negated value. */ | |
20870 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
20871 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
20872 | /* Otherwise - give up. */ | |
20873 | else | |
20874 | { | |
20875 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20876 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
20877 | (long) value); | |
20878 | break; | |
20879 | } | |
b99bd4ef | 20880 | |
c19d1205 ZW |
20881 | /* Replace the first operand in the 2nd instruction (which |
20882 | is the PC) with the destination register. We have | |
20883 | already added in the PC in the first instruction and we | |
20884 | do not want to do it again. */ | |
20885 | newinsn &= ~ 0xf0000; | |
20886 | newinsn |= ((newinsn & 0x0f000) << 4); | |
20887 | } | |
b99bd4ef | 20888 | |
c19d1205 ZW |
20889 | newimm |= (temp & 0xfffff000); |
20890 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 20891 | |
c19d1205 ZW |
20892 | highpart |= (newinsn & 0xfffff000); |
20893 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
20894 | } | |
20895 | break; | |
b99bd4ef | 20896 | |
c19d1205 | 20897 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20898 | if (!fixP->fx_done && seg->use_rela_p) |
20899 | value = 0; | |
20900 | ||
c19d1205 | 20901 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 20902 | sign = value > 0; |
b99bd4ef | 20903 | |
c19d1205 ZW |
20904 | if (value < 0) |
20905 | value = - value; | |
b99bd4ef | 20906 | |
c19d1205 | 20907 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 20908 | { |
c19d1205 ZW |
20909 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
20910 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20911 | _("invalid literal constant: pool needs to be closer")); | |
20912 | else | |
20913 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20914 | _("bad immediate value for offset (%ld)"), | |
20915 | (long) value); | |
20916 | break; | |
f03698e6 RE |
20917 | } |
20918 | ||
c19d1205 | 20919 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20920 | if (value == 0) |
20921 | newval &= 0xfffff000; | |
20922 | else | |
20923 | { | |
20924 | newval &= 0xff7ff000; | |
20925 | newval |= value | (sign ? INDEX_UP : 0); | |
20926 | } | |
c19d1205 ZW |
20927 | md_number_to_chars (buf, newval, INSN_SIZE); |
20928 | break; | |
b99bd4ef | 20929 | |
c19d1205 ZW |
20930 | case BFD_RELOC_ARM_OFFSET_IMM8: |
20931 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 20932 | sign = value > 0; |
b99bd4ef | 20933 | |
c19d1205 ZW |
20934 | if (value < 0) |
20935 | value = - value; | |
b99bd4ef | 20936 | |
c19d1205 | 20937 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 20938 | { |
c19d1205 ZW |
20939 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
20940 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20941 | _("invalid literal constant: pool needs to be closer")); | |
20942 | else | |
f9d4405b | 20943 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
20944 | (long) value); |
20945 | break; | |
b99bd4ef NC |
20946 | } |
20947 | ||
c19d1205 | 20948 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20949 | if (value == 0) |
20950 | newval &= 0xfffff0f0; | |
20951 | else | |
20952 | { | |
20953 | newval &= 0xff7ff0f0; | |
20954 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
20955 | } | |
c19d1205 ZW |
20956 | md_number_to_chars (buf, newval, INSN_SIZE); |
20957 | break; | |
b99bd4ef | 20958 | |
c19d1205 ZW |
20959 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
20960 | if (value < 0 || value > 1020 || value % 4 != 0) | |
20961 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20962 | _("bad immediate value for offset (%ld)"), (long) value); | |
20963 | value /= 4; | |
b99bd4ef | 20964 | |
c19d1205 | 20965 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
20966 | newval |= value; |
20967 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
20968 | break; | |
b99bd4ef | 20969 | |
c19d1205 ZW |
20970 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
20971 | /* This is a complicated relocation used for all varieties of Thumb32 | |
20972 | load/store instruction with immediate offset: | |
20973 | ||
20974 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
20975 | *4, optional writeback(W) | |
20976 | (doubleword load/store) | |
20977 | ||
20978 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
20979 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
20980 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
20981 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
20982 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
20983 | ||
20984 | Uppercase letters indicate bits that are already encoded at | |
20985 | this point. Lowercase letters are our problem. For the | |
20986 | second block of instructions, the secondary opcode nybble | |
20987 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
20988 | a PC-relative operation. */ | |
20989 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20990 | newval <<= 16; | |
20991 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 20992 | |
c19d1205 | 20993 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 20994 | { |
c19d1205 ZW |
20995 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
20996 | if (value >= 0) | |
20997 | newval |= (1 << 23); | |
20998 | else | |
20999 | value = -value; | |
21000 | if (value % 4 != 0) | |
21001 | { | |
21002 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21003 | _("offset not a multiple of 4")); | |
21004 | break; | |
21005 | } | |
21006 | value /= 4; | |
216d22bc | 21007 | if (value > 0xff) |
c19d1205 ZW |
21008 | { |
21009 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21010 | _("offset out of range")); | |
21011 | break; | |
21012 | } | |
21013 | newval &= ~0xff; | |
b99bd4ef | 21014 | } |
c19d1205 | 21015 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 21016 | { |
c19d1205 ZW |
21017 | /* PC-relative, 12-bit offset. */ |
21018 | if (value >= 0) | |
21019 | newval |= (1 << 23); | |
21020 | else | |
21021 | value = -value; | |
216d22bc | 21022 | if (value > 0xfff) |
c19d1205 ZW |
21023 | { |
21024 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21025 | _("offset out of range")); | |
21026 | break; | |
21027 | } | |
21028 | newval &= ~0xfff; | |
b99bd4ef | 21029 | } |
c19d1205 | 21030 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 21031 | { |
c19d1205 ZW |
21032 | /* Writeback: 8-bit, +/- offset. */ |
21033 | if (value >= 0) | |
21034 | newval |= (1 << 9); | |
21035 | else | |
21036 | value = -value; | |
216d22bc | 21037 | if (value > 0xff) |
c19d1205 ZW |
21038 | { |
21039 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21040 | _("offset out of range")); | |
21041 | break; | |
21042 | } | |
21043 | newval &= ~0xff; | |
b99bd4ef | 21044 | } |
c19d1205 | 21045 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 21046 | { |
c19d1205 | 21047 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 21048 | if (value < 0 || value > 0xff) |
b99bd4ef | 21049 | { |
c19d1205 ZW |
21050 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21051 | _("offset out of range")); | |
21052 | break; | |
b99bd4ef | 21053 | } |
c19d1205 ZW |
21054 | newval &= ~0xff; |
21055 | newval |= value; | |
b99bd4ef NC |
21056 | } |
21057 | else | |
b99bd4ef | 21058 | { |
c19d1205 ZW |
21059 | /* Positive 12-bit or negative 8-bit offset. */ |
21060 | int limit; | |
21061 | if (value >= 0) | |
b99bd4ef | 21062 | { |
c19d1205 ZW |
21063 | newval |= (1 << 23); |
21064 | limit = 0xfff; | |
21065 | } | |
21066 | else | |
21067 | { | |
21068 | value = -value; | |
21069 | limit = 0xff; | |
21070 | } | |
21071 | if (value > limit) | |
21072 | { | |
21073 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21074 | _("offset out of range")); | |
21075 | break; | |
b99bd4ef | 21076 | } |
c19d1205 | 21077 | newval &= ~limit; |
b99bd4ef | 21078 | } |
b99bd4ef | 21079 | |
c19d1205 ZW |
21080 | newval |= value; |
21081 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
21082 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
21083 | break; | |
404ff6b5 | 21084 | |
c19d1205 ZW |
21085 | case BFD_RELOC_ARM_SHIFT_IMM: |
21086 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21087 | if (((unsigned long) value) > 32 | |
21088 | || (value == 32 | |
21089 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
21090 | { | |
21091 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21092 | _("shift expression is too large")); | |
21093 | break; | |
21094 | } | |
404ff6b5 | 21095 | |
c19d1205 ZW |
21096 | if (value == 0) |
21097 | /* Shifts of zero must be done as lsl. */ | |
21098 | newval &= ~0x60; | |
21099 | else if (value == 32) | |
21100 | value = 0; | |
21101 | newval &= 0xfffff07f; | |
21102 | newval |= (value & 0x1f) << 7; | |
21103 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21104 | break; | |
404ff6b5 | 21105 | |
c19d1205 | 21106 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 21107 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 21108 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 21109 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
21110 | /* We claim that this fixup has been processed here, |
21111 | even if in fact we generate an error because we do | |
21112 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
21113 | fixP->fx_done = 1; | |
404ff6b5 | 21114 | |
c19d1205 ZW |
21115 | if (fixP->fx_addsy |
21116 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
21117 | { | |
21118 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21119 | _("undefined symbol %s used as an immediate value"), | |
21120 | S_GET_NAME (fixP->fx_addsy)); | |
21121 | break; | |
21122 | } | |
404ff6b5 | 21123 | |
c19d1205 ZW |
21124 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21125 | newval <<= 16; | |
21126 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 21127 | |
16805f35 PB |
21128 | newimm = FAIL; |
21129 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
21130 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
21131 | { |
21132 | newimm = encode_thumb32_immediate (value); | |
21133 | if (newimm == (unsigned int) FAIL) | |
21134 | newimm = thumb32_negate_data_op (&newval, value); | |
21135 | } | |
16805f35 PB |
21136 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
21137 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 21138 | { |
16805f35 PB |
21139 | /* Turn add/sum into addw/subw. */ |
21140 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
21141 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
21142 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
21143 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 21144 | { |
40f246e3 NC |
21145 | /* 12 bit immediate for addw/subw. */ |
21146 | if (value < 0) | |
21147 | { | |
21148 | value = -value; | |
21149 | newval ^= 0x00a00000; | |
21150 | } | |
21151 | if (value > 0xfff) | |
21152 | newimm = (unsigned int) FAIL; | |
21153 | else | |
21154 | newimm = value; | |
e9f89963 | 21155 | } |
92e90b6e | 21156 | } |
cc8a6dd0 | 21157 | |
c19d1205 | 21158 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 21159 | { |
c19d1205 ZW |
21160 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21161 | _("invalid constant (%lx) after fixup"), | |
21162 | (unsigned long) value); | |
21163 | break; | |
3631a3c8 NC |
21164 | } |
21165 | ||
c19d1205 ZW |
21166 | newval |= (newimm & 0x800) << 15; |
21167 | newval |= (newimm & 0x700) << 4; | |
21168 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 21169 | |
c19d1205 ZW |
21170 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
21171 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
21172 | break; | |
a737bd4d | 21173 | |
3eb17e6b | 21174 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
21175 | if (((unsigned long) value) > 0xffff) |
21176 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 21177 | _("invalid smc expression")); |
2fc8bdac | 21178 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
21179 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
21180 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21181 | break; | |
a737bd4d | 21182 | |
90ec0d68 MGD |
21183 | case BFD_RELOC_ARM_HVC: |
21184 | if (((unsigned long) value) > 0xffff) | |
21185 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21186 | _("invalid hvc expression")); | |
21187 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21188 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
21189 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21190 | break; | |
21191 | ||
c19d1205 | 21192 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 21193 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
21194 | { |
21195 | if (((unsigned long) value) > 0xff) | |
21196 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21197 | _("invalid swi expression")); | |
2fc8bdac | 21198 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
21199 | newval |= value; |
21200 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21201 | } | |
21202 | else | |
21203 | { | |
21204 | if (((unsigned long) value) > 0x00ffffff) | |
21205 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21206 | _("invalid swi expression")); | |
2fc8bdac | 21207 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
21208 | newval |= value; |
21209 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21210 | } | |
21211 | break; | |
a737bd4d | 21212 | |
c19d1205 ZW |
21213 | case BFD_RELOC_ARM_MULTI: |
21214 | if (((unsigned long) value) > 0xffff) | |
21215 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21216 | _("invalid expression in load/store multiple")); | |
21217 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
21218 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21219 | break; | |
a737bd4d | 21220 | |
c19d1205 | 21221 | #ifdef OBJ_ELF |
39b41c9c | 21222 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
21223 | |
21224 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
21225 | && fixP->fx_addsy | |
34e77a92 | 21226 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21227 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21228 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21229 | /* Flip the bl to blx. This is a simple flip | |
21230 | bit here because we generate PCREL_CALL for | |
21231 | unconditional bls. */ | |
21232 | { | |
21233 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21234 | newval = newval | 0x10000000; | |
21235 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21236 | temp = 1; | |
21237 | fixP->fx_done = 1; | |
21238 | } | |
39b41c9c PB |
21239 | else |
21240 | temp = 3; | |
21241 | goto arm_branch_common; | |
21242 | ||
21243 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
21244 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
21245 | && fixP->fx_addsy | |
34e77a92 | 21246 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21247 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21248 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21249 | { | |
21250 | /* This would map to a bl<cond>, b<cond>, | |
21251 | b<always> to a Thumb function. We | |
21252 | need to force a relocation for this particular | |
21253 | case. */ | |
21254 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21255 | fixP->fx_done = 0; | |
21256 | } | |
21257 | ||
2fc8bdac | 21258 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 21259 | #endif |
39b41c9c PB |
21260 | case BFD_RELOC_ARM_PCREL_BRANCH: |
21261 | temp = 3; | |
21262 | goto arm_branch_common; | |
a737bd4d | 21263 | |
39b41c9c | 21264 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 21265 | |
39b41c9c | 21266 | temp = 1; |
267bf995 RR |
21267 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
21268 | && fixP->fx_addsy | |
34e77a92 | 21269 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21270 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21271 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
21272 | { | |
21273 | /* Flip the blx to a bl and warn. */ | |
21274 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21275 | newval = 0xeb000000; | |
21276 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21277 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
21278 | name); | |
21279 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21280 | temp = 3; | |
21281 | fixP->fx_done = 1; | |
21282 | } | |
21283 | ||
21284 | #ifdef OBJ_ELF | |
21285 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21286 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
21287 | #endif | |
21288 | ||
39b41c9c | 21289 | arm_branch_common: |
c19d1205 | 21290 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
21291 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
21292 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
21293 | also be be clear. */ | |
21294 | if (value & temp) | |
c19d1205 | 21295 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
21296 | _("misaligned branch destination")); |
21297 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
21298 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 21299 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21300 | |
2fc8bdac | 21301 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21302 | { |
2fc8bdac ZW |
21303 | newval = md_chars_to_number (buf, INSN_SIZE); |
21304 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
21305 | /* Set the H bit on BLX instructions. */ |
21306 | if (temp == 1) | |
21307 | { | |
21308 | if (value & 2) | |
21309 | newval |= 0x01000000; | |
21310 | else | |
21311 | newval &= ~0x01000000; | |
21312 | } | |
2fc8bdac | 21313 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 21314 | } |
c19d1205 | 21315 | break; |
a737bd4d | 21316 | |
25fe350b MS |
21317 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
21318 | /* CBZ can only branch forward. */ | |
a737bd4d | 21319 | |
738755b0 MS |
21320 | /* Attempts to use CBZ to branch to the next instruction |
21321 | (which, strictly speaking, are prohibited) will be turned into | |
21322 | no-ops. | |
21323 | ||
21324 | FIXME: It may be better to remove the instruction completely and | |
21325 | perform relaxation. */ | |
21326 | if (value == -2) | |
2fc8bdac ZW |
21327 | { |
21328 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 21329 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
21330 | md_number_to_chars (buf, newval, THUMB_SIZE); |
21331 | } | |
738755b0 MS |
21332 | else |
21333 | { | |
21334 | if (value & ~0x7e) | |
08f10d51 | 21335 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 MS |
21336 | |
21337 | if (fixP->fx_done || !seg->use_rela_p) | |
21338 | { | |
21339 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21340 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
21341 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21342 | } | |
21343 | } | |
c19d1205 | 21344 | break; |
a737bd4d | 21345 | |
c19d1205 | 21346 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 21347 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 21348 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21349 | |
2fc8bdac ZW |
21350 | if (fixP->fx_done || !seg->use_rela_p) |
21351 | { | |
21352 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21353 | newval |= (value & 0x1ff) >> 1; | |
21354 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21355 | } | |
c19d1205 | 21356 | break; |
a737bd4d | 21357 | |
c19d1205 | 21358 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 21359 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 21360 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21361 | |
2fc8bdac ZW |
21362 | if (fixP->fx_done || !seg->use_rela_p) |
21363 | { | |
21364 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21365 | newval |= (value & 0xfff) >> 1; | |
21366 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21367 | } | |
c19d1205 | 21368 | break; |
a737bd4d | 21369 | |
c19d1205 | 21370 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
21371 | if (fixP->fx_addsy |
21372 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21373 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21374 | && ARM_IS_FUNC (fixP->fx_addsy) |
21375 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21376 | { | |
21377 | /* Force a relocation for a branch 20 bits wide. */ | |
21378 | fixP->fx_done = 0; | |
21379 | } | |
08f10d51 | 21380 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
21381 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21382 | _("conditional branch out of range")); | |
404ff6b5 | 21383 | |
2fc8bdac ZW |
21384 | if (fixP->fx_done || !seg->use_rela_p) |
21385 | { | |
21386 | offsetT newval2; | |
21387 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 21388 | |
2fc8bdac ZW |
21389 | S = (value & 0x00100000) >> 20; |
21390 | J2 = (value & 0x00080000) >> 19; | |
21391 | J1 = (value & 0x00040000) >> 18; | |
21392 | hi = (value & 0x0003f000) >> 12; | |
21393 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 21394 | |
2fc8bdac ZW |
21395 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21396 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21397 | newval |= (S << 10) | hi; | |
21398 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
21399 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21400 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
21401 | } | |
c19d1205 | 21402 | break; |
6c43fab6 | 21403 | |
c19d1205 | 21404 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
21405 | /* If there is a blx from a thumb state function to |
21406 | another thumb function flip this to a bl and warn | |
21407 | about it. */ | |
21408 | ||
21409 | if (fixP->fx_addsy | |
34e77a92 | 21410 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21411 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21412 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21413 | { | |
21414 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21415 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21416 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
21417 | name); | |
21418 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21419 | newval = newval | 0x1000; | |
21420 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21421 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21422 | fixP->fx_done = 1; | |
21423 | } | |
21424 | ||
21425 | ||
21426 | goto thumb_bl_common; | |
21427 | ||
c19d1205 | 21428 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
21429 | /* A bl from Thumb state ISA to an internal ARM state function |
21430 | is converted to a blx. */ | |
21431 | if (fixP->fx_addsy | |
21432 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21433 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21434 | && ARM_IS_FUNC (fixP->fx_addsy) |
21435 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21436 | { | |
21437 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21438 | newval = newval & ~0x1000; | |
21439 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21440 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
21441 | fixP->fx_done = 1; | |
21442 | } | |
21443 | ||
21444 | thumb_bl_common: | |
21445 | ||
21446 | #ifdef OBJ_ELF | |
2b2f5df9 NC |
21447 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 |
21448 | && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
267bf995 RR |
21449 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
21450 | #endif | |
21451 | ||
2fc8bdac ZW |
21452 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
21453 | /* For a BLX instruction, make sure that the relocation is rounded up | |
21454 | to a word boundary. This follows the semantics of the instruction | |
21455 | which specifies that bit 1 of the target address will come from bit | |
21456 | 1 of the base address. */ | |
21457 | value = (value + 1) & ~ 1; | |
404ff6b5 | 21458 | |
2b2f5df9 NC |
21459 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
21460 | { | |
21461 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
21462 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
21463 | else if ((value & ~0x1ffffff) | |
21464 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
21465 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21466 | _("Thumb2 branch out of range")); | |
21467 | } | |
4a42ebbc RR |
21468 | |
21469 | if (fixP->fx_done || !seg->use_rela_p) | |
21470 | encode_thumb2_b_bl_offset (buf, value); | |
21471 | ||
c19d1205 | 21472 | break; |
404ff6b5 | 21473 | |
c19d1205 | 21474 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
21475 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
21476 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 21477 | |
2fc8bdac | 21478 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 21479 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 21480 | |
2fc8bdac | 21481 | break; |
a737bd4d | 21482 | |
2fc8bdac ZW |
21483 | case BFD_RELOC_8: |
21484 | if (fixP->fx_done || !seg->use_rela_p) | |
21485 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 21486 | break; |
a737bd4d | 21487 | |
c19d1205 | 21488 | case BFD_RELOC_16: |
2fc8bdac | 21489 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21490 | md_number_to_chars (buf, value, 2); |
c19d1205 | 21491 | break; |
a737bd4d | 21492 | |
c19d1205 | 21493 | #ifdef OBJ_ELF |
0855e32b NS |
21494 | case BFD_RELOC_ARM_TLS_CALL: |
21495 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21496 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21497 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
21498 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21499 | break; | |
21500 | ||
21501 | case BFD_RELOC_ARM_TLS_GOTDESC: | |
c19d1205 ZW |
21502 | case BFD_RELOC_ARM_TLS_GD32: |
21503 | case BFD_RELOC_ARM_TLS_LE32: | |
21504 | case BFD_RELOC_ARM_TLS_IE32: | |
21505 | case BFD_RELOC_ARM_TLS_LDM32: | |
21506 | case BFD_RELOC_ARM_TLS_LDO32: | |
21507 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21508 | /* fall through */ | |
6c43fab6 | 21509 | |
c19d1205 ZW |
21510 | case BFD_RELOC_ARM_GOT32: |
21511 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
21512 | if (fixP->fx_done || !seg->use_rela_p) |
21513 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 21514 | break; |
b43420e6 NC |
21515 | |
21516 | case BFD_RELOC_ARM_GOT_PREL: | |
21517 | if (fixP->fx_done || !seg->use_rela_p) | |
21518 | md_number_to_chars (buf, value, 4); | |
21519 | break; | |
21520 | ||
9a6f4e97 NS |
21521 | case BFD_RELOC_ARM_TARGET2: |
21522 | /* TARGET2 is not partial-inplace, so we need to write the | |
21523 | addend here for REL targets, because it won't be written out | |
21524 | during reloc processing later. */ | |
21525 | if (fixP->fx_done || !seg->use_rela_p) | |
21526 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
21527 | break; | |
c19d1205 | 21528 | #endif |
6c43fab6 | 21529 | |
c19d1205 ZW |
21530 | case BFD_RELOC_RVA: |
21531 | case BFD_RELOC_32: | |
21532 | case BFD_RELOC_ARM_TARGET1: | |
21533 | case BFD_RELOC_ARM_ROSEGREL32: | |
21534 | case BFD_RELOC_ARM_SBREL32: | |
21535 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
21536 | #ifdef TE_PE |
21537 | case BFD_RELOC_32_SECREL: | |
21538 | #endif | |
2fc8bdac | 21539 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
21540 | #ifdef TE_WINCE |
21541 | /* For WinCE we only do this for pcrel fixups. */ | |
21542 | if (fixP->fx_done || fixP->fx_pcrel) | |
21543 | #endif | |
21544 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 21545 | break; |
6c43fab6 | 21546 | |
c19d1205 ZW |
21547 | #ifdef OBJ_ELF |
21548 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 21549 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
21550 | { |
21551 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
21552 | if ((value ^ (value >> 1)) & 0x40000000) | |
21553 | { | |
21554 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21555 | _("rel31 relocation overflow")); | |
21556 | } | |
21557 | newval |= value & 0x7fffffff; | |
21558 | md_number_to_chars (buf, newval, 4); | |
21559 | } | |
21560 | break; | |
c19d1205 | 21561 | #endif |
a737bd4d | 21562 | |
c19d1205 | 21563 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 21564 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
21565 | if (value < -1023 || value > 1023 || (value & 3)) |
21566 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21567 | _("co-processor offset out of range")); | |
21568 | cp_off_common: | |
26d97720 | 21569 | sign = value > 0; |
c19d1205 ZW |
21570 | if (value < 0) |
21571 | value = -value; | |
8f06b2d8 PB |
21572 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21573 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21574 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21575 | else | |
21576 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
21577 | if (value == 0) |
21578 | newval &= 0xffffff00; | |
21579 | else | |
21580 | { | |
21581 | newval &= 0xff7fff00; | |
21582 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
21583 | } | |
8f06b2d8 PB |
21584 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21585 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21586 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21587 | else | |
21588 | put_thumb32_insn (buf, newval); | |
c19d1205 | 21589 | break; |
a737bd4d | 21590 | |
c19d1205 | 21591 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 21592 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
21593 | if (value < -255 || value > 255) |
21594 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21595 | _("co-processor offset out of range")); | |
df7849c5 | 21596 | value *= 4; |
c19d1205 | 21597 | goto cp_off_common; |
6c43fab6 | 21598 | |
c19d1205 ZW |
21599 | case BFD_RELOC_ARM_THUMB_OFFSET: |
21600 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21601 | /* Exactly what ranges, and where the offset is inserted depends | |
21602 | on the type of instruction, we can establish this from the | |
21603 | top 4 bits. */ | |
21604 | switch (newval >> 12) | |
21605 | { | |
21606 | case 4: /* PC load. */ | |
21607 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
21608 | forced to zero for these loads; md_pcrel_from has already | |
21609 | compensated for this. */ | |
21610 | if (value & 3) | |
21611 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21612 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
21613 | (((unsigned long) fixP->fx_frag->fr_address |
21614 | + (unsigned long) fixP->fx_where) & ~3) | |
21615 | + (unsigned long) value); | |
a737bd4d | 21616 | |
c19d1205 ZW |
21617 | if (value & ~0x3fc) |
21618 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21619 | _("invalid offset, value too big (0x%08lX)"), | |
21620 | (long) value); | |
a737bd4d | 21621 | |
c19d1205 ZW |
21622 | newval |= value >> 2; |
21623 | break; | |
a737bd4d | 21624 | |
c19d1205 ZW |
21625 | case 9: /* SP load/store. */ |
21626 | if (value & ~0x3fc) | |
21627 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21628 | _("invalid offset, value too big (0x%08lX)"), | |
21629 | (long) value); | |
21630 | newval |= value >> 2; | |
21631 | break; | |
6c43fab6 | 21632 | |
c19d1205 ZW |
21633 | case 6: /* Word load/store. */ |
21634 | if (value & ~0x7c) | |
21635 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21636 | _("invalid offset, value too big (0x%08lX)"), | |
21637 | (long) value); | |
21638 | newval |= value << 4; /* 6 - 2. */ | |
21639 | break; | |
a737bd4d | 21640 | |
c19d1205 ZW |
21641 | case 7: /* Byte load/store. */ |
21642 | if (value & ~0x1f) | |
21643 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21644 | _("invalid offset, value too big (0x%08lX)"), | |
21645 | (long) value); | |
21646 | newval |= value << 6; | |
21647 | break; | |
a737bd4d | 21648 | |
c19d1205 ZW |
21649 | case 8: /* Halfword load/store. */ |
21650 | if (value & ~0x3e) | |
21651 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21652 | _("invalid offset, value too big (0x%08lX)"), | |
21653 | (long) value); | |
21654 | newval |= value << 5; /* 6 - 1. */ | |
21655 | break; | |
a737bd4d | 21656 | |
c19d1205 ZW |
21657 | default: |
21658 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21659 | "Unable to process relocation for thumb opcode: %lx", | |
21660 | (unsigned long) newval); | |
21661 | break; | |
21662 | } | |
21663 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21664 | break; | |
a737bd4d | 21665 | |
c19d1205 ZW |
21666 | case BFD_RELOC_ARM_THUMB_ADD: |
21667 | /* This is a complicated relocation, since we use it for all of | |
21668 | the following immediate relocations: | |
a737bd4d | 21669 | |
c19d1205 ZW |
21670 | 3bit ADD/SUB |
21671 | 8bit ADD/SUB | |
21672 | 9bit ADD/SUB SP word-aligned | |
21673 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 21674 | |
c19d1205 ZW |
21675 | The type of instruction being processed is encoded in the |
21676 | instruction field: | |
a737bd4d | 21677 | |
c19d1205 ZW |
21678 | 0x8000 SUB |
21679 | 0x00F0 Rd | |
21680 | 0x000F Rs | |
21681 | */ | |
21682 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21683 | { | |
21684 | int rd = (newval >> 4) & 0xf; | |
21685 | int rs = newval & 0xf; | |
21686 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 21687 | |
c19d1205 ZW |
21688 | /* Check for HI regs, only very restricted cases allowed: |
21689 | Adjusting SP, and using PC or SP to get an address. */ | |
21690 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
21691 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
21692 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21693 | _("invalid Hi register with immediate")); | |
a737bd4d | 21694 | |
c19d1205 ZW |
21695 | /* If value is negative, choose the opposite instruction. */ |
21696 | if (value < 0) | |
21697 | { | |
21698 | value = -value; | |
21699 | subtract = !subtract; | |
21700 | if (value < 0) | |
21701 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21702 | _("immediate value out of range")); | |
21703 | } | |
a737bd4d | 21704 | |
c19d1205 ZW |
21705 | if (rd == REG_SP) |
21706 | { | |
21707 | if (value & ~0x1fc) | |
21708 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21709 | _("invalid immediate for stack address calculation")); | |
21710 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
21711 | newval |= value >> 2; | |
21712 | } | |
21713 | else if (rs == REG_PC || rs == REG_SP) | |
21714 | { | |
21715 | if (subtract || value & ~0x3fc) | |
21716 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21717 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
21718 | (unsigned long) value); | |
21719 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
21720 | newval |= rd << 8; | |
21721 | newval |= value >> 2; | |
21722 | } | |
21723 | else if (rs == rd) | |
21724 | { | |
21725 | if (value & ~0xff) | |
21726 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21727 | _("immediate value out of range")); | |
21728 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
21729 | newval |= (rd << 8) | value; | |
21730 | } | |
21731 | else | |
21732 | { | |
21733 | if (value & ~0x7) | |
21734 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21735 | _("immediate value out of range")); | |
21736 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
21737 | newval |= rd | (rs << 3) | (value << 6); | |
21738 | } | |
21739 | } | |
21740 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21741 | break; | |
a737bd4d | 21742 | |
c19d1205 ZW |
21743 | case BFD_RELOC_ARM_THUMB_IMM: |
21744 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21745 | if (value < 0 || value > 255) | |
21746 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 21747 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
21748 | (long) value); |
21749 | newval |= value; | |
21750 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21751 | break; | |
a737bd4d | 21752 | |
c19d1205 ZW |
21753 | case BFD_RELOC_ARM_THUMB_SHIFT: |
21754 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
21755 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
21756 | temp = newval & 0xf800; | |
21757 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
21758 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21759 | _("invalid shift value: %ld"), (long) value); | |
21760 | /* Shifts of zero must be encoded as LSL. */ | |
21761 | if (value == 0) | |
21762 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
21763 | /* Shifts of 32 are encoded as zero. */ | |
21764 | else if (value == 32) | |
21765 | value = 0; | |
21766 | newval |= value << 6; | |
21767 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21768 | break; | |
a737bd4d | 21769 | |
c19d1205 ZW |
21770 | case BFD_RELOC_VTABLE_INHERIT: |
21771 | case BFD_RELOC_VTABLE_ENTRY: | |
21772 | fixP->fx_done = 0; | |
21773 | return; | |
6c43fab6 | 21774 | |
b6895b4f PB |
21775 | case BFD_RELOC_ARM_MOVW: |
21776 | case BFD_RELOC_ARM_MOVT: | |
21777 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21778 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21779 | if (fixP->fx_done || !seg->use_rela_p) | |
21780 | { | |
21781 | /* REL format relocations are limited to a 16-bit addend. */ | |
21782 | if (!fixP->fx_done) | |
21783 | { | |
39623e12 | 21784 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 21785 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 21786 | _("offset out of range")); |
b6895b4f PB |
21787 | } |
21788 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21789 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21790 | { | |
21791 | value >>= 16; | |
21792 | } | |
21793 | ||
21794 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21795 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21796 | { | |
21797 | newval = get_thumb32_insn (buf); | |
21798 | newval &= 0xfbf08f00; | |
21799 | newval |= (value & 0xf000) << 4; | |
21800 | newval |= (value & 0x0800) << 15; | |
21801 | newval |= (value & 0x0700) << 4; | |
21802 | newval |= (value & 0x00ff); | |
21803 | put_thumb32_insn (buf, newval); | |
21804 | } | |
21805 | else | |
21806 | { | |
21807 | newval = md_chars_to_number (buf, 4); | |
21808 | newval &= 0xfff0f000; | |
21809 | newval |= value & 0x0fff; | |
21810 | newval |= (value & 0xf000) << 4; | |
21811 | md_number_to_chars (buf, newval, 4); | |
21812 | } | |
21813 | } | |
21814 | return; | |
21815 | ||
4962c51a MS |
21816 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21817 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21818 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21819 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21820 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21821 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21822 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21823 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21824 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21825 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 21826 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21827 | if (!seg->use_rela_p) |
21828 | { | |
21829 | bfd_vma insn; | |
21830 | bfd_vma encoded_addend; | |
21831 | bfd_vma addend_abs = abs (value); | |
21832 | ||
21833 | /* Check that the absolute value of the addend can be | |
21834 | expressed as an 8-bit constant plus a rotation. */ | |
21835 | encoded_addend = encode_arm_immediate (addend_abs); | |
21836 | if (encoded_addend == (unsigned int) FAIL) | |
21837 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21838 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 21839 | (unsigned long) addend_abs); |
4962c51a MS |
21840 | |
21841 | /* Extract the instruction. */ | |
21842 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21843 | ||
21844 | /* If the addend is positive, use an ADD instruction. | |
21845 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
21846 | insn &= 0xff1fffff; | |
21847 | if (value < 0) | |
21848 | insn |= 1 << 22; | |
21849 | else | |
21850 | insn |= 1 << 23; | |
21851 | ||
21852 | /* Place the encoded addend into the first 12 bits of the | |
21853 | instruction. */ | |
21854 | insn &= 0xfffff000; | |
21855 | insn |= encoded_addend; | |
5f4273c7 NC |
21856 | |
21857 | /* Update the instruction. */ | |
4962c51a MS |
21858 | md_number_to_chars (buf, insn, INSN_SIZE); |
21859 | } | |
21860 | break; | |
21861 | ||
21862 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21863 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21864 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21865 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21866 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21867 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 21868 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21869 | if (!seg->use_rela_p) |
21870 | { | |
21871 | bfd_vma insn; | |
21872 | bfd_vma addend_abs = abs (value); | |
21873 | ||
21874 | /* Check that the absolute value of the addend can be | |
21875 | encoded in 12 bits. */ | |
21876 | if (addend_abs >= 0x1000) | |
21877 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21878 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 21879 | (unsigned long) addend_abs); |
4962c51a MS |
21880 | |
21881 | /* Extract the instruction. */ | |
21882 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21883 | ||
21884 | /* If the addend is negative, clear bit 23 of the instruction. | |
21885 | Otherwise set it. */ | |
21886 | if (value < 0) | |
21887 | insn &= ~(1 << 23); | |
21888 | else | |
21889 | insn |= 1 << 23; | |
21890 | ||
21891 | /* Place the absolute value of the addend into the first 12 bits | |
21892 | of the instruction. */ | |
21893 | insn &= 0xfffff000; | |
21894 | insn |= addend_abs; | |
5f4273c7 NC |
21895 | |
21896 | /* Update the instruction. */ | |
4962c51a MS |
21897 | md_number_to_chars (buf, insn, INSN_SIZE); |
21898 | } | |
21899 | break; | |
21900 | ||
21901 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21902 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21903 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21904 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21905 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21906 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 21907 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21908 | if (!seg->use_rela_p) |
21909 | { | |
21910 | bfd_vma insn; | |
21911 | bfd_vma addend_abs = abs (value); | |
21912 | ||
21913 | /* Check that the absolute value of the addend can be | |
21914 | encoded in 8 bits. */ | |
21915 | if (addend_abs >= 0x100) | |
21916 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21917 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 21918 | (unsigned long) addend_abs); |
4962c51a MS |
21919 | |
21920 | /* Extract the instruction. */ | |
21921 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21922 | ||
21923 | /* If the addend is negative, clear bit 23 of the instruction. | |
21924 | Otherwise set it. */ | |
21925 | if (value < 0) | |
21926 | insn &= ~(1 << 23); | |
21927 | else | |
21928 | insn |= 1 << 23; | |
21929 | ||
21930 | /* Place the first four bits of the absolute value of the addend | |
21931 | into the first 4 bits of the instruction, and the remaining | |
21932 | four into bits 8 .. 11. */ | |
21933 | insn &= 0xfffff0f0; | |
21934 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
21935 | |
21936 | /* Update the instruction. */ | |
4962c51a MS |
21937 | md_number_to_chars (buf, insn, INSN_SIZE); |
21938 | } | |
21939 | break; | |
21940 | ||
21941 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21942 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21943 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21944 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21945 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21946 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 21947 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21948 | if (!seg->use_rela_p) |
21949 | { | |
21950 | bfd_vma insn; | |
21951 | bfd_vma addend_abs = abs (value); | |
21952 | ||
21953 | /* Check that the absolute value of the addend is a multiple of | |
21954 | four and, when divided by four, fits in 8 bits. */ | |
21955 | if (addend_abs & 0x3) | |
21956 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21957 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 21958 | (unsigned long) addend_abs); |
4962c51a MS |
21959 | |
21960 | if ((addend_abs >> 2) > 0xff) | |
21961 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21962 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 21963 | (unsigned long) addend_abs); |
4962c51a MS |
21964 | |
21965 | /* Extract the instruction. */ | |
21966 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21967 | ||
21968 | /* If the addend is negative, clear bit 23 of the instruction. | |
21969 | Otherwise set it. */ | |
21970 | if (value < 0) | |
21971 | insn &= ~(1 << 23); | |
21972 | else | |
21973 | insn |= 1 << 23; | |
21974 | ||
21975 | /* Place the addend (divided by four) into the first eight | |
21976 | bits of the instruction. */ | |
21977 | insn &= 0xfffffff0; | |
21978 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
21979 | |
21980 | /* Update the instruction. */ | |
4962c51a MS |
21981 | md_number_to_chars (buf, insn, INSN_SIZE); |
21982 | } | |
21983 | break; | |
21984 | ||
845b51d6 PB |
21985 | case BFD_RELOC_ARM_V4BX: |
21986 | /* This will need to go in the object file. */ | |
21987 | fixP->fx_done = 0; | |
21988 | break; | |
21989 | ||
c19d1205 ZW |
21990 | case BFD_RELOC_UNUSED: |
21991 | default: | |
21992 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21993 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
21994 | } | |
6c43fab6 RE |
21995 | } |
21996 | ||
c19d1205 ZW |
21997 | /* Translate internal representation of relocation info to BFD target |
21998 | format. */ | |
a737bd4d | 21999 | |
c19d1205 | 22000 | arelent * |
00a97672 | 22001 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 22002 | { |
c19d1205 ZW |
22003 | arelent * reloc; |
22004 | bfd_reloc_code_real_type code; | |
a737bd4d | 22005 | |
21d799b5 | 22006 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 22007 | |
21d799b5 | 22008 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
22009 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
22010 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 22011 | |
2fc8bdac | 22012 | if (fixp->fx_pcrel) |
00a97672 RS |
22013 | { |
22014 | if (section->use_rela_p) | |
22015 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
22016 | else | |
22017 | fixp->fx_offset = reloc->address; | |
22018 | } | |
c19d1205 | 22019 | reloc->addend = fixp->fx_offset; |
a737bd4d | 22020 | |
c19d1205 | 22021 | switch (fixp->fx_r_type) |
a737bd4d | 22022 | { |
c19d1205 ZW |
22023 | case BFD_RELOC_8: |
22024 | if (fixp->fx_pcrel) | |
22025 | { | |
22026 | code = BFD_RELOC_8_PCREL; | |
22027 | break; | |
22028 | } | |
a737bd4d | 22029 | |
c19d1205 ZW |
22030 | case BFD_RELOC_16: |
22031 | if (fixp->fx_pcrel) | |
22032 | { | |
22033 | code = BFD_RELOC_16_PCREL; | |
22034 | break; | |
22035 | } | |
6c43fab6 | 22036 | |
c19d1205 ZW |
22037 | case BFD_RELOC_32: |
22038 | if (fixp->fx_pcrel) | |
22039 | { | |
22040 | code = BFD_RELOC_32_PCREL; | |
22041 | break; | |
22042 | } | |
a737bd4d | 22043 | |
b6895b4f PB |
22044 | case BFD_RELOC_ARM_MOVW: |
22045 | if (fixp->fx_pcrel) | |
22046 | { | |
22047 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
22048 | break; | |
22049 | } | |
22050 | ||
22051 | case BFD_RELOC_ARM_MOVT: | |
22052 | if (fixp->fx_pcrel) | |
22053 | { | |
22054 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
22055 | break; | |
22056 | } | |
22057 | ||
22058 | case BFD_RELOC_ARM_THUMB_MOVW: | |
22059 | if (fixp->fx_pcrel) | |
22060 | { | |
22061 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
22062 | break; | |
22063 | } | |
22064 | ||
22065 | case BFD_RELOC_ARM_THUMB_MOVT: | |
22066 | if (fixp->fx_pcrel) | |
22067 | { | |
22068 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
22069 | break; | |
22070 | } | |
22071 | ||
c19d1205 ZW |
22072 | case BFD_RELOC_NONE: |
22073 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
22074 | case BFD_RELOC_ARM_PCREL_BLX: | |
22075 | case BFD_RELOC_RVA: | |
22076 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
22077 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
22078 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
22079 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
22080 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
22081 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
22082 | case BFD_RELOC_VTABLE_ENTRY: |
22083 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
22084 | #ifdef TE_PE |
22085 | case BFD_RELOC_32_SECREL: | |
22086 | #endif | |
c19d1205 ZW |
22087 | code = fixp->fx_r_type; |
22088 | break; | |
a737bd4d | 22089 | |
00adf2d4 JB |
22090 | case BFD_RELOC_THUMB_PCREL_BLX: |
22091 | #ifdef OBJ_ELF | |
22092 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
22093 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
22094 | else | |
22095 | #endif | |
22096 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
22097 | break; | |
22098 | ||
c19d1205 ZW |
22099 | case BFD_RELOC_ARM_LITERAL: |
22100 | case BFD_RELOC_ARM_HWLITERAL: | |
22101 | /* If this is called then the a literal has | |
22102 | been referenced across a section boundary. */ | |
22103 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22104 | _("literal referenced across section boundary")); | |
22105 | return NULL; | |
a737bd4d | 22106 | |
c19d1205 | 22107 | #ifdef OBJ_ELF |
0855e32b NS |
22108 | case BFD_RELOC_ARM_TLS_CALL: |
22109 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
22110 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
22111 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
22112 | case BFD_RELOC_ARM_GOT32: |
22113 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 22114 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
22115 | case BFD_RELOC_ARM_PLT32: |
22116 | case BFD_RELOC_ARM_TARGET1: | |
22117 | case BFD_RELOC_ARM_ROSEGREL32: | |
22118 | case BFD_RELOC_ARM_SBREL32: | |
22119 | case BFD_RELOC_ARM_PREL31: | |
22120 | case BFD_RELOC_ARM_TARGET2: | |
22121 | case BFD_RELOC_ARM_TLS_LE32: | |
22122 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
22123 | case BFD_RELOC_ARM_PCREL_CALL: |
22124 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
22125 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
22126 | case BFD_RELOC_ARM_ALU_PC_G0: | |
22127 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
22128 | case BFD_RELOC_ARM_ALU_PC_G1: | |
22129 | case BFD_RELOC_ARM_ALU_PC_G2: | |
22130 | case BFD_RELOC_ARM_LDR_PC_G0: | |
22131 | case BFD_RELOC_ARM_LDR_PC_G1: | |
22132 | case BFD_RELOC_ARM_LDR_PC_G2: | |
22133 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
22134 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
22135 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
22136 | case BFD_RELOC_ARM_LDC_PC_G0: | |
22137 | case BFD_RELOC_ARM_LDC_PC_G1: | |
22138 | case BFD_RELOC_ARM_LDC_PC_G2: | |
22139 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
22140 | case BFD_RELOC_ARM_ALU_SB_G0: | |
22141 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
22142 | case BFD_RELOC_ARM_ALU_SB_G1: | |
22143 | case BFD_RELOC_ARM_ALU_SB_G2: | |
22144 | case BFD_RELOC_ARM_LDR_SB_G0: | |
22145 | case BFD_RELOC_ARM_LDR_SB_G1: | |
22146 | case BFD_RELOC_ARM_LDR_SB_G2: | |
22147 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
22148 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
22149 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
22150 | case BFD_RELOC_ARM_LDC_SB_G0: | |
22151 | case BFD_RELOC_ARM_LDC_SB_G1: | |
22152 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 22153 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
22154 | code = fixp->fx_r_type; |
22155 | break; | |
a737bd4d | 22156 | |
0855e32b | 22157 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
22158 | case BFD_RELOC_ARM_TLS_GD32: |
22159 | case BFD_RELOC_ARM_TLS_IE32: | |
22160 | case BFD_RELOC_ARM_TLS_LDM32: | |
22161 | /* BFD will include the symbol's address in the addend. | |
22162 | But we don't want that, so subtract it out again here. */ | |
22163 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
22164 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
22165 | code = fixp->fx_r_type; | |
22166 | break; | |
22167 | #endif | |
a737bd4d | 22168 | |
c19d1205 ZW |
22169 | case BFD_RELOC_ARM_IMMEDIATE: |
22170 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22171 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
22172 | return NULL; | |
a737bd4d | 22173 | |
c19d1205 ZW |
22174 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
22175 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22176 | _("ADRL used for a symbol not defined in the same file")); | |
22177 | return NULL; | |
a737bd4d | 22178 | |
c19d1205 | 22179 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
22180 | if (section->use_rela_p) |
22181 | { | |
22182 | code = fixp->fx_r_type; | |
22183 | break; | |
22184 | } | |
22185 | ||
c19d1205 ZW |
22186 | if (fixp->fx_addsy != NULL |
22187 | && !S_IS_DEFINED (fixp->fx_addsy) | |
22188 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 22189 | { |
c19d1205 ZW |
22190 | as_bad_where (fixp->fx_file, fixp->fx_line, |
22191 | _("undefined local label `%s'"), | |
22192 | S_GET_NAME (fixp->fx_addsy)); | |
22193 | return NULL; | |
a737bd4d NC |
22194 | } |
22195 | ||
c19d1205 ZW |
22196 | as_bad_where (fixp->fx_file, fixp->fx_line, |
22197 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
22198 | return NULL; | |
a737bd4d | 22199 | |
c19d1205 ZW |
22200 | default: |
22201 | { | |
22202 | char * type; | |
6c43fab6 | 22203 | |
c19d1205 ZW |
22204 | switch (fixp->fx_r_type) |
22205 | { | |
22206 | case BFD_RELOC_NONE: type = "NONE"; break; | |
22207 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
22208 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 22209 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
22210 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
22211 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
22212 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 22213 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 22214 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
22215 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
22216 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
22217 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
22218 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
22219 | default: type = _("<unknown>"); break; | |
22220 | } | |
22221 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22222 | _("cannot represent %s relocation in this object file format"), | |
22223 | type); | |
22224 | return NULL; | |
22225 | } | |
a737bd4d | 22226 | } |
6c43fab6 | 22227 | |
c19d1205 ZW |
22228 | #ifdef OBJ_ELF |
22229 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
22230 | && GOT_symbol | |
22231 | && fixp->fx_addsy == GOT_symbol) | |
22232 | { | |
22233 | code = BFD_RELOC_ARM_GOTPC; | |
22234 | reloc->addend = fixp->fx_offset = reloc->address; | |
22235 | } | |
22236 | #endif | |
6c43fab6 | 22237 | |
c19d1205 | 22238 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 22239 | |
c19d1205 ZW |
22240 | if (reloc->howto == NULL) |
22241 | { | |
22242 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
22243 | _("cannot represent %s relocation in this object file format"), | |
22244 | bfd_get_reloc_code_name (code)); | |
22245 | return NULL; | |
22246 | } | |
6c43fab6 | 22247 | |
c19d1205 ZW |
22248 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
22249 | vtable entry to be used in the relocation's section offset. */ | |
22250 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
22251 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 22252 | |
c19d1205 | 22253 | return reloc; |
6c43fab6 RE |
22254 | } |
22255 | ||
c19d1205 | 22256 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 22257 | |
c19d1205 ZW |
22258 | void |
22259 | cons_fix_new_arm (fragS * frag, | |
22260 | int where, | |
22261 | int size, | |
22262 | expressionS * exp) | |
6c43fab6 | 22263 | { |
c19d1205 ZW |
22264 | bfd_reloc_code_real_type type; |
22265 | int pcrel = 0; | |
6c43fab6 | 22266 | |
c19d1205 ZW |
22267 | /* Pick a reloc. |
22268 | FIXME: @@ Should look at CPU word size. */ | |
22269 | switch (size) | |
22270 | { | |
22271 | case 1: | |
22272 | type = BFD_RELOC_8; | |
22273 | break; | |
22274 | case 2: | |
22275 | type = BFD_RELOC_16; | |
22276 | break; | |
22277 | case 4: | |
22278 | default: | |
22279 | type = BFD_RELOC_32; | |
22280 | break; | |
22281 | case 8: | |
22282 | type = BFD_RELOC_64; | |
22283 | break; | |
22284 | } | |
6c43fab6 | 22285 | |
f0927246 NC |
22286 | #ifdef TE_PE |
22287 | if (exp->X_op == O_secrel) | |
22288 | { | |
22289 | exp->X_op = O_symbol; | |
22290 | type = BFD_RELOC_32_SECREL; | |
22291 | } | |
22292 | #endif | |
22293 | ||
c19d1205 ZW |
22294 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
22295 | } | |
6c43fab6 | 22296 | |
4343666d | 22297 | #if defined (OBJ_COFF) |
c19d1205 ZW |
22298 | void |
22299 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 22300 | { |
c19d1205 ZW |
22301 | /* If the destination of the branch is a defined symbol which does not have |
22302 | the THUMB_FUNC attribute, then we must be calling a function which has | |
22303 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
22304 | function and change the branch to refer to that function instead. */ | |
22305 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
22306 | && fixP->fx_addsy != NULL | |
22307 | && S_IS_DEFINED (fixP->fx_addsy) | |
22308 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 22309 | { |
c19d1205 | 22310 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 22311 | } |
c19d1205 ZW |
22312 | } |
22313 | #endif | |
6c43fab6 | 22314 | |
267bf995 | 22315 | |
c19d1205 ZW |
22316 | int |
22317 | arm_force_relocation (struct fix * fixp) | |
22318 | { | |
22319 | #if defined (OBJ_COFF) && defined (TE_PE) | |
22320 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
22321 | return 1; | |
22322 | #endif | |
6c43fab6 | 22323 | |
267bf995 RR |
22324 | /* In case we have a call or a branch to a function in ARM ISA mode from |
22325 | a thumb function or vice-versa force the relocation. These relocations | |
22326 | are cleared off for some cores that might have blx and simple transformations | |
22327 | are possible. */ | |
22328 | ||
22329 | #ifdef OBJ_ELF | |
22330 | switch (fixp->fx_r_type) | |
22331 | { | |
22332 | case BFD_RELOC_ARM_PCREL_JUMP: | |
22333 | case BFD_RELOC_ARM_PCREL_CALL: | |
22334 | case BFD_RELOC_THUMB_PCREL_BLX: | |
22335 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
22336 | return 1; | |
22337 | break; | |
22338 | ||
22339 | case BFD_RELOC_ARM_PCREL_BLX: | |
22340 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
22341 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
22342 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
22343 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
22344 | return 1; | |
22345 | break; | |
22346 | ||
22347 | default: | |
22348 | break; | |
22349 | } | |
22350 | #endif | |
22351 | ||
b5884301 PB |
22352 | /* Resolve these relocations even if the symbol is extern or weak. |
22353 | Technically this is probably wrong due to symbol preemption. | |
22354 | In practice these relocations do not have enough range to be useful | |
22355 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
22356 | expects these references to be resolved. */ | |
c19d1205 ZW |
22357 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
22358 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 22359 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 22360 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
22361 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22362 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
22363 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 22364 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
22365 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
22366 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
22367 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
22368 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
22369 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
22370 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 22371 | return 0; |
a737bd4d | 22372 | |
4962c51a MS |
22373 | /* Always leave these relocations for the linker. */ |
22374 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22375 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22376 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
22377 | return 1; | |
22378 | ||
f0291e4c PB |
22379 | /* Always generate relocations against function symbols. */ |
22380 | if (fixp->fx_r_type == BFD_RELOC_32 | |
22381 | && fixp->fx_addsy | |
22382 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
22383 | return 1; | |
22384 | ||
c19d1205 | 22385 | return generic_force_reloc (fixp); |
404ff6b5 AH |
22386 | } |
22387 | ||
0ffdc86c | 22388 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
22389 | /* Relocations against function names must be left unadjusted, |
22390 | so that the linker can use this information to generate interworking | |
22391 | stubs. The MIPS version of this function | |
c19d1205 ZW |
22392 | also prevents relocations that are mips-16 specific, but I do not |
22393 | know why it does this. | |
404ff6b5 | 22394 | |
c19d1205 ZW |
22395 | FIXME: |
22396 | There is one other problem that ought to be addressed here, but | |
22397 | which currently is not: Taking the address of a label (rather | |
22398 | than a function) and then later jumping to that address. Such | |
22399 | addresses also ought to have their bottom bit set (assuming that | |
22400 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 22401 | |
c19d1205 ZW |
22402 | bfd_boolean |
22403 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 22404 | { |
c19d1205 ZW |
22405 | if (fixP->fx_addsy == NULL) |
22406 | return 1; | |
404ff6b5 | 22407 | |
e28387c3 PB |
22408 | /* Preserve relocations against symbols with function type. */ |
22409 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 22410 | return FALSE; |
e28387c3 | 22411 | |
c19d1205 ZW |
22412 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
22413 | && fixP->fx_subsy == NULL) | |
c921be7d | 22414 | return FALSE; |
a737bd4d | 22415 | |
c19d1205 ZW |
22416 | /* We need the symbol name for the VTABLE entries. */ |
22417 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
22418 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 22419 | return FALSE; |
404ff6b5 | 22420 | |
c19d1205 ZW |
22421 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
22422 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
22423 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
22424 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
22425 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
22426 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
22427 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
22428 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
22429 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
22430 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
22431 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
22432 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
22433 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
22434 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 22435 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 22436 | return FALSE; |
a737bd4d | 22437 | |
4962c51a MS |
22438 | /* Similarly for group relocations. */ |
22439 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22440 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22441 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 22442 | return FALSE; |
4962c51a | 22443 | |
79947c54 CD |
22444 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
22445 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
22446 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
22447 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
22448 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
22449 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
22450 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
22451 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
22452 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 22453 | return FALSE; |
79947c54 | 22454 | |
c921be7d | 22455 | return TRUE; |
a737bd4d | 22456 | } |
0ffdc86c NC |
22457 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
22458 | ||
22459 | #ifdef OBJ_ELF | |
404ff6b5 | 22460 | |
c19d1205 ZW |
22461 | const char * |
22462 | elf32_arm_target_format (void) | |
404ff6b5 | 22463 | { |
c19d1205 ZW |
22464 | #ifdef TE_SYMBIAN |
22465 | return (target_big_endian | |
22466 | ? "elf32-bigarm-symbian" | |
22467 | : "elf32-littlearm-symbian"); | |
22468 | #elif defined (TE_VXWORKS) | |
22469 | return (target_big_endian | |
22470 | ? "elf32-bigarm-vxworks" | |
22471 | : "elf32-littlearm-vxworks"); | |
b38cadfb NC |
22472 | #elif defined (TE_NACL) |
22473 | return (target_big_endian | |
22474 | ? "elf32-bigarm-nacl" | |
22475 | : "elf32-littlearm-nacl"); | |
c19d1205 ZW |
22476 | #else |
22477 | if (target_big_endian) | |
22478 | return "elf32-bigarm"; | |
22479 | else | |
22480 | return "elf32-littlearm"; | |
22481 | #endif | |
404ff6b5 AH |
22482 | } |
22483 | ||
c19d1205 ZW |
22484 | void |
22485 | armelf_frob_symbol (symbolS * symp, | |
22486 | int * puntp) | |
404ff6b5 | 22487 | { |
c19d1205 ZW |
22488 | elf_frob_symbol (symp, puntp); |
22489 | } | |
22490 | #endif | |
404ff6b5 | 22491 | |
c19d1205 | 22492 | /* MD interface: Finalization. */ |
a737bd4d | 22493 | |
c19d1205 ZW |
22494 | void |
22495 | arm_cleanup (void) | |
22496 | { | |
22497 | literal_pool * pool; | |
a737bd4d | 22498 | |
e07e6e58 NC |
22499 | /* Ensure that all the IT blocks are properly closed. */ |
22500 | check_it_blocks_finished (); | |
22501 | ||
c19d1205 ZW |
22502 | for (pool = list_of_pools; pool; pool = pool->next) |
22503 | { | |
5f4273c7 | 22504 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
22505 | subseg_set (pool->section, pool->sub_section); |
22506 | #ifdef OBJ_ELF | |
22507 | arm_elf_change_section (); | |
22508 | #endif | |
22509 | s_ltorg (0); | |
22510 | } | |
404ff6b5 AH |
22511 | } |
22512 | ||
cd000bff DJ |
22513 | #ifdef OBJ_ELF |
22514 | /* Remove any excess mapping symbols generated for alignment frags in | |
22515 | SEC. We may have created a mapping symbol before a zero byte | |
22516 | alignment; remove it if there's a mapping symbol after the | |
22517 | alignment. */ | |
22518 | static void | |
22519 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
22520 | void *dummy ATTRIBUTE_UNUSED) | |
22521 | { | |
22522 | segment_info_type *seginfo = seg_info (sec); | |
22523 | fragS *fragp; | |
22524 | ||
22525 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
22526 | return; | |
22527 | ||
22528 | for (fragp = seginfo->frchainP->frch_root; | |
22529 | fragp != NULL; | |
22530 | fragp = fragp->fr_next) | |
22531 | { | |
22532 | symbolS *sym = fragp->tc_frag_data.last_map; | |
22533 | fragS *next = fragp->fr_next; | |
22534 | ||
22535 | /* Variable-sized frags have been converted to fixed size by | |
22536 | this point. But if this was variable-sized to start with, | |
22537 | there will be a fixed-size frag after it. So don't handle | |
22538 | next == NULL. */ | |
22539 | if (sym == NULL || next == NULL) | |
22540 | continue; | |
22541 | ||
22542 | if (S_GET_VALUE (sym) < next->fr_address) | |
22543 | /* Not at the end of this frag. */ | |
22544 | continue; | |
22545 | know (S_GET_VALUE (sym) == next->fr_address); | |
22546 | ||
22547 | do | |
22548 | { | |
22549 | if (next->tc_frag_data.first_map != NULL) | |
22550 | { | |
22551 | /* Next frag starts with a mapping symbol. Discard this | |
22552 | one. */ | |
22553 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22554 | break; | |
22555 | } | |
22556 | ||
22557 | if (next->fr_next == NULL) | |
22558 | { | |
22559 | /* This mapping symbol is at the end of the section. Discard | |
22560 | it. */ | |
22561 | know (next->fr_fix == 0 && next->fr_var == 0); | |
22562 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22563 | break; | |
22564 | } | |
22565 | ||
22566 | /* As long as we have empty frags without any mapping symbols, | |
22567 | keep looking. */ | |
22568 | /* If the next frag is non-empty and does not start with a | |
22569 | mapping symbol, then this mapping symbol is required. */ | |
22570 | if (next->fr_address != next->fr_next->fr_address) | |
22571 | break; | |
22572 | ||
22573 | next = next->fr_next; | |
22574 | } | |
22575 | while (next != NULL); | |
22576 | } | |
22577 | } | |
22578 | #endif | |
22579 | ||
c19d1205 ZW |
22580 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
22581 | ARM ones. */ | |
404ff6b5 | 22582 | |
c19d1205 ZW |
22583 | void |
22584 | arm_adjust_symtab (void) | |
404ff6b5 | 22585 | { |
c19d1205 ZW |
22586 | #ifdef OBJ_COFF |
22587 | symbolS * sym; | |
404ff6b5 | 22588 | |
c19d1205 ZW |
22589 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
22590 | { | |
22591 | if (ARM_IS_THUMB (sym)) | |
22592 | { | |
22593 | if (THUMB_IS_FUNC (sym)) | |
22594 | { | |
22595 | /* Mark the symbol as a Thumb function. */ | |
22596 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
22597 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
22598 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 22599 | |
c19d1205 ZW |
22600 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
22601 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
22602 | else | |
22603 | as_bad (_("%s: unexpected function type: %d"), | |
22604 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
22605 | } | |
22606 | else switch (S_GET_STORAGE_CLASS (sym)) | |
22607 | { | |
22608 | case C_EXT: | |
22609 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
22610 | break; | |
22611 | case C_STAT: | |
22612 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
22613 | break; | |
22614 | case C_LABEL: | |
22615 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
22616 | break; | |
22617 | default: | |
22618 | /* Do nothing. */ | |
22619 | break; | |
22620 | } | |
22621 | } | |
a737bd4d | 22622 | |
c19d1205 ZW |
22623 | if (ARM_IS_INTERWORK (sym)) |
22624 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 22625 | } |
c19d1205 ZW |
22626 | #endif |
22627 | #ifdef OBJ_ELF | |
22628 | symbolS * sym; | |
22629 | char bind; | |
404ff6b5 | 22630 | |
c19d1205 | 22631 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 22632 | { |
c19d1205 ZW |
22633 | if (ARM_IS_THUMB (sym)) |
22634 | { | |
22635 | elf_symbol_type * elf_sym; | |
404ff6b5 | 22636 | |
c19d1205 ZW |
22637 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
22638 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 22639 | |
b0796911 PB |
22640 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
22641 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
22642 | { |
22643 | /* If it's a .thumb_func, declare it as so, | |
22644 | otherwise tag label as .code 16. */ | |
22645 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
22646 | elf_sym->internal_elf_sym.st_target_internal |
22647 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 22648 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
22649 | elf_sym->internal_elf_sym.st_info = |
22650 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
22651 | } | |
22652 | } | |
22653 | } | |
cd000bff DJ |
22654 | |
22655 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
22656 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
22657 | /* Now do generic ELF adjustments. */ |
22658 | elf_adjust_symtab (); | |
c19d1205 | 22659 | #endif |
404ff6b5 AH |
22660 | } |
22661 | ||
c19d1205 | 22662 | /* MD interface: Initialization. */ |
404ff6b5 | 22663 | |
a737bd4d | 22664 | static void |
c19d1205 | 22665 | set_constant_flonums (void) |
a737bd4d | 22666 | { |
c19d1205 | 22667 | int i; |
404ff6b5 | 22668 | |
c19d1205 ZW |
22669 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
22670 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
22671 | abort (); | |
a737bd4d | 22672 | } |
404ff6b5 | 22673 | |
3e9e4fcf JB |
22674 | /* Auto-select Thumb mode if it's the only available instruction set for the |
22675 | given architecture. */ | |
22676 | ||
22677 | static void | |
22678 | autoselect_thumb_from_cpu_variant (void) | |
22679 | { | |
22680 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
22681 | opcode_select (16); | |
22682 | } | |
22683 | ||
c19d1205 ZW |
22684 | void |
22685 | md_begin (void) | |
a737bd4d | 22686 | { |
c19d1205 ZW |
22687 | unsigned mach; |
22688 | unsigned int i; | |
404ff6b5 | 22689 | |
c19d1205 ZW |
22690 | if ( (arm_ops_hsh = hash_new ()) == NULL |
22691 | || (arm_cond_hsh = hash_new ()) == NULL | |
22692 | || (arm_shift_hsh = hash_new ()) == NULL | |
22693 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 22694 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 22695 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
22696 | || (arm_reloc_hsh = hash_new ()) == NULL |
22697 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
22698 | as_fatal (_("virtual memory exhausted")); |
22699 | ||
22700 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 22701 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 22702 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 22703 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 22704 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 22705 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 22706 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 22707 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 22708 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
22709 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
22710 | (void *) (v7m_psrs + i)); | |
c19d1205 | 22711 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 22712 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
22713 | for (i = 0; |
22714 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
22715 | i++) | |
d3ce72d0 | 22716 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 22717 | (void *) (barrier_opt_names + i)); |
c19d1205 | 22718 | #ifdef OBJ_ELF |
3da1d841 NC |
22719 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
22720 | { | |
22721 | struct reloc_entry * entry = reloc_names + i; | |
22722 | ||
22723 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
22724 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
22725 | entry->reloc = BFD_RELOC_UNUSED; | |
22726 | ||
22727 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
22728 | } | |
c19d1205 ZW |
22729 | #endif |
22730 | ||
22731 | set_constant_flonums (); | |
404ff6b5 | 22732 | |
c19d1205 ZW |
22733 | /* Set the cpu variant based on the command-line options. We prefer |
22734 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
22735 | -mfpu= over any other way of setting the floating point unit. | |
22736 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 22737 | if (legacy_cpu) |
404ff6b5 | 22738 | { |
e74cfd16 | 22739 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
22740 | as_bad (_("use of old and new-style options to set CPU type")); |
22741 | ||
22742 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 22743 | } |
e74cfd16 | 22744 | else if (!mcpu_cpu_opt) |
c19d1205 | 22745 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 22746 | |
e74cfd16 | 22747 | if (legacy_fpu) |
c19d1205 | 22748 | { |
e74cfd16 | 22749 | if (mfpu_opt) |
c19d1205 | 22750 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
22751 | |
22752 | mfpu_opt = legacy_fpu; | |
22753 | } | |
e74cfd16 | 22754 | else if (!mfpu_opt) |
03b1477f | 22755 | { |
45eb4c1b NS |
22756 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
22757 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
22758 | /* Some environments specify a default FPU. If they don't, infer it |
22759 | from the processor. */ | |
e74cfd16 | 22760 | if (mcpu_fpu_opt) |
03b1477f RE |
22761 | mfpu_opt = mcpu_fpu_opt; |
22762 | else | |
22763 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 22764 | #else |
e74cfd16 | 22765 | mfpu_opt = &fpu_default; |
39c2da32 | 22766 | #endif |
03b1477f RE |
22767 | } |
22768 | ||
e74cfd16 | 22769 | if (!mfpu_opt) |
03b1477f | 22770 | { |
493cb6ef | 22771 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 22772 | mfpu_opt = &fpu_default; |
493cb6ef | 22773 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 22774 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 22775 | else |
e74cfd16 | 22776 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
22777 | } |
22778 | ||
ee065d83 | 22779 | #ifdef CPU_DEFAULT |
e74cfd16 | 22780 | if (!mcpu_cpu_opt) |
ee065d83 | 22781 | { |
e74cfd16 PB |
22782 | mcpu_cpu_opt = &cpu_default; |
22783 | selected_cpu = cpu_default; | |
ee065d83 | 22784 | } |
e74cfd16 PB |
22785 | #else |
22786 | if (mcpu_cpu_opt) | |
22787 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 22788 | else |
e74cfd16 | 22789 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 22790 | #endif |
03b1477f | 22791 | |
e74cfd16 | 22792 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 22793 | |
3e9e4fcf JB |
22794 | autoselect_thumb_from_cpu_variant (); |
22795 | ||
e74cfd16 | 22796 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 22797 | |
f17c130b | 22798 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 22799 | { |
7cc69913 NC |
22800 | unsigned int flags = 0; |
22801 | ||
22802 | #if defined OBJ_ELF | |
22803 | flags = meabi_flags; | |
d507cf36 PB |
22804 | |
22805 | switch (meabi_flags) | |
33a392fb | 22806 | { |
d507cf36 | 22807 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 22808 | #endif |
d507cf36 PB |
22809 | /* Set the flags in the private structure. */ |
22810 | if (uses_apcs_26) flags |= F_APCS26; | |
22811 | if (support_interwork) flags |= F_INTERWORK; | |
22812 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 22813 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 22814 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
22815 | flags |= F_SOFT_FLOAT; |
22816 | ||
d507cf36 PB |
22817 | switch (mfloat_abi_opt) |
22818 | { | |
22819 | case ARM_FLOAT_ABI_SOFT: | |
22820 | case ARM_FLOAT_ABI_SOFTFP: | |
22821 | flags |= F_SOFT_FLOAT; | |
22822 | break; | |
33a392fb | 22823 | |
d507cf36 PB |
22824 | case ARM_FLOAT_ABI_HARD: |
22825 | if (flags & F_SOFT_FLOAT) | |
22826 | as_bad (_("hard-float conflicts with specified fpu")); | |
22827 | break; | |
22828 | } | |
03b1477f | 22829 | |
e74cfd16 PB |
22830 | /* Using pure-endian doubles (even if soft-float). */ |
22831 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 22832 | flags |= F_VFP_FLOAT; |
f17c130b | 22833 | |
fde78edd | 22834 | #if defined OBJ_ELF |
e74cfd16 | 22835 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 22836 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
22837 | break; |
22838 | ||
8cb51566 | 22839 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 22840 | case EF_ARM_EABI_VER5: |
c19d1205 | 22841 | /* No additional flags to set. */ |
d507cf36 PB |
22842 | break; |
22843 | ||
22844 | default: | |
22845 | abort (); | |
22846 | } | |
7cc69913 | 22847 | #endif |
b99bd4ef NC |
22848 | bfd_set_private_flags (stdoutput, flags); |
22849 | ||
22850 | /* We have run out flags in the COFF header to encode the | |
22851 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 22852 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
22853 | if (atpcs) |
22854 | { | |
22855 | asection * sec; | |
22856 | ||
22857 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
22858 | ||
22859 | if (sec != NULL) | |
22860 | { | |
22861 | bfd_set_section_flags | |
22862 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
22863 | bfd_set_section_size (stdoutput, sec, 0); | |
22864 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
22865 | } | |
22866 | } | |
7cc69913 | 22867 | } |
f17c130b | 22868 | #endif |
b99bd4ef NC |
22869 | |
22870 | /* Record the CPU type as well. */ | |
2d447fca JM |
22871 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
22872 | mach = bfd_mach_arm_iWMMXt2; | |
22873 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 22874 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 22875 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 22876 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 22877 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 22878 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 22879 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 22880 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 22881 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 22882 | { |
e74cfd16 | 22883 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22884 | mach = bfd_mach_arm_5T; |
22885 | else | |
22886 | mach = bfd_mach_arm_5; | |
22887 | } | |
e74cfd16 | 22888 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 22889 | { |
e74cfd16 | 22890 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22891 | mach = bfd_mach_arm_4T; |
22892 | else | |
22893 | mach = bfd_mach_arm_4; | |
22894 | } | |
e74cfd16 | 22895 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 22896 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
22897 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
22898 | mach = bfd_mach_arm_3; | |
22899 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
22900 | mach = bfd_mach_arm_2a; | |
22901 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
22902 | mach = bfd_mach_arm_2; | |
22903 | else | |
22904 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
22905 | |
22906 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
22907 | } | |
22908 | ||
c19d1205 | 22909 | /* Command line processing. */ |
b99bd4ef | 22910 | |
c19d1205 ZW |
22911 | /* md_parse_option |
22912 | Invocation line includes a switch not recognized by the base assembler. | |
22913 | See if it's a processor-specific option. | |
b99bd4ef | 22914 | |
c19d1205 ZW |
22915 | This routine is somewhat complicated by the need for backwards |
22916 | compatibility (since older releases of gcc can't be changed). | |
22917 | The new options try to make the interface as compatible as | |
22918 | possible with GCC. | |
b99bd4ef | 22919 | |
c19d1205 | 22920 | New options (supported) are: |
b99bd4ef | 22921 | |
c19d1205 ZW |
22922 | -mcpu=<cpu name> Assemble for selected processor |
22923 | -march=<architecture name> Assemble for selected architecture | |
22924 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
22925 | -EB/-mbig-endian Big-endian | |
22926 | -EL/-mlittle-endian Little-endian | |
22927 | -k Generate PIC code | |
22928 | -mthumb Start in Thumb mode | |
22929 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 22930 | |
278df34e | 22931 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 22932 | |
c19d1205 | 22933 | For now we will also provide support for: |
b99bd4ef | 22934 | |
c19d1205 ZW |
22935 | -mapcs-32 32-bit Program counter |
22936 | -mapcs-26 26-bit Program counter | |
22937 | -macps-float Floats passed in FP registers | |
22938 | -mapcs-reentrant Reentrant code | |
22939 | -matpcs | |
22940 | (sometime these will probably be replaced with -mapcs=<list of options> | |
22941 | and -matpcs=<list of options>) | |
b99bd4ef | 22942 | |
c19d1205 ZW |
22943 | The remaining options are only supported for back-wards compatibility. |
22944 | Cpu variants, the arm part is optional: | |
22945 | -m[arm]1 Currently not supported. | |
22946 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
22947 | -m[arm]3 Arm 3 processor | |
22948 | -m[arm]6[xx], Arm 6 processors | |
22949 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
22950 | -m[arm]8[10] Arm 8 processors | |
22951 | -m[arm]9[20][tdmi] Arm 9 processors | |
22952 | -mstrongarm[110[0]] StrongARM processors | |
22953 | -mxscale XScale processors | |
22954 | -m[arm]v[2345[t[e]]] Arm architectures | |
22955 | -mall All (except the ARM1) | |
22956 | FP variants: | |
22957 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
22958 | -mfpe-old (No float load/store multiples) | |
22959 | -mvfpxd VFP Single precision | |
22960 | -mvfp All VFP | |
22961 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 22962 | |
c19d1205 ZW |
22963 | The following CPU names are recognized: |
22964 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
22965 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
22966 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
22967 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
22968 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
22969 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
22970 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 22971 | |
c19d1205 | 22972 | */ |
b99bd4ef | 22973 | |
c19d1205 | 22974 | const char * md_shortopts = "m:k"; |
b99bd4ef | 22975 | |
c19d1205 ZW |
22976 | #ifdef ARM_BI_ENDIAN |
22977 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
22978 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 22979 | #else |
c19d1205 ZW |
22980 | #if TARGET_BYTES_BIG_ENDIAN |
22981 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 22982 | #else |
c19d1205 ZW |
22983 | #define OPTION_EL (OPTION_MD_BASE + 1) |
22984 | #endif | |
b99bd4ef | 22985 | #endif |
845b51d6 | 22986 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 22987 | |
c19d1205 | 22988 | struct option md_longopts[] = |
b99bd4ef | 22989 | { |
c19d1205 ZW |
22990 | #ifdef OPTION_EB |
22991 | {"EB", no_argument, NULL, OPTION_EB}, | |
22992 | #endif | |
22993 | #ifdef OPTION_EL | |
22994 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 22995 | #endif |
845b51d6 | 22996 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
22997 | {NULL, no_argument, NULL, 0} |
22998 | }; | |
b99bd4ef | 22999 | |
c19d1205 | 23000 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 23001 | |
c19d1205 | 23002 | struct arm_option_table |
b99bd4ef | 23003 | { |
c19d1205 ZW |
23004 | char *option; /* Option name to match. */ |
23005 | char *help; /* Help information. */ | |
23006 | int *var; /* Variable to change. */ | |
23007 | int value; /* What to change it to. */ | |
23008 | char *deprecated; /* If non-null, print this message. */ | |
23009 | }; | |
b99bd4ef | 23010 | |
c19d1205 ZW |
23011 | struct arm_option_table arm_opts[] = |
23012 | { | |
23013 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
23014 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
23015 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
23016 | &support_interwork, 1, NULL}, | |
23017 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
23018 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
23019 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
23020 | 1, NULL}, | |
23021 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
23022 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
23023 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
23024 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
23025 | NULL}, | |
b99bd4ef | 23026 | |
c19d1205 ZW |
23027 | /* These are recognized by the assembler, but have no affect on code. */ |
23028 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
23029 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
23030 | |
23031 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
23032 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
23033 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
23034 | {NULL, NULL, NULL, 0, NULL} |
23035 | }; | |
23036 | ||
23037 | struct arm_legacy_option_table | |
23038 | { | |
23039 | char *option; /* Option name to match. */ | |
23040 | const arm_feature_set **var; /* Variable to change. */ | |
23041 | const arm_feature_set value; /* What to change it to. */ | |
23042 | char *deprecated; /* If non-null, print this message. */ | |
23043 | }; | |
b99bd4ef | 23044 | |
e74cfd16 PB |
23045 | const struct arm_legacy_option_table arm_legacy_opts[] = |
23046 | { | |
c19d1205 ZW |
23047 | /* DON'T add any new processors to this list -- we want the whole list |
23048 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
23049 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
23050 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
23051 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
23052 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
23053 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
23054 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
23055 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
23056 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
23057 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
23058 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
23059 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
23060 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
23061 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
23062 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
23063 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
23064 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
23065 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
23066 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
23067 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
23068 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
23069 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
23070 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
23071 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
23072 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
23073 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
23074 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
23075 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
23076 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
23077 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
23078 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
23079 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
23080 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
23081 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
23082 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
23083 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
23084 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
23085 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
23086 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
23087 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
23088 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
23089 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
23090 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
23091 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
23092 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
23093 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
23094 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
23095 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23096 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23097 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23098 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
23099 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
23100 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
23101 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
23102 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
23103 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
23104 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
23105 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
23106 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
23107 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
23108 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
23109 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
23110 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
23111 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
23112 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
23113 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
23114 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
23115 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
23116 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
23117 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
23118 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 23119 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 23120 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 23121 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 23122 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 23123 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
23124 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
23125 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
23126 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 23127 | |
c19d1205 | 23128 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
23129 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
23130 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
23131 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
23132 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
23133 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
23134 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
23135 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
23136 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
23137 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
23138 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
23139 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
23140 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
23141 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
23142 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
23143 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
23144 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
23145 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
23146 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 23147 | |
c19d1205 | 23148 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
23149 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
23150 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
23151 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
23152 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 23153 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 23154 | |
e74cfd16 | 23155 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 23156 | }; |
7ed4c4c5 | 23157 | |
c19d1205 | 23158 | struct arm_cpu_option_table |
7ed4c4c5 | 23159 | { |
c19d1205 | 23160 | char *name; |
f3bad469 | 23161 | size_t name_len; |
e74cfd16 | 23162 | const arm_feature_set value; |
c19d1205 ZW |
23163 | /* For some CPUs we assume an FPU unless the user explicitly sets |
23164 | -mfpu=... */ | |
e74cfd16 | 23165 | const arm_feature_set default_fpu; |
ee065d83 PB |
23166 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
23167 | case. */ | |
23168 | const char *canonical_name; | |
c19d1205 | 23169 | }; |
7ed4c4c5 | 23170 | |
c19d1205 ZW |
23171 | /* This list should, at a minimum, contain all the cpu names |
23172 | recognized by GCC. */ | |
f3bad469 | 23173 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 23174 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 23175 | { |
f3bad469 MGD |
23176 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
23177 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
23178 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
23179 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
23180 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
23181 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23182 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23183 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23184 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23185 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23186 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23187 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
23188 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23189 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
23190 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23191 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
23192 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23193 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23194 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23195 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23196 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23197 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23198 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23199 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23200 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23201 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23202 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23203 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
23204 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23205 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23206 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23207 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23208 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23209 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23210 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23211 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23212 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23213 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23214 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23215 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
23216 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23217 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23218 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23219 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
23220 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
23221 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
23222 | /* For V5 or later processors we default to using VFP; but the user |
23223 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
23224 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
23225 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23226 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
23227 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
23228 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
23229 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
23230 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
23231 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23232 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
23233 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
23234 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23235 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23236 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
23237 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
23238 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23239 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
23240 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
23241 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23242 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23243 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
23244 | "ARM1026EJ-S"), | |
23245 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
23246 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23247 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23248 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23249 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23250 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
23251 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
23252 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
23253 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
23254 | "ARM1136JF-S"), | |
23255 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
23256 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
23257 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
23258 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
23259 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
23260 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL), | |
23261 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL), | |
23262 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, | |
23263 | FPU_NONE, "Cortex-A5"), | |
23264 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, | |
23265 | FPU_ARCH_NEON_VFP_V4, | |
23266 | "Cortex-A7"), | |
23267 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
23268 | ARM_FEATURE (0, FPU_VFP_V3 | |
5287ad62 | 23269 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
23270 | "Cortex-A8"), |
23271 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
23272 | ARM_FEATURE (0, FPU_VFP_V3 | |
15290f0a | 23273 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
23274 | "Cortex-A9"), |
23275 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, | |
23276 | FPU_ARCH_NEON_VFP_V4, | |
23277 | "Cortex-A15"), | |
23278 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), | |
23279 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
23280 | "Cortex-R4F"), | |
23281 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
23282 | FPU_NONE, "Cortex-R5"), | |
23283 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), | |
23284 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
23285 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
23286 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
ce32bd10 | 23287 | ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), |
c19d1205 | 23288 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 23289 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 23290 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
23291 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
23292 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
23293 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 23294 | /* Maverick */ |
f3bad469 MGD |
23295 | ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
23296 | FPU_ARCH_MAVERICK, | |
23297 | "ARM920T"), | |
23298 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } | |
c19d1205 | 23299 | }; |
f3bad469 | 23300 | #undef ARM_CPU_OPT |
7ed4c4c5 | 23301 | |
c19d1205 | 23302 | struct arm_arch_option_table |
7ed4c4c5 | 23303 | { |
c19d1205 | 23304 | char *name; |
f3bad469 | 23305 | size_t name_len; |
e74cfd16 PB |
23306 | const arm_feature_set value; |
23307 | const arm_feature_set default_fpu; | |
c19d1205 | 23308 | }; |
7ed4c4c5 | 23309 | |
c19d1205 ZW |
23310 | /* This list should, at a minimum, contain all the architecture names |
23311 | recognized by GCC. */ | |
f3bad469 | 23312 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 23313 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 23314 | { |
f3bad469 MGD |
23315 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
23316 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
23317 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
23318 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
23319 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
23320 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
23321 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
23322 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
23323 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
23324 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
23325 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
23326 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
23327 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
23328 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
23329 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
23330 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
23331 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
23332 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
23333 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
23334 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
23335 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
23336 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP), | |
23337 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
23338 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
23339 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
23340 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP), | |
23341 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
23342 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
23343 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
23344 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
23345 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 MGD |
23346 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
23347 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
23348 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
23349 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
23350 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
23351 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
23352 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
bca38921 | 23353 | ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), |
f3bad469 MGD |
23354 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), |
23355 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
23356 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
23357 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 23358 | }; |
f3bad469 | 23359 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 23360 | |
69133863 MGD |
23361 | /* ISA extensions in the co-processor and main instruction set space. */ |
23362 | struct arm_option_extension_value_table | |
c19d1205 ZW |
23363 | { |
23364 | char *name; | |
f3bad469 | 23365 | size_t name_len; |
e74cfd16 | 23366 | const arm_feature_set value; |
69133863 | 23367 | const arm_feature_set allowed_archs; |
c19d1205 | 23368 | }; |
7ed4c4c5 | 23369 | |
69133863 MGD |
23370 | /* The following table must be in alphabetical order with a NULL last entry. |
23371 | */ | |
f3bad469 | 23372 | #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA } |
69133863 | 23373 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 23374 | { |
bca38921 MGD |
23375 | ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, |
23376 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
23377 | ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, | |
23378 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
f3bad469 MGD |
23379 | ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
23380 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
23381 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), | |
23382 | ARM_EXT_OPT ("iwmmxt2", | |
23383 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY), | |
23384 | ARM_EXT_OPT ("maverick", | |
23385 | ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), | |
23386 | ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), | |
23387 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
bca38921 MGD |
23388 | ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, |
23389 | ARM_FEATURE (ARM_EXT_V8, 0)), | |
f3bad469 MGD |
23390 | ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), |
23391 | ARM_FEATURE (ARM_EXT_V6M, 0)), | |
23392 | ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), | |
23393 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)), | |
23394 | ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | |
23395 | | ARM_EXT_DIV, 0), | |
23396 | ARM_FEATURE (ARM_EXT_V7A, 0)), | |
23397 | ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY), | |
23398 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
69133863 | 23399 | }; |
f3bad469 | 23400 | #undef ARM_EXT_OPT |
69133863 MGD |
23401 | |
23402 | /* ISA floating-point and Advanced SIMD extensions. */ | |
23403 | struct arm_option_fpu_value_table | |
23404 | { | |
23405 | char *name; | |
23406 | const arm_feature_set value; | |
c19d1205 | 23407 | }; |
7ed4c4c5 | 23408 | |
c19d1205 ZW |
23409 | /* This list should, at a minimum, contain all the fpu names |
23410 | recognized by GCC. */ | |
69133863 | 23411 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
23412 | { |
23413 | {"softfpa", FPU_NONE}, | |
23414 | {"fpe", FPU_ARCH_FPE}, | |
23415 | {"fpe2", FPU_ARCH_FPE}, | |
23416 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
23417 | {"fpa", FPU_ARCH_FPA}, | |
23418 | {"fpa10", FPU_ARCH_FPA}, | |
23419 | {"fpa11", FPU_ARCH_FPA}, | |
23420 | {"arm7500fe", FPU_ARCH_FPA}, | |
23421 | {"softvfp", FPU_ARCH_VFP}, | |
23422 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
23423 | {"vfp", FPU_ARCH_VFP_V2}, | |
23424 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 23425 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
23426 | {"vfp10", FPU_ARCH_VFP_V2}, |
23427 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
23428 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
23429 | {"vfpv2", FPU_ARCH_VFP_V2}, |
23430 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 23431 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 23432 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
23433 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
23434 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
23435 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
23436 | {"arm1020t", FPU_ARCH_VFP_V1}, |
23437 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
23438 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
23439 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
23440 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 23441 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 23442 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
23443 | {"vfpv4", FPU_ARCH_VFP_V4}, |
23444 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 23445 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 23446 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
bca38921 MGD |
23447 | {"fp-armv8", FPU_ARCH_VFP_ARMV8}, |
23448 | {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, | |
23449 | {"crypto-neon-fp-armv8", | |
23450 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, | |
e74cfd16 PB |
23451 | {NULL, ARM_ARCH_NONE} |
23452 | }; | |
23453 | ||
23454 | struct arm_option_value_table | |
23455 | { | |
23456 | char *name; | |
23457 | long value; | |
c19d1205 | 23458 | }; |
7ed4c4c5 | 23459 | |
e74cfd16 | 23460 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
23461 | { |
23462 | {"hard", ARM_FLOAT_ABI_HARD}, | |
23463 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
23464 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 23465 | {NULL, 0} |
c19d1205 | 23466 | }; |
7ed4c4c5 | 23467 | |
c19d1205 | 23468 | #ifdef OBJ_ELF |
3a4a14e9 | 23469 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 23470 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
23471 | { |
23472 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
23473 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 23474 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 23475 | {NULL, 0} |
c19d1205 ZW |
23476 | }; |
23477 | #endif | |
7ed4c4c5 | 23478 | |
c19d1205 ZW |
23479 | struct arm_long_option_table |
23480 | { | |
23481 | char * option; /* Substring to match. */ | |
23482 | char * help; /* Help information. */ | |
23483 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
23484 | char * deprecated; /* If non-null, print this message. */ | |
23485 | }; | |
7ed4c4c5 | 23486 | |
c921be7d | 23487 | static bfd_boolean |
f3bad469 | 23488 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 23489 | { |
21d799b5 NC |
23490 | arm_feature_set *ext_set = (arm_feature_set *) |
23491 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 23492 | |
69133863 | 23493 | /* We insist on extensions being specified in alphabetical order, and with |
fa94de6b RM |
23494 | extensions being added before being removed. We achieve this by having |
23495 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
69133863 | 23496 | ADDING_VALUE variable to indicate whether we are adding an extension (1) |
fa94de6b | 23497 | or removing it (0) and only allowing it to change in the order |
69133863 MGD |
23498 | -1 -> 1 -> 0. */ |
23499 | const struct arm_option_extension_value_table * opt = NULL; | |
23500 | int adding_value = -1; | |
23501 | ||
e74cfd16 PB |
23502 | /* Copy the feature set, so that we can modify it. */ |
23503 | *ext_set = **opt_p; | |
23504 | *opt_p = ext_set; | |
23505 | ||
c19d1205 | 23506 | while (str != NULL && *str != 0) |
7ed4c4c5 | 23507 | { |
f3bad469 MGD |
23508 | char *ext; |
23509 | size_t len; | |
7ed4c4c5 | 23510 | |
c19d1205 ZW |
23511 | if (*str != '+') |
23512 | { | |
23513 | as_bad (_("invalid architectural extension")); | |
c921be7d | 23514 | return FALSE; |
c19d1205 | 23515 | } |
7ed4c4c5 | 23516 | |
c19d1205 ZW |
23517 | str++; |
23518 | ext = strchr (str, '+'); | |
7ed4c4c5 | 23519 | |
c19d1205 | 23520 | if (ext != NULL) |
f3bad469 | 23521 | len = ext - str; |
c19d1205 | 23522 | else |
f3bad469 | 23523 | len = strlen (str); |
7ed4c4c5 | 23524 | |
f3bad469 | 23525 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
23526 | { |
23527 | if (adding_value != 0) | |
23528 | { | |
23529 | adding_value = 0; | |
23530 | opt = arm_extensions; | |
23531 | } | |
23532 | ||
f3bad469 | 23533 | len -= 2; |
69133863 MGD |
23534 | str += 2; |
23535 | } | |
f3bad469 | 23536 | else if (len > 0) |
69133863 MGD |
23537 | { |
23538 | if (adding_value == -1) | |
23539 | { | |
23540 | adding_value = 1; | |
23541 | opt = arm_extensions; | |
23542 | } | |
23543 | else if (adding_value != 1) | |
23544 | { | |
23545 | as_bad (_("must specify extensions to add before specifying " | |
23546 | "those to remove")); | |
23547 | return FALSE; | |
23548 | } | |
23549 | } | |
23550 | ||
f3bad469 | 23551 | if (len == 0) |
c19d1205 ZW |
23552 | { |
23553 | as_bad (_("missing architectural extension")); | |
c921be7d | 23554 | return FALSE; |
c19d1205 | 23555 | } |
7ed4c4c5 | 23556 | |
69133863 MGD |
23557 | gas_assert (adding_value != -1); |
23558 | gas_assert (opt != NULL); | |
23559 | ||
23560 | /* Scan over the options table trying to find an exact match. */ | |
23561 | for (; opt->name != NULL; opt++) | |
f3bad469 | 23562 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23563 | { |
69133863 MGD |
23564 | /* Check we can apply the extension to this architecture. */ |
23565 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
23566 | { | |
23567 | as_bad (_("extension does not apply to the base architecture")); | |
23568 | return FALSE; | |
23569 | } | |
23570 | ||
23571 | /* Add or remove the extension. */ | |
23572 | if (adding_value) | |
23573 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); | |
23574 | else | |
23575 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); | |
23576 | ||
c19d1205 ZW |
23577 | break; |
23578 | } | |
7ed4c4c5 | 23579 | |
c19d1205 ZW |
23580 | if (opt->name == NULL) |
23581 | { | |
69133863 MGD |
23582 | /* Did we fail to find an extension because it wasn't specified in |
23583 | alphabetical order, or because it does not exist? */ | |
23584 | ||
23585 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 23586 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
23587 | break; |
23588 | ||
23589 | if (opt->name == NULL) | |
23590 | as_bad (_("unknown architectural extension `%s'"), str); | |
23591 | else | |
23592 | as_bad (_("architectural extensions must be specified in " | |
23593 | "alphabetical order")); | |
23594 | ||
c921be7d | 23595 | return FALSE; |
c19d1205 | 23596 | } |
69133863 MGD |
23597 | else |
23598 | { | |
23599 | /* We should skip the extension we've just matched the next time | |
23600 | round. */ | |
23601 | opt++; | |
23602 | } | |
7ed4c4c5 | 23603 | |
c19d1205 ZW |
23604 | str = ext; |
23605 | }; | |
7ed4c4c5 | 23606 | |
c921be7d | 23607 | return TRUE; |
c19d1205 | 23608 | } |
7ed4c4c5 | 23609 | |
c921be7d | 23610 | static bfd_boolean |
f3bad469 | 23611 | arm_parse_cpu (char *str) |
7ed4c4c5 | 23612 | { |
f3bad469 MGD |
23613 | const struct arm_cpu_option_table *opt; |
23614 | char *ext = strchr (str, '+'); | |
23615 | size_t len; | |
7ed4c4c5 | 23616 | |
c19d1205 | 23617 | if (ext != NULL) |
f3bad469 | 23618 | len = ext - str; |
7ed4c4c5 | 23619 | else |
f3bad469 | 23620 | len = strlen (str); |
7ed4c4c5 | 23621 | |
f3bad469 | 23622 | if (len == 0) |
7ed4c4c5 | 23623 | { |
c19d1205 | 23624 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 23625 | return FALSE; |
7ed4c4c5 NC |
23626 | } |
23627 | ||
c19d1205 | 23628 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 23629 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23630 | { |
e74cfd16 PB |
23631 | mcpu_cpu_opt = &opt->value; |
23632 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 23633 | if (opt->canonical_name) |
5f4273c7 | 23634 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23635 | else |
23636 | { | |
f3bad469 | 23637 | size_t i; |
c921be7d | 23638 | |
f3bad469 | 23639 | for (i = 0; i < len; i++) |
ee065d83 PB |
23640 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
23641 | selected_cpu_name[i] = 0; | |
23642 | } | |
7ed4c4c5 | 23643 | |
c19d1205 ZW |
23644 | if (ext != NULL) |
23645 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 23646 | |
c921be7d | 23647 | return TRUE; |
c19d1205 | 23648 | } |
7ed4c4c5 | 23649 | |
c19d1205 | 23650 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 23651 | return FALSE; |
7ed4c4c5 NC |
23652 | } |
23653 | ||
c921be7d | 23654 | static bfd_boolean |
f3bad469 | 23655 | arm_parse_arch (char *str) |
7ed4c4c5 | 23656 | { |
e74cfd16 | 23657 | const struct arm_arch_option_table *opt; |
c19d1205 | 23658 | char *ext = strchr (str, '+'); |
f3bad469 | 23659 | size_t len; |
7ed4c4c5 | 23660 | |
c19d1205 | 23661 | if (ext != NULL) |
f3bad469 | 23662 | len = ext - str; |
7ed4c4c5 | 23663 | else |
f3bad469 | 23664 | len = strlen (str); |
7ed4c4c5 | 23665 | |
f3bad469 | 23666 | if (len == 0) |
7ed4c4c5 | 23667 | { |
c19d1205 | 23668 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 23669 | return FALSE; |
7ed4c4c5 NC |
23670 | } |
23671 | ||
c19d1205 | 23672 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 23673 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23674 | { |
e74cfd16 PB |
23675 | march_cpu_opt = &opt->value; |
23676 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 23677 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 23678 | |
c19d1205 ZW |
23679 | if (ext != NULL) |
23680 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 23681 | |
c921be7d | 23682 | return TRUE; |
c19d1205 ZW |
23683 | } |
23684 | ||
23685 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 23686 | return FALSE; |
7ed4c4c5 | 23687 | } |
eb043451 | 23688 | |
c921be7d | 23689 | static bfd_boolean |
c19d1205 ZW |
23690 | arm_parse_fpu (char * str) |
23691 | { | |
69133863 | 23692 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 23693 | |
c19d1205 ZW |
23694 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23695 | if (streq (opt->name, str)) | |
23696 | { | |
e74cfd16 | 23697 | mfpu_opt = &opt->value; |
c921be7d | 23698 | return TRUE; |
c19d1205 | 23699 | } |
b99bd4ef | 23700 | |
c19d1205 | 23701 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 23702 | return FALSE; |
c19d1205 ZW |
23703 | } |
23704 | ||
c921be7d | 23705 | static bfd_boolean |
c19d1205 | 23706 | arm_parse_float_abi (char * str) |
b99bd4ef | 23707 | { |
e74cfd16 | 23708 | const struct arm_option_value_table * opt; |
b99bd4ef | 23709 | |
c19d1205 ZW |
23710 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
23711 | if (streq (opt->name, str)) | |
23712 | { | |
23713 | mfloat_abi_opt = opt->value; | |
c921be7d | 23714 | return TRUE; |
c19d1205 | 23715 | } |
cc8a6dd0 | 23716 | |
c19d1205 | 23717 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 23718 | return FALSE; |
c19d1205 | 23719 | } |
b99bd4ef | 23720 | |
c19d1205 | 23721 | #ifdef OBJ_ELF |
c921be7d | 23722 | static bfd_boolean |
c19d1205 ZW |
23723 | arm_parse_eabi (char * str) |
23724 | { | |
e74cfd16 | 23725 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 23726 | |
c19d1205 ZW |
23727 | for (opt = arm_eabis; opt->name != NULL; opt++) |
23728 | if (streq (opt->name, str)) | |
23729 | { | |
23730 | meabi_flags = opt->value; | |
c921be7d | 23731 | return TRUE; |
c19d1205 ZW |
23732 | } |
23733 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 23734 | return FALSE; |
c19d1205 ZW |
23735 | } |
23736 | #endif | |
cc8a6dd0 | 23737 | |
c921be7d | 23738 | static bfd_boolean |
e07e6e58 NC |
23739 | arm_parse_it_mode (char * str) |
23740 | { | |
c921be7d | 23741 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
23742 | |
23743 | if (streq ("arm", str)) | |
23744 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
23745 | else if (streq ("thumb", str)) | |
23746 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
23747 | else if (streq ("always", str)) | |
23748 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
23749 | else if (streq ("never", str)) | |
23750 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
23751 | else | |
23752 | { | |
23753 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
23754 | "arm, thumb, always, or never."), str); | |
c921be7d | 23755 | ret = FALSE; |
e07e6e58 NC |
23756 | } |
23757 | ||
23758 | return ret; | |
23759 | } | |
23760 | ||
c19d1205 ZW |
23761 | struct arm_long_option_table arm_long_opts[] = |
23762 | { | |
23763 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
23764 | arm_parse_cpu, NULL}, | |
23765 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
23766 | arm_parse_arch, NULL}, | |
23767 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
23768 | arm_parse_fpu, NULL}, | |
23769 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
23770 | arm_parse_float_abi, NULL}, | |
23771 | #ifdef OBJ_ELF | |
7fac0536 | 23772 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
23773 | arm_parse_eabi, NULL}, |
23774 | #endif | |
e07e6e58 NC |
23775 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
23776 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
23777 | {NULL, NULL, 0, NULL} |
23778 | }; | |
cc8a6dd0 | 23779 | |
c19d1205 ZW |
23780 | int |
23781 | md_parse_option (int c, char * arg) | |
23782 | { | |
23783 | struct arm_option_table *opt; | |
e74cfd16 | 23784 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 23785 | struct arm_long_option_table *lopt; |
b99bd4ef | 23786 | |
c19d1205 | 23787 | switch (c) |
b99bd4ef | 23788 | { |
c19d1205 ZW |
23789 | #ifdef OPTION_EB |
23790 | case OPTION_EB: | |
23791 | target_big_endian = 1; | |
23792 | break; | |
23793 | #endif | |
cc8a6dd0 | 23794 | |
c19d1205 ZW |
23795 | #ifdef OPTION_EL |
23796 | case OPTION_EL: | |
23797 | target_big_endian = 0; | |
23798 | break; | |
23799 | #endif | |
b99bd4ef | 23800 | |
845b51d6 PB |
23801 | case OPTION_FIX_V4BX: |
23802 | fix_v4bx = TRUE; | |
23803 | break; | |
23804 | ||
c19d1205 ZW |
23805 | case 'a': |
23806 | /* Listing option. Just ignore these, we don't support additional | |
23807 | ones. */ | |
23808 | return 0; | |
b99bd4ef | 23809 | |
c19d1205 ZW |
23810 | default: |
23811 | for (opt = arm_opts; opt->option != NULL; opt++) | |
23812 | { | |
23813 | if (c == opt->option[0] | |
23814 | && ((arg == NULL && opt->option[1] == 0) | |
23815 | || streq (arg, opt->option + 1))) | |
23816 | { | |
c19d1205 | 23817 | /* If the option is deprecated, tell the user. */ |
278df34e | 23818 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
23819 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23820 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 23821 | |
c19d1205 ZW |
23822 | if (opt->var != NULL) |
23823 | *opt->var = opt->value; | |
cc8a6dd0 | 23824 | |
c19d1205 ZW |
23825 | return 1; |
23826 | } | |
23827 | } | |
b99bd4ef | 23828 | |
e74cfd16 PB |
23829 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
23830 | { | |
23831 | if (c == fopt->option[0] | |
23832 | && ((arg == NULL && fopt->option[1] == 0) | |
23833 | || streq (arg, fopt->option + 1))) | |
23834 | { | |
e74cfd16 | 23835 | /* If the option is deprecated, tell the user. */ |
278df34e | 23836 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
23837 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23838 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
23839 | |
23840 | if (fopt->var != NULL) | |
23841 | *fopt->var = &fopt->value; | |
23842 | ||
23843 | return 1; | |
23844 | } | |
23845 | } | |
23846 | ||
c19d1205 ZW |
23847 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23848 | { | |
23849 | /* These options are expected to have an argument. */ | |
23850 | if (c == lopt->option[0] | |
23851 | && arg != NULL | |
23852 | && strncmp (arg, lopt->option + 1, | |
23853 | strlen (lopt->option + 1)) == 0) | |
23854 | { | |
c19d1205 | 23855 | /* If the option is deprecated, tell the user. */ |
278df34e | 23856 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
23857 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
23858 | _(lopt->deprecated)); | |
b99bd4ef | 23859 | |
c19d1205 ZW |
23860 | /* Call the sup-option parser. */ |
23861 | return lopt->func (arg + strlen (lopt->option) - 1); | |
23862 | } | |
23863 | } | |
a737bd4d | 23864 | |
c19d1205 ZW |
23865 | return 0; |
23866 | } | |
a394c00f | 23867 | |
c19d1205 ZW |
23868 | return 1; |
23869 | } | |
a394c00f | 23870 | |
c19d1205 ZW |
23871 | void |
23872 | md_show_usage (FILE * fp) | |
a394c00f | 23873 | { |
c19d1205 ZW |
23874 | struct arm_option_table *opt; |
23875 | struct arm_long_option_table *lopt; | |
a394c00f | 23876 | |
c19d1205 | 23877 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 23878 | |
c19d1205 ZW |
23879 | for (opt = arm_opts; opt->option != NULL; opt++) |
23880 | if (opt->help != NULL) | |
23881 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 23882 | |
c19d1205 ZW |
23883 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23884 | if (lopt->help != NULL) | |
23885 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 23886 | |
c19d1205 ZW |
23887 | #ifdef OPTION_EB |
23888 | fprintf (fp, _("\ | |
23889 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
23890 | #endif |
23891 | ||
c19d1205 ZW |
23892 | #ifdef OPTION_EL |
23893 | fprintf (fp, _("\ | |
23894 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 23895 | #endif |
845b51d6 PB |
23896 | |
23897 | fprintf (fp, _("\ | |
23898 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 23899 | } |
ee065d83 PB |
23900 | |
23901 | ||
23902 | #ifdef OBJ_ELF | |
62b3e311 PB |
23903 | typedef struct |
23904 | { | |
23905 | int val; | |
23906 | arm_feature_set flags; | |
23907 | } cpu_arch_ver_table; | |
23908 | ||
23909 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
23910 | least features first. */ | |
23911 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
23912 | { | |
23913 | {1, ARM_ARCH_V4}, | |
23914 | {2, ARM_ARCH_V4T}, | |
23915 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 23916 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
23917 | {4, ARM_ARCH_V5TE}, |
23918 | {5, ARM_ARCH_V5TEJ}, | |
23919 | {6, ARM_ARCH_V6}, | |
7e806470 | 23920 | {9, ARM_ARCH_V6K}, |
f4c65163 | 23921 | {7, ARM_ARCH_V6Z}, |
91e22acd | 23922 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 23923 | {12, ARM_ARCH_V6SM}, |
7e806470 | 23924 | {8, ARM_ARCH_V6T2}, |
bca38921 | 23925 | {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT}, |
62b3e311 PB |
23926 | {10, ARM_ARCH_V7R}, |
23927 | {10, ARM_ARCH_V7M}, | |
bca38921 | 23928 | {14, ARM_ARCH_V8A}, |
62b3e311 PB |
23929 | {0, ARM_ARCH_NONE} |
23930 | }; | |
23931 | ||
ee3c0378 AS |
23932 | /* Set an attribute if it has not already been set by the user. */ |
23933 | static void | |
23934 | aeabi_set_attribute_int (int tag, int value) | |
23935 | { | |
23936 | if (tag < 1 | |
23937 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23938 | || !attributes_set_explicitly[tag]) | |
23939 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
23940 | } | |
23941 | ||
23942 | static void | |
23943 | aeabi_set_attribute_string (int tag, const char *value) | |
23944 | { | |
23945 | if (tag < 1 | |
23946 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23947 | || !attributes_set_explicitly[tag]) | |
23948 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
23949 | } | |
23950 | ||
ee065d83 PB |
23951 | /* Set the public EABI object attributes. */ |
23952 | static void | |
23953 | aeabi_set_public_attributes (void) | |
23954 | { | |
23955 | int arch; | |
69239280 | 23956 | char profile; |
90ec0d68 | 23957 | int virt_sec = 0; |
bca38921 | 23958 | int fp16_optional = 0; |
e74cfd16 | 23959 | arm_feature_set flags; |
62b3e311 PB |
23960 | arm_feature_set tmp; |
23961 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
23962 | |
23963 | /* Choose the architecture based on the capabilities of the requested cpu | |
23964 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
23965 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
23966 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
23967 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
23968 | |
23969 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
23970 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
23971 | ||
23972 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
23973 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
23974 | ||
23975 | /* Allow the user to override the reported architecture. */ | |
7a1d4c38 PB |
23976 | if (object_arch) |
23977 | { | |
23978 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
23979 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
23980 | } | |
23981 | ||
251665fc MGD |
23982 | /* We need to make sure that the attributes do not identify us as v6S-M |
23983 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
23984 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
23985 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
23986 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); | |
23987 | ||
62b3e311 PB |
23988 | tmp = flags; |
23989 | arch = 0; | |
23990 | for (p = cpu_arch_ver; p->val; p++) | |
23991 | { | |
23992 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
23993 | { | |
23994 | arch = p->val; | |
23995 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
23996 | } | |
23997 | } | |
ee065d83 | 23998 | |
9e3c6df6 PB |
23999 | /* The table lookup above finds the last architecture to contribute |
24000 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
24001 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
24002 | We can not search for the last entry which is entirely used, | |
24003 | because if no CPU is specified we build up only those flags | |
24004 | actually used. Perhaps we should separate out the specified | |
24005 | and implicit cases. Avoid taking this path for -march=all by | |
24006 | checking for contradictory v7-A / v7-M features. */ | |
24007 | if (arch == 10 | |
24008 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
24009 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
24010 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
24011 | arch = 13; | |
24012 | ||
ee065d83 PB |
24013 | /* Tag_CPU_name. */ |
24014 | if (selected_cpu_name[0]) | |
24015 | { | |
91d6fa6a | 24016 | char *q; |
ee065d83 | 24017 | |
91d6fa6a NC |
24018 | q = selected_cpu_name; |
24019 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
24020 | { |
24021 | int i; | |
5f4273c7 | 24022 | |
91d6fa6a NC |
24023 | q += 4; |
24024 | for (i = 0; q[i]; i++) | |
24025 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 24026 | } |
91d6fa6a | 24027 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 24028 | } |
62f3b8c8 | 24029 | |
ee065d83 | 24030 | /* Tag_CPU_arch. */ |
ee3c0378 | 24031 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 24032 | |
62b3e311 PB |
24033 | /* Tag_CPU_arch_profile. */ |
24034 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
69239280 | 24035 | profile = 'A'; |
62b3e311 | 24036 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
69239280 | 24037 | profile = 'R'; |
7e806470 | 24038 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
69239280 MGD |
24039 | profile = 'M'; |
24040 | else | |
24041 | profile = '\0'; | |
24042 | ||
24043 | if (profile != '\0') | |
24044 | aeabi_set_attribute_int (Tag_CPU_arch_profile, profile); | |
62f3b8c8 | 24045 | |
ee065d83 | 24046 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
24047 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
24048 | || arch == 0) | |
24049 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 24050 | |
ee065d83 | 24051 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
24052 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
24053 | || arch == 0) | |
24054 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
24055 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 24056 | |
ee065d83 | 24057 | /* Tag_VFP_arch. */ |
bca38921 MGD |
24058 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8)) |
24059 | aeabi_set_attribute_int (Tag_VFP_arch, 7); | |
24060 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) | |
62f3b8c8 PB |
24061 | aeabi_set_attribute_int (Tag_VFP_arch, |
24062 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
24063 | ? 5 : 6); | |
24064 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
bca38921 MGD |
24065 | { |
24066 | fp16_optional = 1; | |
24067 | aeabi_set_attribute_int (Tag_VFP_arch, 3); | |
24068 | } | |
ada65aa3 | 24069 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
bca38921 MGD |
24070 | { |
24071 | aeabi_set_attribute_int (Tag_VFP_arch, 4); | |
24072 | fp16_optional = 1; | |
24073 | } | |
ee3c0378 AS |
24074 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) |
24075 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
24076 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
24077 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
24078 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 24079 | |
4547cb56 NC |
24080 | /* Tag_ABI_HardFP_use. */ |
24081 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
24082 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
24083 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
24084 | ||
ee065d83 | 24085 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
24086 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
24087 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
24088 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
24089 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 24090 | |
ee3c0378 | 24091 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
bca38921 MGD |
24092 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) |
24093 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); | |
24094 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) | |
24095 | { | |
24096 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) | |
24097 | { | |
24098 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); | |
24099 | } | |
24100 | else | |
24101 | { | |
24102 | aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); | |
24103 | fp16_optional = 1; | |
24104 | } | |
24105 | } | |
fa94de6b | 24106 | |
ee3c0378 | 24107 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
bca38921 | 24108 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) |
ee3c0378 | 24109 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 | 24110 | |
69239280 MGD |
24111 | /* Tag_DIV_use. |
24112 | ||
24113 | We set Tag_DIV_use to two when integer divide instructions have been used | |
24114 | in ARM state, or when Thumb integer divide instructions have been used, | |
24115 | but we have no architecture profile set, nor have we any ARM instructions. | |
24116 | ||
bca38921 MGD |
24117 | For ARMv8 we set the tag to 0 as integer divide is implied by the base |
24118 | architecture. | |
24119 | ||
69239280 | 24120 | For new architectures we will have to check these tests. */ |
bca38921 MGD |
24121 | gas_assert (arch <= TAG_CPU_ARCH_V8); |
24122 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) | |
24123 | aeabi_set_attribute_int (Tag_DIV_use, 0); | |
24124 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) | |
24125 | || (profile == '\0' | |
24126 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) | |
24127 | && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) | |
eea54501 | 24128 | aeabi_set_attribute_int (Tag_DIV_use, 2); |
60e5ef9f MGD |
24129 | |
24130 | /* Tag_MP_extension_use. */ | |
24131 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
24132 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
24133 | |
24134 | /* Tag Virtualization_use. */ | |
24135 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
24136 | virt_sec |= 1; |
24137 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
24138 | virt_sec |= 2; | |
24139 | if (virt_sec != 0) | |
24140 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
24141 | } |
24142 | ||
104d59d1 | 24143 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
24144 | void |
24145 | arm_md_end (void) | |
24146 | { | |
ee065d83 PB |
24147 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
24148 | return; | |
24149 | ||
24150 | aeabi_set_public_attributes (); | |
ee065d83 | 24151 | } |
8463be01 | 24152 | #endif /* OBJ_ELF */ |
ee065d83 PB |
24153 | |
24154 | ||
24155 | /* Parse a .cpu directive. */ | |
24156 | ||
24157 | static void | |
24158 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
24159 | { | |
e74cfd16 | 24160 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
24161 | char *name; |
24162 | char saved_char; | |
24163 | ||
24164 | name = input_line_pointer; | |
5f4273c7 | 24165 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24166 | input_line_pointer++; |
24167 | saved_char = *input_line_pointer; | |
24168 | *input_line_pointer = 0; | |
24169 | ||
24170 | /* Skip the first "all" entry. */ | |
24171 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
24172 | if (streq (opt->name, name)) | |
24173 | { | |
e74cfd16 PB |
24174 | mcpu_cpu_opt = &opt->value; |
24175 | selected_cpu = opt->value; | |
ee065d83 | 24176 | if (opt->canonical_name) |
5f4273c7 | 24177 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
24178 | else |
24179 | { | |
24180 | int i; | |
24181 | for (i = 0; opt->name[i]; i++) | |
24182 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 24183 | |
ee065d83 PB |
24184 | selected_cpu_name[i] = 0; |
24185 | } | |
e74cfd16 | 24186 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
24187 | *input_line_pointer = saved_char; |
24188 | demand_empty_rest_of_line (); | |
24189 | return; | |
24190 | } | |
24191 | as_bad (_("unknown cpu `%s'"), name); | |
24192 | *input_line_pointer = saved_char; | |
24193 | ignore_rest_of_line (); | |
24194 | } | |
24195 | ||
24196 | ||
24197 | /* Parse a .arch directive. */ | |
24198 | ||
24199 | static void | |
24200 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
24201 | { | |
e74cfd16 | 24202 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
24203 | char saved_char; |
24204 | char *name; | |
24205 | ||
24206 | name = input_line_pointer; | |
5f4273c7 | 24207 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24208 | input_line_pointer++; |
24209 | saved_char = *input_line_pointer; | |
24210 | *input_line_pointer = 0; | |
24211 | ||
24212 | /* Skip the first "all" entry. */ | |
24213 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
24214 | if (streq (opt->name, name)) | |
24215 | { | |
e74cfd16 PB |
24216 | mcpu_cpu_opt = &opt->value; |
24217 | selected_cpu = opt->value; | |
5f4273c7 | 24218 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 24219 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
24220 | *input_line_pointer = saved_char; |
24221 | demand_empty_rest_of_line (); | |
24222 | return; | |
24223 | } | |
24224 | ||
24225 | as_bad (_("unknown architecture `%s'\n"), name); | |
24226 | *input_line_pointer = saved_char; | |
24227 | ignore_rest_of_line (); | |
24228 | } | |
24229 | ||
24230 | ||
7a1d4c38 PB |
24231 | /* Parse a .object_arch directive. */ |
24232 | ||
24233 | static void | |
24234 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
24235 | { | |
24236 | const struct arm_arch_option_table *opt; | |
24237 | char saved_char; | |
24238 | char *name; | |
24239 | ||
24240 | name = input_line_pointer; | |
5f4273c7 | 24241 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
24242 | input_line_pointer++; |
24243 | saved_char = *input_line_pointer; | |
24244 | *input_line_pointer = 0; | |
24245 | ||
24246 | /* Skip the first "all" entry. */ | |
24247 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
24248 | if (streq (opt->name, name)) | |
24249 | { | |
24250 | object_arch = &opt->value; | |
24251 | *input_line_pointer = saved_char; | |
24252 | demand_empty_rest_of_line (); | |
24253 | return; | |
24254 | } | |
24255 | ||
24256 | as_bad (_("unknown architecture `%s'\n"), name); | |
24257 | *input_line_pointer = saved_char; | |
24258 | ignore_rest_of_line (); | |
24259 | } | |
24260 | ||
69133863 MGD |
24261 | /* Parse a .arch_extension directive. */ |
24262 | ||
24263 | static void | |
24264 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
24265 | { | |
24266 | const struct arm_option_extension_value_table *opt; | |
24267 | char saved_char; | |
24268 | char *name; | |
24269 | int adding_value = 1; | |
24270 | ||
24271 | name = input_line_pointer; | |
24272 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
24273 | input_line_pointer++; | |
24274 | saved_char = *input_line_pointer; | |
24275 | *input_line_pointer = 0; | |
24276 | ||
24277 | if (strlen (name) >= 2 | |
24278 | && strncmp (name, "no", 2) == 0) | |
24279 | { | |
24280 | adding_value = 0; | |
24281 | name += 2; | |
24282 | } | |
24283 | ||
24284 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
24285 | if (streq (opt->name, name)) | |
24286 | { | |
24287 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
24288 | { | |
24289 | as_bad (_("architectural extension `%s' is not allowed for the " | |
24290 | "current base architecture"), name); | |
24291 | break; | |
24292 | } | |
24293 | ||
24294 | if (adding_value) | |
24295 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); | |
24296 | else | |
24297 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); | |
24298 | ||
24299 | mcpu_cpu_opt = &selected_cpu; | |
24300 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
24301 | *input_line_pointer = saved_char; | |
24302 | demand_empty_rest_of_line (); | |
24303 | return; | |
24304 | } | |
24305 | ||
24306 | if (opt->name == NULL) | |
24307 | as_bad (_("unknown architecture `%s'\n"), name); | |
24308 | ||
24309 | *input_line_pointer = saved_char; | |
24310 | ignore_rest_of_line (); | |
24311 | } | |
24312 | ||
ee065d83 PB |
24313 | /* Parse a .fpu directive. */ |
24314 | ||
24315 | static void | |
24316 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
24317 | { | |
69133863 | 24318 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
24319 | char saved_char; |
24320 | char *name; | |
24321 | ||
24322 | name = input_line_pointer; | |
5f4273c7 | 24323 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24324 | input_line_pointer++; |
24325 | saved_char = *input_line_pointer; | |
24326 | *input_line_pointer = 0; | |
5f4273c7 | 24327 | |
ee065d83 PB |
24328 | for (opt = arm_fpus; opt->name != NULL; opt++) |
24329 | if (streq (opt->name, name)) | |
24330 | { | |
e74cfd16 PB |
24331 | mfpu_opt = &opt->value; |
24332 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
24333 | *input_line_pointer = saved_char; |
24334 | demand_empty_rest_of_line (); | |
24335 | return; | |
24336 | } | |
24337 | ||
24338 | as_bad (_("unknown floating point format `%s'\n"), name); | |
24339 | *input_line_pointer = saved_char; | |
24340 | ignore_rest_of_line (); | |
24341 | } | |
ee065d83 | 24342 | |
794ba86a | 24343 | /* Copy symbol information. */ |
f31fef98 | 24344 | |
794ba86a DJ |
24345 | void |
24346 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
24347 | { | |
24348 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
24349 | } | |
e04befd0 | 24350 | |
f31fef98 | 24351 | #ifdef OBJ_ELF |
e04befd0 AS |
24352 | /* Given a symbolic attribute NAME, return the proper integer value. |
24353 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 24354 | |
e04befd0 AS |
24355 | int |
24356 | arm_convert_symbolic_attribute (const char *name) | |
24357 | { | |
f31fef98 NC |
24358 | static const struct |
24359 | { | |
24360 | const char * name; | |
24361 | const int tag; | |
24362 | } | |
24363 | attribute_table[] = | |
24364 | { | |
24365 | /* When you modify this table you should | |
24366 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 24367 | #define T(tag) {#tag, tag} |
f31fef98 NC |
24368 | T (Tag_CPU_raw_name), |
24369 | T (Tag_CPU_name), | |
24370 | T (Tag_CPU_arch), | |
24371 | T (Tag_CPU_arch_profile), | |
24372 | T (Tag_ARM_ISA_use), | |
24373 | T (Tag_THUMB_ISA_use), | |
75375b3e | 24374 | T (Tag_FP_arch), |
f31fef98 NC |
24375 | T (Tag_VFP_arch), |
24376 | T (Tag_WMMX_arch), | |
24377 | T (Tag_Advanced_SIMD_arch), | |
24378 | T (Tag_PCS_config), | |
24379 | T (Tag_ABI_PCS_R9_use), | |
24380 | T (Tag_ABI_PCS_RW_data), | |
24381 | T (Tag_ABI_PCS_RO_data), | |
24382 | T (Tag_ABI_PCS_GOT_use), | |
24383 | T (Tag_ABI_PCS_wchar_t), | |
24384 | T (Tag_ABI_FP_rounding), | |
24385 | T (Tag_ABI_FP_denormal), | |
24386 | T (Tag_ABI_FP_exceptions), | |
24387 | T (Tag_ABI_FP_user_exceptions), | |
24388 | T (Tag_ABI_FP_number_model), | |
75375b3e | 24389 | T (Tag_ABI_align_needed), |
f31fef98 | 24390 | T (Tag_ABI_align8_needed), |
75375b3e | 24391 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
24392 | T (Tag_ABI_align8_preserved), |
24393 | T (Tag_ABI_enum_size), | |
24394 | T (Tag_ABI_HardFP_use), | |
24395 | T (Tag_ABI_VFP_args), | |
24396 | T (Tag_ABI_WMMX_args), | |
24397 | T (Tag_ABI_optimization_goals), | |
24398 | T (Tag_ABI_FP_optimization_goals), | |
24399 | T (Tag_compatibility), | |
24400 | T (Tag_CPU_unaligned_access), | |
75375b3e | 24401 | T (Tag_FP_HP_extension), |
f31fef98 NC |
24402 | T (Tag_VFP_HP_extension), |
24403 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
24404 | T (Tag_MPextension_use), |
24405 | T (Tag_DIV_use), | |
f31fef98 NC |
24406 | T (Tag_nodefaults), |
24407 | T (Tag_also_compatible_with), | |
24408 | T (Tag_conformance), | |
24409 | T (Tag_T2EE_use), | |
24410 | T (Tag_Virtualization_use), | |
cd21e546 | 24411 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 24412 | #undef T |
f31fef98 | 24413 | }; |
e04befd0 AS |
24414 | unsigned int i; |
24415 | ||
24416 | if (name == NULL) | |
24417 | return -1; | |
24418 | ||
f31fef98 | 24419 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 24420 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
24421 | return attribute_table[i].tag; |
24422 | ||
24423 | return -1; | |
24424 | } | |
267bf995 RR |
24425 | |
24426 | ||
24427 | /* Apply sym value for relocations only in the case that | |
24428 | they are for local symbols and you have the respective | |
24429 | architectural feature for blx and simple switches. */ | |
24430 | int | |
24431 | arm_apply_sym_value (struct fix * fixP) | |
24432 | { | |
24433 | if (fixP->fx_addsy | |
24434 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 24435 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
24436 | { |
24437 | switch (fixP->fx_r_type) | |
24438 | { | |
24439 | case BFD_RELOC_ARM_PCREL_BLX: | |
24440 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
24441 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
24442 | return 1; | |
24443 | break; | |
24444 | ||
24445 | case BFD_RELOC_ARM_PCREL_CALL: | |
24446 | case BFD_RELOC_THUMB_PCREL_BLX: | |
24447 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
24448 | return 1; | |
24449 | break; | |
24450 | ||
24451 | default: | |
24452 | break; | |
24453 | } | |
24454 | ||
24455 | } | |
24456 | return 0; | |
24457 | } | |
f31fef98 | 24458 | #endif /* OBJ_ELF */ |