Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b AM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
3 | 2004, 2005 | |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2, or (at your option) | |
16 | any later version. | |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
b99bd4ef | 28 | #include <string.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
b99bd4ef | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
b99bd4ef NC |
32 | |
33 | /* Need TARGET_CPU. */ | |
34 | #include "config.h" | |
35 | #include "subsegs.h" | |
36 | #include "obstack.h" | |
37 | #include "symbols.h" | |
38 | #include "listing.h" | |
39 | ||
f263249b RE |
40 | #include "opcode/arm.h" |
41 | ||
b99bd4ef NC |
42 | #ifdef OBJ_ELF |
43 | #include "elf/arm.h" | |
44 | #include "dwarf2dbg.h" | |
a394c00f | 45 | #include "dw2gencfi.h" |
b99bd4ef NC |
46 | #endif |
47 | ||
7ed4c4c5 | 48 | /* XXX Set this to 1 after the next binutils release. */ |
03b1477f RE |
49 | #define WARN_DEPRECATED 0 |
50 | ||
7ed4c4c5 NC |
51 | #ifdef OBJ_ELF |
52 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
53 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
54 | ||
55 | /* This structure holds the unwinding state. */ | |
56 | ||
57 | static struct | |
58 | { | |
c19d1205 ZW |
59 | symbolS * proc_start; |
60 | symbolS * table_entry; | |
61 | symbolS * personality_routine; | |
62 | int personality_index; | |
7ed4c4c5 | 63 | /* The segment containing the function. */ |
c19d1205 ZW |
64 | segT saved_seg; |
65 | subsegT saved_subseg; | |
7ed4c4c5 NC |
66 | /* Opcodes generated from this function. */ |
67 | unsigned char * opcodes; | |
c19d1205 ZW |
68 | int opcode_count; |
69 | int opcode_alloc; | |
7ed4c4c5 | 70 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 71 | offsetT frame_size; |
7ed4c4c5 NC |
72 | /* We don't add stack adjustment opcodes immediately so that we can merge |
73 | multiple adjustments. We can also omit the final adjustment | |
74 | when using a frame pointer. */ | |
c19d1205 | 75 | offsetT pending_offset; |
7ed4c4c5 | 76 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
77 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
78 | offsetT fp_offset; | |
79 | int fp_reg; | |
7ed4c4c5 | 80 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 81 | unsigned fp_used:1; |
7ed4c4c5 | 82 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 83 | unsigned sp_restored:1; |
7ed4c4c5 NC |
84 | } unwind; |
85 | ||
84798bd6 JB |
86 | /* Bit N indicates that an R_ARM_NONE relocation has been output for |
87 | __aeabi_unwind_cpp_prN already if set. This enables dependencies to be | |
88 | emitted only once per section, to save unnecessary bloat. */ | |
89 | static unsigned int marked_pr_dependency = 0; | |
90 | ||
7ed4c4c5 NC |
91 | #endif /* OBJ_ELF */ |
92 | ||
33a392fb PB |
93 | enum arm_float_abi |
94 | { | |
95 | ARM_FLOAT_ABI_HARD, | |
96 | ARM_FLOAT_ABI_SOFTFP, | |
97 | ARM_FLOAT_ABI_SOFT | |
98 | }; | |
99 | ||
c19d1205 | 100 | /* Types of processor to assemble for. */ |
b89dddec RE |
101 | #define ARM_1 ARM_ARCH_V1 |
102 | #define ARM_2 ARM_ARCH_V2 | |
103 | #define ARM_3 ARM_ARCH_V2S | |
104 | #define ARM_250 ARM_ARCH_V2S | |
105 | #define ARM_6 ARM_ARCH_V3 | |
106 | #define ARM_7 ARM_ARCH_V3 | |
107 | #define ARM_8 ARM_ARCH_V4 | |
108 | #define ARM_9 ARM_ARCH_V4T | |
109 | #define ARM_STRONG ARM_ARCH_V4 | |
c19d1205 | 110 | #define ARM_CPU_MASK 0x0000000f /* XXX? */ |
b99bd4ef NC |
111 | |
112 | #ifndef CPU_DEFAULT | |
113 | #if defined __XSCALE__ | |
b89dddec | 114 | #define CPU_DEFAULT (ARM_ARCH_XSCALE) |
b99bd4ef NC |
115 | #else |
116 | #if defined __thumb__ | |
c19d1205 | 117 | #define CPU_DEFAULT (ARM_ARCH_V5T) |
b99bd4ef | 118 | #else |
c19d1205 | 119 | #define CPU_DEFAULT ARM_ANY |
b99bd4ef NC |
120 | #endif |
121 | #endif | |
122 | #endif | |
123 | ||
124 | #ifndef FPU_DEFAULT | |
c820d418 MM |
125 | # ifdef TE_LINUX |
126 | # define FPU_DEFAULT FPU_ARCH_FPA | |
127 | # elif defined (TE_NetBSD) | |
128 | # ifdef OBJ_ELF | |
129 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
130 | # else | |
131 | /* Legacy a.out format. */ | |
132 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
133 | # endif | |
4e7fd91e PB |
134 | # elif defined (TE_VXWORKS) |
135 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
136 | # else |
137 | /* For backwards compatibility, default to FPA. */ | |
138 | # define FPU_DEFAULT FPU_ARCH_FPA | |
139 | # endif | |
140 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 141 | |
c19d1205 | 142 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 143 | |
03b1477f | 144 | static unsigned long cpu_variant; |
b99bd4ef | 145 | |
b99bd4ef | 146 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
147 | static int uses_apcs_26 = FALSE; |
148 | static int atpcs = FALSE; | |
b34976b6 AM |
149 | static int support_interwork = FALSE; |
150 | static int uses_apcs_float = FALSE; | |
c19d1205 | 151 | static int pic_code = FALSE; |
03b1477f RE |
152 | |
153 | /* Variables that we set while parsing command-line options. Once all | |
154 | options have been read we re-process these values to set the real | |
155 | assembly flags. */ | |
156 | static int legacy_cpu = -1; | |
157 | static int legacy_fpu = -1; | |
158 | ||
159 | static int mcpu_cpu_opt = -1; | |
160 | static int mcpu_fpu_opt = -1; | |
161 | static int march_cpu_opt = -1; | |
162 | static int march_fpu_opt = -1; | |
163 | static int mfpu_opt = -1; | |
33a392fb | 164 | static int mfloat_abi_opt = -1; |
7cc69913 | 165 | #ifdef OBJ_ELF |
deeaaff8 DJ |
166 | # ifdef EABI_DEFAULT |
167 | static int meabi_flags = EABI_DEFAULT; | |
168 | # else | |
d507cf36 | 169 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 170 | # endif |
7cc69913 | 171 | #endif |
b99bd4ef | 172 | |
b99bd4ef | 173 | #ifdef OBJ_ELF |
c19d1205 | 174 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
175 | symbolS * GOT_symbol; |
176 | #endif | |
177 | ||
b99bd4ef NC |
178 | /* 0: assemble for ARM, |
179 | 1: assemble for Thumb, | |
180 | 2: assemble for Thumb even though target CPU does not support thumb | |
181 | instructions. */ | |
182 | static int thumb_mode = 0; | |
183 | ||
c19d1205 ZW |
184 | /* If unified_syntax is true, we are processing the new unified |
185 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
186 | ||
187 | - Immediate operands do not require a # prefix. | |
188 | - Conditional affixes always appear at the end of the | |
189 | instruction. (For backward compatibility, those instructions | |
190 | that formerly had them in the middle, continue to accept them | |
191 | there.) | |
192 | - The IT instruction may appear, and if it does is validated | |
193 | against subsequent conditional affixes. It does not generate | |
194 | machine code. | |
195 | ||
196 | Important differences from the old Thumb mode: | |
197 | ||
198 | - Immediate operands do not require a # prefix. | |
199 | - Most of the V6T2 instructions are only available in unified mode. | |
200 | - The .N and .W suffixes are recognized and honored (it is an error | |
201 | if they cannot be honored). | |
202 | - All instructions set the flags if and only if they have an 's' affix. | |
203 | - Conditional affixes may be used. They are validated against | |
204 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
205 | conditional affix except in the scope of an IT instruction. */ | |
206 | ||
207 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef NC |
208 | |
209 | struct arm_it | |
210 | { | |
c19d1205 | 211 | const char * error; |
b99bd4ef | 212 | unsigned long instruction; |
c19d1205 ZW |
213 | int size; |
214 | int size_req; | |
215 | int cond; | |
b99bd4ef NC |
216 | struct |
217 | { | |
218 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
219 | expressionS exp; |
220 | int pc_rel; | |
b99bd4ef | 221 | } reloc; |
b99bd4ef | 222 | |
c19d1205 ZW |
223 | struct |
224 | { | |
225 | unsigned reg; | |
ca3f61f7 NC |
226 | signed int imm; |
227 | unsigned present : 1; /* Operand present. */ | |
228 | unsigned isreg : 1; /* Operand was a register. */ | |
229 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
230 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ | |
231 | unsigned writeback : 1; /* Operand has trailing ! */ | |
232 | unsigned preind : 1; /* Preindexed address. */ | |
233 | unsigned postind : 1; /* Postindexed address. */ | |
234 | unsigned negative : 1; /* Index register was negated. */ | |
235 | unsigned shifted : 1; /* Shift applied to operation. */ | |
236 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 237 | } operands[6]; |
b99bd4ef NC |
238 | }; |
239 | ||
c19d1205 | 240 | static struct arm_it inst; |
b99bd4ef NC |
241 | |
242 | #define NUM_FLOAT_VALS 8 | |
243 | ||
05d2d07e | 244 | const char * fp_const[] = |
b99bd4ef NC |
245 | { |
246 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
247 | }; | |
248 | ||
c19d1205 | 249 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
250 | #define MAX_LITTLENUMS 6 |
251 | ||
252 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
253 | ||
254 | #define FAIL (-1) | |
255 | #define SUCCESS (0) | |
256 | ||
257 | #define SUFF_S 1 | |
258 | #define SUFF_D 2 | |
259 | #define SUFF_E 3 | |
260 | #define SUFF_P 4 | |
261 | ||
c19d1205 ZW |
262 | #define CP_T_X 0x00008000 |
263 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 264 | |
c19d1205 ZW |
265 | #define CONDS_BIT 0x00100000 |
266 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
267 | |
268 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
269 | ||
270 | struct asm_cond | |
271 | { | |
c19d1205 | 272 | const char * template; |
b99bd4ef NC |
273 | unsigned long value; |
274 | }; | |
275 | ||
c19d1205 | 276 | #define COND_ALWAYS 0xE |
b99bd4ef | 277 | |
b99bd4ef NC |
278 | struct asm_psr |
279 | { | |
b34976b6 | 280 | const char *template; |
b99bd4ef NC |
281 | unsigned long field; |
282 | }; | |
283 | ||
2d2255b5 | 284 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
285 | #define SPSR_BIT (1 << 22) |
286 | ||
c19d1205 ZW |
287 | /* The individual PSR flag bits. */ |
288 | #define PSR_c (1 << 16) | |
289 | #define PSR_x (1 << 17) | |
290 | #define PSR_s (1 << 18) | |
291 | #define PSR_f (1 << 19) | |
b99bd4ef | 292 | |
c19d1205 | 293 | struct reloc_entry |
bfae80f2 | 294 | { |
c19d1205 ZW |
295 | char *name; |
296 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
297 | }; |
298 | ||
299 | enum vfp_sp_reg_pos | |
300 | { | |
301 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn | |
302 | }; | |
303 | ||
304 | enum vfp_ldstm_type | |
305 | { | |
306 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
307 | }; | |
308 | ||
c19d1205 ZW |
309 | /* ARM register categories. This includes coprocessor numbers and various |
310 | architecture extensions' registers. */ | |
311 | enum arm_reg_type | |
bfae80f2 | 312 | { |
c19d1205 ZW |
313 | REG_TYPE_RN, |
314 | REG_TYPE_CP, | |
315 | REG_TYPE_CN, | |
316 | REG_TYPE_FN, | |
317 | REG_TYPE_VFS, | |
318 | REG_TYPE_VFD, | |
319 | REG_TYPE_VFC, | |
320 | REG_TYPE_MVF, | |
321 | REG_TYPE_MVD, | |
322 | REG_TYPE_MVFX, | |
323 | REG_TYPE_MVDX, | |
324 | REG_TYPE_MVAX, | |
325 | REG_TYPE_DSPSC, | |
326 | REG_TYPE_MMXWR, | |
327 | REG_TYPE_MMXWC, | |
328 | REG_TYPE_MMXWCG, | |
329 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
330 | }; |
331 | ||
6c43fab6 RE |
332 | /* Structure for a hash table entry for a register. */ |
333 | struct reg_entry | |
334 | { | |
c19d1205 ZW |
335 | const char *name; |
336 | unsigned char number; | |
337 | unsigned char type; | |
338 | unsigned char builtin; | |
6c43fab6 RE |
339 | }; |
340 | ||
c19d1205 ZW |
341 | /* Diagnostics used when we don't get a register of the expected type. */ |
342 | const char *const reg_expected_msgs[] = | |
343 | { | |
344 | N_("ARM register expected"), | |
345 | N_("bad or missing co-processor number"), | |
346 | N_("co-processor register expected"), | |
347 | N_("FPA register expected"), | |
348 | N_("VFP single precision register expected"), | |
349 | N_("VFP double precision register expected"), | |
350 | N_("VFP system register expected"), | |
351 | N_("Maverick MVF register expected"), | |
352 | N_("Maverick MVD register expected"), | |
353 | N_("Maverick MVFX register expected"), | |
354 | N_("Maverick MVDX register expected"), | |
355 | N_("Maverick MVAX register expected"), | |
356 | N_("Maverick DSPSC register expected"), | |
357 | N_("iWMMXt data register expected"), | |
358 | N_("iWMMXt control register expected"), | |
359 | N_("iWMMXt scalar register expected"), | |
360 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
361 | }; |
362 | ||
c19d1205 ZW |
363 | /* Some well known registers that we refer to directly elsewhere. */ |
364 | #define REG_SP 13 | |
365 | #define REG_LR 14 | |
366 | #define REG_PC 15 | |
404ff6b5 | 367 | |
b99bd4ef NC |
368 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
369 | take 2: */ | |
c19d1205 | 370 | #define INSN_SIZE 4 |
b99bd4ef NC |
371 | |
372 | struct asm_opcode | |
373 | { | |
374 | /* Basic string to match. */ | |
c19d1205 ZW |
375 | const char *template; |
376 | ||
377 | /* Parameters to instruction. */ | |
378 | unsigned char operands[8]; | |
379 | ||
380 | /* Conditional tag - see opcode_lookup. */ | |
381 | unsigned int tag : 4; | |
b99bd4ef NC |
382 | |
383 | /* Basic instruction code. */ | |
c19d1205 | 384 | unsigned int avalue : 28; |
b99bd4ef | 385 | |
c19d1205 ZW |
386 | /* Thumb-format instruction code. */ |
387 | unsigned int tvalue; | |
b99bd4ef | 388 | |
90e4755a | 389 | /* Which architecture variant provides this instruction. */ |
c19d1205 ZW |
390 | unsigned long avariant; |
391 | unsigned long tvariant; | |
392 | ||
393 | /* Function to call to encode instruction in ARM format. */ | |
394 | void (* aencode) (void); | |
b99bd4ef | 395 | |
c19d1205 ZW |
396 | /* Function to call to encode instruction in Thumb format. */ |
397 | void (* tencode) (void); | |
b99bd4ef NC |
398 | }; |
399 | ||
a737bd4d NC |
400 | /* Defines for various bits that we will want to toggle. */ |
401 | #define INST_IMMEDIATE 0x02000000 | |
402 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 403 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
404 | #define SHIFT_BY_REG 0x00000010 |
405 | #define PRE_INDEX 0x01000000 | |
406 | #define INDEX_UP 0x00800000 | |
407 | #define WRITE_BACK 0x00200000 | |
408 | #define LDM_TYPE_2_OR_3 0x00400000 | |
90e4755a | 409 | |
a737bd4d NC |
410 | #define LITERAL_MASK 0xf000f000 |
411 | #define OPCODE_MASK 0xfe1fffff | |
412 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 413 | |
a737bd4d | 414 | #define DATA_OP_SHIFT 21 |
90e4755a | 415 | |
a737bd4d NC |
416 | /* Codes to distinguish the arithmetic instructions. */ |
417 | #define OPCODE_AND 0 | |
418 | #define OPCODE_EOR 1 | |
419 | #define OPCODE_SUB 2 | |
420 | #define OPCODE_RSB 3 | |
421 | #define OPCODE_ADD 4 | |
422 | #define OPCODE_ADC 5 | |
423 | #define OPCODE_SBC 6 | |
424 | #define OPCODE_RSC 7 | |
425 | #define OPCODE_TST 8 | |
426 | #define OPCODE_TEQ 9 | |
427 | #define OPCODE_CMP 10 | |
428 | #define OPCODE_CMN 11 | |
429 | #define OPCODE_ORR 12 | |
430 | #define OPCODE_MOV 13 | |
431 | #define OPCODE_BIC 14 | |
432 | #define OPCODE_MVN 15 | |
90e4755a | 433 | |
a737bd4d NC |
434 | #define T_OPCODE_MUL 0x4340 |
435 | #define T_OPCODE_TST 0x4200 | |
436 | #define T_OPCODE_CMN 0x42c0 | |
437 | #define T_OPCODE_NEG 0x4240 | |
438 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 439 | |
a737bd4d NC |
440 | #define T_OPCODE_ADD_R3 0x1800 |
441 | #define T_OPCODE_SUB_R3 0x1a00 | |
442 | #define T_OPCODE_ADD_HI 0x4400 | |
443 | #define T_OPCODE_ADD_ST 0xb000 | |
444 | #define T_OPCODE_SUB_ST 0xb080 | |
445 | #define T_OPCODE_ADD_SP 0xa800 | |
446 | #define T_OPCODE_ADD_PC 0xa000 | |
447 | #define T_OPCODE_ADD_I8 0x3000 | |
448 | #define T_OPCODE_SUB_I8 0x3800 | |
449 | #define T_OPCODE_ADD_I3 0x1c00 | |
450 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 451 | |
a737bd4d NC |
452 | #define T_OPCODE_ASR_R 0x4100 |
453 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
454 | #define T_OPCODE_LSR_R 0x40c0 |
455 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
456 | #define T_OPCODE_ASR_I 0x1000 |
457 | #define T_OPCODE_LSL_I 0x0000 | |
458 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 459 | |
a737bd4d NC |
460 | #define T_OPCODE_MOV_I8 0x2000 |
461 | #define T_OPCODE_CMP_I8 0x2800 | |
462 | #define T_OPCODE_CMP_LR 0x4280 | |
463 | #define T_OPCODE_MOV_HR 0x4600 | |
464 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 465 | |
a737bd4d NC |
466 | #define T_OPCODE_LDR_PC 0x4800 |
467 | #define T_OPCODE_LDR_SP 0x9800 | |
468 | #define T_OPCODE_STR_SP 0x9000 | |
469 | #define T_OPCODE_LDR_IW 0x6800 | |
470 | #define T_OPCODE_STR_IW 0x6000 | |
471 | #define T_OPCODE_LDR_IH 0x8800 | |
472 | #define T_OPCODE_STR_IH 0x8000 | |
473 | #define T_OPCODE_LDR_IB 0x7800 | |
474 | #define T_OPCODE_STR_IB 0x7000 | |
475 | #define T_OPCODE_LDR_RW 0x5800 | |
476 | #define T_OPCODE_STR_RW 0x5000 | |
477 | #define T_OPCODE_LDR_RH 0x5a00 | |
478 | #define T_OPCODE_STR_RH 0x5200 | |
479 | #define T_OPCODE_LDR_RB 0x5c00 | |
480 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 481 | |
a737bd4d NC |
482 | #define T_OPCODE_PUSH 0xb400 |
483 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 484 | |
2fc8bdac | 485 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 486 | |
a737bd4d | 487 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 488 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 ZW |
489 | #define THUMB_LOAD_BIT 0x0800 |
490 | ||
491 | #define BAD_ARGS _("bad arguments to instruction") | |
492 | #define BAD_PC _("r15 not allowed here") | |
493 | #define BAD_COND _("instruction cannot be conditional") | |
494 | #define BAD_OVERLAP _("registers may not be the same") | |
495 | #define BAD_HIREG _("lo register required") | |
496 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
497 | ||
498 | static struct hash_control *arm_ops_hsh; | |
499 | static struct hash_control *arm_cond_hsh; | |
500 | static struct hash_control *arm_shift_hsh; | |
501 | static struct hash_control *arm_psr_hsh; | |
502 | static struct hash_control *arm_reg_hsh; | |
503 | static struct hash_control *arm_reloc_hsh; | |
b99bd4ef | 504 | |
b99bd4ef NC |
505 | /* Stuff needed to resolve the label ambiguity |
506 | As: | |
507 | ... | |
508 | label: <insn> | |
509 | may differ from: | |
510 | ... | |
511 | label: | |
c19d1205 | 512 | <insn> |
b99bd4ef NC |
513 | */ |
514 | ||
515 | symbolS * last_label_seen; | |
b34976b6 | 516 | static int label_is_thumb_function_name = FALSE; |
a737bd4d | 517 | \f |
3d0c9500 NC |
518 | /* Literal pool structure. Held on a per-section |
519 | and per-sub-section basis. */ | |
a737bd4d | 520 | |
c19d1205 | 521 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 522 | typedef struct literal_pool |
b99bd4ef | 523 | { |
c19d1205 ZW |
524 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
525 | unsigned int next_free_entry; | |
526 | unsigned int id; | |
527 | symbolS * symbol; | |
528 | segT section; | |
529 | subsegT sub_section; | |
61b5f74b | 530 | struct literal_pool * next; |
3d0c9500 | 531 | } literal_pool; |
b99bd4ef | 532 | |
3d0c9500 NC |
533 | /* Pointer to a linked list of literal pools. */ |
534 | literal_pool * list_of_pools = NULL; | |
e27ec89e PB |
535 | |
536 | /* State variables for IT block handling. */ | |
537 | static bfd_boolean current_it_mask = 0; | |
538 | static int current_cc; | |
539 | ||
c19d1205 ZW |
540 | \f |
541 | /* Pure syntax. */ | |
b99bd4ef | 542 | |
c19d1205 ZW |
543 | /* This array holds the chars that always start a comment. If the |
544 | pre-processor is disabled, these aren't very useful. */ | |
545 | const char comment_chars[] = "@"; | |
3d0c9500 | 546 | |
c19d1205 ZW |
547 | /* This array holds the chars that only start a comment at the beginning of |
548 | a line. If the line seems to have the form '# 123 filename' | |
549 | .line and .file directives will appear in the pre-processed output. */ | |
550 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
551 | first line of the input file. This is because the compiler outputs | |
552 | #NO_APP at the beginning of its output. */ | |
553 | /* Also note that comments like this one will always work. */ | |
554 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 555 | |
c19d1205 | 556 | const char line_separator_chars[] = ";"; |
b99bd4ef | 557 | |
c19d1205 ZW |
558 | /* Chars that can be used to separate mant |
559 | from exp in floating point numbers. */ | |
560 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 561 | |
c19d1205 ZW |
562 | /* Chars that mean this number is a floating point constant. */ |
563 | /* As in 0f12.456 */ | |
564 | /* or 0d1.2345e12 */ | |
b99bd4ef | 565 | |
c19d1205 | 566 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 567 | |
c19d1205 ZW |
568 | /* Prefix characters that indicate the start of an immediate |
569 | value. */ | |
570 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 571 | |
c19d1205 ZW |
572 | /* Separator character handling. */ |
573 | ||
574 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
575 | ||
576 | static inline int | |
577 | skip_past_char (char ** str, char c) | |
578 | { | |
579 | if (**str == c) | |
580 | { | |
581 | (*str)++; | |
582 | return SUCCESS; | |
3d0c9500 | 583 | } |
c19d1205 ZW |
584 | else |
585 | return FAIL; | |
586 | } | |
587 | #define skip_past_comma(str) skip_past_char (str, ',') | |
3d0c9500 | 588 | |
c19d1205 ZW |
589 | /* Arithmetic expressions (possibly involving symbols). */ |
590 | ||
591 | /* Return TRUE if anything in the expression is a bignum. */ | |
592 | ||
593 | static int | |
594 | walk_no_bignums (symbolS * sp) | |
595 | { | |
596 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
597 | return 1; | |
598 | ||
599 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 600 | { |
c19d1205 ZW |
601 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
602 | || (symbol_get_value_expression (sp)->X_op_symbol | |
603 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
604 | } |
605 | ||
c19d1205 | 606 | return 0; |
3d0c9500 NC |
607 | } |
608 | ||
c19d1205 ZW |
609 | static int in_my_get_expression = 0; |
610 | ||
611 | /* Third argument to my_get_expression. */ | |
612 | #define GE_NO_PREFIX 0 | |
613 | #define GE_IMM_PREFIX 1 | |
614 | #define GE_OPT_PREFIX 2 | |
a737bd4d | 615 | |
b99bd4ef | 616 | static int |
c19d1205 | 617 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 618 | { |
c19d1205 ZW |
619 | char * save_in; |
620 | segT seg; | |
b99bd4ef | 621 | |
c19d1205 ZW |
622 | /* In unified syntax, all prefixes are optional. */ |
623 | if (unified_syntax) | |
624 | prefix_mode = GE_OPT_PREFIX; | |
b99bd4ef | 625 | |
c19d1205 | 626 | switch (prefix_mode) |
b99bd4ef | 627 | { |
c19d1205 ZW |
628 | case GE_NO_PREFIX: break; |
629 | case GE_IMM_PREFIX: | |
630 | if (!is_immediate_prefix (**str)) | |
631 | { | |
632 | inst.error = _("immediate expression requires a # prefix"); | |
633 | return FAIL; | |
634 | } | |
635 | (*str)++; | |
636 | break; | |
637 | case GE_OPT_PREFIX: | |
638 | if (is_immediate_prefix (**str)) | |
639 | (*str)++; | |
640 | break; | |
641 | default: abort (); | |
642 | } | |
b99bd4ef | 643 | |
c19d1205 | 644 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 645 | |
c19d1205 ZW |
646 | save_in = input_line_pointer; |
647 | input_line_pointer = *str; | |
648 | in_my_get_expression = 1; | |
649 | seg = expression (ep); | |
650 | in_my_get_expression = 0; | |
651 | ||
652 | if (ep->X_op == O_illegal) | |
b99bd4ef | 653 | { |
c19d1205 ZW |
654 | /* We found a bad expression in md_operand(). */ |
655 | *str = input_line_pointer; | |
656 | input_line_pointer = save_in; | |
657 | if (inst.error == NULL) | |
658 | inst.error = _("bad expression"); | |
659 | return 1; | |
660 | } | |
b99bd4ef | 661 | |
c19d1205 ZW |
662 | #ifdef OBJ_AOUT |
663 | if (seg != absolute_section | |
664 | && seg != text_section | |
665 | && seg != data_section | |
666 | && seg != bss_section | |
667 | && seg != undefined_section) | |
668 | { | |
669 | inst.error = _("bad segment"); | |
670 | *str = input_line_pointer; | |
671 | input_line_pointer = save_in; | |
672 | return 1; | |
b99bd4ef | 673 | } |
c19d1205 | 674 | #endif |
b99bd4ef | 675 | |
c19d1205 ZW |
676 | /* Get rid of any bignums now, so that we don't generate an error for which |
677 | we can't establish a line number later on. Big numbers are never valid | |
678 | in instructions, which is where this routine is always called. */ | |
679 | if (ep->X_op == O_big | |
680 | || (ep->X_add_symbol | |
681 | && (walk_no_bignums (ep->X_add_symbol) | |
682 | || (ep->X_op_symbol | |
683 | && walk_no_bignums (ep->X_op_symbol))))) | |
684 | { | |
685 | inst.error = _("invalid constant"); | |
686 | *str = input_line_pointer; | |
687 | input_line_pointer = save_in; | |
688 | return 1; | |
689 | } | |
b99bd4ef | 690 | |
c19d1205 ZW |
691 | *str = input_line_pointer; |
692 | input_line_pointer = save_in; | |
693 | return 0; | |
b99bd4ef NC |
694 | } |
695 | ||
c19d1205 ZW |
696 | /* Turn a string in input_line_pointer into a floating point constant |
697 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
698 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
699 | returned, or NULL on OK. | |
b99bd4ef | 700 | |
c19d1205 ZW |
701 | Note that fp constants aren't represent in the normal way on the ARM. |
702 | In big endian mode, things are as expected. However, in little endian | |
703 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
704 | within the words. For example, (double) 1.1 in big endian mode is | |
705 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
706 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 707 | |
c19d1205 | 708 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 709 | |
c19d1205 ZW |
710 | char * |
711 | md_atof (int type, char * litP, int * sizeP) | |
712 | { | |
713 | int prec; | |
714 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
715 | char *t; | |
716 | int i; | |
b99bd4ef | 717 | |
c19d1205 ZW |
718 | switch (type) |
719 | { | |
720 | case 'f': | |
721 | case 'F': | |
722 | case 's': | |
723 | case 'S': | |
724 | prec = 2; | |
725 | break; | |
b99bd4ef | 726 | |
c19d1205 ZW |
727 | case 'd': |
728 | case 'D': | |
729 | case 'r': | |
730 | case 'R': | |
731 | prec = 4; | |
732 | break; | |
b99bd4ef | 733 | |
c19d1205 ZW |
734 | case 'x': |
735 | case 'X': | |
736 | prec = 6; | |
737 | break; | |
b99bd4ef | 738 | |
c19d1205 ZW |
739 | case 'p': |
740 | case 'P': | |
741 | prec = 6; | |
742 | break; | |
a737bd4d | 743 | |
c19d1205 ZW |
744 | default: |
745 | *sizeP = 0; | |
746 | return _("bad call to MD_ATOF()"); | |
747 | } | |
b99bd4ef | 748 | |
c19d1205 ZW |
749 | t = atof_ieee (input_line_pointer, type, words); |
750 | if (t) | |
751 | input_line_pointer = t; | |
752 | *sizeP = prec * 2; | |
b99bd4ef | 753 | |
c19d1205 ZW |
754 | if (target_big_endian) |
755 | { | |
756 | for (i = 0; i < prec; i++) | |
757 | { | |
758 | md_number_to_chars (litP, (valueT) words[i], 2); | |
759 | litP += 2; | |
760 | } | |
761 | } | |
762 | else | |
763 | { | |
764 | if (cpu_variant & FPU_ARCH_VFP) | |
765 | for (i = prec - 1; i >= 0; i--) | |
766 | { | |
767 | md_number_to_chars (litP, (valueT) words[i], 2); | |
768 | litP += 2; | |
769 | } | |
770 | else | |
771 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
772 | For an 8 byte float the order is 1 0 3 2. */ | |
773 | for (i = 0; i < prec; i += 2) | |
774 | { | |
775 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
776 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
777 | litP += 4; | |
778 | } | |
779 | } | |
b99bd4ef | 780 | |
c19d1205 ZW |
781 | return 0; |
782 | } | |
b99bd4ef | 783 | |
c19d1205 ZW |
784 | /* We handle all bad expressions here, so that we can report the faulty |
785 | instruction in the error message. */ | |
786 | void | |
787 | md_operand (expressionS * expr) | |
788 | { | |
789 | if (in_my_get_expression) | |
790 | expr->X_op = O_illegal; | |
b99bd4ef NC |
791 | } |
792 | ||
c19d1205 | 793 | /* Immediate values. */ |
b99bd4ef | 794 | |
c19d1205 ZW |
795 | /* Generic immediate-value read function for use in directives. |
796 | Accepts anything that 'expression' can fold to a constant. | |
797 | *val receives the number. */ | |
798 | #ifdef OBJ_ELF | |
799 | static int | |
800 | immediate_for_directive (int *val) | |
b99bd4ef | 801 | { |
c19d1205 ZW |
802 | expressionS exp; |
803 | exp.X_op = O_illegal; | |
b99bd4ef | 804 | |
c19d1205 ZW |
805 | if (is_immediate_prefix (*input_line_pointer)) |
806 | { | |
807 | input_line_pointer++; | |
808 | expression (&exp); | |
809 | } | |
b99bd4ef | 810 | |
c19d1205 ZW |
811 | if (exp.X_op != O_constant) |
812 | { | |
813 | as_bad (_("expected #constant")); | |
814 | ignore_rest_of_line (); | |
815 | return FAIL; | |
816 | } | |
817 | *val = exp.X_add_number; | |
818 | return SUCCESS; | |
b99bd4ef | 819 | } |
c19d1205 | 820 | #endif |
b99bd4ef | 821 | |
c19d1205 | 822 | /* Register parsing. */ |
b99bd4ef | 823 | |
c19d1205 ZW |
824 | /* Generic register parser. CCP points to what should be the |
825 | beginning of a register name. If it is indeed a valid register | |
826 | name, advance CCP over it and return the reg_entry structure; | |
827 | otherwise return NULL. Does not issue diagnostics. */ | |
828 | ||
829 | static struct reg_entry * | |
830 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 831 | { |
c19d1205 ZW |
832 | char *start = *ccp; |
833 | char *p; | |
834 | struct reg_entry *reg; | |
b99bd4ef | 835 | |
c19d1205 ZW |
836 | #ifdef REGISTER_PREFIX |
837 | if (*start != REGISTER_PREFIX) | |
838 | return FAIL; | |
839 | start++; | |
840 | #endif | |
841 | #ifdef OPTIONAL_REGISTER_PREFIX | |
842 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
843 | start++; | |
844 | #endif | |
b99bd4ef | 845 | |
c19d1205 ZW |
846 | p = start; |
847 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
848 | return NULL; | |
b99bd4ef | 849 | |
c19d1205 ZW |
850 | do |
851 | p++; | |
852 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
853 | ||
854 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
855 | ||
856 | if (!reg) | |
857 | return NULL; | |
858 | ||
859 | *ccp = p; | |
860 | return reg; | |
b99bd4ef NC |
861 | } |
862 | ||
c19d1205 ZW |
863 | /* As above, but the register must be of type TYPE, and the return |
864 | value is the register number or NULL. */ | |
865 | ||
b99bd4ef | 866 | static int |
c19d1205 | 867 | arm_reg_parse (char **ccp, enum arm_reg_type type) |
b99bd4ef | 868 | { |
c19d1205 ZW |
869 | char *start = *ccp; |
870 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
b99bd4ef | 871 | |
c19d1205 ZW |
872 | if (reg && reg->type == type) |
873 | return reg->number; | |
6057a28f | 874 | |
c19d1205 ZW |
875 | /* Alternative syntaxes are accepted for a few register classes. */ |
876 | switch (type) | |
877 | { | |
878 | case REG_TYPE_MVF: | |
879 | case REG_TYPE_MVD: | |
880 | case REG_TYPE_MVFX: | |
881 | case REG_TYPE_MVDX: | |
882 | /* Generic coprocessor register names are allowed for these. */ | |
883 | if (reg->type == REG_TYPE_CN) | |
884 | return reg->number; | |
885 | break; | |
69b97547 | 886 | |
c19d1205 ZW |
887 | case REG_TYPE_CP: |
888 | /* For backward compatibility, a bare number is valid here. */ | |
889 | { | |
890 | unsigned long processor = strtoul (start, ccp, 10); | |
891 | if (*ccp != start && processor <= 15) | |
892 | return processor; | |
893 | } | |
6057a28f | 894 | |
c19d1205 ZW |
895 | case REG_TYPE_MMXWC: |
896 | /* WC includes WCG. ??? I'm not sure this is true for all | |
897 | instructions that take WC registers. */ | |
898 | if (reg->type == REG_TYPE_MMXWCG) | |
899 | return reg->number; | |
6057a28f | 900 | break; |
c19d1205 | 901 | |
6057a28f | 902 | default: |
c19d1205 | 903 | break; |
6057a28f NC |
904 | } |
905 | ||
c19d1205 ZW |
906 | *ccp = start; |
907 | return FAIL; | |
908 | } | |
69b97547 | 909 | |
c19d1205 ZW |
910 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
911 | static long | |
912 | parse_reg_list (char ** strp) | |
913 | { | |
914 | char * str = * strp; | |
915 | long range = 0; | |
916 | int another_range; | |
a737bd4d | 917 | |
c19d1205 ZW |
918 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
919 | do | |
6057a28f | 920 | { |
c19d1205 | 921 | another_range = 0; |
a737bd4d | 922 | |
c19d1205 ZW |
923 | if (*str == '{') |
924 | { | |
925 | int in_range = 0; | |
926 | int cur_reg = -1; | |
a737bd4d | 927 | |
c19d1205 ZW |
928 | str++; |
929 | do | |
930 | { | |
931 | int reg; | |
6057a28f | 932 | |
c19d1205 ZW |
933 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
934 | { | |
935 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
936 | return FAIL; | |
937 | } | |
a737bd4d | 938 | |
c19d1205 ZW |
939 | if (in_range) |
940 | { | |
941 | int i; | |
a737bd4d | 942 | |
c19d1205 ZW |
943 | if (reg <= cur_reg) |
944 | { | |
945 | inst.error = _("bad range in register list"); | |
946 | return FAIL; | |
947 | } | |
40a18ebd | 948 | |
c19d1205 ZW |
949 | for (i = cur_reg + 1; i < reg; i++) |
950 | { | |
951 | if (range & (1 << i)) | |
952 | as_tsktsk | |
953 | (_("Warning: duplicated register (r%d) in register list"), | |
954 | i); | |
955 | else | |
956 | range |= 1 << i; | |
957 | } | |
958 | in_range = 0; | |
959 | } | |
a737bd4d | 960 | |
c19d1205 ZW |
961 | if (range & (1 << reg)) |
962 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
963 | reg); | |
964 | else if (reg <= cur_reg) | |
965 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 966 | |
c19d1205 ZW |
967 | range |= 1 << reg; |
968 | cur_reg = reg; | |
969 | } | |
970 | while (skip_past_comma (&str) != FAIL | |
971 | || (in_range = 1, *str++ == '-')); | |
972 | str--; | |
a737bd4d | 973 | |
c19d1205 ZW |
974 | if (*str++ != '}') |
975 | { | |
976 | inst.error = _("missing `}'"); | |
977 | return FAIL; | |
978 | } | |
979 | } | |
980 | else | |
981 | { | |
982 | expressionS expr; | |
40a18ebd | 983 | |
c19d1205 ZW |
984 | if (my_get_expression (&expr, &str, GE_NO_PREFIX)) |
985 | return FAIL; | |
40a18ebd | 986 | |
c19d1205 ZW |
987 | if (expr.X_op == O_constant) |
988 | { | |
989 | if (expr.X_add_number | |
990 | != (expr.X_add_number & 0x0000ffff)) | |
991 | { | |
992 | inst.error = _("invalid register mask"); | |
993 | return FAIL; | |
994 | } | |
a737bd4d | 995 | |
c19d1205 ZW |
996 | if ((range & expr.X_add_number) != 0) |
997 | { | |
998 | int regno = range & expr.X_add_number; | |
a737bd4d | 999 | |
c19d1205 ZW |
1000 | regno &= -regno; |
1001 | regno = (1 << regno) - 1; | |
1002 | as_tsktsk | |
1003 | (_("Warning: duplicated register (r%d) in register list"), | |
1004 | regno); | |
1005 | } | |
a737bd4d | 1006 | |
c19d1205 ZW |
1007 | range |= expr.X_add_number; |
1008 | } | |
1009 | else | |
1010 | { | |
1011 | if (inst.reloc.type != 0) | |
1012 | { | |
1013 | inst.error = _("expression too complex"); | |
1014 | return FAIL; | |
1015 | } | |
a737bd4d | 1016 | |
c19d1205 ZW |
1017 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); |
1018 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
1019 | inst.reloc.pc_rel = 0; | |
1020 | } | |
1021 | } | |
a737bd4d | 1022 | |
c19d1205 ZW |
1023 | if (*str == '|' || *str == '+') |
1024 | { | |
1025 | str++; | |
1026 | another_range = 1; | |
1027 | } | |
a737bd4d | 1028 | } |
c19d1205 | 1029 | while (another_range); |
a737bd4d | 1030 | |
c19d1205 ZW |
1031 | *strp = str; |
1032 | return range; | |
a737bd4d NC |
1033 | } |
1034 | ||
c19d1205 ZW |
1035 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1036 | Otherwise return the number of registers, and set PBASE to the first | |
1037 | register. Double precision registers are matched if DP is nonzero. */ | |
6057a28f | 1038 | |
c19d1205 | 1039 | static int |
ca3f61f7 | 1040 | parse_vfp_reg_list (char **str, unsigned int *pbase, int dp) |
6057a28f | 1041 | { |
c19d1205 ZW |
1042 | int base_reg; |
1043 | int new_base; | |
1044 | int regtype; | |
1045 | int max_regs; | |
1046 | int count = 0; | |
1047 | int warned = 0; | |
1048 | unsigned long mask = 0; | |
a737bd4d | 1049 | int i; |
6057a28f | 1050 | |
c19d1205 ZW |
1051 | if (**str != '{') |
1052 | return FAIL; | |
6057a28f | 1053 | |
c19d1205 | 1054 | (*str)++; |
6057a28f | 1055 | |
c19d1205 | 1056 | if (dp) |
a737bd4d | 1057 | { |
c19d1205 ZW |
1058 | regtype = REG_TYPE_VFD; |
1059 | max_regs = 16; | |
1060 | } | |
1061 | else | |
1062 | { | |
1063 | regtype = REG_TYPE_VFS; | |
1064 | max_regs = 32; | |
1065 | } | |
6057a28f | 1066 | |
c19d1205 | 1067 | base_reg = max_regs; |
a737bd4d | 1068 | |
c19d1205 ZW |
1069 | do |
1070 | { | |
1071 | new_base = arm_reg_parse (str, regtype); | |
1072 | if (new_base == FAIL) | |
a737bd4d | 1073 | { |
c19d1205 ZW |
1074 | inst.error = gettext (reg_expected_msgs[regtype]); |
1075 | return FAIL; | |
1076 | } | |
a737bd4d | 1077 | |
c19d1205 ZW |
1078 | if (new_base < base_reg) |
1079 | base_reg = new_base; | |
a737bd4d | 1080 | |
c19d1205 ZW |
1081 | if (mask & (1 << new_base)) |
1082 | { | |
1083 | inst.error = _("invalid register list"); | |
1084 | return FAIL; | |
a737bd4d | 1085 | } |
a737bd4d | 1086 | |
c19d1205 ZW |
1087 | if ((mask >> new_base) != 0 && ! warned) |
1088 | { | |
1089 | as_tsktsk (_("register list not in ascending order")); | |
1090 | warned = 1; | |
1091 | } | |
0bbf2aa4 | 1092 | |
c19d1205 ZW |
1093 | mask |= 1 << new_base; |
1094 | count++; | |
0bbf2aa4 | 1095 | |
c19d1205 ZW |
1096 | if (**str == '-') /* We have the start of a range expression */ |
1097 | { | |
1098 | int high_range; | |
0bbf2aa4 | 1099 | |
c19d1205 | 1100 | (*str)++; |
0bbf2aa4 | 1101 | |
c19d1205 ZW |
1102 | if ((high_range = arm_reg_parse (str, regtype)) == FAIL) |
1103 | { | |
1104 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1105 | return FAIL; | |
1106 | } | |
0bbf2aa4 | 1107 | |
c19d1205 ZW |
1108 | if (high_range <= new_base) |
1109 | { | |
1110 | inst.error = _("register range not in ascending order"); | |
1111 | return FAIL; | |
1112 | } | |
0bbf2aa4 | 1113 | |
c19d1205 | 1114 | for (new_base++; new_base <= high_range; new_base++) |
0bbf2aa4 | 1115 | { |
c19d1205 | 1116 | if (mask & (1 << new_base)) |
0bbf2aa4 | 1117 | { |
c19d1205 ZW |
1118 | inst.error = _("invalid register list"); |
1119 | return FAIL; | |
0bbf2aa4 | 1120 | } |
c19d1205 ZW |
1121 | |
1122 | mask |= 1 << new_base; | |
1123 | count++; | |
0bbf2aa4 | 1124 | } |
0bbf2aa4 | 1125 | } |
0bbf2aa4 | 1126 | } |
c19d1205 | 1127 | while (skip_past_comma (str) != FAIL); |
0bbf2aa4 | 1128 | |
c19d1205 | 1129 | (*str)++; |
0bbf2aa4 | 1130 | |
c19d1205 ZW |
1131 | /* Sanity check -- should have raised a parse error above. */ |
1132 | if (count == 0 || count > max_regs) | |
1133 | abort (); | |
1134 | ||
1135 | *pbase = base_reg; | |
1136 | ||
1137 | /* Final test -- the registers must be consecutive. */ | |
1138 | mask >>= base_reg; | |
1139 | for (i = 0; i < count; i++) | |
1140 | { | |
1141 | if ((mask & (1u << i)) == 0) | |
1142 | { | |
1143 | inst.error = _("non-contiguous register range"); | |
1144 | return FAIL; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | return count; | |
b99bd4ef NC |
1149 | } |
1150 | ||
c19d1205 ZW |
1151 | /* Parse an explicit relocation suffix on an expression. This is |
1152 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
1153 | arm_reloc_hsh contains no entries, so this function can only | |
1154 | succeed if there is no () after the word. Returns -1 on error, | |
1155 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
1156 | static int | |
1157 | parse_reloc (char **str) | |
b99bd4ef | 1158 | { |
c19d1205 ZW |
1159 | struct reloc_entry *r; |
1160 | char *p, *q; | |
b99bd4ef | 1161 | |
c19d1205 ZW |
1162 | if (**str != '(') |
1163 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 1164 | |
c19d1205 ZW |
1165 | p = *str + 1; |
1166 | q = p; | |
1167 | ||
1168 | while (*q && *q != ')' && *q != ',') | |
1169 | q++; | |
1170 | if (*q != ')') | |
1171 | return -1; | |
1172 | ||
1173 | if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
1174 | return -1; | |
1175 | ||
1176 | *str = q + 1; | |
1177 | return r->reloc; | |
b99bd4ef NC |
1178 | } |
1179 | ||
c19d1205 ZW |
1180 | /* Directives: register aliases. */ |
1181 | ||
b99bd4ef | 1182 | static void |
c19d1205 | 1183 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 1184 | { |
c19d1205 ZW |
1185 | struct reg_entry *new; |
1186 | const char *name; | |
b99bd4ef | 1187 | |
c19d1205 ZW |
1188 | if ((new = hash_find (arm_reg_hsh, str)) != 0) |
1189 | { | |
1190 | if (new->builtin) | |
1191 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); | |
b99bd4ef | 1192 | |
c19d1205 ZW |
1193 | /* Only warn about a redefinition if it's not defined as the |
1194 | same register. */ | |
1195 | else if (new->number != number || new->type != type) | |
1196 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
69b97547 | 1197 | |
c19d1205 ZW |
1198 | return; |
1199 | } | |
b99bd4ef | 1200 | |
c19d1205 ZW |
1201 | name = xstrdup (str); |
1202 | new = xmalloc (sizeof (struct reg_entry)); | |
b99bd4ef | 1203 | |
c19d1205 ZW |
1204 | new->name = name; |
1205 | new->number = number; | |
1206 | new->type = type; | |
1207 | new->builtin = FALSE; | |
b99bd4ef | 1208 | |
c19d1205 ZW |
1209 | if (hash_insert (arm_reg_hsh, name, (PTR) new)) |
1210 | abort (); | |
1211 | } | |
b99bd4ef | 1212 | |
c19d1205 | 1213 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 1214 | |
c19d1205 | 1215 | new_register_name .req existing_register_name |
b99bd4ef | 1216 | |
c19d1205 ZW |
1217 | If we find one, or if it looks sufficiently like one that we want to |
1218 | handle any error here, return non-zero. Otherwise return zero. */ | |
b99bd4ef | 1219 | |
c19d1205 ZW |
1220 | static int |
1221 | create_register_alias (char * newname, char *p) | |
1222 | { | |
1223 | struct reg_entry *old; | |
1224 | char *oldname, *nbuf; | |
1225 | size_t nlen; | |
b99bd4ef | 1226 | |
c19d1205 ZW |
1227 | /* The input scrubber ensures that whitespace after the mnemonic is |
1228 | collapsed to single spaces. */ | |
1229 | oldname = p; | |
1230 | if (strncmp (oldname, " .req ", 6) != 0) | |
1231 | return 0; | |
b99bd4ef | 1232 | |
c19d1205 ZW |
1233 | oldname += 6; |
1234 | if (*oldname == '\0') | |
1235 | return 0; | |
b99bd4ef | 1236 | |
c19d1205 ZW |
1237 | old = hash_find (arm_reg_hsh, oldname); |
1238 | if (!old) | |
b99bd4ef | 1239 | { |
c19d1205 ZW |
1240 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
1241 | return 1; | |
b99bd4ef NC |
1242 | } |
1243 | ||
c19d1205 ZW |
1244 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
1245 | the desired alias name, and p points to its end. If not, then | |
1246 | the desired alias name is in the global original_case_string. */ | |
1247 | #ifdef TC_CASE_SENSITIVE | |
1248 | nlen = p - newname; | |
1249 | #else | |
1250 | newname = original_case_string; | |
1251 | nlen = strlen (newname); | |
1252 | #endif | |
b99bd4ef | 1253 | |
c19d1205 ZW |
1254 | nbuf = alloca (nlen + 1); |
1255 | memcpy (nbuf, newname, nlen); | |
1256 | nbuf[nlen] = '\0'; | |
b99bd4ef | 1257 | |
c19d1205 ZW |
1258 | /* Create aliases under the new name as stated; an all-lowercase |
1259 | version of the new name; and an all-uppercase version of the new | |
1260 | name. */ | |
1261 | insert_reg_alias (nbuf, old->number, old->type); | |
b99bd4ef | 1262 | |
c19d1205 ZW |
1263 | for (p = nbuf; *p; p++) |
1264 | *p = TOUPPER (*p); | |
1265 | ||
1266 | if (strncmp (nbuf, newname, nlen)) | |
1267 | insert_reg_alias (nbuf, old->number, old->type); | |
1268 | ||
1269 | for (p = nbuf; *p; p++) | |
1270 | *p = TOLOWER (*p); | |
1271 | ||
1272 | if (strncmp (nbuf, newname, nlen)) | |
1273 | insert_reg_alias (nbuf, old->number, old->type); | |
1274 | ||
1275 | return 1; | |
b99bd4ef NC |
1276 | } |
1277 | ||
c19d1205 ZW |
1278 | /* Should never be called, as .req goes between the alias and the |
1279 | register name, not at the beginning of the line. */ | |
b99bd4ef | 1280 | static void |
c19d1205 | 1281 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1282 | { |
c19d1205 ZW |
1283 | as_bad (_("invalid syntax for .req directive")); |
1284 | } | |
b99bd4ef | 1285 | |
c19d1205 ZW |
1286 | /* The .unreq directive deletes an alias which was previously defined |
1287 | by .req. For example: | |
b99bd4ef | 1288 | |
c19d1205 ZW |
1289 | my_alias .req r11 |
1290 | .unreq my_alias */ | |
b99bd4ef NC |
1291 | |
1292 | static void | |
c19d1205 | 1293 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1294 | { |
c19d1205 ZW |
1295 | char * name; |
1296 | char saved_char; | |
b99bd4ef | 1297 | |
c19d1205 ZW |
1298 | name = input_line_pointer; |
1299 | ||
1300 | while (*input_line_pointer != 0 | |
1301 | && *input_line_pointer != ' ' | |
1302 | && *input_line_pointer != '\n') | |
1303 | ++input_line_pointer; | |
1304 | ||
1305 | saved_char = *input_line_pointer; | |
1306 | *input_line_pointer = 0; | |
1307 | ||
1308 | if (!*name) | |
1309 | as_bad (_("invalid syntax for .unreq directive")); | |
1310 | else | |
1311 | { | |
1312 | struct reg_entry *reg = hash_find (arm_reg_hsh, name); | |
1313 | ||
1314 | if (!reg) | |
1315 | as_bad (_("unknown register alias '%s'"), name); | |
1316 | else if (reg->builtin) | |
1317 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
1318 | name); | |
1319 | else | |
1320 | { | |
1321 | hash_delete (arm_reg_hsh, name); | |
1322 | free ((char *) reg->name); | |
1323 | free (reg); | |
1324 | } | |
1325 | } | |
b99bd4ef | 1326 | |
c19d1205 | 1327 | *input_line_pointer = saved_char; |
b99bd4ef NC |
1328 | demand_empty_rest_of_line (); |
1329 | } | |
1330 | ||
c19d1205 ZW |
1331 | /* Directives: Instruction set selection. */ |
1332 | ||
1333 | #ifdef OBJ_ELF | |
1334 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
1335 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
1336 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
1337 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
1338 | ||
1339 | static enum mstate mapstate = MAP_UNDEFINED; | |
b99bd4ef NC |
1340 | |
1341 | static void | |
c19d1205 | 1342 | mapping_state (enum mstate state) |
b99bd4ef | 1343 | { |
a737bd4d | 1344 | symbolS * symbolP; |
c19d1205 ZW |
1345 | const char * symname; |
1346 | int type; | |
b99bd4ef | 1347 | |
c19d1205 ZW |
1348 | if (mapstate == state) |
1349 | /* The mapping symbol has already been emitted. | |
1350 | There is nothing else to do. */ | |
1351 | return; | |
b99bd4ef | 1352 | |
c19d1205 | 1353 | mapstate = state; |
b99bd4ef | 1354 | |
c19d1205 | 1355 | switch (state) |
b99bd4ef | 1356 | { |
c19d1205 ZW |
1357 | case MAP_DATA: |
1358 | symname = "$d"; | |
1359 | type = BSF_NO_FLAGS; | |
1360 | break; | |
1361 | case MAP_ARM: | |
1362 | symname = "$a"; | |
1363 | type = BSF_NO_FLAGS; | |
1364 | break; | |
1365 | case MAP_THUMB: | |
1366 | symname = "$t"; | |
1367 | type = BSF_NO_FLAGS; | |
1368 | break; | |
1369 | case MAP_UNDEFINED: | |
1370 | return; | |
1371 | default: | |
1372 | abort (); | |
1373 | } | |
1374 | ||
1375 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
1376 | ||
1377 | symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); | |
1378 | symbol_table_insert (symbolP); | |
1379 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
1380 | ||
1381 | switch (state) | |
1382 | { | |
1383 | case MAP_ARM: | |
1384 | THUMB_SET_FUNC (symbolP, 0); | |
1385 | ARM_SET_THUMB (symbolP, 0); | |
1386 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1387 | break; | |
1388 | ||
1389 | case MAP_THUMB: | |
1390 | THUMB_SET_FUNC (symbolP, 1); | |
1391 | ARM_SET_THUMB (symbolP, 1); | |
1392 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1393 | break; | |
1394 | ||
1395 | case MAP_DATA: | |
1396 | default: | |
1397 | return; | |
1398 | } | |
1399 | } | |
1400 | #else | |
1401 | #define mapping_state(x) /* nothing */ | |
1402 | #endif | |
1403 | ||
1404 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
1405 | ||
1406 | static symbolS * | |
1407 | find_real_start (symbolS * symbolP) | |
1408 | { | |
1409 | char * real_start; | |
1410 | const char * name = S_GET_NAME (symbolP); | |
1411 | symbolS * new_target; | |
1412 | ||
1413 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
1414 | #define STUB_NAME ".real_start_of" | |
1415 | ||
1416 | if (name == NULL) | |
1417 | abort (); | |
1418 | ||
37f6032b ZW |
1419 | /* The compiler may generate BL instructions to local labels because |
1420 | it needs to perform a branch to a far away location. These labels | |
1421 | do not have a corresponding ".real_start_of" label. We check | |
1422 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
1423 | the ".real_start_of" convention for nonlocal branches. */ | |
1424 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
1425 | return symbolP; |
1426 | ||
37f6032b | 1427 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
1428 | new_target = symbol_find (real_start); |
1429 | ||
1430 | if (new_target == NULL) | |
1431 | { | |
1432 | as_warn ("Failed to find real start of function: %s\n", name); | |
1433 | new_target = symbolP; | |
1434 | } | |
1435 | ||
c19d1205 ZW |
1436 | return new_target; |
1437 | } | |
1438 | ||
1439 | static void | |
1440 | opcode_select (int width) | |
1441 | { | |
1442 | switch (width) | |
1443 | { | |
1444 | case 16: | |
1445 | if (! thumb_mode) | |
1446 | { | |
1447 | if (! (cpu_variant & ARM_EXT_V4T)) | |
1448 | as_bad (_("selected processor does not support THUMB opcodes")); | |
1449 | ||
1450 | thumb_mode = 1; | |
1451 | /* No need to force the alignment, since we will have been | |
1452 | coming from ARM mode, which is word-aligned. */ | |
1453 | record_alignment (now_seg, 1); | |
1454 | } | |
1455 | mapping_state (MAP_THUMB); | |
1456 | break; | |
1457 | ||
1458 | case 32: | |
1459 | if (thumb_mode) | |
1460 | { | |
1461 | if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T) | |
1462 | as_bad (_("selected processor does not support ARM opcodes")); | |
1463 | ||
1464 | thumb_mode = 0; | |
1465 | ||
1466 | if (!need_pass_2) | |
1467 | frag_align (2, 0, 0); | |
1468 | ||
1469 | record_alignment (now_seg, 1); | |
1470 | } | |
1471 | mapping_state (MAP_ARM); | |
1472 | break; | |
1473 | ||
1474 | default: | |
1475 | as_bad (_("invalid instruction size selected (%d)"), width); | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | static void | |
1480 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
1481 | { | |
1482 | opcode_select (32); | |
1483 | demand_empty_rest_of_line (); | |
1484 | } | |
1485 | ||
1486 | static void | |
1487 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
1488 | { | |
1489 | opcode_select (16); | |
1490 | demand_empty_rest_of_line (); | |
1491 | } | |
1492 | ||
1493 | static void | |
1494 | s_code (int unused ATTRIBUTE_UNUSED) | |
1495 | { | |
1496 | int temp; | |
1497 | ||
1498 | temp = get_absolute_expression (); | |
1499 | switch (temp) | |
1500 | { | |
1501 | case 16: | |
1502 | case 32: | |
1503 | opcode_select (temp); | |
1504 | break; | |
1505 | ||
1506 | default: | |
1507 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
1508 | } | |
1509 | } | |
1510 | ||
1511 | static void | |
1512 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
1513 | { | |
1514 | /* If we are not already in thumb mode go into it, EVEN if | |
1515 | the target processor does not support thumb instructions. | |
1516 | This is used by gcc/config/arm/lib1funcs.asm for example | |
1517 | to compile interworking support functions even if the | |
1518 | target processor should not support interworking. */ | |
1519 | if (! thumb_mode) | |
1520 | { | |
1521 | thumb_mode = 2; | |
1522 | record_alignment (now_seg, 1); | |
1523 | } | |
1524 | ||
1525 | demand_empty_rest_of_line (); | |
1526 | } | |
1527 | ||
1528 | static void | |
1529 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
1530 | { | |
1531 | s_thumb (0); | |
1532 | ||
1533 | /* The following label is the name/address of the start of a Thumb function. | |
1534 | We need to know this for the interworking support. */ | |
1535 | label_is_thumb_function_name = TRUE; | |
1536 | } | |
1537 | ||
1538 | /* Perform a .set directive, but also mark the alias as | |
1539 | being a thumb function. */ | |
1540 | ||
1541 | static void | |
1542 | s_thumb_set (int equiv) | |
1543 | { | |
1544 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
1545 | We cannot just call that code as we need to get at the symbol that | |
1546 | is created. */ | |
1547 | char * name; | |
1548 | char delim; | |
1549 | char * end_name; | |
1550 | symbolS * symbolP; | |
1551 | ||
1552 | /* Especial apologies for the random logic: | |
1553 | This just grew, and could be parsed much more simply! | |
1554 | Dean - in haste. */ | |
1555 | name = input_line_pointer; | |
1556 | delim = get_symbol_end (); | |
1557 | end_name = input_line_pointer; | |
1558 | *end_name = delim; | |
1559 | ||
1560 | if (*input_line_pointer != ',') | |
1561 | { | |
1562 | *end_name = 0; | |
1563 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
1564 | *end_name = delim; |
1565 | ignore_rest_of_line (); | |
1566 | return; | |
1567 | } | |
1568 | ||
1569 | input_line_pointer++; | |
1570 | *end_name = 0; | |
1571 | ||
1572 | if (name[0] == '.' && name[1] == '\0') | |
1573 | { | |
1574 | /* XXX - this should not happen to .thumb_set. */ | |
1575 | abort (); | |
1576 | } | |
1577 | ||
1578 | if ((symbolP = symbol_find (name)) == NULL | |
1579 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
1580 | { | |
1581 | #ifndef NO_LISTING | |
1582 | /* When doing symbol listings, play games with dummy fragments living | |
1583 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 1584 | for this symbol. */ |
b99bd4ef NC |
1585 | if (listing & LISTING_SYMBOLS) |
1586 | { | |
1587 | extern struct list_info_struct * listing_tail; | |
a737bd4d | 1588 | fragS * dummy_frag = xmalloc (sizeof (fragS)); |
b99bd4ef NC |
1589 | |
1590 | memset (dummy_frag, 0, sizeof (fragS)); | |
1591 | dummy_frag->fr_type = rs_fill; | |
1592 | dummy_frag->line = listing_tail; | |
1593 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
1594 | dummy_frag->fr_symbol = symbolP; | |
1595 | } | |
1596 | else | |
1597 | #endif | |
1598 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
1599 | ||
1600 | #ifdef OBJ_COFF | |
1601 | /* "set" symbols are local unless otherwise specified. */ | |
1602 | SF_SET_LOCAL (symbolP); | |
1603 | #endif /* OBJ_COFF */ | |
1604 | } /* Make a new symbol. */ | |
1605 | ||
1606 | symbol_table_insert (symbolP); | |
1607 | ||
1608 | * end_name = delim; | |
1609 | ||
1610 | if (equiv | |
1611 | && S_IS_DEFINED (symbolP) | |
1612 | && S_GET_SEGMENT (symbolP) != reg_section) | |
1613 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
1614 | ||
1615 | pseudo_set (symbolP); | |
1616 | ||
1617 | demand_empty_rest_of_line (); | |
1618 | ||
c19d1205 | 1619 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
1620 | |
1621 | THUMB_SET_FUNC (symbolP, 1); | |
1622 | ARM_SET_THUMB (symbolP, 1); | |
1623 | #if defined OBJ_ELF || defined OBJ_COFF | |
1624 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1625 | #endif | |
1626 | } | |
1627 | ||
c19d1205 | 1628 | /* Directives: Mode selection. */ |
b99bd4ef | 1629 | |
c19d1205 ZW |
1630 | /* .syntax [unified|divided] - choose the new unified syntax |
1631 | (same for Arm and Thumb encoding, modulo slight differences in what | |
1632 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 1633 | static void |
c19d1205 | 1634 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1635 | { |
c19d1205 ZW |
1636 | char *name, delim; |
1637 | ||
1638 | name = input_line_pointer; | |
1639 | delim = get_symbol_end (); | |
1640 | ||
1641 | if (!strcasecmp (name, "unified")) | |
1642 | unified_syntax = TRUE; | |
1643 | else if (!strcasecmp (name, "divided")) | |
1644 | unified_syntax = FALSE; | |
1645 | else | |
1646 | { | |
1647 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
1648 | return; | |
1649 | } | |
1650 | *input_line_pointer = delim; | |
b99bd4ef NC |
1651 | demand_empty_rest_of_line (); |
1652 | } | |
1653 | ||
c19d1205 ZW |
1654 | /* Directives: sectioning and alignment. */ |
1655 | ||
1656 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
1657 | ||
b99bd4ef | 1658 | static void |
c19d1205 | 1659 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1660 | { |
a737bd4d | 1661 | int temp; |
c19d1205 ZW |
1662 | long temp_fill; |
1663 | long max_alignment = 15; | |
b99bd4ef NC |
1664 | |
1665 | temp = get_absolute_expression (); | |
c19d1205 ZW |
1666 | if (temp > max_alignment) |
1667 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
1668 | else if (temp < 0) | |
b99bd4ef | 1669 | { |
c19d1205 ZW |
1670 | as_bad (_("alignment negative. 0 assumed.")); |
1671 | temp = 0; | |
1672 | } | |
b99bd4ef | 1673 | |
c19d1205 ZW |
1674 | if (*input_line_pointer == ',') |
1675 | { | |
1676 | input_line_pointer++; | |
1677 | temp_fill = get_absolute_expression (); | |
b99bd4ef | 1678 | } |
c19d1205 ZW |
1679 | else |
1680 | temp_fill = 0; | |
b99bd4ef | 1681 | |
c19d1205 ZW |
1682 | if (!temp) |
1683 | temp = 2; | |
b99bd4ef | 1684 | |
c19d1205 ZW |
1685 | /* Only make a frag if we HAVE to. */ |
1686 | if (temp && !need_pass_2) | |
1687 | frag_align (temp, (int) temp_fill, 0); | |
1688 | demand_empty_rest_of_line (); | |
1689 | ||
1690 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
1691 | } |
1692 | ||
c19d1205 ZW |
1693 | static void |
1694 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 1695 | { |
c19d1205 ZW |
1696 | /* We don't support putting frags in the BSS segment, we fake it by |
1697 | marking in_bss, then looking at s_skip for clues. */ | |
1698 | subseg_set (bss_section, 0); | |
1699 | demand_empty_rest_of_line (); | |
1700 | mapping_state (MAP_DATA); | |
1701 | } | |
b99bd4ef | 1702 | |
c19d1205 ZW |
1703 | static void |
1704 | s_even (int ignore ATTRIBUTE_UNUSED) | |
1705 | { | |
1706 | /* Never make frag if expect extra pass. */ | |
1707 | if (!need_pass_2) | |
1708 | frag_align (1, 0, 0); | |
b99bd4ef | 1709 | |
c19d1205 | 1710 | record_alignment (now_seg, 1); |
b99bd4ef | 1711 | |
c19d1205 | 1712 | demand_empty_rest_of_line (); |
b99bd4ef NC |
1713 | } |
1714 | ||
c19d1205 | 1715 | /* Directives: Literal pools. */ |
a737bd4d | 1716 | |
c19d1205 ZW |
1717 | static literal_pool * |
1718 | find_literal_pool (void) | |
a737bd4d | 1719 | { |
c19d1205 | 1720 | literal_pool * pool; |
a737bd4d | 1721 | |
c19d1205 | 1722 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 1723 | { |
c19d1205 ZW |
1724 | if (pool->section == now_seg |
1725 | && pool->sub_section == now_subseg) | |
1726 | break; | |
a737bd4d NC |
1727 | } |
1728 | ||
c19d1205 | 1729 | return pool; |
a737bd4d NC |
1730 | } |
1731 | ||
c19d1205 ZW |
1732 | static literal_pool * |
1733 | find_or_make_literal_pool (void) | |
a737bd4d | 1734 | { |
c19d1205 ZW |
1735 | /* Next literal pool ID number. */ |
1736 | static unsigned int latest_pool_num = 1; | |
1737 | literal_pool * pool; | |
a737bd4d | 1738 | |
c19d1205 | 1739 | pool = find_literal_pool (); |
a737bd4d | 1740 | |
c19d1205 | 1741 | if (pool == NULL) |
a737bd4d | 1742 | { |
c19d1205 ZW |
1743 | /* Create a new pool. */ |
1744 | pool = xmalloc (sizeof (* pool)); | |
1745 | if (! pool) | |
1746 | return NULL; | |
a737bd4d | 1747 | |
c19d1205 ZW |
1748 | pool->next_free_entry = 0; |
1749 | pool->section = now_seg; | |
1750 | pool->sub_section = now_subseg; | |
1751 | pool->next = list_of_pools; | |
1752 | pool->symbol = NULL; | |
1753 | ||
1754 | /* Add it to the list. */ | |
1755 | list_of_pools = pool; | |
a737bd4d | 1756 | } |
a737bd4d | 1757 | |
c19d1205 ZW |
1758 | /* New pools, and emptied pools, will have a NULL symbol. */ |
1759 | if (pool->symbol == NULL) | |
a737bd4d | 1760 | { |
c19d1205 ZW |
1761 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
1762 | (valueT) 0, &zero_address_frag); | |
1763 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
1764 | } |
1765 | ||
c19d1205 ZW |
1766 | /* Done. */ |
1767 | return pool; | |
a737bd4d NC |
1768 | } |
1769 | ||
c19d1205 ZW |
1770 | /* Add the literal in the global 'inst' |
1771 | structure to the relevent literal pool. */ | |
b99bd4ef NC |
1772 | |
1773 | static int | |
c19d1205 | 1774 | add_to_lit_pool (void) |
b99bd4ef | 1775 | { |
c19d1205 ZW |
1776 | literal_pool * pool; |
1777 | unsigned int entry; | |
b99bd4ef | 1778 | |
c19d1205 ZW |
1779 | pool = find_or_make_literal_pool (); |
1780 | ||
1781 | /* Check if this literal value is already in the pool. */ | |
1782 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 1783 | { |
c19d1205 ZW |
1784 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
1785 | && (inst.reloc.exp.X_op == O_constant) | |
1786 | && (pool->literals[entry].X_add_number | |
1787 | == inst.reloc.exp.X_add_number) | |
1788 | && (pool->literals[entry].X_unsigned | |
1789 | == inst.reloc.exp.X_unsigned)) | |
1790 | break; | |
1791 | ||
1792 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
1793 | && (inst.reloc.exp.X_op == O_symbol) | |
1794 | && (pool->literals[entry].X_add_number | |
1795 | == inst.reloc.exp.X_add_number) | |
1796 | && (pool->literals[entry].X_add_symbol | |
1797 | == inst.reloc.exp.X_add_symbol) | |
1798 | && (pool->literals[entry].X_op_symbol | |
1799 | == inst.reloc.exp.X_op_symbol)) | |
1800 | break; | |
b99bd4ef NC |
1801 | } |
1802 | ||
c19d1205 ZW |
1803 | /* Do we need to create a new entry? */ |
1804 | if (entry == pool->next_free_entry) | |
1805 | { | |
1806 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
1807 | { | |
1808 | inst.error = _("literal pool overflow"); | |
1809 | return FAIL; | |
1810 | } | |
1811 | ||
1812 | pool->literals[entry] = inst.reloc.exp; | |
1813 | pool->next_free_entry += 1; | |
1814 | } | |
b99bd4ef | 1815 | |
c19d1205 ZW |
1816 | inst.reloc.exp.X_op = O_symbol; |
1817 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
1818 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 1819 | |
c19d1205 | 1820 | return SUCCESS; |
b99bd4ef NC |
1821 | } |
1822 | ||
c19d1205 ZW |
1823 | /* Can't use symbol_new here, so have to create a symbol and then at |
1824 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 1825 | |
c19d1205 ZW |
1826 | static void |
1827 | symbol_locate (symbolS * symbolP, | |
1828 | const char * name, /* It is copied, the caller can modify. */ | |
1829 | segT segment, /* Segment identifier (SEG_<something>). */ | |
1830 | valueT valu, /* Symbol value. */ | |
1831 | fragS * frag) /* Associated fragment. */ | |
1832 | { | |
1833 | unsigned int name_length; | |
1834 | char * preserved_copy_of_name; | |
e16bb312 | 1835 | |
c19d1205 ZW |
1836 | name_length = strlen (name) + 1; /* +1 for \0. */ |
1837 | obstack_grow (¬es, name, name_length); | |
1838 | preserved_copy_of_name = obstack_finish (¬es); | |
e16bb312 | 1839 | |
c19d1205 ZW |
1840 | #ifdef tc_canonicalize_symbol_name |
1841 | preserved_copy_of_name = | |
1842 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1843 | #endif | |
b99bd4ef | 1844 | |
c19d1205 | 1845 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 1846 | |
c19d1205 ZW |
1847 | S_SET_SEGMENT (symbolP, segment); |
1848 | S_SET_VALUE (symbolP, valu); | |
1849 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 1850 | |
c19d1205 | 1851 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 1852 | |
c19d1205 ZW |
1853 | /* Link to end of symbol chain. */ |
1854 | { | |
1855 | extern int symbol_table_frozen; | |
b99bd4ef | 1856 | |
c19d1205 ZW |
1857 | if (symbol_table_frozen) |
1858 | abort (); | |
1859 | } | |
b99bd4ef | 1860 | |
c19d1205 | 1861 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 1862 | |
c19d1205 | 1863 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 1864 | |
c19d1205 ZW |
1865 | #ifdef tc_symbol_new_hook |
1866 | tc_symbol_new_hook (symbolP); | |
1867 | #endif | |
1868 | ||
1869 | #ifdef DEBUG_SYMS | |
1870 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1871 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
1872 | } |
1873 | ||
b99bd4ef | 1874 | |
c19d1205 ZW |
1875 | static void |
1876 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 1877 | { |
c19d1205 ZW |
1878 | unsigned int entry; |
1879 | literal_pool * pool; | |
1880 | char sym_name[20]; | |
b99bd4ef | 1881 | |
c19d1205 ZW |
1882 | pool = find_literal_pool (); |
1883 | if (pool == NULL | |
1884 | || pool->symbol == NULL | |
1885 | || pool->next_free_entry == 0) | |
1886 | return; | |
b99bd4ef | 1887 | |
c19d1205 | 1888 | mapping_state (MAP_DATA); |
b99bd4ef | 1889 | |
c19d1205 ZW |
1890 | /* Align pool as you have word accesses. |
1891 | Only make a frag if we have to. */ | |
1892 | if (!need_pass_2) | |
1893 | frag_align (2, 0, 0); | |
b99bd4ef | 1894 | |
c19d1205 | 1895 | record_alignment (now_seg, 2); |
b99bd4ef | 1896 | |
c19d1205 | 1897 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 1898 | |
c19d1205 ZW |
1899 | symbol_locate (pool->symbol, sym_name, now_seg, |
1900 | (valueT) frag_now_fix (), frag_now); | |
1901 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 1902 | |
c19d1205 | 1903 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 1904 | |
c19d1205 ZW |
1905 | #if defined OBJ_COFF || defined OBJ_ELF |
1906 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
1907 | #endif | |
6c43fab6 | 1908 | |
c19d1205 ZW |
1909 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
1910 | /* First output the expression in the instruction to the pool. */ | |
1911 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 1912 | |
c19d1205 ZW |
1913 | /* Mark the pool as empty. */ |
1914 | pool->next_free_entry = 0; | |
1915 | pool->symbol = NULL; | |
b99bd4ef NC |
1916 | } |
1917 | ||
c19d1205 ZW |
1918 | #ifdef OBJ_ELF |
1919 | /* Forward declarations for functions below, in the MD interface | |
1920 | section. */ | |
1921 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
1922 | static valueT create_unwind_entry (int); | |
1923 | static void start_unwind_section (const segT, int); | |
1924 | static void add_unwind_opcode (valueT, int); | |
1925 | static void flush_pending_unwind (void); | |
b99bd4ef | 1926 | |
c19d1205 | 1927 | /* Directives: Data. */ |
b99bd4ef | 1928 | |
c19d1205 ZW |
1929 | static void |
1930 | s_arm_elf_cons (int nbytes) | |
1931 | { | |
1932 | expressionS exp; | |
b99bd4ef | 1933 | |
c19d1205 ZW |
1934 | #ifdef md_flush_pending_output |
1935 | md_flush_pending_output (); | |
1936 | #endif | |
b99bd4ef | 1937 | |
c19d1205 | 1938 | if (is_it_end_of_statement ()) |
b99bd4ef | 1939 | { |
c19d1205 ZW |
1940 | demand_empty_rest_of_line (); |
1941 | return; | |
b99bd4ef NC |
1942 | } |
1943 | ||
c19d1205 ZW |
1944 | #ifdef md_cons_align |
1945 | md_cons_align (nbytes); | |
1946 | #endif | |
b99bd4ef | 1947 | |
c19d1205 ZW |
1948 | mapping_state (MAP_DATA); |
1949 | do | |
b99bd4ef | 1950 | { |
c19d1205 ZW |
1951 | int reloc; |
1952 | char *base = input_line_pointer; | |
b99bd4ef | 1953 | |
c19d1205 | 1954 | expression (& exp); |
b99bd4ef | 1955 | |
c19d1205 ZW |
1956 | if (exp.X_op != O_symbol) |
1957 | emit_expr (&exp, (unsigned int) nbytes); | |
1958 | else | |
1959 | { | |
1960 | char *before_reloc = input_line_pointer; | |
1961 | reloc = parse_reloc (&input_line_pointer); | |
1962 | if (reloc == -1) | |
1963 | { | |
1964 | as_bad (_("unrecognized relocation suffix")); | |
1965 | ignore_rest_of_line (); | |
1966 | return; | |
1967 | } | |
1968 | else if (reloc == BFD_RELOC_UNUSED) | |
1969 | emit_expr (&exp, (unsigned int) nbytes); | |
1970 | else | |
1971 | { | |
1972 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
1973 | int size = bfd_get_reloc_size (howto); | |
b99bd4ef | 1974 | |
2fc8bdac ZW |
1975 | if (reloc == BFD_RELOC_ARM_PLT32) |
1976 | { | |
1977 | as_bad (_("(plt) is only valid on branch targets")); | |
1978 | reloc = BFD_RELOC_UNUSED; | |
1979 | size = 0; | |
1980 | } | |
1981 | ||
c19d1205 | 1982 | if (size > nbytes) |
2fc8bdac | 1983 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
1984 | howto->name, nbytes); |
1985 | else | |
1986 | { | |
1987 | /* We've parsed an expression stopping at O_symbol. | |
1988 | But there may be more expression left now that we | |
1989 | have parsed the relocation marker. Parse it again. | |
1990 | XXX Surely there is a cleaner way to do this. */ | |
1991 | char *p = input_line_pointer; | |
1992 | int offset; | |
1993 | char *save_buf = alloca (input_line_pointer - base); | |
1994 | memcpy (save_buf, base, input_line_pointer - base); | |
1995 | memmove (base + (input_line_pointer - before_reloc), | |
1996 | base, before_reloc - base); | |
1997 | ||
1998 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
1999 | expression (&exp); | |
2000 | memcpy (base, save_buf, p - base); | |
2001 | ||
2002 | offset = nbytes - size; | |
2003 | p = frag_more ((int) nbytes); | |
2004 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
2005 | size, &exp, 0, reloc); | |
2006 | } | |
2007 | } | |
2008 | } | |
b99bd4ef | 2009 | } |
c19d1205 | 2010 | while (*input_line_pointer++ == ','); |
b99bd4ef | 2011 | |
c19d1205 ZW |
2012 | /* Put terminator back into stream. */ |
2013 | input_line_pointer --; | |
2014 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
2015 | } |
2016 | ||
b99bd4ef | 2017 | |
c19d1205 | 2018 | /* Parse a .rel31 directive. */ |
b99bd4ef | 2019 | |
c19d1205 ZW |
2020 | static void |
2021 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
2022 | { | |
2023 | expressionS exp; | |
2024 | char *p; | |
2025 | valueT highbit; | |
b99bd4ef | 2026 | |
c19d1205 ZW |
2027 | highbit = 0; |
2028 | if (*input_line_pointer == '1') | |
2029 | highbit = 0x80000000; | |
2030 | else if (*input_line_pointer != '0') | |
2031 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 2032 | |
c19d1205 ZW |
2033 | input_line_pointer++; |
2034 | if (*input_line_pointer != ',') | |
2035 | as_bad (_("missing comma")); | |
2036 | input_line_pointer++; | |
b99bd4ef | 2037 | |
c19d1205 ZW |
2038 | #ifdef md_flush_pending_output |
2039 | md_flush_pending_output (); | |
2040 | #endif | |
b99bd4ef | 2041 | |
c19d1205 ZW |
2042 | #ifdef md_cons_align |
2043 | md_cons_align (4); | |
2044 | #endif | |
b99bd4ef | 2045 | |
c19d1205 | 2046 | mapping_state (MAP_DATA); |
b99bd4ef | 2047 | |
c19d1205 | 2048 | expression (&exp); |
b99bd4ef | 2049 | |
c19d1205 ZW |
2050 | p = frag_more (4); |
2051 | md_number_to_chars (p, highbit, 4); | |
2052 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
2053 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 2054 | |
c19d1205 | 2055 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2056 | } |
2057 | ||
c19d1205 | 2058 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 2059 | |
c19d1205 | 2060 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 2061 | |
c19d1205 ZW |
2062 | static void |
2063 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
2064 | { | |
2065 | demand_empty_rest_of_line (); | |
2066 | /* Mark the start of the function. */ | |
2067 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 2068 | |
c19d1205 ZW |
2069 | /* Reset the rest of the unwind info. */ |
2070 | unwind.opcode_count = 0; | |
2071 | unwind.table_entry = NULL; | |
2072 | unwind.personality_routine = NULL; | |
2073 | unwind.personality_index = -1; | |
2074 | unwind.frame_size = 0; | |
2075 | unwind.fp_offset = 0; | |
2076 | unwind.fp_reg = 13; | |
2077 | unwind.fp_used = 0; | |
2078 | unwind.sp_restored = 0; | |
2079 | } | |
b99bd4ef | 2080 | |
b99bd4ef | 2081 | |
c19d1205 ZW |
2082 | /* Parse a handlerdata directive. Creates the exception handling table entry |
2083 | for the function. */ | |
b99bd4ef | 2084 | |
c19d1205 ZW |
2085 | static void |
2086 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
2087 | { | |
2088 | demand_empty_rest_of_line (); | |
2089 | if (unwind.table_entry) | |
2090 | as_bad (_("dupicate .handlerdata directive")); | |
f02232aa | 2091 | |
c19d1205 ZW |
2092 | create_unwind_entry (1); |
2093 | } | |
a737bd4d | 2094 | |
c19d1205 | 2095 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 2096 | |
c19d1205 ZW |
2097 | static void |
2098 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
2099 | { | |
2100 | long where; | |
2101 | char *ptr; | |
2102 | valueT val; | |
f02232aa | 2103 | |
c19d1205 | 2104 | demand_empty_rest_of_line (); |
f02232aa | 2105 | |
c19d1205 ZW |
2106 | /* Add eh table entry. */ |
2107 | if (unwind.table_entry == NULL) | |
2108 | val = create_unwind_entry (0); | |
2109 | else | |
2110 | val = 0; | |
f02232aa | 2111 | |
c19d1205 ZW |
2112 | /* Add index table entry. This is two words. */ |
2113 | start_unwind_section (unwind.saved_seg, 1); | |
2114 | frag_align (2, 0, 0); | |
2115 | record_alignment (now_seg, 2); | |
b99bd4ef | 2116 | |
c19d1205 ZW |
2117 | ptr = frag_more (8); |
2118 | where = frag_now_fix () - 8; | |
f02232aa | 2119 | |
c19d1205 ZW |
2120 | /* Self relative offset of the function start. */ |
2121 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
2122 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2123 | |
c19d1205 ZW |
2124 | /* Indicate dependency on EHABI-defined personality routines to the |
2125 | linker, if it hasn't been done already. */ | |
2126 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 | |
2127 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
2128 | { | |
2129 | static const char *const name[] = { | |
2130 | "__aeabi_unwind_cpp_pr0", | |
2131 | "__aeabi_unwind_cpp_pr1", | |
2132 | "__aeabi_unwind_cpp_pr2" | |
2133 | }; | |
2134 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); | |
2135 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
2136 | marked_pr_dependency |= 1 << unwind.personality_index; | |
2137 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency | |
2138 | = marked_pr_dependency; | |
2139 | } | |
f02232aa | 2140 | |
c19d1205 ZW |
2141 | if (val) |
2142 | /* Inline exception table entry. */ | |
2143 | md_number_to_chars (ptr + 4, val, 4); | |
2144 | else | |
2145 | /* Self relative offset of the table entry. */ | |
2146 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
2147 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2148 | |
c19d1205 ZW |
2149 | /* Restore the original section. */ |
2150 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
2151 | } | |
f02232aa | 2152 | |
f02232aa | 2153 | |
c19d1205 | 2154 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 2155 | |
c19d1205 ZW |
2156 | static void |
2157 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
2158 | { | |
2159 | demand_empty_rest_of_line (); | |
2160 | if (unwind.personality_routine || unwind.personality_index != -1) | |
2161 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 2162 | |
c19d1205 ZW |
2163 | unwind.personality_index = -2; |
2164 | } | |
b99bd4ef | 2165 | |
b99bd4ef | 2166 | |
c19d1205 | 2167 | /* Parse a personalityindex directive. */ |
b99bd4ef | 2168 | |
c19d1205 ZW |
2169 | static void |
2170 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
2171 | { | |
2172 | expressionS exp; | |
b99bd4ef | 2173 | |
c19d1205 ZW |
2174 | if (unwind.personality_routine || unwind.personality_index != -1) |
2175 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 2176 | |
c19d1205 | 2177 | expression (&exp); |
b99bd4ef | 2178 | |
c19d1205 ZW |
2179 | if (exp.X_op != O_constant |
2180 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 2181 | { |
c19d1205 ZW |
2182 | as_bad (_("bad personality routine number")); |
2183 | ignore_rest_of_line (); | |
2184 | return; | |
b99bd4ef NC |
2185 | } |
2186 | ||
c19d1205 | 2187 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 2188 | |
c19d1205 ZW |
2189 | demand_empty_rest_of_line (); |
2190 | } | |
e16bb312 | 2191 | |
e16bb312 | 2192 | |
c19d1205 | 2193 | /* Parse a personality directive. */ |
e16bb312 | 2194 | |
c19d1205 ZW |
2195 | static void |
2196 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
2197 | { | |
2198 | char *name, *p, c; | |
a737bd4d | 2199 | |
c19d1205 ZW |
2200 | if (unwind.personality_routine || unwind.personality_index != -1) |
2201 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 2202 | |
c19d1205 ZW |
2203 | name = input_line_pointer; |
2204 | c = get_symbol_end (); | |
2205 | p = input_line_pointer; | |
2206 | unwind.personality_routine = symbol_find_or_make (name); | |
2207 | *p = c; | |
2208 | demand_empty_rest_of_line (); | |
2209 | } | |
e16bb312 | 2210 | |
e16bb312 | 2211 | |
c19d1205 | 2212 | /* Parse a directive saving core registers. */ |
e16bb312 | 2213 | |
c19d1205 ZW |
2214 | static void |
2215 | s_arm_unwind_save_core (void) | |
e16bb312 | 2216 | { |
c19d1205 ZW |
2217 | valueT op; |
2218 | long range; | |
2219 | int n; | |
e16bb312 | 2220 | |
c19d1205 ZW |
2221 | range = parse_reg_list (&input_line_pointer); |
2222 | if (range == FAIL) | |
e16bb312 | 2223 | { |
c19d1205 ZW |
2224 | as_bad (_("expected register list")); |
2225 | ignore_rest_of_line (); | |
2226 | return; | |
2227 | } | |
e16bb312 | 2228 | |
c19d1205 | 2229 | demand_empty_rest_of_line (); |
e16bb312 | 2230 | |
c19d1205 ZW |
2231 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
2232 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
2233 | ip because it is clobbered by calls. */ | |
2234 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
2235 | && (range & 0x3000) == 0x1000) | |
2236 | { | |
2237 | unwind.opcode_count--; | |
2238 | unwind.sp_restored = 0; | |
2239 | range = (range | 0x2000) & ~0x1000; | |
2240 | unwind.pending_offset = 0; | |
2241 | } | |
e16bb312 | 2242 | |
c19d1205 ZW |
2243 | /* See if we can use the short opcodes. These pop a block of upto 8 |
2244 | registers starting with r4, plus maybe r14. */ | |
2245 | for (n = 0; n < 8; n++) | |
2246 | { | |
2247 | /* Break at the first non-saved register. */ | |
2248 | if ((range & (1 << (n + 4))) == 0) | |
2249 | break; | |
e16bb312 | 2250 | } |
c19d1205 ZW |
2251 | /* See if there are any other bits set. */ |
2252 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
e16bb312 | 2253 | { |
c19d1205 ZW |
2254 | /* Use the long form. */ |
2255 | op = 0x8000 | ((range >> 4) & 0xfff); | |
2256 | add_unwind_opcode (op, 2); | |
e16bb312 | 2257 | } |
c19d1205 | 2258 | else |
0dd132b6 | 2259 | { |
c19d1205 ZW |
2260 | /* Use the short form. */ |
2261 | if (range & 0x4000) | |
2262 | op = 0xa8; /* Pop r14. */ | |
0dd132b6 | 2263 | else |
c19d1205 ZW |
2264 | op = 0xa0; /* Do not pop r14. */ |
2265 | op |= (n - 1); | |
2266 | add_unwind_opcode (op, 1); | |
2267 | } | |
0dd132b6 | 2268 | |
c19d1205 ZW |
2269 | /* Pop r0-r3. */ |
2270 | if (range & 0xf) | |
2271 | { | |
2272 | op = 0xb100 | (range & 0xf); | |
2273 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
2274 | } |
2275 | ||
c19d1205 ZW |
2276 | /* Record the number of bytes pushed. */ |
2277 | for (n = 0; n < 16; n++) | |
2278 | { | |
2279 | if (range & (1 << n)) | |
2280 | unwind.frame_size += 4; | |
2281 | } | |
0dd132b6 NC |
2282 | } |
2283 | ||
c19d1205 ZW |
2284 | |
2285 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
2286 | |
2287 | static void | |
c19d1205 | 2288 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 2289 | { |
c19d1205 ZW |
2290 | expressionS exp; |
2291 | int num_regs; | |
2292 | valueT op; | |
b99bd4ef | 2293 | |
c19d1205 ZW |
2294 | /* Get Number of registers to transfer. */ |
2295 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2296 | expression (&exp); | |
2297 | else | |
2298 | exp.X_op = O_illegal; | |
b99bd4ef | 2299 | |
c19d1205 | 2300 | if (exp.X_op != O_constant) |
b99bd4ef | 2301 | { |
c19d1205 ZW |
2302 | as_bad (_("expected , <constant>")); |
2303 | ignore_rest_of_line (); | |
b99bd4ef NC |
2304 | return; |
2305 | } | |
2306 | ||
c19d1205 ZW |
2307 | num_regs = exp.X_add_number; |
2308 | ||
2309 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 2310 | { |
c19d1205 ZW |
2311 | as_bad (_("number of registers must be in the range [1:4]")); |
2312 | ignore_rest_of_line (); | |
b99bd4ef NC |
2313 | return; |
2314 | } | |
2315 | ||
c19d1205 | 2316 | demand_empty_rest_of_line (); |
b99bd4ef | 2317 | |
c19d1205 ZW |
2318 | if (reg == 4) |
2319 | { | |
2320 | /* Short form. */ | |
2321 | op = 0xb4 | (num_regs - 1); | |
2322 | add_unwind_opcode (op, 1); | |
2323 | } | |
b99bd4ef NC |
2324 | else |
2325 | { | |
c19d1205 ZW |
2326 | /* Long form. */ |
2327 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
2328 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2329 | } |
c19d1205 | 2330 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
2331 | } |
2332 | ||
c19d1205 ZW |
2333 | |
2334 | /* Parse a directive saving VFP registers. */ | |
b99bd4ef NC |
2335 | |
2336 | static void | |
c19d1205 | 2337 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 2338 | { |
c19d1205 | 2339 | int count; |
ca3f61f7 | 2340 | unsigned int reg; |
c19d1205 | 2341 | valueT op; |
b99bd4ef | 2342 | |
c19d1205 ZW |
2343 | count = parse_vfp_reg_list (&input_line_pointer, ®, 1); |
2344 | if (count == FAIL) | |
b99bd4ef | 2345 | { |
c19d1205 ZW |
2346 | as_bad (_("expected register list")); |
2347 | ignore_rest_of_line (); | |
b99bd4ef NC |
2348 | return; |
2349 | } | |
2350 | ||
c19d1205 | 2351 | demand_empty_rest_of_line (); |
b99bd4ef | 2352 | |
c19d1205 | 2353 | if (reg == 8) |
b99bd4ef | 2354 | { |
c19d1205 ZW |
2355 | /* Short form. */ |
2356 | op = 0xb8 | (count - 1); | |
2357 | add_unwind_opcode (op, 1); | |
b99bd4ef | 2358 | } |
c19d1205 | 2359 | else |
b99bd4ef | 2360 | { |
c19d1205 ZW |
2361 | /* Long form. */ |
2362 | op = 0xb300 | (reg << 4) | (count - 1); | |
2363 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2364 | } |
c19d1205 ZW |
2365 | unwind.frame_size += count * 8 + 4; |
2366 | } | |
b99bd4ef | 2367 | |
b99bd4ef | 2368 | |
c19d1205 ZW |
2369 | /* Parse a directive saving iWMMXt data registers. */ |
2370 | ||
2371 | static void | |
2372 | s_arm_unwind_save_mmxwr (void) | |
2373 | { | |
2374 | int reg; | |
2375 | int hi_reg; | |
2376 | int i; | |
2377 | unsigned mask = 0; | |
2378 | valueT op; | |
b99bd4ef | 2379 | |
c19d1205 ZW |
2380 | if (*input_line_pointer == '{') |
2381 | input_line_pointer++; | |
b99bd4ef | 2382 | |
c19d1205 | 2383 | do |
b99bd4ef | 2384 | { |
c19d1205 | 2385 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 2386 | |
c19d1205 | 2387 | if (reg == FAIL) |
b99bd4ef | 2388 | { |
c19d1205 ZW |
2389 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); |
2390 | goto error; | |
b99bd4ef NC |
2391 | } |
2392 | ||
c19d1205 ZW |
2393 | if (mask >> reg) |
2394 | as_tsktsk (_("register list not in ascending order")); | |
2395 | mask |= 1 << reg; | |
b99bd4ef | 2396 | |
c19d1205 ZW |
2397 | if (*input_line_pointer == '-') |
2398 | { | |
2399 | input_line_pointer++; | |
2400 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); | |
2401 | if (hi_reg == FAIL) | |
2402 | { | |
2403 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
2404 | goto error; | |
2405 | } | |
2406 | else if (reg >= hi_reg) | |
2407 | { | |
2408 | as_bad (_("bad register range")); | |
2409 | goto error; | |
2410 | } | |
2411 | for (; reg < hi_reg; reg++) | |
2412 | mask |= 1 << reg; | |
2413 | } | |
2414 | } | |
2415 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 2416 | |
c19d1205 ZW |
2417 | if (*input_line_pointer == '}') |
2418 | input_line_pointer++; | |
b99bd4ef | 2419 | |
c19d1205 | 2420 | demand_empty_rest_of_line (); |
b99bd4ef | 2421 | |
c19d1205 ZW |
2422 | /* Generate any deferred opcodes becuuse we're going to be looking at |
2423 | the list. */ | |
2424 | flush_pending_unwind (); | |
b99bd4ef | 2425 | |
c19d1205 | 2426 | for (i = 0; i < 16; i++) |
b99bd4ef | 2427 | { |
c19d1205 ZW |
2428 | if (mask & (1 << i)) |
2429 | unwind.frame_size += 8; | |
b99bd4ef NC |
2430 | } |
2431 | ||
c19d1205 ZW |
2432 | /* Attempt to combine with a previous opcode. We do this because gcc |
2433 | likes to output separate unwind directives for a single block of | |
2434 | registers. */ | |
2435 | if (unwind.opcode_count > 0) | |
b99bd4ef | 2436 | { |
c19d1205 ZW |
2437 | i = unwind.opcodes[unwind.opcode_count - 1]; |
2438 | if ((i & 0xf8) == 0xc0) | |
2439 | { | |
2440 | i &= 7; | |
2441 | /* Only merge if the blocks are contiguous. */ | |
2442 | if (i < 6) | |
2443 | { | |
2444 | if ((mask & 0xfe00) == (1 << 9)) | |
2445 | { | |
2446 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
2447 | unwind.opcode_count--; | |
2448 | } | |
2449 | } | |
2450 | else if (i == 6 && unwind.opcode_count >= 2) | |
2451 | { | |
2452 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
2453 | reg = i >> 4; | |
2454 | i &= 0xf; | |
b99bd4ef | 2455 | |
c19d1205 ZW |
2456 | op = 0xffff << (reg - 1); |
2457 | if (reg > 0 | |
2458 | || ((mask & op) == (1u << (reg - 1)))) | |
2459 | { | |
2460 | op = (1 << (reg + i + 1)) - 1; | |
2461 | op &= ~((1 << reg) - 1); | |
2462 | mask |= op; | |
2463 | unwind.opcode_count -= 2; | |
2464 | } | |
2465 | } | |
2466 | } | |
b99bd4ef NC |
2467 | } |
2468 | ||
c19d1205 ZW |
2469 | hi_reg = 15; |
2470 | /* We want to generate opcodes in the order the registers have been | |
2471 | saved, ie. descending order. */ | |
2472 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 2473 | { |
c19d1205 ZW |
2474 | /* Save registers in blocks. */ |
2475 | if (reg < 0 | |
2476 | || !(mask & (1 << reg))) | |
2477 | { | |
2478 | /* We found an unsaved reg. Generate opcodes to save the | |
2479 | preceeding block. */ | |
2480 | if (reg != hi_reg) | |
2481 | { | |
2482 | if (reg == 9) | |
2483 | { | |
2484 | /* Short form. */ | |
2485 | op = 0xc0 | (hi_reg - 10); | |
2486 | add_unwind_opcode (op, 1); | |
2487 | } | |
2488 | else | |
2489 | { | |
2490 | /* Long form. */ | |
2491 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
2492 | add_unwind_opcode (op, 2); | |
2493 | } | |
2494 | } | |
2495 | hi_reg = reg - 1; | |
2496 | } | |
b99bd4ef NC |
2497 | } |
2498 | ||
c19d1205 ZW |
2499 | return; |
2500 | error: | |
2501 | ignore_rest_of_line (); | |
b99bd4ef NC |
2502 | } |
2503 | ||
2504 | static void | |
c19d1205 | 2505 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 2506 | { |
c19d1205 ZW |
2507 | int reg; |
2508 | int hi_reg; | |
2509 | unsigned mask = 0; | |
2510 | valueT op; | |
b99bd4ef | 2511 | |
c19d1205 ZW |
2512 | if (*input_line_pointer == '{') |
2513 | input_line_pointer++; | |
b99bd4ef | 2514 | |
c19d1205 | 2515 | do |
b99bd4ef | 2516 | { |
c19d1205 | 2517 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 2518 | |
c19d1205 ZW |
2519 | if (reg == FAIL) |
2520 | { | |
2521 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2522 | goto error; | |
2523 | } | |
b99bd4ef | 2524 | |
c19d1205 ZW |
2525 | reg -= 8; |
2526 | if (mask >> reg) | |
2527 | as_tsktsk (_("register list not in ascending order")); | |
2528 | mask |= 1 << reg; | |
b99bd4ef | 2529 | |
c19d1205 ZW |
2530 | if (*input_line_pointer == '-') |
2531 | { | |
2532 | input_line_pointer++; | |
2533 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); | |
2534 | if (hi_reg == FAIL) | |
2535 | { | |
2536 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2537 | goto error; | |
2538 | } | |
2539 | else if (reg >= hi_reg) | |
2540 | { | |
2541 | as_bad (_("bad register range")); | |
2542 | goto error; | |
2543 | } | |
2544 | for (; reg < hi_reg; reg++) | |
2545 | mask |= 1 << reg; | |
2546 | } | |
b99bd4ef | 2547 | } |
c19d1205 | 2548 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 2549 | |
c19d1205 ZW |
2550 | if (*input_line_pointer == '}') |
2551 | input_line_pointer++; | |
b99bd4ef | 2552 | |
c19d1205 ZW |
2553 | demand_empty_rest_of_line (); |
2554 | ||
2555 | /* Generate any deferred opcodes becuuse we're going to be looking at | |
2556 | the list. */ | |
2557 | flush_pending_unwind (); | |
b99bd4ef | 2558 | |
c19d1205 | 2559 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 2560 | { |
c19d1205 ZW |
2561 | if (mask & (1 << reg)) |
2562 | unwind.frame_size += 4; | |
b99bd4ef | 2563 | } |
c19d1205 ZW |
2564 | op = 0xc700 | mask; |
2565 | add_unwind_opcode (op, 2); | |
2566 | return; | |
2567 | error: | |
2568 | ignore_rest_of_line (); | |
b99bd4ef NC |
2569 | } |
2570 | ||
c19d1205 ZW |
2571 | |
2572 | /* Parse an unwind_save directive. */ | |
2573 | ||
b99bd4ef | 2574 | static void |
c19d1205 | 2575 | s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED) |
b99bd4ef | 2576 | { |
c19d1205 ZW |
2577 | char *peek; |
2578 | struct reg_entry *reg; | |
2579 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 2580 | |
c19d1205 ZW |
2581 | /* Figure out what sort of save we have. */ |
2582 | peek = input_line_pointer; | |
b99bd4ef | 2583 | |
c19d1205 | 2584 | if (*peek == '{') |
b99bd4ef | 2585 | { |
c19d1205 ZW |
2586 | had_brace = TRUE; |
2587 | peek++; | |
b99bd4ef NC |
2588 | } |
2589 | ||
c19d1205 | 2590 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 2591 | |
c19d1205 | 2592 | if (!reg) |
b99bd4ef | 2593 | { |
c19d1205 ZW |
2594 | as_bad (_("register expected")); |
2595 | ignore_rest_of_line (); | |
b99bd4ef NC |
2596 | return; |
2597 | } | |
2598 | ||
c19d1205 | 2599 | switch (reg->type) |
b99bd4ef | 2600 | { |
c19d1205 ZW |
2601 | case REG_TYPE_FN: |
2602 | if (had_brace) | |
2603 | { | |
2604 | as_bad (_("FPA .unwind_save does not take a register list")); | |
2605 | ignore_rest_of_line (); | |
2606 | return; | |
2607 | } | |
2608 | s_arm_unwind_save_fpa (reg->number); | |
b99bd4ef | 2609 | return; |
c19d1205 ZW |
2610 | |
2611 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
2612 | case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return; | |
2613 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; | |
2614 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
2615 | ||
2616 | default: | |
2617 | as_bad (_(".unwind_save does not support this kind of register")); | |
2618 | ignore_rest_of_line (); | |
b99bd4ef | 2619 | } |
c19d1205 | 2620 | } |
b99bd4ef | 2621 | |
b99bd4ef | 2622 | |
c19d1205 ZW |
2623 | /* Parse an unwind_movsp directive. */ |
2624 | ||
2625 | static void | |
2626 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
2627 | { | |
2628 | int reg; | |
2629 | valueT op; | |
2630 | ||
2631 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2632 | if (reg == FAIL) | |
b99bd4ef | 2633 | { |
c19d1205 ZW |
2634 | as_bad (_(reg_expected_msgs[REG_TYPE_RN])); |
2635 | ignore_rest_of_line (); | |
b99bd4ef NC |
2636 | return; |
2637 | } | |
c19d1205 | 2638 | demand_empty_rest_of_line (); |
b99bd4ef | 2639 | |
c19d1205 | 2640 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 2641 | { |
c19d1205 | 2642 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
2643 | return; |
2644 | } | |
2645 | ||
c19d1205 ZW |
2646 | if (unwind.fp_reg != REG_SP) |
2647 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 2648 | |
c19d1205 ZW |
2649 | /* Generate opcode to restore the value. */ |
2650 | op = 0x90 | reg; | |
2651 | add_unwind_opcode (op, 1); | |
2652 | ||
2653 | /* Record the information for later. */ | |
2654 | unwind.fp_reg = reg; | |
2655 | unwind.fp_offset = unwind.frame_size; | |
2656 | unwind.sp_restored = 1; | |
b05fe5cf ZW |
2657 | } |
2658 | ||
c19d1205 ZW |
2659 | /* Parse an unwind_pad directive. */ |
2660 | ||
b05fe5cf | 2661 | static void |
c19d1205 | 2662 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 2663 | { |
c19d1205 | 2664 | int offset; |
b05fe5cf | 2665 | |
c19d1205 ZW |
2666 | if (immediate_for_directive (&offset) == FAIL) |
2667 | return; | |
b99bd4ef | 2668 | |
c19d1205 ZW |
2669 | if (offset & 3) |
2670 | { | |
2671 | as_bad (_("stack increment must be multiple of 4")); | |
2672 | ignore_rest_of_line (); | |
2673 | return; | |
2674 | } | |
b99bd4ef | 2675 | |
c19d1205 ZW |
2676 | /* Don't generate any opcodes, just record the details for later. */ |
2677 | unwind.frame_size += offset; | |
2678 | unwind.pending_offset += offset; | |
2679 | ||
2680 | demand_empty_rest_of_line (); | |
2681 | } | |
2682 | ||
2683 | /* Parse an unwind_setfp directive. */ | |
2684 | ||
2685 | static void | |
2686 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 2687 | { |
c19d1205 ZW |
2688 | int sp_reg; |
2689 | int fp_reg; | |
2690 | int offset; | |
2691 | ||
2692 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2693 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2694 | sp_reg = FAIL; | |
2695 | else | |
2696 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
b99bd4ef | 2697 | |
c19d1205 ZW |
2698 | if (fp_reg == FAIL || sp_reg == FAIL) |
2699 | { | |
2700 | as_bad (_("expected <reg>, <reg>")); | |
2701 | ignore_rest_of_line (); | |
2702 | return; | |
2703 | } | |
b99bd4ef | 2704 | |
c19d1205 ZW |
2705 | /* Optional constant. */ |
2706 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2707 | { | |
2708 | if (immediate_for_directive (&offset) == FAIL) | |
2709 | return; | |
2710 | } | |
2711 | else | |
2712 | offset = 0; | |
a737bd4d | 2713 | |
c19d1205 | 2714 | demand_empty_rest_of_line (); |
a737bd4d | 2715 | |
c19d1205 | 2716 | if (sp_reg != 13 && sp_reg != unwind.fp_reg) |
a737bd4d | 2717 | { |
c19d1205 ZW |
2718 | as_bad (_("register must be either sp or set by a previous" |
2719 | "unwind_movsp directive")); | |
2720 | return; | |
a737bd4d NC |
2721 | } |
2722 | ||
c19d1205 ZW |
2723 | /* Don't generate any opcodes, just record the information for later. */ |
2724 | unwind.fp_reg = fp_reg; | |
2725 | unwind.fp_used = 1; | |
2726 | if (sp_reg == 13) | |
2727 | unwind.fp_offset = unwind.frame_size - offset; | |
2728 | else | |
2729 | unwind.fp_offset -= offset; | |
a737bd4d NC |
2730 | } |
2731 | ||
c19d1205 ZW |
2732 | /* Parse an unwind_raw directive. */ |
2733 | ||
2734 | static void | |
2735 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 2736 | { |
c19d1205 ZW |
2737 | expressionS exp; |
2738 | /* This is an arbitary limit. */ | |
2739 | unsigned char op[16]; | |
2740 | int count; | |
a737bd4d | 2741 | |
c19d1205 ZW |
2742 | expression (&exp); |
2743 | if (exp.X_op == O_constant | |
2744 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 2745 | { |
c19d1205 ZW |
2746 | unwind.frame_size += exp.X_add_number; |
2747 | expression (&exp); | |
2748 | } | |
2749 | else | |
2750 | exp.X_op = O_illegal; | |
a737bd4d | 2751 | |
c19d1205 ZW |
2752 | if (exp.X_op != O_constant) |
2753 | { | |
2754 | as_bad (_("expected <offset>, <opcode>")); | |
2755 | ignore_rest_of_line (); | |
2756 | return; | |
2757 | } | |
a737bd4d | 2758 | |
c19d1205 | 2759 | count = 0; |
a737bd4d | 2760 | |
c19d1205 ZW |
2761 | /* Parse the opcode. */ |
2762 | for (;;) | |
2763 | { | |
2764 | if (count >= 16) | |
2765 | { | |
2766 | as_bad (_("unwind opcode too long")); | |
2767 | ignore_rest_of_line (); | |
a737bd4d | 2768 | } |
c19d1205 | 2769 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 2770 | { |
c19d1205 ZW |
2771 | as_bad (_("invalid unwind opcode")); |
2772 | ignore_rest_of_line (); | |
2773 | return; | |
a737bd4d | 2774 | } |
c19d1205 | 2775 | op[count++] = exp.X_add_number; |
a737bd4d | 2776 | |
c19d1205 ZW |
2777 | /* Parse the next byte. */ |
2778 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2779 | break; | |
a737bd4d | 2780 | |
c19d1205 ZW |
2781 | expression (&exp); |
2782 | } | |
b99bd4ef | 2783 | |
c19d1205 ZW |
2784 | /* Add the opcode bytes in reverse order. */ |
2785 | while (count--) | |
2786 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 2787 | |
c19d1205 | 2788 | demand_empty_rest_of_line (); |
b99bd4ef | 2789 | } |
c19d1205 | 2790 | #endif /* OBJ_ELF */ |
b99bd4ef | 2791 | |
c19d1205 ZW |
2792 | /* This table describes all the machine specific pseudo-ops the assembler |
2793 | has to support. The fields are: | |
2794 | pseudo-op name without dot | |
2795 | function to call to execute this pseudo-op | |
2796 | Integer arg to pass to the function. */ | |
b99bd4ef | 2797 | |
c19d1205 | 2798 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 2799 | { |
c19d1205 ZW |
2800 | /* Never called because '.req' does not start a line. */ |
2801 | { "req", s_req, 0 }, | |
2802 | { "unreq", s_unreq, 0 }, | |
2803 | { "bss", s_bss, 0 }, | |
2804 | { "align", s_align, 0 }, | |
2805 | { "arm", s_arm, 0 }, | |
2806 | { "thumb", s_thumb, 0 }, | |
2807 | { "code", s_code, 0 }, | |
2808 | { "force_thumb", s_force_thumb, 0 }, | |
2809 | { "thumb_func", s_thumb_func, 0 }, | |
2810 | { "thumb_set", s_thumb_set, 0 }, | |
2811 | { "even", s_even, 0 }, | |
2812 | { "ltorg", s_ltorg, 0 }, | |
2813 | { "pool", s_ltorg, 0 }, | |
2814 | { "syntax", s_syntax, 0 }, | |
2815 | #ifdef OBJ_ELF | |
2816 | { "word", s_arm_elf_cons, 4 }, | |
2817 | { "long", s_arm_elf_cons, 4 }, | |
2818 | { "rel31", s_arm_rel31, 0 }, | |
2819 | { "fnstart", s_arm_unwind_fnstart, 0 }, | |
2820 | { "fnend", s_arm_unwind_fnend, 0 }, | |
2821 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
2822 | { "personality", s_arm_unwind_personality, 0 }, | |
2823 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
2824 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
2825 | { "save", s_arm_unwind_save, 0 }, | |
2826 | { "movsp", s_arm_unwind_movsp, 0 }, | |
2827 | { "pad", s_arm_unwind_pad, 0 }, | |
2828 | { "setfp", s_arm_unwind_setfp, 0 }, | |
2829 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
2830 | #else | |
2831 | { "word", cons, 4}, | |
2832 | #endif | |
2833 | { "extend", float_cons, 'x' }, | |
2834 | { "ldouble", float_cons, 'x' }, | |
2835 | { "packed", float_cons, 'p' }, | |
2836 | { 0, 0, 0 } | |
2837 | }; | |
2838 | \f | |
2839 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 2840 | |
c19d1205 ZW |
2841 | /* Generic immediate-value read function for use in insn parsing. |
2842 | STR points to the beginning of the immediate (the leading #); | |
2843 | VAL receives the value; if the value is outside [MIN, MAX] | |
2844 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
2845 | optional. */ | |
b99bd4ef | 2846 | |
c19d1205 ZW |
2847 | static int |
2848 | parse_immediate (char **str, int *val, int min, int max, | |
2849 | bfd_boolean prefix_opt) | |
2850 | { | |
2851 | expressionS exp; | |
2852 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
2853 | if (exp.X_op != O_constant) | |
b99bd4ef | 2854 | { |
c19d1205 ZW |
2855 | inst.error = _("constant expression required"); |
2856 | return FAIL; | |
2857 | } | |
b99bd4ef | 2858 | |
c19d1205 ZW |
2859 | if (exp.X_add_number < min || exp.X_add_number > max) |
2860 | { | |
2861 | inst.error = _("immediate value out of range"); | |
2862 | return FAIL; | |
2863 | } | |
b99bd4ef | 2864 | |
c19d1205 ZW |
2865 | *val = exp.X_add_number; |
2866 | return SUCCESS; | |
2867 | } | |
b99bd4ef | 2868 | |
c19d1205 ZW |
2869 | /* Returns the pseudo-register number of an FPA immediate constant, |
2870 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 2871 | |
c19d1205 ZW |
2872 | static int |
2873 | parse_fpa_immediate (char ** str) | |
2874 | { | |
2875 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2876 | char * save_in; | |
2877 | expressionS exp; | |
2878 | int i; | |
2879 | int j; | |
b99bd4ef | 2880 | |
c19d1205 ZW |
2881 | /* First try and match exact strings, this is to guarantee |
2882 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 2883 | |
c19d1205 ZW |
2884 | for (i = 0; fp_const[i]; i++) |
2885 | { | |
2886 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 2887 | { |
c19d1205 | 2888 | char *start = *str; |
b99bd4ef | 2889 | |
c19d1205 ZW |
2890 | *str += strlen (fp_const[i]); |
2891 | if (is_end_of_line[(unsigned char) **str]) | |
2892 | return i + 8; | |
2893 | *str = start; | |
2894 | } | |
2895 | } | |
b99bd4ef | 2896 | |
c19d1205 ZW |
2897 | /* Just because we didn't get a match doesn't mean that the constant |
2898 | isn't valid, just that it is in a format that we don't | |
2899 | automatically recognize. Try parsing it with the standard | |
2900 | expression routines. */ | |
b99bd4ef | 2901 | |
c19d1205 | 2902 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 2903 | |
c19d1205 ZW |
2904 | /* Look for a raw floating point number. */ |
2905 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
2906 | && is_end_of_line[(unsigned char) *save_in]) | |
2907 | { | |
2908 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
2909 | { | |
2910 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 2911 | { |
c19d1205 ZW |
2912 | if (words[j] != fp_values[i][j]) |
2913 | break; | |
b99bd4ef NC |
2914 | } |
2915 | ||
c19d1205 | 2916 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 2917 | { |
c19d1205 ZW |
2918 | *str = save_in; |
2919 | return i + 8; | |
b99bd4ef NC |
2920 | } |
2921 | } | |
2922 | } | |
b99bd4ef | 2923 | |
c19d1205 ZW |
2924 | /* Try and parse a more complex expression, this will probably fail |
2925 | unless the code uses a floating point prefix (eg "0f"). */ | |
2926 | save_in = input_line_pointer; | |
2927 | input_line_pointer = *str; | |
2928 | if (expression (&exp) == absolute_section | |
2929 | && exp.X_op == O_big | |
2930 | && exp.X_add_number < 0) | |
2931 | { | |
2932 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
2933 | Ditto for 15. */ | |
2934 | if (gen_to_words (words, 5, (long) 15) == 0) | |
2935 | { | |
2936 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
2937 | { | |
2938 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
2939 | { | |
2940 | if (words[j] != fp_values[i][j]) | |
2941 | break; | |
2942 | } | |
b99bd4ef | 2943 | |
c19d1205 ZW |
2944 | if (j == MAX_LITTLENUMS) |
2945 | { | |
2946 | *str = input_line_pointer; | |
2947 | input_line_pointer = save_in; | |
2948 | return i + 8; | |
2949 | } | |
2950 | } | |
2951 | } | |
b99bd4ef NC |
2952 | } |
2953 | ||
c19d1205 ZW |
2954 | *str = input_line_pointer; |
2955 | input_line_pointer = save_in; | |
2956 | inst.error = _("invalid FPA immediate expression"); | |
2957 | return FAIL; | |
b99bd4ef NC |
2958 | } |
2959 | ||
c19d1205 ZW |
2960 | /* Shift operands. */ |
2961 | enum shift_kind | |
b99bd4ef | 2962 | { |
c19d1205 ZW |
2963 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
2964 | }; | |
b99bd4ef | 2965 | |
c19d1205 ZW |
2966 | struct asm_shift_name |
2967 | { | |
2968 | const char *name; | |
2969 | enum shift_kind kind; | |
2970 | }; | |
b99bd4ef | 2971 | |
c19d1205 ZW |
2972 | /* Third argument to parse_shift. */ |
2973 | enum parse_shift_mode | |
2974 | { | |
2975 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
2976 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
2977 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
2978 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
2979 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
2980 | }; | |
b99bd4ef | 2981 | |
c19d1205 ZW |
2982 | /* Parse a <shift> specifier on an ARM data processing instruction. |
2983 | This has three forms: | |
b99bd4ef | 2984 | |
c19d1205 ZW |
2985 | (LSL|LSR|ASL|ASR|ROR) Rs |
2986 | (LSL|LSR|ASL|ASR|ROR) #imm | |
2987 | RRX | |
b99bd4ef | 2988 | |
c19d1205 ZW |
2989 | Note that ASL is assimilated to LSL in the instruction encoding, and |
2990 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 2991 | |
c19d1205 ZW |
2992 | static int |
2993 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 2994 | { |
c19d1205 ZW |
2995 | const struct asm_shift_name *shift_name; |
2996 | enum shift_kind shift; | |
2997 | char *s = *str; | |
2998 | char *p = s; | |
2999 | int reg; | |
b99bd4ef | 3000 | |
c19d1205 ZW |
3001 | for (p = *str; ISALPHA (*p); p++) |
3002 | ; | |
b99bd4ef | 3003 | |
c19d1205 | 3004 | if (p == *str) |
b99bd4ef | 3005 | { |
c19d1205 ZW |
3006 | inst.error = _("shift expression expected"); |
3007 | return FAIL; | |
b99bd4ef NC |
3008 | } |
3009 | ||
c19d1205 ZW |
3010 | shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); |
3011 | ||
3012 | if (shift_name == NULL) | |
b99bd4ef | 3013 | { |
c19d1205 ZW |
3014 | inst.error = _("shift expression expected"); |
3015 | return FAIL; | |
b99bd4ef NC |
3016 | } |
3017 | ||
c19d1205 | 3018 | shift = shift_name->kind; |
b99bd4ef | 3019 | |
c19d1205 ZW |
3020 | switch (mode) |
3021 | { | |
3022 | case NO_SHIFT_RESTRICT: | |
3023 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 3024 | |
c19d1205 ZW |
3025 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
3026 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
3027 | { | |
3028 | inst.error = _("'LSL' or 'ASR' required"); | |
3029 | return FAIL; | |
3030 | } | |
3031 | break; | |
b99bd4ef | 3032 | |
c19d1205 ZW |
3033 | case SHIFT_LSL_IMMEDIATE: |
3034 | if (shift != SHIFT_LSL) | |
3035 | { | |
3036 | inst.error = _("'LSL' required"); | |
3037 | return FAIL; | |
3038 | } | |
3039 | break; | |
b99bd4ef | 3040 | |
c19d1205 ZW |
3041 | case SHIFT_ASR_IMMEDIATE: |
3042 | if (shift != SHIFT_ASR) | |
3043 | { | |
3044 | inst.error = _("'ASR' required"); | |
3045 | return FAIL; | |
3046 | } | |
3047 | break; | |
b99bd4ef | 3048 | |
c19d1205 ZW |
3049 | default: abort (); |
3050 | } | |
b99bd4ef | 3051 | |
c19d1205 ZW |
3052 | if (shift != SHIFT_RRX) |
3053 | { | |
3054 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
3055 | skip_whitespace (p); | |
b99bd4ef | 3056 | |
c19d1205 ZW |
3057 | if (mode == NO_SHIFT_RESTRICT |
3058 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
3059 | { | |
3060 | inst.operands[i].imm = reg; | |
3061 | inst.operands[i].immisreg = 1; | |
3062 | } | |
3063 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3064 | return FAIL; | |
3065 | } | |
3066 | inst.operands[i].shift_kind = shift; | |
3067 | inst.operands[i].shifted = 1; | |
3068 | *str = p; | |
3069 | return SUCCESS; | |
b99bd4ef NC |
3070 | } |
3071 | ||
c19d1205 | 3072 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 3073 | |
c19d1205 ZW |
3074 | #<immediate> |
3075 | #<immediate>, <rotate> | |
3076 | <Rm> | |
3077 | <Rm>, <shift> | |
b99bd4ef | 3078 | |
c19d1205 ZW |
3079 | where <shift> is defined by parse_shift above, and <rotate> is a |
3080 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 3081 | is deferred to md_apply_fix. */ |
b99bd4ef | 3082 | |
c19d1205 ZW |
3083 | static int |
3084 | parse_shifter_operand (char **str, int i) | |
3085 | { | |
3086 | int value; | |
3087 | expressionS expr; | |
b99bd4ef | 3088 | |
c19d1205 ZW |
3089 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
3090 | { | |
3091 | inst.operands[i].reg = value; | |
3092 | inst.operands[i].isreg = 1; | |
b99bd4ef | 3093 | |
c19d1205 ZW |
3094 | /* parse_shift will override this if appropriate */ |
3095 | inst.reloc.exp.X_op = O_constant; | |
3096 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 3097 | |
c19d1205 ZW |
3098 | if (skip_past_comma (str) == FAIL) |
3099 | return SUCCESS; | |
b99bd4ef | 3100 | |
c19d1205 ZW |
3101 | /* Shift operation on register. */ |
3102 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
3103 | } |
3104 | ||
c19d1205 ZW |
3105 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
3106 | return FAIL; | |
b99bd4ef | 3107 | |
c19d1205 | 3108 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 3109 | { |
c19d1205 ZW |
3110 | /* #x, y -- ie explicit rotation by Y. */ |
3111 | if (my_get_expression (&expr, str, GE_NO_PREFIX)) | |
3112 | return FAIL; | |
b99bd4ef | 3113 | |
c19d1205 ZW |
3114 | if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
3115 | { | |
3116 | inst.error = _("constant expression expected"); | |
3117 | return FAIL; | |
3118 | } | |
b99bd4ef | 3119 | |
c19d1205 ZW |
3120 | value = expr.X_add_number; |
3121 | if (value < 0 || value > 30 || value % 2 != 0) | |
3122 | { | |
3123 | inst.error = _("invalid rotation"); | |
3124 | return FAIL; | |
3125 | } | |
3126 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
3127 | { | |
3128 | inst.error = _("invalid constant"); | |
3129 | return FAIL; | |
3130 | } | |
09d92015 | 3131 | |
55cf6793 | 3132 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
3133 | inst.reloc.exp.X_add_number |
3134 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
3135 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
3136 | } |
3137 | ||
c19d1205 ZW |
3138 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
3139 | inst.reloc.pc_rel = 0; | |
3140 | return SUCCESS; | |
09d92015 MM |
3141 | } |
3142 | ||
c19d1205 ZW |
3143 | /* Parse all forms of an ARM address expression. Information is written |
3144 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 3145 | |
c19d1205 | 3146 | Preindexed addressing (.preind=1): |
09d92015 | 3147 | |
c19d1205 ZW |
3148 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
3149 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3150 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3151 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3152 | |
c19d1205 | 3153 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 3154 | |
c19d1205 | 3155 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 3156 | |
c19d1205 ZW |
3157 | [Rn], #offset .reg=Rn .reloc.exp=offset |
3158 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3159 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3160 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3161 | |
c19d1205 | 3162 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 3163 | |
c19d1205 | 3164 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 3165 | |
c19d1205 | 3166 | Other: |
09d92015 | 3167 | |
c19d1205 ZW |
3168 | [Rn]{!} shorthand for [Rn,#0]{!} |
3169 | =immediate .isreg=0 .reloc.exp=immediate | |
3170 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 3171 | |
c19d1205 ZW |
3172 | It is the caller's responsibility to check for addressing modes not |
3173 | supported by the instruction, and to set inst.reloc.type. */ | |
3174 | ||
3175 | static int | |
3176 | parse_address (char **str, int i) | |
09d92015 | 3177 | { |
c19d1205 ZW |
3178 | char *p = *str; |
3179 | int reg; | |
09d92015 | 3180 | |
c19d1205 | 3181 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 3182 | { |
c19d1205 ZW |
3183 | if (skip_past_char (&p, '=') == FAIL) |
3184 | { | |
3185 | /* bare address - translate to PC-relative offset */ | |
3186 | inst.reloc.pc_rel = 1; | |
3187 | inst.operands[i].reg = REG_PC; | |
3188 | inst.operands[i].isreg = 1; | |
3189 | inst.operands[i].preind = 1; | |
3190 | } | |
3191 | /* else a load-constant pseudo op, no special treatment needed here */ | |
09d92015 | 3192 | |
c19d1205 ZW |
3193 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
3194 | return FAIL; | |
09d92015 | 3195 | |
c19d1205 ZW |
3196 | *str = p; |
3197 | return SUCCESS; | |
09d92015 MM |
3198 | } |
3199 | ||
c19d1205 | 3200 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 3201 | { |
c19d1205 ZW |
3202 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
3203 | return FAIL; | |
09d92015 | 3204 | } |
c19d1205 ZW |
3205 | inst.operands[i].reg = reg; |
3206 | inst.operands[i].isreg = 1; | |
09d92015 | 3207 | |
c19d1205 | 3208 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3209 | { |
c19d1205 | 3210 | inst.operands[i].preind = 1; |
09d92015 | 3211 | |
c19d1205 ZW |
3212 | if (*p == '+') p++; |
3213 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
3214 | ||
3215 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
09d92015 | 3216 | { |
c19d1205 ZW |
3217 | inst.operands[i].imm = reg; |
3218 | inst.operands[i].immisreg = 1; | |
3219 | ||
3220 | if (skip_past_comma (&p) == SUCCESS) | |
3221 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3222 | return FAIL; | |
3223 | } | |
3224 | else | |
3225 | { | |
3226 | if (inst.operands[i].negative) | |
3227 | { | |
3228 | inst.operands[i].negative = 0; | |
3229 | p--; | |
3230 | } | |
3231 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3232 | return FAIL; | |
09d92015 MM |
3233 | } |
3234 | } | |
3235 | ||
c19d1205 | 3236 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 3237 | { |
c19d1205 ZW |
3238 | inst.error = _("']' expected"); |
3239 | return FAIL; | |
09d92015 MM |
3240 | } |
3241 | ||
c19d1205 ZW |
3242 | if (skip_past_char (&p, '!') == SUCCESS) |
3243 | inst.operands[i].writeback = 1; | |
09d92015 | 3244 | |
c19d1205 | 3245 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3246 | { |
c19d1205 ZW |
3247 | if (skip_past_char (&p, '{') == SUCCESS) |
3248 | { | |
3249 | /* [Rn], {expr} - unindexed, with option */ | |
3250 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 3251 | 0, 255, TRUE) == FAIL) |
c19d1205 | 3252 | return FAIL; |
09d92015 | 3253 | |
c19d1205 ZW |
3254 | if (skip_past_char (&p, '}') == FAIL) |
3255 | { | |
3256 | inst.error = _("'}' expected at end of 'option' field"); | |
3257 | return FAIL; | |
3258 | } | |
3259 | if (inst.operands[i].preind) | |
3260 | { | |
3261 | inst.error = _("cannot combine index with option"); | |
3262 | return FAIL; | |
3263 | } | |
3264 | *str = p; | |
3265 | return SUCCESS; | |
09d92015 | 3266 | } |
c19d1205 ZW |
3267 | else |
3268 | { | |
3269 | inst.operands[i].postind = 1; | |
3270 | inst.operands[i].writeback = 1; | |
09d92015 | 3271 | |
c19d1205 ZW |
3272 | if (inst.operands[i].preind) |
3273 | { | |
3274 | inst.error = _("cannot combine pre- and post-indexing"); | |
3275 | return FAIL; | |
3276 | } | |
09d92015 | 3277 | |
c19d1205 ZW |
3278 | if (*p == '+') p++; |
3279 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 3280 | |
c19d1205 ZW |
3281 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
3282 | { | |
3283 | inst.operands[i].imm = reg; | |
3284 | inst.operands[i].immisreg = 1; | |
a737bd4d | 3285 | |
c19d1205 ZW |
3286 | if (skip_past_comma (&p) == SUCCESS) |
3287 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3288 | return FAIL; | |
3289 | } | |
3290 | else | |
3291 | { | |
3292 | if (inst.operands[i].negative) | |
3293 | { | |
3294 | inst.operands[i].negative = 0; | |
3295 | p--; | |
3296 | } | |
3297 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3298 | return FAIL; | |
3299 | } | |
3300 | } | |
a737bd4d NC |
3301 | } |
3302 | ||
c19d1205 ZW |
3303 | /* If at this point neither .preind nor .postind is set, we have a |
3304 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
3305 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
3306 | { | |
3307 | inst.operands[i].preind = 1; | |
3308 | inst.reloc.exp.X_op = O_constant; | |
3309 | inst.reloc.exp.X_add_number = 0; | |
3310 | } | |
3311 | *str = p; | |
3312 | return SUCCESS; | |
a737bd4d NC |
3313 | } |
3314 | ||
c19d1205 | 3315 | /* Miscellaneous. */ |
a737bd4d | 3316 | |
c19d1205 ZW |
3317 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
3318 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
3319 | static int | |
3320 | parse_psr (char **str) | |
09d92015 | 3321 | { |
c19d1205 ZW |
3322 | char *p; |
3323 | unsigned long psr_field; | |
09d92015 | 3324 | |
c19d1205 ZW |
3325 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
3326 | feature for ease of use and backwards compatibility. */ | |
3327 | p = *str; | |
3328 | if (*p == 's' || *p == 'S') | |
3329 | psr_field = SPSR_BIT; | |
3330 | else if (*p == 'c' || *p == 'C') | |
3331 | psr_field = 0; | |
3332 | else | |
3333 | goto error; | |
09d92015 | 3334 | |
c19d1205 ZW |
3335 | p++; |
3336 | if (strncasecmp (p, "PSR", 3) != 0) | |
3337 | goto error; | |
3338 | p += 3; | |
09d92015 | 3339 | |
c19d1205 ZW |
3340 | if (*p == '_') |
3341 | { | |
3342 | /* A suffix follows. */ | |
3343 | const struct asm_psr *psr; | |
3344 | char *start; | |
a737bd4d | 3345 | |
c19d1205 ZW |
3346 | p++; |
3347 | start = p; | |
a737bd4d | 3348 | |
c19d1205 ZW |
3349 | do |
3350 | p++; | |
3351 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 3352 | |
c19d1205 ZW |
3353 | psr = hash_find_n (arm_psr_hsh, start, p - start); |
3354 | if (!psr) | |
3355 | goto error; | |
a737bd4d | 3356 | |
c19d1205 | 3357 | psr_field |= psr->field; |
a737bd4d | 3358 | } |
c19d1205 | 3359 | else |
a737bd4d | 3360 | { |
c19d1205 ZW |
3361 | if (ISALNUM (*p)) |
3362 | goto error; /* Garbage after "[CS]PSR". */ | |
3363 | ||
3364 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 3365 | } |
c19d1205 ZW |
3366 | *str = p; |
3367 | return psr_field; | |
a737bd4d | 3368 | |
c19d1205 ZW |
3369 | error: |
3370 | inst.error = _("flag for {c}psr instruction expected"); | |
3371 | return FAIL; | |
a737bd4d NC |
3372 | } |
3373 | ||
c19d1205 ZW |
3374 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
3375 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 3376 | |
c19d1205 ZW |
3377 | static int |
3378 | parse_cps_flags (char **str) | |
a737bd4d | 3379 | { |
c19d1205 ZW |
3380 | int val = 0; |
3381 | int saw_a_flag = 0; | |
3382 | char *s = *str; | |
a737bd4d | 3383 | |
c19d1205 ZW |
3384 | for (;;) |
3385 | switch (*s++) | |
3386 | { | |
3387 | case '\0': case ',': | |
3388 | goto done; | |
a737bd4d | 3389 | |
c19d1205 ZW |
3390 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
3391 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
3392 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 3393 | |
c19d1205 ZW |
3394 | default: |
3395 | inst.error = _("unrecognized CPS flag"); | |
3396 | return FAIL; | |
3397 | } | |
a737bd4d | 3398 | |
c19d1205 ZW |
3399 | done: |
3400 | if (saw_a_flag == 0) | |
a737bd4d | 3401 | { |
c19d1205 ZW |
3402 | inst.error = _("missing CPS flags"); |
3403 | return FAIL; | |
a737bd4d | 3404 | } |
a737bd4d | 3405 | |
c19d1205 ZW |
3406 | *str = s - 1; |
3407 | return val; | |
a737bd4d NC |
3408 | } |
3409 | ||
c19d1205 ZW |
3410 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
3411 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
3412 | |
3413 | static int | |
c19d1205 | 3414 | parse_endian_specifier (char **str) |
a737bd4d | 3415 | { |
c19d1205 ZW |
3416 | int little_endian; |
3417 | char *s = *str; | |
a737bd4d | 3418 | |
c19d1205 ZW |
3419 | if (strncasecmp (s, "BE", 2)) |
3420 | little_endian = 0; | |
3421 | else if (strncasecmp (s, "LE", 2)) | |
3422 | little_endian = 1; | |
3423 | else | |
a737bd4d | 3424 | { |
c19d1205 | 3425 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3426 | return FAIL; |
3427 | } | |
3428 | ||
c19d1205 | 3429 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 3430 | { |
c19d1205 | 3431 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3432 | return FAIL; |
3433 | } | |
3434 | ||
c19d1205 ZW |
3435 | *str = s + 2; |
3436 | return little_endian; | |
3437 | } | |
a737bd4d | 3438 | |
c19d1205 ZW |
3439 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
3440 | value suitable for poking into the rotate field of an sxt or sxta | |
3441 | instruction, or FAIL on error. */ | |
3442 | ||
3443 | static int | |
3444 | parse_ror (char **str) | |
3445 | { | |
3446 | int rot; | |
3447 | char *s = *str; | |
3448 | ||
3449 | if (strncasecmp (s, "ROR", 3) == 0) | |
3450 | s += 3; | |
3451 | else | |
a737bd4d | 3452 | { |
c19d1205 | 3453 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
3454 | return FAIL; |
3455 | } | |
c19d1205 ZW |
3456 | |
3457 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
3458 | return FAIL; | |
3459 | ||
3460 | switch (rot) | |
a737bd4d | 3461 | { |
c19d1205 ZW |
3462 | case 0: *str = s; return 0x0; |
3463 | case 8: *str = s; return 0x1; | |
3464 | case 16: *str = s; return 0x2; | |
3465 | case 24: *str = s; return 0x3; | |
3466 | ||
3467 | default: | |
3468 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
3469 | return FAIL; |
3470 | } | |
c19d1205 | 3471 | } |
a737bd4d | 3472 | |
c19d1205 ZW |
3473 | /* Parse a conditional code (from conds[] below). The value returned is in the |
3474 | range 0 .. 14, or FAIL. */ | |
3475 | static int | |
3476 | parse_cond (char **str) | |
3477 | { | |
3478 | char *p, *q; | |
3479 | const struct asm_cond *c; | |
a737bd4d | 3480 | |
c19d1205 ZW |
3481 | p = q = *str; |
3482 | while (ISALPHA (*q)) | |
3483 | q++; | |
a737bd4d | 3484 | |
c19d1205 ZW |
3485 | c = hash_find_n (arm_cond_hsh, p, q - p); |
3486 | if (!c) | |
a737bd4d | 3487 | { |
c19d1205 | 3488 | inst.error = _("condition required"); |
a737bd4d NC |
3489 | return FAIL; |
3490 | } | |
3491 | ||
c19d1205 ZW |
3492 | *str = q; |
3493 | return c->value; | |
3494 | } | |
3495 | ||
92e90b6e PB |
3496 | /* Parse the operands of a table branch instruction. Similar to a memory |
3497 | operand. */ | |
3498 | static int | |
3499 | parse_tb (char **str) | |
3500 | { | |
3501 | char * p = *str; | |
3502 | int reg; | |
3503 | ||
3504 | if (skip_past_char (&p, '[') == FAIL) | |
3505 | return FAIL; | |
3506 | ||
3507 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3508 | { | |
3509 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3510 | return FAIL; | |
3511 | } | |
3512 | inst.operands[0].reg = reg; | |
3513 | ||
3514 | if (skip_past_comma (&p) == FAIL) | |
3515 | return FAIL; | |
3516 | ||
3517 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3518 | { | |
3519 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3520 | return FAIL; | |
3521 | } | |
3522 | inst.operands[0].imm = reg; | |
3523 | ||
3524 | if (skip_past_comma (&p) == SUCCESS) | |
3525 | { | |
3526 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
3527 | return FAIL; | |
3528 | if (inst.reloc.exp.X_add_number != 1) | |
3529 | { | |
3530 | inst.error = _("invalid shift"); | |
3531 | return FAIL; | |
3532 | } | |
3533 | inst.operands[0].shifted = 1; | |
3534 | } | |
3535 | ||
3536 | if (skip_past_char (&p, ']') == FAIL) | |
3537 | { | |
3538 | inst.error = _("']' expected"); | |
3539 | return FAIL; | |
3540 | } | |
3541 | *str = p; | |
3542 | return SUCCESS; | |
3543 | } | |
3544 | ||
c19d1205 ZW |
3545 | /* Matcher codes for parse_operands. */ |
3546 | enum operand_parse_code | |
3547 | { | |
3548 | OP_stop, /* end of line */ | |
3549 | ||
3550 | OP_RR, /* ARM register */ | |
3551 | OP_RRnpc, /* ARM register, not r15 */ | |
3552 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ | |
3553 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
3554 | OP_RCP, /* Coprocessor number */ | |
3555 | OP_RCN, /* Coprocessor register */ | |
3556 | OP_RF, /* FPA register */ | |
3557 | OP_RVS, /* VFP single precision register */ | |
3558 | OP_RVD, /* VFP double precision register */ | |
3559 | OP_RVC, /* VFP control register */ | |
3560 | OP_RMF, /* Maverick F register */ | |
3561 | OP_RMD, /* Maverick D register */ | |
3562 | OP_RMFX, /* Maverick FX register */ | |
3563 | OP_RMDX, /* Maverick DX register */ | |
3564 | OP_RMAX, /* Maverick AX register */ | |
3565 | OP_RMDS, /* Maverick DSPSC register */ | |
3566 | OP_RIWR, /* iWMMXt wR register */ | |
3567 | OP_RIWC, /* iWMMXt wC register */ | |
3568 | OP_RIWG, /* iWMMXt wCG register */ | |
3569 | OP_RXA, /* XScale accumulator register */ | |
3570 | ||
3571 | OP_REGLST, /* ARM register list */ | |
3572 | OP_VRSLST, /* VFP single-precision register list */ | |
3573 | OP_VRDLST, /* VFP double-precision register list */ | |
3574 | ||
3575 | OP_I7, /* immediate value 0 .. 7 */ | |
3576 | OP_I15, /* 0 .. 15 */ | |
3577 | OP_I16, /* 1 .. 16 */ | |
3578 | OP_I31, /* 0 .. 31 */ | |
3579 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
3580 | OP_I32, /* 1 .. 32 */ | |
3581 | OP_I63s, /* -64 .. 63 */ | |
3582 | OP_I255, /* 0 .. 255 */ | |
3583 | OP_Iffff, /* 0 .. 65535 */ | |
3584 | ||
3585 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
3586 | OP_I7b, /* 0 .. 7 */ | |
3587 | OP_I15b, /* 0 .. 15 */ | |
3588 | OP_I31b, /* 0 .. 31 */ | |
3589 | ||
3590 | OP_SH, /* shifter operand */ | |
3591 | OP_ADDR, /* Memory address expression (any mode) */ | |
3592 | OP_EXP, /* arbitrary expression */ | |
3593 | OP_EXPi, /* same, with optional immediate prefix */ | |
3594 | OP_EXPr, /* same, with optional relocation suffix */ | |
3595 | ||
3596 | OP_CPSF, /* CPS flags */ | |
3597 | OP_ENDI, /* Endianness specifier */ | |
3598 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
3599 | OP_COND, /* conditional code */ | |
92e90b6e | 3600 | OP_TB, /* Table branch. */ |
c19d1205 ZW |
3601 | |
3602 | OP_RRnpc_I0, /* ARM register or literal 0 */ | |
3603 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
3604 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
3605 | OP_RF_IF, /* FPA register or immediate */ | |
3606 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
3607 | ||
3608 | /* Optional operands. */ | |
3609 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
3610 | OP_oI31b, /* 0 .. 31 */ | |
3611 | OP_oIffffb, /* 0 .. 65535 */ | |
3612 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
3613 | ||
3614 | OP_oRR, /* ARM register */ | |
3615 | OP_oRRnpc, /* ARM register, not the PC */ | |
3616 | OP_oSHll, /* LSL immediate */ | |
3617 | OP_oSHar, /* ASR immediate */ | |
3618 | OP_oSHllar, /* LSL or ASR immediate */ | |
3619 | OP_oROR, /* ROR 0/8/16/24 */ | |
3620 | ||
3621 | OP_FIRST_OPTIONAL = OP_oI7b | |
3622 | }; | |
a737bd4d | 3623 | |
c19d1205 ZW |
3624 | /* Generic instruction operand parser. This does no encoding and no |
3625 | semantic validation; it merely squirrels values away in the inst | |
3626 | structure. Returns SUCCESS or FAIL depending on whether the | |
3627 | specified grammar matched. */ | |
3628 | static int | |
ca3f61f7 | 3629 | parse_operands (char *str, const unsigned char *pattern) |
c19d1205 ZW |
3630 | { |
3631 | unsigned const char *upat = pattern; | |
3632 | char *backtrack_pos = 0; | |
3633 | const char *backtrack_error = 0; | |
3634 | int i, val, backtrack_index = 0; | |
3635 | ||
3636 | #define po_char_or_fail(chr) do { \ | |
3637 | if (skip_past_char (&str, chr) == FAIL) \ | |
3638 | goto bad_args; \ | |
3639 | } while (0) | |
3640 | ||
3641 | #define po_reg_or_fail(regtype) do { \ | |
3642 | val = arm_reg_parse (&str, regtype); \ | |
3643 | if (val == FAIL) \ | |
3644 | { \ | |
3645 | inst.error = _(reg_expected_msgs[regtype]); \ | |
3646 | goto failure; \ | |
3647 | } \ | |
3648 | inst.operands[i].reg = val; \ | |
3649 | inst.operands[i].isreg = 1; \ | |
3650 | } while (0) | |
3651 | ||
3652 | #define po_reg_or_goto(regtype, label) do { \ | |
3653 | val = arm_reg_parse (&str, regtype); \ | |
3654 | if (val == FAIL) \ | |
3655 | goto label; \ | |
3656 | \ | |
3657 | inst.operands[i].reg = val; \ | |
3658 | inst.operands[i].isreg = 1; \ | |
3659 | } while (0) | |
3660 | ||
3661 | #define po_imm_or_fail(min, max, popt) do { \ | |
3662 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
3663 | goto failure; \ | |
3664 | inst.operands[i].imm = val; \ | |
3665 | } while (0) | |
3666 | ||
3667 | #define po_misc_or_fail(expr) do { \ | |
3668 | if (expr) \ | |
3669 | goto failure; \ | |
3670 | } while (0) | |
3671 | ||
3672 | skip_whitespace (str); | |
3673 | ||
3674 | for (i = 0; upat[i] != OP_stop; i++) | |
3675 | { | |
3676 | if (upat[i] >= OP_FIRST_OPTIONAL) | |
3677 | { | |
3678 | /* Remember where we are in case we need to backtrack. */ | |
3679 | assert (!backtrack_pos); | |
3680 | backtrack_pos = str; | |
3681 | backtrack_error = inst.error; | |
3682 | backtrack_index = i; | |
3683 | } | |
3684 | ||
3685 | if (i > 0) | |
3686 | po_char_or_fail (','); | |
3687 | ||
3688 | switch (upat[i]) | |
3689 | { | |
3690 | /* Registers */ | |
3691 | case OP_oRRnpc: | |
3692 | case OP_RRnpc: | |
3693 | case OP_oRR: | |
3694 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
3695 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
3696 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
3697 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
3698 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
3699 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
3700 | case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break; | |
3701 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; | |
3702 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
3703 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
3704 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
3705 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
3706 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
3707 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
3708 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
3709 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
3710 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
3711 | ||
3712 | case OP_RRnpcb: | |
3713 | po_char_or_fail ('['); | |
3714 | po_reg_or_fail (REG_TYPE_RN); | |
3715 | po_char_or_fail (']'); | |
3716 | break; | |
a737bd4d | 3717 | |
c19d1205 ZW |
3718 | case OP_RRw: |
3719 | po_reg_or_fail (REG_TYPE_RN); | |
3720 | if (skip_past_char (&str, '!') == SUCCESS) | |
3721 | inst.operands[i].writeback = 1; | |
3722 | break; | |
3723 | ||
3724 | /* Immediates */ | |
3725 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
3726 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
3727 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
3728 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; | |
3729 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
3730 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; | |
3731 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; | |
3732 | case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break; | |
3733 | ||
3734 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
3735 | case OP_oI7b: | |
3736 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
3737 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
3738 | case OP_oI31b: | |
3739 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
3740 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; | |
3741 | ||
3742 | /* Immediate variants */ | |
3743 | case OP_oI255c: | |
3744 | po_char_or_fail ('{'); | |
3745 | po_imm_or_fail (0, 255, TRUE); | |
3746 | po_char_or_fail ('}'); | |
3747 | break; | |
3748 | ||
3749 | case OP_I31w: | |
3750 | /* The expression parser chokes on a trailing !, so we have | |
3751 | to find it first and zap it. */ | |
3752 | { | |
3753 | char *s = str; | |
3754 | while (*s && *s != ',') | |
3755 | s++; | |
3756 | if (s[-1] == '!') | |
3757 | { | |
3758 | s[-1] = '\0'; | |
3759 | inst.operands[i].writeback = 1; | |
3760 | } | |
3761 | po_imm_or_fail (0, 31, TRUE); | |
3762 | if (str == s - 1) | |
3763 | str = s; | |
3764 | } | |
3765 | break; | |
3766 | ||
3767 | /* Expressions */ | |
3768 | case OP_EXPi: EXPi: | |
3769 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3770 | GE_OPT_PREFIX)); | |
3771 | break; | |
3772 | ||
3773 | case OP_EXP: | |
3774 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3775 | GE_NO_PREFIX)); | |
3776 | break; | |
3777 | ||
3778 | case OP_EXPr: EXPr: | |
3779 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3780 | GE_NO_PREFIX)); | |
3781 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 3782 | { |
c19d1205 ZW |
3783 | val = parse_reloc (&str); |
3784 | if (val == -1) | |
3785 | { | |
3786 | inst.error = _("unrecognized relocation suffix"); | |
3787 | goto failure; | |
3788 | } | |
3789 | else if (val != BFD_RELOC_UNUSED) | |
3790 | { | |
3791 | inst.operands[i].imm = val; | |
3792 | inst.operands[i].hasreloc = 1; | |
3793 | } | |
a737bd4d | 3794 | } |
c19d1205 | 3795 | break; |
a737bd4d | 3796 | |
c19d1205 ZW |
3797 | /* Register or expression */ |
3798 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; | |
3799 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 3800 | |
c19d1205 ZW |
3801 | /* Register or immediate */ |
3802 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; | |
3803 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 3804 | |
c19d1205 ZW |
3805 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
3806 | IF: | |
3807 | if (!is_immediate_prefix (*str)) | |
3808 | goto bad_args; | |
3809 | str++; | |
3810 | val = parse_fpa_immediate (&str); | |
3811 | if (val == FAIL) | |
3812 | goto failure; | |
3813 | /* FPA immediates are encoded as registers 8-15. | |
3814 | parse_fpa_immediate has already applied the offset. */ | |
3815 | inst.operands[i].reg = val; | |
3816 | inst.operands[i].isreg = 1; | |
3817 | break; | |
09d92015 | 3818 | |
c19d1205 ZW |
3819 | /* Two kinds of register */ |
3820 | case OP_RIWR_RIWC: | |
3821 | { | |
3822 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
3823 | if (rege->type != REG_TYPE_MMXWR | |
3824 | && rege->type != REG_TYPE_MMXWC | |
3825 | && rege->type != REG_TYPE_MMXWCG) | |
3826 | { | |
3827 | inst.error = _("iWMMXt data or control register expected"); | |
3828 | goto failure; | |
3829 | } | |
3830 | inst.operands[i].reg = rege->number; | |
3831 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
3832 | } | |
3833 | break; | |
09d92015 | 3834 | |
c19d1205 ZW |
3835 | /* Misc */ |
3836 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
3837 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
3838 | case OP_oROR: val = parse_ror (&str); break; | |
3839 | case OP_PSR: val = parse_psr (&str); break; | |
3840 | case OP_COND: val = parse_cond (&str); break; | |
3841 | ||
92e90b6e PB |
3842 | case OP_TB: |
3843 | po_misc_or_fail (parse_tb (&str)); | |
3844 | break; | |
3845 | ||
c19d1205 ZW |
3846 | /* Register lists */ |
3847 | case OP_REGLST: | |
3848 | val = parse_reg_list (&str); | |
3849 | if (*str == '^') | |
3850 | { | |
3851 | inst.operands[1].writeback = 1; | |
3852 | str++; | |
3853 | } | |
3854 | break; | |
09d92015 | 3855 | |
c19d1205 ZW |
3856 | case OP_VRSLST: |
3857 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0); | |
3858 | break; | |
09d92015 | 3859 | |
c19d1205 ZW |
3860 | case OP_VRDLST: |
3861 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1); | |
3862 | break; | |
a737bd4d | 3863 | |
c19d1205 ZW |
3864 | /* Addressing modes */ |
3865 | case OP_ADDR: | |
3866 | po_misc_or_fail (parse_address (&str, i)); | |
3867 | break; | |
09d92015 | 3868 | |
c19d1205 ZW |
3869 | case OP_SH: |
3870 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
3871 | break; | |
09d92015 | 3872 | |
c19d1205 ZW |
3873 | case OP_oSHll: |
3874 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
3875 | break; | |
09d92015 | 3876 | |
c19d1205 ZW |
3877 | case OP_oSHar: |
3878 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
3879 | break; | |
09d92015 | 3880 | |
c19d1205 ZW |
3881 | case OP_oSHllar: |
3882 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
3883 | break; | |
09d92015 | 3884 | |
c19d1205 ZW |
3885 | default: |
3886 | as_fatal ("unhandled operand code %d", upat[i]); | |
3887 | } | |
09d92015 | 3888 | |
c19d1205 ZW |
3889 | /* Various value-based sanity checks and shared operations. We |
3890 | do not signal immediate failures for the register constraints; | |
3891 | this allows a syntax error to take precedence. */ | |
3892 | switch (upat[i]) | |
3893 | { | |
3894 | case OP_oRRnpc: | |
3895 | case OP_RRnpc: | |
3896 | case OP_RRnpcb: | |
3897 | case OP_RRw: | |
3898 | case OP_RRnpc_I0: | |
3899 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
3900 | inst.error = BAD_PC; | |
3901 | break; | |
09d92015 | 3902 | |
c19d1205 ZW |
3903 | case OP_CPSF: |
3904 | case OP_ENDI: | |
3905 | case OP_oROR: | |
3906 | case OP_PSR: | |
3907 | case OP_COND: | |
3908 | case OP_REGLST: | |
3909 | case OP_VRSLST: | |
3910 | case OP_VRDLST: | |
3911 | if (val == FAIL) | |
3912 | goto failure; | |
3913 | inst.operands[i].imm = val; | |
3914 | break; | |
a737bd4d | 3915 | |
c19d1205 ZW |
3916 | default: |
3917 | break; | |
3918 | } | |
09d92015 | 3919 | |
c19d1205 ZW |
3920 | /* If we get here, this operand was successfully parsed. */ |
3921 | inst.operands[i].present = 1; | |
3922 | continue; | |
09d92015 | 3923 | |
c19d1205 | 3924 | bad_args: |
09d92015 | 3925 | inst.error = BAD_ARGS; |
c19d1205 ZW |
3926 | |
3927 | failure: | |
3928 | if (!backtrack_pos) | |
3929 | return FAIL; | |
3930 | ||
3931 | /* Do not backtrack over a trailing optional argument that | |
3932 | absorbed some text. We will only fail again, with the | |
3933 | 'garbage following instruction' error message, which is | |
3934 | probably less helpful than the current one. */ | |
3935 | if (backtrack_index == i && backtrack_pos != str | |
3936 | && upat[i+1] == OP_stop) | |
3937 | return FAIL; | |
3938 | ||
3939 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
3940 | str = backtrack_pos; | |
3941 | inst.error = backtrack_error; | |
3942 | inst.operands[backtrack_index].present = 0; | |
3943 | i = backtrack_index; | |
3944 | backtrack_pos = 0; | |
09d92015 | 3945 | } |
09d92015 | 3946 | |
c19d1205 ZW |
3947 | /* Check that we have parsed all the arguments. */ |
3948 | if (*str != '\0' && !inst.error) | |
3949 | inst.error = _("garbage following instruction"); | |
09d92015 | 3950 | |
c19d1205 | 3951 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
3952 | } |
3953 | ||
c19d1205 ZW |
3954 | #undef po_char_or_fail |
3955 | #undef po_reg_or_fail | |
3956 | #undef po_reg_or_goto | |
3957 | #undef po_imm_or_fail | |
3958 | \f | |
3959 | /* Shorthand macro for instruction encoding functions issuing errors. */ | |
3960 | #define constraint(expr, err) do { \ | |
3961 | if (expr) \ | |
3962 | { \ | |
3963 | inst.error = err; \ | |
3964 | return; \ | |
3965 | } \ | |
3966 | } while (0) | |
3967 | ||
3968 | /* Functions for operand encoding. ARM, then Thumb. */ | |
3969 | ||
3970 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
3971 | ||
3972 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
3973 | return the encoded form. Otherwise, return FAIL. */ | |
3974 | ||
3975 | static unsigned int | |
3976 | encode_arm_immediate (unsigned int val) | |
09d92015 | 3977 | { |
c19d1205 ZW |
3978 | unsigned int a, i; |
3979 | ||
3980 | for (i = 0; i < 32; i += 2) | |
3981 | if ((a = rotate_left (val, i)) <= 0xff) | |
3982 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
3983 | ||
3984 | return FAIL; | |
09d92015 MM |
3985 | } |
3986 | ||
c19d1205 ZW |
3987 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
3988 | return the encoded form. Otherwise, return FAIL. */ | |
3989 | static unsigned int | |
3990 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 3991 | { |
c19d1205 | 3992 | unsigned int a, i; |
09d92015 | 3993 | |
9c3c69f2 | 3994 | if (val <= 0xff) |
c19d1205 | 3995 | return val; |
a737bd4d | 3996 | |
9c3c69f2 | 3997 | for (i = 1; i <= 24; i++) |
09d92015 | 3998 | { |
9c3c69f2 PB |
3999 | a = val >> i; |
4000 | if ((val & ~(0xff << i)) == 0) | |
4001 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 4002 | } |
a737bd4d | 4003 | |
c19d1205 ZW |
4004 | a = val & 0xff; |
4005 | if (val == ((a << 16) | a)) | |
4006 | return 0x100 | a; | |
4007 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
4008 | return 0x300 | a; | |
09d92015 | 4009 | |
c19d1205 ZW |
4010 | a = val & 0xff00; |
4011 | if (val == ((a << 16) | a)) | |
4012 | return 0x200 | (a >> 8); | |
a737bd4d | 4013 | |
c19d1205 | 4014 | return FAIL; |
09d92015 | 4015 | } |
c19d1205 | 4016 | /* Encode a VFP SP register number into inst.instruction. */ |
09d92015 MM |
4017 | |
4018 | static void | |
c19d1205 | 4019 | encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos) |
09d92015 | 4020 | { |
c19d1205 | 4021 | switch (pos) |
09d92015 | 4022 | { |
c19d1205 ZW |
4023 | case VFP_REG_Sd: |
4024 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
4025 | break; | |
4026 | ||
4027 | case VFP_REG_Sn: | |
4028 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
4029 | break; | |
4030 | ||
4031 | case VFP_REG_Sm: | |
4032 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
4033 | break; | |
4034 | ||
4035 | default: | |
4036 | abort (); | |
09d92015 | 4037 | } |
09d92015 MM |
4038 | } |
4039 | ||
c19d1205 | 4040 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 4041 | if any, is handled by md_apply_fix. */ |
09d92015 | 4042 | static void |
c19d1205 | 4043 | encode_arm_shift (int i) |
09d92015 | 4044 | { |
c19d1205 ZW |
4045 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
4046 | inst.instruction |= SHIFT_ROR << 5; | |
4047 | else | |
09d92015 | 4048 | { |
c19d1205 ZW |
4049 | inst.instruction |= inst.operands[i].shift_kind << 5; |
4050 | if (inst.operands[i].immisreg) | |
4051 | { | |
4052 | inst.instruction |= SHIFT_BY_REG; | |
4053 | inst.instruction |= inst.operands[i].imm << 8; | |
4054 | } | |
4055 | else | |
4056 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 4057 | } |
c19d1205 | 4058 | } |
09d92015 | 4059 | |
c19d1205 ZW |
4060 | static void |
4061 | encode_arm_shifter_operand (int i) | |
4062 | { | |
4063 | if (inst.operands[i].isreg) | |
09d92015 | 4064 | { |
c19d1205 ZW |
4065 | inst.instruction |= inst.operands[i].reg; |
4066 | encode_arm_shift (i); | |
09d92015 | 4067 | } |
c19d1205 ZW |
4068 | else |
4069 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
4070 | } |
4071 | ||
c19d1205 | 4072 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 4073 | static void |
c19d1205 | 4074 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 4075 | { |
c19d1205 ZW |
4076 | assert (inst.operands[i].isreg); |
4077 | inst.instruction |= inst.operands[i].reg << 16; | |
a737bd4d | 4078 | |
c19d1205 | 4079 | if (inst.operands[i].preind) |
09d92015 | 4080 | { |
c19d1205 ZW |
4081 | if (is_t) |
4082 | { | |
4083 | inst.error = _("instruction does not accept preindexed addressing"); | |
4084 | return; | |
4085 | } | |
4086 | inst.instruction |= PRE_INDEX; | |
4087 | if (inst.operands[i].writeback) | |
4088 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4089 | |
c19d1205 ZW |
4090 | } |
4091 | else if (inst.operands[i].postind) | |
4092 | { | |
4093 | assert (inst.operands[i].writeback); | |
4094 | if (is_t) | |
4095 | inst.instruction |= WRITE_BACK; | |
4096 | } | |
4097 | else /* unindexed - only for coprocessor */ | |
09d92015 | 4098 | { |
c19d1205 | 4099 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
4100 | return; |
4101 | } | |
4102 | ||
c19d1205 ZW |
4103 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
4104 | && (((inst.instruction & 0x000f0000) >> 16) | |
4105 | == ((inst.instruction & 0x0000f000) >> 12))) | |
4106 | as_warn ((inst.instruction & LOAD_BIT) | |
4107 | ? _("destination register same as write-back base") | |
4108 | : _("source register same as write-back base")); | |
09d92015 MM |
4109 | } |
4110 | ||
c19d1205 ZW |
4111 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4112 | ARM-format mode 2 load or store instruction. If is_t is true, | |
4113 | reject forms that cannot be used with a T instruction (i.e. not | |
4114 | post-indexed). */ | |
a737bd4d | 4115 | static void |
c19d1205 | 4116 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 4117 | { |
c19d1205 | 4118 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4119 | |
c19d1205 | 4120 | if (inst.operands[i].immisreg) |
09d92015 | 4121 | { |
c19d1205 ZW |
4122 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
4123 | inst.instruction |= inst.operands[i].imm; | |
4124 | if (!inst.operands[i].negative) | |
4125 | inst.instruction |= INDEX_UP; | |
4126 | if (inst.operands[i].shifted) | |
4127 | { | |
4128 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
4129 | inst.instruction |= SHIFT_ROR << 5; | |
4130 | else | |
4131 | { | |
4132 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
4133 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
4134 | } | |
4135 | } | |
09d92015 | 4136 | } |
c19d1205 | 4137 | else /* immediate offset in inst.reloc */ |
09d92015 | 4138 | { |
c19d1205 ZW |
4139 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
4140 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 4141 | } |
09d92015 MM |
4142 | } |
4143 | ||
c19d1205 ZW |
4144 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4145 | ARM-format mode 3 load or store instruction. Reject forms that | |
4146 | cannot be used with such instructions. If is_t is true, reject | |
4147 | forms that cannot be used with a T instruction (i.e. not | |
4148 | post-indexed). */ | |
4149 | static void | |
4150 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 4151 | { |
c19d1205 | 4152 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 4153 | { |
c19d1205 ZW |
4154 | inst.error = _("instruction does not accept scaled register index"); |
4155 | return; | |
09d92015 | 4156 | } |
a737bd4d | 4157 | |
c19d1205 | 4158 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4159 | |
c19d1205 ZW |
4160 | if (inst.operands[i].immisreg) |
4161 | { | |
4162 | inst.instruction |= inst.operands[i].imm; | |
4163 | if (!inst.operands[i].negative) | |
4164 | inst.instruction |= INDEX_UP; | |
4165 | } | |
4166 | else /* immediate offset in inst.reloc */ | |
4167 | { | |
4168 | inst.instruction |= HWOFFSET_IMM; | |
4169 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
4170 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 4171 | } |
a737bd4d NC |
4172 | } |
4173 | ||
c19d1205 ZW |
4174 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4175 | ARM-format instruction. Reject all forms which cannot be encoded | |
4176 | into a coprocessor load/store instruction. If wb_ok is false, | |
4177 | reject use of writeback; if unind_ok is false, reject use of | |
4178 | unindexed addressing. If reloc_override is not 0, use it instead | |
4179 | of BFD_ARM_CP_OFF_IMM. */ | |
09d92015 | 4180 | |
c19d1205 ZW |
4181 | static int |
4182 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 4183 | { |
c19d1205 | 4184 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 4185 | |
c19d1205 | 4186 | assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 4187 | |
c19d1205 | 4188 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 4189 | { |
c19d1205 ZW |
4190 | assert (!inst.operands[i].writeback); |
4191 | if (!unind_ok) | |
4192 | { | |
4193 | inst.error = _("instruction does not support unindexed addressing"); | |
4194 | return FAIL; | |
4195 | } | |
4196 | inst.instruction |= inst.operands[i].imm; | |
4197 | inst.instruction |= INDEX_UP; | |
4198 | return SUCCESS; | |
09d92015 | 4199 | } |
a737bd4d | 4200 | |
c19d1205 ZW |
4201 | if (inst.operands[i].preind) |
4202 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 4203 | |
c19d1205 | 4204 | if (inst.operands[i].writeback) |
09d92015 | 4205 | { |
c19d1205 ZW |
4206 | if (inst.operands[i].reg == REG_PC) |
4207 | { | |
4208 | inst.error = _("pc may not be used with write-back"); | |
4209 | return FAIL; | |
4210 | } | |
4211 | if (!wb_ok) | |
4212 | { | |
4213 | inst.error = _("instruction does not support writeback"); | |
4214 | return FAIL; | |
4215 | } | |
4216 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4217 | } |
a737bd4d | 4218 | |
c19d1205 ZW |
4219 | if (reloc_override) |
4220 | inst.reloc.type = reloc_override; | |
8f06b2d8 PB |
4221 | else if (thumb_mode) |
4222 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
09d92015 | 4223 | else |
c19d1205 | 4224 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; |
c19d1205 ZW |
4225 | return SUCCESS; |
4226 | } | |
a737bd4d | 4227 | |
c19d1205 ZW |
4228 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
4229 | Determine whether it can be performed with a move instruction; if | |
4230 | it can, convert inst.instruction to that move instruction and | |
4231 | return 1; if it can't, convert inst.instruction to a literal-pool | |
4232 | load and return 0. If this is not a valid thing to do in the | |
4233 | current context, set inst.error and return 1. | |
a737bd4d | 4234 | |
c19d1205 ZW |
4235 | inst.operands[i] describes the destination register. */ |
4236 | ||
4237 | static int | |
4238 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) | |
4239 | { | |
4240 | if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0) | |
09d92015 | 4241 | { |
c19d1205 ZW |
4242 | inst.error = _("invalid pseudo operation"); |
4243 | return 1; | |
09d92015 | 4244 | } |
c19d1205 | 4245 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
4246 | { |
4247 | inst.error = _("constant expression expected"); | |
c19d1205 | 4248 | return 1; |
09d92015 | 4249 | } |
c19d1205 | 4250 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 4251 | { |
c19d1205 ZW |
4252 | if (thumb_p) |
4253 | { | |
4254 | if ((inst.reloc.exp.X_add_number & ~0xFF) == 0) | |
4255 | { | |
4256 | /* This can be done with a mov(1) instruction. */ | |
4257 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
4258 | inst.instruction |= inst.reloc.exp.X_add_number; | |
4259 | return 1; | |
4260 | } | |
4261 | } | |
4262 | else | |
4263 | { | |
4264 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
4265 | if (value != FAIL) | |
4266 | { | |
4267 | /* This can be done with a mov instruction. */ | |
4268 | inst.instruction &= LITERAL_MASK; | |
4269 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
4270 | inst.instruction |= value & 0xfff; | |
4271 | return 1; | |
4272 | } | |
09d92015 | 4273 | |
c19d1205 ZW |
4274 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
4275 | if (value != FAIL) | |
4276 | { | |
4277 | /* This can be done with a mvn instruction. */ | |
4278 | inst.instruction &= LITERAL_MASK; | |
4279 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
4280 | inst.instruction |= value & 0xfff; | |
4281 | return 1; | |
4282 | } | |
4283 | } | |
09d92015 MM |
4284 | } |
4285 | ||
c19d1205 ZW |
4286 | if (add_to_lit_pool () == FAIL) |
4287 | { | |
4288 | inst.error = _("literal pool insertion failed"); | |
4289 | return 1; | |
4290 | } | |
4291 | inst.operands[1].reg = REG_PC; | |
4292 | inst.operands[1].isreg = 1; | |
4293 | inst.operands[1].preind = 1; | |
4294 | inst.reloc.pc_rel = 1; | |
4295 | inst.reloc.type = (thumb_p | |
4296 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
4297 | : (mode_3 | |
4298 | ? BFD_RELOC_ARM_HWLITERAL | |
4299 | : BFD_RELOC_ARM_LITERAL)); | |
4300 | return 0; | |
09d92015 MM |
4301 | } |
4302 | ||
c19d1205 ZW |
4303 | /* Functions for instruction encoding, sorted by subarchitecture. |
4304 | First some generics; their names are taken from the conventional | |
4305 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 4306 | |
a737bd4d | 4307 | static void |
c19d1205 | 4308 | do_noargs (void) |
09d92015 | 4309 | { |
c19d1205 | 4310 | } |
a737bd4d | 4311 | |
c19d1205 ZW |
4312 | static void |
4313 | do_rd (void) | |
4314 | { | |
4315 | inst.instruction |= inst.operands[0].reg << 12; | |
4316 | } | |
a737bd4d | 4317 | |
c19d1205 ZW |
4318 | static void |
4319 | do_rd_rm (void) | |
4320 | { | |
4321 | inst.instruction |= inst.operands[0].reg << 12; | |
4322 | inst.instruction |= inst.operands[1].reg; | |
4323 | } | |
09d92015 | 4324 | |
c19d1205 ZW |
4325 | static void |
4326 | do_rd_rn (void) | |
4327 | { | |
4328 | inst.instruction |= inst.operands[0].reg << 12; | |
4329 | inst.instruction |= inst.operands[1].reg << 16; | |
4330 | } | |
a737bd4d | 4331 | |
c19d1205 ZW |
4332 | static void |
4333 | do_rn_rd (void) | |
4334 | { | |
4335 | inst.instruction |= inst.operands[0].reg << 16; | |
4336 | inst.instruction |= inst.operands[1].reg << 12; | |
4337 | } | |
09d92015 | 4338 | |
c19d1205 ZW |
4339 | static void |
4340 | do_rd_rm_rn (void) | |
4341 | { | |
4342 | inst.instruction |= inst.operands[0].reg << 12; | |
4343 | inst.instruction |= inst.operands[1].reg; | |
4344 | inst.instruction |= inst.operands[2].reg << 16; | |
4345 | } | |
09d92015 | 4346 | |
c19d1205 ZW |
4347 | static void |
4348 | do_rd_rn_rm (void) | |
4349 | { | |
4350 | inst.instruction |= inst.operands[0].reg << 12; | |
4351 | inst.instruction |= inst.operands[1].reg << 16; | |
4352 | inst.instruction |= inst.operands[2].reg; | |
4353 | } | |
a737bd4d | 4354 | |
c19d1205 ZW |
4355 | static void |
4356 | do_rm_rd_rn (void) | |
4357 | { | |
4358 | inst.instruction |= inst.operands[0].reg; | |
4359 | inst.instruction |= inst.operands[1].reg << 12; | |
4360 | inst.instruction |= inst.operands[2].reg << 16; | |
4361 | } | |
09d92015 | 4362 | |
c19d1205 ZW |
4363 | static void |
4364 | do_imm0 (void) | |
4365 | { | |
4366 | inst.instruction |= inst.operands[0].imm; | |
4367 | } | |
09d92015 | 4368 | |
c19d1205 ZW |
4369 | static void |
4370 | do_rd_cpaddr (void) | |
4371 | { | |
4372 | inst.instruction |= inst.operands[0].reg << 12; | |
4373 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 4374 | } |
a737bd4d | 4375 | |
c19d1205 ZW |
4376 | /* ARM instructions, in alphabetical order by function name (except |
4377 | that wrapper functions appear immediately after the function they | |
4378 | wrap). */ | |
09d92015 | 4379 | |
c19d1205 ZW |
4380 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
4381 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
4382 | |
4383 | static void | |
c19d1205 | 4384 | do_adr (void) |
09d92015 | 4385 | { |
c19d1205 | 4386 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 4387 | |
c19d1205 ZW |
4388 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4389 | out to be negative. */ | |
4390 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 4391 | inst.reloc.pc_rel = 1; |
2fc8bdac | 4392 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 4393 | } |
b99bd4ef | 4394 | |
c19d1205 ZW |
4395 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
4396 | into a relative address of the form: | |
4397 | add rd, pc, #low(label-.-8)" | |
4398 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 4399 | |
c19d1205 ZW |
4400 | static void |
4401 | do_adrl (void) | |
4402 | { | |
4403 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 4404 | |
c19d1205 ZW |
4405 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4406 | out to be negative. */ | |
4407 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
4408 | inst.reloc.pc_rel = 1; |
4409 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 4410 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
4411 | } |
4412 | ||
b99bd4ef | 4413 | static void |
c19d1205 | 4414 | do_arit (void) |
b99bd4ef | 4415 | { |
c19d1205 ZW |
4416 | if (!inst.operands[1].present) |
4417 | inst.operands[1].reg = inst.operands[0].reg; | |
4418 | inst.instruction |= inst.operands[0].reg << 12; | |
4419 | inst.instruction |= inst.operands[1].reg << 16; | |
4420 | encode_arm_shifter_operand (2); | |
4421 | } | |
b99bd4ef | 4422 | |
c19d1205 ZW |
4423 | static void |
4424 | do_bfc (void) | |
4425 | { | |
4426 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
4427 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4428 | /* The instruction encoding stores the LSB and MSB, | |
4429 | not the LSB and width. */ | |
4430 | inst.instruction |= inst.operands[0].reg << 12; | |
4431 | inst.instruction |= inst.operands[1].imm << 7; | |
4432 | inst.instruction |= (msb - 1) << 16; | |
4433 | } | |
b99bd4ef | 4434 | |
c19d1205 ZW |
4435 | static void |
4436 | do_bfi (void) | |
4437 | { | |
4438 | unsigned int msb; | |
b99bd4ef | 4439 | |
c19d1205 ZW |
4440 | /* #0 in second position is alternative syntax for bfc, which is |
4441 | the same instruction but with REG_PC in the Rm field. */ | |
4442 | if (!inst.operands[1].isreg) | |
4443 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 4444 | |
c19d1205 ZW |
4445 | msb = inst.operands[2].imm + inst.operands[3].imm; |
4446 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4447 | /* The instruction encoding stores the LSB and MSB, | |
4448 | not the LSB and width. */ | |
4449 | inst.instruction |= inst.operands[0].reg << 12; | |
4450 | inst.instruction |= inst.operands[1].reg; | |
4451 | inst.instruction |= inst.operands[2].imm << 7; | |
4452 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
4453 | } |
4454 | ||
b99bd4ef | 4455 | static void |
c19d1205 | 4456 | do_bfx (void) |
b99bd4ef | 4457 | { |
c19d1205 ZW |
4458 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
4459 | _("bit-field extends past end of register")); | |
4460 | inst.instruction |= inst.operands[0].reg << 12; | |
4461 | inst.instruction |= inst.operands[1].reg; | |
4462 | inst.instruction |= inst.operands[2].imm << 7; | |
4463 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
4464 | } | |
09d92015 | 4465 | |
c19d1205 ZW |
4466 | /* ARM V5 breakpoint instruction (argument parse) |
4467 | BKPT <16 bit unsigned immediate> | |
4468 | Instruction is not conditional. | |
4469 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
4470 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 4471 | |
c19d1205 ZW |
4472 | static void |
4473 | do_bkpt (void) | |
4474 | { | |
4475 | /* Top 12 of 16 bits to bits 19:8. */ | |
4476 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 4477 | |
c19d1205 ZW |
4478 | /* Bottom 4 of 16 bits to bits 3:0. */ |
4479 | inst.instruction |= inst.operands[0].imm & 0xf; | |
4480 | } | |
09d92015 | 4481 | |
c19d1205 ZW |
4482 | static void |
4483 | encode_branch (int default_reloc) | |
4484 | { | |
4485 | if (inst.operands[0].hasreloc) | |
4486 | { | |
4487 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
4488 | _("the only suffix valid here is '(plt)'")); | |
4489 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
c19d1205 | 4490 | } |
b99bd4ef | 4491 | else |
c19d1205 ZW |
4492 | { |
4493 | inst.reloc.type = default_reloc; | |
c19d1205 | 4494 | } |
2fc8bdac | 4495 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
4496 | } |
4497 | ||
b99bd4ef | 4498 | static void |
c19d1205 | 4499 | do_branch (void) |
b99bd4ef | 4500 | { |
c19d1205 ZW |
4501 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); |
4502 | } | |
b99bd4ef | 4503 | |
c19d1205 ZW |
4504 | /* ARM V5 branch-link-exchange instruction (argument parse) |
4505 | BLX <target_addr> ie BLX(1) | |
4506 | BLX{<condition>} <Rm> ie BLX(2) | |
4507 | Unfortunately, there are two different opcodes for this mnemonic. | |
4508 | So, the insns[].value is not used, and the code here zaps values | |
4509 | into inst.instruction. | |
4510 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 4511 | |
c19d1205 ZW |
4512 | static void |
4513 | do_blx (void) | |
4514 | { | |
4515 | if (inst.operands[0].isreg) | |
b99bd4ef | 4516 | { |
c19d1205 ZW |
4517 | /* Arg is a register; the opcode provided by insns[] is correct. |
4518 | It is not illegal to do "blx pc", just useless. */ | |
4519 | if (inst.operands[0].reg == REG_PC) | |
4520 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 4521 | |
c19d1205 ZW |
4522 | inst.instruction |= inst.operands[0].reg; |
4523 | } | |
4524 | else | |
b99bd4ef | 4525 | { |
c19d1205 ZW |
4526 | /* Arg is an address; this instruction cannot be executed |
4527 | conditionally, and the opcode must be adjusted. */ | |
4528 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
2fc8bdac | 4529 | inst.instruction = 0xfa000000; |
c19d1205 | 4530 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 4531 | } |
c19d1205 ZW |
4532 | } |
4533 | ||
4534 | static void | |
4535 | do_bx (void) | |
4536 | { | |
4537 | if (inst.operands[0].reg == REG_PC) | |
4538 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 4539 | |
c19d1205 | 4540 | inst.instruction |= inst.operands[0].reg; |
09d92015 MM |
4541 | } |
4542 | ||
c19d1205 ZW |
4543 | |
4544 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
4545 | |
4546 | static void | |
c19d1205 | 4547 | do_bxj (void) |
a737bd4d | 4548 | { |
c19d1205 ZW |
4549 | if (inst.operands[0].reg == REG_PC) |
4550 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
4551 | ||
4552 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
4553 | } |
4554 | ||
c19d1205 ZW |
4555 | /* Co-processor data operation: |
4556 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
4557 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
4558 | static void | |
4559 | do_cdp (void) | |
4560 | { | |
4561 | inst.instruction |= inst.operands[0].reg << 8; | |
4562 | inst.instruction |= inst.operands[1].imm << 20; | |
4563 | inst.instruction |= inst.operands[2].reg << 12; | |
4564 | inst.instruction |= inst.operands[3].reg << 16; | |
4565 | inst.instruction |= inst.operands[4].reg; | |
4566 | inst.instruction |= inst.operands[5].imm << 5; | |
4567 | } | |
a737bd4d NC |
4568 | |
4569 | static void | |
c19d1205 | 4570 | do_cmp (void) |
a737bd4d | 4571 | { |
c19d1205 ZW |
4572 | inst.instruction |= inst.operands[0].reg << 16; |
4573 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
4574 | } |
4575 | ||
c19d1205 ZW |
4576 | /* Transfer between coprocessor and ARM registers. |
4577 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
4578 | MRC2 | |
4579 | MCR{cond} | |
4580 | MCR2 | |
4581 | ||
4582 | No special properties. */ | |
09d92015 MM |
4583 | |
4584 | static void | |
c19d1205 | 4585 | do_co_reg (void) |
09d92015 | 4586 | { |
c19d1205 ZW |
4587 | inst.instruction |= inst.operands[0].reg << 8; |
4588 | inst.instruction |= inst.operands[1].imm << 21; | |
4589 | inst.instruction |= inst.operands[2].reg << 12; | |
4590 | inst.instruction |= inst.operands[3].reg << 16; | |
4591 | inst.instruction |= inst.operands[4].reg; | |
4592 | inst.instruction |= inst.operands[5].imm << 5; | |
4593 | } | |
09d92015 | 4594 | |
c19d1205 ZW |
4595 | /* Transfer between coprocessor register and pair of ARM registers. |
4596 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
4597 | MCRR2 | |
4598 | MRRC{cond} | |
4599 | MRRC2 | |
b99bd4ef | 4600 | |
c19d1205 | 4601 | Two XScale instructions are special cases of these: |
09d92015 | 4602 | |
c19d1205 ZW |
4603 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
4604 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 4605 | |
c19d1205 | 4606 | Result unpredicatable if Rd or Rn is R15. */ |
a737bd4d | 4607 | |
c19d1205 ZW |
4608 | static void |
4609 | do_co_reg2c (void) | |
4610 | { | |
4611 | inst.instruction |= inst.operands[0].reg << 8; | |
4612 | inst.instruction |= inst.operands[1].imm << 4; | |
4613 | inst.instruction |= inst.operands[2].reg << 12; | |
4614 | inst.instruction |= inst.operands[3].reg << 16; | |
4615 | inst.instruction |= inst.operands[4].reg; | |
b99bd4ef NC |
4616 | } |
4617 | ||
c19d1205 ZW |
4618 | static void |
4619 | do_cpsi (void) | |
4620 | { | |
4621 | inst.instruction |= inst.operands[0].imm << 6; | |
4622 | inst.instruction |= inst.operands[1].imm; | |
4623 | } | |
b99bd4ef NC |
4624 | |
4625 | static void | |
c19d1205 | 4626 | do_it (void) |
b99bd4ef | 4627 | { |
c19d1205 ZW |
4628 | /* There is no IT instruction in ARM mode. We |
4629 | process it but do not generate code for it. */ | |
4630 | inst.size = 0; | |
09d92015 | 4631 | } |
b99bd4ef | 4632 | |
09d92015 | 4633 | static void |
c19d1205 | 4634 | do_ldmstm (void) |
ea6ef066 | 4635 | { |
c19d1205 ZW |
4636 | int base_reg = inst.operands[0].reg; |
4637 | int range = inst.operands[1].imm; | |
ea6ef066 | 4638 | |
c19d1205 ZW |
4639 | inst.instruction |= base_reg << 16; |
4640 | inst.instruction |= range; | |
ea6ef066 | 4641 | |
c19d1205 ZW |
4642 | if (inst.operands[1].writeback) |
4643 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 4644 | |
c19d1205 | 4645 | if (inst.operands[0].writeback) |
ea6ef066 | 4646 | { |
c19d1205 ZW |
4647 | inst.instruction |= WRITE_BACK; |
4648 | /* Check for unpredictable uses of writeback. */ | |
4649 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 4650 | { |
c19d1205 ZW |
4651 | /* Not allowed in LDM type 2. */ |
4652 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
4653 | && ((range & (1 << REG_PC)) == 0)) | |
4654 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4655 | /* Only allowed if base reg not in list for other types. */ | |
4656 | else if (range & (1 << base_reg)) | |
4657 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
4658 | } | |
4659 | else /* STM. */ | |
4660 | { | |
4661 | /* Not allowed for type 2. */ | |
4662 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
4663 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4664 | /* Only allowed if base reg not in list, or first in list. */ | |
4665 | else if ((range & (1 << base_reg)) | |
4666 | && (range & ((1 << base_reg) - 1))) | |
4667 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 4668 | } |
ea6ef066 | 4669 | } |
a737bd4d NC |
4670 | } |
4671 | ||
c19d1205 ZW |
4672 | /* ARMv5TE load-consecutive (argument parse) |
4673 | Mode is like LDRH. | |
4674 | ||
4675 | LDRccD R, mode | |
4676 | STRccD R, mode. */ | |
4677 | ||
a737bd4d | 4678 | static void |
c19d1205 | 4679 | do_ldrd (void) |
a737bd4d | 4680 | { |
c19d1205 ZW |
4681 | constraint (inst.operands[0].reg % 2 != 0, |
4682 | _("first destination register must be even")); | |
4683 | constraint (inst.operands[1].present | |
4684 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4685 | _("can only load two consecutive registers")); | |
4686 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
4687 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 4688 | |
c19d1205 ZW |
4689 | if (!inst.operands[1].present) |
4690 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
4691 | ||
4692 | if (inst.instruction & LOAD_BIT) | |
a737bd4d | 4693 | { |
c19d1205 ZW |
4694 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
4695 | register and the first register written; we have to diagnose | |
4696 | overlap between the base and the second register written here. */ | |
ea6ef066 | 4697 | |
c19d1205 ZW |
4698 | if (inst.operands[2].reg == inst.operands[1].reg |
4699 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
4700 | as_warn (_("base register written back, and overlaps " | |
4701 | "second destination register")); | |
b05fe5cf | 4702 | |
c19d1205 ZW |
4703 | /* For an index-register load, the index register must not overlap the |
4704 | destination (even if not write-back). */ | |
4705 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
4706 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
4707 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 4708 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 4709 | } |
c19d1205 ZW |
4710 | |
4711 | inst.instruction |= inst.operands[0].reg << 12; | |
4712 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
4713 | } |
4714 | ||
4715 | static void | |
c19d1205 | 4716 | do_ldrex (void) |
b05fe5cf | 4717 | { |
c19d1205 ZW |
4718 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
4719 | || inst.operands[1].postind || inst.operands[1].writeback | |
4720 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
4721 | || inst.operands[1].negative, | |
4722 | _("instruction does not accept this addressing mode")); | |
b05fe5cf | 4723 | |
c19d1205 | 4724 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); |
b05fe5cf | 4725 | |
c19d1205 ZW |
4726 | constraint (inst.reloc.exp.X_op != O_constant |
4727 | || inst.reloc.exp.X_add_number != 0, | |
4728 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 4729 | |
c19d1205 ZW |
4730 | inst.instruction |= inst.operands[0].reg << 12; |
4731 | inst.instruction |= inst.operands[1].reg << 16; | |
4732 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
4733 | } |
4734 | ||
4735 | static void | |
c19d1205 | 4736 | do_ldrexd (void) |
b05fe5cf | 4737 | { |
c19d1205 ZW |
4738 | constraint (inst.operands[0].reg % 2 != 0, |
4739 | _("even register required")); | |
4740 | constraint (inst.operands[1].present | |
4741 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4742 | _("can only load two consecutive registers")); | |
4743 | /* If op 1 were present and equal to PC, this function wouldn't | |
4744 | have been called in the first place. */ | |
4745 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 4746 | |
c19d1205 ZW |
4747 | inst.instruction |= inst.operands[0].reg << 12; |
4748 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
4749 | } |
4750 | ||
4751 | static void | |
c19d1205 | 4752 | do_ldst (void) |
b05fe5cf | 4753 | { |
c19d1205 ZW |
4754 | inst.instruction |= inst.operands[0].reg << 12; |
4755 | if (!inst.operands[1].isreg) | |
4756 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 4757 | return; |
c19d1205 | 4758 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
4759 | } |
4760 | ||
4761 | static void | |
c19d1205 | 4762 | do_ldstt (void) |
b05fe5cf | 4763 | { |
c19d1205 ZW |
4764 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
4765 | reject [Rn,...]. */ | |
4766 | if (inst.operands[1].preind) | |
b05fe5cf | 4767 | { |
c19d1205 ZW |
4768 | constraint (inst.reloc.exp.X_op != O_constant || |
4769 | inst.reloc.exp.X_add_number != 0, | |
4770 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 4771 | |
c19d1205 ZW |
4772 | inst.operands[1].preind = 0; |
4773 | inst.operands[1].postind = 1; | |
4774 | inst.operands[1].writeback = 1; | |
b05fe5cf | 4775 | } |
c19d1205 ZW |
4776 | inst.instruction |= inst.operands[0].reg << 12; |
4777 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
4778 | } | |
b05fe5cf | 4779 | |
c19d1205 | 4780 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 4781 | |
c19d1205 ZW |
4782 | static void |
4783 | do_ldstv4 (void) | |
4784 | { | |
4785 | inst.instruction |= inst.operands[0].reg << 12; | |
4786 | if (!inst.operands[1].isreg) | |
4787 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 4788 | return; |
c19d1205 | 4789 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
4790 | } |
4791 | ||
4792 | static void | |
c19d1205 | 4793 | do_ldsttv4 (void) |
b05fe5cf | 4794 | { |
c19d1205 ZW |
4795 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
4796 | reject [Rn,...]. */ | |
4797 | if (inst.operands[1].preind) | |
b05fe5cf | 4798 | { |
c19d1205 ZW |
4799 | constraint (inst.reloc.exp.X_op != O_constant || |
4800 | inst.reloc.exp.X_add_number != 0, | |
4801 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 4802 | |
c19d1205 ZW |
4803 | inst.operands[1].preind = 0; |
4804 | inst.operands[1].postind = 1; | |
4805 | inst.operands[1].writeback = 1; | |
b05fe5cf | 4806 | } |
c19d1205 ZW |
4807 | inst.instruction |= inst.operands[0].reg << 12; |
4808 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
4809 | } | |
b05fe5cf | 4810 | |
c19d1205 ZW |
4811 | /* Co-processor register load/store. |
4812 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
4813 | static void | |
4814 | do_lstc (void) | |
4815 | { | |
4816 | inst.instruction |= inst.operands[0].reg << 8; | |
4817 | inst.instruction |= inst.operands[1].reg << 12; | |
4818 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
4819 | } |
4820 | ||
b05fe5cf | 4821 | static void |
c19d1205 | 4822 | do_mlas (void) |
b05fe5cf | 4823 | { |
c19d1205 ZW |
4824 | /* This restriction does not apply to mls (nor to mla in v6, but |
4825 | that's hard to detect at present). */ | |
4826 | if (inst.operands[0].reg == inst.operands[1].reg | |
4827 | && !(inst.instruction & 0x00400000)) | |
4828 | as_tsktsk (_("rd and rm should be different in mla")); | |
b05fe5cf | 4829 | |
c19d1205 ZW |
4830 | inst.instruction |= inst.operands[0].reg << 16; |
4831 | inst.instruction |= inst.operands[1].reg; | |
4832 | inst.instruction |= inst.operands[2].reg << 8; | |
4833 | inst.instruction |= inst.operands[3].reg << 12; | |
b05fe5cf | 4834 | |
c19d1205 | 4835 | } |
b05fe5cf | 4836 | |
c19d1205 ZW |
4837 | static void |
4838 | do_mov (void) | |
4839 | { | |
4840 | inst.instruction |= inst.operands[0].reg << 12; | |
4841 | encode_arm_shifter_operand (1); | |
4842 | } | |
b05fe5cf | 4843 | |
c19d1205 ZW |
4844 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
4845 | static void | |
4846 | do_mov16 (void) | |
4847 | { | |
4848 | inst.instruction |= inst.operands[0].reg << 12; | |
b05fe5cf | 4849 | /* The value is in two pieces: 0:11, 16:19. */ |
c19d1205 ZW |
4850 | inst.instruction |= (inst.operands[1].imm & 0x00000fff); |
4851 | inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4; | |
b05fe5cf | 4852 | } |
b99bd4ef NC |
4853 | |
4854 | static void | |
c19d1205 | 4855 | do_mrs (void) |
b99bd4ef | 4856 | { |
c19d1205 ZW |
4857 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
4858 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
4859 | != (PSR_c|PSR_f), | |
4860 | _("'CPSR' or 'SPSR' expected")); | |
4861 | inst.instruction |= inst.operands[0].reg << 12; | |
4862 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
4863 | } | |
b99bd4ef | 4864 | |
c19d1205 ZW |
4865 | /* Two possible forms: |
4866 | "{C|S}PSR_<field>, Rm", | |
4867 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 4868 | |
c19d1205 ZW |
4869 | static void |
4870 | do_msr (void) | |
4871 | { | |
4872 | inst.instruction |= inst.operands[0].imm; | |
4873 | if (inst.operands[1].isreg) | |
4874 | inst.instruction |= inst.operands[1].reg; | |
4875 | else | |
b99bd4ef | 4876 | { |
c19d1205 ZW |
4877 | inst.instruction |= INST_IMMEDIATE; |
4878 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
4879 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 4880 | } |
b99bd4ef NC |
4881 | } |
4882 | ||
c19d1205 ZW |
4883 | static void |
4884 | do_mul (void) | |
a737bd4d | 4885 | { |
c19d1205 ZW |
4886 | if (!inst.operands[2].present) |
4887 | inst.operands[2].reg = inst.operands[0].reg; | |
4888 | inst.instruction |= inst.operands[0].reg << 16; | |
4889 | inst.instruction |= inst.operands[1].reg; | |
4890 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 4891 | |
c19d1205 ZW |
4892 | if (inst.operands[0].reg == inst.operands[1].reg) |
4893 | as_tsktsk (_("rd and rm should be different in mul")); | |
a737bd4d NC |
4894 | } |
4895 | ||
c19d1205 ZW |
4896 | /* Long Multiply Parser |
4897 | UMULL RdLo, RdHi, Rm, Rs | |
4898 | SMULL RdLo, RdHi, Rm, Rs | |
4899 | UMLAL RdLo, RdHi, Rm, Rs | |
4900 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
4901 | |
4902 | static void | |
c19d1205 | 4903 | do_mull (void) |
b99bd4ef | 4904 | { |
c19d1205 ZW |
4905 | inst.instruction |= inst.operands[0].reg << 12; |
4906 | inst.instruction |= inst.operands[1].reg << 16; | |
4907 | inst.instruction |= inst.operands[2].reg; | |
4908 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 4909 | |
c19d1205 ZW |
4910 | /* rdhi, rdlo and rm must all be different. */ |
4911 | if (inst.operands[0].reg == inst.operands[1].reg | |
4912 | || inst.operands[0].reg == inst.operands[2].reg | |
4913 | || inst.operands[1].reg == inst.operands[2].reg) | |
4914 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
4915 | } | |
b99bd4ef | 4916 | |
c19d1205 ZW |
4917 | static void |
4918 | do_nop (void) | |
4919 | { | |
4920 | if (inst.operands[0].present) | |
4921 | { | |
4922 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
4923 | inst.instruction &= 0xf0000000; | |
4924 | inst.instruction |= 0x0320f000 + inst.operands[0].imm; | |
4925 | } | |
b99bd4ef NC |
4926 | } |
4927 | ||
c19d1205 ZW |
4928 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
4929 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
4930 | Condition defaults to COND_ALWAYS. | |
4931 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
4932 | |
4933 | static void | |
c19d1205 | 4934 | do_pkhbt (void) |
b99bd4ef | 4935 | { |
c19d1205 ZW |
4936 | inst.instruction |= inst.operands[0].reg << 12; |
4937 | inst.instruction |= inst.operands[1].reg << 16; | |
4938 | inst.instruction |= inst.operands[2].reg; | |
4939 | if (inst.operands[3].present) | |
4940 | encode_arm_shift (3); | |
4941 | } | |
b99bd4ef | 4942 | |
c19d1205 | 4943 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 4944 | |
c19d1205 ZW |
4945 | static void |
4946 | do_pkhtb (void) | |
4947 | { | |
4948 | if (!inst.operands[3].present) | |
b99bd4ef | 4949 | { |
c19d1205 ZW |
4950 | /* If the shift specifier is omitted, turn the instruction |
4951 | into pkhbt rd, rm, rn. */ | |
4952 | inst.instruction &= 0xfff00010; | |
4953 | inst.instruction |= inst.operands[0].reg << 12; | |
4954 | inst.instruction |= inst.operands[1].reg; | |
4955 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
4956 | } |
4957 | else | |
4958 | { | |
c19d1205 ZW |
4959 | inst.instruction |= inst.operands[0].reg << 12; |
4960 | inst.instruction |= inst.operands[1].reg << 16; | |
4961 | inst.instruction |= inst.operands[2].reg; | |
4962 | encode_arm_shift (3); | |
b99bd4ef NC |
4963 | } |
4964 | } | |
4965 | ||
c19d1205 ZW |
4966 | /* ARMv5TE: Preload-Cache |
4967 | ||
4968 | PLD <addr_mode> | |
4969 | ||
4970 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
4971 | |
4972 | static void | |
c19d1205 | 4973 | do_pld (void) |
b99bd4ef | 4974 | { |
c19d1205 ZW |
4975 | constraint (!inst.operands[0].isreg, |
4976 | _("'[' expected after PLD mnemonic")); | |
4977 | constraint (inst.operands[0].postind, | |
4978 | _("post-indexed expression used in preload instruction")); | |
4979 | constraint (inst.operands[0].writeback, | |
4980 | _("writeback used in preload instruction")); | |
4981 | constraint (!inst.operands[0].preind, | |
4982 | _("unindexed addressing used in preload instruction")); | |
4983 | inst.instruction |= inst.operands[0].reg; | |
4984 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
4985 | } | |
b99bd4ef | 4986 | |
c19d1205 ZW |
4987 | static void |
4988 | do_push_pop (void) | |
4989 | { | |
4990 | inst.operands[1] = inst.operands[0]; | |
4991 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
4992 | inst.operands[0].isreg = 1; | |
4993 | inst.operands[0].writeback = 1; | |
4994 | inst.operands[0].reg = REG_SP; | |
4995 | do_ldmstm (); | |
4996 | } | |
b99bd4ef | 4997 | |
c19d1205 ZW |
4998 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
4999 | word at the specified address and the following word | |
5000 | respectively. | |
5001 | Unconditionally executed. | |
5002 | Error if Rn is R15. */ | |
b99bd4ef | 5003 | |
c19d1205 ZW |
5004 | static void |
5005 | do_rfe (void) | |
5006 | { | |
5007 | inst.instruction |= inst.operands[0].reg << 16; | |
5008 | if (inst.operands[0].writeback) | |
5009 | inst.instruction |= WRITE_BACK; | |
5010 | } | |
b99bd4ef | 5011 | |
c19d1205 | 5012 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 5013 | |
c19d1205 ZW |
5014 | static void |
5015 | do_ssat (void) | |
5016 | { | |
5017 | inst.instruction |= inst.operands[0].reg << 12; | |
5018 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
5019 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5020 | |
c19d1205 ZW |
5021 | if (inst.operands[3].present) |
5022 | encode_arm_shift (3); | |
b99bd4ef NC |
5023 | } |
5024 | ||
c19d1205 | 5025 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
5026 | |
5027 | static void | |
c19d1205 | 5028 | do_usat (void) |
b99bd4ef | 5029 | { |
c19d1205 ZW |
5030 | inst.instruction |= inst.operands[0].reg << 12; |
5031 | inst.instruction |= inst.operands[1].imm << 16; | |
5032 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5033 | |
c19d1205 ZW |
5034 | if (inst.operands[3].present) |
5035 | encode_arm_shift (3); | |
b99bd4ef NC |
5036 | } |
5037 | ||
c19d1205 | 5038 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
5039 | |
5040 | static void | |
c19d1205 | 5041 | do_ssat16 (void) |
09d92015 | 5042 | { |
c19d1205 ZW |
5043 | inst.instruction |= inst.operands[0].reg << 12; |
5044 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
5045 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
5046 | } |
5047 | ||
c19d1205 ZW |
5048 | static void |
5049 | do_usat16 (void) | |
a737bd4d | 5050 | { |
c19d1205 ZW |
5051 | inst.instruction |= inst.operands[0].reg << 12; |
5052 | inst.instruction |= inst.operands[1].imm << 16; | |
5053 | inst.instruction |= inst.operands[2].reg; | |
5054 | } | |
a737bd4d | 5055 | |
c19d1205 ZW |
5056 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
5057 | preserving the other bits. | |
a737bd4d | 5058 | |
c19d1205 ZW |
5059 | setend <endian_specifier>, where <endian_specifier> is either |
5060 | BE or LE. */ | |
a737bd4d | 5061 | |
c19d1205 ZW |
5062 | static void |
5063 | do_setend (void) | |
5064 | { | |
5065 | if (inst.operands[0].imm) | |
5066 | inst.instruction |= 0x200; | |
a737bd4d NC |
5067 | } |
5068 | ||
5069 | static void | |
c19d1205 | 5070 | do_shift (void) |
a737bd4d | 5071 | { |
c19d1205 ZW |
5072 | unsigned int Rm = (inst.operands[1].present |
5073 | ? inst.operands[1].reg | |
5074 | : inst.operands[0].reg); | |
a737bd4d | 5075 | |
c19d1205 ZW |
5076 | inst.instruction |= inst.operands[0].reg << 12; |
5077 | inst.instruction |= Rm; | |
5078 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 5079 | { |
c19d1205 ZW |
5080 | constraint (inst.operands[0].reg != Rm, |
5081 | _("source1 and dest must be same register")); | |
5082 | inst.instruction |= inst.operands[2].reg << 8; | |
5083 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
5084 | } |
5085 | else | |
c19d1205 | 5086 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
5087 | } |
5088 | ||
09d92015 | 5089 | static void |
c19d1205 | 5090 | do_smi (void) |
09d92015 | 5091 | { |
c19d1205 ZW |
5092 | inst.reloc.type = BFD_RELOC_ARM_SMI; |
5093 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
5094 | } |
5095 | ||
09d92015 | 5096 | static void |
c19d1205 | 5097 | do_swi (void) |
09d92015 | 5098 | { |
c19d1205 ZW |
5099 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
5100 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
5101 | } |
5102 | ||
c19d1205 ZW |
5103 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
5104 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
5105 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
5106 | Error if any register is R15. */ | |
e16bb312 | 5107 | |
c19d1205 ZW |
5108 | static void |
5109 | do_smla (void) | |
e16bb312 | 5110 | { |
c19d1205 ZW |
5111 | inst.instruction |= inst.operands[0].reg << 16; |
5112 | inst.instruction |= inst.operands[1].reg; | |
5113 | inst.instruction |= inst.operands[2].reg << 8; | |
5114 | inst.instruction |= inst.operands[3].reg << 12; | |
5115 | } | |
a737bd4d | 5116 | |
c19d1205 ZW |
5117 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
5118 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
5119 | Error if any register is R15. | |
5120 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 5121 | |
c19d1205 ZW |
5122 | static void |
5123 | do_smlal (void) | |
5124 | { | |
5125 | inst.instruction |= inst.operands[0].reg << 12; | |
5126 | inst.instruction |= inst.operands[1].reg << 16; | |
5127 | inst.instruction |= inst.operands[2].reg; | |
5128 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 5129 | |
c19d1205 ZW |
5130 | if (inst.operands[0].reg == inst.operands[1].reg) |
5131 | as_tsktsk (_("rdhi and rdlo must be different")); | |
5132 | } | |
a737bd4d | 5133 | |
c19d1205 ZW |
5134 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
5135 | SMULxy{cond} Rd,Rm,Rs | |
5136 | Error if any register is R15. */ | |
a737bd4d | 5137 | |
c19d1205 ZW |
5138 | static void |
5139 | do_smul (void) | |
5140 | { | |
5141 | inst.instruction |= inst.operands[0].reg << 16; | |
5142 | inst.instruction |= inst.operands[1].reg; | |
5143 | inst.instruction |= inst.operands[2].reg << 8; | |
5144 | } | |
a737bd4d | 5145 | |
c19d1205 | 5146 | /* ARM V6 srs (argument parse). */ |
a737bd4d | 5147 | |
c19d1205 ZW |
5148 | static void |
5149 | do_srs (void) | |
5150 | { | |
5151 | inst.instruction |= inst.operands[0].imm; | |
5152 | if (inst.operands[0].writeback) | |
5153 | inst.instruction |= WRITE_BACK; | |
5154 | } | |
a737bd4d | 5155 | |
c19d1205 | 5156 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 5157 | |
c19d1205 ZW |
5158 | static void |
5159 | do_strex (void) | |
5160 | { | |
5161 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
5162 | || inst.operands[2].postind || inst.operands[2].writeback | |
5163 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
5164 | || inst.operands[2].negative, | |
5165 | _("instruction does not accept this addressing mode")); | |
e16bb312 | 5166 | |
c19d1205 | 5167 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
a737bd4d | 5168 | |
c19d1205 ZW |
5169 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5170 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 5171 | |
c19d1205 ZW |
5172 | constraint (inst.reloc.exp.X_op != O_constant |
5173 | || inst.reloc.exp.X_add_number != 0, | |
5174 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 5175 | |
c19d1205 ZW |
5176 | inst.instruction |= inst.operands[0].reg << 12; |
5177 | inst.instruction |= inst.operands[1].reg; | |
5178 | inst.instruction |= inst.operands[2].reg << 16; | |
5179 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
5180 | } |
5181 | ||
5182 | static void | |
c19d1205 | 5183 | do_strexd (void) |
e16bb312 | 5184 | { |
c19d1205 ZW |
5185 | constraint (inst.operands[1].reg % 2 != 0, |
5186 | _("even register required")); | |
5187 | constraint (inst.operands[2].present | |
5188 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
5189 | _("can only store two consecutive registers")); | |
5190 | /* If op 2 were present and equal to PC, this function wouldn't | |
5191 | have been called in the first place. */ | |
5192 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 5193 | |
c19d1205 ZW |
5194 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5195 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
5196 | || inst.operands[0].reg == inst.operands[3].reg, | |
5197 | BAD_OVERLAP); | |
e16bb312 | 5198 | |
c19d1205 ZW |
5199 | inst.instruction |= inst.operands[0].reg << 12; |
5200 | inst.instruction |= inst.operands[1].reg; | |
5201 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
5202 | } |
5203 | ||
c19d1205 ZW |
5204 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
5205 | extends it to 32-bits, and adds the result to a value in another | |
5206 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
5207 | before extracting the 16-bit value. | |
5208 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
5209 | Condition defaults to COND_ALWAYS. | |
5210 | Error if any register uses R15. */ | |
5211 | ||
e16bb312 | 5212 | static void |
c19d1205 | 5213 | do_sxtah (void) |
e16bb312 | 5214 | { |
c19d1205 ZW |
5215 | inst.instruction |= inst.operands[0].reg << 12; |
5216 | inst.instruction |= inst.operands[1].reg << 16; | |
5217 | inst.instruction |= inst.operands[2].reg; | |
5218 | inst.instruction |= inst.operands[3].imm << 10; | |
5219 | } | |
e16bb312 | 5220 | |
c19d1205 | 5221 | /* ARM V6 SXTH. |
e16bb312 | 5222 | |
c19d1205 ZW |
5223 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
5224 | Condition defaults to COND_ALWAYS. | |
5225 | Error if any register uses R15. */ | |
e16bb312 NC |
5226 | |
5227 | static void | |
c19d1205 | 5228 | do_sxth (void) |
e16bb312 | 5229 | { |
c19d1205 ZW |
5230 | inst.instruction |= inst.operands[0].reg << 12; |
5231 | inst.instruction |= inst.operands[1].reg; | |
5232 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 5233 | } |
c19d1205 ZW |
5234 | \f |
5235 | /* VFP instructions. In a logical order: SP variant first, monad | |
5236 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
5237 | |
5238 | static void | |
c19d1205 | 5239 | do_vfp_sp_monadic (void) |
e16bb312 | 5240 | { |
c19d1205 ZW |
5241 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5242 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5243 | } |
5244 | ||
5245 | static void | |
c19d1205 | 5246 | do_vfp_sp_dyadic (void) |
e16bb312 | 5247 | { |
c19d1205 ZW |
5248 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5249 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
5250 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5251 | } |
5252 | ||
5253 | static void | |
c19d1205 | 5254 | do_vfp_sp_compare_z (void) |
e16bb312 | 5255 | { |
c19d1205 | 5256 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
5257 | } |
5258 | ||
5259 | static void | |
c19d1205 | 5260 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 5261 | { |
c19d1205 ZW |
5262 | inst.instruction |= inst.operands[0].reg << 12; |
5263 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5264 | } |
5265 | ||
5266 | static void | |
c19d1205 | 5267 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 5268 | { |
c19d1205 ZW |
5269 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5270 | inst.instruction |= inst.operands[1].reg; | |
e16bb312 NC |
5271 | } |
5272 | ||
5273 | static void | |
c19d1205 | 5274 | do_vfp_reg_from_sp (void) |
e16bb312 | 5275 | { |
c19d1205 ZW |
5276 | inst.instruction |= inst.operands[0].reg << 12; |
5277 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
e16bb312 NC |
5278 | } |
5279 | ||
5280 | static void | |
c19d1205 | 5281 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 5282 | { |
c19d1205 ZW |
5283 | constraint (inst.operands[2].imm != 2, |
5284 | _("only two consecutive VFP SP registers allowed here")); | |
5285 | inst.instruction |= inst.operands[0].reg << 12; | |
5286 | inst.instruction |= inst.operands[1].reg << 16; | |
5287 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5288 | } |
5289 | ||
5290 | static void | |
c19d1205 | 5291 | do_vfp_sp_from_reg (void) |
e16bb312 | 5292 | { |
c19d1205 ZW |
5293 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn); |
5294 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 NC |
5295 | } |
5296 | ||
5297 | static void | |
c19d1205 | 5298 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 5299 | { |
c19d1205 ZW |
5300 | constraint (inst.operands[0].imm != 2, |
5301 | _("only two consecutive VFP SP registers allowed here")); | |
5302 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm); | |
5303 | inst.instruction |= inst.operands[1].reg << 12; | |
5304 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
5305 | } |
5306 | ||
5307 | static void | |
c19d1205 | 5308 | do_vfp_sp_ldst (void) |
e16bb312 | 5309 | { |
c19d1205 ZW |
5310 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5311 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5312 | } |
5313 | ||
5314 | static void | |
c19d1205 | 5315 | do_vfp_dp_ldst (void) |
e16bb312 | 5316 | { |
c19d1205 ZW |
5317 | inst.instruction |= inst.operands[0].reg << 12; |
5318 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5319 | } |
5320 | ||
c19d1205 | 5321 | |
e16bb312 | 5322 | static void |
c19d1205 | 5323 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5324 | { |
c19d1205 ZW |
5325 | if (inst.operands[0].writeback) |
5326 | inst.instruction |= WRITE_BACK; | |
5327 | else | |
5328 | constraint (ldstm_type != VFP_LDSTMIA, | |
5329 | _("this addressing mode requires base-register writeback")); | |
5330 | inst.instruction |= inst.operands[0].reg << 16; | |
5331 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd); | |
5332 | inst.instruction |= inst.operands[1].imm; | |
e16bb312 NC |
5333 | } |
5334 | ||
5335 | static void | |
c19d1205 | 5336 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5337 | { |
c19d1205 | 5338 | int count; |
e16bb312 | 5339 | |
c19d1205 ZW |
5340 | if (inst.operands[0].writeback) |
5341 | inst.instruction |= WRITE_BACK; | |
5342 | else | |
5343 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
5344 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 5345 | |
c19d1205 ZW |
5346 | inst.instruction |= inst.operands[0].reg << 16; |
5347 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 | 5348 | |
c19d1205 ZW |
5349 | count = inst.operands[1].imm << 1; |
5350 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
5351 | count += 1; | |
e16bb312 | 5352 | |
c19d1205 | 5353 | inst.instruction |= count; |
e16bb312 NC |
5354 | } |
5355 | ||
5356 | static void | |
c19d1205 | 5357 | do_vfp_sp_ldstmia (void) |
e16bb312 | 5358 | { |
c19d1205 | 5359 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5360 | } |
5361 | ||
5362 | static void | |
c19d1205 | 5363 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 5364 | { |
c19d1205 | 5365 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5366 | } |
5367 | ||
5368 | static void | |
c19d1205 | 5369 | do_vfp_dp_ldstmia (void) |
e16bb312 | 5370 | { |
c19d1205 | 5371 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5372 | } |
5373 | ||
5374 | static void | |
c19d1205 | 5375 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 5376 | { |
c19d1205 | 5377 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5378 | } |
5379 | ||
5380 | static void | |
c19d1205 | 5381 | do_vfp_xp_ldstmia (void) |
e16bb312 | 5382 | { |
c19d1205 ZW |
5383 | vfp_dp_ldstm (VFP_LDSTMIAX); |
5384 | } | |
e16bb312 | 5385 | |
c19d1205 ZW |
5386 | static void |
5387 | do_vfp_xp_ldstmdb (void) | |
5388 | { | |
5389 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 5390 | } |
c19d1205 ZW |
5391 | \f |
5392 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 5393 | |
c19d1205 ZW |
5394 | static void |
5395 | do_fpa_cmp (void) | |
5396 | { | |
5397 | inst.instruction |= inst.operands[0].reg << 16; | |
5398 | inst.instruction |= inst.operands[1].reg; | |
5399 | } | |
b99bd4ef NC |
5400 | |
5401 | static void | |
c19d1205 | 5402 | do_fpa_ldmstm (void) |
b99bd4ef | 5403 | { |
c19d1205 ZW |
5404 | inst.instruction |= inst.operands[0].reg << 12; |
5405 | switch (inst.operands[1].imm) | |
5406 | { | |
5407 | case 1: inst.instruction |= CP_T_X; break; | |
5408 | case 2: inst.instruction |= CP_T_Y; break; | |
5409 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
5410 | case 4: break; | |
5411 | default: abort (); | |
5412 | } | |
b99bd4ef | 5413 | |
c19d1205 ZW |
5414 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
5415 | { | |
5416 | /* The instruction specified "ea" or "fd", so we can only accept | |
5417 | [Rn]{!}. The instruction does not really support stacking or | |
5418 | unstacking, so we have to emulate these by setting appropriate | |
5419 | bits and offsets. */ | |
5420 | constraint (inst.reloc.exp.X_op != O_constant | |
5421 | || inst.reloc.exp.X_add_number != 0, | |
5422 | _("this instruction does not support indexing")); | |
b99bd4ef | 5423 | |
c19d1205 ZW |
5424 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
5425 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 5426 | |
c19d1205 ZW |
5427 | if (!(inst.instruction & INDEX_UP)) |
5428 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 5429 | |
c19d1205 ZW |
5430 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
5431 | { | |
5432 | inst.operands[2].preind = 0; | |
5433 | inst.operands[2].postind = 1; | |
5434 | } | |
5435 | } | |
b99bd4ef | 5436 | |
c19d1205 | 5437 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 5438 | } |
c19d1205 ZW |
5439 | \f |
5440 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 5441 | |
c19d1205 ZW |
5442 | static void |
5443 | do_iwmmxt_tandorc (void) | |
5444 | { | |
5445 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
5446 | } | |
b99bd4ef | 5447 | |
c19d1205 ZW |
5448 | static void |
5449 | do_iwmmxt_textrc (void) | |
5450 | { | |
5451 | inst.instruction |= inst.operands[0].reg << 12; | |
5452 | inst.instruction |= inst.operands[1].imm; | |
5453 | } | |
b99bd4ef NC |
5454 | |
5455 | static void | |
c19d1205 | 5456 | do_iwmmxt_textrm (void) |
b99bd4ef | 5457 | { |
c19d1205 ZW |
5458 | inst.instruction |= inst.operands[0].reg << 12; |
5459 | inst.instruction |= inst.operands[1].reg << 16; | |
5460 | inst.instruction |= inst.operands[2].imm; | |
5461 | } | |
b99bd4ef | 5462 | |
c19d1205 ZW |
5463 | static void |
5464 | do_iwmmxt_tinsr (void) | |
5465 | { | |
5466 | inst.instruction |= inst.operands[0].reg << 16; | |
5467 | inst.instruction |= inst.operands[1].reg << 12; | |
5468 | inst.instruction |= inst.operands[2].imm; | |
5469 | } | |
b99bd4ef | 5470 | |
c19d1205 ZW |
5471 | static void |
5472 | do_iwmmxt_tmia (void) | |
5473 | { | |
5474 | inst.instruction |= inst.operands[0].reg << 5; | |
5475 | inst.instruction |= inst.operands[1].reg; | |
5476 | inst.instruction |= inst.operands[2].reg << 12; | |
5477 | } | |
b99bd4ef | 5478 | |
c19d1205 ZW |
5479 | static void |
5480 | do_iwmmxt_waligni (void) | |
5481 | { | |
5482 | inst.instruction |= inst.operands[0].reg << 12; | |
5483 | inst.instruction |= inst.operands[1].reg << 16; | |
5484 | inst.instruction |= inst.operands[2].reg; | |
5485 | inst.instruction |= inst.operands[3].imm << 20; | |
5486 | } | |
b99bd4ef | 5487 | |
c19d1205 ZW |
5488 | static void |
5489 | do_iwmmxt_wmov (void) | |
5490 | { | |
5491 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
5492 | inst.instruction |= inst.operands[0].reg << 12; | |
5493 | inst.instruction |= inst.operands[1].reg << 16; | |
5494 | inst.instruction |= inst.operands[1].reg; | |
5495 | } | |
b99bd4ef | 5496 | |
c19d1205 ZW |
5497 | static void |
5498 | do_iwmmxt_wldstbh (void) | |
5499 | { | |
8f06b2d8 | 5500 | int reloc; |
c19d1205 ZW |
5501 | inst.instruction |= inst.operands[0].reg << 12; |
5502 | inst.reloc.exp.X_add_number *= 4; | |
8f06b2d8 PB |
5503 | if (thumb_mode) |
5504 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
5505 | else | |
5506 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
5507 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
5508 | } |
5509 | ||
c19d1205 ZW |
5510 | static void |
5511 | do_iwmmxt_wldstw (void) | |
5512 | { | |
5513 | /* RIWR_RIWC clears .isreg for a control register. */ | |
5514 | if (!inst.operands[0].isreg) | |
5515 | { | |
5516 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
5517 | inst.instruction |= 0xf0000000; | |
5518 | } | |
b99bd4ef | 5519 | |
c19d1205 ZW |
5520 | inst.instruction |= inst.operands[0].reg << 12; |
5521 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
5522 | } | |
b99bd4ef NC |
5523 | |
5524 | static void | |
c19d1205 | 5525 | do_iwmmxt_wldstd (void) |
b99bd4ef | 5526 | { |
c19d1205 | 5527 | inst.instruction |= inst.operands[0].reg << 12; |
f2184508 | 5528 | encode_arm_cp_address (1, TRUE, FALSE, 0); |
c19d1205 | 5529 | } |
b99bd4ef | 5530 | |
c19d1205 ZW |
5531 | static void |
5532 | do_iwmmxt_wshufh (void) | |
5533 | { | |
5534 | inst.instruction |= inst.operands[0].reg << 12; | |
5535 | inst.instruction |= inst.operands[1].reg << 16; | |
5536 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
5537 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
5538 | } | |
b99bd4ef | 5539 | |
c19d1205 ZW |
5540 | static void |
5541 | do_iwmmxt_wzero (void) | |
5542 | { | |
5543 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
5544 | inst.instruction |= inst.operands[0].reg; | |
5545 | inst.instruction |= inst.operands[0].reg << 12; | |
5546 | inst.instruction |= inst.operands[0].reg << 16; | |
5547 | } | |
5548 | \f | |
5549 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
5550 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 5551 | |
c19d1205 | 5552 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 5553 | |
c19d1205 ZW |
5554 | static void |
5555 | do_mav_triple (void) | |
5556 | { | |
5557 | inst.instruction |= inst.operands[0].reg << 16; | |
5558 | inst.instruction |= inst.operands[1].reg; | |
5559 | inst.instruction |= inst.operands[2].reg << 12; | |
5560 | } | |
b99bd4ef | 5561 | |
c19d1205 ZW |
5562 | /* Insns like "foo W,X,Y,Z". |
5563 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 5564 | |
c19d1205 ZW |
5565 | static void |
5566 | do_mav_quad (void) | |
5567 | { | |
5568 | inst.instruction |= inst.operands[0].reg << 5; | |
5569 | inst.instruction |= inst.operands[1].reg << 12; | |
5570 | inst.instruction |= inst.operands[2].reg << 16; | |
5571 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
5572 | } |
5573 | ||
c19d1205 ZW |
5574 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
5575 | static void | |
5576 | do_mav_dspsc (void) | |
a737bd4d | 5577 | { |
c19d1205 ZW |
5578 | inst.instruction |= inst.operands[1].reg << 12; |
5579 | } | |
a737bd4d | 5580 | |
c19d1205 ZW |
5581 | /* Maverick shift immediate instructions. |
5582 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
5583 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 5584 | |
c19d1205 ZW |
5585 | static void |
5586 | do_mav_shift (void) | |
5587 | { | |
5588 | int imm = inst.operands[2].imm; | |
a737bd4d | 5589 | |
c19d1205 ZW |
5590 | inst.instruction |= inst.operands[0].reg << 12; |
5591 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 5592 | |
c19d1205 ZW |
5593 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
5594 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
5595 | Bit 4 should be 0. */ | |
5596 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 5597 | |
c19d1205 ZW |
5598 | inst.instruction |= imm; |
5599 | } | |
5600 | \f | |
5601 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 5602 | |
c19d1205 ZW |
5603 | /* Xscale multiply-accumulate (argument parse) |
5604 | MIAcc acc0,Rm,Rs | |
5605 | MIAPHcc acc0,Rm,Rs | |
5606 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 5607 | |
c19d1205 ZW |
5608 | static void |
5609 | do_xsc_mia (void) | |
5610 | { | |
5611 | inst.instruction |= inst.operands[1].reg; | |
5612 | inst.instruction |= inst.operands[2].reg << 12; | |
5613 | } | |
a737bd4d | 5614 | |
c19d1205 | 5615 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 5616 | |
c19d1205 | 5617 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 5618 | |
c19d1205 ZW |
5619 | static void |
5620 | do_xsc_mar (void) | |
5621 | { | |
5622 | inst.instruction |= inst.operands[1].reg << 12; | |
5623 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
5624 | } |
5625 | ||
c19d1205 | 5626 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 5627 | |
c19d1205 | 5628 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
5629 | |
5630 | static void | |
c19d1205 | 5631 | do_xsc_mra (void) |
b99bd4ef | 5632 | { |
c19d1205 ZW |
5633 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
5634 | inst.instruction |= inst.operands[0].reg << 12; | |
5635 | inst.instruction |= inst.operands[1].reg << 16; | |
5636 | } | |
5637 | \f | |
5638 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 5639 | |
c19d1205 ZW |
5640 | /* inst.operands[i] is a shifted-register operand; encode |
5641 | it into inst.instruction in the format used by Thumb32. */ | |
5642 | ||
5643 | static void | |
5644 | encode_thumb32_shifted_operand (int i) | |
5645 | { | |
5646 | unsigned int value = inst.reloc.exp.X_add_number; | |
5647 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 5648 | |
9c3c69f2 PB |
5649 | constraint (inst.operands[i].immisreg, |
5650 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
5651 | inst.instruction |= inst.operands[i].reg; |
5652 | if (shift == SHIFT_RRX) | |
5653 | inst.instruction |= SHIFT_ROR << 4; | |
5654 | else | |
b99bd4ef | 5655 | { |
c19d1205 ZW |
5656 | constraint (inst.reloc.exp.X_op != O_constant, |
5657 | _("expression too complex")); | |
5658 | ||
5659 | constraint (value > 32 | |
5660 | || (value == 32 && (shift == SHIFT_LSL | |
5661 | || shift == SHIFT_ROR)), | |
5662 | _("shift expression is too large")); | |
5663 | ||
5664 | if (value == 0) | |
5665 | shift = SHIFT_LSL; | |
5666 | else if (value == 32) | |
5667 | value = 0; | |
5668 | ||
5669 | inst.instruction |= shift << 4; | |
5670 | inst.instruction |= (value & 0x1c) << 10; | |
5671 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 5672 | } |
c19d1205 | 5673 | } |
b99bd4ef | 5674 | |
b99bd4ef | 5675 | |
c19d1205 ZW |
5676 | /* inst.operands[i] was set up by parse_address. Encode it into a |
5677 | Thumb32 format load or store instruction. Reject forms that cannot | |
5678 | be used with such instructions. If is_t is true, reject forms that | |
5679 | cannot be used with a T instruction; if is_d is true, reject forms | |
5680 | that cannot be used with a D instruction. */ | |
b99bd4ef | 5681 | |
c19d1205 ZW |
5682 | static void |
5683 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
5684 | { | |
5685 | bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); | |
5686 | ||
5687 | constraint (!inst.operands[i].isreg, | |
5688 | _("Thumb does not support the ldr =N pseudo-operation")); | |
b99bd4ef | 5689 | |
c19d1205 ZW |
5690 | inst.instruction |= inst.operands[i].reg << 16; |
5691 | if (inst.operands[i].immisreg) | |
b99bd4ef | 5692 | { |
c19d1205 ZW |
5693 | constraint (is_pc, _("cannot use register index with PC-relative addressing")); |
5694 | constraint (is_t || is_d, _("cannot use register index with this instruction")); | |
5695 | constraint (inst.operands[i].negative, | |
5696 | _("Thumb does not support negative register indexing")); | |
5697 | constraint (inst.operands[i].postind, | |
5698 | _("Thumb does not support register post-indexing")); | |
5699 | constraint (inst.operands[i].writeback, | |
5700 | _("Thumb does not support register indexing with writeback")); | |
5701 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
5702 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 5703 | |
c19d1205 ZW |
5704 | inst.instruction |= inst.operands[1].imm; |
5705 | if (inst.operands[i].shifted) | |
b99bd4ef | 5706 | { |
c19d1205 ZW |
5707 | constraint (inst.reloc.exp.X_op != O_constant, |
5708 | _("expression too complex")); | |
9c3c69f2 PB |
5709 | constraint (inst.reloc.exp.X_add_number < 0 |
5710 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 5711 | _("shift out of range")); |
9c3c69f2 | 5712 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
5713 | } |
5714 | inst.reloc.type = BFD_RELOC_UNUSED; | |
5715 | } | |
5716 | else if (inst.operands[i].preind) | |
5717 | { | |
5718 | constraint (is_pc && inst.operands[i].writeback, | |
5719 | _("cannot use writeback with PC-relative addressing")); | |
5720 | constraint (is_t && inst.operands[1].writeback, | |
5721 | _("cannot use writeback with this instruction")); | |
5722 | ||
5723 | if (is_d) | |
5724 | { | |
5725 | inst.instruction |= 0x01000000; | |
5726 | if (inst.operands[i].writeback) | |
5727 | inst.instruction |= 0x00200000; | |
b99bd4ef | 5728 | } |
c19d1205 | 5729 | else |
b99bd4ef | 5730 | { |
c19d1205 ZW |
5731 | inst.instruction |= 0x00000c00; |
5732 | if (inst.operands[i].writeback) | |
5733 | inst.instruction |= 0x00000100; | |
b99bd4ef | 5734 | } |
c19d1205 | 5735 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 5736 | } |
c19d1205 | 5737 | else if (inst.operands[i].postind) |
b99bd4ef | 5738 | { |
c19d1205 ZW |
5739 | assert (inst.operands[i].writeback); |
5740 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); | |
5741 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
5742 | ||
5743 | if (is_d) | |
5744 | inst.instruction |= 0x00200000; | |
5745 | else | |
5746 | inst.instruction |= 0x00000900; | |
5747 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
5748 | } | |
5749 | else /* unindexed - only for coprocessor */ | |
5750 | inst.error = _("instruction does not accept unindexed addressing"); | |
5751 | } | |
5752 | ||
5753 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
5754 | encodings (the latter only in post-V6T2 cores). The index is the | |
5755 | value used in the insns table below. When there is more than one | |
5756 | possible 16-bit encoding for the instruction, this table always | |
5757 | holds variant (1). */ | |
5758 | #define T16_32_TAB \ | |
5759 | X(adc, 4140, eb400000), \ | |
5760 | X(adcs, 4140, eb500000), \ | |
5761 | X(add, 1c00, eb000000), \ | |
5762 | X(adds, 1c00, eb100000), \ | |
e9f89963 | 5763 | X(adr, 000f, f20f0000), \ |
c19d1205 ZW |
5764 | X(and, 4000, ea000000), \ |
5765 | X(ands, 4000, ea100000), \ | |
5766 | X(asr, 1000, fa40f000), \ | |
5767 | X(asrs, 1000, fa50f000), \ | |
5768 | X(bic, 4380, ea200000), \ | |
5769 | X(bics, 4380, ea300000), \ | |
5770 | X(cmn, 42c0, eb100f00), \ | |
5771 | X(cmp, 2800, ebb00f00), \ | |
5772 | X(cpsie, b660, f3af8400), \ | |
5773 | X(cpsid, b670, f3af8600), \ | |
5774 | X(cpy, 4600, ea4f0000), \ | |
5775 | X(eor, 4040, ea800000), \ | |
5776 | X(eors, 4040, ea900000), \ | |
5777 | X(ldmia, c800, e8900000), \ | |
5778 | X(ldr, 6800, f8500000), \ | |
5779 | X(ldrb, 7800, f8100000), \ | |
5780 | X(ldrh, 8800, f8300000), \ | |
5781 | X(ldrsb, 5600, f9100000), \ | |
5782 | X(ldrsh, 5e00, f9300000), \ | |
5783 | X(lsl, 0000, fa00f000), \ | |
5784 | X(lsls, 0000, fa10f000), \ | |
5785 | X(lsr, 0800, fa20f000), \ | |
5786 | X(lsrs, 0800, fa30f000), \ | |
5787 | X(mov, 2000, ea4f0000), \ | |
5788 | X(movs, 2000, ea5f0000), \ | |
5789 | X(mul, 4340, fb00f000), \ | |
5790 | X(muls, 4340, ffffffff), /* no 32b muls */ \ | |
5791 | X(mvn, 43c0, ea6f0000), \ | |
5792 | X(mvns, 43c0, ea7f0000), \ | |
5793 | X(neg, 4240, f1c00000), /* rsb #0 */ \ | |
5794 | X(negs, 4240, f1d00000), /* rsbs #0 */ \ | |
5795 | X(orr, 4300, ea400000), \ | |
5796 | X(orrs, 4300, ea500000), \ | |
e9f89963 PB |
5797 | X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
5798 | X(push, b400, e92d0000), /* stmdb sp!,... */ \ | |
c19d1205 ZW |
5799 | X(rev, ba00, fa90f080), \ |
5800 | X(rev16, ba40, fa90f090), \ | |
5801 | X(revsh, bac0, fa90f0b0), \ | |
5802 | X(ror, 41c0, fa60f000), \ | |
5803 | X(rors, 41c0, fa70f000), \ | |
5804 | X(sbc, 4180, eb600000), \ | |
5805 | X(sbcs, 4180, eb700000), \ | |
5806 | X(stmia, c000, e8800000), \ | |
5807 | X(str, 6000, f8400000), \ | |
5808 | X(strb, 7000, f8000000), \ | |
5809 | X(strh, 8000, f8200000), \ | |
5810 | X(sub, 1e00, eba00000), \ | |
5811 | X(subs, 1e00, ebb00000), \ | |
5812 | X(sxtb, b240, fa4ff080), \ | |
5813 | X(sxth, b200, fa0ff080), \ | |
5814 | X(tst, 4200, ea100f00), \ | |
5815 | X(uxtb, b2c0, fa5ff080), \ | |
5816 | X(uxth, b280, fa1ff080), \ | |
5817 | X(nop, bf00, f3af8000), \ | |
5818 | X(yield, bf10, f3af8001), \ | |
5819 | X(wfe, bf20, f3af8002), \ | |
5820 | X(wfi, bf30, f3af8003), \ | |
5821 | X(sev, bf40, f3af9004), /* typo, 8004? */ | |
5822 | ||
5823 | /* To catch errors in encoding functions, the codes are all offset by | |
5824 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
5825 | as 16-bit instructions. */ | |
5826 | #define X(a,b,c) T_MNEM_##a | |
5827 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; | |
5828 | #undef X | |
5829 | ||
5830 | #define X(a,b,c) 0x##b | |
5831 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
5832 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
5833 | #undef X | |
5834 | ||
5835 | #define X(a,b,c) 0x##c | |
5836 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
5837 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) | |
5838 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
5839 | #undef X | |
5840 | #undef T16_32_TAB | |
5841 | ||
5842 | /* Thumb instruction encoders, in alphabetical order. */ | |
5843 | ||
92e90b6e PB |
5844 | /* ADDW or SUBW. */ |
5845 | static void | |
5846 | do_t_add_sub_w (void) | |
5847 | { | |
5848 | int Rd, Rn; | |
5849 | ||
5850 | Rd = inst.operands[0].reg; | |
5851 | Rn = inst.operands[1].reg; | |
5852 | ||
5853 | constraint (Rd == 15, _("PC not allowed as destination")); | |
5854 | inst.instruction |= (Rn << 16) | (Rd << 8); | |
5855 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
5856 | } | |
5857 | ||
c19d1205 ZW |
5858 | /* Parse an add or subtract instruction. We get here with inst.instruction |
5859 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
5860 | ||
5861 | static void | |
5862 | do_t_add_sub (void) | |
5863 | { | |
5864 | int Rd, Rs, Rn; | |
5865 | ||
5866 | Rd = inst.operands[0].reg; | |
5867 | Rs = (inst.operands[1].present | |
5868 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
5869 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
5870 | ||
5871 | if (unified_syntax) | |
5872 | { | |
5873 | if (!inst.operands[2].isreg) | |
b99bd4ef | 5874 | { |
e27ec89e PB |
5875 | /* ??? Convert large immediates to addw/subw. */ |
5876 | /* ??? 16-bit adds with small immediates. */ | |
c19d1205 ZW |
5877 | /* For an immediate, we always generate a 32-bit opcode; |
5878 | section relaxation will shrink it later if possible. */ | |
5879 | inst.instruction = THUMB_OP32 (inst.instruction); | |
5880 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
5881 | inst.instruction |= inst.operands[0].reg << 8; | |
5882 | inst.instruction |= inst.operands[1].reg << 16; | |
5883 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 5884 | } |
c19d1205 ZW |
5885 | else |
5886 | { | |
5887 | Rn = inst.operands[2].reg; | |
5888 | /* See if we can do this with a 16-bit instruction. */ | |
5889 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
5890 | { | |
e27ec89e PB |
5891 | bfd_boolean narrow; |
5892 | ||
5893 | if (inst.instruction == T_MNEM_adds | |
5894 | || inst.instruction == T_MNEM_subs) | |
5895 | narrow = (current_it_mask == 0); | |
5896 | else | |
5897 | narrow = (current_it_mask != 0); | |
5898 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
5899 | narrow = FALSE; | |
5900 | ||
5901 | if (narrow) | |
c19d1205 | 5902 | { |
e27ec89e PB |
5903 | inst.instruction = ((inst.instruction == T_MNEM_adds |
5904 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
5905 | ? T_OPCODE_ADD_R3 |
5906 | : T_OPCODE_SUB_R3); | |
5907 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
5908 | return; | |
5909 | } | |
b99bd4ef | 5910 | |
c19d1205 ZW |
5911 | if (inst.instruction == T_MNEM_add) |
5912 | { | |
5913 | if (Rd == Rs) | |
5914 | { | |
5915 | inst.instruction = T_OPCODE_ADD_HI; | |
5916 | inst.instruction |= (Rd & 8) << 4; | |
5917 | inst.instruction |= (Rd & 7); | |
5918 | inst.instruction |= Rn << 3; | |
5919 | return; | |
5920 | } | |
5921 | /* ... because addition is commutative! */ | |
5922 | else if (Rd == Rn) | |
5923 | { | |
5924 | inst.instruction = T_OPCODE_ADD_HI; | |
5925 | inst.instruction |= (Rd & 8) << 4; | |
5926 | inst.instruction |= (Rd & 7); | |
5927 | inst.instruction |= Rs << 3; | |
5928 | return; | |
5929 | } | |
5930 | } | |
5931 | } | |
5932 | /* If we get here, it can't be done in 16 bits. */ | |
5933 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
5934 | _("shift must be constant")); | |
5935 | inst.instruction = THUMB_OP32 (inst.instruction); | |
5936 | inst.instruction |= Rd << 8; | |
5937 | inst.instruction |= Rs << 16; | |
5938 | encode_thumb32_shifted_operand (2); | |
5939 | } | |
5940 | } | |
5941 | else | |
5942 | { | |
5943 | constraint (inst.instruction == T_MNEM_adds | |
5944 | || inst.instruction == T_MNEM_subs, | |
5945 | BAD_THUMB32); | |
b99bd4ef | 5946 | |
c19d1205 | 5947 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 5948 | { |
c19d1205 ZW |
5949 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
5950 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
5951 | BAD_HIREG); | |
5952 | ||
5953 | inst.instruction = (inst.instruction == T_MNEM_add | |
5954 | ? 0x0000 : 0x8000); | |
5955 | inst.instruction |= (Rd << 4) | Rs; | |
5956 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
5957 | return; |
5958 | } | |
5959 | ||
c19d1205 ZW |
5960 | Rn = inst.operands[2].reg; |
5961 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 5962 | |
c19d1205 ZW |
5963 | /* We now have Rd, Rs, and Rn set to registers. */ |
5964 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 5965 | { |
c19d1205 ZW |
5966 | /* Can't do this for SUB. */ |
5967 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
5968 | inst.instruction = T_OPCODE_ADD_HI; | |
5969 | inst.instruction |= (Rd & 8) << 4; | |
5970 | inst.instruction |= (Rd & 7); | |
5971 | if (Rs == Rd) | |
5972 | inst.instruction |= Rn << 3; | |
5973 | else if (Rn == Rd) | |
5974 | inst.instruction |= Rs << 3; | |
5975 | else | |
5976 | constraint (1, _("dest must overlap one source register")); | |
5977 | } | |
5978 | else | |
5979 | { | |
5980 | inst.instruction = (inst.instruction == T_MNEM_add | |
5981 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
5982 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 5983 | } |
b99bd4ef | 5984 | } |
b99bd4ef NC |
5985 | } |
5986 | ||
c19d1205 ZW |
5987 | static void |
5988 | do_t_adr (void) | |
5989 | { | |
e9f89963 PB |
5990 | if (unified_syntax && inst.size_req != 2) |
5991 | { | |
5992 | /* Always generate a 32-bit opcode; | |
5993 | section relaxation will shrink it later if possible. */ | |
5994 | inst.instruction = THUMB_OP32 (inst.instruction); | |
5995 | inst.instruction |= inst.operands[0].reg << 8; | |
5996 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; | |
5997 | inst.reloc.pc_rel = 1; | |
5998 | } | |
5999 | else | |
6000 | { | |
6001 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6002 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6003 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
6004 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 6005 | |
e9f89963 PB |
6006 | inst.instruction |= inst.operands[0].reg << 4; |
6007 | } | |
c19d1205 | 6008 | } |
b99bd4ef | 6009 | |
c19d1205 ZW |
6010 | /* Arithmetic instructions for which there is just one 16-bit |
6011 | instruction encoding, and it allows only two low registers. | |
6012 | For maximal compatibility with ARM syntax, we allow three register | |
6013 | operands even when Thumb-32 instructions are not available, as long | |
6014 | as the first two are identical. For instance, both "sbc r0,r1" and | |
6015 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 6016 | static void |
c19d1205 | 6017 | do_t_arit3 (void) |
b99bd4ef | 6018 | { |
c19d1205 | 6019 | int Rd, Rs, Rn; |
b99bd4ef | 6020 | |
c19d1205 ZW |
6021 | Rd = inst.operands[0].reg; |
6022 | Rs = (inst.operands[1].present | |
6023 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6024 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6025 | Rn = inst.operands[2].reg; | |
b99bd4ef | 6026 | |
c19d1205 | 6027 | if (unified_syntax) |
b99bd4ef | 6028 | { |
c19d1205 ZW |
6029 | if (!inst.operands[2].isreg) |
6030 | { | |
6031 | /* For an immediate, we always generate a 32-bit opcode; | |
6032 | section relaxation will shrink it later if possible. */ | |
6033 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6034 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6035 | inst.instruction |= Rd << 8; | |
6036 | inst.instruction |= Rs << 16; | |
6037 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6038 | } | |
6039 | else | |
6040 | { | |
e27ec89e PB |
6041 | bfd_boolean narrow; |
6042 | ||
c19d1205 | 6043 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6044 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6045 | narrow = current_it_mask == 0; | |
6046 | else | |
6047 | narrow = current_it_mask != 0; | |
6048 | ||
6049 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6050 | narrow = FALSE; | |
6051 | if (inst.operands[2].shifted) | |
6052 | narrow = FALSE; | |
6053 | if (inst.size_req == 4) | |
6054 | narrow = FALSE; | |
6055 | ||
6056 | if (narrow | |
c19d1205 ZW |
6057 | && Rd == Rs) |
6058 | { | |
6059 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6060 | inst.instruction |= Rd; | |
6061 | inst.instruction |= Rn << 3; | |
6062 | return; | |
6063 | } | |
b99bd4ef | 6064 | |
c19d1205 ZW |
6065 | /* If we get here, it can't be done in 16 bits. */ |
6066 | constraint (inst.operands[2].shifted | |
6067 | && inst.operands[2].immisreg, | |
6068 | _("shift must be constant")); | |
6069 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6070 | inst.instruction |= Rd << 8; | |
6071 | inst.instruction |= Rs << 16; | |
6072 | encode_thumb32_shifted_operand (2); | |
6073 | } | |
a737bd4d | 6074 | } |
c19d1205 | 6075 | else |
b99bd4ef | 6076 | { |
c19d1205 ZW |
6077 | /* On its face this is a lie - the instruction does set the |
6078 | flags. However, the only supported mnemonic in this mode | |
6079 | says it doesn't. */ | |
6080 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6081 | |
c19d1205 ZW |
6082 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6083 | _("unshifted register required")); | |
6084 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6085 | constraint (Rd != Rs, | |
6086 | _("dest and source1 must be the same register")); | |
a737bd4d | 6087 | |
c19d1205 ZW |
6088 | inst.instruction = THUMB_OP16 (inst.instruction); |
6089 | inst.instruction |= Rd; | |
6090 | inst.instruction |= Rn << 3; | |
b99bd4ef | 6091 | } |
a737bd4d | 6092 | } |
b99bd4ef | 6093 | |
c19d1205 ZW |
6094 | /* Similarly, but for instructions where the arithmetic operation is |
6095 | commutative, so we can allow either of them to be different from | |
6096 | the destination operand in a 16-bit instruction. For instance, all | |
6097 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
6098 | accepted. */ | |
6099 | static void | |
6100 | do_t_arit3c (void) | |
a737bd4d | 6101 | { |
c19d1205 | 6102 | int Rd, Rs, Rn; |
b99bd4ef | 6103 | |
c19d1205 ZW |
6104 | Rd = inst.operands[0].reg; |
6105 | Rs = (inst.operands[1].present | |
6106 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6107 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6108 | Rn = inst.operands[2].reg; | |
a737bd4d | 6109 | |
c19d1205 | 6110 | if (unified_syntax) |
a737bd4d | 6111 | { |
c19d1205 | 6112 | if (!inst.operands[2].isreg) |
b99bd4ef | 6113 | { |
c19d1205 ZW |
6114 | /* For an immediate, we always generate a 32-bit opcode; |
6115 | section relaxation will shrink it later if possible. */ | |
6116 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6117 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6118 | inst.instruction |= Rd << 8; | |
6119 | inst.instruction |= Rs << 16; | |
6120 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 6121 | } |
c19d1205 | 6122 | else |
a737bd4d | 6123 | { |
e27ec89e PB |
6124 | bfd_boolean narrow; |
6125 | ||
c19d1205 | 6126 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6127 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6128 | narrow = current_it_mask == 0; | |
6129 | else | |
6130 | narrow = current_it_mask != 0; | |
6131 | ||
6132 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6133 | narrow = FALSE; | |
6134 | if (inst.operands[2].shifted) | |
6135 | narrow = FALSE; | |
6136 | if (inst.size_req == 4) | |
6137 | narrow = FALSE; | |
6138 | ||
6139 | if (narrow) | |
a737bd4d | 6140 | { |
c19d1205 | 6141 | if (Rd == Rs) |
a737bd4d | 6142 | { |
c19d1205 ZW |
6143 | inst.instruction = THUMB_OP16 (inst.instruction); |
6144 | inst.instruction |= Rd; | |
6145 | inst.instruction |= Rn << 3; | |
6146 | return; | |
a737bd4d | 6147 | } |
c19d1205 | 6148 | if (Rd == Rn) |
a737bd4d | 6149 | { |
c19d1205 ZW |
6150 | inst.instruction = THUMB_OP16 (inst.instruction); |
6151 | inst.instruction |= Rd; | |
6152 | inst.instruction |= Rs << 3; | |
6153 | return; | |
a737bd4d NC |
6154 | } |
6155 | } | |
c19d1205 ZW |
6156 | |
6157 | /* If we get here, it can't be done in 16 bits. */ | |
6158 | constraint (inst.operands[2].shifted | |
6159 | && inst.operands[2].immisreg, | |
6160 | _("shift must be constant")); | |
6161 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6162 | inst.instruction |= Rd << 8; | |
6163 | inst.instruction |= Rs << 16; | |
6164 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 6165 | } |
b99bd4ef | 6166 | } |
c19d1205 ZW |
6167 | else |
6168 | { | |
6169 | /* On its face this is a lie - the instruction does set the | |
6170 | flags. However, the only supported mnemonic in this mode | |
6171 | says it doesn't. */ | |
6172 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6173 | |
c19d1205 ZW |
6174 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6175 | _("unshifted register required")); | |
6176 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6177 | ||
6178 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6179 | inst.instruction |= Rd; | |
6180 | ||
6181 | if (Rd == Rs) | |
6182 | inst.instruction |= Rn << 3; | |
6183 | else if (Rd == Rn) | |
6184 | inst.instruction |= Rs << 3; | |
6185 | else | |
6186 | constraint (1, _("dest must overlap one source register")); | |
6187 | } | |
a737bd4d NC |
6188 | } |
6189 | ||
c19d1205 ZW |
6190 | static void |
6191 | do_t_bfc (void) | |
a737bd4d | 6192 | { |
c19d1205 ZW |
6193 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
6194 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6195 | /* The instruction encoding stores the LSB and MSB, | |
6196 | not the LSB and width. */ | |
6197 | inst.instruction |= inst.operands[0].reg << 8; | |
6198 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; | |
6199 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
6200 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6201 | } |
6202 | ||
c19d1205 ZW |
6203 | static void |
6204 | do_t_bfi (void) | |
b99bd4ef | 6205 | { |
c19d1205 | 6206 | unsigned int msb; |
b99bd4ef | 6207 | |
c19d1205 ZW |
6208 | /* #0 in second position is alternative syntax for bfc, which is |
6209 | the same instruction but with REG_PC in the Rm field. */ | |
6210 | if (!inst.operands[1].isreg) | |
6211 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 6212 | |
c19d1205 ZW |
6213 | msb = inst.operands[2].imm + inst.operands[3].imm; |
6214 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6215 | /* The instruction encoding stores the LSB and MSB, | |
6216 | not the LSB and width. */ | |
6217 | inst.instruction |= inst.operands[0].reg << 8; | |
6218 | inst.instruction |= inst.operands[1].reg << 16; | |
6219 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6220 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6221 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6222 | } |
6223 | ||
c19d1205 ZW |
6224 | static void |
6225 | do_t_bfx (void) | |
b99bd4ef | 6226 | { |
c19d1205 ZW |
6227 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
6228 | _("bit-field extends past end of register")); | |
6229 | inst.instruction |= inst.operands[0].reg << 8; | |
6230 | inst.instruction |= inst.operands[1].reg << 16; | |
6231 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6232 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6233 | inst.instruction |= inst.operands[3].imm - 1; | |
6234 | } | |
b99bd4ef | 6235 | |
c19d1205 ZW |
6236 | /* ARM V5 Thumb BLX (argument parse) |
6237 | BLX <target_addr> which is BLX(1) | |
6238 | BLX <Rm> which is BLX(2) | |
6239 | Unfortunately, there are two different opcodes for this mnemonic. | |
6240 | So, the insns[].value is not used, and the code here zaps values | |
6241 | into inst.instruction. | |
b99bd4ef | 6242 | |
c19d1205 ZW |
6243 | ??? How to take advantage of the additional two bits of displacement |
6244 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 6245 | |
c19d1205 ZW |
6246 | static void |
6247 | do_t_blx (void) | |
6248 | { | |
6249 | if (inst.operands[0].isreg) | |
6250 | /* We have a register, so this is BLX(2). */ | |
6251 | inst.instruction |= inst.operands[0].reg << 3; | |
b99bd4ef NC |
6252 | else |
6253 | { | |
c19d1205 | 6254 | /* No register. This must be BLX(1). */ |
2fc8bdac | 6255 | inst.instruction = 0xf000e800; |
c19d1205 ZW |
6256 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; |
6257 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
6258 | } |
6259 | } | |
6260 | ||
c19d1205 ZW |
6261 | static void |
6262 | do_t_branch (void) | |
b99bd4ef | 6263 | { |
c19d1205 ZW |
6264 | if (unified_syntax && inst.size_req != 2) |
6265 | { | |
6266 | if (inst.cond == COND_ALWAYS) | |
6267 | { | |
2fc8bdac | 6268 | inst.instruction = 0xf000b000; |
c19d1205 ZW |
6269 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
6270 | } | |
6271 | else | |
6272 | { | |
6273 | assert (inst.cond != 0xF); | |
2fc8bdac | 6274 | inst.instruction = (inst.cond << 22) | 0xf0008000; |
c19d1205 ZW |
6275 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
6276 | } | |
6277 | } | |
b99bd4ef NC |
6278 | else |
6279 | { | |
c19d1205 ZW |
6280 | if (inst.cond == COND_ALWAYS) |
6281 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
6282 | else | |
b99bd4ef | 6283 | { |
2fc8bdac | 6284 | inst.instruction = 0xd000 | (inst.cond << 8); |
c19d1205 | 6285 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 6286 | } |
b99bd4ef | 6287 | } |
c19d1205 ZW |
6288 | |
6289 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
6290 | } |
6291 | ||
6292 | static void | |
c19d1205 | 6293 | do_t_bkpt (void) |
b99bd4ef | 6294 | { |
c19d1205 | 6295 | if (inst.operands[0].present) |
b99bd4ef | 6296 | { |
c19d1205 ZW |
6297 | constraint (inst.operands[0].imm > 255, |
6298 | _("immediate value out of range")); | |
6299 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 6300 | } |
b99bd4ef NC |
6301 | } |
6302 | ||
6303 | static void | |
c19d1205 | 6304 | do_t_branch23 (void) |
b99bd4ef | 6305 | { |
c19d1205 | 6306 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
6307 | inst.reloc.pc_rel = 1; |
6308 | ||
c19d1205 ZW |
6309 | /* If the destination of the branch is a defined symbol which does not have |
6310 | the THUMB_FUNC attribute, then we must be calling a function which has | |
6311 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
6312 | function and change the branch to refer to that function instead. */ | |
6313 | if ( inst.reloc.exp.X_op == O_symbol | |
6314 | && inst.reloc.exp.X_add_symbol != NULL | |
6315 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
6316 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
6317 | inst.reloc.exp.X_add_symbol = | |
6318 | find_real_start (inst.reloc.exp.X_add_symbol); | |
90e4755a RE |
6319 | } |
6320 | ||
6321 | static void | |
c19d1205 | 6322 | do_t_bx (void) |
90e4755a | 6323 | { |
c19d1205 ZW |
6324 | inst.instruction |= inst.operands[0].reg << 3; |
6325 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
6326 | should cause the alignment to be checked once it is known. This is | |
6327 | because BX PC only works if the instruction is word aligned. */ | |
6328 | } | |
90e4755a | 6329 | |
c19d1205 ZW |
6330 | static void |
6331 | do_t_bxj (void) | |
6332 | { | |
6333 | if (inst.operands[0].reg == REG_PC) | |
6334 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
90e4755a | 6335 | |
c19d1205 | 6336 | inst.instruction |= inst.operands[0].reg << 16; |
90e4755a RE |
6337 | } |
6338 | ||
6339 | static void | |
c19d1205 | 6340 | do_t_clz (void) |
90e4755a | 6341 | { |
c19d1205 ZW |
6342 | inst.instruction |= inst.operands[0].reg << 8; |
6343 | inst.instruction |= inst.operands[1].reg << 16; | |
6344 | inst.instruction |= inst.operands[1].reg; | |
6345 | } | |
90e4755a | 6346 | |
c19d1205 ZW |
6347 | static void |
6348 | do_t_cpsi (void) | |
6349 | { | |
6350 | if (unified_syntax | |
6351 | && (inst.operands[1].present || inst.size_req == 4)) | |
90e4755a | 6352 | { |
c19d1205 ZW |
6353 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
6354 | inst.instruction = 0xf3af8000; | |
6355 | inst.instruction |= imod << 9; | |
6356 | inst.instruction |= inst.operands[0].imm << 5; | |
6357 | if (inst.operands[1].present) | |
6358 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 6359 | } |
c19d1205 | 6360 | else |
90e4755a | 6361 | { |
c19d1205 ZW |
6362 | constraint (inst.operands[1].present, |
6363 | _("Thumb does not support the 2-argument " | |
6364 | "form of this instruction")); | |
6365 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 6366 | } |
90e4755a RE |
6367 | } |
6368 | ||
c19d1205 ZW |
6369 | /* THUMB CPY instruction (argument parse). */ |
6370 | ||
90e4755a | 6371 | static void |
c19d1205 | 6372 | do_t_cpy (void) |
90e4755a | 6373 | { |
c19d1205 | 6374 | if (inst.size_req == 4) |
90e4755a | 6375 | { |
c19d1205 ZW |
6376 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
6377 | inst.instruction |= inst.operands[0].reg << 8; | |
6378 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 6379 | } |
c19d1205 | 6380 | else |
90e4755a | 6381 | { |
c19d1205 ZW |
6382 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
6383 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6384 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 6385 | } |
90e4755a RE |
6386 | } |
6387 | ||
90e4755a | 6388 | static void |
c19d1205 | 6389 | do_t_czb (void) |
90e4755a | 6390 | { |
c19d1205 ZW |
6391 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6392 | inst.instruction |= inst.operands[0].reg; | |
6393 | inst.reloc.pc_rel = 1; | |
6394 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
6395 | } | |
90e4755a | 6396 | |
c19d1205 ZW |
6397 | static void |
6398 | do_t_hint (void) | |
6399 | { | |
6400 | if (unified_syntax && inst.size_req == 4) | |
6401 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6402 | else | |
6403 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6404 | } | |
90e4755a | 6405 | |
c19d1205 ZW |
6406 | static void |
6407 | do_t_it (void) | |
6408 | { | |
6409 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e PB |
6410 | |
6411 | current_it_mask = (inst.instruction & 0xf) | 0x10; | |
6412 | current_cc = cond; | |
6413 | ||
6414 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 6415 | if ((cond & 0x1) == 0x0) |
90e4755a | 6416 | { |
c19d1205 | 6417 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 6418 | |
c19d1205 ZW |
6419 | if ((mask & 0x7) == 0) |
6420 | /* no conversion needed */; | |
6421 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
6422 | mask ^= 0x8; |
6423 | else if ((mask & 0x1) == 0) | |
6424 | mask ^= 0xC; | |
c19d1205 | 6425 | else |
e27ec89e | 6426 | mask ^= 0xE; |
90e4755a | 6427 | |
e27ec89e PB |
6428 | inst.instruction &= 0xfff0; |
6429 | inst.instruction |= mask; | |
c19d1205 | 6430 | } |
90e4755a | 6431 | |
c19d1205 ZW |
6432 | inst.instruction |= cond << 4; |
6433 | } | |
90e4755a | 6434 | |
c19d1205 ZW |
6435 | static void |
6436 | do_t_ldmstm (void) | |
6437 | { | |
6438 | /* This really doesn't seem worth it. */ | |
6439 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
6440 | _("expression too complex")); | |
6441 | constraint (inst.operands[1].writeback, | |
6442 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 6443 | |
c19d1205 ZW |
6444 | if (unified_syntax) |
6445 | { | |
6446 | /* See if we can use a 16-bit instruction. */ | |
6447 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
6448 | && inst.size_req != 4 | |
6449 | && inst.operands[0].reg <= 7 | |
6450 | && !(inst.operands[1].imm & ~0xff) | |
6451 | && (inst.instruction == T_MNEM_stmia | |
6452 | ? inst.operands[0].writeback | |
6453 | : (inst.operands[0].writeback | |
6454 | == !(inst.operands[1].imm & (1 << inst.operands[0].reg))))) | |
90e4755a | 6455 | { |
c19d1205 ZW |
6456 | if (inst.instruction == T_MNEM_stmia |
6457 | && (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6458 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6459 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6460 | inst.operands[0].reg); | |
90e4755a | 6461 | |
c19d1205 ZW |
6462 | inst.instruction = THUMB_OP16 (inst.instruction); |
6463 | inst.instruction |= inst.operands[0].reg << 8; | |
6464 | inst.instruction |= inst.operands[1].imm; | |
6465 | } | |
6466 | else | |
6467 | { | |
6468 | if (inst.operands[1].imm & (1 << 13)) | |
6469 | as_warn (_("SP should not be in register list")); | |
6470 | if (inst.instruction == T_MNEM_stmia) | |
90e4755a | 6471 | { |
c19d1205 ZW |
6472 | if (inst.operands[1].imm & (1 << 15)) |
6473 | as_warn (_("PC should not be in register list")); | |
6474 | if (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6475 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6476 | inst.operands[0].reg); | |
90e4755a RE |
6477 | } |
6478 | else | |
6479 | { | |
c19d1205 ZW |
6480 | if (inst.operands[1].imm & (1 << 14) |
6481 | && inst.operands[1].imm & (1 << 15)) | |
6482 | as_warn (_("LR and PC should not both be in register list")); | |
6483 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6484 | && inst.operands[0].writeback) | |
6485 | as_warn (_("base register should not be in register list " | |
6486 | "when written back")); | |
90e4755a | 6487 | } |
c19d1205 ZW |
6488 | if (inst.instruction < 0xffff) |
6489 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6490 | inst.instruction |= inst.operands[0].reg << 16; | |
6491 | inst.instruction |= inst.operands[1].imm; | |
6492 | if (inst.operands[0].writeback) | |
6493 | inst.instruction |= WRITE_BACK; | |
90e4755a RE |
6494 | } |
6495 | } | |
c19d1205 | 6496 | else |
90e4755a | 6497 | { |
c19d1205 ZW |
6498 | constraint (inst.operands[0].reg > 7 |
6499 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
6500 | if (inst.instruction == T_MNEM_stmia) | |
f03698e6 | 6501 | { |
c19d1205 ZW |
6502 | if (!inst.operands[0].writeback) |
6503 | as_warn (_("this instruction will write back the base register")); | |
6504 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6505 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6506 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6507 | inst.operands[0].reg); | |
f03698e6 | 6508 | } |
c19d1205 | 6509 | else |
90e4755a | 6510 | { |
c19d1205 ZW |
6511 | if (!inst.operands[0].writeback |
6512 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6513 | as_warn (_("this instruction will write back the base register")); | |
6514 | else if (inst.operands[0].writeback | |
6515 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6516 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
6517 | } |
6518 | ||
c19d1205 ZW |
6519 | inst.instruction = THUMB_OP16 (inst.instruction); |
6520 | inst.instruction |= inst.operands[0].reg << 8; | |
6521 | inst.instruction |= inst.operands[1].imm; | |
6522 | } | |
6523 | } | |
e28cd48c | 6524 | |
c19d1205 ZW |
6525 | static void |
6526 | do_t_ldrex (void) | |
6527 | { | |
6528 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
6529 | || inst.operands[1].postind || inst.operands[1].writeback | |
6530 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
6531 | || inst.operands[1].negative, | |
6532 | _("instruction does not accept this addressing mode")); | |
e28cd48c | 6533 | |
c19d1205 ZW |
6534 | inst.instruction |= inst.operands[0].reg << 12; |
6535 | inst.instruction |= inst.operands[1].reg << 16; | |
6536 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
6537 | } | |
e28cd48c | 6538 | |
c19d1205 ZW |
6539 | static void |
6540 | do_t_ldrexd (void) | |
6541 | { | |
6542 | if (!inst.operands[1].present) | |
1cac9012 | 6543 | { |
c19d1205 ZW |
6544 | constraint (inst.operands[0].reg == REG_LR, |
6545 | _("r14 not allowed as first register " | |
6546 | "when second register is omitted")); | |
6547 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 6548 | } |
c19d1205 ZW |
6549 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
6550 | BAD_OVERLAP); | |
b99bd4ef | 6551 | |
c19d1205 ZW |
6552 | inst.instruction |= inst.operands[0].reg << 12; |
6553 | inst.instruction |= inst.operands[1].reg << 8; | |
6554 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
6555 | } |
6556 | ||
6557 | static void | |
c19d1205 | 6558 | do_t_ldst (void) |
b99bd4ef | 6559 | { |
c19d1205 | 6560 | if (unified_syntax) |
b99bd4ef | 6561 | { |
c19d1205 ZW |
6562 | /* Generation of 16-bit instructions for anything other than |
6563 | Rd, [Rn, Ri] is deferred to section relaxation time. */ | |
6564 | if (inst.operands[1].isreg && inst.operands[1].immisreg | |
6565 | && !inst.operands[1].shifted && !inst.operands[1].postind | |
6566 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
6567 | && inst.operands[1].reg <= 7 && inst.operands[1].imm <= 7 | |
6568 | && inst.instruction <= 0xffff) | |
6569 | { | |
6570 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6571 | goto op16; | |
6572 | } | |
6573 | ||
6574 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6575 | inst.instruction |= inst.operands[0].reg << 12; | |
6576 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
6577 | return; |
6578 | } | |
6579 | ||
c19d1205 ZW |
6580 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6581 | ||
6582 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 6583 | { |
c19d1205 ZW |
6584 | /* Only [Rn,Rm] is acceptable. */ |
6585 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
6586 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
6587 | || inst.operands[1].postind || inst.operands[1].shifted | |
6588 | || inst.operands[1].negative, | |
6589 | _("Thumb does not support this addressing mode")); | |
6590 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6591 | goto op16; | |
b99bd4ef | 6592 | } |
c19d1205 ZW |
6593 | |
6594 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6595 | if (!inst.operands[1].isreg) | |
6596 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
6597 | return; | |
b99bd4ef | 6598 | |
c19d1205 ZW |
6599 | constraint (!inst.operands[1].preind |
6600 | || inst.operands[1].shifted | |
6601 | || inst.operands[1].writeback, | |
6602 | _("Thumb does not support this addressing mode")); | |
6603 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 6604 | { |
c19d1205 ZW |
6605 | constraint (inst.instruction & 0x0600, |
6606 | _("byte or halfword not valid for base register")); | |
6607 | constraint (inst.operands[1].reg == REG_PC | |
6608 | && !(inst.instruction & THUMB_LOAD_BIT), | |
6609 | _("r15 based store not allowed")); | |
6610 | constraint (inst.operands[1].immisreg, | |
6611 | _("invalid base register for register offset")); | |
b99bd4ef | 6612 | |
c19d1205 ZW |
6613 | if (inst.operands[1].reg == REG_PC) |
6614 | inst.instruction = T_OPCODE_LDR_PC; | |
6615 | else if (inst.instruction & THUMB_LOAD_BIT) | |
6616 | inst.instruction = T_OPCODE_LDR_SP; | |
6617 | else | |
6618 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 6619 | |
c19d1205 ZW |
6620 | inst.instruction |= inst.operands[0].reg << 8; |
6621 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6622 | return; | |
6623 | } | |
90e4755a | 6624 | |
c19d1205 ZW |
6625 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
6626 | if (!inst.operands[1].immisreg) | |
6627 | { | |
6628 | /* Immediate offset. */ | |
6629 | inst.instruction |= inst.operands[0].reg; | |
6630 | inst.instruction |= inst.operands[1].reg << 3; | |
6631 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6632 | return; | |
6633 | } | |
90e4755a | 6634 | |
c19d1205 ZW |
6635 | /* Register offset. */ |
6636 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
6637 | constraint (inst.operands[1].negative, | |
6638 | _("Thumb does not support this addressing mode")); | |
90e4755a | 6639 | |
c19d1205 ZW |
6640 | op16: |
6641 | switch (inst.instruction) | |
6642 | { | |
6643 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
6644 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
6645 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
6646 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
6647 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
6648 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
6649 | case 0x5600 /* ldrsb */: | |
6650 | case 0x5e00 /* ldrsh */: break; | |
6651 | default: abort (); | |
6652 | } | |
90e4755a | 6653 | |
c19d1205 ZW |
6654 | inst.instruction |= inst.operands[0].reg; |
6655 | inst.instruction |= inst.operands[1].reg << 3; | |
6656 | inst.instruction |= inst.operands[1].imm << 6; | |
6657 | } | |
90e4755a | 6658 | |
c19d1205 ZW |
6659 | static void |
6660 | do_t_ldstd (void) | |
6661 | { | |
6662 | if (!inst.operands[1].present) | |
b99bd4ef | 6663 | { |
c19d1205 ZW |
6664 | inst.operands[1].reg = inst.operands[0].reg + 1; |
6665 | constraint (inst.operands[0].reg == REG_LR, | |
6666 | _("r14 not allowed here")); | |
b99bd4ef | 6667 | } |
c19d1205 ZW |
6668 | inst.instruction |= inst.operands[0].reg << 12; |
6669 | inst.instruction |= inst.operands[1].reg << 8; | |
6670 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
6671 | ||
b99bd4ef NC |
6672 | } |
6673 | ||
c19d1205 ZW |
6674 | static void |
6675 | do_t_ldstt (void) | |
6676 | { | |
6677 | inst.instruction |= inst.operands[0].reg << 12; | |
6678 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
6679 | } | |
a737bd4d | 6680 | |
b99bd4ef | 6681 | static void |
c19d1205 | 6682 | do_t_mla (void) |
b99bd4ef | 6683 | { |
c19d1205 ZW |
6684 | inst.instruction |= inst.operands[0].reg << 8; |
6685 | inst.instruction |= inst.operands[1].reg << 16; | |
6686 | inst.instruction |= inst.operands[2].reg; | |
6687 | inst.instruction |= inst.operands[3].reg << 12; | |
6688 | } | |
b99bd4ef | 6689 | |
c19d1205 ZW |
6690 | static void |
6691 | do_t_mlal (void) | |
6692 | { | |
6693 | inst.instruction |= inst.operands[0].reg << 12; | |
6694 | inst.instruction |= inst.operands[1].reg << 8; | |
6695 | inst.instruction |= inst.operands[2].reg << 16; | |
6696 | inst.instruction |= inst.operands[3].reg; | |
6697 | } | |
b99bd4ef | 6698 | |
c19d1205 ZW |
6699 | static void |
6700 | do_t_mov_cmp (void) | |
6701 | { | |
6702 | if (unified_syntax) | |
b99bd4ef | 6703 | { |
c19d1205 ZW |
6704 | int r0off = (inst.instruction == T_MNEM_mov |
6705 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
3d388997 PB |
6706 | bfd_boolean narrow; |
6707 | bfd_boolean low_regs; | |
6708 | ||
6709 | low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); | |
6710 | if (current_it_mask) | |
6711 | narrow = inst.instruction != T_MNEM_movs; | |
6712 | else | |
6713 | narrow = inst.instruction != T_MNEM_movs || low_regs; | |
6714 | if (inst.size_req == 4 | |
6715 | || inst.operands[1].shifted) | |
6716 | narrow = FALSE; | |
6717 | ||
c19d1205 ZW |
6718 | if (!inst.operands[1].isreg) |
6719 | { | |
6720 | /* For an immediate, we always generate a 32-bit opcode; | |
6721 | section relaxation will shrink it later if possible. */ | |
6722 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6723 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6724 | inst.instruction |= inst.operands[0].reg << r0off; | |
6725 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6726 | } | |
3d388997 | 6727 | else if (!narrow) |
c19d1205 ZW |
6728 | { |
6729 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6730 | inst.instruction |= inst.operands[0].reg << r0off; | |
6731 | encode_thumb32_shifted_operand (1); | |
6732 | } | |
6733 | else | |
6734 | switch (inst.instruction) | |
6735 | { | |
6736 | case T_MNEM_mov: | |
6737 | inst.instruction = T_OPCODE_MOV_HR; | |
6738 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
6739 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6740 | inst.instruction |= inst.operands[1].reg << 3; | |
6741 | break; | |
b99bd4ef | 6742 | |
c19d1205 ZW |
6743 | case T_MNEM_movs: |
6744 | /* We know we have low registers at this point. | |
6745 | Generate ADD Rd, Rs, #0. */ | |
6746 | inst.instruction = T_OPCODE_ADD_I3; | |
6747 | inst.instruction |= inst.operands[0].reg; | |
6748 | inst.instruction |= inst.operands[1].reg << 3; | |
6749 | break; | |
6750 | ||
6751 | case T_MNEM_cmp: | |
3d388997 | 6752 | if (low_regs) |
c19d1205 ZW |
6753 | { |
6754 | inst.instruction = T_OPCODE_CMP_LR; | |
6755 | inst.instruction |= inst.operands[0].reg; | |
6756 | inst.instruction |= inst.operands[1].reg << 3; | |
6757 | } | |
6758 | else | |
6759 | { | |
6760 | inst.instruction = T_OPCODE_CMP_HR; | |
6761 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
6762 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6763 | inst.instruction |= inst.operands[1].reg << 3; | |
6764 | } | |
6765 | break; | |
6766 | } | |
b99bd4ef NC |
6767 | return; |
6768 | } | |
6769 | ||
c19d1205 ZW |
6770 | inst.instruction = THUMB_OP16 (inst.instruction); |
6771 | if (inst.operands[1].isreg) | |
b99bd4ef | 6772 | { |
c19d1205 | 6773 | if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) |
b99bd4ef | 6774 | { |
c19d1205 ZW |
6775 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
6776 | since a MOV instruction produces unpredictable results. */ | |
6777 | if (inst.instruction == T_OPCODE_MOV_I8) | |
6778 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 6779 | else |
c19d1205 | 6780 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 6781 | |
c19d1205 ZW |
6782 | inst.instruction |= inst.operands[0].reg; |
6783 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
6784 | } |
6785 | else | |
6786 | { | |
c19d1205 ZW |
6787 | if (inst.instruction == T_OPCODE_MOV_I8) |
6788 | inst.instruction = T_OPCODE_MOV_HR; | |
6789 | else | |
6790 | inst.instruction = T_OPCODE_CMP_HR; | |
6791 | do_t_cpy (); | |
b99bd4ef NC |
6792 | } |
6793 | } | |
c19d1205 | 6794 | else |
b99bd4ef | 6795 | { |
c19d1205 ZW |
6796 | constraint (inst.operands[0].reg > 7, |
6797 | _("only lo regs allowed with immediate")); | |
6798 | inst.instruction |= inst.operands[0].reg << 8; | |
6799 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
6800 | } | |
6801 | } | |
b99bd4ef | 6802 | |
c19d1205 ZW |
6803 | static void |
6804 | do_t_mov16 (void) | |
6805 | { | |
6806 | inst.instruction |= inst.operands[0].reg << 8; | |
6807 | inst.instruction |= (inst.operands[1].imm & 0xf000) << 4; | |
6808 | inst.instruction |= (inst.operands[1].imm & 0x0800) << 15; | |
6809 | inst.instruction |= (inst.operands[1].imm & 0x0700) << 4; | |
6810 | inst.instruction |= (inst.operands[1].imm & 0x00ff); | |
6811 | } | |
b99bd4ef | 6812 | |
c19d1205 ZW |
6813 | static void |
6814 | do_t_mvn_tst (void) | |
6815 | { | |
6816 | if (unified_syntax) | |
6817 | { | |
6818 | int r0off = (inst.instruction == T_MNEM_mvn | |
6819 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
6820 | bfd_boolean narrow; |
6821 | ||
6822 | if (inst.size_req == 4 | |
6823 | || inst.instruction > 0xffff | |
6824 | || inst.operands[1].shifted | |
6825 | || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
6826 | narrow = FALSE; | |
6827 | else if (inst.instruction == T_MNEM_cmn) | |
6828 | narrow = TRUE; | |
6829 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
6830 | narrow = (current_it_mask == 0); | |
6831 | else | |
6832 | narrow = (current_it_mask != 0); | |
6833 | ||
c19d1205 | 6834 | if (!inst.operands[1].isreg) |
b99bd4ef | 6835 | { |
c19d1205 ZW |
6836 | /* For an immediate, we always generate a 32-bit opcode; |
6837 | section relaxation will shrink it later if possible. */ | |
6838 | if (inst.instruction < 0xffff) | |
6839 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6840 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6841 | inst.instruction |= inst.operands[0].reg << r0off; | |
6842 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 6843 | } |
c19d1205 | 6844 | else |
b99bd4ef | 6845 | { |
c19d1205 | 6846 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 6847 | if (narrow) |
b99bd4ef | 6848 | { |
c19d1205 ZW |
6849 | inst.instruction = THUMB_OP16 (inst.instruction); |
6850 | inst.instruction |= inst.operands[0].reg; | |
6851 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 6852 | } |
c19d1205 | 6853 | else |
b99bd4ef | 6854 | { |
c19d1205 ZW |
6855 | constraint (inst.operands[1].shifted |
6856 | && inst.operands[1].immisreg, | |
6857 | _("shift must be constant")); | |
6858 | if (inst.instruction < 0xffff) | |
6859 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6860 | inst.instruction |= inst.operands[0].reg << r0off; | |
6861 | encode_thumb32_shifted_operand (1); | |
b99bd4ef | 6862 | } |
b99bd4ef NC |
6863 | } |
6864 | } | |
6865 | else | |
6866 | { | |
c19d1205 ZW |
6867 | constraint (inst.instruction > 0xffff |
6868 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
6869 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
6870 | _("unshifted register required")); | |
6871 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
6872 | BAD_HIREG); | |
b99bd4ef | 6873 | |
c19d1205 ZW |
6874 | inst.instruction = THUMB_OP16 (inst.instruction); |
6875 | inst.instruction |= inst.operands[0].reg; | |
6876 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 6877 | } |
b99bd4ef NC |
6878 | } |
6879 | ||
b05fe5cf | 6880 | static void |
c19d1205 | 6881 | do_t_mrs (void) |
b05fe5cf | 6882 | { |
c19d1205 ZW |
6883 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
6884 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
6885 | != (PSR_c|PSR_f), | |
6886 | _("'CPSR' or 'SPSR' expected")); | |
6887 | inst.instruction |= inst.operands[0].reg << 8; | |
6888 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2; | |
6889 | } | |
b05fe5cf | 6890 | |
c19d1205 ZW |
6891 | static void |
6892 | do_t_msr (void) | |
6893 | { | |
6894 | constraint (!inst.operands[1].isreg, | |
6895 | _("Thumb encoding does not support an immediate here")); | |
6896 | inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2; | |
6897 | inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8; | |
6898 | inst.instruction |= inst.operands[1].reg << 16; | |
6899 | } | |
b05fe5cf | 6900 | |
c19d1205 ZW |
6901 | static void |
6902 | do_t_mul (void) | |
6903 | { | |
6904 | if (!inst.operands[2].present) | |
6905 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 6906 | |
c19d1205 ZW |
6907 | /* There is no 32-bit MULS and no 16-bit MUL. */ |
6908 | if (unified_syntax && inst.instruction == T_MNEM_mul) | |
b05fe5cf | 6909 | { |
c19d1205 ZW |
6910 | inst.instruction = THUMB_OP32 (inst.instruction); |
6911 | inst.instruction |= inst.operands[0].reg << 8; | |
6912 | inst.instruction |= inst.operands[1].reg << 16; | |
6913 | inst.instruction |= inst.operands[2].reg << 0; | |
b05fe5cf | 6914 | } |
c19d1205 | 6915 | else |
b05fe5cf | 6916 | { |
c19d1205 ZW |
6917 | constraint (!unified_syntax |
6918 | && inst.instruction == T_MNEM_muls, BAD_THUMB32); | |
6919 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
6920 | BAD_HIREG); | |
b05fe5cf | 6921 | |
c19d1205 ZW |
6922 | inst.instruction = THUMB_OP16 (inst.instruction); |
6923 | inst.instruction |= inst.operands[0].reg; | |
b05fe5cf | 6924 | |
c19d1205 ZW |
6925 | if (inst.operands[0].reg == inst.operands[1].reg) |
6926 | inst.instruction |= inst.operands[2].reg << 3; | |
6927 | else if (inst.operands[0].reg == inst.operands[2].reg) | |
6928 | inst.instruction |= inst.operands[1].reg << 3; | |
6929 | else | |
6930 | constraint (1, _("dest must overlap one source register")); | |
6931 | } | |
6932 | } | |
b05fe5cf | 6933 | |
c19d1205 ZW |
6934 | static void |
6935 | do_t_mull (void) | |
6936 | { | |
6937 | inst.instruction |= inst.operands[0].reg << 12; | |
6938 | inst.instruction |= inst.operands[1].reg << 8; | |
6939 | inst.instruction |= inst.operands[2].reg << 16; | |
6940 | inst.instruction |= inst.operands[3].reg; | |
b05fe5cf | 6941 | |
c19d1205 ZW |
6942 | if (inst.operands[0].reg == inst.operands[1].reg) |
6943 | as_tsktsk (_("rdhi and rdlo must be different")); | |
6944 | } | |
b05fe5cf | 6945 | |
c19d1205 ZW |
6946 | static void |
6947 | do_t_nop (void) | |
6948 | { | |
6949 | if (unified_syntax) | |
6950 | { | |
6951 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 6952 | { |
c19d1205 ZW |
6953 | inst.instruction = THUMB_OP32 (inst.instruction); |
6954 | inst.instruction |= inst.operands[0].imm; | |
6955 | } | |
6956 | else | |
6957 | { | |
6958 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6959 | inst.instruction |= inst.operands[0].imm << 4; | |
6960 | } | |
6961 | } | |
6962 | else | |
6963 | { | |
6964 | constraint (inst.operands[0].present, | |
6965 | _("Thumb does not support NOP with hints")); | |
6966 | inst.instruction = 0x46c0; | |
6967 | } | |
6968 | } | |
b05fe5cf | 6969 | |
c19d1205 ZW |
6970 | static void |
6971 | do_t_neg (void) | |
6972 | { | |
6973 | if (unified_syntax) | |
6974 | { | |
3d388997 PB |
6975 | bfd_boolean narrow; |
6976 | ||
6977 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
6978 | narrow = (current_it_mask == 0); | |
6979 | else | |
6980 | narrow = (current_it_mask != 0); | |
6981 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
6982 | narrow = FALSE; | |
6983 | if (inst.size_req == 4) | |
6984 | narrow = FALSE; | |
6985 | ||
6986 | if (!narrow) | |
c19d1205 ZW |
6987 | { |
6988 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6989 | inst.instruction |= inst.operands[0].reg << 8; | |
6990 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
6991 | } |
6992 | else | |
6993 | { | |
c19d1205 ZW |
6994 | inst.instruction = THUMB_OP16 (inst.instruction); |
6995 | inst.instruction |= inst.operands[0].reg; | |
6996 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
6997 | } |
6998 | } | |
6999 | else | |
7000 | { | |
c19d1205 ZW |
7001 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
7002 | BAD_HIREG); | |
7003 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
7004 | ||
7005 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7006 | inst.instruction |= inst.operands[0].reg; | |
7007 | inst.instruction |= inst.operands[1].reg << 3; | |
7008 | } | |
7009 | } | |
7010 | ||
7011 | static void | |
7012 | do_t_pkhbt (void) | |
7013 | { | |
7014 | inst.instruction |= inst.operands[0].reg << 8; | |
7015 | inst.instruction |= inst.operands[1].reg << 16; | |
7016 | inst.instruction |= inst.operands[2].reg; | |
7017 | if (inst.operands[3].present) | |
7018 | { | |
7019 | unsigned int val = inst.reloc.exp.X_add_number; | |
7020 | constraint (inst.reloc.exp.X_op != O_constant, | |
7021 | _("expression too complex")); | |
7022 | inst.instruction |= (val & 0x1c) << 10; | |
7023 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 7024 | } |
c19d1205 | 7025 | } |
b05fe5cf | 7026 | |
c19d1205 ZW |
7027 | static void |
7028 | do_t_pkhtb (void) | |
7029 | { | |
7030 | if (!inst.operands[3].present) | |
7031 | inst.instruction &= ~0x00000020; | |
7032 | do_t_pkhbt (); | |
b05fe5cf ZW |
7033 | } |
7034 | ||
c19d1205 ZW |
7035 | static void |
7036 | do_t_pld (void) | |
7037 | { | |
7038 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
7039 | } | |
b05fe5cf | 7040 | |
c19d1205 ZW |
7041 | static void |
7042 | do_t_push_pop (void) | |
b99bd4ef | 7043 | { |
e9f89963 PB |
7044 | unsigned mask; |
7045 | ||
c19d1205 ZW |
7046 | constraint (inst.operands[0].writeback, |
7047 | _("push/pop do not support {reglist}^")); | |
7048 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
7049 | _("expression too complex")); | |
b99bd4ef | 7050 | |
e9f89963 PB |
7051 | mask = inst.operands[0].imm; |
7052 | if ((mask & ~0xff) == 0) | |
c19d1205 ZW |
7053 | inst.instruction = THUMB_OP16 (inst.instruction); |
7054 | else if ((inst.instruction == T_MNEM_push | |
e9f89963 | 7055 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 7056 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 7057 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 7058 | { |
c19d1205 ZW |
7059 | inst.instruction = THUMB_OP16 (inst.instruction); |
7060 | inst.instruction |= THUMB_PP_PC_LR; | |
e9f89963 | 7061 | mask &= 0xff; |
c19d1205 ZW |
7062 | } |
7063 | else if (unified_syntax) | |
7064 | { | |
e9f89963 PB |
7065 | if (mask & (1 << 13)) |
7066 | inst.error = _("SP not allowed in register list"); | |
c19d1205 | 7067 | if (inst.instruction == T_MNEM_push) |
b99bd4ef | 7068 | { |
e9f89963 PB |
7069 | if (mask & (1 << 15)) |
7070 | inst.error = _("PC not allowed in register list"); | |
c19d1205 ZW |
7071 | } |
7072 | else | |
7073 | { | |
e9f89963 PB |
7074 | if (mask & (1 << 14) |
7075 | && mask & (1 << 15)) | |
7076 | inst.error = _("LR and PC should not both be in register list"); | |
c19d1205 | 7077 | } |
e9f89963 PB |
7078 | if ((mask & (mask - 1)) == 0) |
7079 | { | |
7080 | /* Single register push/pop implemented as str/ldr. */ | |
7081 | if (inst.instruction == T_MNEM_push) | |
7082 | inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */ | |
7083 | else | |
7084 | inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */ | |
7085 | mask = ffs(mask) - 1; | |
7086 | mask <<= 12; | |
7087 | } | |
7088 | else | |
7089 | inst.instruction = THUMB_OP32 (inst.instruction); | |
c19d1205 ZW |
7090 | } |
7091 | else | |
7092 | { | |
7093 | inst.error = _("invalid register list to push/pop instruction"); | |
7094 | return; | |
7095 | } | |
b99bd4ef | 7096 | |
e9f89963 | 7097 | inst.instruction |= mask; |
c19d1205 | 7098 | } |
b99bd4ef | 7099 | |
c19d1205 ZW |
7100 | static void |
7101 | do_t_rbit (void) | |
7102 | { | |
7103 | inst.instruction |= inst.operands[0].reg << 8; | |
7104 | inst.instruction |= inst.operands[1].reg << 16; | |
7105 | } | |
b99bd4ef | 7106 | |
c19d1205 ZW |
7107 | static void |
7108 | do_t_rev (void) | |
7109 | { | |
7110 | if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7111 | && inst.size_req != 4) | |
7112 | { | |
7113 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7114 | inst.instruction |= inst.operands[0].reg; | |
7115 | inst.instruction |= inst.operands[1].reg << 3; | |
7116 | } | |
7117 | else if (unified_syntax) | |
7118 | { | |
7119 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7120 | inst.instruction |= inst.operands[0].reg << 8; | |
7121 | inst.instruction |= inst.operands[1].reg << 16; | |
7122 | inst.instruction |= inst.operands[1].reg; | |
7123 | } | |
7124 | else | |
7125 | inst.error = BAD_HIREG; | |
7126 | } | |
b99bd4ef | 7127 | |
c19d1205 ZW |
7128 | static void |
7129 | do_t_rsb (void) | |
7130 | { | |
7131 | int Rd, Rs; | |
b99bd4ef | 7132 | |
c19d1205 ZW |
7133 | Rd = inst.operands[0].reg; |
7134 | Rs = (inst.operands[1].present | |
7135 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
7136 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 7137 | |
c19d1205 ZW |
7138 | inst.instruction |= Rd << 8; |
7139 | inst.instruction |= Rs << 16; | |
7140 | if (!inst.operands[2].isreg) | |
7141 | { | |
7142 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7143 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
7144 | } | |
7145 | else | |
7146 | encode_thumb32_shifted_operand (2); | |
7147 | } | |
b99bd4ef | 7148 | |
c19d1205 ZW |
7149 | static void |
7150 | do_t_setend (void) | |
7151 | { | |
7152 | if (inst.operands[0].imm) | |
7153 | inst.instruction |= 0x8; | |
7154 | } | |
b99bd4ef | 7155 | |
c19d1205 ZW |
7156 | static void |
7157 | do_t_shift (void) | |
7158 | { | |
7159 | if (!inst.operands[1].present) | |
7160 | inst.operands[1].reg = inst.operands[0].reg; | |
7161 | ||
7162 | if (unified_syntax) | |
7163 | { | |
3d388997 PB |
7164 | bfd_boolean narrow; |
7165 | int shift_kind; | |
7166 | ||
7167 | switch (inst.instruction) | |
7168 | { | |
7169 | case T_MNEM_asr: | |
7170 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
7171 | case T_MNEM_lsl: | |
7172 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
7173 | case T_MNEM_lsr: | |
7174 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
7175 | case T_MNEM_ror: | |
7176 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
7177 | default: abort (); | |
7178 | } | |
7179 | ||
7180 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7181 | narrow = (current_it_mask == 0); | |
7182 | else | |
7183 | narrow = (current_it_mask != 0); | |
7184 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7185 | narrow = FALSE; | |
7186 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
7187 | narrow = FALSE; | |
7188 | if (inst.operands[2].isreg | |
7189 | && (inst.operands[1].reg != inst.operands[0].reg | |
7190 | || inst.operands[2].reg > 7)) | |
7191 | narrow = FALSE; | |
7192 | if (inst.size_req == 4) | |
7193 | narrow = FALSE; | |
7194 | ||
7195 | if (!narrow) | |
c19d1205 ZW |
7196 | { |
7197 | if (inst.operands[2].isreg) | |
b99bd4ef | 7198 | { |
c19d1205 ZW |
7199 | inst.instruction = THUMB_OP32 (inst.instruction); |
7200 | inst.instruction |= inst.operands[0].reg << 8; | |
7201 | inst.instruction |= inst.operands[1].reg << 16; | |
7202 | inst.instruction |= inst.operands[2].reg; | |
7203 | } | |
7204 | else | |
7205 | { | |
7206 | inst.operands[1].shifted = 1; | |
3d388997 | 7207 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
7208 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
7209 | ? T_MNEM_movs : T_MNEM_mov); | |
7210 | inst.instruction |= inst.operands[0].reg << 8; | |
7211 | encode_thumb32_shifted_operand (1); | |
7212 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
7213 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
7214 | } |
7215 | } | |
7216 | else | |
7217 | { | |
c19d1205 | 7218 | if (inst.operands[2].isreg) |
b99bd4ef | 7219 | { |
3d388997 | 7220 | switch (shift_kind) |
b99bd4ef | 7221 | { |
3d388997 PB |
7222 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
7223 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
7224 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
7225 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 7226 | default: abort (); |
b99bd4ef | 7227 | } |
c19d1205 ZW |
7228 | |
7229 | inst.instruction |= inst.operands[0].reg; | |
7230 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
7231 | } |
7232 | else | |
7233 | { | |
3d388997 | 7234 | switch (shift_kind) |
b99bd4ef | 7235 | { |
3d388997 PB |
7236 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
7237 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
7238 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 7239 | default: abort (); |
b99bd4ef | 7240 | } |
c19d1205 ZW |
7241 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
7242 | inst.instruction |= inst.operands[0].reg; | |
7243 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7244 | } |
7245 | } | |
c19d1205 ZW |
7246 | } |
7247 | else | |
7248 | { | |
7249 | constraint (inst.operands[0].reg > 7 | |
7250 | || inst.operands[1].reg > 7, BAD_HIREG); | |
7251 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 7252 | |
c19d1205 ZW |
7253 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
7254 | { | |
7255 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
7256 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
7257 | _("source1 and dest must be same register")); | |
b99bd4ef | 7258 | |
c19d1205 ZW |
7259 | switch (inst.instruction) |
7260 | { | |
7261 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
7262 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
7263 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
7264 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
7265 | default: abort (); | |
7266 | } | |
7267 | ||
7268 | inst.instruction |= inst.operands[0].reg; | |
7269 | inst.instruction |= inst.operands[2].reg << 3; | |
7270 | } | |
7271 | else | |
b99bd4ef | 7272 | { |
c19d1205 ZW |
7273 | switch (inst.instruction) |
7274 | { | |
7275 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
7276 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
7277 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
7278 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
7279 | default: abort (); | |
7280 | } | |
7281 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
7282 | inst.instruction |= inst.operands[0].reg; | |
7283 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7284 | } |
7285 | } | |
b99bd4ef NC |
7286 | } |
7287 | ||
7288 | static void | |
c19d1205 | 7289 | do_t_simd (void) |
b99bd4ef | 7290 | { |
c19d1205 ZW |
7291 | inst.instruction |= inst.operands[0].reg << 8; |
7292 | inst.instruction |= inst.operands[1].reg << 16; | |
7293 | inst.instruction |= inst.operands[2].reg; | |
7294 | } | |
b99bd4ef | 7295 | |
c19d1205 ZW |
7296 | static void |
7297 | do_t_smi (void) | |
7298 | { | |
7299 | unsigned int value = inst.reloc.exp.X_add_number; | |
7300 | constraint (inst.reloc.exp.X_op != O_constant, | |
7301 | _("expression too complex")); | |
7302 | inst.reloc.type = BFD_RELOC_UNUSED; | |
7303 | inst.instruction |= (value & 0xf000) >> 12; | |
7304 | inst.instruction |= (value & 0x0ff0); | |
7305 | inst.instruction |= (value & 0x000f) << 16; | |
7306 | } | |
b99bd4ef | 7307 | |
c19d1205 ZW |
7308 | static void |
7309 | do_t_ssat (void) | |
7310 | { | |
7311 | inst.instruction |= inst.operands[0].reg << 8; | |
7312 | inst.instruction |= inst.operands[1].imm - 1; | |
7313 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7314 | |
c19d1205 | 7315 | if (inst.operands[3].present) |
b99bd4ef | 7316 | { |
c19d1205 ZW |
7317 | constraint (inst.reloc.exp.X_op != O_constant, |
7318 | _("expression too complex")); | |
b99bd4ef | 7319 | |
c19d1205 | 7320 | if (inst.reloc.exp.X_add_number != 0) |
6189168b | 7321 | { |
c19d1205 ZW |
7322 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
7323 | inst.instruction |= 0x00200000; /* sh bit */ | |
7324 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; | |
7325 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
6189168b | 7326 | } |
c19d1205 | 7327 | inst.reloc.type = BFD_RELOC_UNUSED; |
6189168b | 7328 | } |
b99bd4ef NC |
7329 | } |
7330 | ||
0dd132b6 | 7331 | static void |
c19d1205 | 7332 | do_t_ssat16 (void) |
0dd132b6 | 7333 | { |
c19d1205 ZW |
7334 | inst.instruction |= inst.operands[0].reg << 8; |
7335 | inst.instruction |= inst.operands[1].imm - 1; | |
7336 | inst.instruction |= inst.operands[2].reg << 16; | |
7337 | } | |
0dd132b6 | 7338 | |
c19d1205 ZW |
7339 | static void |
7340 | do_t_strex (void) | |
7341 | { | |
7342 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
7343 | || inst.operands[2].postind || inst.operands[2].writeback | |
7344 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
7345 | || inst.operands[2].negative, | |
7346 | _("instruction does not accept this addressing mode")); | |
0dd132b6 | 7347 | |
c19d1205 ZW |
7348 | inst.instruction |= inst.operands[0].reg << 8; |
7349 | inst.instruction |= inst.operands[1].reg << 12; | |
7350 | inst.instruction |= inst.operands[2].reg << 16; | |
7351 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
7352 | } |
7353 | ||
b99bd4ef | 7354 | static void |
c19d1205 | 7355 | do_t_strexd (void) |
b99bd4ef | 7356 | { |
c19d1205 ZW |
7357 | if (!inst.operands[2].present) |
7358 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 7359 | |
c19d1205 ZW |
7360 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7361 | || inst.operands[0].reg == inst.operands[2].reg | |
7362 | || inst.operands[0].reg == inst.operands[3].reg | |
7363 | || inst.operands[1].reg == inst.operands[2].reg, | |
7364 | BAD_OVERLAP); | |
b99bd4ef | 7365 | |
c19d1205 ZW |
7366 | inst.instruction |= inst.operands[0].reg; |
7367 | inst.instruction |= inst.operands[1].reg << 12; | |
7368 | inst.instruction |= inst.operands[2].reg << 8; | |
7369 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
7370 | } |
7371 | ||
7372 | static void | |
c19d1205 | 7373 | do_t_sxtah (void) |
b99bd4ef | 7374 | { |
c19d1205 ZW |
7375 | inst.instruction |= inst.operands[0].reg << 8; |
7376 | inst.instruction |= inst.operands[1].reg << 16; | |
7377 | inst.instruction |= inst.operands[2].reg; | |
7378 | inst.instruction |= inst.operands[3].imm << 4; | |
7379 | } | |
b99bd4ef | 7380 | |
c19d1205 ZW |
7381 | static void |
7382 | do_t_sxth (void) | |
7383 | { | |
7384 | if (inst.instruction <= 0xffff && inst.size_req != 4 | |
7385 | && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7386 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) | |
b99bd4ef | 7387 | { |
c19d1205 ZW |
7388 | inst.instruction = THUMB_OP16 (inst.instruction); |
7389 | inst.instruction |= inst.operands[0].reg; | |
7390 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7391 | } |
c19d1205 | 7392 | else if (unified_syntax) |
b99bd4ef | 7393 | { |
c19d1205 ZW |
7394 | if (inst.instruction <= 0xffff) |
7395 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7396 | inst.instruction |= inst.operands[0].reg << 8; | |
7397 | inst.instruction |= inst.operands[1].reg; | |
7398 | inst.instruction |= inst.operands[2].imm << 4; | |
b99bd4ef | 7399 | } |
c19d1205 | 7400 | else |
b99bd4ef | 7401 | { |
c19d1205 ZW |
7402 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
7403 | _("Thumb encoding does not support rotation")); | |
7404 | constraint (1, BAD_HIREG); | |
b99bd4ef | 7405 | } |
c19d1205 | 7406 | } |
b99bd4ef | 7407 | |
c19d1205 ZW |
7408 | static void |
7409 | do_t_swi (void) | |
7410 | { | |
7411 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
7412 | } | |
b99bd4ef | 7413 | |
92e90b6e PB |
7414 | static void |
7415 | do_t_tb (void) | |
7416 | { | |
7417 | int half; | |
7418 | ||
7419 | half = (inst.instruction & 0x10) != 0; | |
7420 | constraint (inst.operands[0].imm == 15, | |
7421 | _("PC is not a valid index register")); | |
7422 | constraint (!half && inst.operands[0].shifted, | |
7423 | _("instruction does not allow shifted index")); | |
7424 | constraint (half && !inst.operands[0].shifted, | |
7425 | _("instruction requires shifted index")); | |
7426 | inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; | |
7427 | } | |
7428 | ||
c19d1205 ZW |
7429 | static void |
7430 | do_t_usat (void) | |
7431 | { | |
7432 | inst.instruction |= inst.operands[0].reg << 8; | |
7433 | inst.instruction |= inst.operands[1].imm; | |
7434 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7435 | |
c19d1205 | 7436 | if (inst.operands[3].present) |
b99bd4ef | 7437 | { |
c19d1205 ZW |
7438 | constraint (inst.reloc.exp.X_op != O_constant, |
7439 | _("expression too complex")); | |
7440 | if (inst.reloc.exp.X_add_number != 0) | |
7441 | { | |
7442 | if (inst.operands[3].shift_kind == SHIFT_ASR) | |
7443 | inst.instruction |= 0x00200000; /* sh bit */ | |
b99bd4ef | 7444 | |
c19d1205 ZW |
7445 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; |
7446 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
7447 | } | |
7448 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 7449 | } |
b99bd4ef NC |
7450 | } |
7451 | ||
7452 | static void | |
c19d1205 | 7453 | do_t_usat16 (void) |
b99bd4ef | 7454 | { |
c19d1205 ZW |
7455 | inst.instruction |= inst.operands[0].reg << 8; |
7456 | inst.instruction |= inst.operands[1].imm; | |
7457 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7458 | } |
c19d1205 ZW |
7459 | \f |
7460 | /* Overall per-instruction processing. */ | |
7461 | ||
7462 | /* We need to be able to fix up arbitrary expressions in some statements. | |
7463 | This is so that we can handle symbols that are an arbitrary distance from | |
7464 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
7465 | which returns part of an address in a form which will be valid for | |
7466 | a data instruction. We do this by pushing the expression into a symbol | |
7467 | in the expr_section, and creating a fix for that. */ | |
b99bd4ef NC |
7468 | |
7469 | static void | |
c19d1205 ZW |
7470 | fix_new_arm (fragS * frag, |
7471 | int where, | |
7472 | short int size, | |
7473 | expressionS * exp, | |
7474 | int pc_rel, | |
7475 | int reloc) | |
b99bd4ef | 7476 | { |
c19d1205 | 7477 | fixS * new_fix; |
b99bd4ef | 7478 | |
c19d1205 | 7479 | switch (exp->X_op) |
b99bd4ef | 7480 | { |
c19d1205 ZW |
7481 | case O_constant: |
7482 | case O_symbol: | |
7483 | case O_add: | |
7484 | case O_subtract: | |
7485 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
7486 | break; | |
b99bd4ef | 7487 | |
c19d1205 ZW |
7488 | default: |
7489 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
7490 | pc_rel, reloc); | |
7491 | break; | |
b99bd4ef NC |
7492 | } |
7493 | ||
c19d1205 ZW |
7494 | /* Mark whether the fix is to a THUMB instruction, or an ARM |
7495 | instruction. */ | |
adbaf948 | 7496 | new_fix->tc_fix_data = thumb_mode; |
b99bd4ef NC |
7497 | } |
7498 | ||
7499 | static void | |
c19d1205 | 7500 | output_inst (const char * str) |
b99bd4ef | 7501 | { |
c19d1205 | 7502 | char * to = NULL; |
b99bd4ef | 7503 | |
c19d1205 | 7504 | if (inst.error) |
b99bd4ef | 7505 | { |
c19d1205 | 7506 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
7507 | return; |
7508 | } | |
c19d1205 ZW |
7509 | if (inst.size == 0) |
7510 | return; | |
b99bd4ef | 7511 | |
c19d1205 ZW |
7512 | to = frag_more (inst.size); |
7513 | ||
7514 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 7515 | { |
c19d1205 ZW |
7516 | assert (inst.size == (2 * THUMB_SIZE)); |
7517 | md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE); | |
7518 | md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE); | |
b99bd4ef | 7519 | } |
c19d1205 | 7520 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 7521 | { |
c19d1205 ZW |
7522 | assert (inst.size == (2 * INSN_SIZE)); |
7523 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
7524 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 7525 | } |
c19d1205 ZW |
7526 | else |
7527 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 7528 | |
c19d1205 ZW |
7529 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
7530 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
7531 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
7532 | inst.reloc.type); | |
b99bd4ef | 7533 | |
c19d1205 ZW |
7534 | #ifdef OBJ_ELF |
7535 | dwarf2_emit_insn (inst.size); | |
7536 | #endif | |
7537 | } | |
b99bd4ef | 7538 | |
c19d1205 ZW |
7539 | /* Tag values used in struct asm_opcode's tag field. */ |
7540 | enum opcode_tag | |
7541 | { | |
7542 | OT_unconditional, /* Instruction cannot be conditionalized. | |
7543 | The ARM condition field is still 0xE. */ | |
7544 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
7545 | and carries 0xF in its ARM condition field. */ | |
7546 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
7547 | OT_cinfix3, /* Instruction takes a conditional infix, | |
7548 | beginning at character index 3. (In | |
7549 | unified mode, it becomes a suffix.) */ | |
7550 | OT_csuf_or_in3, /* Instruction takes either a conditional | |
7551 | suffix or an infix at character index 3. | |
7552 | (In unified mode, a suffix only. */ | |
7553 | OT_odd_infix_unc, /* This is the unconditional variant of an | |
7554 | instruction that takes a conditional infix | |
7555 | at an unusual position. In unified mode, | |
7556 | this variant will accept a suffix. */ | |
7557 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
7558 | are the conditional variants of instructions that | |
7559 | take conditional infixes in unusual positions. | |
7560 | The infix appears at character index | |
7561 | (tag - OT_odd_infix_0). These are not accepted | |
7562 | in unified mode. */ | |
7563 | }; | |
b99bd4ef | 7564 | |
c19d1205 ZW |
7565 | /* Subroutine of md_assemble, responsible for looking up the primary |
7566 | opcode from the mnemonic the user wrote. STR points to the | |
7567 | beginning of the mnemonic. | |
7568 | ||
7569 | This is not simply a hash table lookup, because of conditional | |
7570 | variants. Most instructions have conditional variants, which are | |
7571 | expressed with a _conditional affix_ to the mnemonic. If we were | |
7572 | to encode each conditional variant as a literal string in the opcode | |
7573 | table, it would have approximately 20,000 entries. | |
7574 | ||
7575 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
7576 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
7577 | instructions take the affix as an infix, notably the s-variants of | |
7578 | the arithmetic instructions. Of those instructions, all but six | |
7579 | have the infix appear after the third character of the mnemonic. | |
7580 | ||
7581 | Accordingly, the algorithm for looking up primary opcodes given | |
7582 | an identifier is: | |
7583 | ||
7584 | 1. Look up the identifier in the opcode table. | |
7585 | If we find a match, go to step U. | |
7586 | ||
7587 | 2. Look up the last two characters of the identifier in the | |
7588 | conditions table. If we find a match, look up the first N-2 | |
7589 | characters of the identifier in the opcode table. If we | |
7590 | find a match, go to step CE. | |
7591 | ||
7592 | 3. Look up the fourth and fifth characters of the identifier in | |
7593 | the conditions table. If we find a match, extract those | |
7594 | characters from the identifier, and look up the remaining | |
7595 | characters in the opcode table. If we find a match, go | |
7596 | to step CM. | |
7597 | ||
7598 | 4. Fail. | |
7599 | ||
7600 | U. Examine the tag field of the opcode structure, in case this is | |
7601 | one of the six instructions with its conditional infix in an | |
7602 | unusual place. If it is, the tag tells us where to find the | |
7603 | infix; look it up in the conditions table and set inst.cond | |
7604 | accordingly. Otherwise, this is an unconditional instruction. | |
7605 | Again set inst.cond accordingly. Return the opcode structure. | |
7606 | ||
7607 | CE. Examine the tag field to make sure this is an instruction that | |
7608 | should receive a conditional suffix. If it is not, fail. | |
7609 | Otherwise, set inst.cond from the suffix we already looked up, | |
7610 | and return the opcode structure. | |
7611 | ||
7612 | CM. Examine the tag field to make sure this is an instruction that | |
7613 | should receive a conditional infix after the third character. | |
7614 | If it is not, fail. Otherwise, undo the edits to the current | |
7615 | line of input and proceed as for case CE. */ | |
7616 | ||
7617 | static const struct asm_opcode * | |
7618 | opcode_lookup (char **str) | |
7619 | { | |
7620 | char *end, *base; | |
7621 | char *affix; | |
7622 | const struct asm_opcode *opcode; | |
7623 | const struct asm_cond *cond; | |
7624 | ||
7625 | /* Scan up to the end of the mnemonic, which must end in white space, | |
7626 | '.' (in unified mode only), or end of string. */ | |
7627 | for (base = end = *str; *end != '\0'; end++) | |
7628 | if (*end == ' ' || (unified_syntax && *end == '.')) | |
7629 | break; | |
b99bd4ef | 7630 | |
c19d1205 ZW |
7631 | if (end == base) |
7632 | return 0; | |
b99bd4ef | 7633 | |
c19d1205 ZW |
7634 | /* Handle a possible width suffix. */ |
7635 | if (end[0] == '.') | |
b99bd4ef | 7636 | { |
c19d1205 ZW |
7637 | if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0')) |
7638 | inst.size_req = 4; | |
7639 | else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0')) | |
7640 | inst.size_req = 2; | |
7641 | else | |
7642 | return 0; | |
b99bd4ef | 7643 | |
c19d1205 | 7644 | *str = end + 2; |
b99bd4ef | 7645 | } |
c19d1205 ZW |
7646 | else |
7647 | *str = end; | |
b99bd4ef | 7648 | |
c19d1205 ZW |
7649 | /* Look for unaffixed or special-case affixed mnemonic. */ |
7650 | opcode = hash_find_n (arm_ops_hsh, base, end - base); | |
7651 | if (opcode) | |
b99bd4ef | 7652 | { |
c19d1205 ZW |
7653 | /* step U */ |
7654 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 7655 | { |
c19d1205 ZW |
7656 | inst.cond = COND_ALWAYS; |
7657 | return opcode; | |
b99bd4ef | 7658 | } |
b99bd4ef | 7659 | |
c19d1205 ZW |
7660 | if (unified_syntax) |
7661 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
7662 | affix = base + (opcode->tag - OT_odd_infix_0); | |
7663 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
7664 | assert (cond); | |
b99bd4ef | 7665 | |
c19d1205 ZW |
7666 | inst.cond = cond->value; |
7667 | return opcode; | |
7668 | } | |
b99bd4ef | 7669 | |
c19d1205 ZW |
7670 | /* Cannot have a conditional suffix on a mnemonic of less than two |
7671 | characters. */ | |
7672 | if (end - base < 3) | |
7673 | return 0; | |
b99bd4ef | 7674 | |
c19d1205 ZW |
7675 | /* Look for suffixed mnemonic. */ |
7676 | affix = end - 2; | |
7677 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
7678 | opcode = hash_find_n (arm_ops_hsh, base, affix - base); | |
7679 | if (opcode && cond) | |
7680 | { | |
7681 | /* step CE */ | |
7682 | switch (opcode->tag) | |
7683 | { | |
7684 | case OT_cinfix3: | |
7685 | case OT_odd_infix_unc: | |
c4188bc9 PB |
7686 | /* Some mnemonics are ambiguous between infix and suffix |
7687 | conditions. Disambiguate based on assembly syntax. */ | |
c19d1205 | 7688 | if (!unified_syntax) |
c4188bc9 | 7689 | break; |
c19d1205 ZW |
7690 | /* else fall through */ |
7691 | ||
7692 | case OT_csuffix: | |
7693 | case OT_csuf_or_in3: | |
7694 | inst.cond = cond->value; | |
7695 | return opcode; | |
7696 | ||
7697 | case OT_unconditional: | |
7698 | case OT_unconditionalF: | |
7699 | /* delayed diagnostic */ | |
7700 | inst.error = BAD_COND; | |
7701 | inst.cond = COND_ALWAYS; | |
7702 | return opcode; | |
b99bd4ef | 7703 | |
c19d1205 ZW |
7704 | default: |
7705 | return 0; | |
7706 | } | |
7707 | } | |
b99bd4ef | 7708 | |
c19d1205 ZW |
7709 | /* Cannot have a usual-position infix on a mnemonic of less than |
7710 | six characters (five would be a suffix). */ | |
7711 | if (end - base < 6) | |
7712 | return 0; | |
b99bd4ef | 7713 | |
c19d1205 ZW |
7714 | /* Look for infixed mnemonic in the usual position. */ |
7715 | affix = base + 3; | |
7716 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
7717 | if (cond) | |
b99bd4ef | 7718 | { |
c19d1205 ZW |
7719 | char save[2]; |
7720 | memcpy (save, affix, 2); | |
7721 | memmove (affix, affix + 2, (end - affix) - 2); | |
7722 | opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); | |
7723 | memmove (affix + 2, affix, (end - affix) - 2); | |
7724 | memcpy (affix, save, 2); | |
b99bd4ef | 7725 | } |
c19d1205 | 7726 | if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3)) |
b99bd4ef | 7727 | { |
c19d1205 ZW |
7728 | /* step CM */ |
7729 | if (unified_syntax) | |
7730 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
7731 | ||
7732 | inst.cond = cond->value; | |
7733 | return opcode; | |
b99bd4ef NC |
7734 | } |
7735 | ||
c19d1205 | 7736 | return 0; |
b99bd4ef NC |
7737 | } |
7738 | ||
c19d1205 ZW |
7739 | void |
7740 | md_assemble (char *str) | |
b99bd4ef | 7741 | { |
c19d1205 ZW |
7742 | char *p = str; |
7743 | const struct asm_opcode * opcode; | |
b99bd4ef | 7744 | |
c19d1205 ZW |
7745 | /* Align the previous label if needed. */ |
7746 | if (last_label_seen != NULL) | |
b99bd4ef | 7747 | { |
c19d1205 ZW |
7748 | symbol_set_frag (last_label_seen, frag_now); |
7749 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
7750 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
7751 | } |
7752 | ||
c19d1205 ZW |
7753 | memset (&inst, '\0', sizeof (inst)); |
7754 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 7755 | |
c19d1205 ZW |
7756 | opcode = opcode_lookup (&p); |
7757 | if (!opcode) | |
b99bd4ef | 7758 | { |
c19d1205 ZW |
7759 | /* It wasn't an instruction, but it might be a register alias of |
7760 | the form alias .req reg. */ | |
7761 | if (!create_register_alias (str, p)) | |
7762 | as_bad (_("bad instruction `%s'"), str); | |
b99bd4ef | 7763 | |
b99bd4ef NC |
7764 | return; |
7765 | } | |
7766 | ||
c19d1205 | 7767 | if (thumb_mode) |
b99bd4ef | 7768 | { |
8f06b2d8 PB |
7769 | unsigned long variant; |
7770 | ||
7771 | variant = cpu_variant; | |
7772 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
7773 | if ((variant & ARM_EXT_V6T2) == 0) | |
7774 | variant &= ARM_ANY; | |
c19d1205 | 7775 | /* Check that this instruction is supported for this CPU. */ |
8f06b2d8 | 7776 | if (thumb_mode == 1 && (opcode->tvariant & variant) == 0) |
b99bd4ef | 7777 | { |
c19d1205 | 7778 | as_bad (_("selected processor does not support `%s'"), str); |
b99bd4ef NC |
7779 | return; |
7780 | } | |
c19d1205 ZW |
7781 | if (inst.cond != COND_ALWAYS && !unified_syntax |
7782 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 7783 | { |
c19d1205 | 7784 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
7785 | return; |
7786 | } | |
7787 | ||
e27ec89e PB |
7788 | /* Check conditional suffixes. */ |
7789 | if (current_it_mask) | |
7790 | { | |
7791 | int cond; | |
7792 | cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; | |
7793 | if (cond != inst.cond) | |
7794 | { | |
7795 | as_bad (_("incorrect condition in IT block")); | |
7796 | return; | |
7797 | } | |
7798 | current_it_mask <<= 1; | |
7799 | current_it_mask &= 0x1f; | |
7800 | } | |
7801 | else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) | |
7802 | { | |
7803 | as_bad (_("thumb conditional instrunction not in IT block")); | |
7804 | return; | |
7805 | } | |
7806 | ||
c19d1205 ZW |
7807 | mapping_state (MAP_THUMB); |
7808 | inst.instruction = opcode->tvalue; | |
7809 | ||
7810 | if (!parse_operands (p, opcode->operands)) | |
7811 | opcode->tencode (); | |
7812 | ||
e27ec89e PB |
7813 | /* Clear current_it_mask at the end of an IT block. */ |
7814 | if (current_it_mask == 0x10) | |
7815 | current_it_mask = 0; | |
7816 | ||
c19d1205 | 7817 | if (!inst.error) |
b99bd4ef | 7818 | { |
c19d1205 ZW |
7819 | assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
7820 | inst.size = (inst.instruction > 0xffff ? 4 : 2); | |
7821 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 7822 | { |
c19d1205 | 7823 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
7824 | return; |
7825 | } | |
7826 | } | |
c19d1205 ZW |
7827 | } |
7828 | else | |
7829 | { | |
7830 | /* Check that this instruction is supported for this CPU. */ | |
7831 | if ((opcode->avariant & cpu_variant) == 0) | |
b99bd4ef | 7832 | { |
c19d1205 ZW |
7833 | as_bad (_("selected processor does not support `%s'"), str); |
7834 | return; | |
b99bd4ef | 7835 | } |
c19d1205 | 7836 | if (inst.size_req) |
b99bd4ef | 7837 | { |
c19d1205 ZW |
7838 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
7839 | return; | |
b99bd4ef NC |
7840 | } |
7841 | ||
c19d1205 ZW |
7842 | mapping_state (MAP_ARM); |
7843 | inst.instruction = opcode->avalue; | |
7844 | if (opcode->tag == OT_unconditionalF) | |
7845 | inst.instruction |= 0xF << 28; | |
7846 | else | |
7847 | inst.instruction |= inst.cond << 28; | |
7848 | inst.size = INSN_SIZE; | |
7849 | if (!parse_operands (p, opcode->operands)) | |
7850 | opcode->aencode (); | |
b99bd4ef | 7851 | } |
c19d1205 ZW |
7852 | output_inst (str); |
7853 | } | |
b99bd4ef | 7854 | |
c19d1205 ZW |
7855 | /* Various frobbings of labels and their addresses. */ |
7856 | ||
7857 | void | |
7858 | arm_start_line_hook (void) | |
7859 | { | |
7860 | last_label_seen = NULL; | |
b99bd4ef NC |
7861 | } |
7862 | ||
c19d1205 ZW |
7863 | void |
7864 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 7865 | { |
c19d1205 | 7866 | last_label_seen = sym; |
b99bd4ef | 7867 | |
c19d1205 | 7868 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 7869 | |
c19d1205 ZW |
7870 | #if defined OBJ_COFF || defined OBJ_ELF |
7871 | ARM_SET_INTERWORK (sym, support_interwork); | |
7872 | #endif | |
b99bd4ef | 7873 | |
c19d1205 ZW |
7874 | /* Note - do not allow local symbols (.Lxxx) to be labeled |
7875 | as Thumb functions. This is because these labels, whilst | |
7876 | they exist inside Thumb code, are not the entry points for | |
7877 | possible ARM->Thumb calls. Also, these labels can be used | |
7878 | as part of a computed goto or switch statement. eg gcc | |
7879 | can generate code that looks like this: | |
b99bd4ef | 7880 | |
c19d1205 ZW |
7881 | ldr r2, [pc, .Laaa] |
7882 | lsl r3, r3, #2 | |
7883 | ldr r2, [r3, r2] | |
7884 | mov pc, r2 | |
b99bd4ef | 7885 | |
c19d1205 ZW |
7886 | .Lbbb: .word .Lxxx |
7887 | .Lccc: .word .Lyyy | |
7888 | ..etc... | |
7889 | .Laaa: .word Lbbb | |
b99bd4ef | 7890 | |
c19d1205 ZW |
7891 | The first instruction loads the address of the jump table. |
7892 | The second instruction converts a table index into a byte offset. | |
7893 | The third instruction gets the jump address out of the table. | |
7894 | The fourth instruction performs the jump. | |
b99bd4ef | 7895 | |
c19d1205 ZW |
7896 | If the address stored at .Laaa is that of a symbol which has the |
7897 | Thumb_Func bit set, then the linker will arrange for this address | |
7898 | to have the bottom bit set, which in turn would mean that the | |
7899 | address computation performed by the third instruction would end | |
7900 | up with the bottom bit set. Since the ARM is capable of unaligned | |
7901 | word loads, the instruction would then load the incorrect address | |
7902 | out of the jump table, and chaos would ensue. */ | |
7903 | if (label_is_thumb_function_name | |
7904 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
7905 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 7906 | { |
c19d1205 ZW |
7907 | /* When the address of a Thumb function is taken the bottom |
7908 | bit of that address should be set. This will allow | |
7909 | interworking between Arm and Thumb functions to work | |
7910 | correctly. */ | |
b99bd4ef | 7911 | |
c19d1205 | 7912 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 7913 | |
c19d1205 | 7914 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 7915 | } |
b99bd4ef NC |
7916 | } |
7917 | ||
c19d1205 ZW |
7918 | int |
7919 | arm_data_in_code (void) | |
b99bd4ef | 7920 | { |
c19d1205 | 7921 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 7922 | { |
c19d1205 ZW |
7923 | *input_line_pointer = '/'; |
7924 | input_line_pointer += 5; | |
7925 | *input_line_pointer = 0; | |
7926 | return 1; | |
b99bd4ef NC |
7927 | } |
7928 | ||
c19d1205 | 7929 | return 0; |
b99bd4ef NC |
7930 | } |
7931 | ||
c19d1205 ZW |
7932 | char * |
7933 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 7934 | { |
c19d1205 | 7935 | int len; |
b99bd4ef | 7936 | |
c19d1205 ZW |
7937 | if (thumb_mode && (len = strlen (name)) > 5 |
7938 | && streq (name + len - 5, "/data")) | |
7939 | *(name + len - 5) = 0; | |
b99bd4ef | 7940 | |
c19d1205 | 7941 | return name; |
b99bd4ef | 7942 | } |
c19d1205 ZW |
7943 | \f |
7944 | /* Table of all register names defined by default. The user can | |
7945 | define additional names with .req. Note that all register names | |
7946 | should appear in both upper and lowercase variants. Some registers | |
7947 | also have mixed-case names. */ | |
b99bd4ef | 7948 | |
c19d1205 ZW |
7949 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE } |
7950 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) | |
7951 | #define REGSET(p,t) \ | |
7952 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
7953 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
7954 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
7955 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
7ed4c4c5 | 7956 | |
c19d1205 | 7957 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 7958 | { |
c19d1205 ZW |
7959 | /* ARM integer registers. */ |
7960 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 7961 | |
c19d1205 ZW |
7962 | /* ATPCS synonyms. */ |
7963 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
7964 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
7965 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 7966 | |
c19d1205 ZW |
7967 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
7968 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
7969 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 7970 | |
c19d1205 ZW |
7971 | /* Well-known aliases. */ |
7972 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
7973 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
7974 | ||
7975 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
7976 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
7977 | ||
7978 | /* Coprocessor numbers. */ | |
7979 | REGSET(p, CP), REGSET(P, CP), | |
7980 | ||
7981 | /* Coprocessor register numbers. The "cr" variants are for backward | |
7982 | compatibility. */ | |
7983 | REGSET(c, CN), REGSET(C, CN), | |
7984 | REGSET(cr, CN), REGSET(CR, CN), | |
7985 | ||
7986 | /* FPA registers. */ | |
7987 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
7988 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
7989 | ||
7990 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
7991 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
7992 | ||
7993 | /* VFP SP registers. */ | |
7994 | REGSET(s,VFS), | |
7995 | REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS), | |
7996 | REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS), | |
7997 | REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS), | |
7998 | REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS), | |
7999 | ||
8000 | REGSET(S,VFS), | |
8001 | REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS), | |
8002 | REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS), | |
8003 | REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS), | |
8004 | REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS), | |
8005 | ||
8006 | /* VFP DP Registers. */ | |
8007 | REGSET(d,VFD), REGSET(D,VFS), | |
8008 | ||
8009 | /* VFP control registers. */ | |
8010 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
8011 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
8012 | ||
8013 | /* Maverick DSP coprocessor registers. */ | |
8014 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
8015 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
8016 | ||
8017 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
8018 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
8019 | REGDEF(dspsc,0,DSPSC), | |
8020 | ||
8021 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
8022 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
8023 | REGDEF(DSPSC,0,DSPSC), | |
8024 | ||
8025 | /* iWMMXt data registers - p0, c0-15. */ | |
8026 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
8027 | ||
8028 | /* iWMMXt control registers - p1, c0-3. */ | |
8029 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
8030 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
8031 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
8032 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
8033 | ||
8034 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
8035 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
8036 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
8037 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
8038 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
8039 | ||
8040 | /* XScale accumulator registers. */ | |
8041 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
8042 | }; | |
8043 | #undef REGDEF | |
8044 | #undef REGNUM | |
8045 | #undef REGSET | |
7ed4c4c5 | 8046 | |
c19d1205 ZW |
8047 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
8048 | within psr_required_here. */ | |
8049 | static const struct asm_psr psrs[] = | |
8050 | { | |
8051 | /* Backward compatibility notation. Note that "all" is no longer | |
8052 | truly all possible PSR bits. */ | |
8053 | {"all", PSR_c | PSR_f}, | |
8054 | {"flg", PSR_f}, | |
8055 | {"ctl", PSR_c}, | |
8056 | ||
8057 | /* Individual flags. */ | |
8058 | {"f", PSR_f}, | |
8059 | {"c", PSR_c}, | |
8060 | {"x", PSR_x}, | |
8061 | {"s", PSR_s}, | |
8062 | /* Combinations of flags. */ | |
8063 | {"fs", PSR_f | PSR_s}, | |
8064 | {"fx", PSR_f | PSR_x}, | |
8065 | {"fc", PSR_f | PSR_c}, | |
8066 | {"sf", PSR_s | PSR_f}, | |
8067 | {"sx", PSR_s | PSR_x}, | |
8068 | {"sc", PSR_s | PSR_c}, | |
8069 | {"xf", PSR_x | PSR_f}, | |
8070 | {"xs", PSR_x | PSR_s}, | |
8071 | {"xc", PSR_x | PSR_c}, | |
8072 | {"cf", PSR_c | PSR_f}, | |
8073 | {"cs", PSR_c | PSR_s}, | |
8074 | {"cx", PSR_c | PSR_x}, | |
8075 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
8076 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
8077 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
8078 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
8079 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
8080 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
8081 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
8082 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
8083 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
8084 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
8085 | {"scf", PSR_s | PSR_c | PSR_f}, | |
8086 | {"scx", PSR_s | PSR_c | PSR_x}, | |
8087 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
8088 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
8089 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
8090 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
8091 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
8092 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
8093 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
8094 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
8095 | {"csf", PSR_c | PSR_s | PSR_f}, | |
8096 | {"csx", PSR_c | PSR_s | PSR_x}, | |
8097 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
8098 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
8099 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
8100 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
8101 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
8102 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
8103 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
8104 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
8105 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
8106 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
8107 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
8108 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
8109 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
8110 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
8111 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
8112 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
8113 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
8114 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
8115 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
8116 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
8117 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
8118 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
8119 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
8120 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
8121 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
8122 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
8123 | }; | |
8124 | ||
8125 | /* Table of all shift-in-operand names. */ | |
8126 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 8127 | { |
c19d1205 ZW |
8128 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
8129 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
8130 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
8131 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
8132 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
8133 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
8134 | }; | |
b99bd4ef | 8135 | |
c19d1205 ZW |
8136 | /* Table of all explicit relocation names. */ |
8137 | #ifdef OBJ_ELF | |
8138 | static struct reloc_entry reloc_names[] = | |
8139 | { | |
8140 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
8141 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
8142 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
8143 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
8144 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
8145 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
8146 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
8147 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
8148 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
8149 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
8150 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} | |
8151 | }; | |
8152 | #endif | |
b99bd4ef | 8153 | |
c19d1205 ZW |
8154 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
8155 | static const struct asm_cond conds[] = | |
8156 | { | |
8157 | {"eq", 0x0}, | |
8158 | {"ne", 0x1}, | |
8159 | {"cs", 0x2}, {"hs", 0x2}, | |
8160 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
8161 | {"mi", 0x4}, | |
8162 | {"pl", 0x5}, | |
8163 | {"vs", 0x6}, | |
8164 | {"vc", 0x7}, | |
8165 | {"hi", 0x8}, | |
8166 | {"ls", 0x9}, | |
8167 | {"ge", 0xa}, | |
8168 | {"lt", 0xb}, | |
8169 | {"gt", 0xc}, | |
8170 | {"le", 0xd}, | |
8171 | {"al", 0xe} | |
8172 | }; | |
bfae80f2 | 8173 | |
c19d1205 ZW |
8174 | /* Table of ARM-format instructions. */ |
8175 | ||
8176 | /* Macros for gluing together operand strings. N.B. In all cases | |
8177 | other than OPS0, the trailing OP_stop comes from default | |
8178 | zero-initialization of the unspecified elements of the array. */ | |
8179 | #define OPS0() { OP_stop, } | |
8180 | #define OPS1(a) { OP_##a, } | |
8181 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
8182 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
8183 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
8184 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
8185 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
8186 | ||
8187 | /* These macros abstract out the exact format of the mnemonic table and | |
8188 | save some repeated characters. */ | |
8189 | ||
8190 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
8191 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
8192 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8193 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8194 | |
8195 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
8196 | a T_MNEM_xyz enumerator. */ | |
8197 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
8198 | TxCE(mnem, aop, 0x##top, nops, ops, ae, te) | |
8199 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ | |
8200 | TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8201 | ||
8202 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
8203 | infix after the third character. */ | |
8204 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
8205 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8206 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8207 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
8208 | TxC3(mnem, aop, 0x##top, nops, ops, ae, te) | |
8209 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ | |
8210 | TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8211 | ||
8212 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
8213 | appear in the condition table. */ | |
8214 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
8215 | { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
1887dd22 | 8216 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8217 | |
8218 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
8219 | TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ | |
8220 | TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ | |
8221 | TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ | |
8222 | TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ | |
8223 | TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ | |
8224 | TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ | |
8225 | TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ | |
8226 | TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ | |
8227 | TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ | |
8228 | TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ | |
8229 | TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ | |
8230 | TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ | |
8231 | TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ | |
8232 | TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ | |
8233 | TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ | |
8234 | TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ | |
8235 | TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ | |
8236 | TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ | |
8237 | TxCM_(m1, al, m2, op, top, nops, ops, ae, te) | |
8238 | ||
8239 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8240 | TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) | |
8241 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8242 | TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) | |
8243 | ||
8244 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
8245 | field is still 0xE. */ | |
8246 | #define TUE(mnem, op, top, nops, ops, ae, te) \ | |
8247 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8248 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8249 | |
8250 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
8251 | condition code field. */ | |
8252 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
8253 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8254 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8255 | |
8256 | /* ARM-only variants of all the above. */ | |
6a86118a NC |
8257 | #define CE(mnem, op, nops, ops, ae) \ |
8258 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8259 | ||
8260 | #define C3(mnem, op, nops, ops, ae) \ | |
8261 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8262 | ||
8f06b2d8 PB |
8263 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
8264 | #define cCE(mnem, op, nops, ops, ae) \ | |
8265 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8266 | ||
8267 | #define cC3(mnem, op, nops, ops, ae) \ | |
8268 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8269 | ||
6a86118a NC |
8270 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
8271 | { #m1 #m2 #m3, OPS##nops ops, \ | |
8272 | sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
8273 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8274 | ||
8275 | #define CM(m1, m2, op, nops, ops, ae) \ | |
8276 | xCM_(m1, , m2, op, nops, ops, ae), \ | |
8277 | xCM_(m1, eq, m2, op, nops, ops, ae), \ | |
8278 | xCM_(m1, ne, m2, op, nops, ops, ae), \ | |
8279 | xCM_(m1, cs, m2, op, nops, ops, ae), \ | |
8280 | xCM_(m1, hs, m2, op, nops, ops, ae), \ | |
8281 | xCM_(m1, cc, m2, op, nops, ops, ae), \ | |
8282 | xCM_(m1, ul, m2, op, nops, ops, ae), \ | |
8283 | xCM_(m1, lo, m2, op, nops, ops, ae), \ | |
8284 | xCM_(m1, mi, m2, op, nops, ops, ae), \ | |
8285 | xCM_(m1, pl, m2, op, nops, ops, ae), \ | |
8286 | xCM_(m1, vs, m2, op, nops, ops, ae), \ | |
8287 | xCM_(m1, vc, m2, op, nops, ops, ae), \ | |
8288 | xCM_(m1, hi, m2, op, nops, ops, ae), \ | |
8289 | xCM_(m1, ls, m2, op, nops, ops, ae), \ | |
8290 | xCM_(m1, ge, m2, op, nops, ops, ae), \ | |
8291 | xCM_(m1, lt, m2, op, nops, ops, ae), \ | |
8292 | xCM_(m1, gt, m2, op, nops, ops, ae), \ | |
8293 | xCM_(m1, le, m2, op, nops, ops, ae), \ | |
8294 | xCM_(m1, al, m2, op, nops, ops, ae) | |
8295 | ||
8296 | #define UE(mnem, op, nops, ops, ae) \ | |
8297 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8298 | ||
8299 | #define UF(mnem, op, nops, ops, ae) \ | |
8300 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8301 | ||
c19d1205 ZW |
8302 | #define do_0 0 |
8303 | ||
8304 | /* Thumb-only, unconditional. */ | |
8305 | #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) | |
8306 | ||
8307 | /* ARM-only, takes either a suffix or a position-3 infix | |
8308 | (for an FPA corner case). */ | |
8309 | #define C3E(mnem, op, nops, ops, ae) \ | |
8310 | { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 } | |
bfae80f2 | 8311 | |
c19d1205 | 8312 | static const struct asm_opcode insns[] = |
bfae80f2 | 8313 | { |
c19d1205 ZW |
8314 | #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */ |
8315 | #define THUMB_VARIANT ARM_EXT_V4T | |
8316 | tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), | |
8317 | tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
8318 | tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
8319 | tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
8320 | tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
8321 | tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
8322 | tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub), | |
8323 | tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub), | |
8324 | tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
8325 | tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8326 | tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
8327 | tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
8328 | tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
8329 | tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8330 | tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), | |
8331 | tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), | |
8332 | ||
8333 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
8334 | for setting PSR flag bits. They are obsolete in V6 and do not | |
8335 | have Thumb equivalents. */ | |
8336 | tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
8337 | tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
8338 | C3(tstp, 110f000, 2, (RR, SH), cmp), | |
8339 | tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
8340 | tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
8341 | C3(cmpp, 150f000, 2, (RR, SH), cmp), | |
8342 | tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
8343 | tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
8344 | C3(cmnp, 170f000, 2, (RR, SH), cmp), | |
8345 | ||
8346 | tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), | |
8347 | tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), | |
8348 | tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), | |
8349 | tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), | |
8350 | ||
8351 | tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst), | |
8352 | tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst), | |
8353 | tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst), | |
8354 | tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst), | |
8355 | ||
8356 | tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8357 | tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8358 | tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8359 | tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8360 | ||
8361 | TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), | |
2fc8bdac ZW |
8362 | TCE(b, a000000, e000, 1, (EXPr), branch, t_branch), |
8363 | TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23), | |
bfae80f2 | 8364 | |
c19d1205 | 8365 | /* Pseudo ops. */ |
e9f89963 | 8366 | tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac ZW |
8367 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
8368 | tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), | |
c19d1205 ZW |
8369 | |
8370 | /* Thumb-compatibility pseudo ops. */ | |
8371 | tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), | |
8372 | tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), | |
8373 | tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), | |
8374 | tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
8375 | tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), | |
2fc8bdac | 8376 | tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), |
c19d1205 ZW |
8377 | tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), |
8378 | tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), | |
8379 | tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), | |
8380 | tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), | |
8381 | tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), | |
8382 | tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), | |
8383 | ||
8384 | #undef THUMB_VARIANT | |
8385 | #define THUMB_VARIANT ARM_EXT_V6 | |
2fc8bdac | 8386 | TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
8387 | |
8388 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
8389 | #undef THUMB_VARIANT | |
8390 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8391 | TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), | |
8392 | TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
8393 | TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
8394 | TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
8395 | C3(teqp, 130f000, 2, (RR, SH), cmp), | |
8396 | ||
8397 | TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8398 | TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8399 | TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8400 | TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8401 | ||
9c3c69f2 PB |
8402 | TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
8403 | TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 8404 | |
9c3c69f2 PB |
8405 | TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
8406 | TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
8407 | |
8408 | /* V1 instructions with no Thumb analogue at all. */ | |
8409 | CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), | |
8410 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), | |
8411 | ||
8412 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
8413 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
8414 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
8415 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
8416 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
8417 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
8418 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
8419 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
8420 | ||
8421 | #undef ARM_VARIANT | |
8422 | #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */ | |
8423 | #undef THUMB_VARIANT | |
8424 | #define THUMB_VARIANT ARM_EXT_V4T | |
8425 | tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
8426 | tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
8427 | ||
8428 | #undef THUMB_VARIANT | |
8429 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8430 | TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
8431 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), | |
8432 | ||
8433 | /* Generic coprocessor instructions. */ | |
8434 | TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
8435 | TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8436 | TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8437 | TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8438 | TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8439 | TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8440 | TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8441 | ||
8442 | #undef ARM_VARIANT | |
8443 | #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */ | |
8444 | CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
8445 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
8446 | ||
8447 | #undef ARM_VARIANT | |
8448 | #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */ | |
8449 | TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs), | |
8450 | TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr), | |
8451 | ||
8452 | #undef ARM_VARIANT | |
8453 | #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */ | |
8454 | TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8455 | CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8456 | TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8457 | CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8458 | TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8459 | CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8460 | TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8461 | CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8462 | ||
8463 | #undef ARM_VARIANT | |
8464 | #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */ | |
8465 | #undef THUMB_VARIANT | |
8466 | #define THUMB_VARIANT ARM_EXT_V4T | |
8467 | tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8468 | tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8469 | tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8470 | tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
8471 | tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8472 | tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
8473 | ||
8474 | #undef ARM_VARIANT | |
8475 | #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5 | |
8476 | /* ARM Architecture 4T. */ | |
8477 | /* Note: bx (and blx) are required on V5, even if the processor does | |
8478 | not support Thumb. */ | |
8479 | TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), | |
8480 | ||
8481 | #undef ARM_VARIANT | |
8482 | #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */ | |
8483 | #undef THUMB_VARIANT | |
8484 | #define THUMB_VARIANT ARM_EXT_V5T | |
8485 | /* Note: blx has 2 variants; the .value coded here is for | |
8486 | BLX(2). Only this variant has conditional execution. */ | |
8487 | TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), | |
8488 | TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
8489 | ||
8490 | #undef THUMB_VARIANT | |
8491 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8492 | TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), | |
8493 | TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8494 | TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8495 | TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8496 | TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8497 | TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
8498 | TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8499 | TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8500 | ||
8501 | #undef ARM_VARIANT | |
8502 | #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */ | |
8503 | TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8504 | TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8505 | TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8506 | TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8507 | ||
8508 | TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8509 | TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8510 | ||
8511 | TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8512 | TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8513 | TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8514 | TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8515 | ||
8516 | TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8517 | TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8518 | TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8519 | TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8520 | ||
8521 | TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8522 | TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8523 | ||
8524 | TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8525 | TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8526 | TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8527 | TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8528 | ||
8529 | #undef ARM_VARIANT | |
8530 | #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */ | |
8531 | TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), | |
8532 | TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
8533 | TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
8534 | ||
8535 | TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8536 | TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8537 | ||
8538 | #undef ARM_VARIANT | |
8539 | #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */ | |
8540 | TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), | |
8541 | ||
8542 | #undef ARM_VARIANT | |
8543 | #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */ | |
8544 | #undef THUMB_VARIANT | |
8545 | #define THUMB_VARIANT ARM_EXT_V6 | |
8546 | TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
8547 | TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
8548 | tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8549 | tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8550 | tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8551 | tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8552 | tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8553 | tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8554 | tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8555 | TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), | |
8556 | ||
8557 | #undef THUMB_VARIANT | |
8558 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8559 | TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0), | |
8560 | TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), | |
8561 | TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8562 | TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8563 | TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
8564 | TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
8565 | TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8566 | TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8567 | TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8568 | TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8569 | TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8570 | TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8571 | TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8572 | TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8573 | TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8574 | TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8575 | TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8576 | TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8577 | TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8578 | TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8579 | TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8580 | TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8581 | TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8582 | TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8583 | TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8584 | TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8585 | TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8586 | TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8587 | TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8588 | TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8589 | TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8590 | TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8591 | TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8592 | TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8593 | TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8594 | TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8595 | TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8596 | TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8597 | TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8598 | TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8599 | TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8600 | TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8601 | TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
8602 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
8603 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
8604 | TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
8605 | TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
8606 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
8607 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
8608 | TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
8609 | TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8610 | TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8611 | TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8612 | TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8613 | TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8614 | TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8615 | TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8616 | TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8617 | TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8618 | TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8619 | TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8620 | TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8621 | TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8622 | TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8623 | TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8624 | TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8625 | TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8626 | TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8627 | TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8628 | TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8629 | TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8630 | TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8631 | TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8632 | TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8633 | TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8634 | TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8635 | TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8636 | TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs), | |
8637 | UF(srsib, 9cd0500, 1, (I31w), srs), | |
8638 | UF(srsda, 84d0500, 1, (I31w), srs), | |
8639 | TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs), | |
8640 | TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), | |
8641 | TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), | |
8642 | TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), | |
8643 | TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
8644 | TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8645 | TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8646 | TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
8647 | TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
8648 | ||
8649 | #undef ARM_VARIANT | |
8650 | #define ARM_VARIANT ARM_EXT_V6K | |
8651 | #undef THUMB_VARIANT | |
8652 | #define THUMB_VARIANT ARM_EXT_V6K | |
8653 | tCE(yield, 320f001, yield, 0, (), noargs, t_hint), | |
8654 | tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), | |
8655 | tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), | |
8656 | tCE(sev, 320f004, sev, 0, (), noargs, t_hint), | |
8657 | ||
8658 | #undef THUMB_VARIANT | |
8659 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8660 | TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
8661 | TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
8662 | TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), | |
8663 | TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
8664 | TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
8665 | TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), | |
8666 | TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), | |
8667 | ||
8668 | #undef ARM_VARIANT | |
8669 | #define ARM_VARIANT ARM_EXT_V6Z | |
8670 | TCE(smi, 1600070, f7f08000, 1, (EXPi), smi, t_smi), | |
8671 | ||
8672 | #undef ARM_VARIANT | |
8673 | #define ARM_VARIANT ARM_EXT_V6T2 | |
8674 | TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), | |
8675 | TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
8676 | TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
8677 | TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
8678 | ||
8679 | TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
8680 | TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
8681 | TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
8682 | TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
8683 | ||
8684 | TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8685 | TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8686 | TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8687 | TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8688 | ||
8689 | UT(cbnz, b900, 2, (RR, EXP), t_czb), | |
8690 | UT(cbz, b100, 2, (RR, EXP), t_czb), | |
8691 | /* ARM does not really have an IT instruction. */ | |
8692 | TUE(it, 0, bf08, 1, (COND), it, t_it), | |
8693 | TUE(itt, 0, bf0c, 1, (COND), it, t_it), | |
8694 | TUE(ite, 0, bf04, 1, (COND), it, t_it), | |
8695 | TUE(ittt, 0, bf0e, 1, (COND), it, t_it), | |
8696 | TUE(itet, 0, bf06, 1, (COND), it, t_it), | |
8697 | TUE(itte, 0, bf0a, 1, (COND), it, t_it), | |
8698 | TUE(itee, 0, bf02, 1, (COND), it, t_it), | |
8699 | TUE(itttt, 0, bf0f, 1, (COND), it, t_it), | |
8700 | TUE(itett, 0, bf07, 1, (COND), it, t_it), | |
8701 | TUE(ittet, 0, bf0b, 1, (COND), it, t_it), | |
8702 | TUE(iteet, 0, bf03, 1, (COND), it, t_it), | |
8703 | TUE(ittte, 0, bf0d, 1, (COND), it, t_it), | |
8704 | TUE(itete, 0, bf05, 1, (COND), it, t_it), | |
8705 | TUE(ittee, 0, bf09, 1, (COND), it, t_it), | |
8706 | TUE(iteee, 0, bf01, 1, (COND), it, t_it), | |
8707 | ||
92e90b6e PB |
8708 | /* Thumb2 only instructions. */ |
8709 | #undef ARM_VARIANT | |
8710 | #define ARM_VARIANT 0 | |
8711 | ||
8712 | TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
8713 | TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
8714 | TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), | |
8715 | TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), | |
8716 | ||
c19d1205 ZW |
8717 | #undef ARM_VARIANT |
8718 | #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */ | |
8f06b2d8 PB |
8719 | cCE(wfs, e200110, 1, (RR), rd), |
8720 | cCE(rfs, e300110, 1, (RR), rd), | |
8721 | cCE(wfc, e400110, 1, (RR), rd), | |
8722 | cCE(rfc, e500110, 1, (RR), rd), | |
8723 | ||
8724 | cC3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr), | |
8725 | cC3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr), | |
8726 | cC3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr), | |
8727 | cC3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr), | |
8728 | ||
8729 | cC3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr), | |
8730 | cC3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr), | |
8731 | cC3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr), | |
8732 | cC3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr), | |
8733 | ||
8734 | cC3(mvfs, e008100, 2, (RF, RF_IF), rd_rm), | |
8735 | cC3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), | |
8736 | cC3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), | |
8737 | cC3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), | |
8738 | cC3(mvfd, e008180, 2, (RF, RF_IF), rd_rm), | |
8739 | cC3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), | |
8740 | cC3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), | |
8741 | cC3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), | |
8742 | cC3(mvfe, e088100, 2, (RF, RF_IF), rd_rm), | |
8743 | cC3(mvfep, e088120, 2, (RF, RF_IF), rd_rm), | |
8744 | cC3(mvfem, e088140, 2, (RF, RF_IF), rd_rm), | |
8745 | cC3(mvfez, e088160, 2, (RF, RF_IF), rd_rm), | |
8746 | ||
8747 | cC3(mnfs, e108100, 2, (RF, RF_IF), rd_rm), | |
8748 | cC3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), | |
8749 | cC3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), | |
8750 | cC3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), | |
8751 | cC3(mnfd, e108180, 2, (RF, RF_IF), rd_rm), | |
8752 | cC3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), | |
8753 | cC3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), | |
8754 | cC3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), | |
8755 | cC3(mnfe, e188100, 2, (RF, RF_IF), rd_rm), | |
8756 | cC3(mnfep, e188120, 2, (RF, RF_IF), rd_rm), | |
8757 | cC3(mnfem, e188140, 2, (RF, RF_IF), rd_rm), | |
8758 | cC3(mnfez, e188160, 2, (RF, RF_IF), rd_rm), | |
8759 | ||
8760 | cC3(abss, e208100, 2, (RF, RF_IF), rd_rm), | |
8761 | cC3(abssp, e208120, 2, (RF, RF_IF), rd_rm), | |
8762 | cC3(abssm, e208140, 2, (RF, RF_IF), rd_rm), | |
8763 | cC3(abssz, e208160, 2, (RF, RF_IF), rd_rm), | |
8764 | cC3(absd, e208180, 2, (RF, RF_IF), rd_rm), | |
8765 | cC3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), | |
8766 | cC3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), | |
8767 | cC3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), | |
8768 | cC3(abse, e288100, 2, (RF, RF_IF), rd_rm), | |
8769 | cC3(absep, e288120, 2, (RF, RF_IF), rd_rm), | |
8770 | cC3(absem, e288140, 2, (RF, RF_IF), rd_rm), | |
8771 | cC3(absez, e288160, 2, (RF, RF_IF), rd_rm), | |
8772 | ||
8773 | cC3(rnds, e308100, 2, (RF, RF_IF), rd_rm), | |
8774 | cC3(rndsp, e308120, 2, (RF, RF_IF), rd_rm), | |
8775 | cC3(rndsm, e308140, 2, (RF, RF_IF), rd_rm), | |
8776 | cC3(rndsz, e308160, 2, (RF, RF_IF), rd_rm), | |
8777 | cC3(rndd, e308180, 2, (RF, RF_IF), rd_rm), | |
8778 | cC3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), | |
8779 | cC3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), | |
8780 | cC3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), | |
8781 | cC3(rnde, e388100, 2, (RF, RF_IF), rd_rm), | |
8782 | cC3(rndep, e388120, 2, (RF, RF_IF), rd_rm), | |
8783 | cC3(rndem, e388140, 2, (RF, RF_IF), rd_rm), | |
8784 | cC3(rndez, e388160, 2, (RF, RF_IF), rd_rm), | |
8785 | ||
8786 | cC3(sqts, e408100, 2, (RF, RF_IF), rd_rm), | |
8787 | cC3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), | |
8788 | cC3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), | |
8789 | cC3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), | |
8790 | cC3(sqtd, e408180, 2, (RF, RF_IF), rd_rm), | |
8791 | cC3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), | |
8792 | cC3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), | |
8793 | cC3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), | |
8794 | cC3(sqte, e488100, 2, (RF, RF_IF), rd_rm), | |
8795 | cC3(sqtep, e488120, 2, (RF, RF_IF), rd_rm), | |
8796 | cC3(sqtem, e488140, 2, (RF, RF_IF), rd_rm), | |
8797 | cC3(sqtez, e488160, 2, (RF, RF_IF), rd_rm), | |
8798 | ||
8799 | cC3(logs, e508100, 2, (RF, RF_IF), rd_rm), | |
8800 | cC3(logsp, e508120, 2, (RF, RF_IF), rd_rm), | |
8801 | cC3(logsm, e508140, 2, (RF, RF_IF), rd_rm), | |
8802 | cC3(logsz, e508160, 2, (RF, RF_IF), rd_rm), | |
8803 | cC3(logd, e508180, 2, (RF, RF_IF), rd_rm), | |
8804 | cC3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), | |
8805 | cC3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), | |
8806 | cC3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), | |
8807 | cC3(loge, e588100, 2, (RF, RF_IF), rd_rm), | |
8808 | cC3(logep, e588120, 2, (RF, RF_IF), rd_rm), | |
8809 | cC3(logem, e588140, 2, (RF, RF_IF), rd_rm), | |
8810 | cC3(logez, e588160, 2, (RF, RF_IF), rd_rm), | |
8811 | ||
8812 | cC3(lgns, e608100, 2, (RF, RF_IF), rd_rm), | |
8813 | cC3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), | |
8814 | cC3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), | |
8815 | cC3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), | |
8816 | cC3(lgnd, e608180, 2, (RF, RF_IF), rd_rm), | |
8817 | cC3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), | |
8818 | cC3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), | |
8819 | cC3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), | |
8820 | cC3(lgne, e688100, 2, (RF, RF_IF), rd_rm), | |
8821 | cC3(lgnep, e688120, 2, (RF, RF_IF), rd_rm), | |
8822 | cC3(lgnem, e688140, 2, (RF, RF_IF), rd_rm), | |
8823 | cC3(lgnez, e688160, 2, (RF, RF_IF), rd_rm), | |
8824 | ||
8825 | cC3(exps, e708100, 2, (RF, RF_IF), rd_rm), | |
8826 | cC3(expsp, e708120, 2, (RF, RF_IF), rd_rm), | |
8827 | cC3(expsm, e708140, 2, (RF, RF_IF), rd_rm), | |
8828 | cC3(expsz, e708160, 2, (RF, RF_IF), rd_rm), | |
8829 | cC3(expd, e708180, 2, (RF, RF_IF), rd_rm), | |
8830 | cC3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), | |
8831 | cC3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), | |
8832 | cC3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), | |
8833 | cC3(expe, e788100, 2, (RF, RF_IF), rd_rm), | |
8834 | cC3(expep, e788120, 2, (RF, RF_IF), rd_rm), | |
8835 | cC3(expem, e788140, 2, (RF, RF_IF), rd_rm), | |
8836 | cC3(expdz, e788160, 2, (RF, RF_IF), rd_rm), | |
8837 | ||
8838 | cC3(sins, e808100, 2, (RF, RF_IF), rd_rm), | |
8839 | cC3(sinsp, e808120, 2, (RF, RF_IF), rd_rm), | |
8840 | cC3(sinsm, e808140, 2, (RF, RF_IF), rd_rm), | |
8841 | cC3(sinsz, e808160, 2, (RF, RF_IF), rd_rm), | |
8842 | cC3(sind, e808180, 2, (RF, RF_IF), rd_rm), | |
8843 | cC3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), | |
8844 | cC3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), | |
8845 | cC3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), | |
8846 | cC3(sine, e888100, 2, (RF, RF_IF), rd_rm), | |
8847 | cC3(sinep, e888120, 2, (RF, RF_IF), rd_rm), | |
8848 | cC3(sinem, e888140, 2, (RF, RF_IF), rd_rm), | |
8849 | cC3(sinez, e888160, 2, (RF, RF_IF), rd_rm), | |
8850 | ||
8851 | cC3(coss, e908100, 2, (RF, RF_IF), rd_rm), | |
8852 | cC3(cossp, e908120, 2, (RF, RF_IF), rd_rm), | |
8853 | cC3(cossm, e908140, 2, (RF, RF_IF), rd_rm), | |
8854 | cC3(cossz, e908160, 2, (RF, RF_IF), rd_rm), | |
8855 | cC3(cosd, e908180, 2, (RF, RF_IF), rd_rm), | |
8856 | cC3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), | |
8857 | cC3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), | |
8858 | cC3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), | |
8859 | cC3(cose, e988100, 2, (RF, RF_IF), rd_rm), | |
8860 | cC3(cosep, e988120, 2, (RF, RF_IF), rd_rm), | |
8861 | cC3(cosem, e988140, 2, (RF, RF_IF), rd_rm), | |
8862 | cC3(cosez, e988160, 2, (RF, RF_IF), rd_rm), | |
8863 | ||
8864 | cC3(tans, ea08100, 2, (RF, RF_IF), rd_rm), | |
8865 | cC3(tansp, ea08120, 2, (RF, RF_IF), rd_rm), | |
8866 | cC3(tansm, ea08140, 2, (RF, RF_IF), rd_rm), | |
8867 | cC3(tansz, ea08160, 2, (RF, RF_IF), rd_rm), | |
8868 | cC3(tand, ea08180, 2, (RF, RF_IF), rd_rm), | |
8869 | cC3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), | |
8870 | cC3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), | |
8871 | cC3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), | |
8872 | cC3(tane, ea88100, 2, (RF, RF_IF), rd_rm), | |
8873 | cC3(tanep, ea88120, 2, (RF, RF_IF), rd_rm), | |
8874 | cC3(tanem, ea88140, 2, (RF, RF_IF), rd_rm), | |
8875 | cC3(tanez, ea88160, 2, (RF, RF_IF), rd_rm), | |
8876 | ||
8877 | cC3(asns, eb08100, 2, (RF, RF_IF), rd_rm), | |
8878 | cC3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), | |
8879 | cC3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), | |
8880 | cC3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), | |
8881 | cC3(asnd, eb08180, 2, (RF, RF_IF), rd_rm), | |
8882 | cC3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), | |
8883 | cC3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), | |
8884 | cC3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), | |
8885 | cC3(asne, eb88100, 2, (RF, RF_IF), rd_rm), | |
8886 | cC3(asnep, eb88120, 2, (RF, RF_IF), rd_rm), | |
8887 | cC3(asnem, eb88140, 2, (RF, RF_IF), rd_rm), | |
8888 | cC3(asnez, eb88160, 2, (RF, RF_IF), rd_rm), | |
8889 | ||
8890 | cC3(acss, ec08100, 2, (RF, RF_IF), rd_rm), | |
8891 | cC3(acssp, ec08120, 2, (RF, RF_IF), rd_rm), | |
8892 | cC3(acssm, ec08140, 2, (RF, RF_IF), rd_rm), | |
8893 | cC3(acssz, ec08160, 2, (RF, RF_IF), rd_rm), | |
8894 | cC3(acsd, ec08180, 2, (RF, RF_IF), rd_rm), | |
8895 | cC3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), | |
8896 | cC3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), | |
8897 | cC3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), | |
8898 | cC3(acse, ec88100, 2, (RF, RF_IF), rd_rm), | |
8899 | cC3(acsep, ec88120, 2, (RF, RF_IF), rd_rm), | |
8900 | cC3(acsem, ec88140, 2, (RF, RF_IF), rd_rm), | |
8901 | cC3(acsez, ec88160, 2, (RF, RF_IF), rd_rm), | |
8902 | ||
8903 | cC3(atns, ed08100, 2, (RF, RF_IF), rd_rm), | |
8904 | cC3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), | |
8905 | cC3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), | |
8906 | cC3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), | |
8907 | cC3(atnd, ed08180, 2, (RF, RF_IF), rd_rm), | |
8908 | cC3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), | |
8909 | cC3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), | |
8910 | cC3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), | |
8911 | cC3(atne, ed88100, 2, (RF, RF_IF), rd_rm), | |
8912 | cC3(atnep, ed88120, 2, (RF, RF_IF), rd_rm), | |
8913 | cC3(atnem, ed88140, 2, (RF, RF_IF), rd_rm), | |
8914 | cC3(atnez, ed88160, 2, (RF, RF_IF), rd_rm), | |
8915 | ||
8916 | cC3(urds, ee08100, 2, (RF, RF_IF), rd_rm), | |
8917 | cC3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), | |
8918 | cC3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), | |
8919 | cC3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), | |
8920 | cC3(urdd, ee08180, 2, (RF, RF_IF), rd_rm), | |
8921 | cC3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), | |
8922 | cC3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), | |
8923 | cC3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), | |
8924 | cC3(urde, ee88100, 2, (RF, RF_IF), rd_rm), | |
8925 | cC3(urdep, ee88120, 2, (RF, RF_IF), rd_rm), | |
8926 | cC3(urdem, ee88140, 2, (RF, RF_IF), rd_rm), | |
8927 | cC3(urdez, ee88160, 2, (RF, RF_IF), rd_rm), | |
8928 | ||
8929 | cC3(nrms, ef08100, 2, (RF, RF_IF), rd_rm), | |
8930 | cC3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), | |
8931 | cC3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), | |
8932 | cC3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), | |
8933 | cC3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), | |
8934 | cC3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), | |
8935 | cC3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), | |
8936 | cC3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), | |
8937 | cC3(nrme, ef88100, 2, (RF, RF_IF), rd_rm), | |
8938 | cC3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), | |
8939 | cC3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), | |
8940 | cC3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), | |
8941 | ||
8942 | cC3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8943 | cC3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8944 | cC3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8945 | cC3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8946 | cC3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8947 | cC3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8948 | cC3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8949 | cC3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8950 | cC3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8951 | cC3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8952 | cC3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8953 | cC3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8954 | ||
8955 | cC3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8956 | cC3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8957 | cC3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8958 | cC3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8959 | cC3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8960 | cC3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8961 | cC3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8962 | cC3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8963 | cC3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8964 | cC3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8965 | cC3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8966 | cC3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8967 | ||
8968 | cC3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8969 | cC3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8970 | cC3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8971 | cC3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8972 | cC3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8973 | cC3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8974 | cC3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8975 | cC3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8976 | cC3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8977 | cC3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8978 | cC3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8979 | cC3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8980 | ||
8981 | cC3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8982 | cC3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8983 | cC3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8984 | cC3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8985 | cC3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8986 | cC3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8987 | cC3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8988 | cC3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8989 | cC3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8990 | cC3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8991 | cC3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8992 | cC3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8993 | ||
8994 | cC3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8995 | cC3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8996 | cC3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8997 | cC3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8998 | cC3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8999 | cC3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9000 | cC3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9001 | cC3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9002 | cC3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9003 | cC3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9004 | cC3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9005 | cC3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9006 | ||
9007 | cC3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9008 | cC3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9009 | cC3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9010 | cC3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9011 | cC3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9012 | cC3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9013 | cC3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9014 | cC3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9015 | cC3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9016 | cC3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9017 | cC3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9018 | cC3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9019 | ||
9020 | cC3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9021 | cC3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9022 | cC3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9023 | cC3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9024 | cC3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9025 | cC3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9026 | cC3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9027 | cC3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9028 | cC3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9029 | cC3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9030 | cC3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9031 | cC3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9032 | ||
9033 | cC3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9034 | cC3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9035 | cC3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9036 | cC3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9037 | cC3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9038 | cC3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9039 | cC3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9040 | cC3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9041 | cC3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9042 | cC3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9043 | cC3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9044 | cC3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9045 | ||
9046 | cC3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9047 | cC3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9048 | cC3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9049 | cC3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9050 | cC3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9051 | cC3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9052 | cC3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9053 | cC3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9054 | cC3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9055 | cC3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9056 | cC3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9057 | cC3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9058 | ||
9059 | cC3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9060 | cC3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9061 | cC3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9062 | cC3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9063 | cC3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9064 | cC3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9065 | cC3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9066 | cC3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9067 | cC3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9068 | cC3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9069 | cC3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9070 | cC3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9071 | ||
9072 | cC3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9073 | cC3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9074 | cC3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9075 | cC3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9076 | cC3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9077 | cC3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9078 | cC3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9079 | cC3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9080 | cC3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9081 | cC3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9082 | cC3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9083 | cC3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9084 | ||
9085 | cC3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9086 | cC3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9087 | cC3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9088 | cC3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9089 | cC3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9090 | cC3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9091 | cC3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9092 | cC3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9093 | cC3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9094 | cC3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9095 | cC3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9096 | cC3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9097 | ||
9098 | cC3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9099 | cC3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9100 | cC3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9101 | cC3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9102 | cC3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9103 | cC3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9104 | cC3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9105 | cC3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9106 | cC3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9107 | cC3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9108 | cC3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9109 | cC3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9110 | ||
9111 | cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), | |
c19d1205 | 9112 | C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), |
8f06b2d8 | 9113 | cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), |
c19d1205 ZW |
9114 | C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), |
9115 | ||
8f06b2d8 PB |
9116 | cC3(flts, e000110, 2, (RF, RR), rn_rd), |
9117 | cC3(fltsp, e000130, 2, (RF, RR), rn_rd), | |
9118 | cC3(fltsm, e000150, 2, (RF, RR), rn_rd), | |
9119 | cC3(fltsz, e000170, 2, (RF, RR), rn_rd), | |
9120 | cC3(fltd, e000190, 2, (RF, RR), rn_rd), | |
9121 | cC3(fltdp, e0001b0, 2, (RF, RR), rn_rd), | |
9122 | cC3(fltdm, e0001d0, 2, (RF, RR), rn_rd), | |
9123 | cC3(fltdz, e0001f0, 2, (RF, RR), rn_rd), | |
9124 | cC3(flte, e080110, 2, (RF, RR), rn_rd), | |
9125 | cC3(fltep, e080130, 2, (RF, RR), rn_rd), | |
9126 | cC3(fltem, e080150, 2, (RF, RR), rn_rd), | |
9127 | cC3(fltez, e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 9128 | |
c19d1205 ZW |
9129 | /* The implementation of the FIX instruction is broken on some |
9130 | assemblers, in that it accepts a precision specifier as well as a | |
9131 | rounding specifier, despite the fact that this is meaningless. | |
9132 | To be more compatible, we accept it as well, though of course it | |
9133 | does not set any bits. */ | |
8f06b2d8 PB |
9134 | cCE(fix, e100110, 2, (RR, RF), rd_rm), |
9135 | cC3(fixp, e100130, 2, (RR, RF), rd_rm), | |
9136 | cC3(fixm, e100150, 2, (RR, RF), rd_rm), | |
9137 | cC3(fixz, e100170, 2, (RR, RF), rd_rm), | |
9138 | cC3(fixsp, e100130, 2, (RR, RF), rd_rm), | |
9139 | cC3(fixsm, e100150, 2, (RR, RF), rd_rm), | |
9140 | cC3(fixsz, e100170, 2, (RR, RF), rd_rm), | |
9141 | cC3(fixdp, e100130, 2, (RR, RF), rd_rm), | |
9142 | cC3(fixdm, e100150, 2, (RR, RF), rd_rm), | |
9143 | cC3(fixdz, e100170, 2, (RR, RF), rd_rm), | |
9144 | cC3(fixep, e100130, 2, (RR, RF), rd_rm), | |
9145 | cC3(fixem, e100150, 2, (RR, RF), rd_rm), | |
9146 | cC3(fixez, e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 9147 | |
c19d1205 ZW |
9148 | /* Instructions that were new with the real FPA, call them V2. */ |
9149 | #undef ARM_VARIANT | |
9150 | #define ARM_VARIANT FPU_FPA_EXT_V2 | |
8f06b2d8 PB |
9151 | cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
9152 | cC3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9153 | cC3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9154 | cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9155 | cC3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9156 | cC3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 ZW |
9157 | |
9158 | #undef ARM_VARIANT | |
9159 | #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */ | |
9160 | /* Moves and type conversions. */ | |
8f06b2d8 PB |
9161 | cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
9162 | cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
9163 | cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
9164 | cCE(fmstat, ef1fa10, 0, (), noargs), | |
9165 | cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9166 | cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9167 | cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9168 | cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9169 | cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9170 | cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9171 | cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), | |
9172 | cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
9173 | |
9174 | /* Memory operations. */ | |
8f06b2d8 PB |
9175 | cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst), |
9176 | cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst), | |
9177 | cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9178 | cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9179 | cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9180 | cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9181 | cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9182 | cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9183 | cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9184 | cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9185 | cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9186 | cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9187 | cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9188 | cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9189 | cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9190 | cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9191 | cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9192 | cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 9193 | |
c19d1205 | 9194 | /* Monadic operations. */ |
8f06b2d8 PB |
9195 | cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
9196 | cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9197 | cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
9198 | |
9199 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9200 | cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
9201 | cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9202 | cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9203 | cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9204 | cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9205 | cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9206 | cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9207 | cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9208 | cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 9209 | |
c19d1205 | 9210 | /* Comparisons. */ |
8f06b2d8 PB |
9211 | cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
9212 | cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), | |
9213 | cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9214 | cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 9215 | |
c19d1205 ZW |
9216 | #undef ARM_VARIANT |
9217 | #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */ | |
9218 | /* Moves and type conversions. */ | |
8f06b2d8 PB |
9219 | cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm), |
9220 | cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9221 | cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9222 | cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd), | |
9223 | cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd), | |
9224 | cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn), | |
9225 | cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn), | |
9226 | cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9227 | cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9228 | cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9229 | cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9230 | cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9231 | cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 ZW |
9232 | |
9233 | /* Memory operations. */ | |
8f06b2d8 PB |
9234 | cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst), |
9235 | cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst), | |
9236 | cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9237 | cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9238 | cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9239 | cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9240 | cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9241 | cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9242 | cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9243 | cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
b99bd4ef | 9244 | |
c19d1205 | 9245 | /* Monadic operations. */ |
8f06b2d8 PB |
9246 | cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm), |
9247 | cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm), | |
9248 | cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm), | |
c19d1205 ZW |
9249 | |
9250 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9251 | cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm), |
9252 | cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9253 | cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9254 | cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9255 | cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9256 | cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9257 | cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9258 | cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9259 | cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
b99bd4ef | 9260 | |
c19d1205 | 9261 | /* Comparisons. */ |
8f06b2d8 PB |
9262 | cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm), |
9263 | cCE(fcmpzd, eb50b40, 1, (RVD), rd), | |
9264 | cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm), | |
9265 | cCE(fcmpezd, eb50bc0, 1, (RVD), rd), | |
c19d1205 ZW |
9266 | |
9267 | #undef ARM_VARIANT | |
9268 | #define ARM_VARIANT FPU_VFP_EXT_V2 | |
8f06b2d8 PB |
9269 | cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
9270 | cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
9271 | cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn), | |
9272 | cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm), | |
c19d1205 ZW |
9273 | |
9274 | #undef ARM_VARIANT | |
9275 | #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */ | |
8f06b2d8 PB |
9276 | cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
9277 | cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9278 | cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9279 | cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9280 | cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9281 | cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9282 | cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
9283 | cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 ZW |
9284 | |
9285 | #undef ARM_VARIANT | |
9286 | #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */ | |
8f06b2d8 PB |
9287 | cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), |
9288 | cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), | |
9289 | cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), | |
9290 | cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), | |
9291 | cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), | |
9292 | cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), | |
9293 | cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), | |
9294 | cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), | |
9295 | cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), | |
9296 | cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9297 | cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9298 | cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9299 | cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9300 | cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9301 | cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9302 | cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9303 | cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9304 | cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9305 | cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd), | |
9306 | cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
9307 | cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9308 | cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9309 | cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9310 | cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9311 | cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9312 | cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9313 | cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), | |
9314 | cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), | |
9315 | cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), | |
9316 | cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn), | |
9317 | cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
9318 | cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), | |
9319 | cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), | |
9320 | cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), | |
9321 | cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), | |
9322 | cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), | |
9323 | cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), | |
9324 | cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9325 | cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9326 | cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9327 | cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9328 | cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9329 | cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9330 | cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9331 | cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9332 | cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9333 | cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
9334 | cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9335 | cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9336 | cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9337 | cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9338 | cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9339 | cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9340 | cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9341 | cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9342 | cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9343 | cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9344 | cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9345 | cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9346 | cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9347 | cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9348 | cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9349 | cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9350 | cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9351 | cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9352 | cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9353 | cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9354 | cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9355 | cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
9356 | cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
9357 | cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9358 | cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9359 | cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9360 | cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9361 | cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9362 | cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9363 | cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9364 | cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9365 | cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9366 | cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9367 | cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9368 | cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9369 | cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9370 | cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9371 | cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9372 | cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9373 | cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9374 | cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9375 | cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
9376 | cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9377 | cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9378 | cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9379 | cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9380 | cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9381 | cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9382 | cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9383 | cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9384 | cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9385 | cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9386 | cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9387 | cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9388 | cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9389 | cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9390 | cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9391 | cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9392 | cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9393 | cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9394 | cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9395 | cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9396 | cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9397 | cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
9398 | cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9399 | cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9400 | cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9401 | cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9402 | cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9403 | cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9404 | cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9405 | cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9406 | cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9407 | cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9408 | cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9409 | cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9410 | cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9411 | cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9412 | cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9413 | cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9414 | cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9415 | cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9416 | cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9417 | cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9418 | cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
9419 | cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
9420 | cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9421 | cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9422 | cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9423 | cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9424 | cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9425 | cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9426 | cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9427 | cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9428 | cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9429 | cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), | |
9430 | cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), | |
9431 | cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), | |
9432 | cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), | |
9433 | cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), | |
9434 | cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), | |
9435 | cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9436 | cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9437 | cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9438 | cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), | |
9439 | cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), | |
9440 | cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), | |
9441 | cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), | |
9442 | cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), | |
9443 | cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), | |
9444 | cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9445 | cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9446 | cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9447 | cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9448 | cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 ZW |
9449 | |
9450 | #undef ARM_VARIANT | |
9451 | #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */ | |
8f06b2d8 PB |
9452 | cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr), |
9453 | cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr), | |
9454 | cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr), | |
9455 | cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr), | |
9456 | cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr), | |
9457 | cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr), | |
9458 | cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr), | |
9459 | cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr), | |
9460 | cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), | |
9461 | cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), | |
9462 | cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), | |
9463 | cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), | |
9464 | cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), | |
9465 | cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), | |
9466 | cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), | |
9467 | cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), | |
9468 | cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), | |
9469 | cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), | |
9470 | cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), | |
9471 | cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), | |
9472 | cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), | |
9473 | cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), | |
9474 | cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), | |
9475 | cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), | |
9476 | cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), | |
9477 | cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), | |
9478 | cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), | |
9479 | cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), | |
9480 | cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
9481 | cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), | |
9482 | cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), | |
9483 | cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), | |
9484 | cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), | |
9485 | cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), | |
9486 | cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), | |
9487 | cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), | |
9488 | cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), | |
9489 | cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), | |
9490 | cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), | |
9491 | cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), | |
9492 | cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), | |
9493 | cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), | |
9494 | cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
9495 | cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
9496 | cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
9497 | cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
9498 | cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
9499 | cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
9500 | cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
9501 | cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
9502 | cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), | |
9503 | cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), | |
9504 | cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), | |
9505 | cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), | |
9506 | cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9507 | cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9508 | cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9509 | cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9510 | cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9511 | cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9512 | cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), | |
9513 | cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), | |
9514 | cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), | |
9515 | cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), | |
9516 | cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9517 | cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9518 | cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9519 | cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9520 | cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9521 | cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9522 | cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9523 | cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9524 | cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
9525 | cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
9526 | cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
9527 | cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
9528 | }; |
9529 | #undef ARM_VARIANT | |
9530 | #undef THUMB_VARIANT | |
9531 | #undef TCE | |
9532 | #undef TCM | |
9533 | #undef TUE | |
9534 | #undef TUF | |
9535 | #undef TCC | |
8f06b2d8 PB |
9536 | #undef cCE |
9537 | #undef cC3 | |
c19d1205 ZW |
9538 | #undef CE |
9539 | #undef CM | |
9540 | #undef UE | |
9541 | #undef UF | |
9542 | #undef UT | |
9543 | #undef OPS0 | |
9544 | #undef OPS1 | |
9545 | #undef OPS2 | |
9546 | #undef OPS3 | |
9547 | #undef OPS4 | |
9548 | #undef OPS5 | |
9549 | #undef OPS6 | |
9550 | #undef do_0 | |
9551 | \f | |
9552 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 9553 | |
c19d1205 ZW |
9554 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
9555 | for use in the a.out file, and stores them in the array pointed to by buf. | |
9556 | This knows about the endian-ness of the target machine and does | |
9557 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
9558 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
9559 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 9560 | |
c19d1205 ZW |
9561 | void |
9562 | md_number_to_chars (char * buf, valueT val, int n) | |
9563 | { | |
9564 | if (target_big_endian) | |
9565 | number_to_chars_bigendian (buf, val, n); | |
9566 | else | |
9567 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
9568 | } |
9569 | ||
c19d1205 ZW |
9570 | static valueT |
9571 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 9572 | { |
c19d1205 ZW |
9573 | valueT result = 0; |
9574 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 9575 | |
c19d1205 | 9576 | if (target_big_endian) |
b99bd4ef | 9577 | { |
c19d1205 ZW |
9578 | while (n--) |
9579 | { | |
9580 | result <<= 8; | |
9581 | result |= (*where++ & 255); | |
9582 | } | |
b99bd4ef | 9583 | } |
c19d1205 | 9584 | else |
b99bd4ef | 9585 | { |
c19d1205 ZW |
9586 | while (n--) |
9587 | { | |
9588 | result <<= 8; | |
9589 | result |= (where[n] & 255); | |
9590 | } | |
bfae80f2 | 9591 | } |
b99bd4ef | 9592 | |
c19d1205 | 9593 | return result; |
bfae80f2 | 9594 | } |
b99bd4ef | 9595 | |
c19d1205 | 9596 | /* MD interface: Sections. */ |
b99bd4ef | 9597 | |
c19d1205 ZW |
9598 | int |
9599 | md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, | |
9600 | segT segtype ATTRIBUTE_UNUSED) | |
9601 | { | |
9602 | as_fatal (_("md_estimate_size_before_relax\n")); | |
9603 | return 1; | |
9604 | } | |
b99bd4ef | 9605 | |
c19d1205 | 9606 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 9607 | |
c19d1205 ZW |
9608 | valueT |
9609 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
9610 | valueT size) | |
9611 | { | |
9612 | #ifdef OBJ_ELF | |
9613 | return size; | |
9614 | #else | |
9615 | /* Round all sects to multiple of 4. */ | |
9616 | return (size + 3) & ~3; | |
9617 | #endif | |
bfae80f2 | 9618 | } |
b99bd4ef | 9619 | |
c19d1205 ZW |
9620 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
9621 | of an rs_align_code fragment. */ | |
9622 | ||
9623 | void | |
9624 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 9625 | { |
c19d1205 ZW |
9626 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; |
9627 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
9628 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
9629 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
9630 | ||
9631 | int bytes, fix, noop_size; | |
9632 | char * p; | |
9633 | const char * noop; | |
bfae80f2 | 9634 | |
c19d1205 | 9635 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
9636 | return; |
9637 | ||
c19d1205 ZW |
9638 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
9639 | p = fragP->fr_literal + fragP->fr_fix; | |
9640 | fix = 0; | |
bfae80f2 | 9641 | |
c19d1205 ZW |
9642 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
9643 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 9644 | |
c19d1205 | 9645 | if (fragP->tc_frag_data) |
a737bd4d | 9646 | { |
c19d1205 ZW |
9647 | if (target_big_endian) |
9648 | noop = thumb_bigend_noop; | |
9649 | else | |
9650 | noop = thumb_noop; | |
9651 | noop_size = sizeof (thumb_noop); | |
7ed4c4c5 NC |
9652 | } |
9653 | else | |
9654 | { | |
c19d1205 ZW |
9655 | if (target_big_endian) |
9656 | noop = arm_bigend_noop; | |
9657 | else | |
9658 | noop = arm_noop; | |
9659 | noop_size = sizeof (arm_noop); | |
7ed4c4c5 | 9660 | } |
a737bd4d | 9661 | |
c19d1205 | 9662 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 9663 | { |
c19d1205 ZW |
9664 | fix = bytes & (noop_size - 1); |
9665 | memset (p, 0, fix); | |
9666 | p += fix; | |
9667 | bytes -= fix; | |
a737bd4d | 9668 | } |
a737bd4d | 9669 | |
c19d1205 | 9670 | while (bytes >= noop_size) |
a737bd4d | 9671 | { |
c19d1205 ZW |
9672 | memcpy (p, noop, noop_size); |
9673 | p += noop_size; | |
9674 | bytes -= noop_size; | |
9675 | fix += noop_size; | |
a737bd4d NC |
9676 | } |
9677 | ||
c19d1205 ZW |
9678 | fragP->fr_fix += fix; |
9679 | fragP->fr_var = noop_size; | |
a737bd4d NC |
9680 | } |
9681 | ||
c19d1205 ZW |
9682 | /* Called from md_do_align. Used to create an alignment |
9683 | frag in a code section. */ | |
9684 | ||
9685 | void | |
9686 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 9687 | { |
c19d1205 | 9688 | char * p; |
7ed4c4c5 | 9689 | |
c19d1205 ZW |
9690 | /* We assume that there will never be a requirement |
9691 | to support alignments greater than 32 bytes. */ | |
9692 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
9693 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
bfae80f2 | 9694 | |
c19d1205 ZW |
9695 | p = frag_var (rs_align_code, |
9696 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
9697 | 1, | |
9698 | (relax_substateT) max, | |
9699 | (symbolS *) NULL, | |
9700 | (offsetT) n, | |
9701 | (char *) NULL); | |
9702 | *p = 0; | |
9703 | } | |
bfae80f2 | 9704 | |
c19d1205 | 9705 | /* Perform target specific initialisation of a frag. */ |
bfae80f2 | 9706 | |
c19d1205 ZW |
9707 | void |
9708 | arm_init_frag (fragS * fragP) | |
9709 | { | |
9710 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
9711 | fragP->tc_frag_data = thumb_mode; | |
bfae80f2 RE |
9712 | } |
9713 | ||
c19d1205 ZW |
9714 | #ifdef OBJ_ELF |
9715 | /* When we change sections we need to issue a new mapping symbol. */ | |
9716 | ||
9717 | void | |
9718 | arm_elf_change_section (void) | |
bfae80f2 | 9719 | { |
c19d1205 ZW |
9720 | flagword flags; |
9721 | segment_info_type *seginfo; | |
bfae80f2 | 9722 | |
c19d1205 ZW |
9723 | /* Link an unlinked unwind index table section to the .text section. */ |
9724 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
9725 | && elf_linked_to_section (now_seg) == NULL) | |
9726 | elf_linked_to_section (now_seg) = text_section; | |
9727 | ||
9728 | if (!SEG_NORMAL (now_seg)) | |
bfae80f2 RE |
9729 | return; |
9730 | ||
c19d1205 ZW |
9731 | flags = bfd_get_section_flags (stdoutput, now_seg); |
9732 | ||
9733 | /* We can ignore sections that only contain debug info. */ | |
9734 | if ((flags & SEC_ALLOC) == 0) | |
9735 | return; | |
bfae80f2 | 9736 | |
c19d1205 ZW |
9737 | seginfo = seg_info (now_seg); |
9738 | mapstate = seginfo->tc_segment_info_data.mapstate; | |
9739 | marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; | |
bfae80f2 RE |
9740 | } |
9741 | ||
c19d1205 ZW |
9742 | int |
9743 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 9744 | { |
c19d1205 ZW |
9745 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
9746 | return SHT_ARM_EXIDX; | |
e45d0630 | 9747 | |
c19d1205 ZW |
9748 | return -1; |
9749 | } | |
9750 | \f | |
9751 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 9752 | |
c19d1205 | 9753 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 9754 | |
c19d1205 | 9755 | /* Cenerate and deferred unwind frame offset. */ |
e45d0630 | 9756 | |
bfae80f2 | 9757 | static void |
c19d1205 | 9758 | flush_pending_unwind (void) |
bfae80f2 | 9759 | { |
c19d1205 | 9760 | offsetT offset; |
bfae80f2 | 9761 | |
c19d1205 ZW |
9762 | offset = unwind.pending_offset; |
9763 | unwind.pending_offset = 0; | |
9764 | if (offset != 0) | |
9765 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
9766 | } |
9767 | ||
c19d1205 ZW |
9768 | /* Add an opcode to this list for this function. Two-byte opcodes should |
9769 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
9770 | order. */ | |
9771 | ||
bfae80f2 | 9772 | static void |
c19d1205 | 9773 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 9774 | { |
c19d1205 ZW |
9775 | /* Add any deferred stack adjustment. */ |
9776 | if (unwind.pending_offset) | |
9777 | flush_pending_unwind (); | |
bfae80f2 | 9778 | |
c19d1205 | 9779 | unwind.sp_restored = 0; |
bfae80f2 | 9780 | |
c19d1205 | 9781 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 9782 | { |
c19d1205 ZW |
9783 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
9784 | if (unwind.opcodes) | |
9785 | unwind.opcodes = xrealloc (unwind.opcodes, | |
9786 | unwind.opcode_alloc); | |
9787 | else | |
9788 | unwind.opcodes = xmalloc (unwind.opcode_alloc); | |
bfae80f2 | 9789 | } |
c19d1205 | 9790 | while (length > 0) |
bfae80f2 | 9791 | { |
c19d1205 ZW |
9792 | length--; |
9793 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
9794 | op >>= 8; | |
9795 | unwind.opcode_count++; | |
bfae80f2 | 9796 | } |
bfae80f2 RE |
9797 | } |
9798 | ||
c19d1205 ZW |
9799 | /* Add unwind opcodes to adjust the stack pointer. */ |
9800 | ||
bfae80f2 | 9801 | static void |
c19d1205 | 9802 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 9803 | { |
c19d1205 | 9804 | valueT op; |
bfae80f2 | 9805 | |
c19d1205 | 9806 | if (offset > 0x200) |
bfae80f2 | 9807 | { |
c19d1205 ZW |
9808 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
9809 | char bytes[5]; | |
9810 | int n; | |
9811 | valueT o; | |
bfae80f2 | 9812 | |
c19d1205 ZW |
9813 | /* Long form: 0xb2, uleb128. */ |
9814 | /* This might not fit in a word so add the individual bytes, | |
9815 | remembering the list is built in reverse order. */ | |
9816 | o = (valueT) ((offset - 0x204) >> 2); | |
9817 | if (o == 0) | |
9818 | add_unwind_opcode (0, 1); | |
bfae80f2 | 9819 | |
c19d1205 ZW |
9820 | /* Calculate the uleb128 encoding of the offset. */ |
9821 | n = 0; | |
9822 | while (o) | |
9823 | { | |
9824 | bytes[n] = o & 0x7f; | |
9825 | o >>= 7; | |
9826 | if (o) | |
9827 | bytes[n] |= 0x80; | |
9828 | n++; | |
9829 | } | |
9830 | /* Add the insn. */ | |
9831 | for (; n; n--) | |
9832 | add_unwind_opcode (bytes[n - 1], 1); | |
9833 | add_unwind_opcode (0xb2, 1); | |
9834 | } | |
9835 | else if (offset > 0x100) | |
bfae80f2 | 9836 | { |
c19d1205 ZW |
9837 | /* Two short opcodes. */ |
9838 | add_unwind_opcode (0x3f, 1); | |
9839 | op = (offset - 0x104) >> 2; | |
9840 | add_unwind_opcode (op, 1); | |
bfae80f2 | 9841 | } |
c19d1205 ZW |
9842 | else if (offset > 0) |
9843 | { | |
9844 | /* Short opcode. */ | |
9845 | op = (offset - 4) >> 2; | |
9846 | add_unwind_opcode (op, 1); | |
9847 | } | |
9848 | else if (offset < 0) | |
bfae80f2 | 9849 | { |
c19d1205 ZW |
9850 | offset = -offset; |
9851 | while (offset > 0x100) | |
bfae80f2 | 9852 | { |
c19d1205 ZW |
9853 | add_unwind_opcode (0x7f, 1); |
9854 | offset -= 0x100; | |
bfae80f2 | 9855 | } |
c19d1205 ZW |
9856 | op = ((offset - 4) >> 2) | 0x40; |
9857 | add_unwind_opcode (op, 1); | |
bfae80f2 | 9858 | } |
bfae80f2 RE |
9859 | } |
9860 | ||
c19d1205 ZW |
9861 | /* Finish the list of unwind opcodes for this function. */ |
9862 | static void | |
9863 | finish_unwind_opcodes (void) | |
bfae80f2 | 9864 | { |
c19d1205 | 9865 | valueT op; |
bfae80f2 | 9866 | |
c19d1205 | 9867 | if (unwind.fp_used) |
bfae80f2 | 9868 | { |
c19d1205 ZW |
9869 | /* Adjust sp as neccessary. */ |
9870 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; | |
9871 | flush_pending_unwind (); | |
bfae80f2 | 9872 | |
c19d1205 ZW |
9873 | /* After restoring sp from the frame pointer. */ |
9874 | op = 0x90 | unwind.fp_reg; | |
9875 | add_unwind_opcode (op, 1); | |
9876 | } | |
9877 | else | |
9878 | flush_pending_unwind (); | |
bfae80f2 RE |
9879 | } |
9880 | ||
bfae80f2 | 9881 | |
c19d1205 ZW |
9882 | /* Start an exception table entry. If idx is nonzero this is an index table |
9883 | entry. */ | |
bfae80f2 RE |
9884 | |
9885 | static void | |
c19d1205 | 9886 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 9887 | { |
c19d1205 ZW |
9888 | const char * text_name; |
9889 | const char * prefix; | |
9890 | const char * prefix_once; | |
9891 | const char * group_name; | |
9892 | size_t prefix_len; | |
9893 | size_t text_len; | |
9894 | char * sec_name; | |
9895 | size_t sec_name_len; | |
9896 | int type; | |
9897 | int flags; | |
9898 | int linkonce; | |
bfae80f2 | 9899 | |
c19d1205 | 9900 | if (idx) |
bfae80f2 | 9901 | { |
c19d1205 ZW |
9902 | prefix = ELF_STRING_ARM_unwind; |
9903 | prefix_once = ELF_STRING_ARM_unwind_once; | |
9904 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 9905 | } |
c19d1205 | 9906 | else |
bfae80f2 | 9907 | { |
c19d1205 ZW |
9908 | prefix = ELF_STRING_ARM_unwind_info; |
9909 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
9910 | type = SHT_PROGBITS; | |
bfae80f2 RE |
9911 | } |
9912 | ||
c19d1205 ZW |
9913 | text_name = segment_name (text_seg); |
9914 | if (streq (text_name, ".text")) | |
9915 | text_name = ""; | |
9916 | ||
9917 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
9918 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 9919 | { |
c19d1205 ZW |
9920 | prefix = prefix_once; |
9921 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
9922 | } |
9923 | ||
c19d1205 ZW |
9924 | prefix_len = strlen (prefix); |
9925 | text_len = strlen (text_name); | |
9926 | sec_name_len = prefix_len + text_len; | |
9927 | sec_name = xmalloc (sec_name_len + 1); | |
9928 | memcpy (sec_name, prefix, prefix_len); | |
9929 | memcpy (sec_name + prefix_len, text_name, text_len); | |
9930 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 9931 | |
c19d1205 ZW |
9932 | flags = SHF_ALLOC; |
9933 | linkonce = 0; | |
9934 | group_name = 0; | |
bfae80f2 | 9935 | |
c19d1205 ZW |
9936 | /* Handle COMDAT group. */ |
9937 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 9938 | { |
c19d1205 ZW |
9939 | group_name = elf_group_name (text_seg); |
9940 | if (group_name == NULL) | |
9941 | { | |
9942 | as_bad ("Group section `%s' has no group signature", | |
9943 | segment_name (text_seg)); | |
9944 | ignore_rest_of_line (); | |
9945 | return; | |
9946 | } | |
9947 | flags |= SHF_GROUP; | |
9948 | linkonce = 1; | |
bfae80f2 RE |
9949 | } |
9950 | ||
c19d1205 | 9951 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 9952 | |
c19d1205 ZW |
9953 | /* Set the setion link for index tables. */ |
9954 | if (idx) | |
9955 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
9956 | } |
9957 | ||
bfae80f2 | 9958 | |
c19d1205 ZW |
9959 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
9960 | personality routine data. Returns zero, or the index table value for | |
9961 | and inline entry. */ | |
9962 | ||
9963 | static valueT | |
9964 | create_unwind_entry (int have_data) | |
bfae80f2 | 9965 | { |
c19d1205 ZW |
9966 | int size; |
9967 | addressT where; | |
9968 | char *ptr; | |
9969 | /* The current word of data. */ | |
9970 | valueT data; | |
9971 | /* The number of bytes left in this word. */ | |
9972 | int n; | |
bfae80f2 | 9973 | |
c19d1205 | 9974 | finish_unwind_opcodes (); |
bfae80f2 | 9975 | |
c19d1205 ZW |
9976 | /* Remember the current text section. */ |
9977 | unwind.saved_seg = now_seg; | |
9978 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 9979 | |
c19d1205 | 9980 | start_unwind_section (now_seg, 0); |
bfae80f2 | 9981 | |
c19d1205 | 9982 | if (unwind.personality_routine == NULL) |
bfae80f2 | 9983 | { |
c19d1205 ZW |
9984 | if (unwind.personality_index == -2) |
9985 | { | |
9986 | if (have_data) | |
9987 | as_bad (_("handerdata in cantunwind frame")); | |
9988 | return 1; /* EXIDX_CANTUNWIND. */ | |
9989 | } | |
bfae80f2 | 9990 | |
c19d1205 ZW |
9991 | /* Use a default personality routine if none is specified. */ |
9992 | if (unwind.personality_index == -1) | |
9993 | { | |
9994 | if (unwind.opcode_count > 3) | |
9995 | unwind.personality_index = 1; | |
9996 | else | |
9997 | unwind.personality_index = 0; | |
9998 | } | |
bfae80f2 | 9999 | |
c19d1205 ZW |
10000 | /* Space for the personality routine entry. */ |
10001 | if (unwind.personality_index == 0) | |
10002 | { | |
10003 | if (unwind.opcode_count > 3) | |
10004 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 10005 | |
c19d1205 ZW |
10006 | if (!have_data) |
10007 | { | |
10008 | /* All the data is inline in the index table. */ | |
10009 | data = 0x80; | |
10010 | n = 3; | |
10011 | while (unwind.opcode_count > 0) | |
10012 | { | |
10013 | unwind.opcode_count--; | |
10014 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
10015 | n--; | |
10016 | } | |
bfae80f2 | 10017 | |
c19d1205 ZW |
10018 | /* Pad with "finish" opcodes. */ |
10019 | while (n--) | |
10020 | data = (data << 8) | 0xb0; | |
bfae80f2 | 10021 | |
c19d1205 ZW |
10022 | return data; |
10023 | } | |
10024 | size = 0; | |
10025 | } | |
10026 | else | |
10027 | /* We get two opcodes "free" in the first word. */ | |
10028 | size = unwind.opcode_count - 2; | |
10029 | } | |
10030 | else | |
10031 | /* An extra byte is required for the opcode count. */ | |
10032 | size = unwind.opcode_count + 1; | |
bfae80f2 | 10033 | |
c19d1205 ZW |
10034 | size = (size + 3) >> 2; |
10035 | if (size > 0xff) | |
10036 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 10037 | |
c19d1205 ZW |
10038 | frag_align (2, 0, 0); |
10039 | record_alignment (now_seg, 2); | |
10040 | unwind.table_entry = expr_build_dot (); | |
10041 | ||
10042 | /* Allocate the table entry. */ | |
10043 | ptr = frag_more ((size << 2) + 4); | |
10044 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 10045 | |
c19d1205 | 10046 | switch (unwind.personality_index) |
bfae80f2 | 10047 | { |
c19d1205 ZW |
10048 | case -1: |
10049 | /* ??? Should this be a PLT generating relocation? */ | |
10050 | /* Custom personality routine. */ | |
10051 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
10052 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 10053 | |
c19d1205 ZW |
10054 | where += 4; |
10055 | ptr += 4; | |
bfae80f2 | 10056 | |
c19d1205 ZW |
10057 | /* Set the first byte to the number of additional words. */ |
10058 | data = size - 1; | |
10059 | n = 3; | |
10060 | break; | |
bfae80f2 | 10061 | |
c19d1205 ZW |
10062 | /* ABI defined personality routines. */ |
10063 | case 0: | |
10064 | /* Three opcodes bytes are packed into the first word. */ | |
10065 | data = 0x80; | |
10066 | n = 3; | |
10067 | break; | |
bfae80f2 | 10068 | |
c19d1205 ZW |
10069 | case 1: |
10070 | case 2: | |
10071 | /* The size and first two opcode bytes go in the first word. */ | |
10072 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
10073 | n = 2; | |
10074 | break; | |
bfae80f2 | 10075 | |
c19d1205 ZW |
10076 | default: |
10077 | /* Should never happen. */ | |
10078 | abort (); | |
10079 | } | |
bfae80f2 | 10080 | |
c19d1205 ZW |
10081 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
10082 | time. */ | |
10083 | while (unwind.opcode_count > 0) | |
10084 | { | |
10085 | if (n == 0) | |
10086 | { | |
10087 | md_number_to_chars (ptr, data, 4); | |
10088 | ptr += 4; | |
10089 | n = 4; | |
10090 | data = 0; | |
10091 | } | |
10092 | unwind.opcode_count--; | |
10093 | n--; | |
10094 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
10095 | } | |
10096 | ||
10097 | /* Finish off the last word. */ | |
10098 | if (n < 4) | |
10099 | { | |
10100 | /* Pad with "finish" opcodes. */ | |
10101 | while (n--) | |
10102 | data = (data << 8) | 0xb0; | |
10103 | ||
10104 | md_number_to_chars (ptr, data, 4); | |
10105 | } | |
10106 | ||
10107 | if (!have_data) | |
10108 | { | |
10109 | /* Add an empty descriptor if there is no user-specified data. */ | |
10110 | ptr = frag_more (4); | |
10111 | md_number_to_chars (ptr, 0, 4); | |
10112 | } | |
10113 | ||
10114 | return 0; | |
bfae80f2 RE |
10115 | } |
10116 | ||
c19d1205 ZW |
10117 | /* Convert REGNAME to a DWARF-2 register number. */ |
10118 | ||
10119 | int | |
10120 | tc_arm_regname_to_dw2regnum (const char *regname) | |
bfae80f2 | 10121 | { |
c19d1205 ZW |
10122 | int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN); |
10123 | ||
10124 | if (reg == FAIL) | |
10125 | return -1; | |
10126 | ||
10127 | return reg; | |
bfae80f2 RE |
10128 | } |
10129 | ||
c19d1205 ZW |
10130 | /* Initialize the DWARF-2 unwind information for this procedure. */ |
10131 | ||
10132 | void | |
10133 | tc_arm_frame_initial_instructions (void) | |
bfae80f2 | 10134 | { |
c19d1205 | 10135 | cfi_add_CFA_def_cfa (REG_SP, 0); |
bfae80f2 | 10136 | } |
c19d1205 | 10137 | #endif /* OBJ_ELF */ |
bfae80f2 | 10138 | |
bfae80f2 | 10139 | |
c19d1205 | 10140 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 10141 | |
2fc8bdac ZW |
10142 | /* Return the address within the segment that a PC-relative fixup is |
10143 | relative to. For ARM, PC-relative fixups applied to instructions | |
10144 | are generally relative to the location of the fixup plus 8 bytes. | |
10145 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
10146 | require special handling. */ | |
bfae80f2 | 10147 | |
c19d1205 | 10148 | long |
2fc8bdac | 10149 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 10150 | { |
2fc8bdac ZW |
10151 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
10152 | ||
10153 | /* If this is pc-relative and we are going to emit a relocation | |
10154 | then we just want to put out any pipeline compensation that the linker | |
10155 | will need. Otherwise we want to use the calculated base. */ | |
10156 | if (fixP->fx_pcrel | |
10157 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10158 | || arm_force_relocation (fixP))) | |
10159 | base = 0; | |
bfae80f2 | 10160 | |
c19d1205 | 10161 | switch (fixP->fx_r_type) |
bfae80f2 | 10162 | { |
2fc8bdac ZW |
10163 | /* PC relative addressing on the Thumb is slightly odd as the |
10164 | bottom two bits of the PC are forced to zero for the | |
10165 | calculation. This happens *after* application of the | |
10166 | pipeline offset. However, Thumb adrl already adjusts for | |
10167 | this, so we need not do it again. */ | |
c19d1205 | 10168 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 10169 | return base & ~3; |
c19d1205 ZW |
10170 | |
10171 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
10172 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 10173 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 10174 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 10175 | return (base + 4) & ~3; |
c19d1205 | 10176 | |
2fc8bdac ZW |
10177 | /* Thumb branches are simply offset by +4. */ |
10178 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
10179 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
10180 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
10181 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
10182 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
10183 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
10184 | case BFD_RELOC_THUMB_PCREL_BLX: | |
10185 | return base + 4; | |
bfae80f2 | 10186 | |
2fc8bdac ZW |
10187 | /* ARM mode branches are offset by +8. However, the Windows CE |
10188 | loader expects the relocation not to take this into account. */ | |
10189 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
10190 | case BFD_RELOC_ARM_PCREL_BLX: | |
10191 | case BFD_RELOC_ARM_PLT32: | |
c19d1205 | 10192 | #ifdef TE_WINCE |
2fc8bdac | 10193 | return base; |
c19d1205 | 10194 | #else |
2fc8bdac | 10195 | return base + 8; |
c19d1205 | 10196 | #endif |
2fc8bdac ZW |
10197 | |
10198 | /* ARM mode loads relative to PC are also offset by +8. Unlike | |
10199 | branches, the Windows CE loader *does* expect the relocation | |
10200 | to take this into account. */ | |
10201 | case BFD_RELOC_ARM_OFFSET_IMM: | |
10202 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
10203 | case BFD_RELOC_ARM_HWLITERAL: | |
10204 | case BFD_RELOC_ARM_LITERAL: | |
10205 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
10206 | return base + 8; | |
10207 | ||
10208 | ||
10209 | /* Other PC-relative relocations are un-offset. */ | |
10210 | default: | |
10211 | return base; | |
10212 | } | |
bfae80f2 RE |
10213 | } |
10214 | ||
c19d1205 ZW |
10215 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
10216 | Otherwise we have no need to default values of symbols. */ | |
10217 | ||
10218 | symbolS * | |
10219 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 10220 | { |
c19d1205 ZW |
10221 | #ifdef OBJ_ELF |
10222 | if (name[0] == '_' && name[1] == 'G' | |
10223 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
10224 | { | |
10225 | if (!GOT_symbol) | |
10226 | { | |
10227 | if (symbol_find (name)) | |
10228 | as_bad ("GOT already in the symbol table"); | |
bfae80f2 | 10229 | |
c19d1205 ZW |
10230 | GOT_symbol = symbol_new (name, undefined_section, |
10231 | (valueT) 0, & zero_address_frag); | |
10232 | } | |
bfae80f2 | 10233 | |
c19d1205 | 10234 | return GOT_symbol; |
bfae80f2 | 10235 | } |
c19d1205 | 10236 | #endif |
bfae80f2 | 10237 | |
c19d1205 | 10238 | return 0; |
bfae80f2 RE |
10239 | } |
10240 | ||
55cf6793 | 10241 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
10242 | computed as two separate immediate values, added together. We |
10243 | already know that this value cannot be computed by just one ARM | |
10244 | instruction. */ | |
10245 | ||
10246 | static unsigned int | |
10247 | validate_immediate_twopart (unsigned int val, | |
10248 | unsigned int * highpart) | |
bfae80f2 | 10249 | { |
c19d1205 ZW |
10250 | unsigned int a; |
10251 | unsigned int i; | |
bfae80f2 | 10252 | |
c19d1205 ZW |
10253 | for (i = 0; i < 32; i += 2) |
10254 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
10255 | { | |
10256 | if (a & 0xff00) | |
10257 | { | |
10258 | if (a & ~ 0xffff) | |
10259 | continue; | |
10260 | * highpart = (a >> 8) | ((i + 24) << 7); | |
10261 | } | |
10262 | else if (a & 0xff0000) | |
10263 | { | |
10264 | if (a & 0xff000000) | |
10265 | continue; | |
10266 | * highpart = (a >> 16) | ((i + 16) << 7); | |
10267 | } | |
10268 | else | |
10269 | { | |
10270 | assert (a & 0xff000000); | |
10271 | * highpart = (a >> 24) | ((i + 8) << 7); | |
10272 | } | |
bfae80f2 | 10273 | |
c19d1205 ZW |
10274 | return (a & 0xff) | (i << 7); |
10275 | } | |
bfae80f2 | 10276 | |
c19d1205 | 10277 | return FAIL; |
bfae80f2 RE |
10278 | } |
10279 | ||
c19d1205 ZW |
10280 | static int |
10281 | validate_offset_imm (unsigned int val, int hwse) | |
10282 | { | |
10283 | if ((hwse && val > 255) || val > 4095) | |
10284 | return FAIL; | |
10285 | return val; | |
10286 | } | |
bfae80f2 | 10287 | |
55cf6793 | 10288 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
10289 | negative immediate constant by altering the instruction. A bit of |
10290 | a hack really. | |
10291 | MOV <-> MVN | |
10292 | AND <-> BIC | |
10293 | ADC <-> SBC | |
10294 | by inverting the second operand, and | |
10295 | ADD <-> SUB | |
10296 | CMP <-> CMN | |
10297 | by negating the second operand. */ | |
bfae80f2 | 10298 | |
c19d1205 ZW |
10299 | static int |
10300 | negate_data_op (unsigned long * instruction, | |
10301 | unsigned long value) | |
bfae80f2 | 10302 | { |
c19d1205 ZW |
10303 | int op, new_inst; |
10304 | unsigned long negated, inverted; | |
bfae80f2 | 10305 | |
c19d1205 ZW |
10306 | negated = encode_arm_immediate (-value); |
10307 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 10308 | |
c19d1205 ZW |
10309 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
10310 | switch (op) | |
bfae80f2 | 10311 | { |
c19d1205 ZW |
10312 | /* First negates. */ |
10313 | case OPCODE_SUB: /* ADD <-> SUB */ | |
10314 | new_inst = OPCODE_ADD; | |
10315 | value = negated; | |
10316 | break; | |
bfae80f2 | 10317 | |
c19d1205 ZW |
10318 | case OPCODE_ADD: |
10319 | new_inst = OPCODE_SUB; | |
10320 | value = negated; | |
10321 | break; | |
bfae80f2 | 10322 | |
c19d1205 ZW |
10323 | case OPCODE_CMP: /* CMP <-> CMN */ |
10324 | new_inst = OPCODE_CMN; | |
10325 | value = negated; | |
10326 | break; | |
bfae80f2 | 10327 | |
c19d1205 ZW |
10328 | case OPCODE_CMN: |
10329 | new_inst = OPCODE_CMP; | |
10330 | value = negated; | |
10331 | break; | |
bfae80f2 | 10332 | |
c19d1205 ZW |
10333 | /* Now Inverted ops. */ |
10334 | case OPCODE_MOV: /* MOV <-> MVN */ | |
10335 | new_inst = OPCODE_MVN; | |
10336 | value = inverted; | |
10337 | break; | |
bfae80f2 | 10338 | |
c19d1205 ZW |
10339 | case OPCODE_MVN: |
10340 | new_inst = OPCODE_MOV; | |
10341 | value = inverted; | |
10342 | break; | |
bfae80f2 | 10343 | |
c19d1205 ZW |
10344 | case OPCODE_AND: /* AND <-> BIC */ |
10345 | new_inst = OPCODE_BIC; | |
10346 | value = inverted; | |
10347 | break; | |
bfae80f2 | 10348 | |
c19d1205 ZW |
10349 | case OPCODE_BIC: |
10350 | new_inst = OPCODE_AND; | |
10351 | value = inverted; | |
10352 | break; | |
bfae80f2 | 10353 | |
c19d1205 ZW |
10354 | case OPCODE_ADC: /* ADC <-> SBC */ |
10355 | new_inst = OPCODE_SBC; | |
10356 | value = inverted; | |
10357 | break; | |
bfae80f2 | 10358 | |
c19d1205 ZW |
10359 | case OPCODE_SBC: |
10360 | new_inst = OPCODE_ADC; | |
10361 | value = inverted; | |
10362 | break; | |
bfae80f2 | 10363 | |
c19d1205 ZW |
10364 | /* We cannot do anything. */ |
10365 | default: | |
10366 | return FAIL; | |
b99bd4ef NC |
10367 | } |
10368 | ||
c19d1205 ZW |
10369 | if (value == (unsigned) FAIL) |
10370 | return FAIL; | |
10371 | ||
10372 | *instruction &= OPCODE_MASK; | |
10373 | *instruction |= new_inst << DATA_OP_SHIFT; | |
10374 | return value; | |
b99bd4ef NC |
10375 | } |
10376 | ||
8f06b2d8 PB |
10377 | /* Read a 32-bit thumb instruction from buf. */ |
10378 | static unsigned long | |
10379 | get_thumb32_insn (char * buf) | |
10380 | { | |
10381 | unsigned long insn; | |
10382 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
10383 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
10384 | ||
10385 | return insn; | |
10386 | } | |
10387 | ||
10388 | /* Write a 32-bit thumb instruction to buf. */ | |
10389 | static void | |
10390 | put_thumb32_insn (char * buf, unsigned long insn) | |
10391 | { | |
10392 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
10393 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
10394 | } | |
10395 | ||
c19d1205 | 10396 | void |
55cf6793 | 10397 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
10398 | valueT * valP, |
10399 | segT seg) | |
10400 | { | |
10401 | offsetT value = * valP; | |
10402 | offsetT newval; | |
10403 | unsigned int newimm; | |
10404 | unsigned long temp; | |
10405 | int sign; | |
10406 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 10407 | |
c19d1205 | 10408 | assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 10409 | |
c19d1205 ZW |
10410 | /* Note whether this will delete the relocation. */ |
10411 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
10412 | fixP->fx_done = 1; | |
b99bd4ef | 10413 | |
adbaf948 ZW |
10414 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
10415 | consistency with the behavior on 32-bit hosts. Remember value | |
10416 | for emit_reloc. */ | |
10417 | value &= 0xffffffff; | |
10418 | value ^= 0x80000000; | |
10419 | value -= 0x80000000; | |
10420 | ||
10421 | *valP = value; | |
c19d1205 | 10422 | fixP->fx_addnumber = value; |
b99bd4ef | 10423 | |
adbaf948 ZW |
10424 | /* Same treatment for fixP->fx_offset. */ |
10425 | fixP->fx_offset &= 0xffffffff; | |
10426 | fixP->fx_offset ^= 0x80000000; | |
10427 | fixP->fx_offset -= 0x80000000; | |
10428 | ||
c19d1205 | 10429 | switch (fixP->fx_r_type) |
b99bd4ef | 10430 | { |
c19d1205 ZW |
10431 | case BFD_RELOC_NONE: |
10432 | /* This will need to go in the object file. */ | |
10433 | fixP->fx_done = 0; | |
10434 | break; | |
b99bd4ef | 10435 | |
c19d1205 ZW |
10436 | case BFD_RELOC_ARM_IMMEDIATE: |
10437 | /* We claim that this fixup has been processed here, | |
10438 | even if in fact we generate an error because we do | |
10439 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
10440 | fixP->fx_done = 1; | |
b99bd4ef | 10441 | |
c19d1205 ZW |
10442 | if (fixP->fx_addsy |
10443 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
b99bd4ef | 10444 | { |
c19d1205 ZW |
10445 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10446 | _("undefined symbol %s used as an immediate value"), | |
10447 | S_GET_NAME (fixP->fx_addsy)); | |
10448 | break; | |
b99bd4ef NC |
10449 | } |
10450 | ||
c19d1205 ZW |
10451 | newimm = encode_arm_immediate (value); |
10452 | temp = md_chars_to_number (buf, INSN_SIZE); | |
10453 | ||
10454 | /* If the instruction will fail, see if we can fix things up by | |
10455 | changing the opcode. */ | |
10456 | if (newimm == (unsigned int) FAIL | |
10457 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 10458 | { |
c19d1205 ZW |
10459 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10460 | _("invalid constant (%lx) after fixup"), | |
10461 | (unsigned long) value); | |
10462 | break; | |
b99bd4ef | 10463 | } |
b99bd4ef | 10464 | |
c19d1205 ZW |
10465 | newimm |= (temp & 0xfffff000); |
10466 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
10467 | break; | |
b99bd4ef | 10468 | |
c19d1205 ZW |
10469 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
10470 | { | |
10471 | unsigned int highpart = 0; | |
10472 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 10473 | |
c19d1205 ZW |
10474 | newimm = encode_arm_immediate (value); |
10475 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 10476 | |
c19d1205 ZW |
10477 | /* If the instruction will fail, see if we can fix things up by |
10478 | changing the opcode. */ | |
10479 | if (newimm == (unsigned int) FAIL | |
10480 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
10481 | { | |
10482 | /* No ? OK - try using two ADD instructions to generate | |
10483 | the value. */ | |
10484 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 10485 | |
c19d1205 ZW |
10486 | /* Yes - then make sure that the second instruction is |
10487 | also an add. */ | |
10488 | if (newimm != (unsigned int) FAIL) | |
10489 | newinsn = temp; | |
10490 | /* Still No ? Try using a negated value. */ | |
10491 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
10492 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
10493 | /* Otherwise - give up. */ | |
10494 | else | |
10495 | { | |
10496 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10497 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
10498 | (long) value); | |
10499 | break; | |
10500 | } | |
b99bd4ef | 10501 | |
c19d1205 ZW |
10502 | /* Replace the first operand in the 2nd instruction (which |
10503 | is the PC) with the destination register. We have | |
10504 | already added in the PC in the first instruction and we | |
10505 | do not want to do it again. */ | |
10506 | newinsn &= ~ 0xf0000; | |
10507 | newinsn |= ((newinsn & 0x0f000) << 4); | |
10508 | } | |
b99bd4ef | 10509 | |
c19d1205 ZW |
10510 | newimm |= (temp & 0xfffff000); |
10511 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 10512 | |
c19d1205 ZW |
10513 | highpart |= (newinsn & 0xfffff000); |
10514 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
10515 | } | |
10516 | break; | |
b99bd4ef | 10517 | |
c19d1205 ZW |
10518 | case BFD_RELOC_ARM_OFFSET_IMM: |
10519 | case BFD_RELOC_ARM_LITERAL: | |
10520 | sign = value >= 0; | |
b99bd4ef | 10521 | |
c19d1205 ZW |
10522 | if (value < 0) |
10523 | value = - value; | |
b99bd4ef | 10524 | |
c19d1205 | 10525 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 10526 | { |
c19d1205 ZW |
10527 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
10528 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10529 | _("invalid literal constant: pool needs to be closer")); | |
10530 | else | |
10531 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10532 | _("bad immediate value for offset (%ld)"), | |
10533 | (long) value); | |
10534 | break; | |
f03698e6 RE |
10535 | } |
10536 | ||
c19d1205 ZW |
10537 | newval = md_chars_to_number (buf, INSN_SIZE); |
10538 | newval &= 0xff7ff000; | |
10539 | newval |= value | (sign ? INDEX_UP : 0); | |
10540 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10541 | break; | |
b99bd4ef | 10542 | |
c19d1205 ZW |
10543 | case BFD_RELOC_ARM_OFFSET_IMM8: |
10544 | case BFD_RELOC_ARM_HWLITERAL: | |
10545 | sign = value >= 0; | |
b99bd4ef | 10546 | |
c19d1205 ZW |
10547 | if (value < 0) |
10548 | value = - value; | |
b99bd4ef | 10549 | |
c19d1205 | 10550 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 10551 | { |
c19d1205 ZW |
10552 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
10553 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10554 | _("invalid literal constant: pool needs to be closer")); | |
10555 | else | |
10556 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
10557 | (long) value); | |
10558 | break; | |
b99bd4ef NC |
10559 | } |
10560 | ||
c19d1205 ZW |
10561 | newval = md_chars_to_number (buf, INSN_SIZE); |
10562 | newval &= 0xff7ff0f0; | |
10563 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
10564 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10565 | break; | |
b99bd4ef | 10566 | |
c19d1205 ZW |
10567 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
10568 | if (value < 0 || value > 1020 || value % 4 != 0) | |
10569 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10570 | _("bad immediate value for offset (%ld)"), (long) value); | |
10571 | value /= 4; | |
b99bd4ef | 10572 | |
c19d1205 | 10573 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
10574 | newval |= value; |
10575 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
10576 | break; | |
b99bd4ef | 10577 | |
c19d1205 ZW |
10578 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
10579 | /* This is a complicated relocation used for all varieties of Thumb32 | |
10580 | load/store instruction with immediate offset: | |
10581 | ||
10582 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
10583 | *4, optional writeback(W) | |
10584 | (doubleword load/store) | |
10585 | ||
10586 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
10587 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
10588 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
10589 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
10590 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
10591 | ||
10592 | Uppercase letters indicate bits that are already encoded at | |
10593 | this point. Lowercase letters are our problem. For the | |
10594 | second block of instructions, the secondary opcode nybble | |
10595 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
10596 | a PC-relative operation. */ | |
10597 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
10598 | newval <<= 16; | |
10599 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 10600 | |
c19d1205 | 10601 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 10602 | { |
c19d1205 ZW |
10603 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
10604 | if (value >= 0) | |
10605 | newval |= (1 << 23); | |
10606 | else | |
10607 | value = -value; | |
10608 | if (value % 4 != 0) | |
10609 | { | |
10610 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10611 | _("offset not a multiple of 4")); | |
10612 | break; | |
10613 | } | |
10614 | value /= 4; | |
10615 | if (value >= 0xff) | |
10616 | { | |
10617 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10618 | _("offset out of range")); | |
10619 | break; | |
10620 | } | |
10621 | newval &= ~0xff; | |
b99bd4ef | 10622 | } |
c19d1205 | 10623 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 10624 | { |
c19d1205 ZW |
10625 | /* PC-relative, 12-bit offset. */ |
10626 | if (value >= 0) | |
10627 | newval |= (1 << 23); | |
10628 | else | |
10629 | value = -value; | |
10630 | if (value >= 0xfff) | |
10631 | { | |
10632 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10633 | _("offset out of range")); | |
10634 | break; | |
10635 | } | |
10636 | newval &= ~0xfff; | |
b99bd4ef | 10637 | } |
c19d1205 | 10638 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 10639 | { |
c19d1205 ZW |
10640 | /* Writeback: 8-bit, +/- offset. */ |
10641 | if (value >= 0) | |
10642 | newval |= (1 << 9); | |
10643 | else | |
10644 | value = -value; | |
10645 | if (value >= 0xff) | |
10646 | { | |
10647 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10648 | _("offset out of range")); | |
10649 | break; | |
10650 | } | |
10651 | newval &= ~0xff; | |
b99bd4ef | 10652 | } |
c19d1205 | 10653 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 10654 | { |
c19d1205 ZW |
10655 | /* T-instruction: positive 8-bit offset. */ |
10656 | if (value < 0 || value >= 0xff) | |
b99bd4ef | 10657 | { |
c19d1205 ZW |
10658 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10659 | _("offset out of range")); | |
10660 | break; | |
b99bd4ef | 10661 | } |
c19d1205 ZW |
10662 | newval &= ~0xff; |
10663 | newval |= value; | |
b99bd4ef NC |
10664 | } |
10665 | else | |
b99bd4ef | 10666 | { |
c19d1205 ZW |
10667 | /* Positive 12-bit or negative 8-bit offset. */ |
10668 | int limit; | |
10669 | if (value >= 0) | |
b99bd4ef | 10670 | { |
c19d1205 ZW |
10671 | newval |= (1 << 23); |
10672 | limit = 0xfff; | |
10673 | } | |
10674 | else | |
10675 | { | |
10676 | value = -value; | |
10677 | limit = 0xff; | |
10678 | } | |
10679 | if (value > limit) | |
10680 | { | |
10681 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10682 | _("offset out of range")); | |
10683 | break; | |
b99bd4ef | 10684 | } |
c19d1205 | 10685 | newval &= ~limit; |
b99bd4ef | 10686 | } |
b99bd4ef | 10687 | |
c19d1205 ZW |
10688 | newval |= value; |
10689 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
10690 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
10691 | break; | |
404ff6b5 | 10692 | |
c19d1205 ZW |
10693 | case BFD_RELOC_ARM_SHIFT_IMM: |
10694 | newval = md_chars_to_number (buf, INSN_SIZE); | |
10695 | if (((unsigned long) value) > 32 | |
10696 | || (value == 32 | |
10697 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
10698 | { | |
10699 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10700 | _("shift expression is too large")); | |
10701 | break; | |
10702 | } | |
404ff6b5 | 10703 | |
c19d1205 ZW |
10704 | if (value == 0) |
10705 | /* Shifts of zero must be done as lsl. */ | |
10706 | newval &= ~0x60; | |
10707 | else if (value == 32) | |
10708 | value = 0; | |
10709 | newval &= 0xfffff07f; | |
10710 | newval |= (value & 0x1f) << 7; | |
10711 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10712 | break; | |
404ff6b5 | 10713 | |
c19d1205 | 10714 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
92e90b6e | 10715 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 10716 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
10717 | /* We claim that this fixup has been processed here, |
10718 | even if in fact we generate an error because we do | |
10719 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
10720 | fixP->fx_done = 1; | |
404ff6b5 | 10721 | |
c19d1205 ZW |
10722 | if (fixP->fx_addsy |
10723 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
10724 | { | |
10725 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10726 | _("undefined symbol %s used as an immediate value"), | |
10727 | S_GET_NAME (fixP->fx_addsy)); | |
10728 | break; | |
10729 | } | |
404ff6b5 | 10730 | |
c19d1205 ZW |
10731 | newval = md_chars_to_number (buf, THUMB_SIZE); |
10732 | newval <<= 16; | |
10733 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 10734 | |
e9f89963 PB |
10735 | /* FUTURE: Implement analogue of negate_data_op for T32. */ |
10736 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE) | |
10737 | newimm = encode_thumb32_immediate (value); | |
10738 | else | |
92e90b6e | 10739 | { |
e9f89963 PB |
10740 | /* 12 bit immediate for addw/subw. */ |
10741 | if (value < 0) | |
10742 | { | |
10743 | value = -value; | |
10744 | newval ^= 0x00a00000; | |
10745 | } | |
92e90b6e PB |
10746 | if (value > 0xfff) |
10747 | newimm = (unsigned int) FAIL; | |
10748 | else | |
10749 | newimm = value; | |
10750 | } | |
cc8a6dd0 | 10751 | |
c19d1205 | 10752 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 10753 | { |
c19d1205 ZW |
10754 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10755 | _("invalid constant (%lx) after fixup"), | |
10756 | (unsigned long) value); | |
10757 | break; | |
3631a3c8 NC |
10758 | } |
10759 | ||
c19d1205 ZW |
10760 | newval |= (newimm & 0x800) << 15; |
10761 | newval |= (newimm & 0x700) << 4; | |
10762 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 10763 | |
c19d1205 ZW |
10764 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
10765 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
10766 | break; | |
a737bd4d | 10767 | |
c19d1205 ZW |
10768 | case BFD_RELOC_ARM_SMI: |
10769 | if (((unsigned long) value) > 0xffff) | |
10770 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10771 | _("invalid smi expression")); | |
2fc8bdac | 10772 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
10773 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
10774 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10775 | break; | |
a737bd4d | 10776 | |
c19d1205 | 10777 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 10778 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
10779 | { |
10780 | if (((unsigned long) value) > 0xff) | |
10781 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10782 | _("invalid swi expression")); | |
2fc8bdac | 10783 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
10784 | newval |= value; |
10785 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
10786 | } | |
10787 | else | |
10788 | { | |
10789 | if (((unsigned long) value) > 0x00ffffff) | |
10790 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10791 | _("invalid swi expression")); | |
2fc8bdac | 10792 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
10793 | newval |= value; |
10794 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10795 | } | |
10796 | break; | |
a737bd4d | 10797 | |
c19d1205 ZW |
10798 | case BFD_RELOC_ARM_MULTI: |
10799 | if (((unsigned long) value) > 0xffff) | |
10800 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10801 | _("invalid expression in load/store multiple")); | |
10802 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
10803 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10804 | break; | |
a737bd4d | 10805 | |
c19d1205 | 10806 | case BFD_RELOC_ARM_PCREL_BRANCH: |
c19d1205 | 10807 | #ifdef OBJ_ELF |
2fc8bdac | 10808 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 10809 | #endif |
a737bd4d | 10810 | |
c19d1205 | 10811 | /* We are going to store value (shifted right by two) in the |
2fc8bdac ZW |
10812 | instruction, in a 24 bit, signed field. Bits 0 and 1 must be |
10813 | clear, and bits 26 through 32 either all clear or all set. */ | |
10814 | if (value & 0x00000003) | |
c19d1205 | 10815 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
10816 | _("misaligned branch destination")); |
10817 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
10818 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
10819 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10820 | _("branch out of range")); | |
a737bd4d | 10821 | |
2fc8bdac | 10822 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 10823 | { |
2fc8bdac ZW |
10824 | newval = md_chars_to_number (buf, INSN_SIZE); |
10825 | newval |= (value >> 2) & 0x00ffffff; | |
10826 | md_number_to_chars (buf, newval, INSN_SIZE); | |
c19d1205 | 10827 | } |
c19d1205 | 10828 | break; |
a737bd4d | 10829 | |
c19d1205 | 10830 | case BFD_RELOC_ARM_PCREL_BLX: |
2fc8bdac ZW |
10831 | /* BLX allows bit 1 to be set in the branch destination, since |
10832 | it targets a Thumb instruction which is only required to be | |
10833 | aligned modulo 2. Other constraints are as for B/BL. */ | |
10834 | if (value & 0x00000001) | |
10835 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10836 | _("misaligned BLX destination")); | |
10837 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
10838 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
10839 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10840 | _("branch out of range")); | |
a737bd4d | 10841 | |
2fc8bdac ZW |
10842 | if (fixP->fx_done || !seg->use_rela_p) |
10843 | { | |
10844 | offsetT hbit; | |
10845 | hbit = (value >> 1) & 1; | |
10846 | value = (value >> 2) & 0x00ffffff; | |
a737bd4d | 10847 | |
2fc8bdac ZW |
10848 | newval = md_chars_to_number (buf, INSN_SIZE); |
10849 | newval |= value | hbit << 24; | |
10850 | md_number_to_chars (buf, newval, INSN_SIZE); | |
10851 | } | |
c19d1205 | 10852 | break; |
a737bd4d | 10853 | |
c19d1205 | 10854 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */ |
2fc8bdac ZW |
10855 | /* CZB can only branch forward. */ |
10856 | if (value & ~0x7e) | |
10857 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10858 | _("branch out of range")); | |
a737bd4d | 10859 | |
2fc8bdac ZW |
10860 | if (fixP->fx_done || !seg->use_rela_p) |
10861 | { | |
10862 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
c19d1205 | 10863 | newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3); |
2fc8bdac ZW |
10864 | md_number_to_chars (buf, newval, THUMB_SIZE); |
10865 | } | |
c19d1205 | 10866 | break; |
a737bd4d | 10867 | |
c19d1205 | 10868 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
10869 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
10870 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10871 | _("branch out of range")); | |
a737bd4d | 10872 | |
2fc8bdac ZW |
10873 | if (fixP->fx_done || !seg->use_rela_p) |
10874 | { | |
10875 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
10876 | newval |= (value & 0x1ff) >> 1; | |
10877 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
10878 | } | |
c19d1205 | 10879 | break; |
a737bd4d | 10880 | |
c19d1205 | 10881 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
10882 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
10883 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10884 | _("branch out of range")); | |
a737bd4d | 10885 | |
2fc8bdac ZW |
10886 | if (fixP->fx_done || !seg->use_rela_p) |
10887 | { | |
10888 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
10889 | newval |= (value & 0xfff) >> 1; | |
10890 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
10891 | } | |
c19d1205 | 10892 | break; |
a737bd4d | 10893 | |
c19d1205 | 10894 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
2fc8bdac ZW |
10895 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
10896 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10897 | _("conditional branch out of range")); | |
404ff6b5 | 10898 | |
2fc8bdac ZW |
10899 | if (fixP->fx_done || !seg->use_rela_p) |
10900 | { | |
10901 | offsetT newval2; | |
10902 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 10903 | |
2fc8bdac ZW |
10904 | S = (value & 0x00100000) >> 20; |
10905 | J2 = (value & 0x00080000) >> 19; | |
10906 | J1 = (value & 0x00040000) >> 18; | |
10907 | hi = (value & 0x0003f000) >> 12; | |
10908 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 10909 | |
2fc8bdac ZW |
10910 | newval = md_chars_to_number (buf, THUMB_SIZE); |
10911 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
10912 | newval |= (S << 10) | hi; | |
10913 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
10914 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
10915 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
10916 | } | |
c19d1205 | 10917 | break; |
6c43fab6 | 10918 | |
c19d1205 ZW |
10919 | case BFD_RELOC_THUMB_PCREL_BLX: |
10920 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
2fc8bdac ZW |
10921 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
10922 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10923 | _("branch out of range")); | |
404ff6b5 | 10924 | |
2fc8bdac ZW |
10925 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
10926 | /* For a BLX instruction, make sure that the relocation is rounded up | |
10927 | to a word boundary. This follows the semantics of the instruction | |
10928 | which specifies that bit 1 of the target address will come from bit | |
10929 | 1 of the base address. */ | |
10930 | value = (value + 1) & ~ 1; | |
404ff6b5 | 10931 | |
2fc8bdac | 10932 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 10933 | { |
2fc8bdac ZW |
10934 | offsetT newval2; |
10935 | ||
10936 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
10937 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
10938 | newval |= (value & 0x7fffff) >> 12; | |
10939 | newval2 |= (value & 0xfff) >> 1; | |
10940 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
10941 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
c19d1205 | 10942 | } |
c19d1205 | 10943 | break; |
404ff6b5 | 10944 | |
c19d1205 | 10945 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
10946 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
10947 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10948 | _("branch out of range")); | |
6c43fab6 | 10949 | |
2fc8bdac ZW |
10950 | if (fixP->fx_done || !seg->use_rela_p) |
10951 | { | |
10952 | offsetT newval2; | |
10953 | addressT S, I1, I2, lo, hi; | |
6c43fab6 | 10954 | |
2fc8bdac ZW |
10955 | S = (value & 0x01000000) >> 24; |
10956 | I1 = (value & 0x00800000) >> 23; | |
10957 | I2 = (value & 0x00400000) >> 22; | |
10958 | hi = (value & 0x003ff000) >> 12; | |
10959 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 10960 | |
2fc8bdac ZW |
10961 | I1 = !(I1 ^ S); |
10962 | I2 = !(I2 ^ S); | |
a737bd4d | 10963 | |
2fc8bdac ZW |
10964 | newval = md_chars_to_number (buf, THUMB_SIZE); |
10965 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
10966 | newval |= (S << 10) | hi; | |
10967 | newval2 |= (I1 << 13) | (I2 << 11) | lo; | |
10968 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
10969 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
10970 | } | |
10971 | break; | |
a737bd4d | 10972 | |
2fc8bdac ZW |
10973 | case BFD_RELOC_8: |
10974 | if (fixP->fx_done || !seg->use_rela_p) | |
10975 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 10976 | break; |
a737bd4d | 10977 | |
c19d1205 | 10978 | case BFD_RELOC_16: |
2fc8bdac | 10979 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 10980 | md_number_to_chars (buf, value, 2); |
c19d1205 | 10981 | break; |
a737bd4d | 10982 | |
c19d1205 ZW |
10983 | #ifdef OBJ_ELF |
10984 | case BFD_RELOC_ARM_TLS_GD32: | |
10985 | case BFD_RELOC_ARM_TLS_LE32: | |
10986 | case BFD_RELOC_ARM_TLS_IE32: | |
10987 | case BFD_RELOC_ARM_TLS_LDM32: | |
10988 | case BFD_RELOC_ARM_TLS_LDO32: | |
10989 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10990 | /* fall through */ | |
6c43fab6 | 10991 | |
c19d1205 ZW |
10992 | case BFD_RELOC_ARM_GOT32: |
10993 | case BFD_RELOC_ARM_GOTOFF: | |
10994 | case BFD_RELOC_ARM_TARGET2: | |
2fc8bdac ZW |
10995 | if (fixP->fx_done || !seg->use_rela_p) |
10996 | md_number_to_chars (buf, 0, 4); | |
c19d1205 ZW |
10997 | break; |
10998 | #endif | |
6c43fab6 | 10999 | |
c19d1205 ZW |
11000 | case BFD_RELOC_RVA: |
11001 | case BFD_RELOC_32: | |
11002 | case BFD_RELOC_ARM_TARGET1: | |
11003 | case BFD_RELOC_ARM_ROSEGREL32: | |
11004 | case BFD_RELOC_ARM_SBREL32: | |
11005 | case BFD_RELOC_32_PCREL: | |
2fc8bdac | 11006 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11007 | md_number_to_chars (buf, value, 4); |
c19d1205 | 11008 | break; |
6c43fab6 | 11009 | |
c19d1205 ZW |
11010 | #ifdef OBJ_ELF |
11011 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 11012 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
11013 | { |
11014 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
11015 | if ((value ^ (value >> 1)) & 0x40000000) | |
11016 | { | |
11017 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11018 | _("rel31 relocation overflow")); | |
11019 | } | |
11020 | newval |= value & 0x7fffffff; | |
11021 | md_number_to_chars (buf, newval, 4); | |
11022 | } | |
11023 | break; | |
c19d1205 | 11024 | #endif |
a737bd4d | 11025 | |
c19d1205 | 11026 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 11027 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
11028 | if (value < -1023 || value > 1023 || (value & 3)) |
11029 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11030 | _("co-processor offset out of range")); | |
11031 | cp_off_common: | |
11032 | sign = value >= 0; | |
11033 | if (value < 0) | |
11034 | value = -value; | |
8f06b2d8 PB |
11035 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
11036 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
11037 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11038 | else | |
11039 | newval = get_thumb32_insn (buf); | |
11040 | newval &= 0xff7fff00; | |
c19d1205 ZW |
11041 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
11042 | if (value == 0) | |
11043 | newval &= ~WRITE_BACK; | |
8f06b2d8 PB |
11044 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
11045 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
11046 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11047 | else | |
11048 | put_thumb32_insn (buf, newval); | |
c19d1205 | 11049 | break; |
a737bd4d | 11050 | |
c19d1205 | 11051 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 11052 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
11053 | if (value < -255 || value > 255) |
11054 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11055 | _("co-processor offset out of range")); | |
11056 | goto cp_off_common; | |
6c43fab6 | 11057 | |
c19d1205 ZW |
11058 | case BFD_RELOC_ARM_THUMB_OFFSET: |
11059 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11060 | /* Exactly what ranges, and where the offset is inserted depends | |
11061 | on the type of instruction, we can establish this from the | |
11062 | top 4 bits. */ | |
11063 | switch (newval >> 12) | |
11064 | { | |
11065 | case 4: /* PC load. */ | |
11066 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
11067 | forced to zero for these loads; md_pcrel_from has already | |
11068 | compensated for this. */ | |
11069 | if (value & 3) | |
11070 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11071 | _("invalid offset, target not word aligned (0x%08lX)"), | |
11072 | (((unsigned int) fixP->fx_frag->fr_address | |
11073 | + (unsigned int) fixP->fx_where) & ~3) + value); | |
a737bd4d | 11074 | |
c19d1205 ZW |
11075 | if (value & ~0x3fc) |
11076 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11077 | _("invalid offset, value too big (0x%08lX)"), | |
11078 | (long) value); | |
a737bd4d | 11079 | |
c19d1205 ZW |
11080 | newval |= value >> 2; |
11081 | break; | |
a737bd4d | 11082 | |
c19d1205 ZW |
11083 | case 9: /* SP load/store. */ |
11084 | if (value & ~0x3fc) | |
11085 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11086 | _("invalid offset, value too big (0x%08lX)"), | |
11087 | (long) value); | |
11088 | newval |= value >> 2; | |
11089 | break; | |
6c43fab6 | 11090 | |
c19d1205 ZW |
11091 | case 6: /* Word load/store. */ |
11092 | if (value & ~0x7c) | |
11093 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11094 | _("invalid offset, value too big (0x%08lX)"), | |
11095 | (long) value); | |
11096 | newval |= value << 4; /* 6 - 2. */ | |
11097 | break; | |
a737bd4d | 11098 | |
c19d1205 ZW |
11099 | case 7: /* Byte load/store. */ |
11100 | if (value & ~0x1f) | |
11101 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11102 | _("invalid offset, value too big (0x%08lX)"), | |
11103 | (long) value); | |
11104 | newval |= value << 6; | |
11105 | break; | |
a737bd4d | 11106 | |
c19d1205 ZW |
11107 | case 8: /* Halfword load/store. */ |
11108 | if (value & ~0x3e) | |
11109 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11110 | _("invalid offset, value too big (0x%08lX)"), | |
11111 | (long) value); | |
11112 | newval |= value << 5; /* 6 - 1. */ | |
11113 | break; | |
a737bd4d | 11114 | |
c19d1205 ZW |
11115 | default: |
11116 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11117 | "Unable to process relocation for thumb opcode: %lx", | |
11118 | (unsigned long) newval); | |
11119 | break; | |
11120 | } | |
11121 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11122 | break; | |
a737bd4d | 11123 | |
c19d1205 ZW |
11124 | case BFD_RELOC_ARM_THUMB_ADD: |
11125 | /* This is a complicated relocation, since we use it for all of | |
11126 | the following immediate relocations: | |
a737bd4d | 11127 | |
c19d1205 ZW |
11128 | 3bit ADD/SUB |
11129 | 8bit ADD/SUB | |
11130 | 9bit ADD/SUB SP word-aligned | |
11131 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 11132 | |
c19d1205 ZW |
11133 | The type of instruction being processed is encoded in the |
11134 | instruction field: | |
a737bd4d | 11135 | |
c19d1205 ZW |
11136 | 0x8000 SUB |
11137 | 0x00F0 Rd | |
11138 | 0x000F Rs | |
11139 | */ | |
11140 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11141 | { | |
11142 | int rd = (newval >> 4) & 0xf; | |
11143 | int rs = newval & 0xf; | |
11144 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 11145 | |
c19d1205 ZW |
11146 | /* Check for HI regs, only very restricted cases allowed: |
11147 | Adjusting SP, and using PC or SP to get an address. */ | |
11148 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
11149 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
11150 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11151 | _("invalid Hi register with immediate")); | |
a737bd4d | 11152 | |
c19d1205 ZW |
11153 | /* If value is negative, choose the opposite instruction. */ |
11154 | if (value < 0) | |
11155 | { | |
11156 | value = -value; | |
11157 | subtract = !subtract; | |
11158 | if (value < 0) | |
11159 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11160 | _("immediate value out of range")); | |
11161 | } | |
a737bd4d | 11162 | |
c19d1205 ZW |
11163 | if (rd == REG_SP) |
11164 | { | |
11165 | if (value & ~0x1fc) | |
11166 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11167 | _("invalid immediate for stack address calculation")); | |
11168 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
11169 | newval |= value >> 2; | |
11170 | } | |
11171 | else if (rs == REG_PC || rs == REG_SP) | |
11172 | { | |
11173 | if (subtract || value & ~0x3fc) | |
11174 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11175 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
11176 | (unsigned long) value); | |
11177 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
11178 | newval |= rd << 8; | |
11179 | newval |= value >> 2; | |
11180 | } | |
11181 | else if (rs == rd) | |
11182 | { | |
11183 | if (value & ~0xff) | |
11184 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11185 | _("immediate value out of range")); | |
11186 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
11187 | newval |= (rd << 8) | value; | |
11188 | } | |
11189 | else | |
11190 | { | |
11191 | if (value & ~0x7) | |
11192 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11193 | _("immediate value out of range")); | |
11194 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
11195 | newval |= rd | (rs << 3) | (value << 6); | |
11196 | } | |
11197 | } | |
11198 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11199 | break; | |
a737bd4d | 11200 | |
c19d1205 ZW |
11201 | case BFD_RELOC_ARM_THUMB_IMM: |
11202 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11203 | if (value < 0 || value > 255) | |
11204 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11205 | _("invalid immediate: %ld is too large"), | |
11206 | (long) value); | |
11207 | newval |= value; | |
11208 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11209 | break; | |
a737bd4d | 11210 | |
c19d1205 ZW |
11211 | case BFD_RELOC_ARM_THUMB_SHIFT: |
11212 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
11213 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
11214 | temp = newval & 0xf800; | |
11215 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
11216 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11217 | _("invalid shift value: %ld"), (long) value); | |
11218 | /* Shifts of zero must be encoded as LSL. */ | |
11219 | if (value == 0) | |
11220 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
11221 | /* Shifts of 32 are encoded as zero. */ | |
11222 | else if (value == 32) | |
11223 | value = 0; | |
11224 | newval |= value << 6; | |
11225 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11226 | break; | |
a737bd4d | 11227 | |
c19d1205 ZW |
11228 | case BFD_RELOC_VTABLE_INHERIT: |
11229 | case BFD_RELOC_VTABLE_ENTRY: | |
11230 | fixP->fx_done = 0; | |
11231 | return; | |
6c43fab6 | 11232 | |
c19d1205 ZW |
11233 | case BFD_RELOC_UNUSED: |
11234 | default: | |
11235 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11236 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
11237 | } | |
6c43fab6 RE |
11238 | } |
11239 | ||
c19d1205 ZW |
11240 | /* Translate internal representation of relocation info to BFD target |
11241 | format. */ | |
a737bd4d | 11242 | |
c19d1205 ZW |
11243 | arelent * |
11244 | tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, | |
11245 | fixS * fixp) | |
a737bd4d | 11246 | { |
c19d1205 ZW |
11247 | arelent * reloc; |
11248 | bfd_reloc_code_real_type code; | |
a737bd4d | 11249 | |
c19d1205 | 11250 | reloc = xmalloc (sizeof (arelent)); |
a737bd4d | 11251 | |
c19d1205 ZW |
11252 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
11253 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
11254 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 11255 | |
2fc8bdac ZW |
11256 | if (fixp->fx_pcrel) |
11257 | fixp->fx_offset = reloc->address; | |
c19d1205 | 11258 | reloc->addend = fixp->fx_offset; |
a737bd4d | 11259 | |
c19d1205 | 11260 | switch (fixp->fx_r_type) |
a737bd4d | 11261 | { |
c19d1205 ZW |
11262 | case BFD_RELOC_8: |
11263 | if (fixp->fx_pcrel) | |
11264 | { | |
11265 | code = BFD_RELOC_8_PCREL; | |
11266 | break; | |
11267 | } | |
a737bd4d | 11268 | |
c19d1205 ZW |
11269 | case BFD_RELOC_16: |
11270 | if (fixp->fx_pcrel) | |
11271 | { | |
11272 | code = BFD_RELOC_16_PCREL; | |
11273 | break; | |
11274 | } | |
6c43fab6 | 11275 | |
c19d1205 ZW |
11276 | case BFD_RELOC_32: |
11277 | if (fixp->fx_pcrel) | |
11278 | { | |
11279 | code = BFD_RELOC_32_PCREL; | |
11280 | break; | |
11281 | } | |
a737bd4d | 11282 | |
c19d1205 ZW |
11283 | case BFD_RELOC_NONE: |
11284 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
11285 | case BFD_RELOC_ARM_PCREL_BLX: | |
11286 | case BFD_RELOC_RVA: | |
11287 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
11288 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
11289 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
11290 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
11291 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
11292 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
11293 | case BFD_RELOC_THUMB_PCREL_BLX: | |
11294 | case BFD_RELOC_VTABLE_ENTRY: | |
11295 | case BFD_RELOC_VTABLE_INHERIT: | |
11296 | code = fixp->fx_r_type; | |
11297 | break; | |
a737bd4d | 11298 | |
c19d1205 ZW |
11299 | case BFD_RELOC_ARM_LITERAL: |
11300 | case BFD_RELOC_ARM_HWLITERAL: | |
11301 | /* If this is called then the a literal has | |
11302 | been referenced across a section boundary. */ | |
11303 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11304 | _("literal referenced across section boundary")); | |
11305 | return NULL; | |
a737bd4d | 11306 | |
c19d1205 ZW |
11307 | #ifdef OBJ_ELF |
11308 | case BFD_RELOC_ARM_GOT32: | |
11309 | case BFD_RELOC_ARM_GOTOFF: | |
11310 | case BFD_RELOC_ARM_PLT32: | |
11311 | case BFD_RELOC_ARM_TARGET1: | |
11312 | case BFD_RELOC_ARM_ROSEGREL32: | |
11313 | case BFD_RELOC_ARM_SBREL32: | |
11314 | case BFD_RELOC_ARM_PREL31: | |
11315 | case BFD_RELOC_ARM_TARGET2: | |
11316 | case BFD_RELOC_ARM_TLS_LE32: | |
11317 | case BFD_RELOC_ARM_TLS_LDO32: | |
11318 | code = fixp->fx_r_type; | |
11319 | break; | |
a737bd4d | 11320 | |
c19d1205 ZW |
11321 | case BFD_RELOC_ARM_TLS_GD32: |
11322 | case BFD_RELOC_ARM_TLS_IE32: | |
11323 | case BFD_RELOC_ARM_TLS_LDM32: | |
11324 | /* BFD will include the symbol's address in the addend. | |
11325 | But we don't want that, so subtract it out again here. */ | |
11326 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
11327 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
11328 | code = fixp->fx_r_type; | |
11329 | break; | |
11330 | #endif | |
a737bd4d | 11331 | |
c19d1205 ZW |
11332 | case BFD_RELOC_ARM_IMMEDIATE: |
11333 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11334 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
11335 | return NULL; | |
a737bd4d | 11336 | |
c19d1205 ZW |
11337 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
11338 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11339 | _("ADRL used for a symbol not defined in the same file")); | |
11340 | return NULL; | |
a737bd4d | 11341 | |
c19d1205 ZW |
11342 | case BFD_RELOC_ARM_OFFSET_IMM: |
11343 | if (fixp->fx_addsy != NULL | |
11344 | && !S_IS_DEFINED (fixp->fx_addsy) | |
11345 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 11346 | { |
c19d1205 ZW |
11347 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11348 | _("undefined local label `%s'"), | |
11349 | S_GET_NAME (fixp->fx_addsy)); | |
11350 | return NULL; | |
a737bd4d NC |
11351 | } |
11352 | ||
c19d1205 ZW |
11353 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11354 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
11355 | return NULL; | |
a737bd4d | 11356 | |
c19d1205 ZW |
11357 | default: |
11358 | { | |
11359 | char * type; | |
6c43fab6 | 11360 | |
c19d1205 ZW |
11361 | switch (fixp->fx_r_type) |
11362 | { | |
11363 | case BFD_RELOC_NONE: type = "NONE"; break; | |
11364 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
11365 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
11366 | case BFD_RELOC_ARM_SMI: type = "SMI"; break; | |
11367 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; | |
11368 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
11369 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 11370 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
11371 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
11372 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
11373 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
11374 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
11375 | default: type = _("<unknown>"); break; | |
11376 | } | |
11377 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11378 | _("cannot represent %s relocation in this object file format"), | |
11379 | type); | |
11380 | return NULL; | |
11381 | } | |
a737bd4d | 11382 | } |
6c43fab6 | 11383 | |
c19d1205 ZW |
11384 | #ifdef OBJ_ELF |
11385 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
11386 | && GOT_symbol | |
11387 | && fixp->fx_addsy == GOT_symbol) | |
11388 | { | |
11389 | code = BFD_RELOC_ARM_GOTPC; | |
11390 | reloc->addend = fixp->fx_offset = reloc->address; | |
11391 | } | |
11392 | #endif | |
6c43fab6 | 11393 | |
c19d1205 | 11394 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 11395 | |
c19d1205 ZW |
11396 | if (reloc->howto == NULL) |
11397 | { | |
11398 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11399 | _("cannot represent %s relocation in this object file format"), | |
11400 | bfd_get_reloc_code_name (code)); | |
11401 | return NULL; | |
11402 | } | |
6c43fab6 | 11403 | |
c19d1205 ZW |
11404 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
11405 | vtable entry to be used in the relocation's section offset. */ | |
11406 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11407 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 11408 | |
c19d1205 | 11409 | return reloc; |
6c43fab6 RE |
11410 | } |
11411 | ||
c19d1205 | 11412 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 11413 | |
c19d1205 ZW |
11414 | void |
11415 | cons_fix_new_arm (fragS * frag, | |
11416 | int where, | |
11417 | int size, | |
11418 | expressionS * exp) | |
6c43fab6 | 11419 | { |
c19d1205 ZW |
11420 | bfd_reloc_code_real_type type; |
11421 | int pcrel = 0; | |
6c43fab6 | 11422 | |
c19d1205 ZW |
11423 | /* Pick a reloc. |
11424 | FIXME: @@ Should look at CPU word size. */ | |
11425 | switch (size) | |
11426 | { | |
11427 | case 1: | |
11428 | type = BFD_RELOC_8; | |
11429 | break; | |
11430 | case 2: | |
11431 | type = BFD_RELOC_16; | |
11432 | break; | |
11433 | case 4: | |
11434 | default: | |
11435 | type = BFD_RELOC_32; | |
11436 | break; | |
11437 | case 8: | |
11438 | type = BFD_RELOC_64; | |
11439 | break; | |
11440 | } | |
6c43fab6 | 11441 | |
c19d1205 ZW |
11442 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
11443 | } | |
6c43fab6 | 11444 | |
c19d1205 ZW |
11445 | #if defined OBJ_COFF || defined OBJ_ELF |
11446 | void | |
11447 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 11448 | { |
c19d1205 ZW |
11449 | /* If the destination of the branch is a defined symbol which does not have |
11450 | the THUMB_FUNC attribute, then we must be calling a function which has | |
11451 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
11452 | function and change the branch to refer to that function instead. */ | |
11453 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
11454 | && fixP->fx_addsy != NULL | |
11455 | && S_IS_DEFINED (fixP->fx_addsy) | |
11456 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 11457 | { |
c19d1205 | 11458 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 11459 | } |
c19d1205 ZW |
11460 | } |
11461 | #endif | |
6c43fab6 | 11462 | |
c19d1205 ZW |
11463 | int |
11464 | arm_force_relocation (struct fix * fixp) | |
11465 | { | |
11466 | #if defined (OBJ_COFF) && defined (TE_PE) | |
11467 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
11468 | return 1; | |
11469 | #endif | |
6c43fab6 | 11470 | |
c19d1205 ZW |
11471 | /* Resolve these relocations even if the symbol is extern or weak. */ |
11472 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
11473 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
11474 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) | |
11475 | return 0; | |
a737bd4d | 11476 | |
c19d1205 | 11477 | return generic_force_reloc (fixp); |
404ff6b5 AH |
11478 | } |
11479 | ||
c19d1205 ZW |
11480 | #ifdef OBJ_COFF |
11481 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents | |
11482 | local labels from being added to the output symbol table when they | |
11483 | are used with the ADRL pseudo op. The ADRL relocation should always | |
11484 | be resolved before the binbary is emitted, so it is safe to say that | |
11485 | it is adjustable. */ | |
404ff6b5 | 11486 | |
c19d1205 ZW |
11487 | bfd_boolean |
11488 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 11489 | { |
c19d1205 ZW |
11490 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) |
11491 | return 1; | |
11492 | return 0; | |
404ff6b5 | 11493 | } |
c19d1205 | 11494 | #endif |
404ff6b5 | 11495 | |
c19d1205 ZW |
11496 | #ifdef OBJ_ELF |
11497 | /* Relocations against Thumb function names must be left unadjusted, | |
11498 | so that the linker can use this information to correctly set the | |
11499 | bottom bit of their addresses. The MIPS version of this function | |
11500 | also prevents relocations that are mips-16 specific, but I do not | |
11501 | know why it does this. | |
404ff6b5 | 11502 | |
c19d1205 ZW |
11503 | FIXME: |
11504 | There is one other problem that ought to be addressed here, but | |
11505 | which currently is not: Taking the address of a label (rather | |
11506 | than a function) and then later jumping to that address. Such | |
11507 | addresses also ought to have their bottom bit set (assuming that | |
11508 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 11509 | |
c19d1205 ZW |
11510 | bfd_boolean |
11511 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 11512 | { |
c19d1205 ZW |
11513 | if (fixP->fx_addsy == NULL) |
11514 | return 1; | |
404ff6b5 | 11515 | |
c19d1205 ZW |
11516 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
11517 | && fixP->fx_subsy == NULL) | |
11518 | return 0; | |
a737bd4d | 11519 | |
c19d1205 ZW |
11520 | /* We need the symbol name for the VTABLE entries. */ |
11521 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
11522 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11523 | return 0; | |
404ff6b5 | 11524 | |
c19d1205 ZW |
11525 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
11526 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
11527 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
11528 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
11529 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
11530 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
11531 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
11532 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
11533 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
11534 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
11535 | return 0; | |
a737bd4d | 11536 | |
c19d1205 | 11537 | return 1; |
a737bd4d | 11538 | } |
404ff6b5 | 11539 | |
c19d1205 ZW |
11540 | const char * |
11541 | elf32_arm_target_format (void) | |
404ff6b5 | 11542 | { |
c19d1205 ZW |
11543 | #ifdef TE_SYMBIAN |
11544 | return (target_big_endian | |
11545 | ? "elf32-bigarm-symbian" | |
11546 | : "elf32-littlearm-symbian"); | |
11547 | #elif defined (TE_VXWORKS) | |
11548 | return (target_big_endian | |
11549 | ? "elf32-bigarm-vxworks" | |
11550 | : "elf32-littlearm-vxworks"); | |
11551 | #else | |
11552 | if (target_big_endian) | |
11553 | return "elf32-bigarm"; | |
11554 | else | |
11555 | return "elf32-littlearm"; | |
11556 | #endif | |
404ff6b5 AH |
11557 | } |
11558 | ||
c19d1205 ZW |
11559 | void |
11560 | armelf_frob_symbol (symbolS * symp, | |
11561 | int * puntp) | |
404ff6b5 | 11562 | { |
c19d1205 ZW |
11563 | elf_frob_symbol (symp, puntp); |
11564 | } | |
11565 | #endif | |
404ff6b5 | 11566 | |
c19d1205 | 11567 | /* MD interface: Finalization. */ |
a737bd4d | 11568 | |
c19d1205 ZW |
11569 | /* A good place to do this, although this was probably not intended |
11570 | for this kind of use. We need to dump the literal pool before | |
11571 | references are made to a null symbol pointer. */ | |
a737bd4d | 11572 | |
c19d1205 ZW |
11573 | void |
11574 | arm_cleanup (void) | |
11575 | { | |
11576 | literal_pool * pool; | |
a737bd4d | 11577 | |
c19d1205 ZW |
11578 | for (pool = list_of_pools; pool; pool = pool->next) |
11579 | { | |
11580 | /* Put it at the end of the relevent section. */ | |
11581 | subseg_set (pool->section, pool->sub_section); | |
11582 | #ifdef OBJ_ELF | |
11583 | arm_elf_change_section (); | |
11584 | #endif | |
11585 | s_ltorg (0); | |
11586 | } | |
404ff6b5 AH |
11587 | } |
11588 | ||
c19d1205 ZW |
11589 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
11590 | ARM ones. */ | |
404ff6b5 | 11591 | |
c19d1205 ZW |
11592 | void |
11593 | arm_adjust_symtab (void) | |
404ff6b5 | 11594 | { |
c19d1205 ZW |
11595 | #ifdef OBJ_COFF |
11596 | symbolS * sym; | |
404ff6b5 | 11597 | |
c19d1205 ZW |
11598 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
11599 | { | |
11600 | if (ARM_IS_THUMB (sym)) | |
11601 | { | |
11602 | if (THUMB_IS_FUNC (sym)) | |
11603 | { | |
11604 | /* Mark the symbol as a Thumb function. */ | |
11605 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
11606 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
11607 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 11608 | |
c19d1205 ZW |
11609 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
11610 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
11611 | else | |
11612 | as_bad (_("%s: unexpected function type: %d"), | |
11613 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
11614 | } | |
11615 | else switch (S_GET_STORAGE_CLASS (sym)) | |
11616 | { | |
11617 | case C_EXT: | |
11618 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
11619 | break; | |
11620 | case C_STAT: | |
11621 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
11622 | break; | |
11623 | case C_LABEL: | |
11624 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
11625 | break; | |
11626 | default: | |
11627 | /* Do nothing. */ | |
11628 | break; | |
11629 | } | |
11630 | } | |
a737bd4d | 11631 | |
c19d1205 ZW |
11632 | if (ARM_IS_INTERWORK (sym)) |
11633 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 11634 | } |
c19d1205 ZW |
11635 | #endif |
11636 | #ifdef OBJ_ELF | |
11637 | symbolS * sym; | |
11638 | char bind; | |
404ff6b5 | 11639 | |
c19d1205 | 11640 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 11641 | { |
c19d1205 ZW |
11642 | if (ARM_IS_THUMB (sym)) |
11643 | { | |
11644 | elf_symbol_type * elf_sym; | |
404ff6b5 | 11645 | |
c19d1205 ZW |
11646 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
11647 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 11648 | |
c19d1205 ZW |
11649 | if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name)) |
11650 | { | |
11651 | /* If it's a .thumb_func, declare it as so, | |
11652 | otherwise tag label as .code 16. */ | |
11653 | if (THUMB_IS_FUNC (sym)) | |
11654 | elf_sym->internal_elf_sym.st_info = | |
11655 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
11656 | else | |
11657 | elf_sym->internal_elf_sym.st_info = | |
11658 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
11659 | } | |
11660 | } | |
11661 | } | |
11662 | #endif | |
404ff6b5 AH |
11663 | } |
11664 | ||
c19d1205 | 11665 | /* MD interface: Initialization. */ |
404ff6b5 | 11666 | |
a737bd4d | 11667 | static void |
c19d1205 | 11668 | set_constant_flonums (void) |
a737bd4d | 11669 | { |
c19d1205 | 11670 | int i; |
404ff6b5 | 11671 | |
c19d1205 ZW |
11672 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
11673 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
11674 | abort (); | |
a737bd4d | 11675 | } |
404ff6b5 | 11676 | |
c19d1205 ZW |
11677 | void |
11678 | md_begin (void) | |
a737bd4d | 11679 | { |
c19d1205 ZW |
11680 | unsigned mach; |
11681 | unsigned int i; | |
404ff6b5 | 11682 | |
c19d1205 ZW |
11683 | if ( (arm_ops_hsh = hash_new ()) == NULL |
11684 | || (arm_cond_hsh = hash_new ()) == NULL | |
11685 | || (arm_shift_hsh = hash_new ()) == NULL | |
11686 | || (arm_psr_hsh = hash_new ()) == NULL | |
11687 | || (arm_reg_hsh = hash_new ()) == NULL | |
11688 | || (arm_reloc_hsh = hash_new ()) == NULL) | |
11689 | as_fatal (_("virtual memory exhausted")); | |
11690 | ||
11691 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
11692 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
11693 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
11694 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
11695 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
11696 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
11697 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
11698 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
11699 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) | |
11700 | hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); | |
11701 | #ifdef OBJ_ELF | |
11702 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
11703 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); | |
11704 | #endif | |
11705 | ||
11706 | set_constant_flonums (); | |
404ff6b5 | 11707 | |
c19d1205 ZW |
11708 | /* Set the cpu variant based on the command-line options. We prefer |
11709 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
11710 | -mfpu= over any other way of setting the floating point unit. | |
11711 | Use of legacy options with new options are faulted. */ | |
11712 | if (legacy_cpu != -1) | |
404ff6b5 | 11713 | { |
c19d1205 ZW |
11714 | if (mcpu_cpu_opt != -1 || march_cpu_opt != -1) |
11715 | as_bad (_("use of old and new-style options to set CPU type")); | |
11716 | ||
11717 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 11718 | } |
c19d1205 ZW |
11719 | else if (mcpu_cpu_opt == -1) |
11720 | mcpu_cpu_opt = march_cpu_opt; | |
404ff6b5 | 11721 | |
c19d1205 ZW |
11722 | if (legacy_fpu != -1) |
11723 | { | |
11724 | if (mfpu_opt != -1) | |
11725 | as_bad (_("use of old and new-style options to set FPU type")); | |
03b1477f RE |
11726 | |
11727 | mfpu_opt = legacy_fpu; | |
11728 | } | |
11729 | else if (mfpu_opt == -1) | |
11730 | { | |
c19d1205 | 11731 | #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) |
39c2da32 RE |
11732 | /* Some environments specify a default FPU. If they don't, infer it |
11733 | from the processor. */ | |
03b1477f RE |
11734 | if (mcpu_fpu_opt != -1) |
11735 | mfpu_opt = mcpu_fpu_opt; | |
11736 | else | |
11737 | mfpu_opt = march_fpu_opt; | |
39c2da32 RE |
11738 | #else |
11739 | mfpu_opt = FPU_DEFAULT; | |
11740 | #endif | |
03b1477f RE |
11741 | } |
11742 | ||
11743 | if (mfpu_opt == -1) | |
11744 | { | |
11745 | if (mcpu_cpu_opt == -1) | |
11746 | mfpu_opt = FPU_DEFAULT; | |
11747 | else if (mcpu_cpu_opt & ARM_EXT_V5) | |
11748 | mfpu_opt = FPU_ARCH_VFP_V2; | |
11749 | else | |
11750 | mfpu_opt = FPU_ARCH_FPA; | |
11751 | } | |
11752 | ||
11753 | if (mcpu_cpu_opt == -1) | |
11754 | mcpu_cpu_opt = CPU_DEFAULT; | |
11755 | ||
11756 | cpu_variant = mcpu_cpu_opt | mfpu_opt; | |
11757 | ||
f17c130b | 11758 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 11759 | { |
7cc69913 NC |
11760 | unsigned int flags = 0; |
11761 | ||
11762 | #if defined OBJ_ELF | |
11763 | flags = meabi_flags; | |
d507cf36 PB |
11764 | |
11765 | switch (meabi_flags) | |
33a392fb | 11766 | { |
d507cf36 | 11767 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 11768 | #endif |
d507cf36 PB |
11769 | /* Set the flags in the private structure. */ |
11770 | if (uses_apcs_26) flags |= F_APCS26; | |
11771 | if (support_interwork) flags |= F_INTERWORK; | |
11772 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 11773 | if (pic_code) flags |= F_PIC; |
d507cf36 PB |
11774 | if ((cpu_variant & FPU_ANY) == FPU_NONE |
11775 | || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */ | |
7cc69913 NC |
11776 | flags |= F_SOFT_FLOAT; |
11777 | ||
d507cf36 PB |
11778 | switch (mfloat_abi_opt) |
11779 | { | |
11780 | case ARM_FLOAT_ABI_SOFT: | |
11781 | case ARM_FLOAT_ABI_SOFTFP: | |
11782 | flags |= F_SOFT_FLOAT; | |
11783 | break; | |
33a392fb | 11784 | |
d507cf36 PB |
11785 | case ARM_FLOAT_ABI_HARD: |
11786 | if (flags & F_SOFT_FLOAT) | |
11787 | as_bad (_("hard-float conflicts with specified fpu")); | |
11788 | break; | |
11789 | } | |
03b1477f | 11790 | |
c19d1205 | 11791 | /* Using VFP conventions (even if soft-float). */ |
7cc69913 NC |
11792 | if (cpu_variant & FPU_VFP_EXT_NONE) |
11793 | flags |= F_VFP_FLOAT; | |
f17c130b | 11794 | |
fde78edd | 11795 | #if defined OBJ_ELF |
d507cf36 PB |
11796 | if (cpu_variant & FPU_ARCH_MAVERICK) |
11797 | flags |= EF_ARM_MAVERICK_FLOAT; | |
d507cf36 PB |
11798 | break; |
11799 | ||
8cb51566 | 11800 | case EF_ARM_EABI_VER4: |
c19d1205 | 11801 | /* No additional flags to set. */ |
d507cf36 PB |
11802 | break; |
11803 | ||
11804 | default: | |
11805 | abort (); | |
11806 | } | |
7cc69913 | 11807 | #endif |
b99bd4ef NC |
11808 | bfd_set_private_flags (stdoutput, flags); |
11809 | ||
11810 | /* We have run out flags in the COFF header to encode the | |
11811 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 11812 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
11813 | if (atpcs) |
11814 | { | |
11815 | asection * sec; | |
11816 | ||
11817 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
11818 | ||
11819 | if (sec != NULL) | |
11820 | { | |
11821 | bfd_set_section_flags | |
11822 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
11823 | bfd_set_section_size (stdoutput, sec, 0); | |
11824 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
11825 | } | |
11826 | } | |
7cc69913 | 11827 | } |
f17c130b | 11828 | #endif |
b99bd4ef NC |
11829 | |
11830 | /* Record the CPU type as well. */ | |
11831 | switch (cpu_variant & ARM_CPU_MASK) | |
11832 | { | |
11833 | case ARM_2: | |
11834 | mach = bfd_mach_arm_2; | |
11835 | break; | |
11836 | ||
c19d1205 | 11837 | case ARM_3: /* Also ARM_250. */ |
b99bd4ef NC |
11838 | mach = bfd_mach_arm_2a; |
11839 | break; | |
11840 | ||
c19d1205 | 11841 | case ARM_6: /* Also ARM_7. */ |
b89dddec RE |
11842 | mach = bfd_mach_arm_3; |
11843 | break; | |
11844 | ||
b99bd4ef | 11845 | default: |
5a6c6817 | 11846 | mach = bfd_mach_arm_unknown; |
b99bd4ef | 11847 | break; |
b99bd4ef NC |
11848 | } |
11849 | ||
11850 | /* Catch special cases. */ | |
e16bb312 NC |
11851 | if (cpu_variant & ARM_CEXT_IWMMXT) |
11852 | mach = bfd_mach_arm_iWMMXt; | |
11853 | else if (cpu_variant & ARM_CEXT_XSCALE) | |
b99bd4ef | 11854 | mach = bfd_mach_arm_XScale; |
fde78edd NC |
11855 | else if (cpu_variant & ARM_CEXT_MAVERICK) |
11856 | mach = bfd_mach_arm_ep9312; | |
b99bd4ef NC |
11857 | else if (cpu_variant & ARM_EXT_V5E) |
11858 | mach = bfd_mach_arm_5TE; | |
11859 | else if (cpu_variant & ARM_EXT_V5) | |
11860 | { | |
b89dddec | 11861 | if (cpu_variant & ARM_EXT_V4T) |
b99bd4ef NC |
11862 | mach = bfd_mach_arm_5T; |
11863 | else | |
11864 | mach = bfd_mach_arm_5; | |
11865 | } | |
b89dddec | 11866 | else if (cpu_variant & ARM_EXT_V4) |
b99bd4ef | 11867 | { |
b89dddec | 11868 | if (cpu_variant & ARM_EXT_V4T) |
b99bd4ef NC |
11869 | mach = bfd_mach_arm_4T; |
11870 | else | |
11871 | mach = bfd_mach_arm_4; | |
11872 | } | |
b89dddec | 11873 | else if (cpu_variant & ARM_EXT_V3M) |
b99bd4ef NC |
11874 | mach = bfd_mach_arm_3M; |
11875 | ||
11876 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
11877 | } | |
11878 | ||
c19d1205 | 11879 | /* Command line processing. */ |
b99bd4ef | 11880 | |
c19d1205 ZW |
11881 | /* md_parse_option |
11882 | Invocation line includes a switch not recognized by the base assembler. | |
11883 | See if it's a processor-specific option. | |
b99bd4ef | 11884 | |
c19d1205 ZW |
11885 | This routine is somewhat complicated by the need for backwards |
11886 | compatibility (since older releases of gcc can't be changed). | |
11887 | The new options try to make the interface as compatible as | |
11888 | possible with GCC. | |
b99bd4ef | 11889 | |
c19d1205 | 11890 | New options (supported) are: |
b99bd4ef | 11891 | |
c19d1205 ZW |
11892 | -mcpu=<cpu name> Assemble for selected processor |
11893 | -march=<architecture name> Assemble for selected architecture | |
11894 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
11895 | -EB/-mbig-endian Big-endian | |
11896 | -EL/-mlittle-endian Little-endian | |
11897 | -k Generate PIC code | |
11898 | -mthumb Start in Thumb mode | |
11899 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 11900 | |
c19d1205 | 11901 | For now we will also provide support for: |
b99bd4ef | 11902 | |
c19d1205 ZW |
11903 | -mapcs-32 32-bit Program counter |
11904 | -mapcs-26 26-bit Program counter | |
11905 | -macps-float Floats passed in FP registers | |
11906 | -mapcs-reentrant Reentrant code | |
11907 | -matpcs | |
11908 | (sometime these will probably be replaced with -mapcs=<list of options> | |
11909 | and -matpcs=<list of options>) | |
b99bd4ef | 11910 | |
c19d1205 ZW |
11911 | The remaining options are only supported for back-wards compatibility. |
11912 | Cpu variants, the arm part is optional: | |
11913 | -m[arm]1 Currently not supported. | |
11914 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
11915 | -m[arm]3 Arm 3 processor | |
11916 | -m[arm]6[xx], Arm 6 processors | |
11917 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
11918 | -m[arm]8[10] Arm 8 processors | |
11919 | -m[arm]9[20][tdmi] Arm 9 processors | |
11920 | -mstrongarm[110[0]] StrongARM processors | |
11921 | -mxscale XScale processors | |
11922 | -m[arm]v[2345[t[e]]] Arm architectures | |
11923 | -mall All (except the ARM1) | |
11924 | FP variants: | |
11925 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
11926 | -mfpe-old (No float load/store multiples) | |
11927 | -mvfpxd VFP Single precision | |
11928 | -mvfp All VFP | |
11929 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 11930 | |
c19d1205 ZW |
11931 | The following CPU names are recognized: |
11932 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
11933 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
11934 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
11935 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
11936 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
11937 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
11938 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 11939 | |
c19d1205 | 11940 | */ |
b99bd4ef | 11941 | |
c19d1205 | 11942 | const char * md_shortopts = "m:k"; |
b99bd4ef | 11943 | |
c19d1205 ZW |
11944 | #ifdef ARM_BI_ENDIAN |
11945 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
11946 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 11947 | #else |
c19d1205 ZW |
11948 | #if TARGET_BYTES_BIG_ENDIAN |
11949 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 11950 | #else |
c19d1205 ZW |
11951 | #define OPTION_EL (OPTION_MD_BASE + 1) |
11952 | #endif | |
b99bd4ef | 11953 | #endif |
b99bd4ef | 11954 | |
c19d1205 | 11955 | struct option md_longopts[] = |
b99bd4ef | 11956 | { |
c19d1205 ZW |
11957 | #ifdef OPTION_EB |
11958 | {"EB", no_argument, NULL, OPTION_EB}, | |
11959 | #endif | |
11960 | #ifdef OPTION_EL | |
11961 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 11962 | #endif |
c19d1205 ZW |
11963 | {NULL, no_argument, NULL, 0} |
11964 | }; | |
b99bd4ef | 11965 | |
c19d1205 | 11966 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 11967 | |
c19d1205 | 11968 | struct arm_option_table |
b99bd4ef | 11969 | { |
c19d1205 ZW |
11970 | char *option; /* Option name to match. */ |
11971 | char *help; /* Help information. */ | |
11972 | int *var; /* Variable to change. */ | |
11973 | int value; /* What to change it to. */ | |
11974 | char *deprecated; /* If non-null, print this message. */ | |
11975 | }; | |
b99bd4ef | 11976 | |
c19d1205 ZW |
11977 | struct arm_option_table arm_opts[] = |
11978 | { | |
11979 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
11980 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
11981 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
11982 | &support_interwork, 1, NULL}, | |
11983 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
11984 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
11985 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
11986 | 1, NULL}, | |
11987 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
11988 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
11989 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
11990 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
11991 | NULL}, | |
b99bd4ef | 11992 | |
c19d1205 ZW |
11993 | /* These are recognized by the assembler, but have no affect on code. */ |
11994 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
11995 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
b99bd4ef | 11996 | |
c19d1205 ZW |
11997 | /* DON'T add any new processors to this list -- we want the whole list |
11998 | to go away... Add them to the processors table instead. */ | |
11999 | {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
12000 | {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
12001 | {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
12002 | {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
12003 | {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
12004 | {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
12005 | {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
12006 | {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
12007 | {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
12008 | {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
12009 | {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
12010 | {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
12011 | {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
12012 | {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
12013 | {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
12014 | {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
12015 | {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
12016 | {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
12017 | {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
12018 | {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
12019 | {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
12020 | {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
12021 | {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
12022 | {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
12023 | {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
12024 | {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
12025 | {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
12026 | {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
12027 | {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
12028 | {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
12029 | {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
12030 | {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
12031 | {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
12032 | {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
12033 | {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
12034 | {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
12035 | {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
12036 | {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
12037 | {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
12038 | {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
12039 | {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
12040 | {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
12041 | {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
12042 | {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
12043 | {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
12044 | {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
12045 | {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12046 | {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12047 | {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12048 | {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12049 | {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
12050 | {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
12051 | {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
12052 | {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
12053 | {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
12054 | {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
12055 | {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
12056 | {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
12057 | {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
12058 | {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
12059 | {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
12060 | {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
12061 | {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
12062 | {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
12063 | {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
12064 | {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
12065 | {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
12066 | {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
12067 | {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
12068 | {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4, | |
12069 | N_("use -mcpu=strongarm110")}, | |
12070 | {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4, | |
12071 | N_("use -mcpu=strongarm1100")}, | |
12072 | {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4, | |
12073 | N_("use -mcpu=strongarm1110")}, | |
12074 | {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, | |
12075 | {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
12076 | {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 12077 | |
c19d1205 ZW |
12078 | /* Architecture variants -- don't add any more to this list either. */ |
12079 | {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
12080 | {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
12081 | {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
12082 | {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
12083 | {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
12084 | {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
12085 | {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
12086 | {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
12087 | {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
12088 | {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
12089 | {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
12090 | {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
12091 | {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
12092 | {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
12093 | {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
12094 | {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
12095 | {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
12096 | {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 12097 | |
c19d1205 ZW |
12098 | /* Floating point variants -- don't add any more to this list either. */ |
12099 | {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, | |
12100 | {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
12101 | {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
12102 | {"mno-fpu", NULL, &legacy_fpu, 0, | |
12103 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, | |
7ed4c4c5 | 12104 | |
c19d1205 ZW |
12105 | {NULL, NULL, NULL, 0, NULL} |
12106 | }; | |
7ed4c4c5 | 12107 | |
c19d1205 | 12108 | struct arm_cpu_option_table |
7ed4c4c5 | 12109 | { |
c19d1205 ZW |
12110 | char *name; |
12111 | int value; | |
12112 | /* For some CPUs we assume an FPU unless the user explicitly sets | |
12113 | -mfpu=... */ | |
12114 | int default_fpu; | |
12115 | }; | |
7ed4c4c5 | 12116 | |
c19d1205 ZW |
12117 | /* This list should, at a minimum, contain all the cpu names |
12118 | recognized by GCC. */ | |
12119 | static struct arm_cpu_option_table arm_cpus[] = | |
12120 | { | |
12121 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
12122 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
12123 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
12124 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12125 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12126 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12127 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12128 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12129 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12130 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12131 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12132 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12133 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12134 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12135 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12136 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12137 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12138 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12139 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12140 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12141 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12142 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12143 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12144 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12145 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12146 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12147 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12148 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12149 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12150 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12151 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12152 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12153 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12154 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12155 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12156 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12157 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12158 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12159 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12160 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12161 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12162 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12163 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12164 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12165 | /* For V5 or later processors we default to using VFP; but the user | |
12166 | should really set the FPU type explicitly. */ | |
12167 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2}, | |
12168 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12169 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12170 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12171 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12172 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2}, | |
12173 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12174 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2}, | |
12175 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12176 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1}, | |
12177 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12178 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12179 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1}, | |
12180 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12181 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12182 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12183 | {"arm1136js", ARM_ARCH_V6, FPU_NONE}, | |
12184 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE}, | |
12185 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2}, | |
12186 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2}, | |
12187 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2}, | |
12188 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE}, | |
12189 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE}, | |
12190 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2}, | |
12191 | /* ??? XSCALE is really an architecture. */ | |
12192 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2}, | |
12193 | /* ??? iwmmxt is not a processor. */ | |
12194 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2}, | |
12195 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2}, | |
12196 | /* Maverick */ | |
12197 | {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK}, | |
12198 | {NULL, 0, 0} | |
12199 | }; | |
7ed4c4c5 | 12200 | |
c19d1205 | 12201 | struct arm_arch_option_table |
7ed4c4c5 | 12202 | { |
c19d1205 ZW |
12203 | char *name; |
12204 | int value; | |
12205 | int default_fpu; | |
12206 | }; | |
7ed4c4c5 | 12207 | |
c19d1205 ZW |
12208 | /* This list should, at a minimum, contain all the architecture names |
12209 | recognized by GCC. */ | |
12210 | static struct arm_arch_option_table arm_archs[] = | |
12211 | { | |
12212 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
12213 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
12214 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
12215 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12216 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12217 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12218 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12219 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12220 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
12221 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12222 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
12223 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
12224 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
12225 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
12226 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
12227 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
12228 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
12229 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
12230 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
12231 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
12232 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
12233 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
12234 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
12235 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
12236 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
12237 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
12238 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, | |
12239 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
12240 | {NULL, 0, 0} | |
12241 | }; | |
7ed4c4c5 | 12242 | |
c19d1205 ZW |
12243 | /* ISA extensions in the co-processor space. */ |
12244 | struct arm_option_value_table | |
12245 | { | |
12246 | char *name; | |
12247 | int value; | |
12248 | }; | |
7ed4c4c5 | 12249 | |
c19d1205 ZW |
12250 | static struct arm_option_value_table arm_extensions[] = |
12251 | { | |
12252 | {"maverick", ARM_CEXT_MAVERICK}, | |
12253 | {"xscale", ARM_CEXT_XSCALE}, | |
12254 | {"iwmmxt", ARM_CEXT_IWMMXT}, | |
12255 | {NULL, 0} | |
12256 | }; | |
7ed4c4c5 | 12257 | |
c19d1205 ZW |
12258 | /* This list should, at a minimum, contain all the fpu names |
12259 | recognized by GCC. */ | |
12260 | static struct arm_option_value_table arm_fpus[] = | |
12261 | { | |
12262 | {"softfpa", FPU_NONE}, | |
12263 | {"fpe", FPU_ARCH_FPE}, | |
12264 | {"fpe2", FPU_ARCH_FPE}, | |
12265 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
12266 | {"fpa", FPU_ARCH_FPA}, | |
12267 | {"fpa10", FPU_ARCH_FPA}, | |
12268 | {"fpa11", FPU_ARCH_FPA}, | |
12269 | {"arm7500fe", FPU_ARCH_FPA}, | |
12270 | {"softvfp", FPU_ARCH_VFP}, | |
12271 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
12272 | {"vfp", FPU_ARCH_VFP_V2}, | |
12273 | {"vfp9", FPU_ARCH_VFP_V2}, | |
12274 | {"vfp10", FPU_ARCH_VFP_V2}, | |
12275 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
12276 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
12277 | {"arm1020t", FPU_ARCH_VFP_V1}, | |
12278 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
12279 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
12280 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
12281 | {"maverick", FPU_ARCH_MAVERICK}, | |
12282 | {NULL, 0} | |
12283 | }; | |
7ed4c4c5 | 12284 | |
c19d1205 ZW |
12285 | static struct arm_option_value_table arm_float_abis[] = |
12286 | { | |
12287 | {"hard", ARM_FLOAT_ABI_HARD}, | |
12288 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
12289 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
12290 | {NULL, 0} | |
12291 | }; | |
7ed4c4c5 | 12292 | |
c19d1205 ZW |
12293 | #ifdef OBJ_ELF |
12294 | /* We only know how to output GNU and ver 4 (AAELF) formats. */ | |
12295 | static struct arm_option_value_table arm_eabis[] = | |
12296 | { | |
12297 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
12298 | {"4", EF_ARM_EABI_VER4}, | |
12299 | {NULL, 0} | |
12300 | }; | |
12301 | #endif | |
7ed4c4c5 | 12302 | |
c19d1205 ZW |
12303 | struct arm_long_option_table |
12304 | { | |
12305 | char * option; /* Substring to match. */ | |
12306 | char * help; /* Help information. */ | |
12307 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
12308 | char * deprecated; /* If non-null, print this message. */ | |
12309 | }; | |
7ed4c4c5 NC |
12310 | |
12311 | static int | |
c19d1205 | 12312 | arm_parse_extension (char * str, int * opt_p) |
7ed4c4c5 | 12313 | { |
c19d1205 | 12314 | while (str != NULL && *str != 0) |
7ed4c4c5 | 12315 | { |
c19d1205 ZW |
12316 | struct arm_option_value_table * opt; |
12317 | char * ext; | |
12318 | int optlen; | |
7ed4c4c5 | 12319 | |
c19d1205 ZW |
12320 | if (*str != '+') |
12321 | { | |
12322 | as_bad (_("invalid architectural extension")); | |
12323 | return 0; | |
12324 | } | |
7ed4c4c5 | 12325 | |
c19d1205 ZW |
12326 | str++; |
12327 | ext = strchr (str, '+'); | |
7ed4c4c5 | 12328 | |
c19d1205 ZW |
12329 | if (ext != NULL) |
12330 | optlen = ext - str; | |
12331 | else | |
12332 | optlen = strlen (str); | |
7ed4c4c5 | 12333 | |
c19d1205 ZW |
12334 | if (optlen == 0) |
12335 | { | |
12336 | as_bad (_("missing architectural extension")); | |
12337 | return 0; | |
12338 | } | |
7ed4c4c5 | 12339 | |
c19d1205 ZW |
12340 | for (opt = arm_extensions; opt->name != NULL; opt++) |
12341 | if (strncmp (opt->name, str, optlen) == 0) | |
12342 | { | |
12343 | *opt_p |= opt->value; | |
12344 | break; | |
12345 | } | |
7ed4c4c5 | 12346 | |
c19d1205 ZW |
12347 | if (opt->name == NULL) |
12348 | { | |
12349 | as_bad (_("unknown architectural extnsion `%s'"), str); | |
12350 | return 0; | |
12351 | } | |
7ed4c4c5 | 12352 | |
c19d1205 ZW |
12353 | str = ext; |
12354 | }; | |
7ed4c4c5 | 12355 | |
c19d1205 ZW |
12356 | return 1; |
12357 | } | |
7ed4c4c5 | 12358 | |
c19d1205 ZW |
12359 | static int |
12360 | arm_parse_cpu (char * str) | |
7ed4c4c5 | 12361 | { |
c19d1205 ZW |
12362 | struct arm_cpu_option_table * opt; |
12363 | char * ext = strchr (str, '+'); | |
12364 | int optlen; | |
7ed4c4c5 | 12365 | |
c19d1205 ZW |
12366 | if (ext != NULL) |
12367 | optlen = ext - str; | |
7ed4c4c5 | 12368 | else |
c19d1205 | 12369 | optlen = strlen (str); |
7ed4c4c5 | 12370 | |
c19d1205 | 12371 | if (optlen == 0) |
7ed4c4c5 | 12372 | { |
c19d1205 ZW |
12373 | as_bad (_("missing cpu name `%s'"), str); |
12374 | return 0; | |
7ed4c4c5 NC |
12375 | } |
12376 | ||
c19d1205 ZW |
12377 | for (opt = arm_cpus; opt->name != NULL; opt++) |
12378 | if (strncmp (opt->name, str, optlen) == 0) | |
12379 | { | |
12380 | mcpu_cpu_opt = opt->value; | |
12381 | mcpu_fpu_opt = opt->default_fpu; | |
7ed4c4c5 | 12382 | |
c19d1205 ZW |
12383 | if (ext != NULL) |
12384 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 12385 | |
c19d1205 ZW |
12386 | return 1; |
12387 | } | |
7ed4c4c5 | 12388 | |
c19d1205 ZW |
12389 | as_bad (_("unknown cpu `%s'"), str); |
12390 | return 0; | |
7ed4c4c5 NC |
12391 | } |
12392 | ||
c19d1205 ZW |
12393 | static int |
12394 | arm_parse_arch (char * str) | |
7ed4c4c5 | 12395 | { |
c19d1205 ZW |
12396 | struct arm_arch_option_table *opt; |
12397 | char *ext = strchr (str, '+'); | |
12398 | int optlen; | |
7ed4c4c5 | 12399 | |
c19d1205 ZW |
12400 | if (ext != NULL) |
12401 | optlen = ext - str; | |
7ed4c4c5 | 12402 | else |
c19d1205 | 12403 | optlen = strlen (str); |
7ed4c4c5 | 12404 | |
c19d1205 | 12405 | if (optlen == 0) |
7ed4c4c5 | 12406 | { |
c19d1205 ZW |
12407 | as_bad (_("missing architecture name `%s'"), str); |
12408 | return 0; | |
7ed4c4c5 NC |
12409 | } |
12410 | ||
7ed4c4c5 | 12411 | |
c19d1205 ZW |
12412 | for (opt = arm_archs; opt->name != NULL; opt++) |
12413 | if (streq (opt->name, str)) | |
12414 | { | |
12415 | march_cpu_opt = opt->value; | |
12416 | march_fpu_opt = opt->default_fpu; | |
7ed4c4c5 | 12417 | |
c19d1205 ZW |
12418 | if (ext != NULL) |
12419 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 12420 | |
c19d1205 ZW |
12421 | return 1; |
12422 | } | |
12423 | ||
12424 | as_bad (_("unknown architecture `%s'\n"), str); | |
12425 | return 0; | |
7ed4c4c5 | 12426 | } |
eb043451 | 12427 | |
c19d1205 ZW |
12428 | static int |
12429 | arm_parse_fpu (char * str) | |
12430 | { | |
12431 | struct arm_option_value_table * opt; | |
b99bd4ef | 12432 | |
c19d1205 ZW |
12433 | for (opt = arm_fpus; opt->name != NULL; opt++) |
12434 | if (streq (opt->name, str)) | |
12435 | { | |
12436 | mfpu_opt = opt->value; | |
12437 | return 1; | |
12438 | } | |
b99bd4ef | 12439 | |
c19d1205 ZW |
12440 | as_bad (_("unknown floating point format `%s'\n"), str); |
12441 | return 0; | |
12442 | } | |
12443 | ||
12444 | static int | |
12445 | arm_parse_float_abi (char * str) | |
b99bd4ef | 12446 | { |
c19d1205 | 12447 | struct arm_option_value_table * opt; |
b99bd4ef | 12448 | |
c19d1205 ZW |
12449 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
12450 | if (streq (opt->name, str)) | |
12451 | { | |
12452 | mfloat_abi_opt = opt->value; | |
12453 | return 1; | |
12454 | } | |
cc8a6dd0 | 12455 | |
c19d1205 ZW |
12456 | as_bad (_("unknown floating point abi `%s'\n"), str); |
12457 | return 0; | |
12458 | } | |
b99bd4ef | 12459 | |
c19d1205 ZW |
12460 | #ifdef OBJ_ELF |
12461 | static int | |
12462 | arm_parse_eabi (char * str) | |
12463 | { | |
12464 | struct arm_option_value_table *opt; | |
cc8a6dd0 | 12465 | |
c19d1205 ZW |
12466 | for (opt = arm_eabis; opt->name != NULL; opt++) |
12467 | if (streq (opt->name, str)) | |
12468 | { | |
12469 | meabi_flags = opt->value; | |
12470 | return 1; | |
12471 | } | |
12472 | as_bad (_("unknown EABI `%s'\n"), str); | |
12473 | return 0; | |
12474 | } | |
12475 | #endif | |
cc8a6dd0 | 12476 | |
c19d1205 ZW |
12477 | struct arm_long_option_table arm_long_opts[] = |
12478 | { | |
12479 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
12480 | arm_parse_cpu, NULL}, | |
12481 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
12482 | arm_parse_arch, NULL}, | |
12483 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
12484 | arm_parse_fpu, NULL}, | |
12485 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
12486 | arm_parse_float_abi, NULL}, | |
12487 | #ifdef OBJ_ELF | |
12488 | {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), | |
12489 | arm_parse_eabi, NULL}, | |
12490 | #endif | |
12491 | {NULL, NULL, 0, NULL} | |
12492 | }; | |
cc8a6dd0 | 12493 | |
c19d1205 ZW |
12494 | int |
12495 | md_parse_option (int c, char * arg) | |
12496 | { | |
12497 | struct arm_option_table *opt; | |
12498 | struct arm_long_option_table *lopt; | |
b99bd4ef | 12499 | |
c19d1205 | 12500 | switch (c) |
b99bd4ef | 12501 | { |
c19d1205 ZW |
12502 | #ifdef OPTION_EB |
12503 | case OPTION_EB: | |
12504 | target_big_endian = 1; | |
12505 | break; | |
12506 | #endif | |
cc8a6dd0 | 12507 | |
c19d1205 ZW |
12508 | #ifdef OPTION_EL |
12509 | case OPTION_EL: | |
12510 | target_big_endian = 0; | |
12511 | break; | |
12512 | #endif | |
b99bd4ef | 12513 | |
c19d1205 ZW |
12514 | case 'a': |
12515 | /* Listing option. Just ignore these, we don't support additional | |
12516 | ones. */ | |
12517 | return 0; | |
b99bd4ef | 12518 | |
c19d1205 ZW |
12519 | default: |
12520 | for (opt = arm_opts; opt->option != NULL; opt++) | |
12521 | { | |
12522 | if (c == opt->option[0] | |
12523 | && ((arg == NULL && opt->option[1] == 0) | |
12524 | || streq (arg, opt->option + 1))) | |
12525 | { | |
12526 | #if WARN_DEPRECATED | |
12527 | /* If the option is deprecated, tell the user. */ | |
12528 | if (opt->deprecated != NULL) | |
12529 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
12530 | arg ? arg : "", _(opt->deprecated)); | |
12531 | #endif | |
b99bd4ef | 12532 | |
c19d1205 ZW |
12533 | if (opt->var != NULL) |
12534 | *opt->var = opt->value; | |
cc8a6dd0 | 12535 | |
c19d1205 ZW |
12536 | return 1; |
12537 | } | |
12538 | } | |
b99bd4ef | 12539 | |
c19d1205 ZW |
12540 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
12541 | { | |
12542 | /* These options are expected to have an argument. */ | |
12543 | if (c == lopt->option[0] | |
12544 | && arg != NULL | |
12545 | && strncmp (arg, lopt->option + 1, | |
12546 | strlen (lopt->option + 1)) == 0) | |
12547 | { | |
12548 | #if WARN_DEPRECATED | |
12549 | /* If the option is deprecated, tell the user. */ | |
12550 | if (lopt->deprecated != NULL) | |
12551 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
12552 | _(lopt->deprecated)); | |
12553 | #endif | |
b99bd4ef | 12554 | |
c19d1205 ZW |
12555 | /* Call the sup-option parser. */ |
12556 | return lopt->func (arg + strlen (lopt->option) - 1); | |
12557 | } | |
12558 | } | |
a737bd4d | 12559 | |
c19d1205 ZW |
12560 | return 0; |
12561 | } | |
a394c00f | 12562 | |
c19d1205 ZW |
12563 | return 1; |
12564 | } | |
a394c00f | 12565 | |
c19d1205 ZW |
12566 | void |
12567 | md_show_usage (FILE * fp) | |
a394c00f | 12568 | { |
c19d1205 ZW |
12569 | struct arm_option_table *opt; |
12570 | struct arm_long_option_table *lopt; | |
a394c00f | 12571 | |
c19d1205 | 12572 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 12573 | |
c19d1205 ZW |
12574 | for (opt = arm_opts; opt->option != NULL; opt++) |
12575 | if (opt->help != NULL) | |
12576 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 12577 | |
c19d1205 ZW |
12578 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
12579 | if (lopt->help != NULL) | |
12580 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 12581 | |
c19d1205 ZW |
12582 | #ifdef OPTION_EB |
12583 | fprintf (fp, _("\ | |
12584 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
12585 | #endif |
12586 | ||
c19d1205 ZW |
12587 | #ifdef OPTION_EL |
12588 | fprintf (fp, _("\ | |
12589 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 12590 | #endif |
c19d1205 | 12591 | } |