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b99bd4ef NC |
1 | /* tc-arm.c -- Assemble for the ARM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 | |
3 | Free Software Foundation, Inc. | |
4 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
5 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 6 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
b99bd4ef NC |
7 | |
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
24 | ||
b99bd4ef NC |
25 | #include <string.h> |
26 | #define NO_RELOC 0 | |
27 | #include "as.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
b99bd4ef NC |
29 | |
30 | /* Need TARGET_CPU. */ | |
31 | #include "config.h" | |
32 | #include "subsegs.h" | |
33 | #include "obstack.h" | |
34 | #include "symbols.h" | |
35 | #include "listing.h" | |
36 | ||
37 | #ifdef OBJ_ELF | |
38 | #include "elf/arm.h" | |
39 | #include "dwarf2dbg.h" | |
40 | #endif | |
41 | ||
b89dddec RE |
42 | /* The following bitmasks control CPU extensions: */ |
43 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ | |
44 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ | |
45 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ | |
46 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ | |
47 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ | |
48 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ | |
49 | #define ARM_EXT_V4T 0x00000040 /* Thumb v1. */ | |
50 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ | |
51 | #define ARM_EXT_V5T 0x00000100 /* Thumb v2. */ | |
52 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ | |
53 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ | |
54 | /* Processor specific extensions. */ | |
55 | #define ARM_EXT_XSCALE 0x00000800 /* Allow MIA etc. */ | |
56 | #define ARM_EXT_MAVERICK 0x00001000 /* Use Cirrus/DSP coprocessor. */ | |
57 | ||
58 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) | |
59 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, | |
60 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add | |
61 | three more to cover cores prior to ARM6. Finally, there are cores which | |
62 | implement further extensions in the co-processor space. */ | |
63 | #define ARM_ARCH_V1 ARM_EXT_V1 | |
64 | #define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2) | |
65 | #define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S) | |
66 | #define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3) | |
67 | #define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M) | |
68 | #define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4) | |
69 | #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4) | |
70 | #define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T) | |
71 | #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T) | |
72 | #define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5) | |
73 | #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5) | |
74 | #define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) | |
75 | #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T) | |
76 | #define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP) | |
77 | #define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E) | |
78 | /* Processors with specific extensions in the co-processor space. */ | |
79 | #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE) | |
b99bd4ef NC |
80 | |
81 | /* Some useful combinations: */ | |
82 | #define ARM_ANY 0x00ffffff | |
83 | #define ARM_2UP (ARM_ANY - ARM_1) | |
b89dddec | 84 | #define ARM_ALL ARM_ANY |
b99bd4ef | 85 | |
b89dddec RE |
86 | #define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */ |
87 | #define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */ | |
b99bd4ef NC |
88 | #define FPU_NONE 0 |
89 | ||
b89dddec RE |
90 | #define FPU_ARCH_FPE FPU_FPA_EXT_V1 |
91 | #define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2) | |
92 | ||
b99bd4ef | 93 | /* Some useful combinations. */ |
b89dddec RE |
94 | #define FPU_ANY 0xff000000 /* Note this is ~ARM_ANY. */ |
95 | ||
96 | /* Types of processor to assemble for. */ | |
97 | #define ARM_1 ARM_ARCH_V1 | |
98 | #define ARM_2 ARM_ARCH_V2 | |
99 | #define ARM_3 ARM_ARCH_V2S | |
100 | #define ARM_250 ARM_ARCH_V2S | |
101 | #define ARM_6 ARM_ARCH_V3 | |
102 | #define ARM_7 ARM_ARCH_V3 | |
103 | #define ARM_8 ARM_ARCH_V4 | |
104 | #define ARM_9 ARM_ARCH_V4T | |
105 | #define ARM_STRONG ARM_ARCH_V4 | |
106 | #define ARM_CPU_MASK 0x0000000f /* XXX? */ | |
b99bd4ef NC |
107 | |
108 | #ifndef CPU_DEFAULT | |
109 | #if defined __XSCALE__ | |
b89dddec | 110 | #define CPU_DEFAULT (ARM_ARCH_XSCALE) |
b99bd4ef NC |
111 | #else |
112 | #if defined __thumb__ | |
b89dddec | 113 | #define CPU_DEFAULT (ARM_ARCH_V5T) |
b99bd4ef NC |
114 | #else |
115 | #define CPU_DEFAULT ARM_ALL | |
116 | #endif | |
117 | #endif | |
118 | #endif | |
119 | ||
120 | #ifndef FPU_DEFAULT | |
b89dddec | 121 | #define FPU_DEFAULT FPU_ARCH_FPA |
b99bd4ef NC |
122 | #endif |
123 | ||
124 | #define streq(a, b) (strcmp (a, b) == 0) | |
125 | #define skip_whitespace(str) while (*(str) == ' ') ++(str) | |
126 | ||
127 | static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT; | |
128 | static int target_oabi = 0; | |
129 | ||
130 | #if defined OBJ_COFF || defined OBJ_ELF | |
131 | /* Flags stored in private area of BFD structure. */ | |
132 | static boolean uses_apcs_26 = false; | |
133 | static boolean atpcs = false; | |
134 | static boolean support_interwork = false; | |
135 | static boolean uses_apcs_float = false; | |
136 | static boolean pic_code = false; | |
137 | #endif | |
138 | ||
139 | /* This array holds the chars that always start a comment. If the | |
140 | pre-processor is disabled, these aren't very useful. */ | |
f57c81f6 | 141 | const char comment_chars[] = "@"; |
b99bd4ef NC |
142 | |
143 | /* This array holds the chars that only start a comment at the beginning of | |
144 | a line. If the line seems to have the form '# 123 filename' | |
145 | .line and .file directives will appear in the pre-processed output. */ | |
146 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
147 | first line of the input file. This is because the compiler outputs | |
148 | #NO_APP at the beginning of its output. */ | |
149 | /* Also note that comments like this one will always work. */ | |
05d2d07e | 150 | const char line_comment_chars[] = "#"; |
b99bd4ef | 151 | |
da89cce1 | 152 | const char line_separator_chars[] = ";"; |
b99bd4ef NC |
153 | |
154 | /* Chars that can be used to separate mant | |
155 | from exp in floating point numbers. */ | |
05d2d07e | 156 | const char EXP_CHARS[] = "eE"; |
b99bd4ef NC |
157 | |
158 | /* Chars that mean this number is a floating point constant. */ | |
159 | /* As in 0f12.456 */ | |
160 | /* or 0d1.2345e12 */ | |
161 | ||
05d2d07e | 162 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
b99bd4ef NC |
163 | |
164 | /* Prefix characters that indicate the start of an immediate | |
165 | value. */ | |
166 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
167 | ||
168 | #ifdef OBJ_ELF | |
169 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
170 | symbolS * GOT_symbol; | |
171 | #endif | |
172 | ||
173 | /* Size of relocation record. */ | |
05d2d07e | 174 | const int md_reloc_size = 8; |
b99bd4ef NC |
175 | |
176 | /* 0: assemble for ARM, | |
177 | 1: assemble for Thumb, | |
178 | 2: assemble for Thumb even though target CPU does not support thumb | |
179 | instructions. */ | |
180 | static int thumb_mode = 0; | |
181 | ||
182 | typedef struct arm_fix | |
183 | { | |
184 | int thumb_mode; | |
185 | } arm_fix_data; | |
186 | ||
187 | struct arm_it | |
188 | { | |
05d2d07e | 189 | const char * error; |
b99bd4ef NC |
190 | unsigned long instruction; |
191 | int suffix; | |
192 | int size; | |
193 | struct | |
194 | { | |
195 | bfd_reloc_code_real_type type; | |
196 | expressionS exp; | |
197 | int pc_rel; | |
198 | } reloc; | |
199 | }; | |
200 | ||
201 | struct arm_it inst; | |
202 | ||
203 | enum asm_shift_index | |
204 | { | |
205 | SHIFT_LSL = 0, | |
206 | SHIFT_LSR, | |
207 | SHIFT_ASR, | |
208 | SHIFT_ROR, | |
209 | SHIFT_RRX | |
210 | }; | |
211 | ||
212 | struct asm_shift_properties | |
213 | { | |
214 | enum asm_shift_index index; | |
215 | unsigned long bit_field; | |
216 | unsigned int allows_0 : 1; | |
217 | unsigned int allows_32 : 1; | |
218 | }; | |
219 | ||
220 | static const struct asm_shift_properties shift_properties [] = | |
221 | { | |
222 | { SHIFT_LSL, 0, 1, 0}, | |
223 | { SHIFT_LSR, 0x20, 0, 1}, | |
224 | { SHIFT_ASR, 0x40, 0, 1}, | |
225 | { SHIFT_ROR, 0x60, 0, 0}, | |
226 | { SHIFT_RRX, 0x60, 0, 0} | |
227 | }; | |
228 | ||
229 | struct asm_shift_name | |
230 | { | |
231 | const char * name; | |
232 | const struct asm_shift_properties * properties; | |
233 | }; | |
234 | ||
235 | static const struct asm_shift_name shift_names [] = | |
236 | { | |
237 | { "asl", shift_properties + SHIFT_LSL }, | |
238 | { "lsl", shift_properties + SHIFT_LSL }, | |
239 | { "lsr", shift_properties + SHIFT_LSR }, | |
240 | { "asr", shift_properties + SHIFT_ASR }, | |
241 | { "ror", shift_properties + SHIFT_ROR }, | |
242 | { "rrx", shift_properties + SHIFT_RRX }, | |
243 | { "ASL", shift_properties + SHIFT_LSL }, | |
244 | { "LSL", shift_properties + SHIFT_LSL }, | |
245 | { "LSR", shift_properties + SHIFT_LSR }, | |
246 | { "ASR", shift_properties + SHIFT_ASR }, | |
247 | { "ROR", shift_properties + SHIFT_ROR }, | |
248 | { "RRX", shift_properties + SHIFT_RRX } | |
249 | }; | |
250 | ||
251 | #define NO_SHIFT_RESTRICT 1 | |
252 | #define SHIFT_RESTRICT 0 | |
253 | ||
254 | #define NUM_FLOAT_VALS 8 | |
255 | ||
05d2d07e | 256 | const char * fp_const[] = |
b99bd4ef NC |
257 | { |
258 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
259 | }; | |
260 | ||
261 | /* Number of littlenums required to hold an extended precision number. */ | |
262 | #define MAX_LITTLENUMS 6 | |
263 | ||
264 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
265 | ||
266 | #define FAIL (-1) | |
267 | #define SUCCESS (0) | |
268 | ||
269 | #define SUFF_S 1 | |
270 | #define SUFF_D 2 | |
271 | #define SUFF_E 3 | |
272 | #define SUFF_P 4 | |
273 | ||
274 | #define CP_T_X 0x00008000 | |
275 | #define CP_T_Y 0x00400000 | |
276 | #define CP_T_Pre 0x01000000 | |
277 | #define CP_T_UD 0x00800000 | |
278 | #define CP_T_WB 0x00200000 | |
279 | ||
280 | #define CONDS_BIT 0x00100000 | |
281 | #define LOAD_BIT 0x00100000 | |
282 | #define TRANS_BIT 0x00200000 | |
283 | ||
284 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
285 | ||
286 | struct asm_cond | |
287 | { | |
05d2d07e | 288 | const char * template; |
b99bd4ef NC |
289 | unsigned long value; |
290 | }; | |
291 | ||
292 | /* This is to save a hash look-up in the common case. */ | |
293 | #define COND_ALWAYS 0xe0000000 | |
294 | ||
05d2d07e | 295 | static const struct asm_cond conds[] = |
b99bd4ef NC |
296 | { |
297 | {"eq", 0x00000000}, | |
298 | {"ne", 0x10000000}, | |
299 | {"cs", 0x20000000}, {"hs", 0x20000000}, | |
300 | {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000}, | |
301 | {"mi", 0x40000000}, | |
302 | {"pl", 0x50000000}, | |
303 | {"vs", 0x60000000}, | |
304 | {"vc", 0x70000000}, | |
305 | {"hi", 0x80000000}, | |
306 | {"ls", 0x90000000}, | |
307 | {"ge", 0xa0000000}, | |
308 | {"lt", 0xb0000000}, | |
309 | {"gt", 0xc0000000}, | |
310 | {"le", 0xd0000000}, | |
311 | {"al", 0xe0000000}, | |
312 | {"nv", 0xf0000000} | |
313 | }; | |
314 | ||
315 | /* Warning: If the top bit of the set_bits is set, then the standard | |
316 | instruction bitmask is ignored, and the new bitmask is taken from | |
317 | the set_bits: */ | |
318 | struct asm_flg | |
319 | { | |
05d2d07e | 320 | const char * template; /* Basic flag string. */ |
b99bd4ef NC |
321 | unsigned long set_bits; /* Bits to set. */ |
322 | }; | |
323 | ||
05d2d07e | 324 | static const struct asm_flg s_flag[] = |
b99bd4ef NC |
325 | { |
326 | {"s", CONDS_BIT}, | |
327 | {NULL, 0} | |
328 | }; | |
329 | ||
05d2d07e | 330 | static const struct asm_flg ldr_flags[] = |
b99bd4ef NC |
331 | { |
332 | {"d", DOUBLE_LOAD_FLAG}, | |
333 | {"b", 0x00400000}, | |
334 | {"t", TRANS_BIT}, | |
335 | {"bt", 0x00400000 | TRANS_BIT}, | |
336 | {"h", 0x801000b0}, | |
337 | {"sh", 0x801000f0}, | |
338 | {"sb", 0x801000d0}, | |
339 | {NULL, 0} | |
340 | }; | |
341 | ||
05d2d07e | 342 | static const struct asm_flg str_flags[] = |
b99bd4ef NC |
343 | { |
344 | {"d", DOUBLE_LOAD_FLAG}, | |
345 | {"b", 0x00400000}, | |
346 | {"t", TRANS_BIT}, | |
347 | {"bt", 0x00400000 | TRANS_BIT}, | |
348 | {"h", 0x800000b0}, | |
349 | {NULL, 0} | |
350 | }; | |
351 | ||
05d2d07e | 352 | static const struct asm_flg byte_flag[] = |
b99bd4ef NC |
353 | { |
354 | {"b", 0x00400000}, | |
355 | {NULL, 0} | |
356 | }; | |
357 | ||
05d2d07e | 358 | static const struct asm_flg cmp_flags[] = |
b99bd4ef NC |
359 | { |
360 | {"s", CONDS_BIT}, | |
361 | {"p", 0x0010f000}, | |
362 | {NULL, 0} | |
363 | }; | |
364 | ||
05d2d07e | 365 | static const struct asm_flg ldm_flags[] = |
b99bd4ef NC |
366 | { |
367 | {"ed", 0x01800000}, | |
368 | {"fd", 0x00800000}, | |
369 | {"ea", 0x01000000}, | |
370 | {"fa", 0x00000000}, | |
371 | {"ib", 0x01800000}, | |
372 | {"ia", 0x00800000}, | |
373 | {"db", 0x01000000}, | |
374 | {"da", 0x00000000}, | |
375 | {NULL, 0} | |
376 | }; | |
377 | ||
05d2d07e | 378 | static const struct asm_flg stm_flags[] = |
b99bd4ef NC |
379 | { |
380 | {"ed", 0x00000000}, | |
381 | {"fd", 0x01000000}, | |
382 | {"ea", 0x00800000}, | |
383 | {"fa", 0x01800000}, | |
384 | {"ib", 0x01800000}, | |
385 | {"ia", 0x00800000}, | |
386 | {"db", 0x01000000}, | |
387 | {"da", 0x00000000}, | |
388 | {NULL, 0} | |
389 | }; | |
390 | ||
05d2d07e | 391 | static const struct asm_flg lfm_flags[] = |
b99bd4ef NC |
392 | { |
393 | {"fd", 0x00800000}, | |
394 | {"ea", 0x01000000}, | |
395 | {NULL, 0} | |
396 | }; | |
397 | ||
05d2d07e | 398 | static const struct asm_flg sfm_flags[] = |
b99bd4ef NC |
399 | { |
400 | {"fd", 0x01000000}, | |
401 | {"ea", 0x00800000}, | |
402 | {NULL, 0} | |
403 | }; | |
404 | ||
05d2d07e | 405 | static const struct asm_flg round_flags[] = |
b99bd4ef NC |
406 | { |
407 | {"p", 0x00000020}, | |
408 | {"m", 0x00000040}, | |
409 | {"z", 0x00000060}, | |
410 | {NULL, 0} | |
411 | }; | |
412 | ||
413 | /* The implementation of the FIX instruction is broken on some assemblers, | |
414 | in that it accepts a precision specifier as well as a rounding specifier, | |
415 | despite the fact that this is meaningless. To be more compatible, we | |
416 | accept it as well, though of course it does not set any bits. */ | |
05d2d07e | 417 | static const struct asm_flg fix_flags[] = |
b99bd4ef NC |
418 | { |
419 | {"p", 0x00000020}, | |
420 | {"m", 0x00000040}, | |
421 | {"z", 0x00000060}, | |
422 | {"sp", 0x00000020}, | |
423 | {"sm", 0x00000040}, | |
424 | {"sz", 0x00000060}, | |
425 | {"dp", 0x00000020}, | |
426 | {"dm", 0x00000040}, | |
427 | {"dz", 0x00000060}, | |
428 | {"ep", 0x00000020}, | |
429 | {"em", 0x00000040}, | |
430 | {"ez", 0x00000060}, | |
431 | {NULL, 0} | |
432 | }; | |
433 | ||
05d2d07e | 434 | static const struct asm_flg except_flag[] = |
b99bd4ef NC |
435 | { |
436 | {"e", 0x00400000}, | |
437 | {NULL, 0} | |
438 | }; | |
439 | ||
05d2d07e | 440 | static const struct asm_flg long_flag[] = |
b99bd4ef NC |
441 | { |
442 | {"l", 0x00400000}, | |
443 | {NULL, 0} | |
444 | }; | |
445 | ||
446 | struct asm_psr | |
447 | { | |
05d2d07e | 448 | const char * template; |
b99bd4ef NC |
449 | boolean cpsr; |
450 | unsigned long field; | |
451 | }; | |
452 | ||
453 | /* The bit that distnguishes CPSR and SPSR. */ | |
454 | #define SPSR_BIT (1 << 22) | |
455 | ||
456 | /* How many bits to shift the PSR_xxx bits up by. */ | |
457 | #define PSR_SHIFT 16 | |
458 | ||
459 | #define PSR_c (1 << 0) | |
460 | #define PSR_x (1 << 1) | |
461 | #define PSR_s (1 << 2) | |
462 | #define PSR_f (1 << 3) | |
463 | ||
05d2d07e | 464 | static const struct asm_psr psrs[] = |
b99bd4ef NC |
465 | { |
466 | {"CPSR", true, PSR_c | PSR_f}, | |
467 | {"CPSR_all", true, PSR_c | PSR_f}, | |
468 | {"SPSR", false, PSR_c | PSR_f}, | |
469 | {"SPSR_all", false, PSR_c | PSR_f}, | |
470 | {"CPSR_flg", true, PSR_f}, | |
471 | {"CPSR_f", true, PSR_f}, | |
472 | {"SPSR_flg", false, PSR_f}, | |
473 | {"SPSR_f", false, PSR_f}, | |
474 | {"CPSR_c", true, PSR_c}, | |
475 | {"CPSR_ctl", true, PSR_c}, | |
476 | {"SPSR_c", false, PSR_c}, | |
477 | {"SPSR_ctl", false, PSR_c}, | |
478 | {"CPSR_x", true, PSR_x}, | |
479 | {"CPSR_s", true, PSR_s}, | |
480 | {"SPSR_x", false, PSR_x}, | |
481 | {"SPSR_s", false, PSR_s}, | |
482 | /* Combinations of flags. */ | |
483 | {"CPSR_fs", true, PSR_f | PSR_s}, | |
484 | {"CPSR_fx", true, PSR_f | PSR_x}, | |
485 | {"CPSR_fc", true, PSR_f | PSR_c}, | |
486 | {"CPSR_sf", true, PSR_s | PSR_f}, | |
487 | {"CPSR_sx", true, PSR_s | PSR_x}, | |
488 | {"CPSR_sc", true, PSR_s | PSR_c}, | |
489 | {"CPSR_xf", true, PSR_x | PSR_f}, | |
490 | {"CPSR_xs", true, PSR_x | PSR_s}, | |
491 | {"CPSR_xc", true, PSR_x | PSR_c}, | |
492 | {"CPSR_cf", true, PSR_c | PSR_f}, | |
493 | {"CPSR_cs", true, PSR_c | PSR_s}, | |
494 | {"CPSR_cx", true, PSR_c | PSR_x}, | |
495 | {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x}, | |
496 | {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c}, | |
497 | {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s}, | |
498 | {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c}, | |
499 | {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s}, | |
500 | {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x}, | |
501 | {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x}, | |
502 | {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c}, | |
503 | {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f}, | |
504 | {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c}, | |
505 | {"CPSR_scf", true, PSR_s | PSR_c | PSR_f}, | |
506 | {"CPSR_scx", true, PSR_s | PSR_c | PSR_x}, | |
507 | {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s}, | |
508 | {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c}, | |
509 | {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f}, | |
510 | {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c}, | |
511 | {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f}, | |
512 | {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s}, | |
513 | {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s}, | |
514 | {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x}, | |
515 | {"CPSR_csf", true, PSR_c | PSR_s | PSR_f}, | |
516 | {"CPSR_csx", true, PSR_c | PSR_s | PSR_x}, | |
517 | {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f}, | |
518 | {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s}, | |
519 | {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c}, | |
520 | {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x}, | |
521 | {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c}, | |
522 | {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s}, | |
523 | {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x}, | |
524 | {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s}, | |
525 | {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c}, | |
526 | {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x}, | |
527 | {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c}, | |
528 | {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f}, | |
529 | {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x}, | |
530 | {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f}, | |
531 | {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c}, | |
532 | {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s}, | |
533 | {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c}, | |
534 | {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f}, | |
535 | {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s}, | |
536 | {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f}, | |
537 | {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x}, | |
538 | {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s}, | |
539 | {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x}, | |
540 | {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f}, | |
541 | {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s}, | |
542 | {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f}, | |
543 | {"SPSR_fs", false, PSR_f | PSR_s}, | |
544 | {"SPSR_fx", false, PSR_f | PSR_x}, | |
545 | {"SPSR_fc", false, PSR_f | PSR_c}, | |
546 | {"SPSR_sf", false, PSR_s | PSR_f}, | |
547 | {"SPSR_sx", false, PSR_s | PSR_x}, | |
548 | {"SPSR_sc", false, PSR_s | PSR_c}, | |
549 | {"SPSR_xf", false, PSR_x | PSR_f}, | |
550 | {"SPSR_xs", false, PSR_x | PSR_s}, | |
551 | {"SPSR_xc", false, PSR_x | PSR_c}, | |
552 | {"SPSR_cf", false, PSR_c | PSR_f}, | |
553 | {"SPSR_cs", false, PSR_c | PSR_s}, | |
554 | {"SPSR_cx", false, PSR_c | PSR_x}, | |
555 | {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x}, | |
556 | {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c}, | |
557 | {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s}, | |
558 | {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c}, | |
559 | {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s}, | |
560 | {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x}, | |
561 | {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x}, | |
562 | {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c}, | |
563 | {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f}, | |
564 | {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c}, | |
565 | {"SPSR_scf", false, PSR_s | PSR_c | PSR_f}, | |
566 | {"SPSR_scx", false, PSR_s | PSR_c | PSR_x}, | |
567 | {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s}, | |
568 | {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c}, | |
569 | {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f}, | |
570 | {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c}, | |
571 | {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f}, | |
572 | {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s}, | |
573 | {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s}, | |
574 | {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x}, | |
575 | {"SPSR_csf", false, PSR_c | PSR_s | PSR_f}, | |
576 | {"SPSR_csx", false, PSR_c | PSR_s | PSR_x}, | |
577 | {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f}, | |
578 | {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s}, | |
579 | {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c}, | |
580 | {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x}, | |
581 | {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c}, | |
582 | {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s}, | |
583 | {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x}, | |
584 | {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s}, | |
585 | {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c}, | |
586 | {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x}, | |
587 | {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c}, | |
588 | {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f}, | |
589 | {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x}, | |
590 | {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f}, | |
591 | {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c}, | |
592 | {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s}, | |
593 | {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c}, | |
594 | {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f}, | |
595 | {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s}, | |
596 | {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f}, | |
597 | {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x}, | |
598 | {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s}, | |
599 | {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x}, | |
600 | {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f}, | |
601 | {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s}, | |
602 | {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f}, | |
603 | }; | |
604 | ||
404ff6b5 AH |
605 | enum cirrus_regtype |
606 | { | |
607 | CIRRUS_REGTYPE_MVF = 1, | |
608 | CIRRUS_REGTYPE_MVFX = 2, | |
609 | CIRRUS_REGTYPE_MVD = 3, | |
610 | CIRRUS_REGTYPE_MVDX = 4, | |
611 | CIRRUS_REGTYPE_MVAX = 5, | |
612 | CIRRUS_REGTYPE_DSPSC = 6, | |
613 | CIRRUS_REGTYPE_ANY = 7 | |
614 | }; | |
615 | ||
b99bd4ef NC |
616 | /* Functions called by parser. */ |
617 | /* ARM instructions. */ | |
618 | static void do_arit PARAMS ((char *, unsigned long)); | |
619 | static void do_cmp PARAMS ((char *, unsigned long)); | |
620 | static void do_mov PARAMS ((char *, unsigned long)); | |
621 | static void do_ldst PARAMS ((char *, unsigned long)); | |
622 | static void do_ldmstm PARAMS ((char *, unsigned long)); | |
623 | static void do_branch PARAMS ((char *, unsigned long)); | |
624 | static void do_swi PARAMS ((char *, unsigned long)); | |
c9b604bd | 625 | |
b99bd4ef NC |
626 | /* Pseudo Op codes. */ |
627 | static void do_adr PARAMS ((char *, unsigned long)); | |
b99bd4ef | 628 | static void do_nop PARAMS ((char *, unsigned long)); |
c9b604bd RE |
629 | |
630 | /* ARM v2. */ | |
b99bd4ef NC |
631 | static void do_mul PARAMS ((char *, unsigned long)); |
632 | static void do_mla PARAMS ((char *, unsigned long)); | |
c9b604bd RE |
633 | |
634 | /* ARM v2S. */ | |
b99bd4ef | 635 | static void do_swap PARAMS ((char *, unsigned long)); |
c9b604bd RE |
636 | |
637 | /* ARM v3. */ | |
b99bd4ef NC |
638 | static void do_msr PARAMS ((char *, unsigned long)); |
639 | static void do_mrs PARAMS ((char *, unsigned long)); | |
c9b604bd RE |
640 | |
641 | /* ARM v3M. */ | |
b99bd4ef | 642 | static void do_mull PARAMS ((char *, unsigned long)); |
b99bd4ef | 643 | |
c9b604bd RE |
644 | /* ARM v4T. */ |
645 | static void do_bx PARAMS ((char *, unsigned long)); | |
b99bd4ef | 646 | |
c9b604bd | 647 | /* ARM_v5. */ |
b99bd4ef NC |
648 | static void do_blx PARAMS ((char *, unsigned long)); |
649 | static void do_bkpt PARAMS ((char *, unsigned long)); | |
650 | static void do_clz PARAMS ((char *, unsigned long)); | |
651 | static void do_lstc2 PARAMS ((char *, unsigned long)); | |
652 | static void do_cdp2 PARAMS ((char *, unsigned long)); | |
653 | static void do_co_reg2 PARAMS ((char *, unsigned long)); | |
654 | ||
c9b604bd | 655 | /* ARM v5ExP. */ |
b99bd4ef NC |
656 | static void do_smla PARAMS ((char *, unsigned long)); |
657 | static void do_smlal PARAMS ((char *, unsigned long)); | |
658 | static void do_smul PARAMS ((char *, unsigned long)); | |
659 | static void do_qadd PARAMS ((char *, unsigned long)); | |
c9b604bd RE |
660 | |
661 | /* ARM v5E. */ | |
662 | static void do_pld PARAMS ((char *, unsigned long)); | |
663 | static void do_ldrd PARAMS ((char *, unsigned long)); | |
b99bd4ef NC |
664 | static void do_co_reg2c PARAMS ((char *, unsigned long)); |
665 | ||
666 | /* Coprocessor Instructions. */ | |
667 | static void do_cdp PARAMS ((char *, unsigned long)); | |
668 | static void do_lstc PARAMS ((char *, unsigned long)); | |
669 | static void do_co_reg PARAMS ((char *, unsigned long)); | |
c9b604bd RE |
670 | |
671 | /* FPA instructions. */ | |
672 | static void do_fpa_ctrl PARAMS ((char *, unsigned long)); | |
673 | static void do_fpa_ldst PARAMS ((char *, unsigned long)); | |
674 | static void do_fpa_ldmstm PARAMS ((char *, unsigned long)); | |
675 | static void do_fpa_dyadic PARAMS ((char *, unsigned long)); | |
676 | static void do_fpa_monadic PARAMS ((char *, unsigned long)); | |
677 | static void do_fpa_cmp PARAMS ((char *, unsigned long)); | |
678 | static void do_fpa_from_reg PARAMS ((char *, unsigned long)); | |
679 | static void do_fpa_to_reg PARAMS ((char *, unsigned long)); | |
680 | ||
681 | /* XScale. */ | |
682 | static void do_mia PARAMS ((char *, unsigned long)); | |
683 | static void do_mar PARAMS ((char *, unsigned long)); | |
684 | static void do_mra PARAMS ((char *, unsigned long)); | |
b99bd4ef | 685 | |
90f9b791 | 686 | /* ARM_EXT_MAVERICK. */ |
404ff6b5 AH |
687 | static void do_c_binops PARAMS ((char *, unsigned long, int)); |
688 | static void do_c_binops_1 PARAMS ((char *, unsigned long)); | |
689 | static void do_c_binops_2 PARAMS ((char *, unsigned long)); | |
690 | static void do_c_binops_3 PARAMS ((char *, unsigned long)); | |
691 | static void do_c_triple PARAMS ((char *, unsigned long, int)); | |
692 | static void do_c_triple_4 PARAMS ((char *, unsigned long)); | |
693 | static void do_c_triple_5 PARAMS ((char *, unsigned long)); | |
694 | static void do_c_quad PARAMS ((char *, unsigned long, int)); | |
695 | static void do_c_quad_6 PARAMS ((char *, unsigned long)); | |
696 | static void do_c_dspsc PARAMS ((char *, unsigned long, int)); | |
697 | static void do_c_dspsc_1 PARAMS ((char *, unsigned long)); | |
698 | static void do_c_dspsc_2 PARAMS ((char *, unsigned long)); | |
699 | static void do_c_shift PARAMS ((char *, unsigned long, int)); | |
700 | static void do_c_shift_1 PARAMS ((char *, unsigned long)); | |
701 | static void do_c_shift_2 PARAMS ((char *, unsigned long)); | |
702 | static void do_c_ldst PARAMS ((char *, unsigned long, int)); | |
703 | static void do_c_ldst_1 PARAMS ((char *, unsigned long)); | |
704 | static void do_c_ldst_2 PARAMS ((char *, unsigned long)); | |
705 | static void do_c_ldst_3 PARAMS ((char *, unsigned long)); | |
706 | static void do_c_ldst_4 PARAMS ((char *, unsigned long)); | |
707 | static int cirrus_reg_required_here PARAMS ((char **, int, enum cirrus_regtype)); | |
708 | static int cirrus_valid_reg PARAMS ((int, enum cirrus_regtype)); | |
709 | static int cirrus_parse_offset PARAMS ((char **, int *)); | |
710 | ||
b99bd4ef NC |
711 | static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int)); |
712 | static int arm_reg_parse PARAMS ((char **)); | |
05d2d07e NC |
713 | static const struct asm_psr * arm_psr_parse PARAMS ((char **)); |
714 | static void symbol_locate PARAMS ((symbolS *, const char *, segT, valueT, fragS *)); | |
b99bd4ef NC |
715 | static int add_to_lit_pool PARAMS ((void)); |
716 | static unsigned validate_immediate PARAMS ((unsigned)); | |
717 | static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *)); | |
718 | static int validate_offset_imm PARAMS ((unsigned int, int)); | |
719 | static void opcode_select PARAMS ((int)); | |
720 | static void end_of_line PARAMS ((char *)); | |
721 | static int reg_required_here PARAMS ((char **, int)); | |
722 | static int psr_required_here PARAMS ((char **)); | |
723 | static int co_proc_number PARAMS ((char **)); | |
724 | static int cp_opc_expr PARAMS ((char **, int, int)); | |
725 | static int cp_reg_required_here PARAMS ((char **, int)); | |
726 | static int fp_reg_required_here PARAMS ((char **, int)); | |
727 | static int cp_address_offset PARAMS ((char **)); | |
728 | static int cp_address_required_here PARAMS ((char **)); | |
729 | static int my_get_float_expression PARAMS ((char **)); | |
730 | static int skip_past_comma PARAMS ((char **)); | |
731 | static int walk_no_bignums PARAMS ((symbolS *)); | |
732 | static int negate_data_op PARAMS ((unsigned long *, unsigned long)); | |
733 | static int data_op2 PARAMS ((char **)); | |
734 | static int fp_op2 PARAMS ((char **)); | |
735 | static long reg_list PARAMS ((char **)); | |
736 | static void thumb_load_store PARAMS ((char *, int, int)); | |
737 | static int decode_shift PARAMS ((char **, int)); | |
738 | static int ldst_extend PARAMS ((char **, int)); | |
739 | static void thumb_add_sub PARAMS ((char *, int)); | |
740 | static void insert_reg PARAMS ((int)); | |
741 | static void thumb_shift PARAMS ((char *, int)); | |
742 | static void thumb_mov_compare PARAMS ((char *, int)); | |
743 | static void set_constant_flonums PARAMS ((void)); | |
744 | static valueT md_chars_to_number PARAMS ((char *, int)); | |
745 | static void insert_reg_alias PARAMS ((char *, int)); | |
746 | static void output_inst PARAMS ((void)); | |
2c20dfb2 NC |
747 | static int accum0_required_here PARAMS ((char **)); |
748 | static int ld_mode_required_here PARAMS ((char **)); | |
749 | static void do_branch25 PARAMS ((char *, unsigned long)); | |
750 | static symbolS * find_real_start PARAMS ((symbolS *)); | |
b99bd4ef NC |
751 | #ifdef OBJ_ELF |
752 | static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void)); | |
753 | #endif | |
754 | ||
755 | /* ARM instructions take 4bytes in the object file, Thumb instructions | |
756 | take 2: */ | |
757 | #define INSN_SIZE 4 | |
758 | ||
759 | /* LONGEST_INST is the longest basic instruction name without | |
760 | conditions or flags. ARM7M has 4 of length 5. El Segundo | |
761 | has one basic instruction name of length 7 (SMLALxy). */ | |
404ff6b5 AH |
762 | #define LONGEST_INST 10 |
763 | ||
764 | /* "INSN<cond> X,Y" where X:bit12, Y:bit16. */ | |
765 | #define CIRRUS_MODE1 0x100c | |
766 | ||
767 | /* "INSN<cond> X,Y" where X:bit16, Y:bit12. */ | |
768 | #define CIRRUS_MODE2 0x0c10 | |
769 | ||
770 | /* "INSN<cond> X,Y" where X:0, Y:bit16. */ | |
771 | #define CIRRUS_MODE3 0x1000 | |
772 | ||
773 | /* "INSN<cond> X,Y,Z" where X:16, Y:0, Z:12. */ | |
774 | #define CIRRUS_MODE4 0x0c0010 | |
775 | ||
776 | /* "INSN<cond> X,Y,Z" where X:12, Y:16, Z:0. */ | |
777 | #define CIRRUS_MODE5 0x00100c | |
778 | ||
779 | /* "INSN<cond> W,X,Y,Z" where W:5, X:12, Y:16, Z:0. */ | |
780 | #define CIRRUS_MODE6 0x00100c05 | |
b99bd4ef NC |
781 | |
782 | struct asm_opcode | |
783 | { | |
784 | /* Basic string to match. */ | |
05d2d07e | 785 | const char * template; |
b99bd4ef NC |
786 | |
787 | /* Basic instruction code. */ | |
788 | unsigned long value; | |
789 | ||
790 | /* Compulsory suffix that must follow conds. If "", then the | |
791 | instruction is not conditional and must have no suffix. */ | |
05d2d07e | 792 | const char * comp_suffix; |
b99bd4ef NC |
793 | |
794 | /* Bits to toggle if flag 'n' set. */ | |
05d2d07e | 795 | const struct asm_flg * flags; |
b99bd4ef NC |
796 | |
797 | /* Which CPU variants this exists for. */ | |
798 | unsigned long variants; | |
799 | ||
800 | /* Function to call to parse args. */ | |
801 | void (* parms) PARAMS ((char *, unsigned long)); | |
802 | }; | |
803 | ||
05d2d07e | 804 | static const struct asm_opcode insns[] = |
b99bd4ef | 805 | { |
c9b604bd | 806 | /* XXX Temporary hack. Override the normal load/store entry points. */ |
b89dddec RE |
807 | {"ldr", 0x000000d0, NULL, ldr_flags, ARM_EXT_V1, do_ldrd}, |
808 | {"str", 0x000000f0, NULL, str_flags, ARM_EXT_V1, do_ldrd}, | |
b99bd4ef | 809 | |
c9b604bd | 810 | /* Core ARM Instructions. */ |
b89dddec RE |
811 | {"and", 0x00000000, NULL, s_flag, ARM_EXT_V1, do_arit}, |
812 | {"eor", 0x00200000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
813 | {"sub", 0x00400000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
814 | {"rsb", 0x00600000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
815 | {"add", 0x00800000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
816 | {"adc", 0x00a00000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
817 | {"sbc", 0x00c00000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
818 | {"rsc", 0x00e00000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
819 | {"orr", 0x01800000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
820 | {"bic", 0x01c00000, NULL, s_flag, ARM_EXT_V1, do_arit}, | |
821 | {"tst", 0x01000000, NULL, cmp_flags, ARM_EXT_V1, do_cmp}, | |
822 | {"teq", 0x01200000, NULL, cmp_flags, ARM_EXT_V1, do_cmp}, | |
823 | {"cmp", 0x01400000, NULL, cmp_flags, ARM_EXT_V1, do_cmp}, | |
824 | {"cmn", 0x01600000, NULL, cmp_flags, ARM_EXT_V1, do_cmp}, | |
825 | {"mov", 0x01a00000, NULL, s_flag, ARM_EXT_V1, do_mov}, | |
826 | {"mvn", 0x01e00000, NULL, s_flag, ARM_EXT_V1, do_mov}, | |
827 | {"str", 0x04000000, NULL, str_flags, ARM_EXT_V1, do_ldst}, | |
828 | {"ldr", 0x04100000, NULL, ldr_flags, ARM_EXT_V1, do_ldst}, | |
829 | {"stm", 0x08000000, NULL, stm_flags, ARM_EXT_V1, do_ldmstm}, | |
830 | {"ldm", 0x08100000, NULL, ldm_flags, ARM_EXT_V1, do_ldmstm}, | |
831 | {"swi", 0x0f000000, NULL, NULL, ARM_EXT_V1, do_swi}, | |
b99bd4ef | 832 | #ifdef TE_WINCE |
c9b604bd | 833 | /* XXX This is the wrong place to do this. Think multi-arch. */ |
b89dddec RE |
834 | {"bl", 0x0b000000, NULL, NULL, ARM_EXT_V1, do_branch}, |
835 | {"b", 0x0a000000, NULL, NULL, ARM_EXT_V1, do_branch}, | |
b99bd4ef | 836 | #else |
b89dddec RE |
837 | {"bl", 0x0bfffffe, NULL, NULL, ARM_EXT_V1, do_branch}, |
838 | {"b", 0x0afffffe, NULL, NULL, ARM_EXT_V1, do_branch}, | |
b99bd4ef NC |
839 | #endif |
840 | ||
c9b604bd | 841 | /* Pseudo ops. */ |
b89dddec RE |
842 | {"adr", 0x028f0000, NULL, long_flag, ARM_EXT_V1, do_adr}, |
843 | {"nop", 0x01a00000, NULL, NULL, ARM_EXT_V1, do_nop}, | |
b99bd4ef | 844 | |
c9b604bd | 845 | /* ARM 2 multiplies. */ |
b89dddec RE |
846 | {"mul", 0x00000090, NULL, s_flag, ARM_EXT_V2, do_mul}, |
847 | {"mla", 0x00200090, NULL, s_flag, ARM_EXT_V2, do_mla}, | |
b99bd4ef | 848 | |
c9b604bd RE |
849 | /* Generic copressor instructions. */ |
850 | {"cdp", 0x0e000000, NULL, NULL, ARM_EXT_V2, do_cdp}, | |
851 | {"ldc", 0x0c100000, NULL, long_flag, ARM_EXT_V2, do_lstc}, | |
852 | {"stc", 0x0c000000, NULL, long_flag, ARM_EXT_V2, do_lstc}, | |
853 | {"mcr", 0x0e000010, NULL, NULL, ARM_EXT_V2, do_co_reg}, | |
854 | {"mrc", 0x0e100010, NULL, NULL, ARM_EXT_V2, do_co_reg}, | |
855 | ||
856 | /* ARM 3 - swp instructions. */ | |
b89dddec | 857 | {"swp", 0x01000090, NULL, byte_flag, ARM_EXT_V2S, do_swap}, |
b99bd4ef | 858 | |
c9b604bd | 859 | /* ARM 6 Status register instructions. */ |
b89dddec RE |
860 | {"mrs", 0x010f0000, NULL, NULL, ARM_EXT_V3, do_mrs}, |
861 | {"msr", 0x0120f000, NULL, NULL, ARM_EXT_V3, do_msr}, | |
c9b604bd RE |
862 | /* ScottB: our code uses 0x0128f000 for msr. |
863 | NickC: but this is wrong because the bits 16 through 19 are | |
864 | handled by the PSR_xxx defines above. */ | |
b99bd4ef | 865 | |
c9b604bd | 866 | /* ARM 7M long multiplies - need signed/unsigned flags! */ |
b89dddec RE |
867 | {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_V3M, do_mull}, |
868 | {"umull", 0x00800090, NULL, s_flag, ARM_EXT_V3M, do_mull}, | |
869 | {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_V3M, do_mull}, | |
870 | {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_V3M, do_mull}, | |
b99bd4ef | 871 | |
c9b604bd | 872 | /* ARM Architecture 4T. */ |
b89dddec RE |
873 | /* Note: bx (and blx) are required on V5, even if the processor does |
874 | not support Thumb. */ | |
875 | {"bx", 0x012fff10, NULL, NULL, ARM_EXT_V4T | ARM_EXT_V5, do_bx}, | |
b99bd4ef | 876 | |
c9b604bd RE |
877 | /* ARM ISA extension 5. */ |
878 | /* Note: blx is actually 2 opcodes, so the .value is set dynamically. | |
879 | And it's sometimes conditional and sometimes not. */ | |
b99bd4ef NC |
880 | {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx}, |
881 | {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz}, | |
882 | {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt}, | |
1cac9012 NC |
883 | {"ldc2", 0xfc100000, "", long_flag, ARM_EXT_V5, do_lstc2}, |
884 | {"stc2", 0xfc000000, "", long_flag, ARM_EXT_V5, do_lstc2}, | |
b99bd4ef NC |
885 | {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2}, |
886 | {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2}, | |
887 | {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2}, | |
888 | ||
c9b604bd RE |
889 | /* ARM Architecture 5ExP. */ |
890 | {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5ExP, do_smla}, | |
891 | {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5ExP, do_smla}, | |
892 | {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5ExP, do_smla}, | |
893 | {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5ExP, do_smla}, | |
894 | ||
895 | {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5ExP, do_smla}, | |
896 | {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5ExP, do_smla}, | |
897 | ||
898 | {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5ExP, do_smlal}, | |
899 | {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5ExP, do_smlal}, | |
900 | {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5ExP, do_smlal}, | |
901 | {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5ExP, do_smlal}, | |
902 | ||
903 | {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5ExP, do_smul}, | |
904 | {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5ExP, do_smul}, | |
905 | {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5ExP, do_smul}, | |
906 | {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5ExP, do_smul}, | |
907 | ||
908 | {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5ExP, do_smul}, | |
909 | {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5ExP, do_smul}, | |
910 | ||
911 | {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5ExP, do_qadd}, | |
912 | {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5ExP, do_qadd}, | |
913 | {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5ExP, do_qadd}, | |
914 | {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5ExP, do_qadd}, | |
915 | ||
916 | /* ARM Architecture 5E. */ | |
917 | {"pld", 0xf450f000, "", NULL, ARM_EXT_V5E, do_pld}, | |
918 | {"ldr", 0x000000d0, NULL, ldr_flags, ARM_EXT_V5E, do_ldrd}, | |
919 | {"str", 0x000000f0, NULL, str_flags, ARM_EXT_V5E, do_ldrd}, | |
b99bd4ef NC |
920 | {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c}, |
921 | {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c}, | |
404ff6b5 | 922 | |
c9b604bd RE |
923 | /* Core FPA instruction set (V1). */ |
924 | {"wfs", 0x0e200110, NULL, NULL, FPU_FPA_EXT_V1, do_fpa_ctrl}, | |
925 | {"rfs", 0x0e300110, NULL, NULL, FPU_FPA_EXT_V1, do_fpa_ctrl}, | |
926 | {"wfc", 0x0e400110, NULL, NULL, FPU_FPA_EXT_V1, do_fpa_ctrl}, | |
927 | {"rfc", 0x0e500110, NULL, NULL, FPU_FPA_EXT_V1, do_fpa_ctrl}, | |
928 | {"ldf", 0x0c100100, "sdep", NULL, FPU_FPA_EXT_V1, do_fpa_ldst}, | |
929 | {"stf", 0x0c000100, "sdep", NULL, FPU_FPA_EXT_V1, do_fpa_ldst}, | |
930 | {"mvf", 0x0e008100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
931 | {"mnf", 0x0e108100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
932 | {"abs", 0x0e208100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
933 | {"rnd", 0x0e308100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
934 | {"sqt", 0x0e408100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
935 | {"log", 0x0e508100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
936 | {"lgn", 0x0e608100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
937 | {"exp", 0x0e708100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
938 | {"sin", 0x0e808100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
939 | {"cos", 0x0e908100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
940 | {"tan", 0x0ea08100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
941 | {"asn", 0x0eb08100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
942 | {"acs", 0x0ec08100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
943 | {"atn", 0x0ed08100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
944 | {"urd", 0x0ee08100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
945 | {"nrm", 0x0ef08100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_monadic}, | |
946 | {"adf", 0x0e000100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
947 | {"suf", 0x0e200100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
948 | {"rsf", 0x0e300100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
949 | {"muf", 0x0e100100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
950 | {"dvf", 0x0e400100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
951 | {"rdf", 0x0e500100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
952 | {"pow", 0x0e600100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
953 | {"rpw", 0x0e700100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
954 | {"rmf", 0x0e800100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
955 | {"fml", 0x0e900100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
956 | {"fdv", 0x0ea00100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
957 | {"frd", 0x0eb00100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
958 | {"pol", 0x0ec00100, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_dyadic}, | |
959 | {"cmf", 0x0e90f110, NULL, except_flag, FPU_FPA_EXT_V1, do_fpa_cmp}, | |
960 | {"cnf", 0x0eb0f110, NULL, except_flag, FPU_FPA_EXT_V1, do_fpa_cmp}, | |
961 | /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not | |
962 | be an optional suffix, but part of the instruction. To be compatible, | |
963 | we accept either. */ | |
964 | {"cmfe", 0x0ed0f110, NULL, NULL, FPU_FPA_EXT_V1, do_fpa_cmp}, | |
965 | {"cnfe", 0x0ef0f110, NULL, NULL, FPU_FPA_EXT_V1, do_fpa_cmp}, | |
966 | {"flt", 0x0e000110, "sde", round_flags, FPU_FPA_EXT_V1, do_fpa_from_reg}, | |
967 | {"fix", 0x0e100110, NULL, fix_flags, FPU_FPA_EXT_V1, do_fpa_to_reg}, | |
968 | ||
969 | /* Instructions that were new with the real FPA, call them V2. */ | |
970 | {"lfm", 0x0c100200, NULL, lfm_flags, FPU_FPA_EXT_V2, do_fpa_ldmstm}, | |
971 | {"sfm", 0x0c000200, NULL, sfm_flags, FPU_FPA_EXT_V2, do_fpa_ldmstm}, | |
972 | ||
973 | /* Intel XScale extensions to ARM V5 ISA. (All use CP0). */ | |
974 | {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
975 | {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
976 | {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
977 | {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
978 | {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
979 | {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
980 | {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar}, | |
981 | {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra}, | |
982 | ||
404ff6b5 | 983 | /* Cirrus DSP instructions. */ |
90f9b791 AH |
984 | {"cfldrs", 0x0c100400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_1}, |
985 | {"cfldrd", 0x0c500400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_2}, | |
986 | {"cfldr32", 0x0c100500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_3}, | |
987 | {"cfldr64", 0x0c500500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_4}, | |
988 | {"cfstrs", 0x0c000400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_1}, | |
989 | {"cfstrd", 0x0c400400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_2}, | |
990 | {"cfstr32", 0x0c000500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_3}, | |
991 | {"cfstr64", 0x0c400500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_4}, | |
992 | {"cfmvsr", 0x0e000450, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2}, | |
993 | {"cfmvrs", 0x0e100450, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
994 | {"cfmvdlr", 0x0e000410, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2}, | |
995 | {"cfmvrdl", 0x0e100410, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
996 | {"cfmvdhr", 0x0e000430, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2}, | |
997 | {"cfmvrdh", 0x0e100430, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
998 | {"cfmv64lr", 0x0e000510, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2}, | |
999 | {"cfmvr64l", 0x0e100510, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1000 | {"cfmv64hr", 0x0e000530, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2}, | |
1001 | {"cfmvr64h", 0x0e100530, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1002 | {"cfmval32", 0x0e100610, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1003 | {"cfmv32al", 0x0e000610, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1004 | {"cfmvam32", 0x0e100630, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1005 | {"cfmv32am", 0x0e000630, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1006 | {"cfmvah32", 0x0e100650, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1007 | {"cfmv32ah", 0x0e000650, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1008 | {"cfmv32a", 0x0e000670, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1009 | {"cfmva32", 0x0e100670, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1010 | {"cfmv64a", 0x0e000690, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1011 | {"cfmva64", 0x0e100690, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3}, | |
1012 | {"cfmvsc32", 0x0e1006b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_dspsc_1}, | |
1013 | {"cfmv32sc", 0x0e0006b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_dspsc_2}, | |
1014 | {"cfcpys", 0x0e000400, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1015 | {"cfcpyd", 0x0e000420, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1016 | {"cfcvtsd", 0x0e000460, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1017 | {"cfcvtds", 0x0e000440, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1018 | {"cfcvt32s", 0x0e000480, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1019 | {"cfcvt32d", 0x0e0004a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1020 | {"cfcvt64s", 0x0e0004c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1021 | {"cfcvt64d", 0x0e0004e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1022 | {"cfcvts32", 0x0e100580, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1023 | {"cfcvtd32", 0x0e1005a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1024 | {"cftruncs32",0x0e1005c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1025 | {"cftruncd32",0x0e1005e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1026 | {"cfrshl32", 0x0e000550, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_4}, | |
1027 | {"cfrshl64", 0x0e000570, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_4}, | |
1028 | {"cfsh32", 0x0e000500, NULL, NULL, ARM_EXT_MAVERICK, do_c_shift_1}, | |
1029 | {"cfsh64", 0x0e200500, NULL, NULL, ARM_EXT_MAVERICK, do_c_shift_2}, | |
1030 | {"cfcmps", 0x0e100490, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1031 | {"cfcmpd", 0x0e1004b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1032 | {"cfcmp32", 0x0e100590, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1033 | {"cfcmp64", 0x0e1005b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1034 | {"cfabss", 0x0e300400, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1035 | {"cfabsd", 0x0e300420, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1036 | {"cfnegs", 0x0e300440, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1037 | {"cfnegd", 0x0e300460, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1038 | {"cfadds", 0x0e300480, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1039 | {"cfaddd", 0x0e3004a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1040 | {"cfsubs", 0x0e3004c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1041 | {"cfsubd", 0x0e3004e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1042 | {"cfmuls", 0x0e100400, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1043 | {"cfmuld", 0x0e100420, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1044 | {"cfabs32", 0x0e300500, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1045 | {"cfabs64", 0x0e300520, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1046 | {"cfneg32", 0x0e300540, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1047 | {"cfneg64", 0x0e300560, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1}, | |
1048 | {"cfadd32", 0x0e300580, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1049 | {"cfadd64", 0x0e3005a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1050 | {"cfsub32", 0x0e3005c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1051 | {"cfsub64", 0x0e3005e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1052 | {"cfmul32", 0x0e100500, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1053 | {"cfmul64", 0x0e100520, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1054 | {"cfmac32", 0x0e100540, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1055 | {"cfmsc32", 0x0e100560, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5}, | |
1056 | {"cfmadd32", 0x0e000600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6}, | |
1057 | {"cfmsub32", 0x0e100600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6}, | |
1058 | {"cfmadda32", 0x0e200600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6}, | |
1059 | {"cfmsuba32", 0x0e300600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6}, | |
b99bd4ef NC |
1060 | }; |
1061 | ||
1062 | /* Defines for various bits that we will want to toggle. */ | |
1063 | #define INST_IMMEDIATE 0x02000000 | |
1064 | #define OFFSET_REG 0x02000000 | |
1065 | #define HWOFFSET_IMM 0x00400000 | |
1066 | #define SHIFT_BY_REG 0x00000010 | |
1067 | #define PRE_INDEX 0x01000000 | |
1068 | #define INDEX_UP 0x00800000 | |
1069 | #define WRITE_BACK 0x00200000 | |
1070 | #define LDM_TYPE_2_OR_3 0x00400000 | |
1071 | ||
1072 | #define LITERAL_MASK 0xf000f000 | |
1073 | #define COND_MASK 0xf0000000 | |
1074 | #define OPCODE_MASK 0xfe1fffff | |
1075 | #define DATA_OP_SHIFT 21 | |
1076 | ||
1077 | /* Codes to distinguish the arithmetic instructions. */ | |
1078 | #define OPCODE_AND 0 | |
1079 | #define OPCODE_EOR 1 | |
1080 | #define OPCODE_SUB 2 | |
1081 | #define OPCODE_RSB 3 | |
1082 | #define OPCODE_ADD 4 | |
1083 | #define OPCODE_ADC 5 | |
1084 | #define OPCODE_SBC 6 | |
1085 | #define OPCODE_RSC 7 | |
1086 | #define OPCODE_TST 8 | |
1087 | #define OPCODE_TEQ 9 | |
1088 | #define OPCODE_CMP 10 | |
1089 | #define OPCODE_CMN 11 | |
1090 | #define OPCODE_ORR 12 | |
1091 | #define OPCODE_MOV 13 | |
1092 | #define OPCODE_BIC 14 | |
1093 | #define OPCODE_MVN 15 | |
1094 | ||
c9b604bd | 1095 | /* Thumb v1 (ARMv4T). */ |
b99bd4ef NC |
1096 | static void do_t_nop PARAMS ((char *)); |
1097 | static void do_t_arit PARAMS ((char *)); | |
1098 | static void do_t_add PARAMS ((char *)); | |
1099 | static void do_t_asr PARAMS ((char *)); | |
1100 | static void do_t_branch9 PARAMS ((char *)); | |
1101 | static void do_t_branch12 PARAMS ((char *)); | |
1102 | static void do_t_branch23 PARAMS ((char *)); | |
1103 | static void do_t_bx PARAMS ((char *)); | |
1104 | static void do_t_compare PARAMS ((char *)); | |
1105 | static void do_t_ldmstm PARAMS ((char *)); | |
1106 | static void do_t_ldr PARAMS ((char *)); | |
1107 | static void do_t_ldrb PARAMS ((char *)); | |
1108 | static void do_t_ldrh PARAMS ((char *)); | |
1109 | static void do_t_lds PARAMS ((char *)); | |
1110 | static void do_t_lsl PARAMS ((char *)); | |
1111 | static void do_t_lsr PARAMS ((char *)); | |
1112 | static void do_t_mov PARAMS ((char *)); | |
1113 | static void do_t_push_pop PARAMS ((char *)); | |
1114 | static void do_t_str PARAMS ((char *)); | |
1115 | static void do_t_strb PARAMS ((char *)); | |
1116 | static void do_t_strh PARAMS ((char *)); | |
1117 | static void do_t_sub PARAMS ((char *)); | |
1118 | static void do_t_swi PARAMS ((char *)); | |
1119 | static void do_t_adr PARAMS ((char *)); | |
1120 | ||
c9b604bd RE |
1121 | /* Thumb v2 (ARMv5T). */ |
1122 | static void do_t_blx PARAMS ((char *)); | |
1123 | static void do_t_bkpt PARAMS ((char *)); | |
1124 | ||
b99bd4ef NC |
1125 | #define T_OPCODE_MUL 0x4340 |
1126 | #define T_OPCODE_TST 0x4200 | |
1127 | #define T_OPCODE_CMN 0x42c0 | |
1128 | #define T_OPCODE_NEG 0x4240 | |
1129 | #define T_OPCODE_MVN 0x43c0 | |
1130 | ||
1131 | #define T_OPCODE_ADD_R3 0x1800 | |
1132 | #define T_OPCODE_SUB_R3 0x1a00 | |
1133 | #define T_OPCODE_ADD_HI 0x4400 | |
1134 | #define T_OPCODE_ADD_ST 0xb000 | |
1135 | #define T_OPCODE_SUB_ST 0xb080 | |
1136 | #define T_OPCODE_ADD_SP 0xa800 | |
1137 | #define T_OPCODE_ADD_PC 0xa000 | |
1138 | #define T_OPCODE_ADD_I8 0x3000 | |
1139 | #define T_OPCODE_SUB_I8 0x3800 | |
1140 | #define T_OPCODE_ADD_I3 0x1c00 | |
1141 | #define T_OPCODE_SUB_I3 0x1e00 | |
1142 | ||
1143 | #define T_OPCODE_ASR_R 0x4100 | |
1144 | #define T_OPCODE_LSL_R 0x4080 | |
1145 | #define T_OPCODE_LSR_R 0x40c0 | |
1146 | #define T_OPCODE_ASR_I 0x1000 | |
1147 | #define T_OPCODE_LSL_I 0x0000 | |
1148 | #define T_OPCODE_LSR_I 0x0800 | |
1149 | ||
1150 | #define T_OPCODE_MOV_I8 0x2000 | |
1151 | #define T_OPCODE_CMP_I8 0x2800 | |
1152 | #define T_OPCODE_CMP_LR 0x4280 | |
1153 | #define T_OPCODE_MOV_HR 0x4600 | |
1154 | #define T_OPCODE_CMP_HR 0x4500 | |
1155 | ||
1156 | #define T_OPCODE_LDR_PC 0x4800 | |
1157 | #define T_OPCODE_LDR_SP 0x9800 | |
1158 | #define T_OPCODE_STR_SP 0x9000 | |
1159 | #define T_OPCODE_LDR_IW 0x6800 | |
1160 | #define T_OPCODE_STR_IW 0x6000 | |
1161 | #define T_OPCODE_LDR_IH 0x8800 | |
1162 | #define T_OPCODE_STR_IH 0x8000 | |
1163 | #define T_OPCODE_LDR_IB 0x7800 | |
1164 | #define T_OPCODE_STR_IB 0x7000 | |
1165 | #define T_OPCODE_LDR_RW 0x5800 | |
1166 | #define T_OPCODE_STR_RW 0x5000 | |
1167 | #define T_OPCODE_LDR_RH 0x5a00 | |
1168 | #define T_OPCODE_STR_RH 0x5200 | |
1169 | #define T_OPCODE_LDR_RB 0x5c00 | |
1170 | #define T_OPCODE_STR_RB 0x5400 | |
1171 | ||
1172 | #define T_OPCODE_PUSH 0xb400 | |
1173 | #define T_OPCODE_POP 0xbc00 | |
1174 | ||
1175 | #define T_OPCODE_BRANCH 0xe7fe | |
1176 | ||
1177 | static int thumb_reg PARAMS ((char ** str, int hi_lo)); | |
1178 | ||
1179 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ | |
1180 | #define THUMB_REG_LO 0x1 | |
1181 | #define THUMB_REG_HI 0x2 | |
1182 | #define THUMB_REG_ANY 0x3 | |
1183 | ||
1184 | #define THUMB_H1 0x0080 | |
1185 | #define THUMB_H2 0x0040 | |
1186 | ||
1187 | #define THUMB_ASR 0 | |
1188 | #define THUMB_LSL 1 | |
1189 | #define THUMB_LSR 2 | |
1190 | ||
1191 | #define THUMB_MOVE 0 | |
1192 | #define THUMB_COMPARE 1 | |
1193 | ||
1194 | #define THUMB_LOAD 0 | |
1195 | #define THUMB_STORE 1 | |
1196 | ||
1197 | #define THUMB_PP_PC_LR 0x0100 | |
1198 | ||
1199 | /* These three are used for immediate shifts, do not alter. */ | |
1200 | #define THUMB_WORD 2 | |
1201 | #define THUMB_HALFWORD 1 | |
1202 | #define THUMB_BYTE 0 | |
1203 | ||
1204 | struct thumb_opcode | |
1205 | { | |
1206 | /* Basic string to match. */ | |
05d2d07e | 1207 | const char * template; |
b99bd4ef NC |
1208 | |
1209 | /* Basic instruction code. */ | |
1210 | unsigned long value; | |
1211 | ||
1212 | int size; | |
1213 | ||
1214 | /* Which CPU variants this exists for. */ | |
1215 | unsigned long variants; | |
1216 | ||
1217 | /* Function to call to parse args. */ | |
1218 | void (* parms) PARAMS ((char *)); | |
1219 | }; | |
1220 | ||
05d2d07e | 1221 | static const struct thumb_opcode tinsns[] = |
b99bd4ef | 1222 | { |
c9b604bd | 1223 | /* Thumb v1 (ARMv4T). */ |
b89dddec RE |
1224 | {"adc", 0x4140, 2, ARM_EXT_V4T, do_t_arit}, |
1225 | {"add", 0x0000, 2, ARM_EXT_V4T, do_t_add}, | |
1226 | {"and", 0x4000, 2, ARM_EXT_V4T, do_t_arit}, | |
1227 | {"asr", 0x0000, 2, ARM_EXT_V4T, do_t_asr}, | |
1228 | {"b", T_OPCODE_BRANCH, 2, ARM_EXT_V4T, do_t_branch12}, | |
1229 | {"beq", 0xd0fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1230 | {"bne", 0xd1fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1231 | {"bcs", 0xd2fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1232 | {"bhs", 0xd2fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1233 | {"bcc", 0xd3fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1234 | {"bul", 0xd3fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1235 | {"blo", 0xd3fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1236 | {"bmi", 0xd4fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1237 | {"bpl", 0xd5fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1238 | {"bvs", 0xd6fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1239 | {"bvc", 0xd7fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1240 | {"bhi", 0xd8fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1241 | {"bls", 0xd9fe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1242 | {"bge", 0xdafe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1243 | {"blt", 0xdbfe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1244 | {"bgt", 0xdcfe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1245 | {"ble", 0xddfe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1246 | {"bal", 0xdefe, 2, ARM_EXT_V4T, do_t_branch9}, | |
1247 | {"bic", 0x4380, 2, ARM_EXT_V4T, do_t_arit}, | |
1248 | {"bl", 0xf7fffffe, 4, ARM_EXT_V4T, do_t_branch23}, | |
b89dddec RE |
1249 | {"bx", 0x4700, 2, ARM_EXT_V4T, do_t_bx}, |
1250 | {"cmn", T_OPCODE_CMN, 2, ARM_EXT_V4T, do_t_arit}, | |
1251 | {"cmp", 0x0000, 2, ARM_EXT_V4T, do_t_compare}, | |
1252 | {"eor", 0x4040, 2, ARM_EXT_V4T, do_t_arit}, | |
1253 | {"ldmia", 0xc800, 2, ARM_EXT_V4T, do_t_ldmstm}, | |
1254 | {"ldr", 0x0000, 2, ARM_EXT_V4T, do_t_ldr}, | |
1255 | {"ldrb", 0x0000, 2, ARM_EXT_V4T, do_t_ldrb}, | |
1256 | {"ldrh", 0x0000, 2, ARM_EXT_V4T, do_t_ldrh}, | |
1257 | {"ldrsb", 0x5600, 2, ARM_EXT_V4T, do_t_lds}, | |
1258 | {"ldrsh", 0x5e00, 2, ARM_EXT_V4T, do_t_lds}, | |
1259 | {"ldsb", 0x5600, 2, ARM_EXT_V4T, do_t_lds}, | |
1260 | {"ldsh", 0x5e00, 2, ARM_EXT_V4T, do_t_lds}, | |
1261 | {"lsl", 0x0000, 2, ARM_EXT_V4T, do_t_lsl}, | |
1262 | {"lsr", 0x0000, 2, ARM_EXT_V4T, do_t_lsr}, | |
1263 | {"mov", 0x0000, 2, ARM_EXT_V4T, do_t_mov}, | |
1264 | {"mul", T_OPCODE_MUL, 2, ARM_EXT_V4T, do_t_arit}, | |
1265 | {"mvn", T_OPCODE_MVN, 2, ARM_EXT_V4T, do_t_arit}, | |
1266 | {"neg", T_OPCODE_NEG, 2, ARM_EXT_V4T, do_t_arit}, | |
1267 | {"orr", 0x4300, 2, ARM_EXT_V4T, do_t_arit}, | |
1268 | {"pop", 0xbc00, 2, ARM_EXT_V4T, do_t_push_pop}, | |
1269 | {"push", 0xb400, 2, ARM_EXT_V4T, do_t_push_pop}, | |
1270 | {"ror", 0x41c0, 2, ARM_EXT_V4T, do_t_arit}, | |
1271 | {"sbc", 0x4180, 2, ARM_EXT_V4T, do_t_arit}, | |
1272 | {"stmia", 0xc000, 2, ARM_EXT_V4T, do_t_ldmstm}, | |
1273 | {"str", 0x0000, 2, ARM_EXT_V4T, do_t_str}, | |
1274 | {"strb", 0x0000, 2, ARM_EXT_V4T, do_t_strb}, | |
1275 | {"strh", 0x0000, 2, ARM_EXT_V4T, do_t_strh}, | |
1276 | {"swi", 0xdf00, 2, ARM_EXT_V4T, do_t_swi}, | |
1277 | {"sub", 0x0000, 2, ARM_EXT_V4T, do_t_sub}, | |
1278 | {"tst", T_OPCODE_TST, 2, ARM_EXT_V4T, do_t_arit}, | |
b99bd4ef | 1279 | /* Pseudo ops: */ |
b89dddec RE |
1280 | {"adr", 0x0000, 2, ARM_EXT_V4T, do_t_adr}, |
1281 | {"nop", 0x46C0, 2, ARM_EXT_V4T, do_t_nop}, /* mov r8,r8 */ | |
c9b604bd RE |
1282 | /* Thumb v2 (ARMv5T). */ |
1283 | {"blx", 0, 0, ARM_EXT_V5T, do_t_blx}, | |
1284 | {"bkpt", 0xbe00, 2, ARM_EXT_V5T, do_t_bkpt}, | |
b99bd4ef NC |
1285 | }; |
1286 | ||
1287 | struct reg_entry | |
1288 | { | |
05d2d07e | 1289 | const char * name; |
b99bd4ef NC |
1290 | int number; |
1291 | }; | |
1292 | ||
1293 | #define int_register(reg) ((reg) >= 0 && (reg) <= 15) | |
1294 | #define cp_register(reg) ((reg) >= 32 && (reg) <= 47) | |
1295 | #define fp_register(reg) ((reg) >= 16 && (reg) <= 23) | |
1296 | ||
90f9b791 | 1297 | #define ARM_EXT_MAVERICKSC_REG 134 |
404ff6b5 AH |
1298 | |
1299 | #define cirrus_register(reg) ((reg) >= 50 && (reg) <= 134) | |
1300 | #define cirrus_mvf_register(reg) ((reg) >= 50 && (reg) <= 65) | |
1301 | #define cirrus_mvd_register(reg) ((reg) >= 70 && (reg) <= 85) | |
1302 | #define cirrus_mvfx_register(reg) ((reg) >= 90 && (reg) <= 105) | |
1303 | #define cirrus_mvdx_register(reg) ((reg) >= 110 && (reg) <= 125) | |
1304 | #define cirrus_mvax_register(reg) ((reg) >= 130 && (reg) <= 133) | |
90f9b791 | 1305 | #define ARM_EXT_MAVERICKsc_register(reg) ((reg) == ARM_EXT_MAVERICKSC_REG) |
404ff6b5 | 1306 | |
b99bd4ef | 1307 | #define REG_SP 13 |
c9b604bd RE |
1308 | #define REG_LR 14 |
1309 | #define REG_PC 15 | |
b99bd4ef NC |
1310 | |
1311 | /* These are the standard names. Users can add aliases with .req. */ | |
05d2d07e | 1312 | static const struct reg_entry reg_table[] = |
b99bd4ef NC |
1313 | { |
1314 | /* Processor Register Numbers. */ | |
1315 | {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, | |
1316 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, | |
1317 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, | |
1318 | {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC}, | |
1319 | /* APCS conventions. */ | |
1320 | {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3}, | |
1321 | {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8}, | |
1322 | {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10}, | |
1323 | {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC}, | |
1324 | /* ATPCS additions to APCS conventions. */ | |
1325 | {"wr", 7}, {"v8", 11}, | |
1326 | /* FP Registers. */ | |
1327 | {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19}, | |
1328 | {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23}, | |
1329 | {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35}, | |
1330 | {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39}, | |
1331 | {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43}, | |
1332 | {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47}, | |
1333 | {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35}, | |
1334 | {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39}, | |
1335 | {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43}, | |
1336 | {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47}, | |
1337 | /* ATPCS additions to float register names. */ | |
1338 | {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19}, | |
1339 | {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23}, | |
1340 | {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19}, | |
1341 | {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23}, | |
404ff6b5 AH |
1342 | /* Cirrus DSP coprocessor registers. */ |
1343 | {"mvf0", 50}, {"mvf1", 51}, {"mvf2", 52}, {"mvf3", 53}, | |
1344 | {"mvf4", 54}, {"mvf5", 55}, {"mvf6", 56}, {"mvf7", 57}, | |
1345 | {"mvf8", 58}, {"mvf9", 59}, {"mvf10", 60}, {"mvf11", 61}, | |
1346 | {"mvf12", 62},{"mvf13", 63}, {"mvf14", 64}, {"mvf15", 65}, | |
1347 | {"mvd0", 70}, {"mvd1", 71}, {"mvd2", 72}, {"mvd3", 73}, | |
1348 | {"mvd4", 74}, {"mvd5", 75}, {"mvd6", 76}, {"mvd7", 77}, | |
1349 | {"mvd8", 78}, {"mvd9", 79}, {"mvd10", 80}, {"mvd11", 81}, | |
1350 | {"mvd12", 82},{"mvd13", 83}, {"mvd14", 84}, {"mvd15", 85}, | |
1351 | {"mvfx0", 90},{"mvfx1", 91}, {"mvfx2", 92}, {"mvfx3", 93}, | |
1352 | {"mvfx4", 94},{"mvfx5", 95}, {"mvfx6", 96}, {"mvfx7", 97}, | |
1353 | {"mvfx8", 98},{"mvfx9", 99}, {"mvfx10", 100},{"mvfx11", 101}, | |
1354 | {"mvfx12", 102},{"mvfx13", 103},{"mvfx14", 104},{"mvfx15", 105}, | |
1355 | {"mvdx0", 110}, {"mvdx1", 111}, {"mvdx2", 112}, {"mvdx3", 113}, | |
1356 | {"mvdx4", 114}, {"mvdx5", 115}, {"mvdx6", 116}, {"mvdx7", 117}, | |
1357 | {"mvdx8", 118}, {"mvdx9", 119}, {"mvdx10", 120},{"mvdx11", 121}, | |
1358 | {"mvdx12", 122},{"mvdx13", 123},{"mvdx14", 124},{"mvdx15", 125}, | |
1359 | {"mvax0", 130}, {"mvax1", 131}, {"mvax2", 132}, {"mvax3", 133}, | |
90f9b791 | 1360 | {"dspsc", ARM_EXT_MAVERICKSC_REG}, |
b99bd4ef NC |
1361 | /* FIXME: At some point we need to add VFP register names. */ |
1362 | /* Array terminator. */ | |
1363 | {NULL, 0} | |
1364 | }; | |
1365 | ||
1366 | #define BAD_ARGS _("Bad arguments to instruction") | |
1367 | #define BAD_PC _("r15 not allowed here") | |
1368 | #define BAD_FLAGS _("Instruction should not have flags") | |
1369 | #define BAD_COND _("Instruction is not conditional") | |
1370 | #define ERR_NO_ACCUM _("acc0 expected") | |
1371 | ||
1372 | static struct hash_control * arm_ops_hsh = NULL; | |
1373 | static struct hash_control * arm_tops_hsh = NULL; | |
1374 | static struct hash_control * arm_cond_hsh = NULL; | |
1375 | static struct hash_control * arm_shift_hsh = NULL; | |
1376 | static struct hash_control * arm_reg_hsh = NULL; | |
1377 | static struct hash_control * arm_psr_hsh = NULL; | |
1378 | ||
1379 | /* This table describes all the machine specific pseudo-ops the assembler | |
1380 | has to support. The fields are: | |
1381 | pseudo-op name without dot | |
1382 | function to call to execute this pseudo-op | |
1383 | Integer arg to pass to the function. */ | |
1384 | ||
1385 | static void s_req PARAMS ((int)); | |
1386 | static void s_align PARAMS ((int)); | |
1387 | static void s_bss PARAMS ((int)); | |
1388 | static void s_even PARAMS ((int)); | |
1389 | static void s_ltorg PARAMS ((int)); | |
1390 | static void s_arm PARAMS ((int)); | |
1391 | static void s_thumb PARAMS ((int)); | |
1392 | static void s_code PARAMS ((int)); | |
1393 | static void s_force_thumb PARAMS ((int)); | |
1394 | static void s_thumb_func PARAMS ((int)); | |
1395 | static void s_thumb_set PARAMS ((int)); | |
1396 | static void arm_s_text PARAMS ((int)); | |
1397 | static void arm_s_data PARAMS ((int)); | |
1398 | #ifdef OBJ_ELF | |
1399 | static void arm_s_section PARAMS ((int)); | |
1400 | static void s_arm_elf_cons PARAMS ((int)); | |
1401 | #endif | |
1402 | ||
1403 | static int my_get_expression PARAMS ((expressionS *, char **)); | |
1404 | ||
05d2d07e | 1405 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef NC |
1406 | { |
1407 | /* Never called becasue '.req' does not start line. */ | |
1408 | { "req", s_req, 0 }, | |
1409 | { "bss", s_bss, 0 }, | |
1410 | { "align", s_align, 0 }, | |
1411 | { "arm", s_arm, 0 }, | |
1412 | { "thumb", s_thumb, 0 }, | |
1413 | { "code", s_code, 0 }, | |
1414 | { "force_thumb", s_force_thumb, 0 }, | |
1415 | { "thumb_func", s_thumb_func, 0 }, | |
1416 | { "thumb_set", s_thumb_set, 0 }, | |
1417 | { "even", s_even, 0 }, | |
1418 | { "ltorg", s_ltorg, 0 }, | |
1419 | { "pool", s_ltorg, 0 }, | |
1420 | /* Allow for the effect of section changes. */ | |
1421 | { "text", arm_s_text, 0 }, | |
1422 | { "data", arm_s_data, 0 }, | |
1423 | #ifdef OBJ_ELF | |
1424 | { "section", arm_s_section, 0 }, | |
1425 | { "section.s", arm_s_section, 0 }, | |
1426 | { "sect", arm_s_section, 0 }, | |
1427 | { "sect.s", arm_s_section, 0 }, | |
1428 | { "word", s_arm_elf_cons, 4 }, | |
1429 | { "long", s_arm_elf_cons, 4 }, | |
1430 | { "file", dwarf2_directive_file, 0 }, | |
1431 | { "loc", dwarf2_directive_loc, 0 }, | |
1432 | #else | |
1433 | { "word", cons, 4}, | |
1434 | #endif | |
1435 | { "extend", float_cons, 'x' }, | |
1436 | { "ldouble", float_cons, 'x' }, | |
1437 | { "packed", float_cons, 'p' }, | |
1438 | { 0, 0, 0 } | |
1439 | }; | |
1440 | ||
1441 | /* Stuff needed to resolve the label ambiguity | |
1442 | As: | |
1443 | ... | |
1444 | label: <insn> | |
1445 | may differ from: | |
1446 | ... | |
1447 | label: | |
1448 | <insn> | |
1449 | */ | |
1450 | ||
1451 | symbolS * last_label_seen; | |
1452 | static int label_is_thumb_function_name = false; | |
1453 | ||
1454 | /* Literal stuff. */ | |
1455 | ||
1456 | #define MAX_LITERAL_POOL_SIZE 1024 | |
1457 | ||
1458 | typedef struct literalS | |
1459 | { | |
1460 | struct expressionS exp; | |
1461 | struct arm_it * inst; | |
1462 | } literalT; | |
1463 | ||
1464 | literalT literals[MAX_LITERAL_POOL_SIZE]; | |
1465 | ||
1466 | /* Next free entry in the pool. */ | |
1467 | int next_literal_pool_place = 0; | |
1468 | ||
1469 | /* Next literal pool number. */ | |
1470 | int lit_pool_num = 1; | |
1471 | ||
1472 | symbolS * current_poolP = NULL; | |
1473 | ||
1474 | static int | |
1475 | add_to_lit_pool () | |
1476 | { | |
1477 | int lit_count = 0; | |
1478 | ||
1479 | if (current_poolP == NULL) | |
1480 | current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section, | |
1481 | (valueT) 0, &zero_address_frag); | |
1482 | ||
1483 | /* Check if this literal value is already in the pool: */ | |
1484 | while (lit_count < next_literal_pool_place) | |
1485 | { | |
1486 | if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op | |
1487 | && inst.reloc.exp.X_op == O_constant | |
1488 | && (literals[lit_count].exp.X_add_number | |
1489 | == inst.reloc.exp.X_add_number) | |
1490 | && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned) | |
1491 | break; | |
1492 | ||
1493 | if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op | |
1494 | && inst.reloc.exp.X_op == O_symbol | |
1495 | && (literals[lit_count].exp.X_add_number | |
1496 | == inst.reloc.exp.X_add_number) | |
1497 | && (literals[lit_count].exp.X_add_symbol | |
1498 | == inst.reloc.exp.X_add_symbol) | |
1499 | && (literals[lit_count].exp.X_op_symbol | |
1500 | == inst.reloc.exp.X_op_symbol)) | |
1501 | break; | |
1502 | ||
1503 | lit_count++; | |
1504 | } | |
1505 | ||
1506 | if (lit_count == next_literal_pool_place) /* New entry. */ | |
1507 | { | |
1508 | if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE) | |
1509 | { | |
1510 | inst.error = _("Literal Pool Overflow"); | |
1511 | return FAIL; | |
1512 | } | |
1513 | ||
1514 | literals[next_literal_pool_place].exp = inst.reloc.exp; | |
1515 | lit_count = next_literal_pool_place++; | |
1516 | } | |
1517 | ||
1518 | inst.reloc.exp.X_op = O_symbol; | |
1519 | inst.reloc.exp.X_add_number = (lit_count) * 4 - 8; | |
1520 | inst.reloc.exp.X_add_symbol = current_poolP; | |
1521 | ||
1522 | return SUCCESS; | |
1523 | } | |
1524 | ||
1525 | /* Can't use symbol_new here, so have to create a symbol and then at | |
1526 | a later date assign it a value. Thats what these functions do. */ | |
1527 | ||
1528 | static void | |
1529 | symbol_locate (symbolP, name, segment, valu, frag) | |
1530 | symbolS * symbolP; | |
05d2d07e | 1531 | const char * name; /* It is copied, the caller can modify. */ |
b99bd4ef NC |
1532 | segT segment; /* Segment identifier (SEG_<something>). */ |
1533 | valueT valu; /* Symbol value. */ | |
1534 | fragS * frag; /* Associated fragment. */ | |
1535 | { | |
1536 | unsigned int name_length; | |
1537 | char * preserved_copy_of_name; | |
1538 | ||
1539 | name_length = strlen (name) + 1; /* +1 for \0. */ | |
1540 | obstack_grow (¬es, name, name_length); | |
1541 | preserved_copy_of_name = obstack_finish (¬es); | |
1542 | #ifdef STRIP_UNDERSCORE | |
1543 | if (preserved_copy_of_name[0] == '_') | |
1544 | preserved_copy_of_name++; | |
1545 | #endif | |
1546 | ||
1547 | #ifdef tc_canonicalize_symbol_name | |
1548 | preserved_copy_of_name = | |
1549 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1550 | #endif | |
1551 | ||
1552 | S_SET_NAME (symbolP, preserved_copy_of_name); | |
1553 | ||
1554 | S_SET_SEGMENT (symbolP, segment); | |
1555 | S_SET_VALUE (symbolP, valu); | |
1556 | symbol_clear_list_pointers(symbolP); | |
1557 | ||
1558 | symbol_set_frag (symbolP, frag); | |
1559 | ||
1560 | /* Link to end of symbol chain. */ | |
1561 | { | |
1562 | extern int symbol_table_frozen; | |
1563 | if (symbol_table_frozen) | |
1564 | abort (); | |
1565 | } | |
1566 | ||
1567 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); | |
1568 | ||
1569 | obj_symbol_new_hook (symbolP); | |
1570 | ||
1571 | #ifdef tc_symbol_new_hook | |
1572 | tc_symbol_new_hook (symbolP); | |
1573 | #endif | |
1574 | ||
1575 | #ifdef DEBUG_SYMS | |
1576 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1577 | #endif /* DEBUG_SYMS */ | |
1578 | } | |
1579 | ||
1580 | /* Check that an immediate is valid. | |
1581 | If so, convert it to the right format. */ | |
1582 | ||
1583 | static unsigned int | |
1584 | validate_immediate (val) | |
1585 | unsigned int val; | |
1586 | { | |
1587 | unsigned int a; | |
1588 | unsigned int i; | |
1589 | ||
1590 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
1591 | ||
1592 | for (i = 0; i < 32; i += 2) | |
1593 | if ((a = rotate_left (val, i)) <= 0xff) | |
1594 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
1595 | ||
1596 | return FAIL; | |
1597 | } | |
1598 | ||
1599 | /* Check to see if an immediate can be computed as two seperate immediate | |
1600 | values, added together. We already know that this value cannot be | |
1601 | computed by just one ARM instruction. */ | |
1602 | ||
1603 | static unsigned int | |
1604 | validate_immediate_twopart (val, highpart) | |
1605 | unsigned int val; | |
1606 | unsigned int * highpart; | |
1607 | { | |
1608 | unsigned int a; | |
1609 | unsigned int i; | |
1610 | ||
1611 | for (i = 0; i < 32; i += 2) | |
1612 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
1613 | { | |
1614 | if (a & 0xff00) | |
1615 | { | |
1616 | if (a & ~ 0xffff) | |
1617 | continue; | |
1618 | * highpart = (a >> 8) | ((i + 24) << 7); | |
1619 | } | |
1620 | else if (a & 0xff0000) | |
1621 | { | |
1622 | if (a & 0xff000000) | |
1623 | continue; | |
1624 | * highpart = (a >> 16) | ((i + 16) << 7); | |
1625 | } | |
1626 | else | |
1627 | { | |
1628 | assert (a & 0xff000000); | |
1629 | * highpart = (a >> 24) | ((i + 8) << 7); | |
1630 | } | |
1631 | ||
1632 | return (a & 0xff) | (i << 7); | |
1633 | } | |
1634 | ||
1635 | return FAIL; | |
1636 | } | |
1637 | ||
1638 | static int | |
1639 | validate_offset_imm (val, hwse) | |
1640 | unsigned int val; | |
1641 | int hwse; | |
1642 | { | |
1643 | if ((hwse && val > 255) || val > 4095) | |
1644 | return FAIL; | |
1645 | return val; | |
1646 | } | |
1647 | ||
1648 | static void | |
1649 | s_req (a) | |
1650 | int a ATTRIBUTE_UNUSED; | |
1651 | { | |
1652 | as_bad (_("Invalid syntax for .req directive.")); | |
1653 | } | |
1654 | ||
1655 | static void | |
1656 | s_bss (ignore) | |
1657 | int ignore ATTRIBUTE_UNUSED; | |
1658 | { | |
1659 | /* We don't support putting frags in the BSS segment, we fake it by | |
1660 | marking in_bss, then looking at s_skip for clues. */ | |
1661 | subseg_set (bss_section, 0); | |
1662 | demand_empty_rest_of_line (); | |
1663 | } | |
1664 | ||
1665 | static void | |
1666 | s_even (ignore) | |
1667 | int ignore ATTRIBUTE_UNUSED; | |
1668 | { | |
1669 | /* Never make frag if expect extra pass. */ | |
1670 | if (!need_pass_2) | |
1671 | frag_align (1, 0, 0); | |
1672 | ||
1673 | record_alignment (now_seg, 1); | |
1674 | ||
1675 | demand_empty_rest_of_line (); | |
1676 | } | |
1677 | ||
1678 | static void | |
1679 | s_ltorg (ignored) | |
1680 | int ignored ATTRIBUTE_UNUSED; | |
1681 | { | |
1682 | int lit_count = 0; | |
1683 | char sym_name[20]; | |
1684 | ||
1685 | if (current_poolP == NULL) | |
1686 | return; | |
1687 | ||
1688 | /* Align pool as you have word accesses. | |
1689 | Only make a frag if we have to. */ | |
1690 | if (!need_pass_2) | |
1691 | frag_align (2, 0, 0); | |
1692 | ||
1693 | record_alignment (now_seg, 2); | |
1694 | ||
1695 | sprintf (sym_name, "$$lit_\002%x", lit_pool_num++); | |
1696 | ||
1697 | symbol_locate (current_poolP, sym_name, now_seg, | |
1698 | (valueT) frag_now_fix (), frag_now); | |
1699 | symbol_table_insert (current_poolP); | |
1700 | ||
1701 | ARM_SET_THUMB (current_poolP, thumb_mode); | |
1702 | ||
1703 | #if defined OBJ_COFF || defined OBJ_ELF | |
1704 | ARM_SET_INTERWORK (current_poolP, support_interwork); | |
1705 | #endif | |
1706 | ||
1707 | while (lit_count < next_literal_pool_place) | |
1708 | /* First output the expression in the instruction to the pool. */ | |
1709 | emit_expr (&(literals[lit_count++].exp), 4); /* .word */ | |
1710 | ||
1711 | next_literal_pool_place = 0; | |
1712 | current_poolP = NULL; | |
1713 | } | |
1714 | ||
1715 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
1716 | ||
1717 | static void | |
1718 | s_align (unused) | |
1719 | int unused ATTRIBUTE_UNUSED; | |
1720 | { | |
1721 | register int temp; | |
1722 | register long temp_fill; | |
1723 | long max_alignment = 15; | |
1724 | ||
1725 | temp = get_absolute_expression (); | |
1726 | if (temp > max_alignment) | |
1727 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
1728 | else if (temp < 0) | |
1729 | { | |
1730 | as_bad (_("Alignment negative. 0 assumed.")); | |
1731 | temp = 0; | |
1732 | } | |
1733 | ||
1734 | if (*input_line_pointer == ',') | |
1735 | { | |
1736 | input_line_pointer++; | |
1737 | temp_fill = get_absolute_expression (); | |
1738 | } | |
1739 | else | |
1740 | temp_fill = 0; | |
1741 | ||
1742 | if (!temp) | |
1743 | temp = 2; | |
1744 | ||
1745 | /* Only make a frag if we HAVE to. */ | |
1746 | if (temp && !need_pass_2) | |
1747 | frag_align (temp, (int) temp_fill, 0); | |
1748 | demand_empty_rest_of_line (); | |
1749 | ||
1750 | record_alignment (now_seg, temp); | |
1751 | } | |
1752 | ||
1753 | static void | |
1754 | s_force_thumb (ignore) | |
1755 | int ignore ATTRIBUTE_UNUSED; | |
1756 | { | |
1757 | /* If we are not already in thumb mode go into it, EVEN if | |
1758 | the target processor does not support thumb instructions. | |
1759 | This is used by gcc/config/arm/lib1funcs.asm for example | |
1760 | to compile interworking support functions even if the | |
1761 | target processor should not support interworking. */ | |
1762 | if (! thumb_mode) | |
1763 | { | |
1764 | thumb_mode = 2; | |
1765 | ||
1766 | record_alignment (now_seg, 1); | |
1767 | } | |
1768 | ||
1769 | demand_empty_rest_of_line (); | |
1770 | } | |
1771 | ||
1772 | static void | |
1773 | s_thumb_func (ignore) | |
1774 | int ignore ATTRIBUTE_UNUSED; | |
1775 | { | |
1776 | if (! thumb_mode) | |
1777 | opcode_select (16); | |
1778 | ||
1779 | /* The following label is the name/address of the start of a Thumb function. | |
1780 | We need to know this for the interworking support. */ | |
1781 | label_is_thumb_function_name = true; | |
1782 | ||
1783 | demand_empty_rest_of_line (); | |
1784 | } | |
1785 | ||
1786 | /* Perform a .set directive, but also mark the alias as | |
1787 | being a thumb function. */ | |
1788 | ||
1789 | static void | |
1790 | s_thumb_set (equiv) | |
1791 | int equiv; | |
1792 | { | |
1793 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
1794 | We cannot just call that code as we need to get at the symbol that | |
1795 | is created. */ | |
1796 | register char * name; | |
1797 | register char delim; | |
1798 | register char * end_name; | |
1799 | register symbolS * symbolP; | |
1800 | ||
1801 | /* Especial apologies for the random logic: | |
1802 | This just grew, and could be parsed much more simply! | |
1803 | Dean - in haste. */ | |
1804 | name = input_line_pointer; | |
1805 | delim = get_symbol_end (); | |
1806 | end_name = input_line_pointer; | |
1807 | *end_name = delim; | |
1808 | ||
1809 | SKIP_WHITESPACE (); | |
1810 | ||
1811 | if (*input_line_pointer != ',') | |
1812 | { | |
1813 | *end_name = 0; | |
1814 | as_bad (_("Expected comma after name \"%s\""), name); | |
1815 | *end_name = delim; | |
1816 | ignore_rest_of_line (); | |
1817 | return; | |
1818 | } | |
1819 | ||
1820 | input_line_pointer++; | |
1821 | *end_name = 0; | |
1822 | ||
1823 | if (name[0] == '.' && name[1] == '\0') | |
1824 | { | |
1825 | /* XXX - this should not happen to .thumb_set. */ | |
1826 | abort (); | |
1827 | } | |
1828 | ||
1829 | if ((symbolP = symbol_find (name)) == NULL | |
1830 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
1831 | { | |
1832 | #ifndef NO_LISTING | |
1833 | /* When doing symbol listings, play games with dummy fragments living | |
1834 | outside the normal fragment chain to record the file and line info | |
1835 | for this symbol. */ | |
1836 | if (listing & LISTING_SYMBOLS) | |
1837 | { | |
1838 | extern struct list_info_struct * listing_tail; | |
1839 | fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS)); | |
1840 | ||
1841 | memset (dummy_frag, 0, sizeof (fragS)); | |
1842 | dummy_frag->fr_type = rs_fill; | |
1843 | dummy_frag->line = listing_tail; | |
1844 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
1845 | dummy_frag->fr_symbol = symbolP; | |
1846 | } | |
1847 | else | |
1848 | #endif | |
1849 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
1850 | ||
1851 | #ifdef OBJ_COFF | |
1852 | /* "set" symbols are local unless otherwise specified. */ | |
1853 | SF_SET_LOCAL (symbolP); | |
1854 | #endif /* OBJ_COFF */ | |
1855 | } /* Make a new symbol. */ | |
1856 | ||
1857 | symbol_table_insert (symbolP); | |
1858 | ||
1859 | * end_name = delim; | |
1860 | ||
1861 | if (equiv | |
1862 | && S_IS_DEFINED (symbolP) | |
1863 | && S_GET_SEGMENT (symbolP) != reg_section) | |
1864 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
1865 | ||
1866 | pseudo_set (symbolP); | |
1867 | ||
1868 | demand_empty_rest_of_line (); | |
1869 | ||
1870 | /* XXX Now we come to the Thumb specific bit of code. */ | |
1871 | ||
1872 | THUMB_SET_FUNC (symbolP, 1); | |
1873 | ARM_SET_THUMB (symbolP, 1); | |
1874 | #if defined OBJ_ELF || defined OBJ_COFF | |
1875 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1876 | #endif | |
1877 | } | |
1878 | ||
1879 | /* If we change section we must dump the literal pool first. */ | |
1880 | ||
1881 | static void | |
1882 | arm_s_text (ignore) | |
1883 | int ignore; | |
1884 | { | |
1885 | if (now_seg != text_section) | |
1886 | s_ltorg (0); | |
1887 | ||
1888 | #ifdef OBJ_ELF | |
1889 | obj_elf_text (ignore); | |
1890 | #else | |
1891 | s_text (ignore); | |
1892 | #endif | |
1893 | } | |
1894 | ||
1895 | static void | |
1896 | arm_s_data (ignore) | |
1897 | int ignore; | |
1898 | { | |
1899 | if (flag_readonly_data_in_text) | |
1900 | { | |
1901 | if (now_seg != text_section) | |
1902 | s_ltorg (0); | |
1903 | } | |
1904 | else if (now_seg != data_section) | |
1905 | s_ltorg (0); | |
1906 | ||
1907 | #ifdef OBJ_ELF | |
1908 | obj_elf_data (ignore); | |
1909 | #else | |
1910 | s_data (ignore); | |
1911 | #endif | |
1912 | } | |
1913 | ||
1914 | #ifdef OBJ_ELF | |
1915 | static void | |
1916 | arm_s_section (ignore) | |
1917 | int ignore; | |
1918 | { | |
1919 | s_ltorg (0); | |
1920 | ||
1921 | obj_elf_section (ignore); | |
1922 | } | |
1923 | #endif | |
1924 | ||
1925 | static void | |
1926 | opcode_select (width) | |
1927 | int width; | |
1928 | { | |
1929 | switch (width) | |
1930 | { | |
1931 | case 16: | |
1932 | if (! thumb_mode) | |
1933 | { | |
b89dddec | 1934 | if (! (cpu_variant & ARM_EXT_V4T)) |
b99bd4ef NC |
1935 | as_bad (_("selected processor does not support THUMB opcodes")); |
1936 | ||
1937 | thumb_mode = 1; | |
1938 | /* No need to force the alignment, since we will have been | |
1939 | coming from ARM mode, which is word-aligned. */ | |
1940 | record_alignment (now_seg, 1); | |
1941 | } | |
1942 | break; | |
1943 | ||
1944 | case 32: | |
1945 | if (thumb_mode) | |
1946 | { | |
b89dddec | 1947 | if ((cpu_variant & ARM_ANY) == ARM_EXT_V4T) |
b99bd4ef NC |
1948 | as_bad (_("selected processor does not support ARM opcodes")); |
1949 | ||
1950 | thumb_mode = 0; | |
1951 | ||
1952 | if (!need_pass_2) | |
1953 | frag_align (2, 0, 0); | |
1954 | ||
1955 | record_alignment (now_seg, 1); | |
1956 | } | |
1957 | break; | |
1958 | ||
1959 | default: | |
1960 | as_bad (_("invalid instruction size selected (%d)"), width); | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | static void | |
1965 | s_arm (ignore) | |
1966 | int ignore ATTRIBUTE_UNUSED; | |
1967 | { | |
1968 | opcode_select (32); | |
1969 | demand_empty_rest_of_line (); | |
1970 | } | |
1971 | ||
1972 | static void | |
1973 | s_thumb (ignore) | |
1974 | int ignore ATTRIBUTE_UNUSED; | |
1975 | { | |
1976 | opcode_select (16); | |
1977 | demand_empty_rest_of_line (); | |
1978 | } | |
1979 | ||
1980 | static void | |
1981 | s_code (unused) | |
1982 | int unused ATTRIBUTE_UNUSED; | |
1983 | { | |
1984 | register int temp; | |
1985 | ||
1986 | temp = get_absolute_expression (); | |
1987 | switch (temp) | |
1988 | { | |
1989 | case 16: | |
1990 | case 32: | |
1991 | opcode_select (temp); | |
1992 | break; | |
1993 | ||
1994 | default: | |
1995 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | static void | |
2000 | end_of_line (str) | |
2001 | char * str; | |
2002 | { | |
2003 | skip_whitespace (str); | |
2004 | ||
2005 | if (* str != '\0') | |
2006 | inst.error = _("Garbage following instruction"); | |
2007 | } | |
2008 | ||
2009 | static int | |
2010 | skip_past_comma (str) | |
2011 | char ** str; | |
2012 | { | |
2013 | char * p = * str, c; | |
2014 | int comma = 0; | |
2015 | ||
2016 | while ((c = *p) == ' ' || c == ',') | |
2017 | { | |
2018 | p++; | |
2019 | if (c == ',' && comma++) | |
2020 | return FAIL; | |
2021 | } | |
2022 | ||
2023 | if (c == '\0') | |
2024 | return FAIL; | |
2025 | ||
2026 | *str = p; | |
2027 | return comma ? SUCCESS : FAIL; | |
2028 | } | |
2029 | ||
2030 | /* A standard register must be given at this point. | |
2031 | SHIFT is the place to put it in inst.instruction. | |
2032 | Restores input start point on error. | |
2033 | Returns the reg#, or FAIL. */ | |
2034 | ||
2035 | static int | |
2036 | reg_required_here (str, shift) | |
2037 | char ** str; | |
2038 | int shift; | |
2039 | { | |
2040 | static char buff [128]; /* XXX */ | |
2041 | int reg; | |
2042 | char * start = * str; | |
2043 | ||
2044 | if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg)) | |
2045 | { | |
2046 | if (shift >= 0) | |
2047 | inst.instruction |= reg << shift; | |
2048 | return reg; | |
2049 | } | |
2050 | ||
2051 | /* Restore the start point, we may have got a reg of the wrong class. */ | |
2052 | *str = start; | |
2053 | ||
2054 | /* In the few cases where we might be able to accept something else | |
2055 | this error can be overridden. */ | |
2056 | sprintf (buff, _("Register expected, not '%.100s'"), start); | |
2057 | inst.error = buff; | |
2058 | ||
2059 | return FAIL; | |
2060 | } | |
2061 | ||
05d2d07e | 2062 | static const struct asm_psr * |
b99bd4ef NC |
2063 | arm_psr_parse (ccp) |
2064 | register char ** ccp; | |
2065 | { | |
2066 | char * start = * ccp; | |
2067 | char c; | |
2068 | char * p; | |
05d2d07e | 2069 | const struct asm_psr * psr; |
b99bd4ef NC |
2070 | |
2071 | p = start; | |
2072 | ||
2073 | /* Skip to the end of the next word in the input stream. */ | |
2074 | do | |
2075 | { | |
2076 | c = *p++; | |
2077 | } | |
3882b010 | 2078 | while (ISALPHA (c) || c == '_'); |
b99bd4ef NC |
2079 | |
2080 | /* Terminate the word. */ | |
2081 | *--p = 0; | |
2082 | ||
2083 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience | |
2084 | feature for ease of use and backwards compatibility. */ | |
2085 | if (!strncmp (start, "cpsr", 4)) | |
2086 | strncpy (start, "CPSR", 4); | |
2087 | else if (!strncmp (start, "spsr", 4)) | |
2088 | strncpy (start, "SPSR", 4); | |
2089 | ||
2090 | /* Now locate the word in the psr hash table. */ | |
05d2d07e | 2091 | psr = (const struct asm_psr *) hash_find (arm_psr_hsh, start); |
b99bd4ef NC |
2092 | |
2093 | /* Restore the input stream. */ | |
2094 | *p = c; | |
2095 | ||
2096 | /* If we found a valid match, advance the | |
2097 | stream pointer past the end of the word. */ | |
2098 | *ccp = p; | |
2099 | ||
2100 | return psr; | |
2101 | } | |
2102 | ||
2103 | /* Parse the input looking for a PSR flag. */ | |
2104 | ||
2105 | static int | |
2106 | psr_required_here (str) | |
2107 | char ** str; | |
2108 | { | |
2109 | char * start = * str; | |
05d2d07e | 2110 | const struct asm_psr * psr; |
b99bd4ef NC |
2111 | |
2112 | psr = arm_psr_parse (str); | |
2113 | ||
2114 | if (psr) | |
2115 | { | |
2116 | /* If this is the SPSR that is being modified, set the R bit. */ | |
2117 | if (! psr->cpsr) | |
2118 | inst.instruction |= SPSR_BIT; | |
2119 | ||
2120 | /* Set the psr flags in the MSR instruction. */ | |
2121 | inst.instruction |= psr->field << PSR_SHIFT; | |
2122 | ||
2123 | return SUCCESS; | |
2124 | } | |
2125 | ||
2126 | /* In the few cases where we might be able to accept | |
2127 | something else this error can be overridden. */ | |
2128 | inst.error = _("flag for {c}psr instruction expected"); | |
2129 | ||
2130 | /* Restore the start point. */ | |
2131 | *str = start; | |
2132 | return FAIL; | |
2133 | } | |
2134 | ||
2135 | static int | |
2136 | co_proc_number (str) | |
2137 | char ** str; | |
2138 | { | |
2139 | int processor, pchar; | |
2140 | ||
2141 | skip_whitespace (* str); | |
2142 | ||
2143 | /* The data sheet seems to imply that just a number on its own is valid | |
2144 | here, but the RISC iX assembler seems to accept a prefix 'p'. We will | |
2145 | accept either. */ | |
2146 | if (**str == 'p' || **str == 'P') | |
2147 | (*str)++; | |
2148 | ||
2149 | pchar = *(*str)++; | |
2150 | if (pchar >= '0' && pchar <= '9') | |
2151 | { | |
2152 | processor = pchar - '0'; | |
2153 | if (**str >= '0' && **str <= '9') | |
2154 | { | |
2155 | processor = processor * 10 + *(*str)++ - '0'; | |
2156 | if (processor > 15) | |
2157 | { | |
2158 | inst.error = _("Illegal co-processor number"); | |
2159 | return FAIL; | |
2160 | } | |
2161 | } | |
2162 | } | |
2163 | else | |
2164 | { | |
2165 | inst.error = _("Bad or missing co-processor number"); | |
2166 | return FAIL; | |
2167 | } | |
2168 | ||
2169 | inst.instruction |= processor << 8; | |
2170 | return SUCCESS; | |
2171 | } | |
2172 | ||
2173 | static int | |
2174 | cp_opc_expr (str, where, length) | |
2175 | char ** str; | |
2176 | int where; | |
2177 | int length; | |
2178 | { | |
2179 | expressionS expr; | |
2180 | ||
2181 | skip_whitespace (* str); | |
2182 | ||
2183 | memset (&expr, '\0', sizeof (expr)); | |
2184 | ||
2185 | if (my_get_expression (&expr, str)) | |
2186 | return FAIL; | |
2187 | if (expr.X_op != O_constant) | |
2188 | { | |
2189 | inst.error = _("bad or missing expression"); | |
2190 | return FAIL; | |
2191 | } | |
2192 | ||
2193 | if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number) | |
2194 | { | |
2195 | inst.error = _("immediate co-processor expression too large"); | |
2196 | return FAIL; | |
2197 | } | |
2198 | ||
2199 | inst.instruction |= expr.X_add_number << where; | |
2200 | return SUCCESS; | |
2201 | } | |
2202 | ||
2203 | static int | |
2204 | cp_reg_required_here (str, where) | |
2205 | char ** str; | |
2206 | int where; | |
2207 | { | |
2208 | int reg; | |
2209 | char * start = *str; | |
2210 | ||
2211 | if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg)) | |
2212 | { | |
2213 | reg &= 15; | |
2214 | inst.instruction |= reg << where; | |
2215 | return reg; | |
2216 | } | |
2217 | ||
2218 | /* In the few cases where we might be able to accept something else | |
2219 | this error can be overridden. */ | |
2220 | inst.error = _("Co-processor register expected"); | |
2221 | ||
2222 | /* Restore the start point. */ | |
2223 | *str = start; | |
2224 | return FAIL; | |
2225 | } | |
2226 | ||
2227 | static int | |
2228 | fp_reg_required_here (str, where) | |
2229 | char ** str; | |
2230 | int where; | |
2231 | { | |
2232 | int reg; | |
2233 | char * start = * str; | |
2234 | ||
2235 | if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg)) | |
2236 | { | |
2237 | reg &= 7; | |
2238 | inst.instruction |= reg << where; | |
2239 | return reg; | |
2240 | } | |
2241 | ||
2242 | /* In the few cases where we might be able to accept something else | |
2243 | this error can be overridden. */ | |
2244 | inst.error = _("Floating point register expected"); | |
2245 | ||
2246 | /* Restore the start point. */ | |
2247 | *str = start; | |
2248 | return FAIL; | |
2249 | } | |
2250 | ||
2251 | static int | |
2252 | cp_address_offset (str) | |
2253 | char ** str; | |
2254 | { | |
2255 | int offset; | |
2256 | ||
2257 | skip_whitespace (* str); | |
2258 | ||
2259 | if (! is_immediate_prefix (**str)) | |
2260 | { | |
2261 | inst.error = _("immediate expression expected"); | |
2262 | return FAIL; | |
2263 | } | |
2264 | ||
2265 | (*str)++; | |
2266 | ||
2267 | if (my_get_expression (& inst.reloc.exp, str)) | |
2268 | return FAIL; | |
2269 | ||
2270 | if (inst.reloc.exp.X_op == O_constant) | |
2271 | { | |
2272 | offset = inst.reloc.exp.X_add_number; | |
2273 | ||
2274 | if (offset & 3) | |
2275 | { | |
2276 | inst.error = _("co-processor address must be word aligned"); | |
2277 | return FAIL; | |
2278 | } | |
2279 | ||
2280 | if (offset > 1023 || offset < -1023) | |
2281 | { | |
2282 | inst.error = _("offset too large"); | |
2283 | return FAIL; | |
2284 | } | |
2285 | ||
2286 | if (offset >= 0) | |
2287 | inst.instruction |= INDEX_UP; | |
2288 | else | |
2289 | offset = -offset; | |
2290 | ||
2291 | inst.instruction |= offset >> 2; | |
2292 | } | |
2293 | else | |
2294 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
2295 | ||
2296 | return SUCCESS; | |
2297 | } | |
2298 | ||
2299 | static int | |
2300 | cp_address_required_here (str) | |
2301 | char ** str; | |
2302 | { | |
2303 | char * p = * str; | |
2304 | int pre_inc = 0; | |
2305 | int write_back = 0; | |
2306 | ||
2307 | if (*p == '[') | |
2308 | { | |
2309 | int reg; | |
2310 | ||
2311 | p++; | |
2312 | skip_whitespace (p); | |
2313 | ||
2314 | if ((reg = reg_required_here (& p, 16)) == FAIL) | |
2315 | return FAIL; | |
2316 | ||
2317 | skip_whitespace (p); | |
2318 | ||
2319 | if (*p == ']') | |
2320 | { | |
2321 | p++; | |
2322 | ||
2323 | if (skip_past_comma (& p) == SUCCESS) | |
2324 | { | |
2325 | /* [Rn], #expr */ | |
2326 | write_back = WRITE_BACK; | |
2327 | ||
2328 | if (reg == REG_PC) | |
2329 | { | |
2330 | inst.error = _("pc may not be used in post-increment"); | |
2331 | return FAIL; | |
2332 | } | |
2333 | ||
2334 | if (cp_address_offset (& p) == FAIL) | |
2335 | return FAIL; | |
2336 | } | |
2337 | else | |
2338 | pre_inc = PRE_INDEX | INDEX_UP; | |
2339 | } | |
2340 | else | |
2341 | { | |
2342 | /* '['Rn, #expr']'[!] */ | |
2343 | ||
2344 | if (skip_past_comma (& p) == FAIL) | |
2345 | { | |
2346 | inst.error = _("pre-indexed expression expected"); | |
2347 | return FAIL; | |
2348 | } | |
2349 | ||
2350 | pre_inc = PRE_INDEX; | |
2351 | ||
2352 | if (cp_address_offset (& p) == FAIL) | |
2353 | return FAIL; | |
2354 | ||
2355 | skip_whitespace (p); | |
2356 | ||
2357 | if (*p++ != ']') | |
2358 | { | |
2359 | inst.error = _("missing ]"); | |
2360 | return FAIL; | |
2361 | } | |
2362 | ||
2363 | skip_whitespace (p); | |
2364 | ||
2365 | if (*p == '!') | |
2366 | { | |
2367 | if (reg == REG_PC) | |
2368 | { | |
2369 | inst.error = _("pc may not be used with write-back"); | |
2370 | return FAIL; | |
2371 | } | |
2372 | ||
2373 | p++; | |
2374 | write_back = WRITE_BACK; | |
2375 | } | |
2376 | } | |
2377 | } | |
2378 | else | |
2379 | { | |
2380 | if (my_get_expression (&inst.reloc.exp, &p)) | |
2381 | return FAIL; | |
2382 | ||
2383 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
2384 | inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */ | |
2385 | inst.reloc.pc_rel = 1; | |
2386 | inst.instruction |= (REG_PC << 16); | |
2387 | pre_inc = PRE_INDEX; | |
2388 | } | |
2389 | ||
2390 | inst.instruction |= write_back | pre_inc; | |
2391 | *str = p; | |
2392 | return SUCCESS; | |
2393 | } | |
2394 | ||
2395 | static void | |
2396 | do_nop (str, flags) | |
2397 | char * str; | |
2398 | unsigned long flags; | |
2399 | { | |
2400 | /* Do nothing really. */ | |
2401 | inst.instruction |= flags; /* This is pointless. */ | |
2402 | end_of_line (str); | |
2403 | return; | |
2404 | } | |
2405 | ||
2406 | static void | |
2407 | do_mrs (str, flags) | |
2408 | char *str; | |
2409 | unsigned long flags; | |
2410 | { | |
2411 | int skip = 0; | |
2412 | ||
2413 | /* Only one syntax. */ | |
2414 | skip_whitespace (str); | |
2415 | ||
2416 | if (reg_required_here (&str, 12) == FAIL) | |
2417 | { | |
2418 | inst.error = BAD_ARGS; | |
2419 | return; | |
2420 | } | |
2421 | ||
2422 | if (skip_past_comma (&str) == FAIL) | |
2423 | { | |
2424 | inst.error = _("comma expected after register name"); | |
2425 | return; | |
2426 | } | |
2427 | ||
2428 | skip_whitespace (str); | |
2429 | ||
2430 | if ( strcmp (str, "CPSR") == 0 | |
2431 | || strcmp (str, "SPSR") == 0 | |
2432 | /* Lower case versions for backwards compatability. */ | |
2433 | || strcmp (str, "cpsr") == 0 | |
2434 | || strcmp (str, "spsr") == 0) | |
2435 | skip = 4; | |
2436 | ||
2437 | /* This is for backwards compatability with older toolchains. */ | |
2438 | else if ( strcmp (str, "cpsr_all") == 0 | |
2439 | || strcmp (str, "spsr_all") == 0) | |
2440 | skip = 8; | |
2441 | else | |
2442 | { | |
2443 | inst.error = _("{C|S}PSR expected"); | |
2444 | return; | |
2445 | } | |
2446 | ||
2447 | if (* str == 's' || * str == 'S') | |
2448 | inst.instruction |= SPSR_BIT; | |
2449 | str += skip; | |
2450 | ||
2451 | inst.instruction |= flags; | |
2452 | end_of_line (str); | |
2453 | } | |
2454 | ||
2455 | /* Two possible forms: | |
2456 | "{C|S}PSR_<field>, Rm", | |
2457 | "{C|S}PSR_f, #expression". */ | |
2458 | ||
2459 | static void | |
2460 | do_msr (str, flags) | |
2461 | char * str; | |
2462 | unsigned long flags; | |
2463 | { | |
2464 | skip_whitespace (str); | |
2465 | ||
2466 | if (psr_required_here (& str) == FAIL) | |
2467 | return; | |
2468 | ||
2469 | if (skip_past_comma (& str) == FAIL) | |
2470 | { | |
2471 | inst.error = _("comma missing after psr flags"); | |
2472 | return; | |
2473 | } | |
2474 | ||
2475 | skip_whitespace (str); | |
2476 | ||
2477 | if (reg_required_here (& str, 0) != FAIL) | |
2478 | { | |
2479 | inst.error = NULL; | |
2480 | inst.instruction |= flags; | |
2481 | end_of_line (str); | |
2482 | return; | |
2483 | } | |
2484 | ||
2485 | if (! is_immediate_prefix (* str)) | |
2486 | { | |
2487 | inst.error = | |
2488 | _("only a register or immediate value can follow a psr flag"); | |
2489 | return; | |
2490 | } | |
2491 | ||
2492 | str ++; | |
2493 | inst.error = NULL; | |
2494 | ||
2495 | if (my_get_expression (& inst.reloc.exp, & str)) | |
2496 | { | |
2497 | inst.error = | |
2498 | _("only a register or immediate value can follow a psr flag"); | |
2499 | return; | |
2500 | } | |
2501 | ||
2502 | #if 0 /* The first edition of the ARM architecture manual stated that | |
2503 | writing anything other than the flags with an immediate operation | |
2504 | had UNPREDICTABLE effects. This constraint was removed in the | |
2505 | second edition of the specification. */ | |
2506 | if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5 | |
2507 | && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT)) | |
2508 | { | |
2509 | inst.error = _("immediate value cannot be used to set this field"); | |
2510 | return; | |
2511 | } | |
2512 | #endif | |
2513 | ||
2514 | flags |= INST_IMMEDIATE; | |
2515 | ||
2516 | if (inst.reloc.exp.X_add_symbol) | |
2517 | { | |
2518 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
2519 | inst.reloc.pc_rel = 0; | |
2520 | } | |
2521 | else | |
2522 | { | |
2523 | unsigned value = validate_immediate (inst.reloc.exp.X_add_number); | |
2524 | ||
2525 | if (value == (unsigned) FAIL) | |
2526 | { | |
2527 | inst.error = _("Invalid constant"); | |
2528 | return; | |
2529 | } | |
2530 | ||
2531 | inst.instruction |= value; | |
2532 | } | |
2533 | ||
2534 | inst.error = NULL; | |
2535 | inst.instruction |= flags; | |
2536 | end_of_line (str); | |
2537 | } | |
2538 | ||
2539 | /* Long Multiply Parser | |
2540 | UMULL RdLo, RdHi, Rm, Rs | |
2541 | SMULL RdLo, RdHi, Rm, Rs | |
2542 | UMLAL RdLo, RdHi, Rm, Rs | |
2543 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
2544 | ||
2545 | static void | |
2546 | do_mull (str, flags) | |
2547 | char * str; | |
2548 | unsigned long flags; | |
2549 | { | |
2550 | int rdlo, rdhi, rm, rs; | |
2551 | ||
2552 | /* Only one format "rdlo, rdhi, rm, rs". */ | |
2553 | skip_whitespace (str); | |
2554 | ||
2555 | if ((rdlo = reg_required_here (&str, 12)) == FAIL) | |
2556 | { | |
2557 | inst.error = BAD_ARGS; | |
2558 | return; | |
2559 | } | |
2560 | ||
2561 | if (skip_past_comma (&str) == FAIL | |
2562 | || (rdhi = reg_required_here (&str, 16)) == FAIL) | |
2563 | { | |
2564 | inst.error = BAD_ARGS; | |
2565 | return; | |
2566 | } | |
2567 | ||
2568 | if (skip_past_comma (&str) == FAIL | |
2569 | || (rm = reg_required_here (&str, 0)) == FAIL) | |
2570 | { | |
2571 | inst.error = BAD_ARGS; | |
2572 | return; | |
2573 | } | |
2574 | ||
2575 | /* rdhi, rdlo and rm must all be different. */ | |
2576 | if (rdlo == rdhi || rdlo == rm || rdhi == rm) | |
2577 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
2578 | ||
2579 | if (skip_past_comma (&str) == FAIL | |
2580 | || (rs = reg_required_here (&str, 8)) == FAIL) | |
2581 | { | |
2582 | inst.error = BAD_ARGS; | |
2583 | return; | |
2584 | } | |
2585 | ||
2586 | if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC) | |
2587 | { | |
2588 | inst.error = BAD_PC; | |
2589 | return; | |
2590 | } | |
2591 | ||
2592 | inst.instruction |= flags; | |
2593 | end_of_line (str); | |
2594 | return; | |
2595 | } | |
2596 | ||
2597 | static void | |
2598 | do_mul (str, flags) | |
2599 | char * str; | |
2600 | unsigned long flags; | |
2601 | { | |
2602 | int rd, rm; | |
2603 | ||
2604 | /* Only one format "rd, rm, rs". */ | |
2605 | skip_whitespace (str); | |
2606 | ||
2607 | if ((rd = reg_required_here (&str, 16)) == FAIL) | |
2608 | { | |
2609 | inst.error = BAD_ARGS; | |
2610 | return; | |
2611 | } | |
2612 | ||
2613 | if (rd == REG_PC) | |
2614 | { | |
2615 | inst.error = BAD_PC; | |
2616 | return; | |
2617 | } | |
2618 | ||
2619 | if (skip_past_comma (&str) == FAIL | |
2620 | || (rm = reg_required_here (&str, 0)) == FAIL) | |
2621 | { | |
2622 | inst.error = BAD_ARGS; | |
2623 | return; | |
2624 | } | |
2625 | ||
2626 | if (rm == REG_PC) | |
2627 | { | |
2628 | inst.error = BAD_PC; | |
2629 | return; | |
2630 | } | |
2631 | ||
2632 | if (rm == rd) | |
2633 | as_tsktsk (_("rd and rm should be different in mul")); | |
2634 | ||
2635 | if (skip_past_comma (&str) == FAIL | |
2636 | || (rm = reg_required_here (&str, 8)) == FAIL) | |
2637 | { | |
2638 | inst.error = BAD_ARGS; | |
2639 | return; | |
2640 | } | |
2641 | ||
2642 | if (rm == REG_PC) | |
2643 | { | |
2644 | inst.error = BAD_PC; | |
2645 | return; | |
2646 | } | |
2647 | ||
2648 | inst.instruction |= flags; | |
2649 | end_of_line (str); | |
2650 | return; | |
2651 | } | |
2652 | ||
2653 | static void | |
2654 | do_mla (str, flags) | |
2655 | char * str; | |
2656 | unsigned long flags; | |
2657 | { | |
2658 | int rd, rm; | |
2659 | ||
2660 | /* Only one format "rd, rm, rs, rn". */ | |
2661 | skip_whitespace (str); | |
2662 | ||
2663 | if ((rd = reg_required_here (&str, 16)) == FAIL) | |
2664 | { | |
2665 | inst.error = BAD_ARGS; | |
2666 | return; | |
2667 | } | |
2668 | ||
2669 | if (rd == REG_PC) | |
2670 | { | |
2671 | inst.error = BAD_PC; | |
2672 | return; | |
2673 | } | |
2674 | ||
2675 | if (skip_past_comma (&str) == FAIL | |
2676 | || (rm = reg_required_here (&str, 0)) == FAIL) | |
2677 | { | |
2678 | inst.error = BAD_ARGS; | |
2679 | return; | |
2680 | } | |
2681 | ||
2682 | if (rm == REG_PC) | |
2683 | { | |
2684 | inst.error = BAD_PC; | |
2685 | return; | |
2686 | } | |
2687 | ||
2688 | if (rm == rd) | |
2689 | as_tsktsk (_("rd and rm should be different in mla")); | |
2690 | ||
2691 | if (skip_past_comma (&str) == FAIL | |
2692 | || (rd = reg_required_here (&str, 8)) == FAIL | |
2693 | || skip_past_comma (&str) == FAIL | |
2694 | || (rm = reg_required_here (&str, 12)) == FAIL) | |
2695 | { | |
2696 | inst.error = BAD_ARGS; | |
2697 | return; | |
2698 | } | |
2699 | ||
2700 | if (rd == REG_PC || rm == REG_PC) | |
2701 | { | |
2702 | inst.error = BAD_PC; | |
2703 | return; | |
2704 | } | |
2705 | ||
2706 | inst.instruction |= flags; | |
2707 | end_of_line (str); | |
2708 | return; | |
2709 | } | |
2710 | ||
2711 | /* Expects *str -> the characters "acc0", possibly with leading blanks. | |
2712 | Advances *str to the next non-alphanumeric. | |
2713 | Returns 0, or else FAIL (in which case sets inst.error). | |
2714 | ||
2715 | (In a future XScale, there may be accumulators other than zero. | |
2716 | At that time this routine and its callers can be upgraded to suit.) */ | |
2717 | ||
2718 | static int | |
2719 | accum0_required_here (str) | |
2720 | char ** str; | |
2721 | { | |
2722 | static char buff [128]; /* Note the address is taken. Hence, static. */ | |
2723 | char * p = * str; | |
2724 | char c; | |
2725 | int result = 0; /* The accum number. */ | |
2726 | ||
2727 | skip_whitespace (p); | |
2728 | ||
2729 | *str = p; /* Advance caller's string pointer too. */ | |
2730 | c = *p++; | |
3882b010 | 2731 | while (ISALNUM (c)) |
b99bd4ef NC |
2732 | c = *p++; |
2733 | ||
2734 | *--p = 0; /* Aap nul into input buffer at non-alnum. */ | |
2735 | ||
2736 | if (! ( streq (*str, "acc0") || streq (*str, "ACC0"))) | |
2737 | { | |
2738 | sprintf (buff, _("acc0 expected, not '%.100s'"), *str); | |
2739 | inst.error = buff; | |
2740 | result = FAIL; | |
2741 | } | |
2742 | ||
2743 | *p = c; /* Unzap. */ | |
2744 | *str = p; /* Caller's string pointer to after match. */ | |
2745 | return result; | |
2746 | } | |
2747 | ||
2748 | /* Expects **str -> after a comma. May be leading blanks. | |
2749 | Advances *str, recognizing a load mode, and setting inst.instruction. | |
2750 | Returns rn, or else FAIL (in which case may set inst.error | |
2751 | and not advance str) | |
2752 | ||
2753 | Note: doesn't know Rd, so no err checks that require such knowledge. */ | |
2754 | ||
2755 | static int | |
2756 | ld_mode_required_here (string) | |
2757 | char ** string; | |
2758 | { | |
2759 | char * str = * string; | |
2760 | int rn; | |
2761 | int pre_inc = 0; | |
2762 | ||
2763 | skip_whitespace (str); | |
2764 | ||
2765 | if (* str == '[') | |
2766 | { | |
2767 | str++; | |
2768 | ||
2769 | skip_whitespace (str); | |
2770 | ||
2771 | if ((rn = reg_required_here (& str, 16)) == FAIL) | |
2772 | return FAIL; | |
2773 | ||
2774 | skip_whitespace (str); | |
2775 | ||
2776 | if (* str == ']') | |
2777 | { | |
2778 | str ++; | |
2779 | ||
2780 | if (skip_past_comma (& str) == SUCCESS) | |
2781 | { | |
2782 | /* [Rn],... (post inc) */ | |
2783 | if (ldst_extend (& str, 1) == FAIL) | |
2784 | return FAIL; | |
2785 | } | |
2786 | else /* [Rn] */ | |
2787 | { | |
2788 | skip_whitespace (str); | |
2789 | ||
2790 | if (* str == '!') | |
2791 | { | |
2792 | str ++; | |
2793 | inst.instruction |= WRITE_BACK; | |
2794 | } | |
2795 | ||
2796 | inst.instruction |= INDEX_UP | HWOFFSET_IMM; | |
2797 | pre_inc = 1; | |
2798 | } | |
2799 | } | |
2800 | else /* [Rn,...] */ | |
2801 | { | |
2802 | if (skip_past_comma (& str) == FAIL) | |
2803 | { | |
2804 | inst.error = _("pre-indexed expression expected"); | |
2805 | return FAIL; | |
2806 | } | |
2807 | ||
2808 | pre_inc = 1; | |
2809 | ||
2810 | if (ldst_extend (& str, 1) == FAIL) | |
2811 | return FAIL; | |
2812 | ||
2813 | skip_whitespace (str); | |
2814 | ||
2815 | if (* str ++ != ']') | |
2816 | { | |
2817 | inst.error = _("missing ]"); | |
2818 | return FAIL; | |
2819 | } | |
2820 | ||
2821 | skip_whitespace (str); | |
2822 | ||
2823 | if (* str == '!') | |
2824 | { | |
2825 | str ++; | |
2826 | inst.instruction |= WRITE_BACK; | |
2827 | } | |
2828 | } | |
2829 | } | |
2830 | else if (* str == '=') /* ldr's "r,=label" syntax */ | |
2831 | /* We should never reach here, because <text> = <expression> is | |
2832 | caught gas/read.c read_a_source_file() as a .set operation. */ | |
2833 | return FAIL; | |
2834 | else /* PC +- 8 bit immediate offset. */ | |
2835 | { | |
2836 | if (my_get_expression (& inst.reloc.exp, & str)) | |
2837 | return FAIL; | |
2838 | ||
2839 | inst.instruction |= HWOFFSET_IMM; /* The I bit. */ | |
2840 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
2841 | inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */ | |
2842 | inst.reloc.pc_rel = 1; | |
2843 | inst.instruction |= (REG_PC << 16); | |
2844 | ||
2845 | rn = REG_PC; | |
2846 | pre_inc = 1; | |
2847 | } | |
2848 | ||
2849 | inst.instruction |= (pre_inc ? PRE_INDEX : 0); | |
2850 | * string = str; | |
2851 | ||
2852 | return rn; | |
2853 | } | |
2854 | ||
2855 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) | |
2856 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
2857 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
2858 | Error if any register is R15. */ | |
2859 | ||
2860 | static void | |
2861 | do_smla (str, flags) | |
2862 | char * str; | |
2863 | unsigned long flags; | |
2864 | { | |
2865 | int rd, rm, rs, rn; | |
2866 | ||
2867 | skip_whitespace (str); | |
2868 | ||
2869 | if ((rd = reg_required_here (& str, 16)) == FAIL | |
2870 | || skip_past_comma (& str) == FAIL | |
2871 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2872 | || skip_past_comma (& str) == FAIL | |
2873 | || (rs = reg_required_here (& str, 8)) == FAIL | |
2874 | || skip_past_comma (& str) == FAIL | |
2875 | || (rn = reg_required_here (& str, 12)) == FAIL) | |
2876 | inst.error = BAD_ARGS; | |
2877 | ||
2878 | else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC) | |
2879 | inst.error = BAD_PC; | |
2880 | ||
2881 | else if (flags) | |
2882 | inst.error = BAD_FLAGS; | |
2883 | ||
2884 | else | |
2885 | end_of_line (str); | |
2886 | } | |
2887 | ||
2888 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) | |
2889 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
2890 | Error if any register is R15. | |
2891 | Warning if Rdlo == Rdhi. */ | |
2892 | ||
2893 | static void | |
2894 | do_smlal (str, flags) | |
2895 | char * str; | |
2896 | unsigned long flags; | |
2897 | { | |
2898 | int rdlo, rdhi, rm, rs; | |
2899 | ||
2900 | skip_whitespace (str); | |
2901 | ||
2902 | if ((rdlo = reg_required_here (& str, 12)) == FAIL | |
2903 | || skip_past_comma (& str) == FAIL | |
2904 | || (rdhi = reg_required_here (& str, 16)) == FAIL | |
2905 | || skip_past_comma (& str) == FAIL | |
2906 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2907 | || skip_past_comma (& str) == FAIL | |
2908 | || (rs = reg_required_here (& str, 8)) == FAIL) | |
2909 | { | |
2910 | inst.error = BAD_ARGS; | |
2911 | return; | |
2912 | } | |
2913 | ||
2914 | if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC) | |
2915 | { | |
2916 | inst.error = BAD_PC; | |
2917 | return; | |
2918 | } | |
2919 | ||
2920 | if (rdlo == rdhi) | |
2921 | as_tsktsk (_("rdhi and rdlo must be different")); | |
2922 | ||
2923 | if (flags) | |
2924 | inst.error = BAD_FLAGS; | |
2925 | else | |
2926 | end_of_line (str); | |
2927 | } | |
2928 | ||
2929 | /* ARM V5E (El Segundo) signed-multiply (argument parse) | |
2930 | SMULxy{cond} Rd,Rm,Rs | |
2931 | Error if any register is R15. */ | |
2932 | ||
2933 | static void | |
2934 | do_smul (str, flags) | |
2935 | char * str; | |
2936 | unsigned long flags; | |
2937 | { | |
2938 | int rd, rm, rs; | |
2939 | ||
2940 | skip_whitespace (str); | |
2941 | ||
2942 | if ((rd = reg_required_here (& str, 16)) == FAIL | |
2943 | || skip_past_comma (& str) == FAIL | |
2944 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2945 | || skip_past_comma (& str) == FAIL | |
2946 | || (rs = reg_required_here (& str, 8)) == FAIL) | |
2947 | inst.error = BAD_ARGS; | |
2948 | ||
2949 | else if (rd == REG_PC || rm == REG_PC || rs == REG_PC) | |
2950 | inst.error = BAD_PC; | |
2951 | ||
2952 | else if (flags) | |
2953 | inst.error = BAD_FLAGS; | |
2954 | ||
2955 | else | |
2956 | end_of_line (str); | |
2957 | } | |
2958 | ||
2959 | /* ARM V5E (El Segundo) saturating-add/subtract (argument parse) | |
2960 | Q[D]{ADD,SUB}{cond} Rd,Rm,Rn | |
2961 | Error if any register is R15. */ | |
2962 | ||
2963 | static void | |
2964 | do_qadd (str, flags) | |
2965 | char * str; | |
2966 | unsigned long flags; | |
2967 | { | |
2968 | int rd, rm, rn; | |
2969 | ||
2970 | skip_whitespace (str); | |
2971 | ||
2972 | if ((rd = reg_required_here (& str, 12)) == FAIL | |
2973 | || skip_past_comma (& str) == FAIL | |
2974 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2975 | || skip_past_comma (& str) == FAIL | |
2976 | || (rn = reg_required_here (& str, 16)) == FAIL) | |
2977 | inst.error = BAD_ARGS; | |
2978 | ||
2979 | else if (rd == REG_PC || rm == REG_PC || rn == REG_PC) | |
2980 | inst.error = BAD_PC; | |
2981 | ||
2982 | else if (flags) | |
2983 | inst.error = BAD_FLAGS; | |
2984 | ||
2985 | else | |
2986 | end_of_line (str); | |
2987 | } | |
2988 | ||
2989 | /* ARM V5E (el Segundo) | |
2990 | MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
2991 | MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
2992 | ||
2993 | These are equivalent to the XScale instructions MAR and MRA, | |
2994 | respectively, when coproc == 0, opcode == 0, and CRm == 0. | |
2995 | ||
2996 | Result unpredicatable if Rd or Rn is R15. */ | |
2997 | ||
2998 | static void | |
2999 | do_co_reg2c (str, flags) | |
3000 | char * str; | |
3001 | unsigned long flags; | |
3002 | { | |
3003 | int rd, rn; | |
3004 | ||
3005 | skip_whitespace (str); | |
3006 | ||
3007 | if (co_proc_number (& str) == FAIL) | |
3008 | { | |
3009 | if (!inst.error) | |
3010 | inst.error = BAD_ARGS; | |
3011 | return; | |
3012 | } | |
3013 | ||
3014 | if (skip_past_comma (& str) == FAIL | |
3015 | || cp_opc_expr (& str, 4, 4) == FAIL) | |
3016 | { | |
3017 | if (!inst.error) | |
3018 | inst.error = BAD_ARGS; | |
3019 | return; | |
3020 | } | |
3021 | ||
3022 | if (skip_past_comma (& str) == FAIL | |
3023 | || (rd = reg_required_here (& str, 12)) == FAIL) | |
3024 | { | |
3025 | if (!inst.error) | |
3026 | inst.error = BAD_ARGS; | |
3027 | return; | |
3028 | } | |
3029 | ||
3030 | if (skip_past_comma (& str) == FAIL | |
3031 | || (rn = reg_required_here (& str, 16)) == FAIL) | |
3032 | { | |
3033 | if (!inst.error) | |
3034 | inst.error = BAD_ARGS; | |
3035 | return; | |
3036 | } | |
3037 | ||
3038 | /* Unpredictable result if rd or rn is R15. */ | |
3039 | if (rd == REG_PC || rn == REG_PC) | |
3040 | as_tsktsk | |
3041 | (_("Warning: Instruction unpredictable when using r15")); | |
3042 | ||
3043 | if (skip_past_comma (& str) == FAIL | |
3044 | || cp_reg_required_here (& str, 0) == FAIL) | |
3045 | { | |
3046 | if (!inst.error) | |
3047 | inst.error = BAD_ARGS; | |
3048 | return; | |
3049 | } | |
3050 | ||
3051 | if (flags) | |
3052 | inst.error = BAD_COND; | |
3053 | ||
3054 | end_of_line (str); | |
3055 | } | |
3056 | ||
3057 | /* ARM V5 count-leading-zeroes instruction (argument parse) | |
3058 | CLZ{<cond>} <Rd>, <Rm> | |
3059 | Condition defaults to COND_ALWAYS. | |
3060 | Error if Rd or Rm are R15. */ | |
3061 | ||
3062 | static void | |
3063 | do_clz (str, flags) | |
3064 | char * str; | |
3065 | unsigned long flags; | |
3066 | { | |
3067 | int rd, rm; | |
3068 | ||
3069 | if (flags) | |
3070 | { | |
3071 | as_bad (BAD_FLAGS); | |
3072 | return; | |
3073 | } | |
3074 | ||
3075 | skip_whitespace (str); | |
3076 | ||
3077 | if (((rd = reg_required_here (& str, 12)) == FAIL) | |
3078 | || (skip_past_comma (& str) == FAIL) | |
3079 | || ((rm = reg_required_here (& str, 0)) == FAIL)) | |
3080 | inst.error = BAD_ARGS; | |
3081 | ||
3082 | else if (rd == REG_PC || rm == REG_PC ) | |
3083 | inst.error = BAD_PC; | |
3084 | ||
3085 | else | |
3086 | end_of_line (str); | |
3087 | } | |
3088 | ||
3089 | /* ARM V5 (argument parse) | |
3090 | LDC2{L} <coproc>, <CRd>, <addressing mode> | |
3091 | STC2{L} <coproc>, <CRd>, <addressing mode> | |
3092 | Instruction is not conditional, and has 0xf in the codition field. | |
3093 | Otherwise, it's the same as LDC/STC. */ | |
3094 | ||
3095 | static void | |
3096 | do_lstc2 (str, flags) | |
3097 | char * str; | |
3098 | unsigned long flags; | |
3099 | { | |
3100 | if (flags) | |
3101 | inst.error = BAD_COND; | |
3102 | ||
3103 | skip_whitespace (str); | |
3104 | ||
3105 | if (co_proc_number (& str) == FAIL) | |
3106 | { | |
3107 | if (!inst.error) | |
3108 | inst.error = BAD_ARGS; | |
3109 | } | |
3110 | else if (skip_past_comma (& str) == FAIL | |
3111 | || cp_reg_required_here (& str, 12) == FAIL) | |
3112 | { | |
3113 | if (!inst.error) | |
3114 | inst.error = BAD_ARGS; | |
3115 | } | |
3116 | else if (skip_past_comma (& str) == FAIL | |
3117 | || cp_address_required_here (& str) == FAIL) | |
3118 | { | |
3119 | if (! inst.error) | |
3120 | inst.error = BAD_ARGS; | |
3121 | } | |
3122 | else | |
3123 | end_of_line (str); | |
3124 | } | |
3125 | ||
3126 | /* ARM V5 (argument parse) | |
3127 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2> | |
3128 | Instruction is not conditional, and has 0xf in the condition field. | |
3129 | Otherwise, it's the same as CDP. */ | |
3130 | ||
3131 | static void | |
3132 | do_cdp2 (str, flags) | |
3133 | char * str; | |
3134 | unsigned long flags; | |
3135 | { | |
3136 | skip_whitespace (str); | |
3137 | ||
3138 | if (co_proc_number (& str) == FAIL) | |
3139 | { | |
3140 | if (!inst.error) | |
3141 | inst.error = BAD_ARGS; | |
3142 | return; | |
3143 | } | |
3144 | ||
3145 | if (skip_past_comma (& str) == FAIL | |
3146 | || cp_opc_expr (& str, 20,4) == FAIL) | |
3147 | { | |
3148 | if (!inst.error) | |
3149 | inst.error = BAD_ARGS; | |
3150 | return; | |
3151 | } | |
3152 | ||
3153 | if (skip_past_comma (& str) == FAIL | |
3154 | || cp_reg_required_here (& str, 12) == FAIL) | |
3155 | { | |
3156 | if (!inst.error) | |
3157 | inst.error = BAD_ARGS; | |
3158 | return; | |
3159 | } | |
3160 | ||
3161 | if (skip_past_comma (& str) == FAIL | |
3162 | || cp_reg_required_here (& str, 16) == FAIL) | |
3163 | { | |
3164 | if (!inst.error) | |
3165 | inst.error = BAD_ARGS; | |
3166 | return; | |
3167 | } | |
3168 | ||
3169 | if (skip_past_comma (& str) == FAIL | |
3170 | || cp_reg_required_here (& str, 0) == FAIL) | |
3171 | { | |
3172 | if (!inst.error) | |
3173 | inst.error = BAD_ARGS; | |
3174 | return; | |
3175 | } | |
3176 | ||
3177 | if (skip_past_comma (& str) == SUCCESS) | |
3178 | { | |
3179 | if (cp_opc_expr (& str, 5, 3) == FAIL) | |
3180 | { | |
3181 | if (!inst.error) | |
3182 | inst.error = BAD_ARGS; | |
3183 | return; | |
3184 | } | |
3185 | } | |
3186 | ||
3187 | if (flags) | |
3188 | inst.error = BAD_FLAGS; | |
3189 | ||
3190 | end_of_line (str); | |
3191 | } | |
3192 | ||
3193 | /* ARM V5 (argument parse) | |
3194 | MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2> | |
3195 | MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2> | |
3196 | Instruction is not conditional, and has 0xf in the condition field. | |
3197 | Otherwise, it's the same as MCR/MRC. */ | |
3198 | ||
3199 | static void | |
3200 | do_co_reg2 (str, flags) | |
3201 | char * str; | |
3202 | unsigned long flags; | |
3203 | { | |
3204 | skip_whitespace (str); | |
3205 | ||
3206 | if (co_proc_number (& str) == FAIL) | |
3207 | { | |
3208 | if (!inst.error) | |
3209 | inst.error = BAD_ARGS; | |
3210 | return; | |
3211 | } | |
3212 | ||
3213 | if (skip_past_comma (& str) == FAIL | |
3214 | || cp_opc_expr (& str, 21, 3) == FAIL) | |
3215 | { | |
3216 | if (!inst.error) | |
3217 | inst.error = BAD_ARGS; | |
3218 | return; | |
3219 | } | |
3220 | ||
3221 | if (skip_past_comma (& str) == FAIL | |
3222 | || reg_required_here (& str, 12) == FAIL) | |
3223 | { | |
3224 | if (!inst.error) | |
3225 | inst.error = BAD_ARGS; | |
3226 | return; | |
3227 | } | |
3228 | ||
3229 | if (skip_past_comma (& str) == FAIL | |
3230 | || cp_reg_required_here (& str, 16) == FAIL) | |
3231 | { | |
3232 | if (!inst.error) | |
3233 | inst.error = BAD_ARGS; | |
3234 | return; | |
3235 | } | |
3236 | ||
3237 | if (skip_past_comma (& str) == FAIL | |
3238 | || cp_reg_required_here (& str, 0) == FAIL) | |
3239 | { | |
3240 | if (!inst.error) | |
3241 | inst.error = BAD_ARGS; | |
3242 | return; | |
3243 | } | |
3244 | ||
3245 | if (skip_past_comma (& str) == SUCCESS) | |
3246 | { | |
3247 | if (cp_opc_expr (& str, 5, 3) == FAIL) | |
3248 | { | |
3249 | if (!inst.error) | |
3250 | inst.error = BAD_ARGS; | |
3251 | return; | |
3252 | } | |
3253 | } | |
3254 | ||
3255 | if (flags) | |
3256 | inst.error = BAD_COND; | |
3257 | ||
3258 | end_of_line (str); | |
3259 | } | |
3260 | ||
3261 | /* THUMB V5 breakpoint instruction (argument parse) | |
3262 | BKPT <immed_8>. */ | |
3263 | ||
3264 | static void | |
3265 | do_t_bkpt (str) | |
3266 | char * str; | |
3267 | { | |
3268 | expressionS expr; | |
3269 | unsigned long number; | |
3270 | ||
3271 | skip_whitespace (str); | |
3272 | ||
3273 | /* Allow optional leading '#'. */ | |
3274 | if (is_immediate_prefix (*str)) | |
3275 | str ++; | |
3276 | ||
3277 | memset (& expr, '\0', sizeof (expr)); | |
3278 | if (my_get_expression (& expr, & str) || (expr.X_op != O_constant)) | |
3279 | { | |
3280 | inst.error = _("bad or missing expression"); | |
3281 | return; | |
3282 | } | |
3283 | ||
3284 | number = expr.X_add_number; | |
3285 | ||
3286 | /* Check it fits an 8 bit unsigned. */ | |
3287 | if (number != (number & 0xff)) | |
3288 | { | |
3289 | inst.error = _("immediate value out of range"); | |
3290 | return; | |
3291 | } | |
3292 | ||
3293 | inst.instruction |= number; | |
3294 | ||
3295 | end_of_line (str); | |
3296 | } | |
3297 | ||
3298 | /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only. | |
3299 | Expects inst.instruction is set for BLX(1). | |
3300 | Note: this is cloned from do_branch, and the reloc changed to be a | |
3301 | new one that can cope with setting one extra bit (the H bit). */ | |
3302 | ||
3303 | static void | |
3304 | do_branch25 (str, flags) | |
3305 | char * str; | |
3306 | unsigned long flags ATTRIBUTE_UNUSED; | |
3307 | { | |
3308 | if (my_get_expression (& inst.reloc.exp, & str)) | |
3309 | return; | |
3310 | ||
3311 | #ifdef OBJ_ELF | |
3312 | { | |
3313 | char * save_in; | |
3314 | ||
3315 | /* ScottB: February 5, 1998 */ | |
3316 | /* Check to see of PLT32 reloc required for the instruction. */ | |
3317 | ||
3318 | /* arm_parse_reloc() works on input_line_pointer. | |
3319 | We actually want to parse the operands to the branch instruction | |
3320 | passed in 'str'. Save the input pointer and restore it later. */ | |
3321 | save_in = input_line_pointer; | |
3322 | input_line_pointer = str; | |
3323 | ||
3324 | if (inst.reloc.exp.X_op == O_symbol | |
3325 | && *str == '(' | |
3326 | && arm_parse_reloc () == BFD_RELOC_ARM_PLT32) | |
3327 | { | |
3328 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
3329 | inst.reloc.pc_rel = 0; | |
3330 | /* Modify str to point to after parsed operands, otherwise | |
3331 | end_of_line() will complain about the (PLT) left in str. */ | |
3332 | str = input_line_pointer; | |
3333 | } | |
3334 | else | |
3335 | { | |
3336 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX; | |
3337 | inst.reloc.pc_rel = 1; | |
3338 | } | |
3339 | ||
3340 | input_line_pointer = save_in; | |
3341 | } | |
3342 | #else | |
3343 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX; | |
3344 | inst.reloc.pc_rel = 1; | |
3345 | #endif /* OBJ_ELF */ | |
3346 | ||
3347 | end_of_line (str); | |
3348 | } | |
3349 | ||
3350 | /* ARM V5 branch-link-exchange instruction (argument parse) | |
3351 | BLX <target_addr> ie BLX(1) | |
3352 | BLX{<condition>} <Rm> ie BLX(2) | |
3353 | Unfortunately, there are two different opcodes for this mnemonic. | |
3354 | So, the insns[].value is not used, and the code here zaps values | |
3355 | into inst.instruction. | |
3356 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
3357 | ||
3358 | static void | |
3359 | do_blx (str, flags) | |
3360 | char * str; | |
3361 | unsigned long flags; | |
3362 | { | |
3363 | char * mystr = str; | |
3364 | int rm; | |
3365 | ||
3366 | if (flags) | |
3367 | { | |
3368 | as_bad (BAD_FLAGS); | |
3369 | return; | |
3370 | } | |
3371 | ||
3372 | skip_whitespace (mystr); | |
3373 | rm = reg_required_here (& mystr, 0); | |
3374 | ||
3375 | /* The above may set inst.error. Ignore his opinion. */ | |
3376 | inst.error = 0; | |
3377 | ||
3378 | if (rm != FAIL) | |
3379 | { | |
3380 | /* Arg is a register. | |
3381 | Use the condition code our caller put in inst.instruction. | |
3382 | Pass ourselves off as a BX with a funny opcode. */ | |
3383 | inst.instruction |= 0x012fff30; | |
3384 | do_bx (str, flags); | |
3385 | } | |
3386 | else | |
3387 | { | |
3388 | /* This must be is BLX <target address>, no condition allowed. */ | |
3389 | if (inst.instruction != COND_ALWAYS) | |
3390 | { | |
3391 | inst.error = BAD_COND; | |
3392 | return; | |
3393 | } | |
3394 | ||
3395 | inst.instruction = 0xfafffffe; | |
3396 | ||
3397 | /* Process like a B/BL, but with a different reloc. | |
3398 | Note that B/BL expecte fffffe, not 0, offset in the opcode table. */ | |
3399 | do_branch25 (str, flags); | |
3400 | } | |
3401 | } | |
3402 | ||
3403 | /* ARM V5 Thumb BLX (argument parse) | |
3404 | BLX <target_addr> which is BLX(1) | |
3405 | BLX <Rm> which is BLX(2) | |
3406 | Unfortunately, there are two different opcodes for this mnemonic. | |
3407 | So, the tinsns[].value is not used, and the code here zaps values | |
3408 | into inst.instruction. */ | |
3409 | ||
3410 | static void | |
3411 | do_t_blx (str) | |
3412 | char * str; | |
3413 | { | |
3414 | char * mystr = str; | |
3415 | int rm; | |
3416 | ||
3417 | skip_whitespace (mystr); | |
3418 | inst.instruction = 0x4780; | |
3419 | ||
3420 | /* Note that this call is to the ARM register recognizer. BLX(2) | |
3421 | uses the ARM register space, not the Thumb one, so a call to | |
3422 | thumb_reg() would be wrong. */ | |
3423 | rm = reg_required_here (& mystr, 3); | |
3424 | inst.error = 0; | |
3425 | ||
3426 | if (rm != FAIL) | |
3427 | { | |
3428 | /* It's BLX(2). The .instruction was zapped with rm & is final. */ | |
3429 | inst.size = 2; | |
3430 | } | |
3431 | else | |
3432 | { | |
3433 | /* No ARM register. This must be BLX(1). Change the .instruction. */ | |
3434 | inst.instruction = 0xf7ffeffe; | |
3435 | inst.size = 4; | |
3436 | ||
3437 | if (my_get_expression (& inst.reloc.exp, & mystr)) | |
3438 | return; | |
3439 | ||
3440 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; | |
3441 | inst.reloc.pc_rel = 1; | |
3442 | } | |
3443 | ||
3444 | end_of_line (mystr); | |
3445 | } | |
3446 | ||
3447 | /* ARM V5 breakpoint instruction (argument parse) | |
3448 | BKPT <16 bit unsigned immediate> | |
3449 | Instruction is not conditional. | |
3450 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
3451 | and it is an error if the caller tried to override that. | |
3452 | Note "flags" is nonzero if a flag was supplied (which is an error). */ | |
3453 | ||
3454 | static void | |
3455 | do_bkpt (str, flags) | |
3456 | char * str; | |
3457 | unsigned long flags; | |
3458 | { | |
3459 | expressionS expr; | |
3460 | unsigned long number; | |
3461 | ||
3462 | skip_whitespace (str); | |
3463 | ||
3464 | /* Allow optional leading '#'. */ | |
3465 | if (is_immediate_prefix (* str)) | |
3466 | str++; | |
3467 | ||
3468 | memset (& expr, '\0', sizeof (expr)); | |
3469 | ||
3470 | if (my_get_expression (& expr, & str) || (expr.X_op != O_constant)) | |
3471 | { | |
3472 | inst.error = _("bad or missing expression"); | |
3473 | return; | |
3474 | } | |
3475 | ||
3476 | number = expr.X_add_number; | |
3477 | ||
3478 | /* Check it fits a 16 bit unsigned. */ | |
3479 | if (number != (number & 0xffff)) | |
3480 | { | |
3481 | inst.error = _("immediate value out of range"); | |
3482 | return; | |
3483 | } | |
3484 | ||
3485 | /* Top 12 of 16 bits to bits 19:8. */ | |
3486 | inst.instruction |= (number & 0xfff0) << 4; | |
3487 | ||
3488 | /* Bottom 4 of 16 bits to bits 3:0. */ | |
3489 | inst.instruction |= number & 0xf; | |
3490 | ||
3491 | end_of_line (str); | |
3492 | ||
3493 | if (flags) | |
3494 | inst.error = BAD_FLAGS; | |
3495 | } | |
3496 | ||
3497 | /* Xscale multiply-accumulate (argument parse) | |
3498 | MIAcc acc0,Rm,Rs | |
3499 | MIAPHcc acc0,Rm,Rs | |
3500 | MIAxycc acc0,Rm,Rs. */ | |
3501 | ||
3502 | static void | |
3503 | do_mia (str, flags) | |
3504 | char * str; | |
3505 | unsigned long flags; | |
3506 | { | |
3507 | int rs; | |
3508 | int rm; | |
3509 | ||
3510 | if (flags) | |
3511 | as_bad (BAD_FLAGS); | |
3512 | ||
3513 | else if (accum0_required_here (& str) == FAIL) | |
3514 | inst.error = ERR_NO_ACCUM; | |
3515 | ||
3516 | else if (skip_past_comma (& str) == FAIL | |
3517 | || (rm = reg_required_here (& str, 0)) == FAIL) | |
3518 | inst.error = BAD_ARGS; | |
3519 | ||
3520 | else if (skip_past_comma (& str) == FAIL | |
3521 | || (rs = reg_required_here (& str, 12)) == FAIL) | |
3522 | inst.error = BAD_ARGS; | |
3523 | ||
3524 | /* inst.instruction has now been zapped with both rm and rs. */ | |
3525 | else if (rm == REG_PC || rs == REG_PC) | |
3526 | inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */ | |
3527 | ||
3528 | else | |
3529 | end_of_line (str); | |
3530 | } | |
3531 | ||
3532 | /* Xscale move-accumulator-register (argument parse) | |
3533 | ||
3534 | MARcc acc0,RdLo,RdHi. */ | |
3535 | ||
3536 | static void | |
3537 | do_mar (str, flags) | |
3538 | char * str; | |
3539 | unsigned long flags; | |
3540 | { | |
3541 | int rdlo, rdhi; | |
3542 | ||
3543 | if (flags) | |
3544 | as_bad (BAD_FLAGS); | |
3545 | ||
3546 | else if (accum0_required_here (& str) == FAIL) | |
3547 | inst.error = ERR_NO_ACCUM; | |
3548 | ||
3549 | else if (skip_past_comma (& str) == FAIL | |
3550 | || (rdlo = reg_required_here (& str, 12)) == FAIL) | |
3551 | inst.error = BAD_ARGS; | |
3552 | ||
3553 | else if (skip_past_comma (& str) == FAIL | |
3554 | || (rdhi = reg_required_here (& str, 16)) == FAIL) | |
3555 | inst.error = BAD_ARGS; | |
3556 | ||
3557 | /* inst.instruction has now been zapped with both rdlo and rdhi. */ | |
3558 | else if (rdlo == REG_PC || rdhi == REG_PC) | |
3559 | inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */ | |
3560 | ||
3561 | else | |
3562 | end_of_line (str); | |
3563 | } | |
3564 | ||
3565 | /* Xscale move-register-accumulator (argument parse) | |
3566 | ||
3567 | MRAcc RdLo,RdHi,acc0. */ | |
3568 | ||
3569 | static void | |
3570 | do_mra (str, flags) | |
3571 | char * str; | |
3572 | unsigned long flags; | |
3573 | { | |
3574 | int rdlo; | |
3575 | int rdhi; | |
3576 | ||
3577 | if (flags) | |
3578 | { | |
3579 | as_bad (BAD_FLAGS); | |
3580 | return; | |
3581 | } | |
3582 | ||
3583 | skip_whitespace (str); | |
3584 | ||
3585 | if ((rdlo = reg_required_here (& str, 12)) == FAIL) | |
3586 | inst.error = BAD_ARGS; | |
3587 | ||
3588 | else if (skip_past_comma (& str) == FAIL | |
3589 | || (rdhi = reg_required_here (& str, 16)) == FAIL) | |
3590 | inst.error = BAD_ARGS; | |
3591 | ||
3592 | else if (skip_past_comma (& str) == FAIL | |
3593 | || accum0_required_here (& str) == FAIL) | |
3594 | inst.error = ERR_NO_ACCUM; | |
3595 | ||
3596 | /* inst.instruction has now been zapped with both rdlo and rdhi. */ | |
3597 | else if (rdlo == rdhi) | |
3598 | inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */ | |
3599 | ||
3600 | else if (rdlo == REG_PC || rdhi == REG_PC) | |
3601 | inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */ | |
3602 | else | |
3603 | end_of_line (str); | |
3604 | } | |
3605 | ||
c9b604bd | 3606 | /* ARMv5TE: Preload-Cache |
b99bd4ef NC |
3607 | |
3608 | PLD <addr_mode> | |
3609 | ||
3610 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
3611 | ||
3612 | static void | |
3613 | do_pld (str, flags) | |
3614 | char * str; | |
3615 | unsigned long flags; | |
3616 | { | |
3617 | int rd; | |
3618 | ||
3619 | if (flags) | |
3620 | { | |
3621 | as_bad (BAD_FLAGS); | |
3622 | return; | |
3623 | } | |
3624 | ||
3625 | skip_whitespace (str); | |
3626 | ||
3627 | if (* str != '[') | |
3628 | { | |
3629 | inst.error = _("'[' expected after PLD mnemonic"); | |
3630 | return; | |
3631 | } | |
3632 | ||
3633 | ++ str; | |
3634 | skip_whitespace (str); | |
3635 | ||
3636 | if ((rd = reg_required_here (& str, 16)) == FAIL) | |
3637 | return; | |
3638 | ||
3639 | skip_whitespace (str); | |
3640 | ||
3641 | if (* str == ']') | |
3642 | { | |
3643 | /* [Rn], ... ? */ | |
3644 | ++ str; | |
3645 | skip_whitespace (str); | |
3646 | ||
3647 | if (skip_past_comma (& str) == SUCCESS) | |
3648 | { | |
3649 | if (ldst_extend (& str, 0) == FAIL) | |
3650 | return; | |
3651 | } | |
3652 | else if (* str == '!') /* [Rn]! */ | |
3653 | { | |
3654 | inst.error = _("writeback used in preload instruction"); | |
3655 | ++ str; | |
3656 | } | |
3657 | else /* [Rn] */ | |
3658 | inst.instruction |= INDEX_UP | PRE_INDEX; | |
3659 | } | |
3660 | else /* [Rn, ...] */ | |
3661 | { | |
3662 | if (skip_past_comma (& str) == FAIL) | |
3663 | { | |
3664 | inst.error = _("pre-indexed expression expected"); | |
3665 | return; | |
3666 | } | |
3667 | ||
3668 | if (ldst_extend (& str, 0) == FAIL) | |
3669 | return; | |
3670 | ||
3671 | skip_whitespace (str); | |
3672 | ||
3673 | if (* str != ']') | |
3674 | { | |
3675 | inst.error = _("missing ]"); | |
3676 | return; | |
3677 | } | |
3678 | ||
3679 | ++ str; | |
3680 | skip_whitespace (str); | |
3681 | ||
3682 | if (* str == '!') /* [Rn]! */ | |
3683 | { | |
3684 | inst.error = _("writeback used in preload instruction"); | |
3685 | ++ str; | |
3686 | } | |
3687 | ||
3688 | inst.instruction |= PRE_INDEX; | |
3689 | } | |
3690 | ||
3691 | end_of_line (str); | |
3692 | } | |
3693 | ||
c9b604bd | 3694 | /* ARMv5TE load-consecutive (argument parse) |
b99bd4ef NC |
3695 | Mode is like LDRH. |
3696 | ||
3697 | LDRccD R, mode | |
3698 | STRccD R, mode. */ | |
3699 | ||
3700 | static void | |
3701 | do_ldrd (str, flags) | |
3702 | char * str; | |
3703 | unsigned long flags; | |
3704 | { | |
3705 | int rd; | |
3706 | int rn; | |
3707 | ||
3708 | if (flags != DOUBLE_LOAD_FLAG) | |
3709 | { | |
3710 | /* Change instruction pattern to normal ldr/str. */ | |
3711 | if (inst.instruction & 0x20) | |
3712 | inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */ | |
3713 | else | |
3714 | inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */ | |
3715 | ||
3716 | /* Perform a normal load/store instruction parse. */ | |
3717 | do_ldst (str, flags); | |
3718 | ||
3719 | return; | |
3720 | } | |
3721 | ||
3722 | if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE) | |
3723 | { | |
3724 | static char buff[128]; | |
3725 | ||
3726 | --str; | |
3882b010 | 3727 | while (ISSPACE (*str)) |
b99bd4ef NC |
3728 | --str; |
3729 | str -= 4; | |
3730 | ||
3731 | /* Deny all knowledge. */ | |
3732 | sprintf (buff, _("bad instruction '%.100s'"), str); | |
3733 | inst.error = buff; | |
3734 | return; | |
3735 | } | |
3736 | ||
3737 | skip_whitespace (str); | |
3738 | ||
3739 | if ((rd = reg_required_here (& str, 12)) == FAIL) | |
3740 | { | |
3741 | inst.error = BAD_ARGS; | |
3742 | return; | |
3743 | } | |
3744 | ||
3745 | if (skip_past_comma (& str) == FAIL | |
3746 | || (rn = ld_mode_required_here (& str)) == FAIL) | |
3747 | { | |
3748 | if (!inst.error) | |
3749 | inst.error = BAD_ARGS; | |
3750 | return; | |
3751 | } | |
3752 | ||
3753 | /* inst.instruction has now been zapped with Rd and the addressing mode. */ | |
3754 | if (rd & 1) /* Unpredictable result if Rd is odd. */ | |
3755 | { | |
3756 | inst.error = _("Destination register must be even"); | |
3757 | return; | |
3758 | } | |
3759 | ||
3760 | if (rd == REG_LR || rd == 12) | |
3761 | { | |
3762 | inst.error = _("r12 or r14 not allowed here"); | |
3763 | return; | |
3764 | } | |
3765 | ||
3766 | if (((rd == rn) || (rd + 1 == rn)) | |
3767 | && | |
3768 | ((inst.instruction & WRITE_BACK) | |
3769 | || (!(inst.instruction & PRE_INDEX)))) | |
3770 | as_warn (_("pre/post-indexing used when modified address register is destination")); | |
3771 | ||
3772 | end_of_line (str); | |
3773 | } | |
3774 | ||
3775 | /* Returns the index into fp_values of a floating point number, | |
3776 | or -1 if not in the table. */ | |
3777 | ||
3778 | static int | |
3779 | my_get_float_expression (str) | |
3780 | char ** str; | |
3781 | { | |
3782 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3783 | char * save_in; | |
3784 | expressionS exp; | |
3785 | int i; | |
3786 | int j; | |
3787 | ||
3788 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); | |
3789 | ||
3790 | /* Look for a raw floating point number. */ | |
3791 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
3792 | && is_end_of_line[(unsigned char) *save_in]) | |
3793 | { | |
3794 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3795 | { | |
3796 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
3797 | { | |
3798 | if (words[j] != fp_values[i][j]) | |
3799 | break; | |
3800 | } | |
3801 | ||
3802 | if (j == MAX_LITTLENUMS) | |
3803 | { | |
3804 | *str = save_in; | |
3805 | return i; | |
3806 | } | |
3807 | } | |
3808 | } | |
3809 | ||
3810 | /* Try and parse a more complex expression, this will probably fail | |
3811 | unless the code uses a floating point prefix (eg "0f"). */ | |
3812 | save_in = input_line_pointer; | |
3813 | input_line_pointer = *str; | |
3814 | if (expression (&exp) == absolute_section | |
3815 | && exp.X_op == O_big | |
3816 | && exp.X_add_number < 0) | |
3817 | { | |
3818 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
3819 | Ditto for 15. */ | |
3820 | if (gen_to_words (words, 5, (long) 15) == 0) | |
3821 | { | |
3822 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3823 | { | |
3824 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
3825 | { | |
3826 | if (words[j] != fp_values[i][j]) | |
3827 | break; | |
3828 | } | |
3829 | ||
3830 | if (j == MAX_LITTLENUMS) | |
3831 | { | |
3832 | *str = input_line_pointer; | |
3833 | input_line_pointer = save_in; | |
3834 | return i; | |
3835 | } | |
3836 | } | |
3837 | } | |
3838 | } | |
3839 | ||
3840 | *str = input_line_pointer; | |
3841 | input_line_pointer = save_in; | |
3842 | return -1; | |
3843 | } | |
3844 | ||
3845 | /* Return true if anything in the expression is a bignum. */ | |
3846 | ||
3847 | static int | |
3848 | walk_no_bignums (sp) | |
3849 | symbolS * sp; | |
3850 | { | |
3851 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
3852 | return 1; | |
3853 | ||
3854 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3855 | { | |
3856 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) | |
3857 | || (symbol_get_value_expression (sp)->X_op_symbol | |
3858 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3859 | } | |
3860 | ||
3861 | return 0; | |
3862 | } | |
3863 | ||
3864 | static int | |
3865 | my_get_expression (ep, str) | |
3866 | expressionS * ep; | |
3867 | char ** str; | |
3868 | { | |
3869 | char * save_in; | |
3870 | segT seg; | |
3871 | ||
3872 | save_in = input_line_pointer; | |
3873 | input_line_pointer = *str; | |
3874 | seg = expression (ep); | |
3875 | ||
3876 | #ifdef OBJ_AOUT | |
3877 | if (seg != absolute_section | |
3878 | && seg != text_section | |
3879 | && seg != data_section | |
3880 | && seg != bss_section | |
3881 | && seg != undefined_section) | |
3882 | { | |
3883 | inst.error = _("bad_segment"); | |
3884 | *str = input_line_pointer; | |
3885 | input_line_pointer = save_in; | |
3886 | return 1; | |
3887 | } | |
3888 | #endif | |
3889 | ||
3890 | /* Get rid of any bignums now, so that we don't generate an error for which | |
3891 | we can't establish a line number later on. Big numbers are never valid | |
3892 | in instructions, which is where this routine is always called. */ | |
3893 | if (ep->X_op == O_big | |
3894 | || (ep->X_add_symbol | |
3895 | && (walk_no_bignums (ep->X_add_symbol) | |
3896 | || (ep->X_op_symbol | |
3897 | && walk_no_bignums (ep->X_op_symbol))))) | |
3898 | { | |
3899 | inst.error = _("Invalid constant"); | |
3900 | *str = input_line_pointer; | |
3901 | input_line_pointer = save_in; | |
3902 | return 1; | |
3903 | } | |
3904 | ||
3905 | *str = input_line_pointer; | |
3906 | input_line_pointer = save_in; | |
3907 | return 0; | |
3908 | } | |
3909 | ||
3910 | /* UNRESTRICT should be one if <shift> <register> is permitted for this | |
3911 | instruction. */ | |
3912 | ||
3913 | static int | |
3914 | decode_shift (str, unrestrict) | |
3915 | char ** str; | |
3916 | int unrestrict; | |
3917 | { | |
3918 | const struct asm_shift_name * shift; | |
3919 | char * p; | |
3920 | char c; | |
3921 | ||
3922 | skip_whitespace (* str); | |
3923 | ||
3882b010 | 3924 | for (p = * str; ISALPHA (* p); p ++) |
b99bd4ef NC |
3925 | ; |
3926 | ||
3927 | if (p == * str) | |
3928 | { | |
3929 | inst.error = _("Shift expression expected"); | |
3930 | return FAIL; | |
3931 | } | |
3932 | ||
3933 | c = * p; | |
3934 | * p = '\0'; | |
3935 | shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str); | |
3936 | * p = c; | |
3937 | ||
3938 | if (shift == NULL) | |
3939 | { | |
3940 | inst.error = _("Shift expression expected"); | |
3941 | return FAIL; | |
3942 | } | |
3943 | ||
3944 | assert (shift->properties->index == shift_properties[shift->properties->index].index); | |
3945 | ||
3946 | if (shift->properties->index == SHIFT_RRX) | |
3947 | { | |
3948 | * str = p; | |
3949 | inst.instruction |= shift->properties->bit_field; | |
3950 | return SUCCESS; | |
3951 | } | |
3952 | ||
3953 | skip_whitespace (p); | |
3954 | ||
3955 | if (unrestrict && reg_required_here (& p, 8) != FAIL) | |
3956 | { | |
3957 | inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG; | |
3958 | * str = p; | |
3959 | return SUCCESS; | |
3960 | } | |
3961 | else if (! is_immediate_prefix (* p)) | |
3962 | { | |
3963 | inst.error = (unrestrict | |
3964 | ? _("shift requires register or #expression") | |
3965 | : _("shift requires #expression")); | |
3966 | * str = p; | |
3967 | return FAIL; | |
3968 | } | |
3969 | ||
3970 | inst.error = NULL; | |
3971 | p ++; | |
3972 | ||
3973 | if (my_get_expression (& inst.reloc.exp, & p)) | |
3974 | return FAIL; | |
3975 | ||
3976 | /* Validate some simple #expressions. */ | |
3977 | if (inst.reloc.exp.X_op == O_constant) | |
3978 | { | |
3979 | unsigned num = inst.reloc.exp.X_add_number; | |
3980 | ||
3981 | /* Reject operations greater than 32. */ | |
3982 | if (num > 32 | |
3983 | /* Reject a shift of 0 unless the mode allows it. */ | |
3984 | || (num == 0 && shift->properties->allows_0 == 0) | |
3985 | /* Reject a shift of 32 unless the mode allows it. */ | |
3986 | || (num == 32 && shift->properties->allows_32 == 0) | |
3987 | ) | |
3988 | { | |
3989 | /* As a special case we allow a shift of zero for | |
3990 | modes that do not support it to be recoded as an | |
3991 | logical shift left of zero (ie nothing). We warn | |
3992 | about this though. */ | |
3993 | if (num == 0) | |
3994 | { | |
3995 | as_warn (_("Shift of 0 ignored.")); | |
3996 | shift = & shift_names[0]; | |
3997 | assert (shift->properties->index == SHIFT_LSL); | |
3998 | } | |
3999 | else | |
4000 | { | |
4001 | inst.error = _("Invalid immediate shift"); | |
4002 | return FAIL; | |
4003 | } | |
4004 | } | |
4005 | ||
4006 | /* Shifts of 32 are encoded as 0, for those shifts that | |
4007 | support it. */ | |
4008 | if (num == 32) | |
4009 | num = 0; | |
4010 | ||
4011 | inst.instruction |= (num << 7) | shift->properties->bit_field; | |
4012 | } | |
4013 | else | |
4014 | { | |
4015 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
4016 | inst.reloc.pc_rel = 0; | |
4017 | inst.instruction |= shift->properties->bit_field; | |
4018 | } | |
4019 | ||
4020 | * str = p; | |
4021 | return SUCCESS; | |
4022 | } | |
4023 | ||
4024 | /* Do those data_ops which can take a negative immediate constant | |
4025 | by altering the instuction. A bit of a hack really. | |
4026 | MOV <-> MVN | |
4027 | AND <-> BIC | |
4028 | ADC <-> SBC | |
4029 | by inverting the second operand, and | |
4030 | ADD <-> SUB | |
4031 | CMP <-> CMN | |
4032 | by negating the second operand. */ | |
4033 | ||
4034 | static int | |
4035 | negate_data_op (instruction, value) | |
4036 | unsigned long * instruction; | |
4037 | unsigned long value; | |
4038 | { | |
4039 | int op, new_inst; | |
4040 | unsigned long negated, inverted; | |
4041 | ||
4042 | negated = validate_immediate (-value); | |
4043 | inverted = validate_immediate (~value); | |
4044 | ||
4045 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; | |
4046 | switch (op) | |
4047 | { | |
4048 | /* First negates. */ | |
4049 | case OPCODE_SUB: /* ADD <-> SUB */ | |
4050 | new_inst = OPCODE_ADD; | |
4051 | value = negated; | |
4052 | break; | |
4053 | ||
4054 | case OPCODE_ADD: | |
4055 | new_inst = OPCODE_SUB; | |
4056 | value = negated; | |
4057 | break; | |
4058 | ||
4059 | case OPCODE_CMP: /* CMP <-> CMN */ | |
4060 | new_inst = OPCODE_CMN; | |
4061 | value = negated; | |
4062 | break; | |
4063 | ||
4064 | case OPCODE_CMN: | |
4065 | new_inst = OPCODE_CMP; | |
4066 | value = negated; | |
4067 | break; | |
4068 | ||
4069 | /* Now Inverted ops. */ | |
4070 | case OPCODE_MOV: /* MOV <-> MVN */ | |
4071 | new_inst = OPCODE_MVN; | |
4072 | value = inverted; | |
4073 | break; | |
4074 | ||
4075 | case OPCODE_MVN: | |
4076 | new_inst = OPCODE_MOV; | |
4077 | value = inverted; | |
4078 | break; | |
4079 | ||
4080 | case OPCODE_AND: /* AND <-> BIC */ | |
4081 | new_inst = OPCODE_BIC; | |
4082 | value = inverted; | |
4083 | break; | |
4084 | ||
4085 | case OPCODE_BIC: | |
4086 | new_inst = OPCODE_AND; | |
4087 | value = inverted; | |
4088 | break; | |
4089 | ||
4090 | case OPCODE_ADC: /* ADC <-> SBC */ | |
4091 | new_inst = OPCODE_SBC; | |
4092 | value = inverted; | |
4093 | break; | |
4094 | ||
4095 | case OPCODE_SBC: | |
4096 | new_inst = OPCODE_ADC; | |
4097 | value = inverted; | |
4098 | break; | |
4099 | ||
4100 | /* We cannot do anything. */ | |
4101 | default: | |
4102 | return FAIL; | |
4103 | } | |
4104 | ||
4105 | if (value == (unsigned) FAIL) | |
4106 | return FAIL; | |
4107 | ||
4108 | *instruction &= OPCODE_MASK; | |
4109 | *instruction |= new_inst << DATA_OP_SHIFT; | |
4110 | return value; | |
4111 | } | |
4112 | ||
4113 | static int | |
4114 | data_op2 (str) | |
4115 | char ** str; | |
4116 | { | |
4117 | int value; | |
4118 | expressionS expr; | |
4119 | ||
4120 | skip_whitespace (* str); | |
4121 | ||
4122 | if (reg_required_here (str, 0) != FAIL) | |
4123 | { | |
4124 | if (skip_past_comma (str) == SUCCESS) | |
4125 | /* Shift operation on register. */ | |
4126 | return decode_shift (str, NO_SHIFT_RESTRICT); | |
4127 | ||
4128 | return SUCCESS; | |
4129 | } | |
4130 | else | |
4131 | { | |
4132 | /* Immediate expression. */ | |
4133 | if (is_immediate_prefix (**str)) | |
4134 | { | |
4135 | (*str)++; | |
4136 | inst.error = NULL; | |
4137 | ||
4138 | if (my_get_expression (&inst.reloc.exp, str)) | |
4139 | return FAIL; | |
4140 | ||
4141 | if (inst.reloc.exp.X_add_symbol) | |
4142 | { | |
4143 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
4144 | inst.reloc.pc_rel = 0; | |
4145 | } | |
4146 | else | |
4147 | { | |
4148 | if (skip_past_comma (str) == SUCCESS) | |
4149 | { | |
4150 | /* #x, y -- ie explicit rotation by Y. */ | |
4151 | if (my_get_expression (&expr, str)) | |
4152 | return FAIL; | |
4153 | ||
4154 | if (expr.X_op != O_constant) | |
4155 | { | |
4156 | inst.error = _("Constant expression expected"); | |
4157 | return FAIL; | |
4158 | } | |
4159 | ||
4160 | /* Rotate must be a multiple of 2. */ | |
4161 | if (((unsigned) expr.X_add_number) > 30 | |
4162 | || (expr.X_add_number & 1) != 0 | |
4163 | || ((unsigned) inst.reloc.exp.X_add_number) > 255) | |
4164 | { | |
4165 | inst.error = _("Invalid constant"); | |
4166 | return FAIL; | |
4167 | } | |
4168 | inst.instruction |= INST_IMMEDIATE; | |
4169 | inst.instruction |= inst.reloc.exp.X_add_number; | |
4170 | inst.instruction |= expr.X_add_number << 7; | |
4171 | return SUCCESS; | |
4172 | } | |
4173 | ||
4174 | /* Implicit rotation, select a suitable one. */ | |
4175 | value = validate_immediate (inst.reloc.exp.X_add_number); | |
4176 | ||
4177 | if (value == FAIL) | |
4178 | { | |
4179 | /* Can't be done. Perhaps the code reads something like | |
4180 | "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */ | |
4181 | if ((value = negate_data_op (&inst.instruction, | |
4182 | inst.reloc.exp.X_add_number)) | |
4183 | == FAIL) | |
4184 | { | |
4185 | inst.error = _("Invalid constant"); | |
4186 | return FAIL; | |
4187 | } | |
4188 | } | |
4189 | ||
4190 | inst.instruction |= value; | |
4191 | } | |
4192 | ||
4193 | inst.instruction |= INST_IMMEDIATE; | |
4194 | return SUCCESS; | |
4195 | } | |
4196 | ||
4197 | (*str)++; | |
4198 | inst.error = _("Register or shift expression expected"); | |
4199 | return FAIL; | |
4200 | } | |
4201 | } | |
4202 | ||
4203 | static int | |
4204 | fp_op2 (str) | |
4205 | char ** str; | |
4206 | { | |
4207 | skip_whitespace (* str); | |
4208 | ||
4209 | if (fp_reg_required_here (str, 0) != FAIL) | |
4210 | return SUCCESS; | |
4211 | else | |
4212 | { | |
4213 | /* Immediate expression. */ | |
4214 | if (*((*str)++) == '#') | |
4215 | { | |
4216 | int i; | |
4217 | ||
4218 | inst.error = NULL; | |
4219 | ||
4220 | skip_whitespace (* str); | |
4221 | ||
4222 | /* First try and match exact strings, this is to guarantee | |
4223 | that some formats will work even for cross assembly. */ | |
4224 | ||
4225 | for (i = 0; fp_const[i]; i++) | |
4226 | { | |
4227 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
4228 | { | |
4229 | char *start = *str; | |
4230 | ||
4231 | *str += strlen (fp_const[i]); | |
4232 | if (is_end_of_line[(unsigned char) **str]) | |
4233 | { | |
4234 | inst.instruction |= i + 8; | |
4235 | return SUCCESS; | |
4236 | } | |
4237 | *str = start; | |
4238 | } | |
4239 | } | |
4240 | ||
4241 | /* Just because we didn't get a match doesn't mean that the | |
4242 | constant isn't valid, just that it is in a format that we | |
4243 | don't automatically recognize. Try parsing it with | |
4244 | the standard expression routines. */ | |
4245 | if ((i = my_get_float_expression (str)) >= 0) | |
4246 | { | |
4247 | inst.instruction |= i + 8; | |
4248 | return SUCCESS; | |
4249 | } | |
4250 | ||
4251 | inst.error = _("Invalid floating point immediate expression"); | |
4252 | return FAIL; | |
4253 | } | |
4254 | inst.error = | |
4255 | _("Floating point register or immediate expression expected"); | |
4256 | return FAIL; | |
4257 | } | |
4258 | } | |
4259 | ||
4260 | static void | |
4261 | do_arit (str, flags) | |
4262 | char * str; | |
4263 | unsigned long flags; | |
4264 | { | |
4265 | skip_whitespace (str); | |
4266 | ||
4267 | if (reg_required_here (&str, 12) == FAIL | |
4268 | || skip_past_comma (&str) == FAIL | |
4269 | || reg_required_here (&str, 16) == FAIL | |
4270 | || skip_past_comma (&str) == FAIL | |
4271 | || data_op2 (&str) == FAIL) | |
4272 | { | |
4273 | if (!inst.error) | |
4274 | inst.error = BAD_ARGS; | |
4275 | return; | |
4276 | } | |
4277 | ||
4278 | inst.instruction |= flags; | |
4279 | end_of_line (str); | |
4280 | return; | |
4281 | } | |
4282 | ||
4283 | static void | |
4284 | do_adr (str, flags) | |
4285 | char * str; | |
4286 | unsigned long flags; | |
4287 | { | |
b99bd4ef NC |
4288 | skip_whitespace (str); |
4289 | ||
4290 | if (reg_required_here (&str, 12) == FAIL | |
4291 | || skip_past_comma (&str) == FAIL | |
4292 | || my_get_expression (&inst.reloc.exp, &str)) | |
4293 | { | |
4294 | if (!inst.error) | |
4295 | inst.error = BAD_ARGS; | |
4296 | return; | |
4297 | } | |
4298 | ||
1cac9012 | 4299 | if (flags & 0x00400000) |
b99bd4ef | 4300 | { |
1cac9012 NC |
4301 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
4302 | into a relative address of the form: | |
4303 | add rd, pc, #low(label-.-8)" | |
4304 | add rd, rd, #high(label-.-8)" */ | |
4305 | /* Frag hacking will turn this into a sub instruction if the offset turns | |
4306 | out to be negative. */ | |
4307 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
4308 | inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */ | |
4309 | inst.reloc.pc_rel = 1; | |
4310 | inst.instruction |= flags & ~0x00400000; | |
4311 | inst.size = INSN_SIZE * 2; | |
4312 | } | |
4313 | else | |
4314 | { | |
4315 | /* This is a pseudo-op of the form "adr rd, label" to be converted | |
4316 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
4317 | /* Frag hacking will turn this into a sub instruction if the offset turns | |
4318 | out to be negative. */ | |
4319 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
4320 | inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */ | |
4321 | inst.reloc.pc_rel = 1; | |
4322 | inst.instruction |= flags; | |
b99bd4ef NC |
4323 | } |
4324 | ||
4325 | end_of_line (str); | |
b99bd4ef NC |
4326 | } |
4327 | ||
4328 | static void | |
4329 | do_cmp (str, flags) | |
4330 | char * str; | |
4331 | unsigned long flags; | |
4332 | { | |
4333 | skip_whitespace (str); | |
4334 | ||
4335 | if (reg_required_here (&str, 16) == FAIL) | |
4336 | { | |
4337 | if (!inst.error) | |
4338 | inst.error = BAD_ARGS; | |
4339 | return; | |
4340 | } | |
4341 | ||
4342 | if (skip_past_comma (&str) == FAIL | |
4343 | || data_op2 (&str) == FAIL) | |
4344 | { | |
4345 | if (!inst.error) | |
4346 | inst.error = BAD_ARGS; | |
4347 | return; | |
4348 | } | |
4349 | ||
4350 | inst.instruction |= flags; | |
4351 | if ((flags & 0x0000f000) == 0) | |
4352 | inst.instruction |= CONDS_BIT; | |
4353 | ||
4354 | end_of_line (str); | |
4355 | return; | |
4356 | } | |
4357 | ||
4358 | static void | |
4359 | do_mov (str, flags) | |
4360 | char * str; | |
4361 | unsigned long flags; | |
4362 | { | |
4363 | skip_whitespace (str); | |
4364 | ||
4365 | if (reg_required_here (&str, 12) == FAIL) | |
4366 | { | |
4367 | if (!inst.error) | |
4368 | inst.error = BAD_ARGS; | |
4369 | return; | |
4370 | } | |
4371 | ||
4372 | if (skip_past_comma (&str) == FAIL | |
4373 | || data_op2 (&str) == FAIL) | |
4374 | { | |
4375 | if (!inst.error) | |
4376 | inst.error = BAD_ARGS; | |
4377 | return; | |
4378 | } | |
4379 | ||
4380 | inst.instruction |= flags; | |
4381 | end_of_line (str); | |
4382 | return; | |
4383 | } | |
4384 | ||
4385 | static int | |
4386 | ldst_extend (str, hwse) | |
4387 | char ** str; | |
4388 | int hwse; | |
4389 | { | |
4390 | int add = INDEX_UP; | |
4391 | ||
4392 | switch (**str) | |
4393 | { | |
4394 | case '#': | |
4395 | case '$': | |
4396 | (*str)++; | |
4397 | if (my_get_expression (& inst.reloc.exp, str)) | |
4398 | return FAIL; | |
4399 | ||
4400 | if (inst.reloc.exp.X_op == O_constant) | |
4401 | { | |
4402 | int value = inst.reloc.exp.X_add_number; | |
4403 | ||
4404 | if ((hwse && (value < -255 || value > 255)) | |
4405 | || (value < -4095 || value > 4095)) | |
4406 | { | |
4407 | inst.error = _("address offset too large"); | |
4408 | return FAIL; | |
4409 | } | |
4410 | ||
4411 | if (value < 0) | |
4412 | { | |
4413 | value = -value; | |
4414 | add = 0; | |
4415 | } | |
4416 | ||
4417 | /* Halfword and signextension instructions have the | |
4418 | immediate value split across bits 11..8 and bits 3..0. */ | |
4419 | if (hwse) | |
4420 | inst.instruction |= (add | HWOFFSET_IMM | |
4421 | | ((value >> 4) << 8) | (value & 0xF)); | |
4422 | else | |
4423 | inst.instruction |= add | value; | |
4424 | } | |
4425 | else | |
4426 | { | |
4427 | if (hwse) | |
4428 | { | |
4429 | inst.instruction |= HWOFFSET_IMM; | |
4430 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
4431 | } | |
4432 | else | |
4433 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
4434 | inst.reloc.pc_rel = 0; | |
4435 | } | |
4436 | return SUCCESS; | |
4437 | ||
4438 | case '-': | |
4439 | add = 0; | |
4440 | /* Fall through. */ | |
4441 | ||
4442 | case '+': | |
4443 | (*str)++; | |
4444 | /* Fall through. */ | |
4445 | ||
4446 | default: | |
4447 | if (reg_required_here (str, 0) == FAIL) | |
4448 | return FAIL; | |
4449 | ||
4450 | if (hwse) | |
4451 | inst.instruction |= add; | |
4452 | else | |
4453 | { | |
4454 | inst.instruction |= add | OFFSET_REG; | |
4455 | if (skip_past_comma (str) == SUCCESS) | |
4456 | return decode_shift (str, SHIFT_RESTRICT); | |
4457 | } | |
4458 | ||
4459 | return SUCCESS; | |
4460 | } | |
4461 | } | |
4462 | ||
4463 | static void | |
4464 | do_ldst (str, flags) | |
4465 | char * str; | |
4466 | unsigned long flags; | |
4467 | { | |
4468 | int halfword = 0; | |
4469 | int pre_inc = 0; | |
4470 | int conflict_reg; | |
4471 | int value; | |
4472 | ||
4473 | /* This is not ideal, but it is the simplest way of dealing with the | |
4474 | ARM7T halfword instructions (since they use a different | |
4475 | encoding, but the same mnemonic): */ | |
4476 | halfword = (flags & 0x80000000) != 0; | |
4477 | if (halfword) | |
4478 | { | |
4479 | /* This is actually a load/store of a halfword, or a | |
4480 | signed-extension load. */ | |
b89dddec | 4481 | if ((cpu_variant & ARM_EXT_V4) == 0) |
b99bd4ef NC |
4482 | { |
4483 | inst.error | |
4484 | = _("Processor does not support halfwords or signed bytes"); | |
4485 | return; | |
4486 | } | |
4487 | ||
4488 | inst.instruction = ((inst.instruction & COND_MASK) | |
4489 | | (flags & ~COND_MASK)); | |
4490 | ||
4491 | flags = 0; | |
4492 | } | |
4493 | ||
4494 | skip_whitespace (str); | |
4495 | ||
4496 | if ((conflict_reg = reg_required_here (& str, 12)) == FAIL) | |
4497 | { | |
4498 | if (!inst.error) | |
4499 | inst.error = BAD_ARGS; | |
4500 | return; | |
4501 | } | |
4502 | ||
4503 | if (skip_past_comma (& str) == FAIL) | |
4504 | { | |
4505 | inst.error = _("Address expected"); | |
4506 | return; | |
4507 | } | |
4508 | ||
4509 | if (*str == '[') | |
4510 | { | |
4511 | int reg; | |
4512 | ||
4513 | str++; | |
4514 | ||
4515 | skip_whitespace (str); | |
4516 | ||
4517 | if ((reg = reg_required_here (&str, 16)) == FAIL) | |
4518 | return; | |
4519 | ||
4520 | /* Conflicts can occur on stores as well as loads. */ | |
4521 | conflict_reg = (conflict_reg == reg); | |
4522 | ||
4523 | skip_whitespace (str); | |
4524 | ||
4525 | if (*str == ']') | |
4526 | { | |
4527 | str ++; | |
4528 | ||
4529 | if (skip_past_comma (&str) == SUCCESS) | |
4530 | { | |
4531 | /* [Rn],... (post inc) */ | |
4532 | if (ldst_extend (&str, halfword) == FAIL) | |
4533 | return; | |
4534 | if (conflict_reg) | |
4535 | { | |
4536 | if (flags & TRANS_BIT) | |
4537 | as_warn (_("Rn and Rd must be different in %s"), | |
4538 | ((inst.instruction & LOAD_BIT) | |
4539 | ? "LDRT" : "STRT")); | |
4540 | else | |
4541 | as_warn (_("%s register same as write-back base"), | |
4542 | ((inst.instruction & LOAD_BIT) | |
4543 | ? _("destination") : _("source"))); | |
4544 | } | |
4545 | } | |
4546 | else | |
4547 | { | |
4548 | /* [Rn] */ | |
4549 | if (halfword) | |
4550 | inst.instruction |= HWOFFSET_IMM; | |
4551 | ||
4552 | skip_whitespace (str); | |
4553 | ||
4554 | if (*str == '!') | |
4555 | { | |
4556 | if (conflict_reg) | |
4557 | as_warn (_("%s register same as write-back base"), | |
4558 | ((inst.instruction & LOAD_BIT) | |
4559 | ? _("destination") : _("source"))); | |
4560 | str++; | |
4561 | inst.instruction |= WRITE_BACK; | |
4562 | } | |
4563 | ||
4564 | flags |= INDEX_UP; | |
4565 | if (flags & TRANS_BIT) | |
4566 | { | |
4567 | if (conflict_reg) | |
4568 | as_warn (_("Rn and Rd must be different in %s"), | |
4569 | ((inst.instruction & LOAD_BIT) | |
4570 | ? "LDRT" : "STRT")); | |
4571 | } | |
4572 | else | |
4573 | pre_inc = 1; | |
4574 | } | |
4575 | } | |
4576 | else | |
4577 | { | |
4578 | /* [Rn,...] */ | |
4579 | if (skip_past_comma (&str) == FAIL) | |
4580 | { | |
4581 | inst.error = _("pre-indexed expression expected"); | |
4582 | return; | |
4583 | } | |
4584 | ||
4585 | pre_inc = 1; | |
4586 | if (ldst_extend (&str, halfword) == FAIL) | |
4587 | return; | |
4588 | ||
4589 | skip_whitespace (str); | |
4590 | ||
4591 | if (*str++ != ']') | |
4592 | { | |
4593 | inst.error = _("missing ]"); | |
4594 | return; | |
4595 | } | |
4596 | ||
4597 | skip_whitespace (str); | |
4598 | ||
4599 | if (*str == '!') | |
4600 | { | |
4601 | if (conflict_reg) | |
4602 | as_warn (_("%s register same as write-back base"), | |
4603 | ((inst.instruction & LOAD_BIT) | |
4604 | ? _("destination") : _("source"))); | |
4605 | str++; | |
4606 | inst.instruction |= WRITE_BACK; | |
4607 | } | |
4608 | } | |
4609 | } | |
4610 | else if (*str == '=') | |
4611 | { | |
4612 | /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */ | |
4613 | str++; | |
4614 | ||
4615 | skip_whitespace (str); | |
4616 | ||
4617 | if (my_get_expression (&inst.reloc.exp, &str)) | |
4618 | return; | |
4619 | ||
4620 | if (inst.reloc.exp.X_op != O_constant | |
4621 | && inst.reloc.exp.X_op != O_symbol) | |
4622 | { | |
4623 | inst.error = _("Constant expression expected"); | |
4624 | return; | |
4625 | } | |
4626 | ||
d8273442 | 4627 | if (inst.reloc.exp.X_op == O_constant) |
b99bd4ef | 4628 | { |
d8273442 NC |
4629 | value = validate_immediate (inst.reloc.exp.X_add_number); |
4630 | ||
4631 | if (value != FAIL) | |
b99bd4ef | 4632 | { |
d8273442 NC |
4633 | /* This can be done with a mov instruction. */ |
4634 | inst.instruction &= LITERAL_MASK; | |
4635 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
4636 | inst.instruction |= (flags & COND_MASK) | (value & 0xfff); | |
4637 | end_of_line (str); | |
b99bd4ef NC |
4638 | return; |
4639 | } | |
d8273442 NC |
4640 | |
4641 | value = validate_immediate (~ inst.reloc.exp.X_add_number); | |
b99bd4ef | 4642 | |
d8273442 | 4643 | if (value != FAIL) |
b99bd4ef | 4644 | { |
d8273442 NC |
4645 | /* This can be done with a mvn instruction. */ |
4646 | inst.instruction &= LITERAL_MASK; | |
4647 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
4648 | inst.instruction |= (flags & COND_MASK) | (value & 0xfff); | |
4649 | end_of_line (str); | |
4650 | return; | |
b99bd4ef | 4651 | } |
b99bd4ef | 4652 | } |
d8273442 NC |
4653 | |
4654 | /* Insert into literal pool. */ | |
4655 | if (add_to_lit_pool () == FAIL) | |
4656 | { | |
4657 | if (!inst.error) | |
4658 | inst.error = _("literal pool insertion failed"); | |
4659 | return; | |
4660 | } | |
4661 | ||
4662 | /* Change the instruction exp to point to the pool. */ | |
4663 | if (halfword) | |
4664 | { | |
4665 | inst.instruction |= HWOFFSET_IMM; | |
4666 | inst.reloc.type = BFD_RELOC_ARM_HWLITERAL; | |
4667 | } | |
4668 | else | |
4669 | inst.reloc.type = BFD_RELOC_ARM_LITERAL; | |
4670 | ||
4671 | inst.reloc.pc_rel = 1; | |
4672 | inst.instruction |= (REG_PC << 16); | |
4673 | pre_inc = 1; | |
b99bd4ef NC |
4674 | } |
4675 | else | |
4676 | { | |
4677 | if (my_get_expression (&inst.reloc.exp, &str)) | |
4678 | return; | |
4679 | ||
4680 | if (halfword) | |
4681 | { | |
4682 | inst.instruction |= HWOFFSET_IMM; | |
4683 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
4684 | } | |
4685 | else | |
4686 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
4687 | #ifndef TE_WINCE | |
4688 | /* PC rel adjust. */ | |
4689 | inst.reloc.exp.X_add_number -= 8; | |
4690 | #endif | |
4691 | inst.reloc.pc_rel = 1; | |
4692 | inst.instruction |= (REG_PC << 16); | |
4693 | pre_inc = 1; | |
4694 | } | |
4695 | ||
4696 | if (pre_inc && (flags & TRANS_BIT)) | |
4697 | inst.error = _("Pre-increment instruction with translate"); | |
4698 | ||
4699 | inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0); | |
4700 | end_of_line (str); | |
4701 | return; | |
4702 | } | |
4703 | ||
4704 | static long | |
4705 | reg_list (strp) | |
4706 | char ** strp; | |
4707 | { | |
4708 | char * str = * strp; | |
4709 | long range = 0; | |
4710 | int another_range; | |
4711 | ||
4712 | /* We come back here if we get ranges concatenated by '+' or '|'. */ | |
4713 | do | |
4714 | { | |
4715 | another_range = 0; | |
4716 | ||
4717 | if (*str == '{') | |
4718 | { | |
4719 | int in_range = 0; | |
4720 | int cur_reg = -1; | |
4721 | ||
4722 | str++; | |
4723 | do | |
4724 | { | |
4725 | int reg; | |
4726 | ||
4727 | skip_whitespace (str); | |
4728 | ||
4729 | if ((reg = reg_required_here (& str, -1)) == FAIL) | |
4730 | return FAIL; | |
4731 | ||
4732 | if (in_range) | |
4733 | { | |
4734 | int i; | |
4735 | ||
4736 | if (reg <= cur_reg) | |
4737 | { | |
4738 | inst.error = _("Bad range in register list"); | |
4739 | return FAIL; | |
4740 | } | |
4741 | ||
4742 | for (i = cur_reg + 1; i < reg; i++) | |
4743 | { | |
4744 | if (range & (1 << i)) | |
4745 | as_tsktsk | |
4746 | (_("Warning: Duplicated register (r%d) in register list"), | |
4747 | i); | |
4748 | else | |
4749 | range |= 1 << i; | |
4750 | } | |
4751 | in_range = 0; | |
4752 | } | |
4753 | ||
4754 | if (range & (1 << reg)) | |
4755 | as_tsktsk (_("Warning: Duplicated register (r%d) in register list"), | |
4756 | reg); | |
4757 | else if (reg <= cur_reg) | |
4758 | as_tsktsk (_("Warning: Register range not in ascending order")); | |
4759 | ||
4760 | range |= 1 << reg; | |
4761 | cur_reg = reg; | |
4762 | } | |
4763 | while (skip_past_comma (&str) != FAIL | |
4764 | || (in_range = 1, *str++ == '-')); | |
4765 | str--; | |
4766 | skip_whitespace (str); | |
4767 | ||
4768 | if (*str++ != '}') | |
4769 | { | |
4770 | inst.error = _("Missing `}'"); | |
4771 | return FAIL; | |
4772 | } | |
4773 | } | |
4774 | else | |
4775 | { | |
4776 | expressionS expr; | |
4777 | ||
4778 | if (my_get_expression (&expr, &str)) | |
4779 | return FAIL; | |
4780 | ||
4781 | if (expr.X_op == O_constant) | |
4782 | { | |
4783 | if (expr.X_add_number | |
4784 | != (expr.X_add_number & 0x0000ffff)) | |
4785 | { | |
4786 | inst.error = _("invalid register mask"); | |
4787 | return FAIL; | |
4788 | } | |
4789 | ||
4790 | if ((range & expr.X_add_number) != 0) | |
4791 | { | |
4792 | int regno = range & expr.X_add_number; | |
4793 | ||
4794 | regno &= -regno; | |
4795 | regno = (1 << regno) - 1; | |
4796 | as_tsktsk | |
4797 | (_("Warning: Duplicated register (r%d) in register list"), | |
4798 | regno); | |
4799 | } | |
4800 | ||
4801 | range |= expr.X_add_number; | |
4802 | } | |
4803 | else | |
4804 | { | |
4805 | if (inst.reloc.type != 0) | |
4806 | { | |
4807 | inst.error = _("expression too complex"); | |
4808 | return FAIL; | |
4809 | } | |
4810 | ||
4811 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); | |
4812 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
4813 | inst.reloc.pc_rel = 0; | |
4814 | } | |
4815 | } | |
4816 | ||
4817 | skip_whitespace (str); | |
4818 | ||
4819 | if (*str == '|' || *str == '+') | |
4820 | { | |
4821 | str++; | |
4822 | another_range = 1; | |
4823 | } | |
4824 | } | |
4825 | while (another_range); | |
4826 | ||
4827 | *strp = str; | |
4828 | return range; | |
4829 | } | |
4830 | ||
4831 | static void | |
4832 | do_ldmstm (str, flags) | |
4833 | char * str; | |
4834 | unsigned long flags; | |
4835 | { | |
4836 | int base_reg; | |
4837 | long range; | |
4838 | ||
4839 | skip_whitespace (str); | |
4840 | ||
4841 | if ((base_reg = reg_required_here (&str, 16)) == FAIL) | |
4842 | return; | |
4843 | ||
4844 | if (base_reg == REG_PC) | |
4845 | { | |
4846 | inst.error = _("r15 not allowed as base register"); | |
4847 | return; | |
4848 | } | |
4849 | ||
4850 | skip_whitespace (str); | |
4851 | ||
4852 | if (*str == '!') | |
4853 | { | |
4854 | flags |= WRITE_BACK; | |
4855 | str++; | |
4856 | } | |
4857 | ||
4858 | if (skip_past_comma (&str) == FAIL | |
4859 | || (range = reg_list (&str)) == FAIL) | |
4860 | { | |
4861 | if (! inst.error) | |
4862 | inst.error = BAD_ARGS; | |
4863 | return; | |
4864 | } | |
4865 | ||
4866 | if (*str == '^') | |
4867 | { | |
4868 | str++; | |
4869 | flags |= LDM_TYPE_2_OR_3; | |
4870 | } | |
4871 | ||
4872 | inst.instruction |= flags | range; | |
4873 | end_of_line (str); | |
4874 | return; | |
4875 | } | |
4876 | ||
4877 | static void | |
4878 | do_swi (str, flags) | |
4879 | char * str; | |
4880 | unsigned long flags; | |
4881 | { | |
4882 | skip_whitespace (str); | |
4883 | ||
4884 | /* Allow optional leading '#'. */ | |
4885 | if (is_immediate_prefix (*str)) | |
4886 | str++; | |
4887 | ||
4888 | if (my_get_expression (& inst.reloc.exp, & str)) | |
4889 | return; | |
4890 | ||
4891 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
4892 | inst.reloc.pc_rel = 0; | |
4893 | inst.instruction |= flags; | |
4894 | ||
4895 | end_of_line (str); | |
4896 | ||
4897 | return; | |
4898 | } | |
4899 | ||
4900 | static void | |
4901 | do_swap (str, flags) | |
4902 | char * str; | |
4903 | unsigned long flags; | |
4904 | { | |
4905 | int reg; | |
4906 | ||
4907 | skip_whitespace (str); | |
4908 | ||
4909 | if ((reg = reg_required_here (&str, 12)) == FAIL) | |
4910 | return; | |
4911 | ||
4912 | if (reg == REG_PC) | |
4913 | { | |
4914 | inst.error = _("r15 not allowed in swap"); | |
4915 | return; | |
4916 | } | |
4917 | ||
4918 | if (skip_past_comma (&str) == FAIL | |
4919 | || (reg = reg_required_here (&str, 0)) == FAIL) | |
4920 | { | |
4921 | if (!inst.error) | |
4922 | inst.error = BAD_ARGS; | |
4923 | return; | |
4924 | } | |
4925 | ||
4926 | if (reg == REG_PC) | |
4927 | { | |
4928 | inst.error = _("r15 not allowed in swap"); | |
4929 | return; | |
4930 | } | |
4931 | ||
4932 | if (skip_past_comma (&str) == FAIL | |
4933 | || *str++ != '[') | |
4934 | { | |
4935 | inst.error = BAD_ARGS; | |
4936 | return; | |
4937 | } | |
4938 | ||
4939 | skip_whitespace (str); | |
4940 | ||
4941 | if ((reg = reg_required_here (&str, 16)) == FAIL) | |
4942 | return; | |
4943 | ||
4944 | if (reg == REG_PC) | |
4945 | { | |
4946 | inst.error = BAD_PC; | |
4947 | return; | |
4948 | } | |
4949 | ||
4950 | skip_whitespace (str); | |
4951 | ||
4952 | if (*str++ != ']') | |
4953 | { | |
4954 | inst.error = _("missing ]"); | |
4955 | return; | |
4956 | } | |
4957 | ||
4958 | inst.instruction |= flags; | |
4959 | end_of_line (str); | |
4960 | return; | |
4961 | } | |
4962 | ||
4963 | static void | |
4964 | do_branch (str, flags) | |
4965 | char * str; | |
4966 | unsigned long flags ATTRIBUTE_UNUSED; | |
4967 | { | |
4968 | if (my_get_expression (&inst.reloc.exp, &str)) | |
4969 | return; | |
4970 | ||
4971 | #ifdef OBJ_ELF | |
4972 | { | |
4973 | char * save_in; | |
4974 | ||
4975 | /* ScottB: February 5, 1998 - Check to see of PLT32 reloc | |
4976 | required for the instruction. */ | |
4977 | ||
4978 | /* arm_parse_reloc () works on input_line_pointer. | |
4979 | We actually want to parse the operands to the branch instruction | |
4980 | passed in 'str'. Save the input pointer and restore it later. */ | |
4981 | save_in = input_line_pointer; | |
4982 | input_line_pointer = str; | |
4983 | if (inst.reloc.exp.X_op == O_symbol | |
4984 | && *str == '(' | |
4985 | && arm_parse_reloc () == BFD_RELOC_ARM_PLT32) | |
4986 | { | |
4987 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
4988 | inst.reloc.pc_rel = 0; | |
4989 | /* Modify str to point to after parsed operands, otherwise | |
4990 | end_of_line() will complain about the (PLT) left in str. */ | |
4991 | str = input_line_pointer; | |
4992 | } | |
4993 | else | |
4994 | { | |
4995 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH; | |
4996 | inst.reloc.pc_rel = 1; | |
4997 | } | |
4998 | input_line_pointer = save_in; | |
4999 | } | |
5000 | #else | |
5001 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH; | |
5002 | inst.reloc.pc_rel = 1; | |
5003 | #endif /* OBJ_ELF */ | |
5004 | ||
5005 | end_of_line (str); | |
5006 | return; | |
5007 | } | |
5008 | ||
5009 | static void | |
5010 | do_bx (str, flags) | |
5011 | char * str; | |
5012 | unsigned long flags ATTRIBUTE_UNUSED; | |
5013 | { | |
5014 | int reg; | |
5015 | ||
5016 | skip_whitespace (str); | |
5017 | ||
5018 | if ((reg = reg_required_here (&str, 0)) == FAIL) | |
5019 | { | |
5020 | inst.error = BAD_ARGS; | |
5021 | return; | |
5022 | } | |
5023 | ||
5024 | /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */ | |
5025 | if (reg == REG_PC) | |
5026 | as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful")); | |
5027 | ||
5028 | end_of_line (str); | |
5029 | } | |
5030 | ||
5031 | static void | |
5032 | do_cdp (str, flags) | |
5033 | char * str; | |
5034 | unsigned long flags ATTRIBUTE_UNUSED; | |
5035 | { | |
5036 | /* Co-processor data operation. | |
5037 | Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */ | |
5038 | skip_whitespace (str); | |
5039 | ||
5040 | if (co_proc_number (&str) == FAIL) | |
5041 | { | |
5042 | if (!inst.error) | |
5043 | inst.error = BAD_ARGS; | |
5044 | return; | |
5045 | } | |
5046 | ||
5047 | if (skip_past_comma (&str) == FAIL | |
5048 | || cp_opc_expr (&str, 20,4) == FAIL) | |
5049 | { | |
5050 | if (!inst.error) | |
5051 | inst.error = BAD_ARGS; | |
5052 | return; | |
5053 | } | |
5054 | ||
5055 | if (skip_past_comma (&str) == FAIL | |
5056 | || cp_reg_required_here (&str, 12) == FAIL) | |
5057 | { | |
5058 | if (!inst.error) | |
5059 | inst.error = BAD_ARGS; | |
5060 | return; | |
5061 | } | |
5062 | ||
5063 | if (skip_past_comma (&str) == FAIL | |
5064 | || cp_reg_required_here (&str, 16) == FAIL) | |
5065 | { | |
5066 | if (!inst.error) | |
5067 | inst.error = BAD_ARGS; | |
5068 | return; | |
5069 | } | |
5070 | ||
5071 | if (skip_past_comma (&str) == FAIL | |
5072 | || cp_reg_required_here (&str, 0) == FAIL) | |
5073 | { | |
5074 | if (!inst.error) | |
5075 | inst.error = BAD_ARGS; | |
5076 | return; | |
5077 | } | |
5078 | ||
5079 | if (skip_past_comma (&str) == SUCCESS) | |
5080 | { | |
5081 | if (cp_opc_expr (&str, 5, 3) == FAIL) | |
5082 | { | |
5083 | if (!inst.error) | |
5084 | inst.error = BAD_ARGS; | |
5085 | return; | |
5086 | } | |
5087 | } | |
5088 | ||
5089 | end_of_line (str); | |
5090 | return; | |
5091 | } | |
5092 | ||
5093 | static void | |
5094 | do_lstc (str, flags) | |
5095 | char * str; | |
5096 | unsigned long flags; | |
5097 | { | |
5098 | /* Co-processor register load/store. | |
5099 | Format: <LDC|STC{cond}[L] CP#,CRd,<address> */ | |
5100 | ||
5101 | skip_whitespace (str); | |
5102 | ||
5103 | if (co_proc_number (&str) == FAIL) | |
5104 | { | |
5105 | if (!inst.error) | |
5106 | inst.error = BAD_ARGS; | |
5107 | return; | |
5108 | } | |
5109 | ||
5110 | if (skip_past_comma (&str) == FAIL | |
5111 | || cp_reg_required_here (&str, 12) == FAIL) | |
5112 | { | |
5113 | if (!inst.error) | |
5114 | inst.error = BAD_ARGS; | |
5115 | return; | |
5116 | } | |
5117 | ||
5118 | if (skip_past_comma (&str) == FAIL | |
5119 | || cp_address_required_here (&str) == FAIL) | |
5120 | { | |
5121 | if (! inst.error) | |
5122 | inst.error = BAD_ARGS; | |
5123 | return; | |
5124 | } | |
5125 | ||
5126 | inst.instruction |= flags; | |
5127 | end_of_line (str); | |
5128 | return; | |
5129 | } | |
5130 | ||
5131 | static void | |
5132 | do_co_reg (str, flags) | |
5133 | char * str; | |
5134 | unsigned long flags; | |
5135 | { | |
5136 | /* Co-processor register transfer. | |
5137 | Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */ | |
5138 | ||
5139 | skip_whitespace (str); | |
5140 | ||
5141 | if (co_proc_number (&str) == FAIL) | |
5142 | { | |
5143 | if (!inst.error) | |
5144 | inst.error = BAD_ARGS; | |
5145 | return; | |
5146 | } | |
5147 | ||
5148 | if (skip_past_comma (&str) == FAIL | |
5149 | || cp_opc_expr (&str, 21, 3) == FAIL) | |
5150 | { | |
5151 | if (!inst.error) | |
5152 | inst.error = BAD_ARGS; | |
5153 | return; | |
5154 | } | |
5155 | ||
5156 | if (skip_past_comma (&str) == FAIL | |
5157 | || reg_required_here (&str, 12) == FAIL) | |
5158 | { | |
5159 | if (!inst.error) | |
5160 | inst.error = BAD_ARGS; | |
5161 | return; | |
5162 | } | |
5163 | ||
5164 | if (skip_past_comma (&str) == FAIL | |
5165 | || cp_reg_required_here (&str, 16) == FAIL) | |
5166 | { | |
5167 | if (!inst.error) | |
5168 | inst.error = BAD_ARGS; | |
5169 | return; | |
5170 | } | |
5171 | ||
5172 | if (skip_past_comma (&str) == FAIL | |
5173 | || cp_reg_required_here (&str, 0) == FAIL) | |
5174 | { | |
5175 | if (!inst.error) | |
5176 | inst.error = BAD_ARGS; | |
5177 | return; | |
5178 | } | |
5179 | ||
5180 | if (skip_past_comma (&str) == SUCCESS) | |
5181 | { | |
5182 | if (cp_opc_expr (&str, 5, 3) == FAIL) | |
5183 | { | |
5184 | if (!inst.error) | |
5185 | inst.error = BAD_ARGS; | |
5186 | return; | |
5187 | } | |
5188 | } | |
5189 | if (flags) | |
5190 | { | |
5191 | inst.error = BAD_COND; | |
5192 | } | |
5193 | ||
5194 | end_of_line (str); | |
5195 | return; | |
5196 | } | |
5197 | ||
5198 | static void | |
c9b604bd | 5199 | do_fpa_ctrl (str, flags) |
b99bd4ef NC |
5200 | char * str; |
5201 | unsigned long flags ATTRIBUTE_UNUSED; | |
5202 | { | |
5203 | /* FP control registers. | |
5204 | Format: <WFS|RFS|WFC|RFC>{cond} Rn */ | |
5205 | ||
5206 | skip_whitespace (str); | |
5207 | ||
5208 | if (reg_required_here (&str, 12) == FAIL) | |
5209 | { | |
5210 | if (!inst.error) | |
5211 | inst.error = BAD_ARGS; | |
5212 | return; | |
5213 | } | |
5214 | ||
5215 | end_of_line (str); | |
5216 | return; | |
5217 | } | |
5218 | ||
5219 | static void | |
c9b604bd | 5220 | do_fpa_ldst (str, flags) |
b99bd4ef NC |
5221 | char * str; |
5222 | unsigned long flags ATTRIBUTE_UNUSED; | |
5223 | { | |
5224 | skip_whitespace (str); | |
5225 | ||
5226 | switch (inst.suffix) | |
5227 | { | |
5228 | case SUFF_S: | |
5229 | break; | |
5230 | case SUFF_D: | |
5231 | inst.instruction |= CP_T_X; | |
5232 | break; | |
5233 | case SUFF_E: | |
5234 | inst.instruction |= CP_T_Y; | |
5235 | break; | |
5236 | case SUFF_P: | |
5237 | inst.instruction |= CP_T_X | CP_T_Y; | |
5238 | break; | |
5239 | default: | |
5240 | abort (); | |
5241 | } | |
5242 | ||
5243 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5244 | { | |
5245 | if (!inst.error) | |
5246 | inst.error = BAD_ARGS; | |
5247 | return; | |
5248 | } | |
5249 | ||
5250 | if (skip_past_comma (&str) == FAIL | |
5251 | || cp_address_required_here (&str) == FAIL) | |
5252 | { | |
5253 | if (!inst.error) | |
5254 | inst.error = BAD_ARGS; | |
5255 | return; | |
5256 | } | |
5257 | ||
5258 | end_of_line (str); | |
5259 | } | |
5260 | ||
5261 | static void | |
c9b604bd | 5262 | do_fpa_ldmstm (str, flags) |
b99bd4ef NC |
5263 | char * str; |
5264 | unsigned long flags; | |
5265 | { | |
5266 | int num_regs; | |
5267 | ||
5268 | skip_whitespace (str); | |
5269 | ||
5270 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5271 | { | |
5272 | if (! inst.error) | |
5273 | inst.error = BAD_ARGS; | |
5274 | return; | |
5275 | } | |
5276 | ||
5277 | /* Get Number of registers to transfer. */ | |
5278 | if (skip_past_comma (&str) == FAIL | |
5279 | || my_get_expression (&inst.reloc.exp, &str)) | |
5280 | { | |
5281 | if (! inst.error) | |
5282 | inst.error = _("constant expression expected"); | |
5283 | return; | |
5284 | } | |
5285 | ||
5286 | if (inst.reloc.exp.X_op != O_constant) | |
5287 | { | |
5288 | inst.error = _("Constant value required for number of registers"); | |
5289 | return; | |
5290 | } | |
5291 | ||
5292 | num_regs = inst.reloc.exp.X_add_number; | |
5293 | ||
5294 | if (num_regs < 1 || num_regs > 4) | |
5295 | { | |
5296 | inst.error = _("number of registers must be in the range [1:4]"); | |
5297 | return; | |
5298 | } | |
5299 | ||
5300 | switch (num_regs) | |
5301 | { | |
5302 | case 1: | |
5303 | inst.instruction |= CP_T_X; | |
5304 | break; | |
5305 | case 2: | |
5306 | inst.instruction |= CP_T_Y; | |
5307 | break; | |
5308 | case 3: | |
5309 | inst.instruction |= CP_T_Y | CP_T_X; | |
5310 | break; | |
5311 | case 4: | |
5312 | break; | |
5313 | default: | |
5314 | abort (); | |
5315 | } | |
5316 | ||
5317 | if (flags) | |
5318 | { | |
5319 | int reg; | |
5320 | int write_back; | |
5321 | int offset; | |
5322 | ||
5323 | /* The instruction specified "ea" or "fd", so we can only accept | |
5324 | [Rn]{!}. The instruction does not really support stacking or | |
5325 | unstacking, so we have to emulate these by setting appropriate | |
5326 | bits and offsets. */ | |
5327 | if (skip_past_comma (&str) == FAIL | |
5328 | || *str != '[') | |
5329 | { | |
5330 | if (! inst.error) | |
5331 | inst.error = BAD_ARGS; | |
5332 | return; | |
5333 | } | |
5334 | ||
5335 | str++; | |
5336 | skip_whitespace (str); | |
5337 | ||
5338 | if ((reg = reg_required_here (&str, 16)) == FAIL) | |
5339 | return; | |
5340 | ||
5341 | skip_whitespace (str); | |
5342 | ||
5343 | if (*str != ']') | |
5344 | { | |
5345 | inst.error = BAD_ARGS; | |
5346 | return; | |
5347 | } | |
5348 | ||
5349 | str++; | |
5350 | if (*str == '!') | |
5351 | { | |
5352 | write_back = 1; | |
5353 | str++; | |
5354 | if (reg == REG_PC) | |
5355 | { | |
5356 | inst.error = | |
5357 | _("R15 not allowed as base register with write-back"); | |
5358 | return; | |
5359 | } | |
5360 | } | |
5361 | else | |
5362 | write_back = 0; | |
5363 | ||
5364 | if (flags & CP_T_Pre) | |
5365 | { | |
5366 | /* Pre-decrement. */ | |
5367 | offset = 3 * num_regs; | |
5368 | if (write_back) | |
5369 | flags |= CP_T_WB; | |
5370 | } | |
5371 | else | |
5372 | { | |
5373 | /* Post-increment. */ | |
5374 | if (write_back) | |
5375 | { | |
5376 | flags |= CP_T_WB; | |
5377 | offset = 3 * num_regs; | |
5378 | } | |
5379 | else | |
5380 | { | |
5381 | /* No write-back, so convert this into a standard pre-increment | |
5382 | instruction -- aesthetically more pleasing. */ | |
5383 | flags = CP_T_Pre | CP_T_UD; | |
5384 | offset = 0; | |
5385 | } | |
5386 | } | |
5387 | ||
5388 | inst.instruction |= flags | offset; | |
5389 | } | |
5390 | else if (skip_past_comma (&str) == FAIL | |
5391 | || cp_address_required_here (&str) == FAIL) | |
5392 | { | |
5393 | if (! inst.error) | |
5394 | inst.error = BAD_ARGS; | |
5395 | return; | |
5396 | } | |
5397 | ||
5398 | end_of_line (str); | |
5399 | } | |
5400 | ||
5401 | static void | |
c9b604bd | 5402 | do_fpa_dyadic (str, flags) |
b99bd4ef NC |
5403 | char * str; |
5404 | unsigned long flags; | |
5405 | { | |
5406 | skip_whitespace (str); | |
5407 | ||
5408 | switch (inst.suffix) | |
5409 | { | |
5410 | case SUFF_S: | |
5411 | break; | |
5412 | case SUFF_D: | |
5413 | inst.instruction |= 0x00000080; | |
5414 | break; | |
5415 | case SUFF_E: | |
5416 | inst.instruction |= 0x00080000; | |
5417 | break; | |
5418 | default: | |
5419 | abort (); | |
5420 | } | |
5421 | ||
5422 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5423 | { | |
5424 | if (! inst.error) | |
5425 | inst.error = BAD_ARGS; | |
5426 | return; | |
5427 | } | |
5428 | ||
5429 | if (skip_past_comma (&str) == FAIL | |
5430 | || fp_reg_required_here (&str, 16) == FAIL) | |
5431 | { | |
5432 | if (! inst.error) | |
5433 | inst.error = BAD_ARGS; | |
5434 | return; | |
5435 | } | |
5436 | ||
5437 | if (skip_past_comma (&str) == FAIL | |
5438 | || fp_op2 (&str) == FAIL) | |
5439 | { | |
5440 | if (! inst.error) | |
5441 | inst.error = BAD_ARGS; | |
5442 | return; | |
5443 | } | |
5444 | ||
5445 | inst.instruction |= flags; | |
5446 | end_of_line (str); | |
5447 | return; | |
5448 | } | |
5449 | ||
5450 | static void | |
c9b604bd | 5451 | do_fpa_monadic (str, flags) |
b99bd4ef NC |
5452 | char * str; |
5453 | unsigned long flags; | |
5454 | { | |
5455 | skip_whitespace (str); | |
5456 | ||
5457 | switch (inst.suffix) | |
5458 | { | |
5459 | case SUFF_S: | |
5460 | break; | |
5461 | case SUFF_D: | |
5462 | inst.instruction |= 0x00000080; | |
5463 | break; | |
5464 | case SUFF_E: | |
5465 | inst.instruction |= 0x00080000; | |
5466 | break; | |
5467 | default: | |
5468 | abort (); | |
5469 | } | |
5470 | ||
5471 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5472 | { | |
5473 | if (! inst.error) | |
5474 | inst.error = BAD_ARGS; | |
5475 | return; | |
5476 | } | |
5477 | ||
5478 | if (skip_past_comma (&str) == FAIL | |
5479 | || fp_op2 (&str) == FAIL) | |
5480 | { | |
5481 | if (! inst.error) | |
5482 | inst.error = BAD_ARGS; | |
5483 | return; | |
5484 | } | |
5485 | ||
5486 | inst.instruction |= flags; | |
5487 | end_of_line (str); | |
5488 | return; | |
5489 | } | |
5490 | ||
5491 | static void | |
c9b604bd | 5492 | do_fpa_cmp (str, flags) |
b99bd4ef NC |
5493 | char * str; |
5494 | unsigned long flags; | |
5495 | { | |
5496 | skip_whitespace (str); | |
5497 | ||
5498 | if (fp_reg_required_here (&str, 16) == FAIL) | |
5499 | { | |
5500 | if (! inst.error) | |
5501 | inst.error = BAD_ARGS; | |
5502 | return; | |
5503 | } | |
5504 | ||
5505 | if (skip_past_comma (&str) == FAIL | |
5506 | || fp_op2 (&str) == FAIL) | |
5507 | { | |
5508 | if (! inst.error) | |
5509 | inst.error = BAD_ARGS; | |
5510 | return; | |
5511 | } | |
5512 | ||
5513 | inst.instruction |= flags; | |
5514 | end_of_line (str); | |
5515 | return; | |
5516 | } | |
5517 | ||
5518 | static void | |
c9b604bd | 5519 | do_fpa_from_reg (str, flags) |
b99bd4ef NC |
5520 | char * str; |
5521 | unsigned long flags; | |
5522 | { | |
5523 | skip_whitespace (str); | |
5524 | ||
5525 | switch (inst.suffix) | |
5526 | { | |
5527 | case SUFF_S: | |
5528 | break; | |
5529 | case SUFF_D: | |
5530 | inst.instruction |= 0x00000080; | |
5531 | break; | |
5532 | case SUFF_E: | |
5533 | inst.instruction |= 0x00080000; | |
5534 | break; | |
5535 | default: | |
5536 | abort (); | |
5537 | } | |
5538 | ||
5539 | if (fp_reg_required_here (&str, 16) == FAIL) | |
5540 | { | |
5541 | if (! inst.error) | |
5542 | inst.error = BAD_ARGS; | |
5543 | return; | |
5544 | } | |
5545 | ||
5546 | if (skip_past_comma (&str) == FAIL | |
5547 | || reg_required_here (&str, 12) == FAIL) | |
5548 | { | |
5549 | if (! inst.error) | |
5550 | inst.error = BAD_ARGS; | |
5551 | return; | |
5552 | } | |
5553 | ||
5554 | inst.instruction |= flags; | |
5555 | end_of_line (str); | |
5556 | return; | |
5557 | } | |
5558 | ||
5559 | static void | |
c9b604bd | 5560 | do_fpa_to_reg (str, flags) |
b99bd4ef NC |
5561 | char * str; |
5562 | unsigned long flags; | |
5563 | { | |
5564 | skip_whitespace (str); | |
5565 | ||
5566 | if (reg_required_here (&str, 12) == FAIL) | |
5567 | return; | |
5568 | ||
5569 | if (skip_past_comma (&str) == FAIL | |
5570 | || fp_reg_required_here (&str, 0) == FAIL) | |
5571 | { | |
5572 | if (! inst.error) | |
5573 | inst.error = BAD_ARGS; | |
5574 | return; | |
5575 | } | |
5576 | ||
5577 | inst.instruction |= flags; | |
5578 | end_of_line (str); | |
5579 | return; | |
5580 | } | |
5581 | ||
5582 | /* Thumb specific routines. */ | |
5583 | ||
5584 | /* Parse and validate that a register is of the right form, this saves | |
5585 | repeated checking of this information in many similar cases. | |
5586 | Unlike the 32-bit case we do not insert the register into the opcode | |
5587 | here, since the position is often unknown until the full instruction | |
5588 | has been parsed. */ | |
5589 | ||
5590 | static int | |
5591 | thumb_reg (strp, hi_lo) | |
5592 | char ** strp; | |
5593 | int hi_lo; | |
5594 | { | |
5595 | int reg; | |
5596 | ||
5597 | if ((reg = reg_required_here (strp, -1)) == FAIL) | |
5598 | return FAIL; | |
5599 | ||
5600 | switch (hi_lo) | |
5601 | { | |
5602 | case THUMB_REG_LO: | |
5603 | if (reg > 7) | |
5604 | { | |
5605 | inst.error = _("lo register required"); | |
5606 | return FAIL; | |
5607 | } | |
5608 | break; | |
5609 | ||
5610 | case THUMB_REG_HI: | |
5611 | if (reg < 8) | |
5612 | { | |
5613 | inst.error = _("hi register required"); | |
5614 | return FAIL; | |
5615 | } | |
5616 | break; | |
5617 | ||
5618 | default: | |
5619 | break; | |
5620 | } | |
5621 | ||
5622 | return reg; | |
5623 | } | |
5624 | ||
5625 | /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode | |
5626 | was SUB. */ | |
5627 | ||
5628 | static void | |
5629 | thumb_add_sub (str, subtract) | |
5630 | char * str; | |
5631 | int subtract; | |
5632 | { | |
5633 | int Rd, Rs, Rn = FAIL; | |
5634 | ||
5635 | skip_whitespace (str); | |
5636 | ||
5637 | if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL | |
5638 | || skip_past_comma (&str) == FAIL) | |
5639 | { | |
5640 | if (! inst.error) | |
5641 | inst.error = BAD_ARGS; | |
5642 | return; | |
5643 | } | |
5644 | ||
5645 | if (is_immediate_prefix (*str)) | |
5646 | { | |
5647 | Rs = Rd; | |
5648 | str++; | |
5649 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5650 | return; | |
5651 | } | |
5652 | else | |
5653 | { | |
5654 | if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5655 | return; | |
5656 | ||
5657 | if (skip_past_comma (&str) == FAIL) | |
5658 | { | |
5659 | /* Two operand format, shuffle the registers | |
5660 | and pretend there are 3. */ | |
5661 | Rn = Rs; | |
5662 | Rs = Rd; | |
5663 | } | |
5664 | else if (is_immediate_prefix (*str)) | |
5665 | { | |
5666 | str++; | |
5667 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5668 | return; | |
5669 | } | |
5670 | else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5671 | return; | |
5672 | } | |
5673 | ||
5674 | /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL; | |
5675 | for the latter case, EXPR contains the immediate that was found. */ | |
5676 | if (Rn != FAIL) | |
5677 | { | |
5678 | /* All register format. */ | |
5679 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
5680 | { | |
5681 | if (Rs != Rd) | |
5682 | { | |
5683 | inst.error = _("dest and source1 must be the same register"); | |
5684 | return; | |
5685 | } | |
5686 | ||
5687 | /* Can't do this for SUB. */ | |
5688 | if (subtract) | |
5689 | { | |
5690 | inst.error = _("subtract valid only on lo regs"); | |
5691 | return; | |
5692 | } | |
5693 | ||
5694 | inst.instruction = (T_OPCODE_ADD_HI | |
5695 | | (Rd > 7 ? THUMB_H1 : 0) | |
5696 | | (Rn > 7 ? THUMB_H2 : 0)); | |
5697 | inst.instruction |= (Rd & 7) | ((Rn & 7) << 3); | |
5698 | } | |
5699 | else | |
5700 | { | |
5701 | inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3; | |
5702 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
5703 | } | |
5704 | } | |
5705 | else | |
5706 | { | |
5707 | /* Immediate expression, now things start to get nasty. */ | |
5708 | ||
5709 | /* First deal with HI regs, only very restricted cases allowed: | |
5710 | Adjusting SP, and using PC or SP to get an address. */ | |
5711 | if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) | |
5712 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC)) | |
5713 | { | |
5714 | inst.error = _("invalid Hi register with immediate"); | |
5715 | return; | |
5716 | } | |
5717 | ||
5718 | if (inst.reloc.exp.X_op != O_constant) | |
5719 | { | |
5720 | /* Value isn't known yet, all we can do is store all the fragments | |
5721 | we know about in the instruction and let the reloc hacking | |
5722 | work it all out. */ | |
5723 | inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs; | |
5724 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
5725 | } | |
5726 | else | |
5727 | { | |
5728 | int offset = inst.reloc.exp.X_add_number; | |
5729 | ||
5730 | if (subtract) | |
5731 | offset = -offset; | |
5732 | ||
5733 | if (offset < 0) | |
5734 | { | |
5735 | offset = -offset; | |
5736 | subtract = 1; | |
5737 | ||
5738 | /* Quick check, in case offset is MIN_INT. */ | |
5739 | if (offset < 0) | |
5740 | { | |
5741 | inst.error = _("immediate value out of range"); | |
5742 | return; | |
5743 | } | |
5744 | } | |
5745 | else | |
5746 | subtract = 0; | |
5747 | ||
5748 | if (Rd == REG_SP) | |
5749 | { | |
5750 | if (offset & ~0x1fc) | |
5751 | { | |
5752 | inst.error = _("invalid immediate value for stack adjust"); | |
5753 | return; | |
5754 | } | |
5755 | inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
5756 | inst.instruction |= offset >> 2; | |
5757 | } | |
5758 | else if (Rs == REG_PC || Rs == REG_SP) | |
5759 | { | |
5760 | if (subtract | |
5761 | || (offset & ~0x3fc)) | |
5762 | { | |
5763 | inst.error = _("invalid immediate for address calculation"); | |
5764 | return; | |
5765 | } | |
5766 | inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC | |
5767 | : T_OPCODE_ADD_SP); | |
5768 | inst.instruction |= (Rd << 8) | (offset >> 2); | |
5769 | } | |
5770 | else if (Rs == Rd) | |
5771 | { | |
5772 | if (offset & ~0xff) | |
5773 | { | |
5774 | inst.error = _("immediate value out of range"); | |
5775 | return; | |
5776 | } | |
5777 | inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
5778 | inst.instruction |= (Rd << 8) | offset; | |
5779 | } | |
5780 | else | |
5781 | { | |
5782 | if (offset & ~0x7) | |
5783 | { | |
5784 | inst.error = _("immediate value out of range"); | |
5785 | return; | |
5786 | } | |
5787 | inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
5788 | inst.instruction |= Rd | (Rs << 3) | (offset << 6); | |
5789 | } | |
5790 | } | |
5791 | } | |
5792 | ||
5793 | end_of_line (str); | |
5794 | } | |
5795 | ||
5796 | static void | |
5797 | thumb_shift (str, shift) | |
5798 | char * str; | |
5799 | int shift; | |
5800 | { | |
5801 | int Rd, Rs, Rn = FAIL; | |
5802 | ||
5803 | skip_whitespace (str); | |
5804 | ||
5805 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
5806 | || skip_past_comma (&str) == FAIL) | |
5807 | { | |
5808 | if (! inst.error) | |
5809 | inst.error = BAD_ARGS; | |
5810 | return; | |
5811 | } | |
5812 | ||
5813 | if (is_immediate_prefix (*str)) | |
5814 | { | |
5815 | /* Two operand immediate format, set Rs to Rd. */ | |
5816 | Rs = Rd; | |
5817 | str ++; | |
5818 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5819 | return; | |
5820 | } | |
5821 | else | |
5822 | { | |
5823 | if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
5824 | return; | |
5825 | ||
5826 | if (skip_past_comma (&str) == FAIL) | |
5827 | { | |
5828 | /* Two operand format, shuffle the registers | |
5829 | and pretend there are 3. */ | |
5830 | Rn = Rs; | |
5831 | Rs = Rd; | |
5832 | } | |
5833 | else if (is_immediate_prefix (*str)) | |
5834 | { | |
5835 | str++; | |
5836 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5837 | return; | |
5838 | } | |
5839 | else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
5840 | return; | |
5841 | } | |
5842 | ||
5843 | /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL; | |
5844 | for the latter case, EXPR contains the immediate that was found. */ | |
5845 | ||
5846 | if (Rn != FAIL) | |
5847 | { | |
5848 | if (Rs != Rd) | |
5849 | { | |
5850 | inst.error = _("source1 and dest must be same register"); | |
5851 | return; | |
5852 | } | |
5853 | ||
5854 | switch (shift) | |
5855 | { | |
5856 | case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break; | |
5857 | case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
5858 | case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
5859 | } | |
5860 | ||
5861 | inst.instruction |= Rd | (Rn << 3); | |
5862 | } | |
5863 | else | |
5864 | { | |
5865 | switch (shift) | |
5866 | { | |
5867 | case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
5868 | case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
5869 | case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
5870 | } | |
5871 | ||
5872 | if (inst.reloc.exp.X_op != O_constant) | |
5873 | { | |
5874 | /* Value isn't known yet, create a dummy reloc and let reloc | |
5875 | hacking fix it up. */ | |
5876 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
5877 | } | |
5878 | else | |
5879 | { | |
5880 | unsigned shift_value = inst.reloc.exp.X_add_number; | |
5881 | ||
5882 | if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL)) | |
5883 | { | |
5884 | inst.error = _("Invalid immediate for shift"); | |
5885 | return; | |
5886 | } | |
5887 | ||
5888 | /* Shifts of zero are handled by converting to LSL. */ | |
5889 | if (shift_value == 0) | |
5890 | inst.instruction = T_OPCODE_LSL_I; | |
5891 | ||
5892 | /* Shifts of 32 are encoded as a shift of zero. */ | |
5893 | if (shift_value == 32) | |
5894 | shift_value = 0; | |
5895 | ||
5896 | inst.instruction |= shift_value << 6; | |
5897 | } | |
5898 | ||
5899 | inst.instruction |= Rd | (Rs << 3); | |
5900 | } | |
5901 | ||
5902 | end_of_line (str); | |
5903 | } | |
5904 | ||
5905 | static void | |
5906 | thumb_mov_compare (str, move) | |
5907 | char * str; | |
5908 | int move; | |
5909 | { | |
5910 | int Rd, Rs = FAIL; | |
5911 | ||
5912 | skip_whitespace (str); | |
5913 | ||
5914 | if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL | |
5915 | || skip_past_comma (&str) == FAIL) | |
5916 | { | |
5917 | if (! inst.error) | |
5918 | inst.error = BAD_ARGS; | |
5919 | return; | |
5920 | } | |
5921 | ||
5922 | if (is_immediate_prefix (*str)) | |
5923 | { | |
5924 | str++; | |
5925 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5926 | return; | |
5927 | } | |
5928 | else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5929 | return; | |
5930 | ||
5931 | if (Rs != FAIL) | |
5932 | { | |
5933 | if (Rs < 8 && Rd < 8) | |
5934 | { | |
5935 | if (move == THUMB_MOVE) | |
5936 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 | |
5937 | since a MOV instruction produces unpredictable results. */ | |
5938 | inst.instruction = T_OPCODE_ADD_I3; | |
5939 | else | |
5940 | inst.instruction = T_OPCODE_CMP_LR; | |
5941 | inst.instruction |= Rd | (Rs << 3); | |
5942 | } | |
5943 | else | |
5944 | { | |
5945 | if (move == THUMB_MOVE) | |
5946 | inst.instruction = T_OPCODE_MOV_HR; | |
5947 | else | |
5948 | inst.instruction = T_OPCODE_CMP_HR; | |
5949 | ||
5950 | if (Rd > 7) | |
5951 | inst.instruction |= THUMB_H1; | |
5952 | ||
5953 | if (Rs > 7) | |
5954 | inst.instruction |= THUMB_H2; | |
5955 | ||
5956 | inst.instruction |= (Rd & 7) | ((Rs & 7) << 3); | |
5957 | } | |
5958 | } | |
5959 | else | |
5960 | { | |
5961 | if (Rd > 7) | |
5962 | { | |
5963 | inst.error = _("only lo regs allowed with immediate"); | |
5964 | return; | |
5965 | } | |
5966 | ||
5967 | if (move == THUMB_MOVE) | |
5968 | inst.instruction = T_OPCODE_MOV_I8; | |
5969 | else | |
5970 | inst.instruction = T_OPCODE_CMP_I8; | |
5971 | ||
5972 | inst.instruction |= Rd << 8; | |
5973 | ||
5974 | if (inst.reloc.exp.X_op != O_constant) | |
5975 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
5976 | else | |
5977 | { | |
5978 | unsigned value = inst.reloc.exp.X_add_number; | |
5979 | ||
5980 | if (value > 255) | |
5981 | { | |
5982 | inst.error = _("invalid immediate"); | |
5983 | return; | |
5984 | } | |
5985 | ||
5986 | inst.instruction |= value; | |
5987 | } | |
5988 | } | |
5989 | ||
5990 | end_of_line (str); | |
5991 | } | |
5992 | ||
5993 | static void | |
5994 | thumb_load_store (str, load_store, size) | |
5995 | char * str; | |
5996 | int load_store; | |
5997 | int size; | |
5998 | { | |
5999 | int Rd, Rb, Ro = FAIL; | |
6000 | ||
6001 | skip_whitespace (str); | |
6002 | ||
6003 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
6004 | || skip_past_comma (&str) == FAIL) | |
6005 | { | |
6006 | if (! inst.error) | |
6007 | inst.error = BAD_ARGS; | |
6008 | return; | |
6009 | } | |
6010 | ||
6011 | if (*str == '[') | |
6012 | { | |
6013 | str++; | |
6014 | if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
6015 | return; | |
6016 | ||
6017 | if (skip_past_comma (&str) != FAIL) | |
6018 | { | |
6019 | if (is_immediate_prefix (*str)) | |
6020 | { | |
6021 | str++; | |
6022 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6023 | return; | |
6024 | } | |
6025 | else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
6026 | return; | |
6027 | } | |
6028 | else | |
6029 | { | |
6030 | inst.reloc.exp.X_op = O_constant; | |
6031 | inst.reloc.exp.X_add_number = 0; | |
6032 | } | |
6033 | ||
6034 | if (*str != ']') | |
6035 | { | |
6036 | inst.error = _("expected ']'"); | |
6037 | return; | |
6038 | } | |
6039 | str++; | |
6040 | } | |
6041 | else if (*str == '=') | |
6042 | { | |
6043 | /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */ | |
6044 | str++; | |
6045 | ||
6046 | skip_whitespace (str); | |
6047 | ||
6048 | if (my_get_expression (& inst.reloc.exp, & str)) | |
6049 | return; | |
6050 | ||
6051 | end_of_line (str); | |
6052 | ||
6053 | if ( inst.reloc.exp.X_op != O_constant | |
6054 | && inst.reloc.exp.X_op != O_symbol) | |
6055 | { | |
6056 | inst.error = "Constant expression expected"; | |
6057 | return; | |
6058 | } | |
6059 | ||
6060 | if (inst.reloc.exp.X_op == O_constant | |
6061 | && ((inst.reloc.exp.X_add_number & ~0xFF) == 0)) | |
6062 | { | |
6063 | /* This can be done with a mov instruction. */ | |
6064 | ||
6065 | inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8); | |
6066 | inst.instruction |= inst.reloc.exp.X_add_number; | |
6067 | return; | |
6068 | } | |
6069 | ||
6070 | /* Insert into literal pool. */ | |
6071 | if (add_to_lit_pool () == FAIL) | |
6072 | { | |
6073 | if (!inst.error) | |
6074 | inst.error = "literal pool insertion failed"; | |
6075 | return; | |
6076 | } | |
6077 | ||
6078 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6079 | inst.reloc.pc_rel = 1; | |
6080 | inst.instruction = T_OPCODE_LDR_PC | (Rd << 8); | |
6081 | /* Adjust ARM pipeline offset to Thumb. */ | |
6082 | inst.reloc.exp.X_add_number += 4; | |
6083 | ||
6084 | return; | |
6085 | } | |
6086 | else | |
6087 | { | |
6088 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6089 | return; | |
6090 | ||
6091 | inst.instruction = T_OPCODE_LDR_PC | (Rd << 8); | |
6092 | inst.reloc.pc_rel = 1; | |
6093 | inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */ | |
6094 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6095 | end_of_line (str); | |
6096 | return; | |
6097 | } | |
6098 | ||
6099 | if (Rb == REG_PC || Rb == REG_SP) | |
6100 | { | |
6101 | if (size != THUMB_WORD) | |
6102 | { | |
6103 | inst.error = _("byte or halfword not valid for base register"); | |
6104 | return; | |
6105 | } | |
6106 | else if (Rb == REG_PC && load_store != THUMB_LOAD) | |
6107 | { | |
6108 | inst.error = _("R15 based store not allowed"); | |
6109 | return; | |
6110 | } | |
6111 | else if (Ro != FAIL) | |
6112 | { | |
6113 | inst.error = _("Invalid base register for register offset"); | |
6114 | return; | |
6115 | } | |
6116 | ||
6117 | if (Rb == REG_PC) | |
6118 | inst.instruction = T_OPCODE_LDR_PC; | |
6119 | else if (load_store == THUMB_LOAD) | |
6120 | inst.instruction = T_OPCODE_LDR_SP; | |
6121 | else | |
6122 | inst.instruction = T_OPCODE_STR_SP; | |
6123 | ||
6124 | inst.instruction |= Rd << 8; | |
6125 | if (inst.reloc.exp.X_op == O_constant) | |
6126 | { | |
6127 | unsigned offset = inst.reloc.exp.X_add_number; | |
6128 | ||
6129 | if (offset & ~0x3fc) | |
6130 | { | |
6131 | inst.error = _("invalid offset"); | |
6132 | return; | |
6133 | } | |
6134 | ||
6135 | inst.instruction |= offset >> 2; | |
6136 | } | |
6137 | else | |
6138 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6139 | } | |
6140 | else if (Rb > 7) | |
6141 | { | |
6142 | inst.error = _("invalid base register in load/store"); | |
6143 | return; | |
6144 | } | |
6145 | else if (Ro == FAIL) | |
6146 | { | |
6147 | /* Immediate offset. */ | |
6148 | if (size == THUMB_WORD) | |
6149 | inst.instruction = (load_store == THUMB_LOAD | |
6150 | ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW); | |
6151 | else if (size == THUMB_HALFWORD) | |
6152 | inst.instruction = (load_store == THUMB_LOAD | |
6153 | ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH); | |
6154 | else | |
6155 | inst.instruction = (load_store == THUMB_LOAD | |
6156 | ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB); | |
6157 | ||
6158 | inst.instruction |= Rd | (Rb << 3); | |
6159 | ||
6160 | if (inst.reloc.exp.X_op == O_constant) | |
6161 | { | |
6162 | unsigned offset = inst.reloc.exp.X_add_number; | |
6163 | ||
6164 | if (offset & ~(0x1f << size)) | |
6165 | { | |
6166 | inst.error = _("Invalid offset"); | |
6167 | return; | |
6168 | } | |
6169 | inst.instruction |= (offset >> size) << 6; | |
6170 | } | |
6171 | else | |
6172 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6173 | } | |
6174 | else | |
6175 | { | |
6176 | /* Register offset. */ | |
6177 | if (size == THUMB_WORD) | |
6178 | inst.instruction = (load_store == THUMB_LOAD | |
6179 | ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW); | |
6180 | else if (size == THUMB_HALFWORD) | |
6181 | inst.instruction = (load_store == THUMB_LOAD | |
6182 | ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH); | |
6183 | else | |
6184 | inst.instruction = (load_store == THUMB_LOAD | |
6185 | ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB); | |
6186 | ||
6187 | inst.instruction |= Rd | (Rb << 3) | (Ro << 6); | |
6188 | } | |
6189 | ||
6190 | end_of_line (str); | |
6191 | } | |
6192 | ||
404ff6b5 AH |
6193 | /* Given a register and a register type, return 1 if |
6194 | the register is of the given type, else return 0. */ | |
6195 | ||
6196 | static int | |
6197 | cirrus_valid_reg (reg, regtype) | |
6198 | int reg; | |
6199 | enum cirrus_regtype regtype; | |
6200 | { | |
6201 | switch (regtype) | |
6202 | { | |
6203 | case CIRRUS_REGTYPE_ANY: | |
6204 | return 1; | |
6205 | ||
6206 | case CIRRUS_REGTYPE_MVF: | |
6207 | return cirrus_mvf_register (reg); | |
6208 | ||
6209 | case CIRRUS_REGTYPE_MVFX: | |
6210 | return cirrus_mvfx_register (reg); | |
6211 | ||
6212 | case CIRRUS_REGTYPE_MVD: | |
6213 | return cirrus_mvd_register (reg); | |
6214 | ||
6215 | case CIRRUS_REGTYPE_MVDX: | |
6216 | return cirrus_mvdx_register (reg); | |
6217 | ||
6218 | case CIRRUS_REGTYPE_MVAX: | |
6219 | return cirrus_mvax_register (reg); | |
6220 | ||
6221 | case CIRRUS_REGTYPE_DSPSC: | |
90f9b791 | 6222 | return ARM_EXT_MAVERICKsc_register (reg); |
404ff6b5 AH |
6223 | } |
6224 | ||
6225 | return 0; | |
6226 | } | |
6227 | ||
6228 | /* A register must be given at this point. | |
6229 | ||
6230 | If the register is a Cirrus register, convert it's reg# appropriately. | |
6231 | ||
6232 | Shift is the place to put it in inst.instruction. | |
6233 | ||
6234 | regtype is type register type expected, and is: | |
6235 | CIRRUS_REGTYPE_MVF | |
6236 | CIRRUS_REGTYPE_MVFX | |
6237 | CIRRUS_REGTYPE_MVD | |
6238 | CIRRUS_REGTYPE_MVDX | |
6239 | CIRRUS_REGTYPE_MVAX | |
6240 | CIRRUS_REGTYPE_DSPSC | |
6241 | ||
6242 | Restores input start point on err. | |
6243 | Returns the reg#, or FAIL. */ | |
6244 | ||
6245 | static int | |
6246 | cirrus_reg_required_here (str, shift, regtype) | |
6247 | char ** str; | |
6248 | int shift; | |
6249 | enum cirrus_regtype regtype; | |
6250 | { | |
6251 | static char buff [135]; /* XXX */ | |
6252 | int reg; | |
6253 | char * start = * str; | |
6254 | ||
6255 | if ((reg = arm_reg_parse (str)) != FAIL | |
6256 | && (int_register (reg) | |
6257 | || cirrus_register (reg))) | |
6258 | { | |
6259 | int orig_reg = reg; | |
6260 | ||
6261 | /* Calculate actual register # for opcode. */ | |
6262 | if (cirrus_register (reg) | |
90f9b791 | 6263 | && !ARM_EXT_MAVERICKsc_register (reg)) /* Leave this one as is. */ |
404ff6b5 AH |
6264 | { |
6265 | if (reg >= 130) | |
6266 | reg -= 130; | |
6267 | else if (reg >= 110) | |
6268 | reg -= 110; | |
6269 | else if (reg >= 90) | |
6270 | reg -= 90; | |
6271 | else if (reg >= 70) | |
6272 | reg -= 70; | |
6273 | else if (reg >= 50) | |
6274 | reg -= 50; | |
6275 | } | |
6276 | ||
6277 | if (!cirrus_valid_reg (orig_reg, regtype)) | |
6278 | { | |
6279 | sprintf (buff, _("invalid register type at '%.100s'"), start); | |
6280 | inst.error = buff; | |
6281 | return FAIL; | |
6282 | } | |
6283 | ||
6284 | if (shift >= 0) | |
6285 | inst.instruction |= reg << shift; | |
6286 | ||
6287 | return orig_reg; | |
6288 | } | |
6289 | ||
6290 | /* Restore the start point, we may have got a reg of the wrong class. */ | |
6291 | *str = start; | |
6292 | ||
6293 | /* In the few cases where we might be able to accept something else | |
6294 | this error can be overridden. */ | |
6295 | sprintf (buff, _("Cirrus register expected, not '%.100s'"), start); | |
6296 | inst.error = buff; | |
6297 | ||
6298 | return FAIL; | |
6299 | } | |
6300 | ||
6301 | /* Cirrus Instructions. */ | |
6302 | ||
6303 | /* Wrapper functions. */ | |
6304 | ||
6305 | static void | |
6306 | do_c_binops_1 (str, flags) | |
6307 | char * str; | |
6308 | unsigned long flags; | |
6309 | { | |
6310 | do_c_binops (str, flags, CIRRUS_MODE1); | |
6311 | } | |
6312 | ||
6313 | static void | |
6314 | do_c_binops_2 (str, flags) | |
6315 | char * str; | |
6316 | unsigned long flags; | |
6317 | { | |
6318 | do_c_binops (str, flags, CIRRUS_MODE2); | |
6319 | } | |
6320 | ||
6321 | static void | |
6322 | do_c_binops_3 (str, flags) | |
6323 | char * str; | |
6324 | unsigned long flags; | |
6325 | { | |
6326 | do_c_binops (str, flags, CIRRUS_MODE3); | |
6327 | } | |
6328 | ||
6329 | static void | |
6330 | do_c_triple_4 (str, flags) | |
6331 | char * str; | |
6332 | unsigned long flags; | |
6333 | { | |
6334 | do_c_triple (str, flags, CIRRUS_MODE4); | |
6335 | } | |
6336 | ||
6337 | static void | |
6338 | do_c_triple_5 (str, flags) | |
6339 | char * str; | |
6340 | unsigned long flags; | |
6341 | { | |
6342 | do_c_triple (str, flags, CIRRUS_MODE5); | |
6343 | } | |
6344 | ||
6345 | static void | |
6346 | do_c_quad_6 (str, flags) | |
6347 | char * str; | |
6348 | unsigned long flags; | |
6349 | { | |
6350 | do_c_quad (str, flags, CIRRUS_MODE6); | |
6351 | } | |
6352 | ||
6353 | static void | |
6354 | do_c_dspsc_1 (str, flags) | |
6355 | char * str; | |
6356 | unsigned long flags; | |
6357 | { | |
6358 | do_c_dspsc (str, flags, CIRRUS_MODE1); | |
6359 | } | |
6360 | ||
6361 | static void | |
6362 | do_c_dspsc_2 (str, flags) | |
6363 | char * str; | |
6364 | unsigned long flags; | |
6365 | { | |
6366 | do_c_dspsc (str, flags, CIRRUS_MODE2); | |
6367 | } | |
6368 | ||
6369 | static void | |
6370 | do_c_shift_1 (str, flags) | |
6371 | char * str; | |
6372 | unsigned long flags; | |
6373 | { | |
6374 | do_c_shift (str, flags, CIRRUS_MODE1); | |
6375 | } | |
6376 | ||
6377 | static void | |
6378 | do_c_shift_2 (str, flags) | |
6379 | char * str; | |
6380 | unsigned long flags; | |
6381 | { | |
6382 | do_c_shift (str, flags, CIRRUS_MODE2); | |
6383 | } | |
6384 | ||
6385 | static void | |
6386 | do_c_ldst_1 (str, flags) | |
6387 | char * str; | |
6388 | unsigned long flags; | |
6389 | { | |
6390 | do_c_ldst (str, flags, CIRRUS_MODE1); | |
6391 | } | |
6392 | ||
6393 | static void | |
6394 | do_c_ldst_2 (str, flags) | |
6395 | char * str; | |
6396 | unsigned long flags; | |
6397 | { | |
6398 | do_c_ldst (str, flags, CIRRUS_MODE2); | |
6399 | } | |
6400 | ||
6401 | static void | |
6402 | do_c_ldst_3 (str, flags) | |
6403 | char * str; | |
6404 | unsigned long flags; | |
6405 | { | |
6406 | do_c_ldst (str, flags, CIRRUS_MODE3); | |
6407 | } | |
6408 | ||
6409 | static void | |
6410 | do_c_ldst_4 (str, flags) | |
6411 | char * str; | |
6412 | unsigned long flags; | |
6413 | { | |
6414 | do_c_ldst (str, flags, CIRRUS_MODE4); | |
6415 | } | |
6416 | ||
6417 | /* Isnsn like "foo X,Y". */ | |
6418 | ||
6419 | static void | |
6420 | do_c_binops (str, flags, mode) | |
6421 | char * str; | |
6422 | unsigned long flags; | |
6423 | int mode; | |
6424 | { | |
6425 | int shift1, shift2; | |
6426 | ||
6427 | shift1 = mode & 0xff; | |
6428 | shift2 = (mode >> 8) & 0xff; | |
6429 | ||
6430 | skip_whitespace (str); | |
6431 | ||
6432 | if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL | |
6433 | || skip_past_comma (&str) == FAIL | |
6434 | || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL) | |
6435 | { | |
6436 | if (!inst.error) | |
6437 | inst.error = BAD_ARGS; | |
6438 | } | |
6439 | else | |
6440 | end_of_line (str); | |
6441 | ||
6442 | inst.instruction |= flags; | |
6443 | return; | |
6444 | } | |
6445 | ||
6446 | /* Isnsn like "foo X,Y,Z". */ | |
6447 | ||
6448 | static void | |
6449 | do_c_triple (str, flags, mode) | |
6450 | char * str; | |
6451 | unsigned long flags; | |
6452 | int mode; | |
6453 | { | |
6454 | int shift1, shift2, shift3; | |
6455 | ||
6456 | shift1 = mode & 0xff; | |
6457 | shift2 = (mode >> 8) & 0xff; | |
6458 | shift3 = (mode >> 16) & 0xff; | |
6459 | ||
6460 | skip_whitespace (str); | |
6461 | ||
6462 | if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL | |
6463 | || skip_past_comma (&str) == FAIL | |
6464 | || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL | |
6465 | || skip_past_comma (&str) == FAIL | |
6466 | || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_ANY) == FAIL) | |
6467 | { | |
6468 | if (!inst.error) | |
6469 | inst.error = BAD_ARGS; | |
6470 | } | |
6471 | else | |
6472 | end_of_line (str); | |
6473 | ||
6474 | inst.instruction |= flags; | |
6475 | return; | |
6476 | } | |
6477 | ||
6478 | /* Isnsn like "foo W,X,Y,Z". | |
6479 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
6480 | ||
6481 | static void | |
6482 | do_c_quad (str, flags, mode) | |
6483 | char * str; | |
6484 | unsigned long flags; | |
6485 | int mode; | |
6486 | { | |
6487 | int shift1, shift2, shift3, shift4; | |
6488 | enum cirrus_regtype rt; | |
6489 | ||
6490 | rt = (inst.instruction << 4 == 0xe2006000 | |
6491 | || inst.instruction << 4 == 0xe3006000) ? CIRRUS_REGTYPE_MVAX | |
6492 | : CIRRUS_REGTYPE_MVFX; | |
6493 | ||
6494 | shift1 = mode & 0xff; | |
6495 | shift2 = (mode >> 8) & 0xff; | |
6496 | shift3 = (mode >> 16) & 0xff; | |
6497 | shift4 = (mode >> 24) & 0xff; | |
6498 | ||
6499 | skip_whitespace (str); | |
6500 | ||
6501 | if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_MVAX) == FAIL | |
6502 | || skip_past_comma (&str) == FAIL | |
6503 | || cirrus_reg_required_here (&str, shift2, rt) == FAIL | |
6504 | || skip_past_comma (&str) == FAIL | |
6505 | || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_MVFX) == FAIL | |
6506 | || skip_past_comma (&str) == FAIL | |
6507 | || cirrus_reg_required_here (&str, shift4, CIRRUS_REGTYPE_MVFX) == FAIL) | |
6508 | { | |
6509 | if (!inst.error) | |
6510 | inst.error = BAD_ARGS; | |
6511 | } | |
6512 | else | |
6513 | end_of_line (str); | |
6514 | ||
6515 | inst.instruction |= flags; | |
6516 | return; | |
6517 | } | |
6518 | ||
6519 | /* cfmvsc32<cond> DSPSC,MVFX[15:0]. | |
6520 | cfmv32sc<cond> MVFX[15:0],DSPSC. */ | |
6521 | ||
6522 | static void | |
6523 | do_c_dspsc (str, flags, mode) | |
6524 | char * str; | |
6525 | unsigned long flags; | |
6526 | int mode; | |
6527 | { | |
6528 | int error; | |
6529 | ||
6530 | skip_whitespace (str); | |
6531 | ||
6532 | error = 0; | |
6533 | ||
6534 | if (mode == CIRRUS_MODE1) | |
6535 | { | |
6536 | /* cfmvsc32. */ | |
6537 | if (cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL | |
6538 | || skip_past_comma (&str) == FAIL | |
6539 | || cirrus_reg_required_here (&str, 16, CIRRUS_REGTYPE_MVFX) == FAIL) | |
6540 | error = 1; | |
6541 | } | |
6542 | else | |
6543 | { | |
6544 | /* cfmv32sc. */ | |
6545 | if (cirrus_reg_required_here (&str, 0, CIRRUS_REGTYPE_MVFX) == FAIL | |
6546 | || skip_past_comma (&str) == FAIL | |
6547 | || cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL) | |
6548 | error = 1; | |
6549 | } | |
6550 | ||
6551 | if (error) | |
6552 | { | |
6553 | if (!inst.error) | |
6554 | inst.error = BAD_ARGS; | |
6555 | } | |
6556 | else | |
6557 | { | |
6558 | inst.instruction |= flags; | |
6559 | end_of_line (str); | |
6560 | } | |
6561 | ||
6562 | return; | |
6563 | } | |
6564 | ||
6565 | /* Cirrus shift immediate instructions. | |
6566 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
6567 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
6568 | ||
6569 | static void | |
6570 | do_c_shift (str, flags, mode) | |
6571 | char * str; | |
6572 | unsigned long flags; | |
6573 | int mode; | |
6574 | { | |
6575 | int error; | |
6576 | int imm, neg = 0; | |
6577 | ||
6578 | skip_whitespace (str); | |
6579 | ||
6580 | error = 0; | |
6581 | ||
6582 | if (cirrus_reg_required_here (&str, 12, | |
6583 | (mode == CIRRUS_MODE1) | |
6584 | ? CIRRUS_REGTYPE_MVFX | |
6585 | : CIRRUS_REGTYPE_MVDX) == FAIL | |
6586 | || skip_past_comma (&str) == FAIL | |
6587 | || cirrus_reg_required_here (&str, 16, | |
6588 | (mode == CIRRUS_MODE1) | |
6589 | ? CIRRUS_REGTYPE_MVFX | |
6590 | : CIRRUS_REGTYPE_MVDX) == FAIL | |
6591 | || skip_past_comma (&str) == FAIL) | |
6592 | { | |
6593 | if (!inst.error) | |
6594 | inst.error = BAD_ARGS; | |
6595 | return; | |
6596 | } | |
6597 | ||
6598 | /* Calculate the immediate operand. | |
6599 | The operand is a 7bit signed number. */ | |
6600 | skip_whitespace (str); | |
6601 | ||
6602 | if (*str == '#') | |
6603 | ++str; | |
6604 | ||
8420dfca | 6605 | if (!ISDIGIT (*str) && *str != '-') |
404ff6b5 AH |
6606 | { |
6607 | inst.error = _("expecting immediate, 7bit operand"); | |
6608 | return; | |
6609 | } | |
6610 | ||
6611 | if (*str == '-') | |
6612 | { | |
6613 | neg = 1; | |
6614 | ++str; | |
6615 | } | |
6616 | ||
8420dfca | 6617 | for (imm = 0; *str && ISDIGIT (*str); ++str) |
404ff6b5 AH |
6618 | imm = imm * 10 + *str - '0'; |
6619 | ||
6620 | if (imm > 64) | |
6621 | { | |
6622 | inst.error = _("immediate out of range"); | |
6623 | return; | |
6624 | } | |
6625 | ||
6626 | /* Make negative imm's into 7bit signed numbers. */ | |
6627 | if (neg) | |
6628 | { | |
6629 | imm = -imm; | |
6630 | imm &= 0x0000007f; | |
6631 | } | |
6632 | ||
6633 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. | |
6634 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
6635 | Bit 4 should be 0. */ | |
6636 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
6637 | ||
6638 | inst.instruction |= imm; | |
6639 | inst.instruction |= flags; | |
6640 | ||
6641 | end_of_line (str); | |
6642 | ||
6643 | return; | |
6644 | } | |
6645 | ||
6646 | static int | |
6647 | cirrus_parse_offset (str, negative) | |
6648 | char ** str; | |
6649 | int *negative; | |
6650 | { | |
6651 | char * p = *str; | |
6652 | int offset; | |
6653 | ||
6654 | *negative = 0; | |
6655 | ||
6656 | skip_whitespace (p); | |
6657 | ||
6658 | if (*p == '#') | |
6659 | ++p; | |
6660 | ||
6661 | if (*p == '-') | |
6662 | { | |
6663 | *negative = 1; | |
6664 | ++p; | |
6665 | } | |
6666 | ||
8420dfca | 6667 | if (!ISDIGIT (*p)) |
404ff6b5 AH |
6668 | { |
6669 | inst.error = _("offset expected"); | |
6670 | return 0; | |
6671 | } | |
6672 | ||
8420dfca | 6673 | for (offset = 0; *p && ISDIGIT (*p); ++p) |
404ff6b5 AH |
6674 | offset = offset * 10 + *p - '0'; |
6675 | ||
6676 | if (offset > 0xff) | |
6677 | { | |
6678 | inst.error = _("offset out of range"); | |
6679 | return 0; | |
6680 | } | |
6681 | ||
6682 | *str = p; | |
6683 | ||
6684 | return *negative ? -offset : offset; | |
6685 | } | |
6686 | ||
6687 | /* Cirrus load/store instructions. | |
6688 | <insn><cond> CRd,[Rn,<offset>]{!}. | |
6689 | <insn><cond> CRd,[Rn],<offset>. */ | |
6690 | ||
6691 | static void | |
6692 | do_c_ldst (str, flags, mode) | |
6693 | char * str; | |
6694 | unsigned long flags; | |
6695 | int mode; | |
6696 | { | |
6697 | int offset, negative; | |
6698 | enum cirrus_regtype rt; | |
6699 | ||
6700 | rt = mode == CIRRUS_MODE1 ? CIRRUS_REGTYPE_MVF | |
6701 | : mode == CIRRUS_MODE2 ? CIRRUS_REGTYPE_MVD | |
6702 | : mode == CIRRUS_MODE3 ? CIRRUS_REGTYPE_MVFX | |
6703 | : mode == CIRRUS_MODE4 ? CIRRUS_REGTYPE_MVDX : CIRRUS_REGTYPE_MVF; | |
6704 | ||
6705 | skip_whitespace (str); | |
6706 | ||
6707 | if (cirrus_reg_required_here (& str, 12, rt) == FAIL | |
6708 | || skip_past_comma (& str) == FAIL | |
6709 | || *str++ != '[' | |
6710 | || reg_required_here (& str, 16) == FAIL) | |
6711 | goto fail_ldst; | |
6712 | ||
6713 | if (skip_past_comma (& str) == SUCCESS) | |
6714 | { | |
6715 | /* You are here: "<offset>]{!}". */ | |
6716 | inst.instruction |= PRE_INDEX; | |
6717 | ||
6718 | offset = cirrus_parse_offset (&str, &negative); | |
6719 | ||
6720 | if (inst.error) | |
6721 | return; | |
6722 | ||
6723 | if (*str++ != ']') | |
6724 | { | |
6725 | inst.error = _("missing ]"); | |
6726 | return; | |
6727 | } | |
6728 | ||
6729 | if (*str == '!') | |
6730 | { | |
6731 | inst.instruction |= WRITE_BACK; | |
6732 | ++str; | |
6733 | } | |
6734 | } | |
6735 | else | |
6736 | { | |
6737 | /* You are here: "], <offset>". */ | |
6738 | if (*str++ != ']') | |
6739 | { | |
6740 | inst.error = _("missing ]"); | |
6741 | return; | |
6742 | } | |
6743 | ||
6744 | if (skip_past_comma (&str) == FAIL | |
6745 | || (offset = cirrus_parse_offset (&str, &negative), inst.error)) | |
6746 | goto fail_ldst; | |
6747 | ||
6748 | inst.instruction |= CP_T_WB; /* Post indexed, set bit W. */ | |
6749 | } | |
6750 | ||
6751 | if (negative) | |
6752 | offset = -offset; | |
6753 | else | |
6754 | inst.instruction |= CP_T_UD; /* Postive, so set bit U. */ | |
6755 | ||
6756 | inst.instruction |= offset >> 2; | |
6757 | inst.instruction |= flags; | |
6758 | ||
6759 | end_of_line (str); | |
6760 | return; | |
6761 | ||
6762 | fail_ldst: | |
6763 | if (!inst.error) | |
6764 | inst.error = BAD_ARGS; | |
6765 | return; | |
6766 | } | |
6767 | ||
b99bd4ef NC |
6768 | static void |
6769 | do_t_nop (str) | |
6770 | char * str; | |
6771 | { | |
6772 | /* Do nothing. */ | |
6773 | end_of_line (str); | |
6774 | return; | |
6775 | } | |
6776 | ||
6777 | /* Handle the Format 4 instructions that do not have equivalents in other | |
6778 | formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL, | |
6779 | BIC and MVN. */ | |
6780 | ||
6781 | static void | |
6782 | do_t_arit (str) | |
6783 | char * str; | |
6784 | { | |
6785 | int Rd, Rs, Rn; | |
6786 | ||
6787 | skip_whitespace (str); | |
6788 | ||
6789 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
6790 | || skip_past_comma (&str) == FAIL | |
6791 | || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
6792 | { | |
6793 | inst.error = BAD_ARGS; | |
6794 | return; | |
6795 | } | |
6796 | ||
6797 | if (skip_past_comma (&str) != FAIL) | |
6798 | { | |
6799 | /* Three operand format not allowed for TST, CMN, NEG and MVN. | |
6800 | (It isn't allowed for CMP either, but that isn't handled by this | |
6801 | function.) */ | |
6802 | if (inst.instruction == T_OPCODE_TST | |
6803 | || inst.instruction == T_OPCODE_CMN | |
6804 | || inst.instruction == T_OPCODE_NEG | |
6805 | || inst.instruction == T_OPCODE_MVN) | |
6806 | { | |
6807 | inst.error = BAD_ARGS; | |
6808 | return; | |
6809 | } | |
6810 | ||
6811 | if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
6812 | return; | |
6813 | ||
6814 | if (Rs != Rd) | |
6815 | { | |
6816 | inst.error = _("dest and source1 must be the same register"); | |
6817 | return; | |
6818 | } | |
6819 | Rs = Rn; | |
6820 | } | |
6821 | ||
6822 | if (inst.instruction == T_OPCODE_MUL | |
6823 | && Rs == Rd) | |
6824 | as_tsktsk (_("Rs and Rd must be different in MUL")); | |
6825 | ||
6826 | inst.instruction |= Rd | (Rs << 3); | |
6827 | end_of_line (str); | |
6828 | } | |
6829 | ||
6830 | static void | |
6831 | do_t_add (str) | |
6832 | char * str; | |
6833 | { | |
6834 | thumb_add_sub (str, 0); | |
6835 | } | |
6836 | ||
6837 | static void | |
6838 | do_t_asr (str) | |
6839 | char * str; | |
6840 | { | |
6841 | thumb_shift (str, THUMB_ASR); | |
6842 | } | |
6843 | ||
6844 | static void | |
6845 | do_t_branch9 (str) | |
6846 | char * str; | |
6847 | { | |
6848 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6849 | return; | |
6850 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
6851 | inst.reloc.pc_rel = 1; | |
6852 | end_of_line (str); | |
6853 | } | |
6854 | ||
6855 | static void | |
6856 | do_t_branch12 (str) | |
6857 | char * str; | |
6858 | { | |
6859 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6860 | return; | |
6861 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
6862 | inst.reloc.pc_rel = 1; | |
6863 | end_of_line (str); | |
6864 | } | |
6865 | ||
6866 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
6867 | ||
6868 | static symbolS * | |
6869 | find_real_start (symbolP) | |
6870 | symbolS * symbolP; | |
6871 | { | |
6872 | char * real_start; | |
6873 | const char * name = S_GET_NAME (symbolP); | |
6874 | symbolS * new_target; | |
6875 | ||
6876 | /* This definiton must agree with the one in gcc/config/arm/thumb.c. */ | |
6877 | #define STUB_NAME ".real_start_of" | |
6878 | ||
6879 | if (name == NULL) | |
6880 | abort (); | |
6881 | ||
6882 | /* Names that start with '.' are local labels, not function entry points. | |
6883 | The compiler may generate BL instructions to these labels because it | |
6884 | needs to perform a branch to a far away location. */ | |
6885 | if (name[0] == '.') | |
6886 | return symbolP; | |
6887 | ||
6888 | real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1); | |
6889 | sprintf (real_start, "%s%s", STUB_NAME, name); | |
6890 | ||
6891 | new_target = symbol_find (real_start); | |
6892 | ||
6893 | if (new_target == NULL) | |
6894 | { | |
6895 | as_warn ("Failed to find real start of function: %s\n", name); | |
6896 | new_target = symbolP; | |
6897 | } | |
6898 | ||
6899 | free (real_start); | |
6900 | ||
6901 | return new_target; | |
6902 | } | |
6903 | ||
6904 | static void | |
6905 | do_t_branch23 (str) | |
6906 | char * str; | |
6907 | { | |
6908 | if (my_get_expression (& inst.reloc.exp, & str)) | |
6909 | return; | |
6910 | ||
6911 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
6912 | inst.reloc.pc_rel = 1; | |
6913 | end_of_line (str); | |
6914 | ||
6915 | /* If the destination of the branch is a defined symbol which does not have | |
6916 | the THUMB_FUNC attribute, then we must be calling a function which has | |
6917 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
6918 | function and change the branch to refer to that function instead. */ | |
6919 | if ( inst.reloc.exp.X_op == O_symbol | |
6920 | && inst.reloc.exp.X_add_symbol != NULL | |
6921 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
6922 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
6923 | inst.reloc.exp.X_add_symbol = | |
6924 | find_real_start (inst.reloc.exp.X_add_symbol); | |
6925 | } | |
6926 | ||
6927 | static void | |
6928 | do_t_bx (str) | |
6929 | char * str; | |
6930 | { | |
6931 | int reg; | |
6932 | ||
6933 | skip_whitespace (str); | |
6934 | ||
6935 | if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
6936 | return; | |
6937 | ||
6938 | /* This sets THUMB_H2 from the top bit of reg. */ | |
6939 | inst.instruction |= reg << 3; | |
6940 | ||
6941 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
6942 | should cause the alignment to be checked once it is known. This is | |
6943 | because BX PC only works if the instruction is word aligned. */ | |
6944 | ||
6945 | end_of_line (str); | |
6946 | } | |
6947 | ||
6948 | static void | |
6949 | do_t_compare (str) | |
6950 | char * str; | |
6951 | { | |
6952 | thumb_mov_compare (str, THUMB_COMPARE); | |
6953 | } | |
6954 | ||
6955 | static void | |
6956 | do_t_ldmstm (str) | |
6957 | char * str; | |
6958 | { | |
6959 | int Rb; | |
6960 | long range; | |
6961 | ||
6962 | skip_whitespace (str); | |
6963 | ||
6964 | if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
6965 | return; | |
6966 | ||
6967 | if (*str != '!') | |
6968 | as_warn (_("Inserted missing '!': load/store multiple always writes back base register")); | |
6969 | else | |
6970 | str++; | |
6971 | ||
6972 | if (skip_past_comma (&str) == FAIL | |
6973 | || (range = reg_list (&str)) == FAIL) | |
6974 | { | |
6975 | if (! inst.error) | |
6976 | inst.error = BAD_ARGS; | |
6977 | return; | |
6978 | } | |
6979 | ||
6980 | if (inst.reloc.type != BFD_RELOC_NONE) | |
6981 | { | |
6982 | /* This really doesn't seem worth it. */ | |
6983 | inst.reloc.type = BFD_RELOC_NONE; | |
6984 | inst.error = _("Expression too complex"); | |
6985 | return; | |
6986 | } | |
6987 | ||
6988 | if (range & ~0xff) | |
6989 | { | |
6990 | inst.error = _("only lo-regs valid in load/store multiple"); | |
6991 | return; | |
6992 | } | |
6993 | ||
6994 | inst.instruction |= (Rb << 8) | range; | |
6995 | end_of_line (str); | |
6996 | } | |
6997 | ||
6998 | static void | |
6999 | do_t_ldr (str) | |
7000 | char * str; | |
7001 | { | |
7002 | thumb_load_store (str, THUMB_LOAD, THUMB_WORD); | |
7003 | } | |
7004 | ||
7005 | static void | |
7006 | do_t_ldrb (str) | |
7007 | char * str; | |
7008 | { | |
7009 | thumb_load_store (str, THUMB_LOAD, THUMB_BYTE); | |
7010 | } | |
7011 | ||
7012 | static void | |
7013 | do_t_ldrh (str) | |
7014 | char * str; | |
7015 | { | |
7016 | thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD); | |
7017 | } | |
7018 | ||
7019 | static void | |
7020 | do_t_lds (str) | |
7021 | char * str; | |
7022 | { | |
7023 | int Rd, Rb, Ro; | |
7024 | ||
7025 | skip_whitespace (str); | |
7026 | ||
7027 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
7028 | || skip_past_comma (&str) == FAIL | |
7029 | || *str++ != '[' | |
7030 | || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
7031 | || skip_past_comma (&str) == FAIL | |
7032 | || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
7033 | || *str++ != ']') | |
7034 | { | |
7035 | if (! inst.error) | |
7036 | inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]"); | |
7037 | return; | |
7038 | } | |
7039 | ||
7040 | inst.instruction |= Rd | (Rb << 3) | (Ro << 6); | |
7041 | end_of_line (str); | |
7042 | } | |
7043 | ||
7044 | static void | |
7045 | do_t_lsl (str) | |
7046 | char * str; | |
7047 | { | |
7048 | thumb_shift (str, THUMB_LSL); | |
7049 | } | |
7050 | ||
7051 | static void | |
7052 | do_t_lsr (str) | |
7053 | char * str; | |
7054 | { | |
7055 | thumb_shift (str, THUMB_LSR); | |
7056 | } | |
7057 | ||
7058 | static void | |
7059 | do_t_mov (str) | |
7060 | char * str; | |
7061 | { | |
7062 | thumb_mov_compare (str, THUMB_MOVE); | |
7063 | } | |
7064 | ||
7065 | static void | |
7066 | do_t_push_pop (str) | |
7067 | char * str; | |
7068 | { | |
7069 | long range; | |
7070 | ||
7071 | skip_whitespace (str); | |
7072 | ||
7073 | if ((range = reg_list (&str)) == FAIL) | |
7074 | { | |
7075 | if (! inst.error) | |
7076 | inst.error = BAD_ARGS; | |
7077 | return; | |
7078 | } | |
7079 | ||
7080 | if (inst.reloc.type != BFD_RELOC_NONE) | |
7081 | { | |
7082 | /* This really doesn't seem worth it. */ | |
7083 | inst.reloc.type = BFD_RELOC_NONE; | |
7084 | inst.error = _("Expression too complex"); | |
7085 | return; | |
7086 | } | |
7087 | ||
7088 | if (range & ~0xff) | |
7089 | { | |
7090 | if ((inst.instruction == T_OPCODE_PUSH | |
7091 | && (range & ~0xff) == 1 << REG_LR) | |
7092 | || (inst.instruction == T_OPCODE_POP | |
7093 | && (range & ~0xff) == 1 << REG_PC)) | |
7094 | { | |
7095 | inst.instruction |= THUMB_PP_PC_LR; | |
7096 | range &= 0xff; | |
7097 | } | |
7098 | else | |
7099 | { | |
7100 | inst.error = _("invalid register list to push/pop instruction"); | |
7101 | return; | |
7102 | } | |
7103 | } | |
7104 | ||
7105 | inst.instruction |= range; | |
7106 | end_of_line (str); | |
7107 | } | |
7108 | ||
7109 | static void | |
7110 | do_t_str (str) | |
7111 | char * str; | |
7112 | { | |
7113 | thumb_load_store (str, THUMB_STORE, THUMB_WORD); | |
7114 | } | |
7115 | ||
7116 | static void | |
7117 | do_t_strb (str) | |
7118 | char * str; | |
7119 | { | |
7120 | thumb_load_store (str, THUMB_STORE, THUMB_BYTE); | |
7121 | } | |
7122 | ||
7123 | static void | |
7124 | do_t_strh (str) | |
7125 | char * str; | |
7126 | { | |
7127 | thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD); | |
7128 | } | |
7129 | ||
7130 | static void | |
7131 | do_t_sub (str) | |
7132 | char * str; | |
7133 | { | |
7134 | thumb_add_sub (str, 1); | |
7135 | } | |
7136 | ||
7137 | static void | |
7138 | do_t_swi (str) | |
7139 | char * str; | |
7140 | { | |
7141 | skip_whitespace (str); | |
7142 | ||
7143 | if (my_get_expression (&inst.reloc.exp, &str)) | |
7144 | return; | |
7145 | ||
7146 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
7147 | end_of_line (str); | |
7148 | return; | |
7149 | } | |
7150 | ||
7151 | static void | |
7152 | do_t_adr (str) | |
7153 | char * str; | |
7154 | { | |
7155 | int reg; | |
7156 | ||
7157 | /* This is a pseudo-op of the form "adr rd, label" to be converted | |
7158 | into a relative address of the form "add rd, pc, #label-.-4". */ | |
7159 | skip_whitespace (str); | |
7160 | ||
7161 | /* Store Rd in temporary location inside instruction. */ | |
7162 | if ((reg = reg_required_here (&str, 4)) == FAIL | |
7163 | || (reg > 7) /* For Thumb reg must be r0..r7. */ | |
7164 | || skip_past_comma (&str) == FAIL | |
7165 | || my_get_expression (&inst.reloc.exp, &str)) | |
7166 | { | |
7167 | if (!inst.error) | |
7168 | inst.error = BAD_ARGS; | |
7169 | return; | |
7170 | } | |
7171 | ||
7172 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
7173 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
7174 | inst.reloc.pc_rel = 1; | |
7175 | inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */ | |
7176 | ||
7177 | end_of_line (str); | |
7178 | } | |
7179 | ||
7180 | static void | |
7181 | insert_reg (entry) | |
7182 | int entry; | |
7183 | { | |
7184 | int len = strlen (reg_table[entry].name) + 2; | |
7185 | char * buf = (char *) xmalloc (len); | |
7186 | char * buf2 = (char *) xmalloc (len); | |
7187 | int i = 0; | |
7188 | ||
7189 | #ifdef REGISTER_PREFIX | |
7190 | buf[i++] = REGISTER_PREFIX; | |
7191 | #endif | |
7192 | ||
7193 | strcpy (buf + i, reg_table[entry].name); | |
7194 | ||
7195 | for (i = 0; buf[i]; i++) | |
3882b010 | 7196 | buf2[i] = TOUPPER (buf[i]); |
b99bd4ef NC |
7197 | |
7198 | buf2[i] = '\0'; | |
7199 | ||
7200 | hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]); | |
7201 | hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]); | |
7202 | } | |
7203 | ||
7204 | static void | |
7205 | insert_reg_alias (str, regnum) | |
7206 | char *str; | |
7207 | int regnum; | |
7208 | { | |
7209 | struct reg_entry *new = | |
7210 | (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); | |
7211 | char *name = xmalloc (strlen (str) + 1); | |
7212 | strcpy (name, str); | |
7213 | ||
7214 | new->name = name; | |
7215 | new->number = regnum; | |
7216 | ||
7217 | hash_insert (arm_reg_hsh, name, (PTR) new); | |
7218 | } | |
7219 | ||
7220 | static void | |
7221 | set_constant_flonums () | |
7222 | { | |
7223 | int i; | |
7224 | ||
7225 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
7226 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
7227 | abort (); | |
7228 | } | |
7229 | ||
7230 | void | |
7231 | md_begin () | |
7232 | { | |
7233 | unsigned mach; | |
7234 | unsigned int i; | |
7235 | ||
7236 | if ( (arm_ops_hsh = hash_new ()) == NULL | |
7237 | || (arm_tops_hsh = hash_new ()) == NULL | |
7238 | || (arm_cond_hsh = hash_new ()) == NULL | |
7239 | || (arm_shift_hsh = hash_new ()) == NULL | |
7240 | || (arm_reg_hsh = hash_new ()) == NULL | |
7241 | || (arm_psr_hsh = hash_new ()) == NULL) | |
7242 | as_fatal (_("Virtual memory exhausted")); | |
7243 | ||
7244 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
7245 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
7246 | for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++) | |
7247 | hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i)); | |
7248 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
7249 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
7250 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
7251 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
7252 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
7253 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
7254 | ||
7255 | for (i = 0; reg_table[i].name; i++) | |
7256 | insert_reg (i); | |
7257 | ||
7258 | set_constant_flonums (); | |
7259 | ||
7260 | #if defined OBJ_COFF || defined OBJ_ELF | |
7261 | { | |
7262 | unsigned int flags = 0; | |
7263 | ||
7264 | /* Set the flags in the private structure. */ | |
7265 | if (uses_apcs_26) flags |= F_APCS26; | |
7266 | if (support_interwork) flags |= F_INTERWORK; | |
7267 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
7268 | if (pic_code) flags |= F_PIC; | |
b89dddec | 7269 | if ((cpu_variant & FPU_ANY) == FPU_NONE) flags |= F_SOFT_FLOAT; |
b99bd4ef NC |
7270 | |
7271 | bfd_set_private_flags (stdoutput, flags); | |
7272 | ||
7273 | /* We have run out flags in the COFF header to encode the | |
7274 | status of ATPCS support, so instead we create a dummy, | |
7275 | empty, debug section called .arm.atpcs. */ | |
7276 | if (atpcs) | |
7277 | { | |
7278 | asection * sec; | |
7279 | ||
7280 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
7281 | ||
7282 | if (sec != NULL) | |
7283 | { | |
7284 | bfd_set_section_flags | |
7285 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
7286 | bfd_set_section_size (stdoutput, sec, 0); | |
7287 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
7288 | } | |
7289 | } | |
7290 | } | |
7291 | #endif | |
7292 | ||
7293 | /* Record the CPU type as well. */ | |
7294 | switch (cpu_variant & ARM_CPU_MASK) | |
7295 | { | |
7296 | case ARM_2: | |
7297 | mach = bfd_mach_arm_2; | |
7298 | break; | |
7299 | ||
7300 | case ARM_3: /* Also ARM_250. */ | |
7301 | mach = bfd_mach_arm_2a; | |
7302 | break; | |
7303 | ||
b89dddec RE |
7304 | case ARM_6: /* Also ARM_7. */ |
7305 | mach = bfd_mach_arm_3; | |
7306 | break; | |
7307 | ||
b99bd4ef | 7308 | default: |
b99bd4ef NC |
7309 | mach = bfd_mach_arm_4; |
7310 | break; | |
7311 | ||
b99bd4ef NC |
7312 | } |
7313 | ||
7314 | /* Catch special cases. */ | |
7315 | if (cpu_variant & ARM_EXT_XSCALE) | |
7316 | mach = bfd_mach_arm_XScale; | |
7317 | else if (cpu_variant & ARM_EXT_V5E) | |
7318 | mach = bfd_mach_arm_5TE; | |
7319 | else if (cpu_variant & ARM_EXT_V5) | |
7320 | { | |
b89dddec | 7321 | if (cpu_variant & ARM_EXT_V4T) |
b99bd4ef NC |
7322 | mach = bfd_mach_arm_5T; |
7323 | else | |
7324 | mach = bfd_mach_arm_5; | |
7325 | } | |
b89dddec | 7326 | else if (cpu_variant & ARM_EXT_V4) |
b99bd4ef | 7327 | { |
b89dddec | 7328 | if (cpu_variant & ARM_EXT_V4T) |
b99bd4ef NC |
7329 | mach = bfd_mach_arm_4T; |
7330 | else | |
7331 | mach = bfd_mach_arm_4; | |
7332 | } | |
b89dddec | 7333 | else if (cpu_variant & ARM_EXT_V3M) |
b99bd4ef NC |
7334 | mach = bfd_mach_arm_3M; |
7335 | ||
7336 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
7337 | } | |
7338 | ||
7339 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
7340 | for use in the a.out file, and stores them in the array pointed to by buf. | |
7341 | This knows about the endian-ness of the target machine and does | |
7342 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
7343 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
7344 | LITTLENUMS (shorts, here at least). */ | |
7345 | ||
7346 | void | |
7347 | md_number_to_chars (buf, val, n) | |
7348 | char * buf; | |
7349 | valueT val; | |
7350 | int n; | |
7351 | { | |
7352 | if (target_big_endian) | |
7353 | number_to_chars_bigendian (buf, val, n); | |
7354 | else | |
7355 | number_to_chars_littleendian (buf, val, n); | |
7356 | } | |
7357 | ||
7358 | static valueT | |
7359 | md_chars_to_number (buf, n) | |
7360 | char * buf; | |
7361 | int n; | |
7362 | { | |
7363 | valueT result = 0; | |
7364 | unsigned char * where = (unsigned char *) buf; | |
7365 | ||
7366 | if (target_big_endian) | |
7367 | { | |
7368 | while (n--) | |
7369 | { | |
7370 | result <<= 8; | |
7371 | result |= (*where++ & 255); | |
7372 | } | |
7373 | } | |
7374 | else | |
7375 | { | |
7376 | while (n--) | |
7377 | { | |
7378 | result <<= 8; | |
7379 | result |= (where[n] & 255); | |
7380 | } | |
7381 | } | |
7382 | ||
7383 | return result; | |
7384 | } | |
7385 | ||
7386 | /* Turn a string in input_line_pointer into a floating point constant | |
7387 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
7388 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
7389 | returned, or NULL on OK. | |
7390 | ||
7391 | Note that fp constants aren't represent in the normal way on the ARM. | |
7392 | In big endian mode, things are as expected. However, in little endian | |
7393 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
7394 | within the words. For example, (double) 1.1 in big endian mode is | |
7395 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
7396 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
7397 | ||
7398 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ | |
7399 | ||
7400 | char * | |
7401 | md_atof (type, litP, sizeP) | |
7402 | char type; | |
7403 | char * litP; | |
7404 | int * sizeP; | |
7405 | { | |
7406 | int prec; | |
7407 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
7408 | char *t; | |
7409 | int i; | |
7410 | ||
7411 | switch (type) | |
7412 | { | |
7413 | case 'f': | |
7414 | case 'F': | |
7415 | case 's': | |
7416 | case 'S': | |
7417 | prec = 2; | |
7418 | break; | |
7419 | ||
7420 | case 'd': | |
7421 | case 'D': | |
7422 | case 'r': | |
7423 | case 'R': | |
7424 | prec = 4; | |
7425 | break; | |
7426 | ||
7427 | case 'x': | |
7428 | case 'X': | |
7429 | prec = 6; | |
7430 | break; | |
7431 | ||
7432 | case 'p': | |
7433 | case 'P': | |
7434 | prec = 6; | |
7435 | break; | |
7436 | ||
7437 | default: | |
7438 | *sizeP = 0; | |
7439 | return _("Bad call to MD_ATOF()"); | |
7440 | } | |
7441 | ||
7442 | t = atof_ieee (input_line_pointer, type, words); | |
7443 | if (t) | |
7444 | input_line_pointer = t; | |
7445 | *sizeP = prec * 2; | |
7446 | ||
7447 | if (target_big_endian) | |
7448 | { | |
7449 | for (i = 0; i < prec; i++) | |
7450 | { | |
7451 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7452 | litP += 2; | |
7453 | } | |
7454 | } | |
7455 | else | |
7456 | { | |
7457 | /* For a 4 byte float the order of elements in `words' is 1 0. For an | |
7458 | 8 byte float the order is 1 0 3 2. */ | |
7459 | for (i = 0; i < prec; i += 2) | |
7460 | { | |
7461 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
7462 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
7463 | litP += 4; | |
7464 | } | |
7465 | } | |
7466 | ||
7467 | return 0; | |
7468 | } | |
7469 | ||
7470 | /* The knowledge of the PC's pipeline offset is built into the insns | |
7471 | themselves. */ | |
7472 | ||
7473 | long | |
7474 | md_pcrel_from (fixP) | |
7475 | fixS * fixP; | |
7476 | { | |
7477 | if (fixP->fx_addsy | |
7478 | && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section | |
7479 | && fixP->fx_subsy == NULL) | |
7480 | return 0; | |
7481 | ||
7482 | if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD)) | |
7483 | { | |
7484 | /* PC relative addressing on the Thumb is slightly odd | |
7485 | as the bottom two bits of the PC are forced to zero | |
7486 | for the calculation. */ | |
7487 | return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3; | |
7488 | } | |
7489 | ||
7490 | #ifdef TE_WINCE | |
7491 | /* The pattern was adjusted to accomodate CE's off-by-one fixups, | |
7492 | so we un-adjust here to compensate for the accomodation. */ | |
7493 | return fixP->fx_where + fixP->fx_frag->fr_address + 8; | |
7494 | #else | |
7495 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
7496 | #endif | |
7497 | } | |
7498 | ||
7499 | /* Round up a section size to the appropriate boundary. */ | |
7500 | ||
7501 | valueT | |
7502 | md_section_align (segment, size) | |
7503 | segT segment ATTRIBUTE_UNUSED; | |
7504 | valueT size; | |
7505 | { | |
7506 | #ifdef OBJ_ELF | |
7507 | return size; | |
7508 | #else | |
7509 | /* Round all sects to multiple of 4. */ | |
7510 | return (size + 3) & ~3; | |
7511 | #endif | |
7512 | } | |
7513 | ||
7514 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
7515 | Otherwise we have no need to default values of symbols. */ | |
7516 | ||
7517 | symbolS * | |
7518 | md_undefined_symbol (name) | |
7519 | char * name ATTRIBUTE_UNUSED; | |
7520 | { | |
7521 | #ifdef OBJ_ELF | |
7522 | if (name[0] == '_' && name[1] == 'G' | |
7523 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
7524 | { | |
7525 | if (!GOT_symbol) | |
7526 | { | |
7527 | if (symbol_find (name)) | |
7528 | as_bad ("GOT already in the symbol table"); | |
7529 | ||
7530 | GOT_symbol = symbol_new (name, undefined_section, | |
7531 | (valueT) 0, & zero_address_frag); | |
7532 | } | |
7533 | ||
7534 | return GOT_symbol; | |
7535 | } | |
7536 | #endif | |
7537 | ||
7538 | return 0; | |
7539 | } | |
7540 | ||
7541 | /* arm_reg_parse () := if it looks like a register, return its token and | |
7542 | advance the pointer. */ | |
7543 | ||
7544 | static int | |
7545 | arm_reg_parse (ccp) | |
7546 | register char ** ccp; | |
7547 | { | |
7548 | char * start = * ccp; | |
7549 | char c; | |
7550 | char * p; | |
7551 | struct reg_entry * reg; | |
7552 | ||
7553 | #ifdef REGISTER_PREFIX | |
7554 | if (*start != REGISTER_PREFIX) | |
7555 | return FAIL; | |
7556 | p = start + 1; | |
7557 | #else | |
7558 | p = start; | |
7559 | #ifdef OPTIONAL_REGISTER_PREFIX | |
7560 | if (*p == OPTIONAL_REGISTER_PREFIX) | |
7561 | p++, start++; | |
7562 | #endif | |
7563 | #endif | |
3882b010 | 7564 | if (!ISALPHA (*p) || !is_name_beginner (*p)) |
b99bd4ef NC |
7565 | return FAIL; |
7566 | ||
7567 | c = *p++; | |
3882b010 | 7568 | while (ISALPHA (c) || ISDIGIT (c) || c == '_') |
b99bd4ef NC |
7569 | c = *p++; |
7570 | ||
7571 | *--p = 0; | |
7572 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, start); | |
7573 | *p = c; | |
7574 | ||
7575 | if (reg) | |
7576 | { | |
7577 | *ccp = p; | |
7578 | return reg->number; | |
7579 | } | |
7580 | ||
7581 | return FAIL; | |
7582 | } | |
7583 | ||
7584 | int | |
7585 | md_apply_fix3 (fixP, val, seg) | |
7586 | fixS * fixP; | |
7587 | valueT * val; | |
7588 | segT seg; | |
7589 | { | |
7590 | offsetT value = * val; | |
7591 | offsetT newval; | |
7592 | unsigned int newimm; | |
7593 | unsigned long temp; | |
7594 | int sign; | |
7595 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
7596 | arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data; | |
7597 | ||
7598 | assert (fixP->fx_r_type < BFD_RELOC_UNUSED); | |
7599 | ||
7600 | /* Note whether this will delete the relocation. */ | |
7601 | #if 0 | |
7602 | /* Patch from REarnshaw to JDavis (disabled for the moment, since it | |
7603 | doesn't work fully.) */ | |
7604 | if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy)) | |
7605 | && !fixP->fx_pcrel) | |
7606 | #else | |
7607 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
7608 | #endif | |
7609 | fixP->fx_done = 1; | |
7610 | ||
7611 | /* If this symbol is in a different section then we need to leave it for | |
7612 | the linker to deal with. Unfortunately, md_pcrel_from can't tell, | |
7613 | so we have to undo it's effects here. */ | |
7614 | if (fixP->fx_pcrel) | |
7615 | { | |
7616 | if (fixP->fx_addsy != NULL | |
7617 | && S_IS_DEFINED (fixP->fx_addsy) | |
7618 | && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
7619 | { | |
7620 | if (target_oabi | |
7621 | && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH | |
7622 | || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX | |
7623 | )) | |
7624 | value = 0; | |
7625 | else | |
7626 | value += md_pcrel_from (fixP); | |
7627 | } | |
7628 | } | |
7629 | ||
7630 | /* Remember value for emit_reloc. */ | |
7631 | fixP->fx_addnumber = value; | |
7632 | ||
7633 | switch (fixP->fx_r_type) | |
7634 | { | |
7635 | case BFD_RELOC_ARM_IMMEDIATE: | |
7636 | newimm = validate_immediate (value); | |
7637 | temp = md_chars_to_number (buf, INSN_SIZE); | |
7638 | ||
7639 | /* If the instruction will fail, see if we can fix things up by | |
7640 | changing the opcode. */ | |
7641 | if (newimm == (unsigned int) FAIL | |
7642 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
7643 | { | |
7644 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7645 | _("invalid constant (%lx) after fixup"), | |
7646 | (unsigned long) value); | |
7647 | break; | |
7648 | } | |
7649 | ||
7650 | newimm |= (temp & 0xfffff000); | |
7651 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
7652 | break; | |
7653 | ||
7654 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: | |
7655 | { | |
7656 | unsigned int highpart = 0; | |
7657 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
7658 | newimm = validate_immediate (value); | |
7659 | temp = md_chars_to_number (buf, INSN_SIZE); | |
7660 | ||
7661 | /* If the instruction will fail, see if we can fix things up by | |
7662 | changing the opcode. */ | |
7663 | if (newimm == (unsigned int) FAIL | |
7664 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
7665 | { | |
7666 | /* No ? OK - try using two ADD instructions to generate | |
7667 | the value. */ | |
7668 | newimm = validate_immediate_twopart (value, & highpart); | |
7669 | ||
7670 | /* Yes - then make sure that the second instruction is | |
7671 | also an add. */ | |
7672 | if (newimm != (unsigned int) FAIL) | |
7673 | newinsn = temp; | |
7674 | /* Still No ? Try using a negated value. */ | |
7675 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
7676 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
7677 | /* Otherwise - give up. */ | |
7678 | else | |
7679 | { | |
7680 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7681 | _("Unable to compute ADRL instructions for PC offset of 0x%lx"), | |
7682 | value); | |
7683 | break; | |
7684 | } | |
7685 | ||
7686 | /* Replace the first operand in the 2nd instruction (which | |
7687 | is the PC) with the destination register. We have | |
7688 | already added in the PC in the first instruction and we | |
7689 | do not want to do it again. */ | |
7690 | newinsn &= ~ 0xf0000; | |
7691 | newinsn |= ((newinsn & 0x0f000) << 4); | |
7692 | } | |
7693 | ||
7694 | newimm |= (temp & 0xfffff000); | |
7695 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
7696 | ||
7697 | highpart |= (newinsn & 0xfffff000); | |
7698 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
7699 | } | |
7700 | break; | |
7701 | ||
7702 | case BFD_RELOC_ARM_OFFSET_IMM: | |
7703 | sign = value >= 0; | |
7704 | ||
7705 | if (value < 0) | |
7706 | value = - value; | |
7707 | ||
7708 | if (validate_offset_imm (value, 0) == FAIL) | |
7709 | { | |
7710 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7711 | _("bad immediate value for offset (%ld)"), | |
7712 | (long) value); | |
7713 | break; | |
7714 | } | |
7715 | ||
7716 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7717 | newval &= 0xff7ff000; | |
7718 | newval |= value | (sign ? INDEX_UP : 0); | |
7719 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7720 | break; | |
7721 | ||
7722 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
7723 | case BFD_RELOC_ARM_HWLITERAL: | |
7724 | sign = value >= 0; | |
7725 | ||
7726 | if (value < 0) | |
7727 | value = - value; | |
7728 | ||
7729 | if (validate_offset_imm (value, 1) == FAIL) | |
7730 | { | |
7731 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) | |
7732 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7733 | _("invalid literal constant: pool needs to be closer")); | |
7734 | else | |
7735 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
7736 | (long) value); | |
7737 | break; | |
7738 | } | |
7739 | ||
7740 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7741 | newval &= 0xff7ff0f0; | |
7742 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
7743 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7744 | break; | |
7745 | ||
7746 | case BFD_RELOC_ARM_LITERAL: | |
7747 | sign = value >= 0; | |
7748 | ||
7749 | if (value < 0) | |
7750 | value = - value; | |
7751 | ||
7752 | if (validate_offset_imm (value, 0) == FAIL) | |
7753 | { | |
7754 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7755 | _("invalid literal constant: pool needs to be closer")); | |
7756 | break; | |
7757 | } | |
7758 | ||
7759 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7760 | newval &= 0xff7ff000; | |
7761 | newval |= value | (sign ? INDEX_UP : 0); | |
7762 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7763 | break; | |
7764 | ||
7765 | case BFD_RELOC_ARM_SHIFT_IMM: | |
7766 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7767 | if (((unsigned long) value) > 32 | |
7768 | || (value == 32 | |
7769 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
7770 | { | |
7771 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7772 | _("shift expression is too large")); | |
7773 | break; | |
7774 | } | |
7775 | ||
7776 | if (value == 0) | |
7777 | /* Shifts of zero must be done as lsl. */ | |
7778 | newval &= ~0x60; | |
7779 | else if (value == 32) | |
7780 | value = 0; | |
7781 | newval &= 0xfffff07f; | |
7782 | newval |= (value & 0x1f) << 7; | |
7783 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7784 | break; | |
7785 | ||
7786 | case BFD_RELOC_ARM_SWI: | |
7787 | if (arm_data->thumb_mode) | |
7788 | { | |
7789 | if (((unsigned long) value) > 0xff) | |
7790 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7791 | _("Invalid swi expression")); | |
7792 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00; | |
7793 | newval |= value; | |
7794 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7795 | } | |
7796 | else | |
7797 | { | |
7798 | if (((unsigned long) value) > 0x00ffffff) | |
7799 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7800 | _("Invalid swi expression")); | |
7801 | newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000; | |
7802 | newval |= value; | |
7803 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7804 | } | |
7805 | break; | |
7806 | ||
7807 | case BFD_RELOC_ARM_MULTI: | |
7808 | if (((unsigned long) value) > 0xffff) | |
7809 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7810 | _("Invalid expression in load/store multiple")); | |
7811 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
7812 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7813 | break; | |
7814 | ||
7815 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
7816 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7817 | ||
7818 | /* Sign-extend a 24-bit number. */ | |
7819 | #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000) | |
7820 | ||
7821 | #ifdef OBJ_ELF | |
7822 | if (! target_oabi) | |
7823 | value = fixP->fx_offset; | |
7824 | #endif | |
7825 | ||
7826 | /* We are going to store value (shifted right by two) in the | |
7827 | instruction, in a 24 bit, signed field. Thus we need to check | |
7828 | that none of the top 8 bits of the shifted value (top 7 bits of | |
7829 | the unshifted, unsigned value) are set, or that they are all set. */ | |
7830 | if ((value & ~ ((offsetT) 0x1ffffff)) != 0 | |
7831 | && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff))) | |
7832 | { | |
7833 | #ifdef OBJ_ELF | |
7834 | /* Normally we would be stuck at this point, since we cannot store | |
7835 | the absolute address that is the destination of the branch in the | |
7836 | 24 bits of the branch instruction. If however, we happen to know | |
7837 | that the destination of the branch is in the same section as the | |
7838 | branch instruciton itself, then we can compute the relocation for | |
7839 | ourselves and not have to bother the linker with it. | |
7840 | ||
7841 | FIXME: The tests for OBJ_ELF and ! target_oabi are only here | |
7842 | because I have not worked out how to do this for OBJ_COFF or | |
7843 | target_oabi. */ | |
7844 | if (! target_oabi | |
7845 | && fixP->fx_addsy != NULL | |
7846 | && S_IS_DEFINED (fixP->fx_addsy) | |
7847 | && S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
7848 | { | |
7849 | /* Get pc relative value to go into the branch. */ | |
7850 | value = * val; | |
7851 | ||
7852 | /* Permit a backward branch provided that enough bits | |
7853 | are set. Allow a forwards branch, provided that | |
7854 | enough bits are clear. */ | |
7855 | if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff) | |
7856 | || (value & ~ ((offsetT) 0x1ffffff)) == 0) | |
7857 | fixP->fx_done = 1; | |
7858 | } | |
7859 | ||
7860 | if (! fixP->fx_done) | |
7861 | #endif | |
7862 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7863 | _("gas can't handle same-section branch dest >= 0x04000000")); | |
7864 | } | |
7865 | ||
7866 | value >>= 2; | |
7867 | value += SEXT24 (newval); | |
7868 | ||
7869 | if ( (value & ~ ((offsetT) 0xffffff)) != 0 | |
7870 | && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff))) | |
7871 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7872 | _("out of range branch")); | |
7873 | ||
7874 | newval = (value & 0x00ffffff) | (newval & 0xff000000); | |
7875 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7876 | break; | |
7877 | ||
7878 | case BFD_RELOC_ARM_PCREL_BLX: | |
7879 | { | |
7880 | offsetT hbit; | |
7881 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7882 | ||
7883 | #ifdef OBJ_ELF | |
7884 | if (! target_oabi) | |
7885 | value = fixP->fx_offset; | |
7886 | #endif | |
7887 | hbit = (value >> 1) & 1; | |
7888 | value = (value >> 2) & 0x00ffffff; | |
7889 | value = (value + (newval & 0x00ffffff)) & 0x00ffffff; | |
7890 | newval = value | (newval & 0xfe000000) | (hbit << 24); | |
7891 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7892 | } | |
7893 | break; | |
7894 | ||
7895 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ | |
7896 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7897 | { | |
7898 | addressT diff = (newval & 0xff) << 1; | |
7899 | if (diff & 0x100) | |
7900 | diff |= ~0xff; | |
7901 | ||
7902 | value += diff; | |
7903 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) | |
7904 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7905 | _("Branch out of range")); | |
7906 | newval = (newval & 0xff00) | ((value & 0x1ff) >> 1); | |
7907 | } | |
7908 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7909 | break; | |
7910 | ||
7911 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ | |
7912 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7913 | { | |
7914 | addressT diff = (newval & 0x7ff) << 1; | |
7915 | if (diff & 0x800) | |
7916 | diff |= ~0x7ff; | |
7917 | ||
7918 | value += diff; | |
7919 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) | |
7920 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7921 | _("Branch out of range")); | |
7922 | newval = (newval & 0xf800) | ((value & 0xfff) >> 1); | |
7923 | } | |
7924 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7925 | break; | |
7926 | ||
7927 | case BFD_RELOC_THUMB_PCREL_BLX: | |
7928 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
7929 | { | |
7930 | offsetT newval2; | |
7931 | addressT diff; | |
7932 | ||
7933 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7934 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
7935 | diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1); | |
7936 | if (diff & 0x400000) | |
7937 | diff |= ~0x3fffff; | |
7938 | #ifdef OBJ_ELF | |
7939 | value = fixP->fx_offset; | |
7940 | #endif | |
7941 | value += diff; | |
7942 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) | |
7943 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7944 | _("Branch with link out of range")); | |
7945 | ||
7946 | newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12); | |
7947 | newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1); | |
7948 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
7949 | /* Remove bit zero of the adjusted offset. Bit zero can only be | |
7950 | set if the upper insn is at a half-word boundary, since the | |
7951 | destination address, an ARM instruction, must always be on a | |
7952 | word boundary. The semantics of the BLX (1) instruction, however, | |
7953 | are that bit zero in the offset must always be zero, and the | |
7954 | corresponding bit one in the target address will be set from bit | |
7955 | one of the source address. */ | |
7956 | newval2 &= ~1; | |
7957 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7958 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
7959 | } | |
7960 | break; | |
7961 | ||
7962 | case BFD_RELOC_8: | |
7963 | if (fixP->fx_done || fixP->fx_pcrel) | |
7964 | md_number_to_chars (buf, value, 1); | |
7965 | #ifdef OBJ_ELF | |
7966 | else if (!target_oabi) | |
7967 | { | |
7968 | value = fixP->fx_offset; | |
7969 | md_number_to_chars (buf, value, 1); | |
7970 | } | |
7971 | #endif | |
7972 | break; | |
7973 | ||
7974 | case BFD_RELOC_16: | |
7975 | if (fixP->fx_done || fixP->fx_pcrel) | |
7976 | md_number_to_chars (buf, value, 2); | |
7977 | #ifdef OBJ_ELF | |
7978 | else if (!target_oabi) | |
7979 | { | |
7980 | value = fixP->fx_offset; | |
7981 | md_number_to_chars (buf, value, 2); | |
7982 | } | |
7983 | #endif | |
7984 | break; | |
7985 | ||
7986 | #ifdef OBJ_ELF | |
7987 | case BFD_RELOC_ARM_GOT32: | |
7988 | case BFD_RELOC_ARM_GOTOFF: | |
7989 | md_number_to_chars (buf, 0, 4); | |
7990 | break; | |
7991 | #endif | |
7992 | ||
7993 | case BFD_RELOC_RVA: | |
7994 | case BFD_RELOC_32: | |
7995 | if (fixP->fx_done || fixP->fx_pcrel) | |
7996 | md_number_to_chars (buf, value, 4); | |
7997 | #ifdef OBJ_ELF | |
7998 | else if (!target_oabi) | |
7999 | { | |
8000 | value = fixP->fx_offset; | |
8001 | md_number_to_chars (buf, value, 4); | |
8002 | } | |
8003 | #endif | |
8004 | break; | |
8005 | ||
8006 | #ifdef OBJ_ELF | |
8007 | case BFD_RELOC_ARM_PLT32: | |
8008 | /* It appears the instruction is fully prepared at this point. */ | |
8009 | break; | |
8010 | #endif | |
8011 | ||
8012 | case BFD_RELOC_ARM_GOTPC: | |
8013 | md_number_to_chars (buf, value, 4); | |
8014 | break; | |
8015 | ||
8016 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
8017 | sign = value >= 0; | |
8018 | if (value < -1023 || value > 1023 || (value & 3)) | |
8019 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8020 | _("Illegal value for co-processor offset")); | |
8021 | if (value < 0) | |
8022 | value = -value; | |
8023 | newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00; | |
8024 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
8025 | md_number_to_chars (buf, newval, INSN_SIZE); | |
8026 | break; | |
8027 | ||
8028 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
8029 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
8030 | /* Exactly what ranges, and where the offset is inserted depends | |
8031 | on the type of instruction, we can establish this from the | |
8032 | top 4 bits. */ | |
8033 | switch (newval >> 12) | |
8034 | { | |
8035 | case 4: /* PC load. */ | |
8036 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
8037 | forced to zero for these loads, so we will need to round | |
8038 | up the offset if the instruction address is not word | |
8039 | aligned (since the final address produced must be, and | |
8040 | we can only describe word-aligned immediate offsets). */ | |
8041 | ||
8042 | if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3) | |
8043 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8044 | _("Invalid offset, target not word aligned (0x%08X)"), | |
8045 | (unsigned int) (fixP->fx_frag->fr_address | |
8046 | + fixP->fx_where + value)); | |
8047 | ||
8048 | if ((value + 2) & ~0x3fe) | |
8049 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8050 | _("Invalid offset, value too big (0x%08lX)"), value); | |
8051 | ||
8052 | /* Round up, since pc will be rounded down. */ | |
8053 | newval |= (value + 2) >> 2; | |
8054 | break; | |
8055 | ||
8056 | case 9: /* SP load/store. */ | |
8057 | if (value & ~0x3fc) | |
8058 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8059 | _("Invalid offset, value too big (0x%08lX)"), value); | |
8060 | newval |= value >> 2; | |
8061 | break; | |
8062 | ||
8063 | case 6: /* Word load/store. */ | |
8064 | if (value & ~0x7c) | |
8065 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8066 | _("Invalid offset, value too big (0x%08lX)"), value); | |
8067 | newval |= value << 4; /* 6 - 2. */ | |
8068 | break; | |
8069 | ||
8070 | case 7: /* Byte load/store. */ | |
8071 | if (value & ~0x1f) | |
8072 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8073 | _("Invalid offset, value too big (0x%08lX)"), value); | |
8074 | newval |= value << 6; | |
8075 | break; | |
8076 | ||
8077 | case 8: /* Halfword load/store. */ | |
8078 | if (value & ~0x3e) | |
8079 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8080 | _("Invalid offset, value too big (0x%08lX)"), value); | |
8081 | newval |= value << 5; /* 6 - 1. */ | |
8082 | break; | |
8083 | ||
8084 | default: | |
8085 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8086 | "Unable to process relocation for thumb opcode: %lx", | |
8087 | (unsigned long) newval); | |
8088 | break; | |
8089 | } | |
8090 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
8091 | break; | |
8092 | ||
8093 | case BFD_RELOC_ARM_THUMB_ADD: | |
8094 | /* This is a complicated relocation, since we use it for all of | |
8095 | the following immediate relocations: | |
8096 | ||
8097 | 3bit ADD/SUB | |
8098 | 8bit ADD/SUB | |
8099 | 9bit ADD/SUB SP word-aligned | |
8100 | 10bit ADD PC/SP word-aligned | |
8101 | ||
8102 | The type of instruction being processed is encoded in the | |
8103 | instruction field: | |
8104 | ||
8105 | 0x8000 SUB | |
8106 | 0x00F0 Rd | |
8107 | 0x000F Rs | |
8108 | */ | |
8109 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
8110 | { | |
8111 | int rd = (newval >> 4) & 0xf; | |
8112 | int rs = newval & 0xf; | |
8113 | int subtract = newval & 0x8000; | |
8114 | ||
8115 | if (rd == REG_SP) | |
8116 | { | |
8117 | if (value & ~0x1fc) | |
8118 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8119 | _("Invalid immediate for stack address calculation")); | |
8120 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
8121 | newval |= value >> 2; | |
8122 | } | |
8123 | else if (rs == REG_PC || rs == REG_SP) | |
8124 | { | |
8125 | if (subtract || | |
8126 | value & ~0x3fc) | |
8127 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8128 | _("Invalid immediate for address calculation (value = 0x%08lX)"), | |
8129 | (unsigned long) value); | |
8130 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
8131 | newval |= rd << 8; | |
8132 | newval |= value >> 2; | |
8133 | } | |
8134 | else if (rs == rd) | |
8135 | { | |
8136 | if (value & ~0xff) | |
8137 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8138 | _("Invalid 8bit immediate")); | |
8139 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
8140 | newval |= (rd << 8) | value; | |
8141 | } | |
8142 | else | |
8143 | { | |
8144 | if (value & ~0x7) | |
8145 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8146 | _("Invalid 3bit immediate")); | |
8147 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
8148 | newval |= rd | (rs << 3) | (value << 6); | |
8149 | } | |
8150 | } | |
8151 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
8152 | break; | |
8153 | ||
8154 | case BFD_RELOC_ARM_THUMB_IMM: | |
8155 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
8156 | switch (newval >> 11) | |
8157 | { | |
8158 | case 0x04: /* 8bit immediate MOV. */ | |
8159 | case 0x05: /* 8bit immediate CMP. */ | |
8160 | if (value < 0 || value > 255) | |
8161 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8162 | _("Invalid immediate: %ld is too large"), | |
8163 | (long) value); | |
8164 | newval |= value; | |
8165 | break; | |
8166 | ||
8167 | default: | |
8168 | abort (); | |
8169 | } | |
8170 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
8171 | break; | |
8172 | ||
8173 | case BFD_RELOC_ARM_THUMB_SHIFT: | |
8174 | /* 5bit shift value (0..31). */ | |
8175 | if (value < 0 || value > 31) | |
8176 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8177 | _("Illegal Thumb shift value: %ld"), (long) value); | |
8178 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f; | |
8179 | newval |= value << 6; | |
8180 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
8181 | break; | |
8182 | ||
8183 | case BFD_RELOC_VTABLE_INHERIT: | |
8184 | case BFD_RELOC_VTABLE_ENTRY: | |
8185 | fixP->fx_done = 0; | |
8186 | return 1; | |
8187 | ||
8188 | case BFD_RELOC_NONE: | |
8189 | default: | |
8190 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8191 | _("Bad relocation fixup type (%d)"), fixP->fx_r_type); | |
8192 | } | |
8193 | ||
8194 | return 1; | |
8195 | } | |
8196 | ||
8197 | /* Translate internal representation of relocation info to BFD target | |
8198 | format. */ | |
8199 | ||
8200 | arelent * | |
8201 | tc_gen_reloc (section, fixp) | |
8202 | asection * section ATTRIBUTE_UNUSED; | |
8203 | fixS * fixp; | |
8204 | { | |
8205 | arelent * reloc; | |
8206 | bfd_reloc_code_real_type code; | |
8207 | ||
8208 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
8209 | ||
8210 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
8211 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
8212 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
8213 | ||
8214 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
8215 | #ifndef OBJ_ELF | |
8216 | if (fixp->fx_pcrel == 0) | |
8217 | reloc->addend = fixp->fx_offset; | |
8218 | else | |
8219 | reloc->addend = fixp->fx_offset = reloc->address; | |
8220 | #else /* OBJ_ELF */ | |
8221 | reloc->addend = fixp->fx_offset; | |
8222 | #endif | |
8223 | ||
8224 | switch (fixp->fx_r_type) | |
8225 | { | |
8226 | case BFD_RELOC_8: | |
8227 | if (fixp->fx_pcrel) | |
8228 | { | |
8229 | code = BFD_RELOC_8_PCREL; | |
8230 | break; | |
8231 | } | |
8232 | ||
8233 | case BFD_RELOC_16: | |
8234 | if (fixp->fx_pcrel) | |
8235 | { | |
8236 | code = BFD_RELOC_16_PCREL; | |
8237 | break; | |
8238 | } | |
8239 | ||
8240 | case BFD_RELOC_32: | |
8241 | if (fixp->fx_pcrel) | |
8242 | { | |
8243 | code = BFD_RELOC_32_PCREL; | |
8244 | break; | |
8245 | } | |
8246 | ||
8247 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
8248 | case BFD_RELOC_ARM_PCREL_BLX: | |
8249 | case BFD_RELOC_RVA: | |
8250 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
8251 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
8252 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
8253 | case BFD_RELOC_THUMB_PCREL_BLX: | |
8254 | case BFD_RELOC_VTABLE_ENTRY: | |
8255 | case BFD_RELOC_VTABLE_INHERIT: | |
8256 | code = fixp->fx_r_type; | |
8257 | break; | |
8258 | ||
8259 | case BFD_RELOC_ARM_LITERAL: | |
8260 | case BFD_RELOC_ARM_HWLITERAL: | |
8261 | /* If this is called then the a literal has been referenced across | |
8262 | a section boundary - possibly due to an implicit dump. */ | |
8263 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8264 | _("Literal referenced across section boundary (Implicit dump?)")); | |
8265 | return NULL; | |
8266 | ||
8267 | #ifdef OBJ_ELF | |
8268 | case BFD_RELOC_ARM_GOT32: | |
8269 | case BFD_RELOC_ARM_GOTOFF: | |
8270 | case BFD_RELOC_ARM_PLT32: | |
8271 | code = fixp->fx_r_type; | |
8272 | break; | |
8273 | #endif | |
8274 | ||
8275 | case BFD_RELOC_ARM_IMMEDIATE: | |
8276 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8277 | _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"), | |
8278 | fixp->fx_r_type); | |
8279 | return NULL; | |
8280 | ||
8281 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: | |
8282 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8283 | _("ADRL used for a symbol not defined in the same file")); | |
8284 | return NULL; | |
8285 | ||
8286 | case BFD_RELOC_ARM_OFFSET_IMM: | |
8287 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8288 | _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"), | |
8289 | fixp->fx_r_type); | |
8290 | return NULL; | |
8291 | ||
8292 | default: | |
8293 | { | |
8294 | char * type; | |
8295 | ||
8296 | switch (fixp->fx_r_type) | |
8297 | { | |
8298 | case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break; | |
8299 | case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break; | |
8300 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
8301 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
8302 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; | |
8303 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
8304 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8305 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; | |
8306 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
8307 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
8308 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
8309 | default: type = _("<unknown>"); break; | |
8310 | } | |
8311 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8312 | _("Cannot represent %s relocation in this object file format"), | |
8313 | type); | |
8314 | return NULL; | |
8315 | } | |
8316 | } | |
8317 | ||
8318 | #ifdef OBJ_ELF | |
8319 | if (code == BFD_RELOC_32_PCREL | |
8320 | && GOT_symbol | |
8321 | && fixp->fx_addsy == GOT_symbol) | |
8322 | { | |
8323 | code = BFD_RELOC_ARM_GOTPC; | |
8324 | reloc->addend = fixp->fx_offset = reloc->address; | |
8325 | } | |
8326 | #endif | |
8327 | ||
8328 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
8329 | ||
8330 | if (reloc->howto == NULL) | |
8331 | { | |
8332 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8333 | _("Can not represent %s relocation in this object file format"), | |
8334 | bfd_get_reloc_code_name (code)); | |
8335 | return NULL; | |
8336 | } | |
8337 | ||
8338 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the | |
8339 | vtable entry to be used in the relocation's section offset. */ | |
8340 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8341 | reloc->address = fixp->fx_offset; | |
8342 | ||
8343 | return reloc; | |
8344 | } | |
8345 | ||
8346 | int | |
8347 | md_estimate_size_before_relax (fragP, segtype) | |
8348 | fragS * fragP ATTRIBUTE_UNUSED; | |
8349 | segT segtype ATTRIBUTE_UNUSED; | |
8350 | { | |
8351 | as_fatal (_("md_estimate_size_before_relax\n")); | |
8352 | return 1; | |
8353 | } | |
8354 | ||
8355 | static void | |
8356 | output_inst PARAMS ((void)) | |
8357 | { | |
8358 | char * to = NULL; | |
8359 | ||
8360 | if (inst.error) | |
8361 | { | |
8362 | as_bad (inst.error); | |
8363 | return; | |
8364 | } | |
8365 | ||
8366 | to = frag_more (inst.size); | |
8367 | ||
8368 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
8369 | { | |
8370 | assert (inst.size == (2 * THUMB_SIZE)); | |
8371 | md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE); | |
8372 | md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE); | |
8373 | } | |
8374 | else if (inst.size > INSN_SIZE) | |
8375 | { | |
8376 | assert (inst.size == (2 * INSN_SIZE)); | |
8377 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
8378 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
8379 | } | |
8380 | else | |
8381 | md_number_to_chars (to, inst.instruction, inst.size); | |
8382 | ||
8383 | if (inst.reloc.type != BFD_RELOC_NONE) | |
8384 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
8385 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
8386 | inst.reloc.type); | |
8387 | ||
8388 | #ifdef OBJ_ELF | |
8389 | dwarf2_emit_insn (inst.size); | |
8390 | #endif | |
8391 | } | |
8392 | ||
8393 | void | |
8394 | md_assemble (str) | |
8395 | char * str; | |
8396 | { | |
8397 | char c; | |
8398 | char * p; | |
8399 | char * q; | |
8400 | char * start; | |
8401 | ||
8402 | /* Align the instruction. | |
8403 | This may not be the right thing to do but ... */ | |
8404 | #if 0 | |
8405 | arm_align (2, 0); | |
8406 | #endif | |
8407 | listing_prev_line (); /* Defined in listing.h. */ | |
8408 | ||
8409 | /* Align the previous label if needed. */ | |
8410 | if (last_label_seen != NULL) | |
8411 | { | |
8412 | symbol_set_frag (last_label_seen, frag_now); | |
8413 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
8414 | S_SET_SEGMENT (last_label_seen, now_seg); | |
8415 | } | |
8416 | ||
8417 | memset (&inst, '\0', sizeof (inst)); | |
8418 | inst.reloc.type = BFD_RELOC_NONE; | |
8419 | ||
8420 | skip_whitespace (str); | |
8421 | ||
8422 | /* Scan up to the end of the op-code, which must end in white space or | |
8423 | end of string. */ | |
8424 | for (start = p = str; *p != '\0'; p++) | |
8425 | if (*p == ' ') | |
8426 | break; | |
8427 | ||
8428 | if (p == str) | |
8429 | { | |
8430 | as_bad (_("No operator -- statement `%s'\n"), str); | |
8431 | return; | |
8432 | } | |
8433 | ||
8434 | if (thumb_mode) | |
8435 | { | |
05d2d07e | 8436 | const struct thumb_opcode * opcode; |
b99bd4ef NC |
8437 | |
8438 | c = *p; | |
8439 | *p = '\0'; | |
05d2d07e | 8440 | opcode = (const struct thumb_opcode *) hash_find (arm_tops_hsh, str); |
b99bd4ef NC |
8441 | *p = c; |
8442 | ||
8443 | if (opcode) | |
8444 | { | |
8445 | /* Check that this instruction is supported for this CPU. */ | |
8446 | if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0) | |
8447 | { | |
8448 | as_bad (_("selected processor does not support this opcode")); | |
8449 | return; | |
8450 | } | |
8451 | ||
8452 | inst.instruction = opcode->value; | |
8453 | inst.size = opcode->size; | |
8454 | (*opcode->parms) (p); | |
8455 | output_inst (); | |
8456 | return; | |
8457 | } | |
8458 | } | |
8459 | else | |
8460 | { | |
05d2d07e | 8461 | const struct asm_opcode * opcode; |
b99bd4ef NC |
8462 | unsigned long cond_code; |
8463 | ||
8464 | inst.size = INSN_SIZE; | |
8465 | /* P now points to the end of the opcode, probably white space, but we | |
8466 | have to break the opcode up in case it contains condionals and flags; | |
8467 | keep trying with progressively smaller basic instructions until one | |
8468 | matches, or we run out of opcode. */ | |
8469 | q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p; | |
8470 | ||
8471 | for (; q != str; q--) | |
8472 | { | |
8473 | c = *q; | |
8474 | *q = '\0'; | |
8475 | ||
05d2d07e | 8476 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, str); |
b99bd4ef NC |
8477 | *q = c; |
8478 | ||
8479 | if (opcode && opcode->template) | |
8480 | { | |
8481 | unsigned long flag_bits = 0; | |
8482 | char * r; | |
8483 | ||
8484 | /* Check that this instruction is supported for this CPU. */ | |
8485 | if ((opcode->variants & cpu_variant) == 0) | |
8486 | goto try_shorter; | |
8487 | ||
8488 | inst.instruction = opcode->value; | |
8489 | if (q == p) /* Just a simple opcode. */ | |
8490 | { | |
8491 | if (opcode->comp_suffix) | |
8492 | { | |
8493 | if (*opcode->comp_suffix != '\0') | |
8494 | as_bad (_("Opcode `%s' must have suffix from list: <%s>"), | |
8495 | str, opcode->comp_suffix); | |
8496 | else | |
8497 | /* Not a conditional instruction. */ | |
8498 | (*opcode->parms) (q, 0); | |
8499 | } | |
8500 | else | |
8501 | { | |
8502 | /* A conditional instruction with default condition. */ | |
8503 | inst.instruction |= COND_ALWAYS; | |
8504 | (*opcode->parms) (q, 0); | |
8505 | } | |
8506 | output_inst (); | |
8507 | return; | |
8508 | } | |
8509 | ||
8510 | /* Not just a simple opcode. Check if extra is a | |
8511 | conditional. */ | |
8512 | r = q; | |
8513 | if (p - r >= 2) | |
8514 | { | |
05d2d07e | 8515 | const struct asm_cond *cond; |
b99bd4ef NC |
8516 | char d = *(r + 2); |
8517 | ||
8518 | *(r + 2) = '\0'; | |
05d2d07e | 8519 | cond = (const struct asm_cond *) hash_find (arm_cond_hsh, r); |
b99bd4ef NC |
8520 | *(r + 2) = d; |
8521 | if (cond) | |
8522 | { | |
8523 | if (cond->value == 0xf0000000) | |
8524 | as_tsktsk ( | |
8525 | _("Warning: Use of the 'nv' conditional is deprecated\n")); | |
8526 | ||
8527 | cond_code = cond->value; | |
8528 | r += 2; | |
8529 | } | |
8530 | else | |
8531 | cond_code = COND_ALWAYS; | |
8532 | } | |
8533 | else | |
8534 | cond_code = COND_ALWAYS; | |
8535 | ||
8536 | /* Apply the conditional, or complain it's not allowed. */ | |
8537 | if (opcode->comp_suffix && *opcode->comp_suffix == '\0') | |
8538 | { | |
8539 | /* Instruction isn't conditional. */ | |
8540 | if (cond_code != COND_ALWAYS) | |
8541 | { | |
8542 | as_bad (_("Opcode `%s' is unconditional\n"), str); | |
8543 | return; | |
8544 | } | |
8545 | } | |
8546 | else | |
8547 | /* Instruction is conditional: set the condition into it. */ | |
8548 | inst.instruction |= cond_code; | |
8549 | ||
8550 | /* If there is a compulsory suffix, it should come here | |
8551 | before any optional flags. */ | |
8552 | if (opcode->comp_suffix && *opcode->comp_suffix != '\0') | |
8553 | { | |
05d2d07e | 8554 | const char *s = opcode->comp_suffix; |
b99bd4ef NC |
8555 | |
8556 | while (*s) | |
8557 | { | |
8558 | inst.suffix++; | |
8559 | if (*r == *s) | |
8560 | break; | |
8561 | s++; | |
8562 | } | |
8563 | ||
8564 | if (*s == '\0') | |
8565 | { | |
8566 | as_bad (_("Opcode `%s' must have suffix from <%s>\n"), | |
8567 | str, opcode->comp_suffix); | |
8568 | return; | |
8569 | } | |
8570 | ||
8571 | r++; | |
8572 | } | |
8573 | ||
8574 | /* The remainder, if any should now be flags for the instruction; | |
8575 | Scan these checking each one found with the opcode. */ | |
8576 | if (r != p) | |
8577 | { | |
8578 | char d; | |
05d2d07e | 8579 | const struct asm_flg *flag = opcode->flags; |
b99bd4ef NC |
8580 | |
8581 | if (flag) | |
8582 | { | |
8583 | int flagno; | |
8584 | ||
8585 | d = *p; | |
8586 | *p = '\0'; | |
8587 | ||
8588 | for (flagno = 0; flag[flagno].template; flagno++) | |
8589 | { | |
8590 | if (streq (r, flag[flagno].template)) | |
8591 | { | |
8592 | flag_bits |= flag[flagno].set_bits; | |
8593 | break; | |
8594 | } | |
8595 | } | |
8596 | ||
8597 | *p = d; | |
8598 | if (! flag[flagno].template) | |
8599 | goto try_shorter; | |
8600 | } | |
8601 | else | |
8602 | goto try_shorter; | |
8603 | } | |
8604 | ||
8605 | (*opcode->parms) (p, flag_bits); | |
8606 | output_inst (); | |
8607 | return; | |
8608 | } | |
8609 | ||
8610 | try_shorter: | |
8611 | ; | |
8612 | } | |
8613 | } | |
8614 | ||
8615 | /* It wasn't an instruction, but it might be a register alias of the form | |
8616 | alias .req reg. */ | |
8617 | q = p; | |
8618 | skip_whitespace (q); | |
8619 | ||
8620 | c = *p; | |
8621 | *p = '\0'; | |
8622 | ||
8623 | if (*q && !strncmp (q, ".req ", 4)) | |
8624 | { | |
8625 | int reg; | |
8626 | char * copy_of_str; | |
8627 | char * r; | |
8628 | ||
8629 | #ifdef IGNORE_OPCODE_CASE | |
8630 | str = original_case_string; | |
8631 | #endif | |
8632 | copy_of_str = str; | |
8633 | ||
8634 | q += 4; | |
8635 | skip_whitespace (q); | |
8636 | ||
8637 | for (r = q; *r != '\0'; r++) | |
8638 | if (*r == ' ') | |
8639 | break; | |
8640 | ||
8641 | if (r != q) | |
8642 | { | |
8643 | int regnum; | |
8644 | char d = *r; | |
8645 | ||
8646 | *r = '\0'; | |
8647 | regnum = arm_reg_parse (& q); | |
8648 | *r = d; | |
8649 | ||
8650 | reg = arm_reg_parse (& str); | |
8651 | ||
8652 | if (reg == FAIL) | |
8653 | { | |
8654 | if (regnum != FAIL) | |
8655 | insert_reg_alias (str, regnum); | |
8656 | else | |
8657 | as_warn (_("register '%s' does not exist\n"), q); | |
8658 | } | |
8659 | else if (regnum != FAIL) | |
8660 | { | |
8661 | if (reg != regnum) | |
8662 | as_warn (_("ignoring redefinition of register alias '%s'"), | |
8663 | copy_of_str); | |
8664 | ||
8665 | /* Do not warn about redefinitions to the same alias. */ | |
8666 | } | |
8667 | else | |
8668 | as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"), | |
8669 | copy_of_str, q); | |
8670 | } | |
8671 | else | |
8672 | as_warn (_("ignoring incomplete .req pseuso op")); | |
8673 | ||
8674 | *p = c; | |
8675 | return; | |
8676 | } | |
8677 | ||
8678 | *p = c; | |
8679 | as_bad (_("bad instruction `%s'"), start); | |
8680 | } | |
8681 | ||
8682 | /* md_parse_option | |
8683 | Invocation line includes a switch not recognized by the base assembler. | |
8684 | See if it's a processor-specific option. These are: | |
8685 | Cpu variants, the arm part is optional: | |
8686 | -m[arm]1 Currently not supported. | |
8687 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
8688 | -m[arm]3 Arm 3 processor | |
8689 | -m[arm]6[xx], Arm 6 processors | |
8690 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
8691 | -m[arm]8[10] Arm 8 processors | |
8692 | -m[arm]9[20][tdmi] Arm 9 processors | |
404ff6b5 | 8693 | -marm9e Allow Cirrus/DSP instructions |
b99bd4ef NC |
8694 | -mstrongarm[110[0]] StrongARM processors |
8695 | -mxscale XScale processors | |
8696 | -m[arm]v[2345[t[e]]] Arm architectures | |
8697 | -mall All (except the ARM1) | |
8698 | FP variants: | |
8699 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
8700 | -mfpe-old (No float load/store multiples) | |
8701 | -mno-fpu Disable all floating point instructions | |
8702 | Run-time endian selection: | |
8703 | -EB big endian cpu | |
8704 | -EL little endian cpu | |
8705 | ARM Procedure Calling Standard: | |
8706 | -mapcs-32 32 bit APCS | |
8707 | -mapcs-26 26 bit APCS | |
8708 | -mapcs-float Pass floats in float regs | |
8709 | -mapcs-reentrant Position independent code | |
8710 | -mthumb-interwork Code supports Arm/Thumb interworking | |
8711 | -matpcs ARM/Thumb Procedure Call Standard | |
8712 | -moabi Old ELF ABI */ | |
8713 | ||
05d2d07e | 8714 | const char * md_shortopts = "m:k"; |
b99bd4ef NC |
8715 | |
8716 | struct option md_longopts[] = | |
8717 | { | |
8718 | #ifdef ARM_BI_ENDIAN | |
8719 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
8720 | {"EB", no_argument, NULL, OPTION_EB}, | |
8721 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
8722 | {"EL", no_argument, NULL, OPTION_EL}, | |
8723 | #ifdef OBJ_ELF | |
8724 | #define OPTION_OABI (OPTION_MD_BASE +2) | |
8725 | {"oabi", no_argument, NULL, OPTION_OABI}, | |
8726 | #endif | |
8727 | #endif | |
8728 | {NULL, no_argument, NULL, 0} | |
8729 | }; | |
8730 | ||
8731 | size_t md_longopts_size = sizeof (md_longopts); | |
8732 | ||
8733 | int | |
8734 | md_parse_option (c, arg) | |
8735 | int c; | |
8736 | char * arg; | |
8737 | { | |
8738 | char * str = arg; | |
8739 | ||
8740 | switch (c) | |
8741 | { | |
8742 | #ifdef ARM_BI_ENDIAN | |
8743 | case OPTION_EB: | |
8744 | target_big_endian = 1; | |
8745 | break; | |
8746 | case OPTION_EL: | |
8747 | target_big_endian = 0; | |
8748 | break; | |
8749 | #endif | |
8750 | ||
8751 | case 'm': | |
8752 | switch (*str) | |
8753 | { | |
8754 | case 'f': | |
b89dddec RE |
8755 | if (streq (str, "fpa10") || streq (str, "fpa11")) |
8756 | cpu_variant = (cpu_variant & ~FPU_ANY) | FPU_ARCH_FPA; | |
b99bd4ef | 8757 | else if (streq (str, "fpe-old")) |
b89dddec | 8758 | cpu_variant = (cpu_variant & ~FPU_ANY) | FPU_ARCH_FPE; |
b99bd4ef NC |
8759 | else |
8760 | goto bad; | |
8761 | break; | |
8762 | ||
8763 | case 'n': | |
8764 | if (streq (str, "no-fpu")) | |
b89dddec | 8765 | cpu_variant &= ~FPU_ANY; |
b99bd4ef NC |
8766 | break; |
8767 | ||
8768 | #ifdef OBJ_ELF | |
8769 | case 'o': | |
8770 | if (streq (str, "oabi")) | |
8771 | target_oabi = true; | |
8772 | break; | |
8773 | #endif | |
8774 | ||
8775 | case 't': | |
8776 | /* Limit assembler to generating only Thumb instructions: */ | |
8777 | if (streq (str, "thumb")) | |
8778 | { | |
b89dddec RE |
8779 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_V4T; |
8780 | cpu_variant = (cpu_variant & ~FPU_ANY) | FPU_NONE; | |
b99bd4ef NC |
8781 | thumb_mode = 1; |
8782 | } | |
8783 | else if (streq (str, "thumb-interwork")) | |
8784 | { | |
b89dddec | 8785 | if ((cpu_variant & ARM_EXT_V4T) == 0) |
b99bd4ef NC |
8786 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T; |
8787 | #if defined OBJ_COFF || defined OBJ_ELF | |
8788 | support_interwork = true; | |
8789 | #endif | |
8790 | } | |
8791 | else | |
8792 | goto bad; | |
8793 | break; | |
8794 | ||
8795 | default: | |
8796 | if (streq (str, "all")) | |
8797 | { | |
b89dddec | 8798 | cpu_variant = ARM_ALL | FPU_DEFAULT; |
b99bd4ef NC |
8799 | return 1; |
8800 | } | |
8801 | #if defined OBJ_COFF || defined OBJ_ELF | |
8802 | if (! strncmp (str, "apcs-", 5)) | |
8803 | { | |
8804 | /* GCC passes on all command line options starting "-mapcs-..." | |
8805 | to us, so we must parse them here. */ | |
8806 | ||
8807 | str += 5; | |
8808 | ||
8809 | if (streq (str, "32")) | |
8810 | { | |
8811 | uses_apcs_26 = false; | |
8812 | return 1; | |
8813 | } | |
8814 | else if (streq (str, "26")) | |
8815 | { | |
8816 | uses_apcs_26 = true; | |
8817 | return 1; | |
8818 | } | |
8819 | else if (streq (str, "frame")) | |
8820 | { | |
8821 | /* Stack frames are being generated - does not affect | |
8822 | linkage of code. */ | |
8823 | return 1; | |
8824 | } | |
8825 | else if (streq (str, "stack-check")) | |
8826 | { | |
8827 | /* Stack checking is being performed - does not affect | |
8828 | linkage, but does require that the functions | |
8829 | __rt_stkovf_split_small and __rt_stkovf_split_big be | |
8830 | present in the final link. */ | |
8831 | ||
8832 | return 1; | |
8833 | } | |
8834 | else if (streq (str, "float")) | |
8835 | { | |
8836 | /* Floating point arguments are being passed in the floating | |
8837 | point registers. This does affect linking, since this | |
8838 | version of the APCS is incompatible with the version that | |
8839 | passes floating points in the integer registers. */ | |
8840 | ||
8841 | uses_apcs_float = true; | |
8842 | return 1; | |
8843 | } | |
8844 | else if (streq (str, "reentrant")) | |
8845 | { | |
8846 | /* Reentrant code has been generated. This does affect | |
8847 | linking, since there is no point in linking reentrant/ | |
8848 | position independent code with absolute position code. */ | |
8849 | pic_code = true; | |
8850 | return 1; | |
8851 | } | |
8852 | ||
8853 | as_bad (_("Unrecognised APCS switch -m%s"), arg); | |
8854 | return 0; | |
8855 | } | |
8856 | ||
8857 | if (! strcmp (str, "atpcs")) | |
8858 | { | |
8859 | atpcs = true; | |
8860 | return 1; | |
8861 | } | |
8862 | #endif | |
8863 | /* Strip off optional "arm". */ | |
8864 | if (! strncmp (str, "arm", 3)) | |
8865 | str += 3; | |
8866 | ||
8867 | switch (*str) | |
8868 | { | |
8869 | case '1': | |
8870 | if (streq (str, "1")) | |
8871 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1; | |
8872 | else | |
8873 | goto bad; | |
8874 | break; | |
8875 | ||
8876 | case '2': | |
8877 | if (streq (str, "2")) | |
8878 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; | |
8879 | else if (streq (str, "250")) | |
8880 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250; | |
8881 | else | |
8882 | goto bad; | |
8883 | break; | |
8884 | ||
8885 | case '3': | |
8886 | if (streq (str, "3")) | |
8887 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; | |
8888 | else | |
8889 | goto bad; | |
8890 | break; | |
8891 | ||
8892 | case '6': | |
8893 | switch (strtol (str, NULL, 10)) | |
8894 | { | |
8895 | case 6: | |
8896 | case 60: | |
8897 | case 600: | |
8898 | case 610: | |
8899 | case 620: | |
8900 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6; | |
8901 | break; | |
8902 | default: | |
8903 | goto bad; | |
8904 | } | |
8905 | break; | |
8906 | ||
8907 | case '7': | |
8908 | /* Eat the processor name. */ | |
8909 | switch (strtol (str, & str, 10)) | |
8910 | { | |
8911 | case 7: | |
8912 | case 70: | |
8913 | case 700: | |
8914 | case 710: | |
8915 | case 720: | |
8916 | case 7100: | |
8917 | case 7500: | |
8918 | break; | |
8919 | default: | |
8920 | goto bad; | |
8921 | } | |
8922 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7; | |
8923 | for (; *str; str++) | |
8924 | { | |
8925 | switch (*str) | |
8926 | { | |
8927 | case 't': | |
8928 | cpu_variant |= ARM_ARCH_V4T; | |
8929 | break; | |
8930 | ||
8931 | case 'm': | |
b89dddec | 8932 | cpu_variant |= ARM_EXT_V3M; |
b99bd4ef NC |
8933 | break; |
8934 | ||
8935 | case 'f': /* fe => fp enabled cpu. */ | |
8936 | if (str[1] == 'e') | |
8937 | ++ str; | |
8938 | else | |
8939 | goto bad; | |
8940 | ||
8941 | case 'c': /* Left over from 710c processor name. */ | |
8942 | case 'd': /* Debug. */ | |
8943 | case 'i': /* Embedded ICE. */ | |
8944 | /* Included for completeness in ARM processor naming. */ | |
8945 | break; | |
8946 | ||
8947 | default: | |
8948 | goto bad; | |
8949 | } | |
8950 | } | |
8951 | break; | |
8952 | ||
8953 | case '8': | |
8954 | if (streq (str, "8") || streq (str, "810")) | |
8955 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8956 | | ARM_8 | ARM_ARCH_V4; | |
8957 | else | |
8958 | goto bad; | |
8959 | break; | |
8960 | ||
8961 | case '9': | |
8962 | if (streq (str, "9")) | |
8963 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8964 | | ARM_9 | ARM_ARCH_V4T; | |
8965 | else if (streq (str, "920")) | |
8966 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8967 | | ARM_9 | ARM_ARCH_V4; | |
8968 | else if (streq (str, "920t")) | |
8969 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8970 | | ARM_9 | ARM_ARCH_V4T; | |
8971 | else if (streq (str, "9tdmi")) | |
8972 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8973 | | ARM_9 | ARM_ARCH_V4T; | |
404ff6b5 AH |
8974 | else if (streq (str, "9e")) |
8975 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
90f9b791 | 8976 | | ARM_9 | ARM_ARCH_V4T | ARM_EXT_MAVERICK; |
b99bd4ef NC |
8977 | else |
8978 | goto bad; | |
8979 | break; | |
8980 | ||
8981 | case 's': | |
8982 | if (streq (str, "strongarm") | |
8983 | || streq (str, "strongarm110") | |
8984 | || streq (str, "strongarm1100")) | |
8985 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8986 | | ARM_8 | ARM_ARCH_V4; | |
8987 | else | |
8988 | goto bad; | |
8989 | break; | |
8990 | ||
8991 | case 'x': | |
8992 | if (streq (str, "xscale")) | |
8993 | cpu_variant = ARM_9 | ARM_ARCH_XSCALE; | |
8994 | else | |
8995 | goto bad; | |
8996 | break; | |
8997 | ||
8998 | case 'v': | |
8999 | /* Select variant based on architecture rather than | |
9000 | processor. */ | |
9001 | switch (*++str) | |
9002 | { | |
9003 | case '2': | |
9004 | switch (*++str) | |
9005 | { | |
9006 | case 'a': | |
9007 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; | |
9008 | break; | |
9009 | case 0: | |
9010 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; | |
9011 | break; | |
9012 | default: | |
9013 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
9014 | break; | |
9015 | } | |
9016 | break; | |
9017 | ||
9018 | case '3': | |
9019 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7; | |
9020 | ||
9021 | switch (*++str) | |
9022 | { | |
b89dddec | 9023 | case 'm': cpu_variant |= ARM_EXT_V3M; break; |
b99bd4ef NC |
9024 | case 0: break; |
9025 | default: | |
9026 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
9027 | break; | |
9028 | } | |
9029 | break; | |
9030 | ||
9031 | case '4': | |
9032 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4; | |
9033 | ||
9034 | switch (*++str) | |
9035 | { | |
b89dddec | 9036 | case 't': cpu_variant |= ARM_EXT_V4T; break; |
b99bd4ef NC |
9037 | case 0: break; |
9038 | default: | |
9039 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
9040 | break; | |
9041 | } | |
9042 | break; | |
9043 | ||
9044 | case '5': | |
9045 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5; | |
9046 | switch (*++str) | |
9047 | { | |
b89dddec | 9048 | case 't': cpu_variant |= ARM_EXT_V4T; break; |
b99bd4ef NC |
9049 | case 'e': cpu_variant |= ARM_EXT_V5E; break; |
9050 | case 0: break; | |
9051 | default: | |
9052 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
9053 | break; | |
9054 | } | |
9055 | break; | |
9056 | ||
9057 | default: | |
9058 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
9059 | break; | |
9060 | } | |
9061 | break; | |
9062 | ||
9063 | default: | |
9064 | bad: | |
9065 | as_bad (_("Invalid processor variant -m%s"), arg); | |
9066 | return 0; | |
9067 | } | |
9068 | } | |
9069 | break; | |
9070 | ||
9071 | #if defined OBJ_ELF || defined OBJ_COFF | |
9072 | case 'k': | |
9073 | pic_code = 1; | |
9074 | break; | |
9075 | #endif | |
9076 | ||
9077 | default: | |
9078 | return 0; | |
9079 | } | |
9080 | ||
9081 | return 1; | |
9082 | } | |
9083 | ||
9084 | void | |
9085 | md_show_usage (fp) | |
9086 | FILE * fp; | |
9087 | { | |
9088 | fprintf (fp, _("\ | |
9089 | ARM Specific Assembler Options:\n\ | |
9090 | -m[arm][<processor name>] select processor variant\n\ | |
9091 | -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\ | |
404ff6b5 | 9092 | -marm9e allow Cirrus/DSP instructions\n\ |
b99bd4ef NC |
9093 | -mthumb only allow Thumb instructions\n\ |
9094 | -mthumb-interwork mark the assembled code as supporting interworking\n\ | |
9095 | -mall allow any instruction\n\ | |
9096 | -mfpa10, -mfpa11 select floating point architecture\n\ | |
9097 | -mfpe-old don't allow floating-point multiple instructions\n\ | |
9098 | -mno-fpu don't allow any floating-point instructions.\n\ | |
9099 | -k generate PIC code.\n")); | |
9100 | #if defined OBJ_COFF || defined OBJ_ELF | |
9101 | fprintf (fp, _("\ | |
9102 | -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\ | |
9103 | -matpcs use ARM/Thumb Procedure Calling Standard\n\ | |
9104 | -mapcs-float floating point args are passed in FP regs\n\ | |
9105 | -mapcs-reentrant the code is position independent/reentrant\n")); | |
9106 | #endif | |
9107 | #ifdef OBJ_ELF | |
9108 | fprintf (fp, _("\ | |
9109 | -moabi support the old ELF ABI\n")); | |
9110 | #endif | |
9111 | #ifdef ARM_BI_ENDIAN | |
9112 | fprintf (fp, _("\ | |
9113 | -EB assemble code for a big endian cpu\n\ | |
9114 | -EL assemble code for a little endian cpu\n")); | |
9115 | #endif | |
9116 | } | |
9117 | ||
9118 | /* We need to be able to fix up arbitrary expressions in some statements. | |
9119 | This is so that we can handle symbols that are an arbitrary distance from | |
9120 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
9121 | which returns part of an address in a form which will be valid for | |
9122 | a data instruction. We do this by pushing the expression into a symbol | |
9123 | in the expr_section, and creating a fix for that. */ | |
9124 | ||
9125 | static void | |
9126 | fix_new_arm (frag, where, size, exp, pc_rel, reloc) | |
9127 | fragS * frag; | |
9128 | int where; | |
9129 | short int size; | |
9130 | expressionS * exp; | |
9131 | int pc_rel; | |
9132 | int reloc; | |
9133 | { | |
9134 | fixS * new_fix; | |
9135 | arm_fix_data * arm_data; | |
9136 | ||
9137 | switch (exp->X_op) | |
9138 | { | |
9139 | case O_constant: | |
9140 | case O_symbol: | |
9141 | case O_add: | |
9142 | case O_subtract: | |
9143 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
9144 | break; | |
9145 | ||
9146 | default: | |
9147 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
9148 | pc_rel, reloc); | |
9149 | break; | |
9150 | } | |
9151 | ||
9152 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
9153 | instruction. */ | |
9154 | arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data)); | |
9155 | new_fix->tc_fix_data = (PTR) arm_data; | |
9156 | arm_data->thumb_mode = thumb_mode; | |
9157 | ||
9158 | return; | |
9159 | } | |
9160 | ||
9161 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ | |
9162 | ||
9163 | void | |
9164 | cons_fix_new_arm (frag, where, size, exp) | |
9165 | fragS * frag; | |
9166 | int where; | |
9167 | int size; | |
9168 | expressionS * exp; | |
9169 | { | |
9170 | bfd_reloc_code_real_type type; | |
9171 | int pcrel = 0; | |
9172 | ||
9173 | /* Pick a reloc. | |
9174 | FIXME: @@ Should look at CPU word size. */ | |
9175 | switch (size) | |
9176 | { | |
9177 | case 1: | |
9178 | type = BFD_RELOC_8; | |
9179 | break; | |
9180 | case 2: | |
9181 | type = BFD_RELOC_16; | |
9182 | break; | |
9183 | case 4: | |
9184 | default: | |
9185 | type = BFD_RELOC_32; | |
9186 | break; | |
9187 | case 8: | |
9188 | type = BFD_RELOC_64; | |
9189 | break; | |
9190 | } | |
9191 | ||
9192 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); | |
9193 | } | |
9194 | ||
9195 | /* A good place to do this, although this was probably not intended | |
9196 | for this kind of use. We need to dump the literal pool before | |
9197 | references are made to a null symbol pointer. */ | |
9198 | ||
9199 | void | |
9200 | arm_cleanup () | |
9201 | { | |
9202 | if (current_poolP == NULL) | |
9203 | return; | |
9204 | ||
9205 | /* Put it at the end of text section. */ | |
9206 | subseg_set (text_section, 0); | |
9207 | s_ltorg (0); | |
9208 | listing_prev_line (); | |
9209 | } | |
9210 | ||
9211 | void | |
9212 | arm_start_line_hook () | |
9213 | { | |
9214 | last_label_seen = NULL; | |
9215 | } | |
9216 | ||
9217 | void | |
9218 | arm_frob_label (sym) | |
9219 | symbolS * sym; | |
9220 | { | |
9221 | last_label_seen = sym; | |
9222 | ||
9223 | ARM_SET_THUMB (sym, thumb_mode); | |
9224 | ||
9225 | #if defined OBJ_COFF || defined OBJ_ELF | |
9226 | ARM_SET_INTERWORK (sym, support_interwork); | |
9227 | #endif | |
9228 | ||
9229 | /* Note - do not allow local symbols (.Lxxx) to be labeled | |
9230 | as Thumb functions. This is because these labels, whilst | |
9231 | they exist inside Thumb code, are not the entry points for | |
9232 | possible ARM->Thumb calls. Also, these labels can be used | |
9233 | as part of a computed goto or switch statement. eg gcc | |
9234 | can generate code that looks like this: | |
9235 | ||
9236 | ldr r2, [pc, .Laaa] | |
9237 | lsl r3, r3, #2 | |
9238 | ldr r2, [r3, r2] | |
9239 | mov pc, r2 | |
9240 | ||
9241 | .Lbbb: .word .Lxxx | |
9242 | .Lccc: .word .Lyyy | |
9243 | ..etc... | |
9244 | .Laaa: .word Lbbb | |
9245 | ||
9246 | The first instruction loads the address of the jump table. | |
9247 | The second instruction converts a table index into a byte offset. | |
9248 | The third instruction gets the jump address out of the table. | |
9249 | The fourth instruction performs the jump. | |
9250 | ||
9251 | If the address stored at .Laaa is that of a symbol which has the | |
9252 | Thumb_Func bit set, then the linker will arrange for this address | |
9253 | to have the bottom bit set, which in turn would mean that the | |
9254 | address computation performed by the third instruction would end | |
9255 | up with the bottom bit set. Since the ARM is capable of unaligned | |
9256 | word loads, the instruction would then load the incorrect address | |
9257 | out of the jump table, and chaos would ensue. */ | |
9258 | if (label_is_thumb_function_name | |
9259 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
9260 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
9261 | { | |
9262 | /* When the address of a Thumb function is taken the bottom | |
9263 | bit of that address should be set. This will allow | |
9264 | interworking between Arm and Thumb functions to work | |
9265 | correctly. */ | |
9266 | ||
9267 | THUMB_SET_FUNC (sym, 1); | |
9268 | ||
9269 | label_is_thumb_function_name = false; | |
9270 | } | |
9271 | } | |
9272 | ||
9273 | /* Adjust the symbol table. This marks Thumb symbols as distinct from | |
9274 | ARM ones. */ | |
9275 | ||
9276 | void | |
9277 | arm_adjust_symtab () | |
9278 | { | |
9279 | #ifdef OBJ_COFF | |
9280 | symbolS * sym; | |
9281 | ||
9282 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
9283 | { | |
9284 | if (ARM_IS_THUMB (sym)) | |
9285 | { | |
9286 | if (THUMB_IS_FUNC (sym)) | |
9287 | { | |
9288 | /* Mark the symbol as a Thumb function. */ | |
9289 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
9290 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
9291 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
9292 | ||
9293 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) | |
9294 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
9295 | else | |
9296 | as_bad (_("%s: unexpected function type: %d"), | |
9297 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
9298 | } | |
9299 | else switch (S_GET_STORAGE_CLASS (sym)) | |
9300 | { | |
9301 | case C_EXT: | |
9302 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
9303 | break; | |
9304 | case C_STAT: | |
9305 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
9306 | break; | |
9307 | case C_LABEL: | |
9308 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
9309 | break; | |
9310 | default: | |
9311 | /* Do nothing. */ | |
9312 | break; | |
9313 | } | |
9314 | } | |
9315 | ||
9316 | if (ARM_IS_INTERWORK (sym)) | |
9317 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
9318 | } | |
9319 | #endif | |
9320 | #ifdef OBJ_ELF | |
9321 | symbolS * sym; | |
9322 | char bind; | |
9323 | ||
9324 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
9325 | { | |
9326 | if (ARM_IS_THUMB (sym)) | |
9327 | { | |
9328 | elf_symbol_type * elf_sym; | |
9329 | ||
9330 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); | |
9331 | bind = ELF_ST_BIND (elf_sym); | |
9332 | ||
9333 | /* If it's a .thumb_func, declare it as so, | |
9334 | otherwise tag label as .code 16. */ | |
9335 | if (THUMB_IS_FUNC (sym)) | |
9336 | elf_sym->internal_elf_sym.st_info = | |
9337 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
9338 | else | |
9339 | elf_sym->internal_elf_sym.st_info = | |
9340 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
9341 | } | |
9342 | } | |
9343 | #endif | |
9344 | } | |
9345 | ||
9346 | int | |
9347 | arm_data_in_code () | |
9348 | { | |
9349 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) | |
9350 | { | |
9351 | *input_line_pointer = '/'; | |
9352 | input_line_pointer += 5; | |
9353 | *input_line_pointer = 0; | |
9354 | return 1; | |
9355 | } | |
9356 | ||
9357 | return 0; | |
9358 | } | |
9359 | ||
9360 | char * | |
9361 | arm_canonicalize_symbol_name (name) | |
9362 | char * name; | |
9363 | { | |
9364 | int len; | |
9365 | ||
9366 | if (thumb_mode && (len = strlen (name)) > 5 | |
9367 | && streq (name + len - 5, "/data")) | |
9368 | *(name + len - 5) = 0; | |
9369 | ||
9370 | return name; | |
9371 | } | |
9372 | ||
9373 | boolean | |
9374 | arm_validate_fix (fixP) | |
9375 | fixS * fixP; | |
9376 | { | |
9377 | /* If the destination of the branch is a defined symbol which does not have | |
9378 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9379 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9380 | function and change the branch to refer to that function instead. */ | |
9381 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
9382 | && fixP->fx_addsy != NULL | |
9383 | && S_IS_DEFINED (fixP->fx_addsy) | |
9384 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
9385 | { | |
9386 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); | |
9387 | return true; | |
9388 | } | |
9389 | ||
9390 | return false; | |
9391 | } | |
9392 | ||
9393 | #ifdef OBJ_COFF | |
9394 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents | |
9395 | local labels from being added to the output symbol table when they | |
9396 | are used with the ADRL pseudo op. The ADRL relocation should always | |
9397 | be resolved before the binbary is emitted, so it is safe to say that | |
9398 | it is adjustable. */ | |
9399 | ||
9400 | boolean | |
9401 | arm_fix_adjustable (fixP) | |
9402 | fixS * fixP; | |
9403 | { | |
9404 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) | |
9405 | return 1; | |
9406 | return 0; | |
9407 | } | |
9408 | #endif | |
9409 | #ifdef OBJ_ELF | |
9410 | /* Relocations against Thumb function names must be left unadjusted, | |
9411 | so that the linker can use this information to correctly set the | |
9412 | bottom bit of their addresses. The MIPS version of this function | |
9413 | also prevents relocations that are mips-16 specific, but I do not | |
9414 | know why it does this. | |
9415 | ||
9416 | FIXME: | |
9417 | There is one other problem that ought to be addressed here, but | |
9418 | which currently is not: Taking the address of a label (rather | |
9419 | than a function) and then later jumping to that address. Such | |
9420 | addresses also ought to have their bottom bit set (assuming that | |
9421 | they reside in Thumb code), but at the moment they will not. */ | |
9422 | ||
9423 | boolean | |
9424 | arm_fix_adjustable (fixP) | |
9425 | fixS * fixP; | |
9426 | { | |
9427 | if (fixP->fx_addsy == NULL) | |
9428 | return 1; | |
9429 | ||
9430 | /* Prevent all adjustments to global symbols. */ | |
9431 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
9432 | return 0; | |
9433 | ||
9434 | if (S_IS_WEAK (fixP->fx_addsy)) | |
9435 | return 0; | |
9436 | ||
9437 | if (THUMB_IS_FUNC (fixP->fx_addsy) | |
9438 | && fixP->fx_subsy == NULL) | |
9439 | return 0; | |
9440 | ||
9441 | /* We need the symbol name for the VTABLE entries. */ | |
9442 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9443 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9444 | return 0; | |
9445 | ||
9446 | return 1; | |
9447 | } | |
9448 | ||
9449 | const char * | |
9450 | elf32_arm_target_format () | |
9451 | { | |
9452 | if (target_big_endian) | |
9453 | { | |
9454 | if (target_oabi) | |
9455 | return "elf32-bigarm-oabi"; | |
9456 | else | |
9457 | return "elf32-bigarm"; | |
9458 | } | |
9459 | else | |
9460 | { | |
9461 | if (target_oabi) | |
9462 | return "elf32-littlearm-oabi"; | |
9463 | else | |
9464 | return "elf32-littlearm"; | |
9465 | } | |
9466 | } | |
9467 | ||
9468 | void | |
9469 | armelf_frob_symbol (symp, puntp) | |
9470 | symbolS * symp; | |
9471 | int * puntp; | |
9472 | { | |
9473 | elf_frob_symbol (symp, puntp); | |
9474 | } | |
9475 | ||
9476 | int | |
9477 | arm_force_relocation (fixp) | |
9478 | struct fix * fixp; | |
9479 | { | |
9480 | if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9481 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
9482 | || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH | |
9483 | || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX | |
9484 | || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX | |
9485 | || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23) | |
9486 | return 1; | |
9487 | ||
9488 | return 0; | |
9489 | } | |
9490 | ||
9491 | static bfd_reloc_code_real_type | |
9492 | arm_parse_reloc () | |
9493 | { | |
9494 | char id [16]; | |
9495 | char * ip; | |
9496 | unsigned int i; | |
9497 | static struct | |
9498 | { | |
9499 | char * str; | |
9500 | int len; | |
9501 | bfd_reloc_code_real_type reloc; | |
9502 | } | |
9503 | reloc_map[] = | |
9504 | { | |
9505 | #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } | |
9506 | MAP ("(got)", BFD_RELOC_ARM_GOT32), | |
9507 | MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF), | |
9508 | /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)" | |
9509 | branch instructions generated by GCC for PLT relocs. */ | |
9510 | MAP ("(plt)", BFD_RELOC_ARM_PLT32), | |
9511 | { NULL, 0, BFD_RELOC_UNUSED } | |
9512 | #undef MAP | |
9513 | }; | |
9514 | ||
9515 | for (i = 0, ip = input_line_pointer; | |
3882b010 | 9516 | i < sizeof (id) && (ISALNUM (*ip) || ISPUNCT (*ip)); |
b99bd4ef | 9517 | i++, ip++) |
3882b010 | 9518 | id[i] = TOLOWER (*ip); |
b99bd4ef NC |
9519 | |
9520 | for (i = 0; reloc_map[i].str; i++) | |
9521 | if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0) | |
9522 | break; | |
9523 | ||
9524 | input_line_pointer += reloc_map[i].len; | |
9525 | ||
9526 | return reloc_map[i].reloc; | |
9527 | } | |
9528 | ||
9529 | static void | |
9530 | s_arm_elf_cons (nbytes) | |
9531 | int nbytes; | |
9532 | { | |
9533 | expressionS exp; | |
9534 | ||
9535 | #ifdef md_flush_pending_output | |
9536 | md_flush_pending_output (); | |
9537 | #endif | |
9538 | ||
9539 | if (is_it_end_of_statement ()) | |
9540 | { | |
9541 | demand_empty_rest_of_line (); | |
9542 | return; | |
9543 | } | |
9544 | ||
9545 | #ifdef md_cons_align | |
9546 | md_cons_align (nbytes); | |
9547 | #endif | |
9548 | ||
9549 | do | |
9550 | { | |
9551 | bfd_reloc_code_real_type reloc; | |
9552 | ||
9553 | expression (& exp); | |
9554 | ||
9555 | if (exp.X_op == O_symbol | |
9556 | && * input_line_pointer == '(' | |
9557 | && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED) | |
9558 | { | |
9559 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
9560 | int size = bfd_get_reloc_size (howto); | |
9561 | ||
9562 | if (size > nbytes) | |
9563 | as_bad ("%s relocations do not fit in %d bytes", | |
9564 | howto->name, nbytes); | |
9565 | else | |
9566 | { | |
9567 | register char *p = frag_more ((int) nbytes); | |
9568 | int offset = nbytes - size; | |
9569 | ||
9570 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, | |
9571 | &exp, 0, reloc); | |
9572 | } | |
9573 | } | |
9574 | else | |
9575 | emit_expr (&exp, (unsigned int) nbytes); | |
9576 | } | |
9577 | while (*input_line_pointer++ == ','); | |
9578 | ||
9579 | /* Put terminator back into stream. */ | |
9580 | input_line_pointer --; | |
9581 | demand_empty_rest_of_line (); | |
9582 | } | |
9583 | ||
9584 | #endif /* OBJ_ELF */ | |
9585 | ||
9586 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents | |
9587 | of an rs_align_code fragment. */ | |
9588 | ||
9589 | void | |
9590 | arm_handle_align (fragP) | |
9591 | fragS *fragP; | |
9592 | { | |
9593 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; | |
9594 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
9595 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
9596 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
9597 | ||
9598 | int bytes, fix, noop_size; | |
9599 | char * p; | |
9600 | const char * noop; | |
9601 | ||
9602 | if (fragP->fr_type != rs_align_code) | |
9603 | return; | |
9604 | ||
9605 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
9606 | p = fragP->fr_literal + fragP->fr_fix; | |
9607 | fix = 0; | |
9608 | ||
9609 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) | |
9610 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
9611 | ||
9612 | if (fragP->tc_frag_data) | |
9613 | { | |
9614 | if (target_big_endian) | |
9615 | noop = thumb_bigend_noop; | |
9616 | else | |
9617 | noop = thumb_noop; | |
9618 | noop_size = sizeof (thumb_noop); | |
9619 | } | |
9620 | else | |
9621 | { | |
9622 | if (target_big_endian) | |
9623 | noop = arm_bigend_noop; | |
9624 | else | |
9625 | noop = arm_noop; | |
9626 | noop_size = sizeof (arm_noop); | |
9627 | } | |
9628 | ||
9629 | if (bytes & (noop_size - 1)) | |
9630 | { | |
9631 | fix = bytes & (noop_size - 1); | |
9632 | memset (p, 0, fix); | |
9633 | p += fix; | |
9634 | bytes -= fix; | |
9635 | } | |
9636 | ||
9637 | while (bytes >= noop_size) | |
9638 | { | |
9639 | memcpy (p, noop, noop_size); | |
9640 | p += noop_size; | |
9641 | bytes -= noop_size; | |
9642 | fix += noop_size; | |
9643 | } | |
9644 | ||
9645 | fragP->fr_fix += fix; | |
9646 | fragP->fr_var = noop_size; | |
9647 | } | |
9648 | ||
9649 | /* Called from md_do_align. Used to create an alignment | |
9650 | frag in a code section. */ | |
9651 | ||
9652 | void | |
9653 | arm_frag_align_code (n, max) | |
9654 | int n; | |
9655 | int max; | |
9656 | { | |
9657 | char * p; | |
9658 | ||
9659 | /* We assume that there will never be a requirment | |
9660 | to support alignments greater than 32 bytes. */ | |
9661 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
9662 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
9663 | ||
9664 | p = frag_var (rs_align_code, | |
9665 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
9666 | 1, | |
9667 | (relax_substateT) max, | |
9668 | (symbolS *) NULL, | |
9669 | (offsetT) n, | |
9670 | (char *) NULL); | |
9671 | *p = 0; | |
9672 | ||
9673 | } | |
9674 | ||
9675 | /* Perform target specific initialisation of a frag. */ | |
9676 | ||
9677 | void | |
9678 | arm_init_frag (fragP) | |
9679 | fragS *fragP; | |
9680 | { | |
9681 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
9682 | fragP->tc_frag_data = thumb_mode; | |
9683 | } |