PR 9722
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
f17c130b 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
35997600 3 2004, 2005, 2006, 2007, 2008
b99bd4ef
NC
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC
10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
ec2655a6 15 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
b99bd4ef 27
5287ad62 28#include <limits.h>
037e8744 29#include <stdarg.h>
c19d1205 30#define NO_RELOC 0
b99bd4ef 31#include "as.h"
3882b010 32#include "safe-ctype.h"
b99bd4ef
NC
33#include "subsegs.h"
34#include "obstack.h"
b99bd4ef 35
f263249b
RE
36#include "opcode/arm.h"
37
b99bd4ef
NC
38#ifdef OBJ_ELF
39#include "elf/arm.h"
a394c00f 40#include "dw2gencfi.h"
b99bd4ef
NC
41#endif
42
f0927246
NC
43#include "dwarf2dbg.h"
44
720abc60 45#define WARN_DEPRECATED 1
03b1477f 46
7ed4c4c5
NC
47#ifdef OBJ_ELF
48/* Must be at least the size of the largest unwind opcode (currently two). */
49#define ARM_OPCODE_CHUNK_SIZE 8
50
51/* This structure holds the unwinding state. */
52
53static struct
54{
c19d1205
ZW
55 symbolS * proc_start;
56 symbolS * table_entry;
57 symbolS * personality_routine;
58 int personality_index;
7ed4c4c5 59 /* The segment containing the function. */
c19d1205
ZW
60 segT saved_seg;
61 subsegT saved_subseg;
7ed4c4c5
NC
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes;
c19d1205
ZW
64 int opcode_count;
65 int opcode_alloc;
7ed4c4c5 66 /* The number of bytes pushed to the stack. */
c19d1205 67 offsetT frame_size;
7ed4c4c5
NC
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
c19d1205 71 offsetT pending_offset;
7ed4c4c5 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW
73 hold the reg+offset to use when restoring sp from a frame pointer. */
74 offsetT fp_offset;
75 int fp_reg;
7ed4c4c5 76 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 77 unsigned fp_used:1;
7ed4c4c5 78 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 79 unsigned sp_restored:1;
7ed4c4c5
NC
80} unwind;
81
8b1ad454
NC
82/* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85static unsigned int marked_pr_dependency = 0;
86
87#endif /* OBJ_ELF */
88
4962c51a
MS
89/* Results from operand parsing worker functions. */
90
91typedef enum
92{
93 PARSE_OPERAND_SUCCESS,
94 PARSE_OPERAND_FAIL,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96} parse_operand_result;
97
33a392fb
PB
98enum arm_float_abi
99{
100 ARM_FLOAT_ABI_HARD,
101 ARM_FLOAT_ABI_SOFTFP,
102 ARM_FLOAT_ABI_SOFT
103};
104
c19d1205 105/* Types of processor to assemble for. */
b99bd4ef
NC
106#ifndef CPU_DEFAULT
107#if defined __XSCALE__
e74cfd16 108#define CPU_DEFAULT ARM_ARCH_XSCALE
b99bd4ef
NC
109#else
110#if defined __thumb__
e74cfd16 111#define CPU_DEFAULT ARM_ARCH_V5T
b99bd4ef
NC
112#endif
113#endif
114#endif
115
116#ifndef FPU_DEFAULT
c820d418
MM
117# ifdef TE_LINUX
118# define FPU_DEFAULT FPU_ARCH_FPA
119# elif defined (TE_NetBSD)
120# ifdef OBJ_ELF
121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
122# else
123 /* Legacy a.out format. */
124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
125# endif
4e7fd91e
PB
126# elif defined (TE_VXWORKS)
127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM
128# else
129 /* For backwards compatibility, default to FPA. */
130# define FPU_DEFAULT FPU_ARCH_FPA
131# endif
132#endif /* ifndef FPU_DEFAULT */
b99bd4ef 133
c19d1205 134#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 135
e74cfd16
PB
136static arm_feature_set cpu_variant;
137static arm_feature_set arm_arch_used;
138static arm_feature_set thumb_arch_used;
b99bd4ef 139
b99bd4ef 140/* Flags stored in private area of BFD structure. */
c19d1205
ZW
141static int uses_apcs_26 = FALSE;
142static int atpcs = FALSE;
b34976b6
AM
143static int support_interwork = FALSE;
144static int uses_apcs_float = FALSE;
c19d1205 145static int pic_code = FALSE;
845b51d6 146static int fix_v4bx = FALSE;
03b1477f
RE
147
148/* Variables that we set while parsing command-line options. Once all
149 options have been read we re-process these values to set the real
150 assembly flags. */
e74cfd16
PB
151static const arm_feature_set *legacy_cpu = NULL;
152static const arm_feature_set *legacy_fpu = NULL;
153
154static const arm_feature_set *mcpu_cpu_opt = NULL;
155static const arm_feature_set *mcpu_fpu_opt = NULL;
156static const arm_feature_set *march_cpu_opt = NULL;
157static const arm_feature_set *march_fpu_opt = NULL;
158static const arm_feature_set *mfpu_opt = NULL;
7a1d4c38 159static const arm_feature_set *object_arch = NULL;
e74cfd16
PB
160
161/* Constants for known architecture features. */
162static const arm_feature_set fpu_default = FPU_DEFAULT;
163static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
164static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
5287ad62
JB
165static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
166static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
e74cfd16
PB
167static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
168static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
169static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
170static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
171
172#ifdef CPU_DEFAULT
173static const arm_feature_set cpu_default = CPU_DEFAULT;
174#endif
175
176static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
177static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
178static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
179static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
180static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
181static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
182static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
183static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
184static const arm_feature_set arm_ext_v4t_5 =
185 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
186static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
187static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
188static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
189static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
190static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
191static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
192static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
193static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
62b3e311 194static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
7e806470
PB
195static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
196static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
62b3e311
PB
197static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
198static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
199static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
200static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
7e806470
PB
201static const arm_feature_set arm_ext_m =
202 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0);
e74cfd16
PB
203
204static const arm_feature_set arm_arch_any = ARM_ANY;
205static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
206static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
207static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
208
2d447fca
JM
209static const arm_feature_set arm_cext_iwmmxt2 =
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
e74cfd16
PB
211static const arm_feature_set arm_cext_iwmmxt =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
213static const arm_feature_set arm_cext_xscale =
214 ARM_FEATURE (0, ARM_CEXT_XSCALE);
215static const arm_feature_set arm_cext_maverick =
216 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
217static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
218static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
219static const arm_feature_set fpu_vfp_ext_v1xd =
220 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
221static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
222static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
5287ad62 223static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
b1cc4aeb
PB
224static const arm_feature_set fpu_vfp_ext_d32 =
225 ARM_FEATURE (0, FPU_VFP_EXT_D32);
5287ad62
JB
226static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
227static const arm_feature_set fpu_vfp_v3_or_neon_ext =
228 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
8e79c3df 229static const arm_feature_set fpu_neon_fp16 = ARM_FEATURE (0, FPU_NEON_FP16);
e74cfd16 230
33a392fb 231static int mfloat_abi_opt = -1;
e74cfd16
PB
232/* Record user cpu selection for object attributes. */
233static arm_feature_set selected_cpu = ARM_ARCH_NONE;
ee065d83
PB
234/* Must be long enough to hold any of the names in arm_cpus. */
235static char selected_cpu_name[16];
7cc69913 236#ifdef OBJ_ELF
deeaaff8
DJ
237# ifdef EABI_DEFAULT
238static int meabi_flags = EABI_DEFAULT;
239# else
d507cf36 240static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 241# endif
e1da3f5b
PB
242
243bfd_boolean
5f4273c7 244arm_is_eabi (void)
e1da3f5b
PB
245{
246 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
247}
7cc69913 248#endif
b99bd4ef 249
b99bd4ef 250#ifdef OBJ_ELF
c19d1205 251/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC
252symbolS * GOT_symbol;
253#endif
254
b99bd4ef
NC
255/* 0: assemble for ARM,
256 1: assemble for Thumb,
257 2: assemble for Thumb even though target CPU does not support thumb
258 instructions. */
259static int thumb_mode = 0;
260
c19d1205
ZW
261/* If unified_syntax is true, we are processing the new unified
262 ARM/Thumb syntax. Important differences from the old ARM mode:
263
264 - Immediate operands do not require a # prefix.
265 - Conditional affixes always appear at the end of the
266 instruction. (For backward compatibility, those instructions
267 that formerly had them in the middle, continue to accept them
268 there.)
269 - The IT instruction may appear, and if it does is validated
270 against subsequent conditional affixes. It does not generate
271 machine code.
272
273 Important differences from the old Thumb mode:
274
275 - Immediate operands do not require a # prefix.
276 - Most of the V6T2 instructions are only available in unified mode.
277 - The .N and .W suffixes are recognized and honored (it is an error
278 if they cannot be honored).
279 - All instructions set the flags if and only if they have an 's' affix.
280 - Conditional affixes may be used. They are validated against
281 preceding IT instructions. Unlike ARM mode, you cannot use a
282 conditional affix except in the scope of an IT instruction. */
283
284static bfd_boolean unified_syntax = FALSE;
b99bd4ef 285
5287ad62
JB
286enum neon_el_type
287{
dcbf9037 288 NT_invtype,
5287ad62
JB
289 NT_untyped,
290 NT_integer,
291 NT_float,
292 NT_poly,
293 NT_signed,
dcbf9037 294 NT_unsigned
5287ad62
JB
295};
296
297struct neon_type_el
298{
299 enum neon_el_type type;
300 unsigned size;
301};
302
303#define NEON_MAX_TYPE_ELS 4
304
305struct neon_type
306{
307 struct neon_type_el el[NEON_MAX_TYPE_ELS];
308 unsigned elems;
309};
310
b99bd4ef
NC
311struct arm_it
312{
c19d1205 313 const char * error;
b99bd4ef 314 unsigned long instruction;
c19d1205
ZW
315 int size;
316 int size_req;
317 int cond;
037e8744
JB
318 /* "uncond_value" is set to the value in place of the conditional field in
319 unconditional versions of the instruction, or -1 if nothing is
320 appropriate. */
321 int uncond_value;
5287ad62 322 struct neon_type vectype;
0110f2b8
PB
323 /* Set to the opcode if the instruction needs relaxation.
324 Zero if the instruction is not relaxed. */
325 unsigned long relax;
b99bd4ef
NC
326 struct
327 {
328 bfd_reloc_code_real_type type;
c19d1205
ZW
329 expressionS exp;
330 int pc_rel;
b99bd4ef 331 } reloc;
b99bd4ef 332
c19d1205
ZW
333 struct
334 {
335 unsigned reg;
ca3f61f7 336 signed int imm;
dcbf9037 337 struct neon_type_el vectype;
ca3f61f7
NC
338 unsigned present : 1; /* Operand present. */
339 unsigned isreg : 1; /* Operand was a register. */
340 unsigned immisreg : 1; /* .imm field is a second register. */
5287ad62
JB
341 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
342 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 343 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB
344 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
345 instructions. This allows us to disambiguate ARM <-> vector insns. */
346 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 347 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5287ad62 348 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
037e8744 349 unsigned issingle : 1; /* Operand is VFP single-precision register. */
ca3f61f7
NC
350 unsigned hasreloc : 1; /* Operand has relocation suffix. */
351 unsigned writeback : 1; /* Operand has trailing ! */
352 unsigned preind : 1; /* Preindexed address. */
353 unsigned postind : 1; /* Postindexed address. */
354 unsigned negative : 1; /* Index register was negated. */
355 unsigned shifted : 1; /* Shift applied to operation. */
356 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
c19d1205 357 } operands[6];
b99bd4ef
NC
358};
359
c19d1205 360static struct arm_it inst;
b99bd4ef
NC
361
362#define NUM_FLOAT_VALS 8
363
05d2d07e 364const char * fp_const[] =
b99bd4ef
NC
365{
366 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
367};
368
c19d1205 369/* Number of littlenums required to hold an extended precision number. */
b99bd4ef
NC
370#define MAX_LITTLENUMS 6
371
372LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
373
374#define FAIL (-1)
375#define SUCCESS (0)
376
377#define SUFF_S 1
378#define SUFF_D 2
379#define SUFF_E 3
380#define SUFF_P 4
381
c19d1205
ZW
382#define CP_T_X 0x00008000
383#define CP_T_Y 0x00400000
b99bd4ef 384
c19d1205
ZW
385#define CONDS_BIT 0x00100000
386#define LOAD_BIT 0x00100000
b99bd4ef
NC
387
388#define DOUBLE_LOAD_FLAG 0x00000001
389
390struct asm_cond
391{
c19d1205 392 const char * template;
b99bd4ef
NC
393 unsigned long value;
394};
395
c19d1205 396#define COND_ALWAYS 0xE
b99bd4ef 397
b99bd4ef
NC
398struct asm_psr
399{
b34976b6 400 const char *template;
b99bd4ef
NC
401 unsigned long field;
402};
403
62b3e311
PB
404struct asm_barrier_opt
405{
406 const char *template;
407 unsigned long value;
408};
409
2d2255b5 410/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC
411#define SPSR_BIT (1 << 22)
412
c19d1205
ZW
413/* The individual PSR flag bits. */
414#define PSR_c (1 << 16)
415#define PSR_x (1 << 17)
416#define PSR_s (1 << 18)
417#define PSR_f (1 << 19)
b99bd4ef 418
c19d1205 419struct reloc_entry
bfae80f2 420{
c19d1205
ZW
421 char *name;
422 bfd_reloc_code_real_type reloc;
bfae80f2
RE
423};
424
5287ad62 425enum vfp_reg_pos
bfae80f2 426{
5287ad62
JB
427 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
428 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE
429};
430
431enum vfp_ldstm_type
432{
433 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
434};
435
dcbf9037
JB
436/* Bits for DEFINED field in neon_typed_alias. */
437#define NTA_HASTYPE 1
438#define NTA_HASINDEX 2
439
440struct neon_typed_alias
441{
442 unsigned char defined;
443 unsigned char index;
444 struct neon_type_el eltype;
445};
446
c19d1205
ZW
447/* ARM register categories. This includes coprocessor numbers and various
448 architecture extensions' registers. */
449enum arm_reg_type
bfae80f2 450{
c19d1205
ZW
451 REG_TYPE_RN,
452 REG_TYPE_CP,
453 REG_TYPE_CN,
454 REG_TYPE_FN,
455 REG_TYPE_VFS,
456 REG_TYPE_VFD,
5287ad62 457 REG_TYPE_NQ,
037e8744 458 REG_TYPE_VFSD,
5287ad62 459 REG_TYPE_NDQ,
037e8744 460 REG_TYPE_NSDQ,
c19d1205
ZW
461 REG_TYPE_VFC,
462 REG_TYPE_MVF,
463 REG_TYPE_MVD,
464 REG_TYPE_MVFX,
465 REG_TYPE_MVDX,
466 REG_TYPE_MVAX,
467 REG_TYPE_DSPSC,
468 REG_TYPE_MMXWR,
469 REG_TYPE_MMXWC,
470 REG_TYPE_MMXWCG,
471 REG_TYPE_XSCALE,
bfae80f2
RE
472};
473
dcbf9037
JB
474/* Structure for a hash table entry for a register.
475 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
476 information which states whether a vector type or index is specified (for a
477 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE
478struct reg_entry
479{
dcbf9037
JB
480 const char *name;
481 unsigned char number;
482 unsigned char type;
483 unsigned char builtin;
484 struct neon_typed_alias *neon;
6c43fab6
RE
485};
486
c19d1205
ZW
487/* Diagnostics used when we don't get a register of the expected type. */
488const char *const reg_expected_msgs[] =
489{
490 N_("ARM register expected"),
491 N_("bad or missing co-processor number"),
492 N_("co-processor register expected"),
493 N_("FPA register expected"),
494 N_("VFP single precision register expected"),
5287ad62
JB
495 N_("VFP/Neon double precision register expected"),
496 N_("Neon quad precision register expected"),
037e8744 497 N_("VFP single or double precision register expected"),
5287ad62 498 N_("Neon double or quad precision register expected"),
037e8744 499 N_("VFP single, double or Neon quad precision register expected"),
c19d1205
ZW
500 N_("VFP system register expected"),
501 N_("Maverick MVF register expected"),
502 N_("Maverick MVD register expected"),
503 N_("Maverick MVFX register expected"),
504 N_("Maverick MVDX register expected"),
505 N_("Maverick MVAX register expected"),
506 N_("Maverick DSPSC register expected"),
507 N_("iWMMXt data register expected"),
508 N_("iWMMXt control register expected"),
509 N_("iWMMXt scalar register expected"),
510 N_("XScale accumulator register expected"),
6c43fab6
RE
511};
512
c19d1205
ZW
513/* Some well known registers that we refer to directly elsewhere. */
514#define REG_SP 13
515#define REG_LR 14
516#define REG_PC 15
404ff6b5 517
b99bd4ef
NC
518/* ARM instructions take 4bytes in the object file, Thumb instructions
519 take 2: */
c19d1205 520#define INSN_SIZE 4
b99bd4ef
NC
521
522struct asm_opcode
523{
524 /* Basic string to match. */
c19d1205
ZW
525 const char *template;
526
527 /* Parameters to instruction. */
528 unsigned char operands[8];
529
530 /* Conditional tag - see opcode_lookup. */
531 unsigned int tag : 4;
b99bd4ef
NC
532
533 /* Basic instruction code. */
c19d1205 534 unsigned int avalue : 28;
b99bd4ef 535
c19d1205
ZW
536 /* Thumb-format instruction code. */
537 unsigned int tvalue;
b99bd4ef 538
90e4755a 539 /* Which architecture variant provides this instruction. */
e74cfd16
PB
540 const arm_feature_set *avariant;
541 const arm_feature_set *tvariant;
c19d1205
ZW
542
543 /* Function to call to encode instruction in ARM format. */
544 void (* aencode) (void);
b99bd4ef 545
c19d1205
ZW
546 /* Function to call to encode instruction in Thumb format. */
547 void (* tencode) (void);
b99bd4ef
NC
548};
549
a737bd4d
NC
550/* Defines for various bits that we will want to toggle. */
551#define INST_IMMEDIATE 0x02000000
552#define OFFSET_REG 0x02000000
c19d1205 553#define HWOFFSET_IMM 0x00400000
a737bd4d
NC
554#define SHIFT_BY_REG 0x00000010
555#define PRE_INDEX 0x01000000
556#define INDEX_UP 0x00800000
557#define WRITE_BACK 0x00200000
558#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 559#define CPSI_MMOD 0x00020000
90e4755a 560
a737bd4d
NC
561#define LITERAL_MASK 0xf000f000
562#define OPCODE_MASK 0xfe1fffff
563#define V4_STR_BIT 0x00000020
90e4755a 564
efd81785
PB
565#define T2_SUBS_PC_LR 0xf3de8f00
566
a737bd4d 567#define DATA_OP_SHIFT 21
90e4755a 568
ef8d22e6
PB
569#define T2_OPCODE_MASK 0xfe1fffff
570#define T2_DATA_OP_SHIFT 21
571
a737bd4d
NC
572/* Codes to distinguish the arithmetic instructions. */
573#define OPCODE_AND 0
574#define OPCODE_EOR 1
575#define OPCODE_SUB 2
576#define OPCODE_RSB 3
577#define OPCODE_ADD 4
578#define OPCODE_ADC 5
579#define OPCODE_SBC 6
580#define OPCODE_RSC 7
581#define OPCODE_TST 8
582#define OPCODE_TEQ 9
583#define OPCODE_CMP 10
584#define OPCODE_CMN 11
585#define OPCODE_ORR 12
586#define OPCODE_MOV 13
587#define OPCODE_BIC 14
588#define OPCODE_MVN 15
90e4755a 589
ef8d22e6
PB
590#define T2_OPCODE_AND 0
591#define T2_OPCODE_BIC 1
592#define T2_OPCODE_ORR 2
593#define T2_OPCODE_ORN 3
594#define T2_OPCODE_EOR 4
595#define T2_OPCODE_ADD 8
596#define T2_OPCODE_ADC 10
597#define T2_OPCODE_SBC 11
598#define T2_OPCODE_SUB 13
599#define T2_OPCODE_RSB 14
600
a737bd4d
NC
601#define T_OPCODE_MUL 0x4340
602#define T_OPCODE_TST 0x4200
603#define T_OPCODE_CMN 0x42c0
604#define T_OPCODE_NEG 0x4240
605#define T_OPCODE_MVN 0x43c0
90e4755a 606
a737bd4d
NC
607#define T_OPCODE_ADD_R3 0x1800
608#define T_OPCODE_SUB_R3 0x1a00
609#define T_OPCODE_ADD_HI 0x4400
610#define T_OPCODE_ADD_ST 0xb000
611#define T_OPCODE_SUB_ST 0xb080
612#define T_OPCODE_ADD_SP 0xa800
613#define T_OPCODE_ADD_PC 0xa000
614#define T_OPCODE_ADD_I8 0x3000
615#define T_OPCODE_SUB_I8 0x3800
616#define T_OPCODE_ADD_I3 0x1c00
617#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 618
a737bd4d
NC
619#define T_OPCODE_ASR_R 0x4100
620#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW
621#define T_OPCODE_LSR_R 0x40c0
622#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC
623#define T_OPCODE_ASR_I 0x1000
624#define T_OPCODE_LSL_I 0x0000
625#define T_OPCODE_LSR_I 0x0800
b99bd4ef 626
a737bd4d
NC
627#define T_OPCODE_MOV_I8 0x2000
628#define T_OPCODE_CMP_I8 0x2800
629#define T_OPCODE_CMP_LR 0x4280
630#define T_OPCODE_MOV_HR 0x4600
631#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 632
a737bd4d
NC
633#define T_OPCODE_LDR_PC 0x4800
634#define T_OPCODE_LDR_SP 0x9800
635#define T_OPCODE_STR_SP 0x9000
636#define T_OPCODE_LDR_IW 0x6800
637#define T_OPCODE_STR_IW 0x6000
638#define T_OPCODE_LDR_IH 0x8800
639#define T_OPCODE_STR_IH 0x8000
640#define T_OPCODE_LDR_IB 0x7800
641#define T_OPCODE_STR_IB 0x7000
642#define T_OPCODE_LDR_RW 0x5800
643#define T_OPCODE_STR_RW 0x5000
644#define T_OPCODE_LDR_RH 0x5a00
645#define T_OPCODE_STR_RH 0x5200
646#define T_OPCODE_LDR_RB 0x5c00
647#define T_OPCODE_STR_RB 0x5400
c9b604bd 648
a737bd4d
NC
649#define T_OPCODE_PUSH 0xb400
650#define T_OPCODE_POP 0xbc00
b99bd4ef 651
2fc8bdac 652#define T_OPCODE_BRANCH 0xe000
b99bd4ef 653
a737bd4d 654#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 655#define THUMB_PP_PC_LR 0x0100
c19d1205 656#define THUMB_LOAD_BIT 0x0800
53365c0d 657#define THUMB2_LOAD_BIT 0x00100000
c19d1205
ZW
658
659#define BAD_ARGS _("bad arguments to instruction")
660#define BAD_PC _("r15 not allowed here")
661#define BAD_COND _("instruction cannot be conditional")
662#define BAD_OVERLAP _("registers may not be the same")
663#define BAD_HIREG _("lo register required")
664#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
01cfc07f 665#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
dfa9f0d5
PB
666#define BAD_BRANCH _("branch must be last instruction in IT block")
667#define BAD_NOT_IT _("instruction not allowed in IT block")
037e8744 668#define BAD_FPU _("selected FPU does not support instruction")
c19d1205
ZW
669
670static struct hash_control *arm_ops_hsh;
671static struct hash_control *arm_cond_hsh;
672static struct hash_control *arm_shift_hsh;
673static struct hash_control *arm_psr_hsh;
62b3e311 674static struct hash_control *arm_v7m_psr_hsh;
c19d1205
ZW
675static struct hash_control *arm_reg_hsh;
676static struct hash_control *arm_reloc_hsh;
62b3e311 677static struct hash_control *arm_barrier_opt_hsh;
b99bd4ef 678
b99bd4ef
NC
679/* Stuff needed to resolve the label ambiguity
680 As:
681 ...
682 label: <insn>
683 may differ from:
684 ...
685 label:
5f4273c7 686 <insn> */
b99bd4ef
NC
687
688symbolS * last_label_seen;
b34976b6 689static int label_is_thumb_function_name = FALSE;
a737bd4d 690\f
3d0c9500
NC
691/* Literal pool structure. Held on a per-section
692 and per-sub-section basis. */
a737bd4d 693
c19d1205 694#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 695typedef struct literal_pool
b99bd4ef 696{
c19d1205
ZW
697 expressionS literals [MAX_LITERAL_POOL_SIZE];
698 unsigned int next_free_entry;
699 unsigned int id;
700 symbolS * symbol;
701 segT section;
702 subsegT sub_section;
61b5f74b 703 struct literal_pool * next;
3d0c9500 704} literal_pool;
b99bd4ef 705
3d0c9500
NC
706/* Pointer to a linked list of literal pools. */
707literal_pool * list_of_pools = NULL;
e27ec89e
PB
708
709/* State variables for IT block handling. */
710static bfd_boolean current_it_mask = 0;
711static int current_cc;
c19d1205
ZW
712\f
713/* Pure syntax. */
b99bd4ef 714
c19d1205
ZW
715/* This array holds the chars that always start a comment. If the
716 pre-processor is disabled, these aren't very useful. */
717const char comment_chars[] = "@";
3d0c9500 718
c19d1205
ZW
719/* This array holds the chars that only start a comment at the beginning of
720 a line. If the line seems to have the form '# 123 filename'
721 .line and .file directives will appear in the pre-processed output. */
722/* Note that input_file.c hand checks for '#' at the beginning of the
723 first line of the input file. This is because the compiler outputs
724 #NO_APP at the beginning of its output. */
725/* Also note that comments like this one will always work. */
726const char line_comment_chars[] = "#";
3d0c9500 727
c19d1205 728const char line_separator_chars[] = ";";
b99bd4ef 729
c19d1205
ZW
730/* Chars that can be used to separate mant
731 from exp in floating point numbers. */
732const char EXP_CHARS[] = "eE";
3d0c9500 733
c19d1205
ZW
734/* Chars that mean this number is a floating point constant. */
735/* As in 0f12.456 */
736/* or 0d1.2345e12 */
b99bd4ef 737
c19d1205 738const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 739
c19d1205
ZW
740/* Prefix characters that indicate the start of an immediate
741 value. */
742#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 743
c19d1205
ZW
744/* Separator character handling. */
745
746#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
747
748static inline int
749skip_past_char (char ** str, char c)
750{
751 if (**str == c)
752 {
753 (*str)++;
754 return SUCCESS;
3d0c9500 755 }
c19d1205
ZW
756 else
757 return FAIL;
758}
759#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 760
c19d1205
ZW
761/* Arithmetic expressions (possibly involving symbols). */
762
763/* Return TRUE if anything in the expression is a bignum. */
764
765static int
766walk_no_bignums (symbolS * sp)
767{
768 if (symbol_get_value_expression (sp)->X_op == O_big)
769 return 1;
770
771 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 772 {
c19d1205
ZW
773 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
774 || (symbol_get_value_expression (sp)->X_op_symbol
775 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC
776 }
777
c19d1205 778 return 0;
3d0c9500
NC
779}
780
c19d1205
ZW
781static int in_my_get_expression = 0;
782
783/* Third argument to my_get_expression. */
784#define GE_NO_PREFIX 0
785#define GE_IMM_PREFIX 1
786#define GE_OPT_PREFIX 2
5287ad62
JB
787/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
788 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
789#define GE_OPT_PREFIX_BIG 3
a737bd4d 790
b99bd4ef 791static int
c19d1205 792my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 793{
c19d1205
ZW
794 char * save_in;
795 segT seg;
b99bd4ef 796
c19d1205
ZW
797 /* In unified syntax, all prefixes are optional. */
798 if (unified_syntax)
5287ad62
JB
799 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
800 : GE_OPT_PREFIX;
b99bd4ef 801
c19d1205 802 switch (prefix_mode)
b99bd4ef 803 {
c19d1205
ZW
804 case GE_NO_PREFIX: break;
805 case GE_IMM_PREFIX:
806 if (!is_immediate_prefix (**str))
807 {
808 inst.error = _("immediate expression requires a # prefix");
809 return FAIL;
810 }
811 (*str)++;
812 break;
813 case GE_OPT_PREFIX:
5287ad62 814 case GE_OPT_PREFIX_BIG:
c19d1205
ZW
815 if (is_immediate_prefix (**str))
816 (*str)++;
817 break;
818 default: abort ();
819 }
b99bd4ef 820
c19d1205 821 memset (ep, 0, sizeof (expressionS));
b99bd4ef 822
c19d1205
ZW
823 save_in = input_line_pointer;
824 input_line_pointer = *str;
825 in_my_get_expression = 1;
826 seg = expression (ep);
827 in_my_get_expression = 0;
828
829 if (ep->X_op == O_illegal)
b99bd4ef 830 {
c19d1205
ZW
831 /* We found a bad expression in md_operand(). */
832 *str = input_line_pointer;
833 input_line_pointer = save_in;
834 if (inst.error == NULL)
835 inst.error = _("bad expression");
836 return 1;
837 }
b99bd4ef 838
c19d1205
ZW
839#ifdef OBJ_AOUT
840 if (seg != absolute_section
841 && seg != text_section
842 && seg != data_section
843 && seg != bss_section
844 && seg != undefined_section)
845 {
846 inst.error = _("bad segment");
847 *str = input_line_pointer;
848 input_line_pointer = save_in;
849 return 1;
b99bd4ef 850 }
c19d1205 851#endif
b99bd4ef 852
c19d1205
ZW
853 /* Get rid of any bignums now, so that we don't generate an error for which
854 we can't establish a line number later on. Big numbers are never valid
855 in instructions, which is where this routine is always called. */
5287ad62
JB
856 if (prefix_mode != GE_OPT_PREFIX_BIG
857 && (ep->X_op == O_big
858 || (ep->X_add_symbol
859 && (walk_no_bignums (ep->X_add_symbol)
860 || (ep->X_op_symbol
861 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW
862 {
863 inst.error = _("invalid constant");
864 *str = input_line_pointer;
865 input_line_pointer = save_in;
866 return 1;
867 }
b99bd4ef 868
c19d1205
ZW
869 *str = input_line_pointer;
870 input_line_pointer = save_in;
871 return 0;
b99bd4ef
NC
872}
873
c19d1205
ZW
874/* Turn a string in input_line_pointer into a floating point constant
875 of type TYPE, and store the appropriate bytes in *LITP. The number
876 of LITTLENUMS emitted is stored in *SIZEP. An error message is
877 returned, or NULL on OK.
b99bd4ef 878
c19d1205
ZW
879 Note that fp constants aren't represent in the normal way on the ARM.
880 In big endian mode, things are as expected. However, in little endian
881 mode fp constants are big-endian word-wise, and little-endian byte-wise
882 within the words. For example, (double) 1.1 in big endian mode is
883 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
884 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 885
c19d1205 886 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 887
c19d1205
ZW
888char *
889md_atof (int type, char * litP, int * sizeP)
890{
891 int prec;
892 LITTLENUM_TYPE words[MAX_LITTLENUMS];
893 char *t;
894 int i;
b99bd4ef 895
c19d1205
ZW
896 switch (type)
897 {
898 case 'f':
899 case 'F':
900 case 's':
901 case 'S':
902 prec = 2;
903 break;
b99bd4ef 904
c19d1205
ZW
905 case 'd':
906 case 'D':
907 case 'r':
908 case 'R':
909 prec = 4;
910 break;
b99bd4ef 911
c19d1205
ZW
912 case 'x':
913 case 'X':
499ac353 914 prec = 5;
c19d1205 915 break;
b99bd4ef 916
c19d1205
ZW
917 case 'p':
918 case 'P':
499ac353 919 prec = 5;
c19d1205 920 break;
a737bd4d 921
c19d1205
ZW
922 default:
923 *sizeP = 0;
499ac353 924 return _("Unrecognized or unsupported floating point constant");
c19d1205 925 }
b99bd4ef 926
c19d1205
ZW
927 t = atof_ieee (input_line_pointer, type, words);
928 if (t)
929 input_line_pointer = t;
499ac353 930 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 931
c19d1205
ZW
932 if (target_big_endian)
933 {
934 for (i = 0; i < prec; i++)
935 {
499ac353
NC
936 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
937 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW
938 }
939 }
940 else
941 {
e74cfd16 942 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
c19d1205
ZW
943 for (i = prec - 1; i >= 0; i--)
944 {
499ac353
NC
945 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
946 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW
947 }
948 else
949 /* For a 4 byte float the order of elements in `words' is 1 0.
950 For an 8 byte float the order is 1 0 3 2. */
951 for (i = 0; i < prec; i += 2)
952 {
499ac353
NC
953 md_number_to_chars (litP, (valueT) words[i + 1],
954 sizeof (LITTLENUM_TYPE));
955 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
956 (valueT) words[i], sizeof (LITTLENUM_TYPE));
957 litP += 2 * sizeof (LITTLENUM_TYPE);
c19d1205
ZW
958 }
959 }
b99bd4ef 960
499ac353 961 return NULL;
c19d1205 962}
b99bd4ef 963
c19d1205
ZW
964/* We handle all bad expressions here, so that we can report the faulty
965 instruction in the error message. */
966void
967md_operand (expressionS * expr)
968{
969 if (in_my_get_expression)
970 expr->X_op = O_illegal;
b99bd4ef
NC
971}
972
c19d1205 973/* Immediate values. */
b99bd4ef 974
c19d1205
ZW
975/* Generic immediate-value read function for use in directives.
976 Accepts anything that 'expression' can fold to a constant.
977 *val receives the number. */
978#ifdef OBJ_ELF
979static int
980immediate_for_directive (int *val)
b99bd4ef 981{
c19d1205
ZW
982 expressionS exp;
983 exp.X_op = O_illegal;
b99bd4ef 984
c19d1205
ZW
985 if (is_immediate_prefix (*input_line_pointer))
986 {
987 input_line_pointer++;
988 expression (&exp);
989 }
b99bd4ef 990
c19d1205
ZW
991 if (exp.X_op != O_constant)
992 {
993 as_bad (_("expected #constant"));
994 ignore_rest_of_line ();
995 return FAIL;
996 }
997 *val = exp.X_add_number;
998 return SUCCESS;
b99bd4ef 999}
c19d1205 1000#endif
b99bd4ef 1001
c19d1205 1002/* Register parsing. */
b99bd4ef 1003
c19d1205
ZW
1004/* Generic register parser. CCP points to what should be the
1005 beginning of a register name. If it is indeed a valid register
1006 name, advance CCP over it and return the reg_entry structure;
1007 otherwise return NULL. Does not issue diagnostics. */
1008
1009static struct reg_entry *
1010arm_reg_parse_multi (char **ccp)
b99bd4ef 1011{
c19d1205
ZW
1012 char *start = *ccp;
1013 char *p;
1014 struct reg_entry *reg;
b99bd4ef 1015
c19d1205
ZW
1016#ifdef REGISTER_PREFIX
1017 if (*start != REGISTER_PREFIX)
01cfc07f 1018 return NULL;
c19d1205
ZW
1019 start++;
1020#endif
1021#ifdef OPTIONAL_REGISTER_PREFIX
1022 if (*start == OPTIONAL_REGISTER_PREFIX)
1023 start++;
1024#endif
b99bd4ef 1025
c19d1205
ZW
1026 p = start;
1027 if (!ISALPHA (*p) || !is_name_beginner (*p))
1028 return NULL;
b99bd4ef 1029
c19d1205
ZW
1030 do
1031 p++;
1032 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1033
1034 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1035
1036 if (!reg)
1037 return NULL;
1038
1039 *ccp = p;
1040 return reg;
b99bd4ef
NC
1041}
1042
1043static int
dcbf9037
JB
1044arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1045 enum arm_reg_type type)
b99bd4ef 1046{
c19d1205
ZW
1047 /* Alternative syntaxes are accepted for a few register classes. */
1048 switch (type)
1049 {
1050 case REG_TYPE_MVF:
1051 case REG_TYPE_MVD:
1052 case REG_TYPE_MVFX:
1053 case REG_TYPE_MVDX:
1054 /* Generic coprocessor register names are allowed for these. */
79134647 1055 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW
1056 return reg->number;
1057 break;
69b97547 1058
c19d1205
ZW
1059 case REG_TYPE_CP:
1060 /* For backward compatibility, a bare number is valid here. */
1061 {
1062 unsigned long processor = strtoul (start, ccp, 10);
1063 if (*ccp != start && processor <= 15)
1064 return processor;
1065 }
6057a28f 1066
c19d1205
ZW
1067 case REG_TYPE_MMXWC:
1068 /* WC includes WCG. ??? I'm not sure this is true for all
1069 instructions that take WC registers. */
79134647 1070 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1071 return reg->number;
6057a28f 1072 break;
c19d1205 1073
6057a28f 1074 default:
c19d1205 1075 break;
6057a28f
NC
1076 }
1077
dcbf9037
JB
1078 return FAIL;
1079}
1080
1081/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1082 return value is the register number or FAIL. */
1083
1084static int
1085arm_reg_parse (char **ccp, enum arm_reg_type type)
1086{
1087 char *start = *ccp;
1088 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1089 int ret;
1090
1091 /* Do not allow a scalar (reg+index) to parse as a register. */
1092 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1093 return FAIL;
1094
1095 if (reg && reg->type == type)
1096 return reg->number;
1097
1098 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1099 return ret;
1100
c19d1205
ZW
1101 *ccp = start;
1102 return FAIL;
1103}
69b97547 1104
dcbf9037
JB
1105/* Parse a Neon type specifier. *STR should point at the leading '.'
1106 character. Does no verification at this stage that the type fits the opcode
1107 properly. E.g.,
1108
1109 .i32.i32.s16
1110 .s32.f32
1111 .u16
1112
1113 Can all be legally parsed by this function.
1114
1115 Fills in neon_type struct pointer with parsed information, and updates STR
1116 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1117 type, FAIL if not. */
1118
1119static int
1120parse_neon_type (struct neon_type *type, char **str)
1121{
1122 char *ptr = *str;
1123
1124 if (type)
1125 type->elems = 0;
1126
1127 while (type->elems < NEON_MAX_TYPE_ELS)
1128 {
1129 enum neon_el_type thistype = NT_untyped;
1130 unsigned thissize = -1u;
1131
1132 if (*ptr != '.')
1133 break;
1134
1135 ptr++;
1136
1137 /* Just a size without an explicit type. */
1138 if (ISDIGIT (*ptr))
1139 goto parsesize;
1140
1141 switch (TOLOWER (*ptr))
1142 {
1143 case 'i': thistype = NT_integer; break;
1144 case 'f': thistype = NT_float; break;
1145 case 'p': thistype = NT_poly; break;
1146 case 's': thistype = NT_signed; break;
1147 case 'u': thistype = NT_unsigned; break;
037e8744
JB
1148 case 'd':
1149 thistype = NT_float;
1150 thissize = 64;
1151 ptr++;
1152 goto done;
dcbf9037
JB
1153 default:
1154 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1155 return FAIL;
1156 }
1157
1158 ptr++;
1159
1160 /* .f is an abbreviation for .f32. */
1161 if (thistype == NT_float && !ISDIGIT (*ptr))
1162 thissize = 32;
1163 else
1164 {
1165 parsesize:
1166 thissize = strtoul (ptr, &ptr, 10);
1167
1168 if (thissize != 8 && thissize != 16 && thissize != 32
1169 && thissize != 64)
1170 {
1171 as_bad (_("bad size %d in type specifier"), thissize);
1172 return FAIL;
1173 }
1174 }
1175
037e8744 1176 done:
dcbf9037
JB
1177 if (type)
1178 {
1179 type->el[type->elems].type = thistype;
1180 type->el[type->elems].size = thissize;
1181 type->elems++;
1182 }
1183 }
1184
1185 /* Empty/missing type is not a successful parse. */
1186 if (type->elems == 0)
1187 return FAIL;
1188
1189 *str = ptr;
1190
1191 return SUCCESS;
1192}
1193
1194/* Errors may be set multiple times during parsing or bit encoding
1195 (particularly in the Neon bits), but usually the earliest error which is set
1196 will be the most meaningful. Avoid overwriting it with later (cascading)
1197 errors by calling this function. */
1198
1199static void
1200first_error (const char *err)
1201{
1202 if (!inst.error)
1203 inst.error = err;
1204}
1205
1206/* Parse a single type, e.g. ".s32", leading period included. */
1207static int
1208parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1209{
1210 char *str = *ccp;
1211 struct neon_type optype;
1212
1213 if (*str == '.')
1214 {
1215 if (parse_neon_type (&optype, &str) == SUCCESS)
1216 {
1217 if (optype.elems == 1)
1218 *vectype = optype.el[0];
1219 else
1220 {
1221 first_error (_("only one type should be specified for operand"));
1222 return FAIL;
1223 }
1224 }
1225 else
1226 {
1227 first_error (_("vector type expected"));
1228 return FAIL;
1229 }
1230 }
1231 else
1232 return FAIL;
5f4273c7 1233
dcbf9037 1234 *ccp = str;
5f4273c7 1235
dcbf9037
JB
1236 return SUCCESS;
1237}
1238
1239/* Special meanings for indices (which have a range of 0-7), which will fit into
1240 a 4-bit integer. */
1241
1242#define NEON_ALL_LANES 15
1243#define NEON_INTERLEAVE_LANES 14
1244
1245/* Parse either a register or a scalar, with an optional type. Return the
1246 register number, and optionally fill in the actual type of the register
1247 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1248 type/index information in *TYPEINFO. */
1249
1250static int
1251parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1252 enum arm_reg_type *rtype,
1253 struct neon_typed_alias *typeinfo)
1254{
1255 char *str = *ccp;
1256 struct reg_entry *reg = arm_reg_parse_multi (&str);
1257 struct neon_typed_alias atype;
1258 struct neon_type_el parsetype;
1259
1260 atype.defined = 0;
1261 atype.index = -1;
1262 atype.eltype.type = NT_invtype;
1263 atype.eltype.size = -1;
1264
1265 /* Try alternate syntax for some types of register. Note these are mutually
1266 exclusive with the Neon syntax extensions. */
1267 if (reg == NULL)
1268 {
1269 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1270 if (altreg != FAIL)
1271 *ccp = str;
1272 if (typeinfo)
1273 *typeinfo = atype;
1274 return altreg;
1275 }
1276
037e8744
JB
1277 /* Undo polymorphism when a set of register types may be accepted. */
1278 if ((type == REG_TYPE_NDQ
1279 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1280 || (type == REG_TYPE_VFSD
1281 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1282 || (type == REG_TYPE_NSDQ
1283 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
f512f76f
NC
1284 || reg->type == REG_TYPE_NQ))
1285 || (type == REG_TYPE_MMXWC
1286 && (reg->type == REG_TYPE_MMXWCG)))
dcbf9037
JB
1287 type = reg->type;
1288
1289 if (type != reg->type)
1290 return FAIL;
1291
1292 if (reg->neon)
1293 atype = *reg->neon;
5f4273c7 1294
dcbf9037
JB
1295 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1296 {
1297 if ((atype.defined & NTA_HASTYPE) != 0)
1298 {
1299 first_error (_("can't redefine type for operand"));
1300 return FAIL;
1301 }
1302 atype.defined |= NTA_HASTYPE;
1303 atype.eltype = parsetype;
1304 }
5f4273c7 1305
dcbf9037
JB
1306 if (skip_past_char (&str, '[') == SUCCESS)
1307 {
1308 if (type != REG_TYPE_VFD)
1309 {
1310 first_error (_("only D registers may be indexed"));
1311 return FAIL;
1312 }
5f4273c7 1313
dcbf9037
JB
1314 if ((atype.defined & NTA_HASINDEX) != 0)
1315 {
1316 first_error (_("can't change index for operand"));
1317 return FAIL;
1318 }
1319
1320 atype.defined |= NTA_HASINDEX;
1321
1322 if (skip_past_char (&str, ']') == SUCCESS)
1323 atype.index = NEON_ALL_LANES;
1324 else
1325 {
1326 expressionS exp;
1327
1328 my_get_expression (&exp, &str, GE_NO_PREFIX);
1329
1330 if (exp.X_op != O_constant)
1331 {
1332 first_error (_("constant expression required"));
1333 return FAIL;
1334 }
1335
1336 if (skip_past_char (&str, ']') == FAIL)
1337 return FAIL;
1338
1339 atype.index = exp.X_add_number;
1340 }
1341 }
5f4273c7 1342
dcbf9037
JB
1343 if (typeinfo)
1344 *typeinfo = atype;
5f4273c7 1345
dcbf9037
JB
1346 if (rtype)
1347 *rtype = type;
5f4273c7 1348
dcbf9037 1349 *ccp = str;
5f4273c7 1350
dcbf9037
JB
1351 return reg->number;
1352}
1353
1354/* Like arm_reg_parse, but allow allow the following extra features:
1355 - If RTYPE is non-zero, return the (possibly restricted) type of the
1356 register (e.g. Neon double or quad reg when either has been requested).
1357 - If this is a Neon vector type with additional type information, fill
1358 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1359 This function will fault on encountering a scalar. */
dcbf9037
JB
1360
1361static int
1362arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1363 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1364{
1365 struct neon_typed_alias atype;
1366 char *str = *ccp;
1367 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1368
1369 if (reg == FAIL)
1370 return FAIL;
1371
1372 /* Do not allow a scalar (reg+index) to parse as a register. */
1373 if ((atype.defined & NTA_HASINDEX) != 0)
1374 {
1375 first_error (_("register operand expected, but got scalar"));
1376 return FAIL;
1377 }
1378
1379 if (vectype)
1380 *vectype = atype.eltype;
1381
1382 *ccp = str;
1383
1384 return reg;
1385}
1386
1387#define NEON_SCALAR_REG(X) ((X) >> 4)
1388#define NEON_SCALAR_INDEX(X) ((X) & 15)
1389
5287ad62
JB
1390/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1391 have enough information to be able to do a good job bounds-checking. So, we
1392 just do easy checks here, and do further checks later. */
1393
1394static int
dcbf9037 1395parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
5287ad62 1396{
dcbf9037 1397 int reg;
5287ad62 1398 char *str = *ccp;
dcbf9037 1399 struct neon_typed_alias atype;
5f4273c7 1400
dcbf9037 1401 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
5f4273c7 1402
dcbf9037 1403 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1404 return FAIL;
5f4273c7 1405
dcbf9037 1406 if (atype.index == NEON_ALL_LANES)
5287ad62 1407 {
dcbf9037 1408 first_error (_("scalar must have an index"));
5287ad62
JB
1409 return FAIL;
1410 }
dcbf9037 1411 else if (atype.index >= 64 / elsize)
5287ad62 1412 {
dcbf9037 1413 first_error (_("scalar index out of range"));
5287ad62
JB
1414 return FAIL;
1415 }
5f4273c7 1416
dcbf9037
JB
1417 if (type)
1418 *type = atype.eltype;
5f4273c7 1419
5287ad62 1420 *ccp = str;
5f4273c7 1421
dcbf9037 1422 return reg * 16 + atype.index;
5287ad62
JB
1423}
1424
c19d1205
ZW
1425/* Parse an ARM register list. Returns the bitmask, or FAIL. */
1426static long
1427parse_reg_list (char ** strp)
1428{
1429 char * str = * strp;
1430 long range = 0;
1431 int another_range;
a737bd4d 1432
c19d1205
ZW
1433 /* We come back here if we get ranges concatenated by '+' or '|'. */
1434 do
6057a28f 1435 {
c19d1205 1436 another_range = 0;
a737bd4d 1437
c19d1205
ZW
1438 if (*str == '{')
1439 {
1440 int in_range = 0;
1441 int cur_reg = -1;
a737bd4d 1442
c19d1205
ZW
1443 str++;
1444 do
1445 {
1446 int reg;
6057a28f 1447
dcbf9037 1448 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
c19d1205 1449 {
dcbf9037 1450 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
c19d1205
ZW
1451 return FAIL;
1452 }
a737bd4d 1453
c19d1205
ZW
1454 if (in_range)
1455 {
1456 int i;
a737bd4d 1457
c19d1205
ZW
1458 if (reg <= cur_reg)
1459 {
dcbf9037 1460 first_error (_("bad range in register list"));
c19d1205
ZW
1461 return FAIL;
1462 }
40a18ebd 1463
c19d1205
ZW
1464 for (i = cur_reg + 1; i < reg; i++)
1465 {
1466 if (range & (1 << i))
1467 as_tsktsk
1468 (_("Warning: duplicated register (r%d) in register list"),
1469 i);
1470 else
1471 range |= 1 << i;
1472 }
1473 in_range = 0;
1474 }
a737bd4d 1475
c19d1205
ZW
1476 if (range & (1 << reg))
1477 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1478 reg);
1479 else if (reg <= cur_reg)
1480 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1481
c19d1205
ZW
1482 range |= 1 << reg;
1483 cur_reg = reg;
1484 }
1485 while (skip_past_comma (&str) != FAIL
1486 || (in_range = 1, *str++ == '-'));
1487 str--;
a737bd4d 1488
c19d1205
ZW
1489 if (*str++ != '}')
1490 {
dcbf9037 1491 first_error (_("missing `}'"));
c19d1205
ZW
1492 return FAIL;
1493 }
1494 }
1495 else
1496 {
1497 expressionS expr;
40a18ebd 1498
c19d1205
ZW
1499 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1500 return FAIL;
40a18ebd 1501
c19d1205
ZW
1502 if (expr.X_op == O_constant)
1503 {
1504 if (expr.X_add_number
1505 != (expr.X_add_number & 0x0000ffff))
1506 {
1507 inst.error = _("invalid register mask");
1508 return FAIL;
1509 }
a737bd4d 1510
c19d1205
ZW
1511 if ((range & expr.X_add_number) != 0)
1512 {
1513 int regno = range & expr.X_add_number;
a737bd4d 1514
c19d1205
ZW
1515 regno &= -regno;
1516 regno = (1 << regno) - 1;
1517 as_tsktsk
1518 (_("Warning: duplicated register (r%d) in register list"),
1519 regno);
1520 }
a737bd4d 1521
c19d1205
ZW
1522 range |= expr.X_add_number;
1523 }
1524 else
1525 {
1526 if (inst.reloc.type != 0)
1527 {
1528 inst.error = _("expression too complex");
1529 return FAIL;
1530 }
a737bd4d 1531
c19d1205
ZW
1532 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1533 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1534 inst.reloc.pc_rel = 0;
1535 }
1536 }
a737bd4d 1537
c19d1205
ZW
1538 if (*str == '|' || *str == '+')
1539 {
1540 str++;
1541 another_range = 1;
1542 }
a737bd4d 1543 }
c19d1205 1544 while (another_range);
a737bd4d 1545
c19d1205
ZW
1546 *strp = str;
1547 return range;
a737bd4d
NC
1548}
1549
5287ad62
JB
1550/* Types of registers in a list. */
1551
1552enum reg_list_els
1553{
1554 REGLIST_VFP_S,
1555 REGLIST_VFP_D,
1556 REGLIST_NEON_D
1557};
1558
c19d1205
ZW
1559/* Parse a VFP register list. If the string is invalid return FAIL.
1560 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB
1561 register. Parses registers of type ETYPE.
1562 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1563 - Q registers can be used to specify pairs of D registers
1564 - { } can be omitted from around a singleton register list
1565 FIXME: This is not implemented, as it would require backtracking in
1566 some cases, e.g.:
1567 vtbl.8 d3,d4,d5
1568 This could be done (the meaning isn't really ambiguous), but doesn't
1569 fit in well with the current parsing framework.
dcbf9037
JB
1570 - 32 D registers may be used (also true for VFPv3).
1571 FIXME: Types are ignored in these register lists, which is probably a
1572 bug. */
6057a28f 1573
c19d1205 1574static int
037e8744 1575parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
6057a28f 1576{
037e8744 1577 char *str = *ccp;
c19d1205
ZW
1578 int base_reg;
1579 int new_base;
5287ad62
JB
1580 enum arm_reg_type regtype = 0;
1581 int max_regs = 0;
c19d1205
ZW
1582 int count = 0;
1583 int warned = 0;
1584 unsigned long mask = 0;
a737bd4d 1585 int i;
6057a28f 1586
037e8744 1587 if (*str != '{')
5287ad62
JB
1588 {
1589 inst.error = _("expecting {");
1590 return FAIL;
1591 }
6057a28f 1592
037e8744 1593 str++;
6057a28f 1594
5287ad62 1595 switch (etype)
c19d1205 1596 {
5287ad62 1597 case REGLIST_VFP_S:
c19d1205
ZW
1598 regtype = REG_TYPE_VFS;
1599 max_regs = 32;
5287ad62 1600 break;
5f4273c7 1601
5287ad62
JB
1602 case REGLIST_VFP_D:
1603 regtype = REG_TYPE_VFD;
b7fc2769 1604 break;
5f4273c7 1605
b7fc2769
JB
1606 case REGLIST_NEON_D:
1607 regtype = REG_TYPE_NDQ;
1608 break;
1609 }
1610
1611 if (etype != REGLIST_VFP_S)
1612 {
b1cc4aeb
PB
1613 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1614 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
5287ad62
JB
1615 {
1616 max_regs = 32;
1617 if (thumb_mode)
1618 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
b1cc4aeb 1619 fpu_vfp_ext_d32);
5287ad62
JB
1620 else
1621 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
b1cc4aeb 1622 fpu_vfp_ext_d32);
5287ad62
JB
1623 }
1624 else
1625 max_regs = 16;
c19d1205 1626 }
6057a28f 1627
c19d1205 1628 base_reg = max_regs;
a737bd4d 1629
c19d1205
ZW
1630 do
1631 {
5287ad62 1632 int setmask = 1, addregs = 1;
dcbf9037 1633
037e8744 1634 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 1635
c19d1205 1636 if (new_base == FAIL)
a737bd4d 1637 {
dcbf9037 1638 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW
1639 return FAIL;
1640 }
5f4273c7 1641
b7fc2769
JB
1642 if (new_base >= max_regs)
1643 {
1644 first_error (_("register out of range in list"));
1645 return FAIL;
1646 }
5f4273c7 1647
5287ad62
JB
1648 /* Note: a value of 2 * n is returned for the register Q<n>. */
1649 if (regtype == REG_TYPE_NQ)
1650 {
1651 setmask = 3;
1652 addregs = 2;
1653 }
1654
c19d1205
ZW
1655 if (new_base < base_reg)
1656 base_reg = new_base;
a737bd4d 1657
5287ad62 1658 if (mask & (setmask << new_base))
c19d1205 1659 {
dcbf9037 1660 first_error (_("invalid register list"));
c19d1205 1661 return FAIL;
a737bd4d 1662 }
a737bd4d 1663
c19d1205
ZW
1664 if ((mask >> new_base) != 0 && ! warned)
1665 {
1666 as_tsktsk (_("register list not in ascending order"));
1667 warned = 1;
1668 }
0bbf2aa4 1669
5287ad62
JB
1670 mask |= setmask << new_base;
1671 count += addregs;
0bbf2aa4 1672
037e8744 1673 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW
1674 {
1675 int high_range;
0bbf2aa4 1676
037e8744 1677 str++;
0bbf2aa4 1678
037e8744 1679 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
dcbf9037 1680 == FAIL)
c19d1205
ZW
1681 {
1682 inst.error = gettext (reg_expected_msgs[regtype]);
1683 return FAIL;
1684 }
0bbf2aa4 1685
b7fc2769
JB
1686 if (high_range >= max_regs)
1687 {
1688 first_error (_("register out of range in list"));
1689 return FAIL;
1690 }
1691
5287ad62
JB
1692 if (regtype == REG_TYPE_NQ)
1693 high_range = high_range + 1;
1694
c19d1205
ZW
1695 if (high_range <= new_base)
1696 {
1697 inst.error = _("register range not in ascending order");
1698 return FAIL;
1699 }
0bbf2aa4 1700
5287ad62 1701 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 1702 {
5287ad62 1703 if (mask & (setmask << new_base))
0bbf2aa4 1704 {
c19d1205
ZW
1705 inst.error = _("invalid register list");
1706 return FAIL;
0bbf2aa4 1707 }
c19d1205 1708
5287ad62
JB
1709 mask |= setmask << new_base;
1710 count += addregs;
0bbf2aa4 1711 }
0bbf2aa4 1712 }
0bbf2aa4 1713 }
037e8744 1714 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 1715
037e8744 1716 str++;
0bbf2aa4 1717
c19d1205
ZW
1718 /* Sanity check -- should have raised a parse error above. */
1719 if (count == 0 || count > max_regs)
1720 abort ();
1721
1722 *pbase = base_reg;
1723
1724 /* Final test -- the registers must be consecutive. */
1725 mask >>= base_reg;
1726 for (i = 0; i < count; i++)
1727 {
1728 if ((mask & (1u << i)) == 0)
1729 {
1730 inst.error = _("non-contiguous register range");
1731 return FAIL;
1732 }
1733 }
1734
037e8744
JB
1735 *ccp = str;
1736
c19d1205 1737 return count;
b99bd4ef
NC
1738}
1739
dcbf9037
JB
1740/* True if two alias types are the same. */
1741
1742static int
1743neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1744{
1745 if (!a && !b)
1746 return 1;
5f4273c7 1747
dcbf9037
JB
1748 if (!a || !b)
1749 return 0;
1750
1751 if (a->defined != b->defined)
1752 return 0;
5f4273c7 1753
dcbf9037
JB
1754 if ((a->defined & NTA_HASTYPE) != 0
1755 && (a->eltype.type != b->eltype.type
1756 || a->eltype.size != b->eltype.size))
1757 return 0;
1758
1759 if ((a->defined & NTA_HASINDEX) != 0
1760 && (a->index != b->index))
1761 return 0;
5f4273c7 1762
dcbf9037
JB
1763 return 1;
1764}
1765
5287ad62
JB
1766/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1767 The base register is put in *PBASE.
dcbf9037 1768 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB
1769 the return value.
1770 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB
1771 Bits [6:5] encode the list length (minus one).
1772 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 1773
5287ad62 1774#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 1775#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB
1776#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1777
1778static int
dcbf9037
JB
1779parse_neon_el_struct_list (char **str, unsigned *pbase,
1780 struct neon_type_el *eltype)
5287ad62
JB
1781{
1782 char *ptr = *str;
1783 int base_reg = -1;
1784 int reg_incr = -1;
1785 int count = 0;
1786 int lane = -1;
1787 int leading_brace = 0;
1788 enum arm_reg_type rtype = REG_TYPE_NDQ;
1789 int addregs = 1;
1790 const char *const incr_error = "register stride must be 1 or 2";
1791 const char *const type_error = "mismatched element/structure types in list";
dcbf9037 1792 struct neon_typed_alias firsttype;
5f4273c7 1793
5287ad62
JB
1794 if (skip_past_char (&ptr, '{') == SUCCESS)
1795 leading_brace = 1;
5f4273c7 1796
5287ad62
JB
1797 do
1798 {
dcbf9037
JB
1799 struct neon_typed_alias atype;
1800 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1801
5287ad62
JB
1802 if (getreg == FAIL)
1803 {
dcbf9037 1804 first_error (_(reg_expected_msgs[rtype]));
5287ad62
JB
1805 return FAIL;
1806 }
5f4273c7 1807
5287ad62
JB
1808 if (base_reg == -1)
1809 {
1810 base_reg = getreg;
1811 if (rtype == REG_TYPE_NQ)
1812 {
1813 reg_incr = 1;
1814 addregs = 2;
1815 }
dcbf9037 1816 firsttype = atype;
5287ad62
JB
1817 }
1818 else if (reg_incr == -1)
1819 {
1820 reg_incr = getreg - base_reg;
1821 if (reg_incr < 1 || reg_incr > 2)
1822 {
dcbf9037 1823 first_error (_(incr_error));
5287ad62
JB
1824 return FAIL;
1825 }
1826 }
1827 else if (getreg != base_reg + reg_incr * count)
1828 {
dcbf9037
JB
1829 first_error (_(incr_error));
1830 return FAIL;
1831 }
1832
1833 if (!neon_alias_types_same (&atype, &firsttype))
1834 {
1835 first_error (_(type_error));
5287ad62
JB
1836 return FAIL;
1837 }
5f4273c7 1838
5287ad62
JB
1839 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1840 modes. */
1841 if (ptr[0] == '-')
1842 {
dcbf9037 1843 struct neon_typed_alias htype;
5287ad62
JB
1844 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1845 if (lane == -1)
1846 lane = NEON_INTERLEAVE_LANES;
1847 else if (lane != NEON_INTERLEAVE_LANES)
1848 {
dcbf9037 1849 first_error (_(type_error));
5287ad62
JB
1850 return FAIL;
1851 }
1852 if (reg_incr == -1)
1853 reg_incr = 1;
1854 else if (reg_incr != 1)
1855 {
dcbf9037 1856 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5287ad62
JB
1857 return FAIL;
1858 }
1859 ptr++;
dcbf9037 1860 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
5287ad62
JB
1861 if (hireg == FAIL)
1862 {
dcbf9037
JB
1863 first_error (_(reg_expected_msgs[rtype]));
1864 return FAIL;
1865 }
1866 if (!neon_alias_types_same (&htype, &firsttype))
1867 {
1868 first_error (_(type_error));
5287ad62
JB
1869 return FAIL;
1870 }
1871 count += hireg + dregs - getreg;
1872 continue;
1873 }
5f4273c7 1874
5287ad62
JB
1875 /* If we're using Q registers, we can't use [] or [n] syntax. */
1876 if (rtype == REG_TYPE_NQ)
1877 {
1878 count += 2;
1879 continue;
1880 }
5f4273c7 1881
dcbf9037 1882 if ((atype.defined & NTA_HASINDEX) != 0)
5287ad62 1883 {
dcbf9037
JB
1884 if (lane == -1)
1885 lane = atype.index;
1886 else if (lane != atype.index)
5287ad62 1887 {
dcbf9037
JB
1888 first_error (_(type_error));
1889 return FAIL;
5287ad62
JB
1890 }
1891 }
1892 else if (lane == -1)
1893 lane = NEON_INTERLEAVE_LANES;
1894 else if (lane != NEON_INTERLEAVE_LANES)
1895 {
dcbf9037 1896 first_error (_(type_error));
5287ad62
JB
1897 return FAIL;
1898 }
1899 count++;
1900 }
1901 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 1902
5287ad62
JB
1903 /* No lane set by [x]. We must be interleaving structures. */
1904 if (lane == -1)
1905 lane = NEON_INTERLEAVE_LANES;
5f4273c7 1906
5287ad62
JB
1907 /* Sanity check. */
1908 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
1909 || (count > 1 && reg_incr == -1))
1910 {
dcbf9037 1911 first_error (_("error parsing element/structure list"));
5287ad62
JB
1912 return FAIL;
1913 }
1914
1915 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
1916 {
dcbf9037 1917 first_error (_("expected }"));
5287ad62
JB
1918 return FAIL;
1919 }
5f4273c7 1920
5287ad62
JB
1921 if (reg_incr == -1)
1922 reg_incr = 1;
1923
dcbf9037
JB
1924 if (eltype)
1925 *eltype = firsttype.eltype;
1926
5287ad62
JB
1927 *pbase = base_reg;
1928 *str = ptr;
5f4273c7 1929
5287ad62
JB
1930 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
1931}
1932
c19d1205
ZW
1933/* Parse an explicit relocation suffix on an expression. This is
1934 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1935 arm_reloc_hsh contains no entries, so this function can only
1936 succeed if there is no () after the word. Returns -1 on error,
1937 BFD_RELOC_UNUSED if there wasn't any suffix. */
1938static int
1939parse_reloc (char **str)
b99bd4ef 1940{
c19d1205
ZW
1941 struct reloc_entry *r;
1942 char *p, *q;
b99bd4ef 1943
c19d1205
ZW
1944 if (**str != '(')
1945 return BFD_RELOC_UNUSED;
b99bd4ef 1946
c19d1205
ZW
1947 p = *str + 1;
1948 q = p;
1949
1950 while (*q && *q != ')' && *q != ',')
1951 q++;
1952 if (*q != ')')
1953 return -1;
1954
1955 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1956 return -1;
1957
1958 *str = q + 1;
1959 return r->reloc;
b99bd4ef
NC
1960}
1961
c19d1205
ZW
1962/* Directives: register aliases. */
1963
dcbf9037 1964static struct reg_entry *
c19d1205 1965insert_reg_alias (char *str, int number, int type)
b99bd4ef 1966{
c19d1205
ZW
1967 struct reg_entry *new;
1968 const char *name;
b99bd4ef 1969
c19d1205
ZW
1970 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1971 {
1972 if (new->builtin)
1973 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 1974
c19d1205
ZW
1975 /* Only warn about a redefinition if it's not defined as the
1976 same register. */
1977 else if (new->number != number || new->type != type)
1978 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 1979
d929913e 1980 return NULL;
c19d1205 1981 }
b99bd4ef 1982
c19d1205
ZW
1983 name = xstrdup (str);
1984 new = xmalloc (sizeof (struct reg_entry));
b99bd4ef 1985
c19d1205
ZW
1986 new->name = name;
1987 new->number = number;
1988 new->type = type;
1989 new->builtin = FALSE;
dcbf9037 1990 new->neon = NULL;
b99bd4ef 1991
5a49b8ac 1992 if (hash_insert (arm_reg_hsh, name, (void *) new))
c19d1205 1993 abort ();
5f4273c7 1994
dcbf9037
JB
1995 return new;
1996}
1997
1998static void
1999insert_neon_reg_alias (char *str, int number, int type,
2000 struct neon_typed_alias *atype)
2001{
2002 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2003
dcbf9037
JB
2004 if (!reg)
2005 {
2006 first_error (_("attempt to redefine typed alias"));
2007 return;
2008 }
5f4273c7 2009
dcbf9037
JB
2010 if (atype)
2011 {
2012 reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2013 *reg->neon = *atype;
2014 }
c19d1205 2015}
b99bd4ef 2016
c19d1205 2017/* Look for the .req directive. This is of the form:
b99bd4ef 2018
c19d1205 2019 new_register_name .req existing_register_name
b99bd4ef 2020
c19d1205 2021 If we find one, or if it looks sufficiently like one that we want to
d929913e 2022 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2023
d929913e 2024static bfd_boolean
c19d1205
ZW
2025create_register_alias (char * newname, char *p)
2026{
2027 struct reg_entry *old;
2028 char *oldname, *nbuf;
2029 size_t nlen;
b99bd4ef 2030
c19d1205
ZW
2031 /* The input scrubber ensures that whitespace after the mnemonic is
2032 collapsed to single spaces. */
2033 oldname = p;
2034 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2035 return FALSE;
b99bd4ef 2036
c19d1205
ZW
2037 oldname += 6;
2038 if (*oldname == '\0')
d929913e 2039 return FALSE;
b99bd4ef 2040
c19d1205
ZW
2041 old = hash_find (arm_reg_hsh, oldname);
2042 if (!old)
b99bd4ef 2043 {
c19d1205 2044 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2045 return TRUE;
b99bd4ef
NC
2046 }
2047
c19d1205
ZW
2048 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2049 the desired alias name, and p points to its end. If not, then
2050 the desired alias name is in the global original_case_string. */
2051#ifdef TC_CASE_SENSITIVE
2052 nlen = p - newname;
2053#else
2054 newname = original_case_string;
2055 nlen = strlen (newname);
2056#endif
b99bd4ef 2057
c19d1205
ZW
2058 nbuf = alloca (nlen + 1);
2059 memcpy (nbuf, newname, nlen);
2060 nbuf[nlen] = '\0';
b99bd4ef 2061
c19d1205
ZW
2062 /* Create aliases under the new name as stated; an all-lowercase
2063 version of the new name; and an all-uppercase version of the new
2064 name. */
d929913e
NC
2065 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2066 {
2067 for (p = nbuf; *p; p++)
2068 *p = TOUPPER (*p);
c19d1205 2069
d929913e
NC
2070 if (strncmp (nbuf, newname, nlen))
2071 {
2072 /* If this attempt to create an additional alias fails, do not bother
2073 trying to create the all-lower case alias. We will fail and issue
2074 a second, duplicate error message. This situation arises when the
2075 programmer does something like:
2076 foo .req r0
2077 Foo .req r1
2078 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2079 the artificial FOO alias because it has already been created by the
d929913e
NC
2080 first .req. */
2081 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2082 return TRUE;
2083 }
c19d1205 2084
d929913e
NC
2085 for (p = nbuf; *p; p++)
2086 *p = TOLOWER (*p);
c19d1205 2087
d929913e
NC
2088 if (strncmp (nbuf, newname, nlen))
2089 insert_reg_alias (nbuf, old->number, old->type);
2090 }
c19d1205 2091
d929913e 2092 return TRUE;
b99bd4ef
NC
2093}
2094
dcbf9037
JB
2095/* Create a Neon typed/indexed register alias using directives, e.g.:
2096 X .dn d5.s32[1]
2097 Y .qn 6.s16
2098 Z .dn d7
2099 T .dn Z[0]
2100 These typed registers can be used instead of the types specified after the
2101 Neon mnemonic, so long as all operands given have types. Types can also be
2102 specified directly, e.g.:
5f4273c7 2103 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037
JB
2104
2105static int
2106create_neon_reg_alias (char *newname, char *p)
2107{
2108 enum arm_reg_type basetype;
2109 struct reg_entry *basereg;
2110 struct reg_entry mybasereg;
2111 struct neon_type ntype;
2112 struct neon_typed_alias typeinfo;
2113 char *namebuf, *nameend;
2114 int namelen;
5f4273c7 2115
dcbf9037
JB
2116 typeinfo.defined = 0;
2117 typeinfo.eltype.type = NT_invtype;
2118 typeinfo.eltype.size = -1;
2119 typeinfo.index = -1;
5f4273c7 2120
dcbf9037 2121 nameend = p;
5f4273c7 2122
dcbf9037
JB
2123 if (strncmp (p, " .dn ", 5) == 0)
2124 basetype = REG_TYPE_VFD;
2125 else if (strncmp (p, " .qn ", 5) == 0)
2126 basetype = REG_TYPE_NQ;
2127 else
2128 return 0;
5f4273c7 2129
dcbf9037 2130 p += 5;
5f4273c7 2131
dcbf9037
JB
2132 if (*p == '\0')
2133 return 0;
5f4273c7 2134
dcbf9037
JB
2135 basereg = arm_reg_parse_multi (&p);
2136
2137 if (basereg && basereg->type != basetype)
2138 {
2139 as_bad (_("bad type for register"));
2140 return 0;
2141 }
2142
2143 if (basereg == NULL)
2144 {
2145 expressionS exp;
2146 /* Try parsing as an integer. */
2147 my_get_expression (&exp, &p, GE_NO_PREFIX);
2148 if (exp.X_op != O_constant)
2149 {
2150 as_bad (_("expression must be constant"));
2151 return 0;
2152 }
2153 basereg = &mybasereg;
2154 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2155 : exp.X_add_number;
2156 basereg->neon = 0;
2157 }
2158
2159 if (basereg->neon)
2160 typeinfo = *basereg->neon;
2161
2162 if (parse_neon_type (&ntype, &p) == SUCCESS)
2163 {
2164 /* We got a type. */
2165 if (typeinfo.defined & NTA_HASTYPE)
2166 {
2167 as_bad (_("can't redefine the type of a register alias"));
2168 return 0;
2169 }
5f4273c7 2170
dcbf9037
JB
2171 typeinfo.defined |= NTA_HASTYPE;
2172 if (ntype.elems != 1)
2173 {
2174 as_bad (_("you must specify a single type only"));
2175 return 0;
2176 }
2177 typeinfo.eltype = ntype.el[0];
2178 }
5f4273c7 2179
dcbf9037
JB
2180 if (skip_past_char (&p, '[') == SUCCESS)
2181 {
2182 expressionS exp;
2183 /* We got a scalar index. */
5f4273c7 2184
dcbf9037
JB
2185 if (typeinfo.defined & NTA_HASINDEX)
2186 {
2187 as_bad (_("can't redefine the index of a scalar alias"));
2188 return 0;
2189 }
5f4273c7 2190
dcbf9037 2191 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2192
dcbf9037
JB
2193 if (exp.X_op != O_constant)
2194 {
2195 as_bad (_("scalar index must be constant"));
2196 return 0;
2197 }
5f4273c7 2198
dcbf9037
JB
2199 typeinfo.defined |= NTA_HASINDEX;
2200 typeinfo.index = exp.X_add_number;
5f4273c7 2201
dcbf9037
JB
2202 if (skip_past_char (&p, ']') == FAIL)
2203 {
2204 as_bad (_("expecting ]"));
2205 return 0;
2206 }
2207 }
2208
2209 namelen = nameend - newname;
2210 namebuf = alloca (namelen + 1);
2211 strncpy (namebuf, newname, namelen);
2212 namebuf[namelen] = '\0';
5f4273c7 2213
dcbf9037
JB
2214 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2215 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2216
dcbf9037
JB
2217 /* Insert name in all uppercase. */
2218 for (p = namebuf; *p; p++)
2219 *p = TOUPPER (*p);
5f4273c7 2220
dcbf9037
JB
2221 if (strncmp (namebuf, newname, namelen))
2222 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2223 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2224
dcbf9037
JB
2225 /* Insert name in all lowercase. */
2226 for (p = namebuf; *p; p++)
2227 *p = TOLOWER (*p);
5f4273c7 2228
dcbf9037
JB
2229 if (strncmp (namebuf, newname, namelen))
2230 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2231 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2232
dcbf9037
JB
2233 return 1;
2234}
2235
c19d1205
ZW
2236/* Should never be called, as .req goes between the alias and the
2237 register name, not at the beginning of the line. */
b99bd4ef 2238static void
c19d1205 2239s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2240{
c19d1205
ZW
2241 as_bad (_("invalid syntax for .req directive"));
2242}
b99bd4ef 2243
dcbf9037
JB
2244static void
2245s_dn (int a ATTRIBUTE_UNUSED)
2246{
2247 as_bad (_("invalid syntax for .dn directive"));
2248}
2249
2250static void
2251s_qn (int a ATTRIBUTE_UNUSED)
2252{
2253 as_bad (_("invalid syntax for .qn directive"));
2254}
2255
c19d1205
ZW
2256/* The .unreq directive deletes an alias which was previously defined
2257 by .req. For example:
b99bd4ef 2258
c19d1205
ZW
2259 my_alias .req r11
2260 .unreq my_alias */
b99bd4ef
NC
2261
2262static void
c19d1205 2263s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2264{
c19d1205
ZW
2265 char * name;
2266 char saved_char;
b99bd4ef 2267
c19d1205
ZW
2268 name = input_line_pointer;
2269
2270 while (*input_line_pointer != 0
2271 && *input_line_pointer != ' '
2272 && *input_line_pointer != '\n')
2273 ++input_line_pointer;
2274
2275 saved_char = *input_line_pointer;
2276 *input_line_pointer = 0;
2277
2278 if (!*name)
2279 as_bad (_("invalid syntax for .unreq directive"));
2280 else
2281 {
2282 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2283
2284 if (!reg)
2285 as_bad (_("unknown register alias '%s'"), name);
2286 else if (reg->builtin)
2287 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2288 name);
2289 else
2290 {
d929913e
NC
2291 char * p;
2292 char * nbuf;
2293
db0bc284 2294 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2295 free ((char *) reg->name);
dcbf9037
JB
2296 if (reg->neon)
2297 free (reg->neon);
c19d1205 2298 free (reg);
d929913e
NC
2299
2300 /* Also locate the all upper case and all lower case versions.
2301 Do not complain if we cannot find one or the other as it
2302 was probably deleted above. */
5f4273c7 2303
d929913e
NC
2304 nbuf = strdup (name);
2305 for (p = nbuf; *p; p++)
2306 *p = TOUPPER (*p);
2307 reg = hash_find (arm_reg_hsh, nbuf);
2308 if (reg)
2309 {
db0bc284 2310 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC
2311 free ((char *) reg->name);
2312 if (reg->neon)
2313 free (reg->neon);
2314 free (reg);
2315 }
2316
2317 for (p = nbuf; *p; p++)
2318 *p = TOLOWER (*p);
2319 reg = hash_find (arm_reg_hsh, nbuf);
2320 if (reg)
2321 {
db0bc284 2322 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC
2323 free ((char *) reg->name);
2324 if (reg->neon)
2325 free (reg->neon);
2326 free (reg);
2327 }
2328
2329 free (nbuf);
c19d1205
ZW
2330 }
2331 }
b99bd4ef 2332
c19d1205 2333 *input_line_pointer = saved_char;
b99bd4ef
NC
2334 demand_empty_rest_of_line ();
2335}
2336
c19d1205
ZW
2337/* Directives: Instruction set selection. */
2338
2339#ifdef OBJ_ELF
2340/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2341 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2342 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2343 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2344
2345static enum mstate mapstate = MAP_UNDEFINED;
b99bd4ef 2346
e821645d 2347void
c19d1205 2348mapping_state (enum mstate state)
b99bd4ef 2349{
a737bd4d 2350 symbolS * symbolP;
c19d1205
ZW
2351 const char * symname;
2352 int type;
b99bd4ef 2353
c19d1205
ZW
2354 if (mapstate == state)
2355 /* The mapping symbol has already been emitted.
2356 There is nothing else to do. */
2357 return;
b99bd4ef 2358
c19d1205 2359 mapstate = state;
b99bd4ef 2360
c19d1205 2361 switch (state)
b99bd4ef 2362 {
c19d1205
ZW
2363 case MAP_DATA:
2364 symname = "$d";
2365 type = BSF_NO_FLAGS;
2366 break;
2367 case MAP_ARM:
2368 symname = "$a";
2369 type = BSF_NO_FLAGS;
2370 break;
2371 case MAP_THUMB:
2372 symname = "$t";
2373 type = BSF_NO_FLAGS;
2374 break;
2375 case MAP_UNDEFINED:
2376 return;
2377 default:
2378 abort ();
2379 }
2380
2381 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2382
2383 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
2384 symbol_table_insert (symbolP);
2385 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2386
2387 switch (state)
2388 {
2389 case MAP_ARM:
2390 THUMB_SET_FUNC (symbolP, 0);
2391 ARM_SET_THUMB (symbolP, 0);
2392 ARM_SET_INTERWORK (symbolP, support_interwork);
2393 break;
2394
2395 case MAP_THUMB:
2396 THUMB_SET_FUNC (symbolP, 1);
2397 ARM_SET_THUMB (symbolP, 1);
2398 ARM_SET_INTERWORK (symbolP, support_interwork);
2399 break;
2400
2401 case MAP_DATA:
2402 default:
2403 return;
2404 }
2405}
2406#else
2407#define mapping_state(x) /* nothing */
2408#endif
2409
2410/* Find the real, Thumb encoded start of a Thumb function. */
2411
2412static symbolS *
2413find_real_start (symbolS * symbolP)
2414{
2415 char * real_start;
2416 const char * name = S_GET_NAME (symbolP);
2417 symbolS * new_target;
2418
2419 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2420#define STUB_NAME ".real_start_of"
2421
2422 if (name == NULL)
2423 abort ();
2424
37f6032b
ZW
2425 /* The compiler may generate BL instructions to local labels because
2426 it needs to perform a branch to a far away location. These labels
2427 do not have a corresponding ".real_start_of" label. We check
2428 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2429 the ".real_start_of" convention for nonlocal branches. */
2430 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW
2431 return symbolP;
2432
37f6032b 2433 real_start = ACONCAT ((STUB_NAME, name, NULL));
c19d1205
ZW
2434 new_target = symbol_find (real_start);
2435
2436 if (new_target == NULL)
2437 {
bd3ba5d1 2438 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW
2439 new_target = symbolP;
2440 }
2441
c19d1205
ZW
2442 return new_target;
2443}
2444
2445static void
2446opcode_select (int width)
2447{
2448 switch (width)
2449 {
2450 case 16:
2451 if (! thumb_mode)
2452 {
e74cfd16 2453 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW
2454 as_bad (_("selected processor does not support THUMB opcodes"));
2455
2456 thumb_mode = 1;
2457 /* No need to force the alignment, since we will have been
2458 coming from ARM mode, which is word-aligned. */
2459 record_alignment (now_seg, 1);
2460 }
2461 mapping_state (MAP_THUMB);
2462 break;
2463
2464 case 32:
2465 if (thumb_mode)
2466 {
e74cfd16 2467 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW
2468 as_bad (_("selected processor does not support ARM opcodes"));
2469
2470 thumb_mode = 0;
2471
2472 if (!need_pass_2)
2473 frag_align (2, 0, 0);
2474
2475 record_alignment (now_seg, 1);
2476 }
2477 mapping_state (MAP_ARM);
2478 break;
2479
2480 default:
2481 as_bad (_("invalid instruction size selected (%d)"), width);
2482 }
2483}
2484
2485static void
2486s_arm (int ignore ATTRIBUTE_UNUSED)
2487{
2488 opcode_select (32);
2489 demand_empty_rest_of_line ();
2490}
2491
2492static void
2493s_thumb (int ignore ATTRIBUTE_UNUSED)
2494{
2495 opcode_select (16);
2496 demand_empty_rest_of_line ();
2497}
2498
2499static void
2500s_code (int unused ATTRIBUTE_UNUSED)
2501{
2502 int temp;
2503
2504 temp = get_absolute_expression ();
2505 switch (temp)
2506 {
2507 case 16:
2508 case 32:
2509 opcode_select (temp);
2510 break;
2511
2512 default:
2513 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2514 }
2515}
2516
2517static void
2518s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2519{
2520 /* If we are not already in thumb mode go into it, EVEN if
2521 the target processor does not support thumb instructions.
2522 This is used by gcc/config/arm/lib1funcs.asm for example
2523 to compile interworking support functions even if the
2524 target processor should not support interworking. */
2525 if (! thumb_mode)
2526 {
2527 thumb_mode = 2;
2528 record_alignment (now_seg, 1);
2529 }
2530
2531 demand_empty_rest_of_line ();
2532}
2533
2534static void
2535s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2536{
2537 s_thumb (0);
2538
2539 /* The following label is the name/address of the start of a Thumb function.
2540 We need to know this for the interworking support. */
2541 label_is_thumb_function_name = TRUE;
2542}
2543
2544/* Perform a .set directive, but also mark the alias as
2545 being a thumb function. */
2546
2547static void
2548s_thumb_set (int equiv)
2549{
2550 /* XXX the following is a duplicate of the code for s_set() in read.c
2551 We cannot just call that code as we need to get at the symbol that
2552 is created. */
2553 char * name;
2554 char delim;
2555 char * end_name;
2556 symbolS * symbolP;
2557
2558 /* Especial apologies for the random logic:
2559 This just grew, and could be parsed much more simply!
2560 Dean - in haste. */
2561 name = input_line_pointer;
2562 delim = get_symbol_end ();
2563 end_name = input_line_pointer;
2564 *end_name = delim;
2565
2566 if (*input_line_pointer != ',')
2567 {
2568 *end_name = 0;
2569 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC
2570 *end_name = delim;
2571 ignore_rest_of_line ();
2572 return;
2573 }
2574
2575 input_line_pointer++;
2576 *end_name = 0;
2577
2578 if (name[0] == '.' && name[1] == '\0')
2579 {
2580 /* XXX - this should not happen to .thumb_set. */
2581 abort ();
2582 }
2583
2584 if ((symbolP = symbol_find (name)) == NULL
2585 && (symbolP = md_undefined_symbol (name)) == NULL)
2586 {
2587#ifndef NO_LISTING
2588 /* When doing symbol listings, play games with dummy fragments living
2589 outside the normal fragment chain to record the file and line info
c19d1205 2590 for this symbol. */
b99bd4ef
NC
2591 if (listing & LISTING_SYMBOLS)
2592 {
2593 extern struct list_info_struct * listing_tail;
a737bd4d 2594 fragS * dummy_frag = xmalloc (sizeof (fragS));
b99bd4ef
NC
2595
2596 memset (dummy_frag, 0, sizeof (fragS));
2597 dummy_frag->fr_type = rs_fill;
2598 dummy_frag->line = listing_tail;
2599 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2600 dummy_frag->fr_symbol = symbolP;
2601 }
2602 else
2603#endif
2604 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2605
2606#ifdef OBJ_COFF
2607 /* "set" symbols are local unless otherwise specified. */
2608 SF_SET_LOCAL (symbolP);
2609#endif /* OBJ_COFF */
2610 } /* Make a new symbol. */
2611
2612 symbol_table_insert (symbolP);
2613
2614 * end_name = delim;
2615
2616 if (equiv
2617 && S_IS_DEFINED (symbolP)
2618 && S_GET_SEGMENT (symbolP) != reg_section)
2619 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2620
2621 pseudo_set (symbolP);
2622
2623 demand_empty_rest_of_line ();
2624
c19d1205 2625 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC
2626
2627 THUMB_SET_FUNC (symbolP, 1);
2628 ARM_SET_THUMB (symbolP, 1);
2629#if defined OBJ_ELF || defined OBJ_COFF
2630 ARM_SET_INTERWORK (symbolP, support_interwork);
2631#endif
2632}
2633
c19d1205 2634/* Directives: Mode selection. */
b99bd4ef 2635
c19d1205
ZW
2636/* .syntax [unified|divided] - choose the new unified syntax
2637 (same for Arm and Thumb encoding, modulo slight differences in what
2638 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 2639static void
c19d1205 2640s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2641{
c19d1205
ZW
2642 char *name, delim;
2643
2644 name = input_line_pointer;
2645 delim = get_symbol_end ();
2646
2647 if (!strcasecmp (name, "unified"))
2648 unified_syntax = TRUE;
2649 else if (!strcasecmp (name, "divided"))
2650 unified_syntax = FALSE;
2651 else
2652 {
2653 as_bad (_("unrecognized syntax mode \"%s\""), name);
2654 return;
2655 }
2656 *input_line_pointer = delim;
b99bd4ef
NC
2657 demand_empty_rest_of_line ();
2658}
2659
c19d1205
ZW
2660/* Directives: sectioning and alignment. */
2661
2662/* Same as s_align_ptwo but align 0 => align 2. */
2663
b99bd4ef 2664static void
c19d1205 2665s_align (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2666{
a737bd4d 2667 int temp;
dce323d1 2668 bfd_boolean fill_p;
c19d1205
ZW
2669 long temp_fill;
2670 long max_alignment = 15;
b99bd4ef
NC
2671
2672 temp = get_absolute_expression ();
c19d1205
ZW
2673 if (temp > max_alignment)
2674 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2675 else if (temp < 0)
b99bd4ef 2676 {
c19d1205
ZW
2677 as_bad (_("alignment negative. 0 assumed."));
2678 temp = 0;
2679 }
b99bd4ef 2680
c19d1205
ZW
2681 if (*input_line_pointer == ',')
2682 {
2683 input_line_pointer++;
2684 temp_fill = get_absolute_expression ();
dce323d1 2685 fill_p = TRUE;
b99bd4ef 2686 }
c19d1205 2687 else
dce323d1
PB
2688 {
2689 fill_p = FALSE;
2690 temp_fill = 0;
2691 }
b99bd4ef 2692
c19d1205
ZW
2693 if (!temp)
2694 temp = 2;
b99bd4ef 2695
c19d1205
ZW
2696 /* Only make a frag if we HAVE to. */
2697 if (temp && !need_pass_2)
dce323d1
PB
2698 {
2699 if (!fill_p && subseg_text_p (now_seg))
2700 frag_align_code (temp, 0);
2701 else
2702 frag_align (temp, (int) temp_fill, 0);
2703 }
c19d1205
ZW
2704 demand_empty_rest_of_line ();
2705
2706 record_alignment (now_seg, temp);
b99bd4ef
NC
2707}
2708
c19d1205
ZW
2709static void
2710s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 2711{
c19d1205
ZW
2712 /* We don't support putting frags in the BSS segment, we fake it by
2713 marking in_bss, then looking at s_skip for clues. */
2714 subseg_set (bss_section, 0);
2715 demand_empty_rest_of_line ();
2716 mapping_state (MAP_DATA);
2717}
b99bd4ef 2718
c19d1205
ZW
2719static void
2720s_even (int ignore ATTRIBUTE_UNUSED)
2721{
2722 /* Never make frag if expect extra pass. */
2723 if (!need_pass_2)
2724 frag_align (1, 0, 0);
b99bd4ef 2725
c19d1205 2726 record_alignment (now_seg, 1);
b99bd4ef 2727
c19d1205 2728 demand_empty_rest_of_line ();
b99bd4ef
NC
2729}
2730
c19d1205 2731/* Directives: Literal pools. */
a737bd4d 2732
c19d1205
ZW
2733static literal_pool *
2734find_literal_pool (void)
a737bd4d 2735{
c19d1205 2736 literal_pool * pool;
a737bd4d 2737
c19d1205 2738 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 2739 {
c19d1205
ZW
2740 if (pool->section == now_seg
2741 && pool->sub_section == now_subseg)
2742 break;
a737bd4d
NC
2743 }
2744
c19d1205 2745 return pool;
a737bd4d
NC
2746}
2747
c19d1205
ZW
2748static literal_pool *
2749find_or_make_literal_pool (void)
a737bd4d 2750{
c19d1205
ZW
2751 /* Next literal pool ID number. */
2752 static unsigned int latest_pool_num = 1;
2753 literal_pool * pool;
a737bd4d 2754
c19d1205 2755 pool = find_literal_pool ();
a737bd4d 2756
c19d1205 2757 if (pool == NULL)
a737bd4d 2758 {
c19d1205
ZW
2759 /* Create a new pool. */
2760 pool = xmalloc (sizeof (* pool));
2761 if (! pool)
2762 return NULL;
a737bd4d 2763
c19d1205
ZW
2764 pool->next_free_entry = 0;
2765 pool->section = now_seg;
2766 pool->sub_section = now_subseg;
2767 pool->next = list_of_pools;
2768 pool->symbol = NULL;
2769
2770 /* Add it to the list. */
2771 list_of_pools = pool;
a737bd4d 2772 }
a737bd4d 2773
c19d1205
ZW
2774 /* New pools, and emptied pools, will have a NULL symbol. */
2775 if (pool->symbol == NULL)
a737bd4d 2776 {
c19d1205
ZW
2777 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2778 (valueT) 0, &zero_address_frag);
2779 pool->id = latest_pool_num ++;
a737bd4d
NC
2780 }
2781
c19d1205
ZW
2782 /* Done. */
2783 return pool;
a737bd4d
NC
2784}
2785
c19d1205 2786/* Add the literal in the global 'inst'
5f4273c7 2787 structure to the relevant literal pool. */
b99bd4ef
NC
2788
2789static int
c19d1205 2790add_to_lit_pool (void)
b99bd4ef 2791{
c19d1205
ZW
2792 literal_pool * pool;
2793 unsigned int entry;
b99bd4ef 2794
c19d1205
ZW
2795 pool = find_or_make_literal_pool ();
2796
2797 /* Check if this literal value is already in the pool. */
2798 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 2799 {
c19d1205
ZW
2800 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2801 && (inst.reloc.exp.X_op == O_constant)
2802 && (pool->literals[entry].X_add_number
2803 == inst.reloc.exp.X_add_number)
2804 && (pool->literals[entry].X_unsigned
2805 == inst.reloc.exp.X_unsigned))
2806 break;
2807
2808 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2809 && (inst.reloc.exp.X_op == O_symbol)
2810 && (pool->literals[entry].X_add_number
2811 == inst.reloc.exp.X_add_number)
2812 && (pool->literals[entry].X_add_symbol
2813 == inst.reloc.exp.X_add_symbol)
2814 && (pool->literals[entry].X_op_symbol
2815 == inst.reloc.exp.X_op_symbol))
2816 break;
b99bd4ef
NC
2817 }
2818
c19d1205
ZW
2819 /* Do we need to create a new entry? */
2820 if (entry == pool->next_free_entry)
2821 {
2822 if (entry >= MAX_LITERAL_POOL_SIZE)
2823 {
2824 inst.error = _("literal pool overflow");
2825 return FAIL;
2826 }
2827
2828 pool->literals[entry] = inst.reloc.exp;
2829 pool->next_free_entry += 1;
2830 }
b99bd4ef 2831
c19d1205
ZW
2832 inst.reloc.exp.X_op = O_symbol;
2833 inst.reloc.exp.X_add_number = ((int) entry) * 4;
2834 inst.reloc.exp.X_add_symbol = pool->symbol;
b99bd4ef 2835
c19d1205 2836 return SUCCESS;
b99bd4ef
NC
2837}
2838
c19d1205
ZW
2839/* Can't use symbol_new here, so have to create a symbol and then at
2840 a later date assign it a value. Thats what these functions do. */
e16bb312 2841
c19d1205
ZW
2842static void
2843symbol_locate (symbolS * symbolP,
2844 const char * name, /* It is copied, the caller can modify. */
2845 segT segment, /* Segment identifier (SEG_<something>). */
2846 valueT valu, /* Symbol value. */
2847 fragS * frag) /* Associated fragment. */
2848{
2849 unsigned int name_length;
2850 char * preserved_copy_of_name;
e16bb312 2851
c19d1205
ZW
2852 name_length = strlen (name) + 1; /* +1 for \0. */
2853 obstack_grow (&notes, name, name_length);
2854 preserved_copy_of_name = obstack_finish (&notes);
e16bb312 2855
c19d1205
ZW
2856#ifdef tc_canonicalize_symbol_name
2857 preserved_copy_of_name =
2858 tc_canonicalize_symbol_name (preserved_copy_of_name);
2859#endif
b99bd4ef 2860
c19d1205 2861 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 2862
c19d1205
ZW
2863 S_SET_SEGMENT (symbolP, segment);
2864 S_SET_VALUE (symbolP, valu);
2865 symbol_clear_list_pointers (symbolP);
b99bd4ef 2866
c19d1205 2867 symbol_set_frag (symbolP, frag);
b99bd4ef 2868
c19d1205
ZW
2869 /* Link to end of symbol chain. */
2870 {
2871 extern int symbol_table_frozen;
b99bd4ef 2872
c19d1205
ZW
2873 if (symbol_table_frozen)
2874 abort ();
2875 }
b99bd4ef 2876
c19d1205 2877 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 2878
c19d1205 2879 obj_symbol_new_hook (symbolP);
b99bd4ef 2880
c19d1205
ZW
2881#ifdef tc_symbol_new_hook
2882 tc_symbol_new_hook (symbolP);
2883#endif
2884
2885#ifdef DEBUG_SYMS
2886 verify_symbol_chain (symbol_rootP, symbol_lastP);
2887#endif /* DEBUG_SYMS */
b99bd4ef
NC
2888}
2889
b99bd4ef 2890
c19d1205
ZW
2891static void
2892s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 2893{
c19d1205
ZW
2894 unsigned int entry;
2895 literal_pool * pool;
2896 char sym_name[20];
b99bd4ef 2897
c19d1205
ZW
2898 pool = find_literal_pool ();
2899 if (pool == NULL
2900 || pool->symbol == NULL
2901 || pool->next_free_entry == 0)
2902 return;
b99bd4ef 2903
c19d1205 2904 mapping_state (MAP_DATA);
b99bd4ef 2905
c19d1205
ZW
2906 /* Align pool as you have word accesses.
2907 Only make a frag if we have to. */
2908 if (!need_pass_2)
2909 frag_align (2, 0, 0);
b99bd4ef 2910
c19d1205 2911 record_alignment (now_seg, 2);
b99bd4ef 2912
c19d1205 2913 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 2914
c19d1205
ZW
2915 symbol_locate (pool->symbol, sym_name, now_seg,
2916 (valueT) frag_now_fix (), frag_now);
2917 symbol_table_insert (pool->symbol);
b99bd4ef 2918
c19d1205 2919 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 2920
c19d1205
ZW
2921#if defined OBJ_COFF || defined OBJ_ELF
2922 ARM_SET_INTERWORK (pool->symbol, support_interwork);
2923#endif
6c43fab6 2924
c19d1205
ZW
2925 for (entry = 0; entry < pool->next_free_entry; entry ++)
2926 /* First output the expression in the instruction to the pool. */
2927 emit_expr (&(pool->literals[entry]), 4); /* .word */
b99bd4ef 2928
c19d1205
ZW
2929 /* Mark the pool as empty. */
2930 pool->next_free_entry = 0;
2931 pool->symbol = NULL;
b99bd4ef
NC
2932}
2933
c19d1205
ZW
2934#ifdef OBJ_ELF
2935/* Forward declarations for functions below, in the MD interface
2936 section. */
2937static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2938static valueT create_unwind_entry (int);
2939static void start_unwind_section (const segT, int);
2940static void add_unwind_opcode (valueT, int);
2941static void flush_pending_unwind (void);
b99bd4ef 2942
c19d1205 2943/* Directives: Data. */
b99bd4ef 2944
c19d1205
ZW
2945static void
2946s_arm_elf_cons (int nbytes)
2947{
2948 expressionS exp;
b99bd4ef 2949
c19d1205
ZW
2950#ifdef md_flush_pending_output
2951 md_flush_pending_output ();
2952#endif
b99bd4ef 2953
c19d1205 2954 if (is_it_end_of_statement ())
b99bd4ef 2955 {
c19d1205
ZW
2956 demand_empty_rest_of_line ();
2957 return;
b99bd4ef
NC
2958 }
2959
c19d1205
ZW
2960#ifdef md_cons_align
2961 md_cons_align (nbytes);
2962#endif
b99bd4ef 2963
c19d1205
ZW
2964 mapping_state (MAP_DATA);
2965 do
b99bd4ef 2966 {
c19d1205
ZW
2967 int reloc;
2968 char *base = input_line_pointer;
b99bd4ef 2969
c19d1205 2970 expression (& exp);
b99bd4ef 2971
c19d1205
ZW
2972 if (exp.X_op != O_symbol)
2973 emit_expr (&exp, (unsigned int) nbytes);
2974 else
2975 {
2976 char *before_reloc = input_line_pointer;
2977 reloc = parse_reloc (&input_line_pointer);
2978 if (reloc == -1)
2979 {
2980 as_bad (_("unrecognized relocation suffix"));
2981 ignore_rest_of_line ();
2982 return;
2983 }
2984 else if (reloc == BFD_RELOC_UNUSED)
2985 emit_expr (&exp, (unsigned int) nbytes);
2986 else
2987 {
2988 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2989 int size = bfd_get_reloc_size (howto);
b99bd4ef 2990
2fc8bdac
ZW
2991 if (reloc == BFD_RELOC_ARM_PLT32)
2992 {
2993 as_bad (_("(plt) is only valid on branch targets"));
2994 reloc = BFD_RELOC_UNUSED;
2995 size = 0;
2996 }
2997
c19d1205 2998 if (size > nbytes)
2fc8bdac 2999 as_bad (_("%s relocations do not fit in %d bytes"),
c19d1205
ZW
3000 howto->name, nbytes);
3001 else
3002 {
3003 /* We've parsed an expression stopping at O_symbol.
3004 But there may be more expression left now that we
3005 have parsed the relocation marker. Parse it again.
3006 XXX Surely there is a cleaner way to do this. */
3007 char *p = input_line_pointer;
3008 int offset;
3009 char *save_buf = alloca (input_line_pointer - base);
3010 memcpy (save_buf, base, input_line_pointer - base);
3011 memmove (base + (input_line_pointer - before_reloc),
3012 base, before_reloc - base);
3013
3014 input_line_pointer = base + (input_line_pointer-before_reloc);
3015 expression (&exp);
3016 memcpy (base, save_buf, p - base);
3017
3018 offset = nbytes - size;
3019 p = frag_more ((int) nbytes);
3020 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3021 size, &exp, 0, reloc);
3022 }
3023 }
3024 }
b99bd4ef 3025 }
c19d1205 3026 while (*input_line_pointer++ == ',');
b99bd4ef 3027
c19d1205
ZW
3028 /* Put terminator back into stream. */
3029 input_line_pointer --;
3030 demand_empty_rest_of_line ();
b99bd4ef
NC
3031}
3032
b99bd4ef 3033
c19d1205 3034/* Parse a .rel31 directive. */
b99bd4ef 3035
c19d1205
ZW
3036static void
3037s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3038{
3039 expressionS exp;
3040 char *p;
3041 valueT highbit;
b99bd4ef 3042
c19d1205
ZW
3043 highbit = 0;
3044 if (*input_line_pointer == '1')
3045 highbit = 0x80000000;
3046 else if (*input_line_pointer != '0')
3047 as_bad (_("expected 0 or 1"));
b99bd4ef 3048
c19d1205
ZW
3049 input_line_pointer++;
3050 if (*input_line_pointer != ',')
3051 as_bad (_("missing comma"));
3052 input_line_pointer++;
b99bd4ef 3053
c19d1205
ZW
3054#ifdef md_flush_pending_output
3055 md_flush_pending_output ();
3056#endif
b99bd4ef 3057
c19d1205
ZW
3058#ifdef md_cons_align
3059 md_cons_align (4);
3060#endif
b99bd4ef 3061
c19d1205 3062 mapping_state (MAP_DATA);
b99bd4ef 3063
c19d1205 3064 expression (&exp);
b99bd4ef 3065
c19d1205
ZW
3066 p = frag_more (4);
3067 md_number_to_chars (p, highbit, 4);
3068 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3069 BFD_RELOC_ARM_PREL31);
b99bd4ef 3070
c19d1205 3071 demand_empty_rest_of_line ();
b99bd4ef
NC
3072}
3073
c19d1205 3074/* Directives: AEABI stack-unwind tables. */
b99bd4ef 3075
c19d1205 3076/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 3077
c19d1205
ZW
3078static void
3079s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3080{
3081 demand_empty_rest_of_line ();
3082 /* Mark the start of the function. */
3083 unwind.proc_start = expr_build_dot ();
b99bd4ef 3084
c19d1205
ZW
3085 /* Reset the rest of the unwind info. */
3086 unwind.opcode_count = 0;
3087 unwind.table_entry = NULL;
3088 unwind.personality_routine = NULL;
3089 unwind.personality_index = -1;
3090 unwind.frame_size = 0;
3091 unwind.fp_offset = 0;
3092 unwind.fp_reg = 13;
3093 unwind.fp_used = 0;
3094 unwind.sp_restored = 0;
3095}
b99bd4ef 3096
b99bd4ef 3097
c19d1205
ZW
3098/* Parse a handlerdata directive. Creates the exception handling table entry
3099 for the function. */
b99bd4ef 3100
c19d1205
ZW
3101static void
3102s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3103{
3104 demand_empty_rest_of_line ();
3105 if (unwind.table_entry)
6decc662 3106 as_bad (_("duplicate .handlerdata directive"));
f02232aa 3107
c19d1205
ZW
3108 create_unwind_entry (1);
3109}
a737bd4d 3110
c19d1205 3111/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 3112
c19d1205
ZW
3113static void
3114s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3115{
3116 long where;
3117 char *ptr;
3118 valueT val;
f02232aa 3119
c19d1205 3120 demand_empty_rest_of_line ();
f02232aa 3121
c19d1205
ZW
3122 /* Add eh table entry. */
3123 if (unwind.table_entry == NULL)
3124 val = create_unwind_entry (0);
3125 else
3126 val = 0;
f02232aa 3127
c19d1205
ZW
3128 /* Add index table entry. This is two words. */
3129 start_unwind_section (unwind.saved_seg, 1);
3130 frag_align (2, 0, 0);
3131 record_alignment (now_seg, 2);
b99bd4ef 3132
c19d1205
ZW
3133 ptr = frag_more (8);
3134 where = frag_now_fix () - 8;
f02232aa 3135
c19d1205
ZW
3136 /* Self relative offset of the function start. */
3137 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3138 BFD_RELOC_ARM_PREL31);
f02232aa 3139
c19d1205
ZW
3140 /* Indicate dependency on EHABI-defined personality routines to the
3141 linker, if it hasn't been done already. */
3142 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3143 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3144 {
5f4273c7
NC
3145 static const char *const name[] =
3146 {
3147 "__aeabi_unwind_cpp_pr0",
3148 "__aeabi_unwind_cpp_pr1",
3149 "__aeabi_unwind_cpp_pr2"
3150 };
c19d1205
ZW
3151 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3152 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3153 marked_pr_dependency |= 1 << unwind.personality_index;
3154 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3155 = marked_pr_dependency;
3156 }
f02232aa 3157
c19d1205
ZW
3158 if (val)
3159 /* Inline exception table entry. */
3160 md_number_to_chars (ptr + 4, val, 4);
3161 else
3162 /* Self relative offset of the table entry. */
3163 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3164 BFD_RELOC_ARM_PREL31);
f02232aa 3165
c19d1205
ZW
3166 /* Restore the original section. */
3167 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3168}
f02232aa 3169
f02232aa 3170
c19d1205 3171/* Parse an unwind_cantunwind directive. */
b99bd4ef 3172
c19d1205
ZW
3173static void
3174s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3175{
3176 demand_empty_rest_of_line ();
3177 if (unwind.personality_routine || unwind.personality_index != -1)
3178 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 3179
c19d1205
ZW
3180 unwind.personality_index = -2;
3181}
b99bd4ef 3182
b99bd4ef 3183
c19d1205 3184/* Parse a personalityindex directive. */
b99bd4ef 3185
c19d1205
ZW
3186static void
3187s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3188{
3189 expressionS exp;
b99bd4ef 3190
c19d1205
ZW
3191 if (unwind.personality_routine || unwind.personality_index != -1)
3192 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 3193
c19d1205 3194 expression (&exp);
b99bd4ef 3195
c19d1205
ZW
3196 if (exp.X_op != O_constant
3197 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 3198 {
c19d1205
ZW
3199 as_bad (_("bad personality routine number"));
3200 ignore_rest_of_line ();
3201 return;
b99bd4ef
NC
3202 }
3203
c19d1205 3204 unwind.personality_index = exp.X_add_number;
b99bd4ef 3205
c19d1205
ZW
3206 demand_empty_rest_of_line ();
3207}
e16bb312 3208
e16bb312 3209
c19d1205 3210/* Parse a personality directive. */
e16bb312 3211
c19d1205
ZW
3212static void
3213s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3214{
3215 char *name, *p, c;
a737bd4d 3216
c19d1205
ZW
3217 if (unwind.personality_routine || unwind.personality_index != -1)
3218 as_bad (_("duplicate .personality directive"));
a737bd4d 3219
c19d1205
ZW
3220 name = input_line_pointer;
3221 c = get_symbol_end ();
3222 p = input_line_pointer;
3223 unwind.personality_routine = symbol_find_or_make (name);
3224 *p = c;
3225 demand_empty_rest_of_line ();
3226}
e16bb312 3227
e16bb312 3228
c19d1205 3229/* Parse a directive saving core registers. */
e16bb312 3230
c19d1205
ZW
3231static void
3232s_arm_unwind_save_core (void)
e16bb312 3233{
c19d1205
ZW
3234 valueT op;
3235 long range;
3236 int n;
e16bb312 3237
c19d1205
ZW
3238 range = parse_reg_list (&input_line_pointer);
3239 if (range == FAIL)
e16bb312 3240 {
c19d1205
ZW
3241 as_bad (_("expected register list"));
3242 ignore_rest_of_line ();
3243 return;
3244 }
e16bb312 3245
c19d1205 3246 demand_empty_rest_of_line ();
e16bb312 3247
c19d1205
ZW
3248 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3249 into .unwind_save {..., sp...}. We aren't bothered about the value of
3250 ip because it is clobbered by calls. */
3251 if (unwind.sp_restored && unwind.fp_reg == 12
3252 && (range & 0x3000) == 0x1000)
3253 {
3254 unwind.opcode_count--;
3255 unwind.sp_restored = 0;
3256 range = (range | 0x2000) & ~0x1000;
3257 unwind.pending_offset = 0;
3258 }
e16bb312 3259
01ae4198
DJ
3260 /* Pop r4-r15. */
3261 if (range & 0xfff0)
c19d1205 3262 {
01ae4198
DJ
3263 /* See if we can use the short opcodes. These pop a block of up to 8
3264 registers starting with r4, plus maybe r14. */
3265 for (n = 0; n < 8; n++)
3266 {
3267 /* Break at the first non-saved register. */
3268 if ((range & (1 << (n + 4))) == 0)
3269 break;
3270 }
3271 /* See if there are any other bits set. */
3272 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3273 {
3274 /* Use the long form. */
3275 op = 0x8000 | ((range >> 4) & 0xfff);
3276 add_unwind_opcode (op, 2);
3277 }
0dd132b6 3278 else
01ae4198
DJ
3279 {
3280 /* Use the short form. */
3281 if (range & 0x4000)
3282 op = 0xa8; /* Pop r14. */
3283 else
3284 op = 0xa0; /* Do not pop r14. */
3285 op |= (n - 1);
3286 add_unwind_opcode (op, 1);
3287 }
c19d1205 3288 }
0dd132b6 3289
c19d1205
ZW
3290 /* Pop r0-r3. */
3291 if (range & 0xf)
3292 {
3293 op = 0xb100 | (range & 0xf);
3294 add_unwind_opcode (op, 2);
0dd132b6
NC
3295 }
3296
c19d1205
ZW
3297 /* Record the number of bytes pushed. */
3298 for (n = 0; n < 16; n++)
3299 {
3300 if (range & (1 << n))
3301 unwind.frame_size += 4;
3302 }
0dd132b6
NC
3303}
3304
c19d1205
ZW
3305
3306/* Parse a directive saving FPA registers. */
b99bd4ef
NC
3307
3308static void
c19d1205 3309s_arm_unwind_save_fpa (int reg)
b99bd4ef 3310{
c19d1205
ZW
3311 expressionS exp;
3312 int num_regs;
3313 valueT op;
b99bd4ef 3314
c19d1205
ZW
3315 /* Get Number of registers to transfer. */
3316 if (skip_past_comma (&input_line_pointer) != FAIL)
3317 expression (&exp);
3318 else
3319 exp.X_op = O_illegal;
b99bd4ef 3320
c19d1205 3321 if (exp.X_op != O_constant)
b99bd4ef 3322 {
c19d1205
ZW
3323 as_bad (_("expected , <constant>"));
3324 ignore_rest_of_line ();
b99bd4ef
NC
3325 return;
3326 }
3327
c19d1205
ZW
3328 num_regs = exp.X_add_number;
3329
3330 if (num_regs < 1 || num_regs > 4)
b99bd4ef 3331 {
c19d1205
ZW
3332 as_bad (_("number of registers must be in the range [1:4]"));
3333 ignore_rest_of_line ();
b99bd4ef
NC
3334 return;
3335 }
3336
c19d1205 3337 demand_empty_rest_of_line ();
b99bd4ef 3338
c19d1205
ZW
3339 if (reg == 4)
3340 {
3341 /* Short form. */
3342 op = 0xb4 | (num_regs - 1);
3343 add_unwind_opcode (op, 1);
3344 }
b99bd4ef
NC
3345 else
3346 {
c19d1205
ZW
3347 /* Long form. */
3348 op = 0xc800 | (reg << 4) | (num_regs - 1);
3349 add_unwind_opcode (op, 2);
b99bd4ef 3350 }
c19d1205 3351 unwind.frame_size += num_regs * 12;
b99bd4ef
NC
3352}
3353
c19d1205 3354
fa073d69
MS
3355/* Parse a directive saving VFP registers for ARMv6 and above. */
3356
3357static void
3358s_arm_unwind_save_vfp_armv6 (void)
3359{
3360 int count;
3361 unsigned int start;
3362 valueT op;
3363 int num_vfpv3_regs = 0;
3364 int num_regs_below_16;
3365
3366 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3367 if (count == FAIL)
3368 {
3369 as_bad (_("expected register list"));
3370 ignore_rest_of_line ();
3371 return;
3372 }
3373
3374 demand_empty_rest_of_line ();
3375
3376 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3377 than FSTMX/FLDMX-style ones). */
3378
3379 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3380 if (start >= 16)
3381 num_vfpv3_regs = count;
3382 else if (start + count > 16)
3383 num_vfpv3_regs = start + count - 16;
3384
3385 if (num_vfpv3_regs > 0)
3386 {
3387 int start_offset = start > 16 ? start - 16 : 0;
3388 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3389 add_unwind_opcode (op, 2);
3390 }
3391
3392 /* Generate opcode for registers numbered in the range 0 .. 15. */
3393 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3394 assert (num_regs_below_16 + num_vfpv3_regs == count);
3395 if (num_regs_below_16 > 0)
3396 {
3397 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3398 add_unwind_opcode (op, 2);
3399 }
3400
3401 unwind.frame_size += count * 8;
3402}
3403
3404
3405/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC
3406
3407static void
c19d1205 3408s_arm_unwind_save_vfp (void)
b99bd4ef 3409{
c19d1205 3410 int count;
ca3f61f7 3411 unsigned int reg;
c19d1205 3412 valueT op;
b99bd4ef 3413
5287ad62 3414 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
c19d1205 3415 if (count == FAIL)
b99bd4ef 3416 {
c19d1205
ZW
3417 as_bad (_("expected register list"));
3418 ignore_rest_of_line ();
b99bd4ef
NC
3419 return;
3420 }
3421
c19d1205 3422 demand_empty_rest_of_line ();
b99bd4ef 3423
c19d1205 3424 if (reg == 8)
b99bd4ef 3425 {
c19d1205
ZW
3426 /* Short form. */
3427 op = 0xb8 | (count - 1);
3428 add_unwind_opcode (op, 1);
b99bd4ef 3429 }
c19d1205 3430 else
b99bd4ef 3431 {
c19d1205
ZW
3432 /* Long form. */
3433 op = 0xb300 | (reg << 4) | (count - 1);
3434 add_unwind_opcode (op, 2);
b99bd4ef 3435 }
c19d1205
ZW
3436 unwind.frame_size += count * 8 + 4;
3437}
b99bd4ef 3438
b99bd4ef 3439
c19d1205
ZW
3440/* Parse a directive saving iWMMXt data registers. */
3441
3442static void
3443s_arm_unwind_save_mmxwr (void)
3444{
3445 int reg;
3446 int hi_reg;
3447 int i;
3448 unsigned mask = 0;
3449 valueT op;
b99bd4ef 3450
c19d1205
ZW
3451 if (*input_line_pointer == '{')
3452 input_line_pointer++;
b99bd4ef 3453
c19d1205 3454 do
b99bd4ef 3455 {
dcbf9037 3456 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 3457
c19d1205 3458 if (reg == FAIL)
b99bd4ef 3459 {
9b7132d3 3460 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 3461 goto error;
b99bd4ef
NC
3462 }
3463
c19d1205
ZW
3464 if (mask >> reg)
3465 as_tsktsk (_("register list not in ascending order"));
3466 mask |= 1 << reg;
b99bd4ef 3467
c19d1205
ZW
3468 if (*input_line_pointer == '-')
3469 {
3470 input_line_pointer++;
dcbf9037 3471 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW
3472 if (hi_reg == FAIL)
3473 {
9b7132d3 3474 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW
3475 goto error;
3476 }
3477 else if (reg >= hi_reg)
3478 {
3479 as_bad (_("bad register range"));
3480 goto error;
3481 }
3482 for (; reg < hi_reg; reg++)
3483 mask |= 1 << reg;
3484 }
3485 }
3486 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 3487
c19d1205
ZW
3488 if (*input_line_pointer == '}')
3489 input_line_pointer++;
b99bd4ef 3490
c19d1205 3491 demand_empty_rest_of_line ();
b99bd4ef 3492
708587a4 3493 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW
3494 the list. */
3495 flush_pending_unwind ();
b99bd4ef 3496
c19d1205 3497 for (i = 0; i < 16; i++)
b99bd4ef 3498 {
c19d1205
ZW
3499 if (mask & (1 << i))
3500 unwind.frame_size += 8;
b99bd4ef
NC
3501 }
3502
c19d1205
ZW
3503 /* Attempt to combine with a previous opcode. We do this because gcc
3504 likes to output separate unwind directives for a single block of
3505 registers. */
3506 if (unwind.opcode_count > 0)
b99bd4ef 3507 {
c19d1205
ZW
3508 i = unwind.opcodes[unwind.opcode_count - 1];
3509 if ((i & 0xf8) == 0xc0)
3510 {
3511 i &= 7;
3512 /* Only merge if the blocks are contiguous. */
3513 if (i < 6)
3514 {
3515 if ((mask & 0xfe00) == (1 << 9))
3516 {
3517 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3518 unwind.opcode_count--;
3519 }
3520 }
3521 else if (i == 6 && unwind.opcode_count >= 2)
3522 {
3523 i = unwind.opcodes[unwind.opcode_count - 2];
3524 reg = i >> 4;
3525 i &= 0xf;
b99bd4ef 3526
c19d1205
ZW
3527 op = 0xffff << (reg - 1);
3528 if (reg > 0
87a1fd79 3529 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW
3530 {
3531 op = (1 << (reg + i + 1)) - 1;
3532 op &= ~((1 << reg) - 1);
3533 mask |= op;
3534 unwind.opcode_count -= 2;
3535 }
3536 }
3537 }
b99bd4ef
NC
3538 }
3539
c19d1205
ZW
3540 hi_reg = 15;
3541 /* We want to generate opcodes in the order the registers have been
3542 saved, ie. descending order. */
3543 for (reg = 15; reg >= -1; reg--)
b99bd4ef 3544 {
c19d1205
ZW
3545 /* Save registers in blocks. */
3546 if (reg < 0
3547 || !(mask & (1 << reg)))
3548 {
3549 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 3550 preceding block. */
c19d1205
ZW
3551 if (reg != hi_reg)
3552 {
3553 if (reg == 9)
3554 {
3555 /* Short form. */
3556 op = 0xc0 | (hi_reg - 10);
3557 add_unwind_opcode (op, 1);
3558 }
3559 else
3560 {
3561 /* Long form. */
3562 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3563 add_unwind_opcode (op, 2);
3564 }
3565 }
3566 hi_reg = reg - 1;
3567 }
b99bd4ef
NC
3568 }
3569
c19d1205
ZW
3570 return;
3571error:
3572 ignore_rest_of_line ();
b99bd4ef
NC
3573}
3574
3575static void
c19d1205 3576s_arm_unwind_save_mmxwcg (void)
b99bd4ef 3577{
c19d1205
ZW
3578 int reg;
3579 int hi_reg;
3580 unsigned mask = 0;
3581 valueT op;
b99bd4ef 3582
c19d1205
ZW
3583 if (*input_line_pointer == '{')
3584 input_line_pointer++;
b99bd4ef 3585
c19d1205 3586 do
b99bd4ef 3587 {
dcbf9037 3588 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 3589
c19d1205
ZW
3590 if (reg == FAIL)
3591 {
9b7132d3 3592 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW
3593 goto error;
3594 }
b99bd4ef 3595
c19d1205
ZW
3596 reg -= 8;
3597 if (mask >> reg)
3598 as_tsktsk (_("register list not in ascending order"));
3599 mask |= 1 << reg;
b99bd4ef 3600
c19d1205
ZW
3601 if (*input_line_pointer == '-')
3602 {
3603 input_line_pointer++;
dcbf9037 3604 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW
3605 if (hi_reg == FAIL)
3606 {
9b7132d3 3607 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW
3608 goto error;
3609 }
3610 else if (reg >= hi_reg)
3611 {
3612 as_bad (_("bad register range"));
3613 goto error;
3614 }
3615 for (; reg < hi_reg; reg++)
3616 mask |= 1 << reg;
3617 }
b99bd4ef 3618 }
c19d1205 3619 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 3620
c19d1205
ZW
3621 if (*input_line_pointer == '}')
3622 input_line_pointer++;
b99bd4ef 3623
c19d1205
ZW
3624 demand_empty_rest_of_line ();
3625
708587a4 3626 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW
3627 the list. */
3628 flush_pending_unwind ();
b99bd4ef 3629
c19d1205 3630 for (reg = 0; reg < 16; reg++)
b99bd4ef 3631 {
c19d1205
ZW
3632 if (mask & (1 << reg))
3633 unwind.frame_size += 4;
b99bd4ef 3634 }
c19d1205
ZW
3635 op = 0xc700 | mask;
3636 add_unwind_opcode (op, 2);
3637 return;
3638error:
3639 ignore_rest_of_line ();
b99bd4ef
NC
3640}
3641
c19d1205 3642
fa073d69
MS
3643/* Parse an unwind_save directive.
3644 If the argument is non-zero, this is a .vsave directive. */
c19d1205 3645
b99bd4ef 3646static void
fa073d69 3647s_arm_unwind_save (int arch_v6)
b99bd4ef 3648{
c19d1205
ZW
3649 char *peek;
3650 struct reg_entry *reg;
3651 bfd_boolean had_brace = FALSE;
b99bd4ef 3652
c19d1205
ZW
3653 /* Figure out what sort of save we have. */
3654 peek = input_line_pointer;
b99bd4ef 3655
c19d1205 3656 if (*peek == '{')
b99bd4ef 3657 {
c19d1205
ZW
3658 had_brace = TRUE;
3659 peek++;
b99bd4ef
NC
3660 }
3661
c19d1205 3662 reg = arm_reg_parse_multi (&peek);
b99bd4ef 3663
c19d1205 3664 if (!reg)
b99bd4ef 3665 {
c19d1205
ZW
3666 as_bad (_("register expected"));
3667 ignore_rest_of_line ();
b99bd4ef
NC
3668 return;
3669 }
3670
c19d1205 3671 switch (reg->type)
b99bd4ef 3672 {
c19d1205
ZW
3673 case REG_TYPE_FN:
3674 if (had_brace)
3675 {
3676 as_bad (_("FPA .unwind_save does not take a register list"));
3677 ignore_rest_of_line ();
3678 return;
3679 }
93ac2687 3680 input_line_pointer = peek;
c19d1205 3681 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 3682 return;
c19d1205
ZW
3683
3684 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
fa073d69
MS
3685 case REG_TYPE_VFD:
3686 if (arch_v6)
3687 s_arm_unwind_save_vfp_armv6 ();
3688 else
3689 s_arm_unwind_save_vfp ();
3690 return;
c19d1205
ZW
3691 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
3692 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
3693
3694 default:
3695 as_bad (_(".unwind_save does not support this kind of register"));
3696 ignore_rest_of_line ();
b99bd4ef 3697 }
c19d1205 3698}
b99bd4ef 3699
b99bd4ef 3700
c19d1205
ZW
3701/* Parse an unwind_movsp directive. */
3702
3703static void
3704s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
3705{
3706 int reg;
3707 valueT op;
4fa3602b 3708 int offset;
c19d1205 3709
dcbf9037 3710 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 3711 if (reg == FAIL)
b99bd4ef 3712 {
9b7132d3 3713 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 3714 ignore_rest_of_line ();
b99bd4ef
NC
3715 return;
3716 }
4fa3602b
PB
3717
3718 /* Optional constant. */
3719 if (skip_past_comma (&input_line_pointer) != FAIL)
3720 {
3721 if (immediate_for_directive (&offset) == FAIL)
3722 return;
3723 }
3724 else
3725 offset = 0;
3726
c19d1205 3727 demand_empty_rest_of_line ();
b99bd4ef 3728
c19d1205 3729 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 3730 {
c19d1205 3731 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC
3732 return;
3733 }
3734
c19d1205
ZW
3735 if (unwind.fp_reg != REG_SP)
3736 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 3737
c19d1205
ZW
3738 /* Generate opcode to restore the value. */
3739 op = 0x90 | reg;
3740 add_unwind_opcode (op, 1);
3741
3742 /* Record the information for later. */
3743 unwind.fp_reg = reg;
4fa3602b 3744 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 3745 unwind.sp_restored = 1;
b05fe5cf
ZW
3746}
3747
c19d1205
ZW
3748/* Parse an unwind_pad directive. */
3749
b05fe5cf 3750static void
c19d1205 3751s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 3752{
c19d1205 3753 int offset;
b05fe5cf 3754
c19d1205
ZW
3755 if (immediate_for_directive (&offset) == FAIL)
3756 return;
b99bd4ef 3757
c19d1205
ZW
3758 if (offset & 3)
3759 {
3760 as_bad (_("stack increment must be multiple of 4"));
3761 ignore_rest_of_line ();
3762 return;
3763 }
b99bd4ef 3764
c19d1205
ZW
3765 /* Don't generate any opcodes, just record the details for later. */
3766 unwind.frame_size += offset;
3767 unwind.pending_offset += offset;
3768
3769 demand_empty_rest_of_line ();
3770}
3771
3772/* Parse an unwind_setfp directive. */
3773
3774static void
3775s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3776{
c19d1205
ZW
3777 int sp_reg;
3778 int fp_reg;
3779 int offset;
3780
dcbf9037 3781 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW
3782 if (skip_past_comma (&input_line_pointer) == FAIL)
3783 sp_reg = FAIL;
3784 else
dcbf9037 3785 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 3786
c19d1205
ZW
3787 if (fp_reg == FAIL || sp_reg == FAIL)
3788 {
3789 as_bad (_("expected <reg>, <reg>"));
3790 ignore_rest_of_line ();
3791 return;
3792 }
b99bd4ef 3793
c19d1205
ZW
3794 /* Optional constant. */
3795 if (skip_past_comma (&input_line_pointer) != FAIL)
3796 {
3797 if (immediate_for_directive (&offset) == FAIL)
3798 return;
3799 }
3800 else
3801 offset = 0;
a737bd4d 3802
c19d1205 3803 demand_empty_rest_of_line ();
a737bd4d 3804
c19d1205 3805 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
a737bd4d 3806 {
c19d1205
ZW
3807 as_bad (_("register must be either sp or set by a previous"
3808 "unwind_movsp directive"));
3809 return;
a737bd4d
NC
3810 }
3811
c19d1205
ZW
3812 /* Don't generate any opcodes, just record the information for later. */
3813 unwind.fp_reg = fp_reg;
3814 unwind.fp_used = 1;
3815 if (sp_reg == 13)
3816 unwind.fp_offset = unwind.frame_size - offset;
3817 else
3818 unwind.fp_offset -= offset;
a737bd4d
NC
3819}
3820
c19d1205
ZW
3821/* Parse an unwind_raw directive. */
3822
3823static void
3824s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 3825{
c19d1205 3826 expressionS exp;
708587a4 3827 /* This is an arbitrary limit. */
c19d1205
ZW
3828 unsigned char op[16];
3829 int count;
a737bd4d 3830
c19d1205
ZW
3831 expression (&exp);
3832 if (exp.X_op == O_constant
3833 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 3834 {
c19d1205
ZW
3835 unwind.frame_size += exp.X_add_number;
3836 expression (&exp);
3837 }
3838 else
3839 exp.X_op = O_illegal;
a737bd4d 3840
c19d1205
ZW
3841 if (exp.X_op != O_constant)
3842 {
3843 as_bad (_("expected <offset>, <opcode>"));
3844 ignore_rest_of_line ();
3845 return;
3846 }
a737bd4d 3847
c19d1205 3848 count = 0;
a737bd4d 3849
c19d1205
ZW
3850 /* Parse the opcode. */
3851 for (;;)
3852 {
3853 if (count >= 16)
3854 {
3855 as_bad (_("unwind opcode too long"));
3856 ignore_rest_of_line ();
a737bd4d 3857 }
c19d1205 3858 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 3859 {
c19d1205
ZW
3860 as_bad (_("invalid unwind opcode"));
3861 ignore_rest_of_line ();
3862 return;
a737bd4d 3863 }
c19d1205 3864 op[count++] = exp.X_add_number;
a737bd4d 3865
c19d1205
ZW
3866 /* Parse the next byte. */
3867 if (skip_past_comma (&input_line_pointer) == FAIL)
3868 break;
a737bd4d 3869
c19d1205
ZW
3870 expression (&exp);
3871 }
b99bd4ef 3872
c19d1205
ZW
3873 /* Add the opcode bytes in reverse order. */
3874 while (count--)
3875 add_unwind_opcode (op[count], 1);
b99bd4ef 3876
c19d1205 3877 demand_empty_rest_of_line ();
b99bd4ef 3878}
ee065d83
PB
3879
3880
3881/* Parse a .eabi_attribute directive. */
3882
3883static void
3884s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
3885{
104d59d1 3886 s_vendor_attribute (OBJ_ATTR_PROC);
ee065d83 3887}
8463be01 3888#endif /* OBJ_ELF */
ee065d83
PB
3889
3890static void s_arm_arch (int);
7a1d4c38 3891static void s_arm_object_arch (int);
ee065d83
PB
3892static void s_arm_cpu (int);
3893static void s_arm_fpu (int);
b99bd4ef 3894
f0927246
NC
3895#ifdef TE_PE
3896
3897static void
5f4273c7 3898pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC
3899{
3900 expressionS exp;
3901
3902 do
3903 {
3904 expression (&exp);
3905 if (exp.X_op == O_symbol)
3906 exp.X_op = O_secrel;
3907
3908 emit_expr (&exp, 4);
3909 }
3910 while (*input_line_pointer++ == ',');
3911
3912 input_line_pointer--;
3913 demand_empty_rest_of_line ();
3914}
3915#endif /* TE_PE */
3916
c19d1205
ZW
3917/* This table describes all the machine specific pseudo-ops the assembler
3918 has to support. The fields are:
3919 pseudo-op name without dot
3920 function to call to execute this pseudo-op
3921 Integer arg to pass to the function. */
b99bd4ef 3922
c19d1205 3923const pseudo_typeS md_pseudo_table[] =
b99bd4ef 3924{
c19d1205
ZW
3925 /* Never called because '.req' does not start a line. */
3926 { "req", s_req, 0 },
dcbf9037
JB
3927 /* Following two are likewise never called. */
3928 { "dn", s_dn, 0 },
3929 { "qn", s_qn, 0 },
c19d1205
ZW
3930 { "unreq", s_unreq, 0 },
3931 { "bss", s_bss, 0 },
3932 { "align", s_align, 0 },
3933 { "arm", s_arm, 0 },
3934 { "thumb", s_thumb, 0 },
3935 { "code", s_code, 0 },
3936 { "force_thumb", s_force_thumb, 0 },
3937 { "thumb_func", s_thumb_func, 0 },
3938 { "thumb_set", s_thumb_set, 0 },
3939 { "even", s_even, 0 },
3940 { "ltorg", s_ltorg, 0 },
3941 { "pool", s_ltorg, 0 },
3942 { "syntax", s_syntax, 0 },
8463be01
PB
3943 { "cpu", s_arm_cpu, 0 },
3944 { "arch", s_arm_arch, 0 },
7a1d4c38 3945 { "object_arch", s_arm_object_arch, 0 },
8463be01 3946 { "fpu", s_arm_fpu, 0 },
c19d1205
ZW
3947#ifdef OBJ_ELF
3948 { "word", s_arm_elf_cons, 4 },
3949 { "long", s_arm_elf_cons, 4 },
3950 { "rel31", s_arm_rel31, 0 },
3951 { "fnstart", s_arm_unwind_fnstart, 0 },
3952 { "fnend", s_arm_unwind_fnend, 0 },
3953 { "cantunwind", s_arm_unwind_cantunwind, 0 },
3954 { "personality", s_arm_unwind_personality, 0 },
3955 { "personalityindex", s_arm_unwind_personalityindex, 0 },
3956 { "handlerdata", s_arm_unwind_handlerdata, 0 },
3957 { "save", s_arm_unwind_save, 0 },
fa073d69 3958 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW
3959 { "movsp", s_arm_unwind_movsp, 0 },
3960 { "pad", s_arm_unwind_pad, 0 },
3961 { "setfp", s_arm_unwind_setfp, 0 },
3962 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 3963 { "eabi_attribute", s_arm_eabi_attribute, 0 },
c19d1205
ZW
3964#else
3965 { "word", cons, 4},
f0927246
NC
3966
3967 /* These are used for dwarf. */
3968 {"2byte", cons, 2},
3969 {"4byte", cons, 4},
3970 {"8byte", cons, 8},
3971 /* These are used for dwarf2. */
3972 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
3973 { "loc", dwarf2_directive_loc, 0 },
3974 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW
3975#endif
3976 { "extend", float_cons, 'x' },
3977 { "ldouble", float_cons, 'x' },
3978 { "packed", float_cons, 'p' },
f0927246
NC
3979#ifdef TE_PE
3980 {"secrel32", pe_directive_secrel, 0},
3981#endif
c19d1205
ZW
3982 { 0, 0, 0 }
3983};
3984\f
3985/* Parser functions used exclusively in instruction operands. */
b99bd4ef 3986
c19d1205
ZW
3987/* Generic immediate-value read function for use in insn parsing.
3988 STR points to the beginning of the immediate (the leading #);
3989 VAL receives the value; if the value is outside [MIN, MAX]
3990 issue an error. PREFIX_OPT is true if the immediate prefix is
3991 optional. */
b99bd4ef 3992
c19d1205
ZW
3993static int
3994parse_immediate (char **str, int *val, int min, int max,
3995 bfd_boolean prefix_opt)
3996{
3997 expressionS exp;
3998 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3999 if (exp.X_op != O_constant)
b99bd4ef 4000 {
c19d1205
ZW
4001 inst.error = _("constant expression required");
4002 return FAIL;
4003 }
b99bd4ef 4004
c19d1205
ZW
4005 if (exp.X_add_number < min || exp.X_add_number > max)
4006 {
4007 inst.error = _("immediate value out of range");
4008 return FAIL;
4009 }
b99bd4ef 4010
c19d1205
ZW
4011 *val = exp.X_add_number;
4012 return SUCCESS;
4013}
b99bd4ef 4014
5287ad62 4015/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 4016 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB
4017 instructions. Puts the result directly in inst.operands[i]. */
4018
4019static int
4020parse_big_immediate (char **str, int i)
4021{
4022 expressionS exp;
4023 char *ptr = *str;
4024
4025 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4026
4027 if (exp.X_op == O_constant)
036dc3f7
PB
4028 {
4029 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4030 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4031 O_constant. We have to be careful not to break compilation for
4032 32-bit X_add_number, though. */
4033 if ((exp.X_add_number & ~0xffffffffl) != 0)
4034 {
4035 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4036 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4037 inst.operands[i].regisimm = 1;
4038 }
4039 }
5287ad62
JB
4040 else if (exp.X_op == O_big
4041 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
4042 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
4043 {
4044 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4045 /* Bignums have their least significant bits in
4046 generic_bignum[0]. Make sure we put 32 bits in imm and
4047 32 bits in reg, in a (hopefully) portable way. */
4048 assert (parts != 0);
4049 inst.operands[i].imm = 0;
4050 for (j = 0; j < parts; j++, idx++)
4051 inst.operands[i].imm |= generic_bignum[idx]
4052 << (LITTLENUM_NUMBER_OF_BITS * j);
4053 inst.operands[i].reg = 0;
4054 for (j = 0; j < parts; j++, idx++)
4055 inst.operands[i].reg |= generic_bignum[idx]
4056 << (LITTLENUM_NUMBER_OF_BITS * j);
4057 inst.operands[i].regisimm = 1;
4058 }
4059 else
4060 return FAIL;
5f4273c7 4061
5287ad62
JB
4062 *str = ptr;
4063
4064 return SUCCESS;
4065}
4066
c19d1205
ZW
4067/* Returns the pseudo-register number of an FPA immediate constant,
4068 or FAIL if there isn't a valid constant here. */
b99bd4ef 4069
c19d1205
ZW
4070static int
4071parse_fpa_immediate (char ** str)
4072{
4073 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4074 char * save_in;
4075 expressionS exp;
4076 int i;
4077 int j;
b99bd4ef 4078
c19d1205
ZW
4079 /* First try and match exact strings, this is to guarantee
4080 that some formats will work even for cross assembly. */
b99bd4ef 4081
c19d1205
ZW
4082 for (i = 0; fp_const[i]; i++)
4083 {
4084 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 4085 {
c19d1205 4086 char *start = *str;
b99bd4ef 4087
c19d1205
ZW
4088 *str += strlen (fp_const[i]);
4089 if (is_end_of_line[(unsigned char) **str])
4090 return i + 8;
4091 *str = start;
4092 }
4093 }
b99bd4ef 4094
c19d1205
ZW
4095 /* Just because we didn't get a match doesn't mean that the constant
4096 isn't valid, just that it is in a format that we don't
4097 automatically recognize. Try parsing it with the standard
4098 expression routines. */
b99bd4ef 4099
c19d1205 4100 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 4101
c19d1205
ZW
4102 /* Look for a raw floating point number. */
4103 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4104 && is_end_of_line[(unsigned char) *save_in])
4105 {
4106 for (i = 0; i < NUM_FLOAT_VALS; i++)
4107 {
4108 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 4109 {
c19d1205
ZW
4110 if (words[j] != fp_values[i][j])
4111 break;
b99bd4ef
NC
4112 }
4113
c19d1205 4114 if (j == MAX_LITTLENUMS)
b99bd4ef 4115 {
c19d1205
ZW
4116 *str = save_in;
4117 return i + 8;
b99bd4ef
NC
4118 }
4119 }
4120 }
b99bd4ef 4121
c19d1205
ZW
4122 /* Try and parse a more complex expression, this will probably fail
4123 unless the code uses a floating point prefix (eg "0f"). */
4124 save_in = input_line_pointer;
4125 input_line_pointer = *str;
4126 if (expression (&exp) == absolute_section
4127 && exp.X_op == O_big
4128 && exp.X_add_number < 0)
4129 {
4130 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4131 Ditto for 15. */
4132 if (gen_to_words (words, 5, (long) 15) == 0)
4133 {
4134 for (i = 0; i < NUM_FLOAT_VALS; i++)
4135 {
4136 for (j = 0; j < MAX_LITTLENUMS; j++)
4137 {
4138 if (words[j] != fp_values[i][j])
4139 break;
4140 }
b99bd4ef 4141
c19d1205
ZW
4142 if (j == MAX_LITTLENUMS)
4143 {
4144 *str = input_line_pointer;
4145 input_line_pointer = save_in;
4146 return i + 8;
4147 }
4148 }
4149 }
b99bd4ef
NC
4150 }
4151
c19d1205
ZW
4152 *str = input_line_pointer;
4153 input_line_pointer = save_in;
4154 inst.error = _("invalid FPA immediate expression");
4155 return FAIL;
b99bd4ef
NC
4156}
4157
136da414
JB
4158/* Returns 1 if a number has "quarter-precision" float format
4159 0baBbbbbbc defgh000 00000000 00000000. */
4160
4161static int
4162is_quarter_float (unsigned imm)
4163{
4164 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4165 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4166}
4167
4168/* Parse an 8-bit "quarter-precision" floating point number of the form:
4169 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB
4170 The zero and minus-zero cases need special handling, since they can't be
4171 encoded in the "quarter-precision" float format, but can nonetheless be
4172 loaded as integer constants. */
136da414
JB
4173
4174static unsigned
4175parse_qfloat_immediate (char **ccp, int *immed)
4176{
4177 char *str = *ccp;
c96612cc 4178 char *fpnum;
136da414 4179 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 4180 int found_fpchar = 0;
5f4273c7 4181
136da414 4182 skip_past_char (&str, '#');
5f4273c7 4183
c96612cc
JB
4184 /* We must not accidentally parse an integer as a floating-point number. Make
4185 sure that the value we parse is not an integer by checking for special
4186 characters '.' or 'e'.
4187 FIXME: This is a horrible hack, but doing better is tricky because type
4188 information isn't in a very usable state at parse time. */
4189 fpnum = str;
4190 skip_whitespace (fpnum);
4191
4192 if (strncmp (fpnum, "0x", 2) == 0)
4193 return FAIL;
4194 else
4195 {
4196 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4197 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4198 {
4199 found_fpchar = 1;
4200 break;
4201 }
4202
4203 if (!found_fpchar)
4204 return FAIL;
4205 }
5f4273c7 4206
136da414
JB
4207 if ((str = atof_ieee (str, 's', words)) != NULL)
4208 {
4209 unsigned fpword = 0;
4210 int i;
5f4273c7 4211
136da414
JB
4212 /* Our FP word must be 32 bits (single-precision FP). */
4213 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4214 {
4215 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4216 fpword |= words[i];
4217 }
5f4273c7 4218
c96612cc 4219 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
136da414
JB
4220 *immed = fpword;
4221 else
4222 return FAIL;
4223
4224 *ccp = str;
5f4273c7 4225
136da414
JB
4226 return SUCCESS;
4227 }
5f4273c7 4228
136da414
JB
4229 return FAIL;
4230}
4231
c19d1205
ZW
4232/* Shift operands. */
4233enum shift_kind
b99bd4ef 4234{
c19d1205
ZW
4235 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4236};
b99bd4ef 4237
c19d1205
ZW
4238struct asm_shift_name
4239{
4240 const char *name;
4241 enum shift_kind kind;
4242};
b99bd4ef 4243
c19d1205
ZW
4244/* Third argument to parse_shift. */
4245enum parse_shift_mode
4246{
4247 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4248 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4249 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4250 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4251 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4252};
b99bd4ef 4253
c19d1205
ZW
4254/* Parse a <shift> specifier on an ARM data processing instruction.
4255 This has three forms:
b99bd4ef 4256
c19d1205
ZW
4257 (LSL|LSR|ASL|ASR|ROR) Rs
4258 (LSL|LSR|ASL|ASR|ROR) #imm
4259 RRX
b99bd4ef 4260
c19d1205
ZW
4261 Note that ASL is assimilated to LSL in the instruction encoding, and
4262 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 4263
c19d1205
ZW
4264static int
4265parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 4266{
c19d1205
ZW
4267 const struct asm_shift_name *shift_name;
4268 enum shift_kind shift;
4269 char *s = *str;
4270 char *p = s;
4271 int reg;
b99bd4ef 4272
c19d1205
ZW
4273 for (p = *str; ISALPHA (*p); p++)
4274 ;
b99bd4ef 4275
c19d1205 4276 if (p == *str)
b99bd4ef 4277 {
c19d1205
ZW
4278 inst.error = _("shift expression expected");
4279 return FAIL;
b99bd4ef
NC
4280 }
4281
c19d1205
ZW
4282 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
4283
4284 if (shift_name == NULL)
b99bd4ef 4285 {
c19d1205
ZW
4286 inst.error = _("shift expression expected");
4287 return FAIL;
b99bd4ef
NC
4288 }
4289
c19d1205 4290 shift = shift_name->kind;
b99bd4ef 4291
c19d1205
ZW
4292 switch (mode)
4293 {
4294 case NO_SHIFT_RESTRICT:
4295 case SHIFT_IMMEDIATE: break;
b99bd4ef 4296
c19d1205
ZW
4297 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4298 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4299 {
4300 inst.error = _("'LSL' or 'ASR' required");
4301 return FAIL;
4302 }
4303 break;
b99bd4ef 4304
c19d1205
ZW
4305 case SHIFT_LSL_IMMEDIATE:
4306 if (shift != SHIFT_LSL)
4307 {
4308 inst.error = _("'LSL' required");
4309 return FAIL;
4310 }
4311 break;
b99bd4ef 4312
c19d1205
ZW
4313 case SHIFT_ASR_IMMEDIATE:
4314 if (shift != SHIFT_ASR)
4315 {
4316 inst.error = _("'ASR' required");
4317 return FAIL;
4318 }
4319 break;
b99bd4ef 4320
c19d1205
ZW
4321 default: abort ();
4322 }
b99bd4ef 4323
c19d1205
ZW
4324 if (shift != SHIFT_RRX)
4325 {
4326 /* Whitespace can appear here if the next thing is a bare digit. */
4327 skip_whitespace (p);
b99bd4ef 4328
c19d1205 4329 if (mode == NO_SHIFT_RESTRICT
dcbf9037 4330 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW
4331 {
4332 inst.operands[i].imm = reg;
4333 inst.operands[i].immisreg = 1;
4334 }
4335 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4336 return FAIL;
4337 }
4338 inst.operands[i].shift_kind = shift;
4339 inst.operands[i].shifted = 1;
4340 *str = p;
4341 return SUCCESS;
b99bd4ef
NC
4342}
4343
c19d1205 4344/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 4345
c19d1205
ZW
4346 #<immediate>
4347 #<immediate>, <rotate>
4348 <Rm>
4349 <Rm>, <shift>
b99bd4ef 4350
c19d1205
ZW
4351 where <shift> is defined by parse_shift above, and <rotate> is a
4352 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 4353 is deferred to md_apply_fix. */
b99bd4ef 4354
c19d1205
ZW
4355static int
4356parse_shifter_operand (char **str, int i)
4357{
4358 int value;
4359 expressionS expr;
b99bd4ef 4360
dcbf9037 4361 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW
4362 {
4363 inst.operands[i].reg = value;
4364 inst.operands[i].isreg = 1;
b99bd4ef 4365
c19d1205
ZW
4366 /* parse_shift will override this if appropriate */
4367 inst.reloc.exp.X_op = O_constant;
4368 inst.reloc.exp.X_add_number = 0;
b99bd4ef 4369
c19d1205
ZW
4370 if (skip_past_comma (str) == FAIL)
4371 return SUCCESS;
b99bd4ef 4372
c19d1205
ZW
4373 /* Shift operation on register. */
4374 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC
4375 }
4376
c19d1205
ZW
4377 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4378 return FAIL;
b99bd4ef 4379
c19d1205 4380 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 4381 {
c19d1205
ZW
4382 /* #x, y -- ie explicit rotation by Y. */
4383 if (my_get_expression (&expr, str, GE_NO_PREFIX))
4384 return FAIL;
b99bd4ef 4385
c19d1205
ZW
4386 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4387 {
4388 inst.error = _("constant expression expected");
4389 return FAIL;
4390 }
b99bd4ef 4391
c19d1205
ZW
4392 value = expr.X_add_number;
4393 if (value < 0 || value > 30 || value % 2 != 0)
4394 {
4395 inst.error = _("invalid rotation");
4396 return FAIL;
4397 }
4398 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4399 {
4400 inst.error = _("invalid constant");
4401 return FAIL;
4402 }
09d92015 4403
55cf6793 4404 /* Convert to decoded value. md_apply_fix will put it back. */
c19d1205
ZW
4405 inst.reloc.exp.X_add_number
4406 = (((inst.reloc.exp.X_add_number << (32 - value))
4407 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
09d92015
MM
4408 }
4409
c19d1205
ZW
4410 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4411 inst.reloc.pc_rel = 0;
4412 return SUCCESS;
09d92015
MM
4413}
4414
4962c51a
MS
4415/* Group relocation information. Each entry in the table contains the
4416 textual name of the relocation as may appear in assembler source
4417 and must end with a colon.
4418 Along with this textual name are the relocation codes to be used if
4419 the corresponding instruction is an ALU instruction (ADD or SUB only),
4420 an LDR, an LDRS, or an LDC. */
4421
4422struct group_reloc_table_entry
4423{
4424 const char *name;
4425 int alu_code;
4426 int ldr_code;
4427 int ldrs_code;
4428 int ldc_code;
4429};
4430
4431typedef enum
4432{
4433 /* Varieties of non-ALU group relocation. */
4434
4435 GROUP_LDR,
4436 GROUP_LDRS,
4437 GROUP_LDC
4438} group_reloc_type;
4439
4440static struct group_reloc_table_entry group_reloc_table[] =
4441 { /* Program counter relative: */
4442 { "pc_g0_nc",
4443 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4444 0, /* LDR */
4445 0, /* LDRS */
4446 0 }, /* LDC */
4447 { "pc_g0",
4448 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4449 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4450 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4451 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4452 { "pc_g1_nc",
4453 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4454 0, /* LDR */
4455 0, /* LDRS */
4456 0 }, /* LDC */
4457 { "pc_g1",
4458 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4459 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4460 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4461 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4462 { "pc_g2",
4463 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4464 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4465 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4466 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4467 /* Section base relative */
4468 { "sb_g0_nc",
4469 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4470 0, /* LDR */
4471 0, /* LDRS */
4472 0 }, /* LDC */
4473 { "sb_g0",
4474 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4475 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4476 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4477 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4478 { "sb_g1_nc",
4479 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4480 0, /* LDR */
4481 0, /* LDRS */
4482 0 }, /* LDC */
4483 { "sb_g1",
4484 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4485 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4486 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4487 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4488 { "sb_g2",
4489 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4490 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4491 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4492 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4493
4494/* Given the address of a pointer pointing to the textual name of a group
4495 relocation as may appear in assembler source, attempt to find its details
4496 in group_reloc_table. The pointer will be updated to the character after
4497 the trailing colon. On failure, FAIL will be returned; SUCCESS
4498 otherwise. On success, *entry will be updated to point at the relevant
4499 group_reloc_table entry. */
4500
4501static int
4502find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4503{
4504 unsigned int i;
4505 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4506 {
4507 int length = strlen (group_reloc_table[i].name);
4508
5f4273c7
NC
4509 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4510 && (*str)[length] == ':')
4962c51a
MS
4511 {
4512 *out = &group_reloc_table[i];
4513 *str += (length + 1);
4514 return SUCCESS;
4515 }
4516 }
4517
4518 return FAIL;
4519}
4520
4521/* Parse a <shifter_operand> for an ARM data processing instruction
4522 (as for parse_shifter_operand) where group relocations are allowed:
4523
4524 #<immediate>
4525 #<immediate>, <rotate>
4526 #:<group_reloc>:<expression>
4527 <Rm>
4528 <Rm>, <shift>
4529
4530 where <group_reloc> is one of the strings defined in group_reloc_table.
4531 The hashes are optional.
4532
4533 Everything else is as for parse_shifter_operand. */
4534
4535static parse_operand_result
4536parse_shifter_operand_group_reloc (char **str, int i)
4537{
4538 /* Determine if we have the sequence of characters #: or just :
4539 coming next. If we do, then we check for a group relocation.
4540 If we don't, punt the whole lot to parse_shifter_operand. */
4541
4542 if (((*str)[0] == '#' && (*str)[1] == ':')
4543 || (*str)[0] == ':')
4544 {
4545 struct group_reloc_table_entry *entry;
4546
4547 if ((*str)[0] == '#')
4548 (*str) += 2;
4549 else
4550 (*str)++;
4551
4552 /* Try to parse a group relocation. Anything else is an error. */
4553 if (find_group_reloc_table_entry (str, &entry) == FAIL)
4554 {
4555 inst.error = _("unknown group relocation");
4556 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4557 }
4558
4559 /* We now have the group relocation table entry corresponding to
4560 the name in the assembler source. Next, we parse the expression. */
4561 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4562 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4563
4564 /* Record the relocation type (always the ALU variant here). */
4565 inst.reloc.type = entry->alu_code;
4566 assert (inst.reloc.type != 0);
4567
4568 return PARSE_OPERAND_SUCCESS;
4569 }
4570 else
4571 return parse_shifter_operand (str, i) == SUCCESS
4572 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4573
4574 /* Never reached. */
4575}
4576
c19d1205
ZW
4577/* Parse all forms of an ARM address expression. Information is written
4578 to inst.operands[i] and/or inst.reloc.
09d92015 4579
c19d1205 4580 Preindexed addressing (.preind=1):
09d92015 4581
c19d1205
ZW
4582 [Rn, #offset] .reg=Rn .reloc.exp=offset
4583 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4584 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4585 .shift_kind=shift .reloc.exp=shift_imm
09d92015 4586
c19d1205 4587 These three may have a trailing ! which causes .writeback to be set also.
09d92015 4588
c19d1205 4589 Postindexed addressing (.postind=1, .writeback=1):
09d92015 4590
c19d1205
ZW
4591 [Rn], #offset .reg=Rn .reloc.exp=offset
4592 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4593 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4594 .shift_kind=shift .reloc.exp=shift_imm
09d92015 4595
c19d1205 4596 Unindexed addressing (.preind=0, .postind=0):
09d92015 4597
c19d1205 4598 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 4599
c19d1205 4600 Other:
09d92015 4601
c19d1205
ZW
4602 [Rn]{!} shorthand for [Rn,#0]{!}
4603 =immediate .isreg=0 .reloc.exp=immediate
4604 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
09d92015 4605
c19d1205
ZW
4606 It is the caller's responsibility to check for addressing modes not
4607 supported by the instruction, and to set inst.reloc.type. */
4608
4962c51a
MS
4609static parse_operand_result
4610parse_address_main (char **str, int i, int group_relocations,
4611 group_reloc_type group_type)
09d92015 4612{
c19d1205
ZW
4613 char *p = *str;
4614 int reg;
09d92015 4615
c19d1205 4616 if (skip_past_char (&p, '[') == FAIL)
09d92015 4617 {
c19d1205
ZW
4618 if (skip_past_char (&p, '=') == FAIL)
4619 {
4620 /* bare address - translate to PC-relative offset */
4621 inst.reloc.pc_rel = 1;
4622 inst.operands[i].reg = REG_PC;
4623 inst.operands[i].isreg = 1;
4624 inst.operands[i].preind = 1;
4625 }
4626 /* else a load-constant pseudo op, no special treatment needed here */
09d92015 4627
c19d1205 4628 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4962c51a 4629 return PARSE_OPERAND_FAIL;
09d92015 4630
c19d1205 4631 *str = p;
4962c51a 4632 return PARSE_OPERAND_SUCCESS;
09d92015
MM
4633 }
4634
dcbf9037 4635 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 4636 {
c19d1205 4637 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 4638 return PARSE_OPERAND_FAIL;
09d92015 4639 }
c19d1205
ZW
4640 inst.operands[i].reg = reg;
4641 inst.operands[i].isreg = 1;
09d92015 4642
c19d1205 4643 if (skip_past_comma (&p) == SUCCESS)
09d92015 4644 {
c19d1205 4645 inst.operands[i].preind = 1;
09d92015 4646
c19d1205
ZW
4647 if (*p == '+') p++;
4648 else if (*p == '-') p++, inst.operands[i].negative = 1;
4649
dcbf9037 4650 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 4651 {
c19d1205
ZW
4652 inst.operands[i].imm = reg;
4653 inst.operands[i].immisreg = 1;
4654
4655 if (skip_past_comma (&p) == SUCCESS)
4656 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 4657 return PARSE_OPERAND_FAIL;
c19d1205 4658 }
5287ad62
JB
4659 else if (skip_past_char (&p, ':') == SUCCESS)
4660 {
4661 /* FIXME: '@' should be used here, but it's filtered out by generic
4662 code before we get to see it here. This may be subject to
4663 change. */
4664 expressionS exp;
4665 my_get_expression (&exp, &p, GE_NO_PREFIX);
4666 if (exp.X_op != O_constant)
4667 {
4668 inst.error = _("alignment must be constant");
4962c51a 4669 return PARSE_OPERAND_FAIL;
5287ad62
JB
4670 }
4671 inst.operands[i].imm = exp.X_add_number << 8;
4672 inst.operands[i].immisalign = 1;
4673 /* Alignments are not pre-indexes. */
4674 inst.operands[i].preind = 0;
4675 }
c19d1205
ZW
4676 else
4677 {
4678 if (inst.operands[i].negative)
4679 {
4680 inst.operands[i].negative = 0;
4681 p--;
4682 }
4962c51a 4683
5f4273c7
NC
4684 if (group_relocations
4685 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS
4686 {
4687 struct group_reloc_table_entry *entry;
4688
4689 /* Skip over the #: or : sequence. */
4690 if (*p == '#')
4691 p += 2;
4692 else
4693 p++;
4694
4695 /* Try to parse a group relocation. Anything else is an
4696 error. */
4697 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
4698 {
4699 inst.error = _("unknown group relocation");
4700 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4701 }
4702
4703 /* We now have the group relocation table entry corresponding to
4704 the name in the assembler source. Next, we parse the
4705 expression. */
4706 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4707 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4708
4709 /* Record the relocation type. */
4710 switch (group_type)
4711 {
4712 case GROUP_LDR:
4713 inst.reloc.type = entry->ldr_code;
4714 break;
4715
4716 case GROUP_LDRS:
4717 inst.reloc.type = entry->ldrs_code;
4718 break;
4719
4720 case GROUP_LDC:
4721 inst.reloc.type = entry->ldc_code;
4722 break;
4723
4724 default:
4725 assert (0);
4726 }
4727
4728 if (inst.reloc.type == 0)
4729 {
4730 inst.error = _("this group relocation is not allowed on this instruction");
4731 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4732 }
4733 }
4734 else
4735 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4736 return PARSE_OPERAND_FAIL;
09d92015
MM
4737 }
4738 }
4739
c19d1205 4740 if (skip_past_char (&p, ']') == FAIL)
09d92015 4741 {
c19d1205 4742 inst.error = _("']' expected");
4962c51a 4743 return PARSE_OPERAND_FAIL;
09d92015
MM
4744 }
4745
c19d1205
ZW
4746 if (skip_past_char (&p, '!') == SUCCESS)
4747 inst.operands[i].writeback = 1;
09d92015 4748
c19d1205 4749 else if (skip_past_comma (&p) == SUCCESS)
09d92015 4750 {
c19d1205
ZW
4751 if (skip_past_char (&p, '{') == SUCCESS)
4752 {
4753 /* [Rn], {expr} - unindexed, with option */
4754 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 4755 0, 255, TRUE) == FAIL)
4962c51a 4756 return PARSE_OPERAND_FAIL;
09d92015 4757
c19d1205
ZW
4758 if (skip_past_char (&p, '}') == FAIL)
4759 {
4760 inst.error = _("'}' expected at end of 'option' field");
4962c51a 4761 return PARSE_OPERAND_FAIL;
c19d1205
ZW
4762 }
4763 if (inst.operands[i].preind)
4764 {
4765 inst.error = _("cannot combine index with option");
4962c51a 4766 return PARSE_OPERAND_FAIL;
c19d1205
ZW
4767 }
4768 *str = p;
4962c51a 4769 return PARSE_OPERAND_SUCCESS;
09d92015 4770 }
c19d1205
ZW
4771 else
4772 {
4773 inst.operands[i].postind = 1;
4774 inst.operands[i].writeback = 1;
09d92015 4775
c19d1205
ZW
4776 if (inst.operands[i].preind)
4777 {
4778 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 4779 return PARSE_OPERAND_FAIL;
c19d1205 4780 }
09d92015 4781
c19d1205
ZW
4782 if (*p == '+') p++;
4783 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 4784
dcbf9037 4785 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 4786 {
5287ad62
JB
4787 /* We might be using the immediate for alignment already. If we
4788 are, OR the register number into the low-order bits. */
4789 if (inst.operands[i].immisalign)
4790 inst.operands[i].imm |= reg;
4791 else
4792 inst.operands[i].imm = reg;
c19d1205 4793 inst.operands[i].immisreg = 1;
a737bd4d 4794
c19d1205
ZW
4795 if (skip_past_comma (&p) == SUCCESS)
4796 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 4797 return PARSE_OPERAND_FAIL;
c19d1205
ZW
4798 }
4799 else
4800 {
4801 if (inst.operands[i].negative)
4802 {
4803 inst.operands[i].negative = 0;
4804 p--;
4805 }
4806 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4962c51a 4807 return PARSE_OPERAND_FAIL;
c19d1205
ZW
4808 }
4809 }
a737bd4d
NC
4810 }
4811
c19d1205
ZW
4812 /* If at this point neither .preind nor .postind is set, we have a
4813 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4814 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
4815 {
4816 inst.operands[i].preind = 1;
4817 inst.reloc.exp.X_op = O_constant;
4818 inst.reloc.exp.X_add_number = 0;
4819 }
4820 *str = p;
4962c51a
MS
4821 return PARSE_OPERAND_SUCCESS;
4822}
4823
4824static int
4825parse_address (char **str, int i)
4826{
4827 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
4828 ? SUCCESS : FAIL;
4829}
4830
4831static parse_operand_result
4832parse_address_group_reloc (char **str, int i, group_reloc_type type)
4833{
4834 return parse_address_main (str, i, 1, type);
a737bd4d
NC
4835}
4836
b6895b4f
PB
4837/* Parse an operand for a MOVW or MOVT instruction. */
4838static int
4839parse_half (char **str)
4840{
4841 char * p;
5f4273c7 4842
b6895b4f
PB
4843 p = *str;
4844 skip_past_char (&p, '#');
5f4273c7 4845 if (strncasecmp (p, ":lower16:", 9) == 0)
b6895b4f
PB
4846 inst.reloc.type = BFD_RELOC_ARM_MOVW;
4847 else if (strncasecmp (p, ":upper16:", 9) == 0)
4848 inst.reloc.type = BFD_RELOC_ARM_MOVT;
4849
4850 if (inst.reloc.type != BFD_RELOC_UNUSED)
4851 {
4852 p += 9;
5f4273c7 4853 skip_whitespace (p);
b6895b4f
PB
4854 }
4855
4856 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4857 return FAIL;
4858
4859 if (inst.reloc.type == BFD_RELOC_UNUSED)
4860 {
4861 if (inst.reloc.exp.X_op != O_constant)
4862 {
4863 inst.error = _("constant expression expected");
4864 return FAIL;
4865 }
4866 if (inst.reloc.exp.X_add_number < 0
4867 || inst.reloc.exp.X_add_number > 0xffff)
4868 {
4869 inst.error = _("immediate value out of range");
4870 return FAIL;
4871 }
4872 }
4873 *str = p;
4874 return SUCCESS;
4875}
4876
c19d1205 4877/* Miscellaneous. */
a737bd4d 4878
c19d1205
ZW
4879/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4880 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4881static int
4882parse_psr (char **str)
09d92015 4883{
c19d1205
ZW
4884 char *p;
4885 unsigned long psr_field;
62b3e311
PB
4886 const struct asm_psr *psr;
4887 char *start;
09d92015 4888
c19d1205
ZW
4889 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4890 feature for ease of use and backwards compatibility. */
4891 p = *str;
62b3e311 4892 if (strncasecmp (p, "SPSR", 4) == 0)
c19d1205 4893 psr_field = SPSR_BIT;
62b3e311 4894 else if (strncasecmp (p, "CPSR", 4) == 0)
c19d1205
ZW
4895 psr_field = 0;
4896 else
62b3e311
PB
4897 {
4898 start = p;
4899 do
4900 p++;
4901 while (ISALNUM (*p) || *p == '_');
4902
4903 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
4904 if (!psr)
4905 return FAIL;
09d92015 4906
62b3e311
PB
4907 *str = p;
4908 return psr->field;
4909 }
09d92015 4910
62b3e311 4911 p += 4;
c19d1205
ZW
4912 if (*p == '_')
4913 {
4914 /* A suffix follows. */
c19d1205
ZW
4915 p++;
4916 start = p;
a737bd4d 4917
c19d1205
ZW
4918 do
4919 p++;
4920 while (ISALNUM (*p) || *p == '_');
a737bd4d 4921
c19d1205
ZW
4922 psr = hash_find_n (arm_psr_hsh, start, p - start);
4923 if (!psr)
4924 goto error;
a737bd4d 4925
c19d1205 4926 psr_field |= psr->field;
a737bd4d 4927 }
c19d1205 4928 else
a737bd4d 4929 {
c19d1205
ZW
4930 if (ISALNUM (*p))
4931 goto error; /* Garbage after "[CS]PSR". */
4932
4933 psr_field |= (PSR_c | PSR_f);
a737bd4d 4934 }
c19d1205
ZW
4935 *str = p;
4936 return psr_field;
a737bd4d 4937
c19d1205
ZW
4938 error:
4939 inst.error = _("flag for {c}psr instruction expected");
4940 return FAIL;
a737bd4d
NC
4941}
4942
c19d1205
ZW
4943/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4944 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 4945
c19d1205
ZW
4946static int
4947parse_cps_flags (char **str)
a737bd4d 4948{
c19d1205
ZW
4949 int val = 0;
4950 int saw_a_flag = 0;
4951 char *s = *str;
a737bd4d 4952
c19d1205
ZW
4953 for (;;)
4954 switch (*s++)
4955 {
4956 case '\0': case ',':
4957 goto done;
a737bd4d 4958
c19d1205
ZW
4959 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
4960 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
4961 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 4962
c19d1205
ZW
4963 default:
4964 inst.error = _("unrecognized CPS flag");
4965 return FAIL;
4966 }
a737bd4d 4967
c19d1205
ZW
4968 done:
4969 if (saw_a_flag == 0)
a737bd4d 4970 {
c19d1205
ZW
4971 inst.error = _("missing CPS flags");
4972 return FAIL;
a737bd4d 4973 }
a737bd4d 4974
c19d1205
ZW
4975 *str = s - 1;
4976 return val;
a737bd4d
NC
4977}
4978
c19d1205
ZW
4979/* Parse an endian specifier ("BE" or "LE", case insensitive);
4980 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC
4981
4982static int
c19d1205 4983parse_endian_specifier (char **str)
a737bd4d 4984{
c19d1205
ZW
4985 int little_endian;
4986 char *s = *str;
a737bd4d 4987
c19d1205
ZW
4988 if (strncasecmp (s, "BE", 2))
4989 little_endian = 0;
4990 else if (strncasecmp (s, "LE", 2))
4991 little_endian = 1;
4992 else
a737bd4d 4993 {
c19d1205 4994 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
4995 return FAIL;
4996 }
4997
c19d1205 4998 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 4999 {
c19d1205 5000 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC
5001 return FAIL;
5002 }
5003
c19d1205
ZW
5004 *str = s + 2;
5005 return little_endian;
5006}
a737bd4d 5007
c19d1205
ZW
5008/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5009 value suitable for poking into the rotate field of an sxt or sxta
5010 instruction, or FAIL on error. */
5011
5012static int
5013parse_ror (char **str)
5014{
5015 int rot;
5016 char *s = *str;
5017
5018 if (strncasecmp (s, "ROR", 3) == 0)
5019 s += 3;
5020 else
a737bd4d 5021 {
c19d1205 5022 inst.error = _("missing rotation field after comma");
a737bd4d
NC
5023 return FAIL;
5024 }
c19d1205
ZW
5025
5026 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5027 return FAIL;
5028
5029 switch (rot)
a737bd4d 5030 {
c19d1205
ZW
5031 case 0: *str = s; return 0x0;
5032 case 8: *str = s; return 0x1;
5033 case 16: *str = s; return 0x2;
5034 case 24: *str = s; return 0x3;
5035
5036 default:
5037 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC
5038 return FAIL;
5039 }
c19d1205 5040}
a737bd4d 5041
c19d1205
ZW
5042/* Parse a conditional code (from conds[] below). The value returned is in the
5043 range 0 .. 14, or FAIL. */
5044static int
5045parse_cond (char **str)
5046{
c462b453 5047 char *q;
c19d1205 5048 const struct asm_cond *c;
c462b453
PB
5049 int n;
5050 /* Condition codes are always 2 characters, so matching up to
5051 3 characters is sufficient. */
5052 char cond[3];
a737bd4d 5053
c462b453
PB
5054 q = *str;
5055 n = 0;
5056 while (ISALPHA (*q) && n < 3)
5057 {
5058 cond[n] = TOLOWER(*q);
5059 q++;
5060 n++;
5061 }
a737bd4d 5062
c462b453 5063 c = hash_find_n (arm_cond_hsh, cond, n);
c19d1205 5064 if (!c)
a737bd4d 5065 {
c19d1205 5066 inst.error = _("condition required");
a737bd4d
NC
5067 return FAIL;
5068 }
5069
c19d1205
ZW
5070 *str = q;
5071 return c->value;
5072}
5073
62b3e311
PB
5074/* Parse an option for a barrier instruction. Returns the encoding for the
5075 option, or FAIL. */
5076static int
5077parse_barrier (char **str)
5078{
5079 char *p, *q;
5080 const struct asm_barrier_opt *o;
5081
5082 p = q = *str;
5083 while (ISALPHA (*q))
5084 q++;
5085
5086 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
5087 if (!o)
5088 return FAIL;
5089
5090 *str = q;
5091 return o->value;
5092}
5093
92e90b6e
PB
5094/* Parse the operands of a table branch instruction. Similar to a memory
5095 operand. */
5096static int
5097parse_tb (char **str)
5098{
5099 char * p = *str;
5100 int reg;
5101
5102 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB
5103 {
5104 inst.error = _("'[' expected");
5105 return FAIL;
5106 }
92e90b6e 5107
dcbf9037 5108 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB
5109 {
5110 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5111 return FAIL;
5112 }
5113 inst.operands[0].reg = reg;
5114
5115 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB
5116 {
5117 inst.error = _("',' expected");
5118 return FAIL;
5119 }
5f4273c7 5120
dcbf9037 5121 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB
5122 {
5123 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5124 return FAIL;
5125 }
5126 inst.operands[0].imm = reg;
5127
5128 if (skip_past_comma (&p) == SUCCESS)
5129 {
5130 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5131 return FAIL;
5132 if (inst.reloc.exp.X_add_number != 1)
5133 {
5134 inst.error = _("invalid shift");
5135 return FAIL;
5136 }
5137 inst.operands[0].shifted = 1;
5138 }
5139
5140 if (skip_past_char (&p, ']') == FAIL)
5141 {
5142 inst.error = _("']' expected");
5143 return FAIL;
5144 }
5145 *str = p;
5146 return SUCCESS;
5147}
5148
5287ad62
JB
5149/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5150 information on the types the operands can take and how they are encoded.
037e8744
JB
5151 Up to four operands may be read; this function handles setting the
5152 ".present" field for each read operand itself.
5287ad62
JB
5153 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5154 else returns FAIL. */
5155
5156static int
5157parse_neon_mov (char **str, int *which_operand)
5158{
5159 int i = *which_operand, val;
5160 enum arm_reg_type rtype;
5161 char *ptr = *str;
dcbf9037 5162 struct neon_type_el optype;
5f4273c7 5163
dcbf9037 5164 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB
5165 {
5166 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5167 inst.operands[i].reg = val;
5168 inst.operands[i].isscalar = 1;
dcbf9037 5169 inst.operands[i].vectype = optype;
5287ad62
JB
5170 inst.operands[i++].present = 1;
5171
5172 if (skip_past_comma (&ptr) == FAIL)
5173 goto wanted_comma;
5f4273c7 5174
dcbf9037 5175 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5287ad62 5176 goto wanted_arm;
5f4273c7 5177
5287ad62
JB
5178 inst.operands[i].reg = val;
5179 inst.operands[i].isreg = 1;
5180 inst.operands[i].present = 1;
5181 }
037e8744 5182 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
dcbf9037 5183 != FAIL)
5287ad62
JB
5184 {
5185 /* Cases 0, 1, 2, 3, 5 (D only). */
5186 if (skip_past_comma (&ptr) == FAIL)
5187 goto wanted_comma;
5f4273c7 5188
5287ad62
JB
5189 inst.operands[i].reg = val;
5190 inst.operands[i].isreg = 1;
5191 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB
5192 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5193 inst.operands[i].isvec = 1;
dcbf9037 5194 inst.operands[i].vectype = optype;
5287ad62
JB
5195 inst.operands[i++].present = 1;
5196
dcbf9037 5197 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62 5198 {
037e8744
JB
5199 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5200 Case 13: VMOV <Sd>, <Rm> */
5287ad62
JB
5201 inst.operands[i].reg = val;
5202 inst.operands[i].isreg = 1;
037e8744 5203 inst.operands[i].present = 1;
5287ad62
JB
5204
5205 if (rtype == REG_TYPE_NQ)
5206 {
dcbf9037 5207 first_error (_("can't use Neon quad register here"));
5287ad62
JB
5208 return FAIL;
5209 }
037e8744
JB
5210 else if (rtype != REG_TYPE_VFS)
5211 {
5212 i++;
5213 if (skip_past_comma (&ptr) == FAIL)
5214 goto wanted_comma;
5215 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5216 goto wanted_arm;
5217 inst.operands[i].reg = val;
5218 inst.operands[i].isreg = 1;
5219 inst.operands[i].present = 1;
5220 }
5287ad62 5221 }
037e8744
JB
5222 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5223 &optype)) != FAIL)
5287ad62
JB
5224 {
5225 /* Case 0: VMOV<c><q> <Qd>, <Qm>
037e8744
JB
5226 Case 1: VMOV<c><q> <Dd>, <Dm>
5227 Case 8: VMOV.F32 <Sd>, <Sm>
5228 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5287ad62
JB
5229
5230 inst.operands[i].reg = val;
5231 inst.operands[i].isreg = 1;
5232 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB
5233 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5234 inst.operands[i].isvec = 1;
dcbf9037 5235 inst.operands[i].vectype = optype;
5287ad62 5236 inst.operands[i].present = 1;
5f4273c7 5237
037e8744
JB
5238 if (skip_past_comma (&ptr) == SUCCESS)
5239 {
5240 /* Case 15. */
5241 i++;
5242
5243 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5244 goto wanted_arm;
5245
5246 inst.operands[i].reg = val;
5247 inst.operands[i].isreg = 1;
5248 inst.operands[i++].present = 1;
5f4273c7 5249
037e8744
JB
5250 if (skip_past_comma (&ptr) == FAIL)
5251 goto wanted_comma;
5f4273c7 5252
037e8744
JB
5253 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5254 goto wanted_arm;
5f4273c7 5255
037e8744
JB
5256 inst.operands[i].reg = val;
5257 inst.operands[i].isreg = 1;
5258 inst.operands[i++].present = 1;
5259 }
5287ad62 5260 }
4641781c
PB
5261 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5262 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5263 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5264 Case 10: VMOV.F32 <Sd>, #<imm>
5265 Case 11: VMOV.F64 <Dd>, #<imm> */
5266 inst.operands[i].immisfloat = 1;
5267 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5268 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5269 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5270 ;
5287ad62
JB
5271 else
5272 {
dcbf9037 5273 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5287ad62
JB
5274 return FAIL;
5275 }
5276 }
dcbf9037 5277 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB
5278 {
5279 /* Cases 6, 7. */
5280 inst.operands[i].reg = val;
5281 inst.operands[i].isreg = 1;
5282 inst.operands[i++].present = 1;
5f4273c7 5283
5287ad62
JB
5284 if (skip_past_comma (&ptr) == FAIL)
5285 goto wanted_comma;
5f4273c7 5286
dcbf9037 5287 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB
5288 {
5289 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5290 inst.operands[i].reg = val;
5291 inst.operands[i].isscalar = 1;
5292 inst.operands[i].present = 1;
dcbf9037 5293 inst.operands[i].vectype = optype;
5287ad62 5294 }
dcbf9037 5295 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB
5296 {
5297 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5298 inst.operands[i].reg = val;
5299 inst.operands[i].isreg = 1;
5300 inst.operands[i++].present = 1;
5f4273c7 5301
5287ad62
JB
5302 if (skip_past_comma (&ptr) == FAIL)
5303 goto wanted_comma;
5f4273c7 5304
037e8744 5305 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
dcbf9037 5306 == FAIL)
5287ad62 5307 {
037e8744 5308 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5287ad62
JB
5309 return FAIL;
5310 }
5311
5312 inst.operands[i].reg = val;
5313 inst.operands[i].isreg = 1;
037e8744
JB
5314 inst.operands[i].isvec = 1;
5315 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
dcbf9037 5316 inst.operands[i].vectype = optype;
5287ad62 5317 inst.operands[i].present = 1;
5f4273c7 5318
037e8744
JB
5319 if (rtype == REG_TYPE_VFS)
5320 {
5321 /* Case 14. */
5322 i++;
5323 if (skip_past_comma (&ptr) == FAIL)
5324 goto wanted_comma;
5325 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5326 &optype)) == FAIL)
5327 {
5328 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5329 return FAIL;
5330 }
5331 inst.operands[i].reg = val;
5332 inst.operands[i].isreg = 1;
5333 inst.operands[i].isvec = 1;
5334 inst.operands[i].issingle = 1;
5335 inst.operands[i].vectype = optype;
5336 inst.operands[i].present = 1;
5337 }
5338 }
5339 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5340 != FAIL)
5341 {
5342 /* Case 13. */
5343 inst.operands[i].reg = val;
5344 inst.operands[i].isreg = 1;
5345 inst.operands[i].isvec = 1;
5346 inst.operands[i].issingle = 1;
5347 inst.operands[i].vectype = optype;
5348 inst.operands[i++].present = 1;
5287ad62
JB
5349 }
5350 }
5351 else
5352 {
dcbf9037 5353 first_error (_("parse error"));
5287ad62
JB
5354 return FAIL;
5355 }
5356
5357 /* Successfully parsed the operands. Update args. */
5358 *which_operand = i;
5359 *str = ptr;
5360 return SUCCESS;
5361
5f4273c7 5362 wanted_comma:
dcbf9037 5363 first_error (_("expected comma"));
5287ad62 5364 return FAIL;
5f4273c7
NC
5365
5366 wanted_arm:
dcbf9037 5367 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 5368 return FAIL;
5287ad62
JB
5369}
5370
c19d1205
ZW
5371/* Matcher codes for parse_operands. */
5372enum operand_parse_code
5373{
5374 OP_stop, /* end of line */
5375
5376 OP_RR, /* ARM register */
5377 OP_RRnpc, /* ARM register, not r15 */
5378 OP_RRnpcb, /* ARM register, not r15, in square brackets */
5379 OP_RRw, /* ARM register, not r15, optional trailing ! */
5380 OP_RCP, /* Coprocessor number */
5381 OP_RCN, /* Coprocessor register */
5382 OP_RF, /* FPA register */
5383 OP_RVS, /* VFP single precision register */
5287ad62
JB
5384 OP_RVD, /* VFP double precision register (0..15) */
5385 OP_RND, /* Neon double precision register (0..31) */
5386 OP_RNQ, /* Neon quad precision register */
037e8744 5387 OP_RVSD, /* VFP single or double precision register */
5287ad62 5388 OP_RNDQ, /* Neon double or quad precision register */
037e8744 5389 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 5390 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW
5391 OP_RVC, /* VFP control register */
5392 OP_RMF, /* Maverick F register */
5393 OP_RMD, /* Maverick D register */
5394 OP_RMFX, /* Maverick FX register */
5395 OP_RMDX, /* Maverick DX register */
5396 OP_RMAX, /* Maverick AX register */
5397 OP_RMDS, /* Maverick DSPSC register */
5398 OP_RIWR, /* iWMMXt wR register */
5399 OP_RIWC, /* iWMMXt wC register */
5400 OP_RIWG, /* iWMMXt wCG register */
5401 OP_RXA, /* XScale accumulator register */
5402
5403 OP_REGLST, /* ARM register list */
5404 OP_VRSLST, /* VFP single-precision register list */
5405 OP_VRDLST, /* VFP double-precision register list */
037e8744 5406 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB
5407 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
5408 OP_NSTRLST, /* Neon element/structure list */
5409
5410 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5411 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 5412 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5287ad62 5413 OP_RR_RNSC, /* ARM reg or Neon scalar. */
037e8744 5414 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5287ad62
JB
5415 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5416 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5417 OP_VMOV, /* Neon VMOV operands. */
5418 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5419 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
2d447fca 5420 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5287ad62
JB
5421
5422 OP_I0, /* immediate zero */
c19d1205
ZW
5423 OP_I7, /* immediate value 0 .. 7 */
5424 OP_I15, /* 0 .. 15 */
5425 OP_I16, /* 1 .. 16 */
5287ad62 5426 OP_I16z, /* 0 .. 16 */
c19d1205
ZW
5427 OP_I31, /* 0 .. 31 */
5428 OP_I31w, /* 0 .. 31, optional trailing ! */
5429 OP_I32, /* 1 .. 32 */
5287ad62
JB
5430 OP_I32z, /* 0 .. 32 */
5431 OP_I63, /* 0 .. 63 */
c19d1205 5432 OP_I63s, /* -64 .. 63 */
5287ad62
JB
5433 OP_I64, /* 1 .. 64 */
5434 OP_I64z, /* 0 .. 64 */
c19d1205 5435 OP_I255, /* 0 .. 255 */
c19d1205
ZW
5436
5437 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5438 OP_I7b, /* 0 .. 7 */
5439 OP_I15b, /* 0 .. 15 */
5440 OP_I31b, /* 0 .. 31 */
5441
5442 OP_SH, /* shifter operand */
4962c51a 5443 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 5444 OP_ADDR, /* Memory address expression (any mode) */
4962c51a
MS
5445 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
5446 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5447 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW
5448 OP_EXP, /* arbitrary expression */
5449 OP_EXPi, /* same, with optional immediate prefix */
5450 OP_EXPr, /* same, with optional relocation suffix */
b6895b4f 5451 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c19d1205
ZW
5452
5453 OP_CPSF, /* CPS flags */
5454 OP_ENDI, /* Endianness specifier */
5455 OP_PSR, /* CPSR/SPSR mask for msr */
5456 OP_COND, /* conditional code */
92e90b6e 5457 OP_TB, /* Table branch. */
c19d1205 5458
037e8744
JB
5459 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
5460 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
5461
c19d1205
ZW
5462 OP_RRnpc_I0, /* ARM register or literal 0 */
5463 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
5464 OP_RR_EXi, /* ARM register or expression with imm prefix */
5465 OP_RF_IF, /* FPA register or immediate */
5466 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 5467 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW
5468
5469 /* Optional operands. */
5470 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5471 OP_oI31b, /* 0 .. 31 */
5287ad62 5472 OP_oI32b, /* 1 .. 32 */
c19d1205
ZW
5473 OP_oIffffb, /* 0 .. 65535 */
5474 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
5475
5476 OP_oRR, /* ARM register */
5477 OP_oRRnpc, /* ARM register, not the PC */
b6702015 5478 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB
5479 OP_oRND, /* Optional Neon double precision register */
5480 OP_oRNQ, /* Optional Neon quad precision register */
5481 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 5482 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
c19d1205
ZW
5483 OP_oSHll, /* LSL immediate */
5484 OP_oSHar, /* ASR immediate */
5485 OP_oSHllar, /* LSL or ASR immediate */
5486 OP_oROR, /* ROR 0/8/16/24 */
62b3e311 5487 OP_oBARRIER, /* Option argument for a barrier instruction. */
c19d1205
ZW
5488
5489 OP_FIRST_OPTIONAL = OP_oI7b
5490};
a737bd4d 5491
c19d1205
ZW
5492/* Generic instruction operand parser. This does no encoding and no
5493 semantic validation; it merely squirrels values away in the inst
5494 structure. Returns SUCCESS or FAIL depending on whether the
5495 specified grammar matched. */
5496static int
ca3f61f7 5497parse_operands (char *str, const unsigned char *pattern)
c19d1205
ZW
5498{
5499 unsigned const char *upat = pattern;
5500 char *backtrack_pos = 0;
5501 const char *backtrack_error = 0;
5502 int i, val, backtrack_index = 0;
5287ad62 5503 enum arm_reg_type rtype;
4962c51a 5504 parse_operand_result result;
c19d1205
ZW
5505
5506#define po_char_or_fail(chr) do { \
5507 if (skip_past_char (&str, chr) == FAIL) \
5508 goto bad_args; \
5509} while (0)
5510
dcbf9037
JB
5511#define po_reg_or_fail(regtype) do { \
5512 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5513 &inst.operands[i].vectype); \
5514 if (val == FAIL) \
5515 { \
5516 first_error (_(reg_expected_msgs[regtype])); \
5517 goto failure; \
5518 } \
5519 inst.operands[i].reg = val; \
5520 inst.operands[i].isreg = 1; \
5521 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
037e8744
JB
5522 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5523 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5524 || rtype == REG_TYPE_VFD \
5525 || rtype == REG_TYPE_NQ); \
c19d1205
ZW
5526} while (0)
5527
dcbf9037
JB
5528#define po_reg_or_goto(regtype, label) do { \
5529 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5530 &inst.operands[i].vectype); \
5531 if (val == FAIL) \
5532 goto label; \
5533 \
5534 inst.operands[i].reg = val; \
5535 inst.operands[i].isreg = 1; \
5536 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
037e8744
JB
5537 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5538 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5539 || rtype == REG_TYPE_VFD \
5540 || rtype == REG_TYPE_NQ); \
c19d1205
ZW
5541} while (0)
5542
5543#define po_imm_or_fail(min, max, popt) do { \
5544 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5545 goto failure; \
5546 inst.operands[i].imm = val; \
5547} while (0)
5548
dcbf9037
JB
5549#define po_scalar_or_goto(elsz, label) do { \
5550 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5551 if (val == FAIL) \
5552 goto label; \
5553 inst.operands[i].reg = val; \
5554 inst.operands[i].isscalar = 1; \
5287ad62
JB
5555} while (0)
5556
c19d1205
ZW
5557#define po_misc_or_fail(expr) do { \
5558 if (expr) \
5559 goto failure; \
5560} while (0)
5561
4962c51a
MS
5562#define po_misc_or_fail_no_backtrack(expr) do { \
5563 result = expr; \
5564 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5565 backtrack_pos = 0; \
5566 if (result != PARSE_OPERAND_SUCCESS) \
5567 goto failure; \
5568} while (0)
5569
c19d1205
ZW
5570 skip_whitespace (str);
5571
5572 for (i = 0; upat[i] != OP_stop; i++)
5573 {
5574 if (upat[i] >= OP_FIRST_OPTIONAL)
5575 {
5576 /* Remember where we are in case we need to backtrack. */
5577 assert (!backtrack_pos);
5578 backtrack_pos = str;
5579 backtrack_error = inst.error;
5580 backtrack_index = i;
5581 }
5582
b6702015 5583 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW
5584 po_char_or_fail (',');
5585
5586 switch (upat[i])
5587 {
5588 /* Registers */
5589 case OP_oRRnpc:
5590 case OP_RRnpc:
5591 case OP_oRR:
5592 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
5593 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
5594 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
5595 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
5596 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
5597 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
5287ad62
JB
5598 case OP_oRND:
5599 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB
5600 case OP_RVC:
5601 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
5602 break;
5603 /* Also accept generic coprocessor regs for unknown registers. */
5604 coproc_reg:
5605 po_reg_or_fail (REG_TYPE_CN);
5606 break;
c19d1205
ZW
5607 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
5608 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
5609 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
5610 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
5611 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
5612 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
5613 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
5614 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
5615 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
5616 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
5287ad62
JB
5617 case OP_oRNQ:
5618 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
5619 case OP_oRNDQ:
5620 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
037e8744
JB
5621 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
5622 case OP_oRNSDQ:
5623 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5287ad62
JB
5624
5625 /* Neon scalar. Using an element size of 8 means that some invalid
5626 scalars are accepted here, so deal with those in later code. */
5627 case OP_RNSC: po_scalar_or_goto (8, failure); break;
5628
5629 /* WARNING: We can expand to two operands here. This has the potential
5630 to totally confuse the backtracking mechanism! It will be OK at
5631 least as long as we don't try to use optional args as well,
5632 though. */
5633 case OP_NILO:
5634 {
5635 po_reg_or_goto (REG_TYPE_NDQ, try_imm);
466bbf93 5636 inst.operands[i].present = 1;
5287ad62
JB
5637 i++;
5638 skip_past_comma (&str);
5639 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
5640 break;
5641 one_reg_only:
5642 /* Optional register operand was omitted. Unfortunately, it's in
5643 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5644 here (this is a bit grotty). */
5645 inst.operands[i] = inst.operands[i-1];
5646 inst.operands[i-1].present = 0;
5647 break;
5648 try_imm:
036dc3f7
PB
5649 /* There's a possibility of getting a 64-bit immediate here, so
5650 we need special handling. */
5651 if (parse_big_immediate (&str, i) == FAIL)
5652 {
5653 inst.error = _("immediate value is out of range");
5654 goto failure;
5655 }
5287ad62
JB
5656 }
5657 break;
5658
5659 case OP_RNDQ_I0:
5660 {
5661 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
5662 break;
5663 try_imm0:
5664 po_imm_or_fail (0, 0, TRUE);
5665 }
5666 break;
5667
037e8744
JB
5668 case OP_RVSD_I0:
5669 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
5670 break;
5671
5287ad62
JB
5672 case OP_RR_RNSC:
5673 {
5674 po_scalar_or_goto (8, try_rr);
5675 break;
5676 try_rr:
5677 po_reg_or_fail (REG_TYPE_RN);
5678 }
5679 break;
5680
037e8744
JB
5681 case OP_RNSDQ_RNSC:
5682 {
5683 po_scalar_or_goto (8, try_nsdq);
5684 break;
5685 try_nsdq:
5686 po_reg_or_fail (REG_TYPE_NSDQ);
5687 }
5688 break;
5689
5287ad62
JB
5690 case OP_RNDQ_RNSC:
5691 {
5692 po_scalar_or_goto (8, try_ndq);
5693 break;
5694 try_ndq:
5695 po_reg_or_fail (REG_TYPE_NDQ);
5696 }
5697 break;
5698
5699 case OP_RND_RNSC:
5700 {
5701 po_scalar_or_goto (8, try_vfd);
5702 break;
5703 try_vfd:
5704 po_reg_or_fail (REG_TYPE_VFD);
5705 }
5706 break;
5707
5708 case OP_VMOV:
5709 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5710 not careful then bad things might happen. */
5711 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
5712 break;
5713
5714 case OP_RNDQ_IMVNb:
5715 {
5716 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
5717 break;
5718 try_mvnimm:
5719 /* There's a possibility of getting a 64-bit immediate here, so
5720 we need special handling. */
5721 if (parse_big_immediate (&str, i) == FAIL)
5722 {
5723 inst.error = _("immediate value is out of range");
5724 goto failure;
5725 }
5726 }
5727 break;
5728
5729 case OP_RNDQ_I63b:
5730 {
5731 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
5732 break;
5733 try_shimm:
5734 po_imm_or_fail (0, 63, TRUE);
5735 }
5736 break;
c19d1205
ZW
5737
5738 case OP_RRnpcb:
5739 po_char_or_fail ('[');
5740 po_reg_or_fail (REG_TYPE_RN);
5741 po_char_or_fail (']');
5742 break;
a737bd4d 5743
c19d1205 5744 case OP_RRw:
b6702015 5745 case OP_oRRw:
c19d1205
ZW
5746 po_reg_or_fail (REG_TYPE_RN);
5747 if (skip_past_char (&str, '!') == SUCCESS)
5748 inst.operands[i].writeback = 1;
5749 break;
5750
5751 /* Immediates */
5752 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
5753 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
5754 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
5287ad62 5755 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW
5756 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
5757 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
5287ad62 5758 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
c19d1205 5759 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
5287ad62
JB
5760 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
5761 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
5762 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 5763 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW
5764
5765 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
5766 case OP_oI7b:
5767 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
5768 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
5769 case OP_oI31b:
5770 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
5287ad62 5771 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
c19d1205
ZW
5772 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
5773
5774 /* Immediate variants */
5775 case OP_oI255c:
5776 po_char_or_fail ('{');
5777 po_imm_or_fail (0, 255, TRUE);
5778 po_char_or_fail ('}');
5779 break;
5780
5781 case OP_I31w:
5782 /* The expression parser chokes on a trailing !, so we have
5783 to find it first and zap it. */
5784 {
5785 char *s = str;
5786 while (*s && *s != ',')
5787 s++;
5788 if (s[-1] == '!')
5789 {
5790 s[-1] = '\0';
5791 inst.operands[i].writeback = 1;
5792 }
5793 po_imm_or_fail (0, 31, TRUE);
5794 if (str == s - 1)
5795 str = s;
5796 }
5797 break;
5798
5799 /* Expressions */
5800 case OP_EXPi: EXPi:
5801 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5802 GE_OPT_PREFIX));
5803 break;
5804
5805 case OP_EXP:
5806 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5807 GE_NO_PREFIX));
5808 break;
5809
5810 case OP_EXPr: EXPr:
5811 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5812 GE_NO_PREFIX));
5813 if (inst.reloc.exp.X_op == O_symbol)
a737bd4d 5814 {
c19d1205
ZW
5815 val = parse_reloc (&str);
5816 if (val == -1)
5817 {
5818 inst.error = _("unrecognized relocation suffix");
5819 goto failure;
5820 }
5821 else if (val != BFD_RELOC_UNUSED)
5822 {
5823 inst.operands[i].imm = val;
5824 inst.operands[i].hasreloc = 1;
5825 }
a737bd4d 5826 }
c19d1205 5827 break;
a737bd4d 5828
b6895b4f
PB
5829 /* Operand for MOVW or MOVT. */
5830 case OP_HALF:
5831 po_misc_or_fail (parse_half (&str));
5832 break;
5833
c19d1205
ZW
5834 /* Register or expression */
5835 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
5836 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 5837
c19d1205
ZW
5838 /* Register or immediate */
5839 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
5840 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 5841
c19d1205
ZW
5842 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
5843 IF:
5844 if (!is_immediate_prefix (*str))
5845 goto bad_args;
5846 str++;
5847 val = parse_fpa_immediate (&str);
5848 if (val == FAIL)
5849 goto failure;
5850 /* FPA immediates are encoded as registers 8-15.
5851 parse_fpa_immediate has already applied the offset. */
5852 inst.operands[i].reg = val;
5853 inst.operands[i].isreg = 1;
5854 break;
09d92015 5855
2d447fca
JM
5856 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
5857 I32z: po_imm_or_fail (0, 32, FALSE); break;
5858
c19d1205
ZW
5859 /* Two kinds of register */
5860 case OP_RIWR_RIWC:
5861 {
5862 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM
5863 if (!rege
5864 || (rege->type != REG_TYPE_MMXWR
5865 && rege->type != REG_TYPE_MMXWC
5866 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW
5867 {
5868 inst.error = _("iWMMXt data or control register expected");
5869 goto failure;
5870 }
5871 inst.operands[i].reg = rege->number;
5872 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
5873 }
5874 break;
09d92015 5875
41adaa5c
JM
5876 case OP_RIWC_RIWG:
5877 {
5878 struct reg_entry *rege = arm_reg_parse_multi (&str);
5879 if (!rege
5880 || (rege->type != REG_TYPE_MMXWC
5881 && rege->type != REG_TYPE_MMXWCG))
5882 {
5883 inst.error = _("iWMMXt control register expected");
5884 goto failure;
5885 }
5886 inst.operands[i].reg = rege->number;
5887 inst.operands[i].isreg = 1;
5888 }
5889 break;
5890
c19d1205
ZW
5891 /* Misc */
5892 case OP_CPSF: val = parse_cps_flags (&str); break;
5893 case OP_ENDI: val = parse_endian_specifier (&str); break;
5894 case OP_oROR: val = parse_ror (&str); break;
5895 case OP_PSR: val = parse_psr (&str); break;
5896 case OP_COND: val = parse_cond (&str); break;
62b3e311 5897 case OP_oBARRIER:val = parse_barrier (&str); break;
c19d1205 5898
037e8744
JB
5899 case OP_RVC_PSR:
5900 po_reg_or_goto (REG_TYPE_VFC, try_psr);
5901 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
5902 break;
5903 try_psr:
5904 val = parse_psr (&str);
5905 break;
5906
5907 case OP_APSR_RR:
5908 po_reg_or_goto (REG_TYPE_RN, try_apsr);
5909 break;
5910 try_apsr:
5911 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5912 instruction). */
5913 if (strncasecmp (str, "APSR_", 5) == 0)
5914 {
5915 unsigned found = 0;
5916 str += 5;
5917 while (found < 15)
5918 switch (*str++)
5919 {
5920 case 'c': found = (found & 1) ? 16 : found | 1; break;
5921 case 'n': found = (found & 2) ? 16 : found | 2; break;
5922 case 'z': found = (found & 4) ? 16 : found | 4; break;
5923 case 'v': found = (found & 8) ? 16 : found | 8; break;
5924 default: found = 16;
5925 }
5926 if (found != 15)
5927 goto failure;
5928 inst.operands[i].isvec = 1;
5929 }
5930 else
5931 goto failure;
5932 break;
5933
92e90b6e
PB
5934 case OP_TB:
5935 po_misc_or_fail (parse_tb (&str));
5936 break;
5937
c19d1205
ZW
5938 /* Register lists */
5939 case OP_REGLST:
5940 val = parse_reg_list (&str);
5941 if (*str == '^')
5942 {
5943 inst.operands[1].writeback = 1;
5944 str++;
5945 }
5946 break;
09d92015 5947
c19d1205 5948 case OP_VRSLST:
5287ad62 5949 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
c19d1205 5950 break;
09d92015 5951
c19d1205 5952 case OP_VRDLST:
5287ad62 5953 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
c19d1205 5954 break;
a737bd4d 5955
037e8744
JB
5956 case OP_VRSDLST:
5957 /* Allow Q registers too. */
5958 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5959 REGLIST_NEON_D);
5960 if (val == FAIL)
5961 {
5962 inst.error = NULL;
5963 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5964 REGLIST_VFP_S);
5965 inst.operands[i].issingle = 1;
5966 }
5967 break;
5968
5287ad62
JB
5969 case OP_NRDLST:
5970 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5971 REGLIST_NEON_D);
5972 break;
5973
5974 case OP_NSTRLST:
dcbf9037
JB
5975 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
5976 &inst.operands[i].vectype);
5287ad62
JB
5977 break;
5978
c19d1205
ZW
5979 /* Addressing modes */
5980 case OP_ADDR:
5981 po_misc_or_fail (parse_address (&str, i));
5982 break;
09d92015 5983
4962c51a
MS
5984 case OP_ADDRGLDR:
5985 po_misc_or_fail_no_backtrack (
5986 parse_address_group_reloc (&str, i, GROUP_LDR));
5987 break;
5988
5989 case OP_ADDRGLDRS:
5990 po_misc_or_fail_no_backtrack (
5991 parse_address_group_reloc (&str, i, GROUP_LDRS));
5992 break;
5993
5994 case OP_ADDRGLDC:
5995 po_misc_or_fail_no_backtrack (
5996 parse_address_group_reloc (&str, i, GROUP_LDC));
5997 break;
5998
c19d1205
ZW
5999 case OP_SH:
6000 po_misc_or_fail (parse_shifter_operand (&str, i));
6001 break;
09d92015 6002
4962c51a
MS
6003 case OP_SHG:
6004 po_misc_or_fail_no_backtrack (
6005 parse_shifter_operand_group_reloc (&str, i));
6006 break;
6007
c19d1205
ZW
6008 case OP_oSHll:
6009 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6010 break;
09d92015 6011
c19d1205
ZW
6012 case OP_oSHar:
6013 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6014 break;
09d92015 6015
c19d1205
ZW
6016 case OP_oSHllar:
6017 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6018 break;
09d92015 6019
c19d1205 6020 default:
bd3ba5d1 6021 as_fatal (_("unhandled operand code %d"), upat[i]);
c19d1205 6022 }
09d92015 6023
c19d1205
ZW
6024 /* Various value-based sanity checks and shared operations. We
6025 do not signal immediate failures for the register constraints;
6026 this allows a syntax error to take precedence. */
6027 switch (upat[i])
6028 {
6029 case OP_oRRnpc:
6030 case OP_RRnpc:
6031 case OP_RRnpcb:
6032 case OP_RRw:
b6702015 6033 case OP_oRRw:
c19d1205
ZW
6034 case OP_RRnpc_I0:
6035 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6036 inst.error = BAD_PC;
6037 break;
09d92015 6038
c19d1205
ZW
6039 case OP_CPSF:
6040 case OP_ENDI:
6041 case OP_oROR:
6042 case OP_PSR:
037e8744 6043 case OP_RVC_PSR:
c19d1205 6044 case OP_COND:
62b3e311 6045 case OP_oBARRIER:
c19d1205
ZW
6046 case OP_REGLST:
6047 case OP_VRSLST:
6048 case OP_VRDLST:
037e8744 6049 case OP_VRSDLST:
5287ad62
JB
6050 case OP_NRDLST:
6051 case OP_NSTRLST:
c19d1205
ZW
6052 if (val == FAIL)
6053 goto failure;
6054 inst.operands[i].imm = val;
6055 break;
a737bd4d 6056
c19d1205
ZW
6057 default:
6058 break;
6059 }
09d92015 6060
c19d1205
ZW
6061 /* If we get here, this operand was successfully parsed. */
6062 inst.operands[i].present = 1;
6063 continue;
09d92015 6064
c19d1205 6065 bad_args:
09d92015 6066 inst.error = BAD_ARGS;
c19d1205
ZW
6067
6068 failure:
6069 if (!backtrack_pos)
d252fdde
PB
6070 {
6071 /* The parse routine should already have set inst.error, but set a
5f4273c7 6072 default here just in case. */
d252fdde
PB
6073 if (!inst.error)
6074 inst.error = _("syntax error");
6075 return FAIL;
6076 }
c19d1205
ZW
6077
6078 /* Do not backtrack over a trailing optional argument that
6079 absorbed some text. We will only fail again, with the
6080 'garbage following instruction' error message, which is
6081 probably less helpful than the current one. */
6082 if (backtrack_index == i && backtrack_pos != str
6083 && upat[i+1] == OP_stop)
d252fdde
PB
6084 {
6085 if (!inst.error)
6086 inst.error = _("syntax error");
6087 return FAIL;
6088 }
c19d1205
ZW
6089
6090 /* Try again, skipping the optional argument at backtrack_pos. */
6091 str = backtrack_pos;
6092 inst.error = backtrack_error;
6093 inst.operands[backtrack_index].present = 0;
6094 i = backtrack_index;
6095 backtrack_pos = 0;
09d92015 6096 }
09d92015 6097
c19d1205
ZW
6098 /* Check that we have parsed all the arguments. */
6099 if (*str != '\0' && !inst.error)
6100 inst.error = _("garbage following instruction");
09d92015 6101
c19d1205 6102 return inst.error ? FAIL : SUCCESS;
09d92015
MM
6103}
6104
c19d1205
ZW
6105#undef po_char_or_fail
6106#undef po_reg_or_fail
6107#undef po_reg_or_goto
6108#undef po_imm_or_fail
5287ad62 6109#undef po_scalar_or_fail
c19d1205
ZW
6110\f
6111/* Shorthand macro for instruction encoding functions issuing errors. */
6112#define constraint(expr, err) do { \
6113 if (expr) \
6114 { \
6115 inst.error = err; \
6116 return; \
6117 } \
6118} while (0)
6119
6120/* Functions for operand encoding. ARM, then Thumb. */
6121
6122#define rotate_left(v, n) (v << n | v >> (32 - n))
6123
6124/* If VAL can be encoded in the immediate field of an ARM instruction,
6125 return the encoded form. Otherwise, return FAIL. */
6126
6127static unsigned int
6128encode_arm_immediate (unsigned int val)
09d92015 6129{
c19d1205
ZW
6130 unsigned int a, i;
6131
6132 for (i = 0; i < 32; i += 2)
6133 if ((a = rotate_left (val, i)) <= 0xff)
6134 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6135
6136 return FAIL;
09d92015
MM
6137}
6138
c19d1205
ZW
6139/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6140 return the encoded form. Otherwise, return FAIL. */
6141static unsigned int
6142encode_thumb32_immediate (unsigned int val)
09d92015 6143{
c19d1205 6144 unsigned int a, i;
09d92015 6145
9c3c69f2 6146 if (val <= 0xff)
c19d1205 6147 return val;
a737bd4d 6148
9c3c69f2 6149 for (i = 1; i <= 24; i++)
09d92015 6150 {
9c3c69f2
PB
6151 a = val >> i;
6152 if ((val & ~(0xff << i)) == 0)
6153 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 6154 }
a737bd4d 6155
c19d1205
ZW
6156 a = val & 0xff;
6157 if (val == ((a << 16) | a))
6158 return 0x100 | a;
6159 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6160 return 0x300 | a;
09d92015 6161
c19d1205
ZW
6162 a = val & 0xff00;
6163 if (val == ((a << 16) | a))
6164 return 0x200 | (a >> 8);
a737bd4d 6165
c19d1205 6166 return FAIL;
09d92015 6167}
5287ad62 6168/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM
6169
6170static void
5287ad62
JB
6171encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6172{
6173 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6174 && reg > 15)
6175 {
b1cc4aeb 6176 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
5287ad62
JB
6177 {
6178 if (thumb_mode)
6179 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
b1cc4aeb 6180 fpu_vfp_ext_d32);
5287ad62
JB
6181 else
6182 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
b1cc4aeb 6183 fpu_vfp_ext_d32);
5287ad62
JB
6184 }
6185 else
6186 {
dcbf9037 6187 first_error (_("D register out of range for selected VFP version"));
5287ad62
JB
6188 return;
6189 }
6190 }
6191
c19d1205 6192 switch (pos)
09d92015 6193 {
c19d1205
ZW
6194 case VFP_REG_Sd:
6195 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6196 break;
6197
6198 case VFP_REG_Sn:
6199 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6200 break;
6201
6202 case VFP_REG_Sm:
6203 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6204 break;
6205
5287ad62
JB
6206 case VFP_REG_Dd:
6207 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6208 break;
5f4273c7 6209
5287ad62
JB
6210 case VFP_REG_Dn:
6211 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6212 break;
5f4273c7 6213
5287ad62
JB
6214 case VFP_REG_Dm:
6215 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6216 break;
6217
c19d1205
ZW
6218 default:
6219 abort ();
09d92015 6220 }
09d92015
MM
6221}
6222
c19d1205 6223/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 6224 if any, is handled by md_apply_fix. */
09d92015 6225static void
c19d1205 6226encode_arm_shift (int i)
09d92015 6227{
c19d1205
ZW
6228 if (inst.operands[i].shift_kind == SHIFT_RRX)
6229 inst.instruction |= SHIFT_ROR << 5;
6230 else
09d92015 6231 {
c19d1205
ZW
6232 inst.instruction |= inst.operands[i].shift_kind << 5;
6233 if (inst.operands[i].immisreg)
6234 {
6235 inst.instruction |= SHIFT_BY_REG;
6236 inst.instruction |= inst.operands[i].imm << 8;
6237 }
6238 else
6239 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 6240 }
c19d1205 6241}
09d92015 6242
c19d1205
ZW
6243static void
6244encode_arm_shifter_operand (int i)
6245{
6246 if (inst.operands[i].isreg)
09d92015 6247 {
c19d1205
ZW
6248 inst.instruction |= inst.operands[i].reg;
6249 encode_arm_shift (i);
09d92015 6250 }
c19d1205
ZW
6251 else
6252 inst.instruction |= INST_IMMEDIATE;
09d92015
MM
6253}
6254
c19d1205 6255/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 6256static void
c19d1205 6257encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 6258{
c19d1205
ZW
6259 assert (inst.operands[i].isreg);
6260 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 6261
c19d1205 6262 if (inst.operands[i].preind)
09d92015 6263 {
c19d1205
ZW
6264 if (is_t)
6265 {
6266 inst.error = _("instruction does not accept preindexed addressing");
6267 return;
6268 }
6269 inst.instruction |= PRE_INDEX;
6270 if (inst.operands[i].writeback)
6271 inst.instruction |= WRITE_BACK;
09d92015 6272
c19d1205
ZW
6273 }
6274 else if (inst.operands[i].postind)
6275 {
6276 assert (inst.operands[i].writeback);
6277 if (is_t)
6278 inst.instruction |= WRITE_BACK;
6279 }
6280 else /* unindexed - only for coprocessor */
09d92015 6281 {
c19d1205 6282 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM
6283 return;
6284 }
6285
c19d1205
ZW
6286 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6287 && (((inst.instruction & 0x000f0000) >> 16)
6288 == ((inst.instruction & 0x0000f000) >> 12)))
6289 as_warn ((inst.instruction & LOAD_BIT)
6290 ? _("destination register same as write-back base")
6291 : _("source register same as write-back base"));
09d92015
MM
6292}
6293
c19d1205
ZW
6294/* inst.operands[i] was set up by parse_address. Encode it into an
6295 ARM-format mode 2 load or store instruction. If is_t is true,
6296 reject forms that cannot be used with a T instruction (i.e. not
6297 post-indexed). */
a737bd4d 6298static void
c19d1205 6299encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 6300{
c19d1205 6301 encode_arm_addr_mode_common (i, is_t);
a737bd4d 6302
c19d1205 6303 if (inst.operands[i].immisreg)
09d92015 6304 {
c19d1205
ZW
6305 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
6306 inst.instruction |= inst.operands[i].imm;
6307 if (!inst.operands[i].negative)
6308 inst.instruction |= INDEX_UP;
6309 if (inst.operands[i].shifted)
6310 {
6311 if (inst.operands[i].shift_kind == SHIFT_RRX)
6312 inst.instruction |= SHIFT_ROR << 5;
6313 else
6314 {
6315 inst.instruction |= inst.operands[i].shift_kind << 5;
6316 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6317 }
6318 }
09d92015 6319 }
c19d1205 6320 else /* immediate offset in inst.reloc */
09d92015 6321 {
c19d1205
ZW
6322 if (inst.reloc.type == BFD_RELOC_UNUSED)
6323 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
09d92015 6324 }
09d92015
MM
6325}
6326
c19d1205
ZW
6327/* inst.operands[i] was set up by parse_address. Encode it into an
6328 ARM-format mode 3 load or store instruction. Reject forms that
6329 cannot be used with such instructions. If is_t is true, reject
6330 forms that cannot be used with a T instruction (i.e. not
6331 post-indexed). */
6332static void
6333encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 6334{
c19d1205 6335 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 6336 {
c19d1205
ZW
6337 inst.error = _("instruction does not accept scaled register index");
6338 return;
09d92015 6339 }
a737bd4d 6340
c19d1205 6341 encode_arm_addr_mode_common (i, is_t);
a737bd4d 6342
c19d1205
ZW
6343 if (inst.operands[i].immisreg)
6344 {
6345 inst.instruction |= inst.operands[i].imm;
6346 if (!inst.operands[i].negative)
6347 inst.instruction |= INDEX_UP;
6348 }
6349 else /* immediate offset in inst.reloc */
6350 {
6351 inst.instruction |= HWOFFSET_IMM;
6352 if (inst.reloc.type == BFD_RELOC_UNUSED)
6353 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
c19d1205 6354 }
a737bd4d
NC
6355}
6356
c19d1205
ZW
6357/* inst.operands[i] was set up by parse_address. Encode it into an
6358 ARM-format instruction. Reject all forms which cannot be encoded
6359 into a coprocessor load/store instruction. If wb_ok is false,
6360 reject use of writeback; if unind_ok is false, reject use of
6361 unindexed addressing. If reloc_override is not 0, use it instead
4962c51a
MS
6362 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6363 (in which case it is preserved). */
09d92015 6364
c19d1205
ZW
6365static int
6366encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
09d92015 6367{
c19d1205 6368 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 6369
c19d1205 6370 assert (!(inst.operands[i].preind && inst.operands[i].postind));
09d92015 6371
c19d1205 6372 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
09d92015 6373 {
c19d1205
ZW
6374 assert (!inst.operands[i].writeback);
6375 if (!unind_ok)
6376 {
6377 inst.error = _("instruction does not support unindexed addressing");
6378 return FAIL;
6379 }
6380 inst.instruction |= inst.operands[i].imm;
6381 inst.instruction |= INDEX_UP;
6382 return SUCCESS;
09d92015 6383 }
a737bd4d 6384
c19d1205
ZW
6385 if (inst.operands[i].preind)
6386 inst.instruction |= PRE_INDEX;
a737bd4d 6387
c19d1205 6388 if (inst.operands[i].writeback)
09d92015 6389 {
c19d1205
ZW
6390 if (inst.operands[i].reg == REG_PC)
6391 {
6392 inst.error = _("pc may not be used with write-back");
6393 return FAIL;
6394 }
6395 if (!wb_ok)
6396 {
6397 inst.error = _("instruction does not support writeback");
6398 return FAIL;
6399 }
6400 inst.instruction |= WRITE_BACK;
09d92015 6401 }
a737bd4d 6402
c19d1205
ZW
6403 if (reloc_override)
6404 inst.reloc.type = reloc_override;
4962c51a
MS
6405 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6406 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6407 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6408 {
6409 if (thumb_mode)
6410 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6411 else
6412 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6413 }
6414
c19d1205
ZW
6415 return SUCCESS;
6416}
a737bd4d 6417
c19d1205
ZW
6418/* inst.reloc.exp describes an "=expr" load pseudo-operation.
6419 Determine whether it can be performed with a move instruction; if
6420 it can, convert inst.instruction to that move instruction and
6421 return 1; if it can't, convert inst.instruction to a literal-pool
6422 load and return 0. If this is not a valid thing to do in the
6423 current context, set inst.error and return 1.
a737bd4d 6424
c19d1205
ZW
6425 inst.operands[i] describes the destination register. */
6426
6427static int
6428move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6429{
53365c0d
PB
6430 unsigned long tbit;
6431
6432 if (thumb_p)
6433 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6434 else
6435 tbit = LOAD_BIT;
6436
6437 if ((inst.instruction & tbit) == 0)
09d92015 6438 {
c19d1205
ZW
6439 inst.error = _("invalid pseudo operation");
6440 return 1;
09d92015 6441 }
c19d1205 6442 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
09d92015
MM
6443 {
6444 inst.error = _("constant expression expected");
c19d1205 6445 return 1;
09d92015 6446 }
c19d1205 6447 if (inst.reloc.exp.X_op == O_constant)
09d92015 6448 {
c19d1205
ZW
6449 if (thumb_p)
6450 {
53365c0d 6451 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
c19d1205
ZW
6452 {
6453 /* This can be done with a mov(1) instruction. */
6454 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6455 inst.instruction |= inst.reloc.exp.X_add_number;
6456 return 1;
6457 }
6458 }
6459 else
6460 {
6461 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6462 if (value != FAIL)
6463 {
6464 /* This can be done with a mov instruction. */
6465 inst.instruction &= LITERAL_MASK;
6466 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6467 inst.instruction |= value & 0xfff;
6468 return 1;
6469 }
09d92015 6470
c19d1205
ZW
6471 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6472 if (value != FAIL)
6473 {
6474 /* This can be done with a mvn instruction. */
6475 inst.instruction &= LITERAL_MASK;
6476 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6477 inst.instruction |= value & 0xfff;
6478 return 1;
6479 }
6480 }
09d92015
MM
6481 }
6482
c19d1205
ZW
6483 if (add_to_lit_pool () == FAIL)
6484 {
6485 inst.error = _("literal pool insertion failed");
6486 return 1;
6487 }
6488 inst.operands[1].reg = REG_PC;
6489 inst.operands[1].isreg = 1;
6490 inst.operands[1].preind = 1;
6491 inst.reloc.pc_rel = 1;
6492 inst.reloc.type = (thumb_p
6493 ? BFD_RELOC_ARM_THUMB_OFFSET
6494 : (mode_3
6495 ? BFD_RELOC_ARM_HWLITERAL
6496 : BFD_RELOC_ARM_LITERAL));
6497 return 0;
09d92015
MM
6498}
6499
5f4273c7 6500/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW
6501 First some generics; their names are taken from the conventional
6502 bit positions for register arguments in ARM format instructions. */
09d92015 6503
a737bd4d 6504static void
c19d1205 6505do_noargs (void)
09d92015 6506{
c19d1205 6507}
a737bd4d 6508
c19d1205
ZW
6509static void
6510do_rd (void)
6511{
6512 inst.instruction |= inst.operands[0].reg << 12;
6513}
a737bd4d 6514
c19d1205
ZW
6515static void
6516do_rd_rm (void)
6517{
6518 inst.instruction |= inst.operands[0].reg << 12;
6519 inst.instruction |= inst.operands[1].reg;
6520}
09d92015 6521
c19d1205
ZW
6522static void
6523do_rd_rn (void)
6524{
6525 inst.instruction |= inst.operands[0].reg << 12;
6526 inst.instruction |= inst.operands[1].reg << 16;
6527}
a737bd4d 6528
c19d1205
ZW
6529static void
6530do_rn_rd (void)
6531{
6532 inst.instruction |= inst.operands[0].reg << 16;
6533 inst.instruction |= inst.operands[1].reg << 12;
6534}
09d92015 6535
c19d1205
ZW
6536static void
6537do_rd_rm_rn (void)
6538{
9a64e435 6539 unsigned Rn = inst.operands[2].reg;
708587a4 6540 /* Enforce restrictions on SWP instruction. */
9a64e435
PB
6541 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
6542 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6543 _("Rn must not overlap other operands"));
c19d1205
ZW
6544 inst.instruction |= inst.operands[0].reg << 12;
6545 inst.instruction |= inst.operands[1].reg;
9a64e435 6546 inst.instruction |= Rn << 16;
c19d1205 6547}
09d92015 6548
c19d1205
ZW
6549static void
6550do_rd_rn_rm (void)
6551{
6552 inst.instruction |= inst.operands[0].reg << 12;
6553 inst.instruction |= inst.operands[1].reg << 16;
6554 inst.instruction |= inst.operands[2].reg;
6555}
a737bd4d 6556
c19d1205
ZW
6557static void
6558do_rm_rd_rn (void)
6559{
6560 inst.instruction |= inst.operands[0].reg;
6561 inst.instruction |= inst.operands[1].reg << 12;
6562 inst.instruction |= inst.operands[2].reg << 16;
6563}
09d92015 6564
c19d1205
ZW
6565static void
6566do_imm0 (void)
6567{
6568 inst.instruction |= inst.operands[0].imm;
6569}
09d92015 6570
c19d1205
ZW
6571static void
6572do_rd_cpaddr (void)
6573{
6574 inst.instruction |= inst.operands[0].reg << 12;
6575 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 6576}
a737bd4d 6577
c19d1205
ZW
6578/* ARM instructions, in alphabetical order by function name (except
6579 that wrapper functions appear immediately after the function they
6580 wrap). */
09d92015 6581
c19d1205
ZW
6582/* This is a pseudo-op of the form "adr rd, label" to be converted
6583 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM
6584
6585static void
c19d1205 6586do_adr (void)
09d92015 6587{
c19d1205 6588 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 6589
c19d1205
ZW
6590 /* Frag hacking will turn this into a sub instruction if the offset turns
6591 out to be negative. */
6592 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
c19d1205 6593 inst.reloc.pc_rel = 1;
2fc8bdac 6594 inst.reloc.exp.X_add_number -= 8;
c19d1205 6595}
b99bd4ef 6596
c19d1205
ZW
6597/* This is a pseudo-op of the form "adrl rd, label" to be converted
6598 into a relative address of the form:
6599 add rd, pc, #low(label-.-8)"
6600 add rd, rd, #high(label-.-8)" */
b99bd4ef 6601
c19d1205
ZW
6602static void
6603do_adrl (void)
6604{
6605 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 6606
c19d1205
ZW
6607 /* Frag hacking will turn this into a sub instruction if the offset turns
6608 out to be negative. */
6609 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
c19d1205
ZW
6610 inst.reloc.pc_rel = 1;
6611 inst.size = INSN_SIZE * 2;
2fc8bdac 6612 inst.reloc.exp.X_add_number -= 8;
b99bd4ef
NC
6613}
6614
b99bd4ef 6615static void
c19d1205 6616do_arit (void)
b99bd4ef 6617{
c19d1205
ZW
6618 if (!inst.operands[1].present)
6619 inst.operands[1].reg = inst.operands[0].reg;
6620 inst.instruction |= inst.operands[0].reg << 12;
6621 inst.instruction |= inst.operands[1].reg << 16;
6622 encode_arm_shifter_operand (2);
6623}
b99bd4ef 6624
62b3e311
PB
6625static void
6626do_barrier (void)
6627{
6628 if (inst.operands[0].present)
6629 {
6630 constraint ((inst.instruction & 0xf0) != 0x40
6631 && inst.operands[0].imm != 0xf,
bd3ba5d1 6632 _("bad barrier type"));
62b3e311
PB
6633 inst.instruction |= inst.operands[0].imm;
6634 }
6635 else
6636 inst.instruction |= 0xf;
6637}
6638
c19d1205
ZW
6639static void
6640do_bfc (void)
6641{
6642 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6643 constraint (msb > 32, _("bit-field extends past end of register"));
6644 /* The instruction encoding stores the LSB and MSB,
6645 not the LSB and width. */
6646 inst.instruction |= inst.operands[0].reg << 12;
6647 inst.instruction |= inst.operands[1].imm << 7;
6648 inst.instruction |= (msb - 1) << 16;
6649}
b99bd4ef 6650
c19d1205
ZW
6651static void
6652do_bfi (void)
6653{
6654 unsigned int msb;
b99bd4ef 6655
c19d1205
ZW
6656 /* #0 in second position is alternative syntax for bfc, which is
6657 the same instruction but with REG_PC in the Rm field. */
6658 if (!inst.operands[1].isreg)
6659 inst.operands[1].reg = REG_PC;
b99bd4ef 6660
c19d1205
ZW
6661 msb = inst.operands[2].imm + inst.operands[3].imm;
6662 constraint (msb > 32, _("bit-field extends past end of register"));
6663 /* The instruction encoding stores the LSB and MSB,
6664 not the LSB and width. */
6665 inst.instruction |= inst.operands[0].reg << 12;
6666 inst.instruction |= inst.operands[1].reg;
6667 inst.instruction |= inst.operands[2].imm << 7;
6668 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC
6669}
6670
b99bd4ef 6671static void
c19d1205 6672do_bfx (void)
b99bd4ef 6673{
c19d1205
ZW
6674 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6675 _("bit-field extends past end of register"));
6676 inst.instruction |= inst.operands[0].reg << 12;
6677 inst.instruction |= inst.operands[1].reg;
6678 inst.instruction |= inst.operands[2].imm << 7;
6679 inst.instruction |= (inst.operands[3].imm - 1) << 16;
6680}
09d92015 6681
c19d1205
ZW
6682/* ARM V5 breakpoint instruction (argument parse)
6683 BKPT <16 bit unsigned immediate>
6684 Instruction is not conditional.
6685 The bit pattern given in insns[] has the COND_ALWAYS condition,
6686 and it is an error if the caller tried to override that. */
b99bd4ef 6687
c19d1205
ZW
6688static void
6689do_bkpt (void)
6690{
6691 /* Top 12 of 16 bits to bits 19:8. */
6692 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 6693
c19d1205
ZW
6694 /* Bottom 4 of 16 bits to bits 3:0. */
6695 inst.instruction |= inst.operands[0].imm & 0xf;
6696}
09d92015 6697
c19d1205
ZW
6698static void
6699encode_branch (int default_reloc)
6700{
6701 if (inst.operands[0].hasreloc)
6702 {
6703 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6704 _("the only suffix valid here is '(plt)'"));
6705 inst.reloc.type = BFD_RELOC_ARM_PLT32;
c19d1205 6706 }
b99bd4ef 6707 else
c19d1205
ZW
6708 {
6709 inst.reloc.type = default_reloc;
c19d1205 6710 }
2fc8bdac 6711 inst.reloc.pc_rel = 1;
b99bd4ef
NC
6712}
6713
b99bd4ef 6714static void
c19d1205 6715do_branch (void)
b99bd4ef 6716{
39b41c9c
PB
6717#ifdef OBJ_ELF
6718 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6719 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6720 else
6721#endif
6722 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6723}
6724
6725static void
6726do_bl (void)
6727{
6728#ifdef OBJ_ELF
6729 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6730 {
6731 if (inst.cond == COND_ALWAYS)
6732 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6733 else
6734 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6735 }
6736 else
6737#endif
6738 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 6739}
b99bd4ef 6740
c19d1205
ZW
6741/* ARM V5 branch-link-exchange instruction (argument parse)
6742 BLX <target_addr> ie BLX(1)
6743 BLX{<condition>} <Rm> ie BLX(2)
6744 Unfortunately, there are two different opcodes for this mnemonic.
6745 So, the insns[].value is not used, and the code here zaps values
6746 into inst.instruction.
6747 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 6748
c19d1205
ZW
6749static void
6750do_blx (void)
6751{
6752 if (inst.operands[0].isreg)
b99bd4ef 6753 {
c19d1205
ZW
6754 /* Arg is a register; the opcode provided by insns[] is correct.
6755 It is not illegal to do "blx pc", just useless. */
6756 if (inst.operands[0].reg == REG_PC)
6757 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 6758
c19d1205
ZW
6759 inst.instruction |= inst.operands[0].reg;
6760 }
6761 else
b99bd4ef 6762 {
c19d1205
ZW
6763 /* Arg is an address; this instruction cannot be executed
6764 conditionally, and the opcode must be adjusted. */
6765 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 6766 inst.instruction = 0xfa000000;
39b41c9c
PB
6767#ifdef OBJ_ELF
6768 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6769 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6770 else
6771#endif
6772 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 6773 }
c19d1205
ZW
6774}
6775
6776static void
6777do_bx (void)
6778{
845b51d6
PB
6779 bfd_boolean want_reloc;
6780
c19d1205
ZW
6781 if (inst.operands[0].reg == REG_PC)
6782 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 6783
c19d1205 6784 inst.instruction |= inst.operands[0].reg;
845b51d6
PB
6785 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6786 it is for ARMv4t or earlier. */
6787 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
6788 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
6789 want_reloc = TRUE;
6790
5ad34203 6791#ifdef OBJ_ELF
845b51d6 6792 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 6793#endif
584206db 6794 want_reloc = FALSE;
845b51d6
PB
6795
6796 if (want_reloc)
6797 inst.reloc.type = BFD_RELOC_ARM_V4BX;
09d92015
MM
6798}
6799
c19d1205
ZW
6800
6801/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC
6802
6803static void
c19d1205 6804do_bxj (void)
a737bd4d 6805{
c19d1205
ZW
6806 if (inst.operands[0].reg == REG_PC)
6807 as_tsktsk (_("use of r15 in bxj is not really useful"));
6808
6809 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC
6810}
6811
c19d1205
ZW
6812/* Co-processor data operation:
6813 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6814 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6815static void
6816do_cdp (void)
6817{
6818 inst.instruction |= inst.operands[0].reg << 8;
6819 inst.instruction |= inst.operands[1].imm << 20;
6820 inst.instruction |= inst.operands[2].reg << 12;
6821 inst.instruction |= inst.operands[3].reg << 16;
6822 inst.instruction |= inst.operands[4].reg;
6823 inst.instruction |= inst.operands[5].imm << 5;
6824}
a737bd4d
NC
6825
6826static void
c19d1205 6827do_cmp (void)
a737bd4d 6828{
c19d1205
ZW
6829 inst.instruction |= inst.operands[0].reg << 16;
6830 encode_arm_shifter_operand (1);
a737bd4d
NC
6831}
6832
c19d1205
ZW
6833/* Transfer between coprocessor and ARM registers.
6834 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6835 MRC2
6836 MCR{cond}
6837 MCR2
6838
6839 No special properties. */
09d92015
MM
6840
6841static void
c19d1205 6842do_co_reg (void)
09d92015 6843{
c19d1205
ZW
6844 inst.instruction |= inst.operands[0].reg << 8;
6845 inst.instruction |= inst.operands[1].imm << 21;
6846 inst.instruction |= inst.operands[2].reg << 12;
6847 inst.instruction |= inst.operands[3].reg << 16;
6848 inst.instruction |= inst.operands[4].reg;
6849 inst.instruction |= inst.operands[5].imm << 5;
6850}
09d92015 6851
c19d1205
ZW
6852/* Transfer between coprocessor register and pair of ARM registers.
6853 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6854 MCRR2
6855 MRRC{cond}
6856 MRRC2
b99bd4ef 6857
c19d1205 6858 Two XScale instructions are special cases of these:
09d92015 6859
c19d1205
ZW
6860 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6861 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 6862
5f4273c7 6863 Result unpredictable if Rd or Rn is R15. */
a737bd4d 6864
c19d1205
ZW
6865static void
6866do_co_reg2c (void)
6867{
6868 inst.instruction |= inst.operands[0].reg << 8;
6869 inst.instruction |= inst.operands[1].imm << 4;
6870 inst.instruction |= inst.operands[2].reg << 12;
6871 inst.instruction |= inst.operands[3].reg << 16;
6872 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC
6873}
6874
c19d1205
ZW
6875static void
6876do_cpsi (void)
6877{
6878 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB
6879 if (inst.operands[1].present)
6880 {
6881 inst.instruction |= CPSI_MMOD;
6882 inst.instruction |= inst.operands[1].imm;
6883 }
c19d1205 6884}
b99bd4ef 6885
62b3e311
PB
6886static void
6887do_dbg (void)
6888{
6889 inst.instruction |= inst.operands[0].imm;
6890}
6891
b99bd4ef 6892static void
c19d1205 6893do_it (void)
b99bd4ef 6894{
c19d1205
ZW
6895 /* There is no IT instruction in ARM mode. We
6896 process it but do not generate code for it. */
6897 inst.size = 0;
09d92015 6898}
b99bd4ef 6899
09d92015 6900static void
c19d1205 6901do_ldmstm (void)
ea6ef066 6902{
c19d1205
ZW
6903 int base_reg = inst.operands[0].reg;
6904 int range = inst.operands[1].imm;
ea6ef066 6905
c19d1205
ZW
6906 inst.instruction |= base_reg << 16;
6907 inst.instruction |= range;
ea6ef066 6908
c19d1205
ZW
6909 if (inst.operands[1].writeback)
6910 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 6911
c19d1205 6912 if (inst.operands[0].writeback)
ea6ef066 6913 {
c19d1205
ZW
6914 inst.instruction |= WRITE_BACK;
6915 /* Check for unpredictable uses of writeback. */
6916 if (inst.instruction & LOAD_BIT)
09d92015 6917 {
c19d1205
ZW
6918 /* Not allowed in LDM type 2. */
6919 if ((inst.instruction & LDM_TYPE_2_OR_3)
6920 && ((range & (1 << REG_PC)) == 0))
6921 as_warn (_("writeback of base register is UNPREDICTABLE"));
6922 /* Only allowed if base reg not in list for other types. */
6923 else if (range & (1 << base_reg))
6924 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6925 }
6926 else /* STM. */
6927 {
6928 /* Not allowed for type 2. */
6929 if (inst.instruction & LDM_TYPE_2_OR_3)
6930 as_warn (_("writeback of base register is UNPREDICTABLE"));
6931 /* Only allowed if base reg not in list, or first in list. */
6932 else if ((range & (1 << base_reg))
6933 && (range & ((1 << base_reg) - 1)))
6934 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 6935 }
ea6ef066 6936 }
a737bd4d
NC
6937}
6938
c19d1205
ZW
6939/* ARMv5TE load-consecutive (argument parse)
6940 Mode is like LDRH.
6941
6942 LDRccD R, mode
6943 STRccD R, mode. */
6944
a737bd4d 6945static void
c19d1205 6946do_ldrd (void)
a737bd4d 6947{
c19d1205
ZW
6948 constraint (inst.operands[0].reg % 2 != 0,
6949 _("first destination register must be even"));
6950 constraint (inst.operands[1].present
6951 && inst.operands[1].reg != inst.operands[0].reg + 1,
6952 _("can only load two consecutive registers"));
6953 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6954 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 6955
c19d1205
ZW
6956 if (!inst.operands[1].present)
6957 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 6958
c19d1205 6959 if (inst.instruction & LOAD_BIT)
a737bd4d 6960 {
c19d1205
ZW
6961 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6962 register and the first register written; we have to diagnose
6963 overlap between the base and the second register written here. */
ea6ef066 6964
c19d1205
ZW
6965 if (inst.operands[2].reg == inst.operands[1].reg
6966 && (inst.operands[2].writeback || inst.operands[2].postind))
6967 as_warn (_("base register written back, and overlaps "
6968 "second destination register"));
b05fe5cf 6969
c19d1205
ZW
6970 /* For an index-register load, the index register must not overlap the
6971 destination (even if not write-back). */
6972 else if (inst.operands[2].immisreg
ca3f61f7
NC
6973 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6974 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
c19d1205 6975 as_warn (_("index register overlaps destination register"));
b05fe5cf 6976 }
c19d1205
ZW
6977
6978 inst.instruction |= inst.operands[0].reg << 12;
6979 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW
6980}
6981
6982static void
c19d1205 6983do_ldrex (void)
b05fe5cf 6984{
c19d1205
ZW
6985 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6986 || inst.operands[1].postind || inst.operands[1].writeback
6987 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC
6988 || inst.operands[1].negative
6989 /* This can arise if the programmer has written
6990 strex rN, rM, foo
6991 or if they have mistakenly used a register name as the last
6992 operand, eg:
6993 strex rN, rM, rX
6994 It is very difficult to distinguish between these two cases
6995 because "rX" might actually be a label. ie the register
6996 name has been occluded by a symbol of the same name. So we
6997 just generate a general 'bad addressing mode' type error
6998 message and leave it up to the programmer to discover the
6999 true cause and fix their mistake. */
7000 || (inst.operands[1].reg == REG_PC),
7001 BAD_ADDR_MODE);
b05fe5cf 7002
c19d1205
ZW
7003 constraint (inst.reloc.exp.X_op != O_constant
7004 || inst.reloc.exp.X_add_number != 0,
7005 _("offset must be zero in ARM encoding"));
b05fe5cf 7006
c19d1205
ZW
7007 inst.instruction |= inst.operands[0].reg << 12;
7008 inst.instruction |= inst.operands[1].reg << 16;
7009 inst.reloc.type = BFD_RELOC_UNUSED;
b05fe5cf
ZW
7010}
7011
7012static void
c19d1205 7013do_ldrexd (void)
b05fe5cf 7014{
c19d1205
ZW
7015 constraint (inst.operands[0].reg % 2 != 0,
7016 _("even register required"));
7017 constraint (inst.operands[1].present
7018 && inst.operands[1].reg != inst.operands[0].reg + 1,
7019 _("can only load two consecutive registers"));
7020 /* If op 1 were present and equal to PC, this function wouldn't
7021 have been called in the first place. */
7022 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 7023
c19d1205
ZW
7024 inst.instruction |= inst.operands[0].reg << 12;
7025 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW
7026}
7027
7028static void
c19d1205 7029do_ldst (void)
b05fe5cf 7030{
c19d1205
ZW
7031 inst.instruction |= inst.operands[0].reg << 12;
7032 if (!inst.operands[1].isreg)
7033 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
b05fe5cf 7034 return;
c19d1205 7035 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
7036}
7037
7038static void
c19d1205 7039do_ldstt (void)
b05fe5cf 7040{
c19d1205
ZW
7041 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7042 reject [Rn,...]. */
7043 if (inst.operands[1].preind)
b05fe5cf 7044 {
bd3ba5d1
NC
7045 constraint (inst.reloc.exp.X_op != O_constant
7046 || inst.reloc.exp.X_add_number != 0,
c19d1205 7047 _("this instruction requires a post-indexed address"));
b05fe5cf 7048
c19d1205
ZW
7049 inst.operands[1].preind = 0;
7050 inst.operands[1].postind = 1;
7051 inst.operands[1].writeback = 1;
b05fe5cf 7052 }
c19d1205
ZW
7053 inst.instruction |= inst.operands[0].reg << 12;
7054 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7055}
b05fe5cf 7056
c19d1205 7057/* Halfword and signed-byte load/store operations. */
b05fe5cf 7058
c19d1205
ZW
7059static void
7060do_ldstv4 (void)
7061{
7062 inst.instruction |= inst.operands[0].reg << 12;
7063 if (!inst.operands[1].isreg)
7064 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
b05fe5cf 7065 return;
c19d1205 7066 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW
7067}
7068
7069static void
c19d1205 7070do_ldsttv4 (void)
b05fe5cf 7071{
c19d1205
ZW
7072 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7073 reject [Rn,...]. */
7074 if (inst.operands[1].preind)
b05fe5cf 7075 {
bd3ba5d1
NC
7076 constraint (inst.reloc.exp.X_op != O_constant
7077 || inst.reloc.exp.X_add_number != 0,
c19d1205 7078 _("this instruction requires a post-indexed address"));
b05fe5cf 7079
c19d1205
ZW
7080 inst.operands[1].preind = 0;
7081 inst.operands[1].postind = 1;
7082 inst.operands[1].writeback = 1;
b05fe5cf 7083 }
c19d1205
ZW
7084 inst.instruction |= inst.operands[0].reg << 12;
7085 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7086}
b05fe5cf 7087
c19d1205
ZW
7088/* Co-processor register load/store.
7089 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7090static void
7091do_lstc (void)
7092{
7093 inst.instruction |= inst.operands[0].reg << 8;
7094 inst.instruction |= inst.operands[1].reg << 12;
7095 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW
7096}
7097
b05fe5cf 7098static void
c19d1205 7099do_mlas (void)
b05fe5cf 7100{
8fb9d7b9 7101 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 7102 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 7103 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 7104 && !(inst.instruction & 0x00400000))
8fb9d7b9 7105 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 7106
c19d1205
ZW
7107 inst.instruction |= inst.operands[0].reg << 16;
7108 inst.instruction |= inst.operands[1].reg;
7109 inst.instruction |= inst.operands[2].reg << 8;
7110 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 7111}
b05fe5cf 7112
c19d1205
ZW
7113static void
7114do_mov (void)
7115{
7116 inst.instruction |= inst.operands[0].reg << 12;
7117 encode_arm_shifter_operand (1);
7118}
b05fe5cf 7119
c19d1205
ZW
7120/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7121static void
7122do_mov16 (void)
7123{
b6895b4f
PB
7124 bfd_vma imm;
7125 bfd_boolean top;
7126
7127 top = (inst.instruction & 0x00400000) != 0;
7128 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7129 _(":lower16: not allowed this instruction"));
7130 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7131 _(":upper16: not allowed instruction"));
c19d1205 7132 inst.instruction |= inst.operands[0].reg << 12;
b6895b4f
PB
7133 if (inst.reloc.type == BFD_RELOC_UNUSED)
7134 {
7135 imm = inst.reloc.exp.X_add_number;
7136 /* The value is in two pieces: 0:11, 16:19. */
7137 inst.instruction |= (imm & 0x00000fff);
7138 inst.instruction |= (imm & 0x0000f000) << 4;
7139 }
b05fe5cf 7140}
b99bd4ef 7141
037e8744
JB
7142static void do_vfp_nsyn_opcode (const char *);
7143
7144static int
7145do_vfp_nsyn_mrs (void)
7146{
7147 if (inst.operands[0].isvec)
7148 {
7149 if (inst.operands[1].reg != 1)
7150 first_error (_("operand 1 must be FPSCR"));
7151 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7152 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7153 do_vfp_nsyn_opcode ("fmstat");
7154 }
7155 else if (inst.operands[1].isvec)
7156 do_vfp_nsyn_opcode ("fmrx");
7157 else
7158 return FAIL;
5f4273c7 7159
037e8744
JB
7160 return SUCCESS;
7161}
7162
7163static int
7164do_vfp_nsyn_msr (void)
7165{
7166 if (inst.operands[0].isvec)
7167 do_vfp_nsyn_opcode ("fmxr");
7168 else
7169 return FAIL;
7170
7171 return SUCCESS;
7172}
7173
b99bd4ef 7174static void
c19d1205 7175do_mrs (void)
b99bd4ef 7176{
037e8744
JB
7177 if (do_vfp_nsyn_mrs () == SUCCESS)
7178 return;
7179
c19d1205
ZW
7180 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7181 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7182 != (PSR_c|PSR_f),
7183 _("'CPSR' or 'SPSR' expected"));
7184 inst.instruction |= inst.operands[0].reg << 12;
7185 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7186}
b99bd4ef 7187
c19d1205
ZW
7188/* Two possible forms:
7189 "{C|S}PSR_<field>, Rm",
7190 "{C|S}PSR_f, #expression". */
b99bd4ef 7191
c19d1205
ZW
7192static void
7193do_msr (void)
7194{
037e8744
JB
7195 if (do_vfp_nsyn_msr () == SUCCESS)
7196 return;
7197
c19d1205
ZW
7198 inst.instruction |= inst.operands[0].imm;
7199 if (inst.operands[1].isreg)
7200 inst.instruction |= inst.operands[1].reg;
7201 else
b99bd4ef 7202 {
c19d1205
ZW
7203 inst.instruction |= INST_IMMEDIATE;
7204 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7205 inst.reloc.pc_rel = 0;
b99bd4ef 7206 }
b99bd4ef
NC
7207}
7208
c19d1205
ZW
7209static void
7210do_mul (void)
a737bd4d 7211{
c19d1205
ZW
7212 if (!inst.operands[2].present)
7213 inst.operands[2].reg = inst.operands[0].reg;
7214 inst.instruction |= inst.operands[0].reg << 16;
7215 inst.instruction |= inst.operands[1].reg;
7216 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 7217
8fb9d7b9
MS
7218 if (inst.operands[0].reg == inst.operands[1].reg
7219 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7220 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC
7221}
7222
c19d1205
ZW
7223/* Long Multiply Parser
7224 UMULL RdLo, RdHi, Rm, Rs
7225 SMULL RdLo, RdHi, Rm, Rs
7226 UMLAL RdLo, RdHi, Rm, Rs
7227 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC
7228
7229static void
c19d1205 7230do_mull (void)
b99bd4ef 7231{
c19d1205
ZW
7232 inst.instruction |= inst.operands[0].reg << 12;
7233 inst.instruction |= inst.operands[1].reg << 16;
7234 inst.instruction |= inst.operands[2].reg;
7235 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 7236
682b27ad
PB
7237 /* rdhi and rdlo must be different. */
7238 if (inst.operands[0].reg == inst.operands[1].reg)
7239 as_tsktsk (_("rdhi and rdlo must be different"));
7240
7241 /* rdhi, rdlo and rm must all be different before armv6. */
7242 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 7243 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 7244 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW
7245 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7246}
b99bd4ef 7247
c19d1205
ZW
7248static void
7249do_nop (void)
7250{
7251 if (inst.operands[0].present)
7252 {
7253 /* Architectural NOP hints are CPSR sets with no bits selected. */
7254 inst.instruction &= 0xf0000000;
7255 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7256 }
b99bd4ef
NC
7257}
7258
c19d1205
ZW
7259/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7260 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7261 Condition defaults to COND_ALWAYS.
7262 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC
7263
7264static void
c19d1205 7265do_pkhbt (void)
b99bd4ef 7266{
c19d1205
ZW
7267 inst.instruction |= inst.operands[0].reg << 12;
7268 inst.instruction |= inst.operands[1].reg << 16;
7269 inst.instruction |= inst.operands[2].reg;
7270 if (inst.operands[3].present)
7271 encode_arm_shift (3);
7272}
b99bd4ef 7273
c19d1205 7274/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 7275
c19d1205
ZW
7276static void
7277do_pkhtb (void)
7278{
7279 if (!inst.operands[3].present)
b99bd4ef 7280 {
c19d1205
ZW
7281 /* If the shift specifier is omitted, turn the instruction
7282 into pkhbt rd, rm, rn. */
7283 inst.instruction &= 0xfff00010;
7284 inst.instruction |= inst.operands[0].reg << 12;
7285 inst.instruction |= inst.operands[1].reg;
7286 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
7287 }
7288 else
7289 {
c19d1205
ZW
7290 inst.instruction |= inst.operands[0].reg << 12;
7291 inst.instruction |= inst.operands[1].reg << 16;
7292 inst.instruction |= inst.operands[2].reg;
7293 encode_arm_shift (3);
b99bd4ef
NC
7294 }
7295}
7296
c19d1205
ZW
7297/* ARMv5TE: Preload-Cache
7298
7299 PLD <addr_mode>
7300
7301 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC
7302
7303static void
c19d1205 7304do_pld (void)
b99bd4ef 7305{
c19d1205
ZW
7306 constraint (!inst.operands[0].isreg,
7307 _("'[' expected after PLD mnemonic"));
7308 constraint (inst.operands[0].postind,
7309 _("post-indexed expression used in preload instruction"));
7310 constraint (inst.operands[0].writeback,
7311 _("writeback used in preload instruction"));
7312 constraint (!inst.operands[0].preind,
7313 _("unindexed addressing used in preload instruction"));
c19d1205
ZW
7314 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7315}
b99bd4ef 7316
62b3e311
PB
7317/* ARMv7: PLI <addr_mode> */
7318static void
7319do_pli (void)
7320{
7321 constraint (!inst.operands[0].isreg,
7322 _("'[' expected after PLI mnemonic"));
7323 constraint (inst.operands[0].postind,
7324 _("post-indexed expression used in preload instruction"));
7325 constraint (inst.operands[0].writeback,
7326 _("writeback used in preload instruction"));
7327 constraint (!inst.operands[0].preind,
7328 _("unindexed addressing used in preload instruction"));
7329 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7330 inst.instruction &= ~PRE_INDEX;
7331}
7332
c19d1205
ZW
7333static void
7334do_push_pop (void)
7335{
7336 inst.operands[1] = inst.operands[0];
7337 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7338 inst.operands[0].isreg = 1;
7339 inst.operands[0].writeback = 1;
7340 inst.operands[0].reg = REG_SP;
7341 do_ldmstm ();
7342}
b99bd4ef 7343
c19d1205
ZW
7344/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7345 word at the specified address and the following word
7346 respectively.
7347 Unconditionally executed.
7348 Error if Rn is R15. */
b99bd4ef 7349
c19d1205
ZW
7350static void
7351do_rfe (void)
7352{
7353 inst.instruction |= inst.operands[0].reg << 16;
7354 if (inst.operands[0].writeback)
7355 inst.instruction |= WRITE_BACK;
7356}
b99bd4ef 7357
c19d1205 7358/* ARM V6 ssat (argument parse). */
b99bd4ef 7359
c19d1205
ZW
7360static void
7361do_ssat (void)
7362{
7363 inst.instruction |= inst.operands[0].reg << 12;
7364 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7365 inst.instruction |= inst.operands[2].reg;
b99bd4ef 7366
c19d1205
ZW
7367 if (inst.operands[3].present)
7368 encode_arm_shift (3);
b99bd4ef
NC
7369}
7370
c19d1205 7371/* ARM V6 usat (argument parse). */
b99bd4ef
NC
7372
7373static void
c19d1205 7374do_usat (void)
b99bd4ef 7375{
c19d1205
ZW
7376 inst.instruction |= inst.operands[0].reg << 12;
7377 inst.instruction |= inst.operands[1].imm << 16;
7378 inst.instruction |= inst.operands[2].reg;
b99bd4ef 7379
c19d1205
ZW
7380 if (inst.operands[3].present)
7381 encode_arm_shift (3);
b99bd4ef
NC
7382}
7383
c19d1205 7384/* ARM V6 ssat16 (argument parse). */
09d92015
MM
7385
7386static void
c19d1205 7387do_ssat16 (void)
09d92015 7388{
c19d1205
ZW
7389 inst.instruction |= inst.operands[0].reg << 12;
7390 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7391 inst.instruction |= inst.operands[2].reg;
09d92015
MM
7392}
7393
c19d1205
ZW
7394static void
7395do_usat16 (void)
a737bd4d 7396{
c19d1205
ZW
7397 inst.instruction |= inst.operands[0].reg << 12;
7398 inst.instruction |= inst.operands[1].imm << 16;
7399 inst.instruction |= inst.operands[2].reg;
7400}
a737bd4d 7401
c19d1205
ZW
7402/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7403 preserving the other bits.
a737bd4d 7404
c19d1205
ZW
7405 setend <endian_specifier>, where <endian_specifier> is either
7406 BE or LE. */
a737bd4d 7407
c19d1205
ZW
7408static void
7409do_setend (void)
7410{
7411 if (inst.operands[0].imm)
7412 inst.instruction |= 0x200;
a737bd4d
NC
7413}
7414
7415static void
c19d1205 7416do_shift (void)
a737bd4d 7417{
c19d1205
ZW
7418 unsigned int Rm = (inst.operands[1].present
7419 ? inst.operands[1].reg
7420 : inst.operands[0].reg);
a737bd4d 7421
c19d1205
ZW
7422 inst.instruction |= inst.operands[0].reg << 12;
7423 inst.instruction |= Rm;
7424 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 7425 {
c19d1205
ZW
7426 inst.instruction |= inst.operands[2].reg << 8;
7427 inst.instruction |= SHIFT_BY_REG;
a737bd4d
NC
7428 }
7429 else
c19d1205 7430 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC
7431}
7432
09d92015 7433static void
3eb17e6b 7434do_smc (void)
09d92015 7435{
3eb17e6b 7436 inst.reloc.type = BFD_RELOC_ARM_SMC;
c19d1205 7437 inst.reloc.pc_rel = 0;
09d92015
MM
7438}
7439
09d92015 7440static void
c19d1205 7441do_swi (void)
09d92015 7442{
c19d1205
ZW
7443 inst.reloc.type = BFD_RELOC_ARM_SWI;
7444 inst.reloc.pc_rel = 0;
09d92015
MM
7445}
7446
c19d1205
ZW
7447/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7448 SMLAxy{cond} Rd,Rm,Rs,Rn
7449 SMLAWy{cond} Rd,Rm,Rs,Rn
7450 Error if any register is R15. */
e16bb312 7451
c19d1205
ZW
7452static void
7453do_smla (void)
e16bb312 7454{
c19d1205
ZW
7455 inst.instruction |= inst.operands[0].reg << 16;
7456 inst.instruction |= inst.operands[1].reg;
7457 inst.instruction |= inst.operands[2].reg << 8;
7458 inst.instruction |= inst.operands[3].reg << 12;
7459}
a737bd4d 7460
c19d1205
ZW
7461/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7462 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7463 Error if any register is R15.
7464 Warning if Rdlo == Rdhi. */
a737bd4d 7465
c19d1205
ZW
7466static void
7467do_smlal (void)
7468{
7469 inst.instruction |= inst.operands[0].reg << 12;
7470 inst.instruction |= inst.operands[1].reg << 16;
7471 inst.instruction |= inst.operands[2].reg;
7472 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 7473
c19d1205
ZW
7474 if (inst.operands[0].reg == inst.operands[1].reg)
7475 as_tsktsk (_("rdhi and rdlo must be different"));
7476}
a737bd4d 7477
c19d1205
ZW
7478/* ARM V5E (El Segundo) signed-multiply (argument parse)
7479 SMULxy{cond} Rd,Rm,Rs
7480 Error if any register is R15. */
a737bd4d 7481
c19d1205
ZW
7482static void
7483do_smul (void)
7484{
7485 inst.instruction |= inst.operands[0].reg << 16;
7486 inst.instruction |= inst.operands[1].reg;
7487 inst.instruction |= inst.operands[2].reg << 8;
7488}
a737bd4d 7489
b6702015
PB
7490/* ARM V6 srs (argument parse). The variable fields in the encoding are
7491 the same for both ARM and Thumb-2. */
a737bd4d 7492
c19d1205
ZW
7493static void
7494do_srs (void)
7495{
b6702015
PB
7496 int reg;
7497
7498 if (inst.operands[0].present)
7499 {
7500 reg = inst.operands[0].reg;
7501 constraint (reg != 13, _("SRS base register must be r13"));
7502 }
7503 else
7504 reg = 13;
7505
7506 inst.instruction |= reg << 16;
7507 inst.instruction |= inst.operands[1].imm;
7508 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW
7509 inst.instruction |= WRITE_BACK;
7510}
a737bd4d 7511
c19d1205 7512/* ARM V6 strex (argument parse). */
a737bd4d 7513
c19d1205
ZW
7514static void
7515do_strex (void)
7516{
7517 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7518 || inst.operands[2].postind || inst.operands[2].writeback
7519 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC
7520 || inst.operands[2].negative
7521 /* See comment in do_ldrex(). */
7522 || (inst.operands[2].reg == REG_PC),
7523 BAD_ADDR_MODE);
a737bd4d 7524
c19d1205
ZW
7525 constraint (inst.operands[0].reg == inst.operands[1].reg
7526 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 7527
c19d1205
ZW
7528 constraint (inst.reloc.exp.X_op != O_constant
7529 || inst.reloc.exp.X_add_number != 0,
7530 _("offset must be zero in ARM encoding"));
a737bd4d 7531
c19d1205
ZW
7532 inst.instruction |= inst.operands[0].reg << 12;
7533 inst.instruction |= inst.operands[1].reg;
7534 inst.instruction |= inst.operands[2].reg << 16;
7535 inst.reloc.type = BFD_RELOC_UNUSED;
e16bb312
NC
7536}
7537
7538static void
c19d1205 7539do_strexd (void)
e16bb312 7540{
c19d1205
ZW
7541 constraint (inst.operands[1].reg % 2 != 0,
7542 _("even register required"));
7543 constraint (inst.operands[2].present
7544 && inst.operands[2].reg != inst.operands[1].reg + 1,
7545 _("can only store two consecutive registers"));
7546 /* If op 2 were present and equal to PC, this function wouldn't
7547 have been called in the first place. */
7548 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 7549
c19d1205
ZW
7550 constraint (inst.operands[0].reg == inst.operands[1].reg
7551 || inst.operands[0].reg == inst.operands[1].reg + 1
7552 || inst.operands[0].reg == inst.operands[3].reg,
7553 BAD_OVERLAP);
e16bb312 7554
c19d1205
ZW
7555 inst.instruction |= inst.operands[0].reg << 12;
7556 inst.instruction |= inst.operands[1].reg;
7557 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC
7558}
7559
c19d1205
ZW
7560/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7561 extends it to 32-bits, and adds the result to a value in another
7562 register. You can specify a rotation by 0, 8, 16, or 24 bits
7563 before extracting the 16-bit value.
7564 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7565 Condition defaults to COND_ALWAYS.
7566 Error if any register uses R15. */
7567
e16bb312 7568static void
c19d1205 7569do_sxtah (void)
e16bb312 7570{
c19d1205
ZW
7571 inst.instruction |= inst.operands[0].reg << 12;
7572 inst.instruction |= inst.operands[1].reg << 16;
7573 inst.instruction |= inst.operands[2].reg;
7574 inst.instruction |= inst.operands[3].imm << 10;
7575}
e16bb312 7576
c19d1205 7577/* ARM V6 SXTH.
e16bb312 7578
c19d1205
ZW
7579 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7580 Condition defaults to COND_ALWAYS.
7581 Error if any register uses R15. */
e16bb312
NC
7582
7583static void
c19d1205 7584do_sxth (void)
e16bb312 7585{
c19d1205
ZW
7586 inst.instruction |= inst.operands[0].reg << 12;
7587 inst.instruction |= inst.operands[1].reg;
7588 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 7589}
c19d1205
ZW
7590\f
7591/* VFP instructions. In a logical order: SP variant first, monad
7592 before dyad, arithmetic then move then load/store. */
e16bb312
NC
7593
7594static void
c19d1205 7595do_vfp_sp_monadic (void)
e16bb312 7596{
5287ad62
JB
7597 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7598 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
7599}
7600
7601static void
c19d1205 7602do_vfp_sp_dyadic (void)
e16bb312 7603{
5287ad62
JB
7604 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7605 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7606 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
7607}
7608
7609static void
c19d1205 7610do_vfp_sp_compare_z (void)
e16bb312 7611{
5287ad62 7612 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC
7613}
7614
7615static void
c19d1205 7616do_vfp_dp_sp_cvt (void)
e16bb312 7617{
5287ad62
JB
7618 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7619 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC
7620}
7621
7622static void
c19d1205 7623do_vfp_sp_dp_cvt (void)
e16bb312 7624{
5287ad62
JB
7625 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7626 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC
7627}
7628
7629static void
c19d1205 7630do_vfp_reg_from_sp (void)
e16bb312 7631{
c19d1205 7632 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 7633 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC
7634}
7635
7636static void
c19d1205 7637do_vfp_reg2_from_sp2 (void)
e16bb312 7638{
c19d1205
ZW
7639 constraint (inst.operands[2].imm != 2,
7640 _("only two consecutive VFP SP registers allowed here"));
7641 inst.instruction |= inst.operands[0].reg << 12;
7642 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 7643 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC
7644}
7645
7646static void
c19d1205 7647do_vfp_sp_from_reg (void)
e16bb312 7648{
5287ad62 7649 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 7650 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC
7651}
7652
7653static void
c19d1205 7654do_vfp_sp2_from_reg2 (void)
e16bb312 7655{
c19d1205
ZW
7656 constraint (inst.operands[0].imm != 2,
7657 _("only two consecutive VFP SP registers allowed here"));
5287ad62 7658 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW
7659 inst.instruction |= inst.operands[1].reg << 12;
7660 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC
7661}
7662
7663static void
c19d1205 7664do_vfp_sp_ldst (void)
e16bb312 7665{
5287ad62 7666 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 7667 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
7668}
7669
7670static void
c19d1205 7671do_vfp_dp_ldst (void)
e16bb312 7672{
5287ad62 7673 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 7674 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC
7675}
7676
c19d1205 7677
e16bb312 7678static void
c19d1205 7679vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 7680{
c19d1205
ZW
7681 if (inst.operands[0].writeback)
7682 inst.instruction |= WRITE_BACK;
7683 else
7684 constraint (ldstm_type != VFP_LDSTMIA,
7685 _("this addressing mode requires base-register writeback"));
7686 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 7687 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 7688 inst.instruction |= inst.operands[1].imm;
e16bb312
NC
7689}
7690
7691static void
c19d1205 7692vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 7693{
c19d1205 7694 int count;
e16bb312 7695
c19d1205
ZW
7696 if (inst.operands[0].writeback)
7697 inst.instruction |= WRITE_BACK;
7698 else
7699 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
7700 _("this addressing mode requires base-register writeback"));
e16bb312 7701
c19d1205 7702 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 7703 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 7704
c19d1205
ZW
7705 count = inst.operands[1].imm << 1;
7706 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
7707 count += 1;
e16bb312 7708
c19d1205 7709 inst.instruction |= count;
e16bb312
NC
7710}
7711
7712static void
c19d1205 7713do_vfp_sp_ldstmia (void)
e16bb312 7714{
c19d1205 7715 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC
7716}
7717
7718static void
c19d1205 7719do_vfp_sp_ldstmdb (void)
e16bb312 7720{
c19d1205 7721 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC
7722}
7723
7724static void
c19d1205 7725do_vfp_dp_ldstmia (void)
e16bb312 7726{
c19d1205 7727 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC
7728}
7729
7730static void
c19d1205 7731do_vfp_dp_ldstmdb (void)
e16bb312 7732{
c19d1205 7733 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC
7734}
7735
7736static void
c19d1205 7737do_vfp_xp_ldstmia (void)
e16bb312 7738{
c19d1205
ZW
7739 vfp_dp_ldstm (VFP_LDSTMIAX);
7740}
e16bb312 7741
c19d1205
ZW
7742static void
7743do_vfp_xp_ldstmdb (void)
7744{
7745 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 7746}
5287ad62
JB
7747
7748static void
7749do_vfp_dp_rd_rm (void)
7750{
7751 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7752 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7753}
7754
7755static void
7756do_vfp_dp_rn_rd (void)
7757{
7758 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7759 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7760}
7761
7762static void
7763do_vfp_dp_rd_rn (void)
7764{
7765 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7766 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7767}
7768
7769static void
7770do_vfp_dp_rd_rn_rm (void)
7771{
7772 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7773 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7774 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7775}
7776
7777static void
7778do_vfp_dp_rd (void)
7779{
7780 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7781}
7782
7783static void
7784do_vfp_dp_rm_rd_rn (void)
7785{
7786 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7787 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7788 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7789}
7790
7791/* VFPv3 instructions. */
7792static void
7793do_vfp_sp_const (void)
7794{
7795 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB
7796 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7797 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB
7798}
7799
7800static void
7801do_vfp_dp_const (void)
7802{
7803 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB
7804 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7805 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB
7806}
7807
7808static void
7809vfp_conv (int srcsize)
7810{
7811 unsigned immbits = srcsize - inst.operands[1].imm;
7812 inst.instruction |= (immbits & 1) << 5;
7813 inst.instruction |= (immbits >> 1);
7814}
7815
7816static void
7817do_vfp_sp_conv_16 (void)
7818{
7819 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7820 vfp_conv (16);
7821}
7822
7823static void
7824do_vfp_dp_conv_16 (void)
7825{
7826 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7827 vfp_conv (16);
7828}
7829
7830static void
7831do_vfp_sp_conv_32 (void)
7832{
7833 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7834 vfp_conv (32);
7835}
7836
7837static void
7838do_vfp_dp_conv_32 (void)
7839{
7840 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7841 vfp_conv (32);
7842}
c19d1205
ZW
7843\f
7844/* FPA instructions. Also in a logical order. */
e16bb312 7845
c19d1205
ZW
7846static void
7847do_fpa_cmp (void)
7848{
7849 inst.instruction |= inst.operands[0].reg << 16;
7850 inst.instruction |= inst.operands[1].reg;
7851}
b99bd4ef
NC
7852
7853static void
c19d1205 7854do_fpa_ldmstm (void)
b99bd4ef 7855{
c19d1205
ZW
7856 inst.instruction |= inst.operands[0].reg << 12;
7857 switch (inst.operands[1].imm)
7858 {
7859 case 1: inst.instruction |= CP_T_X; break;
7860 case 2: inst.instruction |= CP_T_Y; break;
7861 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
7862 case 4: break;
7863 default: abort ();
7864 }
b99bd4ef 7865
c19d1205
ZW
7866 if (inst.instruction & (PRE_INDEX | INDEX_UP))
7867 {
7868 /* The instruction specified "ea" or "fd", so we can only accept
7869 [Rn]{!}. The instruction does not really support stacking or
7870 unstacking, so we have to emulate these by setting appropriate
7871 bits and offsets. */
7872 constraint (inst.reloc.exp.X_op != O_constant
7873 || inst.reloc.exp.X_add_number != 0,
7874 _("this instruction does not support indexing"));
b99bd4ef 7875
c19d1205
ZW
7876 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
7877 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 7878
c19d1205
ZW
7879 if (!(inst.instruction & INDEX_UP))
7880 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
b99bd4ef 7881
c19d1205
ZW
7882 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
7883 {
7884 inst.operands[2].preind = 0;
7885 inst.operands[2].postind = 1;
7886 }
7887 }
b99bd4ef 7888
c19d1205 7889 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 7890}
c19d1205
ZW
7891\f
7892/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 7893
c19d1205
ZW
7894static void
7895do_iwmmxt_tandorc (void)
7896{
7897 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7898}
b99bd4ef 7899
c19d1205
ZW
7900static void
7901do_iwmmxt_textrc (void)
7902{
7903 inst.instruction |= inst.operands[0].reg << 12;
7904 inst.instruction |= inst.operands[1].imm;
7905}
b99bd4ef
NC
7906
7907static void
c19d1205 7908do_iwmmxt_textrm (void)
b99bd4ef 7909{
c19d1205
ZW
7910 inst.instruction |= inst.operands[0].reg << 12;
7911 inst.instruction |= inst.operands[1].reg << 16;
7912 inst.instruction |= inst.operands[2].imm;
7913}
b99bd4ef 7914
c19d1205
ZW
7915static void
7916do_iwmmxt_tinsr (void)
7917{
7918 inst.instruction |= inst.operands[0].reg << 16;
7919 inst.instruction |= inst.operands[1].reg << 12;
7920 inst.instruction |= inst.operands[2].imm;
7921}
b99bd4ef 7922
c19d1205
ZW
7923static void
7924do_iwmmxt_tmia (void)
7925{
7926 inst.instruction |= inst.operands[0].reg << 5;
7927 inst.instruction |= inst.operands[1].reg;
7928 inst.instruction |= inst.operands[2].reg << 12;
7929}
b99bd4ef 7930
c19d1205
ZW
7931static void
7932do_iwmmxt_waligni (void)
7933{
7934 inst.instruction |= inst.operands[0].reg << 12;
7935 inst.instruction |= inst.operands[1].reg << 16;
7936 inst.instruction |= inst.operands[2].reg;
7937 inst.instruction |= inst.operands[3].imm << 20;
7938}
b99bd4ef 7939
2d447fca
JM
7940static void
7941do_iwmmxt_wmerge (void)
7942{
7943 inst.instruction |= inst.operands[0].reg << 12;
7944 inst.instruction |= inst.operands[1].reg << 16;
7945 inst.instruction |= inst.operands[2].reg;
7946 inst.instruction |= inst.operands[3].imm << 21;
7947}
7948
c19d1205
ZW
7949static void
7950do_iwmmxt_wmov (void)
7951{
7952 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7953 inst.instruction |= inst.operands[0].reg << 12;
7954 inst.instruction |= inst.operands[1].reg << 16;
7955 inst.instruction |= inst.operands[1].reg;
7956}
b99bd4ef 7957
c19d1205
ZW
7958static void
7959do_iwmmxt_wldstbh (void)
7960{
8f06b2d8 7961 int reloc;
c19d1205 7962 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB
7963 if (thumb_mode)
7964 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
7965 else
7966 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
7967 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC
7968}
7969
c19d1205
ZW
7970static void
7971do_iwmmxt_wldstw (void)
7972{
7973 /* RIWR_RIWC clears .isreg for a control register. */
7974 if (!inst.operands[0].isreg)
7975 {
7976 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7977 inst.instruction |= 0xf0000000;
7978 }
b99bd4ef 7979
c19d1205
ZW
7980 inst.instruction |= inst.operands[0].reg << 12;
7981 encode_arm_cp_address (1, TRUE, TRUE, 0);
7982}
b99bd4ef
NC
7983
7984static void
c19d1205 7985do_iwmmxt_wldstd (void)
b99bd4ef 7986{
c19d1205 7987 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM
7988 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
7989 && inst.operands[1].immisreg)
7990 {
7991 inst.instruction &= ~0x1a000ff;
7992 inst.instruction |= (0xf << 28);
7993 if (inst.operands[1].preind)
7994 inst.instruction |= PRE_INDEX;
7995 if (!inst.operands[1].negative)
7996 inst.instruction |= INDEX_UP;
7997 if (inst.operands[1].writeback)
7998 inst.instruction |= WRITE_BACK;
7999 inst.instruction |= inst.operands[1].reg << 16;
8000 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8001 inst.instruction |= inst.operands[1].imm;
8002 }
8003 else
8004 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 8005}
b99bd4ef 8006
c19d1205
ZW
8007static void
8008do_iwmmxt_wshufh (void)
8009{
8010 inst.instruction |= inst.operands[0].reg << 12;
8011 inst.instruction |= inst.operands[1].reg << 16;
8012 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8013 inst.instruction |= (inst.operands[2].imm & 0x0f);
8014}
b99bd4ef 8015
c19d1205
ZW
8016static void
8017do_iwmmxt_wzero (void)
8018{
8019 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8020 inst.instruction |= inst.operands[0].reg;
8021 inst.instruction |= inst.operands[0].reg << 12;
8022 inst.instruction |= inst.operands[0].reg << 16;
8023}
2d447fca
JM
8024
8025static void
8026do_iwmmxt_wrwrwr_or_imm5 (void)
8027{
8028 if (inst.operands[2].isreg)
8029 do_rd_rn_rm ();
8030 else {
8031 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8032 _("immediate operand requires iWMMXt2"));
8033 do_rd_rn ();
8034 if (inst.operands[2].imm == 0)
8035 {
8036 switch ((inst.instruction >> 20) & 0xf)
8037 {
8038 case 4:
8039 case 5:
8040 case 6:
5f4273c7 8041 case 7:
2d447fca
JM
8042 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8043 inst.operands[2].imm = 16;
8044 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8045 break;
8046 case 8:
8047 case 9:
8048 case 10:
8049 case 11:
8050 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8051 inst.operands[2].imm = 32;
8052 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8053 break;
8054 case 12:
8055 case 13:
8056 case 14:
8057 case 15:
8058 {
8059 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8060 unsigned long wrn;
8061 wrn = (inst.instruction >> 16) & 0xf;
8062 inst.instruction &= 0xff0fff0f;
8063 inst.instruction |= wrn;
8064 /* Bail out here; the instruction is now assembled. */
8065 return;
8066 }
8067 }
8068 }
8069 /* Map 32 -> 0, etc. */
8070 inst.operands[2].imm &= 0x1f;
8071 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8072 }
8073}
c19d1205
ZW
8074\f
8075/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8076 operations first, then control, shift, and load/store. */
b99bd4ef 8077
c19d1205 8078/* Insns like "foo X,Y,Z". */
b99bd4ef 8079
c19d1205
ZW
8080static void
8081do_mav_triple (void)
8082{
8083 inst.instruction |= inst.operands[0].reg << 16;
8084 inst.instruction |= inst.operands[1].reg;
8085 inst.instruction |= inst.operands[2].reg << 12;
8086}
b99bd4ef 8087
c19d1205
ZW
8088/* Insns like "foo W,X,Y,Z".
8089 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 8090
c19d1205
ZW
8091static void
8092do_mav_quad (void)
8093{
8094 inst.instruction |= inst.operands[0].reg << 5;
8095 inst.instruction |= inst.operands[1].reg << 12;
8096 inst.instruction |= inst.operands[2].reg << 16;
8097 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC
8098}
8099
c19d1205
ZW
8100/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8101static void
8102do_mav_dspsc (void)
a737bd4d 8103{
c19d1205
ZW
8104 inst.instruction |= inst.operands[1].reg << 12;
8105}
a737bd4d 8106
c19d1205
ZW
8107/* Maverick shift immediate instructions.
8108 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8109 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 8110
c19d1205
ZW
8111static void
8112do_mav_shift (void)
8113{
8114 int imm = inst.operands[2].imm;
a737bd4d 8115
c19d1205
ZW
8116 inst.instruction |= inst.operands[0].reg << 12;
8117 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 8118
c19d1205
ZW
8119 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8120 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8121 Bit 4 should be 0. */
8122 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 8123
c19d1205
ZW
8124 inst.instruction |= imm;
8125}
8126\f
8127/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 8128
c19d1205
ZW
8129/* Xscale multiply-accumulate (argument parse)
8130 MIAcc acc0,Rm,Rs
8131 MIAPHcc acc0,Rm,Rs
8132 MIAxycc acc0,Rm,Rs. */
a737bd4d 8133
c19d1205
ZW
8134static void
8135do_xsc_mia (void)
8136{
8137 inst.instruction |= inst.operands[1].reg;
8138 inst.instruction |= inst.operands[2].reg << 12;
8139}
a737bd4d 8140
c19d1205 8141/* Xscale move-accumulator-register (argument parse)
a737bd4d 8142
c19d1205 8143 MARcc acc0,RdLo,RdHi. */
b99bd4ef 8144
c19d1205
ZW
8145static void
8146do_xsc_mar (void)
8147{
8148 inst.instruction |= inst.operands[1].reg << 12;
8149 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
8150}
8151
c19d1205 8152/* Xscale move-register-accumulator (argument parse)
b99bd4ef 8153
c19d1205 8154 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC
8155
8156static void
c19d1205 8157do_xsc_mra (void)
b99bd4ef 8158{
c19d1205
ZW
8159 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8160 inst.instruction |= inst.operands[0].reg << 12;
8161 inst.instruction |= inst.operands[1].reg << 16;
8162}
8163\f
8164/* Encoding functions relevant only to Thumb. */
b99bd4ef 8165
c19d1205
ZW
8166/* inst.operands[i] is a shifted-register operand; encode
8167 it into inst.instruction in the format used by Thumb32. */
8168
8169static void
8170encode_thumb32_shifted_operand (int i)
8171{
8172 unsigned int value = inst.reloc.exp.X_add_number;
8173 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 8174
9c3c69f2
PB
8175 constraint (inst.operands[i].immisreg,
8176 _("shift by register not allowed in thumb mode"));
c19d1205
ZW
8177 inst.instruction |= inst.operands[i].reg;
8178 if (shift == SHIFT_RRX)
8179 inst.instruction |= SHIFT_ROR << 4;
8180 else
b99bd4ef 8181 {
c19d1205
ZW
8182 constraint (inst.reloc.exp.X_op != O_constant,
8183 _("expression too complex"));
8184
8185 constraint (value > 32
8186 || (value == 32 && (shift == SHIFT_LSL
8187 || shift == SHIFT_ROR)),
8188 _("shift expression is too large"));
8189
8190 if (value == 0)
8191 shift = SHIFT_LSL;
8192 else if (value == 32)
8193 value = 0;
8194
8195 inst.instruction |= shift << 4;
8196 inst.instruction |= (value & 0x1c) << 10;
8197 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 8198 }
c19d1205 8199}
b99bd4ef 8200
b99bd4ef 8201
c19d1205
ZW
8202/* inst.operands[i] was set up by parse_address. Encode it into a
8203 Thumb32 format load or store instruction. Reject forms that cannot
8204 be used with such instructions. If is_t is true, reject forms that
8205 cannot be used with a T instruction; if is_d is true, reject forms
8206 that cannot be used with a D instruction. */
b99bd4ef 8207
c19d1205
ZW
8208static void
8209encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8210{
8211 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8212
8213 constraint (!inst.operands[i].isreg,
53365c0d 8214 _("Instruction does not support =N addresses"));
b99bd4ef 8215
c19d1205
ZW
8216 inst.instruction |= inst.operands[i].reg << 16;
8217 if (inst.operands[i].immisreg)
b99bd4ef 8218 {
c19d1205
ZW
8219 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
8220 constraint (is_t || is_d, _("cannot use register index with this instruction"));
8221 constraint (inst.operands[i].negative,
8222 _("Thumb does not support negative register indexing"));
8223 constraint (inst.operands[i].postind,
8224 _("Thumb does not support register post-indexing"));
8225 constraint (inst.operands[i].writeback,
8226 _("Thumb does not support register indexing with writeback"));
8227 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8228 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 8229
f40d1643 8230 inst.instruction |= inst.operands[i].imm;
c19d1205 8231 if (inst.operands[i].shifted)
b99bd4ef 8232 {
c19d1205
ZW
8233 constraint (inst.reloc.exp.X_op != O_constant,
8234 _("expression too complex"));
9c3c69f2
PB
8235 constraint (inst.reloc.exp.X_add_number < 0
8236 || inst.reloc.exp.X_add_number > 3,
c19d1205 8237 _("shift out of range"));
9c3c69f2 8238 inst.instruction |= inst.reloc.exp.X_add_number << 4;
c19d1205
ZW
8239 }
8240 inst.reloc.type = BFD_RELOC_UNUSED;
8241 }
8242 else if (inst.operands[i].preind)
8243 {
8244 constraint (is_pc && inst.operands[i].writeback,
8245 _("cannot use writeback with PC-relative addressing"));
f40d1643 8246 constraint (is_t && inst.operands[i].writeback,
c19d1205
ZW
8247 _("cannot use writeback with this instruction"));
8248
8249 if (is_d)
8250 {
8251 inst.instruction |= 0x01000000;
8252 if (inst.operands[i].writeback)
8253 inst.instruction |= 0x00200000;
b99bd4ef 8254 }
c19d1205 8255 else
b99bd4ef 8256 {
c19d1205
ZW
8257 inst.instruction |= 0x00000c00;
8258 if (inst.operands[i].writeback)
8259 inst.instruction |= 0x00000100;
b99bd4ef 8260 }
c19d1205 8261 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 8262 }
c19d1205 8263 else if (inst.operands[i].postind)
b99bd4ef 8264 {
c19d1205
ZW
8265 assert (inst.operands[i].writeback);
8266 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8267 constraint (is_t, _("cannot use post-indexing with this instruction"));
8268
8269 if (is_d)
8270 inst.instruction |= 0x00200000;
8271 else
8272 inst.instruction |= 0x00000900;
8273 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8274 }
8275 else /* unindexed - only for coprocessor */
8276 inst.error = _("instruction does not accept unindexed addressing");
8277}
8278
8279/* Table of Thumb instructions which exist in both 16- and 32-bit
8280 encodings (the latter only in post-V6T2 cores). The index is the
8281 value used in the insns table below. When there is more than one
8282 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB
8283 holds variant (1).
8284 Also contains several pseudo-instructions used during relaxation. */
c19d1205
ZW
8285#define T16_32_TAB \
8286 X(adc, 4140, eb400000), \
8287 X(adcs, 4140, eb500000), \
8288 X(add, 1c00, eb000000), \
8289 X(adds, 1c00, eb100000), \
0110f2b8
PB
8290 X(addi, 0000, f1000000), \
8291 X(addis, 0000, f1100000), \
8292 X(add_pc,000f, f20f0000), \
8293 X(add_sp,000d, f10d0000), \
e9f89963 8294 X(adr, 000f, f20f0000), \
c19d1205
ZW
8295 X(and, 4000, ea000000), \
8296 X(ands, 4000, ea100000), \
8297 X(asr, 1000, fa40f000), \
8298 X(asrs, 1000, fa50f000), \
0110f2b8
PB
8299 X(b, e000, f000b000), \
8300 X(bcond, d000, f0008000), \
c19d1205
ZW
8301 X(bic, 4380, ea200000), \
8302 X(bics, 4380, ea300000), \
8303 X(cmn, 42c0, eb100f00), \
8304 X(cmp, 2800, ebb00f00), \
8305 X(cpsie, b660, f3af8400), \
8306 X(cpsid, b670, f3af8600), \
8307 X(cpy, 4600, ea4f0000), \
155257ea 8308 X(dec_sp,80dd, f1ad0d00), \
c19d1205
ZW
8309 X(eor, 4040, ea800000), \
8310 X(eors, 4040, ea900000), \
0110f2b8 8311 X(inc_sp,00dd, f10d0d00), \
c19d1205
ZW
8312 X(ldmia, c800, e8900000), \
8313 X(ldr, 6800, f8500000), \
8314 X(ldrb, 7800, f8100000), \
8315 X(ldrh, 8800, f8300000), \
8316 X(ldrsb, 5600, f9100000), \
8317 X(ldrsh, 5e00, f9300000), \
0110f2b8
PB
8318 X(ldr_pc,4800, f85f0000), \
8319 X(ldr_pc2,4800, f85f0000), \
8320 X(ldr_sp,9800, f85d0000), \
c19d1205
ZW
8321 X(lsl, 0000, fa00f000), \
8322 X(lsls, 0000, fa10f000), \
8323 X(lsr, 0800, fa20f000), \
8324 X(lsrs, 0800, fa30f000), \
8325 X(mov, 2000, ea4f0000), \
8326 X(movs, 2000, ea5f0000), \
8327 X(mul, 4340, fb00f000), \
8328 X(muls, 4340, ffffffff), /* no 32b muls */ \
8329 X(mvn, 43c0, ea6f0000), \
8330 X(mvns, 43c0, ea7f0000), \
8331 X(neg, 4240, f1c00000), /* rsb #0 */ \
8332 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8333 X(orr, 4300, ea400000), \
8334 X(orrs, 4300, ea500000), \
e9f89963
PB
8335 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8336 X(push, b400, e92d0000), /* stmdb sp!,... */ \
c19d1205
ZW
8337 X(rev, ba00, fa90f080), \
8338 X(rev16, ba40, fa90f090), \
8339 X(revsh, bac0, fa90f0b0), \
8340 X(ror, 41c0, fa60f000), \
8341 X(rors, 41c0, fa70f000), \
8342 X(sbc, 4180, eb600000), \
8343 X(sbcs, 4180, eb700000), \
8344 X(stmia, c000, e8800000), \
8345 X(str, 6000, f8400000), \
8346 X(strb, 7000, f8000000), \
8347 X(strh, 8000, f8200000), \
0110f2b8 8348 X(str_sp,9000, f84d0000), \
c19d1205
ZW
8349 X(sub, 1e00, eba00000), \
8350 X(subs, 1e00, ebb00000), \
0110f2b8
PB
8351 X(subi, 8000, f1a00000), \
8352 X(subis, 8000, f1b00000), \
c19d1205
ZW
8353 X(sxtb, b240, fa4ff080), \
8354 X(sxth, b200, fa0ff080), \
8355 X(tst, 4200, ea100f00), \
8356 X(uxtb, b2c0, fa5ff080), \
8357 X(uxth, b280, fa1ff080), \
8358 X(nop, bf00, f3af8000), \
8359 X(yield, bf10, f3af8001), \
8360 X(wfe, bf20, f3af8002), \
8361 X(wfi, bf30, f3af8003), \
8362 X(sev, bf40, f3af9004), /* typo, 8004? */
8363
8364/* To catch errors in encoding functions, the codes are all offset by
8365 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8366 as 16-bit instructions. */
8367#define X(a,b,c) T_MNEM_##a
8368enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8369#undef X
8370
8371#define X(a,b,c) 0x##b
8372static const unsigned short thumb_op16[] = { T16_32_TAB };
8373#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8374#undef X
8375
8376#define X(a,b,c) 0x##c
8377static const unsigned int thumb_op32[] = { T16_32_TAB };
8378#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8379#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8380#undef X
8381#undef T16_32_TAB
8382
8383/* Thumb instruction encoders, in alphabetical order. */
8384
92e90b6e
PB
8385/* ADDW or SUBW. */
8386static void
8387do_t_add_sub_w (void)
8388{
8389 int Rd, Rn;
8390
8391 Rd = inst.operands[0].reg;
8392 Rn = inst.operands[1].reg;
8393
8394 constraint (Rd == 15, _("PC not allowed as destination"));
8395 inst.instruction |= (Rn << 16) | (Rd << 8);
8396 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8397}
8398
c19d1205
ZW
8399/* Parse an add or subtract instruction. We get here with inst.instruction
8400 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8401
8402static void
8403do_t_add_sub (void)
8404{
8405 int Rd, Rs, Rn;
8406
8407 Rd = inst.operands[0].reg;
8408 Rs = (inst.operands[1].present
8409 ? inst.operands[1].reg /* Rd, Rs, foo */
8410 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8411
8412 if (unified_syntax)
8413 {
0110f2b8
PB
8414 bfd_boolean flags;
8415 bfd_boolean narrow;
8416 int opcode;
8417
8418 flags = (inst.instruction == T_MNEM_adds
8419 || inst.instruction == T_MNEM_subs);
8420 if (flags)
8421 narrow = (current_it_mask == 0);
8422 else
8423 narrow = (current_it_mask != 0);
c19d1205 8424 if (!inst.operands[2].isreg)
b99bd4ef 8425 {
16805f35
PB
8426 int add;
8427
8428 add = (inst.instruction == T_MNEM_add
8429 || inst.instruction == T_MNEM_adds);
0110f2b8
PB
8430 opcode = 0;
8431 if (inst.size_req != 4)
8432 {
0110f2b8
PB
8433 /* Attempt to use a narrow opcode, with relaxation if
8434 appropriate. */
8435 if (Rd == REG_SP && Rs == REG_SP && !flags)
8436 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
8437 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
8438 opcode = T_MNEM_add_sp;
8439 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
8440 opcode = T_MNEM_add_pc;
8441 else if (Rd <= 7 && Rs <= 7 && narrow)
8442 {
8443 if (flags)
8444 opcode = add ? T_MNEM_addis : T_MNEM_subis;
8445 else
8446 opcode = add ? T_MNEM_addi : T_MNEM_subi;
8447 }
8448 if (opcode)
8449 {
8450 inst.instruction = THUMB_OP16(opcode);
8451 inst.instruction |= (Rd << 4) | Rs;
8452 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8453 if (inst.size_req != 2)
8454 inst.relax = opcode;
8455 }
8456 else
8457 constraint (inst.size_req == 2, BAD_HIREG);
8458 }
8459 if (inst.size_req == 4
8460 || (inst.size_req != 2 && !opcode))
8461 {
efd81785
PB
8462 if (Rd == REG_PC)
8463 {
8464 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
8465 _("only SUBS PC, LR, #const allowed"));
8466 constraint (inst.reloc.exp.X_op != O_constant,
8467 _("expression too complex"));
8468 constraint (inst.reloc.exp.X_add_number < 0
8469 || inst.reloc.exp.X_add_number > 0xff,
8470 _("immediate value out of range"));
8471 inst.instruction = T2_SUBS_PC_LR
8472 | inst.reloc.exp.X_add_number;
8473 inst.reloc.type = BFD_RELOC_UNUSED;
8474 return;
8475 }
8476 else if (Rs == REG_PC)
16805f35
PB
8477 {
8478 /* Always use addw/subw. */
8479 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
8480 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8481 }
8482 else
8483 {
8484 inst.instruction = THUMB_OP32 (inst.instruction);
8485 inst.instruction = (inst.instruction & 0xe1ffffff)
8486 | 0x10000000;
8487 if (flags)
8488 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8489 else
8490 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
8491 }
dc4503c6
PB
8492 inst.instruction |= Rd << 8;
8493 inst.instruction |= Rs << 16;
0110f2b8 8494 }
b99bd4ef 8495 }
c19d1205
ZW
8496 else
8497 {
8498 Rn = inst.operands[2].reg;
8499 /* See if we can do this with a 16-bit instruction. */
8500 if (!inst.operands[2].shifted && inst.size_req != 4)
8501 {
e27ec89e
PB
8502 if (Rd > 7 || Rs > 7 || Rn > 7)
8503 narrow = FALSE;
8504
8505 if (narrow)
c19d1205 8506 {
e27ec89e
PB
8507 inst.instruction = ((inst.instruction == T_MNEM_adds
8508 || inst.instruction == T_MNEM_add)
c19d1205
ZW
8509 ? T_OPCODE_ADD_R3
8510 : T_OPCODE_SUB_R3);
8511 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8512 return;
8513 }
b99bd4ef 8514
7e806470 8515 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 8516 {
7e806470
PB
8517 /* Thumb-1 cores (except v6-M) require at least one high
8518 register in a narrow non flag setting add. */
8519 if (Rd > 7 || Rn > 7
8520 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
8521 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 8522 {
7e806470
PB
8523 if (Rd == Rn)
8524 {
8525 Rn = Rs;
8526 Rs = Rd;
8527 }
c19d1205
ZW
8528 inst.instruction = T_OPCODE_ADD_HI;
8529 inst.instruction |= (Rd & 8) << 4;
8530 inst.instruction |= (Rd & 7);
8531 inst.instruction |= Rn << 3;
8532 return;
8533 }
c19d1205
ZW
8534 }
8535 }
8536 /* If we get here, it can't be done in 16 bits. */
8537 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
8538 _("shift must be constant"));
8539 inst.instruction = THUMB_OP32 (inst.instruction);
8540 inst.instruction |= Rd << 8;
8541 inst.instruction |= Rs << 16;
8542 encode_thumb32_shifted_operand (2);
8543 }
8544 }
8545 else
8546 {
8547 constraint (inst.instruction == T_MNEM_adds
8548 || inst.instruction == T_MNEM_subs,
8549 BAD_THUMB32);
b99bd4ef 8550
c19d1205 8551 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 8552 {
c19d1205
ZW
8553 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
8554 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
8555 BAD_HIREG);
8556
8557 inst.instruction = (inst.instruction == T_MNEM_add
8558 ? 0x0000 : 0x8000);
8559 inst.instruction |= (Rd << 4) | Rs;
8560 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC
8561 return;
8562 }
8563
c19d1205
ZW
8564 Rn = inst.operands[2].reg;
8565 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 8566
c19d1205
ZW
8567 /* We now have Rd, Rs, and Rn set to registers. */
8568 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 8569 {
c19d1205
ZW
8570 /* Can't do this for SUB. */
8571 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
8572 inst.instruction = T_OPCODE_ADD_HI;
8573 inst.instruction |= (Rd & 8) << 4;
8574 inst.instruction |= (Rd & 7);
8575 if (Rs == Rd)
8576 inst.instruction |= Rn << 3;
8577 else if (Rn == Rd)
8578 inst.instruction |= Rs << 3;
8579 else
8580 constraint (1, _("dest must overlap one source register"));
8581 }
8582 else
8583 {
8584 inst.instruction = (inst.instruction == T_MNEM_add
8585 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
8586 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 8587 }
b99bd4ef 8588 }
b99bd4ef
NC
8589}
8590
c19d1205
ZW
8591static void
8592do_t_adr (void)
8593{
0110f2b8
PB
8594 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8595 {
8596 /* Defer to section relaxation. */
8597 inst.relax = inst.instruction;
8598 inst.instruction = THUMB_OP16 (inst.instruction);
8599 inst.instruction |= inst.operands[0].reg << 4;
8600 }
8601 else if (unified_syntax && inst.size_req != 2)
e9f89963 8602 {
0110f2b8 8603 /* Generate a 32-bit opcode. */
e9f89963
PB
8604 inst.instruction = THUMB_OP32 (inst.instruction);
8605 inst.instruction |= inst.operands[0].reg << 8;
8606 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
8607 inst.reloc.pc_rel = 1;
8608 }
8609 else
8610 {
0110f2b8 8611 /* Generate a 16-bit opcode. */
e9f89963
PB
8612 inst.instruction = THUMB_OP16 (inst.instruction);
8613 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8614 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
8615 inst.reloc.pc_rel = 1;
b99bd4ef 8616
e9f89963
PB
8617 inst.instruction |= inst.operands[0].reg << 4;
8618 }
c19d1205 8619}
b99bd4ef 8620
c19d1205
ZW
8621/* Arithmetic instructions for which there is just one 16-bit
8622 instruction encoding, and it allows only two low registers.
8623 For maximal compatibility with ARM syntax, we allow three register
8624 operands even when Thumb-32 instructions are not available, as long
8625 as the first two are identical. For instance, both "sbc r0,r1" and
8626 "sbc r0,r0,r1" are allowed. */
b99bd4ef 8627static void
c19d1205 8628do_t_arit3 (void)
b99bd4ef 8629{
c19d1205 8630 int Rd, Rs, Rn;
b99bd4ef 8631
c19d1205
ZW
8632 Rd = inst.operands[0].reg;
8633 Rs = (inst.operands[1].present
8634 ? inst.operands[1].reg /* Rd, Rs, foo */
8635 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8636 Rn = inst.operands[2].reg;
b99bd4ef 8637
c19d1205 8638 if (unified_syntax)
b99bd4ef 8639 {
c19d1205
ZW
8640 if (!inst.operands[2].isreg)
8641 {
8642 /* For an immediate, we always generate a 32-bit opcode;
8643 section relaxation will shrink it later if possible. */
8644 inst.instruction = THUMB_OP32 (inst.instruction);
8645 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8646 inst.instruction |= Rd << 8;
8647 inst.instruction |= Rs << 16;
8648 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8649 }
8650 else
8651 {
e27ec89e
PB
8652 bfd_boolean narrow;
8653
c19d1205 8654 /* See if we can do this with a 16-bit instruction. */
e27ec89e
PB
8655 if (THUMB_SETS_FLAGS (inst.instruction))
8656 narrow = current_it_mask == 0;
8657 else
8658 narrow = current_it_mask != 0;
8659
8660 if (Rd > 7 || Rn > 7 || Rs > 7)
8661 narrow = FALSE;
8662 if (inst.operands[2].shifted)
8663 narrow = FALSE;
8664 if (inst.size_req == 4)
8665 narrow = FALSE;
8666
8667 if (narrow
c19d1205
ZW
8668 && Rd == Rs)
8669 {
8670 inst.instruction = THUMB_OP16 (inst.instruction);
8671 inst.instruction |= Rd;
8672 inst.instruction |= Rn << 3;
8673 return;
8674 }
b99bd4ef 8675
c19d1205
ZW
8676 /* If we get here, it can't be done in 16 bits. */
8677 constraint (inst.operands[2].shifted
8678 && inst.operands[2].immisreg,
8679 _("shift must be constant"));
8680 inst.instruction = THUMB_OP32 (inst.instruction);
8681 inst.instruction |= Rd << 8;
8682 inst.instruction |= Rs << 16;
8683 encode_thumb32_shifted_operand (2);
8684 }
a737bd4d 8685 }
c19d1205 8686 else
b99bd4ef 8687 {
c19d1205
ZW
8688 /* On its face this is a lie - the instruction does set the
8689 flags. However, the only supported mnemonic in this mode
8690 says it doesn't. */
8691 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 8692
c19d1205
ZW
8693 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8694 _("unshifted register required"));
8695 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8696 constraint (Rd != Rs,
8697 _("dest and source1 must be the same register"));
a737bd4d 8698
c19d1205
ZW
8699 inst.instruction = THUMB_OP16 (inst.instruction);
8700 inst.instruction |= Rd;
8701 inst.instruction |= Rn << 3;
b99bd4ef 8702 }
a737bd4d 8703}
b99bd4ef 8704
c19d1205
ZW
8705/* Similarly, but for instructions where the arithmetic operation is
8706 commutative, so we can allow either of them to be different from
8707 the destination operand in a 16-bit instruction. For instance, all
8708 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8709 accepted. */
8710static void
8711do_t_arit3c (void)
a737bd4d 8712{
c19d1205 8713 int Rd, Rs, Rn;
b99bd4ef 8714
c19d1205
ZW
8715 Rd = inst.operands[0].reg;
8716 Rs = (inst.operands[1].present
8717 ? inst.operands[1].reg /* Rd, Rs, foo */
8718 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8719 Rn = inst.operands[2].reg;
a737bd4d 8720
c19d1205 8721 if (unified_syntax)
a737bd4d 8722 {
c19d1205 8723 if (!inst.operands[2].isreg)
b99bd4ef 8724 {
c19d1205
ZW
8725 /* For an immediate, we always generate a 32-bit opcode;
8726 section relaxation will shrink it later if possible. */
8727 inst.instruction = THUMB_OP32 (inst.instruction);
8728 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8729 inst.instruction |= Rd << 8;
8730 inst.instruction |= Rs << 16;
8731 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 8732 }
c19d1205 8733 else
a737bd4d 8734 {
e27ec89e
PB
8735 bfd_boolean narrow;
8736
c19d1205 8737 /* See if we can do this with a 16-bit instruction. */
e27ec89e
PB
8738 if (THUMB_SETS_FLAGS (inst.instruction))
8739 narrow = current_it_mask == 0;
8740 else
8741 narrow = current_it_mask != 0;
8742
8743 if (Rd > 7 || Rn > 7 || Rs > 7)
8744 narrow = FALSE;
8745 if (inst.operands[2].shifted)
8746 narrow = FALSE;
8747 if (inst.size_req == 4)
8748 narrow = FALSE;
8749
8750 if (narrow)
a737bd4d 8751 {
c19d1205 8752 if (Rd == Rs)
a737bd4d 8753 {
c19d1205
ZW
8754 inst.instruction = THUMB_OP16 (inst.instruction);
8755 inst.instruction |= Rd;
8756 inst.instruction |= Rn << 3;
8757 return;
a737bd4d 8758 }
c19d1205 8759 if (Rd == Rn)
a737bd4d 8760 {
c19d1205
ZW
8761 inst.instruction = THUMB_OP16 (inst.instruction);
8762 inst.instruction |= Rd;
8763 inst.instruction |= Rs << 3;
8764 return;
a737bd4d
NC
8765 }
8766 }
c19d1205
ZW
8767
8768 /* If we get here, it can't be done in 16 bits. */
8769 constraint (inst.operands[2].shifted
8770 && inst.operands[2].immisreg,
8771 _("shift must be constant"));
8772 inst.instruction = THUMB_OP32 (inst.instruction);
8773 inst.instruction |= Rd << 8;
8774 inst.instruction |= Rs << 16;
8775 encode_thumb32_shifted_operand (2);
a737bd4d 8776 }
b99bd4ef 8777 }
c19d1205
ZW
8778 else
8779 {
8780 /* On its face this is a lie - the instruction does set the
8781 flags. However, the only supported mnemonic in this mode
8782 says it doesn't. */
8783 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 8784
c19d1205
ZW
8785 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8786 _("unshifted register required"));
8787 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8788
8789 inst.instruction = THUMB_OP16 (inst.instruction);
8790 inst.instruction |= Rd;
8791
8792 if (Rd == Rs)
8793 inst.instruction |= Rn << 3;
8794 else if (Rd == Rn)
8795 inst.instruction |= Rs << 3;
8796 else
8797 constraint (1, _("dest must overlap one source register"));
8798 }
a737bd4d
NC
8799}
8800
62b3e311
PB
8801static void
8802do_t_barrier (void)
8803{
8804 if (inst.operands[0].present)
8805 {
8806 constraint ((inst.instruction & 0xf0) != 0x40
8807 && inst.operands[0].imm != 0xf,
bd3ba5d1 8808 _("bad barrier type"));
62b3e311
PB
8809 inst.instruction |= inst.operands[0].imm;
8810 }
8811 else
8812 inst.instruction |= 0xf;
8813}
8814
c19d1205
ZW
8815static void
8816do_t_bfc (void)
a737bd4d 8817{
c19d1205
ZW
8818 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8819 constraint (msb > 32, _("bit-field extends past end of register"));
8820 /* The instruction encoding stores the LSB and MSB,
8821 not the LSB and width. */
8822 inst.instruction |= inst.operands[0].reg << 8;
8823 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8824 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8825 inst.instruction |= msb - 1;
b99bd4ef
NC
8826}
8827
c19d1205
ZW
8828static void
8829do_t_bfi (void)
b99bd4ef 8830{
c19d1205 8831 unsigned int msb;
b99bd4ef 8832
c19d1205
ZW
8833 /* #0 in second position is alternative syntax for bfc, which is
8834 the same instruction but with REG_PC in the Rm field. */
8835 if (!inst.operands[1].isreg)
8836 inst.operands[1].reg = REG_PC;
b99bd4ef 8837
c19d1205
ZW
8838 msb = inst.operands[2].imm + inst.operands[3].imm;
8839 constraint (msb > 32, _("bit-field extends past end of register"));
8840 /* The instruction encoding stores the LSB and MSB,
8841 not the LSB and width. */
8842 inst.instruction |= inst.operands[0].reg << 8;
8843 inst.instruction |= inst.operands[1].reg << 16;
8844 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8845 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8846 inst.instruction |= msb - 1;
b99bd4ef
NC
8847}
8848
c19d1205
ZW
8849static void
8850do_t_bfx (void)
b99bd4ef 8851{
c19d1205
ZW
8852 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8853 _("bit-field extends past end of register"));
8854 inst.instruction |= inst.operands[0].reg << 8;
8855 inst.instruction |= inst.operands[1].reg << 16;
8856 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8857 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8858 inst.instruction |= inst.operands[3].imm - 1;
8859}
b99bd4ef 8860
c19d1205
ZW
8861/* ARM V5 Thumb BLX (argument parse)
8862 BLX <target_addr> which is BLX(1)
8863 BLX <Rm> which is BLX(2)
8864 Unfortunately, there are two different opcodes for this mnemonic.
8865 So, the insns[].value is not used, and the code here zaps values
8866 into inst.instruction.
b99bd4ef 8867
c19d1205
ZW
8868 ??? How to take advantage of the additional two bits of displacement
8869 available in Thumb32 mode? Need new relocation? */
b99bd4ef 8870
c19d1205
ZW
8871static void
8872do_t_blx (void)
8873{
dfa9f0d5 8874 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
c19d1205
ZW
8875 if (inst.operands[0].isreg)
8876 /* We have a register, so this is BLX(2). */
8877 inst.instruction |= inst.operands[0].reg << 3;
b99bd4ef
NC
8878 else
8879 {
c19d1205 8880 /* No register. This must be BLX(1). */
2fc8bdac 8881 inst.instruction = 0xf000e800;
39b41c9c
PB
8882#ifdef OBJ_ELF
8883 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8884 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8885 else
8886#endif
8887 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
c19d1205 8888 inst.reloc.pc_rel = 1;
b99bd4ef
NC
8889 }
8890}
8891
c19d1205
ZW
8892static void
8893do_t_branch (void)
b99bd4ef 8894{
0110f2b8 8895 int opcode;
dfa9f0d5
PB
8896 int cond;
8897
8898 if (current_it_mask)
8899 {
8900 /* Conditional branches inside IT blocks are encoded as unconditional
8901 branches. */
8902 cond = COND_ALWAYS;
8903 /* A branch must be the last instruction in an IT block. */
8904 constraint (current_it_mask != 0x10, BAD_BRANCH);
8905 }
8906 else
8907 cond = inst.cond;
8908
8909 if (cond != COND_ALWAYS)
0110f2b8
PB
8910 opcode = T_MNEM_bcond;
8911 else
8912 opcode = inst.instruction;
8913
8914 if (unified_syntax && inst.size_req == 4)
c19d1205 8915 {
0110f2b8 8916 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 8917 if (cond == COND_ALWAYS)
0110f2b8 8918 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW
8919 else
8920 {
dfa9f0d5
PB
8921 assert (cond != 0xF);
8922 inst.instruction |= cond << 22;
c19d1205
ZW
8923 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
8924 }
8925 }
b99bd4ef
NC
8926 else
8927 {
0110f2b8 8928 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 8929 if (cond == COND_ALWAYS)
c19d1205
ZW
8930 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
8931 else
b99bd4ef 8932 {
dfa9f0d5 8933 inst.instruction |= cond << 8;
c19d1205 8934 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 8935 }
0110f2b8
PB
8936 /* Allow section relaxation. */
8937 if (unified_syntax && inst.size_req != 2)
8938 inst.relax = opcode;
b99bd4ef 8939 }
c19d1205
ZW
8940
8941 inst.reloc.pc_rel = 1;
b99bd4ef
NC
8942}
8943
8944static void
c19d1205 8945do_t_bkpt (void)
b99bd4ef 8946{
dfa9f0d5
PB
8947 constraint (inst.cond != COND_ALWAYS,
8948 _("instruction is always unconditional"));
c19d1205 8949 if (inst.operands[0].present)
b99bd4ef 8950 {
c19d1205
ZW
8951 constraint (inst.operands[0].imm > 255,
8952 _("immediate value out of range"));
8953 inst.instruction |= inst.operands[0].imm;
b99bd4ef 8954 }
b99bd4ef
NC
8955}
8956
8957static void
c19d1205 8958do_t_branch23 (void)
b99bd4ef 8959{
dfa9f0d5 8960 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
c19d1205 8961 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a
RE
8962 inst.reloc.pc_rel = 1;
8963
c19d1205
ZW
8964 /* If the destination of the branch is a defined symbol which does not have
8965 the THUMB_FUNC attribute, then we must be calling a function which has
8966 the (interfacearm) attribute. We look for the Thumb entry point to that
8967 function and change the branch to refer to that function instead. */
8968 if ( inst.reloc.exp.X_op == O_symbol
8969 && inst.reloc.exp.X_add_symbol != NULL
8970 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8971 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8972 inst.reloc.exp.X_add_symbol =
8973 find_real_start (inst.reloc.exp.X_add_symbol);
90e4755a
RE
8974}
8975
8976static void
c19d1205 8977do_t_bx (void)
90e4755a 8978{
dfa9f0d5 8979 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
c19d1205
ZW
8980 inst.instruction |= inst.operands[0].reg << 3;
8981 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8982 should cause the alignment to be checked once it is known. This is
8983 because BX PC only works if the instruction is word aligned. */
8984}
90e4755a 8985
c19d1205
ZW
8986static void
8987do_t_bxj (void)
8988{
dfa9f0d5 8989 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
c19d1205
ZW
8990 if (inst.operands[0].reg == REG_PC)
8991 as_tsktsk (_("use of r15 in bxj is not really useful"));
90e4755a 8992
c19d1205 8993 inst.instruction |= inst.operands[0].reg << 16;
90e4755a
RE
8994}
8995
8996static void
c19d1205 8997do_t_clz (void)
90e4755a 8998{
c19d1205
ZW
8999 inst.instruction |= inst.operands[0].reg << 8;
9000 inst.instruction |= inst.operands[1].reg << 16;
9001 inst.instruction |= inst.operands[1].reg;
9002}
90e4755a 9003
dfa9f0d5
PB
9004static void
9005do_t_cps (void)
9006{
9007 constraint (current_it_mask, BAD_NOT_IT);
9008 inst.instruction |= inst.operands[0].imm;
9009}
9010
c19d1205
ZW
9011static void
9012do_t_cpsi (void)
9013{
dfa9f0d5 9014 constraint (current_it_mask, BAD_NOT_IT);
c19d1205 9015 if (unified_syntax
62b3e311
PB
9016 && (inst.operands[1].present || inst.size_req == 4)
9017 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 9018 {
c19d1205
ZW
9019 unsigned int imod = (inst.instruction & 0x0030) >> 4;
9020 inst.instruction = 0xf3af8000;
9021 inst.instruction |= imod << 9;
9022 inst.instruction |= inst.operands[0].imm << 5;
9023 if (inst.operands[1].present)
9024 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 9025 }
c19d1205 9026 else
90e4755a 9027 {
62b3e311
PB
9028 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
9029 && (inst.operands[0].imm & 4),
9030 _("selected processor does not support 'A' form "
9031 "of this instruction"));
9032 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW
9033 _("Thumb does not support the 2-argument "
9034 "form of this instruction"));
9035 inst.instruction |= inst.operands[0].imm;
90e4755a 9036 }
90e4755a
RE
9037}
9038
c19d1205
ZW
9039/* THUMB CPY instruction (argument parse). */
9040
90e4755a 9041static void
c19d1205 9042do_t_cpy (void)
90e4755a 9043{
c19d1205 9044 if (inst.size_req == 4)
90e4755a 9045 {
c19d1205
ZW
9046 inst.instruction = THUMB_OP32 (T_MNEM_mov);
9047 inst.instruction |= inst.operands[0].reg << 8;
9048 inst.instruction |= inst.operands[1].reg;
90e4755a 9049 }
c19d1205 9050 else
90e4755a 9051 {
c19d1205
ZW
9052 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9053 inst.instruction |= (inst.operands[0].reg & 0x7);
9054 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 9055 }
90e4755a
RE
9056}
9057
90e4755a 9058static void
25fe350b 9059do_t_cbz (void)
90e4755a 9060{
dfa9f0d5 9061 constraint (current_it_mask, BAD_NOT_IT);
c19d1205
ZW
9062 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9063 inst.instruction |= inst.operands[0].reg;
9064 inst.reloc.pc_rel = 1;
9065 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
9066}
90e4755a 9067
62b3e311
PB
9068static void
9069do_t_dbg (void)
9070{
9071 inst.instruction |= inst.operands[0].imm;
9072}
9073
9074static void
9075do_t_div (void)
9076{
9077 if (!inst.operands[1].present)
9078 inst.operands[1].reg = inst.operands[0].reg;
9079 inst.instruction |= inst.operands[0].reg << 8;
9080 inst.instruction |= inst.operands[1].reg << 16;
9081 inst.instruction |= inst.operands[2].reg;
9082}
9083
c19d1205
ZW
9084static void
9085do_t_hint (void)
9086{
9087 if (unified_syntax && inst.size_req == 4)
9088 inst.instruction = THUMB_OP32 (inst.instruction);
9089 else
9090 inst.instruction = THUMB_OP16 (inst.instruction);
9091}
90e4755a 9092
c19d1205
ZW
9093static void
9094do_t_it (void)
9095{
9096 unsigned int cond = inst.operands[0].imm;
e27ec89e 9097
dfa9f0d5 9098 constraint (current_it_mask, BAD_NOT_IT);
e27ec89e
PB
9099 current_it_mask = (inst.instruction & 0xf) | 0x10;
9100 current_cc = cond;
9101
9102 /* If the condition is a negative condition, invert the mask. */
c19d1205 9103 if ((cond & 0x1) == 0x0)
90e4755a 9104 {
c19d1205 9105 unsigned int mask = inst.instruction & 0x000f;
90e4755a 9106
c19d1205
ZW
9107 if ((mask & 0x7) == 0)
9108 /* no conversion needed */;
9109 else if ((mask & 0x3) == 0)
e27ec89e
PB
9110 mask ^= 0x8;
9111 else if ((mask & 0x1) == 0)
9112 mask ^= 0xC;
c19d1205 9113 else
e27ec89e 9114 mask ^= 0xE;
90e4755a 9115
e27ec89e
PB
9116 inst.instruction &= 0xfff0;
9117 inst.instruction |= mask;
c19d1205 9118 }
90e4755a 9119
c19d1205
ZW
9120 inst.instruction |= cond << 4;
9121}
90e4755a 9122
3c707909
PB
9123/* Helper function used for both push/pop and ldm/stm. */
9124static void
9125encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9126{
9127 bfd_boolean load;
9128
9129 load = (inst.instruction & (1 << 20)) != 0;
9130
9131 if (mask & (1 << 13))
9132 inst.error = _("SP not allowed in register list");
9133 if (load)
9134 {
9135 if (mask & (1 << 14)
9136 && mask & (1 << 15))
9137 inst.error = _("LR and PC should not both be in register list");
9138
9139 if ((mask & (1 << base)) != 0
9140 && writeback)
9141 as_warn (_("base register should not be in register list "
9142 "when written back"));
9143 }
9144 else
9145 {
9146 if (mask & (1 << 15))
9147 inst.error = _("PC not allowed in register list");
9148
9149 if (mask & (1 << base))
9150 as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
9151 }
9152
9153 if ((mask & (mask - 1)) == 0)
9154 {
9155 /* Single register transfers implemented as str/ldr. */
9156 if (writeback)
9157 {
9158 if (inst.instruction & (1 << 23))
9159 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9160 else
9161 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9162 }
9163 else
9164 {
9165 if (inst.instruction & (1 << 23))
9166 inst.instruction = 0x00800000; /* ia -> [base] */
9167 else
9168 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9169 }
9170
9171 inst.instruction |= 0xf8400000;
9172 if (load)
9173 inst.instruction |= 0x00100000;
9174
5f4273c7 9175 mask = ffs (mask) - 1;
3c707909
PB
9176 mask <<= 12;
9177 }
9178 else if (writeback)
9179 inst.instruction |= WRITE_BACK;
9180
9181 inst.instruction |= mask;
9182 inst.instruction |= base << 16;
9183}
9184
c19d1205
ZW
9185static void
9186do_t_ldmstm (void)
9187{
9188 /* This really doesn't seem worth it. */
9189 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9190 _("expression too complex"));
9191 constraint (inst.operands[1].writeback,
9192 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 9193
c19d1205
ZW
9194 if (unified_syntax)
9195 {
3c707909
PB
9196 bfd_boolean narrow;
9197 unsigned mask;
9198
9199 narrow = FALSE;
c19d1205
ZW
9200 /* See if we can use a 16-bit instruction. */
9201 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9202 && inst.size_req != 4
3c707909 9203 && !(inst.operands[1].imm & ~0xff))
90e4755a 9204 {
3c707909 9205 mask = 1 << inst.operands[0].reg;
90e4755a 9206
3c707909
PB
9207 if (inst.operands[0].reg <= 7
9208 && (inst.instruction == T_MNEM_stmia
9209 ? inst.operands[0].writeback
9210 : (inst.operands[0].writeback
9211 == !(inst.operands[1].imm & mask))))
90e4755a 9212 {
3c707909
PB
9213 if (inst.instruction == T_MNEM_stmia
9214 && (inst.operands[1].imm & mask)
9215 && (inst.operands[1].imm & (mask - 1)))
c19d1205
ZW
9216 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9217 inst.operands[0].reg);
3c707909
PB
9218
9219 inst.instruction = THUMB_OP16 (inst.instruction);
9220 inst.instruction |= inst.operands[0].reg << 8;
9221 inst.instruction |= inst.operands[1].imm;
9222 narrow = TRUE;
90e4755a 9223 }
3c707909
PB
9224 else if (inst.operands[0] .reg == REG_SP
9225 && inst.operands[0].writeback)
90e4755a 9226 {
3c707909
PB
9227 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9228 ? T_MNEM_push : T_MNEM_pop);
9229 inst.instruction |= inst.operands[1].imm;
9230 narrow = TRUE;
90e4755a 9231 }
3c707909
PB
9232 }
9233
9234 if (!narrow)
9235 {
c19d1205
ZW
9236 if (inst.instruction < 0xffff)
9237 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 9238
5f4273c7
NC
9239 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
9240 inst.operands[0].writeback);
90e4755a
RE
9241 }
9242 }
c19d1205 9243 else
90e4755a 9244 {
c19d1205
ZW
9245 constraint (inst.operands[0].reg > 7
9246 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB
9247 constraint (inst.instruction != T_MNEM_ldmia
9248 && inst.instruction != T_MNEM_stmia,
9249 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 9250 if (inst.instruction == T_MNEM_stmia)
f03698e6 9251 {
c19d1205
ZW
9252 if (!inst.operands[0].writeback)
9253 as_warn (_("this instruction will write back the base register"));
9254 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9255 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9256 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9257 inst.operands[0].reg);
f03698e6 9258 }
c19d1205 9259 else
90e4755a 9260 {
c19d1205
ZW
9261 if (!inst.operands[0].writeback
9262 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9263 as_warn (_("this instruction will write back the base register"));
9264 else if (inst.operands[0].writeback
9265 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9266 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE
9267 }
9268
c19d1205
ZW
9269 inst.instruction = THUMB_OP16 (inst.instruction);
9270 inst.instruction |= inst.operands[0].reg << 8;
9271 inst.instruction |= inst.operands[1].imm;
9272 }
9273}
e28cd48c 9274
c19d1205
ZW
9275static void
9276do_t_ldrex (void)
9277{
9278 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9279 || inst.operands[1].postind || inst.operands[1].writeback
9280 || inst.operands[1].immisreg || inst.operands[1].shifted
9281 || inst.operands[1].negative,
01cfc07f 9282 BAD_ADDR_MODE);
e28cd48c 9283
c19d1205
ZW
9284 inst.instruction |= inst.operands[0].reg << 12;
9285 inst.instruction |= inst.operands[1].reg << 16;
9286 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9287}
e28cd48c 9288
c19d1205
ZW
9289static void
9290do_t_ldrexd (void)
9291{
9292 if (!inst.operands[1].present)
1cac9012 9293 {
c19d1205
ZW
9294 constraint (inst.operands[0].reg == REG_LR,
9295 _("r14 not allowed as first register "
9296 "when second register is omitted"));
9297 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 9298 }
c19d1205
ZW
9299 constraint (inst.operands[0].reg == inst.operands[1].reg,
9300 BAD_OVERLAP);
b99bd4ef 9301
c19d1205
ZW
9302 inst.instruction |= inst.operands[0].reg << 12;
9303 inst.instruction |= inst.operands[1].reg << 8;
9304 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC
9305}
9306
9307static void
c19d1205 9308do_t_ldst (void)
b99bd4ef 9309{
0110f2b8
PB
9310 unsigned long opcode;
9311 int Rn;
9312
9313 opcode = inst.instruction;
c19d1205 9314 if (unified_syntax)
b99bd4ef 9315 {
53365c0d
PB
9316 if (!inst.operands[1].isreg)
9317 {
9318 if (opcode <= 0xffff)
9319 inst.instruction = THUMB_OP32 (opcode);
9320 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9321 return;
9322 }
0110f2b8
PB
9323 if (inst.operands[1].isreg
9324 && !inst.operands[1].writeback
c19d1205
ZW
9325 && !inst.operands[1].shifted && !inst.operands[1].postind
9326 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB
9327 && opcode <= 0xffff
9328 && inst.size_req != 4)
c19d1205 9329 {
0110f2b8
PB
9330 /* Insn may have a 16-bit form. */
9331 Rn = inst.operands[1].reg;
9332 if (inst.operands[1].immisreg)
9333 {
9334 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 9335 /* [Rn, Rik] */
0110f2b8
PB
9336 if (Rn <= 7 && inst.operands[1].imm <= 7)
9337 goto op16;
9338 }
9339 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9340 && opcode != T_MNEM_ldrsb)
9341 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9342 || (Rn == REG_SP && opcode == T_MNEM_str))
9343 {
9344 /* [Rn, #const] */
9345 if (Rn > 7)
9346 {
9347 if (Rn == REG_PC)
9348 {
9349 if (inst.reloc.pc_rel)
9350 opcode = T_MNEM_ldr_pc2;
9351 else
9352 opcode = T_MNEM_ldr_pc;
9353 }
9354 else
9355 {
9356 if (opcode == T_MNEM_ldr)
9357 opcode = T_MNEM_ldr_sp;
9358 else
9359 opcode = T_MNEM_str_sp;
9360 }
9361 inst.instruction = inst.operands[0].reg << 8;
9362 }
9363 else
9364 {
9365 inst.instruction = inst.operands[0].reg;
9366 inst.instruction |= inst.operands[1].reg << 3;
9367 }
9368 inst.instruction |= THUMB_OP16 (opcode);
9369 if (inst.size_req == 2)
9370 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9371 else
9372 inst.relax = opcode;
9373 return;
9374 }
c19d1205 9375 }
0110f2b8
PB
9376 /* Definitely a 32-bit variant. */
9377 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW
9378 inst.instruction |= inst.operands[0].reg << 12;
9379 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
b99bd4ef
NC
9380 return;
9381 }
9382
c19d1205
ZW
9383 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9384
9385 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 9386 {
c19d1205
ZW
9387 /* Only [Rn,Rm] is acceptable. */
9388 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9389 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
9390 || inst.operands[1].postind || inst.operands[1].shifted
9391 || inst.operands[1].negative,
9392 _("Thumb does not support this addressing mode"));
9393 inst.instruction = THUMB_OP16 (inst.instruction);
9394 goto op16;
b99bd4ef 9395 }
5f4273c7 9396
c19d1205
ZW
9397 inst.instruction = THUMB_OP16 (inst.instruction);
9398 if (!inst.operands[1].isreg)
9399 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9400 return;
b99bd4ef 9401
c19d1205
ZW
9402 constraint (!inst.operands[1].preind
9403 || inst.operands[1].shifted
9404 || inst.operands[1].writeback,
9405 _("Thumb does not support this addressing mode"));
9406 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 9407 {
c19d1205
ZW
9408 constraint (inst.instruction & 0x0600,
9409 _("byte or halfword not valid for base register"));
9410 constraint (inst.operands[1].reg == REG_PC
9411 && !(inst.instruction & THUMB_LOAD_BIT),
9412 _("r15 based store not allowed"));
9413 constraint (inst.operands[1].immisreg,
9414 _("invalid base register for register offset"));
b99bd4ef 9415
c19d1205
ZW
9416 if (inst.operands[1].reg == REG_PC)
9417 inst.instruction = T_OPCODE_LDR_PC;
9418 else if (inst.instruction & THUMB_LOAD_BIT)
9419 inst.instruction = T_OPCODE_LDR_SP;
9420 else
9421 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 9422
c19d1205
ZW
9423 inst.instruction |= inst.operands[0].reg << 8;
9424 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9425 return;
9426 }
90e4755a 9427
c19d1205
ZW
9428 constraint (inst.operands[1].reg > 7, BAD_HIREG);
9429 if (!inst.operands[1].immisreg)
9430 {
9431 /* Immediate offset. */
9432 inst.instruction |= inst.operands[0].reg;
9433 inst.instruction |= inst.operands[1].reg << 3;
9434 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9435 return;
9436 }
90e4755a 9437
c19d1205
ZW
9438 /* Register offset. */
9439 constraint (inst.operands[1].imm > 7, BAD_HIREG);
9440 constraint (inst.operands[1].negative,
9441 _("Thumb does not support this addressing mode"));
90e4755a 9442
c19d1205
ZW
9443 op16:
9444 switch (inst.instruction)
9445 {
9446 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
9447 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
9448 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
9449 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
9450 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
9451 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
9452 case 0x5600 /* ldrsb */:
9453 case 0x5e00 /* ldrsh */: break;
9454 default: abort ();
9455 }
90e4755a 9456
c19d1205
ZW
9457 inst.instruction |= inst.operands[0].reg;
9458 inst.instruction |= inst.operands[1].reg << 3;
9459 inst.instruction |= inst.operands[1].imm << 6;
9460}
90e4755a 9461
c19d1205
ZW
9462static void
9463do_t_ldstd (void)
9464{
9465 if (!inst.operands[1].present)
b99bd4ef 9466 {
c19d1205
ZW
9467 inst.operands[1].reg = inst.operands[0].reg + 1;
9468 constraint (inst.operands[0].reg == REG_LR,
9469 _("r14 not allowed here"));
b99bd4ef 9470 }
c19d1205
ZW
9471 inst.instruction |= inst.operands[0].reg << 12;
9472 inst.instruction |= inst.operands[1].reg << 8;
9473 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC
9474}
9475
c19d1205
ZW
9476static void
9477do_t_ldstt (void)
9478{
9479 inst.instruction |= inst.operands[0].reg << 12;
9480 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
9481}
a737bd4d 9482
b99bd4ef 9483static void
c19d1205 9484do_t_mla (void)
b99bd4ef 9485{
c19d1205
ZW
9486 inst.instruction |= inst.operands[0].reg << 8;
9487 inst.instruction |= inst.operands[1].reg << 16;
9488 inst.instruction |= inst.operands[2].reg;
9489 inst.instruction |= inst.operands[3].reg << 12;
9490}
b99bd4ef 9491
c19d1205
ZW
9492static void
9493do_t_mlal (void)
9494{
9495 inst.instruction |= inst.operands[0].reg << 12;
9496 inst.instruction |= inst.operands[1].reg << 8;
9497 inst.instruction |= inst.operands[2].reg << 16;
9498 inst.instruction |= inst.operands[3].reg;
9499}
b99bd4ef 9500
c19d1205
ZW
9501static void
9502do_t_mov_cmp (void)
9503{
9504 if (unified_syntax)
b99bd4ef 9505 {
c19d1205
ZW
9506 int r0off = (inst.instruction == T_MNEM_mov
9507 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 9508 unsigned long opcode;
3d388997
PB
9509 bfd_boolean narrow;
9510 bfd_boolean low_regs;
9511
9512 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
0110f2b8 9513 opcode = inst.instruction;
3d388997 9514 if (current_it_mask)
0110f2b8 9515 narrow = opcode != T_MNEM_movs;
3d388997 9516 else
0110f2b8 9517 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB
9518 if (inst.size_req == 4
9519 || inst.operands[1].shifted)
9520 narrow = FALSE;
9521
efd81785
PB
9522 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9523 if (opcode == T_MNEM_movs && inst.operands[1].isreg
9524 && !inst.operands[1].shifted
9525 && inst.operands[0].reg == REG_PC
9526 && inst.operands[1].reg == REG_LR)
9527 {
9528 inst.instruction = T2_SUBS_PC_LR;
9529 return;
9530 }
9531
c19d1205
ZW
9532 if (!inst.operands[1].isreg)
9533 {
0110f2b8
PB
9534 /* Immediate operand. */
9535 if (current_it_mask == 0 && opcode == T_MNEM_mov)
9536 narrow = 0;
9537 if (low_regs && narrow)
9538 {
9539 inst.instruction = THUMB_OP16 (opcode);
9540 inst.instruction |= inst.operands[0].reg << 8;
9541 if (inst.size_req == 2)
9542 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9543 else
9544 inst.relax = opcode;
9545 }
9546 else
9547 {
9548 inst.instruction = THUMB_OP32 (inst.instruction);
9549 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9550 inst.instruction |= inst.operands[0].reg << r0off;
9551 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9552 }
c19d1205 9553 }
728ca7c9
PB
9554 else if (inst.operands[1].shifted && inst.operands[1].immisreg
9555 && (inst.instruction == T_MNEM_mov
9556 || inst.instruction == T_MNEM_movs))
9557 {
9558 /* Register shifts are encoded as separate shift instructions. */
9559 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
9560
9561 if (current_it_mask)
9562 narrow = !flags;
9563 else
9564 narrow = flags;
9565
9566 if (inst.size_req == 4)
9567 narrow = FALSE;
9568
9569 if (!low_regs || inst.operands[1].imm > 7)
9570 narrow = FALSE;
9571
9572 if (inst.operands[0].reg != inst.operands[1].reg)
9573 narrow = FALSE;
9574
9575 switch (inst.operands[1].shift_kind)
9576 {
9577 case SHIFT_LSL:
9578 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
9579 break;
9580 case SHIFT_ASR:
9581 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
9582 break;
9583 case SHIFT_LSR:
9584 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
9585 break;
9586 case SHIFT_ROR:
9587 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
9588 break;
9589 default:
5f4273c7 9590 abort ();
728ca7c9
PB
9591 }
9592
9593 inst.instruction = opcode;
9594 if (narrow)
9595 {
9596 inst.instruction |= inst.operands[0].reg;
9597 inst.instruction |= inst.operands[1].imm << 3;
9598 }
9599 else
9600 {
9601 if (flags)
9602 inst.instruction |= CONDS_BIT;
9603
9604 inst.instruction |= inst.operands[0].reg << 8;
9605 inst.instruction |= inst.operands[1].reg << 16;
9606 inst.instruction |= inst.operands[1].imm;
9607 }
9608 }
3d388997 9609 else if (!narrow)
c19d1205 9610 {
728ca7c9
PB
9611 /* Some mov with immediate shift have narrow variants.
9612 Register shifts are handled above. */
9613 if (low_regs && inst.operands[1].shifted
9614 && (inst.instruction == T_MNEM_mov
9615 || inst.instruction == T_MNEM_movs))
9616 {
9617 if (current_it_mask)
9618 narrow = (inst.instruction == T_MNEM_mov);
9619 else
9620 narrow = (inst.instruction == T_MNEM_movs);
9621 }
9622
9623 if (narrow)
9624 {
9625 switch (inst.operands[1].shift_kind)
9626 {
9627 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
9628 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
9629 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
9630 default: narrow = FALSE; break;
9631 }
9632 }
9633
9634 if (narrow)
9635 {
9636 inst.instruction |= inst.operands[0].reg;
9637 inst.instruction |= inst.operands[1].reg << 3;
9638 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
9639 }
9640 else
9641 {
9642 inst.instruction = THUMB_OP32 (inst.instruction);
9643 inst.instruction |= inst.operands[0].reg << r0off;
9644 encode_thumb32_shifted_operand (1);
9645 }
c19d1205
ZW
9646 }
9647 else
9648 switch (inst.instruction)
9649 {
9650 case T_MNEM_mov:
9651 inst.instruction = T_OPCODE_MOV_HR;
9652 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9653 inst.instruction |= (inst.operands[0].reg & 0x7);
9654 inst.instruction |= inst.operands[1].reg << 3;
9655 break;
b99bd4ef 9656
c19d1205
ZW
9657 case T_MNEM_movs:
9658 /* We know we have low registers at this point.
9659 Generate ADD Rd, Rs, #0. */
9660 inst.instruction = T_OPCODE_ADD_I3;
9661 inst.instruction |= inst.operands[0].reg;
9662 inst.instruction |= inst.operands[1].reg << 3;
9663 break;
9664
9665 case T_MNEM_cmp:
3d388997 9666 if (low_regs)
c19d1205
ZW
9667 {
9668 inst.instruction = T_OPCODE_CMP_LR;
9669 inst.instruction |= inst.operands[0].reg;
9670 inst.instruction |= inst.operands[1].reg << 3;
9671 }
9672 else
9673 {
9674 inst.instruction = T_OPCODE_CMP_HR;
9675 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9676 inst.instruction |= (inst.operands[0].reg & 0x7);
9677 inst.instruction |= inst.operands[1].reg << 3;
9678 }
9679 break;
9680 }
b99bd4ef
NC
9681 return;
9682 }
9683
c19d1205
ZW
9684 inst.instruction = THUMB_OP16 (inst.instruction);
9685 if (inst.operands[1].isreg)
b99bd4ef 9686 {
c19d1205 9687 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
b99bd4ef 9688 {
c19d1205
ZW
9689 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9690 since a MOV instruction produces unpredictable results. */
9691 if (inst.instruction == T_OPCODE_MOV_I8)
9692 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 9693 else
c19d1205 9694 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 9695
c19d1205
ZW
9696 inst.instruction |= inst.operands[0].reg;
9697 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
9698 }
9699 else
9700 {
c19d1205
ZW
9701 if (inst.instruction == T_OPCODE_MOV_I8)
9702 inst.instruction = T_OPCODE_MOV_HR;
9703 else
9704 inst.instruction = T_OPCODE_CMP_HR;
9705 do_t_cpy ();
b99bd4ef
NC
9706 }
9707 }
c19d1205 9708 else
b99bd4ef 9709 {
c19d1205
ZW
9710 constraint (inst.operands[0].reg > 7,
9711 _("only lo regs allowed with immediate"));
9712 inst.instruction |= inst.operands[0].reg << 8;
9713 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9714 }
9715}
b99bd4ef 9716
c19d1205
ZW
9717static void
9718do_t_mov16 (void)
9719{
b6895b4f
PB
9720 bfd_vma imm;
9721 bfd_boolean top;
9722
9723 top = (inst.instruction & 0x00800000) != 0;
9724 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
9725 {
9726 constraint (top, _(":lower16: not allowed this instruction"));
9727 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
9728 }
9729 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
9730 {
9731 constraint (!top, _(":upper16: not allowed this instruction"));
9732 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
9733 }
9734
c19d1205 9735 inst.instruction |= inst.operands[0].reg << 8;
b6895b4f
PB
9736 if (inst.reloc.type == BFD_RELOC_UNUSED)
9737 {
9738 imm = inst.reloc.exp.X_add_number;
9739 inst.instruction |= (imm & 0xf000) << 4;
9740 inst.instruction |= (imm & 0x0800) << 15;
9741 inst.instruction |= (imm & 0x0700) << 4;
9742 inst.instruction |= (imm & 0x00ff);
9743 }
c19d1205 9744}
b99bd4ef 9745
c19d1205
ZW
9746static void
9747do_t_mvn_tst (void)
9748{
9749 if (unified_syntax)
9750 {
9751 int r0off = (inst.instruction == T_MNEM_mvn
9752 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB
9753 bfd_boolean narrow;
9754
9755 if (inst.size_req == 4
9756 || inst.instruction > 0xffff
9757 || inst.operands[1].shifted
9758 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9759 narrow = FALSE;
9760 else if (inst.instruction == T_MNEM_cmn)
9761 narrow = TRUE;
9762 else if (THUMB_SETS_FLAGS (inst.instruction))
9763 narrow = (current_it_mask == 0);
9764 else
9765 narrow = (current_it_mask != 0);
9766
c19d1205 9767 if (!inst.operands[1].isreg)
b99bd4ef 9768 {
c19d1205
ZW
9769 /* For an immediate, we always generate a 32-bit opcode;
9770 section relaxation will shrink it later if possible. */
9771 if (inst.instruction < 0xffff)
9772 inst.instruction = THUMB_OP32 (inst.instruction);
9773 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9774 inst.instruction |= inst.operands[0].reg << r0off;
9775 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 9776 }
c19d1205 9777 else
b99bd4ef 9778 {
c19d1205 9779 /* See if we can do this with a 16-bit instruction. */
3d388997 9780 if (narrow)
b99bd4ef 9781 {
c19d1205
ZW
9782 inst.instruction = THUMB_OP16 (inst.instruction);
9783 inst.instruction |= inst.operands[0].reg;
9784 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef 9785 }
c19d1205 9786 else
b99bd4ef 9787 {
c19d1205
ZW
9788 constraint (inst.operands[1].shifted
9789 && inst.operands[1].immisreg,
9790 _("shift must be constant"));
9791 if (inst.instruction < 0xffff)
9792 inst.instruction = THUMB_OP32 (inst.instruction);
9793 inst.instruction |= inst.operands[0].reg << r0off;
9794 encode_thumb32_shifted_operand (1);
b99bd4ef 9795 }
b99bd4ef
NC
9796 }
9797 }
9798 else
9799 {
c19d1205
ZW
9800 constraint (inst.instruction > 0xffff
9801 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
9802 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
9803 _("unshifted register required"));
9804 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9805 BAD_HIREG);
b99bd4ef 9806
c19d1205
ZW
9807 inst.instruction = THUMB_OP16 (inst.instruction);
9808 inst.instruction |= inst.operands[0].reg;
9809 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef 9810 }
b99bd4ef
NC
9811}
9812
b05fe5cf 9813static void
c19d1205 9814do_t_mrs (void)
b05fe5cf 9815{
62b3e311 9816 int flags;
037e8744
JB
9817
9818 if (do_vfp_nsyn_mrs () == SUCCESS)
9819 return;
9820
62b3e311
PB
9821 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9822 if (flags == 0)
9823 {
7e806470 9824 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
62b3e311
PB
9825 _("selected processor does not support "
9826 "requested special purpose register"));
9827 }
9828 else
9829 {
9830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9831 _("selected processor does not support "
44bf2362 9832 "requested special purpose register"));
62b3e311
PB
9833 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9834 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
9835 _("'CPSR' or 'SPSR' expected"));
9836 }
5f4273c7 9837
c19d1205 9838 inst.instruction |= inst.operands[0].reg << 8;
62b3e311
PB
9839 inst.instruction |= (flags & SPSR_BIT) >> 2;
9840 inst.instruction |= inst.operands[1].imm & 0xff;
c19d1205 9841}
b05fe5cf 9842
c19d1205
ZW
9843static void
9844do_t_msr (void)
9845{
62b3e311
PB
9846 int flags;
9847
037e8744
JB
9848 if (do_vfp_nsyn_msr () == SUCCESS)
9849 return;
9850
c19d1205
ZW
9851 constraint (!inst.operands[1].isreg,
9852 _("Thumb encoding does not support an immediate here"));
62b3e311
PB
9853 flags = inst.operands[0].imm;
9854 if (flags & ~0xff)
9855 {
9856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9857 _("selected processor does not support "
9858 "requested special purpose register"));
9859 }
9860 else
9861 {
7e806470 9862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
62b3e311
PB
9863 _("selected processor does not support "
9864 "requested special purpose register"));
9865 flags |= PSR_f;
9866 }
9867 inst.instruction |= (flags & SPSR_BIT) >> 2;
9868 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
9869 inst.instruction |= (flags & 0xff);
c19d1205
ZW
9870 inst.instruction |= inst.operands[1].reg << 16;
9871}
b05fe5cf 9872
c19d1205
ZW
9873static void
9874do_t_mul (void)
9875{
9876 if (!inst.operands[2].present)
9877 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 9878
c19d1205
ZW
9879 /* There is no 32-bit MULS and no 16-bit MUL. */
9880 if (unified_syntax && inst.instruction == T_MNEM_mul)
b05fe5cf 9881 {
c19d1205
ZW
9882 inst.instruction = THUMB_OP32 (inst.instruction);
9883 inst.instruction |= inst.operands[0].reg << 8;
9884 inst.instruction |= inst.operands[1].reg << 16;
9885 inst.instruction |= inst.operands[2].reg << 0;
b05fe5cf 9886 }
c19d1205 9887 else
b05fe5cf 9888 {
c19d1205
ZW
9889 constraint (!unified_syntax
9890 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
9891 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9892 BAD_HIREG);
b05fe5cf 9893
c19d1205
ZW
9894 inst.instruction = THUMB_OP16 (inst.instruction);
9895 inst.instruction |= inst.operands[0].reg;
b05fe5cf 9896
c19d1205
ZW
9897 if (inst.operands[0].reg == inst.operands[1].reg)
9898 inst.instruction |= inst.operands[2].reg << 3;
9899 else if (inst.operands[0].reg == inst.operands[2].reg)
9900 inst.instruction |= inst.operands[1].reg << 3;
9901 else
9902 constraint (1, _("dest must overlap one source register"));
9903 }
9904}
b05fe5cf 9905
c19d1205
ZW
9906static void
9907do_t_mull (void)
9908{
9909 inst.instruction |= inst.operands[0].reg << 12;
9910 inst.instruction |= inst.operands[1].reg << 8;
9911 inst.instruction |= inst.operands[2].reg << 16;
9912 inst.instruction |= inst.operands[3].reg;
b05fe5cf 9913
c19d1205
ZW
9914 if (inst.operands[0].reg == inst.operands[1].reg)
9915 as_tsktsk (_("rdhi and rdlo must be different"));
9916}
b05fe5cf 9917
c19d1205
ZW
9918static void
9919do_t_nop (void)
9920{
9921 if (unified_syntax)
9922 {
9923 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 9924 {
c19d1205
ZW
9925 inst.instruction = THUMB_OP32 (inst.instruction);
9926 inst.instruction |= inst.operands[0].imm;
9927 }
9928 else
9929 {
bc2d1808
NC
9930 /* PR9722: Check for Thumb2 availability before
9931 generating a thumb2 nop instruction. */
9932 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
9933 {
9934 inst.instruction = THUMB_OP16 (inst.instruction);
9935 inst.instruction |= inst.operands[0].imm << 4;
9936 }
9937 else
9938 inst.instruction = 0x46c0;
c19d1205
ZW
9939 }
9940 }
9941 else
9942 {
9943 constraint (inst.operands[0].present,
9944 _("Thumb does not support NOP with hints"));
9945 inst.instruction = 0x46c0;
9946 }
9947}
b05fe5cf 9948
c19d1205
ZW
9949static void
9950do_t_neg (void)
9951{
9952 if (unified_syntax)
9953 {
3d388997
PB
9954 bfd_boolean narrow;
9955
9956 if (THUMB_SETS_FLAGS (inst.instruction))
9957 narrow = (current_it_mask == 0);
9958 else
9959 narrow = (current_it_mask != 0);
9960 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9961 narrow = FALSE;
9962 if (inst.size_req == 4)
9963 narrow = FALSE;
9964
9965 if (!narrow)
c19d1205
ZW
9966 {
9967 inst.instruction = THUMB_OP32 (inst.instruction);
9968 inst.instruction |= inst.operands[0].reg << 8;
9969 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW
9970 }
9971 else
9972 {
c19d1205
ZW
9973 inst.instruction = THUMB_OP16 (inst.instruction);
9974 inst.instruction |= inst.operands[0].reg;
9975 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW
9976 }
9977 }
9978 else
9979 {
c19d1205
ZW
9980 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9981 BAD_HIREG);
9982 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9983
9984 inst.instruction = THUMB_OP16 (inst.instruction);
9985 inst.instruction |= inst.operands[0].reg;
9986 inst.instruction |= inst.operands[1].reg << 3;
9987 }
9988}
9989
9990static void
9991do_t_pkhbt (void)
9992{
9993 inst.instruction |= inst.operands[0].reg << 8;
9994 inst.instruction |= inst.operands[1].reg << 16;
9995 inst.instruction |= inst.operands[2].reg;
9996 if (inst.operands[3].present)
9997 {
9998 unsigned int val = inst.reloc.exp.X_add_number;
9999 constraint (inst.reloc.exp.X_op != O_constant,
10000 _("expression too complex"));
10001 inst.instruction |= (val & 0x1c) << 10;
10002 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 10003 }
c19d1205 10004}
b05fe5cf 10005
c19d1205
ZW
10006static void
10007do_t_pkhtb (void)
10008{
10009 if (!inst.operands[3].present)
10010 inst.instruction &= ~0x00000020;
10011 do_t_pkhbt ();
b05fe5cf
ZW
10012}
10013
c19d1205
ZW
10014static void
10015do_t_pld (void)
10016{
10017 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
10018}
b05fe5cf 10019
c19d1205
ZW
10020static void
10021do_t_push_pop (void)
b99bd4ef 10022{
e9f89963 10023 unsigned mask;
5f4273c7 10024
c19d1205
ZW
10025 constraint (inst.operands[0].writeback,
10026 _("push/pop do not support {reglist}^"));
10027 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10028 _("expression too complex"));
b99bd4ef 10029
e9f89963
PB
10030 mask = inst.operands[0].imm;
10031 if ((mask & ~0xff) == 0)
3c707909 10032 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
c19d1205 10033 else if ((inst.instruction == T_MNEM_push
e9f89963 10034 && (mask & ~0xff) == 1 << REG_LR)
c19d1205 10035 || (inst.instruction == T_MNEM_pop
e9f89963 10036 && (mask & ~0xff) == 1 << REG_PC))
b99bd4ef 10037 {
c19d1205
ZW
10038 inst.instruction = THUMB_OP16 (inst.instruction);
10039 inst.instruction |= THUMB_PP_PC_LR;
3c707909 10040 inst.instruction |= mask & 0xff;
c19d1205
ZW
10041 }
10042 else if (unified_syntax)
10043 {
3c707909 10044 inst.instruction = THUMB_OP32 (inst.instruction);
5f4273c7 10045 encode_thumb2_ldmstm (13, mask, TRUE);
c19d1205
ZW
10046 }
10047 else
10048 {
10049 inst.error = _("invalid register list to push/pop instruction");
10050 return;
10051 }
c19d1205 10052}
b99bd4ef 10053
c19d1205
ZW
10054static void
10055do_t_rbit (void)
10056{
10057 inst.instruction |= inst.operands[0].reg << 8;
10058 inst.instruction |= inst.operands[1].reg << 16;
4ecab7d4 10059 inst.instruction |= inst.operands[1].reg;
c19d1205 10060}
b99bd4ef 10061
c19d1205
ZW
10062static void
10063do_t_rev (void)
10064{
10065 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10066 && inst.size_req != 4)
10067 {
10068 inst.instruction = THUMB_OP16 (inst.instruction);
10069 inst.instruction |= inst.operands[0].reg;
10070 inst.instruction |= inst.operands[1].reg << 3;
10071 }
10072 else if (unified_syntax)
10073 {
10074 inst.instruction = THUMB_OP32 (inst.instruction);
10075 inst.instruction |= inst.operands[0].reg << 8;
10076 inst.instruction |= inst.operands[1].reg << 16;
10077 inst.instruction |= inst.operands[1].reg;
10078 }
10079 else
10080 inst.error = BAD_HIREG;
10081}
b99bd4ef 10082
c19d1205
ZW
10083static void
10084do_t_rsb (void)
10085{
10086 int Rd, Rs;
b99bd4ef 10087
c19d1205
ZW
10088 Rd = inst.operands[0].reg;
10089 Rs = (inst.operands[1].present
10090 ? inst.operands[1].reg /* Rd, Rs, foo */
10091 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 10092
c19d1205
ZW
10093 inst.instruction |= Rd << 8;
10094 inst.instruction |= Rs << 16;
10095 if (!inst.operands[2].isreg)
10096 {
026d3abb
PB
10097 bfd_boolean narrow;
10098
10099 if ((inst.instruction & 0x00100000) != 0)
10100 narrow = (current_it_mask == 0);
10101 else
10102 narrow = (current_it_mask != 0);
10103
10104 if (Rd > 7 || Rs > 7)
10105 narrow = FALSE;
10106
10107 if (inst.size_req == 4 || !unified_syntax)
10108 narrow = FALSE;
10109
10110 if (inst.reloc.exp.X_op != O_constant
10111 || inst.reloc.exp.X_add_number != 0)
10112 narrow = FALSE;
10113
10114 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10115 relaxation, but it doesn't seem worth the hassle. */
10116 if (narrow)
10117 {
10118 inst.reloc.type = BFD_RELOC_UNUSED;
10119 inst.instruction = THUMB_OP16 (T_MNEM_negs);
10120 inst.instruction |= Rs << 3;
10121 inst.instruction |= Rd;
10122 }
10123 else
10124 {
10125 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10126 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10127 }
c19d1205
ZW
10128 }
10129 else
10130 encode_thumb32_shifted_operand (2);
10131}
b99bd4ef 10132
c19d1205
ZW
10133static void
10134do_t_setend (void)
10135{
dfa9f0d5 10136 constraint (current_it_mask, BAD_NOT_IT);
c19d1205
ZW
10137 if (inst.operands[0].imm)
10138 inst.instruction |= 0x8;
10139}
b99bd4ef 10140
c19d1205
ZW
10141static void
10142do_t_shift (void)
10143{
10144 if (!inst.operands[1].present)
10145 inst.operands[1].reg = inst.operands[0].reg;
10146
10147 if (unified_syntax)
10148 {
3d388997
PB
10149 bfd_boolean narrow;
10150 int shift_kind;
10151
10152 switch (inst.instruction)
10153 {
10154 case T_MNEM_asr:
10155 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
10156 case T_MNEM_lsl:
10157 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
10158 case T_MNEM_lsr:
10159 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
10160 case T_MNEM_ror:
10161 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
10162 default: abort ();
10163 }
10164
10165 if (THUMB_SETS_FLAGS (inst.instruction))
10166 narrow = (current_it_mask == 0);
10167 else
10168 narrow = (current_it_mask != 0);
10169 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10170 narrow = FALSE;
10171 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
10172 narrow = FALSE;
10173 if (inst.operands[2].isreg
10174 && (inst.operands[1].reg != inst.operands[0].reg
10175 || inst.operands[2].reg > 7))
10176 narrow = FALSE;
10177 if (inst.size_req == 4)
10178 narrow = FALSE;
10179
10180 if (!narrow)
c19d1205
ZW
10181 {
10182 if (inst.operands[2].isreg)
b99bd4ef 10183 {
c19d1205
ZW
10184 inst.instruction = THUMB_OP32 (inst.instruction);
10185 inst.instruction |= inst.operands[0].reg << 8;
10186 inst.instruction |= inst.operands[1].reg << 16;
10187 inst.instruction |= inst.operands[2].reg;
10188 }
10189 else
10190 {
10191 inst.operands[1].shifted = 1;
3d388997 10192 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW
10193 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
10194 ? T_MNEM_movs : T_MNEM_mov);
10195 inst.instruction |= inst.operands[0].reg << 8;
10196 encode_thumb32_shifted_operand (1);
10197 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10198 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef
NC
10199 }
10200 }
10201 else
10202 {
c19d1205 10203 if (inst.operands[2].isreg)
b99bd4ef 10204 {
3d388997 10205 switch (shift_kind)
b99bd4ef 10206 {
3d388997
PB
10207 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
10208 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
10209 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
10210 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 10211 default: abort ();
b99bd4ef 10212 }
5f4273c7 10213
c19d1205
ZW
10214 inst.instruction |= inst.operands[0].reg;
10215 inst.instruction |= inst.operands[2].reg << 3;
b99bd4ef
NC
10216 }
10217 else
10218 {
3d388997 10219 switch (shift_kind)
b99bd4ef 10220 {
3d388997
PB
10221 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10222 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10223 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 10224 default: abort ();
b99bd4ef 10225 }
c19d1205
ZW
10226 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10227 inst.instruction |= inst.operands[0].reg;
10228 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
10229 }
10230 }
c19d1205
ZW
10231 }
10232 else
10233 {
10234 constraint (inst.operands[0].reg > 7
10235 || inst.operands[1].reg > 7, BAD_HIREG);
10236 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 10237
c19d1205
ZW
10238 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
10239 {
10240 constraint (inst.operands[2].reg > 7, BAD_HIREG);
10241 constraint (inst.operands[0].reg != inst.operands[1].reg,
10242 _("source1 and dest must be same register"));
b99bd4ef 10243
c19d1205
ZW
10244 switch (inst.instruction)
10245 {
10246 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
10247 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
10248 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
10249 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
10250 default: abort ();
10251 }
5f4273c7 10252
c19d1205
ZW
10253 inst.instruction |= inst.operands[0].reg;
10254 inst.instruction |= inst.operands[2].reg << 3;
10255 }
10256 else
b99bd4ef 10257 {
c19d1205
ZW
10258 switch (inst.instruction)
10259 {
10260 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
10261 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
10262 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
10263 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10264 default: abort ();
10265 }
10266 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10267 inst.instruction |= inst.operands[0].reg;
10268 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC
10269 }
10270 }
b99bd4ef
NC
10271}
10272
10273static void
c19d1205 10274do_t_simd (void)
b99bd4ef 10275{
c19d1205
ZW
10276 inst.instruction |= inst.operands[0].reg << 8;
10277 inst.instruction |= inst.operands[1].reg << 16;
10278 inst.instruction |= inst.operands[2].reg;
10279}
b99bd4ef 10280
c19d1205 10281static void
3eb17e6b 10282do_t_smc (void)
c19d1205
ZW
10283{
10284 unsigned int value = inst.reloc.exp.X_add_number;
10285 constraint (inst.reloc.exp.X_op != O_constant,
10286 _("expression too complex"));
10287 inst.reloc.type = BFD_RELOC_UNUSED;
10288 inst.instruction |= (value & 0xf000) >> 12;
10289 inst.instruction |= (value & 0x0ff0);
10290 inst.instruction |= (value & 0x000f) << 16;
10291}
b99bd4ef 10292
c19d1205
ZW
10293static void
10294do_t_ssat (void)
10295{
10296 inst.instruction |= inst.operands[0].reg << 8;
10297 inst.instruction |= inst.operands[1].imm - 1;
10298 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef 10299
c19d1205 10300 if (inst.operands[3].present)
b99bd4ef 10301 {
c19d1205
ZW
10302 constraint (inst.reloc.exp.X_op != O_constant,
10303 _("expression too complex"));
b99bd4ef 10304
c19d1205 10305 if (inst.reloc.exp.X_add_number != 0)
6189168b 10306 {
c19d1205
ZW
10307 if (inst.operands[3].shift_kind == SHIFT_ASR)
10308 inst.instruction |= 0x00200000; /* sh bit */
10309 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10310 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
6189168b 10311 }
c19d1205 10312 inst.reloc.type = BFD_RELOC_UNUSED;
6189168b 10313 }
b99bd4ef
NC
10314}
10315
0dd132b6 10316static void
c19d1205 10317do_t_ssat16 (void)
0dd132b6 10318{
c19d1205
ZW
10319 inst.instruction |= inst.operands[0].reg << 8;
10320 inst.instruction |= inst.operands[1].imm - 1;
10321 inst.instruction |= inst.operands[2].reg << 16;
10322}
0dd132b6 10323
c19d1205
ZW
10324static void
10325do_t_strex (void)
10326{
10327 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10328 || inst.operands[2].postind || inst.operands[2].writeback
10329 || inst.operands[2].immisreg || inst.operands[2].shifted
10330 || inst.operands[2].negative,
01cfc07f 10331 BAD_ADDR_MODE);
0dd132b6 10332
c19d1205
ZW
10333 inst.instruction |= inst.operands[0].reg << 8;
10334 inst.instruction |= inst.operands[1].reg << 12;
10335 inst.instruction |= inst.operands[2].reg << 16;
10336 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC
10337}
10338
b99bd4ef 10339static void
c19d1205 10340do_t_strexd (void)
b99bd4ef 10341{
c19d1205
ZW
10342 if (!inst.operands[2].present)
10343 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 10344
c19d1205
ZW
10345 constraint (inst.operands[0].reg == inst.operands[1].reg
10346 || inst.operands[0].reg == inst.operands[2].reg
10347 || inst.operands[0].reg == inst.operands[3].reg
10348 || inst.operands[1].reg == inst.operands[2].reg,
10349 BAD_OVERLAP);
b99bd4ef 10350
c19d1205
ZW
10351 inst.instruction |= inst.operands[0].reg;
10352 inst.instruction |= inst.operands[1].reg << 12;
10353 inst.instruction |= inst.operands[2].reg << 8;
10354 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC
10355}
10356
10357static void
c19d1205 10358do_t_sxtah (void)
b99bd4ef 10359{
c19d1205
ZW
10360 inst.instruction |= inst.operands[0].reg << 8;
10361 inst.instruction |= inst.operands[1].reg << 16;
10362 inst.instruction |= inst.operands[2].reg;
10363 inst.instruction |= inst.operands[3].imm << 4;
10364}
b99bd4ef 10365
c19d1205
ZW
10366static void
10367do_t_sxth (void)
10368{
10369 if (inst.instruction <= 0xffff && inst.size_req != 4
10370 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10371 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 10372 {
c19d1205
ZW
10373 inst.instruction = THUMB_OP16 (inst.instruction);
10374 inst.instruction |= inst.operands[0].reg;
10375 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef 10376 }
c19d1205 10377 else if (unified_syntax)
b99bd4ef 10378 {
c19d1205
ZW
10379 if (inst.instruction <= 0xffff)
10380 inst.instruction = THUMB_OP32 (inst.instruction);
10381 inst.instruction |= inst.operands[0].reg << 8;
10382 inst.instruction |= inst.operands[1].reg;
10383 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 10384 }
c19d1205 10385 else
b99bd4ef 10386 {
c19d1205
ZW
10387 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10388 _("Thumb encoding does not support rotation"));
10389 constraint (1, BAD_HIREG);
b99bd4ef 10390 }
c19d1205 10391}
b99bd4ef 10392
c19d1205
ZW
10393static void
10394do_t_swi (void)
10395{
10396 inst.reloc.type = BFD_RELOC_ARM_SWI;
10397}
b99bd4ef 10398
92e90b6e
PB
10399static void
10400do_t_tb (void)
10401{
10402 int half;
10403
10404 half = (inst.instruction & 0x10) != 0;
dfa9f0d5
PB
10405 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
10406 constraint (inst.operands[0].immisreg,
10407 _("instruction requires register index"));
92e90b6e
PB
10408 constraint (inst.operands[0].imm == 15,
10409 _("PC is not a valid index register"));
10410 constraint (!half && inst.operands[0].shifted,
10411 _("instruction does not allow shifted index"));
92e90b6e
PB
10412 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10413}
10414
c19d1205
ZW
10415static void
10416do_t_usat (void)
10417{
10418 inst.instruction |= inst.operands[0].reg << 8;
10419 inst.instruction |= inst.operands[1].imm;
10420 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef 10421
c19d1205 10422 if (inst.operands[3].present)
b99bd4ef 10423 {
c19d1205
ZW
10424 constraint (inst.reloc.exp.X_op != O_constant,
10425 _("expression too complex"));
10426 if (inst.reloc.exp.X_add_number != 0)
10427 {
10428 if (inst.operands[3].shift_kind == SHIFT_ASR)
10429 inst.instruction |= 0x00200000; /* sh bit */
b99bd4ef 10430
c19d1205
ZW
10431 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10432 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10433 }
10434 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 10435 }
b99bd4ef
NC
10436}
10437
10438static void
c19d1205 10439do_t_usat16 (void)
b99bd4ef 10440{
c19d1205
ZW
10441 inst.instruction |= inst.operands[0].reg << 8;
10442 inst.instruction |= inst.operands[1].imm;
10443 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef 10444}
c19d1205 10445
5287ad62 10446/* Neon instruction encoder helpers. */
5f4273c7 10447
5287ad62 10448/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 10449
5287ad62
JB
10450/* An "invalid" code for the following tables. */
10451#define N_INV -1u
10452
10453struct neon_tab_entry
b99bd4ef 10454{
5287ad62
JB
10455 unsigned integer;
10456 unsigned float_or_poly;
10457 unsigned scalar_or_imm;
10458};
5f4273c7 10459
5287ad62
JB
10460/* Map overloaded Neon opcodes to their respective encodings. */
10461#define NEON_ENC_TAB \
10462 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10463 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10464 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10465 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10466 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10467 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10468 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10469 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10470 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10471 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10472 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10473 /* Register variants of the following two instructions are encoded as
10474 vcge / vcgt with the operands reversed. */ \
92559b5b
PB
10475 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10476 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
5287ad62
JB
10477 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10478 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10479 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10480 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10481 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10482 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10483 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10484 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10485 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10486 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10487 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10488 X(vshl, 0x0000400, N_INV, 0x0800510), \
10489 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10490 X(vand, 0x0000110, N_INV, 0x0800030), \
10491 X(vbic, 0x0100110, N_INV, 0x0800030), \
10492 X(veor, 0x1000110, N_INV, N_INV), \
10493 X(vorn, 0x0300110, N_INV, 0x0800010), \
10494 X(vorr, 0x0200110, N_INV, 0x0800010), \
10495 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10496 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10497 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10498 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10499 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10500 X(vst1, 0x0000000, 0x0800000, N_INV), \
10501 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10502 X(vst2, 0x0000100, 0x0800100, N_INV), \
10503 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10504 X(vst3, 0x0000200, 0x0800200, N_INV), \
10505 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10506 X(vst4, 0x0000300, 0x0800300, N_INV), \
10507 X(vmovn, 0x1b20200, N_INV, N_INV), \
10508 X(vtrn, 0x1b20080, N_INV, N_INV), \
10509 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB
10510 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10511 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10512 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10513 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10514 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10515 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10516 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10517 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
5287ad62
JB
10518
10519enum neon_opc
10520{
10521#define X(OPC,I,F,S) N_MNEM_##OPC
10522NEON_ENC_TAB
10523#undef X
10524};
b99bd4ef 10525
5287ad62
JB
10526static const struct neon_tab_entry neon_enc_tab[] =
10527{
10528#define X(OPC,I,F,S) { (I), (F), (S) }
10529NEON_ENC_TAB
10530#undef X
10531};
b99bd4ef 10532
5287ad62
JB
10533#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10534#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10535#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10536#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10537#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10538#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10539#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10540#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10541#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
037e8744
JB
10542#define NEON_ENC_SINGLE(X) \
10543 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10544#define NEON_ENC_DOUBLE(X) \
10545 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
5287ad62 10546
037e8744
JB
10547/* Define shapes for instruction operands. The following mnemonic characters
10548 are used in this table:
5287ad62 10549
037e8744 10550 F - VFP S<n> register
5287ad62
JB
10551 D - Neon D<n> register
10552 Q - Neon Q<n> register
10553 I - Immediate
10554 S - Scalar
10555 R - ARM register
10556 L - D<n> register list
5f4273c7 10557
037e8744
JB
10558 This table is used to generate various data:
10559 - enumerations of the form NS_DDR to be used as arguments to
10560 neon_select_shape.
10561 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 10562 - a table used to drive neon_select_shape. */
b99bd4ef 10563
037e8744
JB
10564#define NEON_SHAPE_DEF \
10565 X(3, (D, D, D), DOUBLE), \
10566 X(3, (Q, Q, Q), QUAD), \
10567 X(3, (D, D, I), DOUBLE), \
10568 X(3, (Q, Q, I), QUAD), \
10569 X(3, (D, D, S), DOUBLE), \
10570 X(3, (Q, Q, S), QUAD), \
10571 X(2, (D, D), DOUBLE), \
10572 X(2, (Q, Q), QUAD), \
10573 X(2, (D, S), DOUBLE), \
10574 X(2, (Q, S), QUAD), \
10575 X(2, (D, R), DOUBLE), \
10576 X(2, (Q, R), QUAD), \
10577 X(2, (D, I), DOUBLE), \
10578 X(2, (Q, I), QUAD), \
10579 X(3, (D, L, D), DOUBLE), \
10580 X(2, (D, Q), MIXED), \
10581 X(2, (Q, D), MIXED), \
10582 X(3, (D, Q, I), MIXED), \
10583 X(3, (Q, D, I), MIXED), \
10584 X(3, (Q, D, D), MIXED), \
10585 X(3, (D, Q, Q), MIXED), \
10586 X(3, (Q, Q, D), MIXED), \
10587 X(3, (Q, D, S), MIXED), \
10588 X(3, (D, Q, S), MIXED), \
10589 X(4, (D, D, D, I), DOUBLE), \
10590 X(4, (Q, Q, Q, I), QUAD), \
10591 X(2, (F, F), SINGLE), \
10592 X(3, (F, F, F), SINGLE), \
10593 X(2, (F, I), SINGLE), \
10594 X(2, (F, D), MIXED), \
10595 X(2, (D, F), MIXED), \
10596 X(3, (F, F, I), MIXED), \
10597 X(4, (R, R, F, F), SINGLE), \
10598 X(4, (F, F, R, R), SINGLE), \
10599 X(3, (D, R, R), DOUBLE), \
10600 X(3, (R, R, D), DOUBLE), \
10601 X(2, (S, R), SINGLE), \
10602 X(2, (R, S), SINGLE), \
10603 X(2, (F, R), SINGLE), \
10604 X(2, (R, F), SINGLE)
10605
10606#define S2(A,B) NS_##A##B
10607#define S3(A,B,C) NS_##A##B##C
10608#define S4(A,B,C,D) NS_##A##B##C##D
10609
10610#define X(N, L, C) S##N L
10611
5287ad62
JB
10612enum neon_shape
10613{
037e8744
JB
10614 NEON_SHAPE_DEF,
10615 NS_NULL
5287ad62 10616};
b99bd4ef 10617
037e8744
JB
10618#undef X
10619#undef S2
10620#undef S3
10621#undef S4
10622
10623enum neon_shape_class
10624{
10625 SC_SINGLE,
10626 SC_DOUBLE,
10627 SC_QUAD,
10628 SC_MIXED
10629};
10630
10631#define X(N, L, C) SC_##C
10632
10633static enum neon_shape_class neon_shape_class[] =
10634{
10635 NEON_SHAPE_DEF
10636};
10637
10638#undef X
10639
10640enum neon_shape_el
10641{
10642 SE_F,
10643 SE_D,
10644 SE_Q,
10645 SE_I,
10646 SE_S,
10647 SE_R,
10648 SE_L
10649};
10650
10651/* Register widths of above. */
10652static unsigned neon_shape_el_size[] =
10653{
10654 32,
10655 64,
10656 128,
10657 0,
10658 32,
10659 32,
10660 0
10661};
10662
10663struct neon_shape_info
10664{
10665 unsigned els;
10666 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
10667};
10668
10669#define S2(A,B) { SE_##A, SE_##B }
10670#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10671#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10672
10673#define X(N, L, C) { N, S##N L }
10674
10675static struct neon_shape_info neon_shape_tab[] =
10676{
10677 NEON_SHAPE_DEF
10678};
10679
10680#undef X
10681#undef S2
10682#undef S3
10683#undef S4
10684
5287ad62
JB
10685/* Bit masks used in type checking given instructions.
10686 'N_EQK' means the type must be the same as (or based on in some way) the key
10687 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10688 set, various other bits can be set as well in order to modify the meaning of
10689 the type constraint. */
10690
10691enum neon_type_mask
10692{
8e79c3df
CM
10693 N_S8 = 0x0000001,
10694 N_S16 = 0x0000002,
10695 N_S32 = 0x0000004,
10696 N_S64 = 0x0000008,
10697 N_U8 = 0x0000010,
10698 N_U16 = 0x0000020,
10699 N_U32 = 0x0000040,
10700 N_U64 = 0x0000080,
10701 N_I8 = 0x0000100,
10702 N_I16 = 0x0000200,
10703 N_I32 = 0x0000400,
10704 N_I64 = 0x0000800,
10705 N_8 = 0x0001000,
10706 N_16 = 0x0002000,
10707 N_32 = 0x0004000,
10708 N_64 = 0x0008000,
10709 N_P8 = 0x0010000,
10710 N_P16 = 0x0020000,
10711 N_F16 = 0x0040000,
10712 N_F32 = 0x0080000,
10713 N_F64 = 0x0100000,
10714 N_KEY = 0x1000000, /* key element (main type specifier). */
10715 N_EQK = 0x2000000, /* given operand has the same type & size as the key. */
10716 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
10717 N_DBL = 0x0000001, /* if N_EQK, this operand is twice the size. */
10718 N_HLF = 0x0000002, /* if N_EQK, this operand is half the size. */
10719 N_SGN = 0x0000004, /* if N_EQK, this operand is forced to be signed. */
10720 N_UNS = 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
10721 N_INT = 0x0000010, /* if N_EQK, this operand is forced to be integer. */
10722 N_FLT = 0x0000020, /* if N_EQK, this operand is forced to be float. */
10723 N_SIZ = 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
5287ad62 10724 N_UTYP = 0,
037e8744 10725 N_MAX_NONSPECIAL = N_F64
5287ad62
JB
10726};
10727
dcbf9037
JB
10728#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10729
5287ad62
JB
10730#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10731#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10732#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10733#define N_SUF_32 (N_SU_32 | N_F32)
10734#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10735#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10736
10737/* Pass this as the first type argument to neon_check_type to ignore types
10738 altogether. */
10739#define N_IGNORE_TYPE (N_KEY | N_EQK)
10740
037e8744
JB
10741/* Select a "shape" for the current instruction (describing register types or
10742 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10743 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10744 function of operand parsing, so this function doesn't need to be called.
10745 Shapes should be listed in order of decreasing length. */
5287ad62
JB
10746
10747static enum neon_shape
037e8744 10748neon_select_shape (enum neon_shape shape, ...)
5287ad62 10749{
037e8744
JB
10750 va_list ap;
10751 enum neon_shape first_shape = shape;
5287ad62
JB
10752
10753 /* Fix missing optional operands. FIXME: we don't know at this point how
10754 many arguments we should have, so this makes the assumption that we have
10755 > 1. This is true of all current Neon opcodes, I think, but may not be
10756 true in the future. */
10757 if (!inst.operands[1].present)
10758 inst.operands[1] = inst.operands[0];
10759
037e8744 10760 va_start (ap, shape);
5f4273c7 10761
037e8744
JB
10762 for (; shape != NS_NULL; shape = va_arg (ap, int))
10763 {
10764 unsigned j;
10765 int matches = 1;
10766
10767 for (j = 0; j < neon_shape_tab[shape].els; j++)
10768 {
10769 if (!inst.operands[j].present)
10770 {
10771 matches = 0;
10772 break;
10773 }
10774
10775 switch (neon_shape_tab[shape].el[j])
10776 {
10777 case SE_F:
10778 if (!(inst.operands[j].isreg
10779 && inst.operands[j].isvec
10780 && inst.operands[j].issingle
10781 && !inst.operands[j].isquad))
10782 matches = 0;
10783 break;
10784
10785 case SE_D:
10786 if (!(inst.operands[j].isreg
10787 && inst.operands[j].isvec
10788 && !inst.operands[j].isquad
10789 && !inst.operands[j].issingle))
10790 matches = 0;
10791 break;
10792
10793 case SE_R:
10794 if (!(inst.operands[j].isreg
10795 && !inst.operands[j].isvec))
10796 matches = 0;
10797 break;
10798
10799 case SE_Q:
10800 if (!(inst.operands[j].isreg
10801 && inst.operands[j].isvec
10802 && inst.operands[j].isquad
10803 && !inst.operands[j].issingle))
10804 matches = 0;
10805 break;
10806
10807 case SE_I:
10808 if (!(!inst.operands[j].isreg
10809 && !inst.operands[j].isscalar))
10810 matches = 0;
10811 break;
10812
10813 case SE_S:
10814 if (!(!inst.operands[j].isreg
10815 && inst.operands[j].isscalar))
10816 matches = 0;
10817 break;
10818
10819 case SE_L:
10820 break;
10821 }
10822 }
10823 if (matches)
5287ad62 10824 break;
037e8744 10825 }
5f4273c7 10826
037e8744 10827 va_end (ap);
5287ad62 10828
037e8744
JB
10829 if (shape == NS_NULL && first_shape != NS_NULL)
10830 first_error (_("invalid instruction shape"));
5287ad62 10831
037e8744
JB
10832 return shape;
10833}
5287ad62 10834
037e8744
JB
10835/* True if SHAPE is predominantly a quadword operation (most of the time, this
10836 means the Q bit should be set). */
10837
10838static int
10839neon_quad (enum neon_shape shape)
10840{
10841 return neon_shape_class[shape] == SC_QUAD;
5287ad62 10842}
037e8744 10843
5287ad62
JB
10844static void
10845neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
10846 unsigned *g_size)
10847{
10848 /* Allow modification to be made to types which are constrained to be
10849 based on the key element, based on bits set alongside N_EQK. */
10850 if ((typebits & N_EQK) != 0)
10851 {
10852 if ((typebits & N_HLF) != 0)
10853 *g_size /= 2;
10854 else if ((typebits & N_DBL) != 0)
10855 *g_size *= 2;
10856 if ((typebits & N_SGN) != 0)
10857 *g_type = NT_signed;
10858 else if ((typebits & N_UNS) != 0)
10859 *g_type = NT_unsigned;
10860 else if ((typebits & N_INT) != 0)
10861 *g_type = NT_integer;
10862 else if ((typebits & N_FLT) != 0)
10863 *g_type = NT_float;
dcbf9037
JB
10864 else if ((typebits & N_SIZ) != 0)
10865 *g_type = NT_untyped;
5287ad62
JB
10866 }
10867}
5f4273c7 10868
5287ad62
JB
10869/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10870 operand type, i.e. the single type specified in a Neon instruction when it
10871 is the only one given. */
10872
10873static struct neon_type_el
10874neon_type_promote (struct neon_type_el *key, unsigned thisarg)
10875{
10876 struct neon_type_el dest = *key;
5f4273c7 10877
5287ad62 10878 assert ((thisarg & N_EQK) != 0);
5f4273c7 10879
5287ad62
JB
10880 neon_modify_type_size (thisarg, &dest.type, &dest.size);
10881
10882 return dest;
10883}
10884
10885/* Convert Neon type and size into compact bitmask representation. */
10886
10887static enum neon_type_mask
10888type_chk_of_el_type (enum neon_el_type type, unsigned size)
10889{
10890 switch (type)
10891 {
10892 case NT_untyped:
10893 switch (size)
10894 {
10895 case 8: return N_8;
10896 case 16: return N_16;
10897 case 32: return N_32;
10898 case 64: return N_64;
10899 default: ;
10900 }
10901 break;
10902
10903 case NT_integer:
10904 switch (size)
10905 {
10906 case 8: return N_I8;
10907 case 16: return N_I16;
10908 case 32: return N_I32;
10909 case 64: return N_I64;
10910 default: ;
10911 }
10912 break;
10913
10914 case NT_float:
037e8744
JB
10915 switch (size)
10916 {
8e79c3df 10917 case 16: return N_F16;
037e8744
JB
10918 case 32: return N_F32;
10919 case 64: return N_F64;
10920 default: ;
10921 }
5287ad62
JB
10922 break;
10923
10924 case NT_poly:
10925 switch (size)
10926 {
10927 case 8: return N_P8;
10928 case 16: return N_P16;
10929 default: ;
10930 }
10931 break;
10932
10933 case NT_signed:
10934 switch (size)
10935 {
10936 case 8: return N_S8;
10937 case 16: return N_S16;
10938 case 32: return N_S32;
10939 case 64: return N_S64;
10940 default: ;
10941 }
10942 break;
10943
10944 case NT_unsigned:
10945 switch (size)
10946 {
10947 case 8: return N_U8;
10948 case 16: return N_U16;
10949 case 32: return N_U32;
10950 case 64: return N_U64;
10951 default: ;
10952 }
10953 break;
10954
10955 default: ;
10956 }
5f4273c7 10957
5287ad62
JB
10958 return N_UTYP;
10959}
10960
10961/* Convert compact Neon bitmask type representation to a type and size. Only
10962 handles the case where a single bit is set in the mask. */
10963
dcbf9037 10964static int
5287ad62
JB
10965el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
10966 enum neon_type_mask mask)
10967{
dcbf9037
JB
10968 if ((mask & N_EQK) != 0)
10969 return FAIL;
10970
5287ad62
JB
10971 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
10972 *size = 8;
dcbf9037 10973 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
5287ad62 10974 *size = 16;
dcbf9037 10975 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 10976 *size = 32;
037e8744 10977 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
5287ad62 10978 *size = 64;
dcbf9037
JB
10979 else
10980 return FAIL;
10981
5287ad62
JB
10982 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
10983 *type = NT_signed;
dcbf9037 10984 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 10985 *type = NT_unsigned;
dcbf9037 10986 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 10987 *type = NT_integer;
dcbf9037 10988 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 10989 *type = NT_untyped;
dcbf9037 10990 else if ((mask & (N_P8 | N_P16)) != 0)
5287ad62 10991 *type = NT_poly;
037e8744 10992 else if ((mask & (N_F32 | N_F64)) != 0)
5287ad62 10993 *type = NT_float;
dcbf9037
JB
10994 else
10995 return FAIL;
5f4273c7 10996
dcbf9037 10997 return SUCCESS;
5287ad62
JB
10998}
10999
11000/* Modify a bitmask of allowed types. This is only needed for type
11001 relaxation. */
11002
11003static unsigned
11004modify_types_allowed (unsigned allowed, unsigned mods)
11005{
11006 unsigned size;
11007 enum neon_el_type type;
11008 unsigned destmask;
11009 int i;
5f4273c7 11010
5287ad62 11011 destmask = 0;
5f4273c7 11012
5287ad62
JB
11013 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
11014 {
dcbf9037
JB
11015 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
11016 {
11017 neon_modify_type_size (mods, &type, &size);
11018 destmask |= type_chk_of_el_type (type, size);
11019 }
5287ad62 11020 }
5f4273c7 11021
5287ad62
JB
11022 return destmask;
11023}
11024
11025/* Check type and return type classification.
11026 The manual states (paraphrase): If one datatype is given, it indicates the
11027 type given in:
11028 - the second operand, if there is one
11029 - the operand, if there is no second operand
11030 - the result, if there are no operands.
11031 This isn't quite good enough though, so we use a concept of a "key" datatype
11032 which is set on a per-instruction basis, which is the one which matters when
11033 only one data type is written.
11034 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 11035 Neon instructions should call it before performing bit encoding. */
5287ad62
JB
11036
11037static struct neon_type_el
11038neon_check_type (unsigned els, enum neon_shape ns, ...)
11039{
11040 va_list ap;
11041 unsigned i, pass, key_el = 0;
11042 unsigned types[NEON_MAX_TYPE_ELS];
11043 enum neon_el_type k_type = NT_invtype;
11044 unsigned k_size = -1u;
11045 struct neon_type_el badtype = {NT_invtype, -1};
11046 unsigned key_allowed = 0;
11047
11048 /* Optional registers in Neon instructions are always (not) in operand 1.
11049 Fill in the missing operand here, if it was omitted. */
11050 if (els > 1 && !inst.operands[1].present)
11051 inst.operands[1] = inst.operands[0];
11052
11053 /* Suck up all the varargs. */
11054 va_start (ap, ns);
11055 for (i = 0; i < els; i++)
11056 {
11057 unsigned thisarg = va_arg (ap, unsigned);
11058 if (thisarg == N_IGNORE_TYPE)
11059 {
11060 va_end (ap);
11061 return badtype;
11062 }
11063 types[i] = thisarg;
11064 if ((thisarg & N_KEY) != 0)
11065 key_el = i;
11066 }
11067 va_end (ap);
11068
dcbf9037
JB
11069 if (inst.vectype.elems > 0)
11070 for (i = 0; i < els; i++)
11071 if (inst.operands[i].vectype.type != NT_invtype)
11072 {
11073 first_error (_("types specified in both the mnemonic and operands"));
11074 return badtype;
11075 }
11076
5287ad62
JB
11077 /* Duplicate inst.vectype elements here as necessary.
11078 FIXME: No idea if this is exactly the same as the ARM assembler,
11079 particularly when an insn takes one register and one non-register
11080 operand. */
11081 if (inst.vectype.elems == 1 && els > 1)
11082 {
11083 unsigned j;
11084 inst.vectype.elems = els;
11085 inst.vectype.el[key_el] = inst.vectype.el[0];
11086 for (j = 0; j < els; j++)
dcbf9037
JB
11087 if (j != key_el)
11088 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11089 types[j]);
11090 }
11091 else if (inst.vectype.elems == 0 && els > 0)
11092 {
11093 unsigned j;
11094 /* No types were given after the mnemonic, so look for types specified
11095 after each operand. We allow some flexibility here; as long as the
11096 "key" operand has a type, we can infer the others. */
11097 for (j = 0; j < els; j++)
11098 if (inst.operands[j].vectype.type != NT_invtype)
11099 inst.vectype.el[j] = inst.operands[j].vectype;
11100
11101 if (inst.operands[key_el].vectype.type != NT_invtype)
5287ad62 11102 {
dcbf9037
JB
11103 for (j = 0; j < els; j++)
11104 if (inst.operands[j].vectype.type == NT_invtype)
11105 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11106 types[j]);
11107 }
11108 else
11109 {
11110 first_error (_("operand types can't be inferred"));
11111 return badtype;
5287ad62
JB
11112 }
11113 }
11114 else if (inst.vectype.elems != els)
11115 {
dcbf9037 11116 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB
11117 return badtype;
11118 }
11119
11120 for (pass = 0; pass < 2; pass++)
11121 {
11122 for (i = 0; i < els; i++)
11123 {
11124 unsigned thisarg = types[i];
11125 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
11126 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
11127 enum neon_el_type g_type = inst.vectype.el[i].type;
11128 unsigned g_size = inst.vectype.el[i].size;
11129
11130 /* Decay more-specific signed & unsigned types to sign-insensitive
11131 integer types if sign-specific variants are unavailable. */
11132 if ((g_type == NT_signed || g_type == NT_unsigned)
11133 && (types_allowed & N_SU_ALL) == 0)
11134 g_type = NT_integer;
11135
11136 /* If only untyped args are allowed, decay any more specific types to
11137 them. Some instructions only care about signs for some element
11138 sizes, so handle that properly. */
11139 if ((g_size == 8 && (types_allowed & N_8) != 0)
11140 || (g_size == 16 && (types_allowed & N_16) != 0)
11141 || (g_size == 32 && (types_allowed & N_32) != 0)
11142 || (g_size == 64 && (types_allowed & N_64) != 0))
11143 g_type = NT_untyped;
11144
11145 if (pass == 0)
11146 {
11147 if ((thisarg & N_KEY) != 0)
11148 {
11149 k_type = g_type;
11150 k_size = g_size;
11151 key_allowed = thisarg & ~N_KEY;
11152 }
11153 }
11154 else
11155 {
037e8744
JB
11156 if ((thisarg & N_VFP) != 0)
11157 {
11158 enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
11159 unsigned regwidth = neon_shape_el_size[regshape], match;
11160
11161 /* In VFP mode, operands must match register widths. If we
11162 have a key operand, use its width, else use the width of
11163 the current operand. */
11164 if (k_size != -1u)
11165 match = k_size;
11166 else
11167 match = g_size;
11168
11169 if (regwidth != match)
11170 {
11171 first_error (_("operand size must match register width"));
11172 return badtype;
11173 }
11174 }
5f4273c7 11175
5287ad62
JB
11176 if ((thisarg & N_EQK) == 0)
11177 {
11178 unsigned given_type = type_chk_of_el_type (g_type, g_size);
11179
11180 if ((given_type & types_allowed) == 0)
11181 {
dcbf9037 11182 first_error (_("bad type in Neon instruction"));
5287ad62
JB
11183 return badtype;
11184 }
11185 }
11186 else
11187 {
11188 enum neon_el_type mod_k_type = k_type;
11189 unsigned mod_k_size = k_size;
11190 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
11191 if (g_type != mod_k_type || g_size != mod_k_size)
11192 {
dcbf9037 11193 first_error (_("inconsistent types in Neon instruction"));
5287ad62
JB
11194 return badtype;
11195 }
11196 }
11197 }
11198 }
11199 }
11200
11201 return inst.vectype.el[key_el];
11202}
11203
037e8744 11204/* Neon-style VFP instruction forwarding. */
5287ad62 11205
037e8744
JB
11206/* Thumb VFP instructions have 0xE in the condition field. */
11207
11208static void
11209do_vfp_cond_or_thumb (void)
5287ad62
JB
11210{
11211 if (thumb_mode)
037e8744 11212 inst.instruction |= 0xe0000000;
5287ad62 11213 else
037e8744 11214 inst.instruction |= inst.cond << 28;
5287ad62
JB
11215}
11216
037e8744
JB
11217/* Look up and encode a simple mnemonic, for use as a helper function for the
11218 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11219 etc. It is assumed that operand parsing has already been done, and that the
11220 operands are in the form expected by the given opcode (this isn't necessarily
11221 the same as the form in which they were parsed, hence some massaging must
11222 take place before this function is called).
11223 Checks current arch version against that in the looked-up opcode. */
5287ad62 11224
037e8744
JB
11225static void
11226do_vfp_nsyn_opcode (const char *opname)
5287ad62 11227{
037e8744 11228 const struct asm_opcode *opcode;
5f4273c7 11229
037e8744 11230 opcode = hash_find (arm_ops_hsh, opname);
5287ad62 11231
037e8744
JB
11232 if (!opcode)
11233 abort ();
5287ad62 11234
037e8744
JB
11235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
11236 thumb_mode ? *opcode->tvariant : *opcode->avariant),
11237 _(BAD_FPU));
5287ad62 11238
037e8744
JB
11239 if (thumb_mode)
11240 {
11241 inst.instruction = opcode->tvalue;
11242 opcode->tencode ();
11243 }
11244 else
11245 {
11246 inst.instruction = (inst.cond << 28) | opcode->avalue;
11247 opcode->aencode ();
11248 }
11249}
5287ad62
JB
11250
11251static void
037e8744 11252do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 11253{
037e8744
JB
11254 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
11255
11256 if (rs == NS_FFF)
11257 {
11258 if (is_add)
11259 do_vfp_nsyn_opcode ("fadds");
11260 else
11261 do_vfp_nsyn_opcode ("fsubs");
11262 }
11263 else
11264 {
11265 if (is_add)
11266 do_vfp_nsyn_opcode ("faddd");
11267 else
11268 do_vfp_nsyn_opcode ("fsubd");
11269 }
11270}
11271
11272/* Check operand types to see if this is a VFP instruction, and if so call
11273 PFN (). */
11274
11275static int
11276try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
11277{
11278 enum neon_shape rs;
11279 struct neon_type_el et;
11280
11281 switch (args)
11282 {
11283 case 2:
11284 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11285 et = neon_check_type (2, rs,
11286 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11287 break;
5f4273c7 11288
037e8744
JB
11289 case 3:
11290 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11291 et = neon_check_type (3, rs,
11292 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11293 break;
11294
11295 default:
11296 abort ();
11297 }
11298
11299 if (et.type != NT_invtype)
11300 {
11301 pfn (rs);
11302 return SUCCESS;
11303 }
11304 else
11305 inst.error = NULL;
11306
11307 return FAIL;
11308}
11309
11310static void
11311do_vfp_nsyn_mla_mls (enum neon_shape rs)
11312{
11313 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 11314
037e8744
JB
11315 if (rs == NS_FFF)
11316 {
11317 if (is_mla)
11318 do_vfp_nsyn_opcode ("fmacs");
11319 else
11320 do_vfp_nsyn_opcode ("fmscs");
11321 }
11322 else
11323 {
11324 if (is_mla)
11325 do_vfp_nsyn_opcode ("fmacd");
11326 else
11327 do_vfp_nsyn_opcode ("fmscd");
11328 }
11329}
11330
11331static void
11332do_vfp_nsyn_mul (enum neon_shape rs)
11333{
11334 if (rs == NS_FFF)
11335 do_vfp_nsyn_opcode ("fmuls");
11336 else
11337 do_vfp_nsyn_opcode ("fmuld");
11338}
11339
11340static void
11341do_vfp_nsyn_abs_neg (enum neon_shape rs)
11342{
11343 int is_neg = (inst.instruction & 0x80) != 0;
11344 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
11345
11346 if (rs == NS_FF)
11347 {
11348 if (is_neg)
11349 do_vfp_nsyn_opcode ("fnegs");
11350 else
11351 do_vfp_nsyn_opcode ("fabss");
11352 }
11353 else
11354 {
11355 if (is_neg)
11356 do_vfp_nsyn_opcode ("fnegd");
11357 else
11358 do_vfp_nsyn_opcode ("fabsd");
11359 }
11360}
11361
11362/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11363 insns belong to Neon, and are handled elsewhere. */
11364
11365static void
11366do_vfp_nsyn_ldm_stm (int is_dbmode)
11367{
11368 int is_ldm = (inst.instruction & (1 << 20)) != 0;
11369 if (is_ldm)
11370 {
11371 if (is_dbmode)
11372 do_vfp_nsyn_opcode ("fldmdbs");
11373 else
11374 do_vfp_nsyn_opcode ("fldmias");
11375 }
11376 else
11377 {
11378 if (is_dbmode)
11379 do_vfp_nsyn_opcode ("fstmdbs");
11380 else
11381 do_vfp_nsyn_opcode ("fstmias");
11382 }
11383}
11384
037e8744
JB
11385static void
11386do_vfp_nsyn_sqrt (void)
11387{
11388 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11389 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 11390
037e8744
JB
11391 if (rs == NS_FF)
11392 do_vfp_nsyn_opcode ("fsqrts");
11393 else
11394 do_vfp_nsyn_opcode ("fsqrtd");
11395}
11396
11397static void
11398do_vfp_nsyn_div (void)
11399{
11400 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11401 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11402 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 11403
037e8744
JB
11404 if (rs == NS_FFF)
11405 do_vfp_nsyn_opcode ("fdivs");
11406 else
11407 do_vfp_nsyn_opcode ("fdivd");
11408}
11409
11410static void
11411do_vfp_nsyn_nmul (void)
11412{
11413 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11414 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11415 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 11416
037e8744
JB
11417 if (rs == NS_FFF)
11418 {
11419 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11420 do_vfp_sp_dyadic ();
11421 }
11422 else
11423 {
11424 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11425 do_vfp_dp_rd_rn_rm ();
11426 }
11427 do_vfp_cond_or_thumb ();
11428}
11429
11430static void
11431do_vfp_nsyn_cmp (void)
11432{
11433 if (inst.operands[1].isreg)
11434 {
11435 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11436 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 11437
037e8744
JB
11438 if (rs == NS_FF)
11439 {
11440 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11441 do_vfp_sp_monadic ();
11442 }
11443 else
11444 {
11445 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11446 do_vfp_dp_rd_rm ();
11447 }
11448 }
11449 else
11450 {
11451 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
11452 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
11453
11454 switch (inst.instruction & 0x0fffffff)
11455 {
11456 case N_MNEM_vcmp:
11457 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
11458 break;
11459 case N_MNEM_vcmpe:
11460 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
11461 break;
11462 default:
11463 abort ();
11464 }
5f4273c7 11465
037e8744
JB
11466 if (rs == NS_FI)
11467 {
11468 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11469 do_vfp_sp_compare_z ();
11470 }
11471 else
11472 {
11473 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11474 do_vfp_dp_rd ();
11475 }
11476 }
11477 do_vfp_cond_or_thumb ();
11478}
11479
11480static void
11481nsyn_insert_sp (void)
11482{
11483 inst.operands[1] = inst.operands[0];
11484 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
11485 inst.operands[0].reg = 13;
11486 inst.operands[0].isreg = 1;
11487 inst.operands[0].writeback = 1;
11488 inst.operands[0].present = 1;
11489}
11490
11491static void
11492do_vfp_nsyn_push (void)
11493{
11494 nsyn_insert_sp ();
11495 if (inst.operands[1].issingle)
11496 do_vfp_nsyn_opcode ("fstmdbs");
11497 else
11498 do_vfp_nsyn_opcode ("fstmdbd");
11499}
11500
11501static void
11502do_vfp_nsyn_pop (void)
11503{
11504 nsyn_insert_sp ();
11505 if (inst.operands[1].issingle)
22b5b651 11506 do_vfp_nsyn_opcode ("fldmias");
037e8744 11507 else
22b5b651 11508 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB
11509}
11510
11511/* Fix up Neon data-processing instructions, ORing in the correct bits for
11512 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11513
11514static unsigned
11515neon_dp_fixup (unsigned i)
11516{
11517 if (thumb_mode)
11518 {
11519 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11520 if (i & (1 << 24))
11521 i |= 1 << 28;
5f4273c7 11522
037e8744 11523 i &= ~(1 << 24);
5f4273c7 11524
037e8744
JB
11525 i |= 0xef000000;
11526 }
11527 else
11528 i |= 0xf2000000;
5f4273c7 11529
037e8744
JB
11530 return i;
11531}
11532
11533/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11534 (0, 1, 2, 3). */
11535
11536static unsigned
11537neon_logbits (unsigned x)
11538{
11539 return ffs (x) - 4;
11540}
11541
11542#define LOW4(R) ((R) & 0xf)
11543#define HI1(R) (((R) >> 4) & 1)
11544
11545/* Encode insns with bit pattern:
11546
11547 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11548 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 11549
037e8744
JB
11550 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11551 different meaning for some instruction. */
11552
11553static void
11554neon_three_same (int isquad, int ubit, int size)
11555{
11556 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11557 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11558 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11559 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11560 inst.instruction |= LOW4 (inst.operands[2].reg);
11561 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11562 inst.instruction |= (isquad != 0) << 6;
11563 inst.instruction |= (ubit != 0) << 24;
11564 if (size != -1)
11565 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 11566
037e8744
JB
11567 inst.instruction = neon_dp_fixup (inst.instruction);
11568}
11569
11570/* Encode instructions of the form:
11571
11572 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11573 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB
11574
11575 Don't write size if SIZE == -1. */
11576
11577static void
11578neon_two_same (int qbit, int ubit, int size)
11579{
11580 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11581 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11582 inst.instruction |= LOW4 (inst.operands[1].reg);
11583 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11584 inst.instruction |= (qbit != 0) << 6;
11585 inst.instruction |= (ubit != 0) << 24;
11586
11587 if (size != -1)
11588 inst.instruction |= neon_logbits (size) << 18;
11589
11590 inst.instruction = neon_dp_fixup (inst.instruction);
11591}
11592
11593/* Neon instruction encoders, in approximate order of appearance. */
11594
11595static void
11596do_neon_dyadic_i_su (void)
11597{
037e8744 11598 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
11599 struct neon_type_el et = neon_check_type (3, rs,
11600 N_EQK, N_EQK, N_SU_32 | N_KEY);
037e8744 11601 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
11602}
11603
11604static void
11605do_neon_dyadic_i64_su (void)
11606{
037e8744 11607 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
11608 struct neon_type_el et = neon_check_type (3, rs,
11609 N_EQK, N_EQK, N_SU_ALL | N_KEY);
037e8744 11610 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
11611}
11612
11613static void
11614neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
11615 unsigned immbits)
11616{
11617 unsigned size = et.size >> 3;
11618 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11619 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11620 inst.instruction |= LOW4 (inst.operands[1].reg);
11621 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11622 inst.instruction |= (isquad != 0) << 6;
11623 inst.instruction |= immbits << 16;
11624 inst.instruction |= (size >> 3) << 7;
11625 inst.instruction |= (size & 0x7) << 19;
11626 if (write_ubit)
11627 inst.instruction |= (uval != 0) << 24;
11628
11629 inst.instruction = neon_dp_fixup (inst.instruction);
11630}
11631
11632static void
11633do_neon_shl_imm (void)
11634{
11635 if (!inst.operands[2].isreg)
11636 {
037e8744 11637 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
11638 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
11639 inst.instruction = NEON_ENC_IMMED (inst.instruction);
037e8744 11640 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
5287ad62
JB
11641 }
11642 else
11643 {
037e8744 11644 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
11645 struct neon_type_el et = neon_check_type (3, rs,
11646 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB
11647 unsigned int tmp;
11648
11649 /* VSHL/VQSHL 3-register variants have syntax such as:
11650 vshl.xx Dd, Dm, Dn
11651 whereas other 3-register operations encoded by neon_three_same have
11652 syntax like:
11653 vadd.xx Dd, Dn, Dm
11654 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11655 here. */
11656 tmp = inst.operands[2].reg;
11657 inst.operands[2].reg = inst.operands[1].reg;
11658 inst.operands[1].reg = tmp;
5287ad62 11659 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
037e8744 11660 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
11661 }
11662}
11663
11664static void
11665do_neon_qshl_imm (void)
11666{
11667 if (!inst.operands[2].isreg)
11668 {
037e8744 11669 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 11670 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
627907b7 11671
5287ad62 11672 inst.instruction = NEON_ENC_IMMED (inst.instruction);
037e8744 11673 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
5287ad62
JB
11674 inst.operands[2].imm);
11675 }
11676 else
11677 {
037e8744 11678 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
11679 struct neon_type_el et = neon_check_type (3, rs,
11680 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB
11681 unsigned int tmp;
11682
11683 /* See note in do_neon_shl_imm. */
11684 tmp = inst.operands[2].reg;
11685 inst.operands[2].reg = inst.operands[1].reg;
11686 inst.operands[1].reg = tmp;
5287ad62 11687 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
037e8744 11688 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB
11689 }
11690}
11691
627907b7
JB
11692static void
11693do_neon_rshl (void)
11694{
11695 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11696 struct neon_type_el et = neon_check_type (3, rs,
11697 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11698 unsigned int tmp;
11699
11700 tmp = inst.operands[2].reg;
11701 inst.operands[2].reg = inst.operands[1].reg;
11702 inst.operands[1].reg = tmp;
11703 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11704}
11705
5287ad62
JB
11706static int
11707neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11708{
036dc3f7
PB
11709 /* Handle .I8 pseudo-instructions. */
11710 if (size == 8)
5287ad62 11711 {
5287ad62
JB
11712 /* Unfortunately, this will make everything apart from zero out-of-range.
11713 FIXME is this the intended semantics? There doesn't seem much point in
11714 accepting .I8 if so. */
11715 immediate |= immediate << 8;
11716 size = 16;
036dc3f7
PB
11717 }
11718
11719 if (size >= 32)
11720 {
11721 if (immediate == (immediate & 0x000000ff))
11722 {
11723 *immbits = immediate;
11724 return 0x1;
11725 }
11726 else if (immediate == (immediate & 0x0000ff00))
11727 {
11728 *immbits = immediate >> 8;
11729 return 0x3;
11730 }
11731 else if (immediate == (immediate & 0x00ff0000))
11732 {
11733 *immbits = immediate >> 16;
11734 return 0x5;
11735 }
11736 else if (immediate == (immediate & 0xff000000))
11737 {
11738 *immbits = immediate >> 24;
11739 return 0x7;
11740 }
11741 if ((immediate & 0xffff) != (immediate >> 16))
11742 goto bad_immediate;
11743 immediate &= 0xffff;
5287ad62
JB
11744 }
11745
11746 if (immediate == (immediate & 0x000000ff))
11747 {
11748 *immbits = immediate;
036dc3f7 11749 return 0x9;
5287ad62
JB
11750 }
11751 else if (immediate == (immediate & 0x0000ff00))
11752 {
11753 *immbits = immediate >> 8;
036dc3f7 11754 return 0xb;
5287ad62
JB
11755 }
11756
11757 bad_immediate:
dcbf9037 11758 first_error (_("immediate value out of range"));
5287ad62
JB
11759 return FAIL;
11760}
11761
11762/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11763 A, B, C, D. */
11764
11765static int
11766neon_bits_same_in_bytes (unsigned imm)
11767{
11768 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11769 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11770 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11771 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11772}
11773
11774/* For immediate of above form, return 0bABCD. */
11775
11776static unsigned
11777neon_squash_bits (unsigned imm)
11778{
11779 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11780 | ((imm & 0x01000000) >> 21);
11781}
11782
136da414 11783/* Compress quarter-float representation to 0b...000 abcdefgh. */
5287ad62
JB
11784
11785static unsigned
11786neon_qfloat_bits (unsigned imm)
11787{
136da414 11788 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
5287ad62
JB
11789}
11790
11791/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11792 the instruction. *OP is passed as the initial value of the op field, and
11793 may be set to a different value depending on the constant (i.e.
11794 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
5f4273c7 11795 MVN). If the immediate looks like a repeated pattern then also
036dc3f7 11796 try smaller element sizes. */
5287ad62
JB
11797
11798static int
c96612cc
JB
11799neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
11800 unsigned *immbits, int *op, int size,
11801 enum neon_el_type type)
5287ad62 11802{
c96612cc
JB
11803 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11804 float. */
11805 if (type == NT_float && !float_p)
11806 return FAIL;
11807
136da414
JB
11808 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
11809 {
11810 if (size != 32 || *op == 1)
11811 return FAIL;
11812 *immbits = neon_qfloat_bits (immlo);
11813 return 0xf;
11814 }
036dc3f7
PB
11815
11816 if (size == 64)
5287ad62 11817 {
036dc3f7
PB
11818 if (neon_bits_same_in_bytes (immhi)
11819 && neon_bits_same_in_bytes (immlo))
11820 {
11821 if (*op == 1)
11822 return FAIL;
11823 *immbits = (neon_squash_bits (immhi) << 4)
11824 | neon_squash_bits (immlo);
11825 *op = 1;
11826 return 0xe;
11827 }
11828
11829 if (immhi != immlo)
11830 return FAIL;
5287ad62 11831 }
036dc3f7
PB
11832
11833 if (size >= 32)
5287ad62 11834 {
036dc3f7
PB
11835 if (immlo == (immlo & 0x000000ff))
11836 {
11837 *immbits = immlo;
11838 return 0x0;
11839 }
11840 else if (immlo == (immlo & 0x0000ff00))
11841 {
11842 *immbits = immlo >> 8;
11843 return 0x2;
11844 }
11845 else if (immlo == (immlo & 0x00ff0000))
11846 {
11847 *immbits = immlo >> 16;
11848 return 0x4;
11849 }
11850 else if (immlo == (immlo & 0xff000000))
11851 {
11852 *immbits = immlo >> 24;
11853 return 0x6;
11854 }
11855 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
11856 {
11857 *immbits = (immlo >> 8) & 0xff;
11858 return 0xc;
11859 }
11860 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
11861 {
11862 *immbits = (immlo >> 16) & 0xff;
11863 return 0xd;
11864 }
11865
11866 if ((immlo & 0xffff) != (immlo >> 16))
11867 return FAIL;
11868 immlo &= 0xffff;
5287ad62 11869 }
036dc3f7
PB
11870
11871 if (size >= 16)
5287ad62 11872 {
036dc3f7
PB
11873 if (immlo == (immlo & 0x000000ff))
11874 {
11875 *immbits = immlo;
11876 return 0x8;
11877 }
11878 else if (immlo == (immlo & 0x0000ff00))
11879 {
11880 *immbits = immlo >> 8;
11881 return 0xa;
11882 }
11883
11884 if ((immlo & 0xff) != (immlo >> 8))
11885 return FAIL;
11886 immlo &= 0xff;
5287ad62 11887 }
036dc3f7
PB
11888
11889 if (immlo == (immlo & 0x000000ff))
5287ad62 11890 {
036dc3f7
PB
11891 /* Don't allow MVN with 8-bit immediate. */
11892 if (*op == 1)
11893 return FAIL;
11894 *immbits = immlo;
11895 return 0xe;
5287ad62 11896 }
5287ad62
JB
11897
11898 return FAIL;
11899}
11900
11901/* Write immediate bits [7:0] to the following locations:
11902
11903 |28/24|23 19|18 16|15 4|3 0|
11904 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11905
11906 This function is used by VMOV/VMVN/VORR/VBIC. */
11907
11908static void
11909neon_write_immbits (unsigned immbits)
11910{
11911 inst.instruction |= immbits & 0xf;
11912 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
11913 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
11914}
11915
11916/* Invert low-order SIZE bits of XHI:XLO. */
11917
11918static void
11919neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
11920{
11921 unsigned immlo = xlo ? *xlo : 0;
11922 unsigned immhi = xhi ? *xhi : 0;
11923
11924 switch (size)
11925 {
11926 case 8:
11927 immlo = (~immlo) & 0xff;
11928 break;
11929
11930 case 16:
11931 immlo = (~immlo) & 0xffff;
11932 break;
11933
11934 case 64:
11935 immhi = (~immhi) & 0xffffffff;
11936 /* fall through. */
11937
11938 case 32:
11939 immlo = (~immlo) & 0xffffffff;
11940 break;
11941
11942 default:
11943 abort ();
11944 }
11945
11946 if (xlo)
11947 *xlo = immlo;
11948
11949 if (xhi)
11950 *xhi = immhi;
11951}
11952
11953static void
11954do_neon_logic (void)
11955{
11956 if (inst.operands[2].present && inst.operands[2].isreg)
11957 {
037e8744 11958 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
11959 neon_check_type (3, rs, N_IGNORE_TYPE);
11960 /* U bit and size field were set as part of the bitmask. */
11961 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
037e8744 11962 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
11963 }
11964 else
11965 {
037e8744
JB
11966 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
11967 struct neon_type_el et = neon_check_type (2, rs,
11968 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62
JB
11969 enum neon_opc opcode = inst.instruction & 0x0fffffff;
11970 unsigned immbits;
11971 int cmode;
5f4273c7 11972
5287ad62
JB
11973 if (et.type == NT_invtype)
11974 return;
5f4273c7 11975
5287ad62
JB
11976 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11977
036dc3f7
PB
11978 immbits = inst.operands[1].imm;
11979 if (et.size == 64)
11980 {
11981 /* .i64 is a pseudo-op, so the immediate must be a repeating
11982 pattern. */
11983 if (immbits != (inst.operands[1].regisimm ?
11984 inst.operands[1].reg : 0))
11985 {
11986 /* Set immbits to an invalid constant. */
11987 immbits = 0xdeadbeef;
11988 }
11989 }
11990
5287ad62
JB
11991 switch (opcode)
11992 {
11993 case N_MNEM_vbic:
036dc3f7 11994 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
5287ad62 11995 break;
5f4273c7 11996
5287ad62 11997 case N_MNEM_vorr:
036dc3f7 11998 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
5287ad62 11999 break;
5f4273c7 12000
5287ad62
JB
12001 case N_MNEM_vand:
12002 /* Pseudo-instruction for VBIC. */
5287ad62
JB
12003 neon_invert_size (&immbits, 0, et.size);
12004 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12005 break;
5f4273c7 12006
5287ad62
JB
12007 case N_MNEM_vorn:
12008 /* Pseudo-instruction for VORR. */
5287ad62
JB
12009 neon_invert_size (&immbits, 0, et.size);
12010 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12011 break;
5f4273c7 12012
5287ad62
JB
12013 default:
12014 abort ();
12015 }
12016
12017 if (cmode == FAIL)
12018 return;
12019
037e8744 12020 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
12021 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12022 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12023 inst.instruction |= cmode << 8;
12024 neon_write_immbits (immbits);
5f4273c7 12025
5287ad62
JB
12026 inst.instruction = neon_dp_fixup (inst.instruction);
12027 }
12028}
12029
12030static void
12031do_neon_bitfield (void)
12032{
037e8744 12033 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 12034 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 12035 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
12036}
12037
12038static void
dcbf9037
JB
12039neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
12040 unsigned destbits)
5287ad62 12041{
037e8744 12042 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037
JB
12043 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
12044 types | N_KEY);
5287ad62
JB
12045 if (et.type == NT_float)
12046 {
12047 inst.instruction = NEON_ENC_FLOAT (inst.instruction);
037e8744 12048 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
12049 }
12050 else
12051 {
12052 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
037e8744 12053 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB
12054 }
12055}
12056
12057static void
12058do_neon_dyadic_if_su (void)
12059{
dcbf9037 12060 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB
12061}
12062
12063static void
12064do_neon_dyadic_if_su_d (void)
12065{
12066 /* This version only allow D registers, but that constraint is enforced during
12067 operand parsing so we don't need to do anything extra here. */
dcbf9037 12068 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB
12069}
12070
5287ad62
JB
12071static void
12072do_neon_dyadic_if_i_d (void)
12073{
428e3f1f
PB
12074 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12075 affected if we specify unsigned args. */
12076 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB
12077}
12078
037e8744
JB
12079enum vfp_or_neon_is_neon_bits
12080{
12081 NEON_CHECK_CC = 1,
12082 NEON_CHECK_ARCH = 2
12083};
12084
12085/* Call this function if an instruction which may have belonged to the VFP or
12086 Neon instruction sets, but turned out to be a Neon instruction (due to the
12087 operand types involved, etc.). We have to check and/or fix-up a couple of
12088 things:
12089
12090 - Make sure the user hasn't attempted to make a Neon instruction
12091 conditional.
12092 - Alter the value in the condition code field if necessary.
12093 - Make sure that the arch supports Neon instructions.
12094
12095 Which of these operations take place depends on bits from enum
12096 vfp_or_neon_is_neon_bits.
12097
12098 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12099 current instruction's condition is COND_ALWAYS, the condition field is
12100 changed to inst.uncond_value. This is necessary because instructions shared
12101 between VFP and Neon may be conditional for the VFP variants only, and the
12102 unconditional Neon version must have, e.g., 0xF in the condition field. */
12103
12104static int
12105vfp_or_neon_is_neon (unsigned check)
12106{
12107 /* Conditions are always legal in Thumb mode (IT blocks). */
12108 if (!thumb_mode && (check & NEON_CHECK_CC))
12109 {
12110 if (inst.cond != COND_ALWAYS)
12111 {
12112 first_error (_(BAD_COND));
12113 return FAIL;
12114 }
12115 if (inst.uncond_value != -1)
12116 inst.instruction |= inst.uncond_value << 28;
12117 }
5f4273c7 12118
037e8744
JB
12119 if ((check & NEON_CHECK_ARCH)
12120 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
12121 {
12122 first_error (_(BAD_FPU));
12123 return FAIL;
12124 }
5f4273c7 12125
037e8744
JB
12126 return SUCCESS;
12127}
12128
5287ad62
JB
12129static void
12130do_neon_addsub_if_i (void)
12131{
037e8744
JB
12132 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
12133 return;
12134
12135 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12136 return;
12137
5287ad62
JB
12138 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12139 affected if we specify unsigned args. */
dcbf9037 12140 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB
12141}
12142
12143/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12144 result to be:
12145 V<op> A,B (A is operand 0, B is operand 2)
12146 to mean:
12147 V<op> A,B,A
12148 not:
12149 V<op> A,B,B
12150 so handle that case specially. */
12151
12152static void
12153neon_exchange_operands (void)
12154{
12155 void *scratch = alloca (sizeof (inst.operands[0]));
12156 if (inst.operands[1].present)
12157 {
12158 /* Swap operands[1] and operands[2]. */
12159 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
12160 inst.operands[1] = inst.operands[2];
12161 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
12162 }
12163 else
12164 {
12165 inst.operands[1] = inst.operands[2];
12166 inst.operands[2] = inst.operands[0];
12167 }
12168}
12169
12170static void
12171neon_compare (unsigned regtypes, unsigned immtypes, int invert)
12172{
12173 if (inst.operands[2].isreg)
12174 {
12175 if (invert)
12176 neon_exchange_operands ();
dcbf9037 12177 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB
12178 }
12179 else
12180 {
037e8744 12181 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037
JB
12182 struct neon_type_el et = neon_check_type (2, rs,
12183 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62
JB
12184
12185 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12186 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12187 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12188 inst.instruction |= LOW4 (inst.operands[1].reg);
12189 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 12190 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
12191 inst.instruction |= (et.type == NT_float) << 10;
12192 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 12193
5287ad62
JB
12194 inst.instruction = neon_dp_fixup (inst.instruction);
12195 }
12196}
12197
12198static void
12199do_neon_cmp (void)
12200{
12201 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
12202}
12203
12204static void
12205do_neon_cmp_inv (void)
12206{
12207 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
12208}
12209
12210static void
12211do_neon_ceq (void)
12212{
12213 neon_compare (N_IF_32, N_IF_32, FALSE);
12214}
12215
12216/* For multiply instructions, we have the possibility of 16-bit or 32-bit
12217 scalars, which are encoded in 5 bits, M : Rm.
12218 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12219 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12220 index in M. */
12221
12222static unsigned
12223neon_scalar_for_mul (unsigned scalar, unsigned elsize)
12224{
dcbf9037
JB
12225 unsigned regno = NEON_SCALAR_REG (scalar);
12226 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB
12227
12228 switch (elsize)
12229 {
12230 case 16:
12231 if (regno > 7 || elno > 3)
12232 goto bad_scalar;
12233 return regno | (elno << 3);
5f4273c7 12234
5287ad62
JB
12235 case 32:
12236 if (regno > 15 || elno > 1)
12237 goto bad_scalar;
12238 return regno | (elno << 4);
12239
12240 default:
12241 bad_scalar:
dcbf9037 12242 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB
12243 }
12244
12245 return 0;
12246}
12247
12248/* Encode multiply / multiply-accumulate scalar instructions. */
12249
12250static void
12251neon_mul_mac (struct neon_type_el et, int ubit)
12252{
dcbf9037
JB
12253 unsigned scalar;
12254
12255 /* Give a more helpful error message if we have an invalid type. */
12256 if (et.type == NT_invtype)
12257 return;
5f4273c7 12258
dcbf9037 12259 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB
12260 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12261 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12262 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12263 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12264 inst.instruction |= LOW4 (scalar);
12265 inst.instruction |= HI1 (scalar) << 5;
12266 inst.instruction |= (et.type == NT_float) << 8;
12267 inst.instruction |= neon_logbits (et.size) << 20;
12268 inst.instruction |= (ubit != 0) << 24;
12269
12270 inst.instruction = neon_dp_fixup (inst.instruction);
12271}
12272
12273static void
12274do_neon_mac_maybe_scalar (void)
12275{
037e8744
JB
12276 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
12277 return;
12278
12279 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12280 return;
12281
5287ad62
JB
12282 if (inst.operands[2].isscalar)
12283 {
037e8744 12284 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62
JB
12285 struct neon_type_el et = neon_check_type (3, rs,
12286 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
12287 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
037e8744 12288 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB
12289 }
12290 else
428e3f1f
PB
12291 {
12292 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12293 affected if we specify unsigned args. */
12294 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12295 }
5287ad62
JB
12296}
12297
12298static void
12299do_neon_tst (void)
12300{
037e8744 12301 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12302 struct neon_type_el et = neon_check_type (3, rs,
12303 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 12304 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB
12305}
12306
12307/* VMUL with 3 registers allows the P8 type. The scalar version supports the
12308 same types as the MAC equivalents. The polynomial type for this instruction
12309 is encoded the same as the integer type. */
12310
12311static void
12312do_neon_mul (void)
12313{
037e8744
JB
12314 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
12315 return;
12316
12317 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12318 return;
12319
5287ad62
JB
12320 if (inst.operands[2].isscalar)
12321 do_neon_mac_maybe_scalar ();
12322 else
dcbf9037 12323 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
5287ad62
JB
12324}
12325
12326static void
12327do_neon_qdmulh (void)
12328{
12329 if (inst.operands[2].isscalar)
12330 {
037e8744 12331 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62
JB
12332 struct neon_type_el et = neon_check_type (3, rs,
12333 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12334 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
037e8744 12335 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB
12336 }
12337 else
12338 {
037e8744 12339 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12340 struct neon_type_el et = neon_check_type (3, rs,
12341 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12342 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12343 /* The U bit (rounding) comes from bit mask. */
037e8744 12344 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB
12345 }
12346}
12347
12348static void
12349do_neon_fcmp_absolute (void)
12350{
037e8744 12351 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB
12352 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12353 /* Size field comes from bit mask. */
037e8744 12354 neon_three_same (neon_quad (rs), 1, -1);
5287ad62
JB
12355}
12356
12357static void
12358do_neon_fcmp_absolute_inv (void)
12359{
12360 neon_exchange_operands ();
12361 do_neon_fcmp_absolute ();
12362}
12363
12364static void
12365do_neon_step (void)
12366{
037e8744 12367 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 12368 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
037e8744 12369 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB
12370}
12371
12372static void
12373do_neon_abs_neg (void)
12374{
037e8744
JB
12375 enum neon_shape rs;
12376 struct neon_type_el et;
5f4273c7 12377
037e8744
JB
12378 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
12379 return;
12380
12381 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12382 return;
12383
12384 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12385 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
5f4273c7 12386
5287ad62
JB
12387 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12388 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12389 inst.instruction |= LOW4 (inst.operands[1].reg);
12390 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 12391 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
12392 inst.instruction |= (et.type == NT_float) << 10;
12393 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 12394
5287ad62
JB
12395 inst.instruction = neon_dp_fixup (inst.instruction);
12396}
12397
12398static void
12399do_neon_sli (void)
12400{
037e8744 12401 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
12402 struct neon_type_el et = neon_check_type (2, rs,
12403 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12404 int imm = inst.operands[2].imm;
12405 constraint (imm < 0 || (unsigned)imm >= et.size,
12406 _("immediate out of range for insert"));
037e8744 12407 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
12408}
12409
12410static void
12411do_neon_sri (void)
12412{
037e8744 12413 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
12414 struct neon_type_el et = neon_check_type (2, rs,
12415 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12416 int imm = inst.operands[2].imm;
12417 constraint (imm < 1 || (unsigned)imm > et.size,
12418 _("immediate out of range for insert"));
037e8744 12419 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB
12420}
12421
12422static void
12423do_neon_qshlu_imm (void)
12424{
037e8744 12425 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
12426 struct neon_type_el et = neon_check_type (2, rs,
12427 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
12428 int imm = inst.operands[2].imm;
12429 constraint (imm < 0 || (unsigned)imm >= et.size,
12430 _("immediate out of range for shift"));
12431 /* Only encodes the 'U present' variant of the instruction.
12432 In this case, signed types have OP (bit 8) set to 0.
12433 Unsigned types have OP set to 1. */
12434 inst.instruction |= (et.type == NT_unsigned) << 8;
12435 /* The rest of the bits are the same as other immediate shifts. */
037e8744 12436 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB
12437}
12438
12439static void
12440do_neon_qmovn (void)
12441{
12442 struct neon_type_el et = neon_check_type (2, NS_DQ,
12443 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12444 /* Saturating move where operands can be signed or unsigned, and the
12445 destination has the same signedness. */
12446 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12447 if (et.type == NT_unsigned)
12448 inst.instruction |= 0xc0;
12449 else
12450 inst.instruction |= 0x80;
12451 neon_two_same (0, 1, et.size / 2);
12452}
12453
12454static void
12455do_neon_qmovun (void)
12456{
12457 struct neon_type_el et = neon_check_type (2, NS_DQ,
12458 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12459 /* Saturating move with unsigned results. Operands must be signed. */
12460 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12461 neon_two_same (0, 1, et.size / 2);
12462}
12463
12464static void
12465do_neon_rshift_sat_narrow (void)
12466{
12467 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12468 or unsigned. If operands are unsigned, results must also be unsigned. */
12469 struct neon_type_el et = neon_check_type (2, NS_DQI,
12470 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12471 int imm = inst.operands[2].imm;
12472 /* This gets the bounds check, size encoding and immediate bits calculation
12473 right. */
12474 et.size /= 2;
5f4273c7 12475
5287ad62
JB
12476 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12477 VQMOVN.I<size> <Dd>, <Qm>. */
12478 if (imm == 0)
12479 {
12480 inst.operands[2].present = 0;
12481 inst.instruction = N_MNEM_vqmovn;
12482 do_neon_qmovn ();
12483 return;
12484 }
5f4273c7 12485
5287ad62
JB
12486 constraint (imm < 1 || (unsigned)imm > et.size,
12487 _("immediate out of range"));
12488 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12489}
12490
12491static void
12492do_neon_rshift_sat_narrow_u (void)
12493{
12494 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12495 or unsigned. If operands are unsigned, results must also be unsigned. */
12496 struct neon_type_el et = neon_check_type (2, NS_DQI,
12497 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12498 int imm = inst.operands[2].imm;
12499 /* This gets the bounds check, size encoding and immediate bits calculation
12500 right. */
12501 et.size /= 2;
12502
12503 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12504 VQMOVUN.I<size> <Dd>, <Qm>. */
12505 if (imm == 0)
12506 {
12507 inst.operands[2].present = 0;
12508 inst.instruction = N_MNEM_vqmovun;
12509 do_neon_qmovun ();
12510 return;
12511 }
12512
12513 constraint (imm < 1 || (unsigned)imm > et.size,
12514 _("immediate out of range"));
12515 /* FIXME: The manual is kind of unclear about what value U should have in
12516 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12517 must be 1. */
12518 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12519}
12520
12521static void
12522do_neon_movn (void)
12523{
12524 struct neon_type_el et = neon_check_type (2, NS_DQ,
12525 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12526 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12527 neon_two_same (0, 1, et.size / 2);
12528}
12529
12530static void
12531do_neon_rshift_narrow (void)
12532{
12533 struct neon_type_el et = neon_check_type (2, NS_DQI,
12534 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12535 int imm = inst.operands[2].imm;
12536 /* This gets the bounds check, size encoding and immediate bits calculation
12537 right. */
12538 et.size /= 2;
5f4273c7 12539
5287ad62
JB
12540 /* If immediate is zero then we are a pseudo-instruction for
12541 VMOVN.I<size> <Dd>, <Qm> */
12542 if (imm == 0)
12543 {
12544 inst.operands[2].present = 0;
12545 inst.instruction = N_MNEM_vmovn;
12546 do_neon_movn ();
12547 return;
12548 }
5f4273c7 12549
5287ad62
JB
12550 constraint (imm < 1 || (unsigned)imm > et.size,
12551 _("immediate out of range for narrowing operation"));
12552 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12553}
12554
12555static void
12556do_neon_shll (void)
12557{
12558 /* FIXME: Type checking when lengthening. */
12559 struct neon_type_el et = neon_check_type (2, NS_QDI,
12560 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
12561 unsigned imm = inst.operands[2].imm;
12562
12563 if (imm == et.size)
12564 {
12565 /* Maximum shift variant. */
12566 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12567 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12568 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12569 inst.instruction |= LOW4 (inst.operands[1].reg);
12570 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12571 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 12572
5287ad62
JB
12573 inst.instruction = neon_dp_fixup (inst.instruction);
12574 }
12575 else
12576 {
12577 /* A more-specific type check for non-max versions. */
12578 et = neon_check_type (2, NS_QDI,
12579 N_EQK | N_DBL, N_SU_32 | N_KEY);
12580 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12581 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12582 }
12583}
12584
037e8744 12585/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB
12586 the current instruction is. */
12587
12588static int
12589neon_cvt_flavour (enum neon_shape rs)
12590{
037e8744
JB
12591#define CVT_VAR(C,X,Y) \
12592 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12593 if (et.type != NT_invtype) \
12594 { \
12595 inst.error = NULL; \
12596 return (C); \
5287ad62
JB
12597 }
12598 struct neon_type_el et;
037e8744
JB
12599 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
12600 || rs == NS_FF) ? N_VFP : 0;
12601 /* The instruction versions which take an immediate take one register
12602 argument, which is extended to the width of the full register. Thus the
12603 "source" and "destination" registers must have the same width. Hack that
12604 here by making the size equal to the key (wider, in this case) operand. */
12605 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 12606
5287ad62
JB
12607 CVT_VAR (0, N_S32, N_F32);
12608 CVT_VAR (1, N_U32, N_F32);
12609 CVT_VAR (2, N_F32, N_S32);
12610 CVT_VAR (3, N_F32, N_U32);
8e79c3df
CM
12611 /* Half-precision conversions. */
12612 CVT_VAR (4, N_F32, N_F16);
12613 CVT_VAR (5, N_F16, N_F32);
5f4273c7 12614
037e8744 12615 whole_reg = N_VFP;
5f4273c7 12616
037e8744 12617 /* VFP instructions. */
8e79c3df
CM
12618 CVT_VAR (6, N_F32, N_F64);
12619 CVT_VAR (7, N_F64, N_F32);
12620 CVT_VAR (8, N_S32, N_F64 | key);
12621 CVT_VAR (9, N_U32, N_F64 | key);
12622 CVT_VAR (10, N_F64 | key, N_S32);
12623 CVT_VAR (11, N_F64 | key, N_U32);
037e8744 12624 /* VFP instructions with bitshift. */
8e79c3df
CM
12625 CVT_VAR (12, N_F32 | key, N_S16);
12626 CVT_VAR (13, N_F32 | key, N_U16);
12627 CVT_VAR (14, N_F64 | key, N_S16);
12628 CVT_VAR (15, N_F64 | key, N_U16);
12629 CVT_VAR (16, N_S16, N_F32 | key);
12630 CVT_VAR (17, N_U16, N_F32 | key);
12631 CVT_VAR (18, N_S16, N_F64 | key);
12632 CVT_VAR (19, N_U16, N_F64 | key);
5f4273c7 12633
5287ad62
JB
12634 return -1;
12635#undef CVT_VAR
12636}
12637
037e8744
JB
12638/* Neon-syntax VFP conversions. */
12639
5287ad62 12640static void
037e8744 12641do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
5287ad62 12642{
037e8744 12643 const char *opname = 0;
5f4273c7 12644
037e8744 12645 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
5287ad62 12646 {
037e8744
JB
12647 /* Conversions with immediate bitshift. */
12648 const char *enc[] =
12649 {
12650 "ftosls",
12651 "ftouls",
12652 "fsltos",
12653 "fultos",
12654 NULL,
12655 NULL,
8e79c3df
CM
12656 NULL,
12657 NULL,
037e8744
JB
12658 "ftosld",
12659 "ftould",
12660 "fsltod",
12661 "fultod",
12662 "fshtos",
12663 "fuhtos",
12664 "fshtod",
12665 "fuhtod",
12666 "ftoshs",
12667 "ftouhs",
12668 "ftoshd",
12669 "ftouhd"
12670 };
12671
12672 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12673 {
12674 opname = enc[flavour];
12675 constraint (inst.operands[0].reg != inst.operands[1].reg,
12676 _("operands 0 and 1 must be the same register"));
12677 inst.operands[1] = inst.operands[2];
12678 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
12679 }
5287ad62
JB
12680 }
12681 else
12682 {
037e8744
JB
12683 /* Conversions without bitshift. */
12684 const char *enc[] =
12685 {
12686 "ftosis",
12687 "ftouis",
12688 "fsitos",
12689 "fuitos",
8e79c3df
CM
12690 "NULL",
12691 "NULL",
037e8744
JB
12692 "fcvtsd",
12693 "fcvtds",
12694 "ftosid",
12695 "ftouid",
12696 "fsitod",
12697 "fuitod"
12698 };
12699
12700 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12701 opname = enc[flavour];
12702 }
12703
12704 if (opname)
12705 do_vfp_nsyn_opcode (opname);
12706}
12707
12708static void
12709do_vfp_nsyn_cvtz (void)
12710{
12711 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
12712 int flavour = neon_cvt_flavour (rs);
12713 const char *enc[] =
12714 {
12715 "ftosizs",
12716 "ftouizs",
12717 NULL,
12718 NULL,
12719 NULL,
12720 NULL,
8e79c3df
CM
12721 NULL,
12722 NULL,
037e8744
JB
12723 "ftosizd",
12724 "ftouizd"
12725 };
12726
12727 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
12728 do_vfp_nsyn_opcode (enc[flavour]);
12729}
037e8744
JB
12730static void
12731do_neon_cvt (void)
12732{
12733 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
8e79c3df 12734 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
037e8744
JB
12735 int flavour = neon_cvt_flavour (rs);
12736
12737 /* VFP rather than Neon conversions. */
8e79c3df 12738 if (flavour >= 6)
037e8744
JB
12739 {
12740 do_vfp_nsyn_cvt (rs, flavour);
12741 return;
12742 }
12743
12744 switch (rs)
12745 {
12746 case NS_DDI:
12747 case NS_QQI:
12748 {
35997600
NC
12749 unsigned immbits;
12750 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12751
037e8744
JB
12752 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12753 return;
12754
12755 /* Fixed-point conversion with #0 immediate is encoded as an
12756 integer conversion. */
12757 if (inst.operands[2].present && inst.operands[2].imm == 0)
12758 goto int_encode;
35997600 12759 immbits = 32 - inst.operands[2].imm;
037e8744
JB
12760 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12761 if (flavour != -1)
12762 inst.instruction |= enctab[flavour];
12763 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12764 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12765 inst.instruction |= LOW4 (inst.operands[1].reg);
12766 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12767 inst.instruction |= neon_quad (rs) << 6;
12768 inst.instruction |= 1 << 21;
12769 inst.instruction |= immbits << 16;
12770
12771 inst.instruction = neon_dp_fixup (inst.instruction);
12772 }
12773 break;
12774
12775 case NS_DD:
12776 case NS_QQ:
12777 int_encode:
12778 {
12779 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
12780
12781 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12782
12783 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12784 return;
12785
12786 if (flavour != -1)
12787 inst.instruction |= enctab[flavour];
12788
12789 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12790 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12791 inst.instruction |= LOW4 (inst.operands[1].reg);
12792 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12793 inst.instruction |= neon_quad (rs) << 6;
12794 inst.instruction |= 2 << 18;
12795
12796 inst.instruction = neon_dp_fixup (inst.instruction);
12797 }
12798 break;
12799
8e79c3df
CM
12800 /* Half-precision conversions for Advanced SIMD -- neon. */
12801 case NS_QD:
12802 case NS_DQ:
12803
12804 if ((rs == NS_DQ)
12805 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
12806 {
12807 as_bad (_("operand size must match register width"));
12808 break;
12809 }
12810
12811 if ((rs == NS_QD)
12812 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
12813 {
12814 as_bad (_("operand size must match register width"));
12815 break;
12816 }
12817
12818 if (rs == NS_DQ)
12819 inst.instruction = 0x3b60600;
12820 else
12821 inst.instruction = 0x3b60700;
12822
12823 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12824 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12825 inst.instruction |= LOW4 (inst.operands[1].reg);
12826 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12827 inst.instruction = neon_dp_fixup (inst.instruction);
12828 break;
12829
037e8744
JB
12830 default:
12831 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12832 do_vfp_nsyn_cvt (rs, flavour);
5287ad62 12833 }
5287ad62
JB
12834}
12835
8e79c3df
CM
12836static void
12837do_neon_cvtb (void)
12838{
12839 inst.instruction = 0xeb20a40;
12840
12841 /* The sizes are attached to the mnemonic. */
12842 if (inst.vectype.el[0].type != NT_invtype
12843 && inst.vectype.el[0].size == 16)
12844 inst.instruction |= 0x00010000;
12845
12846 /* Programmer's syntax: the sizes are attached to the operands. */
12847 else if (inst.operands[0].vectype.type != NT_invtype
12848 && inst.operands[0].vectype.size == 16)
12849 inst.instruction |= 0x00010000;
12850
12851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
12852 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
12853 do_vfp_cond_or_thumb ();
12854}
12855
12856
12857static void
12858do_neon_cvtt (void)
12859{
12860 do_neon_cvtb ();
12861 inst.instruction |= 0x80;
12862}
12863
5287ad62
JB
12864static void
12865neon_move_immediate (void)
12866{
037e8744
JB
12867 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
12868 struct neon_type_el et = neon_check_type (2, rs,
12869 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 12870 unsigned immlo, immhi = 0, immbits;
c96612cc 12871 int op, cmode, float_p;
5287ad62 12872
037e8744
JB
12873 constraint (et.type == NT_invtype,
12874 _("operand size must be specified for immediate VMOV"));
12875
5287ad62
JB
12876 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12877 op = (inst.instruction & (1 << 5)) != 0;
12878
12879 immlo = inst.operands[1].imm;
12880 if (inst.operands[1].regisimm)
12881 immhi = inst.operands[1].reg;
12882
12883 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
12884 _("immediate has bits set outside the operand size"));
12885
c96612cc
JB
12886 float_p = inst.operands[1].immisfloat;
12887
12888 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
136da414 12889 et.size, et.type)) == FAIL)
5287ad62
JB
12890 {
12891 /* Invert relevant bits only. */
12892 neon_invert_size (&immlo, &immhi, et.size);
12893 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12894 with one or the other; those cases are caught by
12895 neon_cmode_for_move_imm. */
12896 op = !op;
c96612cc
JB
12897 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
12898 &op, et.size, et.type)) == FAIL)
5287ad62 12899 {
dcbf9037 12900 first_error (_("immediate out of range"));
5287ad62
JB
12901 return;
12902 }
12903 }
12904
12905 inst.instruction &= ~(1 << 5);
12906 inst.instruction |= op << 5;
12907
12908 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12909 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 12910 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
12911 inst.instruction |= cmode << 8;
12912
12913 neon_write_immbits (immbits);
12914}
12915
12916static void
12917do_neon_mvn (void)
12918{
12919 if (inst.operands[1].isreg)
12920 {
037e8744 12921 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 12922
5287ad62
JB
12923 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12924 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12925 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12926 inst.instruction |= LOW4 (inst.operands[1].reg);
12927 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 12928 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
12929 }
12930 else
12931 {
12932 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12933 neon_move_immediate ();
12934 }
12935
12936 inst.instruction = neon_dp_fixup (inst.instruction);
12937}
12938
12939/* Encode instructions of form:
12940
12941 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 12942 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB
12943
12944static void
12945neon_mixed_length (struct neon_type_el et, unsigned size)
12946{
12947 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12948 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12949 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12950 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12951 inst.instruction |= LOW4 (inst.operands[2].reg);
12952 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12953 inst.instruction |= (et.type == NT_unsigned) << 24;
12954 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 12955
5287ad62
JB
12956 inst.instruction = neon_dp_fixup (inst.instruction);
12957}
12958
12959static void
12960do_neon_dyadic_long (void)
12961{
12962 /* FIXME: Type checking for lengthening op. */
12963 struct neon_type_el et = neon_check_type (3, NS_QDD,
12964 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
12965 neon_mixed_length (et, et.size);
12966}
12967
12968static void
12969do_neon_abal (void)
12970{
12971 struct neon_type_el et = neon_check_type (3, NS_QDD,
12972 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
12973 neon_mixed_length (et, et.size);
12974}
12975
12976static void
12977neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
12978{
12979 if (inst.operands[2].isscalar)
12980 {
dcbf9037
JB
12981 struct neon_type_el et = neon_check_type (3, NS_QDS,
12982 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
5287ad62
JB
12983 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12984 neon_mul_mac (et, et.type == NT_unsigned);
12985 }
12986 else
12987 {
12988 struct neon_type_el et = neon_check_type (3, NS_QDD,
12989 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
12990 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12991 neon_mixed_length (et, et.size);
12992 }
12993}
12994
12995static void
12996do_neon_mac_maybe_scalar_long (void)
12997{
12998 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
12999}
13000
13001static void
13002do_neon_dyadic_wide (void)
13003{
13004 struct neon_type_el et = neon_check_type (3, NS_QQD,
13005 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
13006 neon_mixed_length (et, et.size);
13007}
13008
13009static void
13010do_neon_dyadic_narrow (void)
13011{
13012 struct neon_type_el et = neon_check_type (3, NS_QDD,
13013 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB
13014 /* Operand sign is unimportant, and the U bit is part of the opcode,
13015 so force the operand type to integer. */
13016 et.type = NT_integer;
5287ad62
JB
13017 neon_mixed_length (et, et.size / 2);
13018}
13019
13020static void
13021do_neon_mul_sat_scalar_long (void)
13022{
13023 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
13024}
13025
13026static void
13027do_neon_vmull (void)
13028{
13029 if (inst.operands[2].isscalar)
13030 do_neon_mac_maybe_scalar_long ();
13031 else
13032 {
13033 struct neon_type_el et = neon_check_type (3, NS_QDD,
13034 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
13035 if (et.type == NT_poly)
13036 inst.instruction = NEON_ENC_POLY (inst.instruction);
13037 else
13038 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
13039 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13040 zero. Should be OK as-is. */
13041 neon_mixed_length (et, et.size);
13042 }
13043}
13044
13045static void
13046do_neon_ext (void)
13047{
037e8744 13048 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB
13049 struct neon_type_el et = neon_check_type (3, rs,
13050 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13051 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC
13052
13053 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
13054 _("shift out of range"));
5287ad62
JB
13055 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13056 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13057 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13058 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13059 inst.instruction |= LOW4 (inst.operands[2].reg);
13060 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 13061 inst.instruction |= neon_quad (rs) << 6;
5287ad62 13062 inst.instruction |= imm << 8;
5f4273c7 13063
5287ad62
JB
13064 inst.instruction = neon_dp_fixup (inst.instruction);
13065}
13066
13067static void
13068do_neon_rev (void)
13069{
037e8744 13070 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13071 struct neon_type_el et = neon_check_type (2, rs,
13072 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13073 unsigned op = (inst.instruction >> 7) & 3;
13074 /* N (width of reversed regions) is encoded as part of the bitmask. We
13075 extract it here to check the elements to be reversed are smaller.
13076 Otherwise we'd get a reserved instruction. */
13077 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
13078 assert (elsize != 0);
13079 constraint (et.size >= elsize,
13080 _("elements must be smaller than reversal region"));
037e8744 13081 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13082}
13083
13084static void
13085do_neon_dup (void)
13086{
13087 if (inst.operands[1].isscalar)
13088 {
037e8744 13089 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037
JB
13090 struct neon_type_el et = neon_check_type (2, rs,
13091 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 13092 unsigned sizebits = et.size >> 3;
dcbf9037 13093 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 13094 int logsize = neon_logbits (et.size);
dcbf9037 13095 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB
13096
13097 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
13098 return;
13099
5287ad62
JB
13100 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
13101 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13102 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13103 inst.instruction |= LOW4 (dm);
13104 inst.instruction |= HI1 (dm) << 5;
037e8744 13105 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB
13106 inst.instruction |= x << 17;
13107 inst.instruction |= sizebits << 16;
5f4273c7 13108
5287ad62
JB
13109 inst.instruction = neon_dp_fixup (inst.instruction);
13110 }
13111 else
13112 {
037e8744
JB
13113 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
13114 struct neon_type_el et = neon_check_type (2, rs,
13115 N_8 | N_16 | N_32 | N_KEY, N_EQK);
5287ad62
JB
13116 /* Duplicate ARM register to lanes of vector. */
13117 inst.instruction = NEON_ENC_ARMREG (inst.instruction);
13118 switch (et.size)
13119 {
13120 case 8: inst.instruction |= 0x400000; break;
13121 case 16: inst.instruction |= 0x000020; break;
13122 case 32: inst.instruction |= 0x000000; break;
13123 default: break;
13124 }
13125 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13126 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
13127 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 13128 inst.instruction |= neon_quad (rs) << 21;
5287ad62
JB
13129 /* The encoding for this instruction is identical for the ARM and Thumb
13130 variants, except for the condition field. */
037e8744 13131 do_vfp_cond_or_thumb ();
5287ad62
JB
13132 }
13133}
13134
13135/* VMOV has particularly many variations. It can be one of:
13136 0. VMOV<c><q> <Qd>, <Qm>
13137 1. VMOV<c><q> <Dd>, <Dm>
13138 (Register operations, which are VORR with Rm = Rn.)
13139 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13140 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13141 (Immediate loads.)
13142 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13143 (ARM register to scalar.)
13144 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13145 (Two ARM registers to vector.)
13146 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13147 (Scalar to ARM register.)
13148 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13149 (Vector to two ARM registers.)
037e8744
JB
13150 8. VMOV.F32 <Sd>, <Sm>
13151 9. VMOV.F64 <Dd>, <Dm>
13152 (VFP register moves.)
13153 10. VMOV.F32 <Sd>, #imm
13154 11. VMOV.F64 <Dd>, #imm
13155 (VFP float immediate load.)
13156 12. VMOV <Rd>, <Sm>
13157 (VFP single to ARM reg.)
13158 13. VMOV <Sd>, <Rm>
13159 (ARM reg to VFP single.)
13160 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13161 (Two ARM regs to two VFP singles.)
13162 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13163 (Two VFP singles to two ARM regs.)
5f4273c7 13164
037e8744
JB
13165 These cases can be disambiguated using neon_select_shape, except cases 1/9
13166 and 3/11 which depend on the operand type too.
5f4273c7 13167
5287ad62 13168 All the encoded bits are hardcoded by this function.
5f4273c7 13169
b7fc2769
JB
13170 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13171 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 13172
5287ad62 13173 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 13174 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB
13175
13176static void
13177do_neon_mov (void)
13178{
037e8744
JB
13179 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
13180 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
13181 NS_NULL);
13182 struct neon_type_el et;
13183 const char *ldconst = 0;
5287ad62 13184
037e8744 13185 switch (rs)
5287ad62 13186 {
037e8744
JB
13187 case NS_DD: /* case 1/9. */
13188 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13189 /* It is not an error here if no type is given. */
13190 inst.error = NULL;
13191 if (et.type == NT_float && et.size == 64)
5287ad62 13192 {
037e8744
JB
13193 do_vfp_nsyn_opcode ("fcpyd");
13194 break;
5287ad62 13195 }
037e8744 13196 /* fall through. */
5287ad62 13197
037e8744
JB
13198 case NS_QQ: /* case 0/1. */
13199 {
13200 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13201 return;
13202 /* The architecture manual I have doesn't explicitly state which
13203 value the U bit should have for register->register moves, but
13204 the equivalent VORR instruction has U = 0, so do that. */
13205 inst.instruction = 0x0200110;
13206 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13207 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13208 inst.instruction |= LOW4 (inst.operands[1].reg);
13209 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13210 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13211 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13212 inst.instruction |= neon_quad (rs) << 6;
13213
13214 inst.instruction = neon_dp_fixup (inst.instruction);
13215 }
13216 break;
5f4273c7 13217
037e8744
JB
13218 case NS_DI: /* case 3/11. */
13219 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13220 inst.error = NULL;
13221 if (et.type == NT_float && et.size == 64)
5287ad62 13222 {
037e8744
JB
13223 /* case 11 (fconstd). */
13224 ldconst = "fconstd";
13225 goto encode_fconstd;
5287ad62 13226 }
037e8744
JB
13227 /* fall through. */
13228
13229 case NS_QI: /* case 2/3. */
13230 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13231 return;
13232 inst.instruction = 0x0800010;
13233 neon_move_immediate ();
13234 inst.instruction = neon_dp_fixup (inst.instruction);
5287ad62 13235 break;
5f4273c7 13236
037e8744
JB
13237 case NS_SR: /* case 4. */
13238 {
13239 unsigned bcdebits = 0;
13240 struct neon_type_el et = neon_check_type (2, NS_NULL,
13241 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13242 int logsize = neon_logbits (et.size);
13243 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13244 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13245
13246 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13247 _(BAD_FPU));
13248 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13249 && et.size != 32, _(BAD_FPU));
13250 constraint (et.type == NT_invtype, _("bad type for scalar"));
13251 constraint (x >= 64 / et.size, _("scalar index out of range"));
13252
13253 switch (et.size)
13254 {
13255 case 8: bcdebits = 0x8; break;
13256 case 16: bcdebits = 0x1; break;
13257 case 32: bcdebits = 0x0; break;
13258 default: ;
13259 }
13260
13261 bcdebits |= x << logsize;
13262
13263 inst.instruction = 0xe000b10;
13264 do_vfp_cond_or_thumb ();
13265 inst.instruction |= LOW4 (dn) << 16;
13266 inst.instruction |= HI1 (dn) << 7;
13267 inst.instruction |= inst.operands[1].reg << 12;
13268 inst.instruction |= (bcdebits & 3) << 5;
13269 inst.instruction |= (bcdebits >> 2) << 21;
13270 }
13271 break;
5f4273c7 13272
037e8744 13273 case NS_DRR: /* case 5 (fmdrr). */
b7fc2769 13274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
037e8744 13275 _(BAD_FPU));
b7fc2769 13276
037e8744
JB
13277 inst.instruction = 0xc400b10;
13278 do_vfp_cond_or_thumb ();
13279 inst.instruction |= LOW4 (inst.operands[0].reg);
13280 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13281 inst.instruction |= inst.operands[1].reg << 12;
13282 inst.instruction |= inst.operands[2].reg << 16;
13283 break;
5f4273c7 13284
037e8744
JB
13285 case NS_RS: /* case 6. */
13286 {
13287 struct neon_type_el et = neon_check_type (2, NS_NULL,
13288 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
13289 unsigned logsize = neon_logbits (et.size);
13290 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13291 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13292 unsigned abcdebits = 0;
13293
13294 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13295 _(BAD_FPU));
13296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13297 && et.size != 32, _(BAD_FPU));
13298 constraint (et.type == NT_invtype, _("bad type for scalar"));
13299 constraint (x >= 64 / et.size, _("scalar index out of range"));
13300
13301 switch (et.size)
13302 {
13303 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
13304 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
13305 case 32: abcdebits = 0x00; break;
13306 default: ;
13307 }
13308
13309 abcdebits |= x << logsize;
13310 inst.instruction = 0xe100b10;
13311 do_vfp_cond_or_thumb ();
13312 inst.instruction |= LOW4 (dn) << 16;
13313 inst.instruction |= HI1 (dn) << 7;
13314 inst.instruction |= inst.operands[0].reg << 12;
13315 inst.instruction |= (abcdebits & 3) << 5;
13316 inst.instruction |= (abcdebits >> 2) << 21;
13317 }
13318 break;
5f4273c7 13319
037e8744
JB
13320 case NS_RRD: /* case 7 (fmrrd). */
13321 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13322 _(BAD_FPU));
13323
13324 inst.instruction = 0xc500b10;
13325 do_vfp_cond_or_thumb ();
13326 inst.instruction |= inst.operands[0].reg << 12;
13327 inst.instruction |= inst.operands[1].reg << 16;
13328 inst.instruction |= LOW4 (inst.operands[2].reg);
13329 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13330 break;
5f4273c7 13331
037e8744
JB
13332 case NS_FF: /* case 8 (fcpys). */
13333 do_vfp_nsyn_opcode ("fcpys");
13334 break;
5f4273c7 13335
037e8744
JB
13336 case NS_FI: /* case 10 (fconsts). */
13337 ldconst = "fconsts";
13338 encode_fconstd:
13339 if (is_quarter_float (inst.operands[1].imm))
5287ad62 13340 {
037e8744
JB
13341 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13342 do_vfp_nsyn_opcode (ldconst);
5287ad62
JB
13343 }
13344 else
037e8744
JB
13345 first_error (_("immediate out of range"));
13346 break;
5f4273c7 13347
037e8744
JB
13348 case NS_RF: /* case 12 (fmrs). */
13349 do_vfp_nsyn_opcode ("fmrs");
13350 break;
5f4273c7 13351
037e8744
JB
13352 case NS_FR: /* case 13 (fmsr). */
13353 do_vfp_nsyn_opcode ("fmsr");
13354 break;
5f4273c7 13355
037e8744
JB
13356 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13357 (one of which is a list), but we have parsed four. Do some fiddling to
13358 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13359 expect. */
13360 case NS_RRFF: /* case 14 (fmrrs). */
13361 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13362 _("VFP registers must be adjacent"));
13363 inst.operands[2].imm = 2;
13364 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13365 do_vfp_nsyn_opcode ("fmrrs");
13366 break;
5f4273c7 13367
037e8744
JB
13368 case NS_FFRR: /* case 15 (fmsrr). */
13369 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13370 _("VFP registers must be adjacent"));
13371 inst.operands[1] = inst.operands[2];
13372 inst.operands[2] = inst.operands[3];
13373 inst.operands[0].imm = 2;
13374 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13375 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 13376 break;
5f4273c7 13377
5287ad62
JB
13378 default:
13379 abort ();
13380 }
13381}
13382
13383static void
13384do_neon_rshift_round_imm (void)
13385{
037e8744 13386 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB
13387 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13388 int imm = inst.operands[2].imm;
13389
13390 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13391 if (imm == 0)
13392 {
13393 inst.operands[2].present = 0;
13394 do_neon_mov ();
13395 return;
13396 }
13397
13398 constraint (imm < 1 || (unsigned)imm > et.size,
13399 _("immediate out of range for shift"));
037e8744 13400 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
5287ad62
JB
13401 et.size - imm);
13402}
13403
13404static void
13405do_neon_movl (void)
13406{
13407 struct neon_type_el et = neon_check_type (2, NS_QD,
13408 N_EQK | N_DBL, N_SU_32 | N_KEY);
13409 unsigned sizebits = et.size >> 3;
13410 inst.instruction |= sizebits << 19;
13411 neon_two_same (0, et.type == NT_unsigned, -1);
13412}
13413
13414static void
13415do_neon_trn (void)
13416{
037e8744 13417 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13418 struct neon_type_el et = neon_check_type (2, rs,
13419 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13420 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
037e8744 13421 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13422}
13423
13424static void
13425do_neon_zip_uzp (void)
13426{
037e8744 13427 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13428 struct neon_type_el et = neon_check_type (2, rs,
13429 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13430 if (rs == NS_DD && et.size == 32)
13431 {
13432 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13433 inst.instruction = N_MNEM_vtrn;
13434 do_neon_trn ();
13435 return;
13436 }
037e8744 13437 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13438}
13439
13440static void
13441do_neon_sat_abs_neg (void)
13442{
037e8744 13443 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13444 struct neon_type_el et = neon_check_type (2, rs,
13445 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 13446 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13447}
13448
13449static void
13450do_neon_pair_long (void)
13451{
037e8744 13452 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13453 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
13454 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13455 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 13456 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13457}
13458
13459static void
13460do_neon_recip_est (void)
13461{
037e8744 13462 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13463 struct neon_type_el et = neon_check_type (2, rs,
13464 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
13465 inst.instruction |= (et.type == NT_float) << 8;
037e8744 13466 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13467}
13468
13469static void
13470do_neon_cls (void)
13471{
037e8744 13472 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13473 struct neon_type_el et = neon_check_type (2, rs,
13474 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 13475 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13476}
13477
13478static void
13479do_neon_clz (void)
13480{
037e8744 13481 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13482 struct neon_type_el et = neon_check_type (2, rs,
13483 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 13484 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13485}
13486
13487static void
13488do_neon_cnt (void)
13489{
037e8744 13490 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB
13491 struct neon_type_el et = neon_check_type (2, rs,
13492 N_EQK | N_INT, N_8 | N_KEY);
037e8744 13493 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB
13494}
13495
13496static void
13497do_neon_swp (void)
13498{
037e8744
JB
13499 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13500 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB
13501}
13502
13503static void
13504do_neon_tbl_tbx (void)
13505{
13506 unsigned listlenbits;
dcbf9037 13507 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 13508
5287ad62
JB
13509 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13510 {
dcbf9037 13511 first_error (_("bad list length for table lookup"));
5287ad62
JB
13512 return;
13513 }
5f4273c7 13514
5287ad62
JB
13515 listlenbits = inst.operands[1].imm - 1;
13516 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13517 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13518 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13519 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13520 inst.instruction |= LOW4 (inst.operands[2].reg);
13521 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13522 inst.instruction |= listlenbits << 8;
5f4273c7 13523
5287ad62
JB
13524 inst.instruction = neon_dp_fixup (inst.instruction);
13525}
13526
13527static void
13528do_neon_ldm_stm (void)
13529{
13530 /* P, U and L bits are part of bitmask. */
13531 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
13532 unsigned offsetbits = inst.operands[1].imm * 2;
13533
037e8744
JB
13534 if (inst.operands[1].issingle)
13535 {
13536 do_vfp_nsyn_ldm_stm (is_dbmode);
13537 return;
13538 }
13539
5287ad62
JB
13540 constraint (is_dbmode && !inst.operands[0].writeback,
13541 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13542
13543 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13544 _("register list must contain at least 1 and at most 16 "
13545 "registers"));
13546
13547 inst.instruction |= inst.operands[0].reg << 16;
13548 inst.instruction |= inst.operands[0].writeback << 21;
13549 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13550 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13551
13552 inst.instruction |= offsetbits;
5f4273c7 13553
037e8744 13554 do_vfp_cond_or_thumb ();
5287ad62
JB
13555}
13556
13557static void
13558do_neon_ldr_str (void)
13559{
5287ad62 13560 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 13561
037e8744
JB
13562 if (inst.operands[0].issingle)
13563 {
cd2f129f
JB
13564 if (is_ldr)
13565 do_vfp_nsyn_opcode ("flds");
13566 else
13567 do_vfp_nsyn_opcode ("fsts");
5287ad62
JB
13568 }
13569 else
5287ad62 13570 {
cd2f129f
JB
13571 if (is_ldr)
13572 do_vfp_nsyn_opcode ("fldd");
5287ad62 13573 else
cd2f129f 13574 do_vfp_nsyn_opcode ("fstd");
5287ad62 13575 }
5287ad62
JB
13576}
13577
13578/* "interleave" version also handles non-interleaving register VLD1/VST1
13579 instructions. */
13580
13581static void
13582do_neon_ld_st_interleave (void)
13583{
037e8744 13584 struct neon_type_el et = neon_check_type (1, NS_NULL,
5287ad62
JB
13585 N_8 | N_16 | N_32 | N_64);
13586 unsigned alignbits = 0;
13587 unsigned idx;
13588 /* The bits in this table go:
13589 0: register stride of one (0) or two (1)
13590 1,2: register list length, minus one (1, 2, 3, 4).
13591 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13592 We use -1 for invalid entries. */
13593 const int typetable[] =
13594 {
13595 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13596 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13597 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13598 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13599 };
13600 int typebits;
13601
dcbf9037
JB
13602 if (et.type == NT_invtype)
13603 return;
13604
5287ad62
JB
13605 if (inst.operands[1].immisalign)
13606 switch (inst.operands[1].imm >> 8)
13607 {
13608 case 64: alignbits = 1; break;
13609 case 128:
13610 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13611 goto bad_alignment;
13612 alignbits = 2;
13613 break;
13614 case 256:
13615 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13616 goto bad_alignment;
13617 alignbits = 3;
13618 break;
13619 default:
13620 bad_alignment:
dcbf9037 13621 first_error (_("bad alignment"));
5287ad62
JB
13622 return;
13623 }
13624
13625 inst.instruction |= alignbits << 4;
13626 inst.instruction |= neon_logbits (et.size) << 6;
13627
13628 /* Bits [4:6] of the immediate in a list specifier encode register stride
13629 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13630 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13631 up the right value for "type" in a table based on this value and the given
13632 list style, then stick it back. */
13633 idx = ((inst.operands[0].imm >> 4) & 7)
13634 | (((inst.instruction >> 8) & 3) << 3);
13635
13636 typebits = typetable[idx];
5f4273c7 13637
5287ad62
JB
13638 constraint (typebits == -1, _("bad list type for instruction"));
13639
13640 inst.instruction &= ~0xf00;
13641 inst.instruction |= typebits << 8;
13642}
13643
13644/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13645 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13646 otherwise. The variable arguments are a list of pairs of legal (size, align)
13647 values, terminated with -1. */
13648
13649static int
13650neon_alignment_bit (int size, int align, int *do_align, ...)
13651{
13652 va_list ap;
13653 int result = FAIL, thissize, thisalign;
5f4273c7 13654
5287ad62
JB
13655 if (!inst.operands[1].immisalign)
13656 {
13657 *do_align = 0;
13658 return SUCCESS;
13659 }
5f4273c7 13660
5287ad62
JB
13661 va_start (ap, do_align);
13662
13663 do
13664 {
13665 thissize = va_arg (ap, int);
13666 if (thissize == -1)
13667 break;
13668 thisalign = va_arg (ap, int);
13669
13670 if (size == thissize && align == thisalign)
13671 result = SUCCESS;
13672 }
13673 while (result != SUCCESS);
13674
13675 va_end (ap);
13676
13677 if (result == SUCCESS)
13678 *do_align = 1;
13679 else
dcbf9037 13680 first_error (_("unsupported alignment for instruction"));
5f4273c7 13681
5287ad62
JB
13682 return result;
13683}
13684
13685static void
13686do_neon_ld_st_lane (void)
13687{
037e8744 13688 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB
13689 int align_good, do_align = 0;
13690 int logsize = neon_logbits (et.size);
13691 int align = inst.operands[1].imm >> 8;
13692 int n = (inst.instruction >> 8) & 3;
13693 int max_el = 64 / et.size;
5f4273c7 13694
dcbf9037
JB
13695 if (et.type == NT_invtype)
13696 return;
5f4273c7 13697
5287ad62
JB
13698 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13699 _("bad list length"));
13700 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13701 _("scalar index out of range"));
13702 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13703 && et.size == 8,
13704 _("stride of 2 unavailable when element size is 8"));
5f4273c7 13705
5287ad62
JB
13706 switch (n)
13707 {
13708 case 0: /* VLD1 / VST1. */
13709 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
13710 32, 32, -1);
13711 if (align_good == FAIL)
13712 return;
13713 if (do_align)
13714 {
13715 unsigned alignbits = 0;
13716 switch (et.size)
13717 {
13718 case 16: alignbits = 0x1; break;
13719 case 32: alignbits = 0x3; break;
13720 default: ;
13721 }
13722 inst.instruction |= alignbits << 4;
13723 }
13724 break;
13725
13726 case 1: /* VLD2 / VST2. */
13727 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
13728 32, 64, -1);
13729 if (align_good == FAIL)
13730 return;
13731 if (do_align)
13732 inst.instruction |= 1 << 4;
13733 break;
13734
13735 case 2: /* VLD3 / VST3. */
13736 constraint (inst.operands[1].immisalign,
13737 _("can't use alignment with this instruction"));
13738 break;
13739
13740 case 3: /* VLD4 / VST4. */
13741 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13742 16, 64, 32, 64, 32, 128, -1);
13743 if (align_good == FAIL)
13744 return;
13745 if (do_align)
13746 {
13747 unsigned alignbits = 0;
13748 switch (et.size)
13749 {
13750 case 8: alignbits = 0x1; break;
13751 case 16: alignbits = 0x1; break;
13752 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
13753 default: ;
13754 }
13755 inst.instruction |= alignbits << 4;
13756 }
13757 break;
13758
13759 default: ;
13760 }
13761
13762 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13763 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13764 inst.instruction |= 1 << (4 + logsize);
5f4273c7 13765
5287ad62
JB
13766 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13767 inst.instruction |= logsize << 10;
13768}
13769
13770/* Encode single n-element structure to all lanes VLD<n> instructions. */
13771
13772static void
13773do_neon_ld_dup (void)
13774{
037e8744 13775 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB
13776 int align_good, do_align = 0;
13777
dcbf9037
JB
13778 if (et.type == NT_invtype)
13779 return;
13780
5287ad62
JB
13781 switch ((inst.instruction >> 8) & 3)
13782 {
13783 case 0: /* VLD1. */
13784 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13785 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13786 &do_align, 16, 16, 32, 32, -1);
13787 if (align_good == FAIL)
13788 return;
13789 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13790 {
13791 case 1: break;
13792 case 2: inst.instruction |= 1 << 5; break;
dcbf9037 13793 default: first_error (_("bad list length")); return;
5287ad62
JB
13794 }
13795 inst.instruction |= neon_logbits (et.size) << 6;
13796 break;
13797
13798 case 1: /* VLD2. */
13799 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13800 &do_align, 8, 16, 16, 32, 32, 64, -1);
13801 if (align_good == FAIL)
13802 return;
13803 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13804 _("bad list length"));
13805 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13806 inst.instruction |= 1 << 5;
13807 inst.instruction |= neon_logbits (et.size) << 6;
13808 break;
13809
13810 case 2: /* VLD3. */
13811 constraint (inst.operands[1].immisalign,
13812 _("can't use alignment with this instruction"));
13813 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13814 _("bad list length"));
13815 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13816 inst.instruction |= 1 << 5;
13817 inst.instruction |= neon_logbits (et.size) << 6;
13818 break;
13819
13820 case 3: /* VLD4. */
13821 {
13822 int align = inst.operands[1].imm >> 8;
13823 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13824 16, 64, 32, 64, 32, 128, -1);
13825 if (align_good == FAIL)
13826 return;
13827 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13828 _("bad list length"));
13829 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13830 inst.instruction |= 1 << 5;
13831 if (et.size == 32 && align == 128)
13832 inst.instruction |= 0x3 << 6;
13833 else
13834 inst.instruction |= neon_logbits (et.size) << 6;
13835 }
13836 break;
13837
13838 default: ;
13839 }
13840
13841 inst.instruction |= do_align << 4;
13842}
13843
13844/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13845 apart from bits [11:4]. */
13846
13847static void
13848do_neon_ldx_stx (void)
13849{
13850 switch (NEON_LANE (inst.operands[0].imm))
13851 {
13852 case NEON_INTERLEAVE_LANES:
13853 inst.instruction = NEON_ENC_INTERLV (inst.instruction);
13854 do_neon_ld_st_interleave ();
13855 break;
5f4273c7 13856
5287ad62
JB
13857 case NEON_ALL_LANES:
13858 inst.instruction = NEON_ENC_DUP (inst.instruction);
13859 do_neon_ld_dup ();
13860 break;
5f4273c7 13861
5287ad62
JB
13862 default:
13863 inst.instruction = NEON_ENC_LANE (inst.instruction);
13864 do_neon_ld_st_lane ();
13865 }
13866
13867 /* L bit comes from bit mask. */
13868 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13869 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13870 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 13871
5287ad62
JB
13872 if (inst.operands[1].postind)
13873 {
13874 int postreg = inst.operands[1].imm & 0xf;
13875 constraint (!inst.operands[1].immisreg,
13876 _("post-index must be a register"));
13877 constraint (postreg == 0xd || postreg == 0xf,
13878 _("bad register for post-index"));
13879 inst.instruction |= postreg;
13880 }
13881 else if (inst.operands[1].writeback)
13882 {
13883 inst.instruction |= 0xd;
13884 }
13885 else
5f4273c7
NC
13886 inst.instruction |= 0xf;
13887
5287ad62
JB
13888 if (thumb_mode)
13889 inst.instruction |= 0xf9000000;
13890 else
13891 inst.instruction |= 0xf4000000;
13892}
5287ad62
JB
13893\f
13894/* Overall per-instruction processing. */
13895
13896/* We need to be able to fix up arbitrary expressions in some statements.
13897 This is so that we can handle symbols that are an arbitrary distance from
13898 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13899 which returns part of an address in a form which will be valid for
13900 a data instruction. We do this by pushing the expression into a symbol
13901 in the expr_section, and creating a fix for that. */
13902
13903static void
13904fix_new_arm (fragS * frag,
13905 int where,
13906 short int size,
13907 expressionS * exp,
13908 int pc_rel,
13909 int reloc)
13910{
13911 fixS * new_fix;
13912
13913 switch (exp->X_op)
13914 {
13915 case O_constant:
13916 case O_symbol:
13917 case O_add:
13918 case O_subtract:
13919 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
13920 break;
13921
13922 default:
13923 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
13924 pc_rel, reloc);
13925 break;
13926 }
13927
13928 /* Mark whether the fix is to a THUMB instruction, or an ARM
13929 instruction. */
13930 new_fix->tc_fix_data = thumb_mode;
13931}
13932
13933/* Create a frg for an instruction requiring relaxation. */
13934static void
13935output_relax_insn (void)
13936{
13937 char * to;
13938 symbolS *sym;
0110f2b8
PB
13939 int offset;
13940
6e1cb1a6
PB
13941 /* The size of the instruction is unknown, so tie the debug info to the
13942 start of the instruction. */
13943 dwarf2_emit_insn (0);
6e1cb1a6 13944
0110f2b8
PB
13945 switch (inst.reloc.exp.X_op)
13946 {
13947 case O_symbol:
13948 sym = inst.reloc.exp.X_add_symbol;
13949 offset = inst.reloc.exp.X_add_number;
13950 break;
13951 case O_constant:
13952 sym = NULL;
13953 offset = inst.reloc.exp.X_add_number;
13954 break;
13955 default:
13956 sym = make_expr_symbol (&inst.reloc.exp);
13957 offset = 0;
13958 break;
13959 }
13960 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13961 inst.relax, sym, offset, NULL/*offset, opcode*/);
13962 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB
13963}
13964
13965/* Write a 32-bit thumb instruction to buf. */
13966static void
13967put_thumb32_insn (char * buf, unsigned long insn)
13968{
13969 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
13970 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
13971}
13972
b99bd4ef 13973static void
c19d1205 13974output_inst (const char * str)
b99bd4ef 13975{
c19d1205 13976 char * to = NULL;
b99bd4ef 13977
c19d1205 13978 if (inst.error)
b99bd4ef 13979 {
c19d1205 13980 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC
13981 return;
13982 }
5f4273c7
NC
13983 if (inst.relax)
13984 {
13985 output_relax_insn ();
0110f2b8 13986 return;
5f4273c7 13987 }
c19d1205
ZW
13988 if (inst.size == 0)
13989 return;
b99bd4ef 13990
c19d1205
ZW
13991 to = frag_more (inst.size);
13992
13993 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 13994 {
c19d1205 13995 assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 13996 put_thumb32_insn (to, inst.instruction);
b99bd4ef 13997 }
c19d1205 13998 else if (inst.size > INSN_SIZE)
b99bd4ef 13999 {
c19d1205
ZW
14000 assert (inst.size == (2 * INSN_SIZE));
14001 md_number_to_chars (to, inst.instruction, INSN_SIZE);
14002 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 14003 }
c19d1205
ZW
14004 else
14005 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 14006
c19d1205
ZW
14007 if (inst.reloc.type != BFD_RELOC_UNUSED)
14008 fix_new_arm (frag_now, to - frag_now->fr_literal,
14009 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
14010 inst.reloc.type);
b99bd4ef 14011
c19d1205 14012 dwarf2_emit_insn (inst.size);
c19d1205 14013}
b99bd4ef 14014
c19d1205
ZW
14015/* Tag values used in struct asm_opcode's tag field. */
14016enum opcode_tag
14017{
14018 OT_unconditional, /* Instruction cannot be conditionalized.
14019 The ARM condition field is still 0xE. */
14020 OT_unconditionalF, /* Instruction cannot be conditionalized
14021 and carries 0xF in its ARM condition field. */
14022 OT_csuffix, /* Instruction takes a conditional suffix. */
037e8744
JB
14023 OT_csuffixF, /* Some forms of the instruction take a conditional
14024 suffix, others place 0xF where the condition field
14025 would be. */
c19d1205
ZW
14026 OT_cinfix3, /* Instruction takes a conditional infix,
14027 beginning at character index 3. (In
14028 unified mode, it becomes a suffix.) */
088fa78e
KH
14029 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
14030 tsts, cmps, cmns, and teqs. */
e3cb604e
PB
14031 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
14032 character index 3, even in unified mode. Used for
14033 legacy instructions where suffix and infix forms
14034 may be ambiguous. */
c19d1205 14035 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 14036 suffix or an infix at character index 3. */
c19d1205
ZW
14037 OT_odd_infix_unc, /* This is the unconditional variant of an
14038 instruction that takes a conditional infix
14039 at an unusual position. In unified mode,
14040 this variant will accept a suffix. */
14041 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
14042 are the conditional variants of instructions that
14043 take conditional infixes in unusual positions.
14044 The infix appears at character index
14045 (tag - OT_odd_infix_0). These are not accepted
14046 in unified mode. */
14047};
b99bd4ef 14048
c19d1205
ZW
14049/* Subroutine of md_assemble, responsible for looking up the primary
14050 opcode from the mnemonic the user wrote. STR points to the
14051 beginning of the mnemonic.
14052
14053 This is not simply a hash table lookup, because of conditional
14054 variants. Most instructions have conditional variants, which are
14055 expressed with a _conditional affix_ to the mnemonic. If we were
14056 to encode each conditional variant as a literal string in the opcode
14057 table, it would have approximately 20,000 entries.
14058
14059 Most mnemonics take this affix as a suffix, and in unified syntax,
14060 'most' is upgraded to 'all'. However, in the divided syntax, some
14061 instructions take the affix as an infix, notably the s-variants of
14062 the arithmetic instructions. Of those instructions, all but six
14063 have the infix appear after the third character of the mnemonic.
14064
14065 Accordingly, the algorithm for looking up primary opcodes given
14066 an identifier is:
14067
14068 1. Look up the identifier in the opcode table.
14069 If we find a match, go to step U.
14070
14071 2. Look up the last two characters of the identifier in the
14072 conditions table. If we find a match, look up the first N-2
14073 characters of the identifier in the opcode table. If we
14074 find a match, go to step CE.
14075
14076 3. Look up the fourth and fifth characters of the identifier in
14077 the conditions table. If we find a match, extract those
14078 characters from the identifier, and look up the remaining
14079 characters in the opcode table. If we find a match, go
14080 to step CM.
14081
14082 4. Fail.
14083
14084 U. Examine the tag field of the opcode structure, in case this is
14085 one of the six instructions with its conditional infix in an
14086 unusual place. If it is, the tag tells us where to find the
14087 infix; look it up in the conditions table and set inst.cond
14088 accordingly. Otherwise, this is an unconditional instruction.
14089 Again set inst.cond accordingly. Return the opcode structure.
14090
14091 CE. Examine the tag field to make sure this is an instruction that
14092 should receive a conditional suffix. If it is not, fail.
14093 Otherwise, set inst.cond from the suffix we already looked up,
14094 and return the opcode structure.
14095
14096 CM. Examine the tag field to make sure this is an instruction that
14097 should receive a conditional infix after the third character.
14098 If it is not, fail. Otherwise, undo the edits to the current
14099 line of input and proceed as for case CE. */
14100
14101static const struct asm_opcode *
14102opcode_lookup (char **str)
14103{
14104 char *end, *base;
14105 char *affix;
14106 const struct asm_opcode *opcode;
14107 const struct asm_cond *cond;
e3cb604e 14108 char save[2];
267d2029 14109 bfd_boolean neon_supported;
5f4273c7 14110
267d2029 14111 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
c19d1205
ZW
14112
14113 /* Scan up to the end of the mnemonic, which must end in white space,
267d2029 14114 '.' (in unified mode, or for Neon instructions), or end of string. */
c19d1205 14115 for (base = end = *str; *end != '\0'; end++)
267d2029 14116 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
c19d1205 14117 break;
b99bd4ef 14118
c19d1205
ZW
14119 if (end == base)
14120 return 0;
b99bd4ef 14121
5287ad62 14122 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 14123 if (end[0] == '.')
b99bd4ef 14124 {
5287ad62 14125 int offset = 2;
5f4273c7 14126
267d2029
JB
14127 /* The .w and .n suffixes are only valid if the unified syntax is in
14128 use. */
14129 if (unified_syntax && end[1] == 'w')
c19d1205 14130 inst.size_req = 4;
267d2029 14131 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW
14132 inst.size_req = 2;
14133 else
5287ad62
JB
14134 offset = 0;
14135
14136 inst.vectype.elems = 0;
14137
14138 *str = end + offset;
b99bd4ef 14139
5f4273c7 14140 if (end[offset] == '.')
5287ad62 14141 {
267d2029
JB
14142 /* See if we have a Neon type suffix (possible in either unified or
14143 non-unified ARM syntax mode). */
dcbf9037 14144 if (parse_neon_type (&inst.vectype, str) == FAIL)
5287ad62
JB
14145 return 0;
14146 }
14147 else if (end[offset] != '\0' && end[offset] != ' ')
14148 return 0;
b99bd4ef 14149 }
c19d1205
ZW
14150 else
14151 *str = end;
b99bd4ef 14152
c19d1205
ZW
14153 /* Look for unaffixed or special-case affixed mnemonic. */
14154 opcode = hash_find_n (arm_ops_hsh, base, end - base);
14155 if (opcode)
b99bd4ef 14156 {
c19d1205
ZW
14157 /* step U */
14158 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 14159 {
c19d1205
ZW
14160 inst.cond = COND_ALWAYS;
14161 return opcode;
b99bd4ef 14162 }
b99bd4ef 14163
c19d1205
ZW
14164 if (unified_syntax)
14165 as_warn (_("conditional infixes are deprecated in unified syntax"));
14166 affix = base + (opcode->tag - OT_odd_infix_0);
14167 cond = hash_find_n (arm_cond_hsh, affix, 2);
14168 assert (cond);
b99bd4ef 14169
c19d1205
ZW
14170 inst.cond = cond->value;
14171 return opcode;
14172 }
b99bd4ef 14173
c19d1205
ZW
14174 /* Cannot have a conditional suffix on a mnemonic of less than two
14175 characters. */
14176 if (end - base < 3)
14177 return 0;
b99bd4ef 14178
c19d1205
ZW
14179 /* Look for suffixed mnemonic. */
14180 affix = end - 2;
14181 cond = hash_find_n (arm_cond_hsh, affix, 2);
14182 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
14183 if (opcode && cond)
14184 {
14185 /* step CE */
14186 switch (opcode->tag)
14187 {
e3cb604e
PB
14188 case OT_cinfix3_legacy:
14189 /* Ignore conditional suffixes matched on infix only mnemonics. */
14190 break;
14191
c19d1205 14192 case OT_cinfix3:
088fa78e 14193 case OT_cinfix3_deprecated:
c19d1205
ZW
14194 case OT_odd_infix_unc:
14195 if (!unified_syntax)
e3cb604e 14196 return 0;
c19d1205
ZW
14197 /* else fall through */
14198
14199 case OT_csuffix:
037e8744 14200 case OT_csuffixF:
c19d1205
ZW
14201 case OT_csuf_or_in3:
14202 inst.cond = cond->value;
14203 return opcode;
14204
14205 case OT_unconditional:
14206 case OT_unconditionalF:
dfa9f0d5
PB
14207 if (thumb_mode)
14208 {
14209 inst.cond = cond->value;
14210 }
14211 else
14212 {
14213 /* delayed diagnostic */
14214 inst.error = BAD_COND;
14215 inst.cond = COND_ALWAYS;
14216 }
c19d1205 14217 return opcode;
b99bd4ef 14218
c19d1205
ZW
14219 default:
14220 return 0;
14221 }
14222 }
b99bd4ef 14223
c19d1205
ZW
14224 /* Cannot have a usual-position infix on a mnemonic of less than
14225 six characters (five would be a suffix). */
14226 if (end - base < 6)
14227 return 0;
b99bd4ef 14228
c19d1205
ZW
14229 /* Look for infixed mnemonic in the usual position. */
14230 affix = base + 3;
14231 cond = hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e
PB
14232 if (!cond)
14233 return 0;
14234
14235 memcpy (save, affix, 2);
14236 memmove (affix, affix + 2, (end - affix) - 2);
14237 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
14238 memmove (affix + 2, affix, (end - affix) - 2);
14239 memcpy (affix, save, 2);
14240
088fa78e
KH
14241 if (opcode
14242 && (opcode->tag == OT_cinfix3
14243 || opcode->tag == OT_cinfix3_deprecated
14244 || opcode->tag == OT_csuf_or_in3
14245 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 14246 {
c19d1205 14247 /* step CM */
088fa78e
KH
14248 if (unified_syntax
14249 && (opcode->tag == OT_cinfix3
14250 || opcode->tag == OT_cinfix3_deprecated))
c19d1205
ZW
14251 as_warn (_("conditional infixes are deprecated in unified syntax"));
14252
14253 inst.cond = cond->value;
14254 return opcode;
b99bd4ef
NC
14255 }
14256
c19d1205 14257 return 0;
b99bd4ef
NC
14258}
14259
c19d1205
ZW
14260void
14261md_assemble (char *str)
b99bd4ef 14262{
c19d1205
ZW
14263 char *p = str;
14264 const struct asm_opcode * opcode;
b99bd4ef 14265
c19d1205
ZW
14266 /* Align the previous label if needed. */
14267 if (last_label_seen != NULL)
b99bd4ef 14268 {
c19d1205
ZW
14269 symbol_set_frag (last_label_seen, frag_now);
14270 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
14271 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC
14272 }
14273
c19d1205
ZW
14274 memset (&inst, '\0', sizeof (inst));
14275 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 14276
c19d1205
ZW
14277 opcode = opcode_lookup (&p);
14278 if (!opcode)
b99bd4ef 14279 {
c19d1205 14280 /* It wasn't an instruction, but it might be a register alias of
dcbf9037
JB
14281 the form alias .req reg, or a Neon .dn/.qn directive. */
14282 if (!create_register_alias (str, p)
14283 && !create_neon_reg_alias (str, p))
c19d1205 14284 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 14285
b99bd4ef
NC
14286 return;
14287 }
14288
088fa78e
KH
14289 if (opcode->tag == OT_cinfix3_deprecated)
14290 as_warn (_("s suffix on comparison instruction is deprecated"));
14291
037e8744
JB
14292 /* The value which unconditional instructions should have in place of the
14293 condition field. */
14294 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
14295
c19d1205 14296 if (thumb_mode)
b99bd4ef 14297 {
e74cfd16 14298 arm_feature_set variant;
8f06b2d8
PB
14299
14300 variant = cpu_variant;
14301 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB
14302 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
14303 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 14304 /* Check that this instruction is supported for this CPU. */
62b3e311
PB
14305 if (!opcode->tvariant
14306 || (thumb_mode == 1
14307 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 14308 {
c19d1205 14309 as_bad (_("selected processor does not support `%s'"), str);
b99bd4ef
NC
14310 return;
14311 }
c19d1205
ZW
14312 if (inst.cond != COND_ALWAYS && !unified_syntax
14313 && opcode->tencode != do_t_branch)
b99bd4ef 14314 {
c19d1205 14315 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC
14316 return;
14317 }
14318
076d447c
PB
14319 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
14320 {
14321 /* Implicit require narrow instructions on Thumb-1. This avoids
14322 relaxation accidentally introducing Thumb-2 instructions. */
7e806470
PB
14323 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
14324 && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
076d447c
PB
14325 inst.size_req = 2;
14326 }
14327
e27ec89e
PB
14328 /* Check conditional suffixes. */
14329 if (current_it_mask)
14330 {
14331 int cond;
14332 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
dfa9f0d5
PB
14333 current_it_mask <<= 1;
14334 current_it_mask &= 0x1f;
14335 /* The BKPT instruction is unconditional even in an IT block. */
14336 if (!inst.error
14337 && cond != inst.cond && opcode->tencode != do_t_bkpt)
e27ec89e
PB
14338 {
14339 as_bad (_("incorrect condition in IT block"));
14340 return;
14341 }
e27ec89e
PB
14342 }
14343 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
14344 {
6decc662 14345 as_bad (_("thumb conditional instruction not in IT block"));
e27ec89e
PB
14346 return;
14347 }
14348
c19d1205
ZW
14349 mapping_state (MAP_THUMB);
14350 inst.instruction = opcode->tvalue;
14351
14352 if (!parse_operands (p, opcode->operands))
14353 opcode->tencode ();
14354
e27ec89e
PB
14355 /* Clear current_it_mask at the end of an IT block. */
14356 if (current_it_mask == 0x10)
14357 current_it_mask = 0;
14358
0110f2b8 14359 if (!(inst.error || inst.relax))
b99bd4ef 14360 {
c19d1205
ZW
14361 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
14362 inst.size = (inst.instruction > 0xffff ? 4 : 2);
14363 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 14364 {
c19d1205 14365 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC
14366 return;
14367 }
14368 }
076d447c
PB
14369
14370 /* Something has gone badly wrong if we try to relax a fixed size
14371 instruction. */
14372 assert (inst.size_req == 0 || !inst.relax);
14373
e74cfd16
PB
14374 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14375 *opcode->tvariant);
ee065d83 14376 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
708587a4 14377 set those bits when Thumb-2 32-bit instructions are seen. ie.
7e806470 14378 anything other than bl/blx and v6-M instructions.
ee065d83 14379 This is overly pessimistic for relaxable instructions. */
7e806470
PB
14380 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
14381 || inst.relax)
14382 && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
e74cfd16
PB
14383 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14384 arm_ext_v6t2);
c19d1205 14385 }
3e9e4fcf 14386 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 14387 {
845b51d6
PB
14388 bfd_boolean is_bx;
14389
14390 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14391 is_bx = (opcode->aencode == do_bx);
14392
c19d1205 14393 /* Check that this instruction is supported for this CPU. */
845b51d6
PB
14394 if (!(is_bx && fix_v4bx)
14395 && !(opcode->avariant &&
14396 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 14397 {
c19d1205
ZW
14398 as_bad (_("selected processor does not support `%s'"), str);
14399 return;
b99bd4ef 14400 }
c19d1205 14401 if (inst.size_req)
b99bd4ef 14402 {
c19d1205
ZW
14403 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
14404 return;
b99bd4ef
NC
14405 }
14406
c19d1205
ZW
14407 mapping_state (MAP_ARM);
14408 inst.instruction = opcode->avalue;
14409 if (opcode->tag == OT_unconditionalF)
14410 inst.instruction |= 0xF << 28;
14411 else
14412 inst.instruction |= inst.cond << 28;
14413 inst.size = INSN_SIZE;
14414 if (!parse_operands (p, opcode->operands))
14415 opcode->aencode ();
ee065d83
PB
14416 /* Arm mode bx is marked as both v4T and v5 because it's still required
14417 on a hypothetical non-thumb v5 core. */
845b51d6 14418 if (is_bx)
e74cfd16 14419 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 14420 else
e74cfd16
PB
14421 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
14422 *opcode->avariant);
b99bd4ef 14423 }
3e9e4fcf
JB
14424 else
14425 {
14426 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14427 "-- `%s'"), str);
14428 return;
14429 }
c19d1205
ZW
14430 output_inst (str);
14431}
b99bd4ef 14432
c19d1205
ZW
14433/* Various frobbings of labels and their addresses. */
14434
14435void
14436arm_start_line_hook (void)
14437{
14438 last_label_seen = NULL;
b99bd4ef
NC
14439}
14440
c19d1205
ZW
14441void
14442arm_frob_label (symbolS * sym)
b99bd4ef 14443{
c19d1205 14444 last_label_seen = sym;
b99bd4ef 14445
c19d1205 14446 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 14447
c19d1205
ZW
14448#if defined OBJ_COFF || defined OBJ_ELF
14449 ARM_SET_INTERWORK (sym, support_interwork);
14450#endif
b99bd4ef 14451
5f4273c7 14452 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW
14453 as Thumb functions. This is because these labels, whilst
14454 they exist inside Thumb code, are not the entry points for
14455 possible ARM->Thumb calls. Also, these labels can be used
14456 as part of a computed goto or switch statement. eg gcc
14457 can generate code that looks like this:
b99bd4ef 14458
c19d1205
ZW
14459 ldr r2, [pc, .Laaa]
14460 lsl r3, r3, #2
14461 ldr r2, [r3, r2]
14462 mov pc, r2
b99bd4ef 14463
c19d1205
ZW
14464 .Lbbb: .word .Lxxx
14465 .Lccc: .word .Lyyy
14466 ..etc...
14467 .Laaa: .word Lbbb
b99bd4ef 14468
c19d1205
ZW
14469 The first instruction loads the address of the jump table.
14470 The second instruction converts a table index into a byte offset.
14471 The third instruction gets the jump address out of the table.
14472 The fourth instruction performs the jump.
b99bd4ef 14473
c19d1205
ZW
14474 If the address stored at .Laaa is that of a symbol which has the
14475 Thumb_Func bit set, then the linker will arrange for this address
14476 to have the bottom bit set, which in turn would mean that the
14477 address computation performed by the third instruction would end
14478 up with the bottom bit set. Since the ARM is capable of unaligned
14479 word loads, the instruction would then load the incorrect address
14480 out of the jump table, and chaos would ensue. */
14481 if (label_is_thumb_function_name
14482 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
14483 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 14484 {
c19d1205
ZW
14485 /* When the address of a Thumb function is taken the bottom
14486 bit of that address should be set. This will allow
14487 interworking between Arm and Thumb functions to work
14488 correctly. */
b99bd4ef 14489
c19d1205 14490 THUMB_SET_FUNC (sym, 1);
b99bd4ef 14491
c19d1205 14492 label_is_thumb_function_name = FALSE;
b99bd4ef 14493 }
07a53e5c 14494
07a53e5c 14495 dwarf2_emit_label (sym);
b99bd4ef
NC
14496}
14497
c19d1205
ZW
14498int
14499arm_data_in_code (void)
b99bd4ef 14500{
c19d1205 14501 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 14502 {
c19d1205
ZW
14503 *input_line_pointer = '/';
14504 input_line_pointer += 5;
14505 *input_line_pointer = 0;
14506 return 1;
b99bd4ef
NC
14507 }
14508
c19d1205 14509 return 0;
b99bd4ef
NC
14510}
14511
c19d1205
ZW
14512char *
14513arm_canonicalize_symbol_name (char * name)
b99bd4ef 14514{
c19d1205 14515 int len;
b99bd4ef 14516
c19d1205
ZW
14517 if (thumb_mode && (len = strlen (name)) > 5
14518 && streq (name + len - 5, "/data"))
14519 *(name + len - 5) = 0;
b99bd4ef 14520
c19d1205 14521 return name;
b99bd4ef 14522}
c19d1205
ZW
14523\f
14524/* Table of all register names defined by default. The user can
14525 define additional names with .req. Note that all register names
14526 should appear in both upper and lowercase variants. Some registers
14527 also have mixed-case names. */
b99bd4ef 14528
dcbf9037 14529#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 14530#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 14531#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW
14532#define REGSET(p,t) \
14533 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14534 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14535 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14536 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB
14537#define REGSETH(p,t) \
14538 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14539 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14540 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14541 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14542#define REGSET2(p,t) \
14543 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14544 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14545 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14546 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
7ed4c4c5 14547
c19d1205 14548static const struct reg_entry reg_names[] =
7ed4c4c5 14549{
c19d1205
ZW
14550 /* ARM integer registers. */
14551 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 14552
c19d1205
ZW
14553 /* ATPCS synonyms. */
14554 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
14555 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
14556 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 14557
c19d1205
ZW
14558 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
14559 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
14560 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 14561
c19d1205
ZW
14562 /* Well-known aliases. */
14563 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
14564 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
14565
14566 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
14567 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
14568
14569 /* Coprocessor numbers. */
14570 REGSET(p, CP), REGSET(P, CP),
14571
14572 /* Coprocessor register numbers. The "cr" variants are for backward
14573 compatibility. */
14574 REGSET(c, CN), REGSET(C, CN),
14575 REGSET(cr, CN), REGSET(CR, CN),
14576
14577 /* FPA registers. */
14578 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
14579 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
14580
14581 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
14582 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
14583
14584 /* VFP SP registers. */
5287ad62
JB
14585 REGSET(s,VFS), REGSET(S,VFS),
14586 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW
14587
14588 /* VFP DP Registers. */
5287ad62
JB
14589 REGSET(d,VFD), REGSET(D,VFD),
14590 /* Extra Neon DP registers. */
14591 REGSETH(d,VFD), REGSETH(D,VFD),
14592
14593 /* Neon QP registers. */
14594 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW
14595
14596 /* VFP control registers. */
14597 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
14598 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB
14599 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
14600 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
14601 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
14602 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
c19d1205
ZW
14603
14604 /* Maverick DSP coprocessor registers. */
14605 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
14606 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
14607
14608 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
14609 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
14610 REGDEF(dspsc,0,DSPSC),
14611
14612 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
14613 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
14614 REGDEF(DSPSC,0,DSPSC),
14615
14616 /* iWMMXt data registers - p0, c0-15. */
14617 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
14618
14619 /* iWMMXt control registers - p1, c0-3. */
14620 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
14621 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
14622 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
14623 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
14624
14625 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14626 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
14627 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
14628 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
14629 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
14630
14631 /* XScale accumulator registers. */
14632 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
14633};
14634#undef REGDEF
14635#undef REGNUM
14636#undef REGSET
7ed4c4c5 14637
c19d1205
ZW
14638/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14639 within psr_required_here. */
14640static const struct asm_psr psrs[] =
14641{
14642 /* Backward compatibility notation. Note that "all" is no longer
14643 truly all possible PSR bits. */
14644 {"all", PSR_c | PSR_f},
14645 {"flg", PSR_f},
14646 {"ctl", PSR_c},
14647
14648 /* Individual flags. */
14649 {"f", PSR_f},
14650 {"c", PSR_c},
14651 {"x", PSR_x},
14652 {"s", PSR_s},
14653 /* Combinations of flags. */
14654 {"fs", PSR_f | PSR_s},
14655 {"fx", PSR_f | PSR_x},
14656 {"fc", PSR_f | PSR_c},
14657 {"sf", PSR_s | PSR_f},
14658 {"sx", PSR_s | PSR_x},
14659 {"sc", PSR_s | PSR_c},
14660 {"xf", PSR_x | PSR_f},
14661 {"xs", PSR_x | PSR_s},
14662 {"xc", PSR_x | PSR_c},
14663 {"cf", PSR_c | PSR_f},
14664 {"cs", PSR_c | PSR_s},
14665 {"cx", PSR_c | PSR_x},
14666 {"fsx", PSR_f | PSR_s | PSR_x},
14667 {"fsc", PSR_f | PSR_s | PSR_c},
14668 {"fxs", PSR_f | PSR_x | PSR_s},
14669 {"fxc", PSR_f | PSR_x | PSR_c},
14670 {"fcs", PSR_f | PSR_c | PSR_s},
14671 {"fcx", PSR_f | PSR_c | PSR_x},
14672 {"sfx", PSR_s | PSR_f | PSR_x},
14673 {"sfc", PSR_s | PSR_f | PSR_c},
14674 {"sxf", PSR_s | PSR_x | PSR_f},
14675 {"sxc", PSR_s | PSR_x | PSR_c},
14676 {"scf", PSR_s | PSR_c | PSR_f},
14677 {"scx", PSR_s | PSR_c | PSR_x},
14678 {"xfs", PSR_x | PSR_f | PSR_s},
14679 {"xfc", PSR_x | PSR_f | PSR_c},
14680 {"xsf", PSR_x | PSR_s | PSR_f},
14681 {"xsc", PSR_x | PSR_s | PSR_c},
14682 {"xcf", PSR_x | PSR_c | PSR_f},
14683 {"xcs", PSR_x | PSR_c | PSR_s},
14684 {"cfs", PSR_c | PSR_f | PSR_s},
14685 {"cfx", PSR_c | PSR_f | PSR_x},
14686 {"csf", PSR_c | PSR_s | PSR_f},
14687 {"csx", PSR_c | PSR_s | PSR_x},
14688 {"cxf", PSR_c | PSR_x | PSR_f},
14689 {"cxs", PSR_c | PSR_x | PSR_s},
14690 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
14691 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
14692 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
14693 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
14694 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
14695 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
14696 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
14697 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
14698 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
14699 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
14700 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
14701 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
14702 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
14703 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
14704 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
14705 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
14706 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
14707 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
14708 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
14709 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
14710 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
14711 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
14712 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
14713 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
14714};
14715
62b3e311
PB
14716/* Table of V7M psr names. */
14717static const struct asm_psr v7m_psrs[] =
14718{
2b744c99
PB
14719 {"apsr", 0 }, {"APSR", 0 },
14720 {"iapsr", 1 }, {"IAPSR", 1 },
14721 {"eapsr", 2 }, {"EAPSR", 2 },
14722 {"psr", 3 }, {"PSR", 3 },
14723 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14724 {"ipsr", 5 }, {"IPSR", 5 },
14725 {"epsr", 6 }, {"EPSR", 6 },
14726 {"iepsr", 7 }, {"IEPSR", 7 },
14727 {"msp", 8 }, {"MSP", 8 },
14728 {"psp", 9 }, {"PSP", 9 },
14729 {"primask", 16}, {"PRIMASK", 16},
14730 {"basepri", 17}, {"BASEPRI", 17},
14731 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14732 {"faultmask", 19}, {"FAULTMASK", 19},
14733 {"control", 20}, {"CONTROL", 20}
62b3e311
PB
14734};
14735
c19d1205
ZW
14736/* Table of all shift-in-operand names. */
14737static const struct asm_shift_name shift_names [] =
b99bd4ef 14738{
c19d1205
ZW
14739 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
14740 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
14741 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
14742 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
14743 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
14744 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
14745};
b99bd4ef 14746
c19d1205
ZW
14747/* Table of all explicit relocation names. */
14748#ifdef OBJ_ELF
14749static struct reloc_entry reloc_names[] =
14750{
14751 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
14752 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
14753 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
14754 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
14755 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
14756 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
14757 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
14758 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
14759 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
14760 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
14761 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
14762};
14763#endif
b99bd4ef 14764
c19d1205
ZW
14765/* Table of all conditional affixes. 0xF is not defined as a condition code. */
14766static const struct asm_cond conds[] =
14767{
14768 {"eq", 0x0},
14769 {"ne", 0x1},
14770 {"cs", 0x2}, {"hs", 0x2},
14771 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14772 {"mi", 0x4},
14773 {"pl", 0x5},
14774 {"vs", 0x6},
14775 {"vc", 0x7},
14776 {"hi", 0x8},
14777 {"ls", 0x9},
14778 {"ge", 0xa},
14779 {"lt", 0xb},
14780 {"gt", 0xc},
14781 {"le", 0xd},
14782 {"al", 0xe}
14783};
bfae80f2 14784
62b3e311
PB
14785static struct asm_barrier_opt barrier_opt_names[] =
14786{
14787 { "sy", 0xf },
14788 { "un", 0x7 },
14789 { "st", 0xe },
14790 { "unst", 0x6 }
14791};
14792
c19d1205
ZW
14793/* Table of ARM-format instructions. */
14794
14795/* Macros for gluing together operand strings. N.B. In all cases
14796 other than OPS0, the trailing OP_stop comes from default
14797 zero-initialization of the unspecified elements of the array. */
14798#define OPS0() { OP_stop, }
14799#define OPS1(a) { OP_##a, }
14800#define OPS2(a,b) { OP_##a,OP_##b, }
14801#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14802#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14803#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14804#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14805
14806/* These macros abstract out the exact format of the mnemonic table and
14807 save some repeated characters. */
14808
14809/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14810#define TxCE(mnem, op, top, nops, ops, ae, te) \
14811 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
1887dd22 14812 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
14813
14814/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14815 a T_MNEM_xyz enumerator. */
14816#define TCE(mnem, aop, top, nops, ops, ae, te) \
14817 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14818#define tCE(mnem, aop, top, nops, ops, ae, te) \
14819 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14820
14821/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14822 infix after the third character. */
14823#define TxC3(mnem, op, top, nops, ops, ae, te) \
14824 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
1887dd22 14825 THUMB_VARIANT, do_##ae, do_##te }
088fa78e
KH
14826#define TxC3w(mnem, op, top, nops, ops, ae, te) \
14827 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14828 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
14829#define TC3(mnem, aop, top, nops, ops, ae, te) \
14830 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e
KH
14831#define TC3w(mnem, aop, top, nops, ops, ae, te) \
14832 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205
ZW
14833#define tC3(mnem, aop, top, nops, ops, ae, te) \
14834 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
088fa78e
KH
14835#define tC3w(mnem, aop, top, nops, ops, ae, te) \
14836 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
c19d1205
ZW
14837
14838/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14839 appear in the condition table. */
14840#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14841 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
1887dd22 14842 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
14843
14844#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14845 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14846 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14847 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14848 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14849 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14850 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14851 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14852 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14853 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14854 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14855 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14856 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14857 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14858 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14859 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14860 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14861 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14862 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14863 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14864
14865#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14866 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14867#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14868 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14869
14870/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB
14871 field is still 0xE. Many of the Thumb variants can be executed
14872 conditionally, so this is checked separately. */
c19d1205
ZW
14873#define TUE(mnem, op, top, nops, ops, ae, te) \
14874 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 14875 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
14876
14877/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14878 condition code field. */
14879#define TUF(mnem, op, top, nops, ops, ae, te) \
14880 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 14881 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW
14882
14883/* ARM-only variants of all the above. */
6a86118a
NC
14884#define CE(mnem, op, nops, ops, ae) \
14885 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14886
14887#define C3(mnem, op, nops, ops, ae) \
14888 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14889
e3cb604e
PB
14890/* Legacy mnemonics that always have conditional infix after the third
14891 character. */
14892#define CL(mnem, op, nops, ops, ae) \
14893 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14894 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14895
8f06b2d8
PB
14896/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14897#define cCE(mnem, op, nops, ops, ae) \
14898 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14899
e3cb604e
PB
14900/* Legacy coprocessor instructions where conditional infix and conditional
14901 suffix are ambiguous. For consistency this includes all FPA instructions,
14902 not just the potentially ambiguous ones. */
14903#define cCL(mnem, op, nops, ops, ae) \
14904 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14905 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14906
14907/* Coprocessor, takes either a suffix or a position-3 infix
14908 (for an FPA corner case). */
14909#define C3E(mnem, op, nops, ops, ae) \
14910 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14911 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 14912
6a86118a
NC
14913#define xCM_(m1, m2, m3, op, nops, ops, ae) \
14914 { #m1 #m2 #m3, OPS##nops ops, \
14915 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14916 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14917
14918#define CM(m1, m2, op, nops, ops, ae) \
14919 xCM_(m1, , m2, op, nops, ops, ae), \
14920 xCM_(m1, eq, m2, op, nops, ops, ae), \
14921 xCM_(m1, ne, m2, op, nops, ops, ae), \
14922 xCM_(m1, cs, m2, op, nops, ops, ae), \
14923 xCM_(m1, hs, m2, op, nops, ops, ae), \
14924 xCM_(m1, cc, m2, op, nops, ops, ae), \
14925 xCM_(m1, ul, m2, op, nops, ops, ae), \
14926 xCM_(m1, lo, m2, op, nops, ops, ae), \
14927 xCM_(m1, mi, m2, op, nops, ops, ae), \
14928 xCM_(m1, pl, m2, op, nops, ops, ae), \
14929 xCM_(m1, vs, m2, op, nops, ops, ae), \
14930 xCM_(m1, vc, m2, op, nops, ops, ae), \
14931 xCM_(m1, hi, m2, op, nops, ops, ae), \
14932 xCM_(m1, ls, m2, op, nops, ops, ae), \
14933 xCM_(m1, ge, m2, op, nops, ops, ae), \
14934 xCM_(m1, lt, m2, op, nops, ops, ae), \
14935 xCM_(m1, gt, m2, op, nops, ops, ae), \
14936 xCM_(m1, le, m2, op, nops, ops, ae), \
14937 xCM_(m1, al, m2, op, nops, ops, ae)
14938
14939#define UE(mnem, op, nops, ops, ae) \
14940 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14941
14942#define UF(mnem, op, nops, ops, ae) \
14943 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14944
5287ad62
JB
14945/* Neon data-processing. ARM versions are unconditional with cond=0xf.
14946 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14947 use the same encoding function for each. */
14948#define NUF(mnem, op, nops, ops, enc) \
14949 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14950 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14951
14952/* Neon data processing, version which indirects through neon_enc_tab for
14953 the various overloaded versions of opcodes. */
14954#define nUF(mnem, op, nops, ops, enc) \
14955 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14956 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14957
14958/* Neon insn with conditional suffix for the ARM version, non-overloaded
14959 version. */
037e8744
JB
14960#define NCE_tag(mnem, op, nops, ops, enc, tag) \
14961 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5287ad62
JB
14962 THUMB_VARIANT, do_##enc, do_##enc }
14963
037e8744
JB
14964#define NCE(mnem, op, nops, ops, enc) \
14965 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14966
14967#define NCEF(mnem, op, nops, ops, enc) \
14968 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14969
5287ad62 14970/* Neon insn with conditional suffix for the ARM version, overloaded types. */
037e8744
JB
14971#define nCE_tag(mnem, op, nops, ops, enc, tag) \
14972 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
5287ad62
JB
14973 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14974
037e8744
JB
14975#define nCE(mnem, op, nops, ops, enc) \
14976 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14977
14978#define nCEF(mnem, op, nops, ops, enc) \
14979 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14980
c19d1205
ZW
14981#define do_0 0
14982
14983/* Thumb-only, unconditional. */
14984#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14985
c19d1205 14986static const struct asm_opcode insns[] =
bfae80f2 14987{
e74cfd16
PB
14988#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14989#define THUMB_VARIANT &arm_ext_v4t
c19d1205
ZW
14990 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
14991 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
14992 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
14993 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
14994 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
14995 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
4962c51a
MS
14996 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub),
14997 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub),
c19d1205
ZW
14998 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
14999 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
15000 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
15001 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
15002 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
15003 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
15004 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
15005 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
15006
15007 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15008 for setting PSR flag bits. They are obsolete in V6 and do not
15009 have Thumb equivalents. */
15010 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
088fa78e 15011 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
e3cb604e 15012 CL(tstp, 110f000, 2, (RR, SH), cmp),
c19d1205 15013 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
088fa78e 15014 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
e3cb604e 15015 CL(cmpp, 150f000, 2, (RR, SH), cmp),
c19d1205 15016 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
088fa78e 15017 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
e3cb604e 15018 CL(cmnp, 170f000, 2, (RR, SH), cmp),
c19d1205
ZW
15019
15020 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
15021 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
15022 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
15023 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
15024
4962c51a
MS
15025 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
15026 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst),
15027 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst),
15028 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst),
c19d1205 15029
f5208ef2 15030 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW
15031 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15032 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
f5208ef2 15033 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW
15034 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15035 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15036
15037 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
c16d2bf0 15038 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi),
0110f2b8 15039 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
39b41c9c 15040 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 15041
c19d1205 15042 /* Pseudo ops. */
e9f89963 15043 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac
ZW
15044 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
15045 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
c19d1205
ZW
15046
15047 /* Thumb-compatibility pseudo ops. */
15048 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
15049 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
15050 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
15051 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
15052 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
2fc8bdac 15053 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
c19d1205
ZW
15054 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
15055 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
15056 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
15057 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
15058 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
15059 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
15060
16a4cf17
PB
15061 /* These may simplify to neg. */
15062 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
15063 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
15064
c19d1205 15065#undef THUMB_VARIANT
e74cfd16 15066#define THUMB_VARIANT &arm_ext_v6
2fc8bdac 15067 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW
15068
15069 /* V1 instructions with no Thumb analogue prior to V6T2. */
15070#undef THUMB_VARIANT
e74cfd16 15071#define THUMB_VARIANT &arm_ext_v6t2
c19d1205 15072 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
088fa78e 15073 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
e3cb604e 15074 CL(teqp, 130f000, 2, (RR, SH), cmp),
c19d1205
ZW
15075
15076 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
3e94bf1a 15077 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt),
c19d1205 15078 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
3e94bf1a 15079 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt),
c19d1205 15080
9c3c69f2
PB
15081 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15082 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 15083
9c3c69f2
PB
15084 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15085 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW
15086
15087 /* V1 instructions with no Thumb analogue at all. */
15088 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
15089 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
15090
15091 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
15092 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
15093 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
15094 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
15095 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
15096 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
15097 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
15098 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
15099
15100#undef ARM_VARIANT
e74cfd16 15101#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
c19d1205 15102#undef THUMB_VARIANT
e74cfd16 15103#define THUMB_VARIANT &arm_ext_v4t
c19d1205
ZW
15104 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
15105 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
15106
15107#undef THUMB_VARIANT
e74cfd16 15108#define THUMB_VARIANT &arm_ext_v6t2
c19d1205
ZW
15109 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15110 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
15111
15112 /* Generic coprocessor instructions. */
15113 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
4962c51a
MS
15114 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15115 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15116 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15117 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
c19d1205
ZW
15118 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15119 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15120
15121#undef ARM_VARIANT
e74cfd16 15122#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
c19d1205
ZW
15123 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15124 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15125
15126#undef ARM_VARIANT
e74cfd16 15127#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
7e806470
PB
15128#undef THUMB_VARIANT
15129#define THUMB_VARIANT &arm_ext_msr
037e8744
JB
15130 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
15131 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
c19d1205
ZW
15132
15133#undef ARM_VARIANT
e74cfd16 15134#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
7e806470
PB
15135#undef THUMB_VARIANT
15136#define THUMB_VARIANT &arm_ext_v6t2
c19d1205
ZW
15137 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15138 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15139 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15140 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15141 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15142 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15143 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15144 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15145
15146#undef ARM_VARIANT
e74cfd16 15147#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
c19d1205 15148#undef THUMB_VARIANT
e74cfd16 15149#define THUMB_VARIANT &arm_ext_v4t
4962c51a
MS
15150 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15151 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15152 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15153 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15154 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15155 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
c19d1205
ZW
15156
15157#undef ARM_VARIANT
e74cfd16 15158#define ARM_VARIANT &arm_ext_v4t_5
c19d1205
ZW
15159 /* ARM Architecture 4T. */
15160 /* Note: bx (and blx) are required on V5, even if the processor does
15161 not support Thumb. */
15162 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
15163
15164#undef ARM_VARIANT
e74cfd16 15165#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
c19d1205 15166#undef THUMB_VARIANT
e74cfd16 15167#define THUMB_VARIANT &arm_ext_v5t
c19d1205
ZW
15168 /* Note: blx has 2 variants; the .value coded here is for
15169 BLX(2). Only this variant has conditional execution. */
15170 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
15171 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
15172
15173#undef THUMB_VARIANT
e74cfd16 15174#define THUMB_VARIANT &arm_ext_v6t2
c19d1205 15175 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
4962c51a
MS
15176 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15177 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15178 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15179 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
c19d1205
ZW
15180 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15181 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15182 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15183
15184#undef ARM_VARIANT
e74cfd16 15185#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
c19d1205
ZW
15186 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15187 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15188 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15189 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15190
15191 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15192 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15193
15194 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15195 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15196 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15197 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15198
15199 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15200 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15201 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15202 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15203
15204 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15205 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15206
15207 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15208 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15209 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15210 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15211
15212#undef ARM_VARIANT
e74cfd16 15213#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
c19d1205 15214 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
79d49516
PB
15215 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15216 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
c19d1205
ZW
15217
15218 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15219 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15220
15221#undef ARM_VARIANT
e74cfd16 15222#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
c19d1205
ZW
15223 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
15224
15225#undef ARM_VARIANT
e74cfd16 15226#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
c19d1205 15227#undef THUMB_VARIANT
e74cfd16 15228#define THUMB_VARIANT &arm_ext_v6
c19d1205
ZW
15229 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
15230 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
15231 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15232 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15233 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15234 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15235 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15236 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15237 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15238 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
15239
15240#undef THUMB_VARIANT
e74cfd16 15241#define THUMB_VARIANT &arm_ext_v6t2
c19d1205 15242 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
91568d08 15243 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
c19d1205
ZW
15244 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15245 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311
PB
15246
15247 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
15248 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
15249
15250/* ARM V6 not included in V7M (eg. integer SIMD). */
15251#undef THUMB_VARIANT
15252#define THUMB_VARIANT &arm_ext_v6_notm
dfa9f0d5 15253 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps),
c19d1205
ZW
15254 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
15255 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
15256 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15257 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15258 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15259 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15260 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15261 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15262 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15263 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15264 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15265 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15266 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15267 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15268 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15269 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15270 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15271 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15272 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15273 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15274 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15275 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15276 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15277 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15278 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15279 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15280 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15281 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15282 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15283 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15284 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15285 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15286 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15287 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15288 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15289 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15290 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15291 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15292 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15293 UF(rfeib, 9900a00, 1, (RRw), rfe),
15294 UF(rfeda, 8100a00, 1, (RRw), rfe),
15295 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15296 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15297 UF(rfefa, 9900a00, 1, (RRw), rfe),
15298 UF(rfeea, 8100a00, 1, (RRw), rfe),
15299 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15300 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15301 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15302 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15303 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15304 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15305 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15306 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15307 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
f1022c90 15308 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
c19d1205
ZW
15309 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15310 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15311 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15312 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15313 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15314 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15315 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15316 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15317 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15318 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15319 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15320 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15321 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15322 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15323 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15324 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15325 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15326 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
b6702015
PB
15327 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
15328 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
15329 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
15330 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
c19d1205 15331 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
c19d1205
ZW
15332 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
15333 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15334 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
c19d1205
ZW
15335 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
15336
15337#undef ARM_VARIANT
e74cfd16 15338#define ARM_VARIANT &arm_ext_v6k
c19d1205 15339#undef THUMB_VARIANT
e74cfd16 15340#define THUMB_VARIANT &arm_ext_v6k
c19d1205
ZW
15341 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
15342 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
15343 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
15344 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
15345
ebdca51a
PB
15346#undef THUMB_VARIANT
15347#define THUMB_VARIANT &arm_ext_v6_notm
15348 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
15349 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
15350
c19d1205 15351#undef THUMB_VARIANT
e74cfd16 15352#define THUMB_VARIANT &arm_ext_v6t2
c19d1205
ZW
15353 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15354 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
c19d1205
ZW
15355 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15356 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
c19d1205
ZW
15357 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
15358
15359#undef ARM_VARIANT
e74cfd16 15360#define ARM_VARIANT &arm_ext_v6z
3eb17e6b 15361 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205
ZW
15362
15363#undef ARM_VARIANT
e74cfd16 15364#define ARM_VARIANT &arm_ext_v6t2
c19d1205
ZW
15365 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
15366 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
15367 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15368 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15369
15370 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
b6895b4f
PB
15371 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
15372 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
401a54cf 15373 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205
ZW
15374
15375 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15376 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15377 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15378 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15379
25fe350b
MS
15380 UT(cbnz, b900, 2, (RR, EXP), t_cbz),
15381 UT(cbz, b100, 2, (RR, EXP), t_cbz),
f91e006c
PB
15382 /* ARM does not really have an IT instruction, so always allow it. */
15383#undef ARM_VARIANT
15384#define ARM_VARIANT &arm_ext_v1
c19d1205
ZW
15385 TUE(it, 0, bf08, 1, (COND), it, t_it),
15386 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
15387 TUE(ite, 0, bf04, 1, (COND), it, t_it),
15388 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
15389 TUE(itet, 0, bf06, 1, (COND), it, t_it),
15390 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
15391 TUE(itee, 0, bf02, 1, (COND), it, t_it),
15392 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
15393 TUE(itett, 0, bf07, 1, (COND), it, t_it),
15394 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
15395 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
15396 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
15397 TUE(itete, 0, bf05, 1, (COND), it, t_it),
15398 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
15399 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
15400
92e90b6e
PB
15401 /* Thumb2 only instructions. */
15402#undef ARM_VARIANT
e74cfd16 15403#define ARM_VARIANT NULL
92e90b6e
PB
15404
15405 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15406 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15407 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
15408 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
15409
62b3e311
PB
15410 /* Thumb-2 hardware division instructions (R and M profiles only). */
15411#undef THUMB_VARIANT
15412#define THUMB_VARIANT &arm_ext_div
15413 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
15414 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
15415
7e806470
PB
15416 /* ARM V6M/V7 instructions. */
15417#undef ARM_VARIANT
15418#define ARM_VARIANT &arm_ext_barrier
15419#undef THUMB_VARIANT
15420#define THUMB_VARIANT &arm_ext_barrier
15421 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
15422 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
15423 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
15424
62b3e311
PB
15425 /* ARM V7 instructions. */
15426#undef ARM_VARIANT
15427#define ARM_VARIANT &arm_ext_v7
15428#undef THUMB_VARIANT
15429#define THUMB_VARIANT &arm_ext_v7
15430 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
15431 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 15432
c19d1205 15433#undef ARM_VARIANT
e74cfd16 15434#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
8f06b2d8
PB
15435 cCE(wfs, e200110, 1, (RR), rd),
15436 cCE(rfs, e300110, 1, (RR), rd),
15437 cCE(wfc, e400110, 1, (RR), rd),
15438 cCE(rfc, e500110, 1, (RR), rd),
15439
4962c51a
MS
15440 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
15441 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
15442 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
15443 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
e3cb604e 15444
4962c51a
MS
15445 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
15446 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
15447 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
15448 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
e3cb604e
PB
15449
15450 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
15451 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
15452 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
15453 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
15454 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
15455 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
15456 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
15457 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
15458 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
15459 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
15460 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
15461 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
15462
15463 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
15464 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
15465 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
15466 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
15467 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
15468 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
15469 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
15470 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
15471 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
15472 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
15473 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
15474 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
15475
15476 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
15477 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
15478 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
15479 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
15480 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
15481 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
15482 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
15483 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
15484 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
15485 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
15486 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
15487 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
15488
15489 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
15490 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
15491 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
15492 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
15493 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
15494 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
15495 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
15496 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
15497 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
15498 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
15499 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
15500 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
15501
15502 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
15503 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
15504 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
15505 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
15506 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
15507 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
15508 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
15509 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
15510 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
15511 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
15512 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
15513 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
15514
15515 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
15516 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
15517 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
15518 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
15519 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
15520 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
15521 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
15522 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
15523 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
15524 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
15525 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
15526 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
15527
15528 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
15529 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
15530 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
15531 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
15532 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
15533 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
15534 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
15535 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
15536 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
15537 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
15538 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
15539 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
15540
15541 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
15542 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
15543 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
15544 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
15545 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
15546 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
15547 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
15548 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
15549 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
15550 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
15551 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
15552 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
15553
15554 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
15555 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
15556 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
15557 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
15558 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
15559 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
15560 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
15561 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
15562 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
15563 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
15564 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
15565 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
15566
15567 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
15568 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
15569 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
15570 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
15571 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
15572 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
15573 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
15574 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
15575 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
15576 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
15577 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
15578 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
15579
15580 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
15581 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
15582 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
15583 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
15584 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
15585 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
15586 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
15587 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
15588 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
15589 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
15590 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
15591 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
15592
15593 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
15594 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
15595 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
15596 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
15597 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
15598 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
15599 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
15600 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
15601 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
15602 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
15603 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
15604 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
15605
15606 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
15607 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
15608 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
15609 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
15610 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
15611 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
15612 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
15613 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
15614 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
15615 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
15616 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
15617 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
15618
15619 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
15620 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
15621 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
15622 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
15623 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
15624 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
15625 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
15626 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
15627 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
15628 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
15629 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
15630 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
15631
15632 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
15633 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
15634 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
15635 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
15636 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
15637 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
15638 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
15639 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
15640 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
15641 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
15642 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
15643 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
15644
15645 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
15646 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
15647 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
15648 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
15649 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
15650 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
15651 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
15652 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
15653 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
15654 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
15655 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
15656 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
15657
15658 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
15659 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
15660 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
15661 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
15662 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
15663 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15664 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15665 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15666 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
15667 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
15668 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
15669 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
15670
15671 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
15672 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
15673 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
15674 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
15675 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
15676 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15677 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15678 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15679 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
15680 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
15681 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
15682 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
15683
15684 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
15685 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
15686 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
15687 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
15688 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
15689 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15690 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15691 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15692 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
15693 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
15694 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
15695 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
15696
15697 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
15698 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
15699 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
15700 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
15701 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
15702 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15703 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15704 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15705 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
15706 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
15707 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
15708 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
15709
15710 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
15711 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
15712 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
15713 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
15714 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
15715 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15716 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15717 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15718 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
15719 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
15720 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
15721 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
15722
15723 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
15724 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
15725 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
15726 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
15727 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
15728 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15729 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15730 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15731 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
15732 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
15733 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
15734 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
15735
15736 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
15737 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
15738 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
15739 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
15740 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
15741 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15742 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15743 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15744 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
15745 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
15746 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
15747 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
15748
15749 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
15750 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
15751 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
15752 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
15753 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
15754 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15755 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15756 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15757 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
15758 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
15759 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
15760 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
15761
15762 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
15763 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
15764 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
15765 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
15766 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
15767 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15768 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15769 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15770 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
15771 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
15772 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
15773 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
15774
15775 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
15776 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
15777 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
15778 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
15779 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
15780 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15781 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15782 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15783 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
15784 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
15785 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
15786 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
15787
15788 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15789 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15790 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15791 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15792 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15793 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15794 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15795 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15796 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15797 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15798 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15799 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15800
15801 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15802 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15803 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15804 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15805 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15806 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15807 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15808 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15809 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15810 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15811 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15812 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15813
15814 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15815 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15816 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15817 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15818 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15819 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15820 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15821 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15822 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15823 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15824 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15825 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8f06b2d8
PB
15826
15827 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
c19d1205 15828 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
8f06b2d8 15829 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
c19d1205
ZW
15830 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
15831
e3cb604e
PB
15832 cCL(flts, e000110, 2, (RF, RR), rn_rd),
15833 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
15834 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
15835 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
15836 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
15837 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
15838 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
15839 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
15840 cCL(flte, e080110, 2, (RF, RR), rn_rd),
15841 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
15842 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
15843 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
b99bd4ef 15844
c19d1205
ZW
15845 /* The implementation of the FIX instruction is broken on some
15846 assemblers, in that it accepts a precision specifier as well as a
15847 rounding specifier, despite the fact that this is meaningless.
15848 To be more compatible, we accept it as well, though of course it
15849 does not set any bits. */
8f06b2d8 15850 cCE(fix, e100110, 2, (RR, RF), rd_rm),
e3cb604e
PB
15851 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
15852 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
15853 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
15854 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
15855 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
15856 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
15857 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
15858 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
15859 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
15860 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
15861 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
15862 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
bfae80f2 15863
c19d1205
ZW
15864 /* Instructions that were new with the real FPA, call them V2. */
15865#undef ARM_VARIANT
e74cfd16 15866#define ARM_VARIANT &fpu_fpa_ext_v2
8f06b2d8 15867 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
e3cb604e
PB
15868 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15869 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8f06b2d8 15870 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
e3cb604e
PB
15871 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15872 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205
ZW
15873
15874#undef ARM_VARIANT
e74cfd16 15875#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
c19d1205 15876 /* Moves and type conversions. */
8f06b2d8
PB
15877 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
15878 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
15879 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
15880 cCE(fmstat, ef1fa10, 0, (), noargs),
15881 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
15882 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
15883 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
15884 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15885 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
15886 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15887 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
15888 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW
15889
15890 /* Memory operations. */
4962c51a
MS
15891 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15892 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
8f06b2d8
PB
15893 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15894 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15895 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15896 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15897 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15898 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15899 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15900 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15901 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15902 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15903 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15904 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15905 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15906 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15907 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15908 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 15909
c19d1205 15910 /* Monadic operations. */
8f06b2d8
PB
15911 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
15912 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
15913 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW
15914
15915 /* Dyadic operations. */
8f06b2d8
PB
15916 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15917 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15918 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15919 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15920 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15921 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15922 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15923 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15924 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 15925
c19d1205 15926 /* Comparisons. */
8f06b2d8
PB
15927 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
15928 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
15929 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
15930 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 15931
c19d1205 15932#undef ARM_VARIANT
e74cfd16 15933#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
c19d1205 15934 /* Moves and type conversions. */
5287ad62 15935 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
8f06b2d8
PB
15936 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15937 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
5287ad62
JB
15938 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
15939 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
15940 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
15941 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
8f06b2d8
PB
15942 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15943 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
15944 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15945 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15946 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15947 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205
ZW
15948
15949 /* Memory operations. */
4962c51a
MS
15950 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15951 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
8f06b2d8
PB
15952 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15953 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15954 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15955 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15956 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15957 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15958 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15959 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
b99bd4ef 15960
c19d1205 15961 /* Monadic operations. */
5287ad62
JB
15962 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15963 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15964 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW
15965
15966 /* Dyadic operations. */
5287ad62
JB
15967 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15968 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15969 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15970 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15971 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15972 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15973 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15974 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15975 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 15976
c19d1205 15977 /* Comparisons. */
5287ad62
JB
15978 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15979 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd),
15980 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15981 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205
ZW
15982
15983#undef ARM_VARIANT
e74cfd16 15984#define ARM_VARIANT &fpu_vfp_ext_v2
8f06b2d8
PB
15985 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
15986 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
5287ad62
JB
15987 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
15988 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
15989
037e8744
JB
15990/* Instructions which may belong to either the Neon or VFP instruction sets.
15991 Individual encoder functions perform additional architecture checks. */
15992#undef ARM_VARIANT
15993#define ARM_VARIANT &fpu_vfp_ext_v1xd
15994#undef THUMB_VARIANT
15995#define THUMB_VARIANT &fpu_vfp_ext_v1xd
15996 /* These mnemonics are unique to VFP. */
15997 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
15998 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
15999 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
16000 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
16001 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
16002 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
16003 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
16004 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
16005 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
16006 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
16007
16008 /* Mnemonics shared by Neon and VFP. */
16009 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
16010 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
16011 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
16012
16013 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
16014 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
16015
16016 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
16017 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
16018
16019 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
16020 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
16021 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
16022 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
16023 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
16024 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
4962c51a
MS
16025 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
16026 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
037e8744
JB
16027
16028 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
8e79c3df
CM
16029 nCEF(vcvtb, vcvt, 2, (RVS, RVS), neon_cvtb),
16030 nCEF(vcvtt, vcvt, 2, (RVS, RVS), neon_cvtt),
16031
037e8744
JB
16032
16033 /* NOTE: All VMOV encoding is special-cased! */
16034 NCE(vmov, 0, 1, (VMOV), neon_mov),
16035 NCE(vmovq, 0, 1, (VMOV), neon_mov),
16036
5287ad62
JB
16037#undef THUMB_VARIANT
16038#define THUMB_VARIANT &fpu_neon_ext_v1
16039#undef ARM_VARIANT
16040#define ARM_VARIANT &fpu_neon_ext_v1
16041 /* Data processing with three registers of the same length. */
16042 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16043 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
16044 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
16045 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
16046 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
16047 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
16048 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
16049 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
16050 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
16051 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16052 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
16053 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
16054 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
16055 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7
JB
16056 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
16057 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
16058 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
16059 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62
JB
16060 /* If not immediate, fall back to neon_dyadic_i64_su.
16061 shl_imm should accept I8 I16 I32 I64,
16062 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16063 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
16064 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
16065 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
16066 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
16067 /* Logic ops, types optional & ignored. */
16068 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic),
16069 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic),
16070 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic),
16071 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic),
16072 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic),
16073 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic),
16074 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic),
16075 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic),
16076 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
16077 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
16078 /* Bitfield ops, untyped. */
16079 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
16080 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
16081 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
16082 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
16083 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
16084 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
16085 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16086 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
16087 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
16088 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
16089 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
16090 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
16091 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
16092 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16093 back to neon_dyadic_if_su. */
16094 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
16095 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
16096 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
16097 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
16098 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16099 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
16100 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16101 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 16102 /* Comparison. Type I8 I16 I32 F32. */
5287ad62
JB
16103 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
16104 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
16105 /* As above, D registers only. */
16106 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
16107 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
16108 /* Int and float variants, signedness unimportant. */
5287ad62 16109 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
5287ad62
JB
16110 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
16111 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
16112 /* Add/sub take types I8 I16 I32 I64 F32. */
5287ad62 16113 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB
16114 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
16115 /* vtst takes sizes 8, 16, 32. */
16116 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
16117 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
16118 /* VMUL takes I8 I16 I32 F32 P8. */
037e8744 16119 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62
JB
16120 /* VQD{R}MULH takes S16 S32. */
16121 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16122 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
16123 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16124 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
16125 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16126 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
16127 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16128 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB
16129 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16130 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
16131 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16132 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB
16133 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
16134 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
16135 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
16136 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
16137
16138 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 16139 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB
16140 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
16141
16142 /* Data processing with two registers and a shift amount. */
16143 /* Right shifts, and variants with rounding.
16144 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16145 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16146 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
16147 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16148 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
16149 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
16150 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
16151 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
16152 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
16153 /* Shift and insert. Sizes accepted 8 16 32 64. */
16154 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
16155 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
16156 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
16157 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
16158 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16159 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
16160 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
16161 /* Right shift immediate, saturating & narrowing, with rounding variants.
16162 Types accepted S16 S32 S64 U16 U32 U64. */
16163 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16164 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16165 /* As above, unsigned. Types accepted S16 S32 S64. */
16166 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16167 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16168 /* Right shift narrowing. Types accepted I16 I32 I64. */
16169 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16170 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16171 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16172 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll),
16173 /* CVT with optional immediate for fixed-point variant. */
037e8744 16174 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 16175
5287ad62
JB
16176 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn),
16177 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn),
16178
16179 /* Data processing, three registers of different lengths. */
16180 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16181 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
16182 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
16183 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
16184 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
16185 /* If not scalar, fall back to neon_dyadic_long.
16186 Vector types as above, scalar types S16 S32 U16 U32. */
16187 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16188 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16189 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16190 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16191 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16192 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16193 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16194 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16195 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16196 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16197 /* Saturating doubling multiplies. Types S16 S32. */
16198 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16199 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16200 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16201 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16202 S16 S32 U16 U32. */
16203 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
16204
16205 /* Extract. Size 8. */
3b8d421e
PB
16206 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
16207 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB
16208
16209 /* Two registers, miscellaneous. */
16210 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16211 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
16212 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
16213 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
16214 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
16215 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
16216 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
16217 /* Vector replicate. Sizes 8 16 32. */
16218 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup),
16219 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup),
16220 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16221 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
16222 /* VMOVN. Types I16 I32 I64. */
16223 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn),
16224 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16225 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn),
16226 /* VQMOVUN. Types S16 S32 S64. */
16227 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun),
16228 /* VZIP / VUZP. Sizes 8 16 32. */
16229 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
16230 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
16231 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
16232 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
16233 /* VQABS / VQNEG. Types S8 S16 S32. */
16234 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16235 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
16236 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16237 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
16238 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16239 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
16240 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
16241 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
16242 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
16243 /* Reciprocal estimates. Types U32 F32. */
16244 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
16245 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
16246 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
16247 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
16248 /* VCLS. Types S8 S16 S32. */
16249 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
16250 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
16251 /* VCLZ. Types I8 I16 I32. */
16252 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
16253 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
16254 /* VCNT. Size 8. */
16255 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
16256 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
16257 /* Two address, untyped. */
16258 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
16259 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
16260 /* VTRN. Sizes 8 16 32. */
16261 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn),
16262 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn),
16263
16264 /* Table lookup. Size 8. */
16265 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16266 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16267
b7fc2769
JB
16268#undef THUMB_VARIANT
16269#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16270#undef ARM_VARIANT
16271#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
5287ad62
JB
16272 /* Neon element/structure load/store. */
16273 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16274 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16275 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16276 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16277 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16278 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16279 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16280 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16281
16282#undef THUMB_VARIANT
16283#define THUMB_VARIANT &fpu_vfp_ext_v3
16284#undef ARM_VARIANT
16285#define ARM_VARIANT &fpu_vfp_ext_v3
5287ad62
JB
16286 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const),
16287 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const),
16288 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16289 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16290 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16291 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16292 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16293 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16294 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16295 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16296 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16297 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16298 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16299 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16300 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16301 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16302 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16303 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 16304
5287ad62 16305#undef THUMB_VARIANT
c19d1205 16306#undef ARM_VARIANT
e74cfd16 16307#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
8f06b2d8
PB
16308 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16309 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16310 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16311 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16312 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16313 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16314 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
16315 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205
ZW
16316
16317#undef ARM_VARIANT
e74cfd16 16318#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
8f06b2d8
PB
16319 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
16320 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
16321 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
16322 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
16323 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
16324 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
16325 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
16326 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
16327 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
16328 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16329 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16330 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16331 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16332 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16333 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16334 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16335 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16336 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
41adaa5c 16337 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd),
8f06b2d8
PB
16338 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
16339 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16340 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16341 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16342 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16343 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16344 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16345 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
16346 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
16347 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
41adaa5c 16348 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn),
8f06b2d8
PB
16349 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
16350 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
16351 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
16352 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
16353 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
16354 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
16355 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
16356 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16357 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16358 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16359 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16360 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16361 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16362 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16363 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16364 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16365 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
16366 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16367 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16368 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16369 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16370 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16371 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16372 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16373 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16374 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16375 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16376 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16377 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16378 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16379 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16380 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16381 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16382 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16383 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16384 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16385 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16386 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16387 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16388 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16389 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16390 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16391 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16392 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16393 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16394 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16395 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16396 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16397 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16398 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16399 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16400 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16401 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16402 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16403 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16404 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16405 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16406 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16407 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
16408 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16409 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16410 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16411 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16412 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16413 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16414 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16415 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16416 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16417 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16418 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 16419 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16420 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16421 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16422 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16423 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8
PB
16424 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16425 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16426 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16427 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16428 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16429 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
2d447fca 16430 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16431 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16432 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16433 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16434 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16435 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16436 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16437 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16438 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16439 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16440 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16441 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16442 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16443 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16444 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8 16445 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
2d447fca 16446 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
8f06b2d8
PB
16447 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16448 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16449 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16450 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16451 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16452 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16453 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16454 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16455 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16456 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16457 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16458 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16459 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16460 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16461 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
16462 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
16463 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
16464 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
16465 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
16466 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
16467 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16468 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16469 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16470 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
16471 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
16472 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
16473 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
16474 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
16475 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
16476 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16477 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16478 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16479 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16480 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 16481
2d447fca
JM
16482#undef ARM_VARIANT
16483#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16484 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc),
16485 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc),
16486 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc),
16487 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn),
16488 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn),
16489 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn),
16490 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16491 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16492 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16493 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16494 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16495 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16496 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16497 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16498 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16499 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16500 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16501 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16502 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16503 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16504 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
16505 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16506 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16507 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16508 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16509 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16510 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16511 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16512 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16513 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16514 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16515 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16516 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16517 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16518 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16519 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16520 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16521 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16522 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16523 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16524 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16525 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16526 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16527 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16528 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16529 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16530 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16531 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16532 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16533 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16534 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16535 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16536 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16537 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16538 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16539 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16540 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16541
c19d1205 16542#undef ARM_VARIANT
e74cfd16 16543#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
4962c51a
MS
16544 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16545 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16546 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16547 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16548 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16549 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16550 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16551 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
8f06b2d8
PB
16552 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
16553 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
16554 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
16555 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
16556 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
16557 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
16558 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
16559 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
16560 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
16561 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
16562 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
16563 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
16564 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
16565 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
16566 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
16567 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
16568 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
16569 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
16570 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
16571 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
16572 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
16573 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
16574 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
16575 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
16576 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
16577 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
16578 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
16579 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
16580 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
16581 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
16582 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
16583 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
16584 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
16585 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
16586 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
16587 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
16588 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
16589 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
16590 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
16591 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
16592 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
16593 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
16594 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
16595 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
16596 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
16597 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
16598 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
16599 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
16600 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
16601 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
16602 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
16603 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
16604 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
16605 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
16606 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
16607 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
16608 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16609 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16610 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16611 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16612 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16613 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16614 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16615 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16616 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16617 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16618 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16619 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
c19d1205
ZW
16620};
16621#undef ARM_VARIANT
16622#undef THUMB_VARIANT
16623#undef TCE
16624#undef TCM
16625#undef TUE
16626#undef TUF
16627#undef TCC
8f06b2d8 16628#undef cCE
e3cb604e
PB
16629#undef cCL
16630#undef C3E
c19d1205
ZW
16631#undef CE
16632#undef CM
16633#undef UE
16634#undef UF
16635#undef UT
5287ad62
JB
16636#undef NUF
16637#undef nUF
16638#undef NCE
16639#undef nCE
c19d1205
ZW
16640#undef OPS0
16641#undef OPS1
16642#undef OPS2
16643#undef OPS3
16644#undef OPS4
16645#undef OPS5
16646#undef OPS6
16647#undef do_0
16648\f
16649/* MD interface: bits in the object file. */
bfae80f2 16650
c19d1205
ZW
16651/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16652 for use in the a.out file, and stores them in the array pointed to by buf.
16653 This knows about the endian-ness of the target machine and does
16654 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16655 2 (short) and 4 (long) Floating numbers are put out as a series of
16656 LITTLENUMS (shorts, here at least). */
b99bd4ef 16657
c19d1205
ZW
16658void
16659md_number_to_chars (char * buf, valueT val, int n)
16660{
16661 if (target_big_endian)
16662 number_to_chars_bigendian (buf, val, n);
16663 else
16664 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE
16665}
16666
c19d1205
ZW
16667static valueT
16668md_chars_to_number (char * buf, int n)
bfae80f2 16669{
c19d1205
ZW
16670 valueT result = 0;
16671 unsigned char * where = (unsigned char *) buf;
bfae80f2 16672
c19d1205 16673 if (target_big_endian)
b99bd4ef 16674 {
c19d1205
ZW
16675 while (n--)
16676 {
16677 result <<= 8;
16678 result |= (*where++ & 255);
16679 }
b99bd4ef 16680 }
c19d1205 16681 else
b99bd4ef 16682 {
c19d1205
ZW
16683 while (n--)
16684 {
16685 result <<= 8;
16686 result |= (where[n] & 255);
16687 }
bfae80f2 16688 }
b99bd4ef 16689
c19d1205 16690 return result;
bfae80f2 16691}
b99bd4ef 16692
c19d1205 16693/* MD interface: Sections. */
b99bd4ef 16694
0110f2b8
PB
16695/* Estimate the size of a frag before relaxing. Assume everything fits in
16696 2 bytes. */
16697
c19d1205 16698int
0110f2b8 16699md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW
16700 segT segtype ATTRIBUTE_UNUSED)
16701{
0110f2b8
PB
16702 fragp->fr_var = 2;
16703 return 2;
16704}
16705
16706/* Convert a machine dependent frag. */
16707
16708void
16709md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
16710{
16711 unsigned long insn;
16712 unsigned long old_op;
16713 char *buf;
16714 expressionS exp;
16715 fixS *fixp;
16716 int reloc_type;
16717 int pc_rel;
16718 int opcode;
16719
16720 buf = fragp->fr_literal + fragp->fr_fix;
16721
16722 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC
16723 if (fragp->fr_symbol)
16724 {
0110f2b8
PB
16725 exp.X_op = O_symbol;
16726 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC
16727 }
16728 else
16729 {
0110f2b8 16730 exp.X_op = O_constant;
5f4273c7 16731 }
0110f2b8
PB
16732 exp.X_add_number = fragp->fr_offset;
16733 opcode = fragp->fr_subtype;
16734 switch (opcode)
16735 {
16736 case T_MNEM_ldr_pc:
16737 case T_MNEM_ldr_pc2:
16738 case T_MNEM_ldr_sp:
16739 case T_MNEM_str_sp:
16740 case T_MNEM_ldr:
16741 case T_MNEM_ldrb:
16742 case T_MNEM_ldrh:
16743 case T_MNEM_str:
16744 case T_MNEM_strb:
16745 case T_MNEM_strh:
16746 if (fragp->fr_var == 4)
16747 {
5f4273c7 16748 insn = THUMB_OP32 (opcode);
0110f2b8
PB
16749 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
16750 {
16751 insn |= (old_op & 0x700) << 4;
16752 }
16753 else
16754 {
16755 insn |= (old_op & 7) << 12;
16756 insn |= (old_op & 0x38) << 13;
16757 }
16758 insn |= 0x00000c00;
16759 put_thumb32_insn (buf, insn);
16760 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
16761 }
16762 else
16763 {
16764 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
16765 }
16766 pc_rel = (opcode == T_MNEM_ldr_pc2);
16767 break;
16768 case T_MNEM_adr:
16769 if (fragp->fr_var == 4)
16770 {
16771 insn = THUMB_OP32 (opcode);
16772 insn |= (old_op & 0xf0) << 4;
16773 put_thumb32_insn (buf, insn);
16774 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
16775 }
16776 else
16777 {
16778 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16779 exp.X_add_number -= 4;
16780 }
16781 pc_rel = 1;
16782 break;
16783 case T_MNEM_mov:
16784 case T_MNEM_movs:
16785 case T_MNEM_cmp:
16786 case T_MNEM_cmn:
16787 if (fragp->fr_var == 4)
16788 {
16789 int r0off = (opcode == T_MNEM_mov
16790 || opcode == T_MNEM_movs) ? 0 : 8;
16791 insn = THUMB_OP32 (opcode);
16792 insn = (insn & 0xe1ffffff) | 0x10000000;
16793 insn |= (old_op & 0x700) << r0off;
16794 put_thumb32_insn (buf, insn);
16795 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16796 }
16797 else
16798 {
16799 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
16800 }
16801 pc_rel = 0;
16802 break;
16803 case T_MNEM_b:
16804 if (fragp->fr_var == 4)
16805 {
16806 insn = THUMB_OP32(opcode);
16807 put_thumb32_insn (buf, insn);
16808 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
16809 }
16810 else
16811 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
16812 pc_rel = 1;
16813 break;
16814 case T_MNEM_bcond:
16815 if (fragp->fr_var == 4)
16816 {
16817 insn = THUMB_OP32(opcode);
16818 insn |= (old_op & 0xf00) << 14;
16819 put_thumb32_insn (buf, insn);
16820 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
16821 }
16822 else
16823 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
16824 pc_rel = 1;
16825 break;
16826 case T_MNEM_add_sp:
16827 case T_MNEM_add_pc:
16828 case T_MNEM_inc_sp:
16829 case T_MNEM_dec_sp:
16830 if (fragp->fr_var == 4)
16831 {
16832 /* ??? Choose between add and addw. */
16833 insn = THUMB_OP32 (opcode);
16834 insn |= (old_op & 0xf0) << 4;
16835 put_thumb32_insn (buf, insn);
16805f35
PB
16836 if (opcode == T_MNEM_add_pc)
16837 reloc_type = BFD_RELOC_ARM_T32_IMM12;
16838 else
16839 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB
16840 }
16841 else
16842 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16843 pc_rel = 0;
16844 break;
16845
16846 case T_MNEM_addi:
16847 case T_MNEM_addis:
16848 case T_MNEM_subi:
16849 case T_MNEM_subis:
16850 if (fragp->fr_var == 4)
16851 {
16852 insn = THUMB_OP32 (opcode);
16853 insn |= (old_op & 0xf0) << 4;
16854 insn |= (old_op & 0xf) << 16;
16855 put_thumb32_insn (buf, insn);
16805f35
PB
16856 if (insn & (1 << 20))
16857 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16858 else
16859 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB
16860 }
16861 else
16862 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16863 pc_rel = 0;
16864 break;
16865 default:
5f4273c7 16866 abort ();
0110f2b8
PB
16867 }
16868 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
16869 reloc_type);
16870 fixp->fx_file = fragp->fr_file;
16871 fixp->fx_line = fragp->fr_line;
16872 fragp->fr_fix += fragp->fr_var;
16873}
16874
16875/* Return the size of a relaxable immediate operand instruction.
16876 SHIFT and SIZE specify the form of the allowable immediate. */
16877static int
16878relax_immediate (fragS *fragp, int size, int shift)
16879{
16880 offsetT offset;
16881 offsetT mask;
16882 offsetT low;
16883
16884 /* ??? Should be able to do better than this. */
16885 if (fragp->fr_symbol)
16886 return 4;
16887
16888 low = (1 << shift) - 1;
16889 mask = (1 << (shift + size)) - (1 << shift);
16890 offset = fragp->fr_offset;
16891 /* Force misaligned offsets to 32-bit variant. */
16892 if (offset & low)
5e77afaa 16893 return 4;
0110f2b8
PB
16894 if (offset & ~mask)
16895 return 4;
16896 return 2;
16897}
16898
5e77afaa
PB
16899/* Get the address of a symbol during relaxation. */
16900static addressT
5f4273c7 16901relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB
16902{
16903 fragS *sym_frag;
16904 addressT addr;
16905 symbolS *sym;
16906
16907 sym = fragp->fr_symbol;
16908 sym_frag = symbol_get_frag (sym);
16909 know (S_GET_SEGMENT (sym) != absolute_section
16910 || sym_frag == &zero_address_frag);
16911 addr = S_GET_VALUE (sym) + fragp->fr_offset;
16912
16913 /* If frag has yet to be reached on this pass, assume it will
16914 move by STRETCH just as we did. If this is not so, it will
16915 be because some frag between grows, and that will force
16916 another pass. */
16917
16918 if (stretch != 0
16919 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB
16920 {
16921 fragS *f;
16922
16923 /* Adjust stretch for any alignment frag. Note that if have
16924 been expanding the earlier code, the symbol may be
16925 defined in what appears to be an earlier frag. FIXME:
16926 This doesn't handle the fr_subtype field, which specifies
16927 a maximum number of bytes to skip when doing an
16928 alignment. */
16929 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16930 {
16931 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16932 {
16933 if (stretch < 0)
16934 stretch = - ((- stretch)
16935 & ~ ((1 << (int) f->fr_offset) - 1));
16936 else
16937 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16938 if (stretch == 0)
16939 break;
16940 }
16941 }
16942 if (f != NULL)
16943 addr += stretch;
16944 }
5e77afaa
PB
16945
16946 return addr;
16947}
16948
0110f2b8
PB
16949/* Return the size of a relaxable adr pseudo-instruction or PC-relative
16950 load. */
16951static int
5e77afaa 16952relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB
16953{
16954 addressT addr;
16955 offsetT val;
16956
16957 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 16958 if (!S_IS_DEFINED (fragp->fr_symbol)
0110f2b8
PB
16959 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16960 return 4;
16961
5f4273c7 16962 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB
16963 addr = fragp->fr_address + fragp->fr_fix;
16964 addr = (addr + 4) & ~3;
5e77afaa 16965 /* Force misaligned targets to 32-bit variant. */
0110f2b8 16966 if (val & 3)
5e77afaa 16967 return 4;
0110f2b8
PB
16968 val -= addr;
16969 if (val < 0 || val > 1020)
16970 return 4;
16971 return 2;
16972}
16973
16974/* Return the size of a relaxable add/sub immediate instruction. */
16975static int
16976relax_addsub (fragS *fragp, asection *sec)
16977{
16978 char *buf;
16979 int op;
16980
16981 buf = fragp->fr_literal + fragp->fr_fix;
16982 op = bfd_get_16(sec->owner, buf);
16983 if ((op & 0xf) == ((op >> 4) & 0xf))
16984 return relax_immediate (fragp, 8, 0);
16985 else
16986 return relax_immediate (fragp, 3, 0);
16987}
16988
16989
16990/* Return the size of a relaxable branch instruction. BITS is the
16991 size of the offset field in the narrow instruction. */
16992
16993static int
5e77afaa 16994relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB
16995{
16996 addressT addr;
16997 offsetT val;
16998 offsetT limit;
16999
17000 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 17001 if (!S_IS_DEFINED (fragp->fr_symbol)
0110f2b8
PB
17002 || sec != S_GET_SEGMENT (fragp->fr_symbol))
17003 return 4;
17004
5f4273c7 17005 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB
17006 addr = fragp->fr_address + fragp->fr_fix + 4;
17007 val -= addr;
17008
17009 /* Offset is a signed value *2 */
17010 limit = 1 << bits;
17011 if (val >= limit || val < -limit)
17012 return 4;
17013 return 2;
17014}
17015
17016
17017/* Relax a machine dependent frag. This returns the amount by which
17018 the current size of the frag should change. */
17019
17020int
5e77afaa 17021arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB
17022{
17023 int oldsize;
17024 int newsize;
17025
17026 oldsize = fragp->fr_var;
17027 switch (fragp->fr_subtype)
17028 {
17029 case T_MNEM_ldr_pc2:
5f4273c7 17030 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB
17031 break;
17032 case T_MNEM_ldr_pc:
17033 case T_MNEM_ldr_sp:
17034 case T_MNEM_str_sp:
5f4273c7 17035 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB
17036 break;
17037 case T_MNEM_ldr:
17038 case T_MNEM_str:
5f4273c7 17039 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB
17040 break;
17041 case T_MNEM_ldrh:
17042 case T_MNEM_strh:
5f4273c7 17043 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB
17044 break;
17045 case T_MNEM_ldrb:
17046 case T_MNEM_strb:
5f4273c7 17047 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB
17048 break;
17049 case T_MNEM_adr:
5f4273c7 17050 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB
17051 break;
17052 case T_MNEM_mov:
17053 case T_MNEM_movs:
17054 case T_MNEM_cmp:
17055 case T_MNEM_cmn:
5f4273c7 17056 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB
17057 break;
17058 case T_MNEM_b:
5f4273c7 17059 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB
17060 break;
17061 case T_MNEM_bcond:
5f4273c7 17062 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB
17063 break;
17064 case T_MNEM_add_sp:
17065 case T_MNEM_add_pc:
17066 newsize = relax_immediate (fragp, 8, 2);
17067 break;
17068 case T_MNEM_inc_sp:
17069 case T_MNEM_dec_sp:
17070 newsize = relax_immediate (fragp, 7, 2);
17071 break;
17072 case T_MNEM_addi:
17073 case T_MNEM_addis:
17074 case T_MNEM_subi:
17075 case T_MNEM_subis:
17076 newsize = relax_addsub (fragp, sec);
17077 break;
17078 default:
5f4273c7 17079 abort ();
0110f2b8 17080 }
5e77afaa
PB
17081
17082 fragp->fr_var = newsize;
17083 /* Freeze wide instructions that are at or before the same location as
17084 in the previous pass. This avoids infinite loops.
5f4273c7
NC
17085 Don't freeze them unconditionally because targets may be artificially
17086 misaligned by the expansion of preceding frags. */
5e77afaa 17087 if (stretch <= 0 && newsize > 2)
0110f2b8 17088 {
0110f2b8 17089 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 17090 frag_wane (fragp);
0110f2b8 17091 }
5e77afaa 17092
0110f2b8 17093 return newsize - oldsize;
c19d1205 17094}
b99bd4ef 17095
c19d1205 17096/* Round up a section size to the appropriate boundary. */
b99bd4ef 17097
c19d1205
ZW
17098valueT
17099md_section_align (segT segment ATTRIBUTE_UNUSED,
17100 valueT size)
17101{
f0927246
NC
17102#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17103 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
17104 {
17105 /* For a.out, force the section size to be aligned. If we don't do
17106 this, BFD will align it for us, but it will not write out the
17107 final bytes of the section. This may be a bug in BFD, but it is
17108 easier to fix it here since that is how the other a.out targets
17109 work. */
17110 int align;
17111
17112 align = bfd_get_section_alignment (stdoutput, segment);
17113 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
17114 }
c19d1205 17115#endif
f0927246
NC
17116
17117 return size;
bfae80f2 17118}
b99bd4ef 17119
c19d1205
ZW
17120/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17121 of an rs_align_code fragment. */
17122
17123void
17124arm_handle_align (fragS * fragP)
bfae80f2 17125{
c19d1205
ZW
17126 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17127 static char const thumb_noop[2] = { 0xc0, 0x46 };
17128 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17129 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
17130
17131 int bytes, fix, noop_size;
17132 char * p;
17133 const char * noop;
bfae80f2 17134
c19d1205 17135 if (fragP->fr_type != rs_align_code)
bfae80f2
RE
17136 return;
17137
c19d1205
ZW
17138 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
17139 p = fragP->fr_literal + fragP->fr_fix;
17140 fix = 0;
bfae80f2 17141
c19d1205
ZW
17142 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
17143 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 17144
c19d1205 17145 if (fragP->tc_frag_data)
a737bd4d 17146 {
c19d1205
ZW
17147 if (target_big_endian)
17148 noop = thumb_bigend_noop;
17149 else
17150 noop = thumb_noop;
17151 noop_size = sizeof (thumb_noop);
7ed4c4c5
NC
17152 }
17153 else
17154 {
c19d1205
ZW
17155 if (target_big_endian)
17156 noop = arm_bigend_noop;
17157 else
17158 noop = arm_noop;
17159 noop_size = sizeof (arm_noop);
7ed4c4c5 17160 }
a737bd4d 17161
c19d1205 17162 if (bytes & (noop_size - 1))
7ed4c4c5 17163 {
c19d1205
ZW
17164 fix = bytes & (noop_size - 1);
17165 memset (p, 0, fix);
17166 p += fix;
17167 bytes -= fix;
a737bd4d 17168 }
a737bd4d 17169
c19d1205 17170 while (bytes >= noop_size)
a737bd4d 17171 {
c19d1205
ZW
17172 memcpy (p, noop, noop_size);
17173 p += noop_size;
17174 bytes -= noop_size;
17175 fix += noop_size;
a737bd4d
NC
17176 }
17177
c19d1205
ZW
17178 fragP->fr_fix += fix;
17179 fragP->fr_var = noop_size;
a737bd4d
NC
17180}
17181
c19d1205
ZW
17182/* Called from md_do_align. Used to create an alignment
17183 frag in a code section. */
17184
17185void
17186arm_frag_align_code (int n, int max)
bfae80f2 17187{
c19d1205 17188 char * p;
7ed4c4c5 17189
c19d1205
ZW
17190 /* We assume that there will never be a requirement
17191 to support alignments greater than 32 bytes. */
17192 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
17193 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
bfae80f2 17194
c19d1205
ZW
17195 p = frag_var (rs_align_code,
17196 MAX_MEM_FOR_RS_ALIGN_CODE,
17197 1,
17198 (relax_substateT) max,
17199 (symbolS *) NULL,
17200 (offsetT) n,
17201 (char *) NULL);
17202 *p = 0;
17203}
bfae80f2 17204
c19d1205 17205/* Perform target specific initialisation of a frag. */
bfae80f2 17206
c19d1205
ZW
17207void
17208arm_init_frag (fragS * fragP)
17209{
17210 /* Record whether this frag is in an ARM or a THUMB area. */
17211 fragP->tc_frag_data = thumb_mode;
bfae80f2
RE
17212}
17213
c19d1205
ZW
17214#ifdef OBJ_ELF
17215/* When we change sections we need to issue a new mapping symbol. */
17216
17217void
17218arm_elf_change_section (void)
bfae80f2 17219{
c19d1205
ZW
17220 flagword flags;
17221 segment_info_type *seginfo;
bfae80f2 17222
c19d1205
ZW
17223 /* Link an unlinked unwind index table section to the .text section. */
17224 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
17225 && elf_linked_to_section (now_seg) == NULL)
17226 elf_linked_to_section (now_seg) = text_section;
17227
17228 if (!SEG_NORMAL (now_seg))
bfae80f2
RE
17229 return;
17230
c19d1205
ZW
17231 flags = bfd_get_section_flags (stdoutput, now_seg);
17232
17233 /* We can ignore sections that only contain debug info. */
17234 if ((flags & SEC_ALLOC) == 0)
17235 return;
bfae80f2 17236
c19d1205
ZW
17237 seginfo = seg_info (now_seg);
17238 mapstate = seginfo->tc_segment_info_data.mapstate;
17239 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
bfae80f2
RE
17240}
17241
c19d1205
ZW
17242int
17243arm_elf_section_type (const char * str, size_t len)
e45d0630 17244{
c19d1205
ZW
17245 if (len == 5 && strncmp (str, "exidx", 5) == 0)
17246 return SHT_ARM_EXIDX;
e45d0630 17247
c19d1205
ZW
17248 return -1;
17249}
17250\f
17251/* Code to deal with unwinding tables. */
e45d0630 17252
c19d1205 17253static void add_unwind_adjustsp (offsetT);
e45d0630 17254
5f4273c7 17255/* Generate any deferred unwind frame offset. */
e45d0630 17256
bfae80f2 17257static void
c19d1205 17258flush_pending_unwind (void)
bfae80f2 17259{
c19d1205 17260 offsetT offset;
bfae80f2 17261
c19d1205
ZW
17262 offset = unwind.pending_offset;
17263 unwind.pending_offset = 0;
17264 if (offset != 0)
17265 add_unwind_adjustsp (offset);
bfae80f2
RE
17266}
17267
c19d1205
ZW
17268/* Add an opcode to this list for this function. Two-byte opcodes should
17269 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17270 order. */
17271
bfae80f2 17272static void
c19d1205 17273add_unwind_opcode (valueT op, int length)
bfae80f2 17274{
c19d1205
ZW
17275 /* Add any deferred stack adjustment. */
17276 if (unwind.pending_offset)
17277 flush_pending_unwind ();
bfae80f2 17278
c19d1205 17279 unwind.sp_restored = 0;
bfae80f2 17280
c19d1205 17281 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 17282 {
c19d1205
ZW
17283 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
17284 if (unwind.opcodes)
17285 unwind.opcodes = xrealloc (unwind.opcodes,
17286 unwind.opcode_alloc);
17287 else
17288 unwind.opcodes = xmalloc (unwind.opcode_alloc);
bfae80f2 17289 }
c19d1205 17290 while (length > 0)
bfae80f2 17291 {
c19d1205
ZW
17292 length--;
17293 unwind.opcodes[unwind.opcode_count] = op & 0xff;
17294 op >>= 8;
17295 unwind.opcode_count++;
bfae80f2 17296 }
bfae80f2
RE
17297}
17298
c19d1205
ZW
17299/* Add unwind opcodes to adjust the stack pointer. */
17300
bfae80f2 17301static void
c19d1205 17302add_unwind_adjustsp (offsetT offset)
bfae80f2 17303{
c19d1205 17304 valueT op;
bfae80f2 17305
c19d1205 17306 if (offset > 0x200)
bfae80f2 17307 {
c19d1205
ZW
17308 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17309 char bytes[5];
17310 int n;
17311 valueT o;
bfae80f2 17312
c19d1205
ZW
17313 /* Long form: 0xb2, uleb128. */
17314 /* This might not fit in a word so add the individual bytes,
17315 remembering the list is built in reverse order. */
17316 o = (valueT) ((offset - 0x204) >> 2);
17317 if (o == 0)
17318 add_unwind_opcode (0, 1);
bfae80f2 17319
c19d1205
ZW
17320 /* Calculate the uleb128 encoding of the offset. */
17321 n = 0;
17322 while (o)
17323 {
17324 bytes[n] = o & 0x7f;
17325 o >>= 7;
17326 if (o)
17327 bytes[n] |= 0x80;
17328 n++;
17329 }
17330 /* Add the insn. */
17331 for (; n; n--)
17332 add_unwind_opcode (bytes[n - 1], 1);
17333 add_unwind_opcode (0xb2, 1);
17334 }
17335 else if (offset > 0x100)
bfae80f2 17336 {
c19d1205
ZW
17337 /* Two short opcodes. */
17338 add_unwind_opcode (0x3f, 1);
17339 op = (offset - 0x104) >> 2;
17340 add_unwind_opcode (op, 1);
bfae80f2 17341 }
c19d1205
ZW
17342 else if (offset > 0)
17343 {
17344 /* Short opcode. */
17345 op = (offset - 4) >> 2;
17346 add_unwind_opcode (op, 1);
17347 }
17348 else if (offset < 0)
bfae80f2 17349 {
c19d1205
ZW
17350 offset = -offset;
17351 while (offset > 0x100)
bfae80f2 17352 {
c19d1205
ZW
17353 add_unwind_opcode (0x7f, 1);
17354 offset -= 0x100;
bfae80f2 17355 }
c19d1205
ZW
17356 op = ((offset - 4) >> 2) | 0x40;
17357 add_unwind_opcode (op, 1);
bfae80f2 17358 }
bfae80f2
RE
17359}
17360
c19d1205
ZW
17361/* Finish the list of unwind opcodes for this function. */
17362static void
17363finish_unwind_opcodes (void)
bfae80f2 17364{
c19d1205 17365 valueT op;
bfae80f2 17366
c19d1205 17367 if (unwind.fp_used)
bfae80f2 17368 {
708587a4 17369 /* Adjust sp as necessary. */
c19d1205
ZW
17370 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
17371 flush_pending_unwind ();
bfae80f2 17372
c19d1205
ZW
17373 /* After restoring sp from the frame pointer. */
17374 op = 0x90 | unwind.fp_reg;
17375 add_unwind_opcode (op, 1);
17376 }
17377 else
17378 flush_pending_unwind ();
bfae80f2
RE
17379}
17380
bfae80f2 17381
c19d1205
ZW
17382/* Start an exception table entry. If idx is nonzero this is an index table
17383 entry. */
bfae80f2
RE
17384
17385static void
c19d1205 17386start_unwind_section (const segT text_seg, int idx)
bfae80f2 17387{
c19d1205
ZW
17388 const char * text_name;
17389 const char * prefix;
17390 const char * prefix_once;
17391 const char * group_name;
17392 size_t prefix_len;
17393 size_t text_len;
17394 char * sec_name;
17395 size_t sec_name_len;
17396 int type;
17397 int flags;
17398 int linkonce;
bfae80f2 17399
c19d1205 17400 if (idx)
bfae80f2 17401 {
c19d1205
ZW
17402 prefix = ELF_STRING_ARM_unwind;
17403 prefix_once = ELF_STRING_ARM_unwind_once;
17404 type = SHT_ARM_EXIDX;
bfae80f2 17405 }
c19d1205 17406 else
bfae80f2 17407 {
c19d1205
ZW
17408 prefix = ELF_STRING_ARM_unwind_info;
17409 prefix_once = ELF_STRING_ARM_unwind_info_once;
17410 type = SHT_PROGBITS;
bfae80f2
RE
17411 }
17412
c19d1205
ZW
17413 text_name = segment_name (text_seg);
17414 if (streq (text_name, ".text"))
17415 text_name = "";
17416
17417 if (strncmp (text_name, ".gnu.linkonce.t.",
17418 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 17419 {
c19d1205
ZW
17420 prefix = prefix_once;
17421 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE
17422 }
17423
c19d1205
ZW
17424 prefix_len = strlen (prefix);
17425 text_len = strlen (text_name);
17426 sec_name_len = prefix_len + text_len;
17427 sec_name = xmalloc (sec_name_len + 1);
17428 memcpy (sec_name, prefix, prefix_len);
17429 memcpy (sec_name + prefix_len, text_name, text_len);
17430 sec_name[prefix_len + text_len] = '\0';
bfae80f2 17431
c19d1205
ZW
17432 flags = SHF_ALLOC;
17433 linkonce = 0;
17434 group_name = 0;
bfae80f2 17435
c19d1205
ZW
17436 /* Handle COMDAT group. */
17437 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 17438 {
c19d1205
ZW
17439 group_name = elf_group_name (text_seg);
17440 if (group_name == NULL)
17441 {
bd3ba5d1 17442 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW
17443 segment_name (text_seg));
17444 ignore_rest_of_line ();
17445 return;
17446 }
17447 flags |= SHF_GROUP;
17448 linkonce = 1;
bfae80f2
RE
17449 }
17450
c19d1205 17451 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
bfae80f2 17452
5f4273c7 17453 /* Set the section link for index tables. */
c19d1205
ZW
17454 if (idx)
17455 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE
17456}
17457
bfae80f2 17458
c19d1205
ZW
17459/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17460 personality routine data. Returns zero, or the index table value for
17461 and inline entry. */
17462
17463static valueT
17464create_unwind_entry (int have_data)
bfae80f2 17465{
c19d1205
ZW
17466 int size;
17467 addressT where;
17468 char *ptr;
17469 /* The current word of data. */
17470 valueT data;
17471 /* The number of bytes left in this word. */
17472 int n;
bfae80f2 17473
c19d1205 17474 finish_unwind_opcodes ();
bfae80f2 17475
c19d1205
ZW
17476 /* Remember the current text section. */
17477 unwind.saved_seg = now_seg;
17478 unwind.saved_subseg = now_subseg;
bfae80f2 17479
c19d1205 17480 start_unwind_section (now_seg, 0);
bfae80f2 17481
c19d1205 17482 if (unwind.personality_routine == NULL)
bfae80f2 17483 {
c19d1205
ZW
17484 if (unwind.personality_index == -2)
17485 {
17486 if (have_data)
5f4273c7 17487 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW
17488 return 1; /* EXIDX_CANTUNWIND. */
17489 }
bfae80f2 17490
c19d1205
ZW
17491 /* Use a default personality routine if none is specified. */
17492 if (unwind.personality_index == -1)
17493 {
17494 if (unwind.opcode_count > 3)
17495 unwind.personality_index = 1;
17496 else
17497 unwind.personality_index = 0;
17498 }
bfae80f2 17499
c19d1205
ZW
17500 /* Space for the personality routine entry. */
17501 if (unwind.personality_index == 0)
17502 {
17503 if (unwind.opcode_count > 3)
17504 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 17505
c19d1205
ZW
17506 if (!have_data)
17507 {
17508 /* All the data is inline in the index table. */
17509 data = 0x80;
17510 n = 3;
17511 while (unwind.opcode_count > 0)
17512 {
17513 unwind.opcode_count--;
17514 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17515 n--;
17516 }
bfae80f2 17517
c19d1205
ZW
17518 /* Pad with "finish" opcodes. */
17519 while (n--)
17520 data = (data << 8) | 0xb0;
bfae80f2 17521
c19d1205
ZW
17522 return data;
17523 }
17524 size = 0;
17525 }
17526 else
17527 /* We get two opcodes "free" in the first word. */
17528 size = unwind.opcode_count - 2;
17529 }
17530 else
17531 /* An extra byte is required for the opcode count. */
17532 size = unwind.opcode_count + 1;
bfae80f2 17533
c19d1205
ZW
17534 size = (size + 3) >> 2;
17535 if (size > 0xff)
17536 as_bad (_("too many unwind opcodes"));
bfae80f2 17537
c19d1205
ZW
17538 frag_align (2, 0, 0);
17539 record_alignment (now_seg, 2);
17540 unwind.table_entry = expr_build_dot ();
17541
17542 /* Allocate the table entry. */
17543 ptr = frag_more ((size << 2) + 4);
17544 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 17545
c19d1205 17546 switch (unwind.personality_index)
bfae80f2 17547 {
c19d1205
ZW
17548 case -1:
17549 /* ??? Should this be a PLT generating relocation? */
17550 /* Custom personality routine. */
17551 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
17552 BFD_RELOC_ARM_PREL31);
bfae80f2 17553
c19d1205
ZW
17554 where += 4;
17555 ptr += 4;
bfae80f2 17556
c19d1205
ZW
17557 /* Set the first byte to the number of additional words. */
17558 data = size - 1;
17559 n = 3;
17560 break;
bfae80f2 17561
c19d1205
ZW
17562 /* ABI defined personality routines. */
17563 case 0:
17564 /* Three opcodes bytes are packed into the first word. */
17565 data = 0x80;
17566 n = 3;
17567 break;
bfae80f2 17568
c19d1205
ZW
17569 case 1:
17570 case 2:
17571 /* The size and first two opcode bytes go in the first word. */
17572 data = ((0x80 + unwind.personality_index) << 8) | size;
17573 n = 2;
17574 break;
bfae80f2 17575
c19d1205
ZW
17576 default:
17577 /* Should never happen. */
17578 abort ();
17579 }
bfae80f2 17580
c19d1205
ZW
17581 /* Pack the opcodes into words (MSB first), reversing the list at the same
17582 time. */
17583 while (unwind.opcode_count > 0)
17584 {
17585 if (n == 0)
17586 {
17587 md_number_to_chars (ptr, data, 4);
17588 ptr += 4;
17589 n = 4;
17590 data = 0;
17591 }
17592 unwind.opcode_count--;
17593 n--;
17594 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17595 }
17596
17597 /* Finish off the last word. */
17598 if (n < 4)
17599 {
17600 /* Pad with "finish" opcodes. */
17601 while (n--)
17602 data = (data << 8) | 0xb0;
17603
17604 md_number_to_chars (ptr, data, 4);
17605 }
17606
17607 if (!have_data)
17608 {
17609 /* Add an empty descriptor if there is no user-specified data. */
17610 ptr = frag_more (4);
17611 md_number_to_chars (ptr, 0, 4);
17612 }
17613
17614 return 0;
bfae80f2
RE
17615}
17616
f0927246
NC
17617
17618/* Initialize the DWARF-2 unwind information for this procedure. */
17619
17620void
17621tc_arm_frame_initial_instructions (void)
17622{
17623 cfi_add_CFA_def_cfa (REG_SP, 0);
17624}
17625#endif /* OBJ_ELF */
17626
c19d1205
ZW
17627/* Convert REGNAME to a DWARF-2 register number. */
17628
17629int
1df69f4f 17630tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 17631{
1df69f4f 17632 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
c19d1205
ZW
17633
17634 if (reg == FAIL)
17635 return -1;
17636
17637 return reg;
bfae80f2
RE
17638}
17639
f0927246 17640#ifdef TE_PE
c19d1205 17641void
f0927246 17642tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 17643{
f0927246 17644 expressionS expr;
bfae80f2 17645
f0927246
NC
17646 expr.X_op = O_secrel;
17647 expr.X_add_symbol = symbol;
17648 expr.X_add_number = 0;
17649 emit_expr (&expr, size);
17650}
17651#endif
bfae80f2 17652
c19d1205 17653/* MD interface: Symbol and relocation handling. */
bfae80f2 17654
2fc8bdac
ZW
17655/* Return the address within the segment that a PC-relative fixup is
17656 relative to. For ARM, PC-relative fixups applied to instructions
17657 are generally relative to the location of the fixup plus 8 bytes.
17658 Thumb branches are offset by 4, and Thumb loads relative to PC
17659 require special handling. */
bfae80f2 17660
c19d1205 17661long
2fc8bdac 17662md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 17663{
2fc8bdac
ZW
17664 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
17665
17666 /* If this is pc-relative and we are going to emit a relocation
17667 then we just want to put out any pipeline compensation that the linker
53baae48
NC
17668 will need. Otherwise we want to use the calculated base.
17669 For WinCE we skip the bias for externals as well, since this
17670 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 17671 if (fixP->fx_pcrel
2fc8bdac 17672 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC
17673 || (arm_force_relocation (fixP)
17674#ifdef TE_WINCE
17675 && !S_IS_EXTERNAL (fixP->fx_addsy)
17676#endif
17677 )))
2fc8bdac 17678 base = 0;
bfae80f2 17679
c19d1205 17680 switch (fixP->fx_r_type)
bfae80f2 17681 {
2fc8bdac
ZW
17682 /* PC relative addressing on the Thumb is slightly odd as the
17683 bottom two bits of the PC are forced to zero for the
17684 calculation. This happens *after* application of the
17685 pipeline offset. However, Thumb adrl already adjusts for
17686 this, so we need not do it again. */
c19d1205 17687 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 17688 return base & ~3;
c19d1205
ZW
17689
17690 case BFD_RELOC_ARM_THUMB_OFFSET:
17691 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 17692 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 17693 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 17694 return (base + 4) & ~3;
c19d1205 17695
2fc8bdac
ZW
17696 /* Thumb branches are simply offset by +4. */
17697 case BFD_RELOC_THUMB_PCREL_BRANCH7:
17698 case BFD_RELOC_THUMB_PCREL_BRANCH9:
17699 case BFD_RELOC_THUMB_PCREL_BRANCH12:
17700 case BFD_RELOC_THUMB_PCREL_BRANCH20:
17701 case BFD_RELOC_THUMB_PCREL_BRANCH23:
17702 case BFD_RELOC_THUMB_PCREL_BRANCH25:
17703 case BFD_RELOC_THUMB_PCREL_BLX:
17704 return base + 4;
bfae80f2 17705
2fc8bdac
ZW
17706 /* ARM mode branches are offset by +8. However, the Windows CE
17707 loader expects the relocation not to take this into account. */
17708 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c
PB
17709 case BFD_RELOC_ARM_PCREL_CALL:
17710 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac
ZW
17711 case BFD_RELOC_ARM_PCREL_BLX:
17712 case BFD_RELOC_ARM_PLT32:
c19d1205 17713#ifdef TE_WINCE
5f4273c7 17714 /* When handling fixups immediately, because we have already
53baae48
NC
17715 discovered the value of a symbol, or the address of the frag involved
17716 we must account for the offset by +8, as the OS loader will never see the reloc.
17717 see fixup_segment() in write.c
17718 The S_IS_EXTERNAL test handles the case of global symbols.
17719 Those need the calculated base, not just the pipe compensation the linker will need. */
17720 if (fixP->fx_pcrel
17721 && fixP->fx_addsy != NULL
17722 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
17723 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
17724 return base + 8;
2fc8bdac 17725 return base;
c19d1205 17726#else
2fc8bdac 17727 return base + 8;
c19d1205 17728#endif
2fc8bdac
ZW
17729
17730 /* ARM mode loads relative to PC are also offset by +8. Unlike
17731 branches, the Windows CE loader *does* expect the relocation
17732 to take this into account. */
17733 case BFD_RELOC_ARM_OFFSET_IMM:
17734 case BFD_RELOC_ARM_OFFSET_IMM8:
17735 case BFD_RELOC_ARM_HWLITERAL:
17736 case BFD_RELOC_ARM_LITERAL:
17737 case BFD_RELOC_ARM_CP_OFF_IMM:
17738 return base + 8;
17739
17740
17741 /* Other PC-relative relocations are un-offset. */
17742 default:
17743 return base;
17744 }
bfae80f2
RE
17745}
17746
c19d1205
ZW
17747/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17748 Otherwise we have no need to default values of symbols. */
17749
17750symbolS *
17751md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
bfae80f2 17752{
c19d1205
ZW
17753#ifdef OBJ_ELF
17754 if (name[0] == '_' && name[1] == 'G'
17755 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
17756 {
17757 if (!GOT_symbol)
17758 {
17759 if (symbol_find (name))
bd3ba5d1 17760 as_bad (_("GOT already in the symbol table"));
bfae80f2 17761
c19d1205
ZW
17762 GOT_symbol = symbol_new (name, undefined_section,
17763 (valueT) 0, & zero_address_frag);
17764 }
bfae80f2 17765
c19d1205 17766 return GOT_symbol;
bfae80f2 17767 }
c19d1205 17768#endif
bfae80f2 17769
c19d1205 17770 return 0;
bfae80f2
RE
17771}
17772
55cf6793 17773/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW
17774 computed as two separate immediate values, added together. We
17775 already know that this value cannot be computed by just one ARM
17776 instruction. */
17777
17778static unsigned int
17779validate_immediate_twopart (unsigned int val,
17780 unsigned int * highpart)
bfae80f2 17781{
c19d1205
ZW
17782 unsigned int a;
17783 unsigned int i;
bfae80f2 17784
c19d1205
ZW
17785 for (i = 0; i < 32; i += 2)
17786 if (((a = rotate_left (val, i)) & 0xff) != 0)
17787 {
17788 if (a & 0xff00)
17789 {
17790 if (a & ~ 0xffff)
17791 continue;
17792 * highpart = (a >> 8) | ((i + 24) << 7);
17793 }
17794 else if (a & 0xff0000)
17795 {
17796 if (a & 0xff000000)
17797 continue;
17798 * highpart = (a >> 16) | ((i + 16) << 7);
17799 }
17800 else
17801 {
17802 assert (a & 0xff000000);
17803 * highpart = (a >> 24) | ((i + 8) << 7);
17804 }
bfae80f2 17805
c19d1205
ZW
17806 return (a & 0xff) | (i << 7);
17807 }
bfae80f2 17808
c19d1205 17809 return FAIL;
bfae80f2
RE
17810}
17811
c19d1205
ZW
17812static int
17813validate_offset_imm (unsigned int val, int hwse)
17814{
17815 if ((hwse && val > 255) || val > 4095)
17816 return FAIL;
17817 return val;
17818}
bfae80f2 17819
55cf6793 17820/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW
17821 negative immediate constant by altering the instruction. A bit of
17822 a hack really.
17823 MOV <-> MVN
17824 AND <-> BIC
17825 ADC <-> SBC
17826 by inverting the second operand, and
17827 ADD <-> SUB
17828 CMP <-> CMN
17829 by negating the second operand. */
bfae80f2 17830
c19d1205
ZW
17831static int
17832negate_data_op (unsigned long * instruction,
17833 unsigned long value)
bfae80f2 17834{
c19d1205
ZW
17835 int op, new_inst;
17836 unsigned long negated, inverted;
bfae80f2 17837
c19d1205
ZW
17838 negated = encode_arm_immediate (-value);
17839 inverted = encode_arm_immediate (~value);
bfae80f2 17840
c19d1205
ZW
17841 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17842 switch (op)
bfae80f2 17843 {
c19d1205
ZW
17844 /* First negates. */
17845 case OPCODE_SUB: /* ADD <-> SUB */
17846 new_inst = OPCODE_ADD;
17847 value = negated;
17848 break;
bfae80f2 17849
c19d1205
ZW
17850 case OPCODE_ADD:
17851 new_inst = OPCODE_SUB;
17852 value = negated;
17853 break;
bfae80f2 17854
c19d1205
ZW
17855 case OPCODE_CMP: /* CMP <-> CMN */
17856 new_inst = OPCODE_CMN;
17857 value = negated;
17858 break;
bfae80f2 17859
c19d1205
ZW
17860 case OPCODE_CMN:
17861 new_inst = OPCODE_CMP;
17862 value = negated;
17863 break;
bfae80f2 17864
c19d1205
ZW
17865 /* Now Inverted ops. */
17866 case OPCODE_MOV: /* MOV <-> MVN */
17867 new_inst = OPCODE_MVN;
17868 value = inverted;
17869 break;
bfae80f2 17870
c19d1205
ZW
17871 case OPCODE_MVN:
17872 new_inst = OPCODE_MOV;
17873 value = inverted;
17874 break;
bfae80f2 17875
c19d1205
ZW
17876 case OPCODE_AND: /* AND <-> BIC */
17877 new_inst = OPCODE_BIC;
17878 value = inverted;
17879 break;
bfae80f2 17880
c19d1205
ZW
17881 case OPCODE_BIC:
17882 new_inst = OPCODE_AND;
17883 value = inverted;
17884 break;
bfae80f2 17885
c19d1205
ZW
17886 case OPCODE_ADC: /* ADC <-> SBC */
17887 new_inst = OPCODE_SBC;
17888 value = inverted;
17889 break;
bfae80f2 17890
c19d1205
ZW
17891 case OPCODE_SBC:
17892 new_inst = OPCODE_ADC;
17893 value = inverted;
17894 break;
bfae80f2 17895
c19d1205
ZW
17896 /* We cannot do anything. */
17897 default:
17898 return FAIL;
b99bd4ef
NC
17899 }
17900
c19d1205
ZW
17901 if (value == (unsigned) FAIL)
17902 return FAIL;
17903
17904 *instruction &= OPCODE_MASK;
17905 *instruction |= new_inst << DATA_OP_SHIFT;
17906 return value;
b99bd4ef
NC
17907}
17908
ef8d22e6
PB
17909/* Like negate_data_op, but for Thumb-2. */
17910
17911static unsigned int
16dd5e42 17912thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB
17913{
17914 int op, new_inst;
17915 int rd;
16dd5e42 17916 unsigned int negated, inverted;
ef8d22e6
PB
17917
17918 negated = encode_thumb32_immediate (-value);
17919 inverted = encode_thumb32_immediate (~value);
17920
17921 rd = (*instruction >> 8) & 0xf;
17922 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17923 switch (op)
17924 {
17925 /* ADD <-> SUB. Includes CMP <-> CMN. */
17926 case T2_OPCODE_SUB:
17927 new_inst = T2_OPCODE_ADD;
17928 value = negated;
17929 break;
17930
17931 case T2_OPCODE_ADD:
17932 new_inst = T2_OPCODE_SUB;
17933 value = negated;
17934 break;
17935
17936 /* ORR <-> ORN. Includes MOV <-> MVN. */
17937 case T2_OPCODE_ORR:
17938 new_inst = T2_OPCODE_ORN;
17939 value = inverted;
17940 break;
17941
17942 case T2_OPCODE_ORN:
17943 new_inst = T2_OPCODE_ORR;
17944 value = inverted;
17945 break;
17946
17947 /* AND <-> BIC. TST has no inverted equivalent. */
17948 case T2_OPCODE_AND:
17949 new_inst = T2_OPCODE_BIC;
17950 if (rd == 15)
17951 value = FAIL;
17952 else
17953 value = inverted;
17954 break;
17955
17956 case T2_OPCODE_BIC:
17957 new_inst = T2_OPCODE_AND;
17958 value = inverted;
17959 break;
17960
17961 /* ADC <-> SBC */
17962 case T2_OPCODE_ADC:
17963 new_inst = T2_OPCODE_SBC;
17964 value = inverted;
17965 break;
17966
17967 case T2_OPCODE_SBC:
17968 new_inst = T2_OPCODE_ADC;
17969 value = inverted;
17970 break;
17971
17972 /* We cannot do anything. */
17973 default:
17974 return FAIL;
17975 }
17976
16dd5e42 17977 if (value == (unsigned int)FAIL)
ef8d22e6
PB
17978 return FAIL;
17979
17980 *instruction &= T2_OPCODE_MASK;
17981 *instruction |= new_inst << T2_DATA_OP_SHIFT;
17982 return value;
17983}
17984
8f06b2d8
PB
17985/* Read a 32-bit thumb instruction from buf. */
17986static unsigned long
17987get_thumb32_insn (char * buf)
17988{
17989 unsigned long insn;
17990 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
17991 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
17992
17993 return insn;
17994}
17995
a8bc6c78
PB
17996
17997/* We usually want to set the low bit on the address of thumb function
17998 symbols. In particular .word foo - . should have the low bit set.
17999 Generic code tries to fold the difference of two symbols to
18000 a constant. Prevent this and force a relocation when the first symbols
18001 is a thumb function. */
18002int
18003arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
18004{
18005 if (op == O_subtract
18006 && l->X_op == O_symbol
18007 && r->X_op == O_symbol
18008 && THUMB_IS_FUNC (l->X_add_symbol))
18009 {
18010 l->X_op = O_subtract;
18011 l->X_op_symbol = r->X_add_symbol;
18012 l->X_add_number -= r->X_add_number;
18013 return 1;
18014 }
18015 /* Process as normal. */
18016 return 0;
18017}
18018
c19d1205 18019void
55cf6793 18020md_apply_fix (fixS * fixP,
c19d1205
ZW
18021 valueT * valP,
18022 segT seg)
18023{
18024 offsetT value = * valP;
18025 offsetT newval;
18026 unsigned int newimm;
18027 unsigned long temp;
18028 int sign;
18029 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 18030
c19d1205 18031 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 18032
c19d1205 18033 /* Note whether this will delete the relocation. */
4962c51a 18034
c19d1205
ZW
18035 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
18036 fixP->fx_done = 1;
b99bd4ef 18037
adbaf948 18038 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 18039 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW
18040 for emit_reloc. */
18041 value &= 0xffffffff;
18042 value ^= 0x80000000;
5f4273c7 18043 value -= 0x80000000;
adbaf948
ZW
18044
18045 *valP = value;
c19d1205 18046 fixP->fx_addnumber = value;
b99bd4ef 18047
adbaf948
ZW
18048 /* Same treatment for fixP->fx_offset. */
18049 fixP->fx_offset &= 0xffffffff;
18050 fixP->fx_offset ^= 0x80000000;
18051 fixP->fx_offset -= 0x80000000;
18052
c19d1205 18053 switch (fixP->fx_r_type)
b99bd4ef 18054 {
c19d1205
ZW
18055 case BFD_RELOC_NONE:
18056 /* This will need to go in the object file. */
18057 fixP->fx_done = 0;
18058 break;
b99bd4ef 18059
c19d1205
ZW
18060 case BFD_RELOC_ARM_IMMEDIATE:
18061 /* We claim that this fixup has been processed here,
18062 even if in fact we generate an error because we do
18063 not have a reloc for it, so tc_gen_reloc will reject it. */
18064 fixP->fx_done = 1;
b99bd4ef 18065
c19d1205
ZW
18066 if (fixP->fx_addsy
18067 && ! S_IS_DEFINED (fixP->fx_addsy))
b99bd4ef 18068 {
c19d1205
ZW
18069 as_bad_where (fixP->fx_file, fixP->fx_line,
18070 _("undefined symbol %s used as an immediate value"),
18071 S_GET_NAME (fixP->fx_addsy));
18072 break;
b99bd4ef
NC
18073 }
18074
c19d1205
ZW
18075 newimm = encode_arm_immediate (value);
18076 temp = md_chars_to_number (buf, INSN_SIZE);
18077
18078 /* If the instruction will fail, see if we can fix things up by
18079 changing the opcode. */
18080 if (newimm == (unsigned int) FAIL
18081 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
b99bd4ef 18082 {
c19d1205
ZW
18083 as_bad_where (fixP->fx_file, fixP->fx_line,
18084 _("invalid constant (%lx) after fixup"),
18085 (unsigned long) value);
18086 break;
b99bd4ef 18087 }
b99bd4ef 18088
c19d1205
ZW
18089 newimm |= (temp & 0xfffff000);
18090 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
18091 break;
b99bd4ef 18092
c19d1205
ZW
18093 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
18094 {
18095 unsigned int highpart = 0;
18096 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 18097
c19d1205
ZW
18098 newimm = encode_arm_immediate (value);
18099 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 18100
c19d1205
ZW
18101 /* If the instruction will fail, see if we can fix things up by
18102 changing the opcode. */
18103 if (newimm == (unsigned int) FAIL
18104 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
18105 {
18106 /* No ? OK - try using two ADD instructions to generate
18107 the value. */
18108 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 18109
c19d1205
ZW
18110 /* Yes - then make sure that the second instruction is
18111 also an add. */
18112 if (newimm != (unsigned int) FAIL)
18113 newinsn = temp;
18114 /* Still No ? Try using a negated value. */
18115 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
18116 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
18117 /* Otherwise - give up. */
18118 else
18119 {
18120 as_bad_where (fixP->fx_file, fixP->fx_line,
18121 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18122 (long) value);
18123 break;
18124 }
b99bd4ef 18125
c19d1205
ZW
18126 /* Replace the first operand in the 2nd instruction (which
18127 is the PC) with the destination register. We have
18128 already added in the PC in the first instruction and we
18129 do not want to do it again. */
18130 newinsn &= ~ 0xf0000;
18131 newinsn |= ((newinsn & 0x0f000) << 4);
18132 }
b99bd4ef 18133
c19d1205
ZW
18134 newimm |= (temp & 0xfffff000);
18135 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 18136
c19d1205
ZW
18137 highpart |= (newinsn & 0xfffff000);
18138 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
18139 }
18140 break;
b99bd4ef 18141
c19d1205 18142 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS
18143 if (!fixP->fx_done && seg->use_rela_p)
18144 value = 0;
18145
c19d1205
ZW
18146 case BFD_RELOC_ARM_LITERAL:
18147 sign = value >= 0;
b99bd4ef 18148
c19d1205
ZW
18149 if (value < 0)
18150 value = - value;
b99bd4ef 18151
c19d1205 18152 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 18153 {
c19d1205
ZW
18154 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
18155 as_bad_where (fixP->fx_file, fixP->fx_line,
18156 _("invalid literal constant: pool needs to be closer"));
18157 else
18158 as_bad_where (fixP->fx_file, fixP->fx_line,
18159 _("bad immediate value for offset (%ld)"),
18160 (long) value);
18161 break;
f03698e6
RE
18162 }
18163
c19d1205
ZW
18164 newval = md_chars_to_number (buf, INSN_SIZE);
18165 newval &= 0xff7ff000;
18166 newval |= value | (sign ? INDEX_UP : 0);
18167 md_number_to_chars (buf, newval, INSN_SIZE);
18168 break;
b99bd4ef 18169
c19d1205
ZW
18170 case BFD_RELOC_ARM_OFFSET_IMM8:
18171 case BFD_RELOC_ARM_HWLITERAL:
18172 sign = value >= 0;
b99bd4ef 18173
c19d1205
ZW
18174 if (value < 0)
18175 value = - value;
b99bd4ef 18176
c19d1205 18177 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 18178 {
c19d1205
ZW
18179 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
18180 as_bad_where (fixP->fx_file, fixP->fx_line,
18181 _("invalid literal constant: pool needs to be closer"));
18182 else
f9d4405b 18183 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
c19d1205
ZW
18184 (long) value);
18185 break;
b99bd4ef
NC
18186 }
18187
c19d1205
ZW
18188 newval = md_chars_to_number (buf, INSN_SIZE);
18189 newval &= 0xff7ff0f0;
18190 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
18191 md_number_to_chars (buf, newval, INSN_SIZE);
18192 break;
b99bd4ef 18193
c19d1205
ZW
18194 case BFD_RELOC_ARM_T32_OFFSET_U8:
18195 if (value < 0 || value > 1020 || value % 4 != 0)
18196 as_bad_where (fixP->fx_file, fixP->fx_line,
18197 _("bad immediate value for offset (%ld)"), (long) value);
18198 value /= 4;
b99bd4ef 18199
c19d1205 18200 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW
18201 newval |= value;
18202 md_number_to_chars (buf+2, newval, THUMB_SIZE);
18203 break;
b99bd4ef 18204
c19d1205
ZW
18205 case BFD_RELOC_ARM_T32_OFFSET_IMM:
18206 /* This is a complicated relocation used for all varieties of Thumb32
18207 load/store instruction with immediate offset:
18208
18209 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18210 *4, optional writeback(W)
18211 (doubleword load/store)
18212
18213 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18214 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18215 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18216 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18217 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18218
18219 Uppercase letters indicate bits that are already encoded at
18220 this point. Lowercase letters are our problem. For the
18221 second block of instructions, the secondary opcode nybble
18222 (bits 8..11) is present, and bit 23 is zero, even if this is
18223 a PC-relative operation. */
18224 newval = md_chars_to_number (buf, THUMB_SIZE);
18225 newval <<= 16;
18226 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 18227
c19d1205 18228 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 18229 {
c19d1205
ZW
18230 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18231 if (value >= 0)
18232 newval |= (1 << 23);
18233 else
18234 value = -value;
18235 if (value % 4 != 0)
18236 {
18237 as_bad_where (fixP->fx_file, fixP->fx_line,
18238 _("offset not a multiple of 4"));
18239 break;
18240 }
18241 value /= 4;
216d22bc 18242 if (value > 0xff)
c19d1205
ZW
18243 {
18244 as_bad_where (fixP->fx_file, fixP->fx_line,
18245 _("offset out of range"));
18246 break;
18247 }
18248 newval &= ~0xff;
b99bd4ef 18249 }
c19d1205 18250 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 18251 {
c19d1205
ZW
18252 /* PC-relative, 12-bit offset. */
18253 if (value >= 0)
18254 newval |= (1 << 23);
18255 else
18256 value = -value;
216d22bc 18257 if (value > 0xfff)
c19d1205
ZW
18258 {
18259 as_bad_where (fixP->fx_file, fixP->fx_line,
18260 _("offset out of range"));
18261 break;
18262 }
18263 newval &= ~0xfff;
b99bd4ef 18264 }
c19d1205 18265 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 18266 {
c19d1205
ZW
18267 /* Writeback: 8-bit, +/- offset. */
18268 if (value >= 0)
18269 newval |= (1 << 9);
18270 else
18271 value = -value;
216d22bc 18272 if (value > 0xff)
c19d1205
ZW
18273 {
18274 as_bad_where (fixP->fx_file, fixP->fx_line,
18275 _("offset out of range"));
18276 break;
18277 }
18278 newval &= ~0xff;
b99bd4ef 18279 }
c19d1205 18280 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 18281 {
c19d1205 18282 /* T-instruction: positive 8-bit offset. */
216d22bc 18283 if (value < 0 || value > 0xff)
b99bd4ef 18284 {
c19d1205
ZW
18285 as_bad_where (fixP->fx_file, fixP->fx_line,
18286 _("offset out of range"));
18287 break;
b99bd4ef 18288 }
c19d1205
ZW
18289 newval &= ~0xff;
18290 newval |= value;
b99bd4ef
NC
18291 }
18292 else
b99bd4ef 18293 {
c19d1205
ZW
18294 /* Positive 12-bit or negative 8-bit offset. */
18295 int limit;
18296 if (value >= 0)
b99bd4ef 18297 {
c19d1205
ZW
18298 newval |= (1 << 23);
18299 limit = 0xfff;
18300 }
18301 else
18302 {
18303 value = -value;
18304 limit = 0xff;
18305 }
18306 if (value > limit)
18307 {
18308 as_bad_where (fixP->fx_file, fixP->fx_line,
18309 _("offset out of range"));
18310 break;
b99bd4ef 18311 }
c19d1205 18312 newval &= ~limit;
b99bd4ef 18313 }
b99bd4ef 18314
c19d1205
ZW
18315 newval |= value;
18316 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
18317 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
18318 break;
404ff6b5 18319
c19d1205
ZW
18320 case BFD_RELOC_ARM_SHIFT_IMM:
18321 newval = md_chars_to_number (buf, INSN_SIZE);
18322 if (((unsigned long) value) > 32
18323 || (value == 32
18324 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
18325 {
18326 as_bad_where (fixP->fx_file, fixP->fx_line,
18327 _("shift expression is too large"));
18328 break;
18329 }
404ff6b5 18330
c19d1205
ZW
18331 if (value == 0)
18332 /* Shifts of zero must be done as lsl. */
18333 newval &= ~0x60;
18334 else if (value == 32)
18335 value = 0;
18336 newval &= 0xfffff07f;
18337 newval |= (value & 0x1f) << 7;
18338 md_number_to_chars (buf, newval, INSN_SIZE);
18339 break;
404ff6b5 18340
c19d1205 18341 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 18342 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 18343 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 18344 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW
18345 /* We claim that this fixup has been processed here,
18346 even if in fact we generate an error because we do
18347 not have a reloc for it, so tc_gen_reloc will reject it. */
18348 fixP->fx_done = 1;
404ff6b5 18349
c19d1205
ZW
18350 if (fixP->fx_addsy
18351 && ! S_IS_DEFINED (fixP->fx_addsy))
18352 {
18353 as_bad_where (fixP->fx_file, fixP->fx_line,
18354 _("undefined symbol %s used as an immediate value"),
18355 S_GET_NAME (fixP->fx_addsy));
18356 break;
18357 }
404ff6b5 18358
c19d1205
ZW
18359 newval = md_chars_to_number (buf, THUMB_SIZE);
18360 newval <<= 16;
18361 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 18362
16805f35
PB
18363 newimm = FAIL;
18364 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
18365 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB
18366 {
18367 newimm = encode_thumb32_immediate (value);
18368 if (newimm == (unsigned int) FAIL)
18369 newimm = thumb32_negate_data_op (&newval, value);
18370 }
16805f35
PB
18371 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
18372 && newimm == (unsigned int) FAIL)
92e90b6e 18373 {
16805f35
PB
18374 /* Turn add/sum into addw/subw. */
18375 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18376 newval = (newval & 0xfeffffff) | 0x02000000;
18377
e9f89963
PB
18378 /* 12 bit immediate for addw/subw. */
18379 if (value < 0)
18380 {
18381 value = -value;
18382 newval ^= 0x00a00000;
18383 }
92e90b6e
PB
18384 if (value > 0xfff)
18385 newimm = (unsigned int) FAIL;
18386 else
18387 newimm = value;
18388 }
cc8a6dd0 18389
c19d1205 18390 if (newimm == (unsigned int)FAIL)
3631a3c8 18391 {
c19d1205
ZW
18392 as_bad_where (fixP->fx_file, fixP->fx_line,
18393 _("invalid constant (%lx) after fixup"),
18394 (unsigned long) value);
18395 break;
3631a3c8
NC
18396 }
18397
c19d1205
ZW
18398 newval |= (newimm & 0x800) << 15;
18399 newval |= (newimm & 0x700) << 4;
18400 newval |= (newimm & 0x0ff);
cc8a6dd0 18401
c19d1205
ZW
18402 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
18403 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
18404 break;
a737bd4d 18405
3eb17e6b 18406 case BFD_RELOC_ARM_SMC:
c19d1205
ZW
18407 if (((unsigned long) value) > 0xffff)
18408 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 18409 _("invalid smc expression"));
2fc8bdac 18410 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
18411 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
18412 md_number_to_chars (buf, newval, INSN_SIZE);
18413 break;
a737bd4d 18414
c19d1205 18415 case BFD_RELOC_ARM_SWI:
adbaf948 18416 if (fixP->tc_fix_data != 0)
c19d1205
ZW
18417 {
18418 if (((unsigned long) value) > 0xff)
18419 as_bad_where (fixP->fx_file, fixP->fx_line,
18420 _("invalid swi expression"));
2fc8bdac 18421 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW
18422 newval |= value;
18423 md_number_to_chars (buf, newval, THUMB_SIZE);
18424 }
18425 else
18426 {
18427 if (((unsigned long) value) > 0x00ffffff)
18428 as_bad_where (fixP->fx_file, fixP->fx_line,
18429 _("invalid swi expression"));
2fc8bdac 18430 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW
18431 newval |= value;
18432 md_number_to_chars (buf, newval, INSN_SIZE);
18433 }
18434 break;
a737bd4d 18435
c19d1205
ZW
18436 case BFD_RELOC_ARM_MULTI:
18437 if (((unsigned long) value) > 0xffff)
18438 as_bad_where (fixP->fx_file, fixP->fx_line,
18439 _("invalid expression in load/store multiple"));
18440 newval = value | md_chars_to_number (buf, INSN_SIZE);
18441 md_number_to_chars (buf, newval, INSN_SIZE);
18442 break;
a737bd4d 18443
c19d1205 18444#ifdef OBJ_ELF
39b41c9c
PB
18445 case BFD_RELOC_ARM_PCREL_CALL:
18446 newval = md_chars_to_number (buf, INSN_SIZE);
18447 if ((newval & 0xf0000000) == 0xf0000000)
18448 temp = 1;
18449 else
18450 temp = 3;
18451 goto arm_branch_common;
18452
18453 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 18454 case BFD_RELOC_ARM_PLT32:
c19d1205 18455#endif
39b41c9c
PB
18456 case BFD_RELOC_ARM_PCREL_BRANCH:
18457 temp = 3;
18458 goto arm_branch_common;
a737bd4d 18459
39b41c9c
PB
18460 case BFD_RELOC_ARM_PCREL_BLX:
18461 temp = 1;
18462 arm_branch_common:
c19d1205 18463 /* We are going to store value (shifted right by two) in the
39b41c9c
PB
18464 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18465 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18466 also be be clear. */
18467 if (value & temp)
c19d1205 18468 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW
18469 _("misaligned branch destination"));
18470 if ((value & (offsetT)0xfe000000) != (offsetT)0
18471 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
18472 as_bad_where (fixP->fx_file, fixP->fx_line,
18473 _("branch out of range"));
a737bd4d 18474
2fc8bdac 18475 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 18476 {
2fc8bdac
ZW
18477 newval = md_chars_to_number (buf, INSN_SIZE);
18478 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB
18479 /* Set the H bit on BLX instructions. */
18480 if (temp == 1)
18481 {
18482 if (value & 2)
18483 newval |= 0x01000000;
18484 else
18485 newval &= ~0x01000000;
18486 }
2fc8bdac 18487 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 18488 }
c19d1205 18489 break;
a737bd4d 18490
25fe350b
MS
18491 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
18492 /* CBZ can only branch forward. */
a737bd4d 18493
738755b0
MS
18494 /* Attempts to use CBZ to branch to the next instruction
18495 (which, strictly speaking, are prohibited) will be turned into
18496 no-ops.
18497
18498 FIXME: It may be better to remove the instruction completely and
18499 perform relaxation. */
18500 if (value == -2)
2fc8bdac
ZW
18501 {
18502 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 18503 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW
18504 md_number_to_chars (buf, newval, THUMB_SIZE);
18505 }
738755b0
MS
18506 else
18507 {
18508 if (value & ~0x7e)
18509 as_bad_where (fixP->fx_file, fixP->fx_line,
18510 _("branch out of range"));
18511
18512 if (fixP->fx_done || !seg->use_rela_p)
18513 {
18514 newval = md_chars_to_number (buf, THUMB_SIZE);
18515 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
18516 md_number_to_chars (buf, newval, THUMB_SIZE);
18517 }
18518 }
c19d1205 18519 break;
a737bd4d 18520
c19d1205 18521 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac
ZW
18522 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
18523 as_bad_where (fixP->fx_file, fixP->fx_line,
18524 _("branch out of range"));
a737bd4d 18525
2fc8bdac
ZW
18526 if (fixP->fx_done || !seg->use_rela_p)
18527 {
18528 newval = md_chars_to_number (buf, THUMB_SIZE);
18529 newval |= (value & 0x1ff) >> 1;
18530 md_number_to_chars (buf, newval, THUMB_SIZE);
18531 }
c19d1205 18532 break;
a737bd4d 18533
c19d1205 18534 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac
ZW
18535 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
18536 as_bad_where (fixP->fx_file, fixP->fx_line,
18537 _("branch out of range"));
a737bd4d 18538
2fc8bdac
ZW
18539 if (fixP->fx_done || !seg->use_rela_p)
18540 {
18541 newval = md_chars_to_number (buf, THUMB_SIZE);
18542 newval |= (value & 0xfff) >> 1;
18543 md_number_to_chars (buf, newval, THUMB_SIZE);
18544 }
c19d1205 18545 break;
a737bd4d 18546
c19d1205 18547 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac
ZW
18548 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
18549 as_bad_where (fixP->fx_file, fixP->fx_line,
18550 _("conditional branch out of range"));
404ff6b5 18551
2fc8bdac
ZW
18552 if (fixP->fx_done || !seg->use_rela_p)
18553 {
18554 offsetT newval2;
18555 addressT S, J1, J2, lo, hi;
404ff6b5 18556
2fc8bdac
ZW
18557 S = (value & 0x00100000) >> 20;
18558 J2 = (value & 0x00080000) >> 19;
18559 J1 = (value & 0x00040000) >> 18;
18560 hi = (value & 0x0003f000) >> 12;
18561 lo = (value & 0x00000ffe) >> 1;
6c43fab6 18562
2fc8bdac
ZW
18563 newval = md_chars_to_number (buf, THUMB_SIZE);
18564 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18565 newval |= (S << 10) | hi;
18566 newval2 |= (J1 << 13) | (J2 << 11) | lo;
18567 md_number_to_chars (buf, newval, THUMB_SIZE);
18568 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18569 }
c19d1205 18570 break;
6c43fab6 18571
c19d1205
ZW
18572 case BFD_RELOC_THUMB_PCREL_BLX:
18573 case BFD_RELOC_THUMB_PCREL_BRANCH23:
2fc8bdac
ZW
18574 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
18575 as_bad_where (fixP->fx_file, fixP->fx_line,
18576 _("branch out of range"));
404ff6b5 18577
2fc8bdac
ZW
18578 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
18579 /* For a BLX instruction, make sure that the relocation is rounded up
18580 to a word boundary. This follows the semantics of the instruction
18581 which specifies that bit 1 of the target address will come from bit
18582 1 of the base address. */
18583 value = (value + 1) & ~ 1;
404ff6b5 18584
2fc8bdac 18585 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 18586 {
2fc8bdac
ZW
18587 offsetT newval2;
18588
18589 newval = md_chars_to_number (buf, THUMB_SIZE);
18590 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18591 newval |= (value & 0x7fffff) >> 12;
18592 newval2 |= (value & 0xfff) >> 1;
18593 md_number_to_chars (buf, newval, THUMB_SIZE);
18594 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
c19d1205 18595 }
c19d1205 18596 break;
404ff6b5 18597
c19d1205 18598 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac
ZW
18599 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
18600 as_bad_where (fixP->fx_file, fixP->fx_line,
18601 _("branch out of range"));
6c43fab6 18602
2fc8bdac
ZW
18603 if (fixP->fx_done || !seg->use_rela_p)
18604 {
18605 offsetT newval2;
18606 addressT S, I1, I2, lo, hi;
6c43fab6 18607
2fc8bdac
ZW
18608 S = (value & 0x01000000) >> 24;
18609 I1 = (value & 0x00800000) >> 23;
18610 I2 = (value & 0x00400000) >> 22;
18611 hi = (value & 0x003ff000) >> 12;
18612 lo = (value & 0x00000ffe) >> 1;
6c43fab6 18613
2fc8bdac
ZW
18614 I1 = !(I1 ^ S);
18615 I2 = !(I2 ^ S);
a737bd4d 18616
2fc8bdac
ZW
18617 newval = md_chars_to_number (buf, THUMB_SIZE);
18618 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18619 newval |= (S << 10) | hi;
18620 newval2 |= (I1 << 13) | (I2 << 11) | lo;
18621 md_number_to_chars (buf, newval, THUMB_SIZE);
18622 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18623 }
18624 break;
a737bd4d 18625
2fc8bdac
ZW
18626 case BFD_RELOC_8:
18627 if (fixP->fx_done || !seg->use_rela_p)
18628 md_number_to_chars (buf, value, 1);
c19d1205 18629 break;
a737bd4d 18630
c19d1205 18631 case BFD_RELOC_16:
2fc8bdac 18632 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 18633 md_number_to_chars (buf, value, 2);
c19d1205 18634 break;
a737bd4d 18635
c19d1205
ZW
18636#ifdef OBJ_ELF
18637 case BFD_RELOC_ARM_TLS_GD32:
18638 case BFD_RELOC_ARM_TLS_LE32:
18639 case BFD_RELOC_ARM_TLS_IE32:
18640 case BFD_RELOC_ARM_TLS_LDM32:
18641 case BFD_RELOC_ARM_TLS_LDO32:
18642 S_SET_THREAD_LOCAL (fixP->fx_addsy);
18643 /* fall through */
6c43fab6 18644
c19d1205
ZW
18645 case BFD_RELOC_ARM_GOT32:
18646 case BFD_RELOC_ARM_GOTOFF:
18647 case BFD_RELOC_ARM_TARGET2:
2fc8bdac
ZW
18648 if (fixP->fx_done || !seg->use_rela_p)
18649 md_number_to_chars (buf, 0, 4);
c19d1205
ZW
18650 break;
18651#endif
6c43fab6 18652
c19d1205
ZW
18653 case BFD_RELOC_RVA:
18654 case BFD_RELOC_32:
18655 case BFD_RELOC_ARM_TARGET1:
18656 case BFD_RELOC_ARM_ROSEGREL32:
18657 case BFD_RELOC_ARM_SBREL32:
18658 case BFD_RELOC_32_PCREL:
f0927246
NC
18659#ifdef TE_PE
18660 case BFD_RELOC_32_SECREL:
18661#endif
2fc8bdac 18662 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC
18663#ifdef TE_WINCE
18664 /* For WinCE we only do this for pcrel fixups. */
18665 if (fixP->fx_done || fixP->fx_pcrel)
18666#endif
18667 md_number_to_chars (buf, value, 4);
c19d1205 18668 break;
6c43fab6 18669
c19d1205
ZW
18670#ifdef OBJ_ELF
18671 case BFD_RELOC_ARM_PREL31:
2fc8bdac 18672 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW
18673 {
18674 newval = md_chars_to_number (buf, 4) & 0x80000000;
18675 if ((value ^ (value >> 1)) & 0x40000000)
18676 {
18677 as_bad_where (fixP->fx_file, fixP->fx_line,
18678 _("rel31 relocation overflow"));
18679 }
18680 newval |= value & 0x7fffffff;
18681 md_number_to_chars (buf, newval, 4);
18682 }
18683 break;
c19d1205 18684#endif
a737bd4d 18685
c19d1205 18686 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 18687 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
c19d1205
ZW
18688 if (value < -1023 || value > 1023 || (value & 3))
18689 as_bad_where (fixP->fx_file, fixP->fx_line,
18690 _("co-processor offset out of range"));
18691 cp_off_common:
18692 sign = value >= 0;
18693 if (value < 0)
18694 value = -value;
8f06b2d8
PB
18695 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18696 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18697 newval = md_chars_to_number (buf, INSN_SIZE);
18698 else
18699 newval = get_thumb32_insn (buf);
18700 newval &= 0xff7fff00;
c19d1205 18701 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
8f06b2d8
PB
18702 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18703 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18704 md_number_to_chars (buf, newval, INSN_SIZE);
18705 else
18706 put_thumb32_insn (buf, newval);
c19d1205 18707 break;
a737bd4d 18708
c19d1205 18709 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 18710 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW
18711 if (value < -255 || value > 255)
18712 as_bad_where (fixP->fx_file, fixP->fx_line,
18713 _("co-processor offset out of range"));
df7849c5 18714 value *= 4;
c19d1205 18715 goto cp_off_common;
6c43fab6 18716
c19d1205
ZW
18717 case BFD_RELOC_ARM_THUMB_OFFSET:
18718 newval = md_chars_to_number (buf, THUMB_SIZE);
18719 /* Exactly what ranges, and where the offset is inserted depends
18720 on the type of instruction, we can establish this from the
18721 top 4 bits. */
18722 switch (newval >> 12)
18723 {
18724 case 4: /* PC load. */
18725 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18726 forced to zero for these loads; md_pcrel_from has already
18727 compensated for this. */
18728 if (value & 3)
18729 as_bad_where (fixP->fx_file, fixP->fx_line,
18730 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC
18731 (((unsigned long) fixP->fx_frag->fr_address
18732 + (unsigned long) fixP->fx_where) & ~3)
18733 + (unsigned long) value);
a737bd4d 18734
c19d1205
ZW
18735 if (value & ~0x3fc)
18736 as_bad_where (fixP->fx_file, fixP->fx_line,
18737 _("invalid offset, value too big (0x%08lX)"),
18738 (long) value);
a737bd4d 18739
c19d1205
ZW
18740 newval |= value >> 2;
18741 break;
a737bd4d 18742
c19d1205
ZW
18743 case 9: /* SP load/store. */
18744 if (value & ~0x3fc)
18745 as_bad_where (fixP->fx_file, fixP->fx_line,
18746 _("invalid offset, value too big (0x%08lX)"),
18747 (long) value);
18748 newval |= value >> 2;
18749 break;
6c43fab6 18750
c19d1205
ZW
18751 case 6: /* Word load/store. */
18752 if (value & ~0x7c)
18753 as_bad_where (fixP->fx_file, fixP->fx_line,
18754 _("invalid offset, value too big (0x%08lX)"),
18755 (long) value);
18756 newval |= value << 4; /* 6 - 2. */
18757 break;
a737bd4d 18758
c19d1205
ZW
18759 case 7: /* Byte load/store. */
18760 if (value & ~0x1f)
18761 as_bad_where (fixP->fx_file, fixP->fx_line,
18762 _("invalid offset, value too big (0x%08lX)"),
18763 (long) value);
18764 newval |= value << 6;
18765 break;
a737bd4d 18766
c19d1205
ZW
18767 case 8: /* Halfword load/store. */
18768 if (value & ~0x3e)
18769 as_bad_where (fixP->fx_file, fixP->fx_line,
18770 _("invalid offset, value too big (0x%08lX)"),
18771 (long) value);
18772 newval |= value << 5; /* 6 - 1. */
18773 break;
a737bd4d 18774
c19d1205
ZW
18775 default:
18776 as_bad_where (fixP->fx_file, fixP->fx_line,
18777 "Unable to process relocation for thumb opcode: %lx",
18778 (unsigned long) newval);
18779 break;
18780 }
18781 md_number_to_chars (buf, newval, THUMB_SIZE);
18782 break;
a737bd4d 18783
c19d1205
ZW
18784 case BFD_RELOC_ARM_THUMB_ADD:
18785 /* This is a complicated relocation, since we use it for all of
18786 the following immediate relocations:
a737bd4d 18787
c19d1205
ZW
18788 3bit ADD/SUB
18789 8bit ADD/SUB
18790 9bit ADD/SUB SP word-aligned
18791 10bit ADD PC/SP word-aligned
a737bd4d 18792
c19d1205
ZW
18793 The type of instruction being processed is encoded in the
18794 instruction field:
a737bd4d 18795
c19d1205
ZW
18796 0x8000 SUB
18797 0x00F0 Rd
18798 0x000F Rs
18799 */
18800 newval = md_chars_to_number (buf, THUMB_SIZE);
18801 {
18802 int rd = (newval >> 4) & 0xf;
18803 int rs = newval & 0xf;
18804 int subtract = !!(newval & 0x8000);
a737bd4d 18805
c19d1205
ZW
18806 /* Check for HI regs, only very restricted cases allowed:
18807 Adjusting SP, and using PC or SP to get an address. */
18808 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
18809 || (rs > 7 && rs != REG_SP && rs != REG_PC))
18810 as_bad_where (fixP->fx_file, fixP->fx_line,
18811 _("invalid Hi register with immediate"));
a737bd4d 18812
c19d1205
ZW
18813 /* If value is negative, choose the opposite instruction. */
18814 if (value < 0)
18815 {
18816 value = -value;
18817 subtract = !subtract;
18818 if (value < 0)
18819 as_bad_where (fixP->fx_file, fixP->fx_line,
18820 _("immediate value out of range"));
18821 }
a737bd4d 18822
c19d1205
ZW
18823 if (rd == REG_SP)
18824 {
18825 if (value & ~0x1fc)
18826 as_bad_where (fixP->fx_file, fixP->fx_line,
18827 _("invalid immediate for stack address calculation"));
18828 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
18829 newval |= value >> 2;
18830 }
18831 else if (rs == REG_PC || rs == REG_SP)
18832 {
18833 if (subtract || value & ~0x3fc)
18834 as_bad_where (fixP->fx_file, fixP->fx_line,
18835 _("invalid immediate for address calculation (value = 0x%08lX)"),
18836 (unsigned long) value);
18837 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
18838 newval |= rd << 8;
18839 newval |= value >> 2;
18840 }
18841 else if (rs == rd)
18842 {
18843 if (value & ~0xff)
18844 as_bad_where (fixP->fx_file, fixP->fx_line,
18845 _("immediate value out of range"));
18846 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
18847 newval |= (rd << 8) | value;
18848 }
18849 else
18850 {
18851 if (value & ~0x7)
18852 as_bad_where (fixP->fx_file, fixP->fx_line,
18853 _("immediate value out of range"));
18854 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
18855 newval |= rd | (rs << 3) | (value << 6);
18856 }
18857 }
18858 md_number_to_chars (buf, newval, THUMB_SIZE);
18859 break;
a737bd4d 18860
c19d1205
ZW
18861 case BFD_RELOC_ARM_THUMB_IMM:
18862 newval = md_chars_to_number (buf, THUMB_SIZE);
18863 if (value < 0 || value > 255)
18864 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 18865 _("invalid immediate: %ld is out of range"),
c19d1205
ZW
18866 (long) value);
18867 newval |= value;
18868 md_number_to_chars (buf, newval, THUMB_SIZE);
18869 break;
a737bd4d 18870
c19d1205
ZW
18871 case BFD_RELOC_ARM_THUMB_SHIFT:
18872 /* 5bit shift value (0..32). LSL cannot take 32. */
18873 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
18874 temp = newval & 0xf800;
18875 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
18876 as_bad_where (fixP->fx_file, fixP->fx_line,
18877 _("invalid shift value: %ld"), (long) value);
18878 /* Shifts of zero must be encoded as LSL. */
18879 if (value == 0)
18880 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
18881 /* Shifts of 32 are encoded as zero. */
18882 else if (value == 32)
18883 value = 0;
18884 newval |= value << 6;
18885 md_number_to_chars (buf, newval, THUMB_SIZE);
18886 break;
a737bd4d 18887
c19d1205
ZW
18888 case BFD_RELOC_VTABLE_INHERIT:
18889 case BFD_RELOC_VTABLE_ENTRY:
18890 fixP->fx_done = 0;
18891 return;
6c43fab6 18892
b6895b4f
PB
18893 case BFD_RELOC_ARM_MOVW:
18894 case BFD_RELOC_ARM_MOVT:
18895 case BFD_RELOC_ARM_THUMB_MOVW:
18896 case BFD_RELOC_ARM_THUMB_MOVT:
18897 if (fixP->fx_done || !seg->use_rela_p)
18898 {
18899 /* REL format relocations are limited to a 16-bit addend. */
18900 if (!fixP->fx_done)
18901 {
39623e12 18902 if (value < -0x8000 || value > 0x7fff)
b6895b4f 18903 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 18904 _("offset out of range"));
b6895b4f
PB
18905 }
18906 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
18907 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18908 {
18909 value >>= 16;
18910 }
18911
18912 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
18913 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18914 {
18915 newval = get_thumb32_insn (buf);
18916 newval &= 0xfbf08f00;
18917 newval |= (value & 0xf000) << 4;
18918 newval |= (value & 0x0800) << 15;
18919 newval |= (value & 0x0700) << 4;
18920 newval |= (value & 0x00ff);
18921 put_thumb32_insn (buf, newval);
18922 }
18923 else
18924 {
18925 newval = md_chars_to_number (buf, 4);
18926 newval &= 0xfff0f000;
18927 newval |= value & 0x0fff;
18928 newval |= (value & 0xf000) << 4;
18929 md_number_to_chars (buf, newval, 4);
18930 }
18931 }
18932 return;
18933
4962c51a
MS
18934 case BFD_RELOC_ARM_ALU_PC_G0_NC:
18935 case BFD_RELOC_ARM_ALU_PC_G0:
18936 case BFD_RELOC_ARM_ALU_PC_G1_NC:
18937 case BFD_RELOC_ARM_ALU_PC_G1:
18938 case BFD_RELOC_ARM_ALU_PC_G2:
18939 case BFD_RELOC_ARM_ALU_SB_G0_NC:
18940 case BFD_RELOC_ARM_ALU_SB_G0:
18941 case BFD_RELOC_ARM_ALU_SB_G1_NC:
18942 case BFD_RELOC_ARM_ALU_SB_G1:
18943 case BFD_RELOC_ARM_ALU_SB_G2:
18944 assert (!fixP->fx_done);
18945 if (!seg->use_rela_p)
18946 {
18947 bfd_vma insn;
18948 bfd_vma encoded_addend;
18949 bfd_vma addend_abs = abs (value);
18950
18951 /* Check that the absolute value of the addend can be
18952 expressed as an 8-bit constant plus a rotation. */
18953 encoded_addend = encode_arm_immediate (addend_abs);
18954 if (encoded_addend == (unsigned int) FAIL)
18955 as_bad_where (fixP->fx_file, fixP->fx_line,
18956 _("the offset 0x%08lX is not representable"),
495bde8e 18957 (unsigned long) addend_abs);
4962c51a
MS
18958
18959 /* Extract the instruction. */
18960 insn = md_chars_to_number (buf, INSN_SIZE);
18961
18962 /* If the addend is positive, use an ADD instruction.
18963 Otherwise use a SUB. Take care not to destroy the S bit. */
18964 insn &= 0xff1fffff;
18965 if (value < 0)
18966 insn |= 1 << 22;
18967 else
18968 insn |= 1 << 23;
18969
18970 /* Place the encoded addend into the first 12 bits of the
18971 instruction. */
18972 insn &= 0xfffff000;
18973 insn |= encoded_addend;
5f4273c7
NC
18974
18975 /* Update the instruction. */
4962c51a
MS
18976 md_number_to_chars (buf, insn, INSN_SIZE);
18977 }
18978 break;
18979
18980 case BFD_RELOC_ARM_LDR_PC_G0:
18981 case BFD_RELOC_ARM_LDR_PC_G1:
18982 case BFD_RELOC_ARM_LDR_PC_G2:
18983 case BFD_RELOC_ARM_LDR_SB_G0:
18984 case BFD_RELOC_ARM_LDR_SB_G1:
18985 case BFD_RELOC_ARM_LDR_SB_G2:
18986 assert (!fixP->fx_done);
18987 if (!seg->use_rela_p)
18988 {
18989 bfd_vma insn;
18990 bfd_vma addend_abs = abs (value);
18991
18992 /* Check that the absolute value of the addend can be
18993 encoded in 12 bits. */
18994 if (addend_abs >= 0x1000)
18995 as_bad_where (fixP->fx_file, fixP->fx_line,
18996 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
495bde8e 18997 (unsigned long) addend_abs);
4962c51a
MS
18998
18999 /* Extract the instruction. */
19000 insn = md_chars_to_number (buf, INSN_SIZE);
19001
19002 /* If the addend is negative, clear bit 23 of the instruction.
19003 Otherwise set it. */
19004 if (value < 0)
19005 insn &= ~(1 << 23);
19006 else
19007 insn |= 1 << 23;
19008
19009 /* Place the absolute value of the addend into the first 12 bits
19010 of the instruction. */
19011 insn &= 0xfffff000;
19012 insn |= addend_abs;
5f4273c7
NC
19013
19014 /* Update the instruction. */
4962c51a
MS
19015 md_number_to_chars (buf, insn, INSN_SIZE);
19016 }
19017 break;
19018
19019 case BFD_RELOC_ARM_LDRS_PC_G0:
19020 case BFD_RELOC_ARM_LDRS_PC_G1:
19021 case BFD_RELOC_ARM_LDRS_PC_G2:
19022 case BFD_RELOC_ARM_LDRS_SB_G0:
19023 case BFD_RELOC_ARM_LDRS_SB_G1:
19024 case BFD_RELOC_ARM_LDRS_SB_G2:
19025 assert (!fixP->fx_done);
19026 if (!seg->use_rela_p)
19027 {
19028 bfd_vma insn;
19029 bfd_vma addend_abs = abs (value);
19030
19031 /* Check that the absolute value of the addend can be
19032 encoded in 8 bits. */
19033 if (addend_abs >= 0x100)
19034 as_bad_where (fixP->fx_file, fixP->fx_line,
19035 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
495bde8e 19036 (unsigned long) addend_abs);
4962c51a
MS
19037
19038 /* Extract the instruction. */
19039 insn = md_chars_to_number (buf, INSN_SIZE);
19040
19041 /* If the addend is negative, clear bit 23 of the instruction.
19042 Otherwise set it. */
19043 if (value < 0)
19044 insn &= ~(1 << 23);
19045 else
19046 insn |= 1 << 23;
19047
19048 /* Place the first four bits of the absolute value of the addend
19049 into the first 4 bits of the instruction, and the remaining
19050 four into bits 8 .. 11. */
19051 insn &= 0xfffff0f0;
19052 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
5f4273c7
NC
19053
19054 /* Update the instruction. */
4962c51a
MS
19055 md_number_to_chars (buf, insn, INSN_SIZE);
19056 }
19057 break;
19058
19059 case BFD_RELOC_ARM_LDC_PC_G0:
19060 case BFD_RELOC_ARM_LDC_PC_G1:
19061 case BFD_RELOC_ARM_LDC_PC_G2:
19062 case BFD_RELOC_ARM_LDC_SB_G0:
19063 case BFD_RELOC_ARM_LDC_SB_G1:
19064 case BFD_RELOC_ARM_LDC_SB_G2:
19065 assert (!fixP->fx_done);
19066 if (!seg->use_rela_p)
19067 {
19068 bfd_vma insn;
19069 bfd_vma addend_abs = abs (value);
19070
19071 /* Check that the absolute value of the addend is a multiple of
19072 four and, when divided by four, fits in 8 bits. */
19073 if (addend_abs & 0x3)
19074 as_bad_where (fixP->fx_file, fixP->fx_line,
19075 _("bad offset 0x%08lX (must be word-aligned)"),
495bde8e 19076 (unsigned long) addend_abs);
4962c51a
MS
19077
19078 if ((addend_abs >> 2) > 0xff)
19079 as_bad_where (fixP->fx_file, fixP->fx_line,
19080 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
495bde8e 19081 (unsigned long) addend_abs);
4962c51a
MS
19082
19083 /* Extract the instruction. */
19084 insn = md_chars_to_number (buf, INSN_SIZE);
19085
19086 /* If the addend is negative, clear bit 23 of the instruction.
19087 Otherwise set it. */
19088 if (value < 0)
19089 insn &= ~(1 << 23);
19090 else
19091 insn |= 1 << 23;
19092
19093 /* Place the addend (divided by four) into the first eight
19094 bits of the instruction. */
19095 insn &= 0xfffffff0;
19096 insn |= addend_abs >> 2;
5f4273c7
NC
19097
19098 /* Update the instruction. */
4962c51a
MS
19099 md_number_to_chars (buf, insn, INSN_SIZE);
19100 }
19101 break;
19102
845b51d6
PB
19103 case BFD_RELOC_ARM_V4BX:
19104 /* This will need to go in the object file. */
19105 fixP->fx_done = 0;
19106 break;
19107
c19d1205
ZW
19108 case BFD_RELOC_UNUSED:
19109 default:
19110 as_bad_where (fixP->fx_file, fixP->fx_line,
19111 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
19112 }
6c43fab6
RE
19113}
19114
c19d1205
ZW
19115/* Translate internal representation of relocation info to BFD target
19116 format. */
a737bd4d 19117
c19d1205 19118arelent *
00a97672 19119tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 19120{
c19d1205
ZW
19121 arelent * reloc;
19122 bfd_reloc_code_real_type code;
a737bd4d 19123
c19d1205 19124 reloc = xmalloc (sizeof (arelent));
a737bd4d 19125
c19d1205
ZW
19126 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
19127 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
19128 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 19129
2fc8bdac 19130 if (fixp->fx_pcrel)
00a97672
RS
19131 {
19132 if (section->use_rela_p)
19133 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
19134 else
19135 fixp->fx_offset = reloc->address;
19136 }
c19d1205 19137 reloc->addend = fixp->fx_offset;
a737bd4d 19138
c19d1205 19139 switch (fixp->fx_r_type)
a737bd4d 19140 {
c19d1205
ZW
19141 case BFD_RELOC_8:
19142 if (fixp->fx_pcrel)
19143 {
19144 code = BFD_RELOC_8_PCREL;
19145 break;
19146 }
a737bd4d 19147
c19d1205
ZW
19148 case BFD_RELOC_16:
19149 if (fixp->fx_pcrel)
19150 {
19151 code = BFD_RELOC_16_PCREL;
19152 break;
19153 }
6c43fab6 19154
c19d1205
ZW
19155 case BFD_RELOC_32:
19156 if (fixp->fx_pcrel)
19157 {
19158 code = BFD_RELOC_32_PCREL;
19159 break;
19160 }
a737bd4d 19161
b6895b4f
PB
19162 case BFD_RELOC_ARM_MOVW:
19163 if (fixp->fx_pcrel)
19164 {
19165 code = BFD_RELOC_ARM_MOVW_PCREL;
19166 break;
19167 }
19168
19169 case BFD_RELOC_ARM_MOVT:
19170 if (fixp->fx_pcrel)
19171 {
19172 code = BFD_RELOC_ARM_MOVT_PCREL;
19173 break;
19174 }
19175
19176 case BFD_RELOC_ARM_THUMB_MOVW:
19177 if (fixp->fx_pcrel)
19178 {
19179 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
19180 break;
19181 }
19182
19183 case BFD_RELOC_ARM_THUMB_MOVT:
19184 if (fixp->fx_pcrel)
19185 {
19186 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
19187 break;
19188 }
19189
c19d1205
ZW
19190 case BFD_RELOC_NONE:
19191 case BFD_RELOC_ARM_PCREL_BRANCH:
19192 case BFD_RELOC_ARM_PCREL_BLX:
19193 case BFD_RELOC_RVA:
19194 case BFD_RELOC_THUMB_PCREL_BRANCH7:
19195 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19196 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19197 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19198 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19199 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19200 case BFD_RELOC_THUMB_PCREL_BLX:
19201 case BFD_RELOC_VTABLE_ENTRY:
19202 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC
19203#ifdef TE_PE
19204 case BFD_RELOC_32_SECREL:
19205#endif
c19d1205
ZW
19206 code = fixp->fx_r_type;
19207 break;
a737bd4d 19208
c19d1205
ZW
19209 case BFD_RELOC_ARM_LITERAL:
19210 case BFD_RELOC_ARM_HWLITERAL:
19211 /* If this is called then the a literal has
19212 been referenced across a section boundary. */
19213 as_bad_where (fixp->fx_file, fixp->fx_line,
19214 _("literal referenced across section boundary"));
19215 return NULL;
a737bd4d 19216
c19d1205
ZW
19217#ifdef OBJ_ELF
19218 case BFD_RELOC_ARM_GOT32:
19219 case BFD_RELOC_ARM_GOTOFF:
19220 case BFD_RELOC_ARM_PLT32:
19221 case BFD_RELOC_ARM_TARGET1:
19222 case BFD_RELOC_ARM_ROSEGREL32:
19223 case BFD_RELOC_ARM_SBREL32:
19224 case BFD_RELOC_ARM_PREL31:
19225 case BFD_RELOC_ARM_TARGET2:
19226 case BFD_RELOC_ARM_TLS_LE32:
19227 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB
19228 case BFD_RELOC_ARM_PCREL_CALL:
19229 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS
19230 case BFD_RELOC_ARM_ALU_PC_G0_NC:
19231 case BFD_RELOC_ARM_ALU_PC_G0:
19232 case BFD_RELOC_ARM_ALU_PC_G1_NC:
19233 case BFD_RELOC_ARM_ALU_PC_G1:
19234 case BFD_RELOC_ARM_ALU_PC_G2:
19235 case BFD_RELOC_ARM_LDR_PC_G0:
19236 case BFD_RELOC_ARM_LDR_PC_G1:
19237 case BFD_RELOC_ARM_LDR_PC_G2:
19238 case BFD_RELOC_ARM_LDRS_PC_G0:
19239 case BFD_RELOC_ARM_LDRS_PC_G1:
19240 case BFD_RELOC_ARM_LDRS_PC_G2:
19241 case BFD_RELOC_ARM_LDC_PC_G0:
19242 case BFD_RELOC_ARM_LDC_PC_G1:
19243 case BFD_RELOC_ARM_LDC_PC_G2:
19244 case BFD_RELOC_ARM_ALU_SB_G0_NC:
19245 case BFD_RELOC_ARM_ALU_SB_G0:
19246 case BFD_RELOC_ARM_ALU_SB_G1_NC:
19247 case BFD_RELOC_ARM_ALU_SB_G1:
19248 case BFD_RELOC_ARM_ALU_SB_G2:
19249 case BFD_RELOC_ARM_LDR_SB_G0:
19250 case BFD_RELOC_ARM_LDR_SB_G1:
19251 case BFD_RELOC_ARM_LDR_SB_G2:
19252 case BFD_RELOC_ARM_LDRS_SB_G0:
19253 case BFD_RELOC_ARM_LDRS_SB_G1:
19254 case BFD_RELOC_ARM_LDRS_SB_G2:
19255 case BFD_RELOC_ARM_LDC_SB_G0:
19256 case BFD_RELOC_ARM_LDC_SB_G1:
19257 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 19258 case BFD_RELOC_ARM_V4BX:
c19d1205
ZW
19259 code = fixp->fx_r_type;
19260 break;
a737bd4d 19261
c19d1205
ZW
19262 case BFD_RELOC_ARM_TLS_GD32:
19263 case BFD_RELOC_ARM_TLS_IE32:
19264 case BFD_RELOC_ARM_TLS_LDM32:
19265 /* BFD will include the symbol's address in the addend.
19266 But we don't want that, so subtract it out again here. */
19267 if (!S_IS_COMMON (fixp->fx_addsy))
19268 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
19269 code = fixp->fx_r_type;
19270 break;
19271#endif
a737bd4d 19272
c19d1205
ZW
19273 case BFD_RELOC_ARM_IMMEDIATE:
19274 as_bad_where (fixp->fx_file, fixp->fx_line,
19275 _("internal relocation (type: IMMEDIATE) not fixed up"));
19276 return NULL;
a737bd4d 19277
c19d1205
ZW
19278 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19279 as_bad_where (fixp->fx_file, fixp->fx_line,
19280 _("ADRL used for a symbol not defined in the same file"));
19281 return NULL;
a737bd4d 19282
c19d1205 19283 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS
19284 if (section->use_rela_p)
19285 {
19286 code = fixp->fx_r_type;
19287 break;
19288 }
19289
c19d1205
ZW
19290 if (fixp->fx_addsy != NULL
19291 && !S_IS_DEFINED (fixp->fx_addsy)
19292 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 19293 {
c19d1205
ZW
19294 as_bad_where (fixp->fx_file, fixp->fx_line,
19295 _("undefined local label `%s'"),
19296 S_GET_NAME (fixp->fx_addsy));
19297 return NULL;
a737bd4d
NC
19298 }
19299
c19d1205
ZW
19300 as_bad_where (fixp->fx_file, fixp->fx_line,
19301 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19302 return NULL;
a737bd4d 19303
c19d1205
ZW
19304 default:
19305 {
19306 char * type;
6c43fab6 19307
c19d1205
ZW
19308 switch (fixp->fx_r_type)
19309 {
19310 case BFD_RELOC_NONE: type = "NONE"; break;
19311 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
19312 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 19313 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW
19314 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
19315 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
19316 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
8f06b2d8 19317 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW
19318 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
19319 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
19320 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
19321 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
19322 default: type = _("<unknown>"); break;
19323 }
19324 as_bad_where (fixp->fx_file, fixp->fx_line,
19325 _("cannot represent %s relocation in this object file format"),
19326 type);
19327 return NULL;
19328 }
a737bd4d 19329 }
6c43fab6 19330
c19d1205
ZW
19331#ifdef OBJ_ELF
19332 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
19333 && GOT_symbol
19334 && fixp->fx_addsy == GOT_symbol)
19335 {
19336 code = BFD_RELOC_ARM_GOTPC;
19337 reloc->addend = fixp->fx_offset = reloc->address;
19338 }
19339#endif
6c43fab6 19340
c19d1205 19341 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 19342
c19d1205
ZW
19343 if (reloc->howto == NULL)
19344 {
19345 as_bad_where (fixp->fx_file, fixp->fx_line,
19346 _("cannot represent %s relocation in this object file format"),
19347 bfd_get_reloc_code_name (code));
19348 return NULL;
19349 }
6c43fab6 19350
c19d1205
ZW
19351 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19352 vtable entry to be used in the relocation's section offset. */
19353 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19354 reloc->address = fixp->fx_offset;
6c43fab6 19355
c19d1205 19356 return reloc;
6c43fab6
RE
19357}
19358
c19d1205 19359/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 19360
c19d1205
ZW
19361void
19362cons_fix_new_arm (fragS * frag,
19363 int where,
19364 int size,
19365 expressionS * exp)
6c43fab6 19366{
c19d1205
ZW
19367 bfd_reloc_code_real_type type;
19368 int pcrel = 0;
6c43fab6 19369
c19d1205
ZW
19370 /* Pick a reloc.
19371 FIXME: @@ Should look at CPU word size. */
19372 switch (size)
19373 {
19374 case 1:
19375 type = BFD_RELOC_8;
19376 break;
19377 case 2:
19378 type = BFD_RELOC_16;
19379 break;
19380 case 4:
19381 default:
19382 type = BFD_RELOC_32;
19383 break;
19384 case 8:
19385 type = BFD_RELOC_64;
19386 break;
19387 }
6c43fab6 19388
f0927246
NC
19389#ifdef TE_PE
19390 if (exp->X_op == O_secrel)
19391 {
19392 exp->X_op = O_symbol;
19393 type = BFD_RELOC_32_SECREL;
19394 }
19395#endif
19396
c19d1205
ZW
19397 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
19398}
6c43fab6 19399
c19d1205
ZW
19400#if defined OBJ_COFF || defined OBJ_ELF
19401void
19402arm_validate_fix (fixS * fixP)
6c43fab6 19403{
c19d1205
ZW
19404 /* If the destination of the branch is a defined symbol which does not have
19405 the THUMB_FUNC attribute, then we must be calling a function which has
19406 the (interfacearm) attribute. We look for the Thumb entry point to that
19407 function and change the branch to refer to that function instead. */
19408 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
19409 && fixP->fx_addsy != NULL
19410 && S_IS_DEFINED (fixP->fx_addsy)
19411 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 19412 {
c19d1205 19413 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 19414 }
c19d1205
ZW
19415}
19416#endif
6c43fab6 19417
c19d1205
ZW
19418int
19419arm_force_relocation (struct fix * fixp)
19420{
19421#if defined (OBJ_COFF) && defined (TE_PE)
19422 if (fixp->fx_r_type == BFD_RELOC_RVA)
19423 return 1;
19424#endif
6c43fab6 19425
c19d1205
ZW
19426 /* Resolve these relocations even if the symbol is extern or weak. */
19427 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
19428 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
0110f2b8 19429 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
16805f35 19430 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB
19431 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
19432 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
19433 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
c19d1205 19434 return 0;
a737bd4d 19435
4962c51a
MS
19436 /* Always leave these relocations for the linker. */
19437 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19438 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19439 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19440 return 1;
19441
f0291e4c
PB
19442 /* Always generate relocations against function symbols. */
19443 if (fixp->fx_r_type == BFD_RELOC_32
19444 && fixp->fx_addsy
19445 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
19446 return 1;
19447
c19d1205 19448 return generic_force_reloc (fixp);
404ff6b5
AH
19449}
19450
0ffdc86c 19451#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB
19452/* Relocations against function names must be left unadjusted,
19453 so that the linker can use this information to generate interworking
19454 stubs. The MIPS version of this function
c19d1205
ZW
19455 also prevents relocations that are mips-16 specific, but I do not
19456 know why it does this.
404ff6b5 19457
c19d1205
ZW
19458 FIXME:
19459 There is one other problem that ought to be addressed here, but
19460 which currently is not: Taking the address of a label (rather
19461 than a function) and then later jumping to that address. Such
19462 addresses also ought to have their bottom bit set (assuming that
19463 they reside in Thumb code), but at the moment they will not. */
404ff6b5 19464
c19d1205
ZW
19465bfd_boolean
19466arm_fix_adjustable (fixS * fixP)
404ff6b5 19467{
c19d1205
ZW
19468 if (fixP->fx_addsy == NULL)
19469 return 1;
404ff6b5 19470
e28387c3
PB
19471 /* Preserve relocations against symbols with function type. */
19472 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
19473 return 0;
19474
c19d1205
ZW
19475 if (THUMB_IS_FUNC (fixP->fx_addsy)
19476 && fixP->fx_subsy == NULL)
19477 return 0;
a737bd4d 19478
c19d1205
ZW
19479 /* We need the symbol name for the VTABLE entries. */
19480 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
19481 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19482 return 0;
404ff6b5 19483
c19d1205
ZW
19484 /* Don't allow symbols to be discarded on GOT related relocs. */
19485 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
19486 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
19487 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
19488 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
19489 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
19490 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
19491 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
19492 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
19493 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
19494 return 0;
a737bd4d 19495
4962c51a
MS
19496 /* Similarly for group relocations. */
19497 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19498 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19499 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19500 return 0;
19501
79947c54
CD
19502 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
19503 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
19504 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
19505 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
19506 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
19507 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
19508 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
19509 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
19510 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
19511 return 0;
19512
c19d1205 19513 return 1;
a737bd4d 19514}
0ffdc86c
NC
19515#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19516
19517#ifdef OBJ_ELF
404ff6b5 19518
c19d1205
ZW
19519const char *
19520elf32_arm_target_format (void)
404ff6b5 19521{
c19d1205
ZW
19522#ifdef TE_SYMBIAN
19523 return (target_big_endian
19524 ? "elf32-bigarm-symbian"
19525 : "elf32-littlearm-symbian");
19526#elif defined (TE_VXWORKS)
19527 return (target_big_endian
19528 ? "elf32-bigarm-vxworks"
19529 : "elf32-littlearm-vxworks");
19530#else
19531 if (target_big_endian)
19532 return "elf32-bigarm";
19533 else
19534 return "elf32-littlearm";
19535#endif
404ff6b5
AH
19536}
19537
c19d1205
ZW
19538void
19539armelf_frob_symbol (symbolS * symp,
19540 int * puntp)
404ff6b5 19541{
c19d1205
ZW
19542 elf_frob_symbol (symp, puntp);
19543}
19544#endif
404ff6b5 19545
c19d1205 19546/* MD interface: Finalization. */
a737bd4d 19547
c19d1205
ZW
19548/* A good place to do this, although this was probably not intended
19549 for this kind of use. We need to dump the literal pool before
19550 references are made to a null symbol pointer. */
a737bd4d 19551
c19d1205
ZW
19552void
19553arm_cleanup (void)
19554{
19555 literal_pool * pool;
a737bd4d 19556
c19d1205
ZW
19557 for (pool = list_of_pools; pool; pool = pool->next)
19558 {
5f4273c7 19559 /* Put it at the end of the relevant section. */
c19d1205
ZW
19560 subseg_set (pool->section, pool->sub_section);
19561#ifdef OBJ_ELF
19562 arm_elf_change_section ();
19563#endif
19564 s_ltorg (0);
19565 }
404ff6b5
AH
19566}
19567
c19d1205
ZW
19568/* Adjust the symbol table. This marks Thumb symbols as distinct from
19569 ARM ones. */
404ff6b5 19570
c19d1205
ZW
19571void
19572arm_adjust_symtab (void)
404ff6b5 19573{
c19d1205
ZW
19574#ifdef OBJ_COFF
19575 symbolS * sym;
404ff6b5 19576
c19d1205
ZW
19577 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19578 {
19579 if (ARM_IS_THUMB (sym))
19580 {
19581 if (THUMB_IS_FUNC (sym))
19582 {
19583 /* Mark the symbol as a Thumb function. */
19584 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
19585 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
19586 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 19587
c19d1205
ZW
19588 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
19589 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
19590 else
19591 as_bad (_("%s: unexpected function type: %d"),
19592 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
19593 }
19594 else switch (S_GET_STORAGE_CLASS (sym))
19595 {
19596 case C_EXT:
19597 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
19598 break;
19599 case C_STAT:
19600 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
19601 break;
19602 case C_LABEL:
19603 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
19604 break;
19605 default:
19606 /* Do nothing. */
19607 break;
19608 }
19609 }
a737bd4d 19610
c19d1205
ZW
19611 if (ARM_IS_INTERWORK (sym))
19612 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 19613 }
c19d1205
ZW
19614#endif
19615#ifdef OBJ_ELF
19616 symbolS * sym;
19617 char bind;
404ff6b5 19618
c19d1205 19619 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 19620 {
c19d1205
ZW
19621 if (ARM_IS_THUMB (sym))
19622 {
19623 elf_symbol_type * elf_sym;
404ff6b5 19624
c19d1205
ZW
19625 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
19626 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 19627
b0796911
PB
19628 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
19629 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW
19630 {
19631 /* If it's a .thumb_func, declare it as so,
19632 otherwise tag label as .code 16. */
19633 if (THUMB_IS_FUNC (sym))
19634 elf_sym->internal_elf_sym.st_info =
19635 ELF_ST_INFO (bind, STT_ARM_TFUNC);
3ba67470 19636 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW
19637 elf_sym->internal_elf_sym.st_info =
19638 ELF_ST_INFO (bind, STT_ARM_16BIT);
19639 }
19640 }
19641 }
19642#endif
404ff6b5
AH
19643}
19644
c19d1205 19645/* MD interface: Initialization. */
404ff6b5 19646
a737bd4d 19647static void
c19d1205 19648set_constant_flonums (void)
a737bd4d 19649{
c19d1205 19650 int i;
404ff6b5 19651
c19d1205
ZW
19652 for (i = 0; i < NUM_FLOAT_VALS; i++)
19653 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
19654 abort ();
a737bd4d 19655}
404ff6b5 19656
3e9e4fcf
JB
19657/* Auto-select Thumb mode if it's the only available instruction set for the
19658 given architecture. */
19659
19660static void
19661autoselect_thumb_from_cpu_variant (void)
19662{
19663 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
19664 opcode_select (16);
19665}
19666
c19d1205
ZW
19667void
19668md_begin (void)
a737bd4d 19669{
c19d1205
ZW
19670 unsigned mach;
19671 unsigned int i;
404ff6b5 19672
c19d1205
ZW
19673 if ( (arm_ops_hsh = hash_new ()) == NULL
19674 || (arm_cond_hsh = hash_new ()) == NULL
19675 || (arm_shift_hsh = hash_new ()) == NULL
19676 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 19677 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 19678 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB
19679 || (arm_reloc_hsh = hash_new ()) == NULL
19680 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW
19681 as_fatal (_("virtual memory exhausted"));
19682
19683 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5a49b8ac 19684 hash_insert (arm_ops_hsh, insns[i].template, (void *) (insns + i));
c19d1205 19685 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5a49b8ac 19686 hash_insert (arm_cond_hsh, conds[i].template, (void *) (conds + i));
c19d1205 19687 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 19688 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 19689 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5a49b8ac 19690 hash_insert (arm_psr_hsh, psrs[i].template, (void *) (psrs + i));
62b3e311 19691 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
5a49b8ac 19692 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (void *) (v7m_psrs + i));
c19d1205 19693 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 19694 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB
19695 for (i = 0;
19696 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
19697 i++)
19698 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
5a49b8ac 19699 (void *) (barrier_opt_names + i));
c19d1205
ZW
19700#ifdef OBJ_ELF
19701 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
5a49b8ac 19702 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
c19d1205
ZW
19703#endif
19704
19705 set_constant_flonums ();
404ff6b5 19706
c19d1205
ZW
19707 /* Set the cpu variant based on the command-line options. We prefer
19708 -mcpu= over -march= if both are set (as for GCC); and we prefer
19709 -mfpu= over any other way of setting the floating point unit.
19710 Use of legacy options with new options are faulted. */
e74cfd16 19711 if (legacy_cpu)
404ff6b5 19712 {
e74cfd16 19713 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW
19714 as_bad (_("use of old and new-style options to set CPU type"));
19715
19716 mcpu_cpu_opt = legacy_cpu;
404ff6b5 19717 }
e74cfd16 19718 else if (!mcpu_cpu_opt)
c19d1205 19719 mcpu_cpu_opt = march_cpu_opt;
404ff6b5 19720
e74cfd16 19721 if (legacy_fpu)
c19d1205 19722 {
e74cfd16 19723 if (mfpu_opt)
c19d1205 19724 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f
RE
19725
19726 mfpu_opt = legacy_fpu;
19727 }
e74cfd16 19728 else if (!mfpu_opt)
03b1477f 19729 {
c19d1205 19730#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE
19731 /* Some environments specify a default FPU. If they don't, infer it
19732 from the processor. */
e74cfd16 19733 if (mcpu_fpu_opt)
03b1477f
RE
19734 mfpu_opt = mcpu_fpu_opt;
19735 else
19736 mfpu_opt = march_fpu_opt;
39c2da32 19737#else
e74cfd16 19738 mfpu_opt = &fpu_default;
39c2da32 19739#endif
03b1477f
RE
19740 }
19741
e74cfd16 19742 if (!mfpu_opt)
03b1477f 19743 {
493cb6ef 19744 if (mcpu_cpu_opt != NULL)
e74cfd16 19745 mfpu_opt = &fpu_default;
493cb6ef 19746 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
e74cfd16 19747 mfpu_opt = &fpu_arch_vfp_v2;
03b1477f 19748 else
e74cfd16 19749 mfpu_opt = &fpu_arch_fpa;
03b1477f
RE
19750 }
19751
ee065d83 19752#ifdef CPU_DEFAULT
e74cfd16 19753 if (!mcpu_cpu_opt)
ee065d83 19754 {
e74cfd16
PB
19755 mcpu_cpu_opt = &cpu_default;
19756 selected_cpu = cpu_default;
ee065d83 19757 }
e74cfd16
PB
19758#else
19759 if (mcpu_cpu_opt)
19760 selected_cpu = *mcpu_cpu_opt;
ee065d83 19761 else
e74cfd16 19762 mcpu_cpu_opt = &arm_arch_any;
ee065d83 19763#endif
03b1477f 19764
e74cfd16 19765 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
03b1477f 19766
3e9e4fcf
JB
19767 autoselect_thumb_from_cpu_variant ();
19768
e74cfd16 19769 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 19770
f17c130b 19771#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 19772 {
7cc69913
NC
19773 unsigned int flags = 0;
19774
19775#if defined OBJ_ELF
19776 flags = meabi_flags;
d507cf36
PB
19777
19778 switch (meabi_flags)
33a392fb 19779 {
d507cf36 19780 case EF_ARM_EABI_UNKNOWN:
7cc69913 19781#endif
d507cf36
PB
19782 /* Set the flags in the private structure. */
19783 if (uses_apcs_26) flags |= F_APCS26;
19784 if (support_interwork) flags |= F_INTERWORK;
19785 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 19786 if (pic_code) flags |= F_PIC;
e74cfd16 19787 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC
19788 flags |= F_SOFT_FLOAT;
19789
d507cf36
PB
19790 switch (mfloat_abi_opt)
19791 {
19792 case ARM_FLOAT_ABI_SOFT:
19793 case ARM_FLOAT_ABI_SOFTFP:
19794 flags |= F_SOFT_FLOAT;
19795 break;
33a392fb 19796
d507cf36
PB
19797 case ARM_FLOAT_ABI_HARD:
19798 if (flags & F_SOFT_FLOAT)
19799 as_bad (_("hard-float conflicts with specified fpu"));
19800 break;
19801 }
03b1477f 19802
e74cfd16
PB
19803 /* Using pure-endian doubles (even if soft-float). */
19804 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 19805 flags |= F_VFP_FLOAT;
f17c130b 19806
fde78edd 19807#if defined OBJ_ELF
e74cfd16 19808 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 19809 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB
19810 break;
19811
8cb51566 19812 case EF_ARM_EABI_VER4:
3a4a14e9 19813 case EF_ARM_EABI_VER5:
c19d1205 19814 /* No additional flags to set. */
d507cf36
PB
19815 break;
19816
19817 default:
19818 abort ();
19819 }
7cc69913 19820#endif
b99bd4ef
NC
19821 bfd_set_private_flags (stdoutput, flags);
19822
19823 /* We have run out flags in the COFF header to encode the
19824 status of ATPCS support, so instead we create a dummy,
c19d1205 19825 empty, debug section called .arm.atpcs. */
b99bd4ef
NC
19826 if (atpcs)
19827 {
19828 asection * sec;
19829
19830 sec = bfd_make_section (stdoutput, ".arm.atpcs");
19831
19832 if (sec != NULL)
19833 {
19834 bfd_set_section_flags
19835 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
19836 bfd_set_section_size (stdoutput, sec, 0);
19837 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
19838 }
19839 }
7cc69913 19840 }
f17c130b 19841#endif
b99bd4ef
NC
19842
19843 /* Record the CPU type as well. */
2d447fca
JM
19844 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
19845 mach = bfd_mach_arm_iWMMXt2;
19846 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 19847 mach = bfd_mach_arm_iWMMXt;
e74cfd16 19848 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 19849 mach = bfd_mach_arm_XScale;
e74cfd16 19850 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 19851 mach = bfd_mach_arm_ep9312;
e74cfd16 19852 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 19853 mach = bfd_mach_arm_5TE;
e74cfd16 19854 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 19855 {
e74cfd16 19856 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC
19857 mach = bfd_mach_arm_5T;
19858 else
19859 mach = bfd_mach_arm_5;
19860 }
e74cfd16 19861 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 19862 {
e74cfd16 19863 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC
19864 mach = bfd_mach_arm_4T;
19865 else
19866 mach = bfd_mach_arm_4;
19867 }
e74cfd16 19868 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 19869 mach = bfd_mach_arm_3M;
e74cfd16
PB
19870 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
19871 mach = bfd_mach_arm_3;
19872 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
19873 mach = bfd_mach_arm_2a;
19874 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
19875 mach = bfd_mach_arm_2;
19876 else
19877 mach = bfd_mach_arm_unknown;
b99bd4ef
NC
19878
19879 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
19880}
19881
c19d1205 19882/* Command line processing. */
b99bd4ef 19883
c19d1205
ZW
19884/* md_parse_option
19885 Invocation line includes a switch not recognized by the base assembler.
19886 See if it's a processor-specific option.
b99bd4ef 19887
c19d1205
ZW
19888 This routine is somewhat complicated by the need for backwards
19889 compatibility (since older releases of gcc can't be changed).
19890 The new options try to make the interface as compatible as
19891 possible with GCC.
b99bd4ef 19892
c19d1205 19893 New options (supported) are:
b99bd4ef 19894
c19d1205
ZW
19895 -mcpu=<cpu name> Assemble for selected processor
19896 -march=<architecture name> Assemble for selected architecture
19897 -mfpu=<fpu architecture> Assemble for selected FPU.
19898 -EB/-mbig-endian Big-endian
19899 -EL/-mlittle-endian Little-endian
19900 -k Generate PIC code
19901 -mthumb Start in Thumb mode
19902 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 19903
c19d1205 19904 For now we will also provide support for:
b99bd4ef 19905
c19d1205
ZW
19906 -mapcs-32 32-bit Program counter
19907 -mapcs-26 26-bit Program counter
19908 -macps-float Floats passed in FP registers
19909 -mapcs-reentrant Reentrant code
19910 -matpcs
19911 (sometime these will probably be replaced with -mapcs=<list of options>
19912 and -matpcs=<list of options>)
b99bd4ef 19913
c19d1205
ZW
19914 The remaining options are only supported for back-wards compatibility.
19915 Cpu variants, the arm part is optional:
19916 -m[arm]1 Currently not supported.
19917 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19918 -m[arm]3 Arm 3 processor
19919 -m[arm]6[xx], Arm 6 processors
19920 -m[arm]7[xx][t][[d]m] Arm 7 processors
19921 -m[arm]8[10] Arm 8 processors
19922 -m[arm]9[20][tdmi] Arm 9 processors
19923 -mstrongarm[110[0]] StrongARM processors
19924 -mxscale XScale processors
19925 -m[arm]v[2345[t[e]]] Arm architectures
19926 -mall All (except the ARM1)
19927 FP variants:
19928 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19929 -mfpe-old (No float load/store multiples)
19930 -mvfpxd VFP Single precision
19931 -mvfp All VFP
19932 -mno-fpu Disable all floating point instructions
b99bd4ef 19933
c19d1205
ZW
19934 The following CPU names are recognized:
19935 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19936 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19937 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19938 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19939 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19940 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19941 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 19942
c19d1205 19943 */
b99bd4ef 19944
c19d1205 19945const char * md_shortopts = "m:k";
b99bd4ef 19946
c19d1205
ZW
19947#ifdef ARM_BI_ENDIAN
19948#define OPTION_EB (OPTION_MD_BASE + 0)
19949#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 19950#else
c19d1205
ZW
19951#if TARGET_BYTES_BIG_ENDIAN
19952#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 19953#else
c19d1205
ZW
19954#define OPTION_EL (OPTION_MD_BASE + 1)
19955#endif
b99bd4ef 19956#endif
845b51d6 19957#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
b99bd4ef 19958
c19d1205 19959struct option md_longopts[] =
b99bd4ef 19960{
c19d1205
ZW
19961#ifdef OPTION_EB
19962 {"EB", no_argument, NULL, OPTION_EB},
19963#endif
19964#ifdef OPTION_EL
19965 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 19966#endif
845b51d6 19967 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
c19d1205
ZW
19968 {NULL, no_argument, NULL, 0}
19969};
b99bd4ef 19970
c19d1205 19971size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 19972
c19d1205 19973struct arm_option_table
b99bd4ef 19974{
c19d1205
ZW
19975 char *option; /* Option name to match. */
19976 char *help; /* Help information. */
19977 int *var; /* Variable to change. */
19978 int value; /* What to change it to. */
19979 char *deprecated; /* If non-null, print this message. */
19980};
b99bd4ef 19981
c19d1205
ZW
19982struct arm_option_table arm_opts[] =
19983{
19984 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
19985 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
19986 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19987 &support_interwork, 1, NULL},
19988 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
19989 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
19990 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
19991 1, NULL},
19992 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
19993 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
19994 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
19995 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
19996 NULL},
b99bd4ef 19997
c19d1205
ZW
19998 /* These are recognized by the assembler, but have no affect on code. */
19999 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
20000 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
e74cfd16
PB
20001 {NULL, NULL, NULL, 0, NULL}
20002};
20003
20004struct arm_legacy_option_table
20005{
20006 char *option; /* Option name to match. */
20007 const arm_feature_set **var; /* Variable to change. */
20008 const arm_feature_set value; /* What to change it to. */
20009 char *deprecated; /* If non-null, print this message. */
20010};
b99bd4ef 20011
e74cfd16
PB
20012const struct arm_legacy_option_table arm_legacy_opts[] =
20013{
c19d1205
ZW
20014 /* DON'T add any new processors to this list -- we want the whole list
20015 to go away... Add them to the processors table instead. */
e74cfd16
PB
20016 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
20017 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
20018 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
20019 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
20020 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
20021 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
20022 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
20023 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
20024 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
20025 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
20026 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
20027 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
20028 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
20029 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
20030 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
20031 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
20032 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
20033 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
20034 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
20035 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
20036 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
20037 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
20038 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
20039 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
20040 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
20041 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
20042 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
20043 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
20044 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
20045 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
20046 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
20047 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
20048 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
20049 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
20050 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
20051 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
20052 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
20053 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
20054 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
20055 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
20056 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
20057 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
20058 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
20059 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
20060 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
20061 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
20062 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
20063 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
20064 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
20065 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
20066 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
20067 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
20068 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
20069 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
20070 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
20071 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
20072 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
20073 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
20074 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
20075 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
20076 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
20077 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
20078 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
20079 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
20080 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
20081 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
20082 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
20083 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
20084 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
20085 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 20086 N_("use -mcpu=strongarm110")},
e74cfd16 20087 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 20088 N_("use -mcpu=strongarm1100")},
e74cfd16 20089 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 20090 N_("use -mcpu=strongarm1110")},
e74cfd16
PB
20091 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
20092 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
20093 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 20094
c19d1205 20095 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB
20096 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
20097 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
20098 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
20099 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
20100 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
20101 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
20102 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
20103 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
20104 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
20105 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
20106 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
20107 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
20108 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
20109 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
20110 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
20111 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
20112 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
20113 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 20114
c19d1205 20115 /* Floating point variants -- don't add any more to this list either. */
e74cfd16
PB
20116 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
20117 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
20118 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
20119 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 20120 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 20121
e74cfd16 20122 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 20123};
7ed4c4c5 20124
c19d1205 20125struct arm_cpu_option_table
7ed4c4c5 20126{
c19d1205 20127 char *name;
e74cfd16 20128 const arm_feature_set value;
c19d1205
ZW
20129 /* For some CPUs we assume an FPU unless the user explicitly sets
20130 -mfpu=... */
e74cfd16 20131 const arm_feature_set default_fpu;
ee065d83
PB
20132 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20133 case. */
20134 const char *canonical_name;
c19d1205 20135};
7ed4c4c5 20136
c19d1205
ZW
20137/* This list should, at a minimum, contain all the cpu names
20138 recognized by GCC. */
e74cfd16 20139static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 20140{
ee065d83
PB
20141 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
20142 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
20143 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
20144 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
20145 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
20146 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20147 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20148 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20149 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20150 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20151 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20152 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20153 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20154 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20155 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20156 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20157 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20158 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20159 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20160 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20161 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20162 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20163 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20164 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20165 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20166 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20167 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20168 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20169 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20170 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20171 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20172 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20173 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20174 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20175 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20176 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20177 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20178 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20179 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20180 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
20181 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20182 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20183 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20184 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
7fac0536
NC
20185 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20186 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
c19d1205
ZW
20187 /* For V5 or later processors we default to using VFP; but the user
20188 should really set the FPU type explicitly. */
ee065d83
PB
20189 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20190 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20191 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20192 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20193 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
20194 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20195 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
20196 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20197 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20198 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
20199 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20200 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20201 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20202 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20203 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20204 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
20205 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20206 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20207 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20208 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
20209 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
7fac0536
NC
20210 {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL},
20211 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
ee065d83
PB
20212 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
20213 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
20214 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
20215 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
20216 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
20217 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
20218 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
20219 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
20220 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
20221 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
5287ad62
JB
20222 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20223 | FPU_NEON_EXT_V1),
15290f0a
PB
20224 NULL},
20225 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20226 | FPU_NEON_EXT_V1),
5287ad62 20227 NULL},
62b3e311
PB
20228 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
20229 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
7e806470 20230 {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL},
c19d1205 20231 /* ??? XSCALE is really an architecture. */
ee065d83 20232 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
c19d1205 20233 /* ??? iwmmxt is not a processor. */
ee065d83 20234 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
2d447fca 20235 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
ee065d83 20236 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
c19d1205 20237 /* Maverick */
e74cfd16
PB
20238 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
20239 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
c19d1205 20240};
7ed4c4c5 20241
c19d1205 20242struct arm_arch_option_table
7ed4c4c5 20243{
c19d1205 20244 char *name;
e74cfd16
PB
20245 const arm_feature_set value;
20246 const arm_feature_set default_fpu;
c19d1205 20247};
7ed4c4c5 20248
c19d1205
ZW
20249/* This list should, at a minimum, contain all the architecture names
20250 recognized by GCC. */
e74cfd16 20251static const struct arm_arch_option_table arm_archs[] =
c19d1205
ZW
20252{
20253 {"all", ARM_ANY, FPU_ARCH_FPA},
20254 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
20255 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
20256 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
20257 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
20258 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
20259 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
20260 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
20261 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
20262 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
20263 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
20264 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
20265 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
20266 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
20267 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
20268 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
20269 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
20270 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
20271 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
20272 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
20273 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
20274 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
20275 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
20276 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
20277 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
20278 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
7e806470 20279 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
62b3e311 20280 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
c450d570
PB
20281 /* The official spelling of the ARMv7 profile variants is the dashed form.
20282 Accept the non-dashed form for compatibility with old toolchains. */
62b3e311
PB
20283 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
20284 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
20285 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
c450d570
PB
20286 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
20287 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
20288 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
c19d1205
ZW
20289 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
20290 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
2d447fca 20291 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
e74cfd16 20292 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
c19d1205 20293};
7ed4c4c5 20294
c19d1205 20295/* ISA extensions in the co-processor space. */
e74cfd16 20296struct arm_option_cpu_value_table
c19d1205
ZW
20297{
20298 char *name;
e74cfd16 20299 const arm_feature_set value;
c19d1205 20300};
7ed4c4c5 20301
e74cfd16 20302static const struct arm_option_cpu_value_table arm_extensions[] =
c19d1205 20303{
e74cfd16
PB
20304 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
20305 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
20306 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
2d447fca 20307 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
e74cfd16 20308 {NULL, ARM_ARCH_NONE}
c19d1205 20309};
7ed4c4c5 20310
c19d1205
ZW
20311/* This list should, at a minimum, contain all the fpu names
20312 recognized by GCC. */
e74cfd16 20313static const struct arm_option_cpu_value_table arm_fpus[] =
c19d1205
ZW
20314{
20315 {"softfpa", FPU_NONE},
20316 {"fpe", FPU_ARCH_FPE},
20317 {"fpe2", FPU_ARCH_FPE},
20318 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
20319 {"fpa", FPU_ARCH_FPA},
20320 {"fpa10", FPU_ARCH_FPA},
20321 {"fpa11", FPU_ARCH_FPA},
20322 {"arm7500fe", FPU_ARCH_FPA},
20323 {"softvfp", FPU_ARCH_VFP},
20324 {"softvfp+vfp", FPU_ARCH_VFP_V2},
20325 {"vfp", FPU_ARCH_VFP_V2},
20326 {"vfp9", FPU_ARCH_VFP_V2},
b1cc4aeb 20327 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
c19d1205
ZW
20328 {"vfp10", FPU_ARCH_VFP_V2},
20329 {"vfp10-r0", FPU_ARCH_VFP_V1},
20330 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB
20331 {"vfpv2", FPU_ARCH_VFP_V2},
20332 {"vfpv3", FPU_ARCH_VFP_V3},
20333 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
c19d1205
ZW
20334 {"arm1020t", FPU_ARCH_VFP_V1},
20335 {"arm1020e", FPU_ARCH_VFP_V2},
20336 {"arm1136jfs", FPU_ARCH_VFP_V2},
20337 {"arm1136jf-s", FPU_ARCH_VFP_V2},
20338 {"maverick", FPU_ARCH_MAVERICK},
5287ad62 20339 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 20340 {"neon-fp16", FPU_ARCH_NEON_FP16},
e74cfd16
PB
20341 {NULL, ARM_ARCH_NONE}
20342};
20343
20344struct arm_option_value_table
20345{
20346 char *name;
20347 long value;
c19d1205 20348};
7ed4c4c5 20349
e74cfd16 20350static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW
20351{
20352 {"hard", ARM_FLOAT_ABI_HARD},
20353 {"softfp", ARM_FLOAT_ABI_SOFTFP},
20354 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 20355 {NULL, 0}
c19d1205 20356};
7ed4c4c5 20357
c19d1205 20358#ifdef OBJ_ELF
3a4a14e9 20359/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 20360static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW
20361{
20362 {"gnu", EF_ARM_EABI_UNKNOWN},
20363 {"4", EF_ARM_EABI_VER4},
3a4a14e9 20364 {"5", EF_ARM_EABI_VER5},
e74cfd16 20365 {NULL, 0}
c19d1205
ZW
20366};
20367#endif
7ed4c4c5 20368
c19d1205
ZW
20369struct arm_long_option_table
20370{
20371 char * option; /* Substring to match. */
20372 char * help; /* Help information. */
20373 int (* func) (char * subopt); /* Function to decode sub-option. */
20374 char * deprecated; /* If non-null, print this message. */
20375};
7ed4c4c5
NC
20376
20377static int
e74cfd16 20378arm_parse_extension (char * str, const arm_feature_set **opt_p)
7ed4c4c5 20379{
e74cfd16
PB
20380 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
20381
20382 /* Copy the feature set, so that we can modify it. */
20383 *ext_set = **opt_p;
20384 *opt_p = ext_set;
20385
c19d1205 20386 while (str != NULL && *str != 0)
7ed4c4c5 20387 {
e74cfd16 20388 const struct arm_option_cpu_value_table * opt;
c19d1205
ZW
20389 char * ext;
20390 int optlen;
7ed4c4c5 20391
c19d1205
ZW
20392 if (*str != '+')
20393 {
20394 as_bad (_("invalid architectural extension"));
20395 return 0;
20396 }
7ed4c4c5 20397
c19d1205
ZW
20398 str++;
20399 ext = strchr (str, '+');
7ed4c4c5 20400
c19d1205
ZW
20401 if (ext != NULL)
20402 optlen = ext - str;
20403 else
20404 optlen = strlen (str);
7ed4c4c5 20405
c19d1205
ZW
20406 if (optlen == 0)
20407 {
20408 as_bad (_("missing architectural extension"));
20409 return 0;
20410 }
7ed4c4c5 20411
c19d1205
ZW
20412 for (opt = arm_extensions; opt->name != NULL; opt++)
20413 if (strncmp (opt->name, str, optlen) == 0)
20414 {
e74cfd16 20415 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
c19d1205
ZW
20416 break;
20417 }
7ed4c4c5 20418
c19d1205
ZW
20419 if (opt->name == NULL)
20420 {
5f4273c7 20421 as_bad (_("unknown architectural extension `%s'"), str);
c19d1205
ZW
20422 return 0;
20423 }
7ed4c4c5 20424
c19d1205
ZW
20425 str = ext;
20426 };
7ed4c4c5 20427
c19d1205
ZW
20428 return 1;
20429}
7ed4c4c5 20430
c19d1205
ZW
20431static int
20432arm_parse_cpu (char * str)
7ed4c4c5 20433{
e74cfd16 20434 const struct arm_cpu_option_table * opt;
c19d1205
ZW
20435 char * ext = strchr (str, '+');
20436 int optlen;
7ed4c4c5 20437
c19d1205
ZW
20438 if (ext != NULL)
20439 optlen = ext - str;
7ed4c4c5 20440 else
c19d1205 20441 optlen = strlen (str);
7ed4c4c5 20442
c19d1205 20443 if (optlen == 0)
7ed4c4c5 20444 {
c19d1205
ZW
20445 as_bad (_("missing cpu name `%s'"), str);
20446 return 0;
7ed4c4c5
NC
20447 }
20448
c19d1205
ZW
20449 for (opt = arm_cpus; opt->name != NULL; opt++)
20450 if (strncmp (opt->name, str, optlen) == 0)
20451 {
e74cfd16
PB
20452 mcpu_cpu_opt = &opt->value;
20453 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 20454 if (opt->canonical_name)
5f4273c7 20455 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB
20456 else
20457 {
20458 int i;
20459 for (i = 0; i < optlen; i++)
20460 selected_cpu_name[i] = TOUPPER (opt->name[i]);
20461 selected_cpu_name[i] = 0;
20462 }
7ed4c4c5 20463
c19d1205
ZW
20464 if (ext != NULL)
20465 return arm_parse_extension (ext, &mcpu_cpu_opt);
7ed4c4c5 20466
c19d1205
ZW
20467 return 1;
20468 }
7ed4c4c5 20469
c19d1205
ZW
20470 as_bad (_("unknown cpu `%s'"), str);
20471 return 0;
7ed4c4c5
NC
20472}
20473
c19d1205
ZW
20474static int
20475arm_parse_arch (char * str)
7ed4c4c5 20476{
e74cfd16 20477 const struct arm_arch_option_table *opt;
c19d1205
ZW
20478 char *ext = strchr (str, '+');
20479 int optlen;
7ed4c4c5 20480
c19d1205
ZW
20481 if (ext != NULL)
20482 optlen = ext - str;
7ed4c4c5 20483 else
c19d1205 20484 optlen = strlen (str);
7ed4c4c5 20485
c19d1205 20486 if (optlen == 0)
7ed4c4c5 20487 {
c19d1205
ZW
20488 as_bad (_("missing architecture name `%s'"), str);
20489 return 0;
7ed4c4c5
NC
20490 }
20491
c19d1205
ZW
20492 for (opt = arm_archs; opt->name != NULL; opt++)
20493 if (streq (opt->name, str))
20494 {
e74cfd16
PB
20495 march_cpu_opt = &opt->value;
20496 march_fpu_opt = &opt->default_fpu;
5f4273c7 20497 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 20498
c19d1205
ZW
20499 if (ext != NULL)
20500 return arm_parse_extension (ext, &march_cpu_opt);
7ed4c4c5 20501
c19d1205
ZW
20502 return 1;
20503 }
20504
20505 as_bad (_("unknown architecture `%s'\n"), str);
20506 return 0;
7ed4c4c5 20507}
eb043451 20508
c19d1205
ZW
20509static int
20510arm_parse_fpu (char * str)
20511{
e74cfd16 20512 const struct arm_option_cpu_value_table * opt;
b99bd4ef 20513
c19d1205
ZW
20514 for (opt = arm_fpus; opt->name != NULL; opt++)
20515 if (streq (opt->name, str))
20516 {
e74cfd16 20517 mfpu_opt = &opt->value;
c19d1205
ZW
20518 return 1;
20519 }
b99bd4ef 20520
c19d1205
ZW
20521 as_bad (_("unknown floating point format `%s'\n"), str);
20522 return 0;
20523}
20524
20525static int
20526arm_parse_float_abi (char * str)
b99bd4ef 20527{
e74cfd16 20528 const struct arm_option_value_table * opt;
b99bd4ef 20529
c19d1205
ZW
20530 for (opt = arm_float_abis; opt->name != NULL; opt++)
20531 if (streq (opt->name, str))
20532 {
20533 mfloat_abi_opt = opt->value;
20534 return 1;
20535 }
cc8a6dd0 20536
c19d1205
ZW
20537 as_bad (_("unknown floating point abi `%s'\n"), str);
20538 return 0;
20539}
b99bd4ef 20540
c19d1205
ZW
20541#ifdef OBJ_ELF
20542static int
20543arm_parse_eabi (char * str)
20544{
e74cfd16 20545 const struct arm_option_value_table *opt;
cc8a6dd0 20546
c19d1205
ZW
20547 for (opt = arm_eabis; opt->name != NULL; opt++)
20548 if (streq (opt->name, str))
20549 {
20550 meabi_flags = opt->value;
20551 return 1;
20552 }
20553 as_bad (_("unknown EABI `%s'\n"), str);
20554 return 0;
20555}
20556#endif
cc8a6dd0 20557
c19d1205
ZW
20558struct arm_long_option_table arm_long_opts[] =
20559{
20560 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20561 arm_parse_cpu, NULL},
20562 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20563 arm_parse_arch, NULL},
20564 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20565 arm_parse_fpu, NULL},
20566 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20567 arm_parse_float_abi, NULL},
20568#ifdef OBJ_ELF
7fac0536 20569 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW
20570 arm_parse_eabi, NULL},
20571#endif
20572 {NULL, NULL, 0, NULL}
20573};
cc8a6dd0 20574
c19d1205
ZW
20575int
20576md_parse_option (int c, char * arg)
20577{
20578 struct arm_option_table *opt;
e74cfd16 20579 const struct arm_legacy_option_table *fopt;
c19d1205 20580 struct arm_long_option_table *lopt;
b99bd4ef 20581
c19d1205 20582 switch (c)
b99bd4ef 20583 {
c19d1205
ZW
20584#ifdef OPTION_EB
20585 case OPTION_EB:
20586 target_big_endian = 1;
20587 break;
20588#endif
cc8a6dd0 20589
c19d1205
ZW
20590#ifdef OPTION_EL
20591 case OPTION_EL:
20592 target_big_endian = 0;
20593 break;
20594#endif
b99bd4ef 20595
845b51d6
PB
20596 case OPTION_FIX_V4BX:
20597 fix_v4bx = TRUE;
20598 break;
20599
c19d1205
ZW
20600 case 'a':
20601 /* Listing option. Just ignore these, we don't support additional
20602 ones. */
20603 return 0;
b99bd4ef 20604
c19d1205
ZW
20605 default:
20606 for (opt = arm_opts; opt->option != NULL; opt++)
20607 {
20608 if (c == opt->option[0]
20609 && ((arg == NULL && opt->option[1] == 0)
20610 || streq (arg, opt->option + 1)))
20611 {
20612#if WARN_DEPRECATED
20613 /* If the option is deprecated, tell the user. */
20614 if (opt->deprecated != NULL)
20615 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20616 arg ? arg : "", _(opt->deprecated));
20617#endif
b99bd4ef 20618
c19d1205
ZW
20619 if (opt->var != NULL)
20620 *opt->var = opt->value;
cc8a6dd0 20621
c19d1205
ZW
20622 return 1;
20623 }
20624 }
b99bd4ef 20625
e74cfd16
PB
20626 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
20627 {
20628 if (c == fopt->option[0]
20629 && ((arg == NULL && fopt->option[1] == 0)
20630 || streq (arg, fopt->option + 1)))
20631 {
20632#if WARN_DEPRECATED
20633 /* If the option is deprecated, tell the user. */
20634 if (fopt->deprecated != NULL)
20635 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20636 arg ? arg : "", _(fopt->deprecated));
20637#endif
20638
20639 if (fopt->var != NULL)
20640 *fopt->var = &fopt->value;
20641
20642 return 1;
20643 }
20644 }
20645
c19d1205
ZW
20646 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20647 {
20648 /* These options are expected to have an argument. */
20649 if (c == lopt->option[0]
20650 && arg != NULL
20651 && strncmp (arg, lopt->option + 1,
20652 strlen (lopt->option + 1)) == 0)
20653 {
20654#if WARN_DEPRECATED
20655 /* If the option is deprecated, tell the user. */
20656 if (lopt->deprecated != NULL)
20657 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
20658 _(lopt->deprecated));
20659#endif
b99bd4ef 20660
c19d1205
ZW
20661 /* Call the sup-option parser. */
20662 return lopt->func (arg + strlen (lopt->option) - 1);
20663 }
20664 }
a737bd4d 20665
c19d1205
ZW
20666 return 0;
20667 }
a394c00f 20668
c19d1205
ZW
20669 return 1;
20670}
a394c00f 20671
c19d1205
ZW
20672void
20673md_show_usage (FILE * fp)
a394c00f 20674{
c19d1205
ZW
20675 struct arm_option_table *opt;
20676 struct arm_long_option_table *lopt;
a394c00f 20677
c19d1205 20678 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 20679
c19d1205
ZW
20680 for (opt = arm_opts; opt->option != NULL; opt++)
20681 if (opt->help != NULL)
20682 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 20683
c19d1205
ZW
20684 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20685 if (lopt->help != NULL)
20686 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 20687
c19d1205
ZW
20688#ifdef OPTION_EB
20689 fprintf (fp, _("\
20690 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC
20691#endif
20692
c19d1205
ZW
20693#ifdef OPTION_EL
20694 fprintf (fp, _("\
20695 -EL assemble code for a little-endian cpu\n"));
a737bd4d 20696#endif
845b51d6
PB
20697
20698 fprintf (fp, _("\
20699 --fix-v4bx Allow BX in ARMv4 code\n"));
c19d1205 20700}
ee065d83
PB
20701
20702
20703#ifdef OBJ_ELF
62b3e311
PB
20704typedef struct
20705{
20706 int val;
20707 arm_feature_set flags;
20708} cpu_arch_ver_table;
20709
20710/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20711 least features first. */
20712static const cpu_arch_ver_table cpu_arch_ver[] =
20713{
20714 {1, ARM_ARCH_V4},
20715 {2, ARM_ARCH_V4T},
20716 {3, ARM_ARCH_V5},
20717 {4, ARM_ARCH_V5TE},
20718 {5, ARM_ARCH_V5TEJ},
20719 {6, ARM_ARCH_V6},
20720 {7, ARM_ARCH_V6Z},
7e806470
PB
20721 {9, ARM_ARCH_V6K},
20722 {9, ARM_ARCH_V6M},
20723 {8, ARM_ARCH_V6T2},
62b3e311
PB
20724 {10, ARM_ARCH_V7A},
20725 {10, ARM_ARCH_V7R},
20726 {10, ARM_ARCH_V7M},
20727 {0, ARM_ARCH_NONE}
20728};
20729
ee065d83
PB
20730/* Set the public EABI object attributes. */
20731static void
20732aeabi_set_public_attributes (void)
20733{
20734 int arch;
e74cfd16 20735 arm_feature_set flags;
62b3e311
PB
20736 arm_feature_set tmp;
20737 const cpu_arch_ver_table *p;
ee065d83
PB
20738
20739 /* Choose the architecture based on the capabilities of the requested cpu
20740 (if any) and/or the instructions actually used. */
e74cfd16
PB
20741 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
20742 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
20743 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
7a1d4c38
PB
20744 /*Allow the user to override the reported architecture. */
20745 if (object_arch)
20746 {
20747 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
20748 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
20749 }
20750
62b3e311
PB
20751 tmp = flags;
20752 arch = 0;
20753 for (p = cpu_arch_ver; p->val; p++)
20754 {
20755 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
20756 {
20757 arch = p->val;
20758 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
20759 }
20760 }
ee065d83
PB
20761
20762 /* Tag_CPU_name. */
20763 if (selected_cpu_name[0])
20764 {
20765 char *p;
20766
20767 p = selected_cpu_name;
5f4273c7 20768 if (strncmp (p, "armv", 4) == 0)
ee065d83
PB
20769 {
20770 int i;
5f4273c7 20771
ee065d83
PB
20772 p += 4;
20773 for (i = 0; p[i]; i++)
20774 p[i] = TOUPPER (p[i]);
20775 }
104d59d1 20776 bfd_elf_add_proc_attr_string (stdoutput, 5, p);
ee065d83
PB
20777 }
20778 /* Tag_CPU_arch. */
104d59d1 20779 bfd_elf_add_proc_attr_int (stdoutput, 6, arch);
62b3e311
PB
20780 /* Tag_CPU_arch_profile. */
20781 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
104d59d1 20782 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
62b3e311 20783 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
104d59d1 20784 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
7e806470 20785 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
104d59d1 20786 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
ee065d83 20787 /* Tag_ARM_ISA_use. */
e74cfd16 20788 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
104d59d1 20789 bfd_elf_add_proc_attr_int (stdoutput, 8, 1);
ee065d83 20790 /* Tag_THUMB_ISA_use. */
e74cfd16 20791 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
104d59d1 20792 bfd_elf_add_proc_attr_int (stdoutput, 9,
e74cfd16 20793 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
ee065d83 20794 /* Tag_VFP_arch. */
b1cc4aeb
PB
20795 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_d32)
20796 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_d32))
20797 bfd_elf_add_proc_attr_int (stdoutput, 10, 4);
20798 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
5287ad62 20799 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
104d59d1 20800 bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
5287ad62
JB
20801 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
20802 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
104d59d1 20803 bfd_elf_add_proc_attr_int (stdoutput, 10, 2);
5287ad62
JB
20804 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
20805 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
20806 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
20807 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
104d59d1 20808 bfd_elf_add_proc_attr_int (stdoutput, 10, 1);
ee065d83 20809 /* Tag_WMMX_arch. */
e74cfd16
PB
20810 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
20811 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
104d59d1 20812 bfd_elf_add_proc_attr_int (stdoutput, 11, 1);
5287ad62 20813 /* Tag_NEON_arch. */
8e79c3df 20814 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
104d59d1 20815 bfd_elf_add_proc_attr_int (stdoutput, 12, 1);
8e79c3df
CM
20816 /* Tag_NEON_FP16_arch. */
20817 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_fp16))
20818 bfd_elf_add_proc_attr_int (stdoutput, 36, 1);
ee065d83
PB
20819}
20820
104d59d1 20821/* Add the default contents for the .ARM.attributes section. */
ee065d83
PB
20822void
20823arm_md_end (void)
20824{
ee065d83
PB
20825 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
20826 return;
20827
20828 aeabi_set_public_attributes ();
ee065d83 20829}
8463be01 20830#endif /* OBJ_ELF */
ee065d83
PB
20831
20832
20833/* Parse a .cpu directive. */
20834
20835static void
20836s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
20837{
e74cfd16 20838 const struct arm_cpu_option_table *opt;
ee065d83
PB
20839 char *name;
20840 char saved_char;
20841
20842 name = input_line_pointer;
5f4273c7 20843 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
20844 input_line_pointer++;
20845 saved_char = *input_line_pointer;
20846 *input_line_pointer = 0;
20847
20848 /* Skip the first "all" entry. */
20849 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
20850 if (streq (opt->name, name))
20851 {
e74cfd16
PB
20852 mcpu_cpu_opt = &opt->value;
20853 selected_cpu = opt->value;
ee065d83 20854 if (opt->canonical_name)
5f4273c7 20855 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB
20856 else
20857 {
20858 int i;
20859 for (i = 0; opt->name[i]; i++)
20860 selected_cpu_name[i] = TOUPPER (opt->name[i]);
20861 selected_cpu_name[i] = 0;
20862 }
e74cfd16 20863 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB
20864 *input_line_pointer = saved_char;
20865 demand_empty_rest_of_line ();
20866 return;
20867 }
20868 as_bad (_("unknown cpu `%s'"), name);
20869 *input_line_pointer = saved_char;
20870 ignore_rest_of_line ();
20871}
20872
20873
20874/* Parse a .arch directive. */
20875
20876static void
20877s_arm_arch (int ignored ATTRIBUTE_UNUSED)
20878{
e74cfd16 20879 const struct arm_arch_option_table *opt;
ee065d83
PB
20880 char saved_char;
20881 char *name;
20882
20883 name = input_line_pointer;
5f4273c7 20884 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
20885 input_line_pointer++;
20886 saved_char = *input_line_pointer;
20887 *input_line_pointer = 0;
20888
20889 /* Skip the first "all" entry. */
20890 for (opt = arm_archs + 1; opt->name != NULL; opt++)
20891 if (streq (opt->name, name))
20892 {
e74cfd16
PB
20893 mcpu_cpu_opt = &opt->value;
20894 selected_cpu = opt->value;
5f4273c7 20895 strcpy (selected_cpu_name, opt->name);
e74cfd16 20896 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB
20897 *input_line_pointer = saved_char;
20898 demand_empty_rest_of_line ();
20899 return;
20900 }
20901
20902 as_bad (_("unknown architecture `%s'\n"), name);
20903 *input_line_pointer = saved_char;
20904 ignore_rest_of_line ();
20905}
20906
20907
7a1d4c38
PB
20908/* Parse a .object_arch directive. */
20909
20910static void
20911s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
20912{
20913 const struct arm_arch_option_table *opt;
20914 char saved_char;
20915 char *name;
20916
20917 name = input_line_pointer;
5f4273c7 20918 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB
20919 input_line_pointer++;
20920 saved_char = *input_line_pointer;
20921 *input_line_pointer = 0;
20922
20923 /* Skip the first "all" entry. */
20924 for (opt = arm_archs + 1; opt->name != NULL; opt++)
20925 if (streq (opt->name, name))
20926 {
20927 object_arch = &opt->value;
20928 *input_line_pointer = saved_char;
20929 demand_empty_rest_of_line ();
20930 return;
20931 }
20932
20933 as_bad (_("unknown architecture `%s'\n"), name);
20934 *input_line_pointer = saved_char;
20935 ignore_rest_of_line ();
20936}
20937
20938
ee065d83
PB
20939/* Parse a .fpu directive. */
20940
20941static void
20942s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
20943{
e74cfd16 20944 const struct arm_option_cpu_value_table *opt;
ee065d83
PB
20945 char saved_char;
20946 char *name;
20947
20948 name = input_line_pointer;
5f4273c7 20949 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB
20950 input_line_pointer++;
20951 saved_char = *input_line_pointer;
20952 *input_line_pointer = 0;
5f4273c7 20953
ee065d83
PB
20954 for (opt = arm_fpus; opt->name != NULL; opt++)
20955 if (streq (opt->name, name))
20956 {
e74cfd16
PB
20957 mfpu_opt = &opt->value;
20958 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB
20959 *input_line_pointer = saved_char;
20960 demand_empty_rest_of_line ();
20961 return;
20962 }
20963
20964 as_bad (_("unknown floating point format `%s'\n"), name);
20965 *input_line_pointer = saved_char;
20966 ignore_rest_of_line ();
20967}
ee065d83 20968
794ba86a
DJ
20969/* Copy symbol information. */
20970void
20971arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
20972{
20973 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
20974}
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